diff --git a/WEEK05/WEEK05a.md b/WEEK05/WEEK05a.md
index d454f5b..92db6a8 100644
--- a/WEEK05/WEEK05a.md
+++ b/WEEK05/WEEK05a.md
@@ -403,13 +403,13 @@ Instead of issuing memory load and store instructions across the system bus, the
 According to **Section 3.6.1**, the GPIOC instruction set provides instantaneous, zero-latency GPIO control:
 
 #### 1. Single-Bit Output Enable (gpioc_bit_oe_put)
-$$\text{Opcode: } \texttt{mcrr p0, #4, Rt, Rt2, c4}$$
+- **Opcode:** `mcrr p0, #4, Rt, Rt2, c4`
 - `Rt`: General-purpose register holding the pin number ($0..47$).
 - `Rt2`: General-purpose register holding the 1-bit value ($1 = \text{Output}, 0 = \text{Input}$).
 - **Operation:** Atomically sets or clears the output enable for pin `Rt` in **1 single clock cycle**! No 32-bit addresses, no bit-shifts (`1 << pin`), and zero bus traffic!
 
 #### 2. Single-Bit Output Data (gpioc_bit_out_put)
-$$\text{Opcode: } \texttt{mcrr p0, #4, Rt, Rt2, c0}$$
+- **Opcode:** `mcrr p0, #4, Rt, Rt2, c0`
 - `Rt`: Pin number ($0..47$).
 - `Rt2`: Value ($1 = \text{High}, 0 = \text{Low}$).
 - **Operation:** Atomically drives pin `Rt` High or Low in 1 clock cycle.
@@ -420,7 +420,7 @@ $$\text{Opcode: } \texttt{mcrr p0, #4, Rt, Rt2, c0}$$
 - Clear pin `Rt` Low: `mcr p0, #7, Rt, c0, c0` (`gpioc_bit_out_clr`)
 
 #### 4. 64-Bit Simultaneous Sampling
-$$\text{Opcode: } \texttt{mrrc p0, #0, Rt, Rt2, c0}$$
+- **Opcode:** `mrrc p0, #0, Rt, Rt2, c0`
 - Reads back all 48 GPIO pins simultaneously into register pair `Rt:Rt2` in a single clock cycle!
 
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diff --git a/WEEK05/WEEK05a.pdf b/WEEK05/WEEK05a.pdf
index a887865..008291b 100644
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