mirror of
https://github.com/mytechnotalent/Embedded-Hacking.git
synced 2026-07-09 22:08:42 +02:00
Add bare-metal I2C driver for RP2350 (0x07_i2c_cbm)
This commit is contained in:
Kevin Thomas
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/**
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******************************************************************************
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* @file rp2350.h
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* @author Kevin Thomas
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* @brief RP2350 Device Peripheral Access Layer Header File.
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*
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* Memory-mapped register structures and peripheral base addresses
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* for the RP2350 microcontroller (Cortex-M33 dual-core). All
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* register offsets verified against the RP2350 datasheet
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* (RP-008373-DS-2).
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 Kevin Thomas.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#ifndef __RP2350_H
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#define __RP2350_H
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#include <stdint.h>
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#include <stdbool.h>
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/*!< Defines 'read / write' permissions */
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#define __IO volatile
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/*!< Stack addresses */
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#define STACK_TOP 0x20082000UL
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#define STACK_LIMIT 0x2007A000UL
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/*!< Memory map */
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#define XIP_BASE 0x10000000UL
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#define SRAM_BASE 0x20000000UL
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#define SIO_BASE 0xD0000000UL
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#define PPB_BASE 0xE0000000UL
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/*!< APB peripherals */
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#define CLOCKS_BASE 0x40010000UL
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#define RESETS_BASE 0x40020000UL
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#define IO_BANK0_BASE 0x40028000UL
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#define PADS_BANK0_BASE 0x40038000UL
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#define XOSC_BASE 0x40048000UL
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#define UART0_BASE 0x40070000UL
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#define I2C1_BASE 0x40098000UL
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/**
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* @brief XOSC (External Crystal Oscillator)
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*/
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typedef struct
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{
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__IO uint32_t CTRL; // Control register Address offset: 0x00
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__IO uint32_t STATUS; // Status register Address offset: 0x04
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__IO uint32_t DORMANT; // Dormant mode Address offset: 0x08
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__IO uint32_t STARTUP; // Startup delay Address offset: 0x0C
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__IO uint32_t COUNT; // Frequency count Address offset: 0x10
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} XOSC_TypeDef;
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/**
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* @brief CLOCKS
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*/
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typedef struct
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{
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__IO uint32_t RESERVED0[12]; // GPOUT0..GPOUT3 registers Address offset: 0x00-0x2C
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__IO uint32_t CLK_REF_CTRL; // Reference clock control Address offset: 0x30
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__IO uint32_t RESERVED1[5]; // CLK_REF_DIV..CLK_SYS_SELECTED Address offset: 0x34-0x44
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__IO uint32_t CLK_PERI_CTRL; // Peripheral clock control Address offset: 0x48
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} CLOCKS_TypeDef;
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/**
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* @brief RESETS
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*/
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typedef struct
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{
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__IO uint32_t RESET; // Reset control Address offset: 0x00
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__IO uint32_t WDSEL; // Watchdog select Address offset: 0x04
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__IO uint32_t RESET_DONE; // Reset done status Address offset: 0x08
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} RESETS_TypeDef;
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/**
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* @brief IO_BANK0 GPIO Control (one per GPIO)
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*/
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typedef struct
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{
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__IO uint32_t STATUS; // GPIO status Address offset: 0x00
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__IO uint32_t CTRL; // GPIO control Address offset: 0x04
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} IO_BANK0_GPIO_TypeDef;
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/**
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* @brief IO_BANK0
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*/
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typedef struct
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{
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IO_BANK0_GPIO_TypeDef GPIO[30]; // GPIO 0-29 status/ctrl pairs Address offset: 0x000-0x0E8
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} IO_BANK0_TypeDef;
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/**
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* @brief PADS_BANK0
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*/
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typedef struct
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{
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__IO uint32_t VOLTAGE_SELECT; // Voltage select Address offset: 0x00
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__IO uint32_t GPIO[30]; // GPIO 0-29 pad control Address offset: 0x04-0x78
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} PADS_BANK0_TypeDef;
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/**
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* @brief I2C (Synopsys DW APB I2C Controller)
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*/
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typedef struct
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{
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__IO uint32_t CON; // Control register Address offset: 0x00
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__IO uint32_t TAR; // Target address Address offset: 0x04
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__IO uint32_t SAR; // Slave address Address offset: 0x08
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__IO uint32_t RESERVED0; // Padding Address offset: 0x0C
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__IO uint32_t DATA_CMD; // Rx/Tx data buffer and command Address offset: 0x10
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__IO uint32_t SS_SCL_HCNT; // Standard speed SCL high count Address offset: 0x14
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__IO uint32_t SS_SCL_LCNT; // Standard speed SCL low count Address offset: 0x18
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__IO uint32_t FS_SCL_HCNT; // Fast mode SCL high count Address offset: 0x1C
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__IO uint32_t FS_SCL_LCNT; // Fast mode SCL low count Address offset: 0x20
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__IO uint32_t RESERVED1[2]; // Padding Address offset: 0x24-0x28
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__IO uint32_t INTR_STAT; // Interrupt status (RO) Address offset: 0x2C
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__IO uint32_t INTR_MASK; // Interrupt mask Address offset: 0x30
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__IO uint32_t RAW_INTR_STAT; // Raw interrupt status (RO) Address offset: 0x34
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__IO uint32_t RX_TL; // Receive FIFO threshold level Address offset: 0x38
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__IO uint32_t TX_TL; // Transmit FIFO threshold level Address offset: 0x3C
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__IO uint32_t CLR_INTR; // Clear combined interrupt (RO) Address offset: 0x40
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__IO uint32_t CLR_RX_UNDER; // Clear RX_UNDER interrupt (RO) Address offset: 0x44
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__IO uint32_t CLR_RX_OVER; // Clear RX_OVER interrupt (RO) Address offset: 0x48
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__IO uint32_t CLR_TX_OVER; // Clear TX_OVER interrupt (RO) Address offset: 0x4C
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__IO uint32_t CLR_RD_REQ; // Clear RD_REQ interrupt (RO) Address offset: 0x50
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__IO uint32_t CLR_TX_ABRT; // Clear TX_ABRT interrupt (RO) Address offset: 0x54
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__IO uint32_t CLR_RX_DONE; // Clear RX_DONE interrupt (RO) Address offset: 0x58
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__IO uint32_t CLR_ACTIVITY; // Clear ACTIVITY interrupt (RO) Address offset: 0x5C
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__IO uint32_t CLR_STOP_DET; // Clear STOP_DET interrupt (RO) Address offset: 0x60
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__IO uint32_t CLR_START_DET; // Clear START_DET interrupt (RO) Address offset: 0x64
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__IO uint32_t CLR_GEN_CALL; // Clear GEN_CALL interrupt (RO) Address offset: 0x68
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__IO uint32_t ENABLE; // I2C enable Address offset: 0x6C
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__IO uint32_t STATUS; // I2C status (RO) Address offset: 0x70
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__IO uint32_t TXFLR; // Transmit FIFO level (RO) Address offset: 0x74
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__IO uint32_t RXFLR; // Receive FIFO level (RO) Address offset: 0x78
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__IO uint32_t SDA_HOLD; // SDA hold time Address offset: 0x7C
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__IO uint32_t TX_ABRT_SRC; // Transmit abort source (RO) Address offset: 0x80
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__IO uint32_t RESERVED2; // SLV_DATA_NACK_ONLY Address offset: 0x84
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__IO uint32_t DMA_CR; // DMA control Address offset: 0x88
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__IO uint32_t DMA_TDLR; // DMA transmit data level Address offset: 0x8C
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__IO uint32_t DMA_RDLR; // DMA receive data level Address offset: 0x90
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__IO uint32_t SDA_SETUP; // SDA setup time Address offset: 0x94
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__IO uint32_t ACK_GEN_CALL; // ACK general call Address offset: 0x98
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__IO uint32_t ENABLE_STATUS; // I2C enable status (RO) Address offset: 0x9C
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__IO uint32_t FS_SPKLEN; // Fast mode spike suppression limit Address offset: 0xA0
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} I2C_TypeDef;
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/**
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* @brief Peripheral Definitions
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*/
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#define XOSC ((XOSC_TypeDef *) XOSC_BASE)
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#define CLOCKS ((CLOCKS_TypeDef *) CLOCKS_BASE)
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#define RESETS ((RESETS_TypeDef *) RESETS_BASE)
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#define IO_BANK0 ((IO_BANK0_TypeDef *) IO_BANK0_BASE)
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#define PADS_BANK0 ((PADS_BANK0_TypeDef *) PADS_BANK0_BASE)
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#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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#define SIO ((volatile uint32_t *) SIO_BASE)
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#define CPACR ((volatile uint32_t *) (PPB_BASE + 0x0ED88UL))
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/**
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* @brief XOSC bit definitions
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*/
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#define XOSC_STATUS_STABLE_SHIFT 31U
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/**
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* @brief CPACR bit definitions
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*/
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#define CPACR_CP0_SHIFT 0U
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#define CPACR_CP1_SHIFT 1U
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/**
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* @brief CLK_REF bit definitions
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*/
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#define CLK_REF_CTRL_SRC_XOSC 2U
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/**
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* @brief CLOCKS bit definitions
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*/
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#define CLK_PERI_CTRL_ENABLE_SHIFT 11U
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#define CLK_PERI_CTRL_AUXSRC_SHIFT 5U
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#define CLK_PERI_CTRL_AUXSRC_MASK (0x07U << CLK_PERI_CTRL_AUXSRC_SHIFT)
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#define CLK_PERI_CTRL_AUXSRC_XOSC 4U
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/**
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* @brief RESETS bit definitions
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*/
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#define RESETS_RESET_IO_BANK0_SHIFT 6U
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#define RESETS_RESET_I2C1_SHIFT 5U
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#define RESETS_RESET_UART0_SHIFT 26U
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/**
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* @brief IO_BANK0 bit definitions
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*/
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#define IO_BANK0_CTRL_FUNCSEL_MASK 0x1FU
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#define IO_BANK0_CTRL_FUNCSEL_UART 0x02U
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#define IO_BANK0_CTRL_FUNCSEL_I2C 0x03U
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#define IO_BANK0_CTRL_FUNCSEL_SIO 0x05U
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#define IO_BANK0_CTRL_FUNCSEL_NULL 0x1FU
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/**
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* @brief PADS_BANK0 bit definitions
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*/
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#define PADS_BANK0_OD_SHIFT 7U
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#define PADS_BANK0_IE_SHIFT 6U
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#define PADS_BANK0_ISO_SHIFT 8U
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#define PADS_BANK0_PUE_SHIFT 3U
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/**
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* @brief UART register offsets (word indices from UART0_BASE)
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*/
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#define UART_DR_OFFSET (0x000U / 4U)
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#define UART_FR_OFFSET (0x018U / 4U)
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#define UART_IBRD_OFFSET (0x024U / 4U)
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#define UART_FBRD_OFFSET (0x028U / 4U)
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#define UART_LCR_H_OFFSET (0x02CU / 4U)
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#define UART_CR_OFFSET (0x030U / 4U)
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/**
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* @brief UART flag register bit definitions
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*/
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#define UART_FR_TXFF_MASK 32U
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#define UART_FR_RXFE_MASK 16U
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/**
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* @brief UART line control and enable values
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*/
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#define UART_LCR_H_8N1_FIFO 0x70U
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#define UART_CR_ENABLE ((3U << 8) | 1U)
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/**
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* @brief GPIO pin definitions
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*/
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#define I2C_SDA_PIN 2U
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#define I2C_SCL_PIN 3U
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/**
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* @brief I2C CON register bit definitions
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*/
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#define I2C_CON_MASTER_MODE_SHIFT 0U
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#define I2C_CON_SPEED_SHIFT 1U
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#define I2C_CON_SPEED_FAST 2U
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#define I2C_CON_IC_RESTART_EN_SHIFT 5U
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#define I2C_CON_IC_SLAVE_DISABLE_SHIFT 6U
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#define I2C_CON_TX_EMPTY_CTRL_SHIFT 8U
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/**
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* @brief I2C DATA_CMD register bit definitions
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*/
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#define I2C_DATA_CMD_CMD_SHIFT 8U
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#define I2C_DATA_CMD_STOP_SHIFT 9U
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#define I2C_DATA_CMD_RESTART_SHIFT 10U
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/**
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* @brief I2C RAW_INTR_STAT register bit masks
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*/
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#define I2C_RAW_INTR_TX_EMPTY (1U << 4)
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#define I2C_RAW_INTR_TX_ABRT (1U << 6)
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#define I2C_RAW_INTR_STOP_DET (1U << 9)
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/**
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* @brief I2C TX_ABRT_SOURCE bit definitions
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*/
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#define I2C_TX_ABRT_7B_ADDR_NOACK (1U << 0)
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/**
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* @brief I2C STATUS register bit definitions
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*/
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#define I2C_STATUS_TFNF_SHIFT 1U
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#define I2C_STATUS_RFNE_SHIFT 3U
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/**
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* @brief I2C clock timing for 100 kHz at 12 MHz clk_sys
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*/
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#define I2C_SYS_CLK_HZ 12000000U
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#define I2C_BAUD_HZ 100000U
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#define I2C_FS_SCL_HCNT_VAL 48U
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#define I2C_FS_SCL_LCNT_VAL 72U
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#define I2C_SDA_TX_HOLD_VAL 4U
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#define I2C_FS_SPKLEN_VAL 4U
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/**
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* @brief I2C timeout
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*/
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#define I2C_TIMEOUT 1000000U
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#endif /* __RP2350_H */
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@@ -0,0 +1,33 @@
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/**
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******************************************************************************
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* @file rp2350_coprocessor.h
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* @author Kevin Thomas
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* @brief Coprocessor access control driver header for RP2350.
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*
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* Enables coprocessor access via the CPACR register.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 Kevin Thomas.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#ifndef __RP2350_COPROCESSOR_H
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#define __RP2350_COPROCESSOR_H
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#include "rp2350.h"
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/**
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* @brief Enable coprocessor access via CPACR with DSB/ISB barriers.
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* @retval None
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*/
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void coprocessor_enable(void);
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#endif /* __RP2350_COPROCESSOR_H */
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@@ -0,0 +1,34 @@
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/**
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******************************************************************************
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* @file rp2350_delay.h
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* @author Kevin Thomas
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* @brief Delay driver header for RP2350.
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*
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* Millisecond busy-wait delay calibrated for a 14.5 MHz clock.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 Kevin Thomas.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
|
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* in the root directory of this software component.
|
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* If no LICENSE file comes with this software, it is provided AS-IS.
|
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*
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******************************************************************************
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*/
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#ifndef __RP2350_DELAY_H
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#define __RP2350_DELAY_H
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#include "rp2350.h"
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/**
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* @brief Delay for the specified number of milliseconds.
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* @param ms number of milliseconds to delay
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* @retval None
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*/
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void delay_ms(uint32_t ms);
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#endif /* __RP2350_DELAY_H */
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@@ -0,0 +1,67 @@
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/**
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******************************************************************************
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* @file rp2350_i2c.h
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* @author Kevin Thomas
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* @brief I2C driver header for RP2350.
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*
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* I2C1 master-mode driver at 100 kHz on SDA=GPIO2 / SCL=GPIO3.
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* Provides init, probe, read, write, and bus scan functions.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
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******************************************************************************
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*/
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#ifndef __RP2350_I2C_H
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#define __RP2350_I2C_H
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#include "rp2350.h"
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/**
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* @brief Release I2C1 from reset and wait for completion.
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* @retval None
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*/
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void i2c_release_reset(void);
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/**
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* @brief Initialize I2C1 as a 100 kHz master on SDA=GPIO2 / SCL=GPIO3.
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*
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* Configures GPIO pads with pull-ups, sets FUNCSEL to I2C,
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* programs SCL timing for 100 kHz at 12 MHz clk_sys, and
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* enables the controller in master mode with 7-bit addressing.
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*
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* @retval None
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*/
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void i2c_init(void);
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/**
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* @brief Probe a 7-bit I2C address and return whether a device responds.
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*
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* Sends a 1-byte read to the target address. Returns true if
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* the device acknowledges, false otherwise.
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*
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* @param addr 7-bit I2C address (0x08-0x77)
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* @retval bool true if a device acknowledged, false otherwise
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*/
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bool i2c_probe(uint8_t addr);
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/**
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* @brief Scan all valid 7-bit addresses and print a formatted table.
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*
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* Iterates addresses 0x00 through 0x7F, probes each valid one
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* via i2c_probe(), and prints a 16-column hex grid showing
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* discovered device addresses over UART.
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*
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* @retval None
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*/
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void i2c_scan(void);
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#endif /* __RP2350_I2C_H */
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@@ -0,0 +1,33 @@
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/**
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******************************************************************************
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* @file rp2350_reset.h
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* @author Kevin Thomas
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* @brief Reset controller driver header for RP2350.
|
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*
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||||
* Provides subsystem reset release for IO_BANK0.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RP2350_RESET_H
|
||||
#define __RP2350_RESET_H
|
||||
|
||||
#include "rp2350.h"
|
||||
|
||||
/**
|
||||
* @brief Release IO_BANK0 from reset and wait until ready.
|
||||
* @retval None
|
||||
*/
|
||||
void reset_init_subsystem(void);
|
||||
|
||||
#endif /* __RP2350_RESET_H */
|
||||
@@ -0,0 +1,33 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rp2350_reset_handler.h
|
||||
* @author Kevin Thomas
|
||||
* @brief Reset handler header for RP2350.
|
||||
*
|
||||
* Entry point after reset. Performs stack initialization, XOSC
|
||||
* setup, subsystem reset release, UART initialization,
|
||||
* coprocessor enable, and branches to main().
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RP2350_RESET_HANDLER_H
|
||||
#define __RP2350_RESET_HANDLER_H
|
||||
|
||||
/**
|
||||
* @brief Reset handler entry point (naked, noreturn).
|
||||
* @retval None
|
||||
*/
|
||||
void Reset_Handler(void) __attribute__((noreturn));
|
||||
|
||||
#endif /* __RP2350_RESET_HANDLER_H */
|
||||
@@ -0,0 +1,34 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rp2350_stack.h
|
||||
* @author Kevin Thomas
|
||||
* @brief Stack pointer initialization header for RP2350.
|
||||
*
|
||||
* Sets MSP, PSP, MSPLIM, and PSPLIM from the STACK_TOP and
|
||||
* STACK_LIMIT values defined in rp2350.h.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RP2350_STACK_H
|
||||
#define __RP2350_STACK_H
|
||||
|
||||
#include "rp2350.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize MSP, PSP, MSPLIM, and PSPLIM stack pointers.
|
||||
* @retval None
|
||||
*/
|
||||
void stack_init(void);
|
||||
|
||||
#endif /* __RP2350_STACK_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rp2350_uart.h
|
||||
* @author Kevin Thomas
|
||||
* @brief UART0 driver header for RP2350.
|
||||
*
|
||||
* Bare-metal UART0 driver supporting TX/RX on GPIO 0/1 at
|
||||
* 115200 baud (14.5 MHz XOSC clock).
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RP2350_UART_H
|
||||
#define __RP2350_UART_H
|
||||
|
||||
#include "rp2350.h"
|
||||
|
||||
/**
|
||||
* @brief Release UART0 from reset and wait until ready.
|
||||
* @retval None
|
||||
*/
|
||||
void uart_release_reset(void);
|
||||
|
||||
/**
|
||||
* @brief Initialize UART0 pins, baud rate, line control, and enable.
|
||||
* @retval None
|
||||
*/
|
||||
void uart_init(void);
|
||||
|
||||
/**
|
||||
* @brief Check whether a received byte is waiting in the UART FIFO.
|
||||
* @retval bool true if at least one byte is available
|
||||
*/
|
||||
bool uart_is_readable(void);
|
||||
|
||||
/**
|
||||
* @brief Read one character from UART0 (blocking).
|
||||
* @retval char the received character
|
||||
*/
|
||||
char uart_getchar(void);
|
||||
|
||||
/**
|
||||
* @brief Transmit one character over UART0 (blocking).
|
||||
* @param c character to transmit
|
||||
* @retval None
|
||||
*/
|
||||
void uart_putchar(char c);
|
||||
|
||||
/**
|
||||
* @brief Transmit a null-terminated string over UART0.
|
||||
* @param str pointer to the string to send
|
||||
* @retval None
|
||||
*/
|
||||
void uart_puts(const char *str);
|
||||
|
||||
/**
|
||||
* @brief Convert a lowercase ASCII character to uppercase.
|
||||
* @param c input character
|
||||
* @retval char uppercase equivalent or original character
|
||||
*/
|
||||
char uart_to_upper(char c);
|
||||
|
||||
#endif /* __RP2350_UART_H */
|
||||
@@ -0,0 +1,46 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file rp2350_xosc.h
|
||||
* @author Kevin Thomas
|
||||
* @brief XOSC driver header for RP2350.
|
||||
*
|
||||
* External crystal oscillator initialization and peripheral
|
||||
* clock enable using the XOSC registers.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2026 Kevin Thomas.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __RP2350_XOSC_H
|
||||
#define __RP2350_XOSC_H
|
||||
|
||||
#include "rp2350.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize the external crystal oscillator and wait until stable.
|
||||
* @retval None
|
||||
*/
|
||||
void xosc_init(void);
|
||||
|
||||
/**
|
||||
* @brief Enable the XOSC peripheral clock via CLK_PERI_CTRL.
|
||||
* @retval None
|
||||
*/
|
||||
void xosc_enable_peri_clk(void);
|
||||
|
||||
/**
|
||||
* @brief Switch CLK_REF source to XOSC for a stable 12 MHz clk_sys.
|
||||
* @retval None
|
||||
*/
|
||||
void xosc_set_clk_ref(void);
|
||||
|
||||
#endif /* __RP2350_XOSC_H */
|
||||
Reference in New Issue
Block a user