Refactor Rust drivers for strict idiomatic documentation and 8-line enforcement

2026-07-05 12:07:51 +02:00 · 2023-10-06 14:27:20 -04:00
commit 46e8b76762
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+//! Implementation module
+//!
+//! **File:** `board.rs`
+//! **Author:** Kevin Thomas
+//! **Date:** 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+// UART driver for echo demo
+use crate::uart;
+
+/// External crystal frequency in Hz (12 MHz).
+pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
+
+/// UART baud rate in bits per second.
+pub(crate) const UART_BAUD: u32 = 115_200;
+
+/// Initialise system clocks and PLLs from the external 12 MHz crystal.
+///
+/// # Arguments
+///
+/// * `xosc` - XOSC peripheral singleton.
+/// * `clocks` - CLOCKS peripheral singleton.
+/// * `pll_sys` - PLL_SYS peripheral singleton.
+/// * `pll_usb` - PLL_USB peripheral singleton.
+/// * `resets` - Mutable reference to the RESETS peripheral.
+/// * `watchdog` - Mutable reference to the watchdog timer.
+///
+/// # Returns
+///
+/// Configured clocks manager.
+///
+/// # Panics
+///
+/// Panics if clock initialisation fails.
+pub(crate) fn init_clocks(
+    xosc: hal::pac::XOSC,
+    clocks: hal::pac::CLOCKS,
+    pll_sys: hal::pac::PLL_SYS,
+    pll_usb: hal::pac::PLL_USB,
+    resets: &mut hal::pac::RESETS,
+    watchdog: &mut hal::Watchdog,
+) -> hal::clocks::ClocksManager {
+    hal::clocks::init_clocks_and_plls(
+        XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog,
+    )
+    .unwrap()
+}
+
+/// Unlock the GPIO bank and return the pin set.
+///
+/// # Arguments
+///
+/// * `io_bank0` - IO_BANK0 peripheral singleton.
+/// * `pads_bank0` - PADS_BANK0 peripheral singleton.
+/// * `sio` - SIO peripheral singleton.
+/// * `resets` - Mutable reference to the RESETS peripheral.
+///
+/// # Returns
+///
+/// GPIO pin set for the entire bank.
+pub(crate) fn init_pins(
+    io_bank0: hal::pac::IO_BANK0,
+    pads_bank0: hal::pac::PADS_BANK0,
+    sio: hal::pac::SIO,
+    resets: &mut hal::pac::RESETS,
+) -> hal::gpio::Pins {
+    let sio = hal::Sio::new(sio);
+    hal::gpio::Pins::new(io_bank0, pads_bank0, sio.gpio_bank0, resets)
+}
+
+/// Initialise all peripherals and run the UART echo demo.
+///
+/// # Arguments
+///
+/// * `pac` - PAC Peripherals singleton (consumed).
+pub(crate) fn run(mut pac: hal::pac::Peripherals) -> ! {
+    let clocks = init_clocks(pac.XOSC, pac.CLOCKS, pac.PLL_SYS, pac.PLL_USB, &mut pac.RESETS, &mut hal::Watchdog::new(pac.WATCHDOG));
+    let p = init_pins(pac.IO_BANK0, pac.PADS_BANK0, pac.SIO, &mut pac.RESETS);
+    let mut drv = uart::UartDriver::init(pac.UART0, p.gpio0, p.gpio1, UART_BAUD, &mut pac.RESETS, &clocks);
+    drv.puts(b"UART driver ready (115200 8N1)\r\nType characters to echo them back in UPPERCASE:\r\n");
+    echo_loop(&mut drv)
+}
+
+/// Run the uppercase echo loop forever.
+///
+/// # Arguments
+///
+/// * `drv` - Mutable reference to the UART driver.
+fn echo_loop(drv: &mut uart::UartDriver) -> ! {
+    loop {
+        if drv.is_readable() {
+            let c = drv.getchar();
+            drv.putchar(uart::UartDriver::to_upper(c));
+        }
+    }
+}
+
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+//! Implementation module
+//!
+//! **File:** `main.rs`
+//! **Author:** Kevin Thomas
+//! **Date:** 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+#![no_std]
+#![no_main]
+
+// Board-level helpers: constants, type aliases, and init functions
+mod board;
+// UART driver module
+mod uart;
+
+// Debugging output over RTT
+use defmt_rtt as _;
+// Panic handler for RISC-V targets
+#[cfg(target_arch = "riscv32")]
+use panic_halt as _;
+// Panic handler for ARM targets
+#[cfg(target_arch = "arm")]
+use panic_probe as _;
+
+// HAL entry-point macro
+use hal::entry;
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+/// Second-stage boot loader for RP2040
+#[unsafe(link_section = ".boot2")]
+#[used]
+#[cfg(rp2040)]
+pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
+
+/// Boot metadata for the RP2350 Boot ROM
+#[unsafe(link_section = ".start_block")]
+#[used]
+#[cfg(rp2350)]
+pub static IMAGE_DEF: hal::block::ImageDef = hal::block::ImageDef::secure_exe();
+
+/// Application entry point for the UART uppercase echo demo.
+#[entry]
+fn main() -> ! {
+    board::run(hal::pac::Peripherals::take().unwrap())
+}
+
+/// Picotool binary info metadata
+#[unsafe(link_section = ".bi_entries")]
+#[used]
+pub static PICOTOOL_ENTRIES: [hal::binary_info::EntryAddr; 5] = [
+    hal::binary_info::rp_cargo_bin_name!(),
+    hal::binary_info::rp_cargo_version!(),
+    hal::binary_info::rp_program_description!(c"UART Uppercase Echo"),
+    hal::binary_info::rp_cargo_homepage_url!(),
+    hal::binary_info::rp_program_build_attribute!(),
+];
+
@@ -0,0 +1,216 @@
+//! Implementation module
+//!
+//! **File:** `uart.rs`
+//! **Author:** Kevin Thomas
+//! **Date:** 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+// Rate extension trait for .Hz() baud rate construction
+use fugit::RateExtU32;
+// Non-blocking I/O helper for UART read/write
+use nb::block;
+// Alias our HAL crate
+use rp235x_hal as hal;
+// Clock trait for accessing system clock frequency
+use hal::Clock;
+// UART configuration and peripheral types
+use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
+// GPIO pin types and function selectors
+use hal::gpio::{FunctionNull, FunctionUart, Pin, PullDown, PullNone};
+// UART0 peripheral singleton type
+use hal::pac::UART0;
+
+/// Type alias for the configured TX pin (GPIO 0, UART function, no pull).
+type TxPin = Pin<hal::gpio::bank0::Gpio0, FunctionUart, PullNone>;
+
+/// Type alias for the configured RX pin (GPIO 1, UART function, no pull).
+type RxPin = Pin<hal::gpio::bank0::Gpio1, FunctionUart, PullNone>;
+
+/// Type alias for the default TX pin state from `Pins::new()`.
+type TxPinDefault = Pin<hal::gpio::bank0::Gpio0, FunctionNull, PullDown>;
+
+/// Type alias for the default RX pin state from `Pins::new()`.
+type RxPinDefault = Pin<hal::gpio::bank0::Gpio1, FunctionNull, PullDown>;
+
+/// Type alias for the fully-enabled UART0 peripheral with TX/RX pins.
+type EnabledUart = UartPeripheral<Enabled, UART0, (TxPin, RxPin)>;
+
+/// Blocking UART0 driver that owns the enabled peripheral and its pins.
+pub struct UartDriver {
+    uart: EnabledUart,
+}
+
+/// Reconfigure TX and RX pins from their default state to UART function.
+fn reconfigure_pins(tx_pin: TxPinDefault, rx_pin: RxPinDefault) -> (TxPin, RxPin) {
+    (
+        tx_pin.reconfigure::<FunctionUart, PullNone>(),
+        rx_pin.reconfigure::<FunctionUart, PullNone>(),
+    )
+}
+
+impl UartDriver {
+    /// Initialize hardware UART0 on the specified TX and RX GPIO pins.
+    ///
+    /// Configures UART0 at the requested baud rate, reconfigures the GPIO
+    /// pins for UART function, and enables 8N1 framing.
+    ///
+    /// # Arguments
+    ///
+    /// * `uart0` - PAC UART0 peripheral singleton.
+    /// * `tx_pin` - GPIO pin to use as UART0 TX (typically GPIO 0).
+    /// * `rx_pin` - GPIO pin to use as UART0 RX (typically GPIO 1).
+    /// * `baud_rate` - Desired baud rate in bits per second (e.g. 115200).
+    /// * `resets` - Mutable reference to the RESETS peripheral.
+    /// * `clocks` - Reference to the initialised clock configuration.
+    ///
+    /// # Panics
+    ///
+    /// Panics if the HAL cannot achieve the requested baud rate.
+    pub fn init(
+        uart0: UART0,
+        tx_pin: TxPinDefault,
+        rx_pin: RxPinDefault,
+        baud_rate: u32,
+        resets: &mut hal::pac::RESETS,
+        clocks: &hal::clocks::ClocksManager,
+    ) -> Self {
+        let pins = reconfigure_pins(tx_pin, rx_pin);
+        let cfg = UartConfig::new(baud_rate.Hz(), DataBits::Eight, None, StopBits::One);
+        let uart = UartPeripheral::new(uart0, pins, resets)
+            .enable(cfg, clocks.peripheral_clock.freq())
+            .unwrap();
+        Self { uart }
+    }
+
+    /// Check whether a received character is waiting in the UART FIFO.
+    ///
+    /// Returns immediately without blocking.
+    ///
+    /// # Returns
+    ///
+    /// `true` if at least one byte is available to read, `false` otherwise.
+    pub fn is_readable(&self) -> bool {
+        self.uart.uart_is_readable()
+    }
+
+    /// Read one character from UART0 (blocking).
+    ///
+    /// Blocks until a byte arrives in the receive FIFO, then returns it.
+    ///
+    /// # Returns
+    ///
+    /// The received byte.
+    pub fn getchar(&mut self) -> u8 {
+        block!(embedded_hal_nb::serial::Read::read(&mut self.uart)).unwrap()
+    }
+
+    /// Transmit one character over UART0 (blocking).
+    ///
+    /// Waits until the transmit FIFO has space, then places the byte into
+    /// the FIFO.
+    ///
+    /// # Arguments
+    ///
+    /// * `c` - Byte to transmit.
+    pub fn putchar(&mut self, c: u8) {
+        block!(embedded_hal_nb::serial::Write::write(&mut self.uart, c)).unwrap();
+    }
+
+    /// Transmit a null-terminated string over UART0.
+    ///
+    /// Sends every byte in the slice, blocking until all bytes are sent.
+    ///
+    /// # Arguments
+    ///
+    /// * `s` - Byte slice to transmit.
+    pub fn puts(&mut self, s: &[u8]) {
+        self.uart.write_full_blocking(s);
+    }
+
+    /// Convert a lowercase ASCII character to uppercase.
+    ///
+    /// Returns the uppercase equivalent if the character is in `b'a'`–`b'z'`;
+    /// all other characters are passed through unchanged.
+    ///
+    /// # Arguments
+    ///
+    /// * `c` - Input byte.
+    ///
+    /// # Returns
+    ///
+    /// Uppercase equivalent, or the original byte.
+    pub fn to_upper(c: u8) -> u8 {
+        if c >= b'a' && c <= b'z' {
+            c - 32
+        } else {
+            c
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    // Import all parent module items
+    use super::*;
+
+    #[test]
+    fn to_upper_lowercase_a() {
+        assert_eq!(UartDriver::to_upper(b'a'), b'A');
+    }
+
+    #[test]
+    fn to_upper_lowercase_z() {
+        assert_eq!(UartDriver::to_upper(b'z'), b'Z');
+    }
+
+    #[test]
+    fn to_upper_lowercase_m() {
+        assert_eq!(UartDriver::to_upper(b'm'), b'M');
+    }
+
+    #[test]
+    fn to_upper_already_uppercase() {
+        assert_eq!(UartDriver::to_upper(b'A'), b'A');
+    }
+
+    #[test]
+    fn to_upper_digit_unchanged() {
+        assert_eq!(UartDriver::to_upper(b'5'), b'5');
+    }
+
+    #[test]
+    fn to_upper_space_unchanged() {
+        assert_eq!(UartDriver::to_upper(b' '), b' ');
+    }
+
+    #[test]
+    fn to_upper_newline_unchanged() {
+        assert_eq!(UartDriver::to_upper(b'\n'), b'\n');
+    }
+
+    #[test]
+    fn to_upper_null_unchanged() {
+        assert_eq!(UartDriver::to_upper(0), 0);
+    }
+}