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Kevin Thomas
2025-10-25 17:25:25 -04:00
committed by GitHub
parent 9f5fdf5076
commit 53cb6cbd8f
3 changed files with 147 additions and 147 deletions
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RA-0x0001-GPIO-Output/main.s
+20 -20
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@@ -22,24 +22,24 @@
/** /**
* Memory addresses and constants. * Memory addresses and constants.
*/ */
.equ STACK_TOP, 0x20082000 // top of non-secure SRAM .equ STACK_TOP, 0x20082000
.equ STACK_LIMIT, 0x2007A000 // stack limit (32 KB below top) .equ STACK_LIMIT, 0x2007A000
.equ XOSC_BASE, 0x40048000 // base address of XOSC .equ XOSC_BASE, 0x40048000
.equ XOSC_CTRL, XOSC_BASE + 0x00 // XOSC->CTRL .equ XOSC_CTRL, XOSC_BASE + 0x00
.equ XOSC_STATUS, XOSC_BASE + 0x04 // XOSC->STATUS .equ XOSC_STATUS, XOSC_BASE + 0x04
.equ XOSC_STARTUP, XOSC_BASE + 0x0C // XOSC->STARTUP .equ XOSC_STARTUP, XOSC_BASE + 0x0C
.equ PPB_BASE, 0xE0000000 // base address of PPB .equ PPB_BASE, 0xE0000000
.equ CPACR, PPB_BASE + 0x0ED88 // PPB_BASE->CPACR .equ CPACR, PPB_BASE + 0x0ED88
.equ CLOCKS_BASE, 0x40010000 // base address of CLOCKS .equ CLOCKS_BASE, 0x40010000
.equ CLK_PERI_CTRL, CLOCKS_BASE + 0x48 // CLOCKS->CLK_PERI_CTRL .equ CLK_PERI_CTRL, CLOCKS_BASE + 0x48
.equ RESETS_BASE, 0x40020000 // base address of RESETS .equ RESETS_BASE, 0x40020000
.equ RESETS_RESET, RESETS_BASE + 0x0 // RESETS->RESET .equ RESETS_RESET, RESETS_BASE + 0x0
.equ RESETS_RESET_CLEAR, RESETS_BASE + 0x3000 // RESETS->RESET_CLEAR .equ RESETS_RESET_CLEAR, RESETS_BASE + 0x3000
.equ RESETS_RESET_DONE, RESETS_BASE + 0x8 // RESETS->RESET_DONE .equ RESETS_RESET_DONE, RESETS_BASE + 0x8
.equ IO_BANK0_BASE, 0x40028000 // base address of IO_BANK0 .equ IO_BANK0_BASE, 0x40028000
.equ IO_BANK0_GPIO16_CTRL_OFFSET, 0x84 // IO_BANK0->GPIO16 offset .equ IO_BANK0_GPIO16_CTRL_OFFSET, 0x84
.equ PADS_BANK0_BASE, 0x40038000 // base address of PADS_BANK0 .equ PADS_BANK0_BASE, 0x40038000
.equ PADS_BANK0_GPIO16_OFFSET, 0x44 // PADS_BANK0->GPIO16 offset .equ PADS_BANK0_GPIO16_OFFSET, 0x44
/** /**
* Initialize the .vectors section. The .vectors section contains vector * Initialize the .vectors section. The .vectors section contains vector
@@ -173,8 +173,8 @@ Init_Subsystem:
Enable_Coprocessor: Enable_Coprocessor:
LDR R0, =CPACR // load CPACR address LDR R0, =CPACR // load CPACR address
LDR R1, [R0] // read CPACR value LDR R1, [R0] // read CPACR value
ORR R1, R1, #(1<<1) // set CP0: Controls access priv coproc 0 bit ORR R1, R1, #(1<<1) // set CP0: Ctrl access priv coproc 0 bit
ORR R1, R1, #(1<<0) // set CP0: Controls access priv coproc 0 bit ORR R1, R1, #(1<<0) // set CP0: Ctrl access priv coproc 0 bit
STR R1, [R0] // store value into CPACR STR R1, [R0] // store value into CPACR
DSB // data sync barrier DSB // data sync barrier
ISB // instruction sync barrier ISB // instruction sync barrier