Add new driver implementations and workspace updates

drivers/0x0a_ir_rust/src/board.rs

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+//! @file board.rs
+//! @brief Board-level HAL helpers for the IR driver
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+// IR pure-logic functions and timing constants
+use crate::ir;
+// Rate extension trait for .Hz() baud rate construction
+use fugit::RateExtU32;
+// Clock trait for accessing system clock frequency
+use hal::Clock;
+// GPIO pin types and function selectors
+use hal::gpio::{FunctionNull, FunctionUart, Pin, PullDown, PullNone};
+// UART configuration and peripheral types
+use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+/// Timer device type for the HAL timer peripheral.
+#[cfg(rp2350)]
+pub(crate) type HalTimer = hal::Timer<hal::timer::CopyableTimer0>;
+/// Timer type alias for RP2040 (non-generic).
+#[cfg(rp2040)]
+pub(crate) type HalTimer = hal::Timer;
+
+/// External crystal frequency in Hz (12 MHz).
+pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
+
+/// UART baud rate in bits per second.
+pub(crate) const UART_BAUD: u32 = 115_200;
+
+/// GPIO pin number connected to the IR receiver output.
+pub(crate) const IR_GPIO: u8 = 5;
+
+/// Delay between decode attempts in milliseconds.
+pub(crate) const POLL_MS: u32 = 10;
+
+/// Type alias for the configured TX pin (GPIO 0, UART function, no pull).
+pub(crate) type TxPin = Pin<hal::gpio::bank0::Gpio0, FunctionUart, PullNone>;
+
+/// Type alias for the configured RX pin (GPIO 1, UART function, no pull).
+pub(crate) type RxPin = Pin<hal::gpio::bank0::Gpio1, FunctionUart, PullNone>;
+
+/// Type alias for the default TX pin state from `Pins::new()`.
+pub(crate) type TxPinDefault = Pin<hal::gpio::bank0::Gpio0, FunctionNull, PullDown>;
+
+/// Type alias for the default RX pin state from `Pins::new()`.
+pub(crate) type RxPinDefault = Pin<hal::gpio::bank0::Gpio1, FunctionNull, PullDown>;
+
+/// Type alias for the fully-enabled UART0 peripheral with TX/RX pins.
+pub(crate) type EnabledUart = UartPeripheral<Enabled, hal::pac::UART0, (TxPin, RxPin)>;
+
+/// Initialise system clocks and PLLs from the external 12 MHz crystal.
+pub(crate) fn init_clocks(
+    xosc: hal::pac::XOSC,
+    clocks: hal::pac::CLOCKS,
+    pll_sys: hal::pac::PLL_SYS,
+    pll_usb: hal::pac::PLL_USB,
+    resets: &mut hal::pac::RESETS,
+    watchdog: &mut hal::Watchdog,
+) -> hal::clocks::ClocksManager {
+    hal::clocks::init_clocks_and_plls(
+        XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog,
+    )
+    .unwrap()
+}
+
+/// Unlock the GPIO bank and return the pin set.
+pub(crate) fn init_pins(
+    io_bank0: hal::pac::IO_BANK0,
+    pads_bank0: hal::pac::PADS_BANK0,
+    sio: hal::pac::SIO,
+    resets: &mut hal::pac::RESETS,
+) -> hal::gpio::Pins {
+    let sio = hal::Sio::new(sio);
+    hal::gpio::Pins::new(io_bank0, pads_bank0, sio.gpio_bank0, resets)
+}
+
+/// Initialise UART0 for serial output.
+pub(crate) fn init_uart(
+    uart0: hal::pac::UART0,
+    tx_pin: TxPinDefault,
+    rx_pin: RxPinDefault,
+    resets: &mut hal::pac::RESETS,
+    clocks: &hal::clocks::ClocksManager,
+) -> EnabledUart {
+    let pins = (
+        tx_pin.reconfigure::<FunctionUart, PullNone>(),
+        rx_pin.reconfigure::<FunctionUart, PullNone>(),
+    );
+    let cfg = UartConfig::new(UART_BAUD.Hz(), DataBits::Eight, None, StopBits::One);
+    UartPeripheral::new(uart0, pins, resets)
+        .enable(cfg, clocks.peripheral_clock.freq())
+        .unwrap()
+}
+
+/// Create a blocking delay timer from the ARM SysTick peripheral.
+pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay::Delay {
+    let core = cortex_m::Peripherals::take().unwrap();
+    cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz())
+}
+
+/// Read the free-running microsecond timer (lower 32 bits).
+fn time_us_32(timer: &HalTimer) -> u32 {
+    timer.get_counter().ticks() as u32
+}
+
+/// Read the current logic level of the IR input pin through the SIO block.
+fn gpio_read() -> bool {
+    unsafe { (*hal::pac::SIO::PTR).gpio_in().read().bits() & (1u32 << IR_GPIO) != 0 }
+}
+
+/// Wait for the IR pin to reach the requested level or time out.
+fn wait_for_level(timer: &HalTimer, level: bool, timeout_us: u32) -> Option<i64> {
+    let start = time_us_32(timer);
+    while gpio_read() != level {
+        let elapsed = time_us_32(timer).wrapping_sub(start) as i64;
+        if elapsed > timeout_us as i64 {
+            return None;
+        }
+    }
+    Some(time_us_32(timer).wrapping_sub(start) as i64)
+}
+
+/// Wait for the NEC leader burst and space.
+fn wait_leader(timer: &HalTimer) -> bool {
+    if wait_for_level(timer, false, ir::LEADER_START_TIMEOUT_US).is_none() {
+        return false;
+    }
+    let Some(mark_width) = wait_for_level(timer, true, ir::LEADER_MARK_TIMEOUT_US) else {
+        return false;
+    };
+    if !ir::is_valid_leader_mark(mark_width) {
+        return false;
+    }
+    let Some(space_width) = wait_for_level(timer, false, ir::LEADER_SPACE_TIMEOUT_US) else {
+        return false;
+    };
+    ir::is_valid_leader_space(space_width)
+}
+
+/// Read one NEC bit and store it in the frame buffer.
+fn read_nec_bit(timer: &HalTimer, data: &mut [u8; 4], bit_index: usize) -> bool {
+    if wait_for_level(timer, true, ir::BIT_MARK_TIMEOUT_US).is_none() {
+        return false;
+    }
+    let Some(space_width) = wait_for_level(timer, false, ir::BIT_SPACE_TIMEOUT_US) else {
+        return false;
+    };
+    if !ir::is_valid_bit_space(space_width) {
+        return false;
+    }
+    ir::accumulate_nec_bit(data, bit_index, space_width);
+    true
+}
+
+/// Read a full 32-bit NEC frame.
+fn read_32_bits(timer: &HalTimer, data: &mut [u8; 4]) -> bool {
+    let mut bit_index = 0usize;
+    while bit_index < ir::FRAME_BITS {
+        if !read_nec_bit(timer, data, bit_index) {
+            return false;
+        }
+        bit_index += 1;
+    }
+    true
+}
+
+/// Block until an NEC key is decoded or return `None` on failure.
+pub(crate) fn ir_getkey(timer: &HalTimer) -> Option<u8> {
+    if !wait_leader(timer) {
+        return None;
+    }
+    let mut data = [0u8; 4];
+    if !read_32_bits(timer, &mut data) {
+        return None;
+    }
+    ir::validate_nec_frame(&data)
+}
+
+/// Poll the decoder and print the key code when a valid frame is received.
+pub(crate) fn poll_receiver(
+    uart: &EnabledUart,
+    timer: &HalTimer,
+    delay: &mut cortex_m::delay::Delay,
+) {
+    let mut buf = [0u8; 26];
+    if let Some(command) = ir_getkey(timer) {
+        let len = ir::format_command(&mut buf, command);
+        uart.write_full_blocking(&buf[..len]);
+    }
+    delay.delay_ms(POLL_MS);
+}

drivers/0x0a_ir_rust/src/ir.rs

@@ -0,0 +1,239 @@
+//! @file ir.rs
+//! @brief Implementation of the NEC IR receiver decoder driver
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+/// Leader wait timeout in microseconds.
+pub const LEADER_START_TIMEOUT_US: u32 = 150_000;
+
+/// Maximum duration accepted for the NEC leader mark wait.
+pub const LEADER_MARK_TIMEOUT_US: u32 = 12_000;
+
+/// Minimum valid NEC leader mark width in microseconds.
+pub const LEADER_MARK_MIN_US: i64 = 8_000;
+
+/// Maximum valid NEC leader mark width in microseconds.
+pub const LEADER_MARK_MAX_US: i64 = 10_000;
+
+/// Maximum duration accepted for the NEC leader space wait.
+pub const LEADER_SPACE_TIMEOUT_US: u32 = 7_000;
+
+/// Minimum valid NEC leader space width in microseconds.
+pub const LEADER_SPACE_MIN_US: i64 = 3_500;
+
+/// Maximum valid NEC leader space width in microseconds.
+pub const LEADER_SPACE_MAX_US: i64 = 5_000;
+
+/// Maximum duration accepted while waiting for the bit mark to end.
+pub const BIT_MARK_TIMEOUT_US: u32 = 1_000;
+
+/// Maximum duration accepted while measuring the data space.
+pub const BIT_SPACE_TIMEOUT_US: u32 = 2_500;
+
+/// Minimum valid data space width in microseconds.
+pub const BIT_SPACE_MIN_US: i64 = 200;
+
+/// Space width above which a NEC bit is interpreted as logical 1.
+pub const BIT_ONE_THRESHOLD_US: i64 = 1_200;
+
+/// Total number of bits in an NEC frame.
+pub const FRAME_BITS: usize = 32;
+
+/// Return true if the measured NEC leader mark width is valid.
+pub fn is_valid_leader_mark(duration_us: i64) -> bool {
+    (LEADER_MARK_MIN_US..=LEADER_MARK_MAX_US).contains(&duration_us)
+}
+
+/// Return true if the measured NEC leader space width is valid.
+pub fn is_valid_leader_space(duration_us: i64) -> bool {
+    (LEADER_SPACE_MIN_US..=LEADER_SPACE_MAX_US).contains(&duration_us)
+}
+
+/// Return true if the measured NEC bit space width is valid.
+pub fn is_valid_bit_space(duration_us: i64) -> bool {
+    duration_us >= BIT_SPACE_MIN_US
+}
+
+/// Accumulate a single NEC bit into the 4-byte frame buffer.
+///
+/// Matches the C implementation exactly: bytes are filled LSB-first.
+pub fn accumulate_nec_bit(data: &mut [u8; 4], bit_index: usize, duration_us: i64) {
+    let byte_idx = bit_index / 8;
+    let bit_idx = bit_index % 8;
+    if duration_us > BIT_ONE_THRESHOLD_US {
+        data[byte_idx] |= 1u8 << bit_idx;
+    }
+}
+
+/// Validate an NEC frame and return the command byte on success.
+pub fn validate_nec_frame(data: &[u8; 4]) -> Option<u8> {
+    if data[0].wrapping_add(data[1]) == 0xFF && data[2].wrapping_add(data[3]) == 0xFF {
+        Some(data[2])
+    } else {
+        None
+    }
+}
+
+/// Format the decoded command as hexadecimal and decimal followed by CRLF.
+pub fn format_command(buf: &mut [u8], command: u8) -> usize {
+    let mut pos = 0;
+    let prefix = b"NEC command: 0x";
+    buf[pos..pos + prefix.len()].copy_from_slice(prefix);
+    pos += prefix.len();
+    pos += format_hex_u8(buf, pos, command);
+    let middle = b"  (";
+    buf[pos..pos + middle.len()].copy_from_slice(middle);
+    pos += middle.len();
+    pos += format_u8(buf, pos, command);
+    buf[pos] = b')';
+    pos += 1;
+    buf[pos] = b'\r';
+    pos += 1;
+    buf[pos] = b'\n';
+    pos += 1;
+    pos
+}
+
+/// Format an unsigned 8-bit integer at the given buffer offset.
+fn format_u8(buf: &mut [u8], pos: usize, value: u8) -> usize {
+    if value >= 100 {
+        buf[pos] = b'0' + value / 100;
+        buf[pos + 1] = b'0' + (value / 10) % 10;
+        buf[pos + 2] = b'0' + value % 10;
+        3
+    } else if value >= 10 {
+        buf[pos] = b'0' + value / 10;
+        buf[pos + 1] = b'0' + value % 10;
+        2
+    } else {
+        buf[pos] = b'0' + value;
+        1
+    }
+}
+
+/// Format an unsigned 8-bit integer as two uppercase hexadecimal digits.
+fn format_hex_u8(buf: &mut [u8], pos: usize, value: u8) -> usize {
+    buf[pos] = hex_digit((value >> 4) & 0x0F);
+    buf[pos + 1] = hex_digit(value & 0x0F);
+    2
+}
+
+/// Convert a 4-bit value to its uppercase ASCII hex digit.
+fn hex_digit(value: u8) -> u8 {
+    if value < 10 {
+        b'0' + value
+    } else {
+        b'A' + (value - 10)
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    // Import all parent module items
+    use super::*;
+
+    #[test]
+    fn leader_mark_accepts_lower_bound() {
+        assert!(is_valid_leader_mark(8_000));
+    }
+
+    #[test]
+    fn leader_mark_rejects_below_lower_bound() {
+        assert!(!is_valid_leader_mark(7_999));
+    }
+
+    #[test]
+    fn leader_space_accepts_upper_bound() {
+        assert!(is_valid_leader_space(5_000));
+    }
+
+    #[test]
+    fn leader_space_rejects_above_upper_bound() {
+        assert!(!is_valid_leader_space(5_001));
+    }
+
+    #[test]
+    fn bit_space_rejects_short_pulse() {
+        assert!(!is_valid_bit_space(199));
+    }
+
+    #[test]
+    fn bit_space_accepts_threshold() {
+        assert!(is_valid_bit_space(200));
+    }
+
+    #[test]
+    fn accumulate_zero_bit_leaves_byte_clear() {
+        let mut data = [0u8; 4];
+        accumulate_nec_bit(&mut data, 0, 800);
+        assert_eq!(data[0], 0);
+    }
+
+    #[test]
+    fn accumulate_one_bit_sets_lsb() {
+        let mut data = [0u8; 4];
+        accumulate_nec_bit(&mut data, 0, 1_300);
+        assert_eq!(data[0], 1);
+    }
+
+    #[test]
+    fn accumulate_crosses_into_next_byte() {
+        let mut data = [0u8; 4];
+        accumulate_nec_bit(&mut data, 8, 1_300);
+        assert_eq!(data[0], 0);
+        assert_eq!(data[1], 1);
+    }
+
+    #[test]
+    fn validate_frame_returns_command() {
+        let data = [0x00, 0xFF, 0x45, 0xBA];
+        assert_eq!(validate_nec_frame(&data), Some(0x45));
+    }
+
+    #[test]
+    fn validate_frame_rejects_bad_inverse() {
+        let data = [0x00, 0xFE, 0x45, 0xBA];
+        assert_eq!(validate_nec_frame(&data), None);
+    }
+
+    #[test]
+    fn format_command_single_digit() {
+        let mut buf = [0u8; 24];
+        let n = format_command(&mut buf, 7);
+        assert_eq!(&buf[..n], b"NEC command: 0x07  (7)\r\n");
+    }
+
+    #[test]
+    fn format_command_three_digits() {
+        let mut buf = [0u8; 26];
+        let n = format_command(&mut buf, 255);
+        assert_eq!(&buf[..n], b"NEC command: 0xFF  (255)\r\n");
+    }
+
+    #[test]
+    fn format_hex_digit_alpha() {
+        assert_eq!(hex_digit(0x0A), b'A');
+    }
+}

drivers/0x0a_ir_rust/src/lib.rs

@@ -0,0 +1,9 @@
+//! @file lib.rs
+//! @brief Library root for the IR driver crate
+//! @author Kevin Thomas
+//! @date 2025
+
+#![no_std]
+
+// IR driver module
+pub mod ir;

drivers/0x0a_ir_rust/src/main.rs

@@ -0,0 +1,113 @@
+//! @file main.rs
+//! @brief NEC IR receiver demonstration
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+//!
+//! -----------------------------------------------------------------------------
+//!
+//! Demonstrates NEC IR receiver decoding using the ir.rs driver. The receiver
+//! output is monitored on GPIO5 with an internal pull-up enabled, and each
+//! successfully decoded command byte is printed over UART. Failed decodes are
+//! ignored, matching the original C demo behavior.
+//!
+//! Wiring:
+//!   GPIO5  -> IR receiver OUT
+//!   3.3V   -> IR receiver VCC
+//!   GND    -> IR receiver GND
+
+#![no_std]
+#![no_main]
+
+// Board-level helpers: constants, type aliases, and init functions
+mod board;
+// IR driver module — suppress warnings for unused public API functions
+#[allow(dead_code)]
+mod ir;
+
+// Debugging output over RTT
+use defmt_rtt as _;
+// Panic handler for RISC-V targets
+#[cfg(target_arch = "riscv32")]
+use panic_halt as _;
+// Panic handler for ARM targets
+#[cfg(target_arch = "arm")]
+use panic_probe as _;
+
+// HAL entry-point macro
+use hal::entry;
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+// Second-stage boot loader for RP2040
+#[unsafe(link_section = ".boot2")]
+#[used]
+#[cfg(rp2040)]
+pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
+
+// Boot metadata for the RP2350 Boot ROM
+#[unsafe(link_section = ".start_block")]
+#[used]
+#[cfg(rp2350)]
+pub static IMAGE_DEF: hal::block::ImageDef = hal::block::ImageDef::secure_exe();
+
+/// Application entry point for the NEC IR receiver demo.
+#[entry]
+fn main() -> ! {
+    let mut pac = hal::pac::Peripherals::take().unwrap();
+    let clocks = board::init_clocks(
+        pac.XOSC, pac.CLOCKS, pac.PLL_SYS, pac.PLL_USB, &mut pac.RESETS,
+        &mut hal::Watchdog::new(pac.WATCHDOG),
+    );
+    let pins = board::init_pins(pac.IO_BANK0, pac.PADS_BANK0, pac.SIO, &mut pac.RESETS);
+    let uart = board::init_uart(pac.UART0, pins.gpio0, pins.gpio1, &mut pac.RESETS, &clocks);
+    let mut delay = board::init_delay(&clocks);
+    #[cfg(rp2350)]
+    let timer = hal::Timer::new_timer0(pac.TIMER0, &mut pac.RESETS, &clocks);
+    #[cfg(rp2040)]
+    let timer = hal::Timer::new(pac.TIMER, &mut pac.RESETS);
+    let _ir_pin = pins.gpio5.into_pull_up_input();
+    uart.write_full_blocking(b"NEC IR driver initialized on GPIO 5\r\n");
+    uart.write_full_blocking(b"Press a button on your NEC remote...\r\n");
+    loop {
+        board::poll_receiver(&uart, &timer, &mut delay);
+    }
+}
+
+// Picotool binary info metadata
+#[unsafe(link_section = ".bi_entries")]
+#[used]
+pub static PICOTOOL_ENTRIES: [hal::binary_info::EntryAddr; 5] = [
+    hal::binary_info::rp_cargo_bin_name!(),
+    hal::binary_info::rp_cargo_version!(),
+    hal::binary_info::rp_program_description!(c"NEC IR Receiver Demo"),
+    hal::binary_info::rp_cargo_homepage_url!(),
+    hal::binary_info::rp_program_build_attribute!(),
+];
+
+// End of file