Add new driver implementations and workspace updates

drivers/0x0c_multicore_rust/src/board.rs

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+//! @file board.rs
+//! @brief Board-level HAL helpers for the multicore driver
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+// Multicore pure-logic helpers and constants
+use crate::multicore;
+// Rate extension trait for .Hz() baud rate construction
+use fugit::RateExtU32;
+// Clock trait for accessing system clock frequency
+use hal::Clock;
+// GPIO pin types and function selectors
+use hal::gpio::{FunctionNull, FunctionUart, Pin, PullDown, PullNone};
+// Multicore execution management and stack type for core 1
+use hal::multicore::{Multicore, Stack};
+// SIO type for inter-core FIFO and GPIO bank ownership
+use hal::sio::{Sio, SioFifo};
+// UART configuration and peripheral types
+use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+/// External crystal frequency in Hz (12 MHz).
+pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
+
+/// UART baud rate in bits per second.
+pub(crate) const UART_BAUD: u32 = 115_200;
+
+/// Delay between FIFO round-trip messages in milliseconds.
+pub(crate) const POLL_MS: u32 = 1_000;
+
+/// Maximum buffer size for formatting a round-trip message.
+pub(crate) const MSG_BUF_LEN: usize = 52;
+
+/// Type alias for the configured TX pin (GPIO 0, UART function, no pull).
+pub(crate) type TxPin = Pin<hal::gpio::bank0::Gpio0, FunctionUart, PullNone>;
+
+/// Type alias for the configured RX pin (GPIO 1, UART function, no pull).
+pub(crate) type RxPin = Pin<hal::gpio::bank0::Gpio1, FunctionUart, PullNone>;
+
+/// Type alias for the default TX pin state from `Pins::new()`.
+pub(crate) type TxPinDefault = Pin<hal::gpio::bank0::Gpio0, FunctionNull, PullDown>;
+
+/// Type alias for the default RX pin state from `Pins::new()`.
+pub(crate) type RxPinDefault = Pin<hal::gpio::bank0::Gpio1, FunctionNull, PullDown>;
+
+/// Type alias for the fully-enabled UART0 peripheral with TX/RX pins.
+pub(crate) type EnabledUart = UartPeripheral<Enabled, hal::pac::UART0, (TxPin, RxPin)>;
+
+// Stack allocation for core 1 (4096 words)
+static CORE1_STACK: Stack<4096> = Stack::new();
+
+/// Initialise system clocks and PLLs from the external 12 MHz crystal.
+pub(crate) fn init_clocks(
+    xosc: hal::pac::XOSC,
+    clocks: hal::pac::CLOCKS,
+    pll_sys: hal::pac::PLL_SYS,
+    pll_usb: hal::pac::PLL_USB,
+    resets: &mut hal::pac::RESETS,
+    watchdog: &mut hal::Watchdog,
+) -> hal::clocks::ClocksManager {
+    hal::clocks::init_clocks_and_plls(
+        XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog,
+    )
+    .unwrap()
+}
+
+/// Unlock the GPIO bank and return the pin set along with the SIO FIFO.
+pub(crate) fn init_pins(
+    io_bank0: hal::pac::IO_BANK0,
+    pads_bank0: hal::pac::PADS_BANK0,
+    sio: hal::pac::SIO,
+    resets: &mut hal::pac::RESETS,
+) -> (hal::gpio::Pins, SioFifo) {
+    let sio = Sio::new(sio);
+    let pins = hal::gpio::Pins::new(io_bank0, pads_bank0, sio.gpio_bank0, resets);
+    (pins, sio.fifo)
+}
+
+/// Initialise UART0 for serial output.
+pub(crate) fn init_uart(
+    uart0: hal::pac::UART0,
+    tx_pin: TxPinDefault,
+    rx_pin: RxPinDefault,
+    resets: &mut hal::pac::RESETS,
+    clocks: &hal::clocks::ClocksManager,
+) -> EnabledUart {
+    let pins = (
+        tx_pin.reconfigure::<FunctionUart, PullNone>(),
+        rx_pin.reconfigure::<FunctionUart, PullNone>(),
+    );
+    let cfg = UartConfig::new(UART_BAUD.Hz(), DataBits::Eight, None, StopBits::One);
+    UartPeripheral::new(uart0, pins, resets)
+        .enable(cfg, clocks.peripheral_clock.freq())
+        .unwrap()
+}
+
+/// Create a blocking delay timer from the ARM SysTick peripheral.
+pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay::Delay {
+    let core = cortex_m::Peripherals::take().unwrap();
+    cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz())
+}
+
+/// Launch core 1 with its FIFO echo task.
+pub(crate) fn spawn_core1(
+    psm: &mut hal::pac::PSM,
+    ppb: &mut hal::pac::PPB,
+    fifo: &mut SioFifo,
+) {
+    let mut mc = Multicore::new(psm, ppb, fifo);
+    let cores = mc.cores();
+    let core1 = &mut cores[1];
+    let _ = core1.spawn(CORE1_STACK.take().unwrap(), move || core1_entry());
+}
+
+/// Core 1 entry point: receive values via FIFO, increment, and return.
+fn core1_entry() -> ! {
+    let pac = unsafe { hal::pac::Peripherals::steal() };
+    let sio = Sio::new(pac.SIO);
+    let mut fifo = sio.fifo;
+    loop {
+        let value = fifo.read_blocking();
+        fifo.write_blocking(multicore::increment_value(value));
+    }
+}
+
+/// Send the counter to core 1 via FIFO and print the round-trip result.
+pub(crate) fn send_and_print(
+    fifo: &mut SioFifo,
+    uart: &EnabledUart,
+    counter: &mut u32,
+    delay: &mut cortex_m::delay::Delay,
+) {
+    fifo.write_blocking(*counter);
+    let response = fifo.read_blocking();
+    let mut buf = [0u8; MSG_BUF_LEN];
+    let n = multicore::format_round_trip(&mut buf, *counter, response);
+    uart.write_full_blocking(&buf[..n]);
+    *counter = counter.wrapping_add(1);
+    delay.delay_ms(POLL_MS);
+}

drivers/0x0c_multicore_rust/src/lib.rs

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+//! @file lib.rs
+//! @brief Library root for the multicore driver crate
+//! @author Kevin Thomas
+//! @date 2025
+
+#![no_std]
+
+// Multicore driver module
+pub mod multicore;

drivers/0x0c_multicore_rust/src/main.rs

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+//! @file main.rs
+//! @brief Multicore FIFO messaging demonstration
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+//!
+//! -----------------------------------------------------------------------------
+//!
+//! Demonstrates dual-core operation using the multicore driver. Core 0 sends an
+//! incrementing counter to core 1 via the FIFO; core 1 returns the value plus
+//! one. Both values are printed over UART every second.
+//!
+//! Wiring:
+//!   No external wiring required (dual-core communication is on-chip)
+
+#![no_std]
+#![no_main]
+
+// Board-level helpers: constants, type aliases, and init functions
+mod board;
+// Multicore driver module — suppress warnings for unused public API functions
+#[allow(dead_code)]
+mod multicore;
+
+// Debugging output over RTT
+use defmt_rtt as _;
+// Panic handler for RISC-V targets
+#[cfg(target_arch = "riscv32")]
+use panic_halt as _;
+// Panic handler for ARM targets
+#[cfg(target_arch = "arm")]
+use panic_probe as _;
+
+// HAL entry-point macro
+use hal::entry;
+
+// Alias our HAL crate
+#[cfg(rp2350)]
+use rp235x_hal as hal;
+#[cfg(rp2040)]
+use rp2040_hal as hal;
+
+// Second-stage boot loader for RP2040
+#[unsafe(link_section = ".boot2")]
+#[used]
+#[cfg(rp2040)]
+pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
+
+// Boot metadata for the RP2350 Boot ROM
+#[unsafe(link_section = ".start_block")]
+#[used]
+#[cfg(rp2350)]
+pub static IMAGE_DEF: hal::block::ImageDef = hal::block::ImageDef::secure_exe();
+
+/// Application entry point for the multicore FIFO demo.
+#[entry]
+fn main() -> ! {
+    let mut pac = hal::pac::Peripherals::take().unwrap();
+    let clocks = board::init_clocks(
+        pac.XOSC, pac.CLOCKS, pac.PLL_SYS, pac.PLL_USB, &mut pac.RESETS,
+        &mut hal::Watchdog::new(pac.WATCHDOG),
+    );
+    let (pins, mut fifo) = board::init_pins(
+        pac.IO_BANK0, pac.PADS_BANK0, pac.SIO, &mut pac.RESETS,
+    );
+    let uart = board::init_uart(pac.UART0, pins.gpio0, pins.gpio1, &mut pac.RESETS, &clocks);
+    let mut delay = board::init_delay(&clocks);
+    board::spawn_core1(&mut pac.PSM, &mut pac.PPB, &mut fifo);
+    let mut counter = 0u32;
+    loop {
+        board::send_and_print(&mut fifo, &uart, &mut counter, &mut delay);
+    }
+}
+
+// Picotool binary info metadata
+#[unsafe(link_section = ".bi_entries")]
+#[used]
+pub static PICOTOOL_ENTRIES: [hal::binary_info::EntryAddr; 5] = [
+    hal::binary_info::rp_cargo_bin_name!(),
+    hal::binary_info::rp_cargo_version!(),
+    hal::binary_info::rp_program_description!(c"Multicore FIFO Demo"),
+    hal::binary_info::rp_cargo_homepage_url!(),
+    hal::binary_info::rp_program_build_attribute!(),
+];
+
+// End of file

drivers/0x0c_multicore_rust/src/multicore.rs

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+//! @file multicore.rs
+//! @brief Implementation of the multicore FIFO driver helper logic
+//! @author Kevin Thomas
+//! @date 2025
+//!
+//! MIT License
+//!
+//! Copyright (c) 2025 Kevin Thomas
+//!
+//! Permission is hereby granted, free of charge, to any person obtaining a copy
+//! of this software and associated documentation files (the "Software"), to deal
+//! in the Software without restriction, including without limitation the rights
+//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+//! copies of the Software, and to permit persons to whom the Software is
+//! furnished to do so, subject to the following conditions:
+//!
+//! The above copyright notice and this permission notice shall be included in
+//! all copies or substantial portions of the Software.
+//!
+//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+//! SOFTWARE.
+
+/// Increment a 32-bit value by one (core 1 processing logic).
+pub fn increment_value(value: u32) -> u32 {
+    value.wrapping_add(1)
+}
+
+/// Format a u32 value as decimal ASCII into a buffer.
+fn format_u32(buf: &mut [u8], value: u32) -> usize {
+    if value == 0 {
+        buf[0] = b'0';
+        return 1;
+    }
+    let mut tmp = [0u8; 10];
+    let mut pos = 0usize;
+    let mut v = value;
+    while v > 0 {
+        tmp[pos] = b'0' + (v % 10) as u8;
+        v /= 10;
+        pos += 1;
+    }
+    for i in 0..pos {
+        buf[i] = tmp[pos - 1 - i];
+    }
+    pos
+}
+
+/// Format the round-trip message for UART output.
+///
+/// Produces: `core0 sent: N, core1 returned: N\r\n`
+pub fn format_round_trip(buf: &mut [u8], sent: u32, returned: u32) -> usize {
+    let prefix = b"core0 sent: ";
+    let middle = b", core1 returned: ";
+    let mut pos = 0usize;
+    buf[pos..pos + prefix.len()].copy_from_slice(prefix);
+    pos += prefix.len();
+    pos += format_u32(&mut buf[pos..], sent);
+    buf[pos..pos + middle.len()].copy_from_slice(middle);
+    pos += middle.len();
+    pos += format_u32(&mut buf[pos..], returned);
+    buf[pos] = b'\r';
+    pos += 1;
+    buf[pos] = b'\n';
+    pos += 1;
+    pos
+}
+
+#[cfg(test)]
+mod tests {
+    // Import all parent module items
+    use super::*;
+
+    #[test]
+    fn increment_value_adds_one() {
+        assert_eq!(increment_value(0), 1);
+        assert_eq!(increment_value(41), 42);
+    }
+
+    #[test]
+    fn increment_value_wraps_at_max() {
+        assert_eq!(increment_value(u32::MAX), 0);
+    }
+
+    #[test]
+    fn format_u32_zero() {
+        let mut buf = [0u8; 10];
+        let n = format_u32(&mut buf, 0);
+        assert_eq!(&buf[..n], b"0");
+    }
+
+    #[test]
+    fn format_u32_single_digit() {
+        let mut buf = [0u8; 10];
+        let n = format_u32(&mut buf, 7);
+        assert_eq!(&buf[..n], b"7");
+    }
+
+    #[test]
+    fn format_u32_multi_digit() {
+        let mut buf = [0u8; 10];
+        let n = format_u32(&mut buf, 12345);
+        assert_eq!(&buf[..n], b"12345");
+    }
+
+    #[test]
+    fn format_u32_max() {
+        let mut buf = [0u8; 10];
+        let n = format_u32(&mut buf, u32::MAX);
+        assert_eq!(&buf[..n], b"4294967295");
+    }
+
+    #[test]
+    fn format_round_trip_small_values() {
+        let mut buf = [0u8; 52];
+        let n = format_round_trip(&mut buf, 0, 1);
+        assert_eq!(&buf[..n], b"core0 sent: 0, core1 returned: 1\r\n");
+    }
+
+    #[test]
+    fn format_round_trip_larger_values() {
+        let mut buf = [0u8; 52];
+        let n = format_round_trip(&mut buf, 42, 43);
+        assert_eq!(&buf[..n], b"core0 sent: 42, core1 returned: 43\r\n");
+    }
+
+    #[test]
+    fn format_round_trip_max_values() {
+        let mut buf = [0u8; 52];
+        let n = format_round_trip(&mut buf, u32::MAX, 0);
+        assert_eq!(
+            &buf[..n],
+            b"core0 sent: 4294967295, core1 returned: 0\r\n"
+        );
+    }
+}