refactor: enforce max 8 code lines, add docstrings, fix warnings across all Rust and C SDK projects

Rust (all 15 projects):
- Refactored overlength functions: format_counter, format_u8, format_f32_1,
  format_u32_minimal, gpio_drive, read_sensor, poll_sensor, format_round_trip,
  format_u32, prepare_write_buf, write_min_digits, write_temp, UartDriver::init,
  init_spi, angle_to_pulse_us, compute_servo_level
- Added 200+ docstrings to test functions, mock structs, impl blocks
- Fixed pub static comments (//) to doc comments (///) in all main.rs files
- Fixed helper function ordering (helpers above callers)
- Fixed Fn(u32) -> FnMut(u32) bound in button poll_button
- Moved OneShot trait import from main.rs to board.rs in adc project
- Added unsafe {} blocks in flash unsafe fn bodies (Rust 2024 edition)
- Removed unused hal::Clock imports from pwm/servo main.rs
- All 15 projects build with zero errors and zero warnings

C Pico SDK (all 15 projects):
- Added docstrings to all public functions, macros, and static variables
- All 15 projects rebuilt with zero errors

Cleanup:
- Removed build/ and target/ directories from git tracking
- Added target/ to .gitignore
- Deleted temporary fix_rust_docs.py script

drivers/0x0c_multicore_rust/src/board.rs

@@ -41,10 +41,10 @@ use hal::sio::{Sio, SioFifo};
 use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
 
 // Alias our HAL crate
-#[cfg(rp2350)]
-use rp235x_hal as hal;
 #[cfg(rp2040)]
 use rp2040_hal as hal;
+#[cfg(rp2350)]
+use rp235x_hal as hal;
 
 /// External crystal frequency in Hz (12 MHz).
 pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
@@ -86,7 +86,13 @@ pub(crate) fn init_clocks(
     watchdog: &mut hal::Watchdog,
 ) -> hal::clocks::ClocksManager {
     hal::clocks::init_clocks_and_plls(
-        XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog,
+        XTAL_FREQ_HZ,
+        xosc,
+        clocks,
+        pll_sys,
+        pll_usb,
+        resets,
+        watchdog,
     )
     .unwrap()
 }
@@ -127,18 +133,6 @@ pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay
     cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz())
 }
 
-/// Launch core 1 with its FIFO echo task.
-pub(crate) fn spawn_core1(
-    psm: &mut hal::pac::PSM,
-    ppb: &mut hal::pac::PPB,
-    fifo: &mut SioFifo,
-) {
-    let mut mc = Multicore::new(psm, ppb, fifo);
-    let cores = mc.cores();
-    let core1 = &mut cores[1];
-    let _ = core1.spawn(CORE1_STACK.take().unwrap(), move || core1_entry());
-}
-
 /// Core 1 entry point: receive values via FIFO, increment, and return.
 fn core1_entry() -> ! {
     let pac = unsafe { hal::pac::Peripherals::steal() };
@@ -150,6 +144,14 @@ fn core1_entry() -> ! {
     }
 }
 
+/// Launch core 1 with its FIFO echo task.
+pub(crate) fn spawn_core1(psm: &mut hal::pac::PSM, ppb: &mut hal::pac::PPB, fifo: &mut SioFifo) {
+    let mut mc = Multicore::new(psm, ppb, fifo);
+    let cores = mc.cores();
+    let core1 = &mut cores[1];
+    let _ = core1.spawn(CORE1_STACK.take().unwrap(), move || core1_entry());
+}
+
 /// Send the counter to core 1 via FIFO and print the round-trip result.
 pub(crate) fn send_and_print(
     fifo: &mut SioFifo,
@@ -173,13 +175,22 @@ pub(crate) fn send_and_print(
 /// * `pac` - PAC Peripherals singleton (consumed).
 pub(crate) fn run(mut pac: hal::pac::Peripherals) -> ! {
     let mut wd = hal::Watchdog::new(pac.WATCHDOG);
-    let clocks = init_clocks(pac.XOSC, pac.CLOCKS, pac.PLL_SYS, pac.PLL_USB, &mut pac.RESETS, &mut wd);
+    let clocks = init_clocks(
+        pac.XOSC,
+        pac.CLOCKS,
+        pac.PLL_SYS,
+        pac.PLL_USB,
+        &mut pac.RESETS,
+        &mut wd,
+    );
     let (pins, mut fifo) = init_pins(pac.IO_BANK0, pac.PADS_BANK0, pac.SIO, &mut pac.RESETS);
     let uart = init_uart(pac.UART0, pins.gpio0, pins.gpio1, &mut pac.RESETS, &clocks);
     let mut delay = init_delay(&clocks);
     spawn_core1(&mut pac.PSM, &mut pac.PPB, &mut fifo);
     let mut counter = 0u32;
-    loop { send_and_print(&mut fifo, &uart, &mut counter, &mut delay); }
+    loop {
+        send_and_print(&mut fifo, &uart, &mut counter, &mut delay);
+    }
 }
 
 // End of file

drivers/0x0c_multicore_rust/src/main.rs

@@ -61,13 +61,13 @@ use rp235x_hal as hal;
 #[cfg(rp2040)]
 use rp2040_hal as hal;
 
-// Second-stage boot loader for RP2040
+/// Second-stage boot loader for RP2040
 #[unsafe(link_section = ".boot2")]
 #[used]
 #[cfg(rp2040)]
 pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
 
-// Boot metadata for the RP2350 Boot ROM
+/// Boot metadata for the RP2350 Boot ROM
 #[unsafe(link_section = ".start_block")]
 #[used]
 #[cfg(rp2350)]
@@ -79,7 +79,7 @@ fn main() -> ! {
     board::run(hal::pac::Peripherals::take().unwrap())
 }
 
-// Picotool binary info metadata
+/// Picotool binary info metadata
 #[unsafe(link_section = ".bi_entries")]
 #[used]
 pub static PICOTOOL_ENTRIES: [hal::binary_info::EntryAddr; 5] = [

drivers/0x0c_multicore_rust/src/multicore.rs

@@ -60,24 +60,28 @@ fn reverse_copy(buf: &mut [u8], tmp: &[u8], n: usize) {
     }
 }
 
+/// Copy a byte slice into `buf` at the given offset, returning bytes written.
+fn copy_slice(buf: &mut [u8], offset: usize, src: &[u8]) -> usize {
+    buf[offset..offset + src.len()].copy_from_slice(src);
+    src.len()
+}
+
+/// Append a CRLF sequence at `pos` in `buf` and return the new position.
+fn append_crlf(buf: &mut [u8], pos: usize) -> usize {
+    buf[pos] = b'\r';
+    buf[pos + 1] = b'\n';
+    pos + 2
+}
+
 /// Format the round-trip message for UART output.
 ///
 /// Produces: `core0 sent: N, core1 returned: N\r\n`
 pub fn format_round_trip(buf: &mut [u8], sent: u32, returned: u32) -> usize {
-    let prefix = b"core0 sent: ";
-    let middle = b", core1 returned: ";
-    let mut pos = 0usize;
-    buf[pos..pos + prefix.len()].copy_from_slice(prefix);
-    pos += prefix.len();
+    let mut pos = copy_slice(buf, 0, b"core0 sent: ");
     pos += format_u32(&mut buf[pos..], sent);
-    buf[pos..pos + middle.len()].copy_from_slice(middle);
-    pos += middle.len();
+    pos += copy_slice(buf, pos, b", core1 returned: ");
     pos += format_u32(&mut buf[pos..], returned);
-    buf[pos] = b'\r';
-    pos += 1;
-    buf[pos] = b'\n';
-    pos += 1;
-    pos
+    append_crlf(buf, pos)
 }
 
 #[cfg(test)]
@@ -85,17 +89,20 @@ mod tests {
     // Import all parent module items
     use super::*;
 
+    /// Increment value adds one.
     #[test]
     fn increment_value_adds_one() {
         assert_eq!(increment_value(0), 1);
         assert_eq!(increment_value(41), 42);
     }
 
+    /// Increment value wraps at max.
     #[test]
     fn increment_value_wraps_at_max() {
         assert_eq!(increment_value(u32::MAX), 0);
     }
 
+    /// Format u32 zero.
     #[test]
     fn format_u32_zero() {
         let mut buf = [0u8; 10];
@@ -103,6 +110,7 @@ mod tests {
         assert_eq!(&buf[..n], b"0");
     }
 
+    /// Format u32 single digit.
     #[test]
     fn format_u32_single_digit() {
         let mut buf = [0u8; 10];
@@ -110,6 +118,7 @@ mod tests {
         assert_eq!(&buf[..n], b"7");
     }
 
+    /// Format u32 multi digit.
     #[test]
     fn format_u32_multi_digit() {
         let mut buf = [0u8; 10];
@@ -117,6 +126,7 @@ mod tests {
         assert_eq!(&buf[..n], b"12345");
     }
 
+    /// Format u32 max.
     #[test]
     fn format_u32_max() {
         let mut buf = [0u8; 10];
@@ -124,6 +134,7 @@ mod tests {
         assert_eq!(&buf[..n], b"4294967295");
     }
 
+    /// Format round trip small values.
     #[test]
     fn format_round_trip_small_values() {
         let mut buf = [0u8; 52];
@@ -131,6 +142,7 @@ mod tests {
         assert_eq!(&buf[..n], b"core0 sent: 0, core1 returned: 1\r\n");
     }
 
+    /// Format round trip larger values.
     #[test]
     fn format_round_trip_larger_values() {
         let mut buf = [0u8; 52];
@@ -138,6 +150,7 @@ mod tests {
         assert_eq!(&buf[..n], b"core0 sent: 42, core1 returned: 43\r\n");
     }
 
+    /// Format round trip max values.
     #[test]
     fn format_round_trip_max_values() {
         let mut buf = [0u8; 52];