refactor: enforce max 8 code lines, add docstrings, fix warnings across all Rust and C SDK projects

Rust (all 15 projects):
- Refactored overlength functions: format_counter, format_u8, format_f32_1,
  format_u32_minimal, gpio_drive, read_sensor, poll_sensor, format_round_trip,
  format_u32, prepare_write_buf, write_min_digits, write_temp, UartDriver::init,
  init_spi, angle_to_pulse_us, compute_servo_level
- Added 200+ docstrings to test functions, mock structs, impl blocks
- Fixed pub static comments (//) to doc comments (///) in all main.rs files
- Fixed helper function ordering (helpers above callers)
- Fixed Fn(u32) -> FnMut(u32) bound in button poll_button
- Moved OneShot trait import from main.rs to board.rs in adc project
- Added unsafe {} blocks in flash unsafe fn bodies (Rust 2024 edition)
- Removed unused hal::Clock imports from pwm/servo main.rs
- All 15 projects build with zero errors and zero warnings

C Pico SDK (all 15 projects):
- Added docstrings to all public functions, macros, and static variables
- All 15 projects rebuilt with zero errors

Cleanup:
- Removed build/ and target/ directories from git tracking
- Added target/ to .gitignore
- Deleted temporary fix_rust_docs.py script
This commit is contained in:
Kevin Thomas
2026-04-06 08:33:17 -04:00
parent 94dac7f76b
commit e54c756423
9896 changed files with 3106 additions and 312146 deletions
+28 -17
View File
@@ -41,10 +41,10 @@ use hal::sio::{Sio, SioFifo};
use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
// Alias our HAL crate
#[cfg(rp2350)]
use rp235x_hal as hal;
#[cfg(rp2040)]
use rp2040_hal as hal;
#[cfg(rp2350)]
use rp235x_hal as hal;
/// External crystal frequency in Hz (12 MHz).
pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
@@ -86,7 +86,13 @@ pub(crate) fn init_clocks(
watchdog: &mut hal::Watchdog,
) -> hal::clocks::ClocksManager {
hal::clocks::init_clocks_and_plls(
XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog,
XTAL_FREQ_HZ,
xosc,
clocks,
pll_sys,
pll_usb,
resets,
watchdog,
)
.unwrap()
}
@@ -127,18 +133,6 @@ pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay
cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz())
}
/// Launch core 1 with its FIFO echo task.
pub(crate) fn spawn_core1(
psm: &mut hal::pac::PSM,
ppb: &mut hal::pac::PPB,
fifo: &mut SioFifo,
) {
let mut mc = Multicore::new(psm, ppb, fifo);
let cores = mc.cores();
let core1 = &mut cores[1];
let _ = core1.spawn(CORE1_STACK.take().unwrap(), move || core1_entry());
}
/// Core 1 entry point: receive values via FIFO, increment, and return.
fn core1_entry() -> ! {
let pac = unsafe { hal::pac::Peripherals::steal() };
@@ -150,6 +144,14 @@ fn core1_entry() -> ! {
}
}
/// Launch core 1 with its FIFO echo task.
pub(crate) fn spawn_core1(psm: &mut hal::pac::PSM, ppb: &mut hal::pac::PPB, fifo: &mut SioFifo) {
let mut mc = Multicore::new(psm, ppb, fifo);
let cores = mc.cores();
let core1 = &mut cores[1];
let _ = core1.spawn(CORE1_STACK.take().unwrap(), move || core1_entry());
}
/// Send the counter to core 1 via FIFO and print the round-trip result.
pub(crate) fn send_and_print(
fifo: &mut SioFifo,
@@ -173,13 +175,22 @@ pub(crate) fn send_and_print(
/// * `pac` - PAC Peripherals singleton (consumed).
pub(crate) fn run(mut pac: hal::pac::Peripherals) -> ! {
let mut wd = hal::Watchdog::new(pac.WATCHDOG);
let clocks = init_clocks(pac.XOSC, pac.CLOCKS, pac.PLL_SYS, pac.PLL_USB, &mut pac.RESETS, &mut wd);
let clocks = init_clocks(
pac.XOSC,
pac.CLOCKS,
pac.PLL_SYS,
pac.PLL_USB,
&mut pac.RESETS,
&mut wd,
);
let (pins, mut fifo) = init_pins(pac.IO_BANK0, pac.PADS_BANK0, pac.SIO, &mut pac.RESETS);
let uart = init_uart(pac.UART0, pins.gpio0, pins.gpio1, &mut pac.RESETS, &clocks);
let mut delay = init_delay(&clocks);
spawn_core1(&mut pac.PSM, &mut pac.PPB, &mut fifo);
let mut counter = 0u32;
loop { send_and_print(&mut fifo, &uart, &mut counter, &mut delay); }
loop {
send_and_print(&mut fifo, &uart, &mut counter, &mut delay);
}
}
// End of file