commit e9cb70b51bf78dfbb4a82bcca5ecd80313fba15b Author: Kevin Thomas Date: Tue Oct 20 09:26:23 2026 -0400 Initial commit diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..b105d83 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,12 @@ +*.c linguist-detectable=true +*.cmake linguist-detectable=false +*.py linguist-detectable=false +*.txt linguist-detectable=false +*.json linguist-detectable=false +*.ps1 linguist-detectable=false + +# Line endings: store LF in the repository; check out LF everywhere except the +# Windows PowerShell scripts, which stay CRLF. Prevents CRLF<->LF churn. +* text=auto eol=lf +*.ps1 text eol=crlf + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..dfd8a18 --- /dev/null +++ b/.gitignore @@ -0,0 +1,96 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb +*.rep +*.gpr + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf + +# Build output +build/ +target/ + +# Node.js and PDF generation script +node_modules/ +package-lock.json +package.json +svg-to-pdf.ps1 + +# Operating System Files +.DS_Store +.DS_Store? +._* +.Spotlight-V100 +.Trashes +ehthumbs.db +Thumbs.db + +# Logs written by the Binary Ninja console helpers (build / flash / OpenOCD) +openocd.log +flash.log +build.log +build-flash.log + +# Nested repositories +eCTF/ + +# Whitelist course binaries in WEEK folders +!WEEK*/**/build/ +!WEEK*/**/build/** +!WEEK*/**/*.elf +!WEEK*/**/*.hex +!WEEK*/**/*.bin +!WEEK*/**/*.uf2 +!WEEK*/**/*.map +!WEEK*/**/*.dis +!WEEK*/**/*.bndb +!WEEK*/**/*.a +!WEEK*/**/*.ld +!WEEK*/**/*.h diff --git a/.opencode/skill/embedded-c-standard/SKILL.md b/.opencode/skill/embedded-c-standard/SKILL.md new file mode 100644 index 0000000..bdfaa96 --- /dev/null +++ b/.opencode/skill/embedded-c-standard/SKILL.md @@ -0,0 +1,54 @@ +--- +name: embedded-c-standard +description: Use ONLY when writing, editing, or reviewing C firmware in a picokit project (firmware/src, firmware/include, firmware/tests). Enforces the strict C standard: no function over 8 executable lines, no blank lines inside a function body, a Doxygen block with @brief/@param/@return on every function, a fixed module layout and naming scheme, and a ban on em/en dashes. Run the bundled audit_c_standard.py before every commit. +--- + +# Embedded C standard (picokit) + +This is non-negotiable and identical in every project in the series. There is +no variation between projects. If a rule is inconvenient, refactor; do not +exempt. + +## Rules + +1. No function longer than 8 executable lines. The audit counts every + non-blank, non-comment, non-brace line in the body, including continuation + lines of a wrapped statement. Split the work into a `static` helper. +2. No blank lines inside a function body. Separate logical steps with a + comment, never with a blank line. +3. Documentation lives in the header. Every function declaration in a `.h` + carries a Doxygen block with `@brief`, a `@param` for each parameter + (`@param void No parameters.` when there are none), and an `@return`. A + `static` function, which has no declaration, carries its Doxygen block in + the `.c`. Never duplicate the block in the `.c` for an exported function. +4. No U+2013 (en dash) or U+2014 (em dash) anywhere. Use the hyphen-minus `-`. +5. Every source file opens with the MIT header block: `Copyright (c) 2026 Kevin + Thomas`, `Author`, `Email`, `GitHub`, `File`, `Desc`, `Created`. +6. Every header uses an include guard `#ifndef _H` / `#define + _H` / `#endif // _H`. +7. Naming: files and modules `snake_case`; functions `module_action`; macros + `UPPER_SNAKE`; types `name_t`; file-scope statics `g_name`. +8. One responsibility per file: `src/.c` with `include/.h`. + All hardware access goes through a HAL seam so the host tests can substitute + mocks. +9. 79-column lines, four-space indent, no tabs. + +## Layout + +``` +firmware/ + src/ .c + include/ .h + tests/ host unit tests, mock/, harness/ + CMakeLists.txt +scripts/ run_tests.py check_coverage.py build.sh +``` + +## Verify + +Run the bundled audit from the repository root. Exit 0 is clean; any output is +a failure and must be fixed before the change is complete. + +```bash +python3 .opencode/skill/embedded-c-standard/audit_c_standard.py +``` diff --git a/.opencode/skill/embedded-c-standard/audit_c_standard.py b/.opencode/skill/embedded-c-standard/audit_c_standard.py new file mode 100644 index 0000000..c003b71 --- /dev/null +++ b/.opencode/skill/embedded-c-standard/audit_c_standard.py @@ -0,0 +1,989 @@ +#!/usr/bin/env python3 +"""Audit owned C files against the strict embedded C standard. + +Checks the no-blank-line-in-function-body rule, the eight-executable-line +function limit, the em/en dash ban, and the documentation placement rules: +a C file documents its static helpers but never its exported definitions, +while a header documents every prototype. Run from the repository root; +exit zero means the tree is clean. +""" +from pathlib import Path + +EXCLUDED_PARTS = ( + ".opencode", + "build", + "build/", + "generated/", + ".venv/", + "node_modules/", + "packet_artifact.h", + "third_party/", + "test/unity", + "unity.c", + "unity_internals.h", + "ghidra/", +) + +EN_DASH = "\u2013" +EM_DASH = "\u2014" +MAX_EXEC_LINES = 8 + + +def _owned_files() -> list[Path]: + """ + Find owned C and header files. + + Parameters + ---------- + None + + Returns + ------- + list[pathlib.Path] + Owned non-generated C and header paths. + """ + paths = Path(".").glob("**/*") + return sorted(path for path in paths if _is_owned(path)) + + +def _is_owned(path: Path) -> bool: + """ + Determine whether a path is in the audit scope. + + Parameters + ---------- + path : pathlib.Path + Candidate source path. + + Returns + ------- + bool + True when the path is an owned C or header file. + """ + name = str(path) + if any(part in name for part in EXCLUDED_PARTS): + return False + return path.suffix in {".c", ".h"} + + +def _next_is(line: str, index: int, mark: str) -> bool: + """ + Test the character following an index against a marker. + + Parameters + ---------- + line : str + Source line. + index : int + Current character index. + mark : str + Single-character marker to compare. + + Returns + ------- + bool + True when the next character equals the marker. + """ + return line[index + 1:index + 2] == mark + + +def _is_comment_open(line: str, index: int) -> bool: + """ + Test whether a slash begins a line or block comment. + + Parameters + ---------- + line : str + Source line. + index : int + Current character index. + + Returns + ------- + bool + True when a comment opens at the index. + """ + return line[index] == "/" and line[index + 1:index + 2] in ("*", "/") + + +def _comment_open(line: str, index: int) -> tuple[int, str]: + """ + Advance past a comment opening at the index. + + Parameters + ---------- + line : str + Source line. + index : int + Index of the opening slash. + + Returns + ------- + tuple[int, str] + Next index and the resulting scanner mode. + """ + if _next_is(line, index, "/"): + return len(line), "normal" + return index + 2, "block" + + +def _literal_mode(char: str) -> str: + """ + Select the scanner mode for a quote character. + + Parameters + ---------- + char : str + Quote character. + + Returns + ------- + str + Scanner mode name for the literal. + """ + return "string" if char == '"' else "char" + + +def _literal_close(mode: str) -> str: + """ + Return the closing quote for a literal mode. + + Parameters + ---------- + mode : str + Scanner mode name. + + Returns + ------- + str + Matching closing quote character. + """ + return '"' if mode == "string" else "'" + + +def _on_normal(out: list, line: str, index: int) -> tuple[int, str]: + """ + Consume one character of ordinary code. + + Parameters + ---------- + out : list + Mutable code accumulator. + line : str + Source line. + index : int + Current character index. + + Returns + ------- + tuple[int, str] + Next index and the resulting scanner mode. + """ + char = line[index] + if _is_comment_open(line, index): + return _comment_open(line, index) + if char in "\"'": + return index + 1, _literal_mode(char) + out.append(char) + return index + 1, "normal" + + +def _on_block(out: list, line: str, index: int) -> tuple[int, str]: + """ + Consume one character inside a block comment. + + Parameters + ---------- + out : list + Mutable code accumulator. + line : str + Source line. + index : int + Current character index. + + Returns + ------- + tuple[int, str] + Next index and the resulting scanner mode. + """ + if line[index] == "*" and _next_is(line, index, "/"): + return index + 2, "normal" + return index + 1, "block" + + +def _on_literal(out: list, line: str, index: int, + mode: str) -> tuple[int, str]: + """ + Consume one character inside a string or character literal. + + Parameters + ---------- + out : list + Mutable code accumulator. + line : str + Source line. + index : int + Current character index. + mode : str + Current literal scanner mode. + + Returns + ------- + tuple[int, str] + Next index and the resulting scanner mode. + """ + char = line[index] + if char == "\\": + return index + 2, mode + if char == _literal_close(mode): + return index + 1, "normal" + return index + 1, mode + + +def _advance(out: list, line: str, index: int, mode: str) -> tuple[int, str]: + """ + Dispatch one character to its scanner handler. + + Parameters + ---------- + out : list + Mutable code accumulator. + line : str + Source line. + index : int + Current character index. + mode : str + Current scanner mode. + + Returns + ------- + tuple[int, str] + Next index and the resulting scanner mode. + """ + if mode == "normal": + return _on_normal(out, line, index) + if mode == "block": + return _on_block(out, line, index) + return _on_literal(out, line, index, mode) + + +def _strip_line(line: str, in_block: bool) -> tuple[str, bool]: + """ + Remove comments and literals from one source line. + + Parameters + ---------- + line : str + Source line. + in_block : bool + Whether a block comment is already open. + + Returns + ------- + tuple[str, bool] + Code-only text and the updated block-comment state. + """ + out = [] + index = 0 + mode = "block" if in_block else "normal" + while index < len(line): + index, mode = _advance(out, line, index, mode) + return "".join(out), mode == "block" + + +def _func_name(code: str) -> str: + """ + Extract the function identifier from a signature head. + + Parameters + ---------- + code : str + Comment-free signature line. + + Returns + ------- + str + Trailing identifier before the opening parenthesis. + """ + head = code.split("(")[0].strip() + return head.split()[-1] if head else "" + + +def _scan_state(path: Path) -> dict: + """ + Build the mutable scanner state for one file. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + + Returns + ------- + dict + Scanner accumulation state. + """ + lines = path.read_text(encoding="utf-8").splitlines() + state = {"lines": lines, "records": [], "protos": []} + state.update(depth=0, in_block=False, cont=False, start=None) + state.update(name="", static=False, sig=0, opened=0, body=[]) + return state + + +def _scan_line(state: dict, line: str, number: int) -> None: + """ + Apply one source line to the scanner state. + + Parameters + ---------- + state : dict + Scanner accumulation state. + line : str + Raw source line. + number : int + One-based line number. + + Returns + ------- + None + """ + code, state["in_block"] = _strip_line(line, state["in_block"]) + _scan_open(state, code, number) + active = state["start"] is not None + if active and number not in (state["start"], state["opened"]): + _collect(code, number, state["body"]) + state["depth"] += code.count("{") - code.count("}") + _scan_close(state, number) + state["cont"] = line.rstrip().endswith("\\") + + +def _scan_open(state: dict, code: str, number: int) -> None: + """ + Open a signature, body, or prototype when one begins. + + Parameters + ---------- + state : dict + Scanner accumulation state. + code : str + Comment-free source line. + number : int + One-based line number. + + Returns + ------- + None + """ + if state["cont"] or state["start"] is not None: + return + if state["depth"] != 0: + return + _pending(state, code, number) + + +def _pending(state: dict, code: str, number: int) -> None: + """ + Resolve a file-scope signature fragment into a record. + + Parameters + ---------- + state : dict + Scanner accumulation state. + code : str + Comment-free source line. + number : int + One-based line number. + + Returns + ------- + None + """ + if state["sig"] == 0 and _proto_line(code): + _add_proto(state, code, number) + elif state["sig"] == 0 and _sig_start(code): + _start_sig(state, code, number) + elif state["sig"] and "{" in code: + _start_body(state, number) + elif state["sig"] and ";" in code: + _finish_proto(state) + + +def _add_proto(state: dict, code: str, number: int) -> None: + """ + Record a single-line function prototype. + + Parameters + ---------- + state : dict + Scanner accumulation state. + code : str + Comment-free source line. + number : int + One-based line number. + + Returns + ------- + None + """ + state["protos"].append({"name": _func_name(code), "start": number}) + + +def _start_sig(state: dict, code: str, number: int) -> None: + """ + Begin a multi-line signature or same-line definition. + + Parameters + ---------- + state : dict + Scanner accumulation state. + code : str + Comment-free source line. + number : int + One-based line number. + + Returns + ------- + None + """ + state["sig"] = number + state["name"] = _func_name(code) + state["static"] = code.lstrip().startswith("static") + if "{" in code: + _start_body(state, number) + + +def _finish_proto(state: dict) -> None: + """ + Record a wrapped prototype at its terminating semicolon. + + Parameters + ---------- + state : dict + Scanner accumulation state. + + Returns + ------- + None + """ + state["protos"].append({"name": state["name"], "start": state["sig"]}) + state["sig"] = 0 + state["name"] = "" + state["static"] = False + + +def _start_body(state: dict, number: int) -> None: + """ + Open a new function body at the given line. + + Parameters + ---------- + state : dict + Scanner accumulation state. + number : int + One-based opening line number. + + Returns + ------- + None + """ + state["start"] = state["sig"] + state["opened"] = number + state["body"] = [] + state["sig"] = 0 + + +def _scan_close(state: dict, number: int) -> None: + """ + Close the current function body when its depth returns to zero. + + Parameters + ---------- + state : dict + Scanner accumulation state. + number : int + One-based line number. + + Returns + ------- + None + """ + if state["start"] is None or state["depth"] > 0: + return + if number <= state["start"]: + return + state["records"].append(_record(state, number)) + _reset(state) + + +def _reset(state: dict) -> None: + """ + Clear the active-function fields of the scanner state. + + Parameters + ---------- + state : dict + Scanner accumulation state. + + Returns + ------- + None + """ + state["start"] = None + state["name"] = "" + state["sig"] = 0 + state["opened"] = 0 + state["static"] = False + + +def _sig_start(code: str) -> bool: + """ + Detect the first line of a function definition signature. + + Parameters + ---------- + code : str + Comment-free source line. + + Returns + ------- + bool + True when the line begins a function definition signature. + """ + text = code.strip() + if not text or text.startswith("#") or text.startswith("}"): + return False + if "(" not in text or text.endswith(";"): + return False + return "=" not in text.split("(")[0] + + +def _proto_line(code: str) -> bool: + """ + Detect a complete single-line function prototype. + + Parameters + ---------- + code : str + Comment-free source line. + + Returns + ------- + bool + True when the line is a function prototype. + """ + text = code.strip() + if not text or text.startswith("#") or "(" not in text: + return False + if not text.endswith(";") or "=" in text.split("(")[0]: + return False + return text.split()[0] not in {"typedef", "return"} + + +def _collect(code: str, number: int, body: list) -> None: + """ + Append one executable or declaration line to the body list. + + Parameters + ---------- + code : str + Comment-free source line. + number : int + One-based line number. + body : list + Mutable body accumulator. + + Returns + ------- + None + """ + text = code.strip() + if not text or text in {"{", "}"} or text.startswith("}"): + return + body.append((number, text)) + + +def _record(state: dict, end: int) -> dict: + """ + Build a function record from the scanner state. + + Parameters + ---------- + state : dict + Scanner accumulation state. + end : int + Closing brace line number. + + Returns + ------- + dict + Function record. + """ + return {"name": state["name"], "start": state["start"], "end": end, + "count": len(state["body"]), "static": state["static"]} + + +def _scan(path: Path) -> dict: + """ + Scan one file into records and prototypes. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + + Returns + ------- + dict + Scanner state with records and prototypes. + """ + state = _scan_state(path) + for number, line in enumerate(state["lines"], 1): + _scan_line(state, line, number) + return state + + +def _blank_lines(path: Path, records: list) -> list[int]: + """ + Find blank lines inside function bodies. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + records : list + Function records for the file. + + Returns + ------- + list[int] + One-based blank-line numbers. + """ + lines = path.read_text(encoding="utf-8").splitlines() + spans = [(r["start"], r["end"]) for r in records] + return [number for number, line in enumerate(lines, 1) + if not line.strip() and _inside(number, spans)] + + +def _inside(number: int, spans: list) -> bool: + """ + Check whether a line lies inside a function span. + + Parameters + ---------- + number : int + One-based source line number. + spans : list + Function start and end line pairs. + + Returns + ------- + bool + True when the line is inside a function body. + """ + return any(start < number < end for start, end in spans) + + +def _block_end(lines: list, start: int) -> int | None: + """ + Locate the closing line of the doc block above a signature. + + Parameters + ---------- + lines : list + Source lines. + start : int + One-based signature line number. + + Returns + ------- + int or None + Zero-based closing `*/` index, or None when absent. + """ + index = start - 2 + while index >= 0 and not lines[index].strip(): + index -= 1 + if index < 0 or "*/" not in lines[index]: + return None + return index + + +def _block_lines(lines: list, index: int) -> list: + """ + Collect the Doxygen block lines ending at an index. + + Parameters + ---------- + lines : list + Source lines. + index : int + Zero-based closing `*/` index. + + Returns + ------- + list + Block lines from opening `/**` through closing `*/`. + """ + block = [] + while index >= 0: + block.append(lines[index]) + if "/*" in lines[index]: + break + index -= 1 + block.reverse() + return block + + +def _is_doxygen(block: list) -> bool: + """ + Test whether a comment block is a Doxygen block with a brief. + + Parameters + ---------- + block : list + Comment block lines from opener through closer. + + Returns + ------- + bool + True when the block opens with `/**` and carries `@brief`. + """ + opener = block[0] if block else "" + return "/**" in opener and "@brief" in "\n".join(block) + + +def _doc_block(lines: list, start: int) -> list | None: + """ + Return the Doxygen block immediately above a signature. + + Parameters + ---------- + lines : list + Source lines. + start : int + One-based signature line number. + + Returns + ------- + list or None + Block lines, or None when no Doxygen block precedes the signature. + """ + index = _block_end(lines, start) + if index is None: + return None + block = _block_lines(lines, index) + if not _is_doxygen(block): + return None + return block + + +def _full_doc(block: list | None) -> bool: + """ + Check a static-function block for all required tags. + + Parameters + ---------- + block : list or None + Doxygen block lines. + + Returns + ------- + bool + True when @brief, @param, and @return are all present. + """ + if block is None: + return False + text = "\n".join(block) + return all(tag in text for tag in ("@brief", "@param", "@return")) + + +def _brief_doc(block: list | None) -> bool: + """ + Check a prototype block for a brief tag. + + Parameters + ---------- + block : list or None + Doxygen block lines. + + Returns + ------- + bool + True when a @brief tag is present. + """ + return block is not None and "@brief" in "\n".join(block) + + +def _c_doc_errors(path: Path, lines: list, records: list) -> list[str]: + """ + Find documentation-placement errors in a C source file. + + Parameters + ---------- + path : pathlib.Path + C source path. + lines : list + Source lines. + records : list + Function records for the file. + + Returns + ------- + list[str] + Human-readable documentation errors. + """ + errors = [] + for record in records: + block = _doc_block(lines, record["start"]) + if record["static"] and not _full_doc(block): + errors.append(f"{path}: {record['name']} static needs full doc") + if not record["static"] and block is not None: + errors.append(f"{path}: {record['name']} exported has doc block") + return errors + + +def _h_doc_errors(path: Path, lines: list, protos: list) -> list[str]: + """ + Find prototypes missing a @brief block in a header. + + Parameters + ---------- + path : pathlib.Path + Header path. + lines : list + Source lines. + protos : list + Prototype records for the file. + + Returns + ------- + list[str] + Human-readable documentation errors. + """ + errors = [] + for proto in protos: + if not _brief_doc(_doc_block(lines, proto["start"])): + errors.append(f"{path}: {proto['name']} missing @brief") + return errors + + +def _doc_errors(path: Path, state: dict) -> list[str]: + """ + Apply the suffix-specific documentation rules. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + state : dict + Scanner state with records and prototypes. + + Returns + ------- + list[str] + Human-readable documentation errors. + """ + lines = state["lines"] + if path.suffix == ".c": + return _c_doc_errors(path, lines, state["records"]) + return _h_doc_errors(path, lines, state["protos"]) + + +def _dash_errors(path: Path) -> list[str]: + """ + Find em/en dashes in one file. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + + Returns + ------- + list[str] + Dash diagnostics. + """ + text = path.read_text(encoding="utf-8") + errors = [] + if EN_DASH in text: + errors.append(f"{path}: en dash U+2013 present") + if EM_DASH in text: + errors.append(f"{path}: em dash U+2014 present") + return errors + + +def _audit_file(path: Path) -> int: + """ + Audit one file and print its violations. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + + Returns + ------- + int + One when any violation was found, otherwise zero. + """ + state = _scan(path) + blank = _blank_lines(path, state["records"]) + long = [r for r in state["records"] if r["count"] > MAX_EXEC_LINES] + docs = _doc_errors(path, state) + dashes = _dash_errors(path) + _report(path, blank, long, docs, dashes) + return int(bool(blank) or bool(long) or bool(docs) or bool(dashes)) + + +def _report(path: Path, blank: list, long: list, docs: list, + dashes: list) -> None: + """ + Print one file's audit findings. + + Parameters + ---------- + path : pathlib.Path + C or header source path. + blank : list + Blank line numbers inside bodies. + long : list + Functions over the executable-line limit. + docs : list + Documentation errors. + dashes : list + Dash errors. + + Returns + ------- + None + """ + if blank: + print(f"{path}: blank lines in body {blank}") + for record in long: + print(f"{path}: {record['name']} has {record['count']} exec lines") + for error in docs: + print(error) + for error in dashes: + print(error) + + +def main() -> int: + """ + Audit all owned C and header files. + + Parameters + ---------- + None + + Returns + ------- + int + Zero for a clean audit, otherwise one. + """ + failures = 0 + for path in _owned_files(): + failures += _audit_file(path) + return int(bool(failures)) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/Embedded-Hacking.png b/Embedded-Hacking.png new file mode 100644 index 0000000..283fec6 Binary files /dev/null and b/Embedded-Hacking.png differ diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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+ +--- +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** +--- + +
+ +## FREE Reverse Engineering Self-Study Course [HERE](https://github.com/mytechnotalent/Reverse-Engineering) + +
+ +# Today's Tutorial [October 20, 2026] +## Lesson 331: Hacking Bits Course (Chapter 9: IO Driver in C) +This chapter covers the development and reverse engineering of an IO driver in C. + +-> Click [HERE](https://github.com/mytechnotalent/Hacking-Bits/blob/main/hacking-bits.pdf) to read the FREE pdf book. + +
+ +# Embedded Hacking +A FREE comprehensive step-by-step embedded hacking course covering Embedded Software Development to Reverse Engineering. + +VIDEO PROMO [HERE](https://www.youtube.com/watch?v=aD7X9sXirF8) + +
+ +# FREE Book [Download](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) + +
+ +# Required Skills +Students must have a working understanding of the following items: + +- **Intermediate C Programming:** In particular, you must understand how pointers reference memory addresses which we will use to perform live variable hijacking. + - Training Link [HERE](https://www.learn-c.org) +- **Bare-Metal Embedded Systems Assembly Basics:** You must have experience with bare-metal assembly as we will be using this extensively throughout the entire course specifically with GDB and Ghidra. + - Training Link [HERE](https://azeria-labs.com/writing-arm-assembly-part-1) +- **Computer Architecture Basics (Registers & Stack):** You need a working mental model of how a CPU/MCU uses registers and the stack to follow the boot process and function calls. + - Training Link [HERE](https://www.geeksforgeeks.org/computer-science-fundamentals/what-is-register-memory) + - Training Link [HERE](https://www.geeksforgeeks.org/computer-organization-architecture/memory-stack-organization-in-computer-architecture) +- **Command Line Interface (CLI) Proficiency:** You must be comfortable navigating directories and executing commands in a terminal to run the necessary OpenOCD and GDB tools. + - Training Link [HERE](https://www.freecodecamp.org/news/command-line-commands-cli-tutorial) +- **Breadboarding Proficiency:** You must be comfortable demonstrating breadboard proficiency by efficiently prototyping circuits and integrating diverse peripherals, sensors, and microcontrollers. + - Training Video [HERE](https://www.youtube.com/watch?v=fq6U5Y14oM4) + +
+ +# Hardware + +### Reference Diagrams & Schematics +- [Fritzing Project](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/EHP2.fzz) +- [Breadboard Diagram](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/EHP2_bb.png) +- [Pico 2 Pinout](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/pico-2-r4-pinout.svg) +- [Debug Probe Wiring](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/dp.png) + +### Required Components & Sensors +The following hardware parts and sensors are used throughout the course experiments, projects, and live CTFs: +- [1x Full-size Breadboard (Long)](https://www.amazon.com/s?k=full+size+breadboard) +- [1x Assorted Jumper Wires (Male-to-Male, Male-to-Female, Female-to-Female)](https://www.amazon.com/s?k=breadboard+jumper+wires+assortment) +- [1x Raspberry Pi Pico 2 w/ Header](https://www.amazon.com/s?k=raspberry+pi+pico+2+with+pre-soldered+header) +- [1x Raspberry Pi Pico Debug Probe](https://www.amazon.com/s?k=raspberry+pi+debug+probe) +- [2x USB A-Male to USB Micro-B Cables (1 for Pico 2, 1 for Debug Probe)](https://www.amazon.com/s?k=micro+usb+cable+2+pack) +- [3x 5mm LEDs (1 Red, 1 Green, 1 Yellow)](https://www.amazon.com/s?k=5mm+led+kit) +- [3x 100, 220 or 330 Ohm Resistors (for LEDs)](https://www.amazon.com/s?k=resistor+assortment+kit) +- [1x Push Button (Tactile switch)](https://www.amazon.com/s?k=tactile+push+button+assortment) +- [1x 1602 LCD (with PCF8574 I2C backpack)](https://www.amazon.com/s?k=1602+lcd+i2c+module) +- [1x DHT11 Temperature & Humidity Sensor](https://www.amazon.com/s?k=dht11+temperature+and+humidity+sensor) +- [1x SG90 Servo Motor](https://www.amazon.com/s?k=sg90+micro+servo+motor) +- [1x 1000uF 25V Capacitor](https://www.amazon.com/Cionyce-Capacitor-Electrolytic-CapacitorsMicrowave/dp/B0B63CCQ2N) +- [1x 100pcs 100nF DIP Ceramic Disc Capacitor](https://www.amazon.com/dp/B09XV2H8JQ) +- [1x Infrared (IR) Receiver (VS1838B)](https://www.amazon.com/s?k=vs1838b+ir+receiver+module) +- [1x Infrared (IR) Remote Controller (NEC-compatible)](https://www.amazon.com/s?k=arduino+ir+remote+control) +- [1x u-blox NEO-6M GPS Receiver Module (with Active Antenna)](https://www.amazon.com/Navigation-Positioning-Microcontroller-Compatible-Sensitivity/dp/B084MK8BS2) +- [2x REYAX RYLR998 868/915MHz LoRa Transceiver Modules (1x Pico 2, 1x Computer)](https://www.amazon.com/dp/B099RM1XMG) +- [1x FT232RL USB to TTL Serial Adapter Module](https://www.amazon.com/FT232RL-Serial-Adapter-Module-Arduino/dp/B0FHP71BCQ) + +

+ +# Breadboard Design +![image](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/EHP2_bb.png?raw=true) + +
+ +# Development Environment Setup + +Everything installs natively on Windows, macOS (Apple Silicon), and Linux x64 — **no VM required**. The core toolchain (Pico SDK, the full Arm GNU Toolchain — `arm-none-eabi-gcc`, `arm-none-eabi-gdb`, `arm-none-eabi-nm`, `objdump` — `picotool`, and OpenOCD) comes from the **Raspberry Pi Pico VS Code extension**, which installs it all under `~/.pico-sdk` on every platform. You then add two reverse-engineering tools and a serial monitor. `arm-none-eabi-gdb` is what the GDB and Binary Ninja (GDB MI) debugging labs use. + +## Windows x64 + +1. Install [VS Code](https://code.visualstudio.com/), [Git for Windows](https://git-scm.com/download/win), and [Python 3](https://www.python.org/downloads/) (check **Add python.exe to PATH**). +2. In VS Code open **Extensions**, search **Raspberry Pi Pico**, install it, and choose **Pico 2** as the board when prompted. This pulls the Pico SDK, Arm GNU Toolchain (includes `arm-none-eabi-gdb`), `picotool`, and OpenOCD. +3. Install [Binary Ninja Personal](https://binary.ninja/) and activate the license. +4. Install [Ghidra](https://github.com/NationalSecurityAgency/ghidra/releases) and [Eclipse Temurin JDK 21](https://adoptium.net/temurin/releases/?version=21). +5. Serial monitor: [PuTTY](https://www.putty.org/). + +## macOS Apple Silicon + +```bash +brew install cmake ninja +``` + +1. Install [VS Code](https://code.visualstudio.com/), then the **Raspberry Pi Pico** extension (choose **Pico 2**). This installs the Pico SDK, Arm GNU Toolchain (includes `arm-none-eabi-gdb`), `picotool`, and OpenOCD. +2. Install [Binary Ninja Personal](https://binary.ninja/) and activate the license. +3. Install Ghidra and JDK 21: `brew install --cask temurin@21`, then the [Ghidra release](https://github.com/NationalSecurityAgency/ghidra/releases). +4. Serial monitor: `screen` (built in). + +> Use the Apple Silicon Homebrew at `/opt/homebrew`. If `file "$(which cmake)"` reports `x86_64`, an Intel Homebrew at `/usr/local` is shadowing it — put `/opt/homebrew/bin` first on your `PATH`. Do **not** fix this with Rosetta; it produces debugger failures that look like bugs. + +## Linux x64 + +```bash +sudo apt update +sudo apt install git python3 cmake ninja-build build-essential screen +``` + +1. Install [VS Code](https://code.visualstudio.com/), then the **Raspberry Pi Pico** extension (choose **Pico 2**). This installs the Pico SDK, Arm GNU Toolchain (includes `arm-none-eabi-gdb`), `picotool`, and OpenOCD. +2. Install [Binary Ninja Personal](https://binary.ninja/) and activate the license. +3. Install Ghidra and JDK 21 (`sudo apt install openjdk-21-jdk`, then the [Ghidra release](https://github.com/NationalSecurityAgency/ghidra/releases)). +4. Serial monitor: `screen` or `minicom`. + +## Example: Compile and Flash `0x0001 hello, world` + +The **build** step is identical on all three platforms — CMake and Ninja are cross-platform, and the Pico extension's `~/.pico-sdk/cmake/pico-vscode.cmake` supplies the SDK, toolchain, and `picotool` paths on every OS. Only the **flash** and **serial** steps differ, so each platform is shown in full below. All three flash over the Debug Probe with SWD (`program 0x10000000 verify reset exit`) — no BOOTSEL, no UF2. + +### Windows x64 + +```powershell +cd WEEK01\0x0001_hello-world +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +..\..\flash.ps1 build\0x0001_hello-world.bin +``` +Serial monitor: **PuTTY** -> *Serial* -> the Debug Probe's COM port -> **115200**. + +### macOS Apple Silicon + +```bash +cd WEEK01/0x0001_hello-world +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +../../flash.sh build/0x0001_hello-world.bin +screen /dev/cu.usbmodem* 115200 +``` + +### Linux x64 + +```bash +cd WEEK01/0x0001_hello-world +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +../../flash.sh build/0x0001_hello-world.bin +screen /dev/ttyACM0 115200 +``` + +You should see `hello, world` repeat at 115200. + +> **If CMake cannot find the SDK or toolchain** (for example you installed the toolchain yourself instead of via the VS Code extension), pass them explicitly: +> ```bash +> cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release \ +> -DPICO_SDK_PATH="$HOME/.pico-sdk/sdk/2.2.0" \ +> -DPICO_TOOLCHAIN_PATH="$HOME/.pico-sdk/toolchain/14_2_Rel1" +> ``` +> On Windows use forward slashes, e.g. `C:/Users//.pico-sdk/sdk/2.2.0`. + +Debug Probe wiring is [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/hardware/dp.png). + +
+ +# Datasheets & References + +This repository includes the complete set of authoritative technical reference manuals and datasheets required for professional embedded engineering and reverse engineering on the Raspberry Pi Pico 2: + +### [RP2350 Datasheet](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/rp2350-datasheet.pdf) +*RP2350 Datasheet: A microcontroller by Raspberry Pi (1,380 pages)* +- **Core Architecture:** Dual Arm Cortex-M33 / Hazard3 RISC-V processors running up to 150MHz, 520kB on-chip SRAM across 10 striped banks, and 8kB one-time-programmable (OTP) storage. +- **System Memory Map (Chapter 2):** Complete physical address map covering external XIP Flash (`0x10000000`), SRAM (`0x20000000`), APB/AHB peripherals (`0x40000000`), and core-local Single-Cycle I/O (`0xd0000000`). +- **Peripheral Register Definitions:** Exhaustive register layouts, reset states, and bitfield descriptions for all 52 peripherals: `IO_BANK0` (pin multiplexing & `FUNCSEL`), `PADS_BANK0` (electrical drive strength, pulls, and Schmitt triggers), `UART0`/`UART1`, `SPI0`/`SPI1`, `I2C0`/`I2C1`, `PWM`, `DMA`, `CLOCKS`, and `WATCHDOG`. +- **Programmable I/O (PIO):** Comprehensive architectural guide for the 3 on-chip PIO blocks (`PIO0`, `PIO1`, `PIO2`) with 12 state machines for deterministic, high-speed custom hardware protocols. +- **Fast GPIO Coprocessor:** Hardware specification for single-cycle atomic GPIO output and direction control via dedicated ARM coprocessor instructions (`mcrr p0`). +- **Bootrom & Hardware Security:** Covers the internal mask ROM boot flow, secure boot signature verification, SHA-256 cryptographic accelerator, and OTP key protection. + +### [Raspberry Pi Pico C/C++ SDK](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/raspberry-pi-pico-c-sdk.pdf) +*Raspberry Pi Pico-series C/C++ SDK: Libraries and tools for development (821 pages)* +- **SDK Architecture & Build System:** CMake configuration, target library linking (`pico_stdlib`, `hardware_gpio`), compiler flags, and the UF2 binary packaging workflow. +- **Hardware Drivers (`hardware_*`):** Low-level driver API documentation: + - `hardware_gpio`: Functions like `gpio_init()`, `gpio_set_dir()`, `gpio_put()`, `gpio_get()`, and hardware pin interrupt handling. + - `hardware_uart`: Serial communication initialization (`uart_init()`, baud rate dividers, FIFO handling). + - `hardware_dma`: Channel configuration, transfer sizing, and background memory pacing. + - `hardware_clocks` & `hardware_resets`: PLL frequency configuration and peripheral unreset sequencing. +- **High-Level Runtimes (`pico_*`):** Standard I/O stream redirection (`stdio_init_all()` over UART/USB CDC), multicore core 1 launching (`pico_multicore`), sleep timers, and thread synchronization. +- **Hardware Structs (`hardware_structs`):** C struct definitions matching chip MMIO registers 1-to-1, used by reverse engineers to reconstruct decompiled peripheral accesses. + +### [Arm Cortex-M33 Technical Reference Manual](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/arm_cortex_m33_trm_100230_0100_03_en.pdf) +*Arm® Cortex®-M33 Processor Technical Reference Manual (Doc ID: 100230_0100_03_en, 168 pages)* +- **Core Microarchitecture:** 3-stage in-order pipeline, Harvard bus architecture (instruction and data buses), integer execution core, and optional IEEE 754 single/double-precision floating-point unit (FPU). +- **Nested Vectored Interrupt Controller (NVIC):** Interrupt priorities, exception vector table mapping, low-latency interrupt entry, and hardware tail-chaining mechanics. +- **Memory Protection & TrustZone:** Memory Protection Unit (MPU) supporting up to 16 configurable regions, and Security Attribution Unit (SAU) for hardware-enforced Secure vs Non-secure domain isolation. +- **CoreSight Debug & Trace:** Debug Access Port (DAP) used by OpenOCD and the Raspberry Pi Debug Probe, Flash Patch and Breakpoint unit (FPB), Data Watchpoint and Trace (DWT), and Instrumentation Trace Macrocell (ITM). +- **Coprocessor Interface:** Bus architecture connecting hardware accelerators directly to the core (utilized by the RP2350 for single-cycle GPIO and math acceleration). + +### [Armv8-M Architecture Reference Manual (DDI0553B)](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/DDI0553B_y_armv8m_arm.pdf) +*Armv8-M Architecture Reference Manual (Doc ID: DDI0553B, 2,149 pages)* +- **Authoritative Instruction Set Reference (Section C2.4, Pages 527–1454):** Complete alphabetical encyclopedia of every assembly instruction supported by the RP2350 Cortex-M33: + - Data processing: `MOV`, `MOVS`, `MVN`, `ADD`, `SUB`, `MUL`, `SDIV`, `UDIV`, `AND`, `ORR`, `EOR`, `BIC`. + - Memory load/store: `LDR`, `STR`, `LDRB`, `STRB`, `LDRH`, `STRH`, `LDRD`, `STRD`, `LDM`, `STM`, `PUSH`, `POP`. + - Control flow: `B`, `BL`, `BX`, `BLX`, `CBZ`, `CBNZ`, `TBB`, `TBH`. + - Coprocessor instructions: `MCR`, `MRC`, `MCRR`, `MRRC` (used by the RP2350 fast GPIO block). + - Floating-point instructions: `VMOV`, `VADD`, `VSUB`, `VMUL`, `VDIV`, `VCMP`, `VMRS`, `VMSR`. +- **Machine Opcode Encodings:** Exact 16-bit Thumb and 32-bit Thumb-2 binary bit patterns for every instruction, essential for binary patching and shellcode analysis. +- **Programmer's Model:** General-purpose registers (`r0`–`r12`), Stack Pointers (`SP`/`MSP`/`PSP`), Link Register (`LR`), Program Counter (`PC`), Status Registers (`APSR`, `IPSR`, `EPSR`, `xPSR`), and Special Registers (`CONTROL`, `PRIMASK`). +- **Exception Mechanics:** Hardware state stacking upon exception entry (`r0`-`r3`, `r12`, `lr`, `pc`, `xPSR`), EXC_RETURN values, and fault analysis (HardFault, MemManage, BusFault, UsageFault). + +### [Procedure Call Standard for the Arm Architecture (AAPCS32)](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/aapcs32.pdf) +*Procedure Call Standard for the Arm® Architecture (AAPCS32 / ABI, 41 pages)* +- **Register Allocation Contract:** Defines caller and callee responsibilities across function calls: + - Parameter passing: `r0`–`r3` pass the first four 32-bit parameters (or 64-bit pairs like `r0`-`r1` and `r2`-`r3`). Additional parameters are pushed to the stack. + - Return values: `r0` returns 32-bit scalar values; `r0`-`r1` returns 64-bit integers and 64-bit IEEE 754 `double` floats. + - Scratch / Caller-Saved registers: `r0`–`r3`, `r12` (`IP`), and `r14` (`LR`) can be freely overwritten by called functions. + - Preserved / Callee-Saved registers: `r4`–`r11` must be preserved across function calls (saved via `push` in prologue and restored via `pop` in epilogue). +- **Floating-Point ABI:** Register allocation for hardware VFP registers (`s0`–`s15`, `d0`–`d7`) vs software floating-point library calls. +- **Data Alignment & Struct Packing:** Alignment rules (1, 2, 4, 8 bytes), structure member padding, and composite type memory layouts. + +### [ARM Application Note 132 (advnote132)](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/datasheets/advnote132.pdf) +*ABI Advisory Note – SP must be 8-byte aligned on entry to AAPCS-conforming functions (10 pages)* +- **The 8-Byte Stack Alignment Rule:** Mandates that the Stack Pointer (`SP`) must be aligned to an 8-byte (doubleword) boundary at all public function call interfaces. +- **Why Unaligned Stacks Fail:** 64-bit memory operations (`LDRD`, `STRD`) and double-precision floating-point operations require 8-byte alignment; misaligned stacks trigger hardware alignment faults or severe memory bus performance penalties. +- **Prologue Disassembly Deconstruction:** Explains why compiler-generated assembly frequently emits `push {r4, lr}` (saving two 32-bit registers) even when `r4` is completely unused—the extra register push serves as deliberate padding to keep `SP` strictly 8-byte aligned! + +
+ +# Syllabus + +## Week 1 +Introduction and Overview of Embedded Reverse Engineering: Ethics, Scoping, and Basic Concepts + +### Week 1 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK01/WEEK01-SLIDES.pdf) + +### Week 1 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK01/WEEK01.md) + +### Week 1a Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK01/WEEK01a.md) + +### Chapter 1: hello, world +This chapter covers the basics of setting up a dev environment and basic template firmware for the Pico 2 MCU in addition to printing hello, world. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 2: Debugging hello, world +This chapter covers the debugging of our firmware for the Pico 2 MCU hello, world program. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 2 +Hello, World - Debugging and Hacking Basics: Debugging and Hacking a Basic Program for the Pico 2 + +### Week 2 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK02/WEEK02-SLIDES.pdf) + +### Week 2 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK02/WEEK02.md) + +### Chapter 3: Hacking hello, world +This chapter covers the hacking of our firmware for the Pico 2 MCU hello, world program. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 3 +Embedded System Analysis: Understanding the RP2350 Architecture w/ Comprehensive Firmware Analysis + +### Week 3 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK03/WEEK03-SLIDES.pdf) + +### Week 3 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK03/WEEK03.md) + +### Ghidra Patching Tutorial [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK03/GHIDRA_PATCHING_TUTORIAL.md) + +### CTF-01 Instructions [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/0x0001b_ctf/CTF-01-I.md) + +### CTF-01 Rubric [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/0x0001b_ctf/CTF-01-R.md) + +### CTF-01 Solution [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/0x0001b_ctf/CTF-01-S.md) + +### CTF-01 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/0x0001b_ctf/CTF-01.bin) + +### CTF-01 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/0x0001b_ctf/CTF-01.uf2) + +### Chapter 4: Embedded System Analysis +This chapter covers a comprehensive embedded system analysis reviewing parts of the RP2350 datasheet and helpful firmware analysis tools. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 4 +Variables in Embedded Systems: Debugging and Hacking Variables w/ GPIO Output Basics + +### Week 4 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/WEEK04-SLIDES.pdf) + +### Week 4 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/WEEK04.md) + +### Week 4a Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/WEEK04a.md) + +### Week 4-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/WEEK04-BN.md) + +### Week 4-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/WEEK04-IDA.md) + +### RP2350 SVD [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK04/rp2350.svd) + +### Chapter 5: Intro To Variables +This chapter covers an introduction to variables as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 6: Debugging Intro To Variables +This chapter covers debugging an introduction to variables as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 7: Hacking Intro To Variables +This chapter covers hacking an introduction to variables as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 8: Uninitialized Variables +This chapter covers uninitialized variables as well as an intro to GPIO outputs as we blink an LED as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 9: Debugging Uninitialized Variables +This chapter covers debugging uninitialized variables as well as an intro to GPIO outputs as we blink an LED as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 10: Hacking Uninitialized Variables +This chapter covers hacking uninitialized variables as well as an intro to GPIO outputs as we blink an LED as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 5 +Integers and Floats in Embedded Systems: Debugging and Hacking Integers and Floats w/ Intermediate GPIO Output Assembler Analysis + +### Week 5 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/WEEK05-SLIDES.pdf) + +### Week 5 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/WEEK05.md) + +### Week 5a Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/WEEK05a.md) + +### Week 5-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/WEEK05-BN.md) + +### Week 5-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/WEEK05-IDA.md) + +### Float/Hex Converter Tool [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK05/float_hex_converter.py) + +### Chapter 11: Integer Data Type +This chapter covers the integer data type in addition to a deeper assembler dive into GPIO outputs as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 12: Debugging Integer Data Type +This chapter covers debugging the integer data type in addition to a deeper assembler dive into GPIO outputs as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 13: Hacking Integer Data Type +This chapter covers hacking the integer data type in addition to a deeper assembler dive into GPIO outputs as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 14: Floating-Point Data Type +This chapter covers the floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 15: Debugging Floating-Point Data Type +This chapter covers debugging the floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 16: Hacking Floating-Point Data Type +This chapter covers hacking the floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 17: Double Floating-Point Data Type +This chapter covers the double floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 18: Debugging Double Floating-Point Data Type +This chapter covers debugging the double floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 19: Hacking Double Floating-Point Data Type +This chapter covers hacking the double floating-point data type as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 6 +Static Variables in Embedded Systems: Debugging and Hacking Static Variables w/ GPIO Input Basics + +### Classified Brief 0x01 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.md) + +### Classified Brief 0x01 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/0x0011a_cb/0x0011a_cb.bin) + +### Classified Brief 0x01 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/0x0011a_cb/0x0011a_cb.uf2) + +### Week 6 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/WEEK06-SLIDES.pdf) + +### Week 6 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/WEEK06.md) + +### Week 6-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/WEEK06-BN.md) + +### Week 6-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK06/WEEK06-IDA.md) + +### Chapter 20: Static Variables +This chapter covers static variables as well as an intro to GPIO inputs as we work with push buttons as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 21: Debugging Static Variables +This chapter covers debugging static variables as well as an intro to GPIO inputs as we work with push buttons as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 22: Hacking Static Variables +This chapter covers hacking static variables as well as an intro to GPIO inputs as we work with push buttons as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 7 +Constants in Embedded Systems: Debugging and Hacking Constants w/ 1602 LCD I2C Basics + +### Classified Brief 0x02 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.md) + +### Classified Brief 0x02 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0014a_cb/0x0014a_cb.bin) + +### Classified Brief 0x02 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0014a_cb/0x0014a_cb.uf2) + +### Week 7 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/WEEK07-SLIDES.pdf) + +### Week 7 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/WEEK07.md) + +### Week 7-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/WEEK07-BN.md) + +### Week 7-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/WEEK07-IDA.md) + +### Chapter 23: Constants +This chapter covers constants as well as an intro to I2C as we work a 1602 LCD as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 24: Debugging Constants +This chapter covers debugging constants as well as an intro to I2C as we work a 1602 LCD as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 25: Hacking Constants +This chapter covers hacking constants as well as an intro to I2C as we work a 1602 LCD as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 8 +### Midterm Exam + +### CTF-02 Instructions [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0017a_ctf/CTF-02-I.md) + +### CTF-02 Rubric [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0017a_ctf/CTF-02-R.md) + +### CTF-02 Solution [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0017a_ctf/CTF-02-S.md) + +### CTF-02 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0017a_ctf/CTF-02.bin) + +### CTF-02 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK07/0x0017a_ctf/CTF-02.uf2) + +## Week 9 +Operators in Embedded Systems: Debugging and Hacking Operators w/ DHT11 Temperature & Humidity Sensor Single-Wire Protocol Basics + + +### Classified Brief 0x03 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.md) + +### Classified Brief 0x03 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/0x001aa_cb/0x001aa_cb.bin) + +### Classified Brief 0x03 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/0x001aa_cb/0x001aa_cb.uf2) + +### Week 9 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/WEEK09-SLIDES.pdf) + +### Week 9 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/WEEK09.md) + +### Week 9-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/WEEK09-BN.md) + +### Week 9-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK09/WEEK09-IDA.md) + +### Chapter 26: Operators +This chapter covers operators as well as an intro to single-wire protocol as we work a DHT11 temperature and humidity sensor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 27: Debugging Operators +This chapter covers debugging operators as well as an intro to single-wire protocol as we work a DHT11 temperature and humidity sensor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 28: Hacking Operators +This chapter covers hacking operators as well as an intro to single-wire protocol as we work a DHT11 temperature and humidity sensor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 10 +Conditionals in Embedded Systems: Debugging and Hacking Static & Dynamic Conditionals w/ SG90 Servo Motor PWM Basics + + +### Classified Brief 0x04 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.md) + +### Classified Brief 0x04 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/0x001da_cb/0x001da_cb.bin) + +### Classified Brief 0x04 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/0x001da_cb/0x001da_cb.uf2) + +## Week 10 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/WEEK10-SLIDES.pdf) + +## Week 10 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/WEEK10.md) + +## Week 10-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/WEEK10-BN.md) + +## Week 10-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK10/WEEK10-IDA.md) + +### Chapter 29: Static Conditionals +This chapter covers static conditionals as well as an intro to PWM as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 30: Debugging Static Conditionals +This chapter covers debugging static conditionals as well as an intro to PWM as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 31: Hacking Static Conditionals +This chapter covers hacking static conditionals as well as an intro to PWM as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 32: Dynamic Conditionals +This chapter covers dynamic conditionals as well as additional PWM examples as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 33: Debugging Dynamic Conditionals +This chapter covers debugging dynamic conditionals as well as additional PWM examples as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 34: Hacking Dynamic Conditionals +This chapter covers hacking dynamic conditionals as well as additional PWM examples as we work a SG90 servo motor as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 11 +Structures and Functions in Embedded Systems: Debugging and Hacking w/ IR Remote Control and NEC Protocol Basics + + +### Classified Brief 0x05 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.md) + +### Classified Brief 0x05 BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0020a_cb/0x0020a_cb.bin) + +### Classified Brief 0x05 UF2 [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0020a_cb/0x0020a_cb.uf2) + +## Week 11 Slides [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/WEEK11-SLIDES.pdf) + +## Week 11 Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/WEEK11.md) + +## Week 11a Secure Boot + Custom Bootloader Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/WEEK11a.md) + +### 0x0026a Custom Secure Bootloader [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0026a_custom-bootloader/README.md) + +### 0x0026a Bootloader BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.bin) + +### 0x0026a Signed Application BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0026a_custom-bootloader/0x0026a_app.bin) + +### 0x0026a Manifest BIN [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0026a_custom-bootloader/manifest.bin) + +### 0x0026a Full Secure Boot UF2 (bootloader + manifest + app) [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/0x0026a_custom-bootloader/0x0026a_full.uf2) + +## Week 11-BN Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/WEEK11-BN.md) + +## Week 11-IDA Notebook [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/WEEK11/WEEK11-IDA.md) + +### Chapter 35: Structures +This chapter covers structures as well as an intro to infrared basics as we work a infrared receiver and infrared remote controller as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 36: Debugging Structures +This chapter covers debugging structures as well as an intro to infrared basics as we work a infrared receiver and infrared remote controller as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 37: Hacking Structures +This chapter covers hacking structures as well as an intro to infrared basics as we work a infrared receiver and infrared remote controller as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 38: Functions, w/ Param, w/ Return +This chapter covers functions, w/ params and w/ a return value as well as additional infrared examples as we work a infrared receiver and infrared remote controller it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 39: Debugging Functions, w/ Param, w/ Return +This chapter covers debugging functions, w/ params and w/ a return value as well as additional infrared examples as we work a infrared receiver and infrared remote controller as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +### Chapter 40: Hacking Functions, w/ Param, w/ Return +This chapter covers hacking functions, w/ params and w/ a return value as it relates to embedded development on the Pico 2. + +-> Click [HERE](https://github.com/mytechnotalent/Embedded-Hacking/blob/main/textbook/Embedded-Hacking.pdf) to read the FREE pdf book. + +## Week 12 +Unknown Firmware Debugging and Hacking + +## Week 13 +Final Review – Embedded Debugging and Hacking Techniques w/ Advanced Firmware Analysis Q&A + +## Week 14 +### Final Projects + +### Final Project Option 1: The InfuSafe Pro Incident +In the aftermath of a catastrophic medical device failure, you are thrust into the role of an FDA forensic investigator facing an impossible crisis: 23 patients dead, 100 million recalled insulin pumps sitting in warehouses worldwide, and 2.3 million lives hanging in the balance all while the only evidence remaining is raw binary firmware after a rogue engineer destroyed every line of source code before fleeing to Montenegro. Armed only with GDB, Ghidra, and the reverse engineering skills honed over the first seven weeks of this course, you must excavate the truth from machine code, identify the lethal bugs spawned by an AI code generator called "OopsieGPT," and determine whether these devices can be salvaged to save millions in underserved communities or if $4.7 billion in humanitarian medical technology must be incinerated. This is not a simulation; this is triage at the intersection of embedded systems security and human survival. + +### Final Project Option 2: Operation Dark Eclipse +Forty-two stories beneath frozen tundra, a shadow intelligence alliance called Dark Eyes operates centrifuges enriching weapons-grade material for a first strike against Washington, D.C. and Agent NIGHTINGALE gave her life to extract the single firmware file that now sits before you. Conventional warfare cannot reach this fortress buried beneath rock and concrete, but you can: as the architect of a precision cyber weapon in the tradition of Stuxnet, you must reverse engineer the RP2350-based centrifuge controller, craft binary patches that double the spin speed while falsifying every sensor readout to show nominal operation, and execute the sabotage that will cascade-destroy their enrichment program and set their nuclear ambitions back a decade. Every skill from the entire semester ARM assembly, Ghidra analysis, IEEE-754 floating-point manipulation, branch modification, log desynchronization converges in this final mission. Agent NIGHTINGALE's seven-year-old daughter still watches the driveway, waiting for a mother who will never return. Honor that sacrifice. Complete the mission. Do not fail. + +
+ +# Supplemental Material (Beyond the Scope of the Course) + +## Pico 2 IoT Projects & CTFs + +### Act I of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/cold-chain-monitor) + +### Act I of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_cold-chain-monitor) + +### Act II of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/access-gate) + +### Act II of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_access-gate) + +### Act III of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/pipeline-valve-controller) + +### Act III of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_pipeline-valve-controller) + +### Act IV of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/hvac-automation-node) + +### Act IV of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_hvac-automation-node) + +### Act V of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/industrial-tamper-system) + +### Act V of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_industrial-tamper-system) + +### Act VI of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/smart-logistics-dropbox) + +### Act VI of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_smart-logistics-dropbox) + +### Act VII of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/factory-andon-station) + +### Act VII of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_factory-andon-station) + +### Act VIII of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/datacenter-vent-controller) + +### Act VIII of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_datacenter-vent-controller) + +### Act IX of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/smart-parking-barrier) + +### Act IX of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_smart-parking-barrier) + +### Act X of OPERATION COLD IRON [HERE](https://github.com/mytechnotalent/chemical-warning-terminal) + +### Act X of OPERATION COLD IRON CTF [HERE](https://github.com/mytechnotalent/CTF_chemical-warning-terminal) + +
+ +## Pi 4B/5 Embedded Linux C IoT Project & CTF + +### OPERATION TELESCREEN [HERE](https://github.com/mytechnotalent/telescreen) + +### OPERATION TELESCREEN CTF [HERE](https://github.com/mytechnotalent/CTF_telescreen) + +
+ +## Pico 2 W C MeshCore Project + +### MeshCore Bare RP2350 [HERE](https://github.com/mytechnotalent/meshcore-bare-rp2350) + +
+ +## Pico 2 Rust Tutorial + +### Chapter 1: What Is Embedded Rust? +This lesson will teach what embedded Rust is within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-01.md) to read the lesson and see the code. + +### Chapter 2: Number Systems and Memory +This lesson will teach number systems and memory within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-02.md) to read the lesson and see the code. + +### Chapter 3: Rust Essentials +This lesson will teach the Rust essentials within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-03.md) to read the lesson and see the code. + +### Chapter 4: Ownership, Borrowing, and Lifetimes +This lesson will teach ownership, borrowing and lifetimes within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-04.md) to read the lesson and see the code. + +### Chapter 5: Structs, Enums, and Pattern Matching +This lesson will teach structs, enums and pattern matching within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-05.md) to read the lesson and see the code. + +### Chapter 6: Traits and Generics +This lesson will teach traits and generics within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-06.md) to read the lesson and see the code. + +### Chapter 7: no_std and no_main +This lesson will teach no_std and no_main within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-07.md) to read the lesson and see the code. + +### Chapter 8: Cargo, Targets, and the Toolchain +This lesson will teach cargo, targets and the toolchain within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-08.md) to read the lesson and see the code. + +### Chapter 9: memory.x and the Linker Script +This lesson will teach the memory.x linker script within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-09.md) to read the lesson and see the code. + +### Chapter 10: build.rs, Makefile, and Flashing +This lesson will teach the build.rs, Makefile and flashing process within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-10.md) to read the lesson and see the code. + +### Chapter 11: Memory-Mapped I/O +This lesson will teach memory-mapped I/O within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-11.md) to read the lesson and see the code. + +### Chapter 12: Real-Time and Concurrency +This lesson will teach real-time and concurrency within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-12.md) to read the lesson and see the code. + +### Chapter 13: Futures and async/await +This lesson will teach futures and async/await within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-13.md) to read the lesson and see the code. + +### Chapter 14: The Embassy Executor +This lesson will teach the Embassy executor within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-14.md) to read the lesson and see the code. + +### Chapter 15: embassy-time +This lesson will teach embassy-time within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-15.md) to read the lesson and see the code. + +### Chapter 16: The embassy-rp HAL +This lesson will teach the embassy-rp HAL within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-16.md) to read the lesson and see the code. + +### Chapter 17: GPIO with embassy-rp +This lesson will teach GPIO with embassy-rp within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-17.md) to read the lesson and see the code. + +### Chapter 18: Driver Architecture +This lesson will teach the driver architecture within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-18.md) to read the lesson and see the code. + +### Chapter 19: config.rs — Blink Configuration +This lesson will teach the config.rs blink configuration within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-19.md) to read the lesson and see the code. + +### Chapter 20: led.rs — The LED State Machine +This lesson will teach the led.rs LED state machine within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-20.md) to read the lesson and see the code. + +### Chapter 21: main.rs — The Async Blink Loop +This lesson will teach the main.rs async blink loop within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-21.md) to read the lesson and see the code. + +### Chapter 22: Button Hardware and Debouncing +This lesson will teach button hardware and debouncing within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-22.md) to read the lesson and see the code. + +### Chapter 23: button.rs — The Button Controller +This lesson will teach the button.rs button controller within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-23.md) to read the lesson and see the code. + +### Chapter 24: main.rs — The Button Polling Loop +This lesson will teach the main.rs button polling loop within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-24.md) to read the lesson and see the code. + +### Chapter 25: Host Testing with cargo test +This lesson will teach host testing with cargo test within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-25.md) to read the lesson and see the code. + +### Chapter 26: UART Fundamentals and the Echo Protocol +This lesson will teach UART fundamentals and the echo protocol within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-26.md) to read the lesson and see the code. + +### Chapter 27: uart.rs — The Echo State Machine +This lesson will teach the uart.rs echo state machine within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-27.md) to read the lesson and see the code. + +### Chapter 28: Interrupts and DMA — Interrupt-Driven UART +This lesson will teach interrupts and DMA interrupt-driven UART within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-28.md) to read the lesson and see the code. + +### Chapter 29: main.rs — The UART Echo Loop +This lesson will teach the main.rs UART echo loop within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-29.md) to read the lesson and see the code. + +### Chapter 30: The Complete Integration +This lesson will teach the complete integration within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-Rust-Tutorial/blob/main/CHAPTER-30.md) to read the lesson and see the code. + +
+ +## Pico 2 Rust Drivers + +### UART Driver [HERE](https://github.com/mytechnotalent/RP2350_Rust_UART_Driver) + +### Blink Driver [HERE](https://github.com/mytechnotalent/RP2350_Rust_Blink_Driver) + +### Button Driver [HERE](https://github.com/mytechnotalent/RP2350_Rust_Button_Driver) + +
+ +## Pico 2 ARM Assembler Tutorial + +### Chapter 1: What Is a Computer? +This lesson will teach you what is a computer with the fundamental model of computation that every computer shares with an intro to the RP2350 and ARM Cortex-M33. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-01.md) to read the lesson and see the code. + +### Chapter 2: Number Systems — Binary, Hexadecimal, and Decimal +This lesson will teach the basics of the three main number systems which are decimal, binary and hexadecimal. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-02.md) to read the lesson and see the code. + +### Chapter 3: Memory — Addresses, Bytes, Words, and Endianness +This lesson will teach the basics addresses, bytes, words and endianness within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-03.md) to read the lesson and see the code. + +### Chapter 4: What Is a Register? +This lesson will teach the general purpose registers within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-04.md) to read the lesson and see the code. + +### Chapter 5: Load-Store Architecture — How ARM Accesses Memory +This lesson will teach how ARM accesses memory with load and store architecture within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-05.md) to read the lesson and see the code. + +### Chapter 6: The Fetch-Decode-Execute Cycle in Detail +This lesson will teach the fetch and decode cycle in more detail within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-06.md) to read the lesson and see the code. + +### Chapter 7: ARM Cortex-M33 ISA Overview +This lesson will teach the ARM Cortex-M33 ISA overview within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-07.md) to read the lesson and see the code. + +### Chapter 8: ARM Immediate and Move Instructions +This lesson will teach ARM immediate and move instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-08.md) to read the lesson and see the code. + +### Chapter 9: ARM Arithmetic and Logic Instructions +This lesson will teach ARM arithmetic and logic instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-09.md) to read the lesson and see the code. + +### Chapter 10: ARM Memory Access Instructions +This lesson will teach ARM memory access instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-10.md) to read the lesson and see the code. + +### Chapter 11: ARM Branch Instructions +This lesson will teach ARM branch instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-11.md) to read the lesson and see the code. + +### Chapter 12: ARM Calls, Returns, and the Stack Frame +This lesson will teach ARM calls, returns and the stack frame within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-12.md) to read the lesson and see the code. + +### Chapter 13: Assembler Directives +This lesson will teach assembler directives within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-13.md) to read the lesson and see the code. + +### Chapter 14: Labels, Symbols, and the Symbol Table +This lesson will teach labels, symbols and the symbol table within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-14.md) to read the lesson and see the code. + +### Chapter 15: Sections, Memory Layout, and the Linker Script +This lesson will teach sections, memory layout, and the linker script within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-15.md) to read the lesson and see the code. + +### Chapter 16: System Registers and Coprocessor Interface +This lesson will teach system registers and coprocessor interface within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-16.md) to read the lesson and see the code. + +### Chapter 17: Bit Manipulation Patterns +This lesson will teach bit manipulation patterns within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-17.md) to read the lesson and see the code. + +### Chapter 18: RP2350 Hardware Architecture +This lesson will teach RP2350 hardware architecture within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-18.md) to read the lesson and see the code. + +### Chapter 19: The Linker Script +This lesson will teach the linker script within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-19.md) to read the lesson and see the code. + +### Chapter 20: The Build System +This lesson will teach the build system within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-20.md) to read the lesson and see the code. + +### Chapter 21: image_def.s — The PICOBIN Boot Block +This lesson will teach the PICOBIN boot block within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-21.md) to read the lesson and see the code. + +### Chapter 22: constants.s — Memory Addresses and Constants +This lesson will teach memory addresses and constants within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-22.md) to read the lesson and see the code. + +### Chapter 23: vector_table.s and stack.s — Boot Foundation +This lesson will teach the boot foundation within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-23.md) to read the lesson and see the code. + +### Chapter 24: reset_handler.s — The Boot Sequence +This lesson will teach the boot sequence within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-24.md) to read the lesson and see the code. + +### Chapter 25: xosc.s — Crystal Oscillator and Clock Configuration +This lesson will teach the crystal oscillator and clock configuration within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-25.md) to read the lesson and see the code. + +### Chapter 26: reset.s — Releasing Peripherals from Reset +This lesson will teach releasing peripherals from reset within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-26.md) to read the lesson and see the code. + +### Chapter 27: gpio.s Part 1 — GPIO_Config +This lesson will teach GPIO config within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-27.md) to read the lesson and see the code. + +### Chapter 28: gpio.s Part 2, delay.s, and coprocessor.s — Output Control and Timing +This lesson will teach output control and timing within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-28.md) to read the lesson and see the code. + +### Chapter 29: main.s — The Blink Loop +This lesson will teach the blink loop within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-29.md) to read the lesson and see the code. + +### Chapter 30: Full Integration — From Source to Blinking LED +This lesson will teach the full source to blinking LED within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-ARM-ASM-Tutorial/blob/main/CHAPTER-30.md) to read the lesson and see the code. + +
+ +## Pico 2 ARM Assembler Drivers + +### UART Driver [HERE](https://github.com/mytechnotalent/RP2350_UART_Driver) + +### Blink Driver [HERE](https://github.com/mytechnotalent/RP2350_Blink_Driver) + +### Button Driver [HERE](https://github.com/mytechnotalent/RP2350_Button_Driver) + +
+ +## Pico 2 RISC-V Assembler Tutorial + +### Chapter 1: What Is a Computer? +This lesson will teach you what is a computer with the fundamental model of computation that every computer shares with an intro to the RP2350 and RISC-V. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-01.md) to read the lesson and see the code. + +### Chapter 2: Number Systems — Binary, Hexadecimal, and Decimal +This lesson will teach the basics of the three main number systems which are decimal, binary and hexadecimal. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-02.md) to read the lesson and see the code. + +### Chapter 3: Memory — Addresses, Bytes, Words, and Endianness +This lesson will teach the basics of addresses, bytes, words and endianness within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-03.md) to read the lesson and see the code. + +### Chapter 4: What Is a Register? +This lesson will teach the general purpose registers within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-04.md) to read the lesson and see the code. + +### Chapter 5: Load-Store Architecture — How RISC-V Accesses Memory +This lesson will teach how RISC-V accesses memory with load and store architecture within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-05.md) to read the lesson and see the code. + +### Chapter 6: The Fetch-Decode-Execute Cycle in Detail +This lesson will teach the fetch, decode and execute cycle in detail within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-06.md) to read the lesson and see the code. + +### Chapter 7: RISC-V Hazard3 ISA Overview +This lesson will teach the RISC-V Hazard3 ISA overview within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-07.md) to read the lesson and see the code. + +### Chapter 8: RISC-V Immediate and Upper-Immediate Instructions +This lesson will teach RISC-V immediate and upper-immediate instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-08.md) to read the lesson and see the code. + +### Chapter 9: RISC-V Arithmetic and Logic Instructions +This lesson will teach RISC-V arithmetic and logic instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-09.md) to read the lesson and see the code. + +### Chapter 10: RISC-V Memory Access — Load and Store Deep Dive +This lesson will teach RISC-V memory access load and store instructions in deep detail within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-10.md) to read the lesson and see the code. + +### Chapter 11: RISC-V Branch Instructions +This lesson will teach RISC-V branch instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-11.md) to read the lesson and see the code. + +### Chapter 12: RISC-V Jumps, Calls, and Returns +This lesson will teach RISC-V jumps, calls and returns within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-12.md) to read the lesson and see the code. + +### Chapter 13: RISC-V Pseudo-Instructions +This lesson will teach RISC-V pseudo-instructions within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-13.md) to read the lesson and see the code. + +### Chapter 14: Assembler Directives +This lesson will teach assembler directives within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-14.md) to read the lesson and see the code. + +### Chapter 15: Calling Convention and Stack Frames +This lesson will teach the calling convention and stack frames within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-15.md) to read the lesson and see the code. + +### Chapter 16: Bitwise Operations for Hardware Programming +This lesson will teach bitwise operations for hardware programming within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-16.md) to read the lesson and see the code. + +### Chapter 17: Memory-Mapped I/O +This lesson will teach memory-mapped I/O within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-17.md) to read the lesson and see the code. + +### Chapter 18: The RP2350 — Architecture and Hardware +This lesson will teach the RP2350 architecture and hardware within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-18.md) to read the lesson and see the code. + +### Chapter 19: The Linker Script — Placing Code in Memory +This lesson will teach the linker script and how code is placed in memory within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-19.md) to read the lesson and see the code. + +### Chapter 20: The Build Pipeline — From Assembly to Flashable Binary +This lesson will teach the build pipeline from assembly to flashable binary within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-20.md) to read the lesson and see the code. + +### Chapter 21: Boot Metadata — image_def.s +This lesson will teach the image_def.s boot metadata within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-21.md) to read the lesson and see the code. + +### Chapter 22: The Constants File — constants.s +This lesson will teach the constants.s file within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-22.md) to read the lesson and see the code. + +### Chapter 23: Stack and Vector Table — stack.s and vector_table.s +This lesson will teach the stack and vector table within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-23.md) to read the lesson and see the code. + +### Chapter 24: Boot Sequence — reset_handler.s +This lesson will teach the reset_handler.s boot sequence within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-24.md) to read the lesson and see the code. + +### Chapter 25: Oscillator Initialization — xosc.s +This lesson will teach the xosc.s oscillator initialization within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-25.md) to read the lesson and see the code. + +### Chapter 26: Reset Controller — reset.s +This lesson will teach the reset.s reset controller within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-26.md) to read the lesson and see the code. + +### Chapter 27: GPIO Configuration — gpio.s Part 1 +This lesson will teach the gpio.s GPIO configuration part 1 within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-27.md) to read the lesson and see the code. + +### Chapter 28: GPIO Set/Clear, Delay, and Coprocessor — gpio.s Part 2, delay.s, coprocessor.s +This lesson will teach the gpio.s GPIO set/clear, delay.s and coprocessor.s within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-28.md) to read the lesson and see the code. + +### Chapter 29: Application Entry Point — main.s +This lesson will teach the main.s application entry point within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-29.md) to read the lesson and see the code. + +### Chapter 30: Full Integration — Build, Flash, Wire, and Test +This lesson will teach the full build, flash, wire and test integration within the MCU. + +-> Click [HERE](https://github.com/mytechnotalent/RP2350-RISCV-ASM-Tutorial/blob/main/CHAPTER-30.md) to read the lesson and see the code. + +
+ +## Pico 2 RISC-V Assembler Drivers + +### UART Driver [HERE](https://github.com/mytechnotalent/RP2350_UART_Driver_RISCV) + +### Blink Driver [HERE](https://github.com/mytechnotalent/RP2350_Blink_Driver_RISCV) + +### Button Driver [HERE](https://github.com/mytechnotalent/RP2350_Button_Driver_RISCV) + +
+ +## Pico 2 Developer Projects + +### LED Chase and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-01-blink) + +### Traffic Light Phases and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-02-traffic-light) + +### Hardware PWM Breathing and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-03-led-pwm-breathing) + +### 1602 I2C LCD Text and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-04-lcd-hello) + +### Live LCD Counter and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-05-lcd-live) + +### SG90 Servo Sweep and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-06-servo-sweep) + +### SG90 Servo Position and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-07-servo-position) + +### SG90 Gauge Needle and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-08-servo-gauge) + +### Tactile Button Poll and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-09-button-poll) + +### Debounced Button Edges and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-10-button-debounce) + +### Short, Long, and Double Press Events and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-11-button-events) + +### DHT11 Temperature and Humidity Read and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-12-dht11-read) + +### DHT11 Reading on the 1602 I2C LCD and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-13-dht11-lcd) + +### DHT11 Comfort LEDs and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-14-dht11-leds) + +### VS1838B NEC Decode and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-15-ir-decode) + +### Remote Key Actions on the LEDs and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-16-ir-keys) + +### Remote Keypad Digits on the LEDs and 1602 I2C LCD and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-17-ir-keypad) + +### Remote Key Lamp Selection and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-18-ir-control-led) + +### Remote Key Preset Angles on the SG90 Servo and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-19-ir-control-servo) + +### Remote Key Status Pages on the 1602 I2C LCD and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-20-ir-lcd-status) + +### Two Way Token Echo and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-21-lora-echo) + +### DHT11 Telemetry and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-22-lora-telemetry) + +### Remote Command LEDs and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-23-lora-command) + +### ACK Timeout and Retry and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-24-lora-ack) + +### Address Filter and Sender Attribution and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-25-lora-addressing) + +### Signal Quality on the LCD and LEDs and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-26-lora-rssi) + +### Buffered Readings and Flush on Link Recovery and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-27-lora-store-forward) + +### Menu Navigation with the GP15 Button and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-28-lcd-menu-button) + +### Menu Navigation with the IR Remote and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-29-lcd-menu-remote) + +### Button and Remote Status Pages on the 1602 I2C LCD and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-30-status-pages) + +### Hysteresis Vent Control with an IR Setpoint and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-31-thermostat) + +### Latched Band Breach, Door Latch Servo, and an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-32-cold-chain-alarm) + +### Buffered Readings, Batched Flush, and an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-33-data-logger) + +### Gateway Command, Servo Position, and an Authenticated ACK [HERE](https://github.com/mytechnotalent/picokit-34-remote-actuator) + +### Latching Alarm LED, Local Acknowledge, and an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-35-annunciator-ack) + +### Timed Vent and LED Actions with an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-36-scheduler) + +### Random-Light Reaction Game, Button Time, and an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-37-reaction-timer) + +### Timed Intersection Phases, a Pedestrian Request, and an Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-38-traffic-controller) + +### Sealed Telemetry, Loopback Verify, and a Forged-Frame Reject [HERE](https://github.com/mytechnotalent/picokit-39-authenticated-telemetry) + +### Per-Node Monotonic Sequence, Replay Window, and a Rejected Replay [HERE](https://github.com/mytechnotalent/picokit-40-anti-replay) + +### Per-Device Key from a Device ID and Salt, Two Keys Proven Different [HERE](https://github.com/mytechnotalent/picokit-41-provisioning) + +### BLAKE2b Hash-Chained Event Log and Recompute on Read [HERE](https://github.com/mytechnotalent/picokit-42-tamper-log) + +### Debug Probe Breakpoints and SWD Variable Reads [HERE](https://github.com/mytechnotalent/picokit-43-swd-breakpoints) + +### Debug Probe Data Watchpoint on a Status Variable [HERE](https://github.com/mytechnotalent/picokit-44-swd-watchpoints) + +### Controlled Fault and Cortex-M33 Fault Status Registers [HERE](https://github.com/mytechnotalent/picokit-45-fault-analysis) + +### ELF and UF2 Inspection of a Known Constant [HERE](https://github.com/mytechnotalent/picokit-46-binary-recon) + +### Two-Node Mesh Relay and Authenticated Heartbeat [HERE](https://github.com/mytechnotalent/picokit-47-two-node-mesh) + +### Sensor Node and Charted Gateway [HERE](https://github.com/mytechnotalent/picokit-48-gateway-dashboard) + +### Fleet and Config Table with Multi-Node Gateway [HERE](https://github.com/mytechnotalent/picokit-49-fleet) + +### Full Peripheral Capstone and Authenticated Telemetry [HERE](https://github.com/mytechnotalent/picokit-50-finale) + +
+ +# License +[Apache License, Version 2.0](https://www.apache.org/licenses/LICENSE-2.0) diff --git a/WEEK01/0x0001_hello-world/.gitignore b/WEEK01/0x0001_hello-world/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK01/0x0001_hello-world/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK01/0x0001_hello-world/.vscode/c_cpp_properties.json b/WEEK01/0x0001_hello-world/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK01/0x0001_hello-world/.vscode/cmake-kits.json b/WEEK01/0x0001_hello-world/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK01/0x0001_hello-world/.vscode/extensions.json b/WEEK01/0x0001_hello-world/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK01/0x0001_hello-world/.vscode/launch.json b/WEEK01/0x0001_hello-world/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK01/0x0001_hello-world/.vscode/settings.json b/WEEK01/0x0001_hello-world/.vscode/settings.json new file mode 100644 index 0000000..688748a --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/settings.json @@ -0,0 +1,43 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja", + "files.associations": { + "stdlib.h": "c" + } +} diff --git a/WEEK01/0x0001_hello-world/.vscode/tasks.json b/WEEK01/0x0001_hello-world/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK01/0x0001_hello-world/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK01/0x0001_hello-world/0x0001_hello-world.c b/WEEK01/0x0001_hello-world/0x0001_hello-world.c new file mode 100644 index 0000000..096aba7 --- /dev/null +++ b/WEEK01/0x0001_hello-world/0x0001_hello-world.c @@ -0,0 +1,9 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} diff --git a/WEEK01/0x0001_hello-world/CMakeLists.txt b/WEEK01/0x0001_hello-world/CMakeLists.txt new file mode 100644 index 0000000..31d8fc5 --- /dev/null +++ b/WEEK01/0x0001_hello-world/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0001_hello-world C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0001_hello-world 0x0001_hello-world.c ) + +pico_set_program_name(0x0001_hello-world "0x0001_hello-world") +pico_set_program_version(0x0001_hello-world "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0001_hello-world 1) +pico_enable_stdio_usb(0x0001_hello-world 0) + +# Add the standard library to the build +target_link_libraries(0x0001_hello-world + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0001_hello-world PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0001_hello-world) + diff --git a/WEEK01/0x0001_hello-world/build/0x0001_hello-world.bin b/WEEK01/0x0001_hello-world/build/0x0001_hello-world.bin new file mode 100755 index 0000000..bc1e0ac Binary files /dev/null and b/WEEK01/0x0001_hello-world/build/0x0001_hello-world.bin differ diff --git a/WEEK01/0x0001_hello-world/build/0x0001_hello-world.dis b/WEEK01/0x0001_hello-world/build/0x0001_hello-world.dis new file mode 100644 index 0000000..08dec5d --- /dev/null +++ b/WEEK01/0x0001_hello-world/build/0x0001_hello-world.dis @@ -0,0 +1,2835 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000019cc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 0000014c 100019cc 100019cc 000029cc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10001b18 10001b18 00002b18 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10001b20 10001b20 00002b20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003cfc 2**0 + CONTENTS + 6 .data 0000019c 20000110 10001b4c 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 200002ac 200002ac 00003cfc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 200002ac 200002ac 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 200002b0 10001ce8 000042b0 2**3 + ALLOC + 10 .heap 00000800 200004d8 10001ce8 000044d8 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003cfc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003cfc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001ce8 10001ce8 00003ce8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003cfc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00003d30 2**0 + CONTENTS, READONLY + 17 .debug_info 0002069a 00000000 00000000 00003d75 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 000054ff 00000000 00000000 0002440f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000af0 00000000 00000000 00029910 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 00002f86 00000000 00000000 0002a400 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 0001562d 00000000 00000000 0002d386 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 000056be 00000000 00000000 000429b3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00001ed4 00000000 00000000 00048074 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000ffd1 00000000 00000000 00049f48 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 00000180 00000000 00000000 00059f19 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10001b20 .word 0x10001b20 +1000012c: 10001b4c .word 0x10001b4c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00001bb0 .word 0x00001bb0 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10001b4c .word 0x10001b4c +100001a4: 20000110 .word 0x20000110 +100001a8: 200002ac .word 0x200002ac +100001ac: 10001ce8 .word 0x10001ce8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001ce8 .word 0x10001ce8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 200002ac .word 0x200002ac +100001d4: 200004d8 .word 0x200004d8 +100001d8: 1000137d .word 0x1000137d +100001dc: 10000235 .word 0x10000235 +100001e0: 10001375 .word 0x10001375 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 200002ac .word 0x200002ac +10000208: 200002ac .word 0x200002ac +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000490 .word 0x20000490 +10000230: 100019cc .word 0x100019cc + +10000234
: +10000234: b508 push {r3, lr} +10000236: f001 f999 bl 1000156c +1000023a: 4802 ldr r0, [pc, #8] @ (10000244 ) +1000023c: f001 f9de bl 100015fc <__wrap_puts> +10000240: e7fb b.n 1000023a +10000242: bf00 nop +10000244: 100019cc .word 0x100019cc + +10000248 : +10000248: b410 push {r4} +1000024a: f44f 7480 mov.w r4, #256 @ 0x100 +1000024e: 4b0c ldr r3, [pc, #48] @ (10000280 ) +10000250: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000254: eb03 0380 add.w r3, r3, r0, lsl #2 +10000258: 00c0 lsls r0, r0, #3 +1000025a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000025e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000262: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000266: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000026a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000026e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000272: f8cc 2000 str.w r2, [ip] +10000276: 6041 str r1, [r0, #4] +10000278: 601c str r4, [r3, #0] +1000027a: f85d 4b04 ldr.w r4, [sp], #4 +1000027e: 4770 bx lr +10000280: 40038004 .word 0x40038004 + +10000284 : +10000284: b40f push {r0, r1, r2, r3} +10000286: b500 push {lr} +10000288: b083 sub sp, #12 +1000028a: 9c04 ldr r4, [sp, #16] +1000028c: 4807 ldr r0, [pc, #28] @ (100002ac ) +1000028e: f001 f9b5 bl 100015fc <__wrap_puts> +10000292: b13c cbz r4, 100002a4 +10000294: a905 add r1, sp, #20 +10000296: 4620 mov r0, r4 +10000298: 9101 str r1, [sp, #4] +1000029a: f001 f851 bl 10001340 +1000029e: 4804 ldr r0, [pc, #16] @ (100002b0 ) +100002a0: f001 f9ac bl 100015fc <__wrap_puts> +100002a4: 2001 movs r0, #1 +100002a6: f001 f863 bl 10001370 <_exit> +100002aa: bf00 nop +100002ac: 100019dc .word 0x100019dc +100002b0: 100019ec .word 0x100019ec + +100002b4 : +100002b4: b570 push {r4, r5, r6, lr} +100002b6: 4686 mov lr, r0 +100002b8: f3ef 8510 mrs r5, PRIMASK +100002bc: b672 cpsid i +100002be: 4c12 ldr r4, [pc, #72] @ (10000308 ) +100002c0: e8d4 6fcf ldaexb r6, [r4] +100002c4: 2001 movs r0, #1 +100002c6: 2e00 cmp r6, #0 +100002c8: d1fa bne.n 100002c0 +100002ca: e8c4 0f46 strexb r6, r0, [r4] +100002ce: 2e00 cmp r6, #0 +100002d0: d1f6 bne.n 100002c0 +100002d2: f3bf 8f5f dmb sy +100002d6: f04f 0c01 mov.w ip, #1 +100002da: 08c8 lsrs r0, r1, #3 +100002dc: f001 0307 and.w r3, r1, #7 +100002e0: fa0c f303 lsl.w r3, ip, r3 +100002e4: f81e c000 ldrb.w ip, [lr, r0] +100002e8: ea1c 0603 ands.w r6, ip, r3 +100002ec: d108 bne.n 10000300 +100002ee: ea4c 0c03 orr.w ip, ip, r3 +100002f2: f80e c000 strb.w ip, [lr, r0] +100002f6: e8c4 6f8f stlb r6, [r4] +100002fa: f385 8810 msr PRIMASK, r5 +100002fe: bd70 pop {r4, r5, r6, pc} +10000300: 4610 mov r0, r2 +10000302: f7ff ffbf bl 10000284 +10000306: bf00 nop +10000308: 2000043b .word 0x2000043b + +1000030c : +1000030c: 4a04 ldr r2, [pc, #16] @ (10000320 ) +1000030e: 7810 ldrb r0, [r2, #0] +10000310: 1c43 adds r3, r0, #1 +10000312: b2db uxtb r3, r3 +10000314: 2b18 cmp r3, #24 +10000316: bf28 it cs +10000318: 2310 movcs r3, #16 +1000031a: 7013 strb r3, [r2, #0] +1000031c: 4770 bx lr +1000031e: bf00 nop +10000320: 20000228 .word 0x20000228 + +10000324 : +10000324: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000328: 6893 ldr r3, [r2, #8] +1000032a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000032e: 6093 str r3, [r2, #8] +10000330: 4770 bx lr +10000332: bf00 nop + +10000334 : +10000334: 2100 movs r1, #0 +10000336: 4b04 ldr r3, [pc, #16] @ (10000348 ) +10000338: f103 0220 add.w r2, r3, #32 +1000033c: e8c3 1f8f stlb r1, [r3] +10000340: 3301 adds r3, #1 +10000342: 4293 cmp r3, r2 +10000344: d1fa bne.n 1000033c +10000346: 4770 bx lr +10000348: 20000430 .word 0x20000430 + +1000034c : +1000034c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000350: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000354: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000358: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000035c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000360: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000364: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000368: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000036c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000370: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000374: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000378: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000037c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000380: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000384: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000388: b662 cpsie i +1000038a: 4770 bx lr + +1000038c : +1000038c: 2301 movs r3, #1 +1000038e: f000 021f and.w r2, r0, #31 +10000392: 4093 lsls r3, r2 +10000394: 0940 lsrs r0, r0, #5 +10000396: b141 cbz r1, 100003aa +10000398: 0080 lsls r0, r0, #2 +1000039a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000039e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003a2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003a6: 6003 str r3, [r0, #0] +100003a8: 4770 bx lr +100003aa: 4a02 ldr r2, [pc, #8] @ (100003b4 ) +100003ac: 3020 adds r0, #32 +100003ae: f842 3020 str.w r3, [r2, r0, lsl #2] +100003b2: 4770 bx lr +100003b4: e000e100 .word 0xe000e100 + +100003b8 : +100003b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ba: 460d mov r5, r1 +100003bc: f3ef 8710 mrs r7, PRIMASK +100003c0: b672 cpsid i +100003c2: 4e12 ldr r6, [pc, #72] @ (1000040c ) +100003c4: e8d6 2fcf ldaexb r2, [r6] +100003c8: 2301 movs r3, #1 +100003ca: 2a00 cmp r2, #0 +100003cc: d1fa bne.n 100003c4 +100003ce: e8c6 3f42 strexb r2, r3, [r6] +100003d2: 2a00 cmp r2, #0 +100003d4: d1f6 bne.n 100003c4 +100003d6: f3bf 8f5f dmb sy +100003da: 4b0d ldr r3, [pc, #52] @ (10000410 ) +100003dc: f100 0410 add.w r4, r0, #16 +100003e0: 689b ldr r3, [r3, #8] +100003e2: 4a0c ldr r2, [pc, #48] @ (10000414 ) +100003e4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003e8: 4293 cmp r3, r2 +100003ea: d003 beq.n 100003f4 +100003ec: 4299 cmp r1, r3 +100003ee: d001 beq.n 100003f4 +100003f0: f000 fe8e bl 10001110 +100003f4: 4b06 ldr r3, [pc, #24] @ (10000410 ) +100003f6: 689b ldr r3, [r3, #8] +100003f8: f843 5024 str.w r5, [r3, r4, lsl #2] +100003fc: f3bf 8f5f dmb sy +10000400: 2300 movs r3, #0 +10000402: e8c6 3f8f stlb r3, [r6] +10000406: f387 8810 msr PRIMASK, r7 +1000040a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000040c: 20000439 .word 0x20000439 +10000410: e000ed00 .word 0xe000ed00 +10000414: 10000111 .word 0x10000111 + +10000418 : +10000418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000041c: b083 sub sp, #12 +1000041e: f3ef 8a10 mrs sl, PRIMASK +10000422: b672 cpsid i +10000424: 4e71 ldr r6, [pc, #452] @ (100005ec ) +10000426: e8d6 2fcf ldaexb r2, [r6] +1000042a: 2301 movs r3, #1 +1000042c: 2a00 cmp r2, #0 +1000042e: d1fa bne.n 10000426 +10000430: e8c6 3f42 strexb r2, r3, [r6] +10000434: 2a00 cmp r2, #0 +10000436: d1f6 bne.n 10000426 +10000438: f3bf 8f5f dmb sy +1000043c: 4b6c ldr r3, [pc, #432] @ (100005f0 ) +1000043e: f100 0810 add.w r8, r0, #16 +10000442: 689b ldr r3, [r3, #8] +10000444: 4a6b ldr r2, [pc, #428] @ (100005f4 ) +10000446: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000044a: 4295 cmp r5, r2 +1000044c: d045 beq.n 100004da +1000044e: 428d cmp r5, r1 +10000450: 460c mov r4, r1 +10000452: d050 beq.n 100004f6 +10000454: 4f68 ldr r7, [pc, #416] @ (100005f8 ) +10000456: 1beb subs r3, r5, r7 +10000458: 2b2f cmp r3, #47 @ 0x2f +1000045a: d83e bhi.n 100004da +1000045c: 2101 movs r1, #1 +1000045e: ea4f 1950 mov.w r9, r0, lsr #5 +10000462: ea4f 0989 mov.w r9, r9, lsl #2 +10000466: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000046a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000046e: f000 031f and.w r3, r0, #31 +10000472: fa01 f003 lsl.w r0, r1, r3 +10000476: f8d9 3000 ldr.w r3, [r9] +1000047a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000047e: ea00 0b03 and.w fp, r0, r3 +10000482: f3bf 8f5f dmb sy +10000486: f3ef 8105 mrs r1, IPSR +1000048a: b2c9 uxtb r1, r1 +1000048c: 2900 cmp r1, #0 +1000048e: d034 beq.n 100004fa +10000490: 4588 cmp r8, r1 +10000492: d005 beq.n 100004a0 +10000494: e9cd 1000 strd r1, r0, [sp] +10000498: f000 fe3a bl 10001110 +1000049c: e9dd 1000 ldrd r1, r0, [sp] +100004a0: f025 0e01 bic.w lr, r5, #1 +100004a4: f8de c008 ldr.w ip, [lr, #8] +100004a8: 4564 cmp r4, ip +100004aa: d105 bne.n 100004b8 +100004ac: e089 b.n 100005c2 +100004ae: f8d3 c008 ldr.w ip, [r3, #8] +100004b2: 4564 cmp r4, ip +100004b4: d031 beq.n 1000051a +100004b6: 469e mov lr, r3 +100004b8: f99e 2006 ldrsb.w r2, [lr, #6] +100004bc: eb02 0342 add.w r3, r2, r2, lsl #1 +100004c0: 2a00 cmp r2, #0 +100004c2: eb07 0383 add.w r3, r7, r3, lsl #2 +100004c6: daf2 bge.n 100004ae +100004c8: 4564 cmp r4, ip +100004ca: d061 beq.n 10000590 +100004cc: f1bb 0f00 cmp.w fp, #0 +100004d0: d020 beq.n 10000514 +100004d2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004d6: f8c9 0000 str.w r0, [r9] +100004da: 4b45 ldr r3, [pc, #276] @ (100005f0 ) +100004dc: 689b ldr r3, [r3, #8] +100004de: f843 5028 str.w r5, [r3, r8, lsl #2] +100004e2: f3bf 8f5f dmb sy +100004e6: 2300 movs r3, #0 +100004e8: e8c6 3f8f stlb r3, [r6] +100004ec: f38a 8810 msr PRIMASK, sl +100004f0: b003 add sp, #12 +100004f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100004f6: 4615 mov r5, r2 +100004f8: e7ef b.n 100004da +100004fa: f025 0e01 bic.w lr, r5, #1 +100004fe: f8de c008 ldr.w ip, [lr, #8] +10000502: 4564 cmp r4, ip +10000504: d1d8 bne.n 100004b8 +10000506: f99e 4006 ldrsb.w r4, [lr, #6] +1000050a: 4673 mov r3, lr +1000050c: 2c00 cmp r4, #0 +1000050e: da08 bge.n 10000522 +10000510: 4615 mov r5, r2 +10000512: e046 b.n 100005a2 +10000514: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000518: e7df b.n 100004da +1000051a: f993 4006 ldrsb.w r4, [r3, #6] +1000051e: 2c00 cmp r4, #0 +10000520: db37 blt.n 10000592 +10000522: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000526: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000052a: f89c 1007 ldrb.w r1, [ip, #7] +1000052e: f8dc 2008 ldr.w r2, [ip, #8] +10000532: 71d9 strb r1, [r3, #7] +10000534: 609a str r2, [r3, #8] +10000536: f99c 2006 ldrsb.w r2, [ip, #6] +1000053a: 0061 lsls r1, r4, #1 +1000053c: 2a00 cmp r2, #0 +1000053e: 719a strb r2, [r3, #6] +10000540: db3d blt.n 100005be +10000542: f8bc e004 ldrh.w lr, [ip, #4] +10000546: ea5f 5e4e movs.w lr, lr, lsl #21 +1000054a: d505 bpl.n 10000558 +1000054c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000550: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000554: f10e 0e1f add.w lr, lr, #31 +10000558: f06f 0c07 mvn.w ip, #7 +1000055c: 190a adds r2, r1, r4 +1000055e: ea4f 5e6e mov.w lr, lr, asr #21 +10000562: 0092 lsls r2, r2, #2 +10000564: eb02 024e add.w r2, r2, lr, lsl #1 +10000568: 3208 adds r2, #8 +1000056a: 443a add r2, r7 +1000056c: ebac 0c03 sub.w ip, ip, r3 +10000570: 4462 add r2, ip +10000572: f3c2 024a ubfx r2, r2, #1, #11 +10000576: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000057a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000057e: 809a strh r2, [r3, #4] +10000580: 4b1e ldr r3, [pc, #120] @ (100005fc ) +10000582: 4421 add r1, r4 +10000584: 781a ldrb r2, [r3, #0] +10000586: eb07 0181 add.w r1, r7, r1, lsl #2 +1000058a: 701c strb r4, [r3, #0] +1000058c: 718a strb r2, [r1, #6] +1000058e: e79d b.n 100004cc +10000590: 4673 mov r3, lr +10000592: b9d9 cbnz r1, 100005cc +10000594: 22ff movs r2, #255 @ 0xff +10000596: f88e 2006 strb.w r2, [lr, #6] +1000059a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000059e: f8ae 2004 strh.w r2, [lr, #4] +100005a2: 4c16 ldr r4, [pc, #88] @ (100005fc ) +100005a4: f64a 22aa movw r2, #43690 @ 0xaaaa +100005a8: f894 c000 ldrb.w ip, [r4] +100005ac: 4619 mov r1, r3 +100005ae: 1bc9 subs r1, r1, r7 +100005b0: 4149 adcs r1, r1 +100005b2: 434a muls r2, r1 +100005b4: 0d12 lsrs r2, r2, #20 +100005b6: f883 c006 strb.w ip, [r3, #6] +100005ba: 7022 strb r2, [r4, #0] +100005bc: e786 b.n 100004cc +100005be: 4a10 ldr r2, [pc, #64] @ (10000600 ) +100005c0: e7dd b.n 1000057e +100005c2: f99e 4006 ldrsb.w r4, [lr, #6] +100005c6: 4673 mov r3, lr +100005c8: 2c00 cmp r4, #0 +100005ca: daaa bge.n 10000522 +100005cc: 4a0d ldr r2, [pc, #52] @ (10000604 ) +100005ce: 4c0e ldr r4, [pc, #56] @ (10000608 ) +100005d0: 1ad2 subs r2, r2, r3 +100005d2: 3a08 subs r2, #8 +100005d4: f3c2 310a ubfx r1, r2, #12, #11 +100005d8: ea6f 5101 mvn.w r1, r1, lsl #20 +100005dc: ea6f 5111 mvn.w r1, r1, lsr #20 +100005e0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005e4: 80da strh r2, [r3, #6] +100005e6: 8099 strh r1, [r3, #4] +100005e8: e770 b.n 100004cc +100005ea: bf00 nop +100005ec: 20000439 .word 0x20000439 +100005f0: e000ed00 .word 0xe000ed00 +100005f4: 10000111 .word 0x10000111 +100005f8: 2000022c .word 0x2000022c +100005fc: 200004d4 .word 0x200004d4 +10000600: ffffbd01 .word 0xffffbd01 +10000604: 20000266 .word 0x20000266 +10000608: fffff800 .word 0xfffff800 + +1000060c : +1000060c: b5f0 push {r4, r5, r6, r7, lr} +1000060e: f3ef 8505 mrs r5, IPSR +10000612: b2ed uxtb r5, r5 +10000614: f3ef 8c10 mrs ip, PRIMASK +10000618: b672 cpsid i +1000061a: 4926 ldr r1, [pc, #152] @ (100006b4 ) +1000061c: e8d1 2fcf ldaexb r2, [r1] +10000620: 2301 movs r3, #1 +10000622: 2a00 cmp r2, #0 +10000624: d1fa bne.n 1000061c +10000626: e8c1 3f42 strexb r2, r3, [r1] +1000062a: 2a00 cmp r2, #0 +1000062c: d1f6 bne.n 1000061c +1000062e: f3bf 8f5f dmb sy +10000632: 4e21 ldr r6, [pc, #132] @ (100006b8 ) +10000634: f040 0e01 orr.w lr, r0, #1 +10000638: 68b4 ldr r4, [r6, #8] +1000063a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000063e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000642: 4a1e ldr r2, [pc, #120] @ (100006bc ) +10000644: 4604 mov r4, r0 +10000646: 1aa4 subs r4, r4, r2 +10000648: 4164 adcs r4, r4 +1000064a: 4363 muls r3, r4 +1000064c: 0d1b lsrs r3, r3, #20 +1000064e: 4577 cmp r7, lr +10000650: b25b sxtb r3, r3 +10000652: d01b beq.n 1000068c +10000654: f992 4006 ldrsb.w r4, [r2, #6] +10000658: 429c cmp r4, r3 +1000065a: d01c beq.n 10000696 +1000065c: f992 4012 ldrsb.w r4, [r2, #18] +10000660: 429c cmp r4, r3 +10000662: d023 beq.n 100006ac +10000664: f992 401e ldrsb.w r4, [r2, #30] +10000668: 429c cmp r4, r3 +1000066a: d021 beq.n 100006b0 +1000066c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000670: 429c cmp r4, r3 +10000672: bf08 it eq +10000674: 2403 moveq r4, #3 +10000676: d00f beq.n 10000698 +10000678: 4a11 ldr r2, [pc, #68] @ (100006c0 ) +1000067a: 2400 movs r4, #0 +1000067c: 7815 ldrb r5, [r2, #0] +1000067e: 7013 strb r3, [r2, #0] +10000680: 7185 strb r5, [r0, #6] +10000682: e8c1 4f8f stlb r4, [r1] +10000686: f38c 8810 msr PRIMASK, ip +1000068a: bdf0 pop {r4, r5, r6, r7, pc} +1000068c: 68b2 ldr r2, [r6, #8] +1000068e: 4c0d ldr r4, [pc, #52] @ (100006c4 ) +10000690: f842 4025 str.w r4, [r2, r5, lsl #2] +10000694: e7f0 b.n 10000678 +10000696: 2400 movs r4, #0 +10000698: eb04 0444 add.w r4, r4, r4, lsl #1 +1000069c: eb02 0284 add.w r2, r2, r4, lsl #2 +100006a0: 24ff movs r4, #255 @ 0xff +100006a2: 7194 strb r4, [r2, #6] +100006a4: f64b 5401 movw r4, #48385 @ 0xbd01 +100006a8: 8094 strh r4, [r2, #4] +100006aa: e7e5 b.n 10000678 +100006ac: 2401 movs r4, #1 +100006ae: e7f3 b.n 10000698 +100006b0: 2402 movs r4, #2 +100006b2: e7f1 b.n 10000698 +100006b4: 20000439 .word 0x20000439 +100006b8: e000ed00 .word 0xe000ed00 +100006bc: 2000022c .word 0x2000022c +100006c0: 200004d4 .word 0x200004d4 +100006c4: 10000111 .word 0x10000111 + +100006c8 : +100006c8: 4b01 ldr r3, [pc, #4] @ (100006d0 ) +100006ca: 440b add r3, r1 +100006cc: 6003 str r3, [r0, #0] +100006ce: 4770 bx lr +100006d0: 20000430 .word 0x20000430 + +100006d4 : +100006d4: b570 push {r4, r5, r6, lr} +100006d6: 4c10 ldr r4, [pc, #64] @ (10000718 ) +100006d8: 4d10 ldr r5, [pc, #64] @ (1000071c ) +100006da: 42ac cmp r4, r5 +100006dc: d20e bcs.n 100006fc +100006de: 26ff movs r6, #255 @ 0xff +100006e0: 6823 ldr r3, [r4, #0] +100006e2: b163 cbz r3, 100006fe +100006e4: f7ff fe12 bl 1000030c +100006e8: 4601 mov r1, r0 +100006ea: 4620 mov r0, r4 +100006ec: f7ff ffec bl 100006c8 +100006f0: 80a6 strh r6, [r4, #4] +100006f2: f3bf 8f5f dmb sy +100006f6: 3408 adds r4, #8 +100006f8: 42ac cmp r4, r5 +100006fa: d3f1 bcc.n 100006e0 +100006fc: bd70 pop {r4, r5, r6, pc} +100006fe: f7ff fe05 bl 1000030c +10000702: 4601 mov r1, r0 +10000704: 4620 mov r0, r4 +10000706: f7ff ffdf bl 100006c8 +1000070a: 7126 strb r6, [r4, #4] +1000070c: f3bf 8f5f dmb sy +10000710: 3408 adds r4, #8 +10000712: 42ac cmp r4, r5 +10000714: d3e4 bcc.n 100006e0 +10000716: bd70 pop {r4, r5, r6, pc} +10000718: 200002a4 .word 0x200002a4 +1000071c: 200002ac .word 0x200002ac + +10000720 : +10000720: 4b0d ldr r3, [pc, #52] @ (10000758 ) +10000722: 681a ldr r2, [r3, #0] +10000724: f3ef 8110 mrs r1, PRIMASK +10000728: b672 cpsid i +1000072a: e8d2 cfcf ldaexb ip, [r2] +1000072e: 2001 movs r0, #1 +10000730: f1bc 0f00 cmp.w ip, #0 +10000734: d1f9 bne.n 1000072a +10000736: e8c2 0f4c strexb ip, r0, [r2] +1000073a: f1bc 0f00 cmp.w ip, #0 +1000073e: d1f4 bne.n 1000072a +10000740: f3bf 8f5f dmb sy +10000744: 2200 movs r2, #0 +10000746: 681b ldr r3, [r3, #0] +10000748: e8c3 2f8f stlb r2, [r3] +1000074c: f381 8810 msr PRIMASK, r1 +10000750: bf40 sev +10000752: 2000 movs r0, #0 +10000754: 2100 movs r1, #0 +10000756: 4770 bx lr +10000758: 200004c8 .word 0x200004c8 +1000075c: 00000000 .word 0x00000000 + +10000760 : +10000760: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000764: ed2d 8b02 vpush {d8} +10000768: b085 sub sp, #20 +1000076a: f3ef 8305 mrs r3, IPSR +1000076e: b2db uxtb r3, r3 +10000770: 3b10 subs r3, #16 +10000772: 089a lsrs r2, r3, #2 +10000774: bf18 it ne +10000776: 2201 movne r2, #1 +10000778: f04f 0101 mov.w r1, #1 +1000077c: f003 0b03 and.w fp, r3, #3 +10000780: bf18 it ne +10000782: 4daf ldrne r5, [pc, #700] @ (10000a40 ) +10000784: 4baf ldr r3, [pc, #700] @ (10000a44 ) +10000786: bf08 it eq +10000788: 4daf ldreq r5, [pc, #700] @ (10000a48 ) +1000078a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000078e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000792: fa01 f20b lsl.w r2, r1, fp +10000796: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000079a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a38 +1000079e: 9201 str r2, [sp, #4] +100007a0: 605a str r2, [r3, #4] +100007a2: e02f b.n 10000804 +100007a4: 88b3 ldrh r3, [r6, #4] +100007a6: 041c lsls r4, r3, #16 +100007a8: f140 8093 bpl.w 100008d2 +100007ac: 79b3 ldrb r3, [r6, #6] +100007ae: 2b00 cmp r3, #0 +100007b0: f040 80dd bne.w 1000096e +100007b4: f9b6 2008 ldrsh.w r2, [r6, #8] +100007b8: 2a00 cmp r2, #0 +100007ba: f2c0 811e blt.w 100009fa +100007be: 6973 ldr r3, [r6, #20] +100007c0: eb02 0242 add.w r2, r2, r2, lsl #1 +100007c4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007c8: e9d3 4702 ldrd r4, r7, [r3, #8] +100007cc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007d0: bf08 it eq +100007d2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007d6: d00e beq.n 100007f6 +100007d8: eb05 018b add.w r1, r5, fp, lsl #2 +100007dc: 6aab ldr r3, [r5, #40] @ 0x28 +100007de: 690a ldr r2, [r1, #16] +100007e0: 1ad2 subs r2, r2, r3 +100007e2: 1ae3 subs r3, r4, r3 +100007e4: 4293 cmp r3, r2 +100007e6: d305 bcc.n 100007f4 +100007e8: 2301 movs r3, #1 +100007ea: 6a2a ldr r2, [r5, #32] +100007ec: fa03 f30b lsl.w r3, r3, fp +100007f0: 4213 tst r3, r2 +100007f2: d100 bne.n 100007f6 +100007f4: 610c str r4, [r1, #16] +100007f6: 4628 mov r0, r5 +100007f8: f000 faca bl 10000d90 +100007fc: 42a0 cmp r0, r4 +100007fe: 41b9 sbcs r1, r7 +10000800: f2c0 80fb blt.w 100009fa +10000804: f9b6 3008 ldrsh.w r3, [r6, #8] +10000808: 9a01 ldr r2, [sp, #4] +1000080a: 2b00 cmp r3, #0 +1000080c: 9300 str r3, [sp, #0] +1000080e: 63ea str r2, [r5, #60] @ 0x3c +10000810: dbc8 blt.n 100007a4 +10000812: f8d6 8014 ldr.w r8, [r6, #20] +10000816: eb03 0943 add.w r9, r3, r3, lsl #1 +1000081a: 4628 mov r0, r5 +1000081c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000820: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000824: f000 fab4 bl 10000d90 +10000828: 42a0 cmp r0, r4 +1000082a: eb71 010a sbcs.w r1, r1, sl +1000082e: dbb9 blt.n 100007a4 +10000830: f1ba 0f00 cmp.w sl, #0 +10000834: f2c0 80c3 blt.w 100009be +10000838: e9d7 3104 ldrd r3, r1, [r7, #16] +1000083c: 4a83 ldr r2, [pc, #524] @ (10000a4c ) +1000083e: 4293 cmp r3, r2 +10000840: f000 80ed beq.w 10000a1e +10000844: 887a ldrh r2, [r7, #2] +10000846: f9b6 0008 ldrsh.w r0, [r6, #8] +1000084a: b292 uxth r2, r2 +1000084c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000850: 4798 blx r3 +10000852: 4602 mov r2, r0 +10000854: 460b mov r3, r1 +10000856: ea52 0103 orrs.w r1, r2, r3 +1000085a: f000 80b0 beq.w 100009be +1000085e: 2b00 cmp r3, #0 +10000860: f280 80d1 bge.w 10000a06 +10000864: ebb4 0e02 subs.w lr, r4, r2 +10000868: eb6a 0a03 sbc.w sl, sl, r3 +1000086c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000870: e9c7 ea02 strd lr, sl, [r7, #8] +10000874: 2b00 cmp r3, #0 +10000876: db95 blt.n 100007a4 +10000878: 6971 ldr r1, [r6, #20] +1000087a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000087e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000882: e9d2 7002 ldrd r7, r0, [r2, #8] +10000886: 45be cmp lr, r7 +10000888: eb7a 0c00 sbcs.w ip, sl, r0 +1000088c: ea4f 0243 mov.w r2, r3, lsl #1 +10000890: db88 blt.n 100007a4 +10000892: 46b4 mov ip, r6 +10000894: f82c 3f08 strh.w r3, [ip, #8]! +10000898: e006 b.n 100008a8 +1000089a: eb03 0043 add.w r0, r3, r3, lsl #1 +1000089e: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008a2: 005a lsls r2, r3, #1 +100008a4: e9d0 7002 ldrd r7, r0, [r0, #8] +100008a8: 45be cmp lr, r7 +100008aa: 441a add r2, r3 +100008ac: eb7a 0000 sbcs.w r0, sl, r0 +100008b0: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008b4: db04 blt.n 100008c0 +100008b6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008ba: 46a4 mov ip, r4 +100008bc: 2b00 cmp r3, #0 +100008be: daec bge.n 1000089a +100008c0: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008c4: 9b00 ldr r3, [sp, #0] +100008c6: f8ac 3000 strh.w r3, [ip] +100008ca: 88b3 ldrh r3, [r6, #4] +100008cc: 041c lsls r4, r3, #16 +100008ce: f53f af6d bmi.w 100007ac +100008d2: 6933 ldr r3, [r6, #16] +100008d4: f3ef 8210 mrs r2, PRIMASK +100008d8: b672 cpsid i +100008da: e8d3 0fcf ldaexb r0, [r3] +100008de: 2101 movs r1, #1 +100008e0: 2800 cmp r0, #0 +100008e2: d1fa bne.n 100008da +100008e4: e8c3 1f40 strexb r0, r1, [r3] +100008e8: 2800 cmp r0, #0 +100008ea: d1f6 bne.n 100008da +100008ec: f3bf 8f5f dmb sy +100008f0: f64f 74ff movw r4, #65535 @ 0xffff +100008f4: 88b0 ldrh r0, [r6, #4] +100008f6: 2300 movs r3, #0 +100008f8: 6931 ldr r1, [r6, #16] +100008fa: b200 sxth r0, r0 +100008fc: 80b4 strh r4, [r6, #4] +100008fe: e8c1 3f8f stlb r3, [r1] +10000902: f382 8810 msr PRIMASK, r2 +10000906: 4298 cmp r0, r3 +10000908: f6ff af50 blt.w 100007ac +1000090c: 4607 mov r7, r0 +1000090e: 46a9 mov r9, r5 +10000910: 6974 ldr r4, [r6, #20] +10000912: f106 0808 add.w r8, r6, #8 +10000916: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000091a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000091e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000922: f9b6 3008 ldrsh.w r3, [r6, #8] +10000926: 46c4 mov ip, r8 +10000928: 2b00 cmp r3, #0 +1000092a: db13 blt.n 10000954 +1000092c: 46b2 mov sl, r6 +1000092e: 9700 str r7, [sp, #0] +10000930: e004 b.n 1000093c +10000932: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000936: 4694 mov ip, r2 +10000938: 2b00 cmp r3, #0 +1000093a: db09 blt.n 10000950 +1000093c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000940: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000944: e9d2 7102 ldrd r7, r1, [r2, #8] +10000948: 42bd cmp r5, r7 +1000094a: eb70 0101 sbcs.w r1, r0, r1 +1000094e: daf0 bge.n 10000932 +10000950: 4656 mov r6, sl +10000952: 9f00 ldr r7, [sp, #0] +10000954: f8ac 7000 strh.w r7, [ip] +10000958: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000095c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000960: 2f00 cmp r7, #0 +10000962: dad8 bge.n 10000916 +10000964: 79b3 ldrb r3, [r6, #6] +10000966: 464d mov r5, r9 +10000968: 2b00 cmp r3, #0 +1000096a: f43f af23 beq.w 100007b4 +1000096e: 2300 movs r3, #0 +10000970: 71b3 strb r3, [r6, #6] +10000972: f9b6 3008 ldrsh.w r3, [r6, #8] +10000976: f106 0808 add.w r8, r6, #8 +1000097a: 1c58 adds r0, r3, #1 +1000097c: d03d beq.n 100009fa +1000097e: 461a mov r2, r3 +10000980: 6977 ldr r7, [r6, #20] +10000982: e003 b.n 1000098c +10000984: 4680 mov r8, r0 +10000986: 1c59 adds r1, r3, #1 +10000988: f43f af16 beq.w 100007b8 +1000098c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000990: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000994: f8b0 c002 ldrh.w ip, [r0, #2] +10000998: 461c mov r4, r3 +1000099a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +1000099e: 469e mov lr, r3 +100009a0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009a4: d0ee beq.n 10000984 +100009a6: 4294 cmp r4, r2 +100009a8: ed80 8b02 vstr d8, [r0, #8] +100009ac: d005 beq.n 100009ba +100009ae: f8a8 3000 strh.w r3, [r8] +100009b2: 8932 ldrh r2, [r6, #8] +100009b4: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009b8: 8134 strh r4, [r6, #8] +100009ba: 4672 mov r2, lr +100009bc: e7e3 b.n 10000986 +100009be: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009c2: 8133 strh r3, [r6, #8] +100009c4: 6933 ldr r3, [r6, #16] +100009c6: f3ef 8210 mrs r2, PRIMASK +100009ca: b672 cpsid i +100009cc: e8d3 0fcf ldaexb r0, [r3] +100009d0: 2101 movs r1, #1 +100009d2: 2800 cmp r0, #0 +100009d4: d1fa bne.n 100009cc +100009d6: e8c3 1f40 strexb r0, r1, [r3] +100009da: 2800 cmp r0, #0 +100009dc: d1f6 bne.n 100009cc +100009de: f3bf 8f5f dmb sy +100009e2: 8873 ldrh r3, [r6, #2] +100009e4: 6931 ldr r1, [r6, #16] +100009e6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009ea: 9b00 ldr r3, [sp, #0] +100009ec: 8073 strh r3, [r6, #2] +100009ee: 2300 movs r3, #0 +100009f0: e8c1 3f8f stlb r3, [r1] +100009f4: f382 8810 msr PRIMASK, r2 +100009f8: e6d4 b.n 100007a4 +100009fa: bf40 sev +100009fc: b005 add sp, #20 +100009fe: ecbd 8b02 vpop {d8} +10000a02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a06: 4628 mov r0, r5 +10000a08: e9cd 2302 strd r2, r3, [sp, #8] +10000a0c: f000 f9c0 bl 10000d90 +10000a10: 9a02 ldr r2, [sp, #8] +10000a12: 9b03 ldr r3, [sp, #12] +10000a14: eb10 0e02 adds.w lr, r0, r2 +10000a18: eb43 0a01 adc.w sl, r3, r1 +10000a1c: e726 b.n 1000086c +10000a1e: 4608 mov r0, r1 +10000a20: 690b ldr r3, [r1, #16] +10000a22: 9102 str r1, [sp, #8] +10000a24: 4798 blx r3 +10000a26: 2800 cmp r0, #0 +10000a28: d0c9 beq.n 100009be +10000a2a: 9902 ldr r1, [sp, #8] +10000a2c: e9d1 2300 ldrd r2, r3, [r1] +10000a30: e711 b.n 10000856 +10000a32: bf00 nop +10000a34: f3af 8000 nop.w +10000a38: ffffffff .word 0xffffffff +10000a3c: ffffffff .word 0xffffffff +10000a40: 400b8000 .word 0x400b8000 +10000a44: 200004a8 .word 0x200004a8 +10000a48: 400b0000 .word 0x400b0000 +10000a4c: 10000761 .word 0x10000761 + +10000a50 : +10000a50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a54: 4c36 ldr r4, [pc, #216] @ (10000b30 ) +10000a56: 6925 ldr r5, [r4, #16] +10000a58: b12d cbz r5, 10000a66 +10000a5a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a5e: 210a movs r1, #10 +10000a60: 4834 ldr r0, [pc, #208] @ (10000b34 ) +10000a62: f7ff be31 b.w 100006c8 +10000a66: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b4c +10000a6a: 2103 movs r1, #3 +10000a6c: 4640 mov r0, r8 +10000a6e: f000 f97d bl 10000d6c +10000a72: 2603 movs r6, #3 +10000a74: f8c4 800c str.w r8, [r4, #12] +10000a78: f7ff fc48 bl 1000030c +10000a7c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a80: 4b2d ldr r3, [pc, #180] @ (10000b38 ) +10000a82: 7026 strb r6, [r4, #0] +10000a84: 4403 add r3, r0 +10000a86: 6123 str r3, [r4, #16] +10000a88: f8dc 3000 ldr.w r3, [ip] +10000a8c: 210f movs r1, #15 +10000a8e: 7063 strb r3, [r4, #1] +10000a90: 6963 ldr r3, [r4, #20] +10000a92: 8061 strh r1, [r4, #2] +10000a94: 831d strh r5, [r3, #24] +10000a96: f04f 0504 mov.w r5, #4 +10000a9a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000a9e: f04f 0505 mov.w r5, #5 +10000aa2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000aa6: f04f 0506 mov.w r5, #6 +10000aaa: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000aae: f04f 0507 mov.w r5, #7 +10000ab2: 210e movs r1, #14 +10000ab4: f64f 72ff movw r2, #65535 @ 0xffff +10000ab8: 2708 movs r7, #8 +10000aba: f04f 0e0a mov.w lr, #10 +10000abe: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000ac2: f04f 0901 mov.w r9, #1 +10000ac6: f04f 0c0c mov.w ip, #12 +10000aca: f04f 0b02 mov.w fp, #2 +10000ace: f04f 0a09 mov.w sl, #9 +10000ad2: 200d movs r0, #13 +10000ad4: f04f 050b mov.w r5, #11 +10000ad8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000adc: 4917 ldr r1, [pc, #92] @ (10000b3c ) +10000ade: 80a2 strh r2, [r4, #4] +10000ae0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000ae4: 60a1 str r1, [r4, #8] +10000ae6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000aea: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000aee: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000af2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000af6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000afa: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000afe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b02: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b06: 801a strh r2, [r3, #0] +10000b08: 4b0d ldr r3, [pc, #52] @ (10000b40 ) +10000b0a: 4630 mov r0, r6 +10000b0c: f8c8 7020 str.w r7, [r8, #32] +10000b10: 490c ldr r1, [pc, #48] @ (10000b44 ) +10000b12: 60dc str r4, [r3, #12] +10000b14: f7ff fc50 bl 100003b8 +10000b18: 4649 mov r1, r9 +10000b1a: 4630 mov r0, r6 +10000b1c: f7ff fc36 bl 1000038c +10000b20: 4b09 ldr r3, [pc, #36] @ (10000b48 ) +10000b22: 210a movs r1, #10 +10000b24: 641f str r7, [r3, #64] @ 0x40 +10000b26: 4803 ldr r0, [pc, #12] @ (10000b34 ) +10000b28: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b2c: f7ff bdcc b.w 100006c8 +10000b30: 20000274 .word 0x20000274 +10000b34: 200004c8 .word 0x200004c8 +10000b38: 20000430 .word 0x20000430 +10000b3c: 0010ffff .word 0x0010ffff +10000b40: 200004a8 .word 0x200004a8 +10000b44: 10000761 .word 0x10000761 +10000b48: 400b2000 .word 0x400b2000 +10000b4c: 400b0000 .word 0x400b0000 + +10000b50 : +10000b50: 4601 mov r1, r0 +10000b52: b5f0 push {r4, r5, r6, r7, lr} +10000b54: 6900 ldr r0, [r0, #16] +10000b56: f3ef 8710 mrs r7, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d0 5fcf ldaexb r5, [r0] +10000b60: 2401 movs r4, #1 +10000b62: 2d00 cmp r5, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c0 4f45 strexb r5, r4, [r0] +10000b6a: 2d00 cmp r5, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b76: 694c ldr r4, [r1, #20] +10000b78: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b7c: f1be 0f00 cmp.w lr, #0 +10000b80: ea4f 05cc mov.w r5, ip, lsl #3 +10000b84: 6908 ldr r0, [r1, #16] +10000b86: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b8a: db3c blt.n 10000c06 +10000b8c: 5b66 ldrh r6, [r4, r5] +10000b8e: 804e strh r6, [r1, #2] +10000b90: 2600 movs r6, #0 +10000b92: e8c0 6f8f stlb r6, [r0] +10000b96: f387 8810 msr PRIMASK, r7 +10000b9a: f8bc 0002 ldrh.w r0, [ip, #2] +10000b9e: e9cc 2302 strd r2, r3, [ip, #8] +10000ba2: 3001 adds r0, #1 +10000ba4: f3c0 000e ubfx r0, r0, #0, #15 +10000ba8: 2801 cmp r0, #1 +10000baa: bf38 it cc +10000bac: 2001 movcc r0, #1 +10000bae: 9b05 ldr r3, [sp, #20] +10000bb0: f8ac 0002 strh.w r0, [ip, #2] +10000bb4: f8cc 3010 str.w r3, [ip, #16] +10000bb8: 9b06 ldr r3, [sp, #24] +10000bba: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bbe: f8cc 3014 str.w r3, [ip, #20] +10000bc2: 690b ldr r3, [r1, #16] +10000bc4: f3ef 8210 mrs r2, PRIMASK +10000bc8: b672 cpsid i +10000bca: e8d3 cfcf ldaexb ip, [r3] +10000bce: 2701 movs r7, #1 +10000bd0: f1bc 0f00 cmp.w ip, #0 +10000bd4: d1f9 bne.n 10000bca +10000bd6: e8c3 7f4c strexb ip, r7, [r3] +10000bda: f1bc 0f00 cmp.w ip, #0 +10000bde: d1f4 bne.n 10000bca +10000be0: f3bf 8f5f dmb sy +10000be4: 888b ldrh r3, [r1, #4] +10000be6: 5363 strh r3, [r4, r5] +10000be8: f8a1 e004 strh.w lr, [r1, #4] +10000bec: 690b ldr r3, [r1, #16] +10000bee: e8c3 6f8f stlb r6, [r3] +10000bf2: f382 8810 msr PRIMASK, r2 +10000bf6: 2201 movs r2, #1 +10000bf8: 68cb ldr r3, [r1, #12] +10000bfa: 7809 ldrb r1, [r1, #0] +10000bfc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c00: 408a lsls r2, r1 +10000c02: 605a str r2, [r3, #4] +10000c04: bdf0 pop {r4, r5, r6, r7, pc} +10000c06: 2300 movs r3, #0 +10000c08: e8c0 3f8f stlb r3, [r0] +10000c0c: f387 8810 msr PRIMASK, r7 +10000c10: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c14: bdf0 pop {r4, r5, r6, r7, pc} +10000c16: bf00 nop + +10000c18 : +10000c18: 4603 mov r3, r0 +10000c1a: 8940 ldrh r0, [r0, #10] +10000c1c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c20: dd37 ble.n 10000c92 +10000c22: 6958 ldr r0, [r3, #20] +10000c24: 140a asrs r2, r1, #16 +10000c26: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c2a: b510 push {r4, lr} +10000c2c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c30: 691c ldr r4, [r3, #16] +10000c32: f3ef 8c10 mrs ip, PRIMASK +10000c36: b672 cpsid i +10000c38: e8d4 efcf ldaexb lr, [r4] +10000c3c: 2201 movs r2, #1 +10000c3e: f1be 0f00 cmp.w lr, #0 +10000c42: d1f9 bne.n 10000c38 +10000c44: e8c4 2f4e strexb lr, r2, [r4] +10000c48: f1be 0f00 cmp.w lr, #0 +10000c4c: d1f4 bne.n 10000c38 +10000c4e: f3bf 8f5f dmb sy +10000c52: 8842 ldrh r2, [r0, #2] +10000c54: b289 uxth r1, r1 +10000c56: b292 uxth r2, r2 +10000c58: 428a cmp r2, r1 +10000c5a: d007 beq.n 10000c6c +10000c5c: 2200 movs r2, #0 +10000c5e: 691b ldr r3, [r3, #16] +10000c60: e8c3 2f8f stlb r2, [r3] +10000c64: f38c 8810 msr PRIMASK, ip +10000c68: 2000 movs r0, #0 +10000c6a: bd10 pop {r4, pc} +10000c6c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c70: 8042 strh r2, [r0, #2] +10000c72: 2101 movs r1, #1 +10000c74: 2200 movs r2, #0 +10000c76: 6918 ldr r0, [r3, #16] +10000c78: 7199 strb r1, [r3, #6] +10000c7a: e8c0 2f8f stlb r2, [r0] +10000c7e: f38c 8810 msr PRIMASK, ip +10000c82: 781c ldrb r4, [r3, #0] +10000c84: 68da ldr r2, [r3, #12] +10000c86: 4608 mov r0, r1 +10000c88: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c8c: 40a1 lsls r1, r4 +10000c8e: 6059 str r1, [r3, #4] +10000c90: bd10 pop {r4, pc} +10000c92: 2000 movs r0, #0 +10000c94: 4770 bx lr +10000c96: bf00 nop + +10000c98 : +10000c98: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000c9c: 4606 mov r6, r0 +10000c9e: 460d mov r5, r1 +10000ca0: b083 sub sp, #12 +10000ca2: f3ef 8405 mrs r4, IPSR +10000ca6: b2e4 uxtb r4, r4 +10000ca8: b13c cbz r4, 10000cba +10000caa: 4b2d ldr r3, [pc, #180] @ (10000d60 ) +10000cac: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cae: 42aa cmp r2, r5 +10000cb0: d21c bcs.n 10000cec +10000cb2: 2000 movs r0, #0 +10000cb4: b003 add sp, #12 +10000cb6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cba: 4f2a ldr r7, [pc, #168] @ (10000d64 ) +10000cbc: f8d7 900c ldr.w r9, [r7, #12] +10000cc0: f897 8000 ldrb.w r8, [r7] +10000cc4: 4648 mov r0, r9 +10000cc6: f000 f863 bl 10000d90 +10000cca: f108 0804 add.w r8, r8, #4 +10000cce: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000cd2: 1a1b subs r3, r3, r0 +10000cd4: 1a30 subs r0, r6, r0 +10000cd6: eb65 0101 sbc.w r1, r5, r1 +10000cda: 4298 cmp r0, r3 +10000cdc: f171 0100 sbcs.w r1, r1, #0 +10000ce0: db10 blt.n 10000d04 +10000ce2: bf20 wfe +10000ce4: 4b1e ldr r3, [pc, #120] @ (10000d60 ) +10000ce6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ce8: 42aa cmp r2, r5 +10000cea: d3e2 bcc.n 10000cb2 +10000cec: bf14 ite ne +10000cee: 2401 movne r4, #1 +10000cf0: 2400 moveq r4, #0 +10000cf2: 6a9b ldr r3, [r3, #40] @ 0x28 +10000cf4: 42b3 cmp r3, r6 +10000cf6: bf34 ite cc +10000cf8: 4620 movcc r0, r4 +10000cfa: f044 0001 orrcs.w r0, r4, #1 +10000cfe: b003 add sp, #12 +10000d00: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d04: f000 f84c bl 10000da0 +10000d08: 4286 cmp r6, r0 +10000d0a: eb65 0101 sbc.w r1, r5, r1 +10000d0e: 2900 cmp r1, #0 +10000d10: db14 blt.n 10000d3c +10000d12: 4b15 ldr r3, [pc, #84] @ (10000d68 ) +10000d14: 4638 mov r0, r7 +10000d16: e9cd 3400 strd r3, r4, [sp] +10000d1a: 4632 mov r2, r6 +10000d1c: 462b mov r3, r5 +10000d1e: f7ff ff17 bl 10000b50 +10000d22: 1e01 subs r1, r0, #0 +10000d24: dd0a ble.n 10000d3c +10000d26: 4b0e ldr r3, [pc, #56] @ (10000d60 ) +10000d28: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d2a: 42aa cmp r2, r5 +10000d2c: d316 bcc.n 10000d5c +10000d2e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d30: 42b3 cmp r3, r6 +10000d32: d311 bcc.n 10000d58 +10000d34: 480b ldr r0, [pc, #44] @ (10000d64 ) +10000d36: f7ff ff6f bl 10000c18 +10000d3a: e7b6 b.n 10000caa +10000d3c: 4b08 ldr r3, [pc, #32] @ (10000d60 ) +10000d3e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d40: 42ac cmp r4, r5 +10000d42: d3b6 bcc.n 10000cb2 +10000d44: 1b64 subs r4, r4, r5 +10000d46: bf18 it ne +10000d48: 2401 movne r4, #1 +10000d4a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d4c: 42b3 cmp r3, r6 +10000d4e: bf34 ite cc +10000d50: 4620 movcc r0, r4 +10000d52: f044 0001 orrcs.w r0, r4, #1 +10000d56: e7ad b.n 10000cb4 +10000d58: 42aa cmp r2, r5 +10000d5a: d1eb bne.n 10000d34 +10000d5c: bf20 wfe +10000d5e: e7e9 b.n 10000d34 +10000d60: 400b0000 .word 0x400b0000 +10000d64: 20000274 .word 0x20000274 +10000d68: 10000721 .word 0x10000721 + +10000d6c : +10000d6c: b410 push {r4} +10000d6e: 4b05 ldr r3, [pc, #20] @ (10000d84 ) +10000d70: 4c05 ldr r4, [pc, #20] @ (10000d88 ) +10000d72: 4a06 ldr r2, [pc, #24] @ (10000d8c ) +10000d74: 42a0 cmp r0, r4 +10000d76: bf14 ite ne +10000d78: 4618 movne r0, r3 +10000d7a: 1c58 addeq r0, r3, #1 +10000d7c: f85d 4b04 ldr.w r4, [sp], #4 +10000d80: f7ff ba98 b.w 100002b4 +10000d84: 20000458 .word 0x20000458 +10000d88: 400b8000 .word 0x400b8000 +10000d8c: 100019f0 .word 0x100019f0 + +10000d90 : +10000d90: 4603 mov r3, r0 +10000d92: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d94: 460a mov r2, r1 +10000d96: 6a98 ldr r0, [r3, #40] @ 0x28 +10000d98: 6a59 ldr r1, [r3, #36] @ 0x24 +10000d9a: 428a cmp r2, r1 +10000d9c: d1fa bne.n 10000d94 +10000d9e: 4770 bx lr + +10000da0 : +10000da0: 4b03 ldr r3, [pc, #12] @ (10000db0 ) +10000da2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 4291 cmp r1, r2 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr +10000db0: 400b0000 .word 0x400b0000 + +10000db4 : +10000db4: b430 push {r4, r5} +10000db6: 4a15 ldr r2, [pc, #84] @ (10000e0c ) +10000db8: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dba: 469c mov ip, r3 +10000dbc: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dbe: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc0: 4563 cmp r3, ip +10000dc2: d1fa bne.n 10000dba +10000dc4: 1902 adds r2, r0, r4 +10000dc6: 4159 adcs r1, r3 +10000dc8: f04f 0500 mov.w r5, #0 +10000dcc: bf28 it cs +10000dce: 2501 movcs r5, #1 +10000dd0: 4b0e ldr r3, [pc, #56] @ (10000e0c ) +10000dd2: 6a5b ldr r3, [r3, #36] @ 0x24 +10000dd4: b1b5 cbz r5, 10000e04 +10000dd6: 1c5a adds r2, r3, #1 +10000dd8: bf08 it eq +10000dda: 461a moveq r2, r3 +10000ddc: d008 beq.n 10000df0 +10000dde: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000de2: 460a mov r2, r1 +10000de4: 4809 ldr r0, [pc, #36] @ (10000e0c ) +10000de6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000de8: 428b cmp r3, r1 +10000dea: d3fc bcc.n 10000de6 +10000dec: 428b cmp r3, r1 +10000dee: d107 bne.n 10000e00 +10000df0: 4906 ldr r1, [pc, #24] @ (10000e0c ) +10000df2: e002 b.n 10000dfa +10000df4: 6a48 ldr r0, [r1, #36] @ 0x24 +10000df6: 4298 cmp r0, r3 +10000df8: d102 bne.n 10000e00 +10000dfa: 6a88 ldr r0, [r1, #40] @ 0x28 +10000dfc: 4290 cmp r0, r2 +10000dfe: d3f9 bcc.n 10000df4 +10000e00: bc30 pop {r4, r5} +10000e02: 4770 bx lr +10000e04: 4299 cmp r1, r3 +10000e06: d8ed bhi.n 10000de4 +10000e08: e7f0 b.n 10000dec +10000e0a: bf00 nop +10000e0c: 400b0000 .word 0x400b0000 + +10000e10 : +10000e10: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e12: 4605 mov r5, r0 +10000e14: 2006 movs r0, #6 +10000e16: 460e mov r6, r1 +10000e18: f000 f8e4 bl 10000fe4 +10000e1c: 2800 cmp r0, #0 +10000e1e: d042 beq.n 10000ea6 +10000e20: 4a35 ldr r2, [pc, #212] @ (10000ef8 ) +10000e22: 4836 ldr r0, [pc, #216] @ (10000efc ) +10000e24: 4295 cmp r5, r2 +10000e26: bf14 ite ne +10000e28: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e2c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e30: 4b33 ldr r3, [pc, #204] @ (10000f00 ) +10000e32: 4934 ldr r1, [pc, #208] @ (10000f04 ) +10000e34: 6002 str r2, [r0, #0] +10000e36: 601a str r2, [r3, #0] +10000e38: 688c ldr r4, [r1, #8] +10000e3a: ea32 0404 bics.w r4, r2, r4 +10000e3e: d1fb bne.n 10000e38 +10000e40: 4b2d ldr r3, [pc, #180] @ (10000ef8 ) +10000e42: f44f 7180 mov.w r1, #256 @ 0x100 +10000e46: 1aeb subs r3, r5, r3 +10000e48: fab3 f383 clz r3, r3 +10000e4c: 4a2e ldr r2, [pc, #184] @ (10000f08 ) +10000e4e: 095b lsrs r3, r3, #5 +10000e50: 2006 movs r0, #6 +10000e52: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e56: f000 f8c5 bl 10000fe4 +10000e5a: 00c3 lsls r3, r0, #3 +10000e5c: fbb3 f3f6 udiv r3, r3, r6 +10000e60: 3301 adds r3, #1 +10000e62: 09da lsrs r2, r3, #7 +10000e64: d120 bne.n 10000ea8 +10000e66: 2640 movs r6, #64 @ 0x40 +10000e68: 2101 movs r1, #1 +10000e6a: 6269 str r1, [r5, #36] @ 0x24 +10000e6c: 62aa str r2, [r5, #40] @ 0x28 +10000e6e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e70: 07fb lsls r3, r7, #31 +10000e72: d422 bmi.n 10000eba +10000e74: 462b mov r3, r5 +10000e76: 2200 movs r2, #0 +10000e78: f853 1f2c ldr.w r1, [r3, #44]! +10000e7c: 2006 movs r0, #6 +10000e7e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e82: 6022 str r2, [r4, #0] +10000e84: 632f str r7, [r5, #48] @ 0x30 +10000e86: f000 f8ad bl 10000fe4 +10000e8a: f240 3101 movw r1, #769 @ 0x301 +10000e8e: 2203 movs r2, #3 +10000e90: 0080 lsls r0, r0, #2 +10000e92: fbb0 f0f6 udiv r0, r0, r6 +10000e96: 6aeb ldr r3, [r5, #44] @ 0x2c +10000e98: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000e9c: f003 037e and.w r3, r3, #126 @ 0x7e +10000ea0: 6023 str r3, [r4, #0] +10000ea2: 6329 str r1, [r5, #48] @ 0x30 +10000ea4: 64aa str r2, [r5, #72] @ 0x48 +10000ea6: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000ea8: f64f 71fe movw r1, #65534 @ 0xfffe +10000eac: 428a cmp r2, r1 +10000eae: d91b bls.n 10000ee8 +10000eb0: 4622 mov r2, r4 +10000eb2: f64f 71ff movw r1, #65535 @ 0xffff +10000eb6: 4e15 ldr r6, [pc, #84] @ (10000f0c ) +10000eb8: e7d7 b.n 10000e6a +10000eba: f240 3201 movw r2, #769 @ 0x301 +10000ebe: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000ec2: 631a str r2, [r3, #48] @ 0x30 +10000ec4: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ec6: 6aac ldr r4, [r5, #40] @ 0x28 +10000ec8: 2006 movs r0, #6 +10000eca: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ece: f000 f889 bl 10000fe4 +10000ed2: 4b0f ldr r3, [pc, #60] @ (10000f10 ) +10000ed4: 02a4 lsls r4, r4, #10 +10000ed6: fba3 2300 umull r2, r3, r3, r0 +10000eda: 0adb lsrs r3, r3, #11 +10000edc: 2100 movs r1, #0 +10000ede: fbb4 f0f3 udiv r0, r4, r3 +10000ee2: f7ff ff67 bl 10000db4 +10000ee6: e7c5 b.n 10000e74 +10000ee8: f3c3 0345 ubfx r3, r3, #1, #6 +10000eec: 4611 mov r1, r2 +10000eee: eb03 1682 add.w r6, r3, r2, lsl #6 +10000ef2: 461a mov r2, r3 +10000ef4: e7b9 b.n 10000e6a +10000ef6: bf00 nop +10000ef8: 40078000 .word 0x40078000 +10000efc: 40022000 .word 0x40022000 +10000f00: 40023000 .word 0x40023000 +10000f04: 40020000 .word 0x40020000 +10000f08: 200004cc .word 0x200004cc +10000f0c: 003fffc0 .word 0x003fffc0 +10000f10: 8f2b7b75 .word 0x8f2b7b75 + +10000f14 : +10000f14: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f18: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f1c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f20: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f24: b5f0 push {r4, r5, r6, r7, lr} +10000f26: 4616 mov r6, r2 +10000f28: f8dc 2004 ldr.w r2, [ip, #4] +10000f2c: 1f05 subs r5, r0, #4 +10000f2e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f32: bf38 it cc +10000f34: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f38: b2ed uxtb r5, r5 +10000f3a: bf38 it cc +10000f3c: f8cc 2004 strcc.w r2, [ip, #4] +10000f40: 2d01 cmp r5, #1 +10000f42: d92a bls.n 10000f9a +10000f44: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f48: 4c25 ldr r4, [pc, #148] @ (10000fe0 ) +10000f4a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f4e: 6017 str r7, [r2, #0] +10000f50: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f54: b9b2 cbnz r2, 10000f84 +10000f56: f8dc 2000 ldr.w r2, [ip] +10000f5a: 2d01 cmp r5, #1 +10000f5c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f60: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f64: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f68: 6032 str r2, [r6, #0] +10000f6a: d92a bls.n 10000fc2 +10000f6c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f70: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f74: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f78: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f7c: 6011 str r1, [r2, #0] +10000f7e: f8cc 3004 str.w r3, [ip, #4] +10000f82: bdf0 pop {r4, r5, r6, r7, pc} +10000f84: 6967 ldr r7, [r4, #20] +10000f86: fbb7 fef2 udiv lr, r7, r2 +10000f8a: f10e 0e01 add.w lr, lr, #1 +10000f8e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000f92: f1be 0e03 subs.w lr, lr, #3 +10000f96: d2fc bcs.n 10000f92 +10000f98: e7dd b.n 10000f56 +10000f9a: 2901 cmp r1, #1 +10000f9c: d1d2 bne.n 10000f44 +10000f9e: 2403 movs r4, #3 +10000fa0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fa4: 6014 str r4, [r2, #0] +10000fa6: f8dc 2008 ldr.w r2, [ip, #8] +10000faa: 07d2 lsls r2, r2, #31 +10000fac: d5fb bpl.n 10000fa6 +10000fae: f8dc 2000 ldr.w r2, [ip] +10000fb2: 4c0b ldr r4, [pc, #44] @ (10000fe0 ) +10000fb4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fb8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fbc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fc0: 6032 str r2, [r6, #0] +10000fc2: 2201 movs r2, #1 +10000fc4: f8dc 5000 ldr.w r5, [ip] +10000fc8: 404d eors r5, r1 +10000fca: f005 0503 and.w r5, r5, #3 +10000fce: 6035 str r5, [r6, #0] +10000fd0: fa02 f101 lsl.w r1, r2, r1 +10000fd4: f8dc 2008 ldr.w r2, [ip, #8] +10000fd8: 420a tst r2, r1 +10000fda: d0fb beq.n 10000fd4 +10000fdc: e7c6 b.n 10000f6c +10000fde: bf00 nop +10000fe0: 2000045c .word 0x2000045c + +10000fe4 : +10000fe4: 4b01 ldr r3, [pc, #4] @ (10000fec ) +10000fe6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000fea: 4770 bx lr +10000fec: 2000045c .word 0x2000045c + +10000ff0 : +10000ff0: b470 push {r4, r5, r6} +10000ff2: 9d03 ldr r5, [sp, #12] +10000ff4: 6804 ldr r4, [r0, #0] +10000ff6: 032d lsls r5, r5, #12 +10000ff8: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000ffc: 4b1b ldr r3, [pc, #108] @ (1000106c ) +10000ffe: 2c00 cmp r4, #0 +10001000: fbb3 f3f1 udiv r3, r3, r1 +10001004: fbb2 f6f3 udiv r6, r2, r3 +10001008: db1f blt.n 1000104a +1000100a: 4a19 ldr r2, [pc, #100] @ (10001070 ) +1000100c: 4b19 ldr r3, [pc, #100] @ (10001074 ) +1000100e: 4290 cmp r0, r2 +10001010: bf14 ite ne +10001012: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001016: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000101a: 4c17 ldr r4, [pc, #92] @ (10001078 ) +1000101c: 601a str r2, [r3, #0] +1000101e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001022: 601a str r2, [r3, #0] +10001024: 68a3 ldr r3, [r4, #8] +10001026: ea32 0303 bics.w r3, r2, r3 +1000102a: d1fb bne.n 10001024 +1000102c: 2221 movs r2, #33 @ 0x21 +1000102e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001032: 3304 adds r3, #4 +10001034: 6001 str r1, [r0, #0] +10001036: 6086 str r6, [r0, #8] +10001038: 601a str r2, [r3, #0] +1000103a: 6802 ldr r2, [r0, #0] +1000103c: 2a00 cmp r2, #0 +1000103e: dafc bge.n 1000103a +10001040: 2208 movs r2, #8 +10001042: 60c5 str r5, [r0, #12] +10001044: 601a str r2, [r3, #0] +10001046: bc70 pop {r4, r5, r6} +10001048: 4770 bx lr +1000104a: 6803 ldr r3, [r0, #0] +1000104c: f003 033f and.w r3, r3, #63 @ 0x3f +10001050: 428b cmp r3, r1 +10001052: d1da bne.n 1000100a +10001054: 6883 ldr r3, [r0, #8] +10001056: f3c3 030b ubfx r3, r3, #0, #12 +1000105a: 42b3 cmp r3, r6 +1000105c: d1d5 bne.n 1000100a +1000105e: 68c3 ldr r3, [r0, #12] +10001060: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001064: 42ab cmp r3, r5 +10001066: d1d0 bne.n 1000100a +10001068: e7ed b.n 10001046 +1000106a: bf00 nop +1000106c: 00b71b00 .word 0x00b71b00 +10001070: 40058000 .word 0x40058000 +10001074: 40022000 .word 0x40022000 +10001078: 40020000 .word 0x40020000 + +1000107c : +1000107c: 2301 movs r3, #1 +1000107e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001082: 0080 lsls r0, r0, #2 +10001084: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001088: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000108c: 6041 str r1, [r0, #4] +1000108e: 6003 str r3, [r0, #0] +10001090: 4770 bx lr +10001092: bf00 nop + +10001094 : +10001094: 2300 movs r3, #0 +10001096: 8adb ldrh r3, [r3, #22] +10001098: 2200 movs r2, #0 +1000109a: e842 f200 tt r2, r2 +1000109e: 0252 lsls r2, r2, #9 +100010a0: d401 bmi.n 100010a6 +100010a2: 2110 movs r1, #16 +100010a4: 4718 bx r3 +100010a6: 2104 movs r1, #4 +100010a8: 4718 bx r3 +100010aa: bf00 nop + +100010ac : +100010ac: 4a03 ldr r2, [pc, #12] @ (100010bc ) +100010ae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010b2: 2b00 cmp r3, #0 +100010b4: d0fb beq.n 100010ae +100010b6: f3bf 8f5f dmb sy +100010ba: 4770 bx lr +100010bc: 400e0000 .word 0x400e0000 + +100010c0 : +100010c0: 2100 movs r1, #0 +100010c2: 4b04 ldr r3, [pc, #16] @ (100010d4 ) +100010c4: 4a04 ldr r2, [pc, #16] @ (100010d8 ) +100010c6: f3bf 8f5f dmb sy +100010ca: f843 1b04 str.w r1, [r3], #4 +100010ce: 4293 cmp r3, r2 +100010d0: d1f9 bne.n 100010c6 +100010d2: 4770 bx lr +100010d4: 400e080c .word 0x400e080c +100010d8: 400e082c .word 0x400e082c + +100010dc : +100010dc: b410 push {r4} +100010de: f44f 708d mov.w r0, #282 @ 0x11a +100010e2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010e6: 4a06 ldr r2, [pc, #24] @ (10001100 ) +100010e8: 4b06 ldr r3, [pc, #24] @ (10001104 ) +100010ea: 4907 ldr r1, [pc, #28] @ (10001108 ) +100010ec: 6014 str r4, [r2, #0] +100010ee: 60d0 str r0, [r2, #12] +100010f0: 6019 str r1, [r3, #0] +100010f2: 6853 ldr r3, [r2, #4] +100010f4: 2b00 cmp r3, #0 +100010f6: dafc bge.n 100010f2 +100010f8: f85d 4b04 ldr.w r4, [sp], #4 +100010fc: 4770 bx lr +100010fe: bf00 nop +10001100: 40048000 .word 0x40048000 +10001104: 4004a000 .word 0x4004a000 +10001108: 00fab000 .word 0x00fab000 + +1000110c : +1000110c: 4770 bx lr +1000110e: bf00 nop + +10001110 : +10001110: b508 push {r3, lr} +10001112: 4801 ldr r0, [pc, #4] @ (10001118 ) +10001114: f7ff f8b6 bl 10000284 +10001118: 10001a14 .word 0x10001a14 + +1000111c : +1000111c: b538 push {r3, r4, r5, lr} +1000111e: 4c05 ldr r4, [pc, #20] @ (10001134 ) +10001120: 4d05 ldr r5, [pc, #20] @ (10001138 ) +10001122: 42ac cmp r4, r5 +10001124: d204 bcs.n 10001130 +10001126: f854 3b04 ldr.w r3, [r4], #4 +1000112a: 4798 blx r3 +1000112c: 42ac cmp r4, r5 +1000112e: d3fa bcc.n 10001126 +10001130: bd38 pop {r3, r4, r5, pc} +10001132: bf00 nop +10001134: 10001988 .word 0x10001988 +10001138: 100019c8 .word 0x100019c8 + +1000113c : +1000113c: b410 push {r4} +1000113e: 4807 ldr r0, [pc, #28] @ (1000115c ) +10001140: 4c07 ldr r4, [pc, #28] @ (10001160 ) +10001142: 4b08 ldr r3, [pc, #32] @ (10001164 ) +10001144: 4a08 ldr r2, [pc, #32] @ (10001168 ) +10001146: 4909 ldr r1, [pc, #36] @ (1000116c ) +10001148: 6004 str r4, [r0, #0] +1000114a: 601a str r2, [r3, #0] +1000114c: 688b ldr r3, [r1, #8] +1000114e: ea32 0303 bics.w r3, r2, r3 +10001152: d1fb bne.n 1000114c +10001154: f85d 4b04 ldr.w r4, [sp], #4 +10001158: 4770 bx lr +1000115a: bf00 nop +1000115c: 40022000 .word 0x40022000 +10001160: efef3b7f .word 0xefef3b7f +10001164: 40023000 .word 0x40023000 +10001168: 03f3fff6 .word 0x03f3fff6 +1000116c: 40020000 .word 0x40020000 + +10001170 : +10001170: 4b04 ldr r3, [pc, #16] @ (10001184 ) +10001172: 6cdb ldr r3, [r3, #76] @ 0x4c +10001174: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001178: d103 bne.n 10001182 +1000117a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000117e: 4b02 ldr r3, [pc, #8] @ (10001188 ) +10001180: 64da str r2, [r3, #76] @ 0x4c +10001182: 4770 bx lr +10001184: 50110000 .word 0x50110000 +10001188: 50112000 .word 0x50112000 + +1000118c : +1000118c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001190: 4b04 ldr r3, [pc, #16] @ (100011a4 ) +10001192: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001196: 430b orrs r3, r1 +10001198: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000119c: ee10 0430 dcp_rcmp r0 +100011a0: 4770 bx lr +100011a2: bf00 nop +100011a4: 00300303 .word 0x00300303 + +100011a8 : +100011a8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011ac: 4b04 ldr r3, [pc, #16] @ (100011c0 ) +100011ae: 4a05 ldr r2, [pc, #20] @ (100011c4 ) +100011b0: 6019 str r1, [r3, #0] +100011b2: 6893 ldr r3, [r2, #8] +100011b4: 43db mvns r3, r3 +100011b6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011ba: d1fa bne.n 100011b2 +100011bc: 4770 bx lr +100011be: bf00 nop +100011c0: 40023000 .word 0x40023000 +100011c4: 40020000 .word 0x40020000 + +100011c8 : +100011c8: b510 push {r4, lr} +100011ca: f245 2053 movw r0, #21075 @ 0x5253 +100011ce: f7ff ff61 bl 10001094 +100011d2: e8bd 4010 ldmia.w sp!, {r4, lr} +100011d6: 4603 mov r3, r0 +100011d8: 2004 movs r0, #4 +100011da: 4718 bx r3 + +100011dc : +100011dc: b510 push {r4, lr} +100011de: f245 2053 movw r0, #21075 @ 0x5253 +100011e2: f7ff ff57 bl 10001094 +100011e6: e8bd 4010 ldmia.w sp!, {r4, lr} +100011ea: 4603 mov r3, r0 +100011ec: 2001 movs r0, #1 +100011ee: 4718 bx r3 + +100011f0 : +100011f0: f7ff b8a0 b.w 10000334 + +100011f4 : +100011f4: 4914 ldr r1, [pc, #80] @ (10001248 ) +100011f6: 4b15 ldr r3, [pc, #84] @ (1000124c ) +100011f8: b570 push {r4, r5, r6, lr} +100011fa: 1a5c subs r4, r3, r1 +100011fc: 10a6 asrs r6, r4, #2 +100011fe: 2e44 cmp r6, #68 @ 0x44 +10001200: 4632 mov r2, r6 +10001202: bf28 it cs +10001204: 2244 movcs r2, #68 @ 0x44 +10001206: 4d12 ldr r5, [pc, #72] @ (10001250 ) +10001208: 0092 lsls r2, r2, #2 +1000120a: 4628 mov r0, r5 +1000120c: f000 fb0e bl 1000182c +10001210: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001214: d813 bhi.n 1000123e +10001216: 4a0f ldr r2, [pc, #60] @ (10001254 ) +10001218: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000121c: d012 beq.n 10001244 +1000121e: 192b adds r3, r5, r4 +10001220: 0841 lsrs r1, r0, #1 +10001222: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001226: e9c3 2200 strd r2, r2, [r3] +1000122a: 3308 adds r3, #8 +1000122c: 428b cmp r3, r1 +1000122e: d1fa bne.n 10001226 +10001230: 07c3 lsls r3, r0, #31 +10001232: d504 bpl.n 1000123e +10001234: f020 0001 bic.w r0, r0, #1 +10001238: 4430 add r0, r6 +1000123a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000123e: 4b06 ldr r3, [pc, #24] @ (10001258 ) +10001240: 609d str r5, [r3, #8] +10001242: bd70 pop {r4, r5, r6, pc} +10001244: 2043 movs r0, #67 @ 0x43 +10001246: e7f8 b.n 1000123a +10001248: 10000000 .word 0x10000000 +1000124c: 10000110 .word 0x10000110 +10001250: 20000000 .word 0x20000000 +10001254: 10000111 .word 0x10000111 +10001258: e000ed00 .word 0xe000ed00 + +1000125c : +1000125c: 2300 movs r3, #0 +1000125e: b570 push {r4, r5, r6, lr} +10001260: 4c2b ldr r4, [pc, #172] @ (10001310 ) +10001262: b082 sub sp, #8 +10001264: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001268: f7ff ff38 bl 100010dc +1000126c: 2201 movs r2, #1 +1000126e: 4b29 ldr r3, [pc, #164] @ (10001314 ) +10001270: 63da str r2, [r3, #60] @ 0x3c +10001272: 6c63 ldr r3, [r4, #68] @ 0x44 +10001274: 2b01 cmp r3, #1 +10001276: d1fc bne.n 10001272 +10001278: 2103 movs r1, #3 +1000127a: 4a26 ldr r2, [pc, #152] @ (10001314 ) +1000127c: 4b24 ldr r3, [pc, #144] @ (10001310 ) +1000127e: 6311 str r1, [r2, #48] @ 0x30 +10001280: 6b9c ldr r4, [r3, #56] @ 0x38 +10001282: 2c01 cmp r4, #1 +10001284: d1fc bne.n 10001280 +10001286: 2602 movs r6, #2 +10001288: 2505 movs r5, #5 +1000128a: 4621 mov r1, r4 +1000128c: 2305 movs r3, #5 +1000128e: 4a22 ldr r2, [pc, #136] @ (10001318 ) +10001290: 4822 ldr r0, [pc, #136] @ (1000131c ) +10001292: 9600 str r6, [sp, #0] +10001294: f7ff feac bl 10000ff0 +10001298: 4621 mov r1, r4 +1000129a: 462b mov r3, r5 +1000129c: 4a20 ldr r2, [pc, #128] @ (10001320 ) +1000129e: 4821 ldr r0, [pc, #132] @ (10001324 ) +100012a0: 9500 str r5, [sp, #0] +100012a2: f7ff fea5 bl 10000ff0 +100012a6: 2200 movs r2, #0 +100012a8: 2004 movs r0, #4 +100012aa: 4631 mov r1, r6 +100012ac: 4b1e ldr r3, [pc, #120] @ (10001328 ) +100012ae: f7ff fe31 bl 10000f14 +100012b2: 4621 mov r1, r4 +100012b4: 4628 mov r0, r5 +100012b6: 2200 movs r2, #0 +100012b8: 4b1c ldr r3, [pc, #112] @ (1000132c ) +100012ba: f7ff fe2b bl 10000f14 +100012be: 2200 movs r2, #0 +100012c0: 2008 movs r0, #8 +100012c2: 4611 mov r1, r2 +100012c4: 4b1a ldr r3, [pc, #104] @ (10001330 ) +100012c6: f7ff fe25 bl 10000f14 +100012ca: 2200 movs r2, #0 +100012cc: 2009 movs r0, #9 +100012ce: 4611 mov r1, r2 +100012d0: 4b17 ldr r3, [pc, #92] @ (10001330 ) +100012d2: f7ff fe1f bl 10000f14 +100012d6: 2200 movs r2, #0 +100012d8: 2006 movs r0, #6 +100012da: 4611 mov r1, r2 +100012dc: 4b13 ldr r3, [pc, #76] @ (1000132c ) +100012de: f7ff fe19 bl 10000f14 +100012e2: 2200 movs r2, #0 +100012e4: 4b11 ldr r3, [pc, #68] @ (1000132c ) +100012e6: 2007 movs r0, #7 +100012e8: 4611 mov r1, r2 +100012ea: f7ff fe13 bl 10000f14 +100012ee: 2004 movs r0, #4 +100012f0: f7ff fe78 bl 10000fe4 +100012f4: 2400 movs r4, #0 +100012f6: 4b0f ldr r3, [pc, #60] @ (10001334 ) +100012f8: fba3 3500 umull r3, r5, r3, r0 +100012fc: 0cad lsrs r5, r5, #18 +100012fe: b2e0 uxtb r0, r4 +10001300: 4629 mov r1, r5 +10001302: 3401 adds r4, #1 +10001304: f7ff feba bl 1000107c +10001308: 2c06 cmp r4, #6 +1000130a: d1f8 bne.n 100012fe +1000130c: b002 add sp, #8 +1000130e: bd70 pop {r4, r5, r6, pc} +10001310: 40010000 .word 0x40010000 +10001314: 40013000 .word 0x40013000 +10001318: 59682f00 .word 0x59682f00 +1000131c: 40050000 .word 0x40050000 +10001320: 47868c00 .word 0x47868c00 +10001324: 40058000 .word 0x40058000 +10001328: 00b71b00 .word 0x00b71b00 +1000132c: 08f0d180 .word 0x08f0d180 +10001330: 02dc6c00 .word 0x02dc6c00 +10001334: 431bde83 .word 0x431bde83 + +10001338 <_out_char>: +10001338: b900 cbnz r0, 1000133c <_out_char+0x4> +1000133a: 4770 bx lr +1000133c: f000 b91c b.w 10001578 <__wrap_putchar> + +10001340 : +10001340: b510 push {r4, lr} +10001342: 4b09 ldr r3, [pc, #36] @ (10001368 ) +10001344: b084 sub sp, #16 +10001346: 681c ldr r4, [r3, #0] +10001348: b14c cbz r4, 1000135e +1000134a: 4603 mov r3, r0 +1000134c: 9100 str r1, [sp, #0] +1000134e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001352: a903 add r1, sp, #12 +10001354: 4805 ldr r0, [pc, #20] @ (1000136c ) +10001356: 47a0 blx r4 +10001358: 2001 movs r0, #1 +1000135a: b004 add sp, #16 +1000135c: bd10 pop {r4, pc} +1000135e: f000 f94d bl 100015fc <__wrap_puts> +10001362: 4620 mov r0, r4 +10001364: b004 add sp, #16 +10001366: bd10 pop {r4, pc} +10001368: 2000048c .word 0x2000048c +1000136c: 10001339 .word 0x10001339 + +10001370 <_exit>: +10001370: be00 bkpt 0x0000 +10001372: e7fd b.n 10001370 <_exit> + +10001374 : +10001374: b508 push {r3, lr} +10001376: f7ff fffb bl 10001370 <_exit> +1000137a: bf00 nop + +1000137c : +1000137c: b538 push {r3, r4, r5, lr} +1000137e: 4c06 ldr r4, [pc, #24] @ (10001398 ) +10001380: 4d06 ldr r5, [pc, #24] @ (1000139c ) +10001382: f7ff fecb bl 1000111c +10001386: 42ac cmp r4, r5 +10001388: d204 bcs.n 10001394 +1000138a: f854 3b04 ldr.w r3, [r4], #4 +1000138e: 4798 blx r3 +10001390: 42ac cmp r4, r5 +10001392: d3fa bcc.n 1000138a +10001394: bd38 pop {r3, r4, r5, pc} +10001396: bf00 nop +10001398: 100019c8 .word 0x100019c8 +1000139c: 100019cc .word 0x100019cc + +100013a0 : +100013a0: 6803 ldr r3, [r0, #0] +100013a2: 4608 mov r0, r1 +100013a4: 4611 mov r1, r2 +100013a6: 4718 bx r3 + +100013a8 : +100013a8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100013ac: 4615 mov r5, r2 +100013ae: 7d42 ldrb r2, [r0, #21] +100013b0: 4607 mov r7, r0 +100013b2: 4688 mov r8, r1 +100013b4: 2a00 cmp r2, #0 +100013b6: d046 beq.n 10001446 +100013b8: 2d00 cmp r5, #0 +100013ba: dd1d ble.n 100013f8 +100013bc: 780b ldrb r3, [r1, #0] +100013be: 2b0a cmp r3, #10 +100013c0: d023 beq.n 1000140a +100013c2: 2d01 cmp r5, #1 +100013c4: f04f 0c00 mov.w ip, #0 +100013c8: d018 beq.n 100013fc +100013ca: 4646 mov r6, r8 +100013cc: 2401 movs r4, #1 +100013ce: f816 2f01 ldrb.w r2, [r6, #1]! +100013d2: 4621 mov r1, r4 +100013d4: 2a0a cmp r2, #10 +100013d6: f104 0401 add.w r4, r4, #1 +100013da: d022 beq.n 10001422 +100013dc: 42a5 cmp r5, r4 +100013de: d1f6 bne.n 100013ce +100013e0: 4565 cmp r5, ip +100013e2: dc0b bgt.n 100013fc +100013e4: eb08 0305 add.w r3, r8, r5 +100013e8: f813 3c01 ldrb.w r3, [r3, #-1] +100013ec: f1a3 030d sub.w r3, r3, #13 +100013f0: fab3 f383 clz r3, r3 +100013f4: 095b lsrs r3, r3, #5 +100013f6: 753b strb r3, [r7, #20] +100013f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100013fc: 683b ldr r3, [r7, #0] +100013fe: eba5 010c sub.w r1, r5, ip +10001402: eb08 000c add.w r0, r8, ip +10001406: 4798 blx r3 +10001408: e7ec b.n 100013e4 +1000140a: 7d03 ldrb r3, [r0, #20] +1000140c: 2b00 cmp r3, #0 +1000140e: d1d8 bne.n 100013c2 +10001410: 6803 ldr r3, [r0, #0] +10001412: 2102 movs r1, #2 +10001414: 480f ldr r0, [pc, #60] @ (10001454 ) +10001416: 4798 blx r3 +10001418: 2d01 cmp r5, #1 +1000141a: d0e3 beq.n 100013e4 +1000141c: f04f 0c01 mov.w ip, #1 +10001420: e7d3 b.n 100013ca +10001422: f816 3c01 ldrb.w r3, [r6, #-1] +10001426: 2b0d cmp r3, #13 +10001428: d0d8 beq.n 100013dc +1000142a: 458c cmp ip, r1 +1000142c: eb08 000c add.w r0, r8, ip +10001430: eba1 010c sub.w r1, r1, ip +10001434: da01 bge.n 1000143a +10001436: 683b ldr r3, [r7, #0] +10001438: 4798 blx r3 +1000143a: 2102 movs r1, #2 +1000143c: 4805 ldr r0, [pc, #20] @ (10001454 ) +1000143e: 683b ldr r3, [r7, #0] +10001440: 4798 blx r3 +10001442: 46a4 mov ip, r4 +10001444: e7ca b.n 100013dc +10001446: 4629 mov r1, r5 +10001448: 4640 mov r0, r8 +1000144a: 683b ldr r3, [r7, #0] +1000144c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001450: 4718 bx r3 +10001452: bf00 nop +10001454: 10001af8 .word 0x10001af8 + +10001458 : +10001458: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +1000145c: b082 sub sp, #8 +1000145e: 460d mov r5, r1 +10001460: 4691 mov r9, r2 +10001462: 461c mov r4, r3 +10001464: 4606 mov r6, r0 +10001466: f7ff fc9b bl 10000da0 +1000146a: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +1000146e: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001472: 4a2e ldr r2, [pc, #184] @ (1000152c ) +10001474: 1882 adds r2, r0, r2 +10001476: f141 0300 adc.w r3, r1, #0 +1000147a: 4594 cmp ip, r2 +1000147c: eb77 0103 sbcs.w r1, r7, r3 +10001480: bf3c itt cc +10001482: 4662 movcc r2, ip +10001484: 463b movcc r3, r7 +10001486: 482a ldr r0, [pc, #168] @ (10001530 ) +10001488: f000 fa7a bl 10001980 <__mutex_try_enter_block_until_veneer> +1000148c: 1c6b adds r3, r5, #1 +1000148e: 4680 mov r8, r0 +10001490: d040 beq.n 10001514 +10001492: b30c cbz r4, 100014d8 +10001494: 4f27 ldr r7, [pc, #156] @ (10001534 ) +10001496: 4b28 ldr r3, [pc, #160] @ (10001538 ) +10001498: 681c ldr r4, [r3, #0] +1000149a: b1b4 cbz r4, 100014ca +1000149c: f1b9 0f00 cmp.w r9, #0 +100014a0: d11c bne.n 100014dc +100014a2: f8df 909c ldr.w r9, [pc, #156] @ 10001540 +100014a6: e001 b.n 100014ac +100014a8: 6924 ldr r4, [r4, #16] +100014aa: b174 cbz r4, 100014ca +100014ac: 6823 ldr r3, [r4, #0] +100014ae: 2b00 cmp r3, #0 +100014b0: d0fa beq.n 100014a8 +100014b2: f8d9 3000 ldr.w r3, [r9] +100014b6: b10b cbz r3, 100014bc +100014b8: 429c cmp r4, r3 +100014ba: d1f5 bne.n 100014a8 +100014bc: 4620 mov r0, r4 +100014be: 462a mov r2, r5 +100014c0: 4631 mov r1, r6 +100014c2: 47b8 blx r7 +100014c4: 6924 ldr r4, [r4, #16] +100014c6: 2c00 cmp r4, #0 +100014c8: d1f0 bne.n 100014ac +100014ca: f1b8 0f00 cmp.w r8, #0 +100014ce: d126 bne.n 1000151e +100014d0: 4628 mov r0, r5 +100014d2: b002 add sp, #8 +100014d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100014d8: 4f18 ldr r7, [pc, #96] @ (1000153c ) +100014da: e7dc b.n 10001496 +100014dc: f04f 0a0a mov.w sl, #10 +100014e0: f8df 905c ldr.w r9, [pc, #92] @ 10001540 +100014e4: e002 b.n 100014ec +100014e6: 6924 ldr r4, [r4, #16] +100014e8: 2c00 cmp r4, #0 +100014ea: d0ee beq.n 100014ca +100014ec: 6823 ldr r3, [r4, #0] +100014ee: 2b00 cmp r3, #0 +100014f0: d0f9 beq.n 100014e6 +100014f2: f8d9 3000 ldr.w r3, [r9] +100014f6: b10b cbz r3, 100014fc +100014f8: 42a3 cmp r3, r4 +100014fa: d1f4 bne.n 100014e6 +100014fc: 462a mov r2, r5 +100014fe: 4631 mov r1, r6 +10001500: 4620 mov r0, r4 +10001502: 47b8 blx r7 +10001504: 2201 movs r2, #1 +10001506: 4620 mov r0, r4 +10001508: f10d 0107 add.w r1, sp, #7 +1000150c: f88d a007 strb.w sl, [sp, #7] +10001510: 47b8 blx r7 +10001512: e7e8 b.n 100014e6 +10001514: 4630 mov r0, r6 +10001516: f000 f9ff bl 10001918 +1000151a: 4605 mov r5, r0 +1000151c: e7b9 b.n 10001492 +1000151e: 4804 ldr r0, [pc, #16] @ (10001530 ) +10001520: f000 fa2a bl 10001978 <__mutex_exit_veneer> +10001524: 4628 mov r0, r5 +10001526: b002 add sp, #8 +10001528: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000152c: 000f4240 .word 0x000f4240 +10001530: 200002a4 .word 0x200002a4 +10001534: 100013a9 .word 0x100013a9 +10001538: 20000484 .word 0x20000484 +1000153c: 100013a1 .word 0x100013a1 +10001540: 20000488 .word 0x20000488 + +10001544 : +10001544: 4a08 ldr r2, [pc, #32] @ (10001568 ) +10001546: 6813 ldr r3, [r2, #0] +10001548: b923 cbnz r3, 10001554 +1000154a: e00a b.n 10001562 +1000154c: f103 0210 add.w r2, r3, #16 +10001550: 691b ldr r3, [r3, #16] +10001552: b133 cbz r3, 10001562 +10001554: 4283 cmp r3, r0 +10001556: d1f9 bne.n 1000154c +10001558: b929 cbnz r1, 10001566 +1000155a: 6918 ldr r0, [r3, #16] +1000155c: 6010 str r0, [r2, #0] +1000155e: 6119 str r1, [r3, #16] +10001560: 4770 bx lr +10001562: b101 cbz r1, 10001566 +10001564: 6010 str r0, [r2, #0] +10001566: 4770 bx lr +10001568: 20000484 .word 0x20000484 + +1000156c : +1000156c: b508 push {r3, lr} +1000156e: f000 f933 bl 100017d8 +10001572: 2001 movs r0, #1 +10001574: bd08 pop {r3, pc} +10001576: bf00 nop + +10001578 <__wrap_putchar>: +10001578: b5f0 push {r4, r5, r6, r7, lr} +1000157a: b083 sub sp, #12 +1000157c: 4606 mov r6, r0 +1000157e: f88d 0007 strb.w r0, [sp, #7] +10001582: f7ff fc0d bl 10000da0 +10001586: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000158a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000158e: 4a17 ldr r2, [pc, #92] @ (100015ec <__wrap_putchar+0x74>) +10001590: 1882 adds r2, r0, r2 +10001592: f141 0300 adc.w r3, r1, #0 +10001596: 4295 cmp r5, r2 +10001598: eb74 0103 sbcs.w r1, r4, r3 +1000159c: bf3c itt cc +1000159e: 4623 movcc r3, r4 +100015a0: 462a movcc r2, r5 +100015a2: 4813 ldr r0, [pc, #76] @ (100015f0 <__wrap_putchar+0x78>) +100015a4: f000 f9ec bl 10001980 <__mutex_try_enter_block_until_veneer> +100015a8: 4b12 ldr r3, [pc, #72] @ (100015f4 <__wrap_putchar+0x7c>) +100015aa: 4607 mov r7, r0 +100015ac: 681c ldr r4, [r3, #0] +100015ae: b19c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b0: 4d11 ldr r5, [pc, #68] @ (100015f8 <__wrap_putchar+0x80>) +100015b2: e001 b.n 100015b8 <__wrap_putchar+0x40> +100015b4: 6924 ldr r4, [r4, #16] +100015b6: b17c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b8: 6823 ldr r3, [r4, #0] +100015ba: 2b00 cmp r3, #0 +100015bc: d0fa beq.n 100015b4 <__wrap_putchar+0x3c> +100015be: 682b ldr r3, [r5, #0] +100015c0: b10b cbz r3, 100015c6 <__wrap_putchar+0x4e> +100015c2: 429c cmp r4, r3 +100015c4: d1f6 bne.n 100015b4 <__wrap_putchar+0x3c> +100015c6: 4620 mov r0, r4 +100015c8: 2201 movs r2, #1 +100015ca: f10d 0107 add.w r1, sp, #7 +100015ce: f7ff feeb bl 100013a8 +100015d2: 6924 ldr r4, [r4, #16] +100015d4: 2c00 cmp r4, #0 +100015d6: d1ef bne.n 100015b8 <__wrap_putchar+0x40> +100015d8: b917 cbnz r7, 100015e0 <__wrap_putchar+0x68> +100015da: 4630 mov r0, r6 +100015dc: b003 add sp, #12 +100015de: bdf0 pop {r4, r5, r6, r7, pc} +100015e0: 4803 ldr r0, [pc, #12] @ (100015f0 <__wrap_putchar+0x78>) +100015e2: f000 f9c9 bl 10001978 <__mutex_exit_veneer> +100015e6: 4630 mov r0, r6 +100015e8: b003 add sp, #12 +100015ea: bdf0 pop {r4, r5, r6, r7, pc} +100015ec: 000f4240 .word 0x000f4240 +100015f0: 200002a4 .word 0x200002a4 +100015f4: 20000484 .word 0x20000484 +100015f8: 20000488 .word 0x20000488 + +100015fc <__wrap_puts>: +100015fc: b538 push {r3, r4, r5, lr} +100015fe: 4604 mov r4, r0 +10001600: f000 f98a bl 10001918 +10001604: 2301 movs r3, #1 +10001606: 4605 mov r5, r0 +10001608: 461a mov r2, r3 +1000160a: 4620 mov r0, r4 +1000160c: 4629 mov r1, r5 +1000160e: f7ff ff23 bl 10001458 +10001612: 4b08 ldr r3, [pc, #32] @ (10001634 <__wrap_puts+0x38>) +10001614: 681c ldr r4, [r3, #0] +10001616: b12c cbz r4, 10001624 <__wrap_puts+0x28> +10001618: 6863 ldr r3, [r4, #4] +1000161a: b12b cbz r3, 10001628 <__wrap_puts+0x2c> +1000161c: 4798 blx r3 +1000161e: 6924 ldr r4, [r4, #16] +10001620: 2c00 cmp r4, #0 +10001622: d1f9 bne.n 10001618 <__wrap_puts+0x1c> +10001624: 4628 mov r0, r5 +10001626: bd38 pop {r3, r4, r5, pc} +10001628: 6924 ldr r4, [r4, #16] +1000162a: 2c00 cmp r4, #0 +1000162c: d1f4 bne.n 10001618 <__wrap_puts+0x1c> +1000162e: 4628 mov r0, r5 +10001630: bd38 pop {r3, r4, r5, pc} +10001632: bf00 nop +10001634: 20000484 .word 0x20000484 + +10001638 : +10001638: f1b1 0c00 subs.w ip, r1, #0 +1000163c: dd1d ble.n 1000167a +1000163e: 4a0f ldr r2, [pc, #60] @ (1000167c ) +10001640: 4b0f ldr r3, [pc, #60] @ (10001680 ) +10001642: 6812 ldr r2, [r2, #0] +10001644: b530 push {r4, r5, lr} +10001646: 1ad3 subs r3, r2, r3 +10001648: fab3 f383 clz r3, r3 +1000164c: 240d movs r4, #13 +1000164e: 4d0d ldr r5, [pc, #52] @ (10001684 ) +10001650: 095b lsrs r3, r3, #5 +10001652: 1e41 subs r1, r0, #1 +10001654: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10001658: 448c add ip, r1 +1000165a: f811 0f01 ldrb.w r0, [r1, #1]! +1000165e: 4586 cmp lr, r0 +10001660: d006 beq.n 10001670 +10001662: 6993 ldr r3, [r2, #24] +10001664: 069b lsls r3, r3, #26 +10001666: d4fc bmi.n 10001662 +10001668: 4561 cmp r1, ip +1000166a: 6010 str r0, [r2, #0] +1000166c: d1f5 bne.n 1000165a +1000166e: bd30 pop {r4, r5, pc} +10001670: 6993 ldr r3, [r2, #24] +10001672: 069d lsls r5, r3, #26 +10001674: d4fc bmi.n 10001670 +10001676: 6014 str r4, [r2, #0] +10001678: e7f3 b.n 10001662 +1000167a: 4770 bx lr +1000167c: 200004d0 .word 0x200004d0 +10001680: 40078000 .word 0x40078000 +10001684: 200004cc .word 0x200004cc + +10001688 : +10001688: 4b22 ldr r3, [pc, #136] @ (10001714 ) +1000168a: f1b1 0c00 subs.w ip, r1, #0 +1000168e: b410 push {r4} +10001690: 681c ldr r4, [r3, #0] +10001692: dd2e ble.n 100016f2 +10001694: 4603 mov r3, r0 +10001696: 2000 movs r0, #0 +10001698: 4a1f ldr r2, [pc, #124] @ (10001718 ) +1000169a: 1e59 subs r1, r3, #1 +1000169c: 6812 ldr r2, [r2, #0] +1000169e: 6993 ldr r3, [r2, #24] +100016a0: 06db lsls r3, r3, #27 +100016a2: d417 bmi.n 100016d4 +100016a4: 3001 adds r0, #1 +100016a6: 6993 ldr r3, [r2, #24] +100016a8: 06db lsls r3, r3, #27 +100016aa: d4fc bmi.n 100016a6 +100016ac: 6813 ldr r3, [r2, #0] +100016ae: 4584 cmp ip, r0 +100016b0: f801 3f01 strb.w r3, [r1, #1]! +100016b4: d1f3 bne.n 1000169e +100016b6: b14c cbz r4, 100016cc +100016b8: 2150 movs r1, #80 @ 0x50 +100016ba: 4613 mov r3, r2 +100016bc: 6391 str r1, [r2, #56] @ 0x38 +100016be: f853 2f34 ldr.w r2, [r3, #52]! +100016c2: f002 0238 and.w r2, r2, #56 @ 0x38 +100016c6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016ca: 601a str r2, [r3, #0] +100016cc: 4660 mov r0, ip +100016ce: f85d 4b04 ldr.w r4, [sp], #4 +100016d2: 4770 bx lr +100016d4: b14c cbz r4, 100016ea +100016d6: 2150 movs r1, #80 @ 0x50 +100016d8: 4613 mov r3, r2 +100016da: 6391 str r1, [r2, #56] @ 0x38 +100016dc: f853 2f34 ldr.w r2, [r3, #52]! +100016e0: f002 0238 and.w r2, r2, #56 @ 0x38 +100016e4: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016e8: 601a str r2, [r3, #0] +100016ea: b178 cbz r0, 1000170c +100016ec: f85d 4b04 ldr.w r4, [sp], #4 +100016f0: 4770 bx lr +100016f2: b15c cbz r4, 1000170c +100016f4: 4b08 ldr r3, [pc, #32] @ (10001718 ) +100016f6: 2150 movs r1, #80 @ 0x50 +100016f8: 681a ldr r2, [r3, #0] +100016fa: 4613 mov r3, r2 +100016fc: 6391 str r1, [r2, #56] @ 0x38 +100016fe: f853 2f34 ldr.w r2, [r3, #52]! +10001702: f002 0238 and.w r2, r2, #56 @ 0x38 +10001706: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000170a: 601a str r2, [r3, #0] +1000170c: f06f 0002 mvn.w r0, #2 +10001710: e7dd b.n 100016ce +10001712: bf00 nop +10001714: 20000450 .word 0x20000450 +10001718: 200004d0 .word 0x200004d0 + +1000171c : +1000171c: 4b05 ldr r3, [pc, #20] @ (10001734 ) +1000171e: 681b ldr r3, [r3, #0] +10001720: b133 cbz r3, 10001730 +10001722: 2100 movs r1, #0 +10001724: 4a04 ldr r2, [pc, #16] @ (10001738 ) +10001726: 4805 ldr r0, [pc, #20] @ (1000173c ) +10001728: 6812 ldr r2, [r2, #0] +1000172a: 6800 ldr r0, [r0, #0] +1000172c: 6391 str r1, [r2, #56] @ 0x38 +1000172e: 4718 bx r3 +10001730: 4770 bx lr +10001732: bf00 nop +10001734: 20000450 .word 0x20000450 +10001738: 200004d0 .word 0x200004d0 +1000173c: 20000454 .word 0x20000454 + +10001740 : +10001740: 4b02 ldr r3, [pc, #8] @ (1000174c ) +10001742: 681a ldr r2, [r3, #0] +10001744: 6993 ldr r3, [r2, #24] +10001746: 071b lsls r3, r3, #28 +10001748: d4fc bmi.n 10001744 +1000174a: 4770 bx lr +1000174c: 200004d0 .word 0x200004d0 + +10001750 : +10001750: b5f8 push {r3, r4, r5, r6, r7, lr} +10001752: 4f1c ldr r7, [pc, #112] @ (100017c4 ) +10001754: 4d1c ldr r5, [pc, #112] @ (100017c8 ) +10001756: 683a ldr r2, [r7, #0] +10001758: 4e1c ldr r6, [pc, #112] @ (100017cc ) +1000175a: 42aa cmp r2, r5 +1000175c: bf14 ite ne +1000175e: 2521 movne r5, #33 @ 0x21 +10001760: 2522 moveq r5, #34 @ 0x22 +10001762: 4604 mov r4, r0 +10001764: f8d6 c000 ldr.w ip, [r6] +10001768: b118 cbz r0, 10001772 +1000176a: f1bc 0f00 cmp.w ip, #0 +1000176e: d010 beq.n 10001792 +10001770: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001772: f1bc 0f00 cmp.w ip, #0 +10001776: d0fb beq.n 10001770 +10001778: 4601 mov r1, r0 +1000177a: 6390 str r0, [r2, #56] @ 0x38 +1000177c: 4628 mov r0, r5 +1000177e: f7fe fe05 bl 1000038c +10001782: 4628 mov r0, r5 +10001784: 4912 ldr r1, [pc, #72] @ (100017d0 ) +10001786: f7fe fe47 bl 10000418 +1000178a: 4b12 ldr r3, [pc, #72] @ (100017d4 ) +1000178c: 6034 str r4, [r6, #0] +1000178e: 601c str r4, [r3, #0] +10001790: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001792: 460b mov r3, r1 +10001794: 4a0f ldr r2, [pc, #60] @ (100017d4 ) +10001796: 490e ldr r1, [pc, #56] @ (100017d0 ) +10001798: 6030 str r0, [r6, #0] +1000179a: 4628 mov r0, r5 +1000179c: 6013 str r3, [r2, #0] +1000179e: f7fe fe0b bl 100003b8 +100017a2: 2101 movs r1, #1 +100017a4: 4628 mov r0, r5 +100017a6: f7fe fdf1 bl 1000038c +100017aa: 683a ldr r2, [r7, #0] +100017ac: 2150 movs r1, #80 @ 0x50 +100017ae: 4613 mov r3, r2 +100017b0: 6391 str r1, [r2, #56] @ 0x38 +100017b2: f853 2f34 ldr.w r2, [r3, #52]! +100017b6: f002 0238 and.w r2, r2, #56 @ 0x38 +100017ba: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100017be: 601a str r2, [r3, #0] +100017c0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100017c2: bf00 nop +100017c4: 200004d0 .word 0x200004d0 +100017c8: 40078000 .word 0x40078000 +100017cc: 20000450 .word 0x20000450 +100017d0: 1000171d .word 0x1000171d +100017d4: 20000454 .word 0x20000454 + +100017d8 : +100017d8: b510 push {r4, lr} +100017da: 490e ldr r1, [pc, #56] @ (10001814 ) +100017dc: 4c0e ldr r4, [pc, #56] @ (10001818 ) +100017de: 480f ldr r0, [pc, #60] @ (1000181c ) +100017e0: 4a0f ldr r2, [pc, #60] @ (10001820 ) +100017e2: 4b10 ldr r3, [pc, #64] @ (10001824 ) +100017e4: 7800 ldrb r0, [r0, #0] +100017e6: 6021 str r1, [r4, #0] +100017e8: 2000 movs r0, #0 +100017ea: 2102 movs r1, #2 +100017ec: 7812 ldrb r2, [r2, #0] +100017ee: 781b ldrb r3, [r3, #0] +100017f0: f7fe fd2a bl 10000248 +100017f4: 2102 movs r1, #2 +100017f6: 2001 movs r0, #1 +100017f8: f7fe fd26 bl 10000248 +100017fc: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10001800: 6820 ldr r0, [r4, #0] +10001802: f7ff fb05 bl 10000e10 +10001806: e8bd 4010 ldmia.w sp!, {r4, lr} +1000180a: 2101 movs r1, #1 +1000180c: 4806 ldr r0, [pc, #24] @ (10001828 ) +1000180e: f7ff be99 b.w 10001544 +10001812: bf00 nop +10001814: 40070000 .word 0x40070000 +10001818: 200004d0 .word 0x200004d0 +1000181c: 10001b48 .word 0x10001b48 +10001820: 10001b44 .word 0x10001b44 +10001824: 10001b40 .word 0x10001b40 +10001828: 2000028c .word 0x2000028c + +1000182c : +1000182c: 4684 mov ip, r0 +1000182e: ea41 0300 orr.w r3, r1, r0 +10001832: f013 0303 ands.w r3, r3, #3 +10001836: d149 bne.n 100018cc +10001838: 3a40 subs r2, #64 @ 0x40 +1000183a: d323 bcc.n 10001884 +1000183c: 680b ldr r3, [r1, #0] +1000183e: 6003 str r3, [r0, #0] +10001840: 684b ldr r3, [r1, #4] +10001842: 6043 str r3, [r0, #4] +10001844: 688b ldr r3, [r1, #8] +10001846: 6083 str r3, [r0, #8] +10001848: 68cb ldr r3, [r1, #12] +1000184a: 60c3 str r3, [r0, #12] +1000184c: 690b ldr r3, [r1, #16] +1000184e: 6103 str r3, [r0, #16] +10001850: 694b ldr r3, [r1, #20] +10001852: 6143 str r3, [r0, #20] +10001854: 698b ldr r3, [r1, #24] +10001856: 6183 str r3, [r0, #24] +10001858: 69cb ldr r3, [r1, #28] +1000185a: 61c3 str r3, [r0, #28] +1000185c: 6a0b ldr r3, [r1, #32] +1000185e: 6203 str r3, [r0, #32] +10001860: 6a4b ldr r3, [r1, #36] @ 0x24 +10001862: 6243 str r3, [r0, #36] @ 0x24 +10001864: 6a8b ldr r3, [r1, #40] @ 0x28 +10001866: 6283 str r3, [r0, #40] @ 0x28 +10001868: 6acb ldr r3, [r1, #44] @ 0x2c +1000186a: 62c3 str r3, [r0, #44] @ 0x2c +1000186c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000186e: 6303 str r3, [r0, #48] @ 0x30 +10001870: 6b4b ldr r3, [r1, #52] @ 0x34 +10001872: 6343 str r3, [r0, #52] @ 0x34 +10001874: 6b8b ldr r3, [r1, #56] @ 0x38 +10001876: 6383 str r3, [r0, #56] @ 0x38 +10001878: 6bcb ldr r3, [r1, #60] @ 0x3c +1000187a: 63c3 str r3, [r0, #60] @ 0x3c +1000187c: 3040 adds r0, #64 @ 0x40 +1000187e: 3140 adds r1, #64 @ 0x40 +10001880: 3a40 subs r2, #64 @ 0x40 +10001882: d2db bcs.n 1000183c +10001884: 3230 adds r2, #48 @ 0x30 +10001886: d30b bcc.n 100018a0 +10001888: 680b ldr r3, [r1, #0] +1000188a: 6003 str r3, [r0, #0] +1000188c: 684b ldr r3, [r1, #4] +1000188e: 6043 str r3, [r0, #4] +10001890: 688b ldr r3, [r1, #8] +10001892: 6083 str r3, [r0, #8] +10001894: 68cb ldr r3, [r1, #12] +10001896: 60c3 str r3, [r0, #12] +10001898: 3010 adds r0, #16 +1000189a: 3110 adds r1, #16 +1000189c: 3a10 subs r2, #16 +1000189e: d2f3 bcs.n 10001888 +100018a0: 320c adds r2, #12 +100018a2: d305 bcc.n 100018b0 +100018a4: f851 3b04 ldr.w r3, [r1], #4 +100018a8: f840 3b04 str.w r3, [r0], #4 +100018ac: 3a04 subs r2, #4 +100018ae: d2f9 bcs.n 100018a4 +100018b0: 3204 adds r2, #4 +100018b2: d008 beq.n 100018c6 +100018b4: 07d2 lsls r2, r2, #31 +100018b6: bf1c itt ne +100018b8: f811 3b01 ldrbne.w r3, [r1], #1 +100018bc: f800 3b01 strbne.w r3, [r0], #1 +100018c0: d301 bcc.n 100018c6 +100018c2: 880b ldrh r3, [r1, #0] +100018c4: 8003 strh r3, [r0, #0] +100018c6: 4660 mov r0, ip +100018c8: 4770 bx lr +100018ca: bf00 nop +100018cc: 2a08 cmp r2, #8 +100018ce: d313 bcc.n 100018f8 +100018d0: 078b lsls r3, r1, #30 +100018d2: d0b1 beq.n 10001838 +100018d4: f010 0303 ands.w r3, r0, #3 +100018d8: d0ae beq.n 10001838 +100018da: f1c3 0304 rsb r3, r3, #4 +100018de: 1ad2 subs r2, r2, r3 +100018e0: 07db lsls r3, r3, #31 +100018e2: bf1c itt ne +100018e4: f811 3b01 ldrbne.w r3, [r1], #1 +100018e8: f800 3b01 strbne.w r3, [r0], #1 +100018ec: d3a4 bcc.n 10001838 +100018ee: f831 3b02 ldrh.w r3, [r1], #2 +100018f2: f820 3b02 strh.w r3, [r0], #2 +100018f6: e79f b.n 10001838 +100018f8: 3a04 subs r2, #4 +100018fa: d3d9 bcc.n 100018b0 +100018fc: 3a01 subs r2, #1 +100018fe: f811 3b01 ldrb.w r3, [r1], #1 +10001902: f800 3b01 strb.w r3, [r0], #1 +10001906: d2f9 bcs.n 100018fc +10001908: 780b ldrb r3, [r1, #0] +1000190a: 7003 strb r3, [r0, #0] +1000190c: 784b ldrb r3, [r1, #1] +1000190e: 7043 strb r3, [r0, #1] +10001910: 788b ldrb r3, [r1, #2] +10001912: 7083 strb r3, [r0, #2] +10001914: 4660 mov r0, ip +10001916: 4770 bx lr + +10001918 : +10001918: f020 0103 bic.w r1, r0, #3 +1000191c: f010 0003 ands.w r0, r0, #3 +10001920: f1c0 0000 rsb r0, r0, #0 +10001924: f851 3b04 ldr.w r3, [r1], #4 +10001928: f100 0c04 add.w ip, r0, #4 +1000192c: ea4f 0ccc mov.w ip, ip, lsl #3 +10001930: f06f 0200 mvn.w r2, #0 +10001934: bf1c itt ne +10001936: fa22 f20c lsrne.w r2, r2, ip +1000193a: 4313 orrne r3, r2 +1000193c: f04f 0c01 mov.w ip, #1 +10001940: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001944: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001948: eba3 020c sub.w r2, r3, ip +1000194c: ea22 0203 bic.w r2, r2, r3 +10001950: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001954: bf04 itt eq +10001956: f851 3b04 ldreq.w r3, [r1], #4 +1000195a: 3004 addeq r0, #4 +1000195c: d0f4 beq.n 10001948 +1000195e: f1c2 0100 rsb r1, r2, #0 +10001962: ea02 0201 and.w r2, r2, r1 +10001966: fab2 f282 clz r2, r2 +1000196a: f1c2 021f rsb r2, r2, #31 +1000196e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10001972: 4770 bx lr + +10001974 <_fini>: +10001974: b5f8 push {r3, r4, r5, r6, r7, lr} +10001976: bf00 nop + +10001978 <__mutex_exit_veneer>: +10001978: f85f f000 ldr.w pc, [pc] @ 1000197c <__mutex_exit_veneer+0x4> +1000197c: 200001e5 .word 0x200001e5 + +10001980 <__mutex_try_enter_block_until_veneer>: +10001980: f85f f000 ldr.w pc, [pc] @ 10001984 <__mutex_try_enter_block_until_veneer+0x4> +10001984: 2000017d .word 0x2000017d + +10001988 <__pre_init_runtime_init_bootrom_reset>: +10001988: 100011c9 .... + +1000198c <__pre_init_runtime_init_early_resets>: +1000198c: 1000113d =... + +10001990 <__pre_init_runtime_init_usb_power_down>: +10001990: 10001171 q... + +10001994 <__pre_init_runtime_init_clocks>: +10001994: 1000125d ]... + +10001998 <__pre_init_runtime_init_post_clock_resets>: +10001998: 100011a9 .... + +1000199c <__pre_init_runtime_init_boot_locks_reset>: +1000199c: 100010c1 .... + +100019a0 <__pre_init_runtime_init_spin_locks_reset>: +100019a0: 100011f1 .... + +100019a4 <__pre_init_runtime_init_bootrom_locking_enable>: +100019a4: 100010ad .... + +100019a8 <__pre_init_runtime_init_mutex>: +100019a8: 100006d5 .... + +100019ac <__pre_init_runtime_init_install_ram_vector_table>: +100019ac: 100011f5 .... + +100019b0 <__pre_init_runtime_init_default_alarm_pool>: +100019b0: 10000a51 Q... + +100019b4 <__pre_init_first_per_core_initializer>: +100019b4: 1000110d .... + +100019b8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100019b8: 100011dd .... + +100019bc <__pre_init_runtime_init_per_core_enable_coprocessors>: +100019bc: 1000118d .... + +100019c0 <__pre_init_spinlock_set_extexclall>: +100019c0: 10000325 %... + +100019c4 <__pre_init_runtime_init_per_core_irq_priorities>: +100019c4: 1000034d M... + +100019c8 <__frame_dummy_init_array_entry>: +100019c8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 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b/WEEK01/0x0001_hello-world/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK01/0x0001_hello-world/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK01/0x0001_hello-world/pico_sdk_import.cmake b/WEEK01/0x0001_hello-world/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK01/0x0001_hello-world/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK01/0x0001a_stack/.gitignore b/WEEK01/0x0001a_stack/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK01/0x0001a_stack/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK01/0x0001a_stack/.vscode/c_cpp_properties.json b/WEEK01/0x0001a_stack/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..5a108f1 --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.3.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.3.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/15_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK01/0x0001a_stack/.vscode/cmake-kits.json b/WEEK01/0x0001a_stack/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK01/0x0001a_stack/.vscode/extensions.json b/WEEK01/0x0001a_stack/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK01/0x0001a_stack/.vscode/launch.json b/WEEK01/0x0001a_stack/.vscode/launch.json new file mode 100644 index 0000000..7078fb1 --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/launch.json @@ -0,0 +1,52 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + } + ] +} diff --git a/WEEK01/0x0001a_stack/.vscode/settings.json b/WEEK01/0x0001a_stack/.vscode/settings.json new file mode 100644 index 0000000..ecbf7dc --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/settings.json @@ -0,0 +1,46 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + }, + "variant": { + "statusBarVisibility": "hidden" + }, + "buildTarget": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.3.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.3.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v4.3.4/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.0/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.0/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.13.2/ninja" +} diff --git a/WEEK01/0x0001a_stack/.vscode/tasks.json b/WEEK01/0x0001a_stack/.vscode/tasks.json new file mode 100644 index 0000000..60f30f6 --- /dev/null +++ b/WEEK01/0x0001a_stack/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.13.2/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.3.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.3.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + } + ] +} diff --git a/WEEK01/0x0001a_stack/0x0001a_stack.c b/WEEK01/0x0001a_stack/0x0001a_stack.c new file mode 100644 index 0000000..5e1945d --- /dev/null +++ b/WEEK01/0x0001a_stack/0x0001a_stack.c @@ -0,0 +1,23 @@ +#include +#include "pico/stdlib.h" + + +int main() +{ + stdio_init_all(); + + while (true) { + __asm volatile( + // Save a low register and the link register. + "push {r4, lr}\n" + // Intentionally unordered: the encoded list is still r2, r3, r6. + "push {r3, r2, r6}\n" + // Thumb PUSH cannot encode high registers r8-r12. + "stmdb sp!, {r9, r10}\n" + // Restore each group in reverse order to return SP to its start. + "ldmia sp!, {r9, r10}\n" + "pop {r2, r3, r6}\n" + "pop {r4, lr}\n" + ::: "memory"); + } +} diff --git a/WEEK01/0x0001a_stack/CMakeLists.txt b/WEEK01/0x0001a_stack/CMakeLists.txt new file mode 100644 index 0000000..c1b84e7 --- /dev/null +++ b/WEEK01/0x0001a_stack/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.3.0) +set(toolchainVersion 15_2_Rel1) +set(picotoolVersion 2.3.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0001a_stack C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0001a_stack 0x0001a_stack.c ) + +pico_set_program_name(0x0001a_stack "0x0001a_stack") +pico_set_program_version(0x0001a_stack "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0001a_stack 1) +pico_enable_stdio_usb(0x0001a_stack 0) + +# Add the standard library to the build +target_link_libraries(0x0001a_stack + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0001a_stack PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0001a_stack) + diff --git a/WEEK01/0x0001a_stack/build/0x0001a_stack.bin b/WEEK01/0x0001a_stack/build/0x0001a_stack.bin new file mode 100755 index 0000000..737e212 Binary files /dev/null and b/WEEK01/0x0001a_stack/build/0x0001a_stack.bin differ diff --git a/WEEK01/0x0001a_stack/build/0x0001a_stack.dis b/WEEK01/0x0001a_stack/build/0x0001a_stack.dis new file mode 100644 index 0000000..48dface --- /dev/null +++ b/WEEK01/0x0001a_stack/build/0x0001a_stack.dis @@ -0,0 +1,2923 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001a_stack/build/0x0001a_stack.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00001920 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000138 10001920 10001920 00002920 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10001a58 10001a58 00002a58 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10001a60 10001a60 00002a60 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .psram_load 00000000 11000000 11000000 00003d88 2**0 + CONTENTS + 5 .psram_noload 00000000 11000000 11000000 00003d88 2**0 + CONTENTS + 6 .xip_ram 00000000 13ffc000 13ffc000 00003d88 2**0 + CONTENTS + 7 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 8 .uninitialized_data 00000000 20000110 20000110 00003d88 2**0 + CONTENTS + 9 .data 000002e8 20000110 10001a8c 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 10 .tdata 00000000 200003f8 200003f8 00003d88 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 11 .tbss 00000000 200003f8 200003f8 00000000 2**0 + ALLOC, THREAD_LOCAL + 12 .tbss_space 00000000 200003f8 200003f8 00003d88 2**0 + CONTENTS + 13 .bss 00000210 200003f8 10001d74 000043f8 2**3 + ALLOC + 14 .tls0 00000000 20000608 20000608 00003d88 2**0 + CONTENTS + 15 .tls1 00000000 20000608 20000608 00003d88 2**0 + CONTENTS + 16 .persistent_data 00000000 20000608 20000608 00003d88 2**0 + CONTENTS + 17 .dummy_pre_heap 00000000 20000608 20000608 00003d88 2**0 + CONTENTS + 18 .heap 00000800 20000608 20000608 00004000 2**2 + ALLOC, READONLY + 19 .scratch_x 00000000 20080000 20080000 00003d88 2**0 + CONTENTS + 20 .scratch_y 00000000 20081000 20081000 00003d88 2**0 + CONTENTS + 21 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 22 .flash_end 00000014 10001d74 10001d74 00003d74 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 23 .debug_info 00020a0d 00000000 00000000 00003d88 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_abbrev 000055c2 00000000 00000000 00024795 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_aranges 00000b20 00000000 00000000 00029d58 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 26 .debug_rnglists 00003062 00000000 00000000 0002a878 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 27 .debug_line 00015c93 00000000 00000000 0002d8da 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 28 .debug_str 00005cac 00000000 00000000 0004356d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 29 .comment 00000045 00000000 00000000 00049219 2**0 + CONTENTS, READONLY + 30 .ARM.attributes 00000036 00000000 00000000 0004925e 2**0 + CONTENTS, READONLY + 31 .debug_frame 00001eb4 00000000 00000000 00049294 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 32 .debug_loclists 00010056 00000000 00000000 0004b148 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 33 .debug_line_str 0000017b 00000000 00000000 0005b19e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001a_stack/build/0x0001a_stack.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015b .word 0x1000015b +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10001a60 .word 0x10001a60 +1000012c: 10001a8c .word 0x10001a8c +10000130: 1000019c .word 0x1000019c +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00001c3c .word 0x00001c3c +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: 2000 movs r0, #0 + +1000014e <_enter_vtable_in_r0>: +1000014e: 491e ldr r1, [pc, #120] @ (100001c8 ) +10000150: 6008 str r0, [r1, #0] +10000152: c806 ldmia r0!, {r1, r2} +10000154: f381 8808 msr MSP, r1 +10000158: 4710 bx r2 + +1000015a <_reset_handler>: +1000015a: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +1000015e: 6800 ldr r0, [r0, #0] +10000160: b108 cbz r0, 10000166 + +10000162 : +10000162: 2000 movs r0, #0 +10000164: e7f3 b.n 1000014e <_enter_vtable_in_r0> +10000166: a40d add r4, pc, #52 @ (adr r4, 1000019c ) +10000168: cc0e ldmia r4!, {r1, r2, r3} +1000016a: 2900 cmp r1, #0 +1000016c: d002 beq.n 10000174 +1000016e: f000 f812 bl 10000196 +10000172: e7f9 b.n 10000168 +10000174: 4915 ldr r1, [pc, #84] @ (100001cc ) +10000176: 4a16 ldr r2, [pc, #88] @ (100001d0 ) +10000178: 2000 movs r0, #0 +1000017a: e000 b.n 1000017e + +1000017c : +1000017c: c101 stmia r1!, {r0} + +1000017e : +1000017e: 4291 cmp r1, r2 +10000180: d1fc bne.n 1000017c + +10000182 : +10000182: 4914 ldr r1, [pc, #80] @ (100001d4 ) +10000184: 4788 blx r1 +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: be00 bkpt 0x0000 +10000190: e7fd b.n 1000018e + +10000192 : +10000192: c901 ldmia r1!, {r0} +10000194: c201 stmia r2!, {r0} + +10000196 : +10000196: 429a cmp r2, r3 +10000198: d3fb bcc.n 10000192 + +1000019a : +1000019a: 4770 bx lr + +1000019c : +1000019c: 10001a8c .word 0x10001a8c +100001a0: 20000110 .word 0x20000110 +100001a4: 200003f8 .word 0x200003f8 +100001a8: 10001d74 .word 0x10001d74 +100001ac: 20080000 .word 0x20080000 +100001b0: 20080000 .word 0x20080000 +100001b4: 10001d74 .word 0x10001d74 +100001b8: 20081000 .word 0x20081000 +100001bc: 20081000 .word 0x20081000 +100001c0: 00000000 .word 0x00000000 +100001c4: 4770 bx lr +100001c6: 0000 .short 0x0000 +100001c8: e000ed08 .word 0xe000ed08 +100001cc: 200003f8 .word 0x200003f8 +100001d0: 20000608 .word 0x20000608 +100001d4: 10001395 .word 0x10001395 +100001d8: 100001e1 .word 0x100001e1 +100001dc: 1000138d .word 0x1000138d + +100001e0
: +100001e0: b508 push {r3, lr} +100001e2: f001 f9d7 bl 10001594 +100001e6: b510 push {r4, lr} +100001e8: b44c push {r2, r3, r6} +100001ea: e92d 0600 stmdb sp!, {r9, sl} +100001ee: e8bd 0600 ldmia.w sp!, {r9, sl} +100001f2: bc4c pop {r2, r3, r6} +100001f4: e8bd 4010 ldmia.w sp!, {r4, lr} +100001f8: e7f5 b.n 100001e6 +100001fa: bf00 nop + +100001fc : +100001fc: f44f 7c80 mov.w ip, #256 @ 0x100 +10000200: 4b0c ldr r3, [pc, #48] @ (10000234 ) +10000202: b500 push {lr} +10000204: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000208: eb03 0380 add.w r3, r3, r0, lsl #2 +1000020c: 00c0 lsls r0, r0, #3 +1000020e: f082 0240 eor.w r2, r2, #64 @ 0x40 +10000212: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000216: f503 5e80 add.w lr, r3, #4096 @ 0x1000 +1000021a: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000021e: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000222: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000226: f8ce 2000 str.w r2, [lr] +1000022a: 6041 str r1, [r0, #4] +1000022c: f8c3 c000 str.w ip, [r3] +10000230: bd00 pop {pc} +10000232: bf00 nop +10000234: 40038004 .word 0x40038004 + +10000238 : +10000238: b40f push {r0, r1, r2, r3} +1000023a: b500 push {lr} +1000023c: 4808 ldr r0, [pc, #32] @ (10000260 ) +1000023e: b083 sub sp, #12 +10000240: f001 f9f0 bl 10001624 <__wrap_puts> +10000244: 9b04 ldr r3, [sp, #16] +10000246: b13b cbz r3, 10000258 +10000248: a905 add r1, sp, #20 +1000024a: 4618 mov r0, r3 +1000024c: 9101 str r1, [sp, #4] +1000024e: f001 f881 bl 10001354 +10000252: 4804 ldr r0, [pc, #16] @ (10000264 ) +10000254: f001 f9e6 bl 10001624 <__wrap_puts> +10000258: 2001 movs r0, #1 +1000025a: f001 f893 bl 10001384 <_exit> +1000025e: bf00 nop +10000260: 10001920 .word 0x10001920 +10000264: 10001930 .word 0x10001930 + +10000268 : +10000268: b570 push {r4, r5, r6, lr} +1000026a: 4616 mov r6, r2 +1000026c: f3ef 8410 mrs r4, PRIMASK +10000270: b672 cpsid i +10000272: f8df e048 ldr.w lr, [pc, #72] @ 100002bc +10000276: e8de 2fcf ldaexb r2, [lr] +1000027a: 2301 movs r3, #1 +1000027c: 2a00 cmp r2, #0 +1000027e: d1fa bne.n 10000276 +10000280: e8ce 3f42 strexb r2, r3, [lr] +10000284: 2a00 cmp r2, #0 +10000286: d1f6 bne.n 10000276 +10000288: f3bf 8f5f dmb sy +1000028c: 2301 movs r3, #1 +1000028e: f001 0c07 and.w ip, r1, #7 +10000292: 08ca lsrs r2, r1, #3 +10000294: fa03 f30c lsl.w r3, r3, ip +10000298: f810 c002 ldrb.w ip, [r0, r2] +1000029c: ea1c 0503 ands.w r5, ip, r3 +100002a0: d108 bne.n 100002b4 +100002a2: ea4c 0c03 orr.w ip, ip, r3 +100002a6: f800 c002 strb.w ip, [r0, r2] +100002aa: e8ce 5f8f stlb r5, [lr] +100002ae: f384 8810 msr PRIMASK, r4 +100002b2: bd70 pop {r4, r5, r6, pc} +100002b4: 4630 mov r0, r6 +100002b6: f7ff ffbf bl 10000238 +100002ba: bf00 nop +100002bc: 20000583 .word 0x20000583 + +100002c0 : +100002c0: 4a04 ldr r2, [pc, #16] @ (100002d4 ) +100002c2: 7810 ldrb r0, [r2, #0] +100002c4: 1c43 adds r3, r0, #1 +100002c6: b2db uxtb r3, r3 +100002c8: 2b18 cmp r3, #24 +100002ca: bf28 it cs +100002cc: 2310 movcs r3, #16 +100002ce: 7013 strb r3, [r2, #0] +100002d0: 4770 bx lr +100002d2: bf00 nop +100002d4: 20000368 .word 0x20000368 + +100002d8 : +100002d8: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100002dc: 6893 ldr r3, [r2, #8] +100002de: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100002e2: 6093 str r3, [r2, #8] +100002e4: 4770 bx lr +100002e6: bf00 nop + +100002e8 : +100002e8: 2100 movs r1, #0 +100002ea: 4b04 ldr r3, [pc, #16] @ (100002fc ) +100002ec: f103 0220 add.w r2, r3, #32 +100002f0: e8c3 1f8f stlb r1, [r3] +100002f4: 3301 adds r3, #1 +100002f6: 4293 cmp r3, r2 +100002f8: d1fa bne.n 100002f0 +100002fa: 4770 bx lr +100002fc: 20000578 .word 0x20000578 + +10000300 : +10000300: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000304: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000308: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +1000030c: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000310: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000314: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000318: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +1000031c: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000320: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000324: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000328: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000032c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000330: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000334: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000338: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000033c: b662 cpsie i +1000033e: 4770 bx lr + +10000340 : +10000340: 2301 movs r3, #1 +10000342: f000 021f and.w r2, r0, #31 +10000346: 4093 lsls r3, r2 +10000348: 0940 lsrs r0, r0, #5 +1000034a: b141 cbz r1, 1000035e +1000034c: 0080 lsls r0, r0, #2 +1000034e: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000352: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000356: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000035a: 6003 str r3, [r0, #0] +1000035c: 4770 bx lr +1000035e: 4a02 ldr r2, [pc, #8] @ (10000368 ) +10000360: 3020 adds r0, #32 +10000362: f842 3020 str.w r3, [r2, r0, lsl #2] +10000366: 4770 bx lr +10000368: e000e100 .word 0xe000e100 + +1000036c : +1000036c: b508 push {r3, lr} +1000036e: f3ef 8e10 mrs lr, PRIMASK +10000372: b672 cpsid i +10000374: 4b13 ldr r3, [pc, #76] @ (100003c4 ) +10000376: e8d3 cfcf ldaexb ip, [r3] +1000037a: 2201 movs r2, #1 +1000037c: f1bc 0f00 cmp.w ip, #0 +10000380: d1f9 bne.n 10000376 +10000382: e8c3 2f4c strexb ip, r2, [r3] +10000386: f1bc 0f00 cmp.w ip, #0 +1000038a: d1f4 bne.n 10000376 +1000038c: f3bf 8f5f dmb sy +10000390: 4a0d ldr r2, [pc, #52] @ (100003c8 ) +10000392: 3010 adds r0, #16 +10000394: 6892 ldr r2, [r2, #8] +10000396: f8df c034 ldr.w ip, [pc, #52] @ 100003cc +1000039a: f852 2020 ldr.w r2, [r2, r0, lsl #2] +1000039e: 4562 cmp r2, ip +100003a0: d001 beq.n 100003a6 +100003a2: 4291 cmp r1, r2 +100003a4: d10b bne.n 100003be +100003a6: 4a08 ldr r2, [pc, #32] @ (100003c8 ) +100003a8: 6892 ldr r2, [r2, #8] +100003aa: f842 1020 str.w r1, [r2, r0, lsl #2] +100003ae: f3bf 8f5f dmb sy +100003b2: 2200 movs r2, #0 +100003b4: e8c3 2f8f stlb r2, [r3] +100003b8: f38e 8810 msr PRIMASK, lr +100003bc: bd08 pop {r3, pc} +100003be: f000 feb5 bl 1000112c +100003c2: bf00 nop +100003c4: 20000581 .word 0x20000581 +100003c8: e000ed00 .word 0xe000ed00 +100003cc: 10000111 .word 0x10000111 + +100003d0 : +100003d0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100003d4: b082 sub sp, #8 +100003d6: f3ef 8510 mrs r5, PRIMASK +100003da: b672 cpsid i +100003dc: f8df c1a8 ldr.w ip, [pc, #424] @ 10000588 +100003e0: e8dc 2fcf ldaexb r2, [ip] +100003e4: 2301 movs r3, #1 +100003e6: 2a00 cmp r2, #0 +100003e8: d1fa bne.n 100003e0 +100003ea: e8cc 3f42 strexb r2, r3, [ip] +100003ee: 2a00 cmp r2, #0 +100003f0: d1f6 bne.n 100003e0 +100003f2: f3bf 8f5f dmb sy +100003f6: 4b5e ldr r3, [pc, #376] @ (10000570 ) +100003f8: f100 0410 add.w r4, r0, #16 +100003fc: 689b ldr r3, [r3, #8] +100003fe: f853 2024 ldr.w r2, [r3, r4, lsl #2] +10000402: 4b5c ldr r3, [pc, #368] @ (10000574 ) +10000404: 429a cmp r2, r3 +10000406: d03d beq.n 10000484 +10000408: 428a cmp r2, r1 +1000040a: d049 beq.n 100004a0 +1000040c: f8df e17c ldr.w lr, [pc, #380] @ 1000058c +10000410: eba2 030e sub.w r3, r2, lr +10000414: 2b2f cmp r3, #47 @ 0x2f +10000416: d835 bhi.n 10000484 +10000418: 2701 movs r7, #1 +1000041a: 0943 lsrs r3, r0, #5 +1000041c: 009b lsls r3, r3, #2 +1000041e: f000 001f and.w r0, r0, #31 +10000422: f103 4360 add.w r3, r3, #3758096384 @ 0xe0000000 +10000426: f503 4361 add.w r3, r3, #57600 @ 0xe100 +1000042a: 4087 lsls r7, r0 +1000042c: 681e ldr r6, [r3, #0] +1000042e: 469a mov sl, r3 +10000430: 46b9 mov r9, r7 +10000432: f8c3 7080 str.w r7, [r3, #128] @ 0x80 +10000436: f3bf 8f5f dmb sy +1000043a: f3ef 8305 mrs r3, IPSR +1000043e: b2db uxtb r3, r3 +10000440: 461f mov r7, r3 +10000442: bb7b cbnz r3, 100004a4 +10000444: 2301 movs r3, #1 +10000446: 4083 lsls r3, r0 +10000448: f022 0001 bic.w r0, r2, #1 +1000044c: ea03 0806 and.w r8, r3, r6 +10000450: 6886 ldr r6, [r0, #8] +10000452: 42b1 cmp r1, r6 +10000454: d108 bne.n 10000468 +10000456: e081 b.n 1000055c +10000458: eb03 0343 add.w r3, r3, r3, lsl #1 +1000045c: eb0e 0383 add.w r3, lr, r3, lsl #2 +10000460: 689e ldr r6, [r3, #8] +10000462: 42b1 cmp r1, r6 +10000464: d025 beq.n 100004b2 +10000466: 4618 mov r0, r3 +10000468: f990 3006 ldrsb.w r3, [r0, #6] +1000046c: 2b00 cmp r3, #0 +1000046e: daf3 bge.n 10000458 +10000470: 42b1 cmp r1, r6 +10000472: d04e beq.n 10000512 +10000474: 4653 mov r3, sl +10000476: f1b8 0f00 cmp.w r8, #0 +1000047a: d017 beq.n 100004ac +1000047c: f8c3 9180 str.w r9, [r3, #384] @ 0x180 +10000480: f8c3 9000 str.w r9, [r3] +10000484: 4b3a ldr r3, [pc, #232] @ (10000570 ) +10000486: 689b ldr r3, [r3, #8] +10000488: f843 2024 str.w r2, [r3, r4, lsl #2] +1000048c: f3bf 8f5f dmb sy +10000490: 2300 movs r3, #0 +10000492: e8cc 3f8f stlb r3, [ip] +10000496: f385 8810 msr PRIMASK, r5 +1000049a: b002 add sp, #8 +1000049c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100004a0: 461a mov r2, r3 +100004a2: e7ef b.n 10000484 +100004a4: 429c cmp r4, r3 +100004a6: d0cd beq.n 10000444 +100004a8: f000 fe40 bl 1000112c +100004ac: f8c3 9080 str.w r9, [r3, #128] @ 0x80 +100004b0: e7e8 b.n 10000484 +100004b2: f993 6006 ldrsb.w r6, [r3, #6] +100004b6: 2e00 cmp r6, #0 +100004b8: db2c blt.n 10000514 +100004ba: eb06 0046 add.w r0, r6, r6, lsl #1 +100004be: eb0e 0180 add.w r1, lr, r0, lsl #2 +100004c2: 0080 lsls r0, r0, #2 +100004c4: 9001 str r0, [sp, #4] +100004c6: 79c8 ldrb r0, [r1, #7] +100004c8: 688f ldr r7, [r1, #8] +100004ca: 71d8 strb r0, [r3, #7] +100004cc: f991 0006 ldrsb.w r0, [r1, #6] +100004d0: 609f str r7, [r3, #8] +100004d2: 2800 cmp r0, #0 +100004d4: 7198 strb r0, [r3, #6] +100004d6: ea4f 0746 mov.w r7, r6, lsl #1 +100004da: db2e blt.n 1000053a +100004dc: 8889 ldrh r1, [r1, #4] +100004de: 9801 ldr r0, [sp, #4] +100004e0: f341 010a sbfx r1, r1, #0, #11 +100004e4: eb00 0141 add.w r1, r0, r1, lsl #1 +100004e8: f06f 0007 mvn.w r0, #7 +100004ec: 3108 adds r1, #8 +100004ee: 4471 add r1, lr +100004f0: 1ac0 subs r0, r0, r3 +100004f2: 4401 add r1, r0 +100004f4: f3c1 014a ubfx r1, r1, #1, #11 +100004f8: ea6f 41c1 mvn.w r1, r1, lsl #19 +100004fc: ea6f 41d1 mvn.w r1, r1, lsr #19 +10000500: 8099 strh r1, [r3, #4] +10000502: 491d ldr r1, [pc, #116] @ (10000578 ) +10000504: 19bb adds r3, r7, r6 +10000506: 7808 ldrb r0, [r1, #0] +10000508: eb0e 0383 add.w r3, lr, r3, lsl #2 +1000050c: 700e strb r6, [r1, #0] +1000050e: 7198 strb r0, [r3, #6] +10000510: e7b0 b.n 10000474 +10000512: 4603 mov r3, r0 +10000514: b99f cbnz r7, 1000053e +10000516: 21ff movs r1, #255 @ 0xff +10000518: 7181 strb r1, [r0, #6] +1000051a: f64b 5101 movw r1, #48385 @ 0xbd01 +1000051e: 8081 strh r1, [r0, #4] +10000520: 4e15 ldr r6, [pc, #84] @ (10000578 ) +10000522: 4618 mov r0, r3 +10000524: 7837 ldrb r7, [r6, #0] +10000526: f64a 21aa movw r1, #43690 @ 0xaaaa +1000052a: 719f strb r7, [r3, #6] +1000052c: 4673 mov r3, lr +1000052e: 1ac0 subs r0, r0, r3 +10000530: 4140 adcs r0, r0 +10000532: 4341 muls r1, r0 +10000534: 0d09 lsrs r1, r1, #20 +10000536: 7031 strb r1, [r6, #0] +10000538: e79c b.n 10000474 +1000053a: 4910 ldr r1, [pc, #64] @ (1000057c ) +1000053c: e7e0 b.n 10000500 +1000053e: 4910 ldr r1, [pc, #64] @ (10000580 ) +10000540: 4e10 ldr r6, [pc, #64] @ (10000584 ) +10000542: 1ac9 subs r1, r1, r3 +10000544: 3908 subs r1, #8 +10000546: f3c1 300a ubfx r0, r1, #12, #11 +1000054a: ea6f 5000 mvn.w r0, r0, lsl #20 +1000054e: ea6f 5010 mvn.w r0, r0, lsr #20 +10000552: ea46 0151 orr.w r1, r6, r1, lsr #1 +10000556: 80d9 strh r1, [r3, #6] +10000558: 8098 strh r0, [r3, #4] +1000055a: e78b b.n 10000474 +1000055c: f990 6006 ldrsb.w r6, [r0, #6] +10000560: 4603 mov r3, r0 +10000562: 2e00 cmp r6, #0 +10000564: daa9 bge.n 100004ba +10000566: 2f00 cmp r7, #0 +10000568: d1e9 bne.n 1000053e +1000056a: 4a02 ldr r2, [pc, #8] @ (10000574 ) +1000056c: e7d8 b.n 10000520 +1000056e: bf00 nop +10000570: e000ed00 .word 0xe000ed00 +10000574: 10000111 .word 0x10000111 +10000578: 20000604 .word 0x20000604 +1000057c: ffffbd01 .word 0xffffbd01 +10000580: 200003a6 .word 0x200003a6 +10000584: fffff800 .word 0xfffff800 +10000588: 20000581 .word 0x20000581 +1000058c: 2000036c .word 0x2000036c + +10000590 : +10000590: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000594: f3ef 8305 mrs r3, IPSR +10000598: b2db uxtb r3, r3 +1000059a: 469e mov lr, r3 +1000059c: f3ef 8510 mrs r5, PRIMASK +100005a0: b672 cpsid i +100005a2: 4929 ldr r1, [pc, #164] @ (10000648 ) +100005a4: e8d1 2fcf ldaexb r2, [r1] +100005a8: 2301 movs r3, #1 +100005aa: 2a00 cmp r2, #0 +100005ac: d1fa bne.n 100005a4 +100005ae: e8c1 3f42 strexb r2, r3, [r1] +100005b2: 2a00 cmp r2, #0 +100005b4: d1f6 bne.n 100005a4 +100005b6: f3bf 8f5f dmb sy +100005ba: f8df 809c ldr.w r8, [pc, #156] @ 10000658 +100005be: f040 0601 orr.w r6, r0, #1 +100005c2: f8d8 7008 ldr.w r7, [r8, #8] +100005c6: f64a 23aa movw r3, #43690 @ 0xaaaa +100005ca: f857 702e ldr.w r7, [r7, lr, lsl #2] +100005ce: 4604 mov r4, r0 +100005d0: 4a1e ldr r2, [pc, #120] @ (1000064c ) +100005d2: 1aa4 subs r4, r4, r2 +100005d4: 4164 adcs r4, r4 +100005d6: 4363 muls r3, r4 +100005d8: 0d1b lsrs r3, r3, #20 +100005da: 42b7 cmp r7, r6 +100005dc: b25b sxtb r3, r3 +100005de: d01e beq.n 1000061e +100005e0: f992 4006 ldrsb.w r4, [r2, #6] +100005e4: 429c cmp r4, r3 +100005e6: d020 beq.n 1000062a +100005e8: f992 4012 ldrsb.w r4, [r2, #18] +100005ec: 429c cmp r4, r3 +100005ee: d027 beq.n 10000640 +100005f0: f992 401e ldrsb.w r4, [r2, #30] +100005f4: 429c cmp r4, r3 +100005f6: d025 beq.n 10000644 +100005f8: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100005fc: 429c cmp r4, r3 +100005fe: bf08 it eq +10000600: 2403 moveq r4, #3 +10000602: d013 beq.n 1000062c +10000604: 4a12 ldr r2, [pc, #72] @ (10000650 ) +10000606: 2400 movs r4, #0 +10000608: f892 c000 ldrb.w ip, [r2] +1000060c: 7013 strb r3, [r2, #0] +1000060e: f880 c006 strb.w ip, [r0, #6] +10000612: e8c1 4f8f stlb r4, [r1] +10000616: f385 8810 msr PRIMASK, r5 +1000061a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000061e: f8d8 2008 ldr.w r2, [r8, #8] +10000622: 4c0c ldr r4, [pc, #48] @ (10000654 ) +10000624: f842 402e str.w r4, [r2, lr, lsl #2] +10000628: e7ec b.n 10000604 +1000062a: 2400 movs r4, #0 +1000062c: eb04 0444 add.w r4, r4, r4, lsl #1 +10000630: eb02 0284 add.w r2, r2, r4, lsl #2 +10000634: 24ff movs r4, #255 @ 0xff +10000636: 7194 strb r4, [r2, #6] +10000638: f64b 5401 movw r4, #48385 @ 0xbd01 +1000063c: 8094 strh r4, [r2, #4] +1000063e: e7e1 b.n 10000604 +10000640: 2401 movs r4, #1 +10000642: e7f3 b.n 1000062c +10000644: 2402 movs r4, #2 +10000646: e7f1 b.n 1000062c +10000648: 20000581 .word 0x20000581 +1000064c: 2000036c .word 0x2000036c +10000650: 20000604 .word 0x20000604 +10000654: 10000111 .word 0x10000111 +10000658: e000ed00 .word 0xe000ed00 + +1000065c : +1000065c: 4b01 ldr r3, [pc, #4] @ (10000664 ) +1000065e: 440b add r3, r1 +10000660: 6003 str r3, [r0, #0] +10000662: 4770 bx lr +10000664: 20000578 .word 0x20000578 + +10000668 : +10000668: b570 push {r4, r5, r6, lr} +1000066a: 4c10 ldr r4, [pc, #64] @ (100006ac ) +1000066c: 4d10 ldr r5, [pc, #64] @ (100006b0 ) +1000066e: 42ac cmp r4, r5 +10000670: d20e bcs.n 10000690 +10000672: 26ff movs r6, #255 @ 0xff +10000674: 6823 ldr r3, [r4, #0] +10000676: b163 cbz r3, 10000692 +10000678: f7ff fe22 bl 100002c0 +1000067c: 4601 mov r1, r0 +1000067e: 4620 mov r0, r4 +10000680: f7ff ffec bl 1000065c +10000684: 80a6 strh r6, [r4, #4] +10000686: f3bf 8f5f dmb sy +1000068a: 3408 adds r4, #8 +1000068c: 42ac cmp r4, r5 +1000068e: d3f1 bcc.n 10000674 +10000690: bd70 pop {r4, r5, r6, pc} +10000692: f7ff fe15 bl 100002c0 +10000696: 4601 mov r1, r0 +10000698: 4620 mov r0, r4 +1000069a: f7ff ffdf bl 1000065c +1000069e: 7126 strb r6, [r4, #4] +100006a0: f3bf 8f5f dmb sy +100006a4: 3408 adds r4, #8 +100006a6: 42ac cmp r4, r5 +100006a8: d3e4 bcc.n 10000674 +100006aa: bd70 pop {r4, r5, r6, pc} +100006ac: 200003f0 .word 0x200003f0 +100006b0: 200003f8 .word 0x200003f8 + +100006b4 : +100006b4: 4910 ldr r1, [pc, #64] @ (100006f8 ) +100006b6: 680b ldr r3, [r1, #0] +100006b8: f3ef 8010 mrs r0, PRIMASK +100006bc: b672 cpsid i +100006be: e8d3 cfcf ldaexb ip, [r3] +100006c2: 2201 movs r2, #1 +100006c4: f1bc 0f00 cmp.w ip, #0 +100006c8: d1f9 bne.n 100006be +100006ca: e8c3 2f4c strexb ip, r2, [r3] +100006ce: f1bc 0f00 cmp.w ip, #0 +100006d2: d1f4 bne.n 100006be +100006d4: f3bf 8f5f dmb sy +100006d8: 4a08 ldr r2, [pc, #32] @ (100006fc ) +100006da: f04f 0c00 mov.w ip, #0 +100006de: 7813 ldrb r3, [r2, #0] +100006e0: 6809 ldr r1, [r1, #0] +100006e2: 3301 adds r3, #1 +100006e4: 7013 strb r3, [r2, #0] +100006e6: e8c1 cf8f stlb ip, [r1] +100006ea: f380 8810 msr PRIMASK, r0 +100006ee: bf40 sev +100006f0: 2000 movs r0, #0 +100006f2: 2100 movs r1, #0 +100006f4: 4770 bx lr +100006f6: bf00 nop +100006f8: 200005f8 .word 0x200005f8 +100006fc: 20000605 .word 0x20000605 + +10000700 : +10000700: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000704: ed2d 8b02 vpush {d8} +10000708: b085 sub sp, #20 +1000070a: f3ef 8305 mrs r3, IPSR +1000070e: b2db uxtb r3, r3 +10000710: 3b10 subs r3, #16 +10000712: 089a lsrs r2, r3, #2 +10000714: bf18 it ne +10000716: 2201 movne r2, #1 +10000718: f04f 0101 mov.w r1, #1 +1000071c: f003 0b03 and.w fp, r3, #3 +10000720: bf18 it ne +10000722: 4ca9 ldrne r4, [pc, #676] @ (100009c8 ) +10000724: 4ba9 ldr r3, [pc, #676] @ (100009cc ) +10000726: bf08 it eq +10000728: 4ca9 ldreq r4, [pc, #676] @ (100009d0 ) +1000072a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000072e: f853 5022 ldr.w r5, [r3, r2, lsl #2] +10000732: fa01 f20b lsl.w r2, r1, fp +10000736: f504 5341 add.w r3, r4, #12352 @ 0x3040 +1000073a: ed9f 8ba1 vldr d8, [pc, #644] @ 100009c0 +1000073e: 9202 str r2, [sp, #8] +10000740: 605a str r2, [r3, #4] +10000742: e02f b.n 100007a4 +10000744: 88ab ldrh r3, [r5, #4] +10000746: 0419 lsls r1, r3, #16 +10000748: f140 8094 bpl.w 10000874 +1000074c: 79ab ldrb r3, [r5, #6] +1000074e: 2b00 cmp r3, #0 +10000750: f040 80de bne.w 10000910 +10000754: f9b5 6008 ldrsh.w r6, [r5, #8] +10000758: 2e00 cmp r6, #0 +1000075a: f2c0 811c blt.w 10000996 +1000075e: 696b ldr r3, [r5, #20] +10000760: eb06 0646 add.w r6, r6, r6, lsl #1 +10000764: eb03 03c6 add.w r3, r3, r6, lsl #3 +10000768: e9d3 6702 ldrd r6, r7, [r3, #8] +1000076c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000770: bf08 it eq +10000772: f1b6 3fff cmpeq.w r6, #4294967295 @ 0xffffffff +10000776: d00e beq.n 10000796 +10000778: eb04 018b add.w r1, r4, fp, lsl #2 +1000077c: 6aa3 ldr r3, [r4, #40] @ 0x28 +1000077e: 690a ldr r2, [r1, #16] +10000780: 1ad2 subs r2, r2, r3 +10000782: 1af3 subs r3, r6, r3 +10000784: 4293 cmp r3, r2 +10000786: d305 bcc.n 10000794 +10000788: 2301 movs r3, #1 +1000078a: 6a22 ldr r2, [r4, #32] +1000078c: fa03 f30b lsl.w r3, r3, fp +10000790: 4213 tst r3, r2 +10000792: d100 bne.n 10000796 +10000794: 610e str r6, [r1, #16] +10000796: 4620 mov r0, r4 +10000798: f000 fafa bl 10000d90 +1000079c: 42b0 cmp r0, r6 +1000079e: 41b9 sbcs r1, r7 +100007a0: f2c0 80f9 blt.w 10000996 +100007a4: f9b5 6008 ldrsh.w r6, [r5, #8] +100007a8: 9b02 ldr r3, [sp, #8] +100007aa: 2e00 cmp r6, #0 +100007ac: 63e3 str r3, [r4, #60] @ 0x3c +100007ae: dbc9 blt.n 10000744 +100007b0: f8d5 9014 ldr.w r9, [r5, #20] +100007b4: eb06 0a46 add.w sl, r6, r6, lsl #1 +100007b8: eb09 07ca add.w r7, r9, sl, lsl #3 +100007bc: 68bb ldr r3, [r7, #8] +100007be: 4620 mov r0, r4 +100007c0: f8d7 800c ldr.w r8, [r7, #12] +100007c4: 9301 str r3, [sp, #4] +100007c6: f000 fae3 bl 10000d90 +100007ca: 9b01 ldr r3, [sp, #4] +100007cc: 4298 cmp r0, r3 +100007ce: eb71 0108 sbcs.w r1, r1, r8 +100007d2: dbb7 blt.n 10000744 +100007d4: f1b8 0f00 cmp.w r8, #0 +100007d8: f2c0 80c0 blt.w 1000095c +100007dc: e9d7 3104 ldrd r3, r1, [r7, #16] +100007e0: 4a7c ldr r2, [pc, #496] @ (100009d4 ) +100007e2: 4293 cmp r3, r2 +100007e4: f000 80f8 beq.w 100009d8 +100007e8: 887a ldrh r2, [r7, #2] +100007ea: f9b5 0008 ldrsh.w r0, [r5, #8] +100007ee: b292 uxth r2, r2 +100007f0: ea42 4000 orr.w r0, r2, r0, lsl #16 +100007f4: 4798 blx r3 +100007f6: 4602 mov r2, r0 +100007f8: 460b mov r3, r1 +100007fa: ea52 0103 orrs.w r1, r2, r3 +100007fe: f000 80ad beq.w 1000095c +10000802: 2b00 cmp r3, #0 +10000804: f280 80cd bge.w 100009a2 +10000808: 9901 ldr r1, [sp, #4] +1000080a: ebb1 0e02 subs.w lr, r1, r2 +1000080e: eb68 0803 sbc.w r8, r8, r3 +10000812: f939 303a ldrsh.w r3, [r9, sl, lsl #3] +10000816: e9c7 e802 strd lr, r8, [r7, #8] +1000081a: 2b00 cmp r3, #0 +1000081c: db92 blt.n 10000744 +1000081e: 6968 ldr r0, [r5, #20] +10000820: eb03 0243 add.w r2, r3, r3, lsl #1 +10000824: eb00 02c2 add.w r2, r0, r2, lsl #3 +10000828: e9d2 7102 ldrd r7, r1, [r2, #8] +1000082c: 45be cmp lr, r7 +1000082e: eb78 0c01 sbcs.w ip, r8, r1 +10000832: ea4f 0243 mov.w r2, r3, lsl #1 +10000836: db85 blt.n 10000744 +10000838: 46ac mov ip, r5 +1000083a: f82c 3f08 strh.w r3, [ip, #8]! +1000083e: e006 b.n 1000084e +10000840: eb03 0143 add.w r1, r3, r3, lsl #1 +10000844: eb00 01c1 add.w r1, r0, r1, lsl #3 +10000848: 005a lsls r2, r3, #1 +1000084a: e9d1 7102 ldrd r7, r1, [r1, #8] +1000084e: 45be cmp lr, r7 +10000850: eb78 0101 sbcs.w r1, r8, r1 +10000854: 441a add r2, r3 +10000856: db05 blt.n 10000864 +10000858: f930 3032 ldrsh.w r3, [r0, r2, lsl #3] +1000085c: eb00 0cc2 add.w ip, r0, r2, lsl #3 +10000860: 2b00 cmp r3, #0 +10000862: daed bge.n 10000840 +10000864: f829 303a strh.w r3, [r9, sl, lsl #3] +10000868: f8ac 6000 strh.w r6, [ip] +1000086c: 88ab ldrh r3, [r5, #4] +1000086e: 0419 lsls r1, r3, #16 +10000870: f53f af6c bmi.w 1000074c +10000874: 692b ldr r3, [r5, #16] +10000876: f3ef 8210 mrs r2, PRIMASK +1000087a: b672 cpsid i +1000087c: e8d3 0fcf ldaexb r0, [r3] +10000880: 2101 movs r1, #1 +10000882: 2800 cmp r0, #0 +10000884: d1fa bne.n 1000087c +10000886: e8c3 1f40 strexb r0, r1, [r3] +1000088a: 2800 cmp r0, #0 +1000088c: d1f6 bne.n 1000087c +1000088e: f3bf 8f5f dmb sy +10000892: f64f 76ff movw r6, #65535 @ 0xffff +10000896: 88a8 ldrh r0, [r5, #4] +10000898: 2300 movs r3, #0 +1000089a: 6929 ldr r1, [r5, #16] +1000089c: b200 sxth r0, r0 +1000089e: 80ae strh r6, [r5, #4] +100008a0: e8c1 3f8f stlb r3, [r1] +100008a4: f382 8810 msr PRIMASK, r2 +100008a8: 4298 cmp r0, r3 +100008aa: f6ff af4f blt.w 1000074c +100008ae: 4607 mov r7, r0 +100008b0: 46a1 mov r9, r4 +100008b2: 696e ldr r6, [r5, #20] +100008b4: f105 0808 add.w r8, r5, #8 +100008b8: f9b5 3008 ldrsh.w r3, [r5, #8] +100008bc: eb07 0e47 add.w lr, r7, r7, lsl #1 +100008c0: 2b00 cmp r3, #0 +100008c2: 46c4 mov ip, r8 +100008c4: eb06 02ce add.w r2, r6, lr, lsl #3 +100008c8: db15 blt.n 100008f6 +100008ca: e9d2 4002 ldrd r4, r0, [r2, #8] +100008ce: 46aa mov sl, r5 +100008d0: 9701 str r7, [sp, #4] +100008d2: e004 b.n 100008de +100008d4: f936 3035 ldrsh.w r3, [r6, r5, lsl #3] +100008d8: 4694 mov ip, r2 +100008da: 2b00 cmp r3, #0 +100008dc: db09 blt.n 100008f2 +100008de: eb03 0543 add.w r5, r3, r3, lsl #1 +100008e2: eb06 02c5 add.w r2, r6, r5, lsl #3 +100008e6: e9d2 7102 ldrd r7, r1, [r2, #8] +100008ea: 42bc cmp r4, r7 +100008ec: eb70 0101 sbcs.w r1, r0, r1 +100008f0: daf0 bge.n 100008d4 +100008f2: 4655 mov r5, sl +100008f4: 9f01 ldr r7, [sp, #4] +100008f6: f8ac 7000 strh.w r7, [ip] +100008fa: f936 703e ldrsh.w r7, [r6, lr, lsl #3] +100008fe: f826 303e strh.w r3, [r6, lr, lsl #3] +10000902: 2f00 cmp r7, #0 +10000904: dad8 bge.n 100008b8 +10000906: 79ab ldrb r3, [r5, #6] +10000908: 464c mov r4, r9 +1000090a: 2b00 cmp r3, #0 +1000090c: f43f af22 beq.w 10000754 +10000910: 2300 movs r3, #0 +10000912: 71ab strb r3, [r5, #6] +10000914: f9b5 6008 ldrsh.w r6, [r5, #8] +10000918: 1c72 adds r2, r6, #1 +1000091a: 4633 mov r3, r6 +1000091c: d03b beq.n 10000996 +1000091e: 6968 ldr r0, [r5, #20] +10000920: f105 0e08 add.w lr, r5, #8 +10000924: e003 b.n 1000092e +10000926: 468e mov lr, r1 +10000928: 1c5a adds r2, r3, #1 +1000092a: f43f af15 beq.w 10000758 +1000092e: eb03 0243 add.w r2, r3, r3, lsl #1 +10000932: eb00 01c2 add.w r1, r0, r2, lsl #3 +10000936: 884f ldrh r7, [r1, #2] +10000938: 469c mov ip, r3 +1000093a: 043f lsls r7, r7, #16 +1000093c: f930 3032 ldrsh.w r3, [r0, r2, lsl #3] +10000940: d5f1 bpl.n 10000926 +10000942: 4566 cmp r6, ip +10000944: ed81 8b02 vstr d8, [r1, #8] +10000948: d0ee beq.n 10000928 +1000094a: f8ae 3000 strh.w r3, [lr] +1000094e: 8929 ldrh r1, [r5, #8] +10000950: 4666 mov r6, ip +10000952: f820 1032 strh.w r1, [r0, r2, lsl #3] +10000956: f8a5 c008 strh.w ip, [r5, #8] +1000095a: e7e5 b.n 10000928 +1000095c: f839 303a ldrh.w r3, [r9, sl, lsl #3] +10000960: 812b strh r3, [r5, #8] +10000962: 692b ldr r3, [r5, #16] +10000964: f3ef 8210 mrs r2, PRIMASK +10000968: b672 cpsid i +1000096a: e8d3 0fcf ldaexb r0, [r3] +1000096e: 2101 movs r1, #1 +10000970: 2800 cmp r0, #0 +10000972: d1fa bne.n 1000096a +10000974: e8c3 1f40 strexb r0, r1, [r3] +10000978: 2800 cmp r0, #0 +1000097a: d1f6 bne.n 1000096a +1000097c: f3bf 8f5f dmb sy +10000980: 886b ldrh r3, [r5, #2] +10000982: 6929 ldr r1, [r5, #16] +10000984: f829 303a strh.w r3, [r9, sl, lsl #3] +10000988: 2300 movs r3, #0 +1000098a: 806e strh r6, [r5, #2] +1000098c: e8c1 3f8f stlb r3, [r1] +10000990: f382 8810 msr PRIMASK, r2 +10000994: e6d6 b.n 10000744 +10000996: bf40 sev +10000998: b005 add sp, #20 +1000099a: ecbd 8b02 vpop {d8} +1000099e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100009a2: 4620 mov r0, r4 +100009a4: 9303 str r3, [sp, #12] +100009a6: 9201 str r2, [sp, #4] +100009a8: f000 f9f2 bl 10000d90 +100009ac: 9a01 ldr r2, [sp, #4] +100009ae: 9b03 ldr r3, [sp, #12] +100009b0: eb10 0e02 adds.w lr, r0, r2 +100009b4: eb43 0801 adc.w r8, r3, r1 +100009b8: e72b b.n 10000812 +100009ba: bf00 nop +100009bc: f3af 8000 nop.w +100009c0: ffffffff .word 0xffffffff +100009c4: ffffffff .word 0xffffffff +100009c8: 400b8000 .word 0x400b8000 +100009cc: 200005d8 .word 0x200005d8 +100009d0: 400b0000 .word 0x400b0000 +100009d4: 10000701 .word 0x10000701 +100009d8: 4608 mov r0, r1 +100009da: 690b ldr r3, [r1, #16] +100009dc: 9103 str r1, [sp, #12] +100009de: 4798 blx r3 +100009e0: 2800 cmp r0, #0 +100009e2: d0bb beq.n 1000095c +100009e4: 9903 ldr r1, [sp, #12] +100009e6: e9d1 2300 ldrd r2, r3, [r1] +100009ea: e706 b.n 100007fa + +100009ec : +100009ec: b538 push {r3, r4, r5, lr} +100009ee: 4b38 ldr r3, [pc, #224] @ (10000ad0 ) +100009f0: 691c ldr r4, [r3, #16] +100009f2: b12c cbz r4, 10000a00 +100009f4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} +100009f8: 210a movs r1, #10 +100009fa: 4836 ldr r0, [pc, #216] @ (10000ad4 ) +100009fc: f7ff be2e b.w 1000065c +10000a00: 2103 movs r1, #3 +10000a02: 4835 ldr r0, [pc, #212] @ (10000ad8 ) +10000a04: f000 f9b2 bl 10000d6c +10000a08: 4d33 ldr r5, [pc, #204] @ (10000ad8 ) +10000a0a: 4b31 ldr r3, [pc, #196] @ (10000ad0 ) +10000a0c: 60dd str r5, [r3, #12] +10000a0e: f7ff fc57 bl 100002c0 +10000a12: 4a32 ldr r2, [pc, #200] @ (10000adc ) +10000a14: f04f 4e50 mov.w lr, #3489660928 @ 0xd0000000 +10000a18: 4402 add r2, r0 +10000a1a: 2003 movs r0, #3 +10000a1c: 4b2c ldr r3, [pc, #176] @ (10000ad0 ) +10000a1e: f04f 0c0f mov.w ip, #15 +10000a22: 7018 strb r0, [r3, #0] +10000a24: 611a str r2, [r3, #16] +10000a26: f8de 2000 ldr.w r2, [lr] +10000a2a: f64f 71ff movw r1, #65535 @ 0xffff +10000a2e: 705a strb r2, [r3, #1] +10000a30: 695a ldr r2, [r3, #20] +10000a32: f8a3 c002 strh.w ip, [r3, #2] +10000a36: 8314 strh r4, [r2, #24] +10000a38: f04f 0402 mov.w r4, #2 +10000a3c: f8a2 4048 strh.w r4, [r2, #72] @ 0x48 +10000a40: f04f 0404 mov.w r4, #4 +10000a44: f8a2 4078 strh.w r4, [r2, #120] @ 0x78 +10000a48: f04f 0405 mov.w r4, #5 +10000a4c: f8a2 4090 strh.w r4, [r2, #144] @ 0x90 +10000a50: f04f 0406 mov.w r4, #6 +10000a54: f8a2 40a8 strh.w r4, [r2, #168] @ 0xa8 +10000a58: f04f 0407 mov.w r4, #7 +10000a5c: f8a2 40c0 strh.w r4, [r2, #192] @ 0xc0 +10000a60: f04f 0409 mov.w r4, #9 +10000a64: f8a2 40f0 strh.w r4, [r2, #240] @ 0xf0 +10000a68: f04f 040a mov.w r4, #10 +10000a6c: f8a2 4108 strh.w r4, [r2, #264] @ 0x108 +10000a70: f04f 040b mov.w r4, #11 +10000a74: f8a2 4120 strh.w r4, [r2, #288] @ 0x120 +10000a78: f04f 040c mov.w r4, #12 +10000a7c: f8a2 4138 strh.w r4, [r2, #312] @ 0x138 +10000a80: f04f 0401 mov.w r4, #1 +10000a84: 8614 strh r4, [r2, #48] @ 0x30 +10000a86: f04f 0408 mov.w r4, #8 +10000a8a: f8a2 40d8 strh.w r4, [r2, #216] @ 0xd8 +10000a8e: 4c14 ldr r4, [pc, #80] @ (10000ae0 ) +10000a90: f04f 0e0d mov.w lr, #13 +10000a94: f04f 0c0e mov.w ip, #14 +10000a98: 609c str r4, [r3, #8] +10000a9a: 2408 movs r4, #8 +10000a9c: 8099 strh r1, [r3, #4] +10000a9e: f8a2 e150 strh.w lr, [r2, #336] @ 0x150 +10000aa2: f8a2 c168 strh.w ip, [r2, #360] @ 0x168 +10000aa6: f8a2 0060 strh.w r0, [r2, #96] @ 0x60 +10000aaa: 8011 strh r1, [r2, #0] +10000aac: 4a0d ldr r2, [pc, #52] @ (10000ae4 ) +10000aae: 622c str r4, [r5, #32] +10000ab0: 490d ldr r1, [pc, #52] @ (10000ae8 ) +10000ab2: 60d3 str r3, [r2, #12] +10000ab4: f7ff fc5a bl 1000036c +10000ab8: 2101 movs r1, #1 +10000aba: 2003 movs r0, #3 +10000abc: f7ff fc40 bl 10000340 +10000ac0: 4b0a ldr r3, [pc, #40] @ (10000aec ) +10000ac2: 210a movs r1, #10 +10000ac4: 641c str r4, [r3, #64] @ 0x40 +10000ac6: 4803 ldr r0, [pc, #12] @ (10000ad4 ) +10000ac8: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} +10000acc: f7ff bdc6 b.w 1000065c +10000ad0: 200003c0 .word 0x200003c0 +10000ad4: 200005f8 .word 0x200005f8 +10000ad8: 400b0000 .word 0x400b0000 +10000adc: 20000578 .word 0x20000578 +10000ae0: 0010ffff .word 0x0010ffff +10000ae4: 200005d8 .word 0x200005d8 +10000ae8: 10000701 .word 0x10000701 +10000aec: 400b2000 .word 0x400b2000 + +10000af0 : +10000af0: b5f0 push {r4, r5, r6, r7, lr} +10000af2: 4616 mov r6, r2 +10000af4: 461f mov r7, r3 +10000af6: 6902 ldr r2, [r0, #16] +10000af8: 4603 mov r3, r0 +10000afa: f3ef 8010 mrs r0, PRIMASK +10000afe: b672 cpsid i +10000b00: e8d2 4fcf ldaexb r4, [r2] +10000b04: 2101 movs r1, #1 +10000b06: 2c00 cmp r4, #0 +10000b08: d1fa bne.n 10000b00 +10000b0a: e8c2 1f44 strexb r4, r1, [r2] +10000b0e: 2c00 cmp r4, #0 +10000b10: d1f6 bne.n 10000b00 +10000b12: f3bf 8f5f dmb sy +10000b16: f9b3 1002 ldrsh.w r1, [r3, #2] +10000b1a: 691d ldr r5, [r3, #16] +10000b1c: 2900 cmp r1, #0 +10000b1e: db45 blt.n 10000bac +10000b20: f8d3 e014 ldr.w lr, [r3, #20] +10000b24: eb01 0241 add.w r2, r1, r1, lsl #1 +10000b28: f83e 4032 ldrh.w r4, [lr, r2, lsl #3] +10000b2c: eb0e 0cc2 add.w ip, lr, r2, lsl #3 +10000b30: 805c strh r4, [r3, #2] +10000b32: 2400 movs r4, #0 +10000b34: e8c5 4f8f stlb r4, [r5] +10000b38: f380 8810 msr PRIMASK, r0 +10000b3c: 9805 ldr r0, [sp, #20] +10000b3e: 4635 mov r5, r6 +10000b40: f8cc 0010 str.w r0, [ip, #16] +10000b44: 9806 ldr r0, [sp, #24] +10000b46: 463e mov r6, r7 +10000b48: f8cc 0014 str.w r0, [ip, #20] +10000b4c: f8bc 0002 ldrh.w r0, [ip, #2] +10000b50: e9cc 5602 strd r5, r6, [ip, #8] +10000b54: 3001 adds r0, #1 +10000b56: f3c0 000e ubfx r0, r0, #0, #15 +10000b5a: 2801 cmp r0, #1 +10000b5c: bf38 it cc +10000b5e: 2001 movcc r0, #1 +10000b60: f8ac 0002 strh.w r0, [ip, #2] +10000b64: ea40 4001 orr.w r0, r0, r1, lsl #16 +10000b68: f8d3 c010 ldr.w ip, [r3, #16] +10000b6c: f3ef 8510 mrs r5, PRIMASK +10000b70: b672 cpsid i +10000b72: e8dc 7fcf ldaexb r7, [ip] +10000b76: 2601 movs r6, #1 +10000b78: 2f00 cmp r7, #0 +10000b7a: d1fa bne.n 10000b72 +10000b7c: e8cc 6f47 strexb r7, r6, [ip] +10000b80: 2f00 cmp r7, #0 +10000b82: d1f6 bne.n 10000b72 +10000b84: f3bf 8f5f dmb sy +10000b88: f8b3 c004 ldrh.w ip, [r3, #4] +10000b8c: f82e c032 strh.w ip, [lr, r2, lsl #3] +10000b90: 8099 strh r1, [r3, #4] +10000b92: 691a ldr r2, [r3, #16] +10000b94: e8c2 4f8f stlb r4, [r2] +10000b98: f385 8810 msr PRIMASK, r5 +10000b9c: 2101 movs r1, #1 +10000b9e: 781c ldrb r4, [r3, #0] +10000ba0: 68da ldr r2, [r3, #12] +10000ba2: 40a1 lsls r1, r4 +10000ba4: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000ba8: 6059 str r1, [r3, #4] +10000baa: bdf0 pop {r4, r5, r6, r7, pc} +10000bac: 2300 movs r3, #0 +10000bae: e8c5 3f8f stlb r3, [r5] +10000bb2: f380 8810 msr PRIMASK, r0 +10000bb6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000bba: bdf0 pop {r4, r5, r6, r7, pc} + +10000bbc : +10000bbc: 4603 mov r3, r0 +10000bbe: 8940 ldrh r0, [r0, #10] +10000bc0: ebb0 4f21 cmp.w r0, r1, asr #16 +10000bc4: dd3a ble.n 10000c3c +10000bc6: 6958 ldr r0, [r3, #20] +10000bc8: 140a asrs r2, r1, #16 +10000bca: eb02 0242 add.w r2, r2, r2, lsl #1 +10000bce: b510 push {r4, lr} +10000bd0: f8d3 c010 ldr.w ip, [r3, #16] +10000bd4: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000bd8: f3ef 8e10 mrs lr, PRIMASK +10000bdc: b672 cpsid i +10000bde: e8dc 4fcf ldaexb r4, [ip] +10000be2: 2201 movs r2, #1 +10000be4: 2c00 cmp r4, #0 +10000be6: d1fa bne.n 10000bde +10000be8: e8cc 2f44 strexb r4, r2, [ip] +10000bec: 2c00 cmp r4, #0 +10000bee: d1f6 bne.n 10000bde +10000bf0: f3bf 8f5f dmb sy +10000bf4: 8842 ldrh r2, [r0, #2] +10000bf6: b289 uxth r1, r1 +10000bf8: b292 uxth r2, r2 +10000bfa: 428a cmp r2, r1 +10000bfc: d007 beq.n 10000c0e +10000bfe: 2200 movs r2, #0 +10000c00: 691b ldr r3, [r3, #16] +10000c02: e8c3 2f8f stlb r2, [r3] +10000c06: f38e 8810 msr PRIMASK, lr +10000c0a: 2000 movs r0, #0 +10000c0c: bd10 pop {r4, pc} +10000c0e: ea6f 4242 mvn.w r2, r2, lsl #17 +10000c12: ea6f 4252 mvn.w r2, r2, lsr #17 +10000c16: 8042 strh r2, [r0, #2] +10000c18: 2101 movs r1, #1 +10000c1a: 2200 movs r2, #0 +10000c1c: 6918 ldr r0, [r3, #16] +10000c1e: 7199 strb r1, [r3, #6] +10000c20: e8c0 2f8f stlb r2, [r0] +10000c24: f38e 8810 msr PRIMASK, lr +10000c28: f893 c000 ldrb.w ip, [r3] +10000c2c: 68da ldr r2, [r3, #12] +10000c2e: 4608 mov r0, r1 +10000c30: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c34: fa01 f10c lsl.w r1, r1, ip +10000c38: 6059 str r1, [r3, #4] +10000c3a: bd10 pop {r4, pc} +10000c3c: 2000 movs r0, #0 +10000c3e: 4770 bx lr + +10000c40 : +10000c40: b5f0 push {r4, r5, r6, r7, lr} +10000c42: 4602 mov r2, r0 +10000c44: b085 sub sp, #20 +10000c46: f3ef 8505 mrs r5, IPSR +10000c4a: b2ed uxtb r5, r5 +10000c4c: 2d00 cmp r5, #0 +10000c4e: d161 bne.n 10000d14 +10000c50: 460b mov r3, r1 +10000c52: 4c42 ldr r4, [pc, #264] @ (10000d5c ) +10000c54: e9d4 0100 ldrd r0, r1, [r4] +10000c58: 4299 cmp r1, r3 +10000c5a: bf08 it eq +10000c5c: 4290 cmpeq r0, r2 +10000c5e: d04a beq.n 10000cf6 +10000c60: e9cd 2302 strd r2, r3, [sp, #8] +10000c64: 4b3e ldr r3, [pc, #248] @ (10000d60 ) +10000c66: 68df ldr r7, [r3, #12] +10000c68: 781e ldrb r6, [r3, #0] +10000c6a: 4638 mov r0, r7 +10000c6c: f000 f890 bl 10000d90 +10000c70: f106 0c04 add.w ip, r6, #4 +10000c74: f857 c02c ldr.w ip, [r7, ip, lsl #2] +10000c78: 9a02 ldr r2, [sp, #8] +10000c7a: 9b03 ldr r3, [sp, #12] +10000c7c: ebac 0c00 sub.w ip, ip, r0 +10000c80: 1a10 subs r0, r2, r0 +10000c82: eb63 0101 sbc.w r1, r3, r1 +10000c86: 4560 cmp r0, ip +10000c88: f171 0100 sbcs.w r1, r1, #0 +10000c8c: da33 bge.n 10000cf6 +10000c8e: e9cd 2302 strd r2, r3, [sp, #8] +10000c92: f000 f885 bl 10000da0 +10000c96: 9a02 ldr r2, [sp, #8] +10000c98: 9b03 ldr r3, [sp, #12] +10000c9a: 4282 cmp r2, r0 +10000c9c: eb63 0101 sbc.w r1, r3, r1 +10000ca0: 2900 cmp r1, #0 +10000ca2: db49 blt.n 10000d38 +10000ca4: 492f ldr r1, [pc, #188] @ (10000d64 ) +10000ca6: 482e ldr r0, [pc, #184] @ (10000d60 ) +10000ca8: 9100 str r1, [sp, #0] +10000caa: 9501 str r5, [sp, #4] +10000cac: e9cd 3202 strd r3, r2, [sp, #8] +10000cb0: f7ff ff1e bl 10000af0 +10000cb4: e9dd 3202 ldrd r3, r2, [sp, #8] +10000cb8: 1e01 subs r1, r0, #0 +10000cba: dd3d ble.n 10000d38 +10000cbc: 482a ldr r0, [pc, #168] @ (10000d68 ) +10000cbe: e9c4 2300 strd r2, r3, [r4] +10000cc2: 6a44 ldr r4, [r0, #36] @ 0x24 +10000cc4: 429c cmp r4, r3 +10000cc6: d346 bcc.n 10000d56 +10000cc8: 6a80 ldr r0, [r0, #40] @ 0x28 +10000cca: 4290 cmp r0, r2 +10000ccc: d341 bcc.n 10000d52 +10000cce: 4824 ldr r0, [pc, #144] @ (10000d60 ) +10000cd0: e9cd 3202 strd r3, r2, [sp, #8] +10000cd4: f7ff ff72 bl 10000bbc +10000cd8: 4923 ldr r1, [pc, #140] @ (10000d68 ) +10000cda: 9b02 ldr r3, [sp, #8] +10000cdc: 6a48 ldr r0, [r1, #36] @ 0x24 +10000cde: 4298 cmp r0, r3 +10000ce0: d31c bcc.n 10000d1c +10000ce2: bf14 ite ne +10000ce4: 2001 movne r0, #1 +10000ce6: 2000 moveq r0, #0 +10000ce8: 6a8b ldr r3, [r1, #40] @ 0x28 +10000cea: 9a03 ldr r2, [sp, #12] +10000cec: 4293 cmp r3, r2 +10000cee: bf28 it cs +10000cf0: f040 0001 orrcs.w r0, r0, #1 +10000cf4: e00c b.n 10000d10 +10000cf6: bf20 wfe +10000cf8: 491b ldr r1, [pc, #108] @ (10000d68 ) +10000cfa: 6a48 ldr r0, [r1, #36] @ 0x24 +10000cfc: 4298 cmp r0, r3 +10000cfe: d30d bcc.n 10000d1c +10000d00: bf14 ite ne +10000d02: 2001 movne r0, #1 +10000d04: 2000 moveq r0, #0 +10000d06: 6a8b ldr r3, [r1, #40] @ 0x28 +10000d08: 4293 cmp r3, r2 +10000d0a: bf28 it cs +10000d0c: f040 0001 orrcs.w r0, r0, #1 +10000d10: b005 add sp, #20 +10000d12: bdf0 pop {r4, r5, r6, r7, pc} +10000d14: 4814 ldr r0, [pc, #80] @ (10000d68 ) +10000d16: 6a43 ldr r3, [r0, #36] @ 0x24 +10000d18: 428b cmp r3, r1 +10000d1a: d202 bcs.n 10000d22 +10000d1c: 2000 movs r0, #0 +10000d1e: b005 add sp, #20 +10000d20: bdf0 pop {r4, r5, r6, r7, pc} +10000d22: bf14 ite ne +10000d24: 2301 movne r3, #1 +10000d26: 2300 moveq r3, #0 +10000d28: 6a81 ldr r1, [r0, #40] @ 0x28 +10000d2a: 4291 cmp r1, r2 +10000d2c: bf34 ite cc +10000d2e: 4618 movcc r0, r3 +10000d30: f043 0001 orrcs.w r0, r3, #1 +10000d34: b005 add sp, #20 +10000d36: bdf0 pop {r4, r5, r6, r7, pc} +10000d38: 490b ldr r1, [pc, #44] @ (10000d68 ) +10000d3a: 6a48 ldr r0, [r1, #36] @ 0x24 +10000d3c: 4298 cmp r0, r3 +10000d3e: d3ed bcc.n 10000d1c +10000d40: 1ac0 subs r0, r0, r3 +10000d42: bf18 it ne +10000d44: 2001 movne r0, #1 +10000d46: 6a8b ldr r3, [r1, #40] @ 0x28 +10000d48: 4293 cmp r3, r2 +10000d4a: bf28 it cs +10000d4c: f040 0001 orrcs.w r0, r0, #1 +10000d50: e7de b.n 10000d10 +10000d52: 429c cmp r4, r3 +10000d54: d1bb bne.n 10000cce +10000d56: bf20 wfe +10000d58: e7b9 b.n 10000cce +10000d5a: bf00 nop +10000d5c: 200003b8 .word 0x200003b8 +10000d60: 200003c0 .word 0x200003c0 +10000d64: 100006b5 .word 0x100006b5 +10000d68: 400b0000 .word 0x400b0000 + +10000d6c : +10000d6c: b410 push {r4} +10000d6e: 4b05 ldr r3, [pc, #20] @ (10000d84 ) +10000d70: 4c05 ldr r4, [pc, #20] @ (10000d88 ) +10000d72: 4a06 ldr r2, [pc, #24] @ (10000d8c ) +10000d74: 42a0 cmp r0, r4 +10000d76: bf14 ite ne +10000d78: 4618 movne r0, r3 +10000d7a: 1c58 addeq r0, r3, #1 +10000d7c: bc10 pop {r4} +10000d7e: f7ff ba73 b.w 10000268 +10000d82: bf00 nop +10000d84: 200005a0 .word 0x200005a0 +10000d88: 400b8000 .word 0x400b8000 +10000d8c: 10001934 .word 0x10001934 + +10000d90 : +10000d90: 4603 mov r3, r0 +10000d92: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d94: 460a mov r2, r1 +10000d96: 6a98 ldr r0, [r3, #40] @ 0x28 +10000d98: 6a59 ldr r1, [r3, #36] @ 0x24 +10000d9a: 428a cmp r2, r1 +10000d9c: d1fa bne.n 10000d94 +10000d9e: 4770 bx lr + +10000da0 : +10000da0: 4b03 ldr r3, [pc, #12] @ (10000db0 ) +10000da2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 4291 cmp r1, r2 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr +10000db0: 400b0000 .word 0x400b0000 + +10000db4 : +10000db4: b500 push {lr} +10000db6: 468e mov lr, r1 +10000db8: 4a15 ldr r2, [pc, #84] @ (10000e10 ) +10000dba: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dbc: 469c mov ip, r3 +10000dbe: 6a91 ldr r1, [r2, #40] @ 0x28 +10000dc0: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc2: 4563 cmp r3, ip +10000dc4: d1fa bne.n 10000dbc +10000dc6: 1840 adds r0, r0, r1 +10000dc8: eb53 030e adcs.w r3, r3, lr +10000dcc: f04f 0200 mov.w r2, #0 +10000dd0: bf28 it cs +10000dd2: 2201 movcs r2, #1 +10000dd4: b1ba cbz r2, 10000e06 +10000dd6: 4b0e ldr r3, [pc, #56] @ (10000e10 ) +10000dd8: 6a5a ldr r2, [r3, #36] @ 0x24 +10000dda: 1c53 adds r3, r2, #1 +10000ddc: bf08 it eq +10000dde: 4610 moveq r0, r2 +10000de0: d008 beq.n 10000df4 +10000de2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10000de6: 4618 mov r0, r3 +10000de8: 4909 ldr r1, [pc, #36] @ (10000e10 ) +10000dea: 6a4a ldr r2, [r1, #36] @ 0x24 +10000dec: 429a cmp r2, r3 +10000dee: d3fc bcc.n 10000dea +10000df0: 429a cmp r2, r3 +10000df2: d107 bne.n 10000e04 +10000df4: 4b06 ldr r3, [pc, #24] @ (10000e10 ) +10000df6: e002 b.n 10000dfe +10000df8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000dfa: 4291 cmp r1, r2 +10000dfc: d102 bne.n 10000e04 +10000dfe: 6a99 ldr r1, [r3, #40] @ 0x28 +10000e00: 4281 cmp r1, r0 +10000e02: d3f9 bcc.n 10000df8 +10000e04: bd00 pop {pc} +10000e06: 4a02 ldr r2, [pc, #8] @ (10000e10 ) +10000e08: 6a52 ldr r2, [r2, #36] @ 0x24 +10000e0a: 4293 cmp r3, r2 +10000e0c: d8ec bhi.n 10000de8 +10000e0e: e7ef b.n 10000df0 +10000e10: 400b0000 .word 0x400b0000 + +10000e14 : +10000e14: b570 push {r4, r5, r6, lr} +10000e16: 4604 mov r4, r0 +10000e18: b082 sub sp, #8 +10000e1a: 2006 movs r0, #6 +10000e1c: 460e mov r6, r1 +10000e1e: f000 f8ef bl 10001000 +10000e22: 2800 cmp r0, #0 +10000e24: d044 beq.n 10000eb0 +10000e26: 4a38 ldr r2, [pc, #224] @ (10000f08 ) +10000e28: 4838 ldr r0, [pc, #224] @ (10000f0c ) +10000e2a: 4294 cmp r4, r2 +10000e2c: bf14 ite ne +10000e2e: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e32: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e36: 4b36 ldr r3, [pc, #216] @ (10000f10 ) +10000e38: 4936 ldr r1, [pc, #216] @ (10000f14 ) +10000e3a: 6002 str r2, [r0, #0] +10000e3c: 601a str r2, [r3, #0] +10000e3e: 688d ldr r5, [r1, #8] +10000e40: ea32 0505 bics.w r5, r2, r5 +10000e44: d1fb bne.n 10000e3e +10000e46: 4a30 ldr r2, [pc, #192] @ (10000f08 ) +10000e48: f44f 7080 mov.w r0, #256 @ 0x100 +10000e4c: 1aa2 subs r2, r4, r2 +10000e4e: fab2 f282 clz r2, r2 +10000e52: 4931 ldr r1, [pc, #196] @ (10000f18 ) +10000e54: 0952 lsrs r2, r2, #5 +10000e56: f821 0012 strh.w r0, [r1, r2, lsl #1] +10000e5a: 2006 movs r0, #6 +10000e5c: f000 f8d0 bl 10001000 +10000e60: 00c2 lsls r2, r0, #3 +10000e62: fbb2 f2f6 udiv r2, r2, r6 +10000e66: 3201 adds r2, #1 +10000e68: 09d1 lsrs r1, r2, #7 +10000e6a: d123 bne.n 10000eb4 +10000e6c: 2640 movs r6, #64 @ 0x40 +10000e6e: 2301 movs r3, #1 +10000e70: 6263 str r3, [r4, #36] @ 0x24 +10000e72: 62a1 str r1, [r4, #40] @ 0x28 +10000e74: 6b25 ldr r5, [r4, #48] @ 0x30 +10000e76: 07eb lsls r3, r5, #31 +10000e78: d425 bmi.n 10000ec6 +10000e7a: 4623 mov r3, r4 +10000e7c: 2100 movs r1, #0 +10000e7e: f853 2f2c ldr.w r2, [r3, #44]! +10000e82: 2006 movs r0, #6 +10000e84: f503 5280 add.w r2, r3, #4096 @ 0x1000 +10000e88: 6011 str r1, [r2, #0] +10000e8a: 6325 str r5, [r4, #48] @ 0x30 +10000e8c: 9201 str r2, [sp, #4] +10000e8e: f000 f8b7 bl 10001000 +10000e92: f240 3501 movw r5, #769 @ 0x301 +10000e96: 2103 movs r1, #3 +10000e98: 0080 lsls r0, r0, #2 +10000e9a: fbb0 f0f6 udiv r0, r0, r6 +10000e9e: 6ae3 ldr r3, [r4, #44] @ 0x2c +10000ea0: 9a01 ldr r2, [sp, #4] +10000ea2: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000ea6: f003 037e and.w r3, r3, #126 @ 0x7e +10000eaa: 6013 str r3, [r2, #0] +10000eac: 6325 str r5, [r4, #48] @ 0x30 +10000eae: 64a1 str r1, [r4, #72] @ 0x48 +10000eb0: b002 add sp, #8 +10000eb2: bd70 pop {r4, r5, r6, pc} +10000eb4: f64f 70fe movw r0, #65534 @ 0xfffe +10000eb8: 4281 cmp r1, r0 +10000eba: d91d bls.n 10000ef8 +10000ebc: 4629 mov r1, r5 +10000ebe: f64f 73ff movw r3, #65535 @ 0xffff +10000ec2: 4e16 ldr r6, [pc, #88] @ (10000f1c ) +10000ec4: e7d4 b.n 10000e70 +10000ec6: f240 3201 movw r2, #769 @ 0x301 +10000eca: f504 5340 add.w r3, r4, #12288 @ 0x3000 +10000ece: 631a str r2, [r3, #48] @ 0x30 +10000ed0: 6a63 ldr r3, [r4, #36] @ 0x24 +10000ed2: 6aa2 ldr r2, [r4, #40] @ 0x28 +10000ed4: 2006 movs r0, #6 +10000ed6: eb02 1283 add.w r2, r2, r3, lsl #6 +10000eda: 9201 str r2, [sp, #4] +10000edc: f000 f890 bl 10001000 +10000ee0: 4b0f ldr r3, [pc, #60] @ (10000f20 ) +10000ee2: 9a01 ldr r2, [sp, #4] +10000ee4: fba3 1300 umull r1, r3, r3, r0 +10000ee8: 0290 lsls r0, r2, #10 +10000eea: 0adb lsrs r3, r3, #11 +10000eec: fbb0 f0f3 udiv r0, r0, r3 +10000ef0: 2100 movs r1, #0 +10000ef2: f7ff ff5f bl 10000db4 +10000ef6: e7c0 b.n 10000e7a +10000ef8: f3c2 0245 ubfx r2, r2, #1, #6 +10000efc: 460b mov r3, r1 +10000efe: eb02 1681 add.w r6, r2, r1, lsl #6 +10000f02: 4611 mov r1, r2 +10000f04: e7b4 b.n 10000e70 +10000f06: bf00 nop +10000f08: 40078000 .word 0x40078000 +10000f0c: 40022000 .word 0x40022000 +10000f10: 40023000 .word 0x40023000 +10000f14: 40020000 .word 0x40020000 +10000f18: 200005fc .word 0x200005fc +10000f1c: 003fffc0 .word 0x003fffc0 +10000f20: 8f2b7b75 .word 0x8f2b7b75 + +10000f24 : +10000f24: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f28: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f2c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f30: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f34: b570 push {r4, r5, r6, lr} +10000f36: 461e mov r6, r3 +10000f38: f8dc 3004 ldr.w r3, [ip, #4] +10000f3c: 1f04 subs r4, r0, #4 +10000f3e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 +10000f42: bf38 it cc +10000f44: f44f 3380 movcc.w r3, #65536 @ 0x10000 +10000f48: b2e4 uxtb r4, r4 +10000f4a: bf38 it cc +10000f4c: f8cc 3004 strcc.w r3, [ip, #4] +10000f50: 2c01 cmp r4, #1 +10000f52: d92e bls.n 10000fb2 +10000f54: f44f 6500 mov.w r5, #2048 @ 0x800 +10000f58: 4b28 ldr r3, [pc, #160] @ (10000ffc ) +10000f5a: f50c 5e40 add.w lr, ip, #12288 @ 0x3000 +10000f5e: f8ce 5000 str.w r5, [lr] +10000f62: f853 e020 ldr.w lr, [r3, r0, lsl #2] +10000f66: f1be 0f00 cmp.w lr, #0 +10000f6a: d117 bne.n 10000f9c +10000f6c: f8dc e000 ldr.w lr, [ip] +10000f70: 2c01 cmp r4, #1 +10000f72: ea8e 1242 eor.w r2, lr, r2, lsl #5 +10000f76: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f7a: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +10000f7e: f8ce 2000 str.w r2, [lr] +10000f82: d92b bls.n 10000fdc +10000f84: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f88: f843 6020 str.w r6, [r3, r0, lsl #2] +10000f8c: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f90: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f94: 6011 str r1, [r2, #0] +10000f96: f8cc 3004 str.w r3, [ip, #4] +10000f9a: bd70 pop {r4, r5, r6, pc} +10000f9c: 695d ldr r5, [r3, #20] +10000f9e: fbb5 fefe udiv lr, r5, lr +10000fa2: f10e 0e01 add.w lr, lr, #1 +10000fa6: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000faa: f1be 0e03 subs.w lr, lr, #3 +10000fae: d2fc bcs.n 10000faa +10000fb0: e7dc b.n 10000f6c +10000fb2: 2901 cmp r1, #1 +10000fb4: d1ce bne.n 10000f54 +10000fb6: 2403 movs r4, #3 +10000fb8: f50c 5340 add.w r3, ip, #12288 @ 0x3000 +10000fbc: 601c str r4, [r3, #0] +10000fbe: f8dc 3008 ldr.w r3, [ip, #8] +10000fc2: 07db lsls r3, r3, #31 +10000fc4: d5fb bpl.n 10000fbe +10000fc6: f8dc 3000 ldr.w r3, [ip] +10000fca: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +10000fce: ea83 1342 eor.w r3, r3, r2, lsl #5 +10000fd2: f003 03e0 and.w r3, r3, #224 @ 0xe0 +10000fd6: f8ce 3000 str.w r3, [lr] +10000fda: 4b08 ldr r3, [pc, #32] @ (10000ffc ) +10000fdc: 2201 movs r2, #1 +10000fde: f8dc 4000 ldr.w r4, [ip] +10000fe2: 404c eors r4, r1 +10000fe4: f004 0403 and.w r4, r4, #3 +10000fe8: f8ce 4000 str.w r4, [lr] +10000fec: fa02 f101 lsl.w r1, r2, r1 +10000ff0: f8dc 2008 ldr.w r2, [ip, #8] +10000ff4: 420a tst r2, r1 +10000ff6: d0fb beq.n 10000ff0 +10000ff8: e7c4 b.n 10000f84 +10000ffa: bf00 nop +10000ffc: 200005a4 .word 0x200005a4 + +10001000 : +10001000: 4b01 ldr r3, [pc, #4] @ (10001008 ) +10001002: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001006: 4770 bx lr +10001008: 200005a4 .word 0x200005a4 + +1000100c : +1000100c: b510 push {r4, lr} +1000100e: 9c02 ldr r4, [sp, #8] +10001010: 468e mov lr, r1 +10001012: ea4f 3c04 mov.w ip, r4, lsl #12 +10001016: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +1000101a: 4b1c ldr r3, [pc, #112] @ (1000108c ) +1000101c: fbb3 f3f1 udiv r3, r3, r1 +10001020: 6801 ldr r1, [r0, #0] +10001022: fbb2 f4f3 udiv r4, r2, r3 +10001026: 2900 cmp r1, #0 +10001028: db20 blt.n 1000106c +1000102a: 4a19 ldr r2, [pc, #100] @ (10001090 ) +1000102c: 4b19 ldr r3, [pc, #100] @ (10001094 ) +1000102e: 4290 cmp r0, r2 +10001030: bf14 ite ne +10001032: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001036: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000103a: 4917 ldr r1, [pc, #92] @ (10001098 ) +1000103c: 601a str r2, [r3, #0] +1000103e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001042: 601a str r2, [r3, #0] +10001044: 688b ldr r3, [r1, #8] +10001046: ea32 0303 bics.w r3, r2, r3 +1000104a: d1fb bne.n 10001044 +1000104c: 2221 movs r2, #33 @ 0x21 +1000104e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001052: 3304 adds r3, #4 +10001054: f8c0 e000 str.w lr, [r0] +10001058: 6084 str r4, [r0, #8] +1000105a: 601a str r2, [r3, #0] +1000105c: 6802 ldr r2, [r0, #0] +1000105e: 2a00 cmp r2, #0 +10001060: dafc bge.n 1000105c +10001062: 2208 movs r2, #8 +10001064: f8c0 c00c str.w ip, [r0, #12] +10001068: 601a str r2, [r3, #0] +1000106a: bd10 pop {r4, pc} +1000106c: 6803 ldr r3, [r0, #0] +1000106e: f003 033f and.w r3, r3, #63 @ 0x3f +10001072: 4573 cmp r3, lr +10001074: d1d9 bne.n 1000102a +10001076: 6883 ldr r3, [r0, #8] +10001078: f3c3 030b ubfx r3, r3, #0, #12 +1000107c: 42a3 cmp r3, r4 +1000107e: d1d4 bne.n 1000102a +10001080: 68c3 ldr r3, [r0, #12] +10001082: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001086: 4563 cmp r3, ip +10001088: d1cf bne.n 1000102a +1000108a: bd10 pop {r4, pc} +1000108c: 00b71b00 .word 0x00b71b00 +10001090: 40058000 .word 0x40058000 +10001094: 40022000 .word 0x40022000 +10001098: 40020000 .word 0x40020000 + +1000109c : +1000109c: 2301 movs r3, #1 +1000109e: eb00 0040 add.w r0, r0, r0, lsl #1 +100010a2: 0080 lsls r0, r0, #2 +100010a4: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100010a8: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +100010ac: 6041 str r1, [r0, #4] +100010ae: 6003 str r3, [r0, #0] +100010b0: 4770 bx lr +100010b2: bf00 nop + +100010b4 : +100010b4: 2300 movs r3, #0 +100010b6: 8adb ldrh r3, [r3, #22] +100010b8: 2200 movs r2, #0 +100010ba: e842 f200 tt r2, r2 +100010be: 0252 lsls r2, r2, #9 +100010c0: d401 bmi.n 100010c6 +100010c2: 2110 movs r1, #16 +100010c4: 4718 bx r3 +100010c6: 2104 movs r1, #4 +100010c8: 4718 bx r3 +100010ca: bf00 nop + +100010cc : +100010cc: 4a03 ldr r2, [pc, #12] @ (100010dc ) +100010ce: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010d2: 2b00 cmp r3, #0 +100010d4: d0fb beq.n 100010ce +100010d6: f3bf 8f5f dmb sy +100010da: 4770 bx lr +100010dc: 400e0000 .word 0x400e0000 + +100010e0 : +100010e0: 2100 movs r1, #0 +100010e2: 4b04 ldr r3, [pc, #16] @ (100010f4 ) +100010e4: 4a04 ldr r2, [pc, #16] @ (100010f8 ) +100010e6: f3bf 8f5f dmb sy +100010ea: f843 1b04 str.w r1, [r3], #4 +100010ee: 4293 cmp r3, r2 +100010f0: d1f9 bne.n 100010e6 +100010f2: 4770 bx lr +100010f4: 400e080c .word 0x400e080c +100010f8: 400e082c .word 0x400e082c + +100010fc : +100010fc: f44f 6c2a mov.w ip, #2720 @ 0xaa0 +10001100: f44f 708d mov.w r0, #282 @ 0x11a +10001104: 4a05 ldr r2, [pc, #20] @ (1000111c ) +10001106: 4b06 ldr r3, [pc, #24] @ (10001120 ) +10001108: 4906 ldr r1, [pc, #24] @ (10001124 ) +1000110a: f8c2 c000 str.w ip, [r2] +1000110e: 60d0 str r0, [r2, #12] +10001110: 6019 str r1, [r3, #0] +10001112: 6853 ldr r3, [r2, #4] +10001114: 2b00 cmp r3, #0 +10001116: dafc bge.n 10001112 +10001118: 4770 bx lr +1000111a: bf00 nop +1000111c: 40048000 .word 0x40048000 +10001120: 4004a000 .word 0x4004a000 +10001124: 00fab000 .word 0x00fab000 + +10001128 : +10001128: 4770 bx lr +1000112a: bf00 nop + +1000112c : +1000112c: b508 push {r3, lr} +1000112e: 4801 ldr r0, [pc, #4] @ (10001134 ) +10001130: f7ff f882 bl 10000238 +10001134: 10001958 .word 0x10001958 + +10001138 : +10001138: b538 push {r3, r4, r5, lr} +1000113a: 4c05 ldr r4, [pc, #20] @ (10001150 ) +1000113c: 4d05 ldr r5, [pc, #20] @ (10001154 ) +1000113e: 42ac cmp r4, r5 +10001140: d204 bcs.n 1000114c +10001142: f854 3b04 ldr.w r3, [r4], #4 +10001146: 4798 blx r3 +10001148: 42ac cmp r4, r5 +1000114a: d3fa bcc.n 10001142 +1000114c: bd38 pop {r3, r4, r5, pc} +1000114e: bf00 nop +10001150: 100018e0 .word 0x100018e0 +10001154: 10001920 .word 0x10001920 + +10001158 : +10001158: 4806 ldr r0, [pc, #24] @ (10001174 ) +1000115a: f8df c028 ldr.w ip, [pc, #40] @ 10001184 +1000115e: 4b06 ldr r3, [pc, #24] @ (10001178 ) +10001160: 4a06 ldr r2, [pc, #24] @ (1000117c ) +10001162: 4907 ldr r1, [pc, #28] @ (10001180 ) +10001164: f8c0 c000 str.w ip, [r0] +10001168: 601a str r2, [r3, #0] +1000116a: 688b ldr r3, [r1, #8] +1000116c: ea32 0303 bics.w r3, r2, r3 +10001170: d1fb bne.n 1000116a +10001172: 4770 bx lr +10001174: 40022000 .word 0x40022000 +10001178: 40023000 .word 0x40023000 +1000117c: 03f3fff6 .word 0x03f3fff6 +10001180: 40020000 .word 0x40020000 +10001184: efef3b7f .word 0xefef3b7f + +10001188 : +10001188: 4b04 ldr r3, [pc, #16] @ (1000119c ) +1000118a: 6cdb ldr r3, [r3, #76] @ 0x4c +1000118c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001190: d103 bne.n 1000119a +10001192: f44f 2280 mov.w r2, #262144 @ 0x40000 +10001196: 4b02 ldr r3, [pc, #8] @ (100011a0 ) +10001198: 64da str r2, [r3, #76] @ 0x4c +1000119a: 4770 bx lr +1000119c: 50110000 .word 0x50110000 +100011a0: 50112000 .word 0x50112000 + +100011a4 : +100011a4: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100011a8: 4b04 ldr r3, [pc, #16] @ (100011bc ) +100011aa: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100011ae: 430b orrs r3, r1 +100011b0: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100011b4: ee10 0430 dcp_rcmp r0 +100011b8: 4770 bx lr +100011ba: bf00 nop +100011bc: 00300303 .word 0x00300303 + +100011c0 : +100011c0: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011c4: 4b04 ldr r3, [pc, #16] @ (100011d8 ) +100011c6: 4a05 ldr r2, [pc, #20] @ (100011dc ) +100011c8: 6019 str r1, [r3, #0] +100011ca: 6893 ldr r3, [r2, #8] +100011cc: 43db mvns r3, r3 +100011ce: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011d2: d1fa bne.n 100011ca +100011d4: 4770 bx lr +100011d6: bf00 nop +100011d8: 40023000 .word 0x40023000 +100011dc: 40020000 .word 0x40020000 + +100011e0 : +100011e0: b510 push {r4, lr} +100011e2: f245 2053 movw r0, #21075 @ 0x5253 +100011e6: f7ff ff65 bl 100010b4 +100011ea: e8bd 4010 ldmia.w sp!, {r4, lr} +100011ee: 4603 mov r3, r0 +100011f0: 2004 movs r0, #4 +100011f2: 4718 bx r3 + +100011f4 : +100011f4: b510 push {r4, lr} +100011f6: f245 2053 movw r0, #21075 @ 0x5253 +100011fa: f7ff ff5b bl 100010b4 +100011fe: e8bd 4010 ldmia.w sp!, {r4, lr} +10001202: 4603 mov r3, r0 +10001204: 2001 movs r0, #1 +10001206: 4718 bx r3 + +10001208 : +10001208: f7ff b86e b.w 100002e8 + +1000120c : +1000120c: 4913 ldr r1, [pc, #76] @ (1000125c ) +1000120e: 4b14 ldr r3, [pc, #80] @ (10001260 ) +10001210: b570 push {r4, r5, r6, lr} +10001212: 1a5c subs r4, r3, r1 +10001214: 08a5 lsrs r5, r4, #2 +10001216: 2d44 cmp r5, #68 @ 0x44 +10001218: 462a mov r2, r5 +1000121a: bf28 it cs +1000121c: 2244 movcs r2, #68 @ 0x44 +1000121e: 4e11 ldr r6, [pc, #68] @ (10001264 ) +10001220: 0092 lsls r2, r2, #2 +10001222: 4630 mov r0, r6 +10001224: f000 fb58 bl 100018d8 <__memcpy_veneer> +10001228: 2d43 cmp r5, #67 @ 0x43 +1000122a: d813 bhi.n 10001254 +1000122c: 4a0e ldr r2, [pc, #56] @ (10001268 ) +1000122e: d00f beq.n 10001250 +10001230: f1c5 0044 rsb r0, r5, #68 @ 0x44 +10001234: 1933 adds r3, r6, r4 +10001236: 0841 lsrs r1, r0, #1 +10001238: eb03 01c1 add.w r1, r3, r1, lsl #3 +1000123c: e9c3 2200 strd r2, r2, [r3] +10001240: 3308 adds r3, #8 +10001242: 428b cmp r3, r1 +10001244: d1fa bne.n 1000123c +10001246: 07c3 lsls r3, r0, #31 +10001248: d504 bpl.n 10001254 +1000124a: f020 0001 bic.w r0, r0, #1 +1000124e: 4405 add r5, r0 +10001250: f846 2025 str.w r2, [r6, r5, lsl #2] +10001254: 4b05 ldr r3, [pc, #20] @ (1000126c ) +10001256: 609e str r6, [r3, #8] +10001258: bd70 pop {r4, r5, r6, pc} +1000125a: bf00 nop +1000125c: 10000000 .word 0x10000000 +10001260: 10000110 .word 0x10000110 +10001264: 20000000 .word 0x20000000 +10001268: 10000111 .word 0x10000111 +1000126c: e000ed00 .word 0xe000ed00 + +10001270 : +10001270: 2300 movs r3, #0 +10001272: b570 push {r4, r5, r6, lr} +10001274: 4c2b ldr r4, [pc, #172] @ (10001324 ) +10001276: b082 sub sp, #8 +10001278: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +1000127c: f7ff ff3e bl 100010fc +10001280: 2201 movs r2, #1 +10001282: 4b29 ldr r3, [pc, #164] @ (10001328 ) +10001284: 63da str r2, [r3, #60] @ 0x3c +10001286: 6c63 ldr r3, [r4, #68] @ 0x44 +10001288: 2b01 cmp r3, #1 +1000128a: d1fc bne.n 10001286 +1000128c: 2103 movs r1, #3 +1000128e: 4a26 ldr r2, [pc, #152] @ (10001328 ) +10001290: 4b24 ldr r3, [pc, #144] @ (10001324 ) +10001292: 6311 str r1, [r2, #48] @ 0x30 +10001294: 6b9c ldr r4, [r3, #56] @ 0x38 +10001296: 2c01 cmp r4, #1 +10001298: d1fc bne.n 10001294 +1000129a: 2602 movs r6, #2 +1000129c: 2505 movs r5, #5 +1000129e: 4621 mov r1, r4 +100012a0: 2305 movs r3, #5 +100012a2: 4a22 ldr r2, [pc, #136] @ (1000132c ) +100012a4: 4822 ldr r0, [pc, #136] @ (10001330 ) +100012a6: 9600 str r6, [sp, #0] +100012a8: f7ff feb0 bl 1000100c +100012ac: 4621 mov r1, r4 +100012ae: 462b mov r3, r5 +100012b0: 4a20 ldr r2, [pc, #128] @ (10001334 ) +100012b2: 4821 ldr r0, [pc, #132] @ (10001338 ) +100012b4: 9500 str r5, [sp, #0] +100012b6: f7ff fea9 bl 1000100c +100012ba: 2200 movs r2, #0 +100012bc: 2004 movs r0, #4 +100012be: 4631 mov r1, r6 +100012c0: 4b1e ldr r3, [pc, #120] @ (1000133c ) +100012c2: f7ff fe2f bl 10000f24 +100012c6: 4621 mov r1, r4 +100012c8: 4628 mov r0, r5 +100012ca: 2200 movs r2, #0 +100012cc: 4b1c ldr r3, [pc, #112] @ (10001340 ) +100012ce: f7ff fe29 bl 10000f24 +100012d2: 2200 movs r2, #0 +100012d4: 2008 movs r0, #8 +100012d6: 4611 mov r1, r2 +100012d8: 4b1a ldr r3, [pc, #104] @ (10001344 ) +100012da: f7ff fe23 bl 10000f24 +100012de: 2200 movs r2, #0 +100012e0: 2009 movs r0, #9 +100012e2: 4611 mov r1, r2 +100012e4: 4b17 ldr r3, [pc, #92] @ (10001344 ) +100012e6: f7ff fe1d bl 10000f24 +100012ea: 2200 movs r2, #0 +100012ec: 2006 movs r0, #6 +100012ee: 4611 mov r1, r2 +100012f0: 4b13 ldr r3, [pc, #76] @ (10001340 ) +100012f2: f7ff fe17 bl 10000f24 +100012f6: 2200 movs r2, #0 +100012f8: 4b11 ldr r3, [pc, #68] @ (10001340 ) +100012fa: 2007 movs r0, #7 +100012fc: 4611 mov r1, r2 +100012fe: f7ff fe11 bl 10000f24 +10001302: 2004 movs r0, #4 +10001304: f7ff fe7c bl 10001000 +10001308: 2400 movs r4, #0 +1000130a: 4b0f ldr r3, [pc, #60] @ (10001348 ) +1000130c: fba3 3500 umull r3, r5, r3, r0 +10001310: 0cad lsrs r5, r5, #18 +10001312: b2e0 uxtb r0, r4 +10001314: 4629 mov r1, r5 +10001316: 3401 adds r4, #1 +10001318: f7ff fec0 bl 1000109c +1000131c: 2c06 cmp r4, #6 +1000131e: d1f8 bne.n 10001312 +10001320: b002 add sp, #8 +10001322: bd70 pop {r4, r5, r6, pc} +10001324: 40010000 .word 0x40010000 +10001328: 40013000 .word 0x40013000 +1000132c: 59682f00 .word 0x59682f00 +10001330: 40050000 .word 0x40050000 +10001334: 47868c00 .word 0x47868c00 +10001338: 40058000 .word 0x40058000 +1000133c: 00b71b00 .word 0x00b71b00 +10001340: 08f0d180 .word 0x08f0d180 +10001344: 02dc6c00 .word 0x02dc6c00 +10001348: 431bde83 .word 0x431bde83 + +1000134c <_out_char>: +1000134c: b900 cbnz r0, 10001350 <_out_char+0x4> +1000134e: 4770 bx lr +10001350: f000 b926 b.w 100015a0 <__wrap_putchar> + +10001354 : +10001354: b510 push {r4, lr} +10001356: 4a09 ldr r2, [pc, #36] @ (1000137c ) +10001358: b084 sub sp, #16 +1000135a: 6814 ldr r4, [r2, #0] +1000135c: b14c cbz r4, 10001372 +1000135e: 4603 mov r3, r0 +10001360: 9100 str r1, [sp, #0] +10001362: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001366: a903 add r1, sp, #12 +10001368: 4805 ldr r0, [pc, #20] @ (10001380 ) +1000136a: 47a0 blx r4 +1000136c: 2001 movs r0, #1 +1000136e: b004 add sp, #16 +10001370: bd10 pop {r4, pc} +10001372: f000 f957 bl 10001624 <__wrap_puts> +10001376: 4620 mov r0, r4 +10001378: b004 add sp, #16 +1000137a: bd10 pop {r4, pc} +1000137c: 200005d4 .word 0x200005d4 +10001380: 1000134d .word 0x1000134d + +10001384 <_exit>: +10001384: be00 bkpt 0x0000 +10001386: e7fd b.n 10001384 <_exit> + +10001388 <_fini>: +10001388: 4770 bx lr +1000138a: bf00 nop + +1000138c : +1000138c: b508 push {r3, lr} +1000138e: f7ff fff9 bl 10001384 <_exit> +10001392: bf00 nop + +10001394 : +10001394: b538 push {r3, r4, r5, lr} +10001396: 4c06 ldr r4, [pc, #24] @ (100013b0 ) +10001398: 4d06 ldr r5, [pc, #24] @ (100013b4 ) +1000139a: f7ff fecd bl 10001138 +1000139e: 42ac cmp r4, r5 +100013a0: d204 bcs.n 100013ac +100013a2: f854 3b04 ldr.w r3, [r4], #4 +100013a6: 4798 blx r3 +100013a8: 42ac cmp r4, r5 +100013aa: d3fa bcc.n 100013a2 +100013ac: bd38 pop {r3, r4, r5, pc} +100013ae: bf00 nop +100013b0: 10001920 .word 0x10001920 +100013b4: 10001920 .word 0x10001920 + +100013b8 : +100013b8: 6803 ldr r3, [r0, #0] +100013ba: 4608 mov r0, r1 +100013bc: 4611 mov r1, r2 +100013be: 4718 bx r3 + +100013c0 : +100013c0: b570 push {r4, r5, r6, lr} +100013c2: 4605 mov r5, r0 +100013c4: 4608 mov r0, r1 +100013c6: 7d69 ldrb r1, [r5, #21] +100013c8: b082 sub sp, #8 +100013ca: 2900 cmp r1, #0 +100013cc: d04f beq.n 1000146e +100013ce: 2a00 cmp r2, #0 +100013d0: dd25 ble.n 1000141e +100013d2: 7803 ldrb r3, [r0, #0] +100013d4: 4614 mov r4, r2 +100013d6: 2b0a cmp r3, #10 +100013d8: 4606 mov r6, r0 +100013da: d022 beq.n 10001422 +100013dc: 2c01 cmp r4, #1 +100013de: f04f 0e00 mov.w lr, #0 +100013e2: d00d beq.n 10001400 +100013e4: 4632 mov r2, r6 +100013e6: 2301 movs r3, #1 +100013e8: f812 cf01 ldrb.w ip, [r2, #1]! +100013ec: 4619 mov r1, r3 +100013ee: f1bc 0f0a cmp.w ip, #10 +100013f2: f103 0301 add.w r3, r3, #1 +100013f6: d020 beq.n 1000143a +100013f8: 429c cmp r4, r3 +100013fa: d1f5 bne.n 100013e8 +100013fc: 4574 cmp r4, lr +100013fe: dd05 ble.n 1000140c +10001400: 682b ldr r3, [r5, #0] +10001402: eba4 010e sub.w r1, r4, lr +10001406: eb06 000e add.w r0, r6, lr +1000140a: 4798 blx r3 +1000140c: 1931 adds r1, r6, r4 +1000140e: f811 3c01 ldrb.w r3, [r1, #-1] +10001412: f1a3 030d sub.w r3, r3, #13 +10001416: fab3 f383 clz r3, r3 +1000141a: 095b lsrs r3, r3, #5 +1000141c: 752b strb r3, [r5, #20] +1000141e: b002 add sp, #8 +10001420: bd70 pop {r4, r5, r6, pc} +10001422: 7d2b ldrb r3, [r5, #20] +10001424: 2b00 cmp r3, #0 +10001426: d1d9 bne.n 100013dc +10001428: 2102 movs r1, #2 +1000142a: 682b ldr r3, [r5, #0] +1000142c: 4813 ldr r0, [pc, #76] @ (1000147c ) +1000142e: 4798 blx r3 +10001430: 2c01 cmp r4, #1 +10001432: d0eb beq.n 1000140c +10001434: f04f 0e01 mov.w lr, #1 +10001438: e7d4 b.n 100013e4 +1000143a: f812 0c01 ldrb.w r0, [r2, #-1] +1000143e: 280d cmp r0, #13 +10001440: d0da beq.n 100013f8 +10001442: 458e cmp lr, r1 +10001444: eb06 000e add.w r0, r6, lr +10001448: eba1 010e sub.w r1, r1, lr +1000144c: da05 bge.n 1000145a +1000144e: e9cd 3200 strd r3, r2, [sp] +10001452: 682b ldr r3, [r5, #0] +10001454: 4798 blx r3 +10001456: e9dd 3200 ldrd r3, r2, [sp] +1000145a: e9cd 3200 strd r3, r2, [sp] +1000145e: 2102 movs r1, #2 +10001460: 682b ldr r3, [r5, #0] +10001462: 4806 ldr r0, [pc, #24] @ (1000147c ) +10001464: 4798 blx r3 +10001466: 9b00 ldr r3, [sp, #0] +10001468: 9a01 ldr r2, [sp, #4] +1000146a: 469e mov lr, r3 +1000146c: e7c4 b.n 100013f8 +1000146e: 4611 mov r1, r2 +10001470: 682b ldr r3, [r5, #0] +10001472: b002 add sp, #8 +10001474: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +10001478: 4718 bx r3 +1000147a: bf00 nop +1000147c: 10001a38 .word 0x10001a38 + +10001480 : +10001480: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10001484: b082 sub sp, #8 +10001486: 4690 mov r8, r2 +10001488: 461c mov r4, r3 +1000148a: 460d mov r5, r1 +1000148c: 4607 mov r7, r0 +1000148e: f7ff fc87 bl 10000da0 +10001492: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10001496: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +1000149a: 4a2e ldr r2, [pc, #184] @ (10001554 ) +1000149c: 1882 adds r2, r0, r2 +1000149e: f141 0300 adc.w r3, r1, #0 +100014a2: 4594 cmp ip, r2 +100014a4: eb76 0103 sbcs.w r1, r6, r3 +100014a8: bf3c itt cc +100014aa: 4662 movcc r2, ip +100014ac: 4633 movcc r3, r6 +100014ae: 482a ldr r0, [pc, #168] @ (10001558 ) +100014b0: f000 fa0a bl 100018c8 <__mutex_try_enter_block_until_veneer> +100014b4: 1c6b adds r3, r5, #1 +100014b6: 4682 mov sl, r0 +100014b8: d040 beq.n 1000153c +100014ba: b30c cbz r4, 10001500 +100014bc: 4e27 ldr r6, [pc, #156] @ (1000155c ) +100014be: 4b28 ldr r3, [pc, #160] @ (10001560 ) +100014c0: 681c ldr r4, [r3, #0] +100014c2: b1b4 cbz r4, 100014f2 +100014c4: f1b8 0f00 cmp.w r8, #0 +100014c8: d11c bne.n 10001504 +100014ca: f8df 809c ldr.w r8, [pc, #156] @ 10001568 +100014ce: e001 b.n 100014d4 +100014d0: 6924 ldr r4, [r4, #16] +100014d2: b174 cbz r4, 100014f2 +100014d4: 6823 ldr r3, [r4, #0] +100014d6: 2b00 cmp r3, #0 +100014d8: d0fa beq.n 100014d0 +100014da: f8d8 3000 ldr.w r3, [r8] +100014de: b10b cbz r3, 100014e4 +100014e0: 429c cmp r4, r3 +100014e2: d1f5 bne.n 100014d0 +100014e4: 4620 mov r0, r4 +100014e6: 462a mov r2, r5 +100014e8: 4639 mov r1, r7 +100014ea: 47b0 blx r6 +100014ec: 6924 ldr r4, [r4, #16] +100014ee: 2c00 cmp r4, #0 +100014f0: d1f0 bne.n 100014d4 +100014f2: f1ba 0f00 cmp.w sl, #0 +100014f6: d126 bne.n 10001546 +100014f8: 4628 mov r0, r5 +100014fa: b002 add sp, #8 +100014fc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001500: 4e18 ldr r6, [pc, #96] @ (10001564 ) +10001502: e7dc b.n 100014be +10001504: f04f 090a mov.w r9, #10 +10001508: f8df 805c ldr.w r8, [pc, #92] @ 10001568 +1000150c: e002 b.n 10001514 +1000150e: 6924 ldr r4, [r4, #16] +10001510: 2c00 cmp r4, #0 +10001512: d0ee beq.n 100014f2 +10001514: 6823 ldr r3, [r4, #0] +10001516: 2b00 cmp r3, #0 +10001518: d0f9 beq.n 1000150e +1000151a: f8d8 3000 ldr.w r3, [r8] +1000151e: b10b cbz r3, 10001524 +10001520: 42a3 cmp r3, r4 +10001522: d1f4 bne.n 1000150e +10001524: 462a mov r2, r5 +10001526: 4639 mov r1, r7 +10001528: 4620 mov r0, r4 +1000152a: 47b0 blx r6 +1000152c: 2201 movs r2, #1 +1000152e: 4620 mov r0, r4 +10001530: f10d 0107 add.w r1, sp, #7 +10001534: f88d 9007 strb.w r9, [sp, #7] +10001538: 47b0 blx r6 +1000153a: e7e8 b.n 1000150e +1000153c: 4638 mov r0, r7 +1000153e: f000 f995 bl 1000186c +10001542: 4605 mov r5, r0 +10001544: e7b9 b.n 100014ba +10001546: 4804 ldr r0, [pc, #16] @ (10001558 ) +10001548: f000 f9c2 bl 100018d0 <__mutex_exit_veneer> +1000154c: 4628 mov r0, r5 +1000154e: b002 add sp, #8 +10001550: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001554: 000f4240 .word 0x000f4240 +10001558: 200003f0 .word 0x200003f0 +1000155c: 100013c1 .word 0x100013c1 +10001560: 200005cc .word 0x200005cc +10001564: 100013b9 .word 0x100013b9 +10001568: 200005d0 .word 0x200005d0 + +1000156c : +1000156c: 4a08 ldr r2, [pc, #32] @ (10001590 ) +1000156e: 6813 ldr r3, [r2, #0] +10001570: b923 cbnz r3, 1000157c +10001572: e00a b.n 1000158a +10001574: f103 0210 add.w r2, r3, #16 +10001578: 691b ldr r3, [r3, #16] +1000157a: b133 cbz r3, 1000158a +1000157c: 4283 cmp r3, r0 +1000157e: d1f9 bne.n 10001574 +10001580: b929 cbnz r1, 1000158e +10001582: 6918 ldr r0, [r3, #16] +10001584: 6010 str r0, [r2, #0] +10001586: 6119 str r1, [r3, #16] +10001588: 4770 bx lr +1000158a: b101 cbz r1, 1000158e +1000158c: 6010 str r0, [r2, #0] +1000158e: 4770 bx lr +10001590: 200005cc .word 0x200005cc + +10001594 : +10001594: b508 push {r3, lr} +10001596: f000 f93f bl 10001818 +1000159a: 2001 movs r0, #1 +1000159c: bd08 pop {r3, pc} +1000159e: bf00 nop + +100015a0 <__wrap_putchar>: +100015a0: b5f0 push {r4, r5, r6, r7, lr} +100015a2: b083 sub sp, #12 +100015a4: 4606 mov r6, r0 +100015a6: f88d 0007 strb.w r0, [sp, #7] +100015aa: f7ff fbf9 bl 10000da0 +100015ae: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100015b2: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100015b6: 4a17 ldr r2, [pc, #92] @ (10001614 <__wrap_putchar+0x74>) +100015b8: 1882 adds r2, r0, r2 +100015ba: f141 0300 adc.w r3, r1, #0 +100015be: 4295 cmp r5, r2 +100015c0: eb74 0103 sbcs.w r1, r4, r3 +100015c4: bf3c itt cc +100015c6: 4623 movcc r3, r4 +100015c8: 462a movcc r2, r5 +100015ca: 4813 ldr r0, [pc, #76] @ (10001618 <__wrap_putchar+0x78>) +100015cc: f000 f97c bl 100018c8 <__mutex_try_enter_block_until_veneer> +100015d0: 4b12 ldr r3, [pc, #72] @ (1000161c <__wrap_putchar+0x7c>) +100015d2: 4607 mov r7, r0 +100015d4: 681c ldr r4, [r3, #0] +100015d6: b19c cbz r4, 10001600 <__wrap_putchar+0x60> +100015d8: 4d11 ldr r5, [pc, #68] @ (10001620 <__wrap_putchar+0x80>) +100015da: e001 b.n 100015e0 <__wrap_putchar+0x40> +100015dc: 6924 ldr r4, [r4, #16] +100015de: b17c cbz r4, 10001600 <__wrap_putchar+0x60> +100015e0: 6823 ldr r3, [r4, #0] +100015e2: 2b00 cmp r3, #0 +100015e4: d0fa beq.n 100015dc <__wrap_putchar+0x3c> +100015e6: 682b ldr r3, [r5, #0] +100015e8: b10b cbz r3, 100015ee <__wrap_putchar+0x4e> +100015ea: 429c cmp r4, r3 +100015ec: d1f6 bne.n 100015dc <__wrap_putchar+0x3c> +100015ee: 4620 mov r0, r4 +100015f0: 2201 movs r2, #1 +100015f2: f10d 0107 add.w r1, sp, #7 +100015f6: f7ff fee3 bl 100013c0 +100015fa: 6924 ldr r4, [r4, #16] +100015fc: 2c00 cmp r4, #0 +100015fe: d1ef bne.n 100015e0 <__wrap_putchar+0x40> +10001600: b917 cbnz r7, 10001608 <__wrap_putchar+0x68> +10001602: 4630 mov r0, r6 +10001604: b003 add sp, #12 +10001606: bdf0 pop {r4, r5, r6, r7, pc} +10001608: 4803 ldr r0, [pc, #12] @ (10001618 <__wrap_putchar+0x78>) +1000160a: f000 f961 bl 100018d0 <__mutex_exit_veneer> +1000160e: 4630 mov r0, r6 +10001610: b003 add sp, #12 +10001612: bdf0 pop {r4, r5, r6, r7, pc} +10001614: 000f4240 .word 0x000f4240 +10001618: 200003f0 .word 0x200003f0 +1000161c: 200005cc .word 0x200005cc +10001620: 200005d0 .word 0x200005d0 + +10001624 <__wrap_puts>: +10001624: b538 push {r3, r4, r5, lr} +10001626: 4604 mov r4, r0 +10001628: f000 f920 bl 1000186c +1000162c: 2301 movs r3, #1 +1000162e: 4605 mov r5, r0 +10001630: 461a mov r2, r3 +10001632: 4620 mov r0, r4 +10001634: 4629 mov r1, r5 +10001636: f7ff ff23 bl 10001480 +1000163a: 4b08 ldr r3, [pc, #32] @ (1000165c <__wrap_puts+0x38>) +1000163c: 681c ldr r4, [r3, #0] +1000163e: b12c cbz r4, 1000164c <__wrap_puts+0x28> +10001640: 6863 ldr r3, [r4, #4] +10001642: b12b cbz r3, 10001650 <__wrap_puts+0x2c> +10001644: 4798 blx r3 +10001646: 6924 ldr r4, [r4, #16] +10001648: 2c00 cmp r4, #0 +1000164a: d1f9 bne.n 10001640 <__wrap_puts+0x1c> +1000164c: 4628 mov r0, r5 +1000164e: bd38 pop {r3, r4, r5, pc} +10001650: 6924 ldr r4, [r4, #16] +10001652: 2c00 cmp r4, #0 +10001654: d1f4 bne.n 10001640 <__wrap_puts+0x1c> +10001656: 4628 mov r0, r5 +10001658: bd38 pop {r3, r4, r5, pc} +1000165a: bf00 nop +1000165c: 200005cc .word 0x200005cc + +10001660 : +10001660: f1b1 0c00 subs.w ip, r1, #0 +10001664: dd1e ble.n 100016a4 +10001666: 4a10 ldr r2, [pc, #64] @ (100016a8 ) +10001668: 4b10 ldr r3, [pc, #64] @ (100016ac ) +1000166a: 6812 ldr r2, [r2, #0] +1000166c: b510 push {r4, lr} +1000166e: 1ad3 subs r3, r2, r3 +10001670: fab3 f383 clz r3, r3 +10001674: 240d movs r4, #13 +10001676: f8df e038 ldr.w lr, [pc, #56] @ 100016b0 +1000167a: 095b lsrs r3, r3, #5 +1000167c: 1e41 subs r1, r0, #1 +1000167e: f93e e013 ldrsh.w lr, [lr, r3, lsl #1] +10001682: 448c add ip, r1 +10001684: f811 0f01 ldrb.w r0, [r1, #1]! +10001688: 4586 cmp lr, r0 +1000168a: d006 beq.n 1000169a +1000168c: 6993 ldr r3, [r2, #24] +1000168e: 069b lsls r3, r3, #26 +10001690: d4fc bmi.n 1000168c +10001692: 4561 cmp r1, ip +10001694: 6010 str r0, [r2, #0] +10001696: d1f5 bne.n 10001684 +10001698: bd10 pop {r4, pc} +1000169a: 6993 ldr r3, [r2, #24] +1000169c: 069b lsls r3, r3, #26 +1000169e: d4fc bmi.n 1000169a +100016a0: 6014 str r4, [r2, #0] +100016a2: e7f3 b.n 1000168c +100016a4: 4770 bx lr +100016a6: bf00 nop +100016a8: 20000600 .word 0x20000600 +100016ac: 40078000 .word 0x40078000 +100016b0: 200005fc .word 0x200005fc + +100016b4 : +100016b4: 4b24 ldr r3, [pc, #144] @ (10001748 ) +100016b6: f1b1 0c00 subs.w ip, r1, #0 +100016ba: b500 push {lr} +100016bc: f8d3 e000 ldr.w lr, [r3] +100016c0: dd2f ble.n 10001722 +100016c2: 2100 movs r1, #0 +100016c4: 4b21 ldr r3, [pc, #132] @ (1000174c ) +100016c6: 3801 subs r0, #1 +100016c8: 681a ldr r2, [r3, #0] +100016ca: 6993 ldr r3, [r2, #24] +100016cc: 06db lsls r3, r3, #27 +100016ce: d418 bmi.n 10001702 +100016d0: 3101 adds r1, #1 +100016d2: 6993 ldr r3, [r2, #24] +100016d4: 06db lsls r3, r3, #27 +100016d6: d4fc bmi.n 100016d2 +100016d8: 6813 ldr r3, [r2, #0] +100016da: 458c cmp ip, r1 +100016dc: f800 3f01 strb.w r3, [r0, #1]! +100016e0: d1f3 bne.n 100016ca +100016e2: f1be 0f00 cmp.w lr, #0 +100016e6: d009 beq.n 100016fc +100016e8: 2150 movs r1, #80 @ 0x50 +100016ea: 4613 mov r3, r2 +100016ec: 6391 str r1, [r2, #56] @ 0x38 +100016ee: f853 2f34 ldr.w r2, [r3, #52]! +100016f2: f002 0238 and.w r2, r2, #56 @ 0x38 +100016f6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016fa: 601a str r2, [r3, #0] +100016fc: 4661 mov r1, ip +100016fe: 4608 mov r0, r1 +10001700: bd00 pop {pc} +10001702: f1be 0f00 cmp.w lr, #0 +10001706: d009 beq.n 1000171c +10001708: 2050 movs r0, #80 @ 0x50 +1000170a: 4613 mov r3, r2 +1000170c: 6390 str r0, [r2, #56] @ 0x38 +1000170e: f853 2f34 ldr.w r2, [r3, #52]! +10001712: f002 0238 and.w r2, r2, #56 @ 0x38 +10001716: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000171a: 601a str r2, [r3, #0] +1000171c: b181 cbz r1, 10001740 +1000171e: 4608 mov r0, r1 +10001720: bd00 pop {pc} +10001722: f1be 0f00 cmp.w lr, #0 +10001726: d00b beq.n 10001740 +10001728: 4b08 ldr r3, [pc, #32] @ (1000174c ) +1000172a: 2150 movs r1, #80 @ 0x50 +1000172c: 681a ldr r2, [r3, #0] +1000172e: 4613 mov r3, r2 +10001730: 6391 str r1, [r2, #56] @ 0x38 +10001732: f853 2f34 ldr.w r2, [r3, #52]! +10001736: f002 0238 and.w r2, r2, #56 @ 0x38 +1000173a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000173e: 601a str r2, [r3, #0] +10001740: f06f 0102 mvn.w r1, #2 +10001744: e7db b.n 100016fe +10001746: bf00 nop +10001748: 20000598 .word 0x20000598 +1000174c: 20000600 .word 0x20000600 + +10001750 : +10001750: 4b05 ldr r3, [pc, #20] @ (10001768 ) +10001752: 681b ldr r3, [r3, #0] +10001754: b133 cbz r3, 10001764 +10001756: 2100 movs r1, #0 +10001758: 4a04 ldr r2, [pc, #16] @ (1000176c ) +1000175a: 4805 ldr r0, [pc, #20] @ (10001770 ) +1000175c: 6812 ldr r2, [r2, #0] +1000175e: 6800 ldr r0, [r0, #0] +10001760: 6391 str r1, [r2, #56] @ 0x38 +10001762: 4718 bx r3 +10001764: 4770 bx lr +10001766: bf00 nop +10001768: 20000598 .word 0x20000598 +1000176c: 20000600 .word 0x20000600 +10001770: 2000059c .word 0x2000059c + +10001774 : +10001774: 4b02 ldr r3, [pc, #8] @ (10001780 ) +10001776: 681a ldr r2, [r3, #0] +10001778: 6993 ldr r3, [r2, #24] +1000177a: 071b lsls r3, r3, #28 +1000177c: d4fc bmi.n 10001778 +1000177e: 4770 bx lr +10001780: 20000600 .word 0x20000600 + +10001784 : +10001784: b530 push {r4, r5, lr} +10001786: 4d1f ldr r5, [pc, #124] @ (10001804 ) +10001788: 4a1f ldr r2, [pc, #124] @ (10001808 ) +1000178a: f8d5 c000 ldr.w ip, [r5] +1000178e: 4c1f ldr r4, [pc, #124] @ (1000180c ) +10001790: 468e mov lr, r1 +10001792: 4594 cmp ip, r2 +10001794: bf14 ite ne +10001796: 2221 movne r2, #33 @ 0x21 +10001798: 2222 moveq r2, #34 @ 0x22 +1000179a: 6821 ldr r1, [r4, #0] +1000179c: b083 sub sp, #12 +1000179e: b110 cbz r0, 100017a6 +100017a0: b1a9 cbz r1, 100017ce +100017a2: b003 add sp, #12 +100017a4: bd30 pop {r4, r5, pc} +100017a6: 2900 cmp r1, #0 +100017a8: d0fb beq.n 100017a2 +100017aa: f8cc 0038 str.w r0, [ip, #56] @ 0x38 +100017ae: 4601 mov r1, r0 +100017b0: 9001 str r0, [sp, #4] +100017b2: 4610 mov r0, r2 +100017b4: 9200 str r2, [sp, #0] +100017b6: f7fe fdc3 bl 10000340 +100017ba: 4915 ldr r1, [pc, #84] @ (10001810 ) +100017bc: 9800 ldr r0, [sp, #0] +100017be: f7fe fe07 bl 100003d0 +100017c2: 9b01 ldr r3, [sp, #4] +100017c4: 4a13 ldr r2, [pc, #76] @ (10001814 ) +100017c6: 6023 str r3, [r4, #0] +100017c8: 6013 str r3, [r2, #0] +100017ca: b003 add sp, #12 +100017cc: bd30 pop {r4, r5, pc} +100017ce: 4b11 ldr r3, [pc, #68] @ (10001814 ) +100017d0: 6020 str r0, [r4, #0] +100017d2: 490f ldr r1, [pc, #60] @ (10001810 ) +100017d4: 4610 mov r0, r2 +100017d6: 9200 str r2, [sp, #0] +100017d8: f8c3 e000 str.w lr, [r3] +100017dc: f7fe fdc6 bl 1000036c +100017e0: 2101 movs r1, #1 +100017e2: 9800 ldr r0, [sp, #0] +100017e4: f7fe fdac bl 10000340 +100017e8: 682a ldr r2, [r5, #0] +100017ea: 2150 movs r1, #80 @ 0x50 +100017ec: 4613 mov r3, r2 +100017ee: 6391 str r1, [r2, #56] @ 0x38 +100017f0: f853 2f34 ldr.w r2, [r3, #52]! +100017f4: f002 0238 and.w r2, r2, #56 @ 0x38 +100017f8: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100017fc: 601a str r2, [r3, #0] +100017fe: b003 add sp, #12 +10001800: bd30 pop {r4, r5, pc} +10001802: bf00 nop +10001804: 20000600 .word 0x20000600 +10001808: 40078000 .word 0x40078000 +1000180c: 20000598 .word 0x20000598 +10001810: 10001751 .word 0x10001751 +10001814: 2000059c .word 0x2000059c + +10001818 : +10001818: b510 push {r4, lr} +1000181a: 490e ldr r1, [pc, #56] @ (10001854 ) +1000181c: 4c0e ldr r4, [pc, #56] @ (10001858 ) +1000181e: 480f ldr r0, [pc, #60] @ (1000185c ) +10001820: 4a0f ldr r2, [pc, #60] @ (10001860 ) +10001822: 4b10 ldr r3, [pc, #64] @ (10001864 ) +10001824: 7800 ldrb r0, [r0, #0] +10001826: 6021 str r1, [r4, #0] +10001828: 2000 movs r0, #0 +1000182a: 2102 movs r1, #2 +1000182c: 7812 ldrb r2, [r2, #0] +1000182e: 781b ldrb r3, [r3, #0] +10001830: f7fe fce4 bl 100001fc +10001834: 2102 movs r1, #2 +10001836: 2001 movs r0, #1 +10001838: f7fe fce0 bl 100001fc +1000183c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10001840: 6820 ldr r0, [r4, #0] +10001842: f7ff fae7 bl 10000e14 +10001846: e8bd 4010 ldmia.w sp!, {r4, lr} +1000184a: 2101 movs r1, #1 +1000184c: 4806 ldr r0, [pc, #24] @ (10001868 ) +1000184e: f7ff be8d b.w 1000156c +10001852: bf00 nop +10001854: 40070000 .word 0x40070000 +10001858: 20000600 .word 0x20000600 +1000185c: 10001a88 .word 0x10001a88 +10001860: 10001a84 .word 0x10001a84 +10001864: 10001a80 .word 0x10001a80 +10001868: 200003d8 .word 0x200003d8 + +1000186c : +1000186c: f020 0103 bic.w r1, r0, #3 +10001870: f010 0003 ands.w r0, r0, #3 +10001874: f1c0 0000 rsb r0, r0, #0 +10001878: f851 3b04 ldr.w r3, [r1], #4 +1000187c: f100 0c04 add.w ip, r0, #4 +10001880: ea4f 0ccc mov.w ip, ip, lsl #3 +10001884: f06f 0200 mvn.w r2, #0 +10001888: bf1c itt ne +1000188a: fa22 f20c lsrne.w r2, r2, ip +1000188e: 4313 orrne r3, r2 +10001890: f04f 0c01 mov.w ip, #1 +10001894: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001898: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +1000189c: eba3 020c sub.w r2, r3, ip +100018a0: ea22 0203 bic.w r2, r2, r3 +100018a4: ea12 12cc ands.w r2, r2, ip, lsl #7 +100018a8: bf04 itt eq +100018aa: f851 3b04 ldreq.w r3, [r1], #4 +100018ae: 3004 addeq r0, #4 +100018b0: d0f4 beq.n 1000189c +100018b2: f1c2 0100 rsb r1, r2, #0 +100018b6: ea02 0201 and.w r2, r2, r1 +100018ba: fab2 f282 clz r2, r2 +100018be: f1c2 021f rsb r2, r2, #31 +100018c2: eb00 00d2 add.w r0, r0, r2, lsr #3 +100018c6: 4770 bx lr + +100018c8 <__mutex_try_enter_block_until_veneer>: +100018c8: f85f f000 ldr.w pc, [pc] @ 100018cc <__mutex_try_enter_block_until_veneer+0x4> +100018cc: 200001f1 .word 0x200001f1 + +100018d0 <__mutex_exit_veneer>: +100018d0: f85f f000 ldr.w pc, [pc] @ 100018d4 <__mutex_exit_veneer+0x4> +100018d4: 20000229 .word 0x20000229 + +100018d8 <__memcpy_veneer>: +100018d8: f85f f000 ldr.w pc, [pc] @ 100018dc <__memcpy_veneer+0x4> +100018dc: 20000271 .word 0x20000271 + +100018e0 <__pre_init_runtime_init_bootrom_reset>: +100018e0: 100011e1 .... + +100018e4 <__pre_init_runtime_init_early_resets>: +100018e4: 10001159 Y... + +100018e8 <__pre_init_runtime_init_usb_power_down>: +100018e8: 10001189 .... + +100018ec <__pre_init_runtime_init_clocks>: +100018ec: 10001271 q... + +100018f0 <__pre_init_runtime_init_post_clock_resets>: +100018f0: 100011c1 .... + +100018f4 <__pre_init_runtime_init_boot_locks_reset>: +100018f4: 100010e1 .... + +100018f8 <__pre_init_runtime_init_spin_locks_reset>: +100018f8: 10001209 .... + +100018fc <__pre_init_runtime_init_bootrom_locking_enable>: +100018fc: 100010cd .... + +10001900 <__pre_init_runtime_init_mutex>: +10001900: 10000669 i... + +10001904 <__pre_init_runtime_init_install_ram_vector_table>: +10001904: 1000120d .... + +10001908 <__pre_init_runtime_init_default_alarm_pool>: +10001908: 100009ed .... + +1000190c <__pre_init_first_per_core_initializer>: +1000190c: 10001129 )... + +10001910 <__pre_init_runtime_init_per_core_bootrom_reset>: +10001910: 100011f5 .... + +10001914 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10001914: 100011a5 .... + +10001918 <__pre_init_spinlock_set_extexclall>: +10001918: 100002d9 .... + +1000191c <__pre_init_runtime_init_per_core_irq_priorities>: +1000191c: 10000301 .... + +Disassembly of section .data: + +20000110 : +20000110: 4603 mov r3, r0 +20000112: b500 push {lr} +20000114: 6802 ldr r2, [r0, #0] +20000116: f3ef 8c10 mrs ip, PRIMASK +2000011a: b672 cpsid i +2000011c: e8d2 efcf ldaexb lr, [r2] +20000120: 2001 movs r0, #1 +20000122: f1be 0f00 cmp.w lr, #0 +20000126: d1f9 bne.n 2000011c +20000128: e8c2 0f4e strexb lr, r0, [r2] +2000012c: f1be 0f00 cmp.w lr, #0 +20000130: d1f4 bne.n 2000011c +20000132: f3bf 8f5f dmb sy +20000136: f993 2004 ldrsb.w r2, [r3, #4] +2000013a: 2a00 cmp r2, #0 +2000013c: db09 blt.n 20000152 +2000013e: b101 cbz r1, 20000142 +20000140: 600a str r2, [r1, #0] +20000142: 2000 movs r0, #0 +20000144: 2200 movs r2, #0 +20000146: 681b ldr r3, [r3, #0] +20000148: e8c3 2f8f stlb r2, [r3] +2000014c: f38c 8810 msr PRIMASK, ip +20000150: bd00 pop {pc} +20000152: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +20000156: 6812 ldr r2, [r2, #0] +20000158: 2001 movs r0, #1 +2000015a: 711a strb r2, [r3, #4] +2000015c: e7f2 b.n 20000144 +2000015e: bf00 nop + +20000160 : +20000160: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000164: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} +20000168: 461f mov r7, r3 +2000016a: 680b ldr r3, [r1, #0] +2000016c: 4604 mov r4, r0 +2000016e: 4616 mov r6, r2 +20000170: 2500 movs r5, #0 +20000172: 4699 mov r9, r3 +20000174: f8df 8074 ldr.w r8, [pc, #116] @ 200001ec +20000178: 6823 ldr r3, [r4, #0] +2000017a: f3ef 8210 mrs r2, PRIMASK +2000017e: b672 cpsid i +20000180: e8d3 0fcf ldaexb r0, [r3] +20000184: 2101 movs r1, #1 +20000186: 2800 cmp r0, #0 +20000188: d1fa bne.n 20000180 +2000018a: e8c3 1f40 strexb r0, r1, [r3] +2000018e: 2800 cmp r0, #0 +20000190: d1f6 bne.n 20000180 +20000192: f3bf 8f5f dmb sy +20000196: f994 3004 ldrsb.w r3, [r4, #4] +2000019a: 6821 ldr r1, [r4, #0] +2000019c: 2b00 cmp r3, #0 +2000019e: db1b blt.n 200001d8 +200001a0: f898 3000 ldrb.w r3, [r8] +200001a4: b2db uxtb r3, r3 +200001a6: e8c1 5f8f stlb r5, [r1] +200001aa: f382 8810 msr PRIMASK, r2 +200001ae: f898 2000 ldrb.w r2, [r8] +200001b2: 429a cmp r2, r3 +200001b4: d008 beq.n 200001c8 +200001b6: 4630 mov r0, r6 +200001b8: 4639 mov r1, r7 +200001ba: f000 f8d1 bl 20000360 <__best_effort_wfe_or_timeout_veneer> +200001be: 2800 cmp r0, #0 +200001c0: d0da beq.n 20000178 +200001c2: 2000 movs r0, #0 +200001c4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} +200001c8: bf20 wfe +200001ca: 4630 mov r0, r6 +200001cc: 4639 mov r1, r7 +200001ce: f000 f8c7 bl 20000360 <__best_effort_wfe_or_timeout_veneer> +200001d2: 2800 cmp r0, #0 +200001d4: d0d0 beq.n 20000178 +200001d6: e7f4 b.n 200001c2 +200001d8: 2300 movs r3, #0 +200001da: f884 9004 strb.w r9, [r4, #4] +200001de: e8c1 3f8f stlb r3, [r1] +200001e2: f382 8810 msr PRIMASK, r2 +200001e6: 2001 movs r0, #1 +200001e8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} +200001ec: 20000605 .word 0x20000605 + +200001f0 : +200001f0: b570 push {r4, r5, r6, lr} +200001f2: b082 sub sp, #8 +200001f4: a901 add r1, sp, #4 +200001f6: 4606 mov r6, r0 +200001f8: 4614 mov r4, r2 +200001fa: 461d mov r5, r3 +200001fc: f7ff ff88 bl 20000110 +20000200: b938 cbnz r0, 20000212 +20000202: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000 +20000206: f99d 2004 ldrsb.w r2, [sp, #4] +2000020a: f993 3000 ldrsb.w r3, [r3] +2000020e: 429a cmp r2, r3 +20000210: d101 bne.n 20000216 +20000212: b002 add sp, #8 +20000214: bd70 pop {r4, r5, r6, pc} +20000216: 4622 mov r2, r4 +20000218: 462b mov r3, r5 +2000021a: 4630 mov r0, r6 +2000021c: b002 add sp, #8 +2000021e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +20000222: f7ff bf9d b.w 20000160 +20000226: bf00 nop + +20000228 : +20000228: 6803 ldr r3, [r0, #0] +2000022a: f3ef 8110 mrs r1, PRIMASK +2000022e: b672 cpsid i +20000230: e8d3 cfcf ldaexb ip, [r3] +20000234: 2201 movs r2, #1 +20000236: f1bc 0f00 cmp.w ip, #0 +2000023a: d1f9 bne.n 20000230 +2000023c: e8c3 2f4c strexb ip, r2, [r3] +20000240: f1bc 0f00 cmp.w ip, #0 +20000244: d1f4 bne.n 20000230 +20000246: f3bf 8f5f dmb sy +2000024a: f04f 0cff mov.w ip, #255 @ 0xff +2000024e: 4a07 ldr r2, [pc, #28] @ (2000026c ) +20000250: f880 c004 strb.w ip, [r0, #4] +20000254: 7813 ldrb r3, [r2, #0] +20000256: 3301 adds r3, #1 +20000258: 7013 strb r3, [r2, #0] +2000025a: 2300 movs r3, #0 +2000025c: 6802 ldr r2, [r0, #0] +2000025e: e8c2 3f8f stlb r3, [r2] +20000262: f381 8810 msr PRIMASK, r1 +20000266: bf40 sev +20000268: 4770 bx lr +2000026a: bf00 nop +2000026c: 20000605 .word 0x20000605 + +20000270 : +20000270: 4684 mov ip, r0 +20000272: ea41 0300 orr.w r3, r1, r0 +20000276: f013 0303 ands.w r3, r3, #3 +2000027a: d149 bne.n 20000310 +2000027c: 3a40 subs r2, #64 @ 0x40 +2000027e: d323 bcc.n 200002c8 +20000280: 680b ldr r3, [r1, #0] +20000282: 6003 str r3, [r0, #0] +20000284: 684b ldr r3, [r1, #4] +20000286: 6043 str r3, [r0, #4] +20000288: 688b ldr r3, [r1, #8] +2000028a: 6083 str r3, [r0, #8] +2000028c: 68cb ldr r3, [r1, #12] +2000028e: 60c3 str r3, [r0, #12] +20000290: 690b ldr r3, [r1, #16] +20000292: 6103 str r3, [r0, #16] +20000294: 694b ldr r3, [r1, #20] +20000296: 6143 str r3, [r0, #20] +20000298: 698b ldr r3, [r1, #24] +2000029a: 6183 str r3, [r0, #24] +2000029c: 69cb ldr r3, [r1, #28] +2000029e: 61c3 str r3, [r0, #28] +200002a0: 6a0b ldr r3, [r1, #32] +200002a2: 6203 str r3, [r0, #32] +200002a4: 6a4b ldr r3, [r1, #36] @ 0x24 +200002a6: 6243 str r3, [r0, #36] @ 0x24 +200002a8: 6a8b ldr r3, [r1, #40] @ 0x28 +200002aa: 6283 str r3, [r0, #40] @ 0x28 +200002ac: 6acb ldr r3, [r1, #44] @ 0x2c +200002ae: 62c3 str r3, [r0, #44] @ 0x2c +200002b0: 6b0b ldr r3, [r1, #48] @ 0x30 +200002b2: 6303 str r3, [r0, #48] @ 0x30 +200002b4: 6b4b ldr r3, [r1, #52] @ 0x34 +200002b6: 6343 str r3, [r0, #52] @ 0x34 +200002b8: 6b8b ldr r3, [r1, #56] @ 0x38 +200002ba: 6383 str r3, [r0, #56] @ 0x38 +200002bc: 6bcb ldr r3, [r1, #60] @ 0x3c +200002be: 63c3 str r3, [r0, #60] @ 0x3c +200002c0: 3040 adds r0, #64 @ 0x40 +200002c2: 3140 adds r1, #64 @ 0x40 +200002c4: 3a40 subs r2, #64 @ 0x40 +200002c6: d2db bcs.n 20000280 +200002c8: 3230 adds r2, #48 @ 0x30 +200002ca: d30b bcc.n 200002e4 +200002cc: 680b ldr r3, [r1, #0] +200002ce: 6003 str r3, [r0, #0] +200002d0: 684b ldr r3, [r1, #4] +200002d2: 6043 str r3, [r0, #4] +200002d4: 688b ldr r3, [r1, #8] +200002d6: 6083 str r3, [r0, #8] +200002d8: 68cb ldr r3, [r1, #12] +200002da: 60c3 str r3, [r0, #12] +200002dc: 3010 adds r0, #16 +200002de: 3110 adds r1, #16 +200002e0: 3a10 subs r2, #16 +200002e2: d2f3 bcs.n 200002cc +200002e4: 320c adds r2, #12 +200002e6: d305 bcc.n 200002f4 +200002e8: f851 3b04 ldr.w r3, [r1], #4 +200002ec: f840 3b04 str.w r3, [r0], #4 +200002f0: 3a04 subs r2, #4 +200002f2: d2f9 bcs.n 200002e8 +200002f4: 3204 adds r2, #4 +200002f6: d008 beq.n 2000030a +200002f8: 07d2 lsls r2, r2, #31 +200002fa: bf1c itt ne +200002fc: f811 3b01 ldrbne.w r3, [r1], #1 +20000300: f800 3b01 strbne.w r3, [r0], #1 +20000304: d301 bcc.n 2000030a +20000306: 880b ldrh r3, [r1, #0] +20000308: 8003 strh r3, [r0, #0] +2000030a: 4660 mov r0, ip +2000030c: 4770 bx lr +2000030e: bf00 nop +20000310: 2a08 cmp r2, #8 +20000312: d313 bcc.n 2000033c +20000314: 078b lsls r3, r1, #30 +20000316: d0b1 beq.n 2000027c +20000318: f010 0303 ands.w r3, r0, #3 +2000031c: d0ae beq.n 2000027c +2000031e: f1c3 0304 rsb r3, r3, #4 +20000322: 1ad2 subs r2, r2, r3 +20000324: 07db lsls r3, r3, #31 +20000326: bf1c itt ne +20000328: f811 3b01 ldrbne.w r3, [r1], #1 +2000032c: f800 3b01 strbne.w r3, [r0], #1 +20000330: d3a4 bcc.n 2000027c +20000332: f831 3b02 ldrh.w r3, [r1], #2 +20000336: f820 3b02 strh.w r3, [r0], #2 +2000033a: e79f b.n 2000027c +2000033c: 3a04 subs r2, #4 +2000033e: d3d9 bcc.n 200002f4 +20000340: 3a01 subs r2, #1 +20000342: f811 3b01 ldrb.w r3, [r1], #1 +20000346: f800 3b01 strb.w r3, [r0], #1 +2000034a: d2f9 bcs.n 20000340 +2000034c: 780b ldrb r3, [r1, #0] +2000034e: 7003 strb r3, [r0, #0] +20000350: 784b ldrb r3, [r1, #1] +20000352: 7043 strb r3, [r0, #1] +20000354: 788b ldrb r3, [r1, #2] +20000356: 7083 strb r3, [r0, #2] +20000358: 4660 mov r0, ip +2000035a: 4770 bx lr +2000035c: 0000 movs r0, r0 + ... + +20000360 <__best_effort_wfe_or_timeout_veneer>: +20000360: f85f f000 ldr.w pc, [pc] @ 20000364 <__best_effort_wfe_or_timeout_veneer+0x4> +20000364: 10000c41 .word 0x10000c41 + +20000368 : +20000368: 00000010 .... + +2000036c : +2000036c: 00000000 .word 0x00000000 +20000370: 00010000 .word 0x00010000 + ... +2000037c: 00020000 .word 0x00020000 + ... +20000388: 00030000 .word 0x00030000 + ... +20000394: 00ff0000 .word 0x00ff0000 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b/WEEK01/0x0001a_stack/build/0x0001a_stack.uf2 differ diff --git a/WEEK01/0x0001a_stack/pico_sdk_import.cmake b/WEEK01/0x0001a_stack/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK01/0x0001a_stack/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK01/WEEK01-SLIDES.pdf b/WEEK01/WEEK01-SLIDES.pdf new file mode 100644 index 0000000..935ca43 Binary files /dev/null and b/WEEK01/WEEK01-SLIDES.pdf differ diff --git a/WEEK01/WEEK01.md b/WEEK01/WEEK01.md new file mode 100644 index 0000000..c42b57e --- /dev/null +++ b/WEEK01/WEEK01.md @@ -0,0 +1,755 @@ +# Week 1: Introduction and Overview of Embedded Reverse Engineering: Ethics, Scoping, and Basic Concepts + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this week, you will be able to: + +- Understand what a microcontroller is and how it works +- Know the basic registers of the ARM Cortex-M33 processor +- Understand memory layout (Flash vs RAM) and why it matters +- Understand how the stack works in embedded systems +- Set up and connect GDB to your Pico 2 for debugging +- Use Ghidra for static analysis of your binary +- Read basic ARM assembly instructions and understand what they do + +--- + +## Part 1: Understanding the Basics + +### What is a Microcontroller? + +Think of a microcontroller as a tiny computer on a single chip. Just like your laptop has a processor, memory, and storage, a microcontroller has all of these packed into one small chip. The **RP2350** is the microcontroller chip that powers the **Raspberry Pi Pico 2**. + +### What is the ARM Cortex-M33? + +The RP2350 has two "brains" inside it - we call these **cores**. One brain uses ARM Cortex-M33 instructions, and the other can use RISC-V instructions. In this course, we'll focus on the **ARM Cortex-M33** core because it's more commonly used in the industry. + +### What is Reverse Engineering? + +Reverse engineering is like being a detective for code. Instead of writing code and compiling it, we take compiled code (the 1s and 0s that the computer actually runs) and figure out what it does. This is useful for: + +- Understanding how things work +- Finding bugs or security issues +- Learning how software interacts with hardware + +--- + +## Part 2: Understanding Processor Registers + +### What is a Register? + +A **register** is like a tiny, super-fast storage box inside the processor. The processor uses registers to hold numbers while it's doing calculations. Think of them like the short-term memory your brain uses when doing math in your head. + +### The ARM Cortex-M33 Registers + +The ARM Cortex-M33 has several important registers: + +| Register | Also Called | Purpose | +| ------------ | -------------------- | ------------------------------------------- | +| `r0` - `r12` | General Purpose | Store numbers, pass data between functions | +| `r13` | SP (Stack Pointer) | Keeps track of where we are in the stack | +| `r14` | LR (Link Register) | Remembers where to go back after a function | +| `r15` | PC (Program Counter) | Points to the next instruction to run | + +##### General Purpose Registers (`r0` - `r12`) + +These 13 registers are your "scratch paper." When the processor needs to add two numbers, subtract, or do any calculation, it uses these registers to hold the values. + +**Example:** If you want to add 5 + 3: + +1. Put 5 in `r0` +2. Put 3 in `r1` +3. Add them and store the result (8) in `r2` + +##### The Stack Pointer (`r13` / SP) + +The **stack** is a special area of memory that works like a stack of plates: + +- When you add something, you put it on top (called a **PUSH**) +- When you remove something, you take it from the top (called a **POP**) + +The Stack Pointer always points to the top of this stack. On ARM systems, the stack **grows downward** in memory. This means when you push something onto the stack, the address number gets smaller! + +The two Arm ABI documents we verified give the formal proof for these rules. In AAPCS32, page 17 defines the core register roles used by the base procedure call standard: `r13` is `SP`, `r14` is `LR`, `r15` is `PC`, `r0`-`r3` are argument and scratch registers, and `r4`-`r11` are the longer-lived variable registers. In Advisory Note 132, page 7 states that `SP` must be aligned to a multiple of 8 at every conforming call site and must already be 8-byte aligned when control first enters conforming code. That is why compiler-generated prologues often push an even number of registers, such as `push {r3, lr}`, to preserve both saved state and the required ABI stack alignment. + +``` +Higher Memory Address (0x20082000) ++------------------+ +| | ← Stack starts here (empty) ++------------------+ +| Pushed Item 1 | ← SP points here after 1 push ++------------------+ +| Pushed Item 2 | ← SP points here after 2 pushes ++------------------+ +Lower Memory Address (0x20081FF8) +``` + +##### The Link Register (`r14` / LR) + +When you call a function, the processor needs to remember where to come back to. The Link Register stores this "return address." + +**Example:** +``` +main() calls print_hello() + ↓ +LR = address right after the call in main() + ↓ +print_hello() runs + ↓ +print_hello() finishes, looks at LR + ↓ +Jumps back to main() at the address stored in LR +``` + +##### The Program Counter (`r15` / PC) + +The Program Counter always points to the **next instruction** the processor will execute. It's like your finger following along as you read a book - it always points to where you are. + +--- + +## Part 3: Understanding Memory Layout + +### XIP - Execute In Place + +The RP2350 uses something called **XIP (Execute In Place)**. This means the processor can run code directly from the flash memory (where your program is stored) without copying it to RAM first. + +**Key Memory Address:** `0x10000000` + +This is where your program code starts in flash memory. Remember this address - we'll use it a lot! + +### Memory Map Overview + +``` ++-------------------------------------+ +| Flash Memory (XIP) | +| Starts at: 0x10000000 | +| Contains: Your program code | ++-------------------------------------+ +| RAM | +| Starts at: 0x20000000 | +| Contains: Stack, Heap, Variables | ++-------------------------------------+ +``` + +### Stack vs Heap + +| Stack | Heap | +| ---------------------------------------- | ---------------------------------- | +| Automatic memory management | Manual memory management | +| Fast | Slower | +| Limited size | More flexible size | +| Used for function calls, local variables | Used for dynamic memory allocation | +| Grows downward | Grows upward | + +--- + +## Part 3.5: Reviewing Our Hello World Code + +Before we start debugging, let's understand the code we'll be working with. Here's our `0x0001_hello-world.c` program: + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} +``` + +### Breaking Down the Code + +##### The Includes + +```c +#include +#include "pico/stdlib.h" +``` + +- **``** - This is the standard input/output library. It gives us access to the `printf()` function that lets us print text. +- **`"pico/stdlib.h"`** - This is the Pico SDK's standard library. It provides essential functions for working with the Raspberry Pi Pico hardware. + +##### The Main Function + +```c +int main(void) { +``` + +Every C program starts running from the `main()` function. The `void` means it takes no arguments, and `int` means it returns an integer (though our program never actually returns). + +##### Initializing Standard I/O + +```c +stdio_init_all(); +``` + +This function initializes all the standard I/O (input/output) for the Pico. It sets up: + +- **USB CDC** (so you can see output when connected to a computer via USB) +- **UART** (serial communication pins) + +Without this line, `printf()` wouldn't have anywhere to send its output! + +##### The Infinite Loop + +```c +while (true) + printf("hello, world\r\n"); +``` + +- **`while (true)`** - This creates an infinite loop. The program will keep running forever (or until you reset/power off the Pico). +- **`printf("hello, world\r\n")`** - This prints the text "hello, world" followed by a carriage return (`\r`) and newline (`\n`). + +> Tip: **Why `\r\n` instead of just `\n`?** +> +> In embedded systems, we often use both carriage return (`\r`) and newline (`\n`) together. The `\r` moves the cursor back to the beginning of the line, and `\n` moves to the next line. This ensures proper display across different terminal programs. + +### What Happens When This Runs? + +1. **Power on** - The Pico boots up and starts executing code from flash memory +2. **`stdio_init_all()`** - Sets up USB and/or UART for communication +3. **Infinite loop begins** - The program enters the `while(true)` loop +4. **Print forever** - "hello, world" is sent over and over as fast as possible + +### Why This Code is Perfect for Learning + +This simple program is ideal for reverse engineering practice because: + +- It has a clear, recognizable function call (`printf`) +- It has an infinite loop we can observe +- It's small enough to understand completely +- It demonstrates real hardware interaction (USB/UART output) + +When we debug this code, we'll be able to see how the C code translates to ARM assembly instructions! + +### Compiling and Flashing to the Pico 2 + +Now that we understand the code, let's get it running on our hardware: + +##### Step 1: Compile the Code + +In VS Code, look for the **Compile** button in the status bar at the bottom of the window. This is provided by the Raspberry Pi Pico extension. Click it to compile your project. + +The extension will run CMake and build your code, creating a `.uf2` file that can be loaded onto the Pico 2. + +##### Step 2: Put the Pico 2 in Flash Loading Mode + +To flash new code to your Pico 2, you need to put it into **BOOTSEL mode**: + +1. **Press and hold** the right-most button on your breadboard (the BOOTSEL button) +2. **While holding BOOTSEL**, press the white **Reset** button +3. **Release the Reset button** first +4. **Then release the BOOTSEL button** + +When done correctly, your Pico 2 will appear as a USB mass storage device (like a flash drive) on your computer. This means it's ready to receive new firmware! + +> Tip: **Tip:** You'll see a drive called "RP2350" appear in your file explorer when the Pico 2 is in flash loading mode. + +##### Step 3: Flash and Run + +Back in VS Code, click the **Run** button in the status bar. The extension will: + +1. Copy the compiled `.uf2` file to the Pico 2 +2. The Pico 2 will automatically reboot and start running your code + +Once flashed, your Pico 2 will immediately start executing the hello-world program, printing "hello, world" continuously when we open PuTTY! + +--- + +## Part 4: Dynamic Analysis with GDB + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. GDB (GNU Debugger) installed +3. OpenOCD or another debug probe connection +4. The sample "hello-world" binary loaded on your Pico 2 + +### Connecting to Your Pico 2 with OpenOCD + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +### Connecting to Your Pico 2 with GDB + +Open another terminal and start GDB with your binary: + +```cmd +arm-none-eabi-gdb build\0x0001_hello-world.elf +``` + +Connect to your target: + +```cmd +(gdb) target extended-remote :3333 +(gdb) monitor reset halt +``` + +### Basic GDB Commands: Your First Steps + +Now that we're connected, let's learn three essential GDB commands that you'll use constantly in embedded reverse engineering. + +##### Setting a Breakpoint with `b main` + +A **breakpoint** tells the debugger to pause execution when it reaches a specific point. Let's set one at our `main` function: + +```gdb +(gdb) b main +Breakpoint 1 at 0x10000234: file ../0x0001_hello-world.c, line 5. +``` + +**What this tells us:** + +- GDB found our `main` function +- It's located at address `0x10000234` in flash memory +- The source file and line number are shown (because we have debug symbols) + +Now let's run to that breakpoint: + +```gdb +(gdb) c +Continuing. + +Breakpoint 1, main () at ../0x0001_hello-world.c:5 +5 stdio_init_all(); +``` + +The program has stopped right at the beginning of `main`! + +##### Disassembling with `disas` + +The `disas` (disassemble) command shows us the assembly instructions for the current function: + +```gdb +(gdb) disas +Dump of assembler code for function main: +=> 0x10000234 <+0>: push {r3, lr} + 0x10000236 <+2>: bl 0x1000156c + 0x1000023a <+6>: ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c <+8>: bl 0x100015fc <__wrap_puts> + 0x10000240 <+12>: b.n 0x1000023a + 0x10000242 <+14>: nop + 0x10000244 <+16>: adds r4, r1, r7 + 0x10000246 <+18>: asrs r0, r0, #32 +End of assembler dump. +``` + +**Understanding the output:** + +- The `=>` arrow shows where we're currently stopped +- Each line shows: `address : instruction operands` +- We can see the calls to `stdio_init_all` and `__wrap_puts` (printf was optimized to puts) +- The `b.n 0x1000023a` at the end is our infinite loop - it jumps back to reload the string! + +##### Viewing ELF Sections with `info files` and `maintenance info sections` + +To see how the ELF is laid out in memory, use: + +```gdb +(gdb) info files +Symbols from "C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0001_hello-world\build\0x0001_hello-world.elf". +Extended remote target using gdb-specific protocol: + `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0001_hello-world\build\0x0001_hello-world.elf', file type elf32-littlearm. + Entry point: 0x1000014c + 0x10000000 - 0x100019cc is .text + 0x100019cc - 0x10001b18 is .rodata + 0x10001b18 - 0x10001b20 is .ARM.exidx + 0x10001b20 - 0x10001b4c is .binary_info + 0x20000000 - 0x20000110 is .ram_vector_table + 0x20000110 - 0x200002ac is .data + 0x200002ac - 0x200002ac is .tdata + 0x200002ac - 0x200002ac is .tbss + 0x200002b0 - 0x200004d8 is .bss + 0x200004d8 - 0x20000cd8 is .heap + 0x20081000 - 0x20081800 is .stack_dummy + 0x10001ce8 - 0x10001cfc is .flash_end + While running this, GDB does not access memory from... +Local exec file: + `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0001_hello-world\build\0x0001_hello-world.elf', file type elf32-littlearm. + Entry point: 0x1000014c + 0x10000000 - 0x100019cc is .text + 0x100019cc - 0x10001b18 is .rodata + 0x10001b18 - 0x10001b20 is .ARM.exidx + 0x10001b20 - 0x10001b4c is .binary_info + 0x20000000 - 0x20000110 is .ram_vector_table + 0x20000110 - 0x200002ac is .data + 0x200002ac - 0x200002ac is .tdata + 0x200002ac - 0x200002ac is .tbss + 0x200002b0 - 0x200004d8 is .bss + 0x200004d8 - 0x20000cd8 is .heap + 0x20081000 - 0x20081800 is .stack_dummy + 0x10001ce8 - 0x10001cfc is .flash_end +(gdb) maintenance info sections +Exec file: `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0001_hello-world\build\0x0001_hello-world.elf', file type elf32-littlearm. + [0] 0x10000000->0x100019cc at 0x00001000: .text ALLOC LOAD READONLY CODE HAS_CONTENTS + [1] 0x100019cc->0x10001b18 at 0x000029cc: .rodata ALLOC LOAD READONLY DATA HAS_CONTENTS + [2] 0x10001b18->0x10001b20 at 0x00002b18: .ARM.exidx ALLOC LOAD READONLY DATA HAS_CONTENTS + [3] 0x10001b20->0x10001b4c at 0x00002b20: .binary_info ALLOC LOAD READONLY DATA HAS_CONTENTS + [4] 0x20000000->0x20000110 at 0x00004000: .ram_vector_table ALLOC + [5] 0x20000110->0x20000110 at 0x00003cfc: .uninitialized_data HAS_CONTENTS + [6] 0x20000110->0x200002ac at 0x00003110: .data ALLOC LOAD READONLY CODE HAS_CONTENTS + [7] 0x200002ac->0x200002ac at 0x00003cfc: .tdata ALLOC LOAD DATA HAS_CONTENTS + [8] 0x200002ac->0x200002ac at 0x00000000: .tbss ALLOC + [9] 0x200002b0->0x200004d8 at 0x000042b0: .bss ALLOC + [10] 0x200004d8->0x20000cd8 at 0x000044d8: .heap ALLOC READONLY + [11] 0x20080000->0x20080000 at 0x00003cfc: .scratch_x HAS_CONTENTS + [12] 0x20081000->0x20081000 at 0x00003cfc: .scratch_y HAS_CONTENTS + [13] 0x20081000->0x20081800 at 0x00004000: .stack_dummy ALLOC READONLY + [14] 0x10001ce8->0x10001cfc at 0x00003ce8: .flash_end ALLOC LOAD READONLY DATA HAS_CONTENTS + [15] 0x0000->0x0034 at 0x00003cfc: .ARM.attributes READONLY HAS_CONTENTS + [16] 0x0000->0x0045 at 0x00003d30: .comment READONLY HAS_CONTENTS + [17] 0x0000->0x2069a at 0x00003d75: .debug_info READONLY HAS_CONTENTS + [18] 0x0000->0x54ff at 0x0002440f: .debug_abbrev READONLY HAS_CONTENTS + [19] 0x0000->0x0af0 at 0x00029910: .debug_aranges READONLY HAS_CONTENTS + [20] 0x0000->0x2f86 at 0x0002a400: .debug_rnglists READONLY HAS_CONTENTS + [21] 0x0000->0x15526 at 0x0002d386: .debug_line READONLY HAS_CONTENTS + [22] 0x0000->0x56a7 at 0x000428ac: .debug_str READONLY HAS_CONTENTS + [23] 0x0000->0x1ed4 at 0x00047f54: .debug_frame READONLY HAS_CONTENTS + [24] 0x0000->0xffd1 at 0x00049e28: .debug_loclists READONLY HAS_CONTENTS + [25] 0x0000->0x0178 at 0x00059df9: .debug_line_str READONLY HAS_CONTENTS +``` + +**What each section means:** + +| Section | Purpose | +| ------- | ------- | +| `.text` | Executable machine code (your functions/instructions). | +| `.rodata` | Read-only constants (strings like `"hello, world"`, lookup tables, const data). | +| `.ARM.exidx` | ARM exception unwind index used for stack unwinding/backtraces. | +| `.binary_info` | Pico metadata used by tools (program identity/build information). | +| `.ram_vector_table` | Interrupt vector table copied/placed in RAM for runtime use. | +| `.uninitialized_data` | Deliberately non-zeroed RAM region that can survive certain reset paths. | +| `.data` | Initialized global/static variables in RAM (initial values come from flash). | +| `.tdata` | Initialized thread-local storage data (often empty in simple bare-metal apps). | +| `.tbss` | Zero-initialized thread-local storage (often empty). | +| `.bss` | Zero-initialized global/static variables in RAM. | +| `.heap` | Heap allocation region (`malloc/new`) reserved in RAM. | +| `.scratch_x` | RP2 scratch RAM bank X section (core-local/low-contention placement). | +| `.scratch_y` | RP2 scratch RAM bank Y section (core-local/low-contention placement). | +| `.stack_dummy` | Linker-reserved stack range marker used to size/place the stack. | +| `.flash_end` | Marker/metadata near the logical end of flash image region. | +| `.ARM.attributes` | ARM build attributes (ABI/architecture metadata for tools/linkers). | +| `.comment` | Compiler/build comment strings (toolchain identification). | +| `.debug_info` | Main DWARF debug database (types, variables, symbols, scopes). | +| `.debug_abbrev` | Abbreviation table referenced by `.debug_info`. | +| `.debug_aranges` | Address-to-compilation-unit lookup acceleration data. | +| `.debug_rnglists` | DWARF range lists for non-contiguous code/data ranges. | +| `.debug_line` | Address-to-source-line mapping used for stepping/breakpoints. | +| `.debug_str` | Shared string pool used by DWARF debug sections. | +| `.debug_frame` | Call frame information used for unwinding stack frames. | +| `.debug_loclists` | Variable location lists (where variables live over PC ranges). | +| `.debug_line_str` | Extra string pool used by `.debug_line` data. | + +> Tip: **Practical rule:** For reverse engineering runtime behavior, focus first on `.text`, `.rodata`, `.data`, `.bss`, heap/stack regions, and the vector table. Debug sections are for source-level mapping and symbol intelligence. + +**Fast interpretation checklist (use this every time):** + +1. **Find where code executes**: Verify `.text` starts at `0x10000000` (XIP flash) and note its end. +2. **Find immutable constants**: Use `.rodata` for strings/tables; cross-reference these addresses in disassembly. +3. **Find initialized RAM state**: `.data` lives in RAM at runtime, but its initial bytes come from flash. +4. **Find zeroed runtime state**: `.bss` is RAM that startup code clears to zero before `main`. +5. **Find interrupt control point**: Confirm `.ram_vector_table` location for exception/IRQ handler mapping. +6. **Bound dynamic memory**: Note `.heap` range so you can classify allocator activity vs static data. +7. **Bound call-stack activity**: Use `.stack_dummy` as linker stack reservation, then track live stack with `$sp`. +8. **Separate runtime vs debug-only sections**: `.debug_*`, `.comment`, and `.ARM.attributes` help tooling, not execution. +9. **Correlate any suspicious address quickly**: Flash/XIP (`0x100...`) usually code/const; SRAM (`0x200...`) usually data/stack/heap. +10. **Validate in memory**: After identifying a section, inspect it with `x` in GDB to confirm actual bytes/instructions. + +##### Viewing Registers with `i r` + +The `i r` (info registers) command shows the current state of all CPU registers: + +```gdb +(gdb) i r +r0 0x0 0 +r1 0x10000235 268436021 +r2 0x80808080 -2139062144 +r3 0xe000ed08 -536810232 +r4 0x100001d0 268435920 +r5 0x88526891 -2007865199 +r6 0x4f54710 83183376 +r7 0x400e0014 1074659348 +r8 0x43280035 1126694965 +r9 0x0 0 +r10 0x10000000 268435456 +r11 0x62707361 1651536737 +r12 0xed07f600 -318245376 +sp 0x20082000 0x20082000 +lr 0x1000018f 268435855 +pc 0x10000234 0x10000234
+xpsr 0x69000000 1761607680 +``` + +**Key registers to watch:** + +| Register | Value | Meaning | +| -------- | ------------ | ----------------------------------------------- | +| `pc` | `0x10000234` | Program Counter - we're at the start of `main` | +| `sp` | `0x20081fc8` | Stack Pointer - top of our stack in RAM | +| `lr` | `0x100002d5` | Link Register - where we return after `main` | +| `r0-r3` | Various | Will hold function arguments and return values | + +> Tip: **Tip:** You can also use `i r pc sp lr` to show only specific registers you care about. + +### Quick Reference: Essential GDB Commands + +| Command | Short Form | What It Does | +| --------------------- | ---------- | ------------------------------------ | +| `break main` | `b main` | Set a breakpoint at main | +| `continue` | `c` | Continue execution until breakpoint | +| `disassemble` | `disas` | Show assembly for current function | +| `info registers` | `i r` | Show all register values | +| `stepi` | `si` | Execute one assembly instruction | +| `nexti` | `ni` | Execute one instruction (skip calls) | +| `x/10i $pc` | | Examine 10 instructions at PC | +| `monitor reset halt` | | Reset the target and halt | + +### Watching the Stack Change After `push {r3, lr}` + +The first instruction in `main` is `push {r3, lr}`. Before we step it, `SP` is `0x20082000`. After a single `si`, `SP` becomes `0x20081ff8`, which tells us the processor reserved 8 bytes on the stack for two 32-bit values. The first word at the new top of stack is `0xe000ed08`, which is the old value of `r3`, and the second word is `0x1000018f`, which is the saved `lr` return address. This matches the ABI rule we discussed earlier: the compiler pushes an even number of registers so the stack stays 8-byte aligned at the next call site before `stdio_init_all()` runs. + +Notice the difference between inspecting memory at `$sp` and inspecting `$lr`. `x/4x $sp` is enough here to show the relevant stack words in RAM, while `x/x $lr` shows the instruction word stored at the flash address held in the link register. In other words, `$sp` points to saved data on the stack, but `$lr` points to code that execution will return to later. + +```gdb +(gdb) x/x $sp +0x20082000: 0x00000000 +(gdb) si +0x10000236 5 stdio_init_all(); + +(gdb) x/x $sp +0x20081ff8: 0xe000ed08 +(gdb) x/4x $sp +0x20081ff8: 0xe000ed08 0x1000018f 0x00000000 0x00000000 +(gdb) x/x $lr +0x1000018f : 0x00478849 +``` + +> Tip: **What's Next?** In Week 2, we'll put these GDB commands to work with hands-on debugging exercises! We'll step through code, examine the stack, watch registers change, and ultimately use these skills to modify a running program. The commands you learned here are the foundation for everything that follows. + +--- + +## Part 5: Static Analysis with Ghidra + +### Setting Up Your First Ghidra Project + +Before we dive into GDB debugging, let's set up Ghidra to analyze our hello-world binary. Ghidra is a powerful reverse engineering tool that will help us visualize the disassembly and decompiled code. + +##### Step 1: Create a New Project + +1. Launch Ghidra +2. A window will appear - select **File -> New Project** +3. Choose **Non-Shared Project** and click **Next** +4. Enter the Project Name: `0x0001_hello-world` +5. Click **Finish** + +##### Step 2: Import the Binary + +1. Open your file explorer and navigate to the `Embedded-Hacking` folder +2. **Drag and drop** the `0x0001_hello-world.elf` file into the folder panel within the Ghidra application + +##### Step 3: Understand the Import Dialog + +In the small window that appears, you will see the file identified as an **ELF** (Executable and Linkable Format). + +> Tip: **What is an ELF file?** +> +> ELF stands for **Executable and Linkable Format**. This format includes **symbols** - human-readable names for functions and variables. These symbols make reverse engineering much easier because you can see function names like `main` and `printf` instead of just memory addresses. +> +> In future weeks, we will work with **stripped binaries** (`.bin` files) that do not contain these symbols. This is more realistic for real-world reverse engineering scenarios where symbols have been removed to make analysis harder. + +3. Click **Ok** to import the file +4. **Double-click** on the file within the project window to open it in the CodeBrowser + +##### Step 4: Auto-Analyze the Binary + +When prompted, click **Yes** to auto-analyze the binary. Accept the default analysis options and click **Analyze**. + +Ghidra will now process the binary, identifying functions, strings, and cross-references. This may take a moment. + +### Reviewing the Main Function in Ghidra + +Once analysis is complete, let's find our `main` function: + +1. In the **Symbol Tree** panel on the left, expand **Functions** +2. Look for `main` in the list (you can also use **Search -> For Address or Label** and type "main") +3. Click on `main` to navigate to it + +##### What You'll See + +Ghidra shows you two views of the code: + +**Listing View (Center Panel)** - The disassembled ARM assembly: +``` + ************************************************************* + * FUNCTION + ************************************************************* + int main (void ) + assume LRset = 0x0 + assume TMode = 0x1 + int r0:4 + main XREF[3]: Entry Point (*) , + _reset_handler:1000018c (c) , + .debug_frame::00000018 (*) + 0x0001_hello-world.c:4 (2) + 0x0001_hello-world.c:5 (2) + 10000234 08 b5 push {r3,lr} + 0x0001_hello-world.c:5 (4) + 10000236 01 f0 99 f9 bl stdio_init_all _Bool stdio_init_all(void) + LAB_1000023a XREF[1]: 10000240 (j) + 0x0001_hello-world.c:7 (6) + 0x0001_hello-world.c:8 (6) + 1000023a 02 48 ldr r0=>__EH_FRAME_BEGIN__ ,[DAT_10000244 ] = "hello, world\r" + = 100019CCh + 1000023c 01 f0 de f9 bl __wrap_puts int __wrap_puts(char * s) + 0x0001_hello-world.c:7 (8) + 10000240 fb e7 b LAB_1000023a + 10000242 00 ?? 00h + 10000243 bf ?? BFh + DAT_10000244 XREF[1]: main:1000023a (R) + 10000244 cc 19 00 10 undefine 100019CCh ? -> 100019cc + +``` + +**Decompile View (Right Panel)** - The reconstructed C code: +```c +int main(void) + +{ + stdio_init_all(); + do { + __wrap_puts("hello, world\r"); + } while( true ); +} +``` + +> **Notice how Ghidra reconstructed our original C code!** The decompiler recognized the infinite loop and the `puts` call (the compiler optimized `printf` to `puts` since we're just printing a simple string). + +##### Why We Start with .elf Files + +We're using the `.elf` file because it contains symbols that help us learn: + +- Function names are visible (`main`, `stdio_init_all`, `puts`) +- Variable names may be preserved +- The structure of the code is easier to understand + +In future weeks, we'll work with `.bin` files that have been stripped of symbols. This will teach you how to identify functions and understand code when you don't have these helpful hints! + +--- + +## Part 6: Summary and Review + +### What We Learned + +1. **Registers**: The ARM Cortex-M33 has 13 general-purpose registers (`r0`-`r12`), plus special registers for the stack pointer (`r13`/SP), link register (`r14`/LR), and program counter (`r15`/PC). + +2. **The Stack**: + - Grows downward in memory + - PUSH adds items (SP decreases) + - POP removes items (SP increases) + - Used to save return addresses and register values + +3. **Memory Layout**: + - Code lives in flash memory starting at `0x10000000` + - Stack lives in RAM around `0x20080000` + +4. **GDB Basics**: We learned the essential commands for connecting to hardware and examining code: + +| Command | What It Does | +| --------------------- | -------------------------------------- | +| `target extended-remote :3333` | Connect to OpenOCD debug server | +| `monitor reset halt` | Reset and halt the processor | +| `b main` | Set breakpoint at main function | +| `c` | Continue running until breakpoint | +| `disas` | Disassemble current function | +| `i r` | Show all register values | + +5. **Ghidra Static Analysis**: We set up a Ghidra project and analyzed our binary: + - Imported the ELF file with symbols + - Found the `main` function + - Saw the decompiled C code + - Understood how assembly maps to C + +6. **Little-Endian**: The RP2350 stores multi-byte values with the least significant byte at the lowest address, making them appear "backwards" when viewed as a single value. + +### The Program Flow + +``` ++-----------------------------------------------------+ +| 1. push {r3, lr} | +| Save registers to stack | ++-----------------------------------------------------+ +| 2. bl stdio_init_all | +| Initialize standard I/O | ++-----------------------------------------------------+ +| 3. ldr r0, [pc, #8] ----------------+ | +| Load address of "hello, world" into r0| | ++-----------------------------------------------------+ +| 4. bl __wrap_puts | | +| Print the string | | ++-----------------------------------------------------+ +| 5. b.n (back to step 3) ----------------+ | +| Infinite loop! | ++-----------------------------------------------------+ +``` + +--- + +> **Note:** The detailed hands-on GDB debugging (stepping through code, watching the stack, examining memory) will be covered in Week 2! + +--- + +## Key Takeaways + +1. **Reverse engineering combines static and dynamic analysis** - we look at the code (static with Ghidra) and run it to see what happens (dynamic with GDB). + +2. **The stack is fundamental** - understanding how push/pop work is essential for following function calls. + +3. **GDB and Ghidra work together** - Ghidra helps you understand the big picture, GDB lets you watch it happen live. + +4. **Assembly isn't scary** - each instruction does one simple thing. Put them together and you understand the whole program! + +5. **Everything is just numbers** - whether it's code, data, or addresses, it's all stored as numbers in memory. + +--- + +## Glossary + +| Term | Definition | +| ------------------- | --------------------------------------------------------- | +| **Assembly** | Human-readable representation of machine code | +| **Breakpoint** | A marker that tells the debugger to pause execution | +| **GDB** | GNU Debugger - a tool for examining running programs | +| **Hex/Hexadecimal** | Base-16 number system (0-9, A-F) | +| **Little-Endian** | Storing the least significant byte at the lowest address | +| **Microcontroller** | A small computer on a single chip | +| **Program Counter** | Register that points to the next instruction | +| **Register** | Fast storage inside the processor | +| **Stack** | Memory region for temporary storage during function calls | +| **Stack Pointer** | Register that points to the top of the stack | +| **XIP** | Execute In Place - running code directly from flash | + + + diff --git a/WEEK01/WEEK01.pdf b/WEEK01/WEEK01.pdf new file mode 100644 index 0000000..80b71a6 Binary files /dev/null and b/WEEK01/WEEK01.pdf differ diff --git a/WEEK01/WEEK01a.md b/WEEK01/WEEK01a.md new file mode 100644 index 0000000..7a2bae8 --- /dev/null +++ b/WEEK01/WEEK01a.md @@ -0,0 +1,718 @@ +# Week 1a: Understanding the ARM Stack: Inline Assembly and Live Debugging + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this week, you will be able to: + +- Understand how the RP2350 Cortex-M33 stack grows in SRAM. +- Identify the ARM registers used by this stack experiment. +- Build and flash a Pico 2 ELF through a Debug Probe. +- Connect OpenOCD and GDB to live hardware. +- Step one assembly instruction at a time with `si`. +- Examine the exact stack words written by each multi-register instruction. +- Prove that an ARM register list is ordered by register number, not source-list spelling. + +--- + +## Part 1: Understanding the Basics + +### What is a Microcontroller? + +A microcontroller is a complete small computer on one chip. It contains processor cores, memory controllers, peripherals, and interfaces for hardware such as GPIO, UART, timers, and SPI. The Raspberry Pi Pico 2 uses the **RP2350** microcontroller. + +### What is the ARM Cortex-M33? + +The RP2350 can run Arm Cortex-M33 cores. The program in this folder is built for that Arm target. We will use the Debug Probe, OpenOCD, and GDB to stop a core and inspect its registers and memory while it executes the program. + +### What is Dynamic Analysis? + +Dynamic analysis means observing a program while it runs on real hardware. In this lesson we will: + +- Stop the processor at `main`. +- View the instructions produced by the compiler. +- Execute one instruction with `si`. +- Read the stack pointer and the memory it points to. + +--- + +## Part 2: Understanding Processor Registers + +### What is a Register? + +A register is very fast storage inside the CPU. Instructions use registers for values, addresses, temporary results, and control flow. + +### The ARM Cortex-M33 Registers + +| Register | Also Called | Purpose | +| --- | --- | --- | +| `r0` - `r12` | General purpose | Hold values and addresses while instructions run. | +| `r13` | SP | Points to the current top of the stack. | +| `r14` | LR | Holds the return address after a function call. | +| `r15` | PC | Points to the next instruction to execute. | + +##### General-Purpose Registers (`r0` - `r12`) + +This lesson uses `r2`, `r3`, `r4`, `r6`, `r9`, and `r10`. The assembly saves their current values to SRAM, then restores them before the loop repeats. + +##### The Stack Pointer (`r13` / SP) + +The stack is a region of SRAM used for temporary values, saved registers, return addresses, and local variables. On Cortex-M, the standard stack grows toward lower addresses. + +- A `push` lowers `sp` and writes values below the old stack pointer. +- A `pop` reads values at `sp` and raises `sp`. +- Each saved register occupies 4 bytes. + +```text +Higher addresses ++------------------+ +| Old SP location | ++------------------+ +| Saved value | ++------------------+ +| Saved value | <- SP after a multi-register push ++------------------+ +Lower addresses +``` + +##### The Link Register (`r14` / LR) + +A `bl` instruction calls a function and stores the return address in `lr`. The compiler-generated prologue for `main` saves `lr` on the stack before calling `stdio_init_all`. + +##### The Program Counter (`r15` / PC) + +The Program Counter identifies the next instruction. In GDB, the `=>` marker in `disas main` points to the instruction that will run when you type `si`. + +--- + +## Part 3: Understanding Memory Layout + +### XIP - Execute In Place + +The Pico 2 executes this firmware directly from external flash through XIP. The executable code normally begins at `0x10000000`. + +### Memory Map Overview + +```text ++-------------------------------------+ +| Flash Memory (XIP) | +| Starts at: 0x10000000 | +| Contains: program instructions | ++-------------------------------------+ +| SRAM | +| Starts at: 0x20000000 | +| Contains: stack, heap, variables | ++-------------------------------------+ +``` + +### Why the Stack Is in SRAM + +The stack changes on every function call and return, so it must be writable. When GDB displays `$sp`, it should show an address in the `0x200...` SRAM range. `x/wx $sp` reads the 32-bit value currently at the top of that stack. + +--- + +## Part 3.5: Reviewing Our Stack Code + +The file `0x0001a_stack.c` initializes standard I/O, then repeats this assembly block forever: + +```c +__asm volatile( + "push {r4, lr}\n" + "push {r3, r2, r6}\n" + "stmdb sp!, {r9, r10}\n" + "ldmia sp!, {r9, r10}\n" + "pop {r2, r3, r6}\n" + "pop {r4, lr}\n" + ::: "memory"); +``` + +### Breaking Down the Code + +##### First Push: `push {r4, lr}` + +This lowers `sp` by 8 bytes. At the new stack pointer, the saved values are: + +```text +[sp + 4] = lr (higher address, visual top) +[sp] = r4 (lower address) <- SP <- TOP OF STACK +``` + +##### Second Push: `push {r3, r2, r6}` + +This is deliberately written in a confusing order. The source says `r3` first, but an ARM register list is a set of registers, not an ordered sequence of operations. The assembler encodes the same register mask as `{r2, r3, r6}` and warns that the list is not ascending. + +After one `si`, the stack layout proves the actual rule: + +```text +[sp + 16] = lr (highest address, visual top) +[sp + 12] = r4 +[sp + 8] = r6 +[sp + 4] = r3 +[sp] = r2 (lowest address) <- SP <- TOP OF STACK +``` + +The first three words were written by this instruction; `r4` and `lr` remain from +the preceding `push {r4, lr}`. The lowest register number in this push is stored +at the lowest address. Because the stack grows down, `[sp]` is the lower address +and the older `lr` at `[sp + 16]` is the higher address at the visual top. + +##### High Registers: `stmdb sp!, {r9, r10}` + +The 16-bit Thumb `push` encoding cannot encode high registers `r8` through `r12`. +`stmdb sp!` is the general full-descending stack instruction used for `r9` and +`r10`. + +```text +[sp + 4] = r10 (higher address, visual top) +[sp] = r9 (lower address) <- SP <- TOP OF STACK +``` + +##### The Restore Instructions + +The next instructions restore the same groups in reverse stack-group order. This matters because the last group saved is at the current top of the stack: + +```text +ldmia sp!, {r9, r10} +pop {r2, r3, r6} +pop {r4, lr} +``` + +The stack pointer ends at the same value it had before the inline assembly, so the infinite loop does not consume stack space. + +### Compiling and Flashing to the Pico 2 + +##### Step 1: Compile the Code + +From the project folder, build the program: + +```powershell +& "$env:USERPROFILE\.pico-sdk\ninja\v1.13.2\ninja.exe" -C build +``` + +The expected artifact is `build\0x0001a_stack.elf`. The assembler reports `register range not in ascending order` for the deliberately unordered source list. That warning is expected for this experiment. + +##### Step 2: Flash and Verify + +Use the Debug Probe to flash the ELF and compare target flash with the built image: + +```powershell +& "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\openocd.exe" -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c 'adapter speed 5000; targets rp2350.dap.core1; cortex_m reset_config sysresetreq; targets rp2350.dap.core0; program "build/0x0001a_stack.elf" verify reset exit' +``` + +You should see: + +```text +** Programming Finished ** +** Verify Started ** +** Verified OK ** +** Resetting Target ** +shutdown command invoked +``` + +`Verified OK` proves that the programmed bytes match the ELF. `shutdown command invoked` is normal because `exit` ends OpenOCD after flashing. + +--- + +## Part 4: Dynamic Analysis with GDB + +### Prerequisites + +Before starting, you need: + +1. A Pico 2 with the Debug Probe connected. +2. OpenOCD from the installed Pico SDK. +3. `arm-none-eabi-gdb`. +4. The verified `build\0x0001a_stack.elf` on the Pico 2. + +### Connecting to Your Pico 2 with OpenOCD + +Open a terminal and start the debug server. Leave it running: + +```powershell +& "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\openocd.exe" -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000; init" +``` + +OpenOCD listens for GDB connections on port `3333`. + +##### VM Command + +If the VM has `openocd` on its `PATH`, use the same command without the full executable path: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000; init" +``` + +The VM needs USB access to the Debug Probe. Nothing else about the build, ELF, or GDB sequence changes. + +### Connecting to Your Pico 2 with GDB + +Open a second terminal in the project folder: + +```powershell +arm-none-eabi-gdb build\0x0001a_stack.elf +``` + +Connect, reset, halt, and stop at `main`: + +```gdb +target extended-remote :3333 +monitor reset halt +b main +c +disas main +``` + +You should see this instruction pattern from the current `build\0x0001a_stack.elf`. +The instruction addresses are determined by the ELF. The register contents shown +later are live target state and are not determined by the ELF. + +```text +=> main: push {r3, lr} + main+2: bl stdio_init_all + main+6: push {r4, lr} + main+8: push {r2, r3, r6} + main+10: stmdb sp!, {r9, r10} + main+14: ldmia.w sp!, {r9, r10} + main+18: pop {r2, r3, r6} + main+20: ldmia.w sp!, {r4, lr} + main+24: b.n main+6 +``` + +Notice that GDB displays `{r2, r3, r6}`, not the source spelling `{r3, r2, r6}`. That is the encoded register set in canonical order. Some disassemblers display `r10` as its conventional alias, `sl`; `{r9, sl}` and `{r9, r10}` name the same register set. + +### Basic GDB Commands: Your First Steps + +| Command | Short Form | What It Does | +| --- | --- | --- | +| `break main` | `b main` | Set a breakpoint at `main`. | +| `continue` | `c` | Run until a breakpoint. | +| `disassemble` | `disas` | Show the current function's assembly. | +| `info registers` | `i r` | Display CPU registers. | +| `stepi` | `si` | Execute exactly one instruction. | +| `nexti` | `ni` | Execute one instruction without entering a call. | +| `x/wx ADDRESS` | | Examine one 32-bit hexadecimal word. | +| `monitor reset halt` | | Ask OpenOCD to reset and halt the target. | + +### Watching the Stack Change + +> **Important: the instruction addresses and stack offsets below come from the +> current ELF. The Step 4 register capture is from the live GDB session shown +> here. Register contents and old SRAM words are target state, not constants +> that can be recovered from the ELF. The deterministic rule is that `push +> {r4, lr}` decreases `sp` by 8 bytes, stores `r4` at the new `[sp]`, and +> stores `lr` at `[sp + 4]`. + +##### Step 1: Inspect the Stack Before the Compiler Prologue + +At the breakpoint, GDB is paused before `push {r3, lr}`. Inspect the current stack pointer and the two words below it: + +```gdb +(gdb) p/x $sp +$1 = 0x20082000 +(gdb) x/2wx $sp-8 +0x20081ff8: 0x88526891 0x10000187 +``` + +The stack pointer is at `0x20082000`. The two words below it contain previous values (before the prologue). + +##### Step 2: Execute One Instruction + +Execute the compiler prologue `push {r3, lr}`: + +```gdb +(gdb) si +0x100001e2 7 stdio_init_all(); +(gdb) p/x $sp +$2 = 0x20081ff8 +(gdb) p/x $r3 +$3 = 0xe000ed08 +(gdb) x/wx $sp +0x20081ff8: 0xe000ed08 +(gdb) p/x $lr +$4 = 0x1000018b +(gdb) x/wx $sp+4 +0x20081ffc: 0x1000018b +``` + +The prologue saved two values to the stack: +```text +[sp + 4] = 0x1000018b (lr, higher address, visual top) +[sp] = 0xe000ed08 (r3, lower address) <- SP <- TOP OF STACK +``` + +**Stack layout after prologue** (memory grows downward; **higher hex addresses = deeper in stack = older data**): + +```text +Address Pointer Value Label +0x20082000 ---------- ---------- (previous data — HIGHEST address, visual top) +0x20081ffc ---------- 0x1000018b (lr, higher address) +0x20081ff8 <- [sp] 0xe000ed08 (r3, lowest address) <- SP <- TOP OF STACK + +MEMORY ORDER: 0x20081ff8 < 0x20081ffc < 0x20082000 + (visual bottom) (visual top) +``` + +**Memory address explanation for newcomers:** +- Hex address `0x20081ffc` is **LARGER** than `0x20081ff8` (compare the last hex digits: `ffc` > `ff8`) +- **Larger addresses = higher in memory = deeper in the stack** +- When we PUSH, sp **DECREASES** (goes to a smaller address, moving DOWN on the page) +- When we POP, sp **INCREASES** (goes to a larger address, moving UP on the page) + +The stack pointer dropped 8 bytes: from `0x20082000` to `0x20081ff8` (it went DOWN, to a smaller/lower address). + +##### Step 3: Step Over `stdio_init_all` + +Do not step into the library initialization code. Use `ni` to execute it and return: + +```gdb +(gdb) ni +0x100001e6 15 __asm volatile( +(gdb) disas main +Dump of assembler code for function main: + 0x100001e0 <+0>: push {r3, lr} + 0x100001e2 <+2>: bl 0x10001594 +=> 0x100001e6 <+6>: push {r4, lr} + 0x100001e8 <+8>: push {r2, r3, r6} + ... +``` + +The arrow now points at `push {r4, lr}`, the first inline assembly instruction. + +##### Step 4: Prove the First Inline Push + +Read the registers and stack pointer before the first inline push: + +```gdb +(gdb) p/x $r4 +$3 = 0x100001cc +(gdb) p/x $lr +$4 = 0x1000159b +(gdb) p/x $sp +$5 = 0x20081ff8 +``` + +Now execute the first inline push: + +```gdb +(gdb) si +0x100001e8 16 "push {r4, lr}\n" +(gdb) p/x $sp +$6 = 0x20081ff0 +(gdb) x/wx $sp +0x20081ff0: 0x100001cc +(gdb) x/wx $sp+4 +0x20081ff4: 0x1000159b +``` + +**After first inline push `push {r4, lr}`:** +- SP = `0x20081ff0` (**new TOP of stack, sp decreased**) +- `r4` = `0x100001cc` (now saved on stack) +- `lr` = `0x1000159b` (now saved on stack) + +The first push saved: +```text +[sp + 4] = 0x1000159b (lr, higher address, visual top) +[sp] = 0x100001cc (r4, lower address) <- SP <- TOP OF STACK +``` + +**Stack layout after first inline push**: + +```text +Address Pointer Value Label +0x20081ffc ---------- 0x1000018b (lr from prologue — highest address, visual top) +0x20081ff8 ---------- 0xe000ed08 (r3 from prologue — higher address) +0x20081ff4 ---------- 0x1000159b (lr — higher address) +0x20081ff0 <- [sp] 0x100001cc (r4, lowest address) <- SP <- TOP OF STACK + +MEMORY ORDER: 0x20081ff0 < 0x20081ff4 < 0x20081ff8 < 0x20081ffc + (visual bottom) (visual top) + Most recent Least recent +``` + +**The stack pointer dropped from `0x20081ff8` to `0x20081ff0` — that's 8 bytes down (toward lower addresses).** +**The value at `[sp]` (the TOP) is now `0x100001cc` (r4).** +**Address `0x20081ff0` is SMALLER than `0x20081ff8`, so sp moved DOWN.** + + +##### Step 5: Prove Register-List Ordering + +Read the three registers before executing the deliberately unordered list `push {r3, r2, r6}`: + +```gdb +(gdb) p/x $r2 +$18 = 0x200005cc +(gdb) p/x $r3 +$19 = 0xe000ed08 +(gdb) p/x $r6 +$20 = 0x04f54710 +(gdb) p/x $sp +$21 = 0x20081ff0 +``` + +Now execute the second inline push: + +```gdb +(gdb) si +0x100001ea <+10>: stmdb sp!, {r9, sl} +(gdb) p/x $sp +$22 = 0x20081fe4 +(gdb) x/wx $sp +0x20081fe4: 0x200005cc +(gdb) x/wx $sp+4 +0x20081fe8: 0xe000ed08 +(gdb) x/wx $sp+8 +0x20081fec: 0x04f54710 +``` + +The second push saved three registers in **numeric order** despite the source spelling `{r3, r2, r6}`: +```text +[sp + 8] = 0x04f54710 (r6, higher address, visual top) +[sp + 4] = 0xe000ed08 (r3, higher address) +[sp] = 0x200005cc (r2, lower address) <- SP <- TOP OF STACK +``` + +**Stack layout after second inline push** (**lower hex addresses = most recent = TOP**): + +```text +Address Pointer Value Label +0x20081ffc ---------- 0x1000018b (lr — HIGHEST address, OLDEST data, visual top) +0x20081ff8 ---------- 0xe000ed08 (r3 — higher address) +0x20081ff4 ---------- 0x1000159b (lr — higher address) +0x20081ff0 ---------- 0x100001cc (r4 — higher address) +0x20081fec ---------- 0x04f54710 (r6 — higher address) +0x20081fe8 ---------- 0xe000ed08 (r3 — higher address) +0x20081fe4 <- [sp] 0x200005cc (r2, lowest address) <- SP <- TOP OF STACK + +ADDRESS ORDERING: 0x20081fe4 < 0x20081fe8 < ... < 0x20081ffc + (visual bottom) (visual top) + Hex comparison: fe4 < fe8 < fec < ff0 < ff4 < ff8 < ffc + Most recent data at the visual bottom +``` + +**The stack pointer dropped from `0x20081ff0` to `0x20081fe4` — that's 12 bytes down (three 4-byte registers).** +**When comparing hex: `0x20081fe4` is SMALLER than `0x20081ff0`, so sp moved to a LOWER address.** +**The value at `[sp]` (the TOP) is now `0x200005cc` (r2).** + +Notice: the source wrote `r3` first, but the CPU pushed `r2` first because `r2` has a lower register number. The encoded register mask is `{r2, r3, r6}`, and the stack layout proves it. + +##### Step 6: Prove the High-Register Save + +Read the high registers before the `stmdb sp!, {r9, r10}` instruction: + +```gdb +(gdb) p/x $r9 +$23 = 0x00000000 +(gdb) p/x $r10 +$24 = 0x10000000 +(gdb) p/x $sp +$25 = 0x20081fe4 +``` + +Execute the high-register save: + +```gdb +(gdb) si +0x100001ee <+14>: ldmia.w sp!, {r9, sl} +(gdb) p/x $sp +$26 = 0x20081fdc +(gdb) p/x $r9 +$27 = 0x00000000 +(gdb) p/x $r10 +$28 = 0x10000000 +(gdb) x/wx $sp +0x20081fdc: 0x00000000 +(gdb) x/wx $sp+4 +0x20081fe0: 0x10000000 +(gdb) x/wx $sp+8 +0x20081fe4: 0x200005cc +(gdb) x/wx $sp+12 +0x20081fe8: 0xe000ed08 +(gdb) x/wx $sp+16 +0x20081fec: 0x04f54710 +(gdb) x/wx $sp+20 +0x20081ff0: 0x100001cc +(gdb) x/wx $sp+24 +0x20081ff4: 0x1000159b +(gdb) x/wx $sp+28 +0x20081ff8: 0xe000ed08 +``` + +**After high-register save `stmdb sp!, {r9, r10}`:** +- SP = `0x20081fdc` (**new TOP of stack, sp decreased further**) +- `r9` = `0x00000000` (now saved on stack) +- `r10` = `0x10000000` (now saved on stack) + +The `stmdb sp!, {r9, r10}` instruction saved: +```text +[sp + 4] = 0x10000000 (r10, higher address, visual top) +[sp] = 0x00000000 (r9, lower address) <- SP <- TOP OF STACK +``` + +**The stack pointer dropped from `0x20081fe4` to `0x20081fdc` — that's 8 more bytes down.** +**The value at `[sp]` (the TOP) is now `0x00000000` (r9).** +**This is the DEEPEST point of the stack during inline assembly.** + +```text +Address Pointer Value Label +0x20081ff8 ---------- 0xe000ed08 (saved prologue r3, highest address, visual top) +0x20081ff4 ---------- 0x1000159b (lr, higher address) +0x20081ff0 ---------- 0x100001cc (r4, higher address) +0x20081fec ---------- 0x04f54710 (r6, higher address) +0x20081fe8 ---------- 0xe000ed08 (r3, higher address) +0x20081fe4 ---------- 0x200005cc (r2, higher address) +0x20081fe0 ---------- 0x10000000 (r10, higher address) +0x20081fdc <- [sp] 0x00000000 (r9, lowest address) <- SP <- TOP OF STACK +``` + +##### Step 7: Watch the Restores + +At this point, the stack is at maximum depth. Now execute the restore instructions one by one: + +**Restore 1: ldmia sp!, {r9, r10}** + +```gdb +(gdb) si +0x100001f2 <+18>: pop {r2, r3, r6} +(gdb) p/x $sp +$29 = 0x20081fe4 +(gdb) p/x $r9 +$30 = 0x00000000 +(gdb) p/x $r10 +$31 = 0x10000000 +``` + +`ldmia sp!` restored `r9` and `r10` from the stack and raised `sp` by 8 bytes (from `0x20081fdc` to `0x20081fe4`). +**SP is now `0x20081fe4`; `[sp]` contains r2, so `SP <- TOP OF STACK` at the next group.** + +**Restore 2: pop {r2, r3, r6}** + +```gdb +(gdb) si +0x100001f4 <+20>: ldmia.w sp!, {r4, lr} +(gdb) p/x $sp +$32 = 0x20081ff0 +(gdb) p/x $r2 +$33 = 0x200005cc +(gdb) p/x $r3 +$34 = 0xe000ed08 +(gdb) p/x $r6 +$35 = 0x04f54710 +``` + +`pop {r2, r3, r6}` restored the three registers from SRAM and raised `sp` by 12 bytes (from `0x20081fe4` to `0x20081ff0`). +**SP is now `0x20081ff0`; `[sp]` contains r4, so `SP <- TOP OF STACK` at the final group.** + +**Restore 3: ldmia.w sp!, {r4, lr}** + +```gdb +(gdb) si +0x100001f8 <+24>: b.n 0x100001e6 +(gdb) p/x $sp +$36 = 0x20081ff8 +(gdb) p/x $r4 +$37 = 0x100001cc +(gdb) p/x $lr +$38 = 0x1000159b +``` + +`ldmia.w sp!, {r4, lr}` restored `r4` and `lr` from SRAM and raised `sp` by 8 bytes (from `0x20081ff0` to `0x20081ff8`). +**SP is now `0x20081ff8`; `[sp]` contains the saved prologue r3, so `SP <- TOP OF STACK` for the remaining prologue stack data.** + +**Result:** After all three restore instructions, `sp` is back at `0x20081ff8`, exactly where it was before the inline assembly block started. The loop branches back to `push {r4, lr}` at address `0x100001e6` and repeats forever without consuming stack space. + +### Understanding the Stack Diagram + +At the deepest point, after `stmdb sp!, {r9, r10}`, the inline assembly has saved 28 bytes. The `old SP` below is the stack pointer after the separate compiler prologue, not the stack pointer at entry to `main`: + +```text +Before inline assembly: At maximum inline stack depth: + +old SP <- SP old SP + [old SP - 4] lr + [old SP - 8] r4 + [old SP - 12] r6 + [old SP - 16] r3 + [old SP - 20] r2 + [old SP - 24] r10 + [old SP - 28] r9 <- SP +``` + +The restoration sequence removes the top group first: `r9/r10`, then `r2/r3/r6`, then `r4/lr`. + +--- + +## Part 5: Summary and Review + +### What We Learned + +1. **Registers**: `sp`, `lr`, and `pc` control stack location, returns, and the next instruction. +2. **The stack**: It grows down in SRAM. Pushes decrease `sp`; pops increase it. +3. **Multi-register instructions**: Register-list source order is not the stack-memory order. ARM stores lower register numbers at lower addresses. +4. **OpenOCD and GDB**: OpenOCD connects to the Debug Probe; GDB connects to OpenOCD on port `3333`. +5. **Live evidence**: `si` executes one instruction, and `x/wx $sp` shows the exact 32-bit word that instruction placed at the stack pointer. + +### The Program Flow + +```text ++-----------------------------------------------------+ +| 1. push {r3, lr} | +| Compiler saves its prologue registers | ++-----------------------------------------------------+ +| 2. bl stdio_init_all | +| Initialize standard I/O | ++-----------------------------------------------------+ +| 3. push {r4, lr} | +| Save the first inline group | ++-----------------------------------------------------+ +| 4. push {r3, r2, r6} | +| Source order differs from stack-memory order | ++-----------------------------------------------------+ +| 5. stmdb / ldmia / pop / pop | +| Save and restore all groups | ++-----------------------------------------------------+ +| 6. b.n main+6 | +| Repeat with the original stack pointer | ++-----------------------------------------------------+ +``` + +--- + +## Key Takeaways + +1. **The stack grows downward**: a push decreases the numeric value in `sp`. +2. **A register list is not a sequence**: `{r3, r2, r6}` and `{r2, r3, r6}` encode the same register set. +3. **Memory is the proof**: after `si`, inspect `[sp]`, `[sp+4]`, and `[sp+8]` with GDB. +4. **The restore order matters**: always restore the most recently saved group first. +5. **Balanced stack operations are required**: the loop returns `sp` to its starting value on every iteration. + +--- + +## Glossary + +| Term | Definition | +| --- | --- | +| **Assembly** | Human-readable form of processor instructions. | +| **Breakpoint** | A debugger stop point. | +| **Debug Probe** | Hardware interface that lets OpenOCD communicate with the target over SWD. | +| **GDB** | GNU Debugger, used to inspect and control the running target. | +| **LR** | Link Register, holding a function return address. | +| **OpenOCD** | Debug server that bridges GDB and the Debug Probe. | +| **PC** | Program Counter, pointing to the next instruction. | +| **SP** | Stack Pointer, pointing to the top of the stack. | +| **SRAM** | Writable memory used for runtime data and the stack. | +| **XIP** | Execute In Place, executing program code directly from flash. | diff --git a/WEEK01/WEEK01a.pdf b/WEEK01/WEEK01a.pdf new file mode 100644 index 0000000..1715af1 Binary files /dev/null and b/WEEK01/WEEK01a.pdf differ diff --git a/WEEK01/slides/WEEK01-IMG00.svg b/WEEK01/slides/WEEK01-IMG00.svg new file mode 100644 index 0000000..e666d03 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 01 + + +Introduction and Overview of +Embedded Reverse Engineering: +Ethics, Scoping, and Basic Concepts + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK01/slides/WEEK01-IMG01.svg b/WEEK01/slides/WEEK01-IMG01.svg new file mode 100644 index 0000000..58888b0 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG01.svg @@ -0,0 +1,112 @@ + + + + + +ARM Cortex-M33 Regs +ARM Architecture & Registers + + + + Key Registers + + + + + r0 + Arg 1 / Return + + + + r1 + Arg 2 + + + + r2 + Arg 3 + + + + r3 + Arg 4 + + + + r0-r3 Caller-saved + r4-r11 Callee-saved + + + + SP (r13) + Stack Ptr + + + + LR (r14) + Return Addr + + + + PC (r15) + Next Instr + + + + xPSR + Status Flags + + + + Function Call Flow + + + + + main() + + + + + BL + + + + func() + + + + + BX LR + + + + + + How It Works + + r0 = first argument + puts(r0) passes the + string address in r0 + + + + LR saves return addr + BL: PC+4 stored in LR + BX LR: jump back + + + + All registers: 32 bits wide + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG02.svg b/WEEK01/slides/WEEK01-IMG02.svg new file mode 100644 index 0000000..3345c63 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG02.svg @@ -0,0 +1,101 @@ + + + + + +Stack Growth Direction +ARM Stack Mechanics + + + + Before PUSH + + + 0x20082000 + SP here + + + (empty) + + + (empty) + + + (empty) + + + (empty) + + 0x20080000 + + + Grows DOWN + + + + + + After PUSH + + + 0x20082000 + + + LR value + + + r3 value + + + (empty) + + + (empty) + + SP here now = 0x20081FF8 + + SP moved down + by 8 bytes + + 0x20080000 + + + + Key Concepts + + + Full Descending + SP points to the + last pushed item + + + + PUSH: SP -= 4 + Each 32-bit val + drops SP by 4 + Two vals = -8 + + + + POP: SP += 4 + Restores values + SP moves back up + + + + Initial SP + Set by vector + table at 0x00 + StackTop=0x20082000 + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG03.svg b/WEEK01/slides/WEEK01-IMG03.svg new file mode 100644 index 0000000..b684520 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG03.svg @@ -0,0 +1,98 @@ + + + + + +RP2350 Memory Map +RP2350 Address Space + + + + Address Space + + + + + ROM Boot + 0x0000_0000 + + + + XIP Flash + 16MB max + 0x1000_0000 + + + + SRAM + 520KB total + 0x2000_0000 + + + + APB Periph + 0x4000_0000 + + + + AHB Periph + 0x5000_0000 + + + + SIO + 0xD000_0000 + + + + PPB Cortex + 0xE000_0000 + + + addr+ + + + + Key Details + + + + XIP Flash + Code runs directly + from flash via cache + Execute-In-Place + + + + + SRAM Banks + SRAM0-7: 8x64KB + SRAM8-9: 2x4KB + Stack + Heap here + + + + + Peripherals + GPIO, UART, SPI + I2C, PWM, ADC + Memory-mapped I/O + + + + + SIO + PPB + Single-cycle I/O + Debug + NVIC + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG04.svg b/WEEK01/slides/WEEK01-IMG04.svg new file mode 100644 index 0000000..d6c7ad5 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG04.svg @@ -0,0 +1,90 @@ + + + + + +Stack vs Heap in RAM +RP2350 SRAM: Data, BSS, Heap, Stack + + + + SRAM Layout + + + + 0x2008_2000 (top) + + + + STACK + Grows DOWN + SP = top of stack + + + + + + + + FREE SPACE + + + + + + + + HEAP + Grows UP + heap_base = __end__ + + + + .data + .bss + + + 0x2000_0000 (base) + + + + How To Read Sizes Quickly + + + + 1) .data size + __data_end__ - __data_start__ + init non-zero globals/statics + + + + 2) .bss size + __bss_end__ - __bss_start__ + zero/uninit globals/statics + + + + 3) Heap starts at + __end__ (aka __HeapBase) + + + + 4) Stack starts at + vector_table[0] (initial SP) + typical: 0x20082000 on RP2350 + + + + 5) Safety rule + Heap must never collide with stack + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG05.svg b/WEEK01/slides/WEEK01-IMG05.svg new file mode 100644 index 0000000..7941c08 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG05.svg @@ -0,0 +1,86 @@ + + + + + +Link Register & Return +ARM Function Calls + + + + BL Call Flow + + + + Step 1: caller + + main: BL add + + + + + + + Step 2: hardware saves LR + + LR = return addr + + + + + + + Step 3: run function + + add: ADD r0, r1 + + + + + + + Step 4: return to caller + + BX LR (jump back) + + + + Key Concepts + + + BL instruction + Branch with Link + Saves return addr + in LR (r14) + + + + BX LR + Branch to addr + stored in LR + Returns to caller + + + + Nested Calls + Must PUSH LR first + PUSH {r3, lr} + POP {r3, pc} + POP into PC = return + + + + r14 = LR + Always check LR in GDB + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG06.svg b/WEEK01/slides/WEEK01-IMG06.svg new file mode 100644 index 0000000..3d6d502 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG06.svg @@ -0,0 +1,101 @@ + + + + + +Program Counter Flow +Instruction Execution + + + + PC Execution + + + + ADDR + INSTRUCTION + + + + 0x1000 + MOV r0, #5 + PC + + + + 0x1002 + MOV r1, #3 + + + + 0x1004 + ADD r0, r1 + + + + 0x1006 + BL func + + + + 0x1010 + func: PUSH {lr} + + + + 0x1012 + SUB r0, #1 + + + + 0x1014 + POP {pc} + + + + + BL = jump to function target + POP {pc} = return to caller + + + + Key Concepts + + + r15 = PC + Points to current + instruction + 4 + Prefetch pipeline + + + + Sequential + Thumb next = +2 or +4 + depends on instruction encoding + Cortex-M33 executes Thumb only + + + + Branch + B = unconditional + BL = save LR, jump + BX = branch reg + BEQ = branch if Z=1 + not linear +2 stepping + + + + GDB tip + stepi = step 1 instr + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG07.svg b/WEEK01/slides/WEEK01-IMG07.svg new file mode 100644 index 0000000..0acc44a --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG07.svg @@ -0,0 +1,110 @@ + + + + + +Little-Endian Bytes +Byte Ordering + + + + Byte Ordering + + + + 0xDEADBEEF + + + Big-Endian + MSB first + + + DE + + + AD + + + BE + + + EF + + + +0 + +1 + +2 + +3 + + + vs + + + Little-Endian + LSB first + + + EF + + + BE + + + AD + + + DE + + + +0 + +1 + +2 + +3 + + + Bytes are reversed! + Lowest address holds + least significant byte + ARM uses little-endian + + + + Key Concepts + + + ARM = Little-Endian + Cortex-M33 uses LE + by default + Also: x86, RISC-V + + + + Why It Matters + Memory dumps show + raw byte order + Must mentally flip + to get true value + + + + GDB Example + x/4xb 0x2000 + EF BE AD DE + = 0xDEADBEEF + + + + x/xw = word view + GDB auto-corrects + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG08.svg b/WEEK01/slides/WEEK01-IMG08.svg new file mode 100644 index 0000000..6b7faad --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG08.svg @@ -0,0 +1,90 @@ + + + + + +XIP Flash Model +Execute-in-Place + + + + Execute-In-Place + + + + + QSPI Flash + External 16MB + + + + + + + + QSPI Controller + + + + + + + + XIP Cache + 16KB cache + + + + + + + + Cortex-M33 CPU + Fetches via PC + + + Mapped at + 0x1000_0000 + + + + Key Details + + + What is XIP? + Code stays in flash + CPU reads it as if + it were normal memory + No copy to SRAM needed + + + + QSPI Interface + 4 data lines + Fast serial flash + CLK, CS, IO0-IO3 + + + + Cache Behavior + Used for XIP flash reads + (code + const data at 0x1000....) + Not used for SRAM/peripherals + or during flash program/erase + + + + RE Insight + Dump flash via SWD + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG09.svg b/WEEK01/slides/WEEK01-IMG09.svg new file mode 100644 index 0000000..7fc15e0 --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG09.svg @@ -0,0 +1,92 @@ + + + + + +ELF File Structure +Binary Format + + + + ELF File Layout (Offsets) + + Higher file offsets + + + + Section Headers + + + + .symtab + + + + .bss + + + + .data + + + + .rodata + + + + .text + Machine code + + + + Program Headers + + + + ELF Header + Magic: 7f 45 4c 46 (off 0x0000) + + + + Section Details + Mapping + + + ELF Header + Arch: ARM 32-bit + Entry point addr + Type: executable + + + + .text = code + All instructions + Maps to XIP flash + Disassemble this! + + + + .data / .rodata + .data = initialized + .rodata = constants + .bss = zeroed vars + + + + .symtab = symbols + Function names + ELF header is file metadata + not runtime address 0x1000.... + Use section VMA/LMA for memory map + \ No newline at end of file diff --git a/WEEK01/slides/WEEK01-IMG10.svg b/WEEK01/slides/WEEK01-IMG10.svg new file mode 100644 index 0000000..ecffd4b --- /dev/null +++ b/WEEK01/slides/WEEK01-IMG10.svg @@ -0,0 +1,94 @@ + + + + + +GDB-OpenOCD Chain +Debug Toolchain + + + + Debug Toolchain + + + + + GDB + Client + + + + + TCP + :3333 + + + + OpenOCD + Server + + + + + USB + + + + CMSIS-DAP + Probe + + + + + SWD + + + + RP2350 + Target + + + + GDB Commands + + + target remote :3333 + Connect to OpenOCD + + monitor reset halt + Reset + stop at entry + + break main + Set breakpoint + + info registers + Dump all regs + + + + SWD Protocol + + + 2 wires only + SWCLK = clock + SWDIO = data + + + + Capabilities + Read/write memory + Read/write regs + Set breakpoints + Full chip control + \ No newline at end of file diff --git a/WEEK02/0x0001_hello-world/.gitignore b/WEEK02/0x0001_hello-world/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK02/0x0001_hello-world/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK02/0x0001_hello-world/.vscode/c_cpp_properties.json b/WEEK02/0x0001_hello-world/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK02/0x0001_hello-world/.vscode/cmake-kits.json b/WEEK02/0x0001_hello-world/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK02/0x0001_hello-world/.vscode/extensions.json b/WEEK02/0x0001_hello-world/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK02/0x0001_hello-world/.vscode/launch.json b/WEEK02/0x0001_hello-world/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK02/0x0001_hello-world/.vscode/settings.json b/WEEK02/0x0001_hello-world/.vscode/settings.json new file mode 100644 index 0000000..688748a --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/settings.json @@ -0,0 +1,43 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja", + "files.associations": { + "stdlib.h": "c" + } +} diff --git a/WEEK02/0x0001_hello-world/.vscode/tasks.json b/WEEK02/0x0001_hello-world/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK02/0x0001_hello-world/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK02/0x0001_hello-world/0x0001_hello-world.c b/WEEK02/0x0001_hello-world/0x0001_hello-world.c new file mode 100644 index 0000000..096aba7 --- /dev/null +++ b/WEEK02/0x0001_hello-world/0x0001_hello-world.c @@ -0,0 +1,9 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} diff --git a/WEEK02/0x0001_hello-world/CMakeLists.txt b/WEEK02/0x0001_hello-world/CMakeLists.txt new file mode 100644 index 0000000..31d8fc5 --- /dev/null +++ b/WEEK02/0x0001_hello-world/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0001_hello-world C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0001_hello-world 0x0001_hello-world.c ) + +pico_set_program_name(0x0001_hello-world "0x0001_hello-world") +pico_set_program_version(0x0001_hello-world "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0001_hello-world 1) +pico_enable_stdio_usb(0x0001_hello-world 0) + +# Add the standard library to the build +target_link_libraries(0x0001_hello-world + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0001_hello-world PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0001_hello-world) + diff --git a/WEEK02/0x0001_hello-world/build/0x0001_hello-world.bin b/WEEK02/0x0001_hello-world/build/0x0001_hello-world.bin new file mode 100755 index 0000000..bc1e0ac Binary files /dev/null and b/WEEK02/0x0001_hello-world/build/0x0001_hello-world.bin differ diff --git a/WEEK02/0x0001_hello-world/build/0x0001_hello-world.dis b/WEEK02/0x0001_hello-world/build/0x0001_hello-world.dis new file mode 100644 index 0000000..08dec5d --- /dev/null +++ b/WEEK02/0x0001_hello-world/build/0x0001_hello-world.dis @@ -0,0 +1,2835 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000019cc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 0000014c 100019cc 100019cc 000029cc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10001b18 10001b18 00002b18 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10001b20 10001b20 00002b20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003cfc 2**0 + CONTENTS + 6 .data 0000019c 20000110 10001b4c 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 200002ac 200002ac 00003cfc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 200002ac 200002ac 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 200002b0 10001ce8 000042b0 2**3 + ALLOC + 10 .heap 00000800 200004d8 10001ce8 000044d8 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003cfc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003cfc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001ce8 10001ce8 00003ce8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003cfc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00003d30 2**0 + CONTENTS, READONLY + 17 .debug_info 0002069a 00000000 00000000 00003d75 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 000054ff 00000000 00000000 0002440f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000af0 00000000 00000000 00029910 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 00002f86 00000000 00000000 0002a400 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 0001562d 00000000 00000000 0002d386 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 000056be 00000000 00000000 000429b3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00001ed4 00000000 00000000 00048074 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000ffd1 00000000 00000000 00049f48 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 00000180 00000000 00000000 00059f19 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10001b20 .word 0x10001b20 +1000012c: 10001b4c .word 0x10001b4c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00001bb0 .word 0x00001bb0 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10001b4c .word 0x10001b4c +100001a4: 20000110 .word 0x20000110 +100001a8: 200002ac .word 0x200002ac +100001ac: 10001ce8 .word 0x10001ce8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001ce8 .word 0x10001ce8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 200002ac .word 0x200002ac +100001d4: 200004d8 .word 0x200004d8 +100001d8: 1000137d .word 0x1000137d +100001dc: 10000235 .word 0x10000235 +100001e0: 10001375 .word 0x10001375 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 200002ac .word 0x200002ac +10000208: 200002ac .word 0x200002ac +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000490 .word 0x20000490 +10000230: 100019cc .word 0x100019cc + +10000234
: +10000234: b508 push {r3, lr} +10000236: f001 f999 bl 1000156c +1000023a: 4802 ldr r0, [pc, #8] @ (10000244 ) +1000023c: f001 f9de bl 100015fc <__wrap_puts> +10000240: e7fb b.n 1000023a +10000242: bf00 nop +10000244: 100019cc .word 0x100019cc + +10000248 : +10000248: b410 push {r4} +1000024a: f44f 7480 mov.w r4, #256 @ 0x100 +1000024e: 4b0c ldr r3, [pc, #48] @ (10000280 ) +10000250: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000254: eb03 0380 add.w r3, r3, r0, lsl #2 +10000258: 00c0 lsls r0, r0, #3 +1000025a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000025e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000262: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000266: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000026a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000026e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000272: f8cc 2000 str.w r2, [ip] +10000276: 6041 str r1, [r0, #4] +10000278: 601c str r4, [r3, #0] +1000027a: f85d 4b04 ldr.w r4, [sp], #4 +1000027e: 4770 bx lr +10000280: 40038004 .word 0x40038004 + +10000284 : +10000284: b40f push {r0, r1, r2, r3} +10000286: b500 push {lr} +10000288: b083 sub sp, #12 +1000028a: 9c04 ldr r4, [sp, #16] +1000028c: 4807 ldr r0, [pc, #28] @ (100002ac ) +1000028e: f001 f9b5 bl 100015fc <__wrap_puts> +10000292: b13c cbz r4, 100002a4 +10000294: a905 add r1, sp, #20 +10000296: 4620 mov r0, r4 +10000298: 9101 str r1, [sp, #4] +1000029a: f001 f851 bl 10001340 +1000029e: 4804 ldr r0, [pc, #16] @ (100002b0 ) +100002a0: f001 f9ac bl 100015fc <__wrap_puts> +100002a4: 2001 movs r0, #1 +100002a6: f001 f863 bl 10001370 <_exit> +100002aa: bf00 nop +100002ac: 100019dc .word 0x100019dc +100002b0: 100019ec .word 0x100019ec + +100002b4 : +100002b4: b570 push {r4, r5, r6, lr} +100002b6: 4686 mov lr, r0 +100002b8: f3ef 8510 mrs r5, PRIMASK +100002bc: b672 cpsid i +100002be: 4c12 ldr r4, [pc, #72] @ (10000308 ) +100002c0: e8d4 6fcf ldaexb r6, [r4] +100002c4: 2001 movs r0, #1 +100002c6: 2e00 cmp r6, #0 +100002c8: d1fa bne.n 100002c0 +100002ca: e8c4 0f46 strexb r6, r0, [r4] +100002ce: 2e00 cmp r6, #0 +100002d0: d1f6 bne.n 100002c0 +100002d2: f3bf 8f5f dmb sy +100002d6: f04f 0c01 mov.w ip, #1 +100002da: 08c8 lsrs r0, r1, #3 +100002dc: f001 0307 and.w r3, r1, #7 +100002e0: fa0c f303 lsl.w r3, ip, r3 +100002e4: f81e c000 ldrb.w ip, [lr, r0] +100002e8: ea1c 0603 ands.w r6, ip, r3 +100002ec: d108 bne.n 10000300 +100002ee: ea4c 0c03 orr.w ip, ip, r3 +100002f2: f80e c000 strb.w ip, [lr, r0] +100002f6: e8c4 6f8f stlb r6, [r4] +100002fa: f385 8810 msr PRIMASK, r5 +100002fe: bd70 pop {r4, r5, r6, pc} +10000300: 4610 mov r0, r2 +10000302: f7ff ffbf bl 10000284 +10000306: bf00 nop +10000308: 2000043b .word 0x2000043b + +1000030c : +1000030c: 4a04 ldr r2, [pc, #16] @ (10000320 ) +1000030e: 7810 ldrb r0, [r2, #0] +10000310: 1c43 adds r3, r0, #1 +10000312: b2db uxtb r3, r3 +10000314: 2b18 cmp r3, #24 +10000316: bf28 it cs +10000318: 2310 movcs r3, #16 +1000031a: 7013 strb r3, [r2, #0] +1000031c: 4770 bx lr +1000031e: bf00 nop +10000320: 20000228 .word 0x20000228 + +10000324 : +10000324: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000328: 6893 ldr r3, [r2, #8] +1000032a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000032e: 6093 str r3, [r2, #8] +10000330: 4770 bx lr +10000332: bf00 nop + +10000334 : +10000334: 2100 movs r1, #0 +10000336: 4b04 ldr r3, [pc, #16] @ (10000348 ) +10000338: f103 0220 add.w r2, r3, #32 +1000033c: e8c3 1f8f stlb r1, [r3] +10000340: 3301 adds r3, #1 +10000342: 4293 cmp r3, r2 +10000344: d1fa bne.n 1000033c +10000346: 4770 bx lr +10000348: 20000430 .word 0x20000430 + +1000034c : +1000034c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000350: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000354: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000358: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000035c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000360: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000364: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000368: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000036c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000370: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000374: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000378: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000037c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000380: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000384: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000388: b662 cpsie i +1000038a: 4770 bx lr + +1000038c : +1000038c: 2301 movs r3, #1 +1000038e: f000 021f and.w r2, r0, #31 +10000392: 4093 lsls r3, r2 +10000394: 0940 lsrs r0, r0, #5 +10000396: b141 cbz r1, 100003aa +10000398: 0080 lsls r0, r0, #2 +1000039a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000039e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003a2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003a6: 6003 str r3, [r0, #0] +100003a8: 4770 bx lr +100003aa: 4a02 ldr r2, [pc, #8] @ (100003b4 ) +100003ac: 3020 adds r0, #32 +100003ae: f842 3020 str.w r3, [r2, r0, lsl #2] +100003b2: 4770 bx lr +100003b4: e000e100 .word 0xe000e100 + +100003b8 : +100003b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ba: 460d mov r5, r1 +100003bc: f3ef 8710 mrs r7, PRIMASK +100003c0: b672 cpsid i +100003c2: 4e12 ldr r6, [pc, #72] @ (1000040c ) +100003c4: e8d6 2fcf ldaexb r2, [r6] +100003c8: 2301 movs r3, #1 +100003ca: 2a00 cmp r2, #0 +100003cc: d1fa bne.n 100003c4 +100003ce: e8c6 3f42 strexb r2, r3, [r6] +100003d2: 2a00 cmp r2, #0 +100003d4: d1f6 bne.n 100003c4 +100003d6: f3bf 8f5f dmb sy +100003da: 4b0d ldr r3, [pc, #52] @ (10000410 ) +100003dc: f100 0410 add.w r4, r0, #16 +100003e0: 689b ldr r3, [r3, #8] +100003e2: 4a0c ldr r2, [pc, #48] @ (10000414 ) +100003e4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003e8: 4293 cmp r3, r2 +100003ea: d003 beq.n 100003f4 +100003ec: 4299 cmp r1, r3 +100003ee: d001 beq.n 100003f4 +100003f0: f000 fe8e bl 10001110 +100003f4: 4b06 ldr r3, [pc, #24] @ (10000410 ) +100003f6: 689b ldr r3, [r3, #8] +100003f8: f843 5024 str.w r5, [r3, r4, lsl #2] +100003fc: f3bf 8f5f dmb sy +10000400: 2300 movs r3, #0 +10000402: e8c6 3f8f stlb r3, [r6] +10000406: f387 8810 msr PRIMASK, r7 +1000040a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000040c: 20000439 .word 0x20000439 +10000410: e000ed00 .word 0xe000ed00 +10000414: 10000111 .word 0x10000111 + +10000418 : +10000418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000041c: b083 sub sp, #12 +1000041e: f3ef 8a10 mrs sl, PRIMASK +10000422: b672 cpsid i +10000424: 4e71 ldr r6, [pc, #452] @ (100005ec ) +10000426: e8d6 2fcf ldaexb r2, [r6] +1000042a: 2301 movs r3, #1 +1000042c: 2a00 cmp r2, #0 +1000042e: d1fa bne.n 10000426 +10000430: e8c6 3f42 strexb r2, r3, [r6] +10000434: 2a00 cmp r2, #0 +10000436: d1f6 bne.n 10000426 +10000438: f3bf 8f5f dmb sy +1000043c: 4b6c ldr r3, [pc, #432] @ (100005f0 ) +1000043e: f100 0810 add.w r8, r0, #16 +10000442: 689b ldr r3, [r3, #8] +10000444: 4a6b ldr r2, [pc, #428] @ (100005f4 ) +10000446: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000044a: 4295 cmp r5, r2 +1000044c: d045 beq.n 100004da +1000044e: 428d cmp r5, r1 +10000450: 460c mov r4, r1 +10000452: d050 beq.n 100004f6 +10000454: 4f68 ldr r7, [pc, #416] @ (100005f8 ) +10000456: 1beb subs r3, r5, r7 +10000458: 2b2f cmp r3, #47 @ 0x2f +1000045a: d83e bhi.n 100004da +1000045c: 2101 movs r1, #1 +1000045e: ea4f 1950 mov.w r9, r0, lsr #5 +10000462: ea4f 0989 mov.w r9, r9, lsl #2 +10000466: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000046a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000046e: f000 031f and.w r3, r0, #31 +10000472: fa01 f003 lsl.w r0, r1, r3 +10000476: f8d9 3000 ldr.w r3, [r9] +1000047a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000047e: ea00 0b03 and.w fp, r0, r3 +10000482: f3bf 8f5f dmb sy +10000486: f3ef 8105 mrs r1, IPSR +1000048a: b2c9 uxtb r1, r1 +1000048c: 2900 cmp r1, #0 +1000048e: d034 beq.n 100004fa +10000490: 4588 cmp r8, r1 +10000492: d005 beq.n 100004a0 +10000494: e9cd 1000 strd r1, r0, [sp] +10000498: f000 fe3a bl 10001110 +1000049c: e9dd 1000 ldrd r1, r0, [sp] +100004a0: f025 0e01 bic.w lr, r5, #1 +100004a4: f8de c008 ldr.w ip, [lr, #8] +100004a8: 4564 cmp r4, ip +100004aa: d105 bne.n 100004b8 +100004ac: e089 b.n 100005c2 +100004ae: f8d3 c008 ldr.w ip, [r3, #8] +100004b2: 4564 cmp r4, ip +100004b4: d031 beq.n 1000051a +100004b6: 469e mov lr, r3 +100004b8: f99e 2006 ldrsb.w r2, [lr, #6] +100004bc: eb02 0342 add.w r3, r2, r2, lsl #1 +100004c0: 2a00 cmp r2, #0 +100004c2: eb07 0383 add.w r3, r7, r3, lsl #2 +100004c6: daf2 bge.n 100004ae +100004c8: 4564 cmp r4, ip +100004ca: d061 beq.n 10000590 +100004cc: f1bb 0f00 cmp.w fp, #0 +100004d0: d020 beq.n 10000514 +100004d2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004d6: f8c9 0000 str.w r0, [r9] +100004da: 4b45 ldr r3, [pc, #276] @ (100005f0 ) +100004dc: 689b ldr r3, [r3, #8] +100004de: f843 5028 str.w r5, [r3, r8, lsl #2] +100004e2: f3bf 8f5f dmb sy +100004e6: 2300 movs r3, #0 +100004e8: e8c6 3f8f stlb r3, [r6] +100004ec: f38a 8810 msr PRIMASK, sl +100004f0: b003 add sp, #12 +100004f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100004f6: 4615 mov r5, r2 +100004f8: e7ef b.n 100004da +100004fa: f025 0e01 bic.w lr, r5, #1 +100004fe: f8de c008 ldr.w ip, [lr, #8] +10000502: 4564 cmp r4, ip +10000504: d1d8 bne.n 100004b8 +10000506: f99e 4006 ldrsb.w r4, [lr, #6] +1000050a: 4673 mov r3, lr +1000050c: 2c00 cmp r4, #0 +1000050e: da08 bge.n 10000522 +10000510: 4615 mov r5, r2 +10000512: e046 b.n 100005a2 +10000514: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000518: e7df b.n 100004da +1000051a: f993 4006 ldrsb.w r4, [r3, #6] +1000051e: 2c00 cmp r4, #0 +10000520: db37 blt.n 10000592 +10000522: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000526: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000052a: f89c 1007 ldrb.w r1, [ip, #7] +1000052e: f8dc 2008 ldr.w r2, [ip, #8] +10000532: 71d9 strb r1, [r3, #7] +10000534: 609a str r2, [r3, #8] +10000536: f99c 2006 ldrsb.w r2, [ip, #6] +1000053a: 0061 lsls r1, r4, #1 +1000053c: 2a00 cmp r2, #0 +1000053e: 719a strb r2, [r3, #6] +10000540: db3d blt.n 100005be +10000542: f8bc e004 ldrh.w lr, [ip, #4] +10000546: ea5f 5e4e movs.w lr, lr, lsl #21 +1000054a: d505 bpl.n 10000558 +1000054c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000550: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000554: f10e 0e1f add.w lr, lr, #31 +10000558: f06f 0c07 mvn.w ip, #7 +1000055c: 190a adds r2, r1, r4 +1000055e: ea4f 5e6e mov.w lr, lr, asr #21 +10000562: 0092 lsls r2, r2, #2 +10000564: eb02 024e add.w r2, r2, lr, lsl #1 +10000568: 3208 adds r2, #8 +1000056a: 443a add r2, r7 +1000056c: ebac 0c03 sub.w ip, ip, r3 +10000570: 4462 add r2, ip +10000572: f3c2 024a ubfx r2, r2, #1, #11 +10000576: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000057a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000057e: 809a strh r2, [r3, #4] +10000580: 4b1e ldr r3, [pc, #120] @ (100005fc ) +10000582: 4421 add r1, r4 +10000584: 781a ldrb r2, [r3, #0] +10000586: eb07 0181 add.w r1, r7, r1, lsl #2 +1000058a: 701c strb r4, [r3, #0] +1000058c: 718a strb r2, [r1, #6] +1000058e: e79d b.n 100004cc +10000590: 4673 mov r3, lr +10000592: b9d9 cbnz r1, 100005cc +10000594: 22ff movs r2, #255 @ 0xff +10000596: f88e 2006 strb.w r2, [lr, #6] +1000059a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000059e: f8ae 2004 strh.w r2, [lr, #4] +100005a2: 4c16 ldr r4, [pc, #88] @ (100005fc ) +100005a4: f64a 22aa movw r2, #43690 @ 0xaaaa +100005a8: f894 c000 ldrb.w ip, [r4] +100005ac: 4619 mov r1, r3 +100005ae: 1bc9 subs r1, r1, r7 +100005b0: 4149 adcs r1, r1 +100005b2: 434a muls r2, r1 +100005b4: 0d12 lsrs r2, r2, #20 +100005b6: f883 c006 strb.w ip, [r3, #6] +100005ba: 7022 strb r2, [r4, #0] +100005bc: e786 b.n 100004cc +100005be: 4a10 ldr r2, [pc, #64] @ (10000600 ) +100005c0: e7dd b.n 1000057e +100005c2: f99e 4006 ldrsb.w r4, [lr, #6] +100005c6: 4673 mov r3, lr +100005c8: 2c00 cmp r4, #0 +100005ca: daaa bge.n 10000522 +100005cc: 4a0d ldr r2, [pc, #52] @ (10000604 ) +100005ce: 4c0e ldr r4, [pc, #56] @ (10000608 ) +100005d0: 1ad2 subs r2, r2, r3 +100005d2: 3a08 subs r2, #8 +100005d4: f3c2 310a ubfx r1, r2, #12, #11 +100005d8: ea6f 5101 mvn.w r1, r1, lsl #20 +100005dc: ea6f 5111 mvn.w r1, r1, lsr #20 +100005e0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005e4: 80da strh r2, [r3, #6] +100005e6: 8099 strh r1, [r3, #4] +100005e8: e770 b.n 100004cc +100005ea: bf00 nop +100005ec: 20000439 .word 0x20000439 +100005f0: e000ed00 .word 0xe000ed00 +100005f4: 10000111 .word 0x10000111 +100005f8: 2000022c .word 0x2000022c +100005fc: 200004d4 .word 0x200004d4 +10000600: ffffbd01 .word 0xffffbd01 +10000604: 20000266 .word 0x20000266 +10000608: fffff800 .word 0xfffff800 + +1000060c : +1000060c: b5f0 push {r4, r5, r6, r7, lr} +1000060e: f3ef 8505 mrs r5, IPSR +10000612: b2ed uxtb r5, r5 +10000614: f3ef 8c10 mrs ip, PRIMASK +10000618: b672 cpsid i +1000061a: 4926 ldr r1, [pc, #152] @ (100006b4 ) +1000061c: e8d1 2fcf ldaexb r2, [r1] +10000620: 2301 movs r3, #1 +10000622: 2a00 cmp r2, #0 +10000624: d1fa bne.n 1000061c +10000626: e8c1 3f42 strexb r2, r3, [r1] +1000062a: 2a00 cmp r2, #0 +1000062c: d1f6 bne.n 1000061c +1000062e: f3bf 8f5f dmb sy +10000632: 4e21 ldr r6, [pc, #132] @ (100006b8 ) +10000634: f040 0e01 orr.w lr, r0, #1 +10000638: 68b4 ldr r4, [r6, #8] +1000063a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000063e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000642: 4a1e ldr r2, [pc, #120] @ (100006bc ) +10000644: 4604 mov r4, r0 +10000646: 1aa4 subs r4, r4, r2 +10000648: 4164 adcs r4, r4 +1000064a: 4363 muls r3, r4 +1000064c: 0d1b lsrs r3, r3, #20 +1000064e: 4577 cmp r7, lr +10000650: b25b sxtb r3, r3 +10000652: d01b beq.n 1000068c +10000654: f992 4006 ldrsb.w r4, [r2, #6] +10000658: 429c cmp r4, r3 +1000065a: d01c beq.n 10000696 +1000065c: f992 4012 ldrsb.w r4, [r2, #18] +10000660: 429c cmp r4, r3 +10000662: d023 beq.n 100006ac +10000664: f992 401e ldrsb.w r4, [r2, #30] +10000668: 429c cmp r4, r3 +1000066a: d021 beq.n 100006b0 +1000066c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000670: 429c cmp r4, r3 +10000672: bf08 it eq +10000674: 2403 moveq r4, #3 +10000676: d00f beq.n 10000698 +10000678: 4a11 ldr r2, [pc, #68] @ (100006c0 ) +1000067a: 2400 movs r4, #0 +1000067c: 7815 ldrb r5, [r2, #0] +1000067e: 7013 strb r3, [r2, #0] +10000680: 7185 strb r5, [r0, #6] +10000682: e8c1 4f8f stlb r4, [r1] +10000686: f38c 8810 msr PRIMASK, ip +1000068a: bdf0 pop {r4, r5, r6, r7, pc} +1000068c: 68b2 ldr r2, [r6, #8] +1000068e: 4c0d ldr r4, [pc, #52] @ (100006c4 ) +10000690: f842 4025 str.w r4, [r2, r5, lsl #2] +10000694: e7f0 b.n 10000678 +10000696: 2400 movs r4, #0 +10000698: eb04 0444 add.w r4, r4, r4, lsl #1 +1000069c: eb02 0284 add.w r2, r2, r4, lsl #2 +100006a0: 24ff movs r4, #255 @ 0xff +100006a2: 7194 strb r4, [r2, #6] +100006a4: f64b 5401 movw r4, #48385 @ 0xbd01 +100006a8: 8094 strh r4, [r2, #4] +100006aa: e7e5 b.n 10000678 +100006ac: 2401 movs r4, #1 +100006ae: e7f3 b.n 10000698 +100006b0: 2402 movs r4, #2 +100006b2: e7f1 b.n 10000698 +100006b4: 20000439 .word 0x20000439 +100006b8: e000ed00 .word 0xe000ed00 +100006bc: 2000022c .word 0x2000022c +100006c0: 200004d4 .word 0x200004d4 +100006c4: 10000111 .word 0x10000111 + +100006c8 : +100006c8: 4b01 ldr r3, [pc, #4] @ (100006d0 ) +100006ca: 440b add r3, r1 +100006cc: 6003 str r3, [r0, #0] +100006ce: 4770 bx lr +100006d0: 20000430 .word 0x20000430 + +100006d4 : +100006d4: b570 push {r4, r5, r6, lr} +100006d6: 4c10 ldr r4, [pc, #64] @ (10000718 ) +100006d8: 4d10 ldr r5, [pc, #64] @ (1000071c ) +100006da: 42ac cmp r4, r5 +100006dc: d20e bcs.n 100006fc +100006de: 26ff movs r6, #255 @ 0xff +100006e0: 6823 ldr r3, [r4, #0] +100006e2: b163 cbz r3, 100006fe +100006e4: f7ff fe12 bl 1000030c +100006e8: 4601 mov r1, r0 +100006ea: 4620 mov r0, r4 +100006ec: f7ff ffec bl 100006c8 +100006f0: 80a6 strh r6, [r4, #4] +100006f2: f3bf 8f5f dmb sy +100006f6: 3408 adds r4, #8 +100006f8: 42ac cmp r4, r5 +100006fa: d3f1 bcc.n 100006e0 +100006fc: bd70 pop {r4, r5, r6, pc} +100006fe: f7ff fe05 bl 1000030c +10000702: 4601 mov r1, r0 +10000704: 4620 mov r0, r4 +10000706: f7ff ffdf bl 100006c8 +1000070a: 7126 strb r6, [r4, #4] +1000070c: f3bf 8f5f dmb sy +10000710: 3408 adds r4, #8 +10000712: 42ac cmp r4, r5 +10000714: d3e4 bcc.n 100006e0 +10000716: bd70 pop {r4, r5, r6, pc} +10000718: 200002a4 .word 0x200002a4 +1000071c: 200002ac .word 0x200002ac + +10000720 : +10000720: 4b0d ldr r3, [pc, #52] @ (10000758 ) +10000722: 681a ldr r2, [r3, #0] +10000724: f3ef 8110 mrs r1, PRIMASK +10000728: b672 cpsid i +1000072a: e8d2 cfcf ldaexb ip, [r2] +1000072e: 2001 movs r0, #1 +10000730: f1bc 0f00 cmp.w ip, #0 +10000734: d1f9 bne.n 1000072a +10000736: e8c2 0f4c strexb ip, r0, [r2] +1000073a: f1bc 0f00 cmp.w ip, #0 +1000073e: d1f4 bne.n 1000072a +10000740: f3bf 8f5f dmb sy +10000744: 2200 movs r2, #0 +10000746: 681b ldr r3, [r3, #0] +10000748: e8c3 2f8f stlb r2, [r3] +1000074c: f381 8810 msr PRIMASK, r1 +10000750: bf40 sev +10000752: 2000 movs r0, #0 +10000754: 2100 movs r1, #0 +10000756: 4770 bx lr +10000758: 200004c8 .word 0x200004c8 +1000075c: 00000000 .word 0x00000000 + +10000760 : +10000760: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000764: ed2d 8b02 vpush {d8} +10000768: b085 sub sp, #20 +1000076a: f3ef 8305 mrs r3, IPSR +1000076e: b2db uxtb r3, r3 +10000770: 3b10 subs r3, #16 +10000772: 089a lsrs r2, r3, #2 +10000774: bf18 it ne +10000776: 2201 movne r2, #1 +10000778: f04f 0101 mov.w r1, #1 +1000077c: f003 0b03 and.w fp, r3, #3 +10000780: bf18 it ne +10000782: 4daf ldrne r5, [pc, #700] @ (10000a40 ) +10000784: 4baf ldr r3, [pc, #700] @ (10000a44 ) +10000786: bf08 it eq +10000788: 4daf ldreq r5, [pc, #700] @ (10000a48 ) +1000078a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000078e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000792: fa01 f20b lsl.w r2, r1, fp +10000796: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000079a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a38 +1000079e: 9201 str r2, [sp, #4] +100007a0: 605a str r2, [r3, #4] +100007a2: e02f b.n 10000804 +100007a4: 88b3 ldrh r3, [r6, #4] +100007a6: 041c lsls r4, r3, #16 +100007a8: f140 8093 bpl.w 100008d2 +100007ac: 79b3 ldrb r3, [r6, #6] +100007ae: 2b00 cmp r3, #0 +100007b0: f040 80dd bne.w 1000096e +100007b4: f9b6 2008 ldrsh.w r2, [r6, #8] +100007b8: 2a00 cmp r2, #0 +100007ba: f2c0 811e blt.w 100009fa +100007be: 6973 ldr r3, [r6, #20] +100007c0: eb02 0242 add.w r2, r2, r2, lsl #1 +100007c4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007c8: e9d3 4702 ldrd r4, r7, [r3, #8] +100007cc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007d0: bf08 it eq +100007d2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007d6: d00e beq.n 100007f6 +100007d8: eb05 018b add.w r1, r5, fp, lsl #2 +100007dc: 6aab ldr r3, [r5, #40] @ 0x28 +100007de: 690a ldr r2, [r1, #16] +100007e0: 1ad2 subs r2, r2, r3 +100007e2: 1ae3 subs r3, r4, r3 +100007e4: 4293 cmp r3, r2 +100007e6: d305 bcc.n 100007f4 +100007e8: 2301 movs r3, #1 +100007ea: 6a2a ldr r2, [r5, #32] +100007ec: fa03 f30b lsl.w r3, r3, fp +100007f0: 4213 tst r3, r2 +100007f2: d100 bne.n 100007f6 +100007f4: 610c str r4, [r1, #16] +100007f6: 4628 mov r0, r5 +100007f8: f000 faca bl 10000d90 +100007fc: 42a0 cmp r0, r4 +100007fe: 41b9 sbcs r1, r7 +10000800: f2c0 80fb blt.w 100009fa +10000804: f9b6 3008 ldrsh.w r3, [r6, #8] +10000808: 9a01 ldr r2, [sp, #4] +1000080a: 2b00 cmp r3, #0 +1000080c: 9300 str r3, [sp, #0] +1000080e: 63ea str r2, [r5, #60] @ 0x3c +10000810: dbc8 blt.n 100007a4 +10000812: f8d6 8014 ldr.w r8, [r6, #20] +10000816: eb03 0943 add.w r9, r3, r3, lsl #1 +1000081a: 4628 mov r0, r5 +1000081c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000820: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000824: f000 fab4 bl 10000d90 +10000828: 42a0 cmp r0, r4 +1000082a: eb71 010a sbcs.w r1, r1, sl +1000082e: dbb9 blt.n 100007a4 +10000830: f1ba 0f00 cmp.w sl, #0 +10000834: f2c0 80c3 blt.w 100009be +10000838: e9d7 3104 ldrd r3, r1, [r7, #16] +1000083c: 4a83 ldr r2, [pc, #524] @ (10000a4c ) +1000083e: 4293 cmp r3, r2 +10000840: f000 80ed beq.w 10000a1e +10000844: 887a ldrh r2, [r7, #2] +10000846: f9b6 0008 ldrsh.w r0, [r6, #8] +1000084a: b292 uxth r2, r2 +1000084c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000850: 4798 blx r3 +10000852: 4602 mov r2, r0 +10000854: 460b mov r3, r1 +10000856: ea52 0103 orrs.w r1, r2, r3 +1000085a: f000 80b0 beq.w 100009be +1000085e: 2b00 cmp r3, #0 +10000860: f280 80d1 bge.w 10000a06 +10000864: ebb4 0e02 subs.w lr, r4, r2 +10000868: eb6a 0a03 sbc.w sl, sl, r3 +1000086c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000870: e9c7 ea02 strd lr, sl, [r7, #8] +10000874: 2b00 cmp r3, #0 +10000876: db95 blt.n 100007a4 +10000878: 6971 ldr r1, [r6, #20] +1000087a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000087e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000882: e9d2 7002 ldrd r7, r0, [r2, #8] +10000886: 45be cmp lr, r7 +10000888: eb7a 0c00 sbcs.w ip, sl, r0 +1000088c: ea4f 0243 mov.w r2, r3, lsl #1 +10000890: db88 blt.n 100007a4 +10000892: 46b4 mov ip, r6 +10000894: f82c 3f08 strh.w r3, [ip, #8]! +10000898: e006 b.n 100008a8 +1000089a: eb03 0043 add.w r0, r3, r3, lsl #1 +1000089e: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008a2: 005a lsls r2, r3, #1 +100008a4: e9d0 7002 ldrd r7, r0, [r0, #8] +100008a8: 45be cmp lr, r7 +100008aa: 441a add r2, r3 +100008ac: eb7a 0000 sbcs.w r0, sl, r0 +100008b0: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008b4: db04 blt.n 100008c0 +100008b6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008ba: 46a4 mov ip, r4 +100008bc: 2b00 cmp r3, #0 +100008be: daec bge.n 1000089a +100008c0: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008c4: 9b00 ldr r3, [sp, #0] +100008c6: f8ac 3000 strh.w r3, [ip] +100008ca: 88b3 ldrh r3, [r6, #4] +100008cc: 041c lsls r4, r3, #16 +100008ce: f53f af6d bmi.w 100007ac +100008d2: 6933 ldr r3, [r6, #16] +100008d4: f3ef 8210 mrs r2, PRIMASK +100008d8: b672 cpsid i +100008da: e8d3 0fcf ldaexb r0, [r3] +100008de: 2101 movs r1, #1 +100008e0: 2800 cmp r0, #0 +100008e2: d1fa bne.n 100008da +100008e4: e8c3 1f40 strexb r0, r1, [r3] +100008e8: 2800 cmp r0, #0 +100008ea: d1f6 bne.n 100008da +100008ec: f3bf 8f5f dmb sy +100008f0: f64f 74ff movw r4, #65535 @ 0xffff +100008f4: 88b0 ldrh r0, [r6, #4] +100008f6: 2300 movs r3, #0 +100008f8: 6931 ldr r1, [r6, #16] +100008fa: b200 sxth r0, r0 +100008fc: 80b4 strh r4, [r6, #4] +100008fe: e8c1 3f8f stlb r3, [r1] +10000902: f382 8810 msr PRIMASK, r2 +10000906: 4298 cmp r0, r3 +10000908: f6ff af50 blt.w 100007ac +1000090c: 4607 mov r7, r0 +1000090e: 46a9 mov r9, r5 +10000910: 6974 ldr r4, [r6, #20] +10000912: f106 0808 add.w r8, r6, #8 +10000916: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000091a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000091e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000922: f9b6 3008 ldrsh.w r3, [r6, #8] +10000926: 46c4 mov ip, r8 +10000928: 2b00 cmp r3, #0 +1000092a: db13 blt.n 10000954 +1000092c: 46b2 mov sl, r6 +1000092e: 9700 str r7, [sp, #0] +10000930: e004 b.n 1000093c +10000932: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000936: 4694 mov ip, r2 +10000938: 2b00 cmp r3, #0 +1000093a: db09 blt.n 10000950 +1000093c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000940: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000944: e9d2 7102 ldrd r7, r1, [r2, #8] +10000948: 42bd cmp r5, r7 +1000094a: eb70 0101 sbcs.w r1, r0, r1 +1000094e: daf0 bge.n 10000932 +10000950: 4656 mov r6, sl +10000952: 9f00 ldr r7, [sp, #0] +10000954: f8ac 7000 strh.w r7, [ip] +10000958: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000095c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000960: 2f00 cmp r7, #0 +10000962: dad8 bge.n 10000916 +10000964: 79b3 ldrb r3, [r6, #6] +10000966: 464d mov r5, r9 +10000968: 2b00 cmp r3, #0 +1000096a: f43f af23 beq.w 100007b4 +1000096e: 2300 movs r3, #0 +10000970: 71b3 strb r3, [r6, #6] +10000972: f9b6 3008 ldrsh.w r3, [r6, #8] +10000976: f106 0808 add.w r8, r6, #8 +1000097a: 1c58 adds r0, r3, #1 +1000097c: d03d beq.n 100009fa +1000097e: 461a mov r2, r3 +10000980: 6977 ldr r7, [r6, #20] +10000982: e003 b.n 1000098c +10000984: 4680 mov r8, r0 +10000986: 1c59 adds r1, r3, #1 +10000988: f43f af16 beq.w 100007b8 +1000098c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000990: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000994: f8b0 c002 ldrh.w ip, [r0, #2] +10000998: 461c mov r4, r3 +1000099a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +1000099e: 469e mov lr, r3 +100009a0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009a4: d0ee beq.n 10000984 +100009a6: 4294 cmp r4, r2 +100009a8: ed80 8b02 vstr d8, [r0, #8] +100009ac: d005 beq.n 100009ba +100009ae: f8a8 3000 strh.w r3, [r8] +100009b2: 8932 ldrh r2, [r6, #8] +100009b4: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009b8: 8134 strh r4, [r6, #8] +100009ba: 4672 mov r2, lr +100009bc: e7e3 b.n 10000986 +100009be: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009c2: 8133 strh r3, [r6, #8] +100009c4: 6933 ldr r3, [r6, #16] +100009c6: f3ef 8210 mrs r2, PRIMASK +100009ca: b672 cpsid i +100009cc: e8d3 0fcf ldaexb r0, [r3] +100009d0: 2101 movs r1, #1 +100009d2: 2800 cmp r0, #0 +100009d4: d1fa bne.n 100009cc +100009d6: e8c3 1f40 strexb r0, r1, [r3] +100009da: 2800 cmp r0, #0 +100009dc: d1f6 bne.n 100009cc +100009de: f3bf 8f5f dmb sy +100009e2: 8873 ldrh r3, [r6, #2] +100009e4: 6931 ldr r1, [r6, #16] +100009e6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009ea: 9b00 ldr r3, [sp, #0] +100009ec: 8073 strh r3, [r6, #2] +100009ee: 2300 movs r3, #0 +100009f0: e8c1 3f8f stlb r3, [r1] +100009f4: f382 8810 msr PRIMASK, r2 +100009f8: e6d4 b.n 100007a4 +100009fa: bf40 sev +100009fc: b005 add sp, #20 +100009fe: ecbd 8b02 vpop {d8} +10000a02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a06: 4628 mov r0, r5 +10000a08: e9cd 2302 strd r2, r3, [sp, #8] +10000a0c: f000 f9c0 bl 10000d90 +10000a10: 9a02 ldr r2, [sp, #8] +10000a12: 9b03 ldr r3, [sp, #12] +10000a14: eb10 0e02 adds.w lr, r0, r2 +10000a18: eb43 0a01 adc.w sl, r3, r1 +10000a1c: e726 b.n 1000086c +10000a1e: 4608 mov r0, r1 +10000a20: 690b ldr r3, [r1, #16] +10000a22: 9102 str r1, [sp, #8] +10000a24: 4798 blx r3 +10000a26: 2800 cmp r0, #0 +10000a28: d0c9 beq.n 100009be +10000a2a: 9902 ldr r1, [sp, #8] +10000a2c: e9d1 2300 ldrd r2, r3, [r1] +10000a30: e711 b.n 10000856 +10000a32: bf00 nop +10000a34: f3af 8000 nop.w +10000a38: ffffffff .word 0xffffffff +10000a3c: ffffffff .word 0xffffffff +10000a40: 400b8000 .word 0x400b8000 +10000a44: 200004a8 .word 0x200004a8 +10000a48: 400b0000 .word 0x400b0000 +10000a4c: 10000761 .word 0x10000761 + +10000a50 : +10000a50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a54: 4c36 ldr r4, [pc, #216] @ (10000b30 ) +10000a56: 6925 ldr r5, [r4, #16] +10000a58: b12d cbz r5, 10000a66 +10000a5a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a5e: 210a movs r1, #10 +10000a60: 4834 ldr r0, [pc, #208] @ (10000b34 ) +10000a62: f7ff be31 b.w 100006c8 +10000a66: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b4c +10000a6a: 2103 movs r1, #3 +10000a6c: 4640 mov r0, r8 +10000a6e: f000 f97d bl 10000d6c +10000a72: 2603 movs r6, #3 +10000a74: f8c4 800c str.w r8, [r4, #12] +10000a78: f7ff fc48 bl 1000030c +10000a7c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a80: 4b2d ldr r3, [pc, #180] @ (10000b38 ) +10000a82: 7026 strb r6, [r4, #0] +10000a84: 4403 add r3, r0 +10000a86: 6123 str r3, [r4, #16] +10000a88: f8dc 3000 ldr.w r3, [ip] +10000a8c: 210f movs r1, #15 +10000a8e: 7063 strb r3, [r4, #1] +10000a90: 6963 ldr r3, [r4, #20] +10000a92: 8061 strh r1, [r4, #2] +10000a94: 831d strh r5, [r3, #24] +10000a96: f04f 0504 mov.w r5, #4 +10000a9a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000a9e: f04f 0505 mov.w r5, #5 +10000aa2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000aa6: f04f 0506 mov.w r5, #6 +10000aaa: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000aae: f04f 0507 mov.w r5, #7 +10000ab2: 210e movs r1, #14 +10000ab4: f64f 72ff movw r2, #65535 @ 0xffff +10000ab8: 2708 movs r7, #8 +10000aba: f04f 0e0a mov.w lr, #10 +10000abe: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000ac2: f04f 0901 mov.w r9, #1 +10000ac6: f04f 0c0c mov.w ip, #12 +10000aca: f04f 0b02 mov.w fp, #2 +10000ace: f04f 0a09 mov.w sl, #9 +10000ad2: 200d movs r0, #13 +10000ad4: f04f 050b mov.w r5, #11 +10000ad8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000adc: 4917 ldr r1, [pc, #92] @ (10000b3c ) +10000ade: 80a2 strh r2, [r4, #4] +10000ae0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000ae4: 60a1 str r1, [r4, #8] +10000ae6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000aea: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000aee: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000af2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000af6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000afa: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000afe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b02: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b06: 801a strh r2, [r3, #0] +10000b08: 4b0d ldr r3, [pc, #52] @ (10000b40 ) +10000b0a: 4630 mov r0, r6 +10000b0c: f8c8 7020 str.w r7, [r8, #32] +10000b10: 490c ldr r1, [pc, #48] @ (10000b44 ) +10000b12: 60dc str r4, [r3, #12] +10000b14: f7ff fc50 bl 100003b8 +10000b18: 4649 mov r1, r9 +10000b1a: 4630 mov r0, r6 +10000b1c: f7ff fc36 bl 1000038c +10000b20: 4b09 ldr r3, [pc, #36] @ (10000b48 ) +10000b22: 210a movs r1, #10 +10000b24: 641f str r7, [r3, #64] @ 0x40 +10000b26: 4803 ldr r0, [pc, #12] @ (10000b34 ) +10000b28: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b2c: f7ff bdcc b.w 100006c8 +10000b30: 20000274 .word 0x20000274 +10000b34: 200004c8 .word 0x200004c8 +10000b38: 20000430 .word 0x20000430 +10000b3c: 0010ffff .word 0x0010ffff +10000b40: 200004a8 .word 0x200004a8 +10000b44: 10000761 .word 0x10000761 +10000b48: 400b2000 .word 0x400b2000 +10000b4c: 400b0000 .word 0x400b0000 + +10000b50 : +10000b50: 4601 mov r1, r0 +10000b52: b5f0 push {r4, r5, r6, r7, lr} +10000b54: 6900 ldr r0, [r0, #16] +10000b56: f3ef 8710 mrs r7, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d0 5fcf ldaexb r5, [r0] +10000b60: 2401 movs r4, #1 +10000b62: 2d00 cmp r5, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c0 4f45 strexb r5, r4, [r0] +10000b6a: 2d00 cmp r5, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b76: 694c ldr r4, [r1, #20] +10000b78: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b7c: f1be 0f00 cmp.w lr, #0 +10000b80: ea4f 05cc mov.w r5, ip, lsl #3 +10000b84: 6908 ldr r0, [r1, #16] +10000b86: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b8a: db3c blt.n 10000c06 +10000b8c: 5b66 ldrh r6, [r4, r5] +10000b8e: 804e strh r6, [r1, #2] +10000b90: 2600 movs r6, #0 +10000b92: e8c0 6f8f stlb r6, [r0] +10000b96: f387 8810 msr PRIMASK, r7 +10000b9a: f8bc 0002 ldrh.w r0, [ip, #2] +10000b9e: e9cc 2302 strd r2, r3, [ip, #8] +10000ba2: 3001 adds r0, #1 +10000ba4: f3c0 000e ubfx r0, r0, #0, #15 +10000ba8: 2801 cmp r0, #1 +10000baa: bf38 it cc +10000bac: 2001 movcc r0, #1 +10000bae: 9b05 ldr r3, [sp, #20] +10000bb0: f8ac 0002 strh.w r0, [ip, #2] +10000bb4: f8cc 3010 str.w r3, [ip, #16] +10000bb8: 9b06 ldr r3, [sp, #24] +10000bba: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bbe: f8cc 3014 str.w r3, [ip, #20] +10000bc2: 690b ldr r3, [r1, #16] +10000bc4: f3ef 8210 mrs r2, PRIMASK +10000bc8: b672 cpsid i +10000bca: e8d3 cfcf ldaexb ip, [r3] +10000bce: 2701 movs r7, #1 +10000bd0: f1bc 0f00 cmp.w ip, #0 +10000bd4: d1f9 bne.n 10000bca +10000bd6: e8c3 7f4c strexb ip, r7, [r3] +10000bda: f1bc 0f00 cmp.w ip, #0 +10000bde: d1f4 bne.n 10000bca +10000be0: f3bf 8f5f dmb sy +10000be4: 888b ldrh r3, [r1, #4] +10000be6: 5363 strh r3, [r4, r5] +10000be8: f8a1 e004 strh.w lr, [r1, #4] +10000bec: 690b ldr r3, [r1, #16] +10000bee: e8c3 6f8f stlb r6, [r3] +10000bf2: f382 8810 msr PRIMASK, r2 +10000bf6: 2201 movs r2, #1 +10000bf8: 68cb ldr r3, [r1, #12] +10000bfa: 7809 ldrb r1, [r1, #0] +10000bfc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c00: 408a lsls r2, r1 +10000c02: 605a str r2, [r3, #4] +10000c04: bdf0 pop {r4, r5, r6, r7, pc} +10000c06: 2300 movs r3, #0 +10000c08: e8c0 3f8f stlb r3, [r0] +10000c0c: f387 8810 msr PRIMASK, r7 +10000c10: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c14: bdf0 pop {r4, r5, r6, r7, pc} +10000c16: bf00 nop + +10000c18 : +10000c18: 4603 mov r3, r0 +10000c1a: 8940 ldrh r0, [r0, #10] +10000c1c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c20: dd37 ble.n 10000c92 +10000c22: 6958 ldr r0, [r3, #20] +10000c24: 140a asrs r2, r1, #16 +10000c26: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c2a: b510 push {r4, lr} +10000c2c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c30: 691c ldr r4, [r3, #16] +10000c32: f3ef 8c10 mrs ip, PRIMASK +10000c36: b672 cpsid i +10000c38: e8d4 efcf ldaexb lr, [r4] +10000c3c: 2201 movs r2, #1 +10000c3e: f1be 0f00 cmp.w lr, #0 +10000c42: d1f9 bne.n 10000c38 +10000c44: e8c4 2f4e strexb lr, r2, [r4] +10000c48: f1be 0f00 cmp.w lr, #0 +10000c4c: d1f4 bne.n 10000c38 +10000c4e: f3bf 8f5f dmb sy +10000c52: 8842 ldrh r2, [r0, #2] +10000c54: b289 uxth r1, r1 +10000c56: b292 uxth r2, r2 +10000c58: 428a cmp r2, r1 +10000c5a: d007 beq.n 10000c6c +10000c5c: 2200 movs r2, #0 +10000c5e: 691b ldr r3, [r3, #16] +10000c60: e8c3 2f8f stlb r2, [r3] +10000c64: f38c 8810 msr PRIMASK, ip +10000c68: 2000 movs r0, #0 +10000c6a: bd10 pop {r4, pc} +10000c6c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c70: 8042 strh r2, [r0, #2] +10000c72: 2101 movs r1, #1 +10000c74: 2200 movs r2, #0 +10000c76: 6918 ldr r0, [r3, #16] +10000c78: 7199 strb r1, [r3, #6] +10000c7a: e8c0 2f8f stlb r2, [r0] +10000c7e: f38c 8810 msr PRIMASK, ip +10000c82: 781c ldrb r4, [r3, #0] +10000c84: 68da ldr r2, [r3, #12] +10000c86: 4608 mov r0, r1 +10000c88: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c8c: 40a1 lsls r1, r4 +10000c8e: 6059 str r1, [r3, #4] +10000c90: bd10 pop {r4, pc} +10000c92: 2000 movs r0, #0 +10000c94: 4770 bx lr +10000c96: bf00 nop + +10000c98 : +10000c98: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000c9c: 4606 mov r6, r0 +10000c9e: 460d mov r5, r1 +10000ca0: b083 sub sp, #12 +10000ca2: f3ef 8405 mrs r4, IPSR +10000ca6: b2e4 uxtb r4, r4 +10000ca8: b13c cbz r4, 10000cba +10000caa: 4b2d ldr r3, [pc, #180] @ (10000d60 ) +10000cac: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cae: 42aa cmp r2, r5 +10000cb0: d21c bcs.n 10000cec +10000cb2: 2000 movs r0, #0 +10000cb4: b003 add sp, #12 +10000cb6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cba: 4f2a ldr r7, [pc, #168] @ (10000d64 ) +10000cbc: f8d7 900c ldr.w r9, [r7, #12] +10000cc0: f897 8000 ldrb.w r8, [r7] +10000cc4: 4648 mov r0, r9 +10000cc6: f000 f863 bl 10000d90 +10000cca: f108 0804 add.w r8, r8, #4 +10000cce: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000cd2: 1a1b subs r3, r3, r0 +10000cd4: 1a30 subs r0, r6, r0 +10000cd6: eb65 0101 sbc.w r1, r5, r1 +10000cda: 4298 cmp r0, r3 +10000cdc: f171 0100 sbcs.w r1, r1, #0 +10000ce0: db10 blt.n 10000d04 +10000ce2: bf20 wfe +10000ce4: 4b1e ldr r3, [pc, #120] @ (10000d60 ) +10000ce6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ce8: 42aa cmp r2, r5 +10000cea: d3e2 bcc.n 10000cb2 +10000cec: bf14 ite ne +10000cee: 2401 movne r4, #1 +10000cf0: 2400 moveq r4, #0 +10000cf2: 6a9b ldr r3, [r3, #40] @ 0x28 +10000cf4: 42b3 cmp r3, r6 +10000cf6: bf34 ite cc +10000cf8: 4620 movcc r0, r4 +10000cfa: f044 0001 orrcs.w r0, r4, #1 +10000cfe: b003 add sp, #12 +10000d00: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d04: f000 f84c bl 10000da0 +10000d08: 4286 cmp r6, r0 +10000d0a: eb65 0101 sbc.w r1, r5, r1 +10000d0e: 2900 cmp r1, #0 +10000d10: db14 blt.n 10000d3c +10000d12: 4b15 ldr r3, [pc, #84] @ (10000d68 ) +10000d14: 4638 mov r0, r7 +10000d16: e9cd 3400 strd r3, r4, [sp] +10000d1a: 4632 mov r2, r6 +10000d1c: 462b mov r3, r5 +10000d1e: f7ff ff17 bl 10000b50 +10000d22: 1e01 subs r1, r0, #0 +10000d24: dd0a ble.n 10000d3c +10000d26: 4b0e ldr r3, [pc, #56] @ (10000d60 ) +10000d28: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d2a: 42aa cmp r2, r5 +10000d2c: d316 bcc.n 10000d5c +10000d2e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d30: 42b3 cmp r3, r6 +10000d32: d311 bcc.n 10000d58 +10000d34: 480b ldr r0, [pc, #44] @ (10000d64 ) +10000d36: f7ff ff6f bl 10000c18 +10000d3a: e7b6 b.n 10000caa +10000d3c: 4b08 ldr r3, [pc, #32] @ (10000d60 ) +10000d3e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d40: 42ac cmp r4, r5 +10000d42: d3b6 bcc.n 10000cb2 +10000d44: 1b64 subs r4, r4, r5 +10000d46: bf18 it ne +10000d48: 2401 movne r4, #1 +10000d4a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d4c: 42b3 cmp r3, r6 +10000d4e: bf34 ite cc +10000d50: 4620 movcc r0, r4 +10000d52: f044 0001 orrcs.w r0, r4, #1 +10000d56: e7ad b.n 10000cb4 +10000d58: 42aa cmp r2, r5 +10000d5a: d1eb bne.n 10000d34 +10000d5c: bf20 wfe +10000d5e: e7e9 b.n 10000d34 +10000d60: 400b0000 .word 0x400b0000 +10000d64: 20000274 .word 0x20000274 +10000d68: 10000721 .word 0x10000721 + +10000d6c : +10000d6c: b410 push {r4} +10000d6e: 4b05 ldr r3, [pc, #20] @ (10000d84 ) +10000d70: 4c05 ldr r4, [pc, #20] @ (10000d88 ) +10000d72: 4a06 ldr r2, [pc, #24] @ (10000d8c ) +10000d74: 42a0 cmp r0, r4 +10000d76: bf14 ite ne +10000d78: 4618 movne r0, r3 +10000d7a: 1c58 addeq r0, r3, #1 +10000d7c: f85d 4b04 ldr.w r4, [sp], #4 +10000d80: f7ff ba98 b.w 100002b4 +10000d84: 20000458 .word 0x20000458 +10000d88: 400b8000 .word 0x400b8000 +10000d8c: 100019f0 .word 0x100019f0 + +10000d90 : +10000d90: 4603 mov r3, r0 +10000d92: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d94: 460a mov r2, r1 +10000d96: 6a98 ldr r0, [r3, #40] @ 0x28 +10000d98: 6a59 ldr r1, [r3, #36] @ 0x24 +10000d9a: 428a cmp r2, r1 +10000d9c: d1fa bne.n 10000d94 +10000d9e: 4770 bx lr + +10000da0 : +10000da0: 4b03 ldr r3, [pc, #12] @ (10000db0 ) +10000da2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 4291 cmp r1, r2 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr +10000db0: 400b0000 .word 0x400b0000 + +10000db4 : +10000db4: b430 push {r4, r5} +10000db6: 4a15 ldr r2, [pc, #84] @ (10000e0c ) +10000db8: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dba: 469c mov ip, r3 +10000dbc: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dbe: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc0: 4563 cmp r3, ip +10000dc2: d1fa bne.n 10000dba +10000dc4: 1902 adds r2, r0, r4 +10000dc6: 4159 adcs r1, r3 +10000dc8: f04f 0500 mov.w r5, #0 +10000dcc: bf28 it cs +10000dce: 2501 movcs r5, #1 +10000dd0: 4b0e ldr r3, [pc, #56] @ (10000e0c ) +10000dd2: 6a5b ldr r3, [r3, #36] @ 0x24 +10000dd4: b1b5 cbz r5, 10000e04 +10000dd6: 1c5a adds r2, r3, #1 +10000dd8: bf08 it eq +10000dda: 461a moveq r2, r3 +10000ddc: d008 beq.n 10000df0 +10000dde: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000de2: 460a mov r2, r1 +10000de4: 4809 ldr r0, [pc, #36] @ (10000e0c ) +10000de6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000de8: 428b cmp r3, r1 +10000dea: d3fc bcc.n 10000de6 +10000dec: 428b cmp r3, r1 +10000dee: d107 bne.n 10000e00 +10000df0: 4906 ldr r1, [pc, #24] @ (10000e0c ) +10000df2: e002 b.n 10000dfa +10000df4: 6a48 ldr r0, [r1, #36] @ 0x24 +10000df6: 4298 cmp r0, r3 +10000df8: d102 bne.n 10000e00 +10000dfa: 6a88 ldr r0, [r1, #40] @ 0x28 +10000dfc: 4290 cmp r0, r2 +10000dfe: d3f9 bcc.n 10000df4 +10000e00: bc30 pop {r4, r5} +10000e02: 4770 bx lr +10000e04: 4299 cmp r1, r3 +10000e06: d8ed bhi.n 10000de4 +10000e08: e7f0 b.n 10000dec +10000e0a: bf00 nop +10000e0c: 400b0000 .word 0x400b0000 + +10000e10 : +10000e10: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e12: 4605 mov r5, r0 +10000e14: 2006 movs r0, #6 +10000e16: 460e mov r6, r1 +10000e18: f000 f8e4 bl 10000fe4 +10000e1c: 2800 cmp r0, #0 +10000e1e: d042 beq.n 10000ea6 +10000e20: 4a35 ldr r2, [pc, #212] @ (10000ef8 ) +10000e22: 4836 ldr r0, [pc, #216] @ (10000efc ) +10000e24: 4295 cmp r5, r2 +10000e26: bf14 ite ne +10000e28: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e2c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e30: 4b33 ldr r3, [pc, #204] @ (10000f00 ) +10000e32: 4934 ldr r1, [pc, #208] @ (10000f04 ) +10000e34: 6002 str r2, [r0, #0] +10000e36: 601a str r2, [r3, #0] +10000e38: 688c ldr r4, [r1, #8] +10000e3a: ea32 0404 bics.w r4, r2, r4 +10000e3e: d1fb bne.n 10000e38 +10000e40: 4b2d ldr r3, [pc, #180] @ (10000ef8 ) +10000e42: f44f 7180 mov.w r1, #256 @ 0x100 +10000e46: 1aeb subs r3, r5, r3 +10000e48: fab3 f383 clz r3, r3 +10000e4c: 4a2e ldr r2, [pc, #184] @ (10000f08 ) +10000e4e: 095b lsrs r3, r3, #5 +10000e50: 2006 movs r0, #6 +10000e52: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e56: f000 f8c5 bl 10000fe4 +10000e5a: 00c3 lsls r3, r0, #3 +10000e5c: fbb3 f3f6 udiv r3, r3, r6 +10000e60: 3301 adds r3, #1 +10000e62: 09da lsrs r2, r3, #7 +10000e64: d120 bne.n 10000ea8 +10000e66: 2640 movs r6, #64 @ 0x40 +10000e68: 2101 movs r1, #1 +10000e6a: 6269 str r1, [r5, #36] @ 0x24 +10000e6c: 62aa str r2, [r5, #40] @ 0x28 +10000e6e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e70: 07fb lsls r3, r7, #31 +10000e72: d422 bmi.n 10000eba +10000e74: 462b mov r3, r5 +10000e76: 2200 movs r2, #0 +10000e78: f853 1f2c ldr.w r1, [r3, #44]! +10000e7c: 2006 movs r0, #6 +10000e7e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e82: 6022 str r2, [r4, #0] +10000e84: 632f str r7, [r5, #48] @ 0x30 +10000e86: f000 f8ad bl 10000fe4 +10000e8a: f240 3101 movw r1, #769 @ 0x301 +10000e8e: 2203 movs r2, #3 +10000e90: 0080 lsls r0, r0, #2 +10000e92: fbb0 f0f6 udiv r0, r0, r6 +10000e96: 6aeb ldr r3, [r5, #44] @ 0x2c +10000e98: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000e9c: f003 037e and.w r3, r3, #126 @ 0x7e +10000ea0: 6023 str r3, [r4, #0] +10000ea2: 6329 str r1, [r5, #48] @ 0x30 +10000ea4: 64aa str r2, [r5, #72] @ 0x48 +10000ea6: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000ea8: f64f 71fe movw r1, #65534 @ 0xfffe +10000eac: 428a cmp r2, r1 +10000eae: d91b bls.n 10000ee8 +10000eb0: 4622 mov r2, r4 +10000eb2: f64f 71ff movw r1, #65535 @ 0xffff +10000eb6: 4e15 ldr r6, [pc, #84] @ (10000f0c ) +10000eb8: e7d7 b.n 10000e6a +10000eba: f240 3201 movw r2, #769 @ 0x301 +10000ebe: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000ec2: 631a str r2, [r3, #48] @ 0x30 +10000ec4: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ec6: 6aac ldr r4, [r5, #40] @ 0x28 +10000ec8: 2006 movs r0, #6 +10000eca: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ece: f000 f889 bl 10000fe4 +10000ed2: 4b0f ldr r3, [pc, #60] @ (10000f10 ) +10000ed4: 02a4 lsls r4, r4, #10 +10000ed6: fba3 2300 umull r2, r3, r3, r0 +10000eda: 0adb lsrs r3, r3, #11 +10000edc: 2100 movs r1, #0 +10000ede: fbb4 f0f3 udiv r0, r4, r3 +10000ee2: f7ff ff67 bl 10000db4 +10000ee6: e7c5 b.n 10000e74 +10000ee8: f3c3 0345 ubfx r3, r3, #1, #6 +10000eec: 4611 mov r1, r2 +10000eee: eb03 1682 add.w r6, r3, r2, lsl #6 +10000ef2: 461a mov r2, r3 +10000ef4: e7b9 b.n 10000e6a +10000ef6: bf00 nop +10000ef8: 40078000 .word 0x40078000 +10000efc: 40022000 .word 0x40022000 +10000f00: 40023000 .word 0x40023000 +10000f04: 40020000 .word 0x40020000 +10000f08: 200004cc .word 0x200004cc +10000f0c: 003fffc0 .word 0x003fffc0 +10000f10: 8f2b7b75 .word 0x8f2b7b75 + +10000f14 : +10000f14: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f18: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f1c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f20: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f24: b5f0 push {r4, r5, r6, r7, lr} +10000f26: 4616 mov r6, r2 +10000f28: f8dc 2004 ldr.w r2, [ip, #4] +10000f2c: 1f05 subs r5, r0, #4 +10000f2e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f32: bf38 it cc +10000f34: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f38: b2ed uxtb r5, r5 +10000f3a: bf38 it cc +10000f3c: f8cc 2004 strcc.w r2, [ip, #4] +10000f40: 2d01 cmp r5, #1 +10000f42: d92a bls.n 10000f9a +10000f44: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f48: 4c25 ldr r4, [pc, #148] @ (10000fe0 ) +10000f4a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f4e: 6017 str r7, [r2, #0] +10000f50: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f54: b9b2 cbnz r2, 10000f84 +10000f56: f8dc 2000 ldr.w r2, [ip] +10000f5a: 2d01 cmp r5, #1 +10000f5c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f60: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f64: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f68: 6032 str r2, [r6, #0] +10000f6a: d92a bls.n 10000fc2 +10000f6c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f70: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f74: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f78: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f7c: 6011 str r1, [r2, #0] +10000f7e: f8cc 3004 str.w r3, [ip, #4] +10000f82: bdf0 pop {r4, r5, r6, r7, pc} +10000f84: 6967 ldr r7, [r4, #20] +10000f86: fbb7 fef2 udiv lr, r7, r2 +10000f8a: f10e 0e01 add.w lr, lr, #1 +10000f8e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000f92: f1be 0e03 subs.w lr, lr, #3 +10000f96: d2fc bcs.n 10000f92 +10000f98: e7dd b.n 10000f56 +10000f9a: 2901 cmp r1, #1 +10000f9c: d1d2 bne.n 10000f44 +10000f9e: 2403 movs r4, #3 +10000fa0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fa4: 6014 str r4, [r2, #0] +10000fa6: f8dc 2008 ldr.w r2, [ip, #8] +10000faa: 07d2 lsls r2, r2, #31 +10000fac: d5fb bpl.n 10000fa6 +10000fae: f8dc 2000 ldr.w r2, [ip] +10000fb2: 4c0b ldr r4, [pc, #44] @ (10000fe0 ) +10000fb4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fb8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fbc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fc0: 6032 str r2, [r6, #0] +10000fc2: 2201 movs r2, #1 +10000fc4: f8dc 5000 ldr.w r5, [ip] +10000fc8: 404d eors r5, r1 +10000fca: f005 0503 and.w r5, r5, #3 +10000fce: 6035 str r5, [r6, #0] +10000fd0: fa02 f101 lsl.w r1, r2, r1 +10000fd4: f8dc 2008 ldr.w r2, [ip, #8] +10000fd8: 420a tst r2, r1 +10000fda: d0fb beq.n 10000fd4 +10000fdc: e7c6 b.n 10000f6c +10000fde: bf00 nop +10000fe0: 2000045c .word 0x2000045c + +10000fe4 : +10000fe4: 4b01 ldr r3, [pc, #4] @ (10000fec ) +10000fe6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000fea: 4770 bx lr +10000fec: 2000045c .word 0x2000045c + +10000ff0 : +10000ff0: b470 push {r4, r5, r6} +10000ff2: 9d03 ldr r5, [sp, #12] +10000ff4: 6804 ldr r4, [r0, #0] +10000ff6: 032d lsls r5, r5, #12 +10000ff8: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000ffc: 4b1b ldr r3, [pc, #108] @ (1000106c ) +10000ffe: 2c00 cmp r4, #0 +10001000: fbb3 f3f1 udiv r3, r3, r1 +10001004: fbb2 f6f3 udiv r6, r2, r3 +10001008: db1f blt.n 1000104a +1000100a: 4a19 ldr r2, [pc, #100] @ (10001070 ) +1000100c: 4b19 ldr r3, [pc, #100] @ (10001074 ) +1000100e: 4290 cmp r0, r2 +10001010: bf14 ite ne +10001012: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001016: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000101a: 4c17 ldr r4, [pc, #92] @ (10001078 ) +1000101c: 601a str r2, [r3, #0] +1000101e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001022: 601a str r2, [r3, #0] +10001024: 68a3 ldr r3, [r4, #8] +10001026: ea32 0303 bics.w r3, r2, r3 +1000102a: d1fb bne.n 10001024 +1000102c: 2221 movs r2, #33 @ 0x21 +1000102e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001032: 3304 adds r3, #4 +10001034: 6001 str r1, [r0, #0] +10001036: 6086 str r6, [r0, #8] +10001038: 601a str r2, [r3, #0] +1000103a: 6802 ldr r2, [r0, #0] +1000103c: 2a00 cmp r2, #0 +1000103e: dafc bge.n 1000103a +10001040: 2208 movs r2, #8 +10001042: 60c5 str r5, [r0, #12] +10001044: 601a str r2, [r3, #0] +10001046: bc70 pop {r4, r5, r6} +10001048: 4770 bx lr +1000104a: 6803 ldr r3, [r0, #0] +1000104c: f003 033f and.w r3, r3, #63 @ 0x3f +10001050: 428b cmp r3, r1 +10001052: d1da bne.n 1000100a +10001054: 6883 ldr r3, [r0, #8] +10001056: f3c3 030b ubfx r3, r3, #0, #12 +1000105a: 42b3 cmp r3, r6 +1000105c: d1d5 bne.n 1000100a +1000105e: 68c3 ldr r3, [r0, #12] +10001060: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001064: 42ab cmp r3, r5 +10001066: d1d0 bne.n 1000100a +10001068: e7ed b.n 10001046 +1000106a: bf00 nop +1000106c: 00b71b00 .word 0x00b71b00 +10001070: 40058000 .word 0x40058000 +10001074: 40022000 .word 0x40022000 +10001078: 40020000 .word 0x40020000 + +1000107c : +1000107c: 2301 movs r3, #1 +1000107e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001082: 0080 lsls r0, r0, #2 +10001084: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001088: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000108c: 6041 str r1, [r0, #4] +1000108e: 6003 str r3, [r0, #0] +10001090: 4770 bx lr +10001092: bf00 nop + +10001094 : +10001094: 2300 movs r3, #0 +10001096: 8adb ldrh r3, [r3, #22] +10001098: 2200 movs r2, #0 +1000109a: e842 f200 tt r2, r2 +1000109e: 0252 lsls r2, r2, #9 +100010a0: d401 bmi.n 100010a6 +100010a2: 2110 movs r1, #16 +100010a4: 4718 bx r3 +100010a6: 2104 movs r1, #4 +100010a8: 4718 bx r3 +100010aa: bf00 nop + +100010ac : +100010ac: 4a03 ldr r2, [pc, #12] @ (100010bc ) +100010ae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010b2: 2b00 cmp r3, #0 +100010b4: d0fb beq.n 100010ae +100010b6: f3bf 8f5f dmb sy +100010ba: 4770 bx lr +100010bc: 400e0000 .word 0x400e0000 + +100010c0 : +100010c0: 2100 movs r1, #0 +100010c2: 4b04 ldr r3, [pc, #16] @ (100010d4 ) +100010c4: 4a04 ldr r2, [pc, #16] @ (100010d8 ) +100010c6: f3bf 8f5f dmb sy +100010ca: f843 1b04 str.w r1, [r3], #4 +100010ce: 4293 cmp r3, r2 +100010d0: d1f9 bne.n 100010c6 +100010d2: 4770 bx lr +100010d4: 400e080c .word 0x400e080c +100010d8: 400e082c .word 0x400e082c + +100010dc : +100010dc: b410 push {r4} +100010de: f44f 708d mov.w r0, #282 @ 0x11a +100010e2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010e6: 4a06 ldr r2, [pc, #24] @ (10001100 ) +100010e8: 4b06 ldr r3, [pc, #24] @ (10001104 ) +100010ea: 4907 ldr r1, [pc, #28] @ (10001108 ) +100010ec: 6014 str r4, [r2, #0] +100010ee: 60d0 str r0, [r2, #12] +100010f0: 6019 str r1, [r3, #0] +100010f2: 6853 ldr r3, [r2, #4] +100010f4: 2b00 cmp r3, #0 +100010f6: dafc bge.n 100010f2 +100010f8: f85d 4b04 ldr.w r4, [sp], #4 +100010fc: 4770 bx lr +100010fe: bf00 nop +10001100: 40048000 .word 0x40048000 +10001104: 4004a000 .word 0x4004a000 +10001108: 00fab000 .word 0x00fab000 + +1000110c : +1000110c: 4770 bx lr +1000110e: bf00 nop + +10001110 : +10001110: b508 push {r3, lr} +10001112: 4801 ldr r0, [pc, #4] @ (10001118 ) +10001114: f7ff f8b6 bl 10000284 +10001118: 10001a14 .word 0x10001a14 + +1000111c : +1000111c: b538 push {r3, r4, r5, lr} +1000111e: 4c05 ldr r4, [pc, #20] @ (10001134 ) +10001120: 4d05 ldr r5, [pc, #20] @ (10001138 ) +10001122: 42ac cmp r4, r5 +10001124: d204 bcs.n 10001130 +10001126: f854 3b04 ldr.w r3, [r4], #4 +1000112a: 4798 blx r3 +1000112c: 42ac cmp r4, r5 +1000112e: d3fa bcc.n 10001126 +10001130: bd38 pop {r3, r4, r5, pc} +10001132: bf00 nop +10001134: 10001988 .word 0x10001988 +10001138: 100019c8 .word 0x100019c8 + +1000113c : +1000113c: b410 push {r4} +1000113e: 4807 ldr r0, [pc, #28] @ (1000115c ) +10001140: 4c07 ldr r4, [pc, #28] @ (10001160 ) +10001142: 4b08 ldr r3, [pc, #32] @ (10001164 ) +10001144: 4a08 ldr r2, [pc, #32] @ (10001168 ) +10001146: 4909 ldr r1, [pc, #36] @ (1000116c ) +10001148: 6004 str r4, [r0, #0] +1000114a: 601a str r2, [r3, #0] +1000114c: 688b ldr r3, [r1, #8] +1000114e: ea32 0303 bics.w r3, r2, r3 +10001152: d1fb bne.n 1000114c +10001154: f85d 4b04 ldr.w r4, [sp], #4 +10001158: 4770 bx lr +1000115a: bf00 nop +1000115c: 40022000 .word 0x40022000 +10001160: efef3b7f .word 0xefef3b7f +10001164: 40023000 .word 0x40023000 +10001168: 03f3fff6 .word 0x03f3fff6 +1000116c: 40020000 .word 0x40020000 + +10001170 : +10001170: 4b04 ldr r3, [pc, #16] @ (10001184 ) +10001172: 6cdb ldr r3, [r3, #76] @ 0x4c +10001174: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001178: d103 bne.n 10001182 +1000117a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000117e: 4b02 ldr r3, [pc, #8] @ (10001188 ) +10001180: 64da str r2, [r3, #76] @ 0x4c +10001182: 4770 bx lr +10001184: 50110000 .word 0x50110000 +10001188: 50112000 .word 0x50112000 + +1000118c : +1000118c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001190: 4b04 ldr r3, [pc, #16] @ (100011a4 ) +10001192: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001196: 430b orrs r3, r1 +10001198: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000119c: ee10 0430 dcp_rcmp r0 +100011a0: 4770 bx lr +100011a2: bf00 nop +100011a4: 00300303 .word 0x00300303 + +100011a8 : +100011a8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011ac: 4b04 ldr r3, [pc, #16] @ (100011c0 ) +100011ae: 4a05 ldr r2, [pc, #20] @ (100011c4 ) +100011b0: 6019 str r1, [r3, #0] +100011b2: 6893 ldr r3, [r2, #8] +100011b4: 43db mvns r3, r3 +100011b6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011ba: d1fa bne.n 100011b2 +100011bc: 4770 bx lr +100011be: bf00 nop +100011c0: 40023000 .word 0x40023000 +100011c4: 40020000 .word 0x40020000 + +100011c8 : +100011c8: b510 push {r4, lr} +100011ca: f245 2053 movw r0, #21075 @ 0x5253 +100011ce: f7ff ff61 bl 10001094 +100011d2: e8bd 4010 ldmia.w sp!, {r4, lr} +100011d6: 4603 mov r3, r0 +100011d8: 2004 movs r0, #4 +100011da: 4718 bx r3 + +100011dc : +100011dc: b510 push {r4, lr} +100011de: f245 2053 movw r0, #21075 @ 0x5253 +100011e2: f7ff ff57 bl 10001094 +100011e6: e8bd 4010 ldmia.w sp!, {r4, lr} +100011ea: 4603 mov r3, r0 +100011ec: 2001 movs r0, #1 +100011ee: 4718 bx r3 + +100011f0 : +100011f0: f7ff b8a0 b.w 10000334 + +100011f4 : +100011f4: 4914 ldr r1, [pc, #80] @ (10001248 ) +100011f6: 4b15 ldr r3, [pc, #84] @ (1000124c ) +100011f8: b570 push {r4, r5, r6, lr} +100011fa: 1a5c subs r4, r3, r1 +100011fc: 10a6 asrs r6, r4, #2 +100011fe: 2e44 cmp r6, #68 @ 0x44 +10001200: 4632 mov r2, r6 +10001202: bf28 it cs +10001204: 2244 movcs r2, #68 @ 0x44 +10001206: 4d12 ldr r5, [pc, #72] @ (10001250 ) +10001208: 0092 lsls r2, r2, #2 +1000120a: 4628 mov r0, r5 +1000120c: f000 fb0e bl 1000182c +10001210: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001214: d813 bhi.n 1000123e +10001216: 4a0f ldr r2, [pc, #60] @ (10001254 ) +10001218: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000121c: d012 beq.n 10001244 +1000121e: 192b adds r3, r5, r4 +10001220: 0841 lsrs r1, r0, #1 +10001222: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001226: e9c3 2200 strd r2, r2, [r3] +1000122a: 3308 adds r3, #8 +1000122c: 428b cmp r3, r1 +1000122e: d1fa bne.n 10001226 +10001230: 07c3 lsls r3, r0, #31 +10001232: d504 bpl.n 1000123e +10001234: f020 0001 bic.w r0, r0, #1 +10001238: 4430 add r0, r6 +1000123a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000123e: 4b06 ldr r3, [pc, #24] @ (10001258 ) +10001240: 609d str r5, [r3, #8] +10001242: bd70 pop {r4, r5, r6, pc} +10001244: 2043 movs r0, #67 @ 0x43 +10001246: e7f8 b.n 1000123a +10001248: 10000000 .word 0x10000000 +1000124c: 10000110 .word 0x10000110 +10001250: 20000000 .word 0x20000000 +10001254: 10000111 .word 0x10000111 +10001258: e000ed00 .word 0xe000ed00 + +1000125c : +1000125c: 2300 movs r3, #0 +1000125e: b570 push {r4, r5, r6, lr} +10001260: 4c2b ldr r4, [pc, #172] @ (10001310 ) +10001262: b082 sub sp, #8 +10001264: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001268: f7ff ff38 bl 100010dc +1000126c: 2201 movs r2, #1 +1000126e: 4b29 ldr r3, [pc, #164] @ (10001314 ) +10001270: 63da str r2, [r3, #60] @ 0x3c +10001272: 6c63 ldr r3, [r4, #68] @ 0x44 +10001274: 2b01 cmp r3, #1 +10001276: d1fc bne.n 10001272 +10001278: 2103 movs r1, #3 +1000127a: 4a26 ldr r2, [pc, #152] @ (10001314 ) +1000127c: 4b24 ldr r3, [pc, #144] @ (10001310 ) +1000127e: 6311 str r1, [r2, #48] @ 0x30 +10001280: 6b9c ldr r4, [r3, #56] @ 0x38 +10001282: 2c01 cmp r4, #1 +10001284: d1fc bne.n 10001280 +10001286: 2602 movs r6, #2 +10001288: 2505 movs r5, #5 +1000128a: 4621 mov r1, r4 +1000128c: 2305 movs r3, #5 +1000128e: 4a22 ldr r2, [pc, #136] @ (10001318 ) +10001290: 4822 ldr r0, [pc, #136] @ (1000131c ) +10001292: 9600 str r6, [sp, #0] +10001294: f7ff feac bl 10000ff0 +10001298: 4621 mov r1, r4 +1000129a: 462b mov r3, r5 +1000129c: 4a20 ldr r2, [pc, #128] @ (10001320 ) +1000129e: 4821 ldr r0, [pc, #132] @ (10001324 ) +100012a0: 9500 str r5, [sp, #0] +100012a2: f7ff fea5 bl 10000ff0 +100012a6: 2200 movs r2, #0 +100012a8: 2004 movs r0, #4 +100012aa: 4631 mov r1, r6 +100012ac: 4b1e ldr r3, [pc, #120] @ (10001328 ) +100012ae: f7ff fe31 bl 10000f14 +100012b2: 4621 mov r1, r4 +100012b4: 4628 mov r0, r5 +100012b6: 2200 movs r2, #0 +100012b8: 4b1c ldr r3, [pc, #112] @ (1000132c ) +100012ba: f7ff fe2b bl 10000f14 +100012be: 2200 movs r2, #0 +100012c0: 2008 movs r0, #8 +100012c2: 4611 mov r1, r2 +100012c4: 4b1a ldr r3, [pc, #104] @ (10001330 ) +100012c6: f7ff fe25 bl 10000f14 +100012ca: 2200 movs r2, #0 +100012cc: 2009 movs r0, #9 +100012ce: 4611 mov r1, r2 +100012d0: 4b17 ldr r3, [pc, #92] @ (10001330 ) +100012d2: f7ff fe1f bl 10000f14 +100012d6: 2200 movs r2, #0 +100012d8: 2006 movs r0, #6 +100012da: 4611 mov r1, r2 +100012dc: 4b13 ldr r3, [pc, #76] @ (1000132c ) +100012de: f7ff fe19 bl 10000f14 +100012e2: 2200 movs r2, #0 +100012e4: 4b11 ldr r3, [pc, #68] @ (1000132c ) +100012e6: 2007 movs r0, #7 +100012e8: 4611 mov r1, r2 +100012ea: f7ff fe13 bl 10000f14 +100012ee: 2004 movs r0, #4 +100012f0: f7ff fe78 bl 10000fe4 +100012f4: 2400 movs r4, #0 +100012f6: 4b0f ldr r3, [pc, #60] @ (10001334 ) +100012f8: fba3 3500 umull r3, r5, r3, r0 +100012fc: 0cad lsrs r5, r5, #18 +100012fe: b2e0 uxtb r0, r4 +10001300: 4629 mov r1, r5 +10001302: 3401 adds r4, #1 +10001304: f7ff feba bl 1000107c +10001308: 2c06 cmp r4, #6 +1000130a: d1f8 bne.n 100012fe +1000130c: b002 add sp, #8 +1000130e: bd70 pop {r4, r5, r6, pc} +10001310: 40010000 .word 0x40010000 +10001314: 40013000 .word 0x40013000 +10001318: 59682f00 .word 0x59682f00 +1000131c: 40050000 .word 0x40050000 +10001320: 47868c00 .word 0x47868c00 +10001324: 40058000 .word 0x40058000 +10001328: 00b71b00 .word 0x00b71b00 +1000132c: 08f0d180 .word 0x08f0d180 +10001330: 02dc6c00 .word 0x02dc6c00 +10001334: 431bde83 .word 0x431bde83 + +10001338 <_out_char>: +10001338: b900 cbnz r0, 1000133c <_out_char+0x4> +1000133a: 4770 bx lr +1000133c: f000 b91c b.w 10001578 <__wrap_putchar> + +10001340 : +10001340: b510 push {r4, lr} +10001342: 4b09 ldr r3, [pc, #36] @ (10001368 ) +10001344: b084 sub sp, #16 +10001346: 681c ldr r4, [r3, #0] +10001348: b14c cbz r4, 1000135e +1000134a: 4603 mov r3, r0 +1000134c: 9100 str r1, [sp, #0] +1000134e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001352: a903 add r1, sp, #12 +10001354: 4805 ldr r0, [pc, #20] @ (1000136c ) +10001356: 47a0 blx r4 +10001358: 2001 movs r0, #1 +1000135a: b004 add sp, #16 +1000135c: bd10 pop {r4, pc} +1000135e: f000 f94d bl 100015fc <__wrap_puts> +10001362: 4620 mov r0, r4 +10001364: b004 add sp, #16 +10001366: bd10 pop {r4, pc} +10001368: 2000048c .word 0x2000048c +1000136c: 10001339 .word 0x10001339 + +10001370 <_exit>: +10001370: be00 bkpt 0x0000 +10001372: e7fd b.n 10001370 <_exit> + +10001374 : +10001374: b508 push {r3, lr} +10001376: f7ff fffb bl 10001370 <_exit> +1000137a: bf00 nop + +1000137c : +1000137c: b538 push {r3, r4, r5, lr} +1000137e: 4c06 ldr r4, [pc, #24] @ (10001398 ) +10001380: 4d06 ldr r5, [pc, #24] @ (1000139c ) +10001382: f7ff fecb bl 1000111c +10001386: 42ac cmp r4, r5 +10001388: d204 bcs.n 10001394 +1000138a: f854 3b04 ldr.w r3, [r4], #4 +1000138e: 4798 blx r3 +10001390: 42ac cmp r4, r5 +10001392: d3fa bcc.n 1000138a +10001394: bd38 pop {r3, r4, r5, pc} +10001396: bf00 nop +10001398: 100019c8 .word 0x100019c8 +1000139c: 100019cc .word 0x100019cc + +100013a0 : +100013a0: 6803 ldr r3, [r0, #0] +100013a2: 4608 mov r0, r1 +100013a4: 4611 mov r1, r2 +100013a6: 4718 bx r3 + +100013a8 : +100013a8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100013ac: 4615 mov r5, r2 +100013ae: 7d42 ldrb r2, [r0, #21] +100013b0: 4607 mov r7, r0 +100013b2: 4688 mov r8, r1 +100013b4: 2a00 cmp r2, #0 +100013b6: d046 beq.n 10001446 +100013b8: 2d00 cmp r5, #0 +100013ba: dd1d ble.n 100013f8 +100013bc: 780b ldrb r3, [r1, #0] +100013be: 2b0a cmp r3, #10 +100013c0: d023 beq.n 1000140a +100013c2: 2d01 cmp r5, #1 +100013c4: f04f 0c00 mov.w ip, #0 +100013c8: d018 beq.n 100013fc +100013ca: 4646 mov r6, r8 +100013cc: 2401 movs r4, #1 +100013ce: f816 2f01 ldrb.w r2, [r6, #1]! +100013d2: 4621 mov r1, r4 +100013d4: 2a0a cmp r2, #10 +100013d6: f104 0401 add.w r4, r4, #1 +100013da: d022 beq.n 10001422 +100013dc: 42a5 cmp r5, r4 +100013de: d1f6 bne.n 100013ce +100013e0: 4565 cmp r5, ip +100013e2: dc0b bgt.n 100013fc +100013e4: eb08 0305 add.w r3, r8, r5 +100013e8: f813 3c01 ldrb.w r3, [r3, #-1] +100013ec: f1a3 030d sub.w r3, r3, #13 +100013f0: fab3 f383 clz r3, r3 +100013f4: 095b lsrs r3, r3, #5 +100013f6: 753b strb r3, [r7, #20] +100013f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100013fc: 683b ldr r3, [r7, #0] +100013fe: eba5 010c sub.w r1, r5, ip +10001402: eb08 000c add.w r0, r8, ip +10001406: 4798 blx r3 +10001408: e7ec b.n 100013e4 +1000140a: 7d03 ldrb r3, [r0, #20] +1000140c: 2b00 cmp r3, #0 +1000140e: d1d8 bne.n 100013c2 +10001410: 6803 ldr r3, [r0, #0] +10001412: 2102 movs r1, #2 +10001414: 480f ldr r0, [pc, #60] @ (10001454 ) +10001416: 4798 blx r3 +10001418: 2d01 cmp r5, #1 +1000141a: d0e3 beq.n 100013e4 +1000141c: f04f 0c01 mov.w ip, #1 +10001420: e7d3 b.n 100013ca +10001422: f816 3c01 ldrb.w r3, [r6, #-1] +10001426: 2b0d cmp r3, #13 +10001428: d0d8 beq.n 100013dc +1000142a: 458c cmp ip, r1 +1000142c: eb08 000c add.w r0, r8, ip +10001430: eba1 010c sub.w r1, r1, ip +10001434: da01 bge.n 1000143a +10001436: 683b ldr r3, [r7, #0] +10001438: 4798 blx r3 +1000143a: 2102 movs r1, #2 +1000143c: 4805 ldr r0, [pc, #20] @ (10001454 ) +1000143e: 683b ldr r3, [r7, #0] +10001440: 4798 blx r3 +10001442: 46a4 mov ip, r4 +10001444: e7ca b.n 100013dc +10001446: 4629 mov r1, r5 +10001448: 4640 mov r0, r8 +1000144a: 683b ldr r3, [r7, #0] +1000144c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001450: 4718 bx r3 +10001452: bf00 nop +10001454: 10001af8 .word 0x10001af8 + +10001458 : +10001458: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +1000145c: b082 sub sp, #8 +1000145e: 460d mov r5, r1 +10001460: 4691 mov r9, r2 +10001462: 461c mov r4, r3 +10001464: 4606 mov r6, r0 +10001466: f7ff fc9b bl 10000da0 +1000146a: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +1000146e: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001472: 4a2e ldr r2, [pc, #184] @ (1000152c ) +10001474: 1882 adds r2, r0, r2 +10001476: f141 0300 adc.w r3, r1, #0 +1000147a: 4594 cmp ip, r2 +1000147c: eb77 0103 sbcs.w r1, r7, r3 +10001480: bf3c itt cc +10001482: 4662 movcc r2, ip +10001484: 463b movcc r3, r7 +10001486: 482a ldr r0, [pc, #168] @ (10001530 ) +10001488: f000 fa7a bl 10001980 <__mutex_try_enter_block_until_veneer> +1000148c: 1c6b adds r3, r5, #1 +1000148e: 4680 mov r8, r0 +10001490: d040 beq.n 10001514 +10001492: b30c cbz r4, 100014d8 +10001494: 4f27 ldr r7, [pc, #156] @ (10001534 ) +10001496: 4b28 ldr r3, [pc, #160] @ (10001538 ) +10001498: 681c ldr r4, [r3, #0] +1000149a: b1b4 cbz r4, 100014ca +1000149c: f1b9 0f00 cmp.w r9, #0 +100014a0: d11c bne.n 100014dc +100014a2: f8df 909c ldr.w r9, [pc, #156] @ 10001540 +100014a6: e001 b.n 100014ac +100014a8: 6924 ldr r4, [r4, #16] +100014aa: b174 cbz r4, 100014ca +100014ac: 6823 ldr r3, [r4, #0] +100014ae: 2b00 cmp r3, #0 +100014b0: d0fa beq.n 100014a8 +100014b2: f8d9 3000 ldr.w r3, [r9] +100014b6: b10b cbz r3, 100014bc +100014b8: 429c cmp r4, r3 +100014ba: d1f5 bne.n 100014a8 +100014bc: 4620 mov r0, r4 +100014be: 462a mov r2, r5 +100014c0: 4631 mov r1, r6 +100014c2: 47b8 blx r7 +100014c4: 6924 ldr r4, [r4, #16] +100014c6: 2c00 cmp r4, #0 +100014c8: d1f0 bne.n 100014ac +100014ca: f1b8 0f00 cmp.w r8, #0 +100014ce: d126 bne.n 1000151e +100014d0: 4628 mov r0, r5 +100014d2: b002 add sp, #8 +100014d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100014d8: 4f18 ldr r7, [pc, #96] @ (1000153c ) +100014da: e7dc b.n 10001496 +100014dc: f04f 0a0a mov.w sl, #10 +100014e0: f8df 905c ldr.w r9, [pc, #92] @ 10001540 +100014e4: e002 b.n 100014ec +100014e6: 6924 ldr r4, [r4, #16] +100014e8: 2c00 cmp r4, #0 +100014ea: d0ee beq.n 100014ca +100014ec: 6823 ldr r3, [r4, #0] +100014ee: 2b00 cmp r3, #0 +100014f0: d0f9 beq.n 100014e6 +100014f2: f8d9 3000 ldr.w r3, [r9] +100014f6: b10b cbz r3, 100014fc +100014f8: 42a3 cmp r3, r4 +100014fa: d1f4 bne.n 100014e6 +100014fc: 462a mov r2, r5 +100014fe: 4631 mov r1, r6 +10001500: 4620 mov r0, r4 +10001502: 47b8 blx r7 +10001504: 2201 movs r2, #1 +10001506: 4620 mov r0, r4 +10001508: f10d 0107 add.w r1, sp, #7 +1000150c: f88d a007 strb.w sl, [sp, #7] +10001510: 47b8 blx r7 +10001512: e7e8 b.n 100014e6 +10001514: 4630 mov r0, r6 +10001516: f000 f9ff bl 10001918 +1000151a: 4605 mov r5, r0 +1000151c: e7b9 b.n 10001492 +1000151e: 4804 ldr r0, [pc, #16] @ (10001530 ) +10001520: f000 fa2a bl 10001978 <__mutex_exit_veneer> +10001524: 4628 mov r0, r5 +10001526: b002 add sp, #8 +10001528: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000152c: 000f4240 .word 0x000f4240 +10001530: 200002a4 .word 0x200002a4 +10001534: 100013a9 .word 0x100013a9 +10001538: 20000484 .word 0x20000484 +1000153c: 100013a1 .word 0x100013a1 +10001540: 20000488 .word 0x20000488 + +10001544 : +10001544: 4a08 ldr r2, [pc, #32] @ (10001568 ) +10001546: 6813 ldr r3, [r2, #0] +10001548: b923 cbnz r3, 10001554 +1000154a: e00a b.n 10001562 +1000154c: f103 0210 add.w r2, r3, #16 +10001550: 691b ldr r3, [r3, #16] +10001552: b133 cbz r3, 10001562 +10001554: 4283 cmp r3, r0 +10001556: d1f9 bne.n 1000154c +10001558: b929 cbnz r1, 10001566 +1000155a: 6918 ldr r0, [r3, #16] +1000155c: 6010 str r0, [r2, #0] +1000155e: 6119 str r1, [r3, #16] +10001560: 4770 bx lr +10001562: b101 cbz r1, 10001566 +10001564: 6010 str r0, [r2, #0] +10001566: 4770 bx lr +10001568: 20000484 .word 0x20000484 + +1000156c : +1000156c: b508 push {r3, lr} +1000156e: f000 f933 bl 100017d8 +10001572: 2001 movs r0, #1 +10001574: bd08 pop {r3, pc} +10001576: bf00 nop + +10001578 <__wrap_putchar>: +10001578: b5f0 push {r4, r5, r6, r7, lr} +1000157a: b083 sub sp, #12 +1000157c: 4606 mov r6, r0 +1000157e: f88d 0007 strb.w r0, [sp, #7] +10001582: f7ff fc0d bl 10000da0 +10001586: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000158a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000158e: 4a17 ldr r2, [pc, #92] @ (100015ec <__wrap_putchar+0x74>) +10001590: 1882 adds r2, r0, r2 +10001592: f141 0300 adc.w r3, r1, #0 +10001596: 4295 cmp r5, r2 +10001598: eb74 0103 sbcs.w r1, r4, r3 +1000159c: bf3c itt cc +1000159e: 4623 movcc r3, r4 +100015a0: 462a movcc r2, r5 +100015a2: 4813 ldr r0, [pc, #76] @ (100015f0 <__wrap_putchar+0x78>) +100015a4: f000 f9ec bl 10001980 <__mutex_try_enter_block_until_veneer> +100015a8: 4b12 ldr r3, [pc, #72] @ (100015f4 <__wrap_putchar+0x7c>) +100015aa: 4607 mov r7, r0 +100015ac: 681c ldr r4, [r3, #0] +100015ae: b19c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b0: 4d11 ldr r5, [pc, #68] @ (100015f8 <__wrap_putchar+0x80>) +100015b2: e001 b.n 100015b8 <__wrap_putchar+0x40> +100015b4: 6924 ldr r4, [r4, #16] +100015b6: b17c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b8: 6823 ldr r3, [r4, #0] +100015ba: 2b00 cmp r3, #0 +100015bc: d0fa beq.n 100015b4 <__wrap_putchar+0x3c> +100015be: 682b ldr r3, [r5, #0] +100015c0: b10b cbz r3, 100015c6 <__wrap_putchar+0x4e> +100015c2: 429c cmp r4, r3 +100015c4: d1f6 bne.n 100015b4 <__wrap_putchar+0x3c> +100015c6: 4620 mov r0, r4 +100015c8: 2201 movs r2, #1 +100015ca: f10d 0107 add.w r1, sp, #7 +100015ce: f7ff feeb bl 100013a8 +100015d2: 6924 ldr r4, [r4, #16] +100015d4: 2c00 cmp r4, #0 +100015d6: d1ef bne.n 100015b8 <__wrap_putchar+0x40> +100015d8: b917 cbnz r7, 100015e0 <__wrap_putchar+0x68> +100015da: 4630 mov r0, r6 +100015dc: b003 add sp, #12 +100015de: bdf0 pop {r4, r5, r6, r7, pc} +100015e0: 4803 ldr r0, [pc, #12] @ (100015f0 <__wrap_putchar+0x78>) +100015e2: f000 f9c9 bl 10001978 <__mutex_exit_veneer> +100015e6: 4630 mov r0, r6 +100015e8: b003 add sp, #12 +100015ea: bdf0 pop {r4, r5, r6, r7, pc} +100015ec: 000f4240 .word 0x000f4240 +100015f0: 200002a4 .word 0x200002a4 +100015f4: 20000484 .word 0x20000484 +100015f8: 20000488 .word 0x20000488 + +100015fc <__wrap_puts>: +100015fc: b538 push {r3, r4, r5, lr} +100015fe: 4604 mov r4, r0 +10001600: f000 f98a bl 10001918 +10001604: 2301 movs r3, #1 +10001606: 4605 mov r5, r0 +10001608: 461a mov r2, r3 +1000160a: 4620 mov r0, r4 +1000160c: 4629 mov r1, r5 +1000160e: f7ff ff23 bl 10001458 +10001612: 4b08 ldr r3, [pc, #32] @ (10001634 <__wrap_puts+0x38>) +10001614: 681c ldr r4, [r3, #0] +10001616: b12c cbz r4, 10001624 <__wrap_puts+0x28> +10001618: 6863 ldr r3, [r4, #4] +1000161a: b12b cbz r3, 10001628 <__wrap_puts+0x2c> +1000161c: 4798 blx r3 +1000161e: 6924 ldr r4, [r4, #16] +10001620: 2c00 cmp r4, #0 +10001622: d1f9 bne.n 10001618 <__wrap_puts+0x1c> +10001624: 4628 mov r0, r5 +10001626: bd38 pop {r3, r4, r5, pc} +10001628: 6924 ldr r4, [r4, #16] +1000162a: 2c00 cmp r4, #0 +1000162c: d1f4 bne.n 10001618 <__wrap_puts+0x1c> +1000162e: 4628 mov r0, r5 +10001630: bd38 pop {r3, r4, r5, pc} +10001632: bf00 nop +10001634: 20000484 .word 0x20000484 + +10001638 : +10001638: f1b1 0c00 subs.w ip, r1, #0 +1000163c: dd1d ble.n 1000167a +1000163e: 4a0f ldr r2, [pc, #60] @ (1000167c ) +10001640: 4b0f ldr r3, [pc, #60] @ (10001680 ) +10001642: 6812 ldr r2, [r2, #0] +10001644: b530 push {r4, r5, lr} +10001646: 1ad3 subs r3, r2, r3 +10001648: fab3 f383 clz r3, r3 +1000164c: 240d movs r4, #13 +1000164e: 4d0d ldr r5, [pc, #52] @ (10001684 ) +10001650: 095b lsrs r3, r3, #5 +10001652: 1e41 subs r1, r0, #1 +10001654: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10001658: 448c add ip, r1 +1000165a: f811 0f01 ldrb.w r0, [r1, #1]! +1000165e: 4586 cmp lr, r0 +10001660: d006 beq.n 10001670 +10001662: 6993 ldr r3, [r2, #24] +10001664: 069b lsls r3, r3, #26 +10001666: d4fc bmi.n 10001662 +10001668: 4561 cmp r1, ip +1000166a: 6010 str r0, [r2, #0] +1000166c: d1f5 bne.n 1000165a +1000166e: bd30 pop {r4, r5, pc} +10001670: 6993 ldr r3, [r2, #24] +10001672: 069d lsls r5, r3, #26 +10001674: d4fc bmi.n 10001670 +10001676: 6014 str r4, [r2, #0] +10001678: e7f3 b.n 10001662 +1000167a: 4770 bx lr +1000167c: 200004d0 .word 0x200004d0 +10001680: 40078000 .word 0x40078000 +10001684: 200004cc .word 0x200004cc + +10001688 : +10001688: 4b22 ldr r3, [pc, #136] @ (10001714 ) +1000168a: f1b1 0c00 subs.w ip, r1, #0 +1000168e: b410 push {r4} +10001690: 681c ldr r4, [r3, #0] +10001692: dd2e ble.n 100016f2 +10001694: 4603 mov r3, r0 +10001696: 2000 movs r0, #0 +10001698: 4a1f ldr r2, [pc, #124] @ (10001718 ) +1000169a: 1e59 subs r1, r3, #1 +1000169c: 6812 ldr r2, [r2, #0] +1000169e: 6993 ldr r3, [r2, #24] +100016a0: 06db lsls r3, r3, #27 +100016a2: d417 bmi.n 100016d4 +100016a4: 3001 adds r0, #1 +100016a6: 6993 ldr r3, [r2, #24] +100016a8: 06db lsls r3, r3, #27 +100016aa: d4fc bmi.n 100016a6 +100016ac: 6813 ldr r3, [r2, #0] +100016ae: 4584 cmp ip, r0 +100016b0: f801 3f01 strb.w r3, [r1, #1]! +100016b4: d1f3 bne.n 1000169e +100016b6: b14c cbz r4, 100016cc +100016b8: 2150 movs r1, #80 @ 0x50 +100016ba: 4613 mov r3, r2 +100016bc: 6391 str r1, [r2, #56] @ 0x38 +100016be: f853 2f34 ldr.w r2, [r3, #52]! +100016c2: f002 0238 and.w r2, r2, #56 @ 0x38 +100016c6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016ca: 601a str r2, [r3, #0] +100016cc: 4660 mov r0, ip +100016ce: f85d 4b04 ldr.w r4, [sp], #4 +100016d2: 4770 bx lr +100016d4: b14c cbz r4, 100016ea +100016d6: 2150 movs r1, #80 @ 0x50 +100016d8: 4613 mov r3, r2 +100016da: 6391 str r1, [r2, #56] @ 0x38 +100016dc: f853 2f34 ldr.w r2, [r3, #52]! +100016e0: f002 0238 and.w r2, r2, #56 @ 0x38 +100016e4: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016e8: 601a str r2, [r3, #0] +100016ea: b178 cbz r0, 1000170c +100016ec: f85d 4b04 ldr.w r4, [sp], #4 +100016f0: 4770 bx lr +100016f2: b15c cbz r4, 1000170c +100016f4: 4b08 ldr r3, [pc, #32] @ (10001718 ) +100016f6: 2150 movs r1, #80 @ 0x50 +100016f8: 681a ldr r2, [r3, #0] +100016fa: 4613 mov r3, r2 +100016fc: 6391 str r1, [r2, #56] @ 0x38 +100016fe: f853 2f34 ldr.w r2, [r3, #52]! +10001702: f002 0238 and.w r2, r2, #56 @ 0x38 +10001706: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000170a: 601a str r2, [r3, #0] +1000170c: f06f 0002 mvn.w r0, #2 +10001710: e7dd b.n 100016ce +10001712: bf00 nop +10001714: 20000450 .word 0x20000450 +10001718: 200004d0 .word 0x200004d0 + +1000171c : +1000171c: 4b05 ldr r3, [pc, #20] @ (10001734 ) +1000171e: 681b ldr r3, [r3, #0] +10001720: b133 cbz r3, 10001730 +10001722: 2100 movs r1, #0 +10001724: 4a04 ldr r2, [pc, #16] @ (10001738 ) +10001726: 4805 ldr r0, [pc, #20] @ (1000173c ) +10001728: 6812 ldr r2, [r2, #0] +1000172a: 6800 ldr r0, [r0, #0] +1000172c: 6391 str r1, [r2, #56] @ 0x38 +1000172e: 4718 bx r3 +10001730: 4770 bx lr +10001732: bf00 nop +10001734: 20000450 .word 0x20000450 +10001738: 200004d0 .word 0x200004d0 +1000173c: 20000454 .word 0x20000454 + +10001740 : +10001740: 4b02 ldr r3, [pc, #8] @ (1000174c ) +10001742: 681a ldr r2, [r3, #0] +10001744: 6993 ldr r3, [r2, #24] +10001746: 071b lsls r3, r3, #28 +10001748: d4fc bmi.n 10001744 +1000174a: 4770 bx lr +1000174c: 200004d0 .word 0x200004d0 + +10001750 : +10001750: b5f8 push {r3, r4, r5, r6, r7, lr} +10001752: 4f1c ldr r7, [pc, #112] @ (100017c4 ) +10001754: 4d1c ldr r5, [pc, #112] @ (100017c8 ) +10001756: 683a ldr r2, [r7, #0] +10001758: 4e1c ldr r6, [pc, #112] @ (100017cc ) +1000175a: 42aa cmp r2, r5 +1000175c: bf14 ite ne +1000175e: 2521 movne r5, #33 @ 0x21 +10001760: 2522 moveq r5, #34 @ 0x22 +10001762: 4604 mov r4, r0 +10001764: f8d6 c000 ldr.w ip, [r6] +10001768: b118 cbz r0, 10001772 +1000176a: f1bc 0f00 cmp.w ip, #0 +1000176e: d010 beq.n 10001792 +10001770: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001772: f1bc 0f00 cmp.w ip, #0 +10001776: d0fb beq.n 10001770 +10001778: 4601 mov r1, r0 +1000177a: 6390 str r0, [r2, #56] @ 0x38 +1000177c: 4628 mov r0, r5 +1000177e: f7fe fe05 bl 1000038c +10001782: 4628 mov r0, r5 +10001784: 4912 ldr r1, [pc, #72] @ (100017d0 ) +10001786: f7fe fe47 bl 10000418 +1000178a: 4b12 ldr r3, [pc, #72] @ (100017d4 ) +1000178c: 6034 str r4, [r6, #0] +1000178e: 601c str r4, [r3, #0] +10001790: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001792: 460b mov r3, r1 +10001794: 4a0f ldr r2, [pc, #60] @ (100017d4 ) +10001796: 490e ldr r1, [pc, #56] @ (100017d0 ) +10001798: 6030 str r0, [r6, #0] +1000179a: 4628 mov r0, r5 +1000179c: 6013 str r3, [r2, #0] +1000179e: f7fe fe0b bl 100003b8 +100017a2: 2101 movs r1, #1 +100017a4: 4628 mov r0, r5 +100017a6: f7fe fdf1 bl 1000038c +100017aa: 683a ldr r2, [r7, #0] +100017ac: 2150 movs r1, #80 @ 0x50 +100017ae: 4613 mov r3, r2 +100017b0: 6391 str r1, [r2, #56] @ 0x38 +100017b2: f853 2f34 ldr.w r2, [r3, #52]! +100017b6: f002 0238 and.w r2, r2, #56 @ 0x38 +100017ba: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100017be: 601a str r2, [r3, #0] +100017c0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100017c2: bf00 nop +100017c4: 200004d0 .word 0x200004d0 +100017c8: 40078000 .word 0x40078000 +100017cc: 20000450 .word 0x20000450 +100017d0: 1000171d .word 0x1000171d +100017d4: 20000454 .word 0x20000454 + +100017d8 : +100017d8: b510 push {r4, lr} +100017da: 490e ldr r1, [pc, #56] @ (10001814 ) +100017dc: 4c0e ldr r4, [pc, #56] @ (10001818 ) +100017de: 480f ldr r0, [pc, #60] @ (1000181c ) +100017e0: 4a0f ldr r2, [pc, #60] @ (10001820 ) +100017e2: 4b10 ldr r3, [pc, #64] @ (10001824 ) +100017e4: 7800 ldrb r0, [r0, #0] +100017e6: 6021 str r1, [r4, #0] +100017e8: 2000 movs r0, #0 +100017ea: 2102 movs r1, #2 +100017ec: 7812 ldrb r2, [r2, #0] +100017ee: 781b ldrb r3, [r3, #0] +100017f0: f7fe fd2a bl 10000248 +100017f4: 2102 movs r1, #2 +100017f6: 2001 movs r0, #1 +100017f8: f7fe fd26 bl 10000248 +100017fc: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10001800: 6820 ldr r0, [r4, #0] +10001802: f7ff fb05 bl 10000e10 +10001806: e8bd 4010 ldmia.w sp!, {r4, lr} +1000180a: 2101 movs r1, #1 +1000180c: 4806 ldr r0, [pc, #24] @ (10001828 ) +1000180e: f7ff be99 b.w 10001544 +10001812: bf00 nop +10001814: 40070000 .word 0x40070000 +10001818: 200004d0 .word 0x200004d0 +1000181c: 10001b48 .word 0x10001b48 +10001820: 10001b44 .word 0x10001b44 +10001824: 10001b40 .word 0x10001b40 +10001828: 2000028c .word 0x2000028c + +1000182c : +1000182c: 4684 mov ip, r0 +1000182e: ea41 0300 orr.w r3, r1, r0 +10001832: f013 0303 ands.w r3, r3, #3 +10001836: d149 bne.n 100018cc +10001838: 3a40 subs r2, #64 @ 0x40 +1000183a: d323 bcc.n 10001884 +1000183c: 680b ldr r3, [r1, #0] +1000183e: 6003 str r3, [r0, #0] +10001840: 684b ldr r3, [r1, #4] +10001842: 6043 str r3, [r0, #4] +10001844: 688b ldr r3, [r1, #8] +10001846: 6083 str r3, [r0, #8] +10001848: 68cb ldr r3, [r1, #12] +1000184a: 60c3 str r3, [r0, #12] +1000184c: 690b ldr r3, [r1, #16] +1000184e: 6103 str r3, [r0, #16] +10001850: 694b ldr r3, [r1, #20] +10001852: 6143 str r3, [r0, #20] +10001854: 698b ldr r3, [r1, #24] +10001856: 6183 str r3, [r0, #24] +10001858: 69cb ldr r3, [r1, #28] +1000185a: 61c3 str r3, [r0, #28] +1000185c: 6a0b ldr r3, [r1, #32] +1000185e: 6203 str r3, [r0, #32] +10001860: 6a4b ldr r3, [r1, #36] @ 0x24 +10001862: 6243 str r3, [r0, #36] @ 0x24 +10001864: 6a8b ldr r3, [r1, #40] @ 0x28 +10001866: 6283 str r3, [r0, #40] @ 0x28 +10001868: 6acb ldr r3, [r1, #44] @ 0x2c +1000186a: 62c3 str r3, [r0, #44] @ 0x2c +1000186c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000186e: 6303 str r3, [r0, #48] @ 0x30 +10001870: 6b4b ldr r3, [r1, #52] @ 0x34 +10001872: 6343 str r3, [r0, #52] @ 0x34 +10001874: 6b8b ldr r3, [r1, #56] @ 0x38 +10001876: 6383 str r3, [r0, #56] @ 0x38 +10001878: 6bcb ldr r3, [r1, #60] @ 0x3c +1000187a: 63c3 str r3, [r0, #60] @ 0x3c +1000187c: 3040 adds r0, #64 @ 0x40 +1000187e: 3140 adds r1, #64 @ 0x40 +10001880: 3a40 subs r2, #64 @ 0x40 +10001882: d2db bcs.n 1000183c +10001884: 3230 adds r2, #48 @ 0x30 +10001886: d30b bcc.n 100018a0 +10001888: 680b ldr r3, [r1, #0] +1000188a: 6003 str r3, [r0, #0] +1000188c: 684b ldr r3, [r1, #4] +1000188e: 6043 str r3, [r0, #4] +10001890: 688b ldr r3, [r1, #8] +10001892: 6083 str r3, [r0, #8] +10001894: 68cb ldr r3, [r1, #12] +10001896: 60c3 str r3, [r0, #12] +10001898: 3010 adds r0, #16 +1000189a: 3110 adds r1, #16 +1000189c: 3a10 subs r2, #16 +1000189e: d2f3 bcs.n 10001888 +100018a0: 320c adds r2, #12 +100018a2: d305 bcc.n 100018b0 +100018a4: f851 3b04 ldr.w r3, [r1], #4 +100018a8: f840 3b04 str.w r3, [r0], #4 +100018ac: 3a04 subs r2, #4 +100018ae: d2f9 bcs.n 100018a4 +100018b0: 3204 adds r2, #4 +100018b2: d008 beq.n 100018c6 +100018b4: 07d2 lsls r2, r2, #31 +100018b6: bf1c itt ne +100018b8: f811 3b01 ldrbne.w r3, [r1], #1 +100018bc: f800 3b01 strbne.w r3, [r0], #1 +100018c0: d301 bcc.n 100018c6 +100018c2: 880b ldrh r3, [r1, #0] +100018c4: 8003 strh r3, [r0, #0] +100018c6: 4660 mov r0, ip +100018c8: 4770 bx lr +100018ca: bf00 nop +100018cc: 2a08 cmp r2, #8 +100018ce: d313 bcc.n 100018f8 +100018d0: 078b lsls r3, r1, #30 +100018d2: d0b1 beq.n 10001838 +100018d4: f010 0303 ands.w r3, r0, #3 +100018d8: d0ae beq.n 10001838 +100018da: f1c3 0304 rsb r3, r3, #4 +100018de: 1ad2 subs r2, r2, r3 +100018e0: 07db lsls r3, r3, #31 +100018e2: bf1c itt ne +100018e4: f811 3b01 ldrbne.w r3, [r1], #1 +100018e8: f800 3b01 strbne.w r3, [r0], #1 +100018ec: d3a4 bcc.n 10001838 +100018ee: f831 3b02 ldrh.w r3, [r1], #2 +100018f2: f820 3b02 strh.w r3, [r0], #2 +100018f6: e79f b.n 10001838 +100018f8: 3a04 subs r2, #4 +100018fa: d3d9 bcc.n 100018b0 +100018fc: 3a01 subs r2, #1 +100018fe: f811 3b01 ldrb.w r3, [r1], #1 +10001902: f800 3b01 strb.w r3, [r0], #1 +10001906: d2f9 bcs.n 100018fc +10001908: 780b ldrb r3, [r1, #0] +1000190a: 7003 strb r3, [r0, #0] +1000190c: 784b ldrb r3, [r1, #1] +1000190e: 7043 strb r3, [r0, #1] +10001910: 788b ldrb r3, [r1, #2] +10001912: 7083 strb r3, [r0, #2] +10001914: 4660 mov r0, ip +10001916: 4770 bx lr + +10001918 : +10001918: f020 0103 bic.w r1, r0, #3 +1000191c: f010 0003 ands.w r0, r0, #3 +10001920: f1c0 0000 rsb r0, r0, #0 +10001924: f851 3b04 ldr.w r3, [r1], #4 +10001928: f100 0c04 add.w ip, r0, #4 +1000192c: ea4f 0ccc mov.w ip, ip, lsl #3 +10001930: f06f 0200 mvn.w r2, #0 +10001934: bf1c itt ne +10001936: fa22 f20c lsrne.w r2, r2, ip +1000193a: 4313 orrne r3, r2 +1000193c: f04f 0c01 mov.w ip, #1 +10001940: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001944: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001948: eba3 020c sub.w r2, r3, ip +1000194c: ea22 0203 bic.w r2, r2, r3 +10001950: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001954: bf04 itt eq +10001956: f851 3b04 ldreq.w r3, [r1], #4 +1000195a: 3004 addeq r0, #4 +1000195c: d0f4 beq.n 10001948 +1000195e: f1c2 0100 rsb r1, r2, #0 +10001962: ea02 0201 and.w r2, r2, r1 +10001966: fab2 f282 clz r2, r2 +1000196a: f1c2 021f rsb r2, r2, #31 +1000196e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10001972: 4770 bx lr + +10001974 <_fini>: +10001974: b5f8 push {r3, r4, r5, r6, r7, lr} +10001976: bf00 nop + +10001978 <__mutex_exit_veneer>: +10001978: f85f f000 ldr.w pc, [pc] @ 1000197c <__mutex_exit_veneer+0x4> +1000197c: 200001e5 .word 0x200001e5 + +10001980 <__mutex_try_enter_block_until_veneer>: +10001980: f85f f000 ldr.w pc, [pc] @ 10001984 <__mutex_try_enter_block_until_veneer+0x4> +10001984: 2000017d .word 0x2000017d + +10001988 <__pre_init_runtime_init_bootrom_reset>: +10001988: 100011c9 .... + +1000198c <__pre_init_runtime_init_early_resets>: +1000198c: 1000113d =... + +10001990 <__pre_init_runtime_init_usb_power_down>: +10001990: 10001171 q... + +10001994 <__pre_init_runtime_init_clocks>: +10001994: 1000125d ]... + +10001998 <__pre_init_runtime_init_post_clock_resets>: +10001998: 100011a9 .... + +1000199c <__pre_init_runtime_init_boot_locks_reset>: +1000199c: 100010c1 .... + +100019a0 <__pre_init_runtime_init_spin_locks_reset>: +100019a0: 100011f1 .... + +100019a4 <__pre_init_runtime_init_bootrom_locking_enable>: +100019a4: 100010ad .... + +100019a8 <__pre_init_runtime_init_mutex>: +100019a8: 100006d5 .... + +100019ac <__pre_init_runtime_init_install_ram_vector_table>: +100019ac: 100011f5 .... + +100019b0 <__pre_init_runtime_init_default_alarm_pool>: +100019b0: 10000a51 Q... + +100019b4 <__pre_init_first_per_core_initializer>: +100019b4: 1000110d .... + +100019b8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100019b8: 100011dd .... + +100019bc <__pre_init_runtime_init_per_core_enable_coprocessors>: +100019bc: 1000118d .... + +100019c0 <__pre_init_spinlock_set_extexclall>: +100019c0: 10000325 %... + +100019c4 <__pre_init_runtime_init_per_core_irq_priorities>: +100019c4: 1000034d M... + +100019c8 <__frame_dummy_init_array_entry>: +100019c8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__best_effort_wfe_or_timeout_veneer>: +20000220: f85f f000 ldr.w pc, [pc] @ 20000224 <__best_effort_wfe_or_timeout_veneer+0x4> +20000224: 10000c99 .word 0x10000c99 + +20000228 : +20000228: 00000010 .... + +2000022c : +2000022c: 00000000 .word 0x00000000 +20000230: 00010000 .word 0x00010000 + ... +2000023c: 00020000 .word 0x00020000 + ... +20000248: 00030000 .word 0x00030000 + ... +20000254: 00ff0000 .word 0x00ff0000 +20000258: 00000000 .word 0x00000000 + +2000025c : +2000025c: b501 push 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b/WEEK02/0x0001_hello-world/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK02/0x0001_hello-world/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK02/0x0001_hello-world/pico_sdk_import.cmake b/WEEK02/0x0001_hello-world/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK02/0x0001_hello-world/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK02/WEEK02-SLIDES.pdf b/WEEK02/WEEK02-SLIDES.pdf new file mode 100644 index 0000000..592fbf1 Binary files /dev/null and b/WEEK02/WEEK02-SLIDES.pdf differ diff --git a/WEEK02/WEEK02.md b/WEEK02/WEEK02.md new file mode 100644 index 0000000..ea41551 --- /dev/null +++ b/WEEK02/WEEK02.md @@ -0,0 +1,1646 @@ +# Week 2: Hello, World - Debugging and Hacking Basics: Debugging and Hacking a Basic Program for the Pico 2 + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Connect to a live embedded system using OpenOCD and GDB +- Step through code instruction by instruction and watch the stack change +- Examine memory, registers, and decode little-endian values +- Set strategic breakpoints to pause execution at key moments +- Understand why direct string assignment fails in bare-metal systems +- Write custom data directly to SRAM memory +- Hijack register values to redirect program behavior +- Modify a running program's output in real-time + +## Review from Week 1 +This week builds directly on Week 1 concepts. You should already be comfortable with: + +- **Registers** (`r0`-`r12`, SP, LR, PC) - We'll watch them change and manipulate `r0` to change program behavior +- **Memory Layout** (Flash at `0x10000000`, RAM at `0x20000000`) - Critical for understanding where we can write +- **The Stack** and how `push`/`pop` work - We'll watch this in action +- **Little-Endian** byte ordering - We'll decode values live +- **GDB basics** from Week 1's dynamic analysis section +- **Ghidra basics** from Week 1's static analysis section + +--- + +## Part 1: Understanding Live Hacking + +#### What is Live Hacking? + +**Live hacking** means modifying a program *while it's running* on real hardware. Instead of changing the source code and recompiling, we intercept the program mid-execution and change what it does on the fly. + +Think of it like this: imagine a train is heading to New York City. Live hacking is like switching the tracks while the train is moving so it goes to Los Angeles instead! + +#### Why is This Important? + +Live hacking techniques are used for: + +- **Security Research**: Finding vulnerabilities in embedded systems +- **Penetration Testing**: Testing if systems can be compromised +- **Malware Analysis**: Understanding how malicious code works +- **Debugging**: Fixing bugs in systems that can't be easily reprogrammed + +#### Real-World Application + +> **"With great power comes great responsibility!"** + +Imagine you're a security researcher testing an industrial control system at a power plant. You need to verify that an attacker couldn't: + +1. Change the values being displayed to engineers +2. Make dangerous equipment appear safe +3. Hide malicious activity from monitoring systems + +The techniques you'll learn today are *exactly* how this would be done. Understanding these attacks helps us build better defenses! + +--- + +## Part 2: Review - Memory Layout (from Week 1) + +> **REVIEW:** In Week 1, we learned about the RP2350's memory layout. This knowledge is essential for our hack! + +Before we hack, let's remember where things live in memory on the RP2350: + +#### The Code We're Hacking + +Remember our `0x0001_hello-world.c` program from Week 1: + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} +``` + +This simple program: + +1. Initializes I/O with `stdio_init_all()` +2. Enters an infinite `while(true)` loop +3. Prints `"hello, world\r\n"` forever + +Our goal: **Make it print something else WITHOUT changing the source code!** + +#### Memory Map + +``` ++-----------------------------------------------------+ +| Flash Memory (XIP) - READ ONLY | +| Starts at: 0x10000000 | +| Contains: Program code, constant strings | +| NOTE: We CANNOT write to flash during runtime! | ++-----------------------------------------------------+ +| SRAM - READ/WRITE | +| Starts at: 0x20000000 | +| Contains: Stack, Heap, Variables | +| NOTE: We CAN write to SRAM during runtime! | ++-----------------------------------------------------+ +``` + +> **REVIEW:** In Week 1, we saw SP values in the `0x20081xxx` range (for example `0x20081fc8`) - that's in the SRAM region. In this run you may see values like `0x20081ff8` depending on where execution is paused. The stack "grows downward" from the top of SRAM. + +#### Why This Matters for Our Hack + +The string `"hello, world"` is stored in **flash memory** (around `0x100019cc`). Flash memory is **read-only** during normal operation - we can't just overwrite it. + +But SRAM (starting at `0x20000000`) is **read-write**! This is where we'll create our hacked string. + +--- + +## Part 3: The Attack Plan + +Here's our step-by-step attack strategy: + +``` ++-----------------------------------------------------+ +| STEP 1: Start the debug server (OpenOCD) | ++-----------------------------------------------------+ +| STEP 2: Connect with GDB and halt the program | ++-----------------------------------------------------+ +| STEP 3: Set a breakpoint right before puts() | ++-----------------------------------------------------+ +| STEP 4: When we hit the breakpoint, r0 contains | +| the address of "hello, world" | ++-----------------------------------------------------+ +| STEP 5: Create our malicious string in SRAM | ++-----------------------------------------------------+ +| STEP 6: Change r0 to point to OUR string | ++-----------------------------------------------------+ +| STEP 7: Continue execution - HACKED! | ++-----------------------------------------------------+ +``` + +--- + +## Part 4: Setting Up Your Environment + +#### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board with debug probe connected +2. OpenOCD installed and configured +3. GDB (arm-none-eabi-gdb) installed +4. A serial monitor application (like PuTTY, minicom, or screen) +5. The "hello-world" binary loaded on your Pico 2 + +#### What You'll Need Open + +You will need **THREE** terminal windows: + +1. **Terminal 1**: Running OpenOCD (the debug server) +2. **Terminal 2**: Running GDB (where we do the hacking) +3. **PuTTY**: Running your serial monitor (to see output) + +--- + +## Part 5: GDB Deep Dive - Exploring the Binary + +Before we start hacking, let's use GDB to thoroughly understand our program. This hands-on tutorial will teach you to examine memory, step through code, and watch the stack in action. + +#### Starting the Debug Environment + +##### Step 0a: Start OpenOCD (Terminal 1) + +OpenOCD is the bridge between your computer and the Pico 2's debug interface. It creates a server that GDB can connect to. + +**Open Terminal 1 and type:** + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +**What this command means:** + +- `openocd` = the OpenOCD program +- `-s ...` = path to OpenOCD scripts folder +- `-f interface/cmsis-dap.cfg` = use the CMSIS-DAP debug probe configuration +- `-f target/rp2350.cfg` = configure for the RP2350 chip +- `-c "adapter speed 5000"` = set the debug speed to 5000 kHz + +**You should see output like:** + +``` +Open On-Chip Debugger 0.12.0 +Licensed under GNU GPL v2 +Info : Listening on port 3333 for gdb connections +Info : CMSIS-DAP: SWD supported +Info : CMSIS-DAP: Interface ready +``` + +**Important:** Leave this terminal running! Don't close it. + +##### Step 0b: Start Your Serial Monitor - PuTTY (Terminal 2) + +PuTTY will show us the output from our Pico 2. When we hack the program, we'll see the results here! + +**To set up PuTTY:** + +1. Open **PuTTY** +2. In the **Session** category: + - **Connection type**: Select **Serial** + - **Serial line**: Enter your COM port (e.g., `COM3` - check Device Manager to find yours) + - **Speed**: Enter `115200` +3. Click **Open** + +> Tip: **Finding your COM port:** Open Device Manager -> Ports (COM & LPT) -> Look for "USB Serial Device" or "Pico" - note the COM number. + +**You should see:** + +``` +hello, world +hello, world +hello, world +hello, world +... +``` + +The program is running and printing `"hello, world"` in an infinite loop! + +**Important:** Leave PuTTY running! We'll watch it change when we hack the system. + +##### Step 0c: Start GDB (Terminal 3) + +**Open Terminal 3** and start GDB with your binary: + +```cmd +arm-none-eabi-gdb build\0x0001_hello-world.elf +``` + +**What this command means:** + +- `arm-none-eabi-gdb` = the ARM version of GDB +- `build\0x0001_hello-world.elf` = our compiled program with debug symbols + +**You should see:** + +``` +GNU gdb (Arm GNU Toolchain 13.2) 13.2 +Reading symbols from build\0x0001_hello-world.elf... +(gdb) +``` + +The `(gdb)` prompt means GDB is ready for commands! + +##### Step 0d: Connect GDB to OpenOCD + +Now we need to connect GDB to OpenOCD. OpenOCD is listening on port `3333`. + +**Type this command:** + +```gdb +(gdb) target extended-remote :3333 +``` + +**You should see:** + +``` +Remote debugging using :3333 +main () + at C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c:5 +5 stdio_init_all(); +``` + +We're connected! GDB shows us the program is currently in the `main` function. + +##### Step 0e: Halt the Running Program + +The program is still running (you can see "hello, world" still printing in PuTTY). Let's stop it: + +**Type this command:** + +```gdb +(gdb) monitor reset halt +``` + +**What this command means:** + +- `monitor` = send a command to OpenOCD (not GDB) +- `reset` = reset the processor +- `halt` = stop execution immediately + +**You should see:** + +``` +[rp2350.cm0] halted due to debug-request, current mode: Thread +xPSR: 0xf9000000 pc: 0x00000088 msp: 0xf0000000 +[rp2350.cm1] halted due to debug-request, current mode: Thread +xPSR: 0xf9000000 pc: 0x00000088 msp: 0xf0000000 +``` + +**Check PuTTY:** The "hello, world" messages should have stopped! The processor is now frozen, waiting for our commands. + +--- + +#### Exploring the Binary + +Now that we're connected and the processor is halted, let's explore! + +##### Step 1: Examine Memory Starting at XIP Base Address + +Our program code starts at address `0x10000000`. Let's look at the first 1000 instructions to find our `main` function. + +**Type this command in GDB:** + +```gdb +(gdb) x/1000i 0x10000000 +``` + +**What this command means:** + +- `x` = examine memory +- `/1000i` = show 1000 instructions +- `0x10000000` = starting address + +**What you're looking for:** + +Scroll through the output and look for something like this: + +``` +0x10000234
: push {r3, lr} +``` + +The `
` label tells us we found our main function! The address `0x10000234` is where main starts. + +##### Step 2: Examine the Main Function in Detail + +Now let's look at just the main function. We'll examine 5 instructions starting at the main function address: + +**Type this command:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**You should see:** + +``` +(gdb) x/5i 0x10000234 +=> 0x10000234
: push {r3, lr} + 0x10000236 : bl 0x1000156c + 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +**Let's understand each instruction:** + +| Address | Instruction | What It Does | +| ------------ | -------------------------------- | --------------------------------------------------- | +| `0x10000234` | `push {r3, lr}` | Save `r3` and the return address onto the stack | +| `0x10000236` | `bl 0x1000156c ` | Call the `stdio_init_all` function | +| `0x1000023a` | `ldr r0, [pc, #8]` | Load the address of our string into `r0` | +| `0x1000023c` | `bl 0x100015fc <__wrap_puts>` | Call `puts` to print our string | +| `0x10000240` | `b.n 0x1000023a` | Jump back to the `ldr` instruction (infinite loop!) | + +##### Step 3: Set a Breakpoint at Main + +A **breakpoint** is like a stop sign for your program. When the processor reaches that address, it will pause and let us examine things. + +**Type this command:** + +```gdb +(gdb) b *0x10000234 +``` + +**You should see:** + +``` +Breakpoint 1 at 0x10000234: file C:/Users/.../0x0001_hello-world.c, line 5. +Note: automatically using hardware breakpoints for read-only addresses. +``` + +**What this means:** + +- `b` = set breakpoint +- `*0x10000234` = at this exact memory address +- GDB confirms the breakpoint is set and even tells us which line of C code this corresponds to! + +##### Step 4: Continue Execution Until Breakpoint + +Now let's run the program until it hits our breakpoint: + +**Type this command:** + +```gdb +(gdb) c +``` + +**You should see:** + +``` +Continuing. + +Thread 1 "rp2350.cm0" hit Breakpoint 1, main () + at C:/Users/.../0x0001_hello-world.c:5 +5 stdio_init_all(); +``` + +**What happened:** + +- The processor ran until it reached address `0x10000234` +- It stopped right before executing the instruction at that address +- GDB shows us we're at line 5 of our C source code + +##### Step 5: Examine Instructions with Arrow + +Let's look at our instructions again: + +**Type this command:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**You should see:** + +``` +(gdb) x/5i 0x10000234 +=> 0x10000234
: push {r3, lr} + 0x10000236 : bl 0x1000156c + 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +**Notice the arrow `=>`!** This arrow shows which instruction we're about to execute. We haven't executed it yet - we're paused right before it. + +--- + +#### Understanding the Stack in Action + +##### Step 6: Examine the Stack Before Push + +Before we execute the `push` instruction, let's see what's on the stack: + +**Type this command:** + +```gdb +(gdb) x/10x $sp +``` + +**What this command means:** + +- `x` = examine memory +- `/10x` = show 10 values in hexadecimal +- `$sp` = starting at the stack pointer address + +**You should see:** + +``` +0x20082000: 0x00000000 0x00000000 0x00000000 0x00000000 +0x20082010: 0x00000000 0x00000000 0x00000000 0x00000000 +0x20082020: 0x00000000 0x00000000 +``` + +**What this shows:** + +- The stack pointer is at address `0x20082000` +- The stack is empty (all zeros) +- This is the "top" of our stack in RAM + +**Verify where this value came from (the Vector Table):** + +Now let's trace back where this initial `0x20082000` value came from. It comes from the first entry in the vector table at `0x10000000`: + +```gdb +(gdb) x/x $sp +0x20082000: 0x00000000 +(gdb) x/x 0x10000000 +0x10000000 <__vectors>: 0x20082000 +``` + +**What this shows:** + +- The first command `x/x $sp` reads one word at the stack pointer (currently `0x00000000`) +- The second command `x/x 0x10000000` reads the **first entry in the vector table** at address `0x10000000` +- That vector table entry contains `0x20082000` - this is the **initial stack pointer value**! +- The Boot ROM reads this value and puts it into the SP register when the chip starts +- This is why our SP register already has `0x20082000` before `main()` runs + +##### Step 7: Execute One Instruction (Step Into) + +Now let's execute just ONE assembly instruction: + +**Type this command:** + +```gdb +(gdb) si +``` + +**What this command means:** + +- `si` = step instruction (execute one assembly instruction) + +**You should see:** + +``` +0x10000236 5 stdio_init_all(); +``` + +Let's verify where we are: + +**Type this command:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**You should see:** + +``` +(gdb) x/5i 0x10000234 + 0x10000234
: push {r3, lr} +=> 0x10000236 : bl 0x1000156c + 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +**Notice:** The arrow `=>` has moved! We've executed the `push` instruction and are now about to execute the `bl` (branch with link) instruction. + +##### Step 8: Examine the Stack After Push + +Now let's see what the push instruction did to our stack: + +**Type this command:** + +```gdb +(gdb) x/10x $sp +``` + +**You should see:** + +``` +0x20081ff8: 0xe000ed08 0x1000018f 0x00000000 0x00000000 +0x20082008: 0x00000000 0x00000000 0x00000000 0x00000000 +0x20082018: 0x00000000 0x00000000 +``` + +**What changed:** + +- The stack pointer moved from `0x20082000` to `0x20081ff8` +- That's 8 bytes lower (2 * 4-byte values) +- Two new values appeared: `0xe000ed08` and `0x1000018f` + +##### Step 9: Verify What Was Pushed + +Let's prove that these values came from `r3` and `lr`: + +**Check `r3`:** + +```gdb +(gdb) x/x $r3 +``` + +**You should see:** + +``` +0xe000ed08: Cannot access memory at address 0xe000ed08 +``` + +This error is expected! The value `0xe000ed08` is in `r3`, and when we try to examine it as an address, that memory location isn't accessible. But we can see the value matches what's on the stack! + +**Check `lr` (Link Register):** + +```gdb +(gdb) x/x $lr +``` + +**You should see:** + +``` +0x1000018f : 0x00478849 +``` + +The value `0x1000018f` is in `lr` - this is the return address! This matches the second value on our stack. + +##### Step 10: Verify Stack Layout + +Let's look at each pushed value individually: + +**First pushed value (`r3`):** + +```gdb +(gdb) x/x $sp +``` + +**You should see:** + +``` +0x20081ff8: 0xe000ed08 +``` + +This is the value from `r3`, pushed first. + +**Second pushed value (`lr`):** + +```gdb +(gdb) x/x $sp+4 +``` + +**You should see:** + +``` +0x20081ffc: 0x1000018f +``` + +This is the value from `lr` (the return address), pushed second. + +### Understanding the Stack Diagram + +``` +Before push {r3, lr}: After push {r3, lr}: + +Address Value Address Value +--------------------- --------------------- +0x20082000 (empty) ← SP 0x20082000 (old SP location) + 0x20081ffc 0x1000018f (lr) + 0x20081ff8 0xe000ed08 (r3) ← SP +``` + +**Key Points:** + +1. The stack grows DOWNWARD (addresses get smaller) +2. The SP always points to the last item pushed +3. `r3` was pushed first, then `lr` was pushed on top of it + +--- + +#### Continuing Through the Program + +##### Step 11: Step Over the stdio_init_all Function + +We don't need to examine every instruction inside `stdio_init_all` - it's just setup code. Let's "step over" it: + +**First, verify where we are:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**You should see:** + +```gdb +(gdb) x/5i 0x10000234 + 0x10000234
: push {r3, lr} +=> 0x10000236 : bl 0x1000156c + 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +**Now step over the function call:** + +```gdb +(gdb) n +``` + +**What this command means:** + +- `n` = next (step over function calls, don't go inside them) + +**You should see:** + +``` +8 printf("hello, world\r\n"); +``` + +**Verify where we are now:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**You should see:** + +```gdb +(gdb) x/5i 0x10000234 + 0x10000234
: push {r3, lr} + 0x10000236 : bl 0x1000156c +=> 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +The arrow has moved past the function call! + +#### Understanding the LDR Instruction + +We're now at: +``` +ldr r0, [pc, #8] @ (0x10000244 ) +``` + +**What does this instruction do?** + +1. Take the current Program Counter (PC) value +2. Add 8 to it +3. Go to that memory address (`0x10000244`) +4. Load the value stored there into `r0` + +This is loading a **pointer** - the address of our "hello, world" string! + +##### Step 13: Execute the LDR and Examine `r0` + +**Execute one instruction:** + +```gdb +(gdb) si +``` + +**You should see:** + +``` +0x1000023c 8 printf("hello, world\r\n"); +``` + +**Now examine what's in `r0`:** + +```gdb +(gdb) x/x $r0 +``` + +**You should see:** + +``` +0x100019cc: 0x6c6c6568 +``` + +##### Step 14: Decoding the Mystery Value + +The value `0x6c6c6568` looks strange, but it's actually ASCII characters! Let's decode it: + +**ASCII Table Reference:** + +| Hex | Character | +| ------ | --------- | +| `0x68` | h | +| `0x65` | e | +| `0x6c` | l | +| `0x6c` | l | + +So `0x6c6c6568` = "lleh" backwards! + +**Why is it backwards?** + +This is called **little-endian** byte order. The RP2350 stores bytes in reverse order in memory. When we read them as a 32-bit value, they appear reversed. + +##### Step 15: View the Full String + +Let's tell GDB to show this as a string instead of a hex number: + +```gdb +(gdb) x/s $r0 +``` + +**What this command means:** + +- `x` = examine memory +- `/s` = show as a string +- `$r0` = at the address stored in `r0` + +**You should see:** + +``` +0x100019cc: "hello, world\r" +``` + +There's our string! The `\r` is a carriage return character (part of `\r\n`). + +> **Key Discovery:** The string `"hello, world"` is stored at address `0x100019cc` in flash memory. This is the value that gets loaded into `r0` before calling `puts()`. We'll use this knowledge in our hack! + +--- + +## Part 6: Continuing the Debug Session for the Hack + +You're right where you need to be from Part 5, so we **do not restart** OpenOCD or GDB here. + +Use this as a quick checkpoint before the hack: + +- OpenOCD is still running and listening on `:3333` +- GDB is still connected (`target extended-remote :3333` already done) +- The target is halted at a known point (or easy to re-halt) + +If your session is still live, continue directly to Part 7. + +If you got disconnected, run only this minimal recovery in GDB: + +```gdb +(gdb) target extended-remote :3333 +(gdb) monitor reset halt +``` + +After that, continue to the analysis steps below. + +--- + +## Part 7: Analyzing the Target + +> **REVIEW:** We're using the same GDB commands we learned earlier. The `x` command examines memory, and `/5i` shows 5 instructions. + +##### Step 6: Examine the Main Function + +Let's look at the main function to understand what we're dealing with: + +**Type this command:** + +```gdb +(gdb) x/5i 0x10000234 +``` + +**What this command means:** + +- `x` = examine memory (Week 1 review!) +- `/5i` = show 5 instructions +- `0x10000234` = the address of main (we found this in Week 1!) + +**You should see:** + +```gdb +(gdb) x/5i 0x10000234 + 0x10000234
: push {r3, lr} + 0x10000236 : bl 0x1000156c + 0x1000023a : ldr r0, [pc, #8] @ (0x10000244 ) +=> 0x1000023c : bl 0x100015fc <__wrap_puts> + 0x10000240 : b.n 0x1000023a +``` + +> **REVIEW:** This is the same disassembly we analyzed in Week 1! Remember: +> +> - `push {r3, lr}` saves registers to the stack +> - `bl` is "branch with link" - it calls a function and saves the return address in LR +> - `b.n` is the infinite loop that jumps back to the `ldr` instruction + +#### Understanding the Code Flow + +> **REVIEW:** In Week 1, we learned that `r0`-`r3` are used to pass arguments to functions. The first argument always goes in `r0`! + +Let's break down what happens each time through the loop: + +| Address | Instruction | What Happens | +| ------------ | ------------------ | ------------------------------------------------------ | +| `0x1000023a` | `ldr r0, [pc, #8]` | Load the address of `"hello, world"` into `r0` | +| `0x1000023c` | `bl __wrap_puts` | Call `puts()` - it reads the string address from `r0`! | +| `0x10000240` | `b.n 0x1000023a` | Jump back to the `ldr` instruction (loop forever) | + +#### How This Maps to Our C Code + +```c +while (true) + printf("hello, world\r\n"); // The compiler optimized this to puts() +``` + +The compiler: + +1. Loads the string address into `r0` (first argument) +2. Calls `puts()` (optimized from `printf()` since we're just printing a string) +3. Loops back forever with `b.n` + +**The Key Insight:** Right before the `bl __wrap_puts` instruction (at `0x1000023c`), the register `r0` contains the address of the string to print! + +If we can change what `r0` points to, we can make it print **anything we want**! + +--- + +## Part 8: Setting the Trap + +> **REVIEW:** In Week 1, we used `b main` and `b *0x10000234` to set breakpoints. Now we'll use the same technique at a more strategic location! + +##### Step 7: Set a Strategic Breakpoint + +We want to stop the program RIGHT BEFORE it calls `puts()`. That's at address `0x1000023c`. + +**Type this command:** + +```gdb +(gdb) b *0x1000023c +``` + +**What this command means:** + +- `b` = set a breakpoint (same as Week 1!) +- `*0x1000023c` = at this exact memory address (the asterisk means "address") + +**You should see:** + +``` +Breakpoint 2 at 0x1000023c: file C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c, line 8 +``` + +**What does "hardware breakpoints" mean?** + +Because our code is in flash memory (read-only), GDB can't insert a software breakpoint by modifying the code. Instead, it uses a special feature of the ARM processor called a **hardware breakpoint**. The processor has a limited number of these (usually 4-8), but they work on any memory type. + +##### Step 8: Continue Execution and Hit the Breakpoint + +Now let's run the program until it hits our breakpoint: + +**Type this command:** + +```gdb +(gdb) c +``` + +**What this command means:** + +- `c` = continue (run until something stops us) + +**You should see:** + +```gdb +Continuing. + +Thread 1 "rp2350.cm0" hit Breakpoint 2, 0x1000023c in main () + at C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c:8 +8 printf("hello, world\r\n"); +``` + +The program has stopped RIGHT BEFORE calling `puts()`! The string address is loaded into `r0`, but the function hasn't been called yet. + +##### Step 9: Verify Our Position with Disassembly + +Let's double-check where we are using the `disas` command: + +**Type this command:** + +```gdb +(gdb) disas +``` + +**What this command means:** + +- `disas` = disassemble the current function + +**You should see:** + +```gdb +(gdb) disas +Dump of assembler code for function main: + 0x10000234 <+0>: push {r3, lr} + 0x10000236 <+2>: bl 0x1000156c + 0x1000023a <+6>: ldr r0, [pc, #8] @ (0x10000244 ) +=> 0x1000023c <+8>: bl 0x100015fc <__wrap_puts> + 0x10000240 <+12>: b.n 0x1000023a + 0x10000242 <+14>: nop + 0x10000244 <+16>: adds r4, r1, r7 + 0x10000246 <+18>: asrs r0, r0, #32 +``` + +**Notice the arrow `=>`** pointing to `0x1000023c`! This confirms we're about to execute the `bl __wrap_puts` instruction. Perfect! + +--- + +## Part 9: Examining the Current State + +> **REVIEW:** In Week 1, we used `x/s $r0` to view the "hello, world" string. We also learned about **little-endian** byte ordering - remember how `0x6c6c6568` spelled "lleh" backwards? + +##### Step 10: Examine What's in r0 + +Let's see what string `r0` is currently pointing to: + +**Type this command:** + +```gdb +(gdb) x/s $r0 +``` + +**What this command means:** + +- `x` = examine memory (Week 1 review!) +- `/s` = display as a string +- `$r0` = the address stored in register `r0` + +**You should see:** + +```gdb +0x100019cc: "hello, world\r" +``` + +There it is! The register `r0` contains `0x100019cc`, which is the address of our `"hello, world"` string in flash memory. + +> **REVIEW:** This is the same address `0x100019cc` we discovered in Week 1, Step 15 when we used `x/s $r0` after executing the `ldr` instruction! + +--- + +## Part 10: The Failed Hack Attempt (Learning Why) + +##### Step 11: Try to Directly Change the String (This Will Fail!) + +Your first instinct might be to just assign a new string to `r0`. Let's try it and see what happens: + +**Type this command:** + +```gdb +(gdb) set $r0 = "hacky, world\r" +``` + +**You should see an error:** + +``` +evaluation of this expression requires the program to have a function "malloc". +``` + +**Oh no! It didn't work!** + +#### Why Did This Fail? + +This is a very important lesson! Here's what happened: + +1. When you type `"hacky, world\r"` in GDB, GDB interprets this as: "Create a new string and give me its address" + +2. To create a new string at runtime, GDB tries to allocate target memory using `malloc()`. + +3. If the target program exposed a working `malloc()` that GDB could call, this style of assignment can work. + +4. In our case, this is a bare-metal firmware image and there is no usable `malloc()` path for GDB expression evaluation, so GDB cannot create temporary storage for that string literal. + +5. That is why this command fails here, and why we switch to writing bytes directly into SRAM ourselves. + +**Let's verify nothing changed:** + +```gdb +(gdb) x/s $r0 +``` + +**You should see:** + +``` +0x100019cc: "hello, world\r" +``` + +The original string is still there. Our hack attempt failed... but we're not giving up! + +--- + +## Part 11: The Real Hack - Writing to SRAM + +##### Step 12: Understanding the Solution + +Since we can't use `malloc()`, we need to manually create our string somewhere in memory. Remember our memory map? + +- Flash (`0x10000000`): **Read-only** - can't write here +- SRAM (`0x20000000`): **Read-write** - we CAN write here! + +> **REVIEW:** In Week 1 we observed SP in the `0x20081xxx` range (for example `0x20081fc8`). In this run, after `push {r3, lr}`, you are seeing `0x20081ff8`, which is also correct and still near the top of SRAM. We'll write our string at a safer SRAM address (`0x20040000`) to avoid vector-table and stack conflicts. + +We'll write our malicious string directly to SRAM, then point `r0` to it. + +##### Step 13: Create Our Malicious String in SRAM + +We need to write 13 bytes (12 characters + null terminator) to SRAM: + +| Character | ASCII Hex | +| --------- | --------- | +| h | - | +| a | - | +| c | - | +| k | - | +| y | - | +| , | - | +| (space) | - | +| w | - | +| o | - | +| r | - | +| l | - | +| d | - | +| `\r` | - | +| \0 | - | + +**Type this command:** + +```gdb +(gdb) set {char[13]} 0x20040000 = "hacky, world" +``` + +**What this command means:** + +- `set` = modify memory +- `{char[13]}` = treat the target as an array of 13 characters +- `0x20040000` = the address where we're writing (safe SRAM offset) +- `= "hacky, world"` = the string bytes to write + +**No output means success!** + +##### Step 14: Verify Our String Was Written + +Let's confirm our malicious string is in SRAM: + +**Type this command:** + +```gdb +(gdb) x/s 0x20040000 +``` + +**You should see:** + +```gdb +0x20040000: "hacky, world" +``` + +**OUR STRING IS IN MEMORY!** + +The important thing is our string is in writable SRAM at a safe offset and ready to use. + +--- + +## Part 12: Hijacking the Register + +> **REVIEW:** In Week 1, we learned that `r0` holds the first argument to a function. When `puts()` is called, it expects `r0` to contain a pointer to the string it should print. By changing `r0`, we change what gets printed! + +##### Step 15: Change r0 to Point to Our String + +Now for the magic moment! We'll change `r0` from pointing to the original string to pointing to OUR string: + +**Type this command:** + +```gdb +(gdb) set $r0 = 0x20040000 +``` + +**What this command means:** + +- `set` = modify a value +- `$r0` = the `r0` register +- `= 0x20040000` = change it to this address (where our string is) + +**No output means success!** + +##### Step 16: Verify the Register Was Changed + +Let's confirm `r0` now points to our malicious string: + +**First, check one byte (explicit byte view):** + +```gdb +(gdb) x/bx $r0 +``` + +**You should see:** + +``` +0x20040000: 0x68 +``` + +The value `0x68` is ASCII `'h'`, the first byte of `"hacky, world"`. + +**Now check one 32-bit word (explicit word view):** + +```gdb +(gdb) x/wx $r0 +``` + +**You should see:** + +``` +0x20040000: 0x6b636168 +``` + +This is the first 4 bytes (`h a c k`) packed into one 32-bit little-endian word. + +**Now check it as a string:** + +```gdb +(gdb) x/s $r0 +``` + +**You should see:** + +``` +0x20040000: "hacky, world" +``` + +**THE HIJACK IS COMPLETE!** When `puts()` runs, it will read the string address from `r0` - which now points to our malicious string! + +--- + +## Part 13: Executing the Hack + +##### Step 17: Continue Execution + +This is the moment of truth! Let's continue the program and watch our hack take effect: + +**Type this command:** + +```gdb +(gdb) c +``` + +**You should see:** + +```gdb +Continuing. + +Thread 1 "rp2350.cm0" hit Breakpoint 2, 0x1000023c in main () + at C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c:8 +8 printf("hello, world\r\n"); +``` + +The program ran through one loop iteration and hit our breakpoint again. + +##### Step 18: Check Your Serial Monitor! + +**Look at Terminal 2 (your serial monitor)!** + +**You should see:** + +``` +hello, world +hello, world +hello, world +hacky, world <-- OUR HACK! +``` + + **BOOM! WE DID IT!** + +You just modified a running program on real hardware! The processor executed code that was supposed to print "hello, world" but instead printed "hacky, world" because we hijacked the data it was using! + +--- + +## Part 14: Static Analysis with Ghidra - Understanding the Hack + +Now that we've performed the hack dynamically with GDB, let's use Ghidra to understand the same concepts through static analysis. This shows how you could plan such an attack without even connecting to the hardware! + +#### Opening the Project in Ghidra + +If you haven't already set up the Ghidra project from Week 1: + +1. Launch Ghidra +2. Select **File -> New Project** -> **Non-Shared Project** +3. Name it `0x0001_hello-world` +4. Drag and drop `0x0001_hello-world.elf` into the project +5. Double-click to open in CodeBrowser +6. Click **Yes** to auto-analyze + +##### Step 1: Navigate to Main + +1. In the **Symbol Tree** panel (left side), expand **Functions** +2. Find and click on `main` + +**What you'll see in the Listing View:** + +``` + ************************************************************* + * FUNCTION + ************************************************************* + int main (void ) + assume LRset = 0x0 + assume TMode = 0x1 + int r0:4 + main XREF[3]: Entry Point (*) , + _reset_handler:1000018c (c) , + .debug_frame::00000018 (*) + 0x0001_hello-world.c:4 (2) + 0x0001_hello-world.c:5 (2) + 10000234 08 b5 push {r3,lr} + 0x0001_hello-world.c:5 (4) + 10000236 01 f0 99 f9 bl stdio_init_all _Bool stdio_init_all(void) + LAB_1000023a XREF[1]: 10000240 (j) + 0x0001_hello-world.c:7 (6) + 0x0001_hello-world.c:8 (6) + 1000023a 02 48 ldr r0=>__EH_FRAME_BEGIN__ ,[DAT_10000244 ] = "hello, world\r" + = 100019CCh + 1000023c 01 f0 de f9 bl __wrap_puts int __wrap_puts(char * s) + 0x0001_hello-world.c:7 (8) + 10000240 fb e7 b LAB_1000023a + 10000242 00 ?? 00h + 10000243 bf ?? BFh + DAT_10000244 XREF[1]: main:1000023a (R) + 10000244 cc 19 00 10 undefine 100019CCh ? -> 100019cc +``` + +**What you'll see in the Decompile View:** + +```c +int main(void) + +{ + stdio_init_all(); + do { + __wrap_puts("hello, world\r"); + } while( true ); +} +``` + +##### Step 2: Identify the Attack Point + +In our GDB hack, we set a breakpoint at `0x1000023c` - right before `bl __wrap_puts`. Let's understand why this was the perfect attack point: + +**Click on address `0x1000023c` in the Listing view.** + +Notice: + +- The instruction is `bl __wrap_puts` - a function call +- The previous instruction at `0x1000023a` loaded `r0` with the string address +- Ghidra shows `= "hello, world\r"` right in the listing! + +> **Key Insight:** Ghidra already tells us the string value! In the Listing, you can see `= "hello, world\r"` and `= 100019CCh`. This is the exact address we discovered through GDB! + +##### Step 3: Find the String in Memory + +Let's trace where the string actually lives: + +1. In the Listing view, look at address `0x1000023a`: + ``` + LAB_1000023a XREF[1]: 10000240 (j) + 0x0001_hello-world.c:7 (6) + 0x0001_hello-world.c:8 (6) + 1000023a 02 48 ldr r0=>__EH_FRAME_BEGIN__ ,[DAT_10000244 ] = "hello, world\r" + = 100019CCh + ``` + +2. **Double-click on `DAT_10000244`** to go to the data reference + +3. You'll see: + ``` + DAT_10000244 XREF[1]: main:1000023a (R) + 10000244 cc 19 00 10 undefine 100019CCh ? -> 100019cc + ``` + +4. **Double-click on `100019CCh`** to navigate to the actual string + +**You'll arrive at the string data:** + +``` + // + // .rodata + // SHT_PROGBITS [0x100019cc - 0x10001b17] + // ram:100019cc-ram:10001b17 + // + __init_array_end XREF[5]: Entry Point (*) , + __boot2_start__ frame_dummy:10000218 (*) , + __boot2_end__ main:1000023a (*) , + __EH_FRAME_BEGIN__ runtime_init:1000138a (R) , + _elfSectionHeaders::0000005c (*) + 100019cc 68 65 6c ds "hello, world\r" + 6c 6f 2c + 20 77 6f +``` + +##### Step 4: Understand Why We Needed SRAM + +Look at the string address: `0x100019cc` + +This starts with `0x10...` which means it's in **Flash memory (XIP region)**! + +| Address Range | Memory Type | Writable? | +| ------------- | ----------- | --------- | +| `0x10000000`+ | Flash (XIP) | **NO** - Read Only | +| `0x20000000`+ | SRAM | **YES** - Read/Write | + +> **This is why our direct string modification failed in GDB!** The string lives in flash memory, which is read-only at runtime. We had to create our malicious string in SRAM at a safe address (`0x20040000`) instead. + +##### Step 5: Examine Cross-References + +Ghidra's cross-reference feature shows everywhere a value is used: + +1. Navigate back to `main` (press **G**, type `main`, press Enter) +2. Click on `__wrap_puts` at address `0x1000023c` +3. Right-click and select **References -> Show References to __wrap_puts** + +This shows every place that calls `puts()`. In a larger program, you could find ALL the print statements and potentially modify any of them! + +##### Step 6: Use the Decompiler to Plan Attacks + +The Decompile view makes attack planning easy: + +```c +int main(void) + +{ + stdio_init_all(); + do { + __wrap_puts("hello, world\r"); + } while( true ); +} +``` + +From this view, you can immediately see: + +- The program loops forever (`do { } while (true)`) +- It calls `__wrap_puts()` with a string argument +- To change the output, you need to change what's passed to `puts()` + +##### Step 7: Viewing the String in the .rodata Section + +When you navigate to the string address `0x100019cc`, you'll see the string stored in the `.rodata` (read-only data) section: + +``` + // + // .rodata + // SHT_PROGBITS [0x100019cc - 0x10001b17] + // ram:100019cc-ram:10001b17 + // + __init_array_end XREF[5]: Entry Point (*) , + __boot2_start__ frame_dummy:10000218 (*) , + __boot2_end__ main:1000023a (*) , + __EH_FRAME_BEGIN__ runtime_init:1000138a (R) , + _elfSectionHeaders::0000005c (*) + 100019cc 68 65 6c ds "hello, world\r" + 6c 6f 2c + 20 77 6f +``` + +This shows the raw bytes of our string: `68 65 6c 6c 6f 2c 20 77 6f...` which spell out `"hello, world\r"` in ASCII. + +##### Step 8: Patching Data in Ghidra (Preview) + +Ghidra allows you to modify data directly in the binary! Here's how to patch the string: + +1. **Navigate to the string** at address `0x100019cc` +2. **Right-click** on the string `"hello, world\r"` in the Listing view +3. **Select** **Patch Data** from the context menu +4. **Type** your new string: `"hacky, world\r"` +5. **Press Enter** to apply the patch + +> **Important:** The new string must be the **same length or shorter** than the original! If your new string is longer, it will overwrite adjacent data and likely crash the program. + +| Original String | Patched String | Result | +| --------------- | -------------- | ------ | +| `hello, world\r` (14 bytes) | `hacky, world\r` (14 bytes) | Works perfectly | +| `hello, world\r` (14 bytes) | `PWNED!\r` (7 bytes) | Works (shorter is OK) | +| `hello, world\r` (14 bytes) | `this is a much longer string\r` | Overwrites other data! | + +After patching, you'll see the change reflected in the Listing view: + +``` + 100019cc 68 61 63 ds "hacky, world\r" + 6b 79 2c + 20 77 6f +``` + +Notice how the bytes changed: `68 65 6c 6c 6f` ("hello") became `68 61 63 6b 79` ("hacky")! + +#### Looking Ahead: Persistent Binary Patching + +> **Coming in Future Lessons:** What we've done in Ghidra so far is just a **preview** of the patch - it modifies the data in Ghidra's view, but doesn't save it back to the actual binary file. + +In future lessons, we will learn how to: + +1. **Export the patched binary** from Ghidra to create a modified `.elf` or `.bin` file +2. **Flash the patched binary** to the Pico 2, making the hack **persistent** + +The key difference: + +| Technique | Persistence | When It's Useful | +| --------- | ----------- | ---------------- | +| **GDB Live Hacking** (this week) | Temporary - lost on reset | Testing, debugging, quick exploitation | +| **Ghidra Patch Preview** (this step) | None - just visualization | Planning and verifying patches | +| **Binary Patching** (future lessons) | **Permanent** - survives reboot | Persistent backdoors, firmware mods | + +This step helps you understand the mechanics of modifying binary data. Once you're comfortable with this concept, you'll be ready to create truly persistent modifications! + +#### Comparing GDB and Ghidra Approaches + +| Task | GDB (Dynamic) | Ghidra (Static) | +| ---- | ------------- | --------------- | +| Find main address | `x/1000i 0x10000000` + search | Symbol Tree -> Functions -> main | +| Find string address | Step through `ldr`, examine `$r0` | Click on `ldr` - shows `= 100019CCh` | +| See string content | `x/s $r0` | Double-click address -> see `ds "hello, world"` | +| Identify attack point | Set breakpoints, step, observe | Read decompiled code, find function calls | +| Verify memory type | Know address ranges | Check address prefix (`0x10...` vs `0x20...`) | + +#### Why Use Both Tools? + +- **Ghidra** helps you **plan** the attack by understanding code structure +- **GDB** lets you **execute** the attack and modify live values +- Together, they form a complete reverse engineering workflow! + +#### Ghidra Tips for Attack Planning + +1. **Use the Decompiler** - It shows you the high-level logic without decoding assembly +2. **Follow Cross-References** - Find all places a function or variable is used +3. **Check Address Ranges** - Quickly identify Flash vs SRAM locations +4. **Add Comments** - Press `;` to annotate what you discover for later +5. **Rename Variables** - Right-click -> Rename to give meaningful names + +--- + +## Part 15: Summary and Review + +#### What We Accomplished + +We successfully performed a **live memory injection attack**: + +1. **Connected** to a running embedded system using OpenOCD and GDB +2. **Analyzed** the program flow to find the perfect attack point +3. **Set a breakpoint** right before the critical function call +4. **Discovered** that direct string assignment doesn't work without `malloc()` +5. **Wrote** our malicious data directly to SRAM +6. **Hijacked** the `r0` register to point to our data +7. **Executed** the hack and watched the output change! + +#### Week 1 Concepts We Applied + +| Week 1 Concept | How We Used It This Week | +| -------------- | ------------------------ | +| Memory Layout (Flash vs RAM) | We knew flash is read-only, so we wrote to SRAM | +| Registers (`r0`) | We hijacked `r0` to point to our malicious string | +| GDB `x` command | We examined memory and verified our injected string | +| GDB breakpoints (`b`) | We set a strategic breakpoint before `puts()` | +| Disassembly (`disas`) | We found the exact instruction to target | +| Little-endian | We understood how our string bytes are stored | + +#### The Attack Flow Diagram + +``` +BEFORE OUR HACK: ++-----------------+ +------------------------------+ +| r0 = 0x100019cc| ---> | Flash: "hello, world\r" | ++-----------------+ +------------------------------+ + | + ▼ + puts() prints "hello, world" + +AFTER OUR HACK: ++-----------------+ +------------------------------+ +| r0 = 0x20040000| ---> | SRAM: "hacky, world" | ++-----------------+ +------------------------------+ + | + ▼ + puts() prints "hacky, world" +``` + +#### New GDB Commands We Learned + +| Command | What It Does | New/Review | +| ---------------------------- | ----------------------------------- | ---------- | +| `target extended-remote :3333` | Connect to OpenOCD debug server | **New** | +| `monitor reset halt` | Reset and halt the processor | **New** | +| `disas` | Disassemble the current function | Review | +| `x/Ni ADDRESS` | Examine N instructions at ADDRESS | Review | +| `x/s ADDRESS` | Examine memory as a string | Review | +| `b *ADDRESS` | Set breakpoint at exact address | Review | +| `c` | Continue execution | Review | +| `set $r0 = VALUE` | Change a register's value | **New** | +| `set {char[N]} ADDR = {...}` | Write characters directly to memory | **New** | + +#### Key Memory Addresses + +| Address | What's There | Read/Write? | +| ------------ | -------------------------------- | ----------- | +| `0x10000234` | Start of `main()` function | Read-only | +| `0x1000023c` | The `bl __wrap_puts` call | Read-only | +| `0x100019cc` | Original `"hello, world"` string | Read-only | +| `0x20040000` | Safe SRAM location (hack target) | Read-Write | + +--- + +--- + +## Key Takeaways + +#### Building on Week 1 + +1. **Memory layout knowledge is power** - Understanding that flash is read-only and SRAM is read-write was essential for our hack. This directly built on Week 1's memory map lesson. + +2. **Registers control everything** - In Week 1, we watched registers change during execution. This week, we CHANGED them ourselves to alter program behavior. + +3. **GDB is a hacking tool** - The same commands we used for learning (`x`, `b`, `c`, `disas`) are the same commands used for exploitation. + +#### New Concepts + +4. **Flash is Read-Only at Runtime** - You can't modify code or constant strings in flash memory while the program runs. You must use SRAM. + +5. **Bare-Metal Means No Runtime** - Without an operating system, there's no `malloc()`, no dynamic memory allocation. You have to manage memory manually. + +6. **Registers Are the Key** - Function arguments are passed in registers (`r0`, `r1`, etc.). By changing these registers at the right moment, you can change what functions do. + +7. **Timing is Everything** - We had to set our breakpoint at exactly the right instruction. One instruction earlier, and `r0` wouldn't be loaded yet. One instruction later, and `puts()` would already have the wrong address. + +8. **This is Real Hacking** - The techniques you learned today are used by security researchers, penetration testers, and yes, attackers. Understanding these attacks helps us build more secure systems. + +--- + +## Security Implications + +#### How Would This Work in the Real World? + +Imagine an attacker with physical access to an industrial control system: + +| Scenario | Attack | +| ---------------------- | ----------------------------------------------------------------- | +| **Nuclear Centrifuge** | Change the displayed RPM from dangerous (15,000) to safe (10,000) | +| **Medical Device** | Modify dosage readings to hide an overdose | +| **Vehicle ECU** | Alter speedometer reading while car actually speeds | +| **Smart Lock** | Change the "locked" status to "unlocked" | + +#### How Do We Defend Against This? + +1. **Disable Debug Ports** - Production devices should have JTAG/SWD disabled +2. **Secure Boot** - Verify firmware hasn't been tampered with +3. **Memory Protection** - Use ARM's MPU to restrict memory access +4. **Tamper Detection** - Hardware that detects physical intrusion +5. **Encryption** - Keep sensitive data encrypted in memory + +--- + +## Glossary + +#### New Terms This Week + +| Term | Definition | +| ------------------------- | ---------------------------------------------------------------------- | +| **Bare-Metal** | Programming directly on hardware without an operating system | +| **CMSIS-DAP** | A standard debug interface protocol for ARM processors | +| **Hijack** | Taking control of a value or flow that was intended for something else | +| **Hardware Breakpoint** | A breakpoint implemented in CPU hardware, works on any memory | +| **Memory Injection** | Writing attacker-controlled data into a program's memory space | +| **OpenOCD** | Open On-Chip Debugger - software that interfaces with debug hardware | +| **Register Manipulation** | Changing the values stored in CPU registers | +| **SRAM** | Static Random Access Memory - fast, volatile, read-write memory | +| **Software Breakpoint** | A breakpoint implemented by modifying code (requires writable memory) | + +#### Review Terms from Week 1 + +| Term | Definition | Where We Used It | +| ------------------- | --------------------------------------------------------- | ---------------- | +| **Breakpoint** | A marker that pauses program execution at a specific location | Part 7 - Setting the trap | +| **Register** | Fast storage inside the processor | Part 11 - Hijacking `r0` | +| **Stack Pointer** | Register that points to the top of the stack | Part 2 - Memory layout | +| **XIP** | Execute In Place - running code directly from flash | Part 2 - Why we can't write to flash | +| **Little-Endian** | Storing the least significant byte at the lowest address | Part 10 - String storage | + + + diff --git a/WEEK02/WEEK02.pdf b/WEEK02/WEEK02.pdf new file mode 100644 index 0000000..d5a3529 Binary files /dev/null and b/WEEK02/WEEK02.pdf differ diff --git a/WEEK02/slides/WEEK02-IMG00.svg b/WEEK02/slides/WEEK02-IMG00.svg new file mode 100644 index 0000000..44adb6f --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 02 + + +Hello, World - Debugging and +Hacking Basics: Debugging and Hacking +a Basic Program for the Pico 2 + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK02/slides/WEEK02-IMG01.svg b/WEEK02/slides/WEEK02-IMG01.svg new file mode 100644 index 0000000..c48c43a --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG01.svg @@ -0,0 +1,73 @@ + + + + + +Live Hacking Overview +Introduction to Live Hacking + + + + What Is Live Hacking? + + + Modify a program + WHILE it is running + on real hardware + + + + The Train Analogy + Train heading to NYC + Switch the tracks + while it moves + Now it goes to LA! + + + + Why It Matters + Security research + Penetration testing + Malware analysis + Hardware debugging + + No recompile needed! + + + + This Week's Goal + + + Target Program + hello-world.c + Prints "hello, world" + in infinite loop + + + + Our Mission + Make it print + something ELSE + without changing + the source code + + + + Tools Used + GDB = live debug + OpenOCD = HW bridge + Ghidra = analysis + + Hack the running binary + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG02.svg b/WEEK02/slides/WEEK02-IMG02.svg new file mode 100644 index 0000000..718b3de --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG02.svg @@ -0,0 +1,85 @@ + + + + + +GDB Debug Session +GDB Fundamentals + + + + Setup Steps + + + + Step 1: Start OpenOCD + + openocd -s <scripts> + -f interface/cmsis-dap.cfg + -f target/rp2350.cfg + -c "adapter speed 5000" + + + Step 2: Launch GDB + + arm-none-eabi-gdb + build\0x0001_hello-world.elf + + + Step 3: Connect to target + + target extended-remote :3333 + + + Step 4: Reset + halt + + monitor reset halt + + + Step 5: Set breakpoint + + break main + + Then: continue (c) + + + + What Each Does + + + openocd + Loads probe + chip + config files + Then listens on :3333 + + + + arm-none-eabi-gdb + ARM debugger from + the embedded toolchain + + + + target extended-remote + GDB connects to + OpenOCD server + + + + monitor reset halt + Reset chip + stop + at very first instr + Clean starting state + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG03.svg b/WEEK02/slides/WEEK02-IMG03.svg new file mode 100644 index 0000000..3932205 --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG03.svg @@ -0,0 +1,88 @@ + + + + + +Breakpoints +GDB Breakpoint Types + + + + How They Work + + + + Normal Execution + + + MOV r0, #5 + + + MOV r1, #3 + + + BL printf + + + With Breakpoint + + + MOV r0, #5 + + + MOV r1, #3 + STOP + + + BL printf + paused + + CPU halts BEFORE + executing breakpoint + instruction + + Now you can inspect + + + + GDB Breakpoints + + + break main + Stop at function + By symbol name + + + + break *0x10000340 + Stop at exact addr + By hex address + + + + info break + List all active + breakpoints + + + + continue (c) + Resume running + until next break + + + + delete 1 + Remove breakpoint #1 + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG04.svg b/WEEK02/slides/WEEK02-IMG04.svg new file mode 100644 index 0000000..494fdda --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG04.svg @@ -0,0 +1,102 @@ + + + + + +Stack in Action +Runtime Stack Analysis + + + + Before Call + + + 0x20082000 + SP here + + + empty (0x20081FFC) + + + empty (0x20081FF8) + + + free stack space + + + unused lower space + + 0x20080000 + + Grows DOWN + + + + + + After PUSH + + + 0x20082000 + PUSH {r4, lr} + + + saved LR + + + saved r4 + + + free stack space + + + free stack space + + SP now = 0x20081FF8 + + SP moved down + by 8 bytes + GDB: x/4xw $sp + saved regs are now visible + + + + Key Points + + + PUSH saves + Preserves regs + before function + body runs + + + + POP restores + Puts values + back when func + returns + + + + Watch in GDB + x/4xw $sp + See stack data + + + + stepi + Step 1 instr + watch stack + change live + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG05.svg b/WEEK02/slides/WEEK02-IMG05.svg new file mode 100644 index 0000000..83ce46a --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG05.svg @@ -0,0 +1,79 @@ + + + + + +LDR Instruction +ARM Load Instructions + + + + How LDR Works + + + + Instruction: + + LDR r0, [pc, #12] + + + Step 1: Calculate addr + + addr = PC + 12 + + + Step 2: Read memory + + value = *(addr) + + + Step 3: Load into reg + + r0 = value + + + r0 now holds the + address of our + "hello, world" string + + + + Why It Matters + + + String Loading + printf needs addr + of string in r0 + r0 = first argument + + + + PC-Relative + Address computed + relative to current + PC position + Works from any addr + + + + The Attack Point + If we change r0 + AFTER the LDR + printf prints OUR + string instead! + + + + This is the hack! + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG06.svg b/WEEK02/slides/WEEK02-IMG06.svg new file mode 100644 index 0000000..52029b8 --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG06.svg @@ -0,0 +1,93 @@ + + + + + +The Attack Plan +Exploit Strategy + + + + Attack Flow (4 Steps) + + + + + 1. Break at + printf call + + + + + + + + 2. Write new + string to SRAM + + + + + + + + 3. Set r0 to + SRAM addr + + + + + + + + 4. Continue + execution + + printf reads r0, prints "hacky, world"! + + + + Normal Flow + + + + LDR r0, ="hello" + + + BL printf + + Output: + "hello, world" + + Prints original string + + + + Hacked Flow + + + + LDR r0, ="hello" + + + r0 = 0x20040000 + + + BL printf + + Output: + "hacky, world" + + Prints our string + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG07.svg b/WEEK02/slides/WEEK02-IMG07.svg new file mode 100644 index 0000000..984e441 --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG07.svg @@ -0,0 +1,80 @@ + + + + + +Failed vs Real Hack +Attack Methodology + + + + Failed Attempt + + + The Bad Idea + Set r0 to point + at a string literal + like "hacky" + + + + Why It Fails + r0 only holds a + 32-bit number + Not a string itself! + + + + set $r0 = "HACK" + GDB interprets this + as an address value + pointing to garbage + + + + Result: CRASH + or prints garbage + + + + Real Hack + + + The Right Way + 1. Write string + bytes to SRAM + 2. Point r0 to + that SRAM addr + + + + GDB Commands + + + set {char[13]}0x20040000 + + + = "hacky, world" + + + set $r0 = 0x20040000 + + + + String exists in + writable SRAM + r0 points to it + + "hacky, world" printed! + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG08.svg b/WEEK02/slides/WEEK02-IMG08.svg new file mode 100644 index 0000000..f9626eb --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG08.svg @@ -0,0 +1,83 @@ + + + + + +Writing to SRAM +Memory Manipulation + + + + SRAM at 0x20040000 + + + + Before (empty) + + + 00 00 00 00 00 00 00 00 + + + 00 00 00 00 00 00 00 00 + + + After writing + + + 68 61 63 6b 79 2c 20 77 + + h a c k y , w + + + GDB Command: + + + set {char[13]} + 0x20040000 = "hacky, world" + + + Verify with: + + x/s 0x20040000 + + + + Why SRAM? + + + SRAM = writable + RAM at 0x20000000 + We can write any + data here via GDB + + + + Flash = read-only + XIP at 0x10000000 + Cannot write to it + during execution + That's why we use RAM + + + + Choosing Address + 0x20040000 is safe + Far from stack + and heap regions + + + + Null terminator + \0 ends the string + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG09.svg b/WEEK02/slides/WEEK02-IMG09.svg new file mode 100644 index 0000000..4cf346e --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG09.svg @@ -0,0 +1,77 @@ + + + + + +Register Hijack +Control Flow Attack + + + + Before Hijack + + + r0 loaded by LDR: + + + r0 = 0x10001234 + + Points to flash: + + + "hello, world\r\n" + + printf will read r0 + and print that string + + + + The Hijack Command + + + set $r0 = 0x20040000 + + Now r0 points to + OUR string in SRAM + instead of flash + + + + After Hijack + + + r0 now contains: + + + r0 = 0x20040000 + + Points to SRAM: + + + "hacky, world" + + + + Then: continue + printf reads r0 + Follows pointer + to 0x20040000 + Finds "hacky, world" + Prints it! + + + + Output changed + without touching code + \ No newline at end of file diff --git a/WEEK02/slides/WEEK02-IMG10.svg b/WEEK02/slides/WEEK02-IMG10.svg new file mode 100644 index 0000000..3582678 --- /dev/null +++ b/WEEK02/slides/WEEK02-IMG10.svg @@ -0,0 +1,75 @@ + + + + + +GDB vs Ghidra +Static vs Dynamic Analysis + + + + GDB (Dynamic) + + + Live analysis + Program is running + on real hardware + + + + Capabilities + Set breakpoints + Read/write memory + Modify registers + Step instructions + Watch values change + + + + Best For + Live modification + Runtime behavior + Testing exploits + Verifying attacks + + Needs running target + + + + Ghidra (Static) + + + Offline analysis + Just the binary file + No hardware needed + + + + Capabilities + Disassembly view + Decompile to C + Find functions + Cross-references + String search + + + + Best For + Planning attacks + Understanding code + Finding targets + Mapping functions + + Works with just ELF + \ No newline at end of file diff --git a/WEEK03/0x0001_hello-world/.gitignore b/WEEK03/0x0001_hello-world/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK03/0x0001_hello-world/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK03/0x0001_hello-world/.vscode/c_cpp_properties.json b/WEEK03/0x0001_hello-world/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK03/0x0001_hello-world/.vscode/cmake-kits.json b/WEEK03/0x0001_hello-world/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK03/0x0001_hello-world/.vscode/extensions.json b/WEEK03/0x0001_hello-world/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK03/0x0001_hello-world/.vscode/launch.json b/WEEK03/0x0001_hello-world/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK03/0x0001_hello-world/.vscode/settings.json b/WEEK03/0x0001_hello-world/.vscode/settings.json new file mode 100644 index 0000000..688748a --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/settings.json @@ -0,0 +1,43 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja", + "files.associations": { + "stdlib.h": "c" + } +} diff --git a/WEEK03/0x0001_hello-world/.vscode/tasks.json b/WEEK03/0x0001_hello-world/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK03/0x0001_hello-world/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK03/0x0001_hello-world/0x0001_hello-world.c b/WEEK03/0x0001_hello-world/0x0001_hello-world.c new file mode 100644 index 0000000..096aba7 --- /dev/null +++ b/WEEK03/0x0001_hello-world/0x0001_hello-world.c @@ -0,0 +1,9 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} diff --git a/WEEK03/0x0001_hello-world/CMakeLists.txt b/WEEK03/0x0001_hello-world/CMakeLists.txt new file mode 100644 index 0000000..31d8fc5 --- /dev/null +++ b/WEEK03/0x0001_hello-world/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0001_hello-world C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0001_hello-world 0x0001_hello-world.c ) + +pico_set_program_name(0x0001_hello-world "0x0001_hello-world") +pico_set_program_version(0x0001_hello-world "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0001_hello-world 1) +pico_enable_stdio_usb(0x0001_hello-world 0) + +# Add the standard library to the build +target_link_libraries(0x0001_hello-world + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0001_hello-world PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0001_hello-world) + diff --git a/WEEK03/0x0001_hello-world/build/0x0001_hello-world.bin b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.bin new file mode 100755 index 0000000..bc1e0ac Binary files /dev/null and b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.bin differ diff --git a/WEEK03/0x0001_hello-world/build/0x0001_hello-world.dis b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.dis new file mode 100644 index 0000000..08dec5d --- /dev/null +++ b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.dis @@ -0,0 +1,2835 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000019cc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 0000014c 100019cc 100019cc 000029cc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10001b18 10001b18 00002b18 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10001b20 10001b20 00002b20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003cfc 2**0 + CONTENTS + 6 .data 0000019c 20000110 10001b4c 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 200002ac 200002ac 00003cfc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 200002ac 200002ac 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 200002b0 10001ce8 000042b0 2**3 + ALLOC + 10 .heap 00000800 200004d8 10001ce8 000044d8 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003cfc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003cfc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001ce8 10001ce8 00003ce8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003cfc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00003d30 2**0 + CONTENTS, READONLY + 17 .debug_info 0002069a 00000000 00000000 00003d75 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 000054ff 00000000 00000000 0002440f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000af0 00000000 00000000 00029910 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 00002f86 00000000 00000000 0002a400 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 0001562d 00000000 00000000 0002d386 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 000056be 00000000 00000000 000429b3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00001ed4 00000000 00000000 00048074 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000ffd1 00000000 00000000 00049f48 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 00000180 00000000 00000000 00059f19 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001_hello-world/build/0x0001_hello-world.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d 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<__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00001bb0 .word 0x00001bb0 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10001b4c .word 0x10001b4c +100001a4: 20000110 .word 0x20000110 +100001a8: 200002ac .word 0x200002ac +100001ac: 10001ce8 .word 0x10001ce8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001ce8 .word 0x10001ce8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 200002ac .word 0x200002ac +100001d4: 200004d8 .word 0x200004d8 +100001d8: 1000137d .word 0x1000137d +100001dc: 10000235 .word 0x10000235 +100001e0: 10001375 .word 0x10001375 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 200002ac .word 0x200002ac +10000208: 200002ac .word 0x200002ac +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000490 .word 0x20000490 +10000230: 100019cc .word 0x100019cc + +10000234
: +10000234: b508 push {r3, lr} +10000236: f001 f999 bl 1000156c +1000023a: 4802 ldr r0, [pc, #8] @ (10000244 ) +1000023c: f001 f9de bl 100015fc <__wrap_puts> +10000240: e7fb b.n 1000023a +10000242: bf00 nop +10000244: 100019cc .word 0x100019cc + +10000248 : +10000248: b410 push {r4} +1000024a: f44f 7480 mov.w r4, #256 @ 0x100 +1000024e: 4b0c ldr r3, [pc, #48] @ (10000280 ) +10000250: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000254: eb03 0380 add.w r3, r3, r0, lsl #2 +10000258: 00c0 lsls r0, r0, #3 +1000025a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000025e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000262: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000266: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000026a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000026e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000272: f8cc 2000 str.w r2, [ip] +10000276: 6041 str r1, [r0, #4] +10000278: 601c str r4, [r3, #0] +1000027a: f85d 4b04 ldr.w r4, [sp], #4 +1000027e: 4770 bx lr +10000280: 40038004 .word 0x40038004 + +10000284 : +10000284: b40f push {r0, r1, r2, r3} +10000286: b500 push {lr} +10000288: b083 sub sp, #12 +1000028a: 9c04 ldr r4, [sp, #16] +1000028c: 4807 ldr r0, [pc, #28] @ (100002ac ) +1000028e: f001 f9b5 bl 100015fc <__wrap_puts> +10000292: b13c cbz r4, 100002a4 +10000294: a905 add r1, sp, #20 +10000296: 4620 mov r0, r4 +10000298: 9101 str r1, [sp, #4] +1000029a: f001 f851 bl 10001340 +1000029e: 4804 ldr r0, [pc, #16] @ (100002b0 ) +100002a0: f001 f9ac bl 100015fc <__wrap_puts> +100002a4: 2001 movs r0, #1 +100002a6: f001 f863 bl 10001370 <_exit> +100002aa: bf00 nop +100002ac: 100019dc .word 0x100019dc +100002b0: 100019ec .word 0x100019ec + +100002b4 : +100002b4: b570 push {r4, r5, r6, lr} +100002b6: 4686 mov lr, r0 +100002b8: f3ef 8510 mrs r5, PRIMASK +100002bc: b672 cpsid i +100002be: 4c12 ldr r4, [pc, #72] @ (10000308 ) +100002c0: e8d4 6fcf ldaexb r6, [r4] +100002c4: 2001 movs r0, #1 +100002c6: 2e00 cmp r6, #0 +100002c8: d1fa bne.n 100002c0 +100002ca: e8c4 0f46 strexb r6, r0, [r4] +100002ce: 2e00 cmp r6, #0 +100002d0: d1f6 bne.n 100002c0 +100002d2: f3bf 8f5f dmb sy +100002d6: f04f 0c01 mov.w ip, #1 +100002da: 08c8 lsrs r0, r1, #3 +100002dc: f001 0307 and.w r3, r1, #7 +100002e0: fa0c f303 lsl.w r3, ip, r3 +100002e4: f81e c000 ldrb.w ip, [lr, r0] +100002e8: ea1c 0603 ands.w r6, ip, r3 +100002ec: d108 bne.n 10000300 +100002ee: ea4c 0c03 orr.w ip, ip, r3 +100002f2: f80e c000 strb.w ip, [lr, r0] +100002f6: e8c4 6f8f stlb r6, [r4] +100002fa: f385 8810 msr PRIMASK, r5 +100002fe: bd70 pop {r4, r5, r6, pc} +10000300: 4610 mov r0, r2 +10000302: f7ff ffbf bl 10000284 +10000306: bf00 nop +10000308: 2000043b .word 0x2000043b + +1000030c : +1000030c: 4a04 ldr r2, [pc, #16] @ (10000320 ) +1000030e: 7810 ldrb r0, [r2, #0] +10000310: 1c43 adds r3, r0, #1 +10000312: b2db uxtb r3, r3 +10000314: 2b18 cmp r3, #24 +10000316: bf28 it cs +10000318: 2310 movcs r3, #16 +1000031a: 7013 strb r3, [r2, #0] +1000031c: 4770 bx lr +1000031e: bf00 nop +10000320: 20000228 .word 0x20000228 + +10000324 : +10000324: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000328: 6893 ldr r3, [r2, #8] +1000032a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000032e: 6093 str r3, [r2, #8] +10000330: 4770 bx lr +10000332: bf00 nop + +10000334 : +10000334: 2100 movs r1, #0 +10000336: 4b04 ldr r3, [pc, #16] @ (10000348 ) +10000338: f103 0220 add.w r2, r3, #32 +1000033c: e8c3 1f8f stlb r1, [r3] +10000340: 3301 adds r3, #1 +10000342: 4293 cmp r3, r2 +10000344: d1fa bne.n 1000033c +10000346: 4770 bx lr +10000348: 20000430 .word 0x20000430 + +1000034c : +1000034c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000350: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000354: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000358: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000035c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000360: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000364: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000368: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000036c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000370: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000374: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000378: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000037c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000380: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000384: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000388: b662 cpsie i +1000038a: 4770 bx lr + +1000038c : +1000038c: 2301 movs r3, #1 +1000038e: f000 021f and.w r2, r0, #31 +10000392: 4093 lsls r3, r2 +10000394: 0940 lsrs r0, r0, #5 +10000396: b141 cbz r1, 100003aa +10000398: 0080 lsls r0, r0, #2 +1000039a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000039e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003a2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003a6: 6003 str r3, [r0, #0] +100003a8: 4770 bx lr +100003aa: 4a02 ldr r2, [pc, #8] @ (100003b4 ) +100003ac: 3020 adds r0, #32 +100003ae: f842 3020 str.w r3, [r2, r0, lsl #2] +100003b2: 4770 bx lr +100003b4: e000e100 .word 0xe000e100 + +100003b8 : +100003b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ba: 460d mov r5, r1 +100003bc: f3ef 8710 mrs r7, PRIMASK +100003c0: b672 cpsid i +100003c2: 4e12 ldr r6, [pc, #72] @ (1000040c ) +100003c4: e8d6 2fcf ldaexb r2, [r6] +100003c8: 2301 movs r3, #1 +100003ca: 2a00 cmp r2, #0 +100003cc: d1fa bne.n 100003c4 +100003ce: e8c6 3f42 strexb r2, r3, [r6] +100003d2: 2a00 cmp r2, #0 +100003d4: d1f6 bne.n 100003c4 +100003d6: f3bf 8f5f dmb sy +100003da: 4b0d ldr r3, [pc, #52] @ (10000410 ) +100003dc: f100 0410 add.w r4, r0, #16 +100003e0: 689b ldr r3, [r3, #8] +100003e2: 4a0c ldr r2, [pc, #48] @ (10000414 ) +100003e4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003e8: 4293 cmp r3, r2 +100003ea: d003 beq.n 100003f4 +100003ec: 4299 cmp r1, r3 +100003ee: d001 beq.n 100003f4 +100003f0: f000 fe8e bl 10001110 +100003f4: 4b06 ldr r3, [pc, #24] @ (10000410 ) +100003f6: 689b ldr r3, [r3, #8] +100003f8: f843 5024 str.w r5, [r3, r4, lsl #2] +100003fc: f3bf 8f5f dmb sy +10000400: 2300 movs r3, #0 +10000402: e8c6 3f8f stlb r3, [r6] +10000406: f387 8810 msr PRIMASK, r7 +1000040a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000040c: 20000439 .word 0x20000439 +10000410: e000ed00 .word 0xe000ed00 +10000414: 10000111 .word 0x10000111 + +10000418 : +10000418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000041c: b083 sub sp, #12 +1000041e: f3ef 8a10 mrs sl, PRIMASK +10000422: b672 cpsid i +10000424: 4e71 ldr r6, [pc, #452] @ (100005ec ) +10000426: e8d6 2fcf ldaexb r2, [r6] +1000042a: 2301 movs r3, #1 +1000042c: 2a00 cmp r2, #0 +1000042e: d1fa bne.n 10000426 +10000430: e8c6 3f42 strexb r2, r3, [r6] +10000434: 2a00 cmp r2, #0 +10000436: d1f6 bne.n 10000426 +10000438: f3bf 8f5f dmb sy +1000043c: 4b6c ldr r3, [pc, #432] @ (100005f0 ) +1000043e: f100 0810 add.w r8, r0, #16 +10000442: 689b ldr r3, [r3, #8] +10000444: 4a6b ldr r2, [pc, #428] @ (100005f4 ) +10000446: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000044a: 4295 cmp r5, r2 +1000044c: d045 beq.n 100004da +1000044e: 428d cmp r5, r1 +10000450: 460c mov r4, r1 +10000452: d050 beq.n 100004f6 +10000454: 4f68 ldr r7, [pc, #416] @ (100005f8 ) +10000456: 1beb subs r3, r5, r7 +10000458: 2b2f cmp r3, #47 @ 0x2f +1000045a: d83e bhi.n 100004da +1000045c: 2101 movs r1, #1 +1000045e: ea4f 1950 mov.w r9, r0, lsr #5 +10000462: ea4f 0989 mov.w r9, r9, lsl #2 +10000466: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000046a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000046e: f000 031f and.w r3, r0, #31 +10000472: fa01 f003 lsl.w r0, r1, r3 +10000476: f8d9 3000 ldr.w r3, [r9] +1000047a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000047e: ea00 0b03 and.w fp, r0, r3 +10000482: f3bf 8f5f dmb sy +10000486: f3ef 8105 mrs r1, IPSR +1000048a: b2c9 uxtb r1, r1 +1000048c: 2900 cmp r1, #0 +1000048e: d034 beq.n 100004fa +10000490: 4588 cmp r8, r1 +10000492: d005 beq.n 100004a0 +10000494: e9cd 1000 strd r1, r0, [sp] +10000498: f000 fe3a bl 10001110 +1000049c: e9dd 1000 ldrd r1, r0, [sp] +100004a0: f025 0e01 bic.w lr, r5, #1 +100004a4: f8de c008 ldr.w ip, [lr, #8] +100004a8: 4564 cmp r4, ip +100004aa: d105 bne.n 100004b8 +100004ac: e089 b.n 100005c2 +100004ae: f8d3 c008 ldr.w ip, [r3, #8] +100004b2: 4564 cmp r4, ip +100004b4: d031 beq.n 1000051a +100004b6: 469e mov lr, r3 +100004b8: f99e 2006 ldrsb.w r2, [lr, #6] +100004bc: eb02 0342 add.w r3, r2, r2, lsl #1 +100004c0: 2a00 cmp r2, #0 +100004c2: eb07 0383 add.w r3, r7, r3, lsl #2 +100004c6: daf2 bge.n 100004ae +100004c8: 4564 cmp r4, ip +100004ca: d061 beq.n 10000590 +100004cc: f1bb 0f00 cmp.w fp, #0 +100004d0: d020 beq.n 10000514 +100004d2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004d6: f8c9 0000 str.w r0, [r9] +100004da: 4b45 ldr r3, [pc, #276] @ (100005f0 ) +100004dc: 689b ldr r3, [r3, #8] +100004de: f843 5028 str.w r5, [r3, r8, lsl #2] +100004e2: f3bf 8f5f dmb sy +100004e6: 2300 movs r3, #0 +100004e8: e8c6 3f8f stlb r3, [r6] +100004ec: f38a 8810 msr PRIMASK, sl +100004f0: b003 add sp, #12 +100004f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100004f6: 4615 mov r5, r2 +100004f8: e7ef b.n 100004da +100004fa: f025 0e01 bic.w lr, r5, #1 +100004fe: f8de c008 ldr.w ip, [lr, #8] +10000502: 4564 cmp r4, ip +10000504: d1d8 bne.n 100004b8 +10000506: f99e 4006 ldrsb.w r4, [lr, #6] +1000050a: 4673 mov r3, lr +1000050c: 2c00 cmp r4, #0 +1000050e: da08 bge.n 10000522 +10000510: 4615 mov r5, r2 +10000512: e046 b.n 100005a2 +10000514: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000518: e7df b.n 100004da +1000051a: f993 4006 ldrsb.w r4, [r3, #6] +1000051e: 2c00 cmp r4, #0 +10000520: db37 blt.n 10000592 +10000522: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000526: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000052a: f89c 1007 ldrb.w r1, [ip, #7] +1000052e: f8dc 2008 ldr.w r2, [ip, #8] +10000532: 71d9 strb r1, [r3, #7] +10000534: 609a str r2, [r3, #8] +10000536: f99c 2006 ldrsb.w r2, [ip, #6] +1000053a: 0061 lsls r1, r4, #1 +1000053c: 2a00 cmp r2, #0 +1000053e: 719a strb r2, [r3, #6] +10000540: db3d blt.n 100005be +10000542: f8bc e004 ldrh.w lr, [ip, #4] +10000546: ea5f 5e4e movs.w lr, lr, lsl #21 +1000054a: d505 bpl.n 10000558 +1000054c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000550: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000554: f10e 0e1f add.w lr, lr, #31 +10000558: f06f 0c07 mvn.w ip, #7 +1000055c: 190a adds r2, r1, r4 +1000055e: ea4f 5e6e mov.w lr, lr, asr #21 +10000562: 0092 lsls r2, r2, #2 +10000564: eb02 024e add.w r2, r2, lr, lsl #1 +10000568: 3208 adds r2, #8 +1000056a: 443a add r2, r7 +1000056c: ebac 0c03 sub.w ip, ip, r3 +10000570: 4462 add r2, ip +10000572: f3c2 024a ubfx r2, r2, #1, #11 +10000576: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000057a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000057e: 809a strh r2, [r3, #4] +10000580: 4b1e ldr r3, [pc, #120] @ (100005fc ) +10000582: 4421 add r1, r4 +10000584: 781a ldrb r2, [r3, #0] +10000586: eb07 0181 add.w r1, r7, r1, lsl #2 +1000058a: 701c strb r4, [r3, #0] +1000058c: 718a strb r2, [r1, #6] +1000058e: e79d b.n 100004cc +10000590: 4673 mov r3, lr +10000592: b9d9 cbnz r1, 100005cc +10000594: 22ff movs r2, #255 @ 0xff +10000596: f88e 2006 strb.w r2, [lr, #6] +1000059a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000059e: f8ae 2004 strh.w r2, [lr, #4] +100005a2: 4c16 ldr r4, [pc, #88] @ (100005fc ) +100005a4: f64a 22aa movw r2, #43690 @ 0xaaaa +100005a8: f894 c000 ldrb.w ip, [r4] +100005ac: 4619 mov r1, r3 +100005ae: 1bc9 subs r1, r1, r7 +100005b0: 4149 adcs r1, r1 +100005b2: 434a muls r2, r1 +100005b4: 0d12 lsrs r2, r2, #20 +100005b6: f883 c006 strb.w ip, [r3, #6] +100005ba: 7022 strb r2, [r4, #0] +100005bc: e786 b.n 100004cc +100005be: 4a10 ldr r2, [pc, #64] @ (10000600 ) +100005c0: e7dd b.n 1000057e +100005c2: f99e 4006 ldrsb.w r4, [lr, #6] +100005c6: 4673 mov r3, lr +100005c8: 2c00 cmp r4, #0 +100005ca: daaa bge.n 10000522 +100005cc: 4a0d ldr r2, [pc, #52] @ (10000604 ) +100005ce: 4c0e ldr r4, [pc, #56] @ (10000608 ) +100005d0: 1ad2 subs r2, r2, r3 +100005d2: 3a08 subs r2, #8 +100005d4: f3c2 310a ubfx r1, r2, #12, #11 +100005d8: ea6f 5101 mvn.w r1, r1, lsl #20 +100005dc: ea6f 5111 mvn.w r1, r1, lsr #20 +100005e0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005e4: 80da strh r2, [r3, #6] +100005e6: 8099 strh r1, [r3, #4] +100005e8: e770 b.n 100004cc +100005ea: bf00 nop +100005ec: 20000439 .word 0x20000439 +100005f0: e000ed00 .word 0xe000ed00 +100005f4: 10000111 .word 0x10000111 +100005f8: 2000022c .word 0x2000022c +100005fc: 200004d4 .word 0x200004d4 +10000600: ffffbd01 .word 0xffffbd01 +10000604: 20000266 .word 0x20000266 +10000608: fffff800 .word 0xfffff800 + +1000060c : +1000060c: b5f0 push {r4, r5, r6, r7, lr} +1000060e: f3ef 8505 mrs r5, IPSR +10000612: b2ed uxtb r5, r5 +10000614: f3ef 8c10 mrs ip, PRIMASK +10000618: b672 cpsid i +1000061a: 4926 ldr r1, [pc, #152] @ (100006b4 ) +1000061c: e8d1 2fcf ldaexb r2, [r1] +10000620: 2301 movs r3, #1 +10000622: 2a00 cmp r2, #0 +10000624: d1fa bne.n 1000061c +10000626: e8c1 3f42 strexb r2, r3, [r1] +1000062a: 2a00 cmp r2, #0 +1000062c: d1f6 bne.n 1000061c +1000062e: f3bf 8f5f dmb sy +10000632: 4e21 ldr r6, [pc, #132] @ (100006b8 ) +10000634: f040 0e01 orr.w lr, r0, #1 +10000638: 68b4 ldr r4, [r6, #8] +1000063a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000063e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000642: 4a1e ldr r2, [pc, #120] @ (100006bc ) +10000644: 4604 mov r4, r0 +10000646: 1aa4 subs r4, r4, r2 +10000648: 4164 adcs r4, r4 +1000064a: 4363 muls r3, r4 +1000064c: 0d1b lsrs r3, r3, #20 +1000064e: 4577 cmp r7, lr +10000650: b25b sxtb r3, r3 +10000652: d01b beq.n 1000068c +10000654: f992 4006 ldrsb.w r4, [r2, #6] +10000658: 429c cmp r4, r3 +1000065a: d01c beq.n 10000696 +1000065c: f992 4012 ldrsb.w r4, [r2, #18] +10000660: 429c cmp r4, r3 +10000662: d023 beq.n 100006ac +10000664: f992 401e ldrsb.w r4, [r2, #30] +10000668: 429c cmp r4, r3 +1000066a: d021 beq.n 100006b0 +1000066c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000670: 429c cmp r4, r3 +10000672: bf08 it eq +10000674: 2403 moveq r4, #3 +10000676: d00f beq.n 10000698 +10000678: 4a11 ldr r2, [pc, #68] @ (100006c0 ) +1000067a: 2400 movs r4, #0 +1000067c: 7815 ldrb r5, [r2, #0] +1000067e: 7013 strb r3, [r2, #0] +10000680: 7185 strb r5, [r0, #6] +10000682: e8c1 4f8f stlb r4, [r1] +10000686: f38c 8810 msr PRIMASK, ip +1000068a: bdf0 pop {r4, r5, r6, r7, pc} +1000068c: 68b2 ldr r2, [r6, #8] +1000068e: 4c0d ldr r4, [pc, #52] @ (100006c4 ) +10000690: f842 4025 str.w r4, [r2, r5, lsl #2] +10000694: e7f0 b.n 10000678 +10000696: 2400 movs r4, #0 +10000698: eb04 0444 add.w r4, r4, r4, lsl #1 +1000069c: eb02 0284 add.w r2, r2, r4, lsl #2 +100006a0: 24ff movs r4, #255 @ 0xff +100006a2: 7194 strb r4, [r2, #6] +100006a4: f64b 5401 movw r4, #48385 @ 0xbd01 +100006a8: 8094 strh r4, [r2, #4] +100006aa: e7e5 b.n 10000678 +100006ac: 2401 movs r4, #1 +100006ae: e7f3 b.n 10000698 +100006b0: 2402 movs r4, #2 +100006b2: e7f1 b.n 10000698 +100006b4: 20000439 .word 0x20000439 +100006b8: e000ed00 .word 0xe000ed00 +100006bc: 2000022c .word 0x2000022c +100006c0: 200004d4 .word 0x200004d4 +100006c4: 10000111 .word 0x10000111 + +100006c8 : +100006c8: 4b01 ldr r3, [pc, #4] @ (100006d0 ) +100006ca: 440b add r3, r1 +100006cc: 6003 str r3, [r0, #0] +100006ce: 4770 bx lr +100006d0: 20000430 .word 0x20000430 + +100006d4 : +100006d4: b570 push {r4, r5, r6, lr} +100006d6: 4c10 ldr r4, [pc, #64] @ (10000718 ) +100006d8: 4d10 ldr r5, [pc, #64] @ (1000071c ) +100006da: 42ac cmp r4, r5 +100006dc: d20e bcs.n 100006fc +100006de: 26ff movs r6, #255 @ 0xff +100006e0: 6823 ldr r3, [r4, #0] +100006e2: b163 cbz r3, 100006fe +100006e4: f7ff fe12 bl 1000030c +100006e8: 4601 mov r1, r0 +100006ea: 4620 mov r0, r4 +100006ec: f7ff ffec bl 100006c8 +100006f0: 80a6 strh r6, [r4, #4] +100006f2: f3bf 8f5f dmb sy +100006f6: 3408 adds r4, #8 +100006f8: 42ac cmp r4, r5 +100006fa: d3f1 bcc.n 100006e0 +100006fc: bd70 pop {r4, r5, r6, pc} +100006fe: f7ff fe05 bl 1000030c +10000702: 4601 mov r1, r0 +10000704: 4620 mov r0, r4 +10000706: f7ff ffdf bl 100006c8 +1000070a: 7126 strb r6, [r4, #4] +1000070c: f3bf 8f5f dmb sy +10000710: 3408 adds r4, #8 +10000712: 42ac cmp r4, r5 +10000714: d3e4 bcc.n 100006e0 +10000716: bd70 pop {r4, r5, r6, pc} +10000718: 200002a4 .word 0x200002a4 +1000071c: 200002ac .word 0x200002ac + +10000720 : +10000720: 4b0d ldr r3, [pc, #52] @ (10000758 ) +10000722: 681a ldr r2, [r3, #0] +10000724: f3ef 8110 mrs r1, PRIMASK +10000728: b672 cpsid i +1000072a: e8d2 cfcf ldaexb ip, [r2] +1000072e: 2001 movs r0, #1 +10000730: f1bc 0f00 cmp.w ip, #0 +10000734: d1f9 bne.n 1000072a +10000736: e8c2 0f4c strexb ip, r0, [r2] +1000073a: f1bc 0f00 cmp.w ip, #0 +1000073e: d1f4 bne.n 1000072a +10000740: f3bf 8f5f dmb sy +10000744: 2200 movs r2, #0 +10000746: 681b ldr r3, [r3, #0] +10000748: e8c3 2f8f stlb r2, [r3] +1000074c: f381 8810 msr PRIMASK, r1 +10000750: bf40 sev +10000752: 2000 movs r0, #0 +10000754: 2100 movs r1, #0 +10000756: 4770 bx lr +10000758: 200004c8 .word 0x200004c8 +1000075c: 00000000 .word 0x00000000 + +10000760 : +10000760: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000764: ed2d 8b02 vpush {d8} +10000768: b085 sub sp, #20 +1000076a: f3ef 8305 mrs r3, IPSR +1000076e: b2db uxtb r3, r3 +10000770: 3b10 subs r3, #16 +10000772: 089a lsrs r2, r3, #2 +10000774: bf18 it ne +10000776: 2201 movne r2, #1 +10000778: f04f 0101 mov.w r1, #1 +1000077c: f003 0b03 and.w fp, r3, #3 +10000780: bf18 it ne +10000782: 4daf ldrne r5, [pc, #700] @ (10000a40 ) +10000784: 4baf ldr r3, [pc, #700] @ (10000a44 ) +10000786: bf08 it eq +10000788: 4daf ldreq r5, [pc, #700] @ (10000a48 ) +1000078a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000078e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000792: fa01 f20b lsl.w r2, r1, fp +10000796: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000079a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a38 +1000079e: 9201 str r2, [sp, #4] +100007a0: 605a str r2, [r3, #4] +100007a2: e02f b.n 10000804 +100007a4: 88b3 ldrh r3, [r6, #4] +100007a6: 041c lsls r4, r3, #16 +100007a8: f140 8093 bpl.w 100008d2 +100007ac: 79b3 ldrb r3, [r6, #6] +100007ae: 2b00 cmp r3, #0 +100007b0: f040 80dd bne.w 1000096e +100007b4: f9b6 2008 ldrsh.w r2, [r6, #8] +100007b8: 2a00 cmp r2, #0 +100007ba: f2c0 811e blt.w 100009fa +100007be: 6973 ldr r3, [r6, #20] +100007c0: eb02 0242 add.w r2, r2, r2, lsl #1 +100007c4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007c8: e9d3 4702 ldrd r4, r7, [r3, #8] +100007cc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007d0: bf08 it eq +100007d2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007d6: d00e beq.n 100007f6 +100007d8: eb05 018b add.w r1, r5, fp, lsl #2 +100007dc: 6aab ldr r3, [r5, #40] @ 0x28 +100007de: 690a ldr r2, [r1, #16] +100007e0: 1ad2 subs r2, r2, r3 +100007e2: 1ae3 subs r3, r4, r3 +100007e4: 4293 cmp r3, r2 +100007e6: d305 bcc.n 100007f4 +100007e8: 2301 movs r3, #1 +100007ea: 6a2a ldr r2, [r5, #32] +100007ec: fa03 f30b lsl.w r3, r3, fp +100007f0: 4213 tst r3, r2 +100007f2: d100 bne.n 100007f6 +100007f4: 610c str r4, [r1, #16] +100007f6: 4628 mov r0, r5 +100007f8: f000 faca bl 10000d90 +100007fc: 42a0 cmp r0, r4 +100007fe: 41b9 sbcs r1, r7 +10000800: f2c0 80fb blt.w 100009fa +10000804: f9b6 3008 ldrsh.w r3, [r6, #8] +10000808: 9a01 ldr r2, [sp, #4] +1000080a: 2b00 cmp r3, #0 +1000080c: 9300 str r3, [sp, #0] +1000080e: 63ea str r2, [r5, #60] @ 0x3c +10000810: dbc8 blt.n 100007a4 +10000812: f8d6 8014 ldr.w r8, [r6, #20] +10000816: eb03 0943 add.w r9, r3, r3, lsl #1 +1000081a: 4628 mov r0, r5 +1000081c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000820: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000824: f000 fab4 bl 10000d90 +10000828: 42a0 cmp r0, r4 +1000082a: eb71 010a sbcs.w r1, r1, sl +1000082e: dbb9 blt.n 100007a4 +10000830: f1ba 0f00 cmp.w sl, #0 +10000834: f2c0 80c3 blt.w 100009be +10000838: e9d7 3104 ldrd r3, r1, [r7, #16] +1000083c: 4a83 ldr r2, [pc, #524] @ (10000a4c ) +1000083e: 4293 cmp r3, r2 +10000840: f000 80ed beq.w 10000a1e +10000844: 887a ldrh r2, [r7, #2] +10000846: f9b6 0008 ldrsh.w r0, [r6, #8] +1000084a: b292 uxth r2, r2 +1000084c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000850: 4798 blx r3 +10000852: 4602 mov r2, r0 +10000854: 460b mov r3, r1 +10000856: ea52 0103 orrs.w r1, r2, r3 +1000085a: f000 80b0 beq.w 100009be +1000085e: 2b00 cmp r3, #0 +10000860: f280 80d1 bge.w 10000a06 +10000864: ebb4 0e02 subs.w lr, r4, r2 +10000868: eb6a 0a03 sbc.w sl, sl, r3 +1000086c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000870: e9c7 ea02 strd lr, sl, [r7, #8] +10000874: 2b00 cmp r3, #0 +10000876: db95 blt.n 100007a4 +10000878: 6971 ldr r1, [r6, #20] +1000087a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000087e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000882: e9d2 7002 ldrd r7, r0, [r2, #8] +10000886: 45be cmp lr, r7 +10000888: eb7a 0c00 sbcs.w ip, sl, r0 +1000088c: ea4f 0243 mov.w r2, r3, lsl #1 +10000890: db88 blt.n 100007a4 +10000892: 46b4 mov ip, r6 +10000894: f82c 3f08 strh.w r3, [ip, #8]! +10000898: e006 b.n 100008a8 +1000089a: eb03 0043 add.w r0, r3, r3, lsl #1 +1000089e: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008a2: 005a lsls r2, r3, #1 +100008a4: e9d0 7002 ldrd r7, r0, [r0, #8] +100008a8: 45be cmp lr, r7 +100008aa: 441a add r2, r3 +100008ac: eb7a 0000 sbcs.w r0, sl, r0 +100008b0: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008b4: db04 blt.n 100008c0 +100008b6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008ba: 46a4 mov ip, r4 +100008bc: 2b00 cmp r3, #0 +100008be: daec bge.n 1000089a +100008c0: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008c4: 9b00 ldr r3, [sp, #0] +100008c6: f8ac 3000 strh.w r3, [ip] +100008ca: 88b3 ldrh r3, [r6, #4] +100008cc: 041c lsls r4, r3, #16 +100008ce: f53f af6d bmi.w 100007ac +100008d2: 6933 ldr r3, [r6, #16] +100008d4: f3ef 8210 mrs r2, PRIMASK +100008d8: b672 cpsid i +100008da: e8d3 0fcf ldaexb r0, [r3] +100008de: 2101 movs r1, #1 +100008e0: 2800 cmp r0, #0 +100008e2: d1fa bne.n 100008da +100008e4: e8c3 1f40 strexb r0, r1, [r3] +100008e8: 2800 cmp r0, #0 +100008ea: d1f6 bne.n 100008da +100008ec: f3bf 8f5f dmb sy +100008f0: f64f 74ff movw r4, #65535 @ 0xffff +100008f4: 88b0 ldrh r0, [r6, #4] +100008f6: 2300 movs r3, #0 +100008f8: 6931 ldr r1, [r6, #16] +100008fa: b200 sxth r0, r0 +100008fc: 80b4 strh r4, [r6, #4] +100008fe: e8c1 3f8f stlb r3, [r1] +10000902: f382 8810 msr PRIMASK, r2 +10000906: 4298 cmp r0, r3 +10000908: f6ff af50 blt.w 100007ac +1000090c: 4607 mov r7, r0 +1000090e: 46a9 mov r9, r5 +10000910: 6974 ldr r4, [r6, #20] +10000912: f106 0808 add.w r8, r6, #8 +10000916: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000091a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000091e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000922: f9b6 3008 ldrsh.w r3, [r6, #8] +10000926: 46c4 mov ip, r8 +10000928: 2b00 cmp r3, #0 +1000092a: db13 blt.n 10000954 +1000092c: 46b2 mov sl, r6 +1000092e: 9700 str r7, [sp, #0] +10000930: e004 b.n 1000093c +10000932: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000936: 4694 mov ip, r2 +10000938: 2b00 cmp r3, #0 +1000093a: db09 blt.n 10000950 +1000093c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000940: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000944: e9d2 7102 ldrd r7, r1, [r2, #8] +10000948: 42bd cmp r5, r7 +1000094a: eb70 0101 sbcs.w r1, r0, r1 +1000094e: daf0 bge.n 10000932 +10000950: 4656 mov r6, sl +10000952: 9f00 ldr r7, [sp, #0] +10000954: f8ac 7000 strh.w r7, [ip] +10000958: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000095c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000960: 2f00 cmp r7, #0 +10000962: dad8 bge.n 10000916 +10000964: 79b3 ldrb r3, [r6, #6] +10000966: 464d mov r5, r9 +10000968: 2b00 cmp r3, #0 +1000096a: f43f af23 beq.w 100007b4 +1000096e: 2300 movs r3, #0 +10000970: 71b3 strb r3, [r6, #6] +10000972: f9b6 3008 ldrsh.w r3, [r6, #8] +10000976: f106 0808 add.w r8, r6, #8 +1000097a: 1c58 adds r0, r3, #1 +1000097c: d03d beq.n 100009fa +1000097e: 461a mov r2, r3 +10000980: 6977 ldr r7, [r6, #20] +10000982: e003 b.n 1000098c +10000984: 4680 mov r8, r0 +10000986: 1c59 adds r1, r3, #1 +10000988: f43f af16 beq.w 100007b8 +1000098c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000990: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000994: f8b0 c002 ldrh.w ip, [r0, #2] +10000998: 461c mov r4, r3 +1000099a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +1000099e: 469e mov lr, r3 +100009a0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009a4: d0ee beq.n 10000984 +100009a6: 4294 cmp r4, r2 +100009a8: ed80 8b02 vstr d8, [r0, #8] +100009ac: d005 beq.n 100009ba +100009ae: f8a8 3000 strh.w r3, [r8] +100009b2: 8932 ldrh r2, [r6, #8] +100009b4: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009b8: 8134 strh r4, [r6, #8] +100009ba: 4672 mov r2, lr +100009bc: e7e3 b.n 10000986 +100009be: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009c2: 8133 strh r3, [r6, #8] +100009c4: 6933 ldr r3, [r6, #16] +100009c6: f3ef 8210 mrs r2, PRIMASK +100009ca: b672 cpsid i +100009cc: e8d3 0fcf ldaexb r0, [r3] +100009d0: 2101 movs r1, #1 +100009d2: 2800 cmp r0, #0 +100009d4: d1fa bne.n 100009cc +100009d6: e8c3 1f40 strexb r0, r1, [r3] +100009da: 2800 cmp r0, #0 +100009dc: d1f6 bne.n 100009cc +100009de: f3bf 8f5f dmb sy +100009e2: 8873 ldrh r3, [r6, #2] +100009e4: 6931 ldr r1, [r6, #16] +100009e6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009ea: 9b00 ldr r3, [sp, #0] +100009ec: 8073 strh r3, [r6, #2] +100009ee: 2300 movs r3, #0 +100009f0: e8c1 3f8f stlb r3, [r1] +100009f4: f382 8810 msr PRIMASK, r2 +100009f8: e6d4 b.n 100007a4 +100009fa: bf40 sev +100009fc: b005 add sp, #20 +100009fe: ecbd 8b02 vpop {d8} +10000a02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a06: 4628 mov r0, r5 +10000a08: e9cd 2302 strd r2, r3, [sp, #8] +10000a0c: f000 f9c0 bl 10000d90 +10000a10: 9a02 ldr r2, [sp, #8] +10000a12: 9b03 ldr r3, [sp, #12] +10000a14: eb10 0e02 adds.w lr, r0, r2 +10000a18: eb43 0a01 adc.w sl, r3, r1 +10000a1c: e726 b.n 1000086c +10000a1e: 4608 mov r0, r1 +10000a20: 690b ldr r3, [r1, #16] +10000a22: 9102 str r1, [sp, #8] +10000a24: 4798 blx r3 +10000a26: 2800 cmp r0, #0 +10000a28: d0c9 beq.n 100009be +10000a2a: 9902 ldr r1, [sp, #8] +10000a2c: e9d1 2300 ldrd r2, r3, [r1] +10000a30: e711 b.n 10000856 +10000a32: bf00 nop +10000a34: f3af 8000 nop.w +10000a38: ffffffff .word 0xffffffff +10000a3c: ffffffff .word 0xffffffff +10000a40: 400b8000 .word 0x400b8000 +10000a44: 200004a8 .word 0x200004a8 +10000a48: 400b0000 .word 0x400b0000 +10000a4c: 10000761 .word 0x10000761 + +10000a50 : +10000a50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a54: 4c36 ldr r4, [pc, #216] @ (10000b30 ) +10000a56: 6925 ldr r5, [r4, #16] +10000a58: b12d cbz r5, 10000a66 +10000a5a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a5e: 210a movs r1, #10 +10000a60: 4834 ldr r0, [pc, #208] @ (10000b34 ) +10000a62: f7ff be31 b.w 100006c8 +10000a66: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b4c +10000a6a: 2103 movs r1, #3 +10000a6c: 4640 mov r0, r8 +10000a6e: f000 f97d bl 10000d6c +10000a72: 2603 movs r6, #3 +10000a74: f8c4 800c str.w r8, [r4, #12] +10000a78: f7ff fc48 bl 1000030c +10000a7c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a80: 4b2d ldr r3, [pc, #180] @ (10000b38 ) +10000a82: 7026 strb r6, [r4, #0] +10000a84: 4403 add r3, r0 +10000a86: 6123 str r3, [r4, #16] +10000a88: f8dc 3000 ldr.w r3, [ip] +10000a8c: 210f movs r1, #15 +10000a8e: 7063 strb r3, [r4, #1] +10000a90: 6963 ldr r3, [r4, #20] +10000a92: 8061 strh r1, [r4, #2] +10000a94: 831d strh r5, [r3, #24] +10000a96: f04f 0504 mov.w r5, #4 +10000a9a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000a9e: f04f 0505 mov.w r5, #5 +10000aa2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000aa6: f04f 0506 mov.w r5, #6 +10000aaa: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000aae: f04f 0507 mov.w r5, #7 +10000ab2: 210e movs r1, #14 +10000ab4: f64f 72ff movw r2, #65535 @ 0xffff +10000ab8: 2708 movs r7, #8 +10000aba: f04f 0e0a mov.w lr, #10 +10000abe: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000ac2: f04f 0901 mov.w r9, #1 +10000ac6: f04f 0c0c mov.w ip, #12 +10000aca: f04f 0b02 mov.w fp, #2 +10000ace: f04f 0a09 mov.w sl, #9 +10000ad2: 200d movs r0, #13 +10000ad4: f04f 050b mov.w r5, #11 +10000ad8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000adc: 4917 ldr r1, [pc, #92] @ (10000b3c ) +10000ade: 80a2 strh r2, [r4, #4] +10000ae0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000ae4: 60a1 str r1, [r4, #8] +10000ae6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000aea: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000aee: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000af2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000af6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000afa: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000afe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b02: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b06: 801a strh r2, [r3, #0] +10000b08: 4b0d ldr r3, [pc, #52] @ (10000b40 ) +10000b0a: 4630 mov r0, r6 +10000b0c: f8c8 7020 str.w r7, [r8, #32] +10000b10: 490c ldr r1, [pc, #48] @ (10000b44 ) +10000b12: 60dc str r4, [r3, #12] +10000b14: f7ff fc50 bl 100003b8 +10000b18: 4649 mov r1, r9 +10000b1a: 4630 mov r0, r6 +10000b1c: f7ff fc36 bl 1000038c +10000b20: 4b09 ldr r3, [pc, #36] @ (10000b48 ) +10000b22: 210a movs r1, #10 +10000b24: 641f str r7, [r3, #64] @ 0x40 +10000b26: 4803 ldr r0, [pc, #12] @ (10000b34 ) +10000b28: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b2c: f7ff bdcc b.w 100006c8 +10000b30: 20000274 .word 0x20000274 +10000b34: 200004c8 .word 0x200004c8 +10000b38: 20000430 .word 0x20000430 +10000b3c: 0010ffff .word 0x0010ffff +10000b40: 200004a8 .word 0x200004a8 +10000b44: 10000761 .word 0x10000761 +10000b48: 400b2000 .word 0x400b2000 +10000b4c: 400b0000 .word 0x400b0000 + +10000b50 : +10000b50: 4601 mov r1, r0 +10000b52: b5f0 push {r4, r5, r6, r7, lr} +10000b54: 6900 ldr r0, [r0, #16] +10000b56: f3ef 8710 mrs r7, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d0 5fcf ldaexb r5, [r0] +10000b60: 2401 movs r4, #1 +10000b62: 2d00 cmp r5, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c0 4f45 strexb r5, r4, [r0] +10000b6a: 2d00 cmp r5, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b76: 694c ldr r4, [r1, #20] +10000b78: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b7c: f1be 0f00 cmp.w lr, #0 +10000b80: ea4f 05cc mov.w r5, ip, lsl #3 +10000b84: 6908 ldr r0, [r1, #16] +10000b86: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b8a: db3c blt.n 10000c06 +10000b8c: 5b66 ldrh r6, [r4, r5] +10000b8e: 804e strh r6, [r1, #2] +10000b90: 2600 movs r6, #0 +10000b92: e8c0 6f8f stlb r6, [r0] +10000b96: f387 8810 msr PRIMASK, r7 +10000b9a: f8bc 0002 ldrh.w r0, [ip, #2] +10000b9e: e9cc 2302 strd r2, r3, [ip, #8] +10000ba2: 3001 adds r0, #1 +10000ba4: f3c0 000e ubfx r0, r0, #0, #15 +10000ba8: 2801 cmp r0, #1 +10000baa: bf38 it cc +10000bac: 2001 movcc r0, #1 +10000bae: 9b05 ldr r3, [sp, #20] +10000bb0: f8ac 0002 strh.w r0, [ip, #2] +10000bb4: f8cc 3010 str.w r3, [ip, #16] +10000bb8: 9b06 ldr r3, [sp, #24] +10000bba: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bbe: f8cc 3014 str.w r3, [ip, #20] +10000bc2: 690b ldr r3, [r1, #16] +10000bc4: f3ef 8210 mrs r2, PRIMASK +10000bc8: b672 cpsid i +10000bca: e8d3 cfcf ldaexb ip, [r3] +10000bce: 2701 movs r7, #1 +10000bd0: f1bc 0f00 cmp.w ip, #0 +10000bd4: d1f9 bne.n 10000bca +10000bd6: e8c3 7f4c strexb ip, r7, [r3] +10000bda: f1bc 0f00 cmp.w ip, #0 +10000bde: d1f4 bne.n 10000bca +10000be0: f3bf 8f5f dmb sy +10000be4: 888b ldrh r3, [r1, #4] +10000be6: 5363 strh r3, [r4, r5] +10000be8: f8a1 e004 strh.w lr, [r1, #4] +10000bec: 690b ldr r3, [r1, #16] +10000bee: e8c3 6f8f stlb r6, [r3] +10000bf2: f382 8810 msr PRIMASK, r2 +10000bf6: 2201 movs r2, #1 +10000bf8: 68cb ldr r3, [r1, #12] +10000bfa: 7809 ldrb r1, [r1, #0] +10000bfc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c00: 408a lsls r2, r1 +10000c02: 605a str r2, [r3, #4] +10000c04: bdf0 pop {r4, r5, r6, r7, pc} +10000c06: 2300 movs r3, #0 +10000c08: e8c0 3f8f stlb r3, [r0] +10000c0c: f387 8810 msr PRIMASK, r7 +10000c10: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c14: bdf0 pop {r4, r5, r6, r7, pc} +10000c16: bf00 nop + +10000c18 : +10000c18: 4603 mov r3, r0 +10000c1a: 8940 ldrh r0, [r0, #10] +10000c1c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c20: dd37 ble.n 10000c92 +10000c22: 6958 ldr r0, [r3, #20] +10000c24: 140a asrs r2, r1, #16 +10000c26: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c2a: b510 push {r4, lr} +10000c2c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c30: 691c ldr r4, [r3, #16] +10000c32: f3ef 8c10 mrs ip, PRIMASK +10000c36: b672 cpsid i +10000c38: e8d4 efcf ldaexb lr, [r4] +10000c3c: 2201 movs r2, #1 +10000c3e: f1be 0f00 cmp.w lr, #0 +10000c42: d1f9 bne.n 10000c38 +10000c44: e8c4 2f4e strexb lr, r2, [r4] +10000c48: f1be 0f00 cmp.w lr, #0 +10000c4c: d1f4 bne.n 10000c38 +10000c4e: f3bf 8f5f dmb sy +10000c52: 8842 ldrh r2, [r0, #2] +10000c54: b289 uxth r1, r1 +10000c56: b292 uxth r2, r2 +10000c58: 428a cmp r2, r1 +10000c5a: d007 beq.n 10000c6c +10000c5c: 2200 movs r2, #0 +10000c5e: 691b ldr r3, [r3, #16] +10000c60: e8c3 2f8f stlb r2, [r3] +10000c64: f38c 8810 msr PRIMASK, ip +10000c68: 2000 movs r0, #0 +10000c6a: bd10 pop {r4, pc} +10000c6c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c70: 8042 strh r2, [r0, #2] +10000c72: 2101 movs r1, #1 +10000c74: 2200 movs r2, #0 +10000c76: 6918 ldr r0, [r3, #16] +10000c78: 7199 strb r1, [r3, #6] +10000c7a: e8c0 2f8f stlb r2, [r0] +10000c7e: f38c 8810 msr PRIMASK, ip +10000c82: 781c ldrb r4, [r3, #0] +10000c84: 68da ldr r2, [r3, #12] +10000c86: 4608 mov r0, r1 +10000c88: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c8c: 40a1 lsls r1, r4 +10000c8e: 6059 str r1, [r3, #4] +10000c90: bd10 pop {r4, pc} +10000c92: 2000 movs r0, #0 +10000c94: 4770 bx lr +10000c96: bf00 nop + +10000c98 : +10000c98: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000c9c: 4606 mov r6, r0 +10000c9e: 460d mov r5, r1 +10000ca0: b083 sub sp, #12 +10000ca2: f3ef 8405 mrs r4, IPSR +10000ca6: b2e4 uxtb r4, r4 +10000ca8: b13c cbz r4, 10000cba +10000caa: 4b2d ldr r3, [pc, #180] @ (10000d60 ) +10000cac: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cae: 42aa cmp r2, r5 +10000cb0: d21c bcs.n 10000cec +10000cb2: 2000 movs r0, #0 +10000cb4: b003 add sp, #12 +10000cb6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cba: 4f2a ldr r7, [pc, #168] @ (10000d64 ) +10000cbc: f8d7 900c ldr.w r9, [r7, #12] +10000cc0: f897 8000 ldrb.w r8, [r7] +10000cc4: 4648 mov r0, r9 +10000cc6: f000 f863 bl 10000d90 +10000cca: f108 0804 add.w r8, r8, #4 +10000cce: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000cd2: 1a1b subs r3, r3, r0 +10000cd4: 1a30 subs r0, r6, r0 +10000cd6: eb65 0101 sbc.w r1, r5, r1 +10000cda: 4298 cmp r0, r3 +10000cdc: f171 0100 sbcs.w r1, r1, #0 +10000ce0: db10 blt.n 10000d04 +10000ce2: bf20 wfe +10000ce4: 4b1e ldr r3, [pc, #120] @ (10000d60 ) +10000ce6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ce8: 42aa cmp r2, r5 +10000cea: d3e2 bcc.n 10000cb2 +10000cec: bf14 ite ne +10000cee: 2401 movne r4, #1 +10000cf0: 2400 moveq r4, #0 +10000cf2: 6a9b ldr r3, [r3, #40] @ 0x28 +10000cf4: 42b3 cmp r3, r6 +10000cf6: bf34 ite cc +10000cf8: 4620 movcc r0, r4 +10000cfa: f044 0001 orrcs.w r0, r4, #1 +10000cfe: b003 add sp, #12 +10000d00: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d04: f000 f84c bl 10000da0 +10000d08: 4286 cmp r6, r0 +10000d0a: eb65 0101 sbc.w r1, r5, r1 +10000d0e: 2900 cmp r1, #0 +10000d10: db14 blt.n 10000d3c +10000d12: 4b15 ldr r3, [pc, #84] @ (10000d68 ) +10000d14: 4638 mov r0, r7 +10000d16: e9cd 3400 strd r3, r4, [sp] +10000d1a: 4632 mov r2, r6 +10000d1c: 462b mov r3, r5 +10000d1e: f7ff ff17 bl 10000b50 +10000d22: 1e01 subs r1, r0, #0 +10000d24: dd0a ble.n 10000d3c +10000d26: 4b0e ldr r3, [pc, #56] @ (10000d60 ) +10000d28: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d2a: 42aa cmp r2, r5 +10000d2c: d316 bcc.n 10000d5c +10000d2e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d30: 42b3 cmp r3, r6 +10000d32: d311 bcc.n 10000d58 +10000d34: 480b ldr r0, [pc, #44] @ (10000d64 ) +10000d36: f7ff ff6f bl 10000c18 +10000d3a: e7b6 b.n 10000caa +10000d3c: 4b08 ldr r3, [pc, #32] @ (10000d60 ) +10000d3e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d40: 42ac cmp r4, r5 +10000d42: d3b6 bcc.n 10000cb2 +10000d44: 1b64 subs r4, r4, r5 +10000d46: bf18 it ne +10000d48: 2401 movne r4, #1 +10000d4a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d4c: 42b3 cmp r3, r6 +10000d4e: bf34 ite cc +10000d50: 4620 movcc r0, r4 +10000d52: f044 0001 orrcs.w r0, r4, #1 +10000d56: e7ad b.n 10000cb4 +10000d58: 42aa cmp r2, r5 +10000d5a: d1eb bne.n 10000d34 +10000d5c: bf20 wfe +10000d5e: e7e9 b.n 10000d34 +10000d60: 400b0000 .word 0x400b0000 +10000d64: 20000274 .word 0x20000274 +10000d68: 10000721 .word 0x10000721 + +10000d6c : +10000d6c: b410 push {r4} +10000d6e: 4b05 ldr r3, [pc, #20] @ (10000d84 ) +10000d70: 4c05 ldr r4, [pc, #20] @ (10000d88 ) +10000d72: 4a06 ldr r2, [pc, #24] @ (10000d8c ) +10000d74: 42a0 cmp r0, r4 +10000d76: bf14 ite ne +10000d78: 4618 movne r0, r3 +10000d7a: 1c58 addeq r0, r3, #1 +10000d7c: f85d 4b04 ldr.w r4, [sp], #4 +10000d80: f7ff ba98 b.w 100002b4 +10000d84: 20000458 .word 0x20000458 +10000d88: 400b8000 .word 0x400b8000 +10000d8c: 100019f0 .word 0x100019f0 + +10000d90 : +10000d90: 4603 mov r3, r0 +10000d92: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d94: 460a mov r2, r1 +10000d96: 6a98 ldr r0, [r3, #40] @ 0x28 +10000d98: 6a59 ldr r1, [r3, #36] @ 0x24 +10000d9a: 428a cmp r2, r1 +10000d9c: d1fa bne.n 10000d94 +10000d9e: 4770 bx lr + +10000da0 : +10000da0: 4b03 ldr r3, [pc, #12] @ (10000db0 ) +10000da2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 4291 cmp r1, r2 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr +10000db0: 400b0000 .word 0x400b0000 + +10000db4 : +10000db4: b430 push {r4, r5} +10000db6: 4a15 ldr r2, [pc, #84] @ (10000e0c ) +10000db8: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dba: 469c mov ip, r3 +10000dbc: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dbe: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc0: 4563 cmp r3, ip +10000dc2: d1fa bne.n 10000dba +10000dc4: 1902 adds r2, r0, r4 +10000dc6: 4159 adcs r1, r3 +10000dc8: f04f 0500 mov.w r5, #0 +10000dcc: bf28 it cs +10000dce: 2501 movcs r5, #1 +10000dd0: 4b0e ldr r3, [pc, #56] @ (10000e0c ) +10000dd2: 6a5b ldr r3, [r3, #36] @ 0x24 +10000dd4: b1b5 cbz r5, 10000e04 +10000dd6: 1c5a adds r2, r3, #1 +10000dd8: bf08 it eq +10000dda: 461a moveq r2, r3 +10000ddc: d008 beq.n 10000df0 +10000dde: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000de2: 460a mov r2, r1 +10000de4: 4809 ldr r0, [pc, #36] @ (10000e0c ) +10000de6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000de8: 428b cmp r3, r1 +10000dea: d3fc bcc.n 10000de6 +10000dec: 428b cmp r3, r1 +10000dee: d107 bne.n 10000e00 +10000df0: 4906 ldr r1, [pc, #24] @ (10000e0c ) +10000df2: e002 b.n 10000dfa +10000df4: 6a48 ldr r0, [r1, #36] @ 0x24 +10000df6: 4298 cmp r0, r3 +10000df8: d102 bne.n 10000e00 +10000dfa: 6a88 ldr r0, [r1, #40] @ 0x28 +10000dfc: 4290 cmp r0, r2 +10000dfe: d3f9 bcc.n 10000df4 +10000e00: bc30 pop {r4, r5} +10000e02: 4770 bx lr +10000e04: 4299 cmp r1, r3 +10000e06: d8ed bhi.n 10000de4 +10000e08: e7f0 b.n 10000dec +10000e0a: bf00 nop +10000e0c: 400b0000 .word 0x400b0000 + +10000e10 : +10000e10: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e12: 4605 mov r5, r0 +10000e14: 2006 movs r0, #6 +10000e16: 460e mov r6, r1 +10000e18: f000 f8e4 bl 10000fe4 +10000e1c: 2800 cmp r0, #0 +10000e1e: d042 beq.n 10000ea6 +10000e20: 4a35 ldr r2, [pc, #212] @ (10000ef8 ) +10000e22: 4836 ldr r0, [pc, #216] @ (10000efc ) +10000e24: 4295 cmp r5, r2 +10000e26: bf14 ite ne +10000e28: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e2c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e30: 4b33 ldr r3, [pc, #204] @ (10000f00 ) +10000e32: 4934 ldr r1, [pc, #208] @ (10000f04 ) +10000e34: 6002 str r2, [r0, #0] +10000e36: 601a str r2, [r3, #0] +10000e38: 688c ldr r4, [r1, #8] +10000e3a: ea32 0404 bics.w r4, r2, r4 +10000e3e: d1fb bne.n 10000e38 +10000e40: 4b2d ldr r3, [pc, #180] @ (10000ef8 ) +10000e42: f44f 7180 mov.w r1, #256 @ 0x100 +10000e46: 1aeb subs r3, r5, r3 +10000e48: fab3 f383 clz r3, r3 +10000e4c: 4a2e ldr r2, [pc, #184] @ (10000f08 ) +10000e4e: 095b lsrs r3, r3, #5 +10000e50: 2006 movs r0, #6 +10000e52: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e56: f000 f8c5 bl 10000fe4 +10000e5a: 00c3 lsls r3, r0, #3 +10000e5c: fbb3 f3f6 udiv r3, r3, r6 +10000e60: 3301 adds r3, #1 +10000e62: 09da lsrs r2, r3, #7 +10000e64: d120 bne.n 10000ea8 +10000e66: 2640 movs r6, #64 @ 0x40 +10000e68: 2101 movs r1, #1 +10000e6a: 6269 str r1, [r5, #36] @ 0x24 +10000e6c: 62aa str r2, [r5, #40] @ 0x28 +10000e6e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e70: 07fb lsls r3, r7, #31 +10000e72: d422 bmi.n 10000eba +10000e74: 462b mov r3, r5 +10000e76: 2200 movs r2, #0 +10000e78: f853 1f2c ldr.w r1, [r3, #44]! +10000e7c: 2006 movs r0, #6 +10000e7e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e82: 6022 str r2, [r4, #0] +10000e84: 632f str r7, [r5, #48] @ 0x30 +10000e86: f000 f8ad bl 10000fe4 +10000e8a: f240 3101 movw r1, #769 @ 0x301 +10000e8e: 2203 movs r2, #3 +10000e90: 0080 lsls r0, r0, #2 +10000e92: fbb0 f0f6 udiv r0, r0, r6 +10000e96: 6aeb ldr r3, [r5, #44] @ 0x2c +10000e98: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000e9c: f003 037e and.w r3, r3, #126 @ 0x7e +10000ea0: 6023 str r3, [r4, #0] +10000ea2: 6329 str r1, [r5, #48] @ 0x30 +10000ea4: 64aa str r2, [r5, #72] @ 0x48 +10000ea6: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000ea8: f64f 71fe movw r1, #65534 @ 0xfffe +10000eac: 428a cmp r2, r1 +10000eae: d91b bls.n 10000ee8 +10000eb0: 4622 mov r2, r4 +10000eb2: f64f 71ff movw r1, #65535 @ 0xffff +10000eb6: 4e15 ldr r6, [pc, #84] @ (10000f0c ) +10000eb8: e7d7 b.n 10000e6a +10000eba: f240 3201 movw r2, #769 @ 0x301 +10000ebe: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000ec2: 631a str r2, [r3, #48] @ 0x30 +10000ec4: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ec6: 6aac ldr r4, [r5, #40] @ 0x28 +10000ec8: 2006 movs r0, #6 +10000eca: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ece: f000 f889 bl 10000fe4 +10000ed2: 4b0f ldr r3, [pc, #60] @ (10000f10 ) +10000ed4: 02a4 lsls r4, r4, #10 +10000ed6: fba3 2300 umull r2, r3, r3, r0 +10000eda: 0adb lsrs r3, r3, #11 +10000edc: 2100 movs r1, #0 +10000ede: fbb4 f0f3 udiv r0, r4, r3 +10000ee2: f7ff ff67 bl 10000db4 +10000ee6: e7c5 b.n 10000e74 +10000ee8: f3c3 0345 ubfx r3, r3, #1, #6 +10000eec: 4611 mov r1, r2 +10000eee: eb03 1682 add.w r6, r3, r2, lsl #6 +10000ef2: 461a mov r2, r3 +10000ef4: e7b9 b.n 10000e6a +10000ef6: bf00 nop +10000ef8: 40078000 .word 0x40078000 +10000efc: 40022000 .word 0x40022000 +10000f00: 40023000 .word 0x40023000 +10000f04: 40020000 .word 0x40020000 +10000f08: 200004cc .word 0x200004cc +10000f0c: 003fffc0 .word 0x003fffc0 +10000f10: 8f2b7b75 .word 0x8f2b7b75 + +10000f14 : +10000f14: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f18: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f1c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f20: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f24: b5f0 push {r4, r5, r6, r7, lr} +10000f26: 4616 mov r6, r2 +10000f28: f8dc 2004 ldr.w r2, [ip, #4] +10000f2c: 1f05 subs r5, r0, #4 +10000f2e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f32: bf38 it cc +10000f34: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f38: b2ed uxtb r5, r5 +10000f3a: bf38 it cc +10000f3c: f8cc 2004 strcc.w r2, [ip, #4] +10000f40: 2d01 cmp r5, #1 +10000f42: d92a bls.n 10000f9a +10000f44: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f48: 4c25 ldr r4, [pc, #148] @ (10000fe0 ) +10000f4a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f4e: 6017 str r7, [r2, #0] +10000f50: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f54: b9b2 cbnz r2, 10000f84 +10000f56: f8dc 2000 ldr.w r2, [ip] +10000f5a: 2d01 cmp r5, #1 +10000f5c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f60: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f64: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f68: 6032 str r2, [r6, #0] +10000f6a: d92a bls.n 10000fc2 +10000f6c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f70: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f74: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f78: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f7c: 6011 str r1, [r2, #0] +10000f7e: f8cc 3004 str.w r3, [ip, #4] +10000f82: bdf0 pop {r4, r5, r6, r7, pc} +10000f84: 6967 ldr r7, [r4, #20] +10000f86: fbb7 fef2 udiv lr, r7, r2 +10000f8a: f10e 0e01 add.w lr, lr, #1 +10000f8e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000f92: f1be 0e03 subs.w lr, lr, #3 +10000f96: d2fc bcs.n 10000f92 +10000f98: e7dd b.n 10000f56 +10000f9a: 2901 cmp r1, #1 +10000f9c: d1d2 bne.n 10000f44 +10000f9e: 2403 movs r4, #3 +10000fa0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fa4: 6014 str r4, [r2, #0] +10000fa6: f8dc 2008 ldr.w r2, [ip, #8] +10000faa: 07d2 lsls r2, r2, #31 +10000fac: d5fb bpl.n 10000fa6 +10000fae: f8dc 2000 ldr.w r2, [ip] +10000fb2: 4c0b ldr r4, [pc, #44] @ (10000fe0 ) +10000fb4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fb8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fbc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fc0: 6032 str r2, [r6, #0] +10000fc2: 2201 movs r2, #1 +10000fc4: f8dc 5000 ldr.w r5, [ip] +10000fc8: 404d eors r5, r1 +10000fca: f005 0503 and.w r5, r5, #3 +10000fce: 6035 str r5, [r6, #0] +10000fd0: fa02 f101 lsl.w r1, r2, r1 +10000fd4: f8dc 2008 ldr.w r2, [ip, #8] +10000fd8: 420a tst r2, r1 +10000fda: d0fb beq.n 10000fd4 +10000fdc: e7c6 b.n 10000f6c +10000fde: bf00 nop +10000fe0: 2000045c .word 0x2000045c + +10000fe4 : +10000fe4: 4b01 ldr r3, [pc, #4] @ (10000fec ) +10000fe6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000fea: 4770 bx lr +10000fec: 2000045c .word 0x2000045c + +10000ff0 : +10000ff0: b470 push {r4, r5, r6} +10000ff2: 9d03 ldr r5, [sp, #12] +10000ff4: 6804 ldr r4, [r0, #0] +10000ff6: 032d lsls r5, r5, #12 +10000ff8: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000ffc: 4b1b ldr r3, [pc, #108] @ (1000106c ) +10000ffe: 2c00 cmp r4, #0 +10001000: fbb3 f3f1 udiv r3, r3, r1 +10001004: fbb2 f6f3 udiv r6, r2, r3 +10001008: db1f blt.n 1000104a +1000100a: 4a19 ldr r2, [pc, #100] @ (10001070 ) +1000100c: 4b19 ldr r3, [pc, #100] @ (10001074 ) +1000100e: 4290 cmp r0, r2 +10001010: bf14 ite ne +10001012: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001016: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000101a: 4c17 ldr r4, [pc, #92] @ (10001078 ) +1000101c: 601a str r2, [r3, #0] +1000101e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001022: 601a str r2, [r3, #0] +10001024: 68a3 ldr r3, [r4, #8] +10001026: ea32 0303 bics.w r3, r2, r3 +1000102a: d1fb bne.n 10001024 +1000102c: 2221 movs r2, #33 @ 0x21 +1000102e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001032: 3304 adds r3, #4 +10001034: 6001 str r1, [r0, #0] +10001036: 6086 str r6, [r0, #8] +10001038: 601a str r2, [r3, #0] +1000103a: 6802 ldr r2, [r0, #0] +1000103c: 2a00 cmp r2, #0 +1000103e: dafc bge.n 1000103a +10001040: 2208 movs r2, #8 +10001042: 60c5 str r5, [r0, #12] +10001044: 601a str r2, [r3, #0] +10001046: bc70 pop {r4, r5, r6} +10001048: 4770 bx lr +1000104a: 6803 ldr r3, [r0, #0] +1000104c: f003 033f and.w r3, r3, #63 @ 0x3f +10001050: 428b cmp r3, r1 +10001052: d1da bne.n 1000100a +10001054: 6883 ldr r3, [r0, #8] +10001056: f3c3 030b ubfx r3, r3, #0, #12 +1000105a: 42b3 cmp r3, r6 +1000105c: d1d5 bne.n 1000100a +1000105e: 68c3 ldr r3, [r0, #12] +10001060: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001064: 42ab cmp r3, r5 +10001066: d1d0 bne.n 1000100a +10001068: e7ed b.n 10001046 +1000106a: bf00 nop +1000106c: 00b71b00 .word 0x00b71b00 +10001070: 40058000 .word 0x40058000 +10001074: 40022000 .word 0x40022000 +10001078: 40020000 .word 0x40020000 + +1000107c : +1000107c: 2301 movs r3, #1 +1000107e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001082: 0080 lsls r0, r0, #2 +10001084: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001088: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000108c: 6041 str r1, [r0, #4] +1000108e: 6003 str r3, [r0, #0] +10001090: 4770 bx lr +10001092: bf00 nop + +10001094 : +10001094: 2300 movs r3, #0 +10001096: 8adb ldrh r3, [r3, #22] +10001098: 2200 movs r2, #0 +1000109a: e842 f200 tt r2, r2 +1000109e: 0252 lsls r2, r2, #9 +100010a0: d401 bmi.n 100010a6 +100010a2: 2110 movs r1, #16 +100010a4: 4718 bx r3 +100010a6: 2104 movs r1, #4 +100010a8: 4718 bx r3 +100010aa: bf00 nop + +100010ac : +100010ac: 4a03 ldr r2, [pc, #12] @ (100010bc ) +100010ae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010b2: 2b00 cmp r3, #0 +100010b4: d0fb beq.n 100010ae +100010b6: f3bf 8f5f dmb sy +100010ba: 4770 bx lr +100010bc: 400e0000 .word 0x400e0000 + +100010c0 : +100010c0: 2100 movs r1, #0 +100010c2: 4b04 ldr r3, [pc, #16] @ (100010d4 ) +100010c4: 4a04 ldr r2, [pc, #16] @ (100010d8 ) +100010c6: f3bf 8f5f dmb sy +100010ca: f843 1b04 str.w r1, [r3], #4 +100010ce: 4293 cmp r3, r2 +100010d0: d1f9 bne.n 100010c6 +100010d2: 4770 bx lr +100010d4: 400e080c .word 0x400e080c +100010d8: 400e082c .word 0x400e082c + +100010dc : +100010dc: b410 push {r4} +100010de: f44f 708d mov.w r0, #282 @ 0x11a +100010e2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010e6: 4a06 ldr r2, [pc, #24] @ (10001100 ) +100010e8: 4b06 ldr r3, [pc, #24] @ (10001104 ) +100010ea: 4907 ldr r1, [pc, #28] @ (10001108 ) +100010ec: 6014 str r4, [r2, #0] +100010ee: 60d0 str r0, [r2, #12] +100010f0: 6019 str r1, [r3, #0] +100010f2: 6853 ldr r3, [r2, #4] +100010f4: 2b00 cmp r3, #0 +100010f6: dafc bge.n 100010f2 +100010f8: f85d 4b04 ldr.w r4, [sp], #4 +100010fc: 4770 bx lr +100010fe: bf00 nop +10001100: 40048000 .word 0x40048000 +10001104: 4004a000 .word 0x4004a000 +10001108: 00fab000 .word 0x00fab000 + +1000110c : +1000110c: 4770 bx lr +1000110e: bf00 nop + +10001110 : +10001110: b508 push {r3, lr} +10001112: 4801 ldr r0, [pc, #4] @ (10001118 ) +10001114: f7ff f8b6 bl 10000284 +10001118: 10001a14 .word 0x10001a14 + +1000111c : +1000111c: b538 push {r3, r4, r5, lr} +1000111e: 4c05 ldr r4, [pc, #20] @ (10001134 ) +10001120: 4d05 ldr r5, [pc, #20] @ (10001138 ) +10001122: 42ac cmp r4, r5 +10001124: d204 bcs.n 10001130 +10001126: f854 3b04 ldr.w r3, [r4], #4 +1000112a: 4798 blx r3 +1000112c: 42ac cmp r4, r5 +1000112e: d3fa bcc.n 10001126 +10001130: bd38 pop {r3, r4, r5, pc} +10001132: bf00 nop +10001134: 10001988 .word 0x10001988 +10001138: 100019c8 .word 0x100019c8 + +1000113c : +1000113c: b410 push {r4} +1000113e: 4807 ldr r0, [pc, #28] @ (1000115c ) +10001140: 4c07 ldr r4, [pc, #28] @ (10001160 ) +10001142: 4b08 ldr r3, [pc, #32] @ (10001164 ) +10001144: 4a08 ldr r2, [pc, #32] @ (10001168 ) +10001146: 4909 ldr r1, [pc, #36] @ (1000116c ) +10001148: 6004 str r4, [r0, #0] +1000114a: 601a str r2, [r3, #0] +1000114c: 688b ldr r3, [r1, #8] +1000114e: ea32 0303 bics.w r3, r2, r3 +10001152: d1fb bne.n 1000114c +10001154: f85d 4b04 ldr.w r4, [sp], #4 +10001158: 4770 bx lr +1000115a: bf00 nop +1000115c: 40022000 .word 0x40022000 +10001160: efef3b7f .word 0xefef3b7f +10001164: 40023000 .word 0x40023000 +10001168: 03f3fff6 .word 0x03f3fff6 +1000116c: 40020000 .word 0x40020000 + +10001170 : +10001170: 4b04 ldr r3, [pc, #16] @ (10001184 ) +10001172: 6cdb ldr r3, [r3, #76] @ 0x4c +10001174: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001178: d103 bne.n 10001182 +1000117a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000117e: 4b02 ldr r3, [pc, #8] @ (10001188 ) +10001180: 64da str r2, [r3, #76] @ 0x4c +10001182: 4770 bx lr +10001184: 50110000 .word 0x50110000 +10001188: 50112000 .word 0x50112000 + +1000118c : +1000118c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001190: 4b04 ldr r3, [pc, #16] @ (100011a4 ) +10001192: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001196: 430b orrs r3, r1 +10001198: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000119c: ee10 0430 dcp_rcmp r0 +100011a0: 4770 bx lr +100011a2: bf00 nop +100011a4: 00300303 .word 0x00300303 + +100011a8 : +100011a8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011ac: 4b04 ldr r3, [pc, #16] @ (100011c0 ) +100011ae: 4a05 ldr r2, [pc, #20] @ (100011c4 ) +100011b0: 6019 str r1, [r3, #0] +100011b2: 6893 ldr r3, [r2, #8] +100011b4: 43db mvns r3, r3 +100011b6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011ba: d1fa bne.n 100011b2 +100011bc: 4770 bx lr +100011be: bf00 nop +100011c0: 40023000 .word 0x40023000 +100011c4: 40020000 .word 0x40020000 + +100011c8 : +100011c8: b510 push {r4, lr} +100011ca: f245 2053 movw r0, #21075 @ 0x5253 +100011ce: f7ff ff61 bl 10001094 +100011d2: e8bd 4010 ldmia.w sp!, {r4, lr} +100011d6: 4603 mov r3, r0 +100011d8: 2004 movs r0, #4 +100011da: 4718 bx r3 + +100011dc : +100011dc: b510 push {r4, lr} +100011de: f245 2053 movw r0, #21075 @ 0x5253 +100011e2: f7ff ff57 bl 10001094 +100011e6: e8bd 4010 ldmia.w sp!, {r4, lr} +100011ea: 4603 mov r3, r0 +100011ec: 2001 movs r0, #1 +100011ee: 4718 bx r3 + +100011f0 : +100011f0: f7ff b8a0 b.w 10000334 + +100011f4 : +100011f4: 4914 ldr r1, [pc, #80] @ (10001248 ) +100011f6: 4b15 ldr r3, [pc, #84] @ (1000124c ) +100011f8: b570 push {r4, r5, r6, lr} +100011fa: 1a5c subs r4, r3, r1 +100011fc: 10a6 asrs r6, r4, #2 +100011fe: 2e44 cmp r6, #68 @ 0x44 +10001200: 4632 mov r2, r6 +10001202: bf28 it cs +10001204: 2244 movcs r2, #68 @ 0x44 +10001206: 4d12 ldr r5, [pc, #72] @ (10001250 ) +10001208: 0092 lsls r2, r2, #2 +1000120a: 4628 mov r0, r5 +1000120c: f000 fb0e bl 1000182c +10001210: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001214: d813 bhi.n 1000123e +10001216: 4a0f ldr r2, [pc, #60] @ (10001254 ) +10001218: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000121c: d012 beq.n 10001244 +1000121e: 192b adds r3, r5, r4 +10001220: 0841 lsrs r1, r0, #1 +10001222: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001226: e9c3 2200 strd r2, r2, [r3] +1000122a: 3308 adds r3, #8 +1000122c: 428b cmp r3, r1 +1000122e: d1fa bne.n 10001226 +10001230: 07c3 lsls r3, r0, #31 +10001232: d504 bpl.n 1000123e +10001234: f020 0001 bic.w r0, r0, #1 +10001238: 4430 add r0, r6 +1000123a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000123e: 4b06 ldr r3, [pc, #24] @ (10001258 ) +10001240: 609d str r5, [r3, #8] +10001242: bd70 pop {r4, r5, r6, pc} +10001244: 2043 movs r0, #67 @ 0x43 +10001246: e7f8 b.n 1000123a +10001248: 10000000 .word 0x10000000 +1000124c: 10000110 .word 0x10000110 +10001250: 20000000 .word 0x20000000 +10001254: 10000111 .word 0x10000111 +10001258: e000ed00 .word 0xe000ed00 + +1000125c : +1000125c: 2300 movs r3, #0 +1000125e: b570 push {r4, r5, r6, lr} +10001260: 4c2b ldr r4, [pc, #172] @ (10001310 ) +10001262: b082 sub sp, #8 +10001264: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001268: f7ff ff38 bl 100010dc +1000126c: 2201 movs r2, #1 +1000126e: 4b29 ldr r3, [pc, #164] @ (10001314 ) +10001270: 63da str r2, [r3, #60] @ 0x3c +10001272: 6c63 ldr r3, [r4, #68] @ 0x44 +10001274: 2b01 cmp r3, #1 +10001276: d1fc bne.n 10001272 +10001278: 2103 movs r1, #3 +1000127a: 4a26 ldr r2, [pc, #152] @ (10001314 ) +1000127c: 4b24 ldr r3, [pc, #144] @ (10001310 ) +1000127e: 6311 str r1, [r2, #48] @ 0x30 +10001280: 6b9c ldr r4, [r3, #56] @ 0x38 +10001282: 2c01 cmp r4, #1 +10001284: d1fc bne.n 10001280 +10001286: 2602 movs r6, #2 +10001288: 2505 movs r5, #5 +1000128a: 4621 mov r1, r4 +1000128c: 2305 movs r3, #5 +1000128e: 4a22 ldr r2, [pc, #136] @ (10001318 ) +10001290: 4822 ldr r0, [pc, #136] @ (1000131c ) +10001292: 9600 str r6, [sp, #0] +10001294: f7ff feac bl 10000ff0 +10001298: 4621 mov r1, r4 +1000129a: 462b mov r3, r5 +1000129c: 4a20 ldr r2, [pc, #128] @ (10001320 ) +1000129e: 4821 ldr r0, [pc, #132] @ (10001324 ) +100012a0: 9500 str r5, [sp, #0] +100012a2: f7ff fea5 bl 10000ff0 +100012a6: 2200 movs r2, #0 +100012a8: 2004 movs r0, #4 +100012aa: 4631 mov r1, r6 +100012ac: 4b1e ldr r3, [pc, #120] @ (10001328 ) +100012ae: f7ff fe31 bl 10000f14 +100012b2: 4621 mov r1, r4 +100012b4: 4628 mov r0, r5 +100012b6: 2200 movs r2, #0 +100012b8: 4b1c ldr r3, [pc, #112] @ (1000132c ) +100012ba: f7ff fe2b bl 10000f14 +100012be: 2200 movs r2, #0 +100012c0: 2008 movs r0, #8 +100012c2: 4611 mov r1, r2 +100012c4: 4b1a ldr r3, [pc, #104] @ (10001330 ) +100012c6: f7ff fe25 bl 10000f14 +100012ca: 2200 movs r2, #0 +100012cc: 2009 movs r0, #9 +100012ce: 4611 mov r1, r2 +100012d0: 4b17 ldr r3, [pc, #92] @ (10001330 ) +100012d2: f7ff fe1f bl 10000f14 +100012d6: 2200 movs r2, #0 +100012d8: 2006 movs r0, #6 +100012da: 4611 mov r1, r2 +100012dc: 4b13 ldr r3, [pc, #76] @ (1000132c ) +100012de: f7ff fe19 bl 10000f14 +100012e2: 2200 movs r2, #0 +100012e4: 4b11 ldr r3, [pc, #68] @ (1000132c ) +100012e6: 2007 movs r0, #7 +100012e8: 4611 mov r1, r2 +100012ea: f7ff fe13 bl 10000f14 +100012ee: 2004 movs r0, #4 +100012f0: f7ff fe78 bl 10000fe4 +100012f4: 2400 movs r4, #0 +100012f6: 4b0f ldr r3, [pc, #60] @ (10001334 ) +100012f8: fba3 3500 umull r3, r5, r3, r0 +100012fc: 0cad lsrs r5, r5, #18 +100012fe: b2e0 uxtb r0, r4 +10001300: 4629 mov r1, r5 +10001302: 3401 adds r4, #1 +10001304: f7ff feba bl 1000107c +10001308: 2c06 cmp r4, #6 +1000130a: d1f8 bne.n 100012fe +1000130c: b002 add sp, #8 +1000130e: bd70 pop {r4, r5, r6, pc} +10001310: 40010000 .word 0x40010000 +10001314: 40013000 .word 0x40013000 +10001318: 59682f00 .word 0x59682f00 +1000131c: 40050000 .word 0x40050000 +10001320: 47868c00 .word 0x47868c00 +10001324: 40058000 .word 0x40058000 +10001328: 00b71b00 .word 0x00b71b00 +1000132c: 08f0d180 .word 0x08f0d180 +10001330: 02dc6c00 .word 0x02dc6c00 +10001334: 431bde83 .word 0x431bde83 + +10001338 <_out_char>: +10001338: b900 cbnz r0, 1000133c <_out_char+0x4> +1000133a: 4770 bx lr +1000133c: f000 b91c b.w 10001578 <__wrap_putchar> + +10001340 : +10001340: b510 push {r4, lr} +10001342: 4b09 ldr r3, [pc, #36] @ (10001368 ) +10001344: b084 sub sp, #16 +10001346: 681c ldr r4, [r3, #0] +10001348: b14c cbz r4, 1000135e +1000134a: 4603 mov r3, r0 +1000134c: 9100 str r1, [sp, #0] +1000134e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001352: a903 add r1, sp, #12 +10001354: 4805 ldr r0, [pc, #20] @ (1000136c ) +10001356: 47a0 blx r4 +10001358: 2001 movs r0, #1 +1000135a: b004 add sp, #16 +1000135c: bd10 pop {r4, pc} +1000135e: f000 f94d bl 100015fc <__wrap_puts> +10001362: 4620 mov r0, r4 +10001364: b004 add sp, #16 +10001366: bd10 pop {r4, pc} +10001368: 2000048c .word 0x2000048c +1000136c: 10001339 .word 0x10001339 + +10001370 <_exit>: +10001370: be00 bkpt 0x0000 +10001372: e7fd b.n 10001370 <_exit> + +10001374 : +10001374: b508 push {r3, lr} +10001376: f7ff fffb bl 10001370 <_exit> +1000137a: bf00 nop + +1000137c : +1000137c: b538 push {r3, r4, r5, lr} +1000137e: 4c06 ldr r4, [pc, #24] @ (10001398 ) +10001380: 4d06 ldr r5, [pc, #24] @ (1000139c ) +10001382: f7ff fecb bl 1000111c +10001386: 42ac cmp r4, r5 +10001388: d204 bcs.n 10001394 +1000138a: f854 3b04 ldr.w r3, [r4], #4 +1000138e: 4798 blx r3 +10001390: 42ac cmp r4, r5 +10001392: d3fa bcc.n 1000138a +10001394: bd38 pop {r3, r4, r5, pc} +10001396: bf00 nop +10001398: 100019c8 .word 0x100019c8 +1000139c: 100019cc .word 0x100019cc + +100013a0 : +100013a0: 6803 ldr r3, [r0, #0] +100013a2: 4608 mov r0, r1 +100013a4: 4611 mov r1, r2 +100013a6: 4718 bx r3 + +100013a8 : +100013a8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100013ac: 4615 mov r5, r2 +100013ae: 7d42 ldrb r2, [r0, #21] +100013b0: 4607 mov r7, r0 +100013b2: 4688 mov r8, r1 +100013b4: 2a00 cmp r2, #0 +100013b6: d046 beq.n 10001446 +100013b8: 2d00 cmp r5, #0 +100013ba: dd1d ble.n 100013f8 +100013bc: 780b ldrb r3, [r1, #0] +100013be: 2b0a cmp r3, #10 +100013c0: d023 beq.n 1000140a +100013c2: 2d01 cmp r5, #1 +100013c4: f04f 0c00 mov.w ip, #0 +100013c8: d018 beq.n 100013fc +100013ca: 4646 mov r6, r8 +100013cc: 2401 movs r4, #1 +100013ce: f816 2f01 ldrb.w r2, [r6, #1]! +100013d2: 4621 mov r1, r4 +100013d4: 2a0a cmp r2, #10 +100013d6: f104 0401 add.w r4, r4, #1 +100013da: d022 beq.n 10001422 +100013dc: 42a5 cmp r5, r4 +100013de: d1f6 bne.n 100013ce +100013e0: 4565 cmp r5, ip +100013e2: dc0b bgt.n 100013fc +100013e4: eb08 0305 add.w r3, r8, r5 +100013e8: f813 3c01 ldrb.w r3, [r3, #-1] +100013ec: f1a3 030d sub.w r3, r3, #13 +100013f0: fab3 f383 clz r3, r3 +100013f4: 095b lsrs r3, r3, #5 +100013f6: 753b strb r3, [r7, #20] +100013f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100013fc: 683b ldr r3, [r7, #0] +100013fe: eba5 010c sub.w r1, r5, ip +10001402: eb08 000c add.w r0, r8, ip +10001406: 4798 blx r3 +10001408: e7ec b.n 100013e4 +1000140a: 7d03 ldrb r3, [r0, #20] +1000140c: 2b00 cmp r3, #0 +1000140e: d1d8 bne.n 100013c2 +10001410: 6803 ldr r3, [r0, #0] +10001412: 2102 movs r1, #2 +10001414: 480f ldr r0, [pc, #60] @ (10001454 ) +10001416: 4798 blx r3 +10001418: 2d01 cmp r5, #1 +1000141a: d0e3 beq.n 100013e4 +1000141c: f04f 0c01 mov.w ip, #1 +10001420: e7d3 b.n 100013ca +10001422: f816 3c01 ldrb.w r3, [r6, #-1] +10001426: 2b0d cmp r3, #13 +10001428: d0d8 beq.n 100013dc +1000142a: 458c cmp ip, r1 +1000142c: eb08 000c add.w r0, r8, ip +10001430: eba1 010c sub.w r1, r1, ip +10001434: da01 bge.n 1000143a +10001436: 683b ldr r3, [r7, #0] +10001438: 4798 blx r3 +1000143a: 2102 movs r1, #2 +1000143c: 4805 ldr r0, [pc, #20] @ (10001454 ) +1000143e: 683b ldr r3, [r7, #0] +10001440: 4798 blx r3 +10001442: 46a4 mov ip, r4 +10001444: e7ca b.n 100013dc +10001446: 4629 mov r1, r5 +10001448: 4640 mov r0, r8 +1000144a: 683b ldr r3, [r7, #0] +1000144c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001450: 4718 bx r3 +10001452: bf00 nop +10001454: 10001af8 .word 0x10001af8 + +10001458 : +10001458: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +1000145c: b082 sub sp, #8 +1000145e: 460d mov r5, r1 +10001460: 4691 mov r9, r2 +10001462: 461c mov r4, r3 +10001464: 4606 mov r6, r0 +10001466: f7ff fc9b bl 10000da0 +1000146a: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +1000146e: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001472: 4a2e ldr r2, [pc, #184] @ (1000152c ) +10001474: 1882 adds r2, r0, r2 +10001476: f141 0300 adc.w r3, r1, #0 +1000147a: 4594 cmp ip, r2 +1000147c: eb77 0103 sbcs.w r1, r7, r3 +10001480: bf3c itt cc +10001482: 4662 movcc r2, ip +10001484: 463b movcc r3, r7 +10001486: 482a ldr r0, [pc, #168] @ (10001530 ) +10001488: f000 fa7a bl 10001980 <__mutex_try_enter_block_until_veneer> +1000148c: 1c6b adds r3, r5, #1 +1000148e: 4680 mov r8, r0 +10001490: d040 beq.n 10001514 +10001492: b30c cbz r4, 100014d8 +10001494: 4f27 ldr r7, [pc, #156] @ (10001534 ) +10001496: 4b28 ldr r3, [pc, #160] @ (10001538 ) +10001498: 681c ldr r4, [r3, #0] +1000149a: b1b4 cbz r4, 100014ca +1000149c: f1b9 0f00 cmp.w r9, #0 +100014a0: d11c bne.n 100014dc +100014a2: f8df 909c ldr.w r9, [pc, #156] @ 10001540 +100014a6: e001 b.n 100014ac +100014a8: 6924 ldr r4, [r4, #16] +100014aa: b174 cbz r4, 100014ca +100014ac: 6823 ldr r3, [r4, #0] +100014ae: 2b00 cmp r3, #0 +100014b0: d0fa beq.n 100014a8 +100014b2: f8d9 3000 ldr.w r3, [r9] +100014b6: b10b cbz r3, 100014bc +100014b8: 429c cmp r4, r3 +100014ba: d1f5 bne.n 100014a8 +100014bc: 4620 mov r0, r4 +100014be: 462a mov r2, r5 +100014c0: 4631 mov r1, r6 +100014c2: 47b8 blx r7 +100014c4: 6924 ldr r4, [r4, #16] +100014c6: 2c00 cmp r4, #0 +100014c8: d1f0 bne.n 100014ac +100014ca: f1b8 0f00 cmp.w r8, #0 +100014ce: d126 bne.n 1000151e +100014d0: 4628 mov r0, r5 +100014d2: b002 add sp, #8 +100014d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100014d8: 4f18 ldr r7, [pc, #96] @ (1000153c ) +100014da: e7dc b.n 10001496 +100014dc: f04f 0a0a mov.w sl, #10 +100014e0: f8df 905c ldr.w r9, [pc, #92] @ 10001540 +100014e4: e002 b.n 100014ec +100014e6: 6924 ldr r4, [r4, #16] +100014e8: 2c00 cmp r4, #0 +100014ea: d0ee beq.n 100014ca +100014ec: 6823 ldr r3, [r4, #0] +100014ee: 2b00 cmp r3, #0 +100014f0: d0f9 beq.n 100014e6 +100014f2: f8d9 3000 ldr.w r3, [r9] +100014f6: b10b cbz r3, 100014fc +100014f8: 42a3 cmp r3, r4 +100014fa: d1f4 bne.n 100014e6 +100014fc: 462a mov r2, r5 +100014fe: 4631 mov r1, r6 +10001500: 4620 mov r0, r4 +10001502: 47b8 blx r7 +10001504: 2201 movs r2, #1 +10001506: 4620 mov r0, r4 +10001508: f10d 0107 add.w r1, sp, #7 +1000150c: f88d a007 strb.w sl, [sp, #7] +10001510: 47b8 blx r7 +10001512: e7e8 b.n 100014e6 +10001514: 4630 mov r0, r6 +10001516: f000 f9ff bl 10001918 +1000151a: 4605 mov r5, r0 +1000151c: e7b9 b.n 10001492 +1000151e: 4804 ldr r0, [pc, #16] @ (10001530 ) +10001520: f000 fa2a bl 10001978 <__mutex_exit_veneer> +10001524: 4628 mov r0, r5 +10001526: b002 add sp, #8 +10001528: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000152c: 000f4240 .word 0x000f4240 +10001530: 200002a4 .word 0x200002a4 +10001534: 100013a9 .word 0x100013a9 +10001538: 20000484 .word 0x20000484 +1000153c: 100013a1 .word 0x100013a1 +10001540: 20000488 .word 0x20000488 + +10001544 : +10001544: 4a08 ldr r2, [pc, #32] @ (10001568 ) +10001546: 6813 ldr r3, [r2, #0] +10001548: b923 cbnz r3, 10001554 +1000154a: e00a b.n 10001562 +1000154c: f103 0210 add.w r2, r3, #16 +10001550: 691b ldr r3, [r3, #16] +10001552: b133 cbz r3, 10001562 +10001554: 4283 cmp r3, r0 +10001556: d1f9 bne.n 1000154c +10001558: b929 cbnz r1, 10001566 +1000155a: 6918 ldr r0, [r3, #16] +1000155c: 6010 str r0, [r2, #0] +1000155e: 6119 str r1, [r3, #16] +10001560: 4770 bx lr +10001562: b101 cbz r1, 10001566 +10001564: 6010 str r0, [r2, #0] +10001566: 4770 bx lr +10001568: 20000484 .word 0x20000484 + +1000156c : +1000156c: b508 push {r3, lr} +1000156e: f000 f933 bl 100017d8 +10001572: 2001 movs r0, #1 +10001574: bd08 pop {r3, pc} +10001576: bf00 nop + +10001578 <__wrap_putchar>: +10001578: b5f0 push {r4, r5, r6, r7, lr} +1000157a: b083 sub sp, #12 +1000157c: 4606 mov r6, r0 +1000157e: f88d 0007 strb.w r0, [sp, #7] +10001582: f7ff fc0d bl 10000da0 +10001586: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000158a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000158e: 4a17 ldr r2, [pc, #92] @ (100015ec <__wrap_putchar+0x74>) +10001590: 1882 adds r2, r0, r2 +10001592: f141 0300 adc.w r3, r1, #0 +10001596: 4295 cmp r5, r2 +10001598: eb74 0103 sbcs.w r1, r4, r3 +1000159c: bf3c itt cc +1000159e: 4623 movcc r3, r4 +100015a0: 462a movcc r2, r5 +100015a2: 4813 ldr r0, [pc, #76] @ (100015f0 <__wrap_putchar+0x78>) +100015a4: f000 f9ec bl 10001980 <__mutex_try_enter_block_until_veneer> +100015a8: 4b12 ldr r3, [pc, #72] @ (100015f4 <__wrap_putchar+0x7c>) +100015aa: 4607 mov r7, r0 +100015ac: 681c ldr r4, [r3, #0] +100015ae: b19c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b0: 4d11 ldr r5, [pc, #68] @ (100015f8 <__wrap_putchar+0x80>) +100015b2: e001 b.n 100015b8 <__wrap_putchar+0x40> +100015b4: 6924 ldr r4, [r4, #16] +100015b6: b17c cbz r4, 100015d8 <__wrap_putchar+0x60> +100015b8: 6823 ldr r3, [r4, #0] +100015ba: 2b00 cmp r3, #0 +100015bc: d0fa beq.n 100015b4 <__wrap_putchar+0x3c> +100015be: 682b ldr r3, [r5, #0] +100015c0: b10b cbz r3, 100015c6 <__wrap_putchar+0x4e> +100015c2: 429c cmp r4, r3 +100015c4: d1f6 bne.n 100015b4 <__wrap_putchar+0x3c> +100015c6: 4620 mov r0, r4 +100015c8: 2201 movs r2, #1 +100015ca: f10d 0107 add.w r1, sp, #7 +100015ce: f7ff feeb bl 100013a8 +100015d2: 6924 ldr r4, [r4, #16] +100015d4: 2c00 cmp r4, #0 +100015d6: d1ef bne.n 100015b8 <__wrap_putchar+0x40> +100015d8: b917 cbnz r7, 100015e0 <__wrap_putchar+0x68> +100015da: 4630 mov r0, r6 +100015dc: b003 add sp, #12 +100015de: bdf0 pop {r4, r5, r6, r7, pc} +100015e0: 4803 ldr r0, [pc, #12] @ (100015f0 <__wrap_putchar+0x78>) +100015e2: f000 f9c9 bl 10001978 <__mutex_exit_veneer> +100015e6: 4630 mov r0, r6 +100015e8: b003 add sp, #12 +100015ea: bdf0 pop {r4, r5, r6, r7, pc} +100015ec: 000f4240 .word 0x000f4240 +100015f0: 200002a4 .word 0x200002a4 +100015f4: 20000484 .word 0x20000484 +100015f8: 20000488 .word 0x20000488 + +100015fc <__wrap_puts>: +100015fc: b538 push {r3, r4, r5, lr} +100015fe: 4604 mov r4, r0 +10001600: f000 f98a bl 10001918 +10001604: 2301 movs r3, #1 +10001606: 4605 mov r5, r0 +10001608: 461a mov r2, r3 +1000160a: 4620 mov r0, r4 +1000160c: 4629 mov r1, r5 +1000160e: f7ff ff23 bl 10001458 +10001612: 4b08 ldr r3, [pc, #32] @ (10001634 <__wrap_puts+0x38>) +10001614: 681c ldr r4, [r3, #0] +10001616: b12c cbz r4, 10001624 <__wrap_puts+0x28> +10001618: 6863 ldr r3, [r4, #4] +1000161a: b12b cbz r3, 10001628 <__wrap_puts+0x2c> +1000161c: 4798 blx r3 +1000161e: 6924 ldr r4, [r4, #16] +10001620: 2c00 cmp r4, #0 +10001622: d1f9 bne.n 10001618 <__wrap_puts+0x1c> +10001624: 4628 mov r0, r5 +10001626: bd38 pop {r3, r4, r5, pc} +10001628: 6924 ldr r4, [r4, #16] +1000162a: 2c00 cmp r4, #0 +1000162c: d1f4 bne.n 10001618 <__wrap_puts+0x1c> +1000162e: 4628 mov r0, r5 +10001630: bd38 pop {r3, r4, r5, pc} +10001632: bf00 nop +10001634: 20000484 .word 0x20000484 + +10001638 : +10001638: f1b1 0c00 subs.w ip, r1, #0 +1000163c: dd1d ble.n 1000167a +1000163e: 4a0f ldr r2, [pc, #60] @ (1000167c ) +10001640: 4b0f ldr r3, [pc, #60] @ (10001680 ) +10001642: 6812 ldr r2, [r2, #0] +10001644: b530 push {r4, r5, lr} +10001646: 1ad3 subs r3, r2, r3 +10001648: fab3 f383 clz r3, r3 +1000164c: 240d movs r4, #13 +1000164e: 4d0d ldr r5, [pc, #52] @ (10001684 ) +10001650: 095b lsrs r3, r3, #5 +10001652: 1e41 subs r1, r0, #1 +10001654: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10001658: 448c add ip, r1 +1000165a: f811 0f01 ldrb.w r0, [r1, #1]! +1000165e: 4586 cmp lr, r0 +10001660: d006 beq.n 10001670 +10001662: 6993 ldr r3, [r2, #24] +10001664: 069b lsls r3, r3, #26 +10001666: d4fc bmi.n 10001662 +10001668: 4561 cmp r1, ip +1000166a: 6010 str r0, [r2, #0] +1000166c: d1f5 bne.n 1000165a +1000166e: bd30 pop {r4, r5, pc} +10001670: 6993 ldr r3, [r2, #24] +10001672: 069d lsls r5, r3, #26 +10001674: d4fc bmi.n 10001670 +10001676: 6014 str r4, [r2, #0] +10001678: e7f3 b.n 10001662 +1000167a: 4770 bx lr +1000167c: 200004d0 .word 0x200004d0 +10001680: 40078000 .word 0x40078000 +10001684: 200004cc .word 0x200004cc + +10001688 : +10001688: 4b22 ldr r3, [pc, #136] @ (10001714 ) +1000168a: f1b1 0c00 subs.w ip, r1, #0 +1000168e: b410 push {r4} +10001690: 681c ldr r4, [r3, #0] +10001692: dd2e ble.n 100016f2 +10001694: 4603 mov r3, r0 +10001696: 2000 movs r0, #0 +10001698: 4a1f ldr r2, [pc, #124] @ (10001718 ) +1000169a: 1e59 subs r1, r3, #1 +1000169c: 6812 ldr r2, [r2, #0] +1000169e: 6993 ldr r3, [r2, #24] +100016a0: 06db lsls r3, r3, #27 +100016a2: d417 bmi.n 100016d4 +100016a4: 3001 adds r0, #1 +100016a6: 6993 ldr r3, [r2, #24] +100016a8: 06db lsls r3, r3, #27 +100016aa: d4fc bmi.n 100016a6 +100016ac: 6813 ldr r3, [r2, #0] +100016ae: 4584 cmp ip, r0 +100016b0: f801 3f01 strb.w r3, [r1, #1]! +100016b4: d1f3 bne.n 1000169e +100016b6: b14c cbz r4, 100016cc +100016b8: 2150 movs r1, #80 @ 0x50 +100016ba: 4613 mov r3, r2 +100016bc: 6391 str r1, [r2, #56] @ 0x38 +100016be: f853 2f34 ldr.w r2, [r3, #52]! +100016c2: f002 0238 and.w r2, r2, #56 @ 0x38 +100016c6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016ca: 601a str r2, [r3, #0] +100016cc: 4660 mov r0, ip +100016ce: f85d 4b04 ldr.w r4, [sp], #4 +100016d2: 4770 bx lr +100016d4: b14c cbz r4, 100016ea +100016d6: 2150 movs r1, #80 @ 0x50 +100016d8: 4613 mov r3, r2 +100016da: 6391 str r1, [r2, #56] @ 0x38 +100016dc: f853 2f34 ldr.w r2, [r3, #52]! +100016e0: f002 0238 and.w r2, r2, #56 @ 0x38 +100016e4: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100016e8: 601a str r2, [r3, #0] +100016ea: b178 cbz r0, 1000170c +100016ec: f85d 4b04 ldr.w r4, [sp], #4 +100016f0: 4770 bx lr +100016f2: b15c cbz r4, 1000170c +100016f4: 4b08 ldr r3, [pc, #32] @ (10001718 ) +100016f6: 2150 movs r1, #80 @ 0x50 +100016f8: 681a ldr r2, [r3, #0] +100016fa: 4613 mov r3, r2 +100016fc: 6391 str r1, [r2, #56] @ 0x38 +100016fe: f853 2f34 ldr.w r2, [r3, #52]! +10001702: f002 0238 and.w r2, r2, #56 @ 0x38 +10001706: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000170a: 601a str r2, [r3, #0] +1000170c: f06f 0002 mvn.w r0, #2 +10001710: e7dd b.n 100016ce +10001712: bf00 nop +10001714: 20000450 .word 0x20000450 +10001718: 200004d0 .word 0x200004d0 + +1000171c : +1000171c: 4b05 ldr r3, [pc, #20] @ (10001734 ) +1000171e: 681b ldr r3, [r3, #0] +10001720: b133 cbz r3, 10001730 +10001722: 2100 movs r1, #0 +10001724: 4a04 ldr r2, [pc, #16] @ (10001738 ) +10001726: 4805 ldr r0, [pc, #20] @ (1000173c ) +10001728: 6812 ldr r2, [r2, #0] +1000172a: 6800 ldr r0, [r0, #0] +1000172c: 6391 str r1, [r2, #56] @ 0x38 +1000172e: 4718 bx r3 +10001730: 4770 bx lr +10001732: bf00 nop +10001734: 20000450 .word 0x20000450 +10001738: 200004d0 .word 0x200004d0 +1000173c: 20000454 .word 0x20000454 + +10001740 : +10001740: 4b02 ldr r3, [pc, #8] @ (1000174c ) +10001742: 681a ldr r2, [r3, #0] +10001744: 6993 ldr r3, [r2, #24] +10001746: 071b lsls r3, r3, #28 +10001748: d4fc bmi.n 10001744 +1000174a: 4770 bx lr +1000174c: 200004d0 .word 0x200004d0 + +10001750 : +10001750: b5f8 push {r3, r4, r5, r6, r7, lr} +10001752: 4f1c ldr r7, [pc, #112] @ (100017c4 ) +10001754: 4d1c ldr r5, [pc, #112] @ (100017c8 ) +10001756: 683a ldr r2, [r7, #0] +10001758: 4e1c ldr r6, [pc, #112] @ (100017cc ) +1000175a: 42aa cmp r2, r5 +1000175c: bf14 ite ne +1000175e: 2521 movne r5, #33 @ 0x21 +10001760: 2522 moveq r5, #34 @ 0x22 +10001762: 4604 mov r4, r0 +10001764: f8d6 c000 ldr.w ip, [r6] +10001768: b118 cbz r0, 10001772 +1000176a: f1bc 0f00 cmp.w ip, #0 +1000176e: d010 beq.n 10001792 +10001770: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001772: f1bc 0f00 cmp.w ip, #0 +10001776: d0fb beq.n 10001770 +10001778: 4601 mov r1, r0 +1000177a: 6390 str r0, [r2, #56] @ 0x38 +1000177c: 4628 mov r0, r5 +1000177e: f7fe fe05 bl 1000038c +10001782: 4628 mov r0, r5 +10001784: 4912 ldr r1, [pc, #72] @ (100017d0 ) +10001786: f7fe fe47 bl 10000418 +1000178a: 4b12 ldr r3, [pc, #72] @ (100017d4 ) +1000178c: 6034 str r4, [r6, #0] +1000178e: 601c str r4, [r3, #0] +10001790: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001792: 460b mov r3, r1 +10001794: 4a0f ldr r2, [pc, #60] @ (100017d4 ) +10001796: 490e ldr r1, [pc, #56] @ (100017d0 ) +10001798: 6030 str r0, [r6, #0] +1000179a: 4628 mov r0, r5 +1000179c: 6013 str r3, [r2, #0] +1000179e: f7fe fe0b bl 100003b8 +100017a2: 2101 movs r1, #1 +100017a4: 4628 mov r0, r5 +100017a6: f7fe fdf1 bl 1000038c +100017aa: 683a ldr r2, [r7, #0] +100017ac: 2150 movs r1, #80 @ 0x50 +100017ae: 4613 mov r3, r2 +100017b0: 6391 str r1, [r2, #56] @ 0x38 +100017b2: f853 2f34 ldr.w r2, [r3, #52]! +100017b6: f002 0238 and.w r2, r2, #56 @ 0x38 +100017ba: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100017be: 601a str r2, [r3, #0] +100017c0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100017c2: bf00 nop +100017c4: 200004d0 .word 0x200004d0 +100017c8: 40078000 .word 0x40078000 +100017cc: 20000450 .word 0x20000450 +100017d0: 1000171d .word 0x1000171d +100017d4: 20000454 .word 0x20000454 + +100017d8 : +100017d8: b510 push {r4, lr} +100017da: 490e ldr r1, [pc, #56] @ (10001814 ) +100017dc: 4c0e ldr r4, [pc, #56] @ (10001818 ) +100017de: 480f ldr r0, [pc, #60] @ (1000181c ) +100017e0: 4a0f ldr r2, [pc, #60] @ (10001820 ) +100017e2: 4b10 ldr r3, [pc, #64] @ (10001824 ) +100017e4: 7800 ldrb r0, [r0, #0] +100017e6: 6021 str r1, [r4, #0] +100017e8: 2000 movs r0, #0 +100017ea: 2102 movs r1, #2 +100017ec: 7812 ldrb r2, [r2, #0] +100017ee: 781b ldrb r3, [r3, #0] +100017f0: f7fe fd2a bl 10000248 +100017f4: 2102 movs r1, #2 +100017f6: 2001 movs r0, #1 +100017f8: f7fe fd26 bl 10000248 +100017fc: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10001800: 6820 ldr r0, [r4, #0] +10001802: f7ff fb05 bl 10000e10 +10001806: e8bd 4010 ldmia.w sp!, {r4, lr} +1000180a: 2101 movs r1, #1 +1000180c: 4806 ldr r0, [pc, #24] @ (10001828 ) +1000180e: f7ff be99 b.w 10001544 +10001812: bf00 nop +10001814: 40070000 .word 0x40070000 +10001818: 200004d0 .word 0x200004d0 +1000181c: 10001b48 .word 0x10001b48 +10001820: 10001b44 .word 0x10001b44 +10001824: 10001b40 .word 0x10001b40 +10001828: 2000028c .word 0x2000028c + +1000182c : +1000182c: 4684 mov ip, r0 +1000182e: ea41 0300 orr.w r3, r1, r0 +10001832: f013 0303 ands.w r3, r3, #3 +10001836: d149 bne.n 100018cc +10001838: 3a40 subs r2, #64 @ 0x40 +1000183a: d323 bcc.n 10001884 +1000183c: 680b ldr r3, [r1, #0] +1000183e: 6003 str r3, [r0, #0] +10001840: 684b ldr r3, [r1, #4] +10001842: 6043 str r3, [r0, #4] +10001844: 688b ldr r3, [r1, #8] +10001846: 6083 str r3, [r0, #8] +10001848: 68cb ldr r3, [r1, #12] +1000184a: 60c3 str r3, [r0, #12] +1000184c: 690b ldr r3, [r1, #16] +1000184e: 6103 str r3, [r0, #16] +10001850: 694b ldr r3, [r1, #20] +10001852: 6143 str r3, [r0, #20] +10001854: 698b ldr r3, [r1, #24] +10001856: 6183 str r3, [r0, #24] +10001858: 69cb ldr r3, [r1, #28] +1000185a: 61c3 str r3, [r0, #28] +1000185c: 6a0b ldr r3, [r1, #32] +1000185e: 6203 str r3, [r0, #32] +10001860: 6a4b ldr r3, [r1, #36] @ 0x24 +10001862: 6243 str r3, [r0, #36] @ 0x24 +10001864: 6a8b ldr r3, [r1, #40] @ 0x28 +10001866: 6283 str r3, [r0, #40] @ 0x28 +10001868: 6acb ldr r3, [r1, #44] @ 0x2c +1000186a: 62c3 str r3, [r0, #44] @ 0x2c +1000186c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000186e: 6303 str r3, [r0, #48] @ 0x30 +10001870: 6b4b ldr r3, [r1, #52] @ 0x34 +10001872: 6343 str r3, [r0, #52] @ 0x34 +10001874: 6b8b ldr r3, [r1, #56] @ 0x38 +10001876: 6383 str r3, [r0, #56] @ 0x38 +10001878: 6bcb ldr r3, [r1, #60] @ 0x3c +1000187a: 63c3 str r3, [r0, #60] @ 0x3c +1000187c: 3040 adds r0, #64 @ 0x40 +1000187e: 3140 adds r1, #64 @ 0x40 +10001880: 3a40 subs r2, #64 @ 0x40 +10001882: d2db bcs.n 1000183c +10001884: 3230 adds r2, #48 @ 0x30 +10001886: d30b bcc.n 100018a0 +10001888: 680b ldr r3, [r1, #0] +1000188a: 6003 str r3, [r0, #0] +1000188c: 684b ldr r3, [r1, #4] +1000188e: 6043 str r3, [r0, #4] +10001890: 688b ldr r3, [r1, #8] +10001892: 6083 str r3, [r0, #8] +10001894: 68cb ldr r3, [r1, #12] +10001896: 60c3 str r3, [r0, #12] +10001898: 3010 adds r0, #16 +1000189a: 3110 adds r1, #16 +1000189c: 3a10 subs r2, #16 +1000189e: d2f3 bcs.n 10001888 +100018a0: 320c adds r2, #12 +100018a2: d305 bcc.n 100018b0 +100018a4: f851 3b04 ldr.w r3, [r1], #4 +100018a8: f840 3b04 str.w r3, [r0], #4 +100018ac: 3a04 subs r2, #4 +100018ae: d2f9 bcs.n 100018a4 +100018b0: 3204 adds r2, #4 +100018b2: d008 beq.n 100018c6 +100018b4: 07d2 lsls r2, r2, #31 +100018b6: bf1c itt ne +100018b8: f811 3b01 ldrbne.w r3, [r1], #1 +100018bc: f800 3b01 strbne.w r3, [r0], #1 +100018c0: d301 bcc.n 100018c6 +100018c2: 880b ldrh r3, [r1, #0] +100018c4: 8003 strh r3, [r0, #0] +100018c6: 4660 mov r0, ip +100018c8: 4770 bx lr +100018ca: bf00 nop +100018cc: 2a08 cmp r2, #8 +100018ce: d313 bcc.n 100018f8 +100018d0: 078b lsls r3, r1, #30 +100018d2: d0b1 beq.n 10001838 +100018d4: f010 0303 ands.w r3, r0, #3 +100018d8: d0ae beq.n 10001838 +100018da: f1c3 0304 rsb r3, r3, #4 +100018de: 1ad2 subs r2, r2, r3 +100018e0: 07db lsls r3, r3, #31 +100018e2: bf1c itt ne +100018e4: f811 3b01 ldrbne.w r3, [r1], #1 +100018e8: f800 3b01 strbne.w r3, [r0], #1 +100018ec: d3a4 bcc.n 10001838 +100018ee: f831 3b02 ldrh.w r3, [r1], #2 +100018f2: f820 3b02 strh.w r3, [r0], #2 +100018f6: e79f b.n 10001838 +100018f8: 3a04 subs r2, #4 +100018fa: d3d9 bcc.n 100018b0 +100018fc: 3a01 subs r2, #1 +100018fe: f811 3b01 ldrb.w r3, [r1], #1 +10001902: f800 3b01 strb.w r3, [r0], #1 +10001906: d2f9 bcs.n 100018fc +10001908: 780b ldrb r3, [r1, #0] +1000190a: 7003 strb r3, [r0, #0] +1000190c: 784b ldrb r3, [r1, #1] +1000190e: 7043 strb r3, [r0, #1] +10001910: 788b ldrb r3, [r1, #2] +10001912: 7083 strb r3, [r0, #2] +10001914: 4660 mov r0, ip +10001916: 4770 bx lr + +10001918 : +10001918: f020 0103 bic.w r1, r0, #3 +1000191c: f010 0003 ands.w r0, r0, #3 +10001920: f1c0 0000 rsb r0, r0, #0 +10001924: f851 3b04 ldr.w r3, [r1], #4 +10001928: f100 0c04 add.w ip, r0, #4 +1000192c: ea4f 0ccc mov.w ip, ip, lsl #3 +10001930: f06f 0200 mvn.w r2, #0 +10001934: bf1c itt ne +10001936: fa22 f20c lsrne.w r2, r2, ip +1000193a: 4313 orrne r3, r2 +1000193c: f04f 0c01 mov.w ip, #1 +10001940: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001944: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001948: eba3 020c sub.w r2, r3, ip +1000194c: ea22 0203 bic.w r2, r2, r3 +10001950: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001954: bf04 itt eq +10001956: f851 3b04 ldreq.w r3, [r1], #4 +1000195a: 3004 addeq r0, #4 +1000195c: d0f4 beq.n 10001948 +1000195e: f1c2 0100 rsb r1, r2, #0 +10001962: ea02 0201 and.w r2, r2, r1 +10001966: fab2 f282 clz r2, r2 +1000196a: f1c2 021f rsb r2, r2, #31 +1000196e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10001972: 4770 bx lr + +10001974 <_fini>: +10001974: b5f8 push {r3, r4, r5, r6, r7, lr} +10001976: bf00 nop + +10001978 <__mutex_exit_veneer>: +10001978: f85f f000 ldr.w pc, [pc] @ 1000197c <__mutex_exit_veneer+0x4> +1000197c: 200001e5 .word 0x200001e5 + +10001980 <__mutex_try_enter_block_until_veneer>: +10001980: f85f f000 ldr.w pc, [pc] @ 10001984 <__mutex_try_enter_block_until_veneer+0x4> +10001984: 2000017d .word 0x2000017d + +10001988 <__pre_init_runtime_init_bootrom_reset>: +10001988: 100011c9 .... + +1000198c <__pre_init_runtime_init_early_resets>: +1000198c: 1000113d =... + +10001990 <__pre_init_runtime_init_usb_power_down>: +10001990: 10001171 q... + +10001994 <__pre_init_runtime_init_clocks>: +10001994: 1000125d ]... + +10001998 <__pre_init_runtime_init_post_clock_resets>: +10001998: 100011a9 .... + +1000199c <__pre_init_runtime_init_boot_locks_reset>: +1000199c: 100010c1 .... + +100019a0 <__pre_init_runtime_init_spin_locks_reset>: +100019a0: 100011f1 .... + +100019a4 <__pre_init_runtime_init_bootrom_locking_enable>: +100019a4: 100010ad .... + +100019a8 <__pre_init_runtime_init_mutex>: +100019a8: 100006d5 .... + +100019ac <__pre_init_runtime_init_install_ram_vector_table>: +100019ac: 100011f5 .... + +100019b0 <__pre_init_runtime_init_default_alarm_pool>: +100019b0: 10000a51 Q... + +100019b4 <__pre_init_first_per_core_initializer>: +100019b4: 1000110d .... + +100019b8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100019b8: 100011dd .... + +100019bc <__pre_init_runtime_init_per_core_enable_coprocessors>: +100019bc: 1000118d .... + +100019c0 <__pre_init_spinlock_set_extexclall>: +100019c0: 10000325 %... + +100019c4 <__pre_init_runtime_init_per_core_irq_priorities>: +100019c4: 1000034d M... + +100019c8 <__frame_dummy_init_array_entry>: +100019c8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__best_effort_wfe_or_timeout_veneer>: +20000220: f85f f000 ldr.w pc, [pc] @ 20000224 <__best_effort_wfe_or_timeout_veneer+0x4> +20000224: 10000c99 .word 0x10000c99 + +20000228 : +20000228: 00000010 .... + +2000022c : +2000022c: 00000000 .word 0x00000000 +20000230: 00010000 .word 0x00010000 + ... +2000023c: 00020000 .word 0x00020000 + ... +20000248: 00030000 .word 0x00030000 + ... +20000254: 00ff0000 .word 0x00ff0000 +20000258: 00000000 .word 0x00000000 + +2000025c : +2000025c: b501 push {r0, lr} +2000025e: 6848 ldr r0, [r1, #4] +20000260: 3101 adds r1, #1 +20000262: 468e mov lr, r1 +20000264: 4700 bx r0 + +20000266 : +20000266: 4670 mov r0, lr +20000268: 3809 subs r0, #9 +2000026a: 4901 ldr r1, [pc, #4] @ (20000270 ) +2000026c: 4788 blx r1 +2000026e: bd01 pop {r0, pc} +20000270: 1000060d .word 0x1000060d + +20000274 : + ... +20000288: 200002b0 ... + +2000028c : +2000028c: 10001639 10001741 10001689 10001751 9...A.......Q... +2000029c: 00000000 00000100 ........ + +200002a4 : + ... diff --git a/WEEK03/0x0001_hello-world/build/0x0001_hello-world.elf b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.elf new file mode 100755 index 0000000..71b92a2 Binary files /dev/null and b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.elf differ diff --git a/WEEK03/0x0001_hello-world/build/0x0001_hello-world.elf.map b/WEEK03/0x0001_hello-world/build/0x0001_hello-world.elf.map new file mode 100644 index 0000000..5bc54d2 --- /dev/null +++ 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b/WEEK03/0x0001_hello-world/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK03/0x0001_hello-world/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK03/0x0001_hello-world/pico_sdk_import.cmake b/WEEK03/0x0001_hello-world/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK03/0x0001_hello-world/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK03/GHIDRA_PATCHING_TUTORIAL.md b/WEEK03/GHIDRA_PATCHING_TUTORIAL.md new file mode 100644 index 0000000..5e2801d --- /dev/null +++ b/WEEK03/GHIDRA_PATCHING_TUTORIAL.md @@ -0,0 +1,252 @@ +# Ghidra Binary Patching Tutorial: ARM Cortex-M Thumb-2 Bytes Window Workflow + +``` ++-----------------------------------------------------------------+ +| GHIDRA BYTES WINDOW BINARY PATCHING GUIDE | +| | +| Target Architecture: ARM Cortex-M33 (ARMv8-M Main / Thumb-2) | +| Tool: Ghidra Software Reverse Engineering Suite | +| Core Technique: Listing Clear (C) -> Bytes Window Edit | +| -> Listing Disassemble (D) | +| Target Firmware: Raspberry Pi Pico 2 (RP2350) Raw Binaries | +| Classification: Defensive Firmware Security & Patching | ++-----------------------------------------------------------------+ +``` + +--- + +## 1. Executive Summary & Overview + +Binary patching is a fundamental capability in embedded systems reverse engineering and defensive firmware security. When analyzing compiled firmware images—such as raw binary files (`.bin`) extracted from bare-metal microcontrollers—security analysts and engineers frequently need to modify program logic directly in machine code without access to the original source code or a compilation toolchain. + +Common operational scenarios for embedded binary patching include: +- **Defensive Telemetry Correction:** Rectifying corrupted or spoofed sensor thresholds in mission-critical industrial or SCADA control nodes. +- **Vulnerability Remediation & Hot-Patching:** Neutralizing memory corruption flaws, logic bugs, or insecure dispatch routines in deployed firmware. +- **Hardware Reverse Engineering Challenges:** Solving embedded Capture The Flag (CTF) challenges where firmware logic gates must be manipulated to uncover security flags. + +While high-level desktop reverse engineering tutorials often recommend right-clicking an instruction and selecting **Patch Instruction**, this GUI action consistently fails when targeting **ARM Cortex-M Thumb-2** binaries. This comprehensive guide documents the underlying architectural reason for this failure and provides the official, step-by-step **Bytes Window Workflow** using high-resolution Ghidra screenshots from live analysis of `CTF-01.bin`. + +--- + +## 2. The Architectural Problem: Why GUI Patching Fails in ARM Thumb-2 + +### 2.1 The ARM Cortex-M Thumb-2 Instruction Set & IT Blocks + +The Raspberry Pi Pico 2 is powered by the dual-core **ARM Cortex-M33** microcontroller, which executes the **ARMv8-M Mainline (Thumb-2)** instruction set. In Thumb-2 mode: +1. Instructions are variable-length: either 16 bits (2 bytes) or 32 bits (4 bytes). +2. Conditional execution is handled via **If-Then (`IT`) blocks** (e.g., `it`, `ite`, `itt`). +3. An instruction immediately preceding an `IT` block sets the Condition Code Flags (e.g., `cmp r3, #0x5e`), and the subsequent `ite hi` instruction evaluates those flags to execute conditionally. + +### 2.2 The Context Collision in Ghidra's Disassembler + +When you right-click a compare instruction (such as `cmp r3, #0x5e` at offset `0x100001FC`) and select **Patch Instruction** (or press `Ctrl+Shift+G`): + +``` ++-----------------------------------------------------------------+ +| GUI PATCH INSTRUCTION FAILURE CHAIN | +| | +| 1. User invokes GUI Patch Instruction at compare site | +| 2. Ghidra PatchInstructionAction invokes ReDisassembleCommand | +| 3. ReDisassembleCommand hits subsequent 'ite' block | +| 4. Ghidra attempts to write internal ITBlock context register | +| 5. CodeManager throws: ContextChangeException | +| 6. Ghidra aborts Thumb decoding -> falls back to 32-bit ARM | +| 7. Downstream instructions collapsed into movwcs / ldmdavs | +| 8. Compare Site B (0x1000020A) completely swallowed & lost | ++-----------------------------------------------------------------+ +``` + +Ghidra maintains internal context registers (such as `TMode` for Thumb execution and `ITBlock` for conditional state tracking). When `ReDisassembleCommand` encounters an existing instruction downstream of the patch site, the context register write collides with existing database state, throwing a `ContextChangeException` (`Context register change conflicts with one or more instructions`). + +Because Ghidra's assembler aborts decoding Thumb instructions upon this conflict, it defaults to **32-bit ARM disassembly mode**. It misinterprets the 16-bit Thumb opcode bytes as 32-bit ARM instructions (`movwcs`, `ldmdavs`, `blcs`), which **swallows downstream code** and completely obliterates subsequent compare sites (such as Compare Site B at `0x1000020A`). + +### 2.3 Why 'Locking TMode = 1' (Ctrl+R) Does Not Solve the Issue + +Attempting to highlight the `.text` section and press `Ctrl+R` (**Set Register Values**) to set `TMode = 1` also fails once Ghidra has already performed its initial auto-analysis. Ghidra's database rules forbid setting context register values across memory ranges that already contain disassembled code. + +The clean, permanent, and battle-tested technique is the **Bytes Window Workflow**. + +--- + +## 3. The 5-Step Bytes Window Workflow + +The **Bytes Window Workflow** completely bypasses Ghidra's assembler context conflicts. By clearing the single instruction to undefined raw bytes, editing the underlying byte in the hex view, and then disassembling just that location, Ghidra's disassembler operates cleanly without attempting to rewrite `ITBlock` context registers over existing downstream code. + +### Step 1: Open the Bytes Window + +By default, Ghidra displays the **Listing** view and the **Decompiler** view. To inspect and edit raw hex bytes directly: + +1. Look at the top Ghidra menu bar. +2. Click **Window** in the menu. +3. Select **Bytes: .bin** (for example, **Bytes: CTF-01.bin**). + +![Ghidra Window Menu - Opening Bytes Window](img/fig1.png) +

Figure 1: Navigating to Window -> Bytes: CTF-01.bin in the Ghidra menu bar.

+ +4. Dock the **Bytes** window side-by-side with your **Listing** window so both panels are simultaneously visible on your screen. + +--- + +### Step 2: Locate the Target Instruction in the Listing Window + +Before making any modifications, navigate to the target function and identify the exact instruction bytes: + +1. Click inside the **Listing** window and press key **`G`** (Go To Address). +2. Enter the target address (for example, `0x100001FC`). +3. Observe the disassembled instruction and its opcode encoding: + +```assembly +100001fc 5e 2b cmp r3,#0x5e +``` + +![Target Instruction in Listing View](img/fig2.png) +

Figure 2: Listing view at offset 100001fc showing the initial instruction: cmp r3,#0x5e (bytes 5e 2b).

+ +#### Technical Breakdown of Opcode `5e 2b`: +In ARMv8-M Thumb-16 architecture, the compare-immediate instruction `cmp , #` is encoded as: +- Bit pattern: `0010 1nnn iiiiiiii` +- Opcode field (`00101`): Specifies `CMP` immediate. +- Register `r3` (`nnn = 011` binary): Specifies operand register `r3`. +- Upper byte: `0010 1011` binary = `0x2B`. +- Lower byte: `0x5E` (hex) = `94` decimal (the comparison threshold). +- Because ARM Cortex-M microcontrollers are **little-endian**, the low byte (`5E`) appears first in memory at address `0x100001FC`, followed by the high byte (`2B`) at address `0x100001FD`. +- To change the threshold from $94$ ($0\text{x}5E$) to $59$ ($0\text{x}3B$), we only need to alter byte `0x100001FC` from `5E` to `3B`! + +--- + +### Step 3: Clear the Code Bytes in the Listing Window (`C`) + +This is the critical step that prevents assembler context conflicts. Before editing a byte, the instruction must be cleared from Ghidra's active instruction database: + +1. In the **Listing** window, click directly on address **`100001fc`** (the row containing `cmp r3,#0x5e`). +2. Press the key **`C`** on your keyboard (or right-click and select **Clear Code Bytes**). +3. Notice that the instruction disassembly immediately clears into undefined raw bytes: + +```assembly +100001fc 5e ?? 5Eh ^ +100001fd 2b ?? 2Bh + +``` + +![Listing View after Clearing Code Bytes](img/fig3.png) +

Figure 3: Listing view after pressing 'C': the instruction at 100001fc is cleared to raw undefined bytes.

+ +By clearing the instruction first, Ghidra's database disarms the active context parser for this address. The subsequent `ite hi` instruction downstream is no longer linked to an active parsing state at this address. + +--- + +### Step 4: Enable Edit Mode and Modify the Byte in the Bytes Window + +Now that the address is cleared, modify the raw hex byte using the Bytes window: + +1. In the **Bytes** window toolbar, locate and click the **Pencil Icon** (**Toggle Edit Mode**). The icon highlights to indicate that byte-editing mode is now active. +2. Locate offset row **`100001f0`** in the Bytes window. +3. Move your cursor to column **`C`** (representing address `100001fc`). +4. Click on the byte **`5E`** and type the replacement value **`3B`**. +5. Notice that Ghidra immediately updates the byte to `3B` and highlights it in red to indicate an uncommitted edit. + +![Side-by-Side View of Listing and Bytes Window with Edit Mode Active](img/fig4.png) +

Figure 4: Side-by-side view showing the active pencil icon, the modified byte '3b' highlighted in red in the Bytes window, and the synchronized Listing window.

+ +6. Look at the **Listing** window. Address `100001fc` now reflects the new byte `3b` while remaining undefined: + +```assembly +100001fc 3b ?? 3Bh ; +100001fd 2b ?? 2Bh + +``` + +![Listing View showing Modified Byte before Disassembly](img/fig5.png) +

Figure 5: Listing view showing the modified byte '3b' at 100001fc ready for disassembly.

+ +--- + +### Step 5: Disassemble the Modified Instruction (`D`) + +With the desired byte safely written to memory, restore the disassembly: + +1. Click back into the **Listing** window. +2. Click directly on address **`100001fc`**. +3. Press the key **`D`** on your keyboard (or right-click and select **Disassemble**). +4. Ghidra immediately decodes the bytes `3b 2b` as Thumb-2 machine code: + +```assembly +100001fc 3b 2b cmp r3,#0x3b +``` + +5. **Verify Downstream Disassembly:** Inspect the instructions immediately following `0x100001FC`: + - `100001fe 8c bf ite hi` remains completely intact! + - `10000200 00 23 movhi r3,#0x0` remains intact! + - `10000202 01 23 movls r3,#0x1` remains intact! + - **Compare Site B at `0x1000020A` remains completely intact and visible!** + +No context conflict was triggered, no instructions were swallowed, and no 32-bit ARM decoding errors occurred. + +--- + +### Step 6: Repeat for Secondary Sites & Export Patched Firmware + +#### Repeating on Compare Site B: +In many defensive patches (such as `CTF-01`), redundant checks or dual comparison gates are enforced by the compiler: +1. In the **Listing** window, click address **`1000020a`** (`cmp r3,#0x5e`). +2. Press **`C`** to clear code bytes. +3. In the **Bytes** window at offset `1000020a`, change byte `5E` to **`3B`**. +4. In the **Listing** window, click back on **`1000020a`** and press **`D`** to disassemble. +5. Both Compare Site A and Compare Site B are now patched to `0x3B` (59 decimal)! + +#### Exporting the Patched Binary Image: +1. Click **File** in the Ghidra menu bar. +2. Select **Export Program** (or press key `O`). +3. Set **Format** to **Raw Bytes**. +4. Click the `...` button next to **Output File** and navigate to your project directory. +5. Set the filename (for example, `CTF-01_fixed.bin`). +6. Click **OK** to save the patched binary image to disk. + +#### Converting to UF2 and Flashing: +Convert the exported raw binary to the Raspberry Pi Pico 2 UF2 format using `uf2conv.py`: + +```bash +python3 uf2conv.py CTF-01_fixed.bin \ + --base 0x10000000 \ + --family 0xe48bff59 \ + --output CTF-01_fixed.uf2 +``` + +Hold the `BOOTSEL` button on your Raspberry Pi Pico 2, plug it into your workstation's USB port, and drag-and-drop `CTF-01_fixed.uf2` onto the `RP2350` drive to verify your patched firmware on physical hardware! + +--- + +## 4. Method Comparison & Reference Guide + +``` ++-----------------------------------------------------------------+ +| GHIDRA ARM THUMB-2 PATCHING METHODS MATRIX | +| | +| Method Downstream Safety IT-Block Safe Status | +| ----------------- ----------------- ------------- ------ | +| GUI Patch Inst. Fails (Swallows) No (Conflict) AVOID | +| TMode = 1 (Ctrl+R) Fails (Database) No (Exception) AVOID | +| Bytes Window (C/D) 100% Safe & Clean Yes (Disarmed) OPTIMAL | ++-----------------------------------------------------------------+ +``` + +
+ +### Keystroke Quick Reference Table + +| Step | Action | Window | Shortcut / Control | Result | +| :--- | :--- | :--- | :--- | :--- | +| **1** | Open Bytes Panel | Menu Bar | `Window` $\rightarrow$ `Bytes: ` | Displays raw hex grid | +| **2** | Locate Target | Listing | Press `G` $\rightarrow$ enter address | Cursor at target opcode | +| **3** | Clear Code Bytes | Listing | Press `C` | Instruction cleared to `??` | +| **4** | Enable Edit Mode | Bytes | Click **Pencil Icon** | Enables write mode | +| **5** | Modify Hex Byte | Bytes | Type new hex byte (`3B`) | Byte highlighted in red | +| **6** | Re-Disassemble | Listing | Click address $\rightarrow$ press `D` | Reassembles cleanly as Thumb-2 | +| **7** | Export Program | Menu Bar | `File` $\rightarrow$ `Export Program` | Saves patched `.bin` file | + +--- + +## 5. Key Takeaways & Best Practices + +1. **Thumb-2 Conditional State is Fragile in Ghidra:** The presence of `IT`/`ITE` blocks creates dynamic context register dependencies. High-level assembler dialogs fail because they attempt to re-evaluate downstream context over existing disassembly. +2. **Clear First (`C`), Edit Second, Disassemble Last (`D`):** Always clear the code bytes before modifying machine code in Ghidra. Clearing breaks the active context dependency graph and allows clean byte substitution. +3. **Always Verify Downstream Code:** After pressing `D`, scan the next 10 instructions to ensure downstream labels, branch targets, and conditional blocks were not disrupted. +4. **Export as Raw Bytes:** When flashing embedded microcontrollers like the RP2350, always export as **Raw Bytes** (`.bin`), never as ELF or PE, before converting to UF2. diff --git a/WEEK03/GHIDRA_PATCHING_TUTORIAL.pdf b/WEEK03/GHIDRA_PATCHING_TUTORIAL.pdf new file mode 100644 index 0000000..6a32f0d Binary files /dev/null and b/WEEK03/GHIDRA_PATCHING_TUTORIAL.pdf differ diff --git a/WEEK03/WEEK03-SLIDES.pdf b/WEEK03/WEEK03-SLIDES.pdf new file mode 100644 index 0000000..226ea8f Binary files /dev/null and b/WEEK03/WEEK03-SLIDES.pdf differ diff --git a/WEEK03/WEEK03.md b/WEEK03/WEEK03.md new file mode 100644 index 0000000..e8167db --- /dev/null +++ b/WEEK03/WEEK03.md @@ -0,0 +1,1663 @@ +# Week 3: Embedded System Analysis: Understanding the RP2350 Architecture w/ Comprehensive Firmware Analysis + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand how the RP2350 boots from the on-chip bootrom +- Know what the vector table is and why it's important +- Trace the complete boot sequence from power-on to `main()` +- Understand XIP (Execute In Place) and how code runs from flash +- Read and analyze the startup assembly code (`crt0.S`) +- Use GDB to examine the boot process step by step +- Use Ghidra to statically analyze the boot sequence +- Understand the difference between Thumb mode addressing and actual addresses + +## Review from Weeks 1-2 +This week builds on your GDB and Ghidra skills from previous weeks: + +- **GDB Commands** (`x`, `b`, `c`, `si`, `disas`, `i r`) - We'll use all of these to trace the boot process +- **Memory Layout** (Flash at `0x10000000`, RAM at `0x20000000`) - Understanding where code and data live +- **Registers** (`r0`-`r12`, SP, LR, PC) - We'll watch how they're initialized during boot +- **Ghidra Analysis** - Decompiling and understanding assembly in a visual tool +- **Thumb Mode** - Remember addresses with LSB=1 indicate Thumb code + +--- + +## The Code We're Analyzing + +Throughout this week, we'll continue working with our `0x0001_hello-world.c` program: + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + while (true) + printf("hello, world\r\n"); +} +``` + +But this week, we're going **deeper** - we'll understand everything that happens BEFORE `main()` even runs! How does the chip know where `main()` is? How does the stack get initialized? Let's find out! + +--- + +## Part 1: Understanding the Boot Process + +### What Happens When You Power On? + +When you plug in your Raspberry Pi Pico 2, a lot happens before your `main()` function runs! Think of it like waking up in the morning: + +1. **First, your alarm goes off** (Power is applied to the chip) +2. **You open your eyes** (The bootrom starts running) +3. **You check your phone** (The bootrom looks for valid code in flash) +4. **You get out of bed** (The bootrom jumps to your program) +5. **You brush your teeth, get dressed** (Startup code initializes everything) +6. **Finally, you start your day** (Your `main()` function runs!) + +Each of these steps has a corresponding piece of code. Let's explore them all! + +### The RP2350 Boot Sequence Overview + +``` ++-----------------------------------------------------------------+ +| STEP 1: Power On | +| - The Cortex-M33 core wakes up | +| - Execution begins at address 0x00000000 (Bootrom) | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| STEP 2: Bootrom Executes (32KB on-chip ROM) | +| - This code is burned into the chip - can't be changed! | +| - It looks for valid firmware in flash memory | +| - It scans the first 4 kB of the image for a valid IMAGE_DEF | +| (Datasheet §4.1, p. 338: 32KB ROM; §5.9.5, p. 429: IMAGE_DEF) | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| STEP 3: Flash XIP Setup (bootrom-managed) | +| - The bootrom configures the flash interface automatically | +| - Sets up XIP (Execute In Place) mode | +| - NOTE: Unlike RP2040, there is NO separate boot2 in flash! | +| (Datasheet §5.2, p. 375: "removal of a boot2 in the first | +| 256 bytes of the image") | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| STEP 4: Vector Table & Reset Handler | +| - Bootrom reads the vector table at 0x10000000 | +| - Gets the initial stack pointer from offset 0x00 | +| - Gets the reset handler address from offset 0x04 | +| - Jumps to the reset handler! | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| STEP 5: C Runtime Startup (crt0.S) | +| - Copies initialized data from flash to RAM | +| - Zeros out the BSS section | +| - Calls runtime_init() | +| - Finally calls main()! | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 2: The Bootrom - Where It All Begins + +### What is the Bootrom? + +The **bootrom** is a 32KB piece of code that is permanently burned into the RP2350 chip at the factory. You cannot change it - it's "mask ROM" (Read Only Memory). + +Think of the bootrom like the BIOS in your computer - it's the first thing that runs and is responsible for finding and loading your actual program. + +### Key Bootrom Facts + +| Property | Value | Description | +| ----------- | ------------- | ---------------------------------- | +| Size | 32 KB | Small but powerful | +| Location | `0x00000000` | The very first address in memory | +| Modifiable? | **NO** | Burned into silicon at the factory | +| Purpose | Boot the chip | Find and load your firmware | + +### What Does the Bootrom Do? + +1. **Initialize Hardware**: Sets up clocks, resets peripherals +2. **Check Boot Sources (Discovery)**: Scans configured boot sources (for this course: flash) to find a candidate firmware image region. +3. **Validate Firmware (Validation)**: Verifies that candidate by finding IMAGE_DEF start/end markers and parsing the block. +4. **Configure Flash**: Sets up the XIP interface +5. **Jump to Your Code**: Reads the vector table and jumps to your reset handler + +### The IMAGE_DEF Structure + +The bootrom looks for a special marker in your firmware called **IMAGE_DEF**. This tells the bootrom "Hey, there's valid code here!" + +Here's what it looks like in the Pico SDK: + +```assembly +.section .picobin_block, "a" // placed in flash +.word 0xffffded3 // PICOBIN_BLOCK_MARKER_START ← ROM looks for this! +.byte 0x42 // PICOBIN_BLOCK_ITEM_1BS_IMAGE_TYPE +.byte 0x1 // item is 1 word in size +.hword 0b0001000000100001 // SECURE mode (0x1021) +.byte 0xff // PICOBIN_BLOCK_ITEM_2BS_LAST +.hword 0x0001 // item is 1 word in size +.byte 0x0 // pad +.word 0x0 // relative pointer to next block (0 = loop to self) +.word 0xab123579 // PICOBIN_BLOCK_MARKER_END +``` + +**The magic numbers:** + +- `0xffffded3` = Start marker ("I'm a valid Pico binary!") +- `0xab123579` = End marker ("End of the header block") + +### See This Exact Block in Your ELF (Commands + Real Output) + +Use these commands to view the IMAGE_DEF bytes directly in the ELF: + +```cmd +arm-none-eabi-objdump -s --start-address=0x1000013c --stop-address=0x10000150 build/0x0001_hello-world.elf +arm-none-eabi-objdump -s --start-address=0x10000130 --stop-address=0x10000154 build/0x0001_hello-world.elf +arm-none-eabi-gdb build/0x0001_hello-world.elf -ex "x/20bx 0x1000013c" -ex quit +``` + +Actual output from this lesson build: + +```text +build/0x0001_hello-world.elf: file format elf32-littlearm + +Contents of section .text: + 1000013c 42012110 ff010000 b01b0000 793512ab B.!.........y5.. + 1000014c 4ff00000 O... + +build/0x0001_hello-world.elf: file format elf32-littlearm + +Contents of section .text: + 10000130 a0010010 90a31ae7 d3deffff 42012110 ............B.!. + 10000140 ff010000 b01b0000 793512ab 4ff00000 ........y5..O... + 10000150 1e490860 .I.` +``` + +Command 1 explained (`--start-address=0x1000013c --stop-address=0x10000150`): + +- Starts at `0x1000013c`, so it does **not** include the start marker at `0x10000138` (`d3deffff`). +- Shows IMAGE_DEF body fields and the end marker: + - `42012110` = `42 01 21 10` (item type/size + secure mode field) + - `ff010000` = last-item marker + size + pad + - `b01b0000` = next word in the block payload for this build + - `793512ab` = `PICOBIN_BLOCK_MARKER_END` (`0xab123579` in little-endian) +- `4ff00000` at `0x1000014c` is already the next instruction word after IMAGE_DEF. + +Command 2 explained (`--start-address=0x10000130 --stop-address=0x10000154`): + +- Starts earlier, so it captures context **and** both IMAGE_DEF markers. +- `a0010010 90a31ae7` = binary-info context before IMAGE_DEF. +- `d3deffff` at `0x10000138` = `PICOBIN_BLOCK_MARKER_START`. +- `793512ab` at `0x10000148` = `PICOBIN_BLOCK_MARKER_END`. +- `4ff00000 1e490860` = code words after the IMAGE_DEF block. +- This command proves the full block location for this build: `0x10000138` to `0x1000014b`. + +Important: IMAGE_DEF offset can vary by build. In this build, the start marker `d3deffff` +is at `0x10000138` (not `0x1000013c`), so always search for the marker bytes instead of +assuming a fixed address. + +--- + +## Part 3: Understanding XIP (Execute In Place) + +> **REVIEW:** In Week 1, we learned that our code lives at `0x10000000` in flash memory. We used `x/1000i 0x10000000` to find our `main` function. Now we'll understand WHY code is at this address! + +### What is XIP? + +**XIP (Execute In Place)** means the processor can run code directly from flash memory without copying it to RAM first. + +Think of it like reading a book: + +- **Without XIP**: You photocopy every page into a notebook, then read from the notebook +- **With XIP**: You just read directly from the book! + +### Why Use XIP? + +| Advantage | Explanation | +| ----------- | ------------------------------------------- | +| Saves RAM | Code stays in flash, RAM is free for data | +| Faster Boot | No need to copy entire program to RAM first | +| Simpler | Less memory management needed | + +### XIP Memory Address + +The XIP flash region starts at address `0x10000000`. This is where your compiled code lives! + +``` ++-----------------------------------------------------+ +| Address: 0x10000000 (XIP Base) | +| +-------------------------------------------------+| +| | Vector Table (first thing here!) || +| | - Stack Pointer at offset 0x00 || +| | - Reset Handler at offset 0x04 || +| | - Other exception handlers... || +| +-------------------------------------------------+| +| | Your Code || +| | - Reset handler || +| | - main() function || +| | - Other functions || +| +-------------------------------------------------+| +| | Read-Only Data || +| | - Strings like "hello, world" || +| | - Constant values || +| +-------------------------------------------------+| ++-----------------------------------------------------+ +``` + +--- + +## Part 4: The Vector Table - The CPU's Instruction Manual + +### What is the Vector Table? + +The **vector table** is a list of addresses at the very beginning of your program. It tells the CPU: + +1. Where to set the stack pointer +2. Where to start executing code (reset handler) +3. Where to go when errors or interrupts happen + +Think of it like the table of contents in a book - it tells you where to find everything! + +### Vector Table Layout + +The vector table lives at `0x10000000` and looks like this: + +| Offset | Address | Content | Description | +| ------ | ------------ | ------------ | --------------------------- | +| `0x00` | `0x10000000` | `0x20082000` | Initial Stack Pointer (SP) | +| `0x04` | `0x10000004` | `0x1000015d` | Reset Handler (entry point) | +| `0x08` | `0x10000008` | `0x1000011b` | NMI Handler | +| `0x0C` | `0x1000000C` | `0x1000011d` | HardFault Handler | + +### Understanding Thumb Mode Addressing + +**Important Concept Alert!** + +Look at the reset handler address: `0x1000015d`. Notice it ends in `d` (an odd number)? + +On ARM Cortex-M processors, all code runs in **Thumb mode**. The processor uses the **least significant bit (LSB)** of an address to indicate this: + +| LSB | Mode | Meaning | +| ---------- | ----- | ----------------------------------------- | +| `1` (odd) | Thumb | "This is Thumb code" | +| `0` (even) | ARM | "This is ARM code" (not used on Cortex-M) | + +So `0x1000015d` means: + +- The actual code is at `0x1000015c` (even address) +- The `+1` tells the processor "use Thumb mode" + +**GDB vs Ghidra:** + +- GDB shows `0x1000015d` (with Thumb bit) +- Ghidra shows `0x1000015c` (actual instruction address) +- Both are correct! They're just displaying it differently. + +--- + +## Part 5: The Linker Script - Memory Mapping + +### What is a Linker Script? + +The **linker script** tells the compiler where to put different parts of your program in memory. It's like an architect's blueprint for memory! + +### Finding the Linker Script + +On Windows with the Pico SDK 2.2.0, you'll find it at: +``` +C:\Users\\.pico-sdk\sdk\2.2.0\src\rp2_common\pico_crt0\rp2350\memmap_default.ld +``` + +### Key Parts of the Linker Script + +```ld +MEMORY +{ + INCLUDE "pico_flash_region.ld" + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} +``` + +**What this means:** + +| Region | Start Address | Size | Purpose | +| --------- | ------------- | -------- | -------------------------------------------- | +| Flash | `0x10000000` | (varies) | Your code (XIP) | +| RAM | `0x20000000` | 512 KB | Main striped SRAM | +| SCRATCH_X | `0x20080000` | 4 KB | SRAM8: shared, non-striped SRAM | +| SCRATCH_Y | `0x20081000` | 4 KB | SRAM9: shared, non-striped SRAM | + +`SCRATCH_X` and `SCRATCH_Y` are linker-script names for SRAM8 and SRAM9. They +are **not hardware-assigned to Core 0 or Core 1**: both cores can access both +banks. Software may reserve either bank for per-core data to reduce bank +contention. This particular linker script selects `SCRATCH_Y` for the Core 0 +stack; that is a software allocation choice, not a property of SRAM9. + +### Where Does This Build's Core 0 Stack Come From? + +The linker script calculates the initial stack pointer: + +```ld +__StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); +``` + +Let's do the math: + +- `ORIGIN(SCRATCH_Y)` = `0x20081000` +- `LENGTH(SCRATCH_Y)` = `0x1000` (4 KB) +- `__StackTop` = `0x20081000` + `0x1000` = **`0x20082000`** + +This value (`0x20082000`) is what we see at offset `0x00` in the vector table. +It is the initial Core 0 stack pointer for this build because its linker script +chose `SCRATCH_Y`; it does not reserve `SCRATCH_Y` for Core 0 in hardware. + +--- + +## Part 6: Setting Up Your Environment (GDB - Dynamic Analysis) + +> **REVIEW:** This setup is identical to Weeks 1-2. If you need a refresher on OpenOCD and GDB connection, refer back to Week 1 Part 4 or Week 2 Part 5. + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board with debug probe connected +2. OpenOCD installed and configured +3. GDB (`arm-none-eabi-gdb`) installed +4. The "hello-world" binary loaded on your Pico 2 +5. Access to the Pico SDK source files (for reference) + +### Starting the Debug Session + +**Terminal 1 - Start OpenOCD:** + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +**Terminal 2 - Start GDB:** + +```cmd +arm-none-eabi-gdb build\0x0001_hello-world.elf +``` + +**Connect to target:** + +```gdb +(gdb) target extended-remote :3333 +(gdb) monitor reset halt +``` + +--- + +## Part 7: Hands-On GDB Tutorial - Examining the Vector Table + +> **REVIEW:** We're using the same `x` (examine) command from Week 1. Remember: `x/Nx` shows N hex values, `x/Ni` shows N instructions, `x/s` shows strings. + +### Step 1: Examine the Vector Table + +Let's look at the first 4 entries of the vector table at `0x10000000`: + +**Type this command:** + +```gdb +(gdb) x/4x 0x10000000 +``` + +**What this command means:** + +- `x` = examine memory (Week 1 review!) +- `/4x` = show 4 values in hexadecimal +- `0x10000000` = the address of the vector table + +**You should see:** + +``` +0x10000000 <__vectors>: 0x20082000 0x1000015d 0x1000011b 0x1000011d +``` + +### Step 2: Understanding What We See + +> **REVIEW:** In Weeks 1-2, we saw both `sp = 0x20082000` at the clean breakpoint at `main` and lower values like `0x20081fc8` or `0x20081ff8` after additional stack activity. Here we are looking at the *initial* stack pointer from the vector table before any code runs. + +Let's decode each value: + +| Address | Value | Meaning | +| ------------ | ------------ | ---------------------------------------- | +| `0x10000000` | `0x20082000` | Initial Stack Pointer - top of SCRATCH_Y | +| `0x10000004` | `0x1000015d` | Reset Handler + 1 (Thumb bit) | +| `0x10000008` | `0x1000011b` | NMI Handler + 1 (Thumb bit) | +| `0x1000000C` | `0x1000011d` | HardFault Handler + 1 (Thumb bit) | + +**Key Insight:** The stack pointer (`0x20082000`) is exactly what the linker script calculated! And all the handler addresses have their LSB set to `1` for Thumb mode. + +### Step 3: Verify the Stack Pointer Calculation + +Let's confirm our math by examining what's at `0x10000000`: + +**Type this command:** + +```gdb +(gdb) x/x 0x10000000 +``` + +**You should see:** + +``` +0x10000000 <__vectors>: 0x20082000 +``` + +This matches: + +- `SCRATCH_Y` starts at `0x20081000` +- `SCRATCH_Y` is 4 KB (`0x1000` bytes) +- `0x20081000` + `0x1000` = `0x20082000` + +--- + +## Part 8: Examining the Reset Handler + +> **REVIEW:** We used `x/5i` extensively in Weeks 1-2 to examine our `main` function. Now we'll use the same technique to examine the code that runs BEFORE `main`! + +### Step 4: Disassemble the Reset Handler + +The reset handler is where execution begins after the bootrom hands off control. Let's look at it: + +**Type this command:** + +```gdb +(gdb) x/3i 0x1000015c +``` + +**Note:** We use `0x1000015c` (even) not `0x1000015d` (odd) because we want to see the actual instructions! + +**You should see:** + +``` + 0x1000015c <_reset_handler>: mov.w r0, #3489660928 @ 0xd0000000 + 0x10000160 <_reset_handler+4>: ldr r0, [r0, #0] + 0x10000162 <_reset_handler+6>: + cbz r0, 0x1000016a +``` + +### Step 5: Understanding the Reset Handler + +Let's break down what these first three instructions do: + +**Instruction 1: `mov.w r0, #0xd0000000`** + +This loads the address `0xd0000000` into register `r0`. But what's at that address? + +That's the **SIO (Single-cycle I/O) base address**! The SIO block contains a special register called **CPUID** that tells us which core we're running on. + +**Instruction 2: `ldr r0, [r0, #0]`** + +This reads the value at address `0xd0000000` (the CPUID register) into `r0`. + +| Core | CPUID Value | +| ------ | ----------- | +| Core 0 | `0` | +| Core 1 | `1` | + +**Instruction 3: `cbz r0, 0x1000016a`** + +This is "Compare and Branch if Zero". If `r0` is `0` (meaning we're on Core 0), branch to `0x1000016a` to continue with startup. Otherwise, we're on Core 1 and need to handle that differently. + +### Why Check Which Core We're On? + +The RP2350 has **two cores**, but only **Core 0** should run the startup code! If both cores tried to initialize the same memory and peripherals, chaos would ensue. + +So the reset handler checks: + +- **Core 0?** -> Continue with startup +- **Core 1?** -> Go back to the bootrom and wait + +--- + +## Part 9: The Complete Reset Handler Flow + +### Step 6: Examine More of the Reset Handler + +Let's look at more instructions to see the full picture: + +**Type this command:** + +```gdb +(gdb) x/20i 0x1000015c +``` + +**You should see:** + +``` + 0x1000015c <_reset_handler>: mov.w r0, #3489660928 @ 0xd0000000 + 0x10000160 <_reset_handler+4>: ldr r0, [r0, #0] + 0x10000162 <_reset_handler+6>: + cbz r0, 0x1000016a + 0x10000164 : mov.w r0, #0 + 0x10000168 : + b.n 0x10000150 <_enter_vtable_in_r0> + 0x1000016a : + add r4, pc, #52 @ (adr r4, 0x100001a0 ) + 0x1000016c : ldmia r4!, {r1, r2, r3} + 0x1000016e : cmp r1, #0 + 0x10000170 : + beq.n 0x10000178 + 0x10000172 : + bl 0x1000019a + 0x10000176 : + b.n 0x1000016c + 0x10000178 : + ldr r1, [pc, #84] @ (0x100001d0 ) + 0x1000017a : + ldr r2, [pc, #88] @ (0x100001d4 ) + 0x1000017c : movs r0, #0 + 0x1000017e : + b.n 0x10000182 + 0x10000180 : stmia r1!, {r0} + 0x10000182 : cmp r1, r2 + 0x10000184 : bne.n 0x10000180 + 0x10000186 : + ldr r1, [pc, #80] @ (0x100001d8 ) + 0x10000188 : blx r1 +``` + +### Step 7: Understanding the Startup Phases + +The reset handler performs several phases: + +``` ++-----------------------------------------------------------------+ +| PHASE 1: Core Check (0x1000015c - 0x10000168) | +| - Check CPUID to see which core we're on | +| - If not Core 0, go back to bootrom | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| PHASE 2: Data Copy Setup & Loop (0x1000016a - 0x10000176) | +| - Set up the data_cpy_table pointer and load each copy triplet | +| - Copy initialized variables from flash to RAM | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| PHASE 3: BSS Setup & Clear (0x10000178 - 0x10000184) | +| - Load the BSS start/end addresses into r1 and r2 | +| - GDB labels those literals as `data_cpy_table+48/+52` | +| - Zero out all uninitialized global variables | ++-----------------------------------------------------------------+ + ↓ ++-----------------------------------------------------------------+ +| PHASE 4: Platform Entry Begins (0x10000186 - 0x10000188 shown) | +| - Load the runtime_init() pointer from the table | +| - Branch to runtime_init() with `blx r1` | +| - `main()` and `exit()` appear a few instructions later | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 10: Understanding the Data Copy Phase + +### What is the Data Copy Phase? + +> **REVIEW:** In Week 2, we learned that flash is read-only and SRAM is read-write. That's why the startup code must COPY initialized variables from flash to RAM - they can't be modified in flash! + +When you write C code like this: + +```c +int my_counter = 42; // Initialized global variable +``` + +The value `42` is stored in flash memory (because flash is non-volatile). But variables need to live in RAM to be modified! So the startup code **copies** these initial values from flash to RAM. + +### Step 8: Find the Data Copy Table + +The data copy table contains entries that describe what to copy where. Let's examine it: + +**Type this command:** + +```gdb +(gdb) x/12x 0x100001a0 +``` + +**You should see something like:** + +``` +0x100001a0 : 0x10001b4c 0x20000110 0x200002ac 0x10001ce8 +0x100001b0 : 0x20080000 0x20080000 0x10001ce8 0x20081000 +0x100001c0 : 0x20081000 0x00000000 0x00004770 0xe000ed08 +``` + +The data_cpy_table contains multiple entries. Each entry has three values: + +1. **Source address** (in flash) +2. **Destination address** (in RAM) +3. **End address** (where to stop copying) + +In the output above, we see: + +- **First entry**: `0x10001b4c` (source), `0x20000110` (dest), `0x200002ac` (end) +- **Second entry starts**: `0x10001ce8` (source of next entry), ... + +The table ends with an entry where the source address is `0x00000000` (which signals "no more entries"). + +### Step 9: Watch the Data Copy Loop + +The data copy loop works like this: + +``` ++---------------------------------------------+ +| 1. Load source, dest, end from table | +| 2. If source == 0, we're done | +| 3. Otherwise, copy word by word | +| 4. Go back to step 1 for next entry | ++---------------------------------------------+ +``` + +The actual code (starting at **`0x1000016c`** in the reset handler): + +```assembly +0x1000016c : ldmia r4!, {r1, r2, r3} +0x1000016e : cmp r1, #0 +0x10000170 : +beq.n 0x10000178 +0x10000172 : +bl 0x1000019a +0x10000176 : +b.n 0x1000016c +``` + +> Tip: **Note:** You can see this code in **Step 6** earlier where we examined the reset handler with `x/20i 0x1000015c`. + +--- + +## Part 11: Understanding the BSS Clear Phase + +### What is BSS? + +**BSS** stands for "Block Started by Symbol" (historical name). It's the section of memory for **uninitialized global variables**. + +When you write: + +```c +int my_counter; // Uninitialized - will be in BSS +``` + +The C standard says this variable **must start at zero**. The BSS clear phase zeros out this entire region. + +### Step 10: Examine the BSS Clear Loop + +**Type this command:** + +```gdb +(gdb) x/5i 0x10000178 +``` + +**You should see:** + +``` +0x10000178 : +ldr r1, [pc, #84] @ (0x100001d0 ) +0x1000017a : +ldr r2, [pc, #88] @ (0x100001d4 ) +0x1000017c : movs r0, #0 +0x1000017e : +b.n 0x10000182 +0x10000180 : stmia r1!, {r0} +``` + +The first two `ldr` instructions are still part of the **BSS clear setup**, even though GDB shows the source words as `data_cpy_table+48` and `data_cpy_table+52`. That label means the two literal words live in the same nearby constant block as the copy-table entries; it does **not** mean the code is still performing `.data` copies. At this point, `r1` becomes the BSS start address, `r2` becomes the BSS end address, and the loop beginning at `0x10000180` zeros that range. + +### Understanding the Loop + +``` ++---------------------------------------------+ +| r1 = start of BSS section | +| r2 = end of BSS section | +| r0 = 0 | +| | +| LOOP: | +| Store 0 at address r1 | +| Increment r1 by 4 bytes | +| If r1 != r2, repeat | ++---------------------------------------------+ +``` + +--- + +## Part 12: Examining Exception Handlers + +### Step 11: Look at the Default Exception Handlers + +What happens if an exception occurs (like a HardFault)? Let's look: + +**Type this command:** + +```gdb +(gdb) x/10i 0x10000110 +``` + +**You should see:** + +``` +0x10000110 : mrs r0, IPSR +0x10000114 : subs r0, #16 +0x10000116 : bkpt 0x0000 +0x10000118 : bkpt 0x0000 +0x1000011a : bkpt 0x0000 +0x1000011c : bkpt 0x0000 +0x1000011e : bkpt 0x0000 +0x10000120 : bkpt 0x0000 +0x10000122 : bkpt 0x0000 +0x10000124 <__default_isrs_end>: + @ instruction: 0xebf27188 +``` + +### What is `bkpt`? + +The `bkpt` instruction is a **breakpoint**. When executed, it stops the processor and triggers the debugger! + +These are the **default** exception handlers - they just stop the program so you can debug. In your own code, you can override these with real handlers. + +### Why So Many Handlers? + +Each type of exception has its own handler: + +| Handler | Purpose | +| --------------- | ------------------------------------------ | +| `isr_nmi` | Non-Maskable Interrupt (can't be disabled) | +| `isr_hardfault` | Serious error (bad memory access, etc.) | +| `isr_svcall` | Supervisor Call (used by RTOSes) | +| `isr_pendsv` | Pendable Supervisor (also for RTOSes) | +| `isr_systick` | System Timer tick interrupt | + +--- + +## Part 13: Finding Where Main is Called + +### Step 12: Trace Reset Handler to `main` + +Start at the **application** Cortex-M vector table in XIP flash. The RP2350 +bootrom occupies `0x00000000`; it is not this firmware's vector table. Word +`0x10000000` is this image's initial stack pointer, and word `0x10000004` is +the **reset-handler pointer** loaded into `pc` when the bootrom enters the +application: + +```gdb +(gdb) x/2wx 0x10000000 +0x10000000 <__vectors>: 0x20082000 0x1000015d +``` + +`0x1000015d` is a Thumb function pointer: bit 0 is set to indicate Thumb +state. Clear that bit before disassembly, so the reset handler's first +instruction address is `0x1000015c`. Then continue through startup until +`platform_entry`: + +```gdb +(gdb) x/10i 0x1000015c +(gdb) x/x 0x10000004 +0x10000004 <__vectors+4>: 0x1000015d +(gdb) b platform_entry +(gdb) c +``` + +At `platform_entry`, the three `ldr r1` / `blx r1` pairs are indirect calls: + +```text +0x10000186 : ldr r1, [pc, #80] +0x10000188 : blx r1 (first call) +0x1000018a : ldr r1, [pc, #80] +0x1000018c : blx r1 (second call) +0x1000018e : ldr r1, [pc, #80] +0x10000190 : blx r1 (third call) +``` + +### Prove That the Second Call Is `main` + +Stop at the second `blx r1`. `r1` holds the target; inspect it and then +disassemble that address: + +```gdb +(gdb) b *0x1000018c +(gdb) c + +Thread 1 "rp2350.dap.core0" hit Breakpoint 1, platform_entry () + at C:/Users/assem.KEVINTHOMAS/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_crt0/crt0.S:515 +515 blx r1 +(gdb) x/x 0x1000018c +0x1000018c : 0x49144788 +(gdb) disas +Dump of assembler code for function platform_entry: + 0x10000186 <+0>: ldr r1, [pc, #80] @ (0x100001d8 ) + 0x10000188 <+2>: blx r1 + 0x1000018a <+4>: ldr r1, [pc, #80] @ (0x100001dc ) +=> 0x1000018c <+6>: blx r1 + 0x1000018e <+8>: ldr r1, [pc, #80] @ (0x100001e0 ) + 0x10000190 <+10>: blx r1 + 0x10000192 <+12>: bkpt 0x0000 + 0x10000194 <+14>: b.n 0x10000192 +End of assembler dump. +(gdb) x/x 0x1000018c +0x1000018c : 0x49144788 +(gdb) x/x $r1 +0x10000235
: 0x99f001b5 +(gdb) disas $r1 +Dump of assembler code for function main: + 0x10000234 <+0>: push {r3, lr} + 0x10000236 <+2>: bl 0x1000156c + 0x1000023a <+6>: ldr r0, [pc, #8] @ (0x10000244 ) + 0x1000023c <+8>: bl 0x100015fc <__wrap_puts> + 0x10000240 <+12>: b.n 0x1000023a + 0x10000242 <+14>: nop + 0x10000244 <+16>: adds r4, r1, r7 + 0x10000246 <+18>: asrs r0, r0, #32 +End of assembler dump. +(gdb) x/x 0x100001dc +0x100001dc : 0x10000235 +``` + +`x/x $r1` reports `0x10000235
` because Thumb function pointers have +bit 0 set. The actual instruction starts at `0x10000234`, as `disas $r1` +shows. The preceding `ldr r1, [pc, #80]` reads the literal-pool word at +`0x100001dc`; `x/x 0x100001dc` confirms that word is `0x10000235`. +This proves that the **second** indirect call enters `main()`. + +The first call performs runtime initialization. When `main()` returns, the +third call enters the SDK exit path; the following `bkpt` catches the +unexpected case where that exit path returns. + +### Step 13: Set a Breakpoint at Main + +> **REVIEW:** We've used `b main` and `b *ADDRESS` many times in Weeks 1-2. This is the same technique! + +Let's verify we understand the boot process by setting a breakpoint at main: + +**Type this command:** + +```gdb +(gdb) b main +``` + +**You should see:** + +``` +Breakpoint 1 at 0x10000234: file C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c, line 5. +Note: automatically using hardware breakpoints for read-only addresses. +``` + +**Now continue:** + +```gdb +(gdb) c +``` + +**You should see:** + +``` +Continuing. + +Thread 1 "rp2350.cm0" hit Breakpoint 1, main () + at C:/Users/assem.KEVINTHOMAS/OneDrive/Documents/Embedded-Hacking/0x0001_hello-world/0x0001_hello-world.c:5 +5 stdio_init_all(); +(gdb) +``` + + We've traced the entire boot process from power-on to `main()`! + +--- + +## Part 14: Understanding the Binary Info Header + +### Step 14: Examine the Binary Info Header + +Between the default ISRs and the reset handler, there's a special data structure called the **binary info header**. Let's look at it: + +**Type this command:** + +```gdb +(gdb) x/5x 0x10000138 +``` + +**You should see:** + +``` +0x10000138 <__binary_info_header_end>: 0xffffded3 0x10210142 0x000001ff 0x00001bb0 +0x10000148 <__binary_info_header_end+16>: 0xab123579 +``` + +### Decoding the Binary Info Header + +| Address | Value | Meaning | +| ------------ | ------------ | ----------------------------------------- | +| `0x10000138` | `0xffffded3` | Start marker (PICOBIN_BLOCK_MARKER_START) | +| `0x1000013c` | `0x10212142` | Image type descriptor | +| `0x10000140` | `0x000001ff` | Item header/size field | +| `0x10000144` | `0x00001bb0` | Link to next block or data | +| `0x10000148` | `0xab123579` | End marker (PICOBIN_BLOCK_MARKER_END) | + +**Why does GDB show this as instructions?** + +GDB doesn't know this is data, not code! It tries to disassemble it as Thumb instructions, which results in nonsense. This is why you'll see things like: + +```gdb +(gdb) x/i 0x10000138 +``` + +``` + 0x10000138 <__binary_info_header_end>: udf #211 @ 0xd3 +``` + +That's not real code - it's the magic number `0xffffded3` being misinterpreted! + +--- + +## Part 15: Static Analysis with Ghidra - Examining the Boot Sequence + +> **REVIEW:** In Week 1, we set up a Ghidra project and analyzed our hello-world binary. Now we'll use Ghidra to understand the boot sequence from a static analysis perspective! + +### Why Use Ghidra for Boot Analysis? + +While GDB is excellent for dynamic analysis (watching code execute), Ghidra excels at: + +- **Seeing the big picture** - Understanding code flow without running it +- **Cross-references** - Finding all places that call a function +- **Decompilation** - Seeing C-like code even for assembly routines +- **Annotation** - Adding notes and renaming functions for clarity + +### Step 15: Open Your Project in Ghidra + +> **REVIEW:** If you haven't created the project yet, refer back to Week 1 Part 5 for setup instructions. + +1. Launch Ghidra and open your `0x0001_hello-world` project +2. Double-click on the `.elf` file to open it in the CodeBrowser +3. If prompted to auto-analyze, click **Yes** + +### Step 16: Navigate to the Vector Table + +1. In the **Navigation** menu, select **Go To...** +2. Type `0x10000000` and press Enter +3. You should see the vector table data + +**What you'll see in the Listing view:** + +``` + // + // .text + // SHT_PROGBITS [0x10000000 - 0x100019cb] + // ram:10000000-ram:100019cb + // + assume spsr = 0x0 (Default) + __vectors XREF[4]: Entry Point (*) , + __flash_binary_start runtime_init_install_ram_vector_ + __VECTOR_TABLE _elfProgramHeaders::00000028 (*) , + __logical_binary_start _elfSectionHeaders::00000034 (*) + 10000000 00 undefine 00h + 10000001 20 ?? 20h + 10000002 08 ?? 08h + 10000003 20 ?? 20h + 10000004 5d ?? 5Dh ] ? -> 1000015d + 10000005 01 ?? 01h + 10000006 00 ?? 00h + 10000007 10 ?? 10h + 10000008 1b ?? 1Bh ? -> 1000011b + 10000009 01 ?? 01h + 1000000a 00 ?? 00h + 1000000b 10 ?? 10h + 1000000c 1d ?? 1Dh ? -> 1000011d + 1000000d 01 ?? 01h + 1000000e 00 ?? 00h + 1000000f 10 ?? 10h +... +``` + +> Tip: **Notice:** Ghidra shows the vector table data as individual bytes by default. You can see it has labeled the start as `__vectors`, `__flash_binary_start`, `__VECTOR_TABLE`, and `__logical_binary_start`. The arrows (like `? -> 1000015d`) show that Ghidra recognizes these bytes as pointers to code addresses! To see the data formatted as 32-bit addresses instead of bytes, you can right-click and retype the data. + +### Step 17: Navigate to the Reset Handler + +1. In the Symbol Tree panel (left side), expand **Functions** +2. Find and click on `_reset_handler` (or search for it) +3. Alternatively, double-click on `_reset_handler` in the vector table listing + +**What you'll see in the Decompile view (right panel):** + +Ghidra will show you a decompiled version of the reset handler. While it won't be perfect C code (since this is hand-written assembly), it helps visualize the flow: + +```c +void _reset_handler(void) + +{ + bool bVar1; + undefined4 uVar2; + int iVar3; + undefined4 *puVar4; + int *piVar5; + int *piVar6; + int *piVar7; + + if (_DAT_d0000000 != 0) { + _DAT_e000ed08 = 0; + bVar1 = (bool)isCurrentModePrivileged(); + if (bVar1) { + setMainStackPointer(_gpio_set_function_masked64); + } + /* WARNING: Could not recover jumptable at 0x1000015a. Too many branches */ + /* WARNING: Treating indirect jump as call */ + (*pcRam00000004)(8,_gpio_set_function_masked64); + return; + } + piVar5 = &data_cpy_table; + uVar2 = 0; + while( true ) { + iVar3 = *piVar5; + piVar6 = piVar5 + 1; + piVar7 = piVar5 + 2; + piVar5 = piVar5 + 3; + if (iVar3 == 0) break; + uVar2 = data_cpy(uVar2,iVar3,*piVar6,*piVar7); + } + for (puVar4 = (undefined4 *)&__TMC_END__; puVar4 != (undefined4 *)&end; puVar4 = puVar4 + 1) { + *puVar4 = 0; + } + runtime_init(); + iVar3 = main(); + /* WARNING: Subroutine does not return */ + exit(iVar3); +} +``` + +### Step 18: Trace the Path to Main + +Use the same evidence chain as GDB, but statically in the Listing view: + +1. In the Symbol Tree, find the `main` function at `0x10000234`. +2. Right-click `main` and select **References -> Show References to main**. +3. Double-click the reference at `0x1000018c` to jump to the second `blx r1`. +4. Select the instruction immediately above it: `ldr r1,[DAT_100001dc]` at + `0x1000018a`. +5. Double-click `DAT_100001dc`, or press **G** and enter `0x100001dc`. + +**You should see:** + +| Location | Type | Label | +| ------------------------- | ---- | ------------------ | +| `1000018c` | CALL | `blx r1` (to main) | + +At `0x100001dc`, Ghidra shows the literal-pool value `0x10000235`. That is +the Thumb function pointer loaded into `r1` immediately before the call. +Clear bit 0 to obtain the actual first instruction address: + +```text +0x10000235 (Thumb function pointer; bit 0 is set) +0x10000234 (main's first instruction; bit 0 cleared) +``` + +This proves the second indirect call at `0x1000018c` reaches `main`. + +### Step 19: Examine Platform Entry + +In Ghidra, look at `platform_entry`: + +**Listing View:** +``` + platform_entry + crt0.S:512 (2) + 10000186 14 49 ldr r1,[DAT_100001d8 ] = 1000137Dh + crt0.S:513 (2) + 10000188 88 47 blx r1=>runtime_init void runtime_init(void) + crt0.S:514 (2) + 1000018a 14 49 ldr r1,[DAT_100001dc ] = 10000235h + crt0.S:515 (2) + 1000018c 88 47 blx r1=>main int main(void) + crt0.S:516 (2) + 1000018e 14 49 ldr r1,[DAT_100001e0 ] = 10001375h + crt0.S:517 (2) + 10000190 88 47 blx r1=>exit void exit(int status) + LAB_10000192 XREF[1]: 10000194 (j) + crt0.S:521 (2) + 10000192 00 be bkpt 0x0 + crt0.S:522 (2) + 10000194 fd e7 b LAB_10000192 +``` + +The `DAT_100001dc = 10000235h` annotation is the static proof. The preceding +`ldr` loads that Thumb function pointer into `r1`; the following `blx r1` at +`0x1000018c` calls it. Ghidra clears the Thumb bit and labels the target +`main` at `0x10000234`. + +> **Key Insight:** The reset vector identifies the reset handler, the reset +> handler reaches `platform_entry`, and this literal-pool entry proves that +> `platform_entry`'s second indirect call reaches `main`. + +### Step 20: Create a Boot Sequence Graph + +Ghidra can visualize the call flow: + +1. With `_reset_handler` selected, go to **Window -> Function Call Graph** +2. This shows a visual graph of all function calls from the reset handler +3. You will see `_reset_handler` at the top with arrows going down to its four direct callees: `data_cpy`, `runtime_init`, `main`, and `exit` + +### Comparing GDB and Ghidra for Boot Analysis + +| Aspect | GDB (Dynamic) | Ghidra (Static) | +| ------ | ------------- | --------------- | +| **Sees runtime values** | Yes - register contents, memory | No - must infer from code | +| **Needs hardware** | Yes - Pico 2 must be connected | No - works offline | +| **Shows code flow** | Step-by-step execution | Full graph visualization | +| **Best for** | Watching what happens | Understanding structure | +| **Thumb bit handling** | Shows with +1 (0x1000015d) | Shows actual addr (0x1000015c) | + +### Ghidra Tips for Boot Analysis + +1. **Rename functions** - Right-click and rename unclear labels for future reference +2. **Add comments** - Press `;` to add inline comments explaining code +3. **Set data types** - Help Ghidra understand structures like the vector table +4. **Use bookmarks** - Mark important locations with **Ctrl+D** + +--- + +## Part 16: Summary and Review + +### The Complete Boot Sequence + +``` ++-----------------------------------------------------------------+ +| 1. POWER ON | +| Cortex-M33 begins at 0x00000000 (bootrom) | ++-----------------------------------------------------------------+ +| 2. BOOTROM | +| - Initializes hardware | +| - Configures flash XIP (no separate boot2 on RP2350) | +| - Finds IMAGE_DEF within first 4 kB of flash image | ++-----------------------------------------------------------------+ +| 3. VECTOR TABLE (0x10000000) | +| - Reads SP from offset 0x00 -> 0x20082000 | +| - Reads Reset Handler from offset 0x04 -> 0x1000015d | ++-----------------------------------------------------------------+ +| 4. RESET HANDLER (0x1000015c) | +| - Checks CPUID (Core 0 continues, Core 1 waits) | +| - Copies .data from flash to RAM | +| - Zeros .bss section | ++-----------------------------------------------------------------+ +| 5. PLATFORM ENTRY (0x10000186) | +| - Calls runtime_init() | +| - Calls main() | +| - Calls exit() when main returns | ++-----------------------------------------------------------------+ +| 6. YOUR CODE RUNS! | +| main() at 0x10000234 | ++-----------------------------------------------------------------+ +``` + +### Key Addresses to Remember + +| Address | What's There | +| ------------ | ---------------------------------------- | +| `0x00000000` | Bootrom (32KB, read-only) | +| `0x10000000` | Vector table / XIP flash start | +| `0x1000015c` | Reset handler (`_reset_handler`) | +| `0x10000234` | Your `main()` function | +| `0x20000000` | Start of RAM | +| `0x20082000` | Initial stack pointer (top of SCRATCH_Y) | +| `0xd0000000` | SIO base (CPUID register) | + +### Weeks 1-2 Concepts We Applied + +| Previous Concept | How We Used It This Week | +| ---------------- | ------------------------ | +| Memory Layout (Flash/RAM) | Understood why data must be copied from flash to RAM | +| GDB `x` command | Examined vector table, reset handler, and boot code | +| Breakpoints (`b`) | Set breakpoints to trace the boot sequence | +| Thumb Mode Addresses | Recognized LSB=1 means Thumb code in vector table | +| Stack Pointer | Saw how SP is initialized from the vector table | +| Ghidra Analysis | Used decompiler to understand boot flow | + +### GDB Commands Reference + +| Command | What It Does | New/Review | +| ---------------- | --------------------------------- | ---------- | +| `x/Nx ADDRESS` | Examine N hex values at ADDRESS | Review | +| `x/Ni ADDRESS` | Examine N instructions at ADDRESS | Review | +| `b main` | Set breakpoint at main function | Review | +| `b *ADDRESS` | Set breakpoint at exact address | Review | +| `si` | Step one instruction | Review | +| `c` | Continue execution | Review | +| `info registers` | Show all register values | Review | +| `monitor reset halt` | Reset and halt the target | Review | + +### Key Concepts + +| Concept | Definition | +| ---------------- | ----------------------------------------------------- | +| **Bootrom** | 32KB factory-programmed ROM that initializes the chip | +| **Vector Table** | List of addresses for SP and exception handlers | +| **XIP** | Execute In Place - running code directly from flash | +| **Thumb Mode** | ARM's compact instruction set (LSB=1 in addresses) | +| **BSS** | Section for uninitialized globals (must be zeroed) | +| **crt0.S** | C Runtime startup assembly file | +| **Reset Handler**| First function called after power-on/reset | +| **CPUID** | Register identifying which CPU core is executing | + +### Ghidra Actions We Used + +| Action | How to Access | Purpose | +| ------ | ------------- | ------- | +| Go To Address | Navigation -> Go To... | Jump to specific memory address | +| Show References | Right-click -> References -> Show References to | Find all callers of a function | +| Function Call Graph | Window -> Function Call Graph | Visualize call flow | +| Add Comment | Press `;` | Document your analysis | +| Rename Symbol | Right-click -> Rename | Give meaningful names to functions | + +--- + +--- + +## Key Takeaways + +### Building on Weeks 1-2 + +1. **GDB skills compound** - The `x`, `b`, `si`, and `disas` commands you learned in Weeks 1-2 are essential for understanding the boot process. Each week adds new applications for the same core skills. + +2. **Memory layout is fundamental** - Understanding flash vs RAM from Week 2 explains why startup code must copy data and zero BSS. + +3. **Ghidra complements GDB** - Dynamic analysis (GDB) shows what happens at runtime; static analysis (Ghidra) reveals the overall structure. Use both together! + +### New Concepts This Week + +4. **The boot process is deterministic** - Every RP2350 boots the same way, and understanding this helps you debug startup problems. + +5. **The bootrom can't be changed** - It's burned into silicon. Security features depend on this immutability. + +6. **The vector table is critical** - It tells the CPU where to start and how to handle errors. + +7. **Thumb mode uses the LSB** - Address `0x1000015d` means "run Thumb code at `0x1000015c`". + +8. **Startup code does essential work** - Copying data, zeroing BSS, and initializing the runtime all happen before `main()`. + +9. **Only Core 0 runs startup** - Core 1 waits in the bootrom until explicitly started. + +--- + +## Security Implications + +### How Boot Sequence Knowledge Applies to Security + +Understanding the boot process is critical for both attackers and defenders. Knowledge of how the RP2350 boots reveals potential attack vectors and defense strategies. + +#### Attack Scenarios + +| Scenario | Attack | Boot Process Knowledge Required | +| -------- | ------ | ------------------------------- | +| **Firmware Replacement** | Replace the entire flash image with malicious firmware | Understanding IMAGE_DEF structure and how bootrom validates firmware | +| **Vector Table Hijacking** | Modify the reset handler address to point to malicious code | Knowing the vector table location at `0x10000000` | +| **Bootrom Exploitation** | Find bugs in the immutable bootrom to bypass security | Understanding bootrom behavior and sequence | +| **Debug Port Attack** | Use SWD/JTAG to dump firmware or inject code | Knowledge of how to halt and examine the boot process | +| **Startup Code Modification** | Change how data is copied or BSS is cleared | Understanding crt0 and runtime_init sequences | + +#### Real-World Applications + +**Industrial Control Systems:** + +- An attacker with physical access could replace firmware to hide malicious behavior +- Understanding the boot sequence helps identify the earliest point where security checks can be added + +**IoT Devices:** + +- Compromised boot code could establish backdoors before the main application runs +- Secure boot implementations verify the vector table and reset handler integrity + +**Medical Devices:** + +- Boot-time attacks could modify critical safety parameters before device operation +- Understanding initialization helps implement tamper detection + +### Defense Strategies + +#### 1. Secure Boot Implementation + +``` ++-----------------------------------------------------+ +| SECURE BOOT FLOW | ++-----------------------------------------------------+ +| Bootrom (immutable) | +| ↓ | +| Verify IMAGE_DEF signature | +| ↓ | +| Verify application image signature | +| ↓ | +| If all valid: Jump to reset handler | +| If any invalid: Refuse to boot | ++-----------------------------------------------------+ +``` + +**Implementation:** Use cryptographic signatures to verify each boot stage before execution. + +#### 2. Debug Port Protection + +- **Production devices:** Permanently disable SWD/JTAG in final products +- **Debug authentication:** Require cryptographic challenge-response before allowing debug access +- **Fuses:** Blow hardware fuses to disable debug ports permanently + +#### 3. Flash Protection + +- **Read protection:** Enable flash read protection to prevent dumping firmware +- **Write protection:** Make critical boot sectors write-protected after initial programming +- **Encrypted storage:** Store firmware encrypted in flash + +#### 4. Memory Protection Unit (MPU) + +Configure the Cortex-M33's MPU to: + +- Mark code regions as execute-only (no reading code as data) +- Separate privileged and unprivileged memory regions +- Prevent execution from RAM regions (defend against code injection) + +#### 5. Boot-Time Integrity Checks + +```c +// Early in reset handler or runtime_init +void verify_boot_integrity(void) { + // Check vector table hasn't been modified + uint32_t vector_table_checksum = calculate_checksum(0x10000000, VECTOR_TABLE_SIZE); + if (vector_table_checksum != EXPECTED_CHECKSUM) { + // Vector table tampered - refuse to boot + secure_halt(); + } + + // Check critical data structures + // Verify stack pointer is in valid range + // etc. +} +``` + +#### 6. Anti-Tampering Hardware + +- **Tamper detection:** Sensors that detect case opening or voltage glitching +- **Response actions:** Erase sensitive keys, refuse to boot, or alert monitoring systems +- **Secure elements:** Store cryptographic keys in separate tamper-resistant chips + +### Lessons for Defenders + +1. **The bootrom is your trust anchor** - Its immutability makes it the foundation of security. RP2350's secure boot features leverage this. + +2. **Early is critical** - Security checks in the reset handler or runtime_init run before any application code, making them harder to bypass. + +3. **Defense in depth** - Multiple layers (hardware fuses, encrypted storage, secure boot, MPU) make attacks much harder. + +4. **Physical access = game over** - If an attacker can connect a debug probe, they can potentially compromise the device. Physical security matters! + +5. **Know your boot sequence** - Understanding exactly what runs when helps you identify where to add security checks and what assets need protection. + +### Security Research Value + +For security researchers and penetration testers, boot sequence analysis helps: + +- **Find vulnerabilities:** Many security bugs exist in startup code that runs before normal security checks +- **Develop exploits:** Understanding memory layout and initialization is essential for exploit development +- **Assess attack surface:** Knowing what's accessible at boot time reveals potential attack vectors +- **Build better defenses:** You can't defend what you don't understand + +> **"To know your enemy, you must become your enemy."** - Sun Tzu + +Understanding how an attacker would analyze and exploit the boot sequence is essential for building robust defenses. + +--- + +## Glossary + +### New Terms This Week + +| Term | Definition | +| ----------------- | ----------------------------------------------------------------------- | +| **Bootrom** | Factory-programmed ROM containing first-stage bootloader | +| **BSS** | Block Started by Symbol - section for uninitialized global variables | +| **CPUID** | Register that identifies which CPU core is executing | +| **crt0** | C Runtime Zero - the startup code that runs before main | +| **IMAGE_DEF** | Structure that marks valid firmware for the bootrom | +| **Linker Script** | File that defines memory layout for the compiled program | +| **Reset Handler** | First function called after reset/power-on | +| **Thumb Mode** | Compact instruction encoding used by Cortex-M | +| **Vector Table** | Array of addresses for stack pointer and exception handlers | +| **VTOR** | Vector Table Offset Register - tells CPU where to find the vector table | +| **XIP** | Execute In Place - running code directly from flash memory | + +### Review Terms from Weeks 1-2 + +| Term | Definition | How We Used It | +| ---- | ---------- | -------------- | +| **Breakpoint** | Marker that pauses program execution | Set at reset handler and main | +| **Register** | Fast storage inside the processor | Watched SP, LR, PC during boot | +| **Stack Pointer** | Register pointing to top of stack | Saw initial value in vector table | +| **Flash Memory** | Read-only storage for code | Contains vector table and boot code | +| **SRAM** | Read-write memory for data | Where stack and variables live | + +--- + +## Additional Resources + +### RP2350 Datasheet + +For more details on the boot process, see Chapter 5 of the RP2350 Datasheet: +https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf + +### Pico SDK Source Code + +The startup code lives in: + +- `crt0.S` - Main startup assembly (vector table at `.section .vectors`, reset handler, data copy, BSS clear, platform_entry) +- `memmap_default.ld` - Default linker script (section ordering: `.vectors` -> `.binary_info_header` -> `.embedded_block` -> `.reset`) +- `embedded_start_block.inc.S` - IMAGE_DEF block (replaces RP2040's `boot2_generic_03h.S`) + +> **Note:** The RP2040 used a `boot2_generic_03h.S` second-stage bootloader occupying the first 256 bytes of flash. The RP2350 eliminated this; the bootrom handles flash XIP setup directly. The SDK still includes a `boot2` mechanism for compatibility, but it is **not** placed at flash address 0 - it is embedded in the data copy table and executed from the stack during startup. + +### Bootrom Source + +The bootrom source is available at: +https://github.com/raspberrypi/pico-bootrom-rp2350 + +--- + +## Part 17: Proving the Boot Sequence with objdump + +Everything we have learned about the boot sequence can be proven directly from the compiled ELF binary using `arm-none-eabi-objdump`. The bootrom is not in your ELF (it is mask ROM burned into the chip at `0x00000000`), but everything your firmware provides - the vector table, the IMAGE_DEF, and the reset handler - lives in your ELF starting at `0x10000000`. + +### Step 1: List All Sections + +```bash +arm-none-eabi-objdump -h build/0x0001_hello-world.elf +``` + +Expected output (key sections): + +``` +Idx Name Size VMA LMA + 0 .text 000019cc 10000000 10000000 + 3 .binary_info 0000002c 10001b20 10001b20 + 4 .ram_vector_table 00000110 20000000 20000000 + 6 .data 0000019c 20000110 10001b4c +``` + +> Tip: The Pico SDK merges `.vectors`, `.embedded_block`, and `.reset` all into `.text` at `0x10000000`. They are not separate named ELF sections - they are sub-regions inside `.text`. + +### Step 2: Dump the First 0x150 Bytes of Flash - One Command, Zero Skips + +```bash +arm-none-eabi-objdump -s --start-address=0x10000000 --stop-address=0x10000150 build/0x0001_hello-world.elf +``` + +Raw output from that command: + +``` + 10000000 00200820 5d010010 1b010010 1d010010 . . ]........... + 10000010 11010010 11010010 11010010 11010010 ................ + 10000020 11010010 11010010 11010010 11010010 ................ + 10000030 11010010 11010010 11010010 11010010 ................ + 10000040 11010010 11010010 11010010 11010010 ................ + 10000050 11010010 11010010 11010010 11010010 ................ + 10000060 11010010 11010010 11010010 11010010 ................ + 10000070 11010010 11010010 11010010 11010010 ................ + 10000080 11010010 11010010 11010010 11010010 ................ + 10000090 11010010 11010010 11010010 11010010 ................ + 100000a0 11010010 11010010 11010010 11010010 ................ + 100000b0 11010010 11010010 11010010 11010010 ................ + 100000c0 11010010 11010010 11010010 11010010 ................ + 100000d0 11010010 11010010 11010010 11010010 ................ + 100000e0 11010010 11010010 11010010 11010010 ................ + 100000f0 11010010 11010010 11010010 11010010 ................ + 10000100 11010010 11010010 11010010 11010010 ................ + 10000110 eff30580 103800be 00be00be 00be00be .....8.......... + 10000120 00be00be f2eb8871 201b0010 4c1b0010 .......q ...L... + 10000130 a0010010 90a31ae7 d3deffff 42012110 ............B.!. + 10000140 ff010000 b01b0000 793512ab ........y5.. +``` + +Every address annotated, no skips: + +#### 0x10000000 - Vector Table, Mandatory Entries + +| Address | Raw Bytes (LE) | Decoded | What it is | +|---------|----------------|---------|------------| +| `0x10000000` | `00 20 08 20` | `0x20082000` | **Initial SP** - top of SCRATCH_Y RAM. Bootrom loads MSP from here before doing anything else. | +| `0x10000004` | `5d 01 00 10` | `0x1000015d` | **Reset_Handler** address with Thumb bit set. Strip bit 0 -> real address `0x1000015c`. Bootrom jumps here. | +| `0x10000008` | `1b 01 00 10` | `0x1000011b` | **NMI** handler address (Thumb, -> `0x1000011a`). | +| `0x1000000c` | `1d 01 00 10` | `0x1000011d` | **HardFault** handler address (Thumb, -> `0x1000011c`). | + +#### 0x10000010-0x1000010f - Vector Table, IRQ Slots (all 52 external IRQs) + +``` + 10000010 11010010 11010010 ...(repeats through 0x1000010f)... +``` + +Every 4-byte word here is `11 01 00 10` = pointer `0x10000111`. +That is the **default IRQ handler** address with Thumb bit set (-> `0x10000110`). +The RP2350 Cortex-M33 has 16 system vectors (offsets 0x00-0x3f) plus up to 52 +external IRQ vectors (offsets 0x40-0xff = addresses `0x10000040`-`0x1000010f`). +Every IRQ the application does not register gets this default handler pointer. +This block is 240 bytes (`0x10000010` to `0x1000010f`) of nothing but that one +repeated pointer. + +#### 0x10000110-0x10000127 - Default IRQ Handler Code + +``` + 10000110 eff30580 103800be 00be00be 00be00be + 10000120 00be00be f2eb8871 +``` + +| Address | Bytes | ARM Thumb-2 Instruction | What it does | +|---------|-------|-------------------------|--------------| +| `0x10000110` | `ef f3 05 80` | `MRS r0, IPSR` | Read the Interrupt Program Status Register into r0. The low 9 bits = the active vector number. | +| `0x10000114` | `10 38` | `SUBS r0, #16` | Vector 16 = IRQ0, so subtract 16 to convert vector number -> IRQ index. | +| `0x10000116` | `00 be` | `BKPT #0` | Software breakpoint. If a debugger is attached, it stops here and you can inspect r0 to see which IRQ fired. If no debugger is attached, the CPU enters a fault loop and the chip hangs. | +| `0x10000118`-`0x10000127` | `00 be` *12 | `BKPT #0` repeating | Alignment padding to the next 4-byte boundary. | + +This is the **entire** default IRQ handler. It is intentionally minimal: if your +code triggers an IRQ you did not register, it crashes visibly instead of silently. + +#### 0x10000128-0x1000013b - Binary Info Pointer Table + +``` + 10000120 201b0010 4c1b0010 + 10000130 a0010010 90a31ae7 +``` + +| Address | Bytes (LE) | Decoded Value | What it is | +|---------|------------|---------------|------------| +| `0x10000128` | `20 1b 00 10` | `0x10001b20` | Pointer to **start** of `.binary_info` data section in flash. | +| `0x1000012c` | `4c 1b 00 10` | `0x10001b4c` | Pointer to **end** of `.binary_info` data section in flash. | +| `0x10000130` | `a0 01 00 10` | `0x100001a0` | Pointer to `binary_info_callback` function. | +| `0x10000134` | `90 a3 1a e7` | (magic marker) | `BINARY_INFO_MARKER_END` - marks the end of this pointer table. | + +`picotool` reads this table to extract the program name, version string, URL, +and GPIO pin map from any compiled binary without running it. + +#### 0x10000138-0x1000014c - IMAGE_DEF Block (this build) + +``` + 10000130 a0010010 90a31ae7 d3deffff 42012110 + 10000140 ff010000 b01b0000 793512ab 4ff00000 +``` + +| Address | Bytes | What it is | +|---------|-------|------------| +| `0x10000138` | `d3 de ff ff` | `PICOBIN_BLOCK_MARKER_START` - the bootrom scans flash for this exact 4-byte sequence to locate the IMAGE_DEF. | +| `0x1000013c` | `42 01 21 10` | IMAGE_DEF content (image type, flags, version). | +| `0x10000140` | `ff 01 00 00` | IMAGE_DEF content (continuation). | +| `0x10000144` | `b0 1b 00 00` | IMAGE_DEF content (continuation). | +| `0x10000148` | `79 35 12 ab` | `PICOBIN_BLOCK_MARKER_END` - bootrom stops scanning here. | + +The IMAGE_DEF sits at `0x10000138`-`0x1000014b` in this build, +well within the 4 KB scan window the bootrom uses (Datasheet 5.9.5, p. 429). + +#### Full Flash Map: 0x10000000-0x1000015c + +``` + 0x10000000-0x1000000f Vector Table: mandatory entries (SP, Reset, NMI, HardFault) + 0x10000010-0x1000010f Vector Table: 52 external IRQ slots -> all point to default handler + 0x10000110-0x10000127 Default IRQ handler code (MRS / SUBS / BKPT) + 0x10000128-0x10000137 Binary info pointer table (start / end / callback / magic end) + 0x10000138-0x1000014b IMAGE_DEF block (d3 de ff ff ... 79 35 12 ab) + 0x10000150-0x1000015b (padding / alignment) + 0x1000015c Reset_Handler (_reset_handler in crt0.S) ← bootrom jumps here +``` + +### Step 4: Confirmed Boot Sequence (proven from ELF) + +``` ++-----------------------------------------------------------------+ +| PROVEN BOOT SEQUENCE (0x0001_hello-world) | ++-----------------------------------------------------------------+ +| 1. Bootrom reads 0x10000000 | +| -> SP = 0x20082000 (offset +0x00 of vector table) | +| -> RST = 0x1000015d (offset +0x04, Thumb -> 0x1000015c) | ++-----------------------------------------------------------------+ +| 2. Bootrom scans first 4 kB for IMAGE_DEF | +| -> Found at 0x10000138 (this build) | +| -> Start marker: d3 de ff ff | +| -> End marker: 79 35 12 ab | ++-----------------------------------------------------------------+ +| 3. Bootrom jumps to reset handler at 0x1000015c | +| -> _reset_handler (crt0.S) runs | +| -> Checks CPUID - Core 1 sent back to bootrom | +| -> Core 0: .data copied, .bss zeroed, platform_entry called | ++-----------------------------------------------------------------+ +| 4. platform_entry calls runtime_init -> main -> exit | ++-----------------------------------------------------------------+ +``` + +> **Datasheet References:** +> +> - 5.1.5.1 (p. 357): Block markers `0xffffded3` (start) and `0xab123579` (end) +> - 5.9.5 (p. 429): IMAGE_DEF must appear within first 4 kB of flash image +> - 5.9.5.1 (p. 429): Bootrom enters via reset handler at vector table offset +4 + +--- + +**Remember:** Understanding the boot process is fundamental to embedded systems work. Whether you're debugging a system that won't start, reverse engineering firmware, or building secure boot chains, this knowledge is essential! + +Happy exploring! + + + diff --git a/WEEK03/WEEK03.pdf b/WEEK03/WEEK03.pdf new file mode 100644 index 0000000..ad2d1cb Binary files /dev/null and b/WEEK03/WEEK03.pdf differ diff --git a/WEEK03/img/fig1.png b/WEEK03/img/fig1.png new file mode 100644 index 0000000..2675b54 Binary files /dev/null and b/WEEK03/img/fig1.png differ diff --git a/WEEK03/img/fig2.png b/WEEK03/img/fig2.png new file mode 100644 index 0000000..ea88c10 Binary files /dev/null and b/WEEK03/img/fig2.png differ diff --git a/WEEK03/img/fig3.png b/WEEK03/img/fig3.png new file mode 100644 index 0000000..d8508da Binary files /dev/null and b/WEEK03/img/fig3.png differ diff --git a/WEEK03/img/fig4.png b/WEEK03/img/fig4.png new file mode 100644 index 0000000..844d58f Binary files /dev/null and b/WEEK03/img/fig4.png differ diff --git a/WEEK03/img/fig5.png b/WEEK03/img/fig5.png new file mode 100644 index 0000000..842d5ee Binary files /dev/null and b/WEEK03/img/fig5.png differ diff --git a/WEEK03/slides/WEEK03-IMG00.svg b/WEEK03/slides/WEEK03-IMG00.svg new file mode 100644 index 0000000..d40fbfd --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 03 + + +Embedded System Analysis: +Understanding the RP2350 Architecture +w/ Comprehensive Firmware Analysis + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK03/slides/WEEK03-IMG01.svg b/WEEK03/slides/WEEK03-IMG01.svg new file mode 100644 index 0000000..0b8b8bd --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG01.svg @@ -0,0 +1,70 @@ + + + + + +RP2350 Boot Sequence +Power-On to main() — 5 Steps + + + +STEP 1 +Power On +Cortex-M33 wakes, execution at 0x00000000 (Bootrom) + + +▼ + + + +STEP 2 +Bootrom Executes +32KB on-chip ROM — finds IMAGE_DEF at 0x10000000 + + +▼ + + + +STEP 3 +Flash XIP Setup (bootrom-managed) +Bootrom configures flash interface & XIP (no boot2 on RP2350) + + +▼ + + + +STEP 4 +Vector Table & Reset Handler +Reads SP from offset 0x00 -> 0x20082000 +Reads Reset Handler from 0x04 -> 0x1000015d + + +▼ + + + +STEP 5 +C Runtime Startup (crt0.S) +Copy .data from flash -> RAM +Zero .bss section +Call runtime_init() -> main() + + + +Key Insight +Your main() is the LAST thing to run. +All 5 steps must complete first! + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG02.svg b/WEEK03/slides/WEEK03-IMG02.svg new file mode 100644 index 0000000..b7c0025 --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG02.svg @@ -0,0 +1,84 @@ + + + + + +The Bootrom +32KB Factory-Programmed ROM — Where It All Begins + + + +Bootrom Properties + + +Size +32 KB + + +Location +0x00000000 + + +Modifiable? +NO — mask ROM + + +Purpose +Boot the chip + +Burned into silicon at factory +Like BIOS in your computer + + + +What It Does + + +1. +Initialize hardware + + +2. +Check boot sources + + +3. +Validate IMAGE_DEF + + +4. +Configure flash + + +5. +Jump to your code + + + +IMAGE_DEF — Magic Markers +Bootrom looks for these to validate firmware + + +Start Marker +0xFFFFDED3 +"I'm a valid Pico binary!" + + +End Marker +0xAB123579 +"End of header block" + +Bootrom reads flash at 0x10000000, +finds these markers, then boots. + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG03.svg b/WEEK03/slides/WEEK03-IMG03.svg new file mode 100644 index 0000000..4db555b --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG03.svg @@ -0,0 +1,74 @@ + + + + + +XIP — Execute In Place +Run Code Directly from Flash — No Copy Needed + + + +Book Analogy + + +Without XIP +Photocopy every page, read copy + + +With XIP +Read directly from the book! + + + +Why Use XIP? + + +Saves RAM +Code stays in flash + + +Faster Boot +No bulk copy needed + + +Simpler +Less memory mgmt + + + +XIP Flash Region at 0x10000000 + + + +Vector Table +SP at offset 0x00 | Reset Handler at offset 0x04 | Exception handlers... + + + +Your Code +_reset_handler | main() | other functions + + + +Read-Only Data +Strings like "hello, world" | constant values + + +0x10000000 +0x100001xx +0x10001xxx + +CPU fetches instructions directly +from flash via XIP cache. + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG04.svg b/WEEK03/slides/WEEK03-IMG04.svg new file mode 100644 index 0000000..22034ba --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG04.svg @@ -0,0 +1,80 @@ + + + + + +The Vector Table +CPU's Instruction Manual at 0x10000000 + + + +Vector Table Layout + + + +Offset +Address +Value +Meaning + + + +0x00 +0x10000000 +0x20082000 +Initial SP + + + +0x04 +0x10000004 +0x1000015D +Reset Handler + + + +0x08 +0x10000008 +0x1000011B +NMI Handler + + + +0x0C +0x1000000C +0x1000011D +HardFault Handler + + + +GDB: +x/4x 0x10000000 + + + +On Power-On +1. CPU reads SP from 0x00 +2. Sets SP = 0x20082000 +3. Reads Reset from 0x04 +4. Jumps to 0x1000015C + + + +Default Handlers +NMI, HardFault, SVCall, +PendSV, SysTick all use: + +bkpt 0x0000 +<- stops debugger + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG05.svg b/WEEK03/slides/WEEK03-IMG05.svg new file mode 100644 index 0000000..c3d03a0 --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG05.svg @@ -0,0 +1,70 @@ + + + + + +Thumb Mode Addressing +Why Addresses End in Odd Numbers + + + +The LSB Rule +ARM Cortex-M uses the Least Significant +Bit (LSB) to indicate instruction mode: + + + +LSB = 1 (odd) +Thumb mode + + + +LSB = 0 (even) +ARM mode + + + +Reset Handler Example + +Vector table stores: +0x1000015D + +Actual code address: +0x1000015C + +The +1 means: +"Use Thumb mode" + + + +GDB Shows + +0x1000015D +with Thumb bit + + +Vector table raw value + + + +Ghidra Shows + +0x1000015C +actual address + + +Real instruction location + +Both are correct — just displayed differently! + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG06.svg b/WEEK03/slides/WEEK03-IMG06.svg new file mode 100644 index 0000000..f7d8b17 --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG06.svg @@ -0,0 +1,69 @@ + + + + + +Linker Script Memory Map +memmap_default.ld — Where Everything Lives + + + +Memory Regions + + + +Flash (XIP) +0x10000000 +varies +Your code (read-only) + + + +RAM +0x20000000 +512 KB +Main RAM (r/w) + + + +SCRATCH_X +0x20080000 +4 KB +Core 0 scratch (HW: SRAM8) + + + +SCRATCH_Y +0x20081000 +4 KB +Core 0 stack! (HW: SRAM9) + + + +Stack Pointer Calculation + +__StackTop = ORIGIN(SCRATCH_Y) + + LENGTH(SCRATCH_Y) + + +ORIGIN +0x20081000 + ++ LENGTH +0x1000 +(4 KB) + += __StackTop = 0x20082000 +<- matches vector table! + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG07.svg b/WEEK03/slides/WEEK03-IMG07.svg new file mode 100644 index 0000000..262aac0 --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG07.svg @@ -0,0 +1,87 @@ + + + + + +Reset Handler — 4 Phases +_reset_handler at 0x1000015C + + + +Phase 1: Core Check +0x1000015C — 0x10000168 + +mov r0, #0xD0000000 +Read CPUID -> Core 0 continues + + + +Phase 2: Data Copy +0x1000016A — 0x10000176 + +ldmia r4!, {r1,r2,r3} +Copy .data from flash -> RAM + + + +Phase 3: BSS Clear +0x10000178 — 0x10000184 + +stmia r1!, {r0} +r0 = 0 +Zero all uninitialized globals + + + +Phase 4: Platform Entry +0x10000186+ + +blx r1 +-> main() +runtime_init -> main -> exit + + + +Execution Flow + + + +Core Check +CPUID == 0? + +-> + + +Data Copy +flash -> RAM + +-> + + +BSS Clear +zero globals + +-> + + +Platform Entry +-> main()! + + + +Why check cores? +RP2350 has 2 cores. +Only Core 0 runs startup. +Core 1 returns to bootrom and waits. + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG08.svg b/WEEK03/slides/WEEK03-IMG08.svg new file mode 100644 index 0000000..b85e7ce --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG08.svg @@ -0,0 +1,93 @@ + + + + + +Data Copy & BSS Clear +Initializing RAM Before main() Can Run + + + +Phase 2: Data Copy +Copy initialized variables flash -> RAM + +C code: + +int counter = 42; + +Value 42 stored in flash +but variables live in RAM! + + + +Flash + +-> + + +RAM + + +data_cpy_table has entries: + +src: 0x10001B4C (flash) +dst: 0x20000110 (RAM) + + + +Phase 3: BSS Clear +Zero uninitialized global variables + +C code: + +int my_counter; + +C standard requires +this to start at zero. + + + +r1 = BSS start +r2 = BSS end +r0 = 0 + +Loop: store 0, advance r1 +Until r1 == r2 -> done! + + + +Key Assembly Instructions + + + +ldmia r4!, {r1,r2,r3} + +Load source, dest, end from table + + +bl data_cpy + +Copy word-by-word until done + + + +movs r0, #0 + +Load zero into r0 + + +stmia r1!, {r0} + +Store zero, advance pointer + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG09.svg b/WEEK03/slides/WEEK03-IMG09.svg new file mode 100644 index 0000000..8f0373c --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG09.svg @@ -0,0 +1,82 @@ + + + + + +Platform Entry -> main() +The Final Step — 3 Function Calls at 0x10000186 + + + +platform_entry Assembly + + +0x10000186 +ldr r1, [DAT] +-> load runtime_init addr + + +0x10000188 +blx r1 +-> call runtime_init() + + +0x1000018C +blx r1 +-> call main() + + +0x10000190 +blx r1 +-> call exit() + + + +Call Sequence + + +runtime_init() +SDK setup + +-> + + +main() +YOUR CODE + +-> + + +exit() +cleanup + + + +runtime_init() +Initializes SDK systems: +• Clock configuration +• GPIO setup +• C++ constructor calls +• Peripheral initialization + + +After main() Returns +exit() handles cleanup. +Then: + +bkpt 0x0000 +<- infinite halt + +Should never be reached! + \ No newline at end of file diff --git a/WEEK03/slides/WEEK03-IMG10.svg b/WEEK03/slides/WEEK03-IMG10.svg new file mode 100644 index 0000000..73b2c7c --- /dev/null +++ b/WEEK03/slides/WEEK03-IMG10.svg @@ -0,0 +1,92 @@ + + + + + +Secure Boot & Attack Vectors +Why Boot Sequence Knowledge Matters for Security + + + +Attack Scenarios + + +Firmware Replacement +Replace flash with malicious code + + +Vector Table Hijack +Modify reset handler address + + +Debug Port Attack +SWD/JTAG to dump or inject code + + +Startup Code Modification +Change crt0 data copy / BSS init + +Physical access = game over + + + +Defense Strategies + + +1. Secure Boot + + +2. Debug Port Lock + + +3. Flash Read Protect + + +4. MPU Configuration + + +5. Integrity Checks + +Defense in depth! + + + +Secure Boot Chain + + +Bootrom +immutable + +-> + + +Verify Sig +IMAGE_DEF + +-> + + +Verify App +signature + +-> + + +Boot! +or refuse + +Each stage cryptographically verifies +the next before handing off control. +Bootrom = trust anchor (can't be changed) + \ No newline at end of file diff --git a/WEEK04/0x0001b_ctf/.gitignore b/WEEK04/0x0001b_ctf/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0001b_ctf/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0001b_ctf/.vscode/c_cpp_properties.json b/WEEK04/0x0001b_ctf/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..613c996 --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.3.1/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.3.1/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/15_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0001b_ctf/.vscode/cmake-kits.json b/WEEK04/0x0001b_ctf/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0001b_ctf/.vscode/extensions.json b/WEEK04/0x0001b_ctf/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0001b_ctf/.vscode/launch.json b/WEEK04/0x0001b_ctf/.vscode/launch.json new file mode 100644 index 0000000..451b846 --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/launch.json @@ -0,0 +1,52 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.1/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.1/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + } + ] +} diff --git a/WEEK04/0x0001b_ctf/.vscode/settings.json b/WEEK04/0x0001b_ctf/.vscode/settings.json new file mode 100644 index 0000000..5b883ba --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/settings.json @@ -0,0 +1,46 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + }, + "variant": { + "statusBarVisibility": "hidden" + }, + "buildTarget": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.3.1/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v4.3.4/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.1/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.1/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.13.2/ninja" +} diff --git a/WEEK04/0x0001b_ctf/.vscode/tasks.json b/WEEK04/0x0001b_ctf/.vscode/tasks.json new file mode 100644 index 0000000..2f07d94 --- /dev/null +++ b/WEEK04/0x0001b_ctf/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.13.2/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.3.1/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.3.1/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + } + ] +} diff --git a/WEEK04/0x0001b_ctf/CMakeLists.txt b/WEEK04/0x0001b_ctf/CMakeLists.txt new file mode 100644 index 0000000..cd4bff3 --- /dev/null +++ b/WEEK04/0x0001b_ctf/CMakeLists.txt @@ -0,0 +1,91 @@ +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: CMakeLists.txt +# Desc: Configures the RP2350 Pico SDK project for the Operation Black Start +# CTF relay firmware. +# Created: 2026 + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.3.1) +set(toolchainVersion 15_2_Rel1) +set(picotoolVersion 2.3.1) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0001b_ctf C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable with modular sources in src/ +add_executable(0x0001b_ctf + src/main.c + src/grid.c + src/console.c +) + +pico_set_program_name(0x0001b_ctf "0x0001b_ctf") +pico_set_program_version(0x0001b_ctf "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0001b_ctf 1) +pico_enable_stdio_usb(0x0001b_ctf 0) +target_compile_definitions(0x0001b_ctf PRIVATE + PICO_DEFAULT_UART_BAUD_RATE=115200 +) + +# Add the standard library to the build +target_link_libraries(0x0001b_ctf + pico_stdlib +) + +# Add the standard include files to the build +target_include_directories(0x0001b_ctf PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/include +) + +pico_add_extra_outputs(0x0001b_ctf) diff --git a/WEEK04/0x0001b_ctf/CTF-01-I.md b/WEEK04/0x0001b_ctf/CTF-01-I.md new file mode 100644 index 0000000..dbda501 --- /dev/null +++ b/WEEK04/0x0001b_ctf/CTF-01-I.md @@ -0,0 +1,442 @@ +# Operation Black Start - Student Instructions + +**⚠ WORLDGRID EMERGENCY INCIDENT ⚠** + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N B L A C K S T A R T | +| | +| *** PRIORITY RED *** | +| | ++----------------------------------------------------------------------------------------+ +``` + +--- + +## Project Overview + +WorldGrid Compact's emergency firmware build for its GRID-7 relay fleet +shipped a miscompiled safety threshold and a hardcoded false status string, +so deployed relays report a false-safe "STABLE" status while the frozen +frequency deviation reading of 0.87 Hz is nearly 50% beyond the 0.60 Hz +engineering limit. The source was overwritten by the next build and cannot +be recovered, so the only surviving evidence is the exact miscompiled +training image. Students reverse engineer `CTF-01.bin` with Ghidra, locate +and patch both defects directly in the binary, export a corrected image, +flash it to a Pico 2, and prove the corrected behavior with GDB and a UART +console. + +--- + +## Scenario Briefing + +### Background + +**WorldGrid Compact** is the emergency interconnection standard shared by +three allied national grid operators. When any member's primary SCADA +network goes dark, a fleet of small embedded relay nodes - call sign +**GRID-7** - is the only thing standing between an orderly recovery and an +uncontrolled cascade. Each relay node watches the last known grid frequency +deviation, decides whether conditions are safe, and either **holds** the +automatic black-start dispatch or **authorizes** it. + +At 03:11 UTC, a coordinated cyberattack severed the primary SCADA uplink +across the GRID-7 corridor and the WATER-3 aqueduct pumping stations that +depend on it. With the network coordination center offline and three +continents' worth of hospitals, rail systems, and water treatment plants +running on backup power, WorldGrid's engineering team did the only thing +they could: they rushed an emergency firmware build for the relay fleet and +pushed it within **eleven minutes** of the attack being detected. + +### The Disaster + +The engineer who built that emergency image, **Dr. Elias Renner**, has not +slept in thirty-one hours. He compiled the fix, ran a five-second bench +test, and shipped it - because the alternative was leaving the relay fleet +completely blind. It appears to work. The relay boots. It prints a status +report. It reports **GRID STATUS: STABLE** and **DISPATCH PATH: +AUTHORIZED**. + +There is a problem: the frozen frequency reading latched at the moment +communications were cut shows a deviation of **0.87 Hz** - nearly *50% +beyond* WorldGrid's hard engineering limit of **0.60 Hz**. A deviation this +large, if trusted, means the grid is nowhere near stable enough for an +automatic black-start dispatch. If the fleet authorizes dispatch on a false +"STABLE" reading, cascading generator trips will follow within minutes, +and GRID-7 and WATER-3 will go dark for the second time - this time with no +backup plan. + +**Dr. Renner's rushed build has a bug. Multiple relay nodes are already +reporting the same false-safe status. Nobody has found where in the +compiled firmware the error lives, because the source code used for that +emergency compile was overwritten by the next build fifteen minutes later +and cannot be recovered.** + +### The Only Surviving Evidence + +One relay node - the training/verification unit - still holds the exact +miscompiled image that shipped to the fleet. This binary, and this binary +alone, is the only remaining copy of the emergency build. There is no +source code. There is no build log. There is only the compiled image, a +UART cable, and whatever a skilled embedded reverse engineer can prove by +reading machine code. + +### The Human Stakes + +| Consequence if the false "STABLE" reading is trusted | Scale | +|---|---| +| Hospitals on generator backup past their fuel reserve | 214 facilities | +| Water treatment and pumping stations losing pressure | 3 aqueduct systems | +| Rail corridors stranded mid-route | 6 national rail networks | +| Estimated population affected by cascading failure | 40+ million people | + +**The options are:** + +1. ❌ **Trust the fleet's reported status** - dispatch fires on a false + reading, cascading failure follows within the hour. +2. ❌ **Shut the entire relay fleet down** - buys time, but leaves 40 + million people with no automated recovery path at all. +3. **REVERSE ENGINEER THE EMERGENCY BUILD** - find the exact + miscompiled bytes, patch them, verify the corrected image on real + hardware, and hand the fix to the field team so the *rest of the fleet* + can be safely repatched before the next attempt. + +### THE SHORTAGE + +For years, the world treated embedded systems as invisible infrastructure. +The engineers who could read a vector table, decode a Thumb branch, or +patch a miscompiled constant directly in a stripped binary were never +numerous enough. Tonight almost all of them are already in the field +chasing other failures. **You are the reserve team.** + +You were called in because you can do something Dr. Renner's exhausted +team cannot do right now: read what the processor is actually doing, with +no source code, no time for a rewrite, and no room for a guess. + +> **⏰ TIME PRESSURE:** The field team is standing by to push your verified +> patch to the rest of the GRID-7 fleet. Every relay node still reporting +> a false "STABLE" status is one dispatch cycle away from disaster. + +> **AUTHORIZED LAB ONLY:** This challenge uses a supplied Pico 2 training +> relay and its exact miscompiled firmware image. Do not connect this +> exercise to a public network, an operational grid, a water utility, or +> any device you do not own or have explicit written authorization to test. + +--- + +## Learning Objectives + +- Decode the RP2350 / ARM Cortex-M33 vector table and identify the reset + handler and initial stack pointer. +- Trace the bootrom-to-reset handoff and translate Thumb reset-vector + addresses into real function entry points. +- Locate a miscompiled boundary comparison and reason about the correct + immediate value the compiler should have encoded. +- Patch compare instructions and a status string directly in a raw binary + with Ghidra. +- Recover a hidden quarantined dispatch frame from the compiled image. +- Export and UF2-convert a corrected image, then verify the corrected + behavior on real hardware with GDB and a UART console. + +--- + +## What This Project Tests + +| Week | Concepts Tested | +|------|-----------------| +| 1 | RP2350 architecture, ARM Cortex-M33 registers, stack, flash/RAM, Thumb assembly, Ghidra static analysis | +| 2 | GDB connection, breakpoints, disassembly, register and memory inspection, UART observation | +| 3 | Bootrom handoff, vector table, reset handler, startup code, XIP, Thumb-bit addressing | + +--- + +## Part 1: Understanding the System + +### GRID-7 Relay Hardware + +| Component | Connection | Purpose | +|-----------|------------|---------| +| Raspberry Pi Pico 2 | RP2350 | Runs the miscompiled emergency firmware | +| UART TX | GPIO 0 | Relay telemetry output | +| UART RX | GPIO 1 | Reserved (no command parser is implemented) | +| SWD debug interface | Supplied probe | Authorized GDB inspection | + +No LED, relay output, sensor, display, or other peripheral is part of this +CTF. Every graded finding lives in flash (`.rodata`/`.text`) or SRAM, and is +reachable with only the Weeks 1-3 toolset: Ghidra, GDB, and a UART monitor. + +### UART Configuration + +- Baud: `115200` +- Data: `8 bits` +- Parity: `none` +- Stop: `1` +- Logic: `3.3 V` + +### Normal (Intended) Behavior + +The relay should latch the frozen deviation reading, compare it against the +**real** WorldGrid safety limit of **60** (0.60 Hz, encoded as an integer +`x100`), and report honestly: + +``` ++-----------------------------------------------------------------+ +| Intended Relay Behavior | +| | +| 1. Boot and initialize UART | +| 2. Print the boot identity and a signal-quality banner | +| 3. Compare the frozen 87 (0.87 Hz) reading against the 60 | +| (0.60 Hz) safety limit | +| 4. 87 exceeds 60, so the grid is NOT stable | +| 5. Report GRID STATUS: CRITICAL and DISPATCH PATH: HELD | +| 6. Repeat the report once per second until conditions change | ++-----------------------------------------------------------------+ +``` + +### Observed (Buggy) Behavior - What You Will See When You First Flash `CTF-01.uf2` + +```text +GLOBAL EMBEDDED RESPONSE NETWORK +BLACK START WINDOW: 27 MINUTES +UART0 115200 8N1 | AUTHORIZED LAB CONSOLE +SIGNAL: NORMAL +RESPONSE> GRID STATUS: STABLE +DISPATCH PATH: AUTHORIZED +LAST FRAME: QUARANTINED +RESPONSE> +``` + +> **Terminal Timing Note:** The first four lines (`GLOBAL EMBEDDED...` through +> `SIGNAL: NORMAL`) represent the **initial boot banner**, emitted once during +> startup. If your serial terminal (PuTTY) connects after the board has +> booted, you will observe the continuous 1-second status stream (`GRID +> STATUS...` and `DISPATCH PATH...`). To view the boot banner in your terminal, +> reset the Pico (pulse `RUN` to `GND`) while PuTTY is actively connected. + +This is exactly what Dr. Renner's team is seeing on the deployed fleet. It +is wrong, and it is wrong in **two independent ways** inside the compiled +binary. Do not assume the first readable sentence is the full truth - +treat every printed line as evidence to be checked against the machine +code, not as a fact on its own. + +--- + +## Part 2: The Firmware + +You do not have the source code. It was overwritten fifteen minutes after +the emergency build shipped. You have only the compiled image. Your job is +to reverse engineer it with Ghidra, locate the defects, and patch the +binary directly - exactly the way Dr. Renner's field team will need to +patch the rest of the deployed fleet. + +### What The Firmware Does + +1. Initializes UART0 and stdio. +2. Reads a frozen grid-frequency-deviation reading that was latched in + memory before communications were severed. +3. Compares that reading against a compiled-in safety threshold - **twice**, + once for each independent status line it reports. +4. Prints a boot banner containing an unconditional signal-quality line. +5. Enters an infinite loop printing the grid classification and dispatch + decision once per second. + +### Bug Summary - What You Are Graded On + +| Bug # | Category | Severity | Description | Hint | +|-------|----------|----------|--------------|------| +| **Bug #1** | Miscompiled safety constant | **CRITICAL** | The safety threshold used to classify the frozen reading was compiled far too permissive. It is used **twice** - once for the operator-facing status and once for the automated dispatch decision - and **both** copies must be corrected. | The real WorldGrid safety limit is 60 (0.60 Hz). Search for the wrong immediate value used in the comparison. | +| **Bug #2** | Hardcoded string literal | **HIGH** | The boot banner unconditionally prints a signal-quality word that does not reflect the actual reading, regardless of what the relay later reports. | The correct word describes the true state of a 0.87 Hz deviation against a 0.60 Hz limit - not "NORMAL". | + +**Important:** The replacement text for Bug #2 **must be the same length** +as the original - patching a shorter or longer string will corrupt +adjacent flash data. + +### A Third Finding - Not a Bug, a Recovery Task + +Somewhere in this image is the **quarantined black-start authorization +frame** - the exact frame the relay is supposed to transmit to the +regional dispatcher once a human operator confirms it is safe to proceed. +It is never printed by the firmware. Recovering it (without patching +anything) is required evidence for your final report. + +--- + +## Part 3: Your Assignment + +Whenever a task asks you to **Document** or **answer**, write your answers +in a single file named `CTF-01-Answers.md`. + +### Task 1: Setup and Initial Analysis + +1. Create a new Ghidra project named `Black_Start_Investigation`. +2. Import `CTF-01.bin`. +3. Configure the language as **ARM Cortex 32-bit, little endian**. +4. Set the base address to `0x10000000`. +5. Run auto-analysis. + +**Document:** +- A screenshot of the Ghidra **Import Results** or **Program Information** + window showing the project name, processor settings, and base address. +- The address of `main()`. +- The address of the recurring status loop (the branch target that repeats + once per second). +- The vector-table base, the initial stack pointer, and the reset-handler + pointer as stored (note its Thumb bit) versus the actual instruction + address. + +### Task 2: Find and Patch Bug #1 - The Miscalibrated Safety Threshold + +1. Find **both** locations where the frozen reading is compared against + the miscompiled safety constant. +2. Document the exact address, the original instruction, and the original + immediate value at each location. +3. Determine the correct immediate value. **Caution:** the compiler may + not have encoded the raw threshold you expect - a strict "less than" + comparison against an unsigned value is often optimized into a + "less-or-equal" comparison against one less than the threshold. Show + your reasoning. +4. Patch **both** locations in Ghidra using the **Bytes Window** workflow: + > **Critical ARM Thumb-2 Patching Note:** In ARM Cortex-M, compare instructions that directly precede conditional execution blocks (`ite hi`) must **not** be patched using the right-click *Patch Instruction* dialog. Ghidra's automatic re-disassembler encounters an internal context conflict with the subsequent `ite hi` instruction, which collapses Thumb decoding and swallows Compare Site B (`0x1000020A`). + > + > To patch cleanly without breaking downstream disassembly, use the **Bytes Window**: + > 1. Ensure the Bytes window is open (**Window** -> **Bytes: CTF-01.bin**). + > 2. In the Bytes window toolbar, click the **pencil icon** (**Toggle Edit Mode**). + > 3. In the Listing window, click on address `0x100001FC` (Compare Site A) and press **`C`** (**Clear Code Bytes**). The instruction temporarily clears into raw bytes (`5E 2B`). + > 4. In the Bytes window, locate offset `100001fc`, click on `5E`, and change it to **`3B`**. + > 5. Click back in the Listing window on address `0x100001FC` and press **`D`** (**Disassemble**). The instruction immediately disassembles cleanly as `cmp r3, #0x3b`. + > 6. Notice that Compare Site B at `0x1000020A` remains completely intact and visible! Repeat the exact same steps at `0x1000020A`: click `0x1000020A` in the Listing, press **`C`**, change `5E` to **`3B`** in the Bytes window, click back in the Listing, and press **`D`**. + +**Questions to answer:** +- Why must both locations be patched? What happens if you only patch one? +- Why is a false "STABLE" classification on an 0.87 Hz reading dangerous + for an automated black-start dispatch? + +### Task 3: Find and Patch Bug #2 - The False Signal Banner + +1. Find the boot-banner string that unconditionally reports the wrong + signal quality. +2. Document its address and the exact bytes that must change. +3. Patch the string, preserving its exact length. + +**Questions to answer:** +- Document the original vs. patched bytes, character by character. +- Why is a hardcoded, unconditional status word more dangerous than one + that is at least computed from a (miscalibrated) reading? + +### Task 4: Recover the Quarantined Dispatch Frame + +1. Use Ghidra's Defined Strings (or a raw string search) to locate the + hidden black-start authorization frame. +2. Document its address and explain why it is never transmitted by the + current firmware. +3. Do **not** attempt to patch this value - it is evidence, not a bug. + +### Task 5: Export and Verify + +1. Export your patched binary as `CTF-01_fixed.bin`. +2. Convert it to UF2 format for the RP2350: + ```bash + python uf2conv.py CTF-01_fixed.bin --base 0x10000000 --family 0xe48bff59 --output CTF-01_fixed.uf2 + ``` +3. Flash `CTF-01_fixed.uf2` to your Pico 2 and capture the corrected UART + output. +4. Confirm that the corrected image now reports **GRID STATUS: CRITICAL**, + **DISPATCH PATH: HELD**, and the corrected signal-quality word - an + honest, safe report instead of a false "all clear." +5. Build a summary table of every patch: address, original bytes, patched + bytes, and a one-line description. + +### Task 6: Written Reflection (short answers, 150 words or less each) + +1. Why is "the build was rushed under emergency pressure" not an + acceptable excuse for shipping a firmware defect that could trigger a + cascading grid failure? +2. Name one concrete engineering practice (code review, static analysis, + hardware-in-the-loop test, etc.) that would have caught **each** of the + two graded bugs before this image ever reached the fleet. + +--- + +## How To Breadboard + +- Pico 2 **GPIO 0 / UART TX** -> USB-UART adapter **RX** +- Pico 2 **GPIO 1 / UART RX** -> USB-UART adapter **TX** +- Pico 2 **GND** -> USB-UART adapter **GND** +- Use **3.3 V logic only**. Never connect a 5 V line to a Pico GPIO. +- Connect the supplied SWD probe according to its documented pinout. + +The supplied image is `CTF-01.bin` (for Ghidra analysis) and `CTF-01.uf2` +(for flashing). If your instructor supplies different filenames, record the +actual filenames in your report. + +--- + +## Memory Map Reference + +| Region | Address | Purpose | +|--------|---------|---------| +| Bootrom | `0x00000000` | Immutable boot code | +| Flash/XIP | `0x10000000` | Vector table, code, constants, strings | +| SRAM | `0x20000000` | Stack and writable state | + +--- + +## Submission Format + +Submit a folder containing: + +- `CTF-01-Answers.md`; +- screenshots or terminal transcripts; +- `CTF-01_fixed.bin` and `CTF-01_fixed.uf2`; +- the original image hash. + +--- + +## Success Criteria + +You complete the challenge when you can prove all of the following: + +- You can explain how the RP2350 reaches the relay's code from reset. +- You can locate and patch both copies of the miscalibrated threshold. +- You can locate and patch the false signal-quality string without + corrupting adjacent data. +- You can export, convert, and flash a corrected image. +- You can prove on real hardware that the corrected image reports the + true, dangerous state instead of the false "all clear." +- You can recover the quarantined dispatch frame as evidence. + +--- + +## Academic Integrity + +By submitting this CTF work, you certify that: + +1. You used only the supplied training relay, image, and lab interface. +2. You did not connect the challenge to a public network, an operational + grid, a water utility, or any third-party device. +3. You understand that embedded reverse engineering and binary patching + require explicit authorization in any real-world context. +4. You will report any discovered weakness responsibly to the course + instructor. + +The world is short on people who can do this work. Treat that +responsibility seriously: verify before you patch, patch before you trust, +and never confuse a clean-looking status line with a safe system. + +--- + +## Reference Material + +- ARM Cortex-M33 Technical Reference Manual +- RP2350 datasheet +- GDB documentation +- Ghidra documentation: [https://ghidra-sre.org/](https://ghidra-sre.org/) diff --git a/WEEK04/0x0001b_ctf/CTF-01-I.pdf b/WEEK04/0x0001b_ctf/CTF-01-I.pdf new file mode 100644 index 0000000..1ed54e3 Binary files /dev/null and b/WEEK04/0x0001b_ctf/CTF-01-I.pdf differ diff --git a/WEEK04/0x0001b_ctf/CTF-01-R.md b/WEEK04/0x0001b_ctf/CTF-01-R.md new file mode 100644 index 0000000..9dbec48 --- /dev/null +++ b/WEEK04/0x0001b_ctf/CTF-01-R.md @@ -0,0 +1,237 @@ +# Operation Black Start - Requirements & Grading Criteria + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N B L A C K S T A R T | +| | +| REQUIREMENTS & GRADING CRITERIA | +| | ++----------------------------------------------------------------------------------------+ +``` + +--- + +## Project Overview + +Students are the reverse-engineering reserve team called in after WorldGrid +Compact's emergency firmware build shipped a miscompiled safety threshold and +a false status string to its GRID-7 relay fleet. Students reverse engineer +`CTF-01.bin` with Ghidra, locate two real defects, patch them in the binary, +export a corrected image, flash it to real hardware, and prove the corrected +behavior with the debugger and the console. + +The challenge is separate from all FINAL projects and contains no FINAL-project +answer, constant, address, bug, or patch. + +--- + +## Learning Objectives + +- Decode an ARM Cortex-M33 vector table and identify the reset handler and + initial stack pointer. +- Translate Thumb reset-vector addresses into real function entry points. +- Locate a miscompiled boundary comparison and reason about its immediate + value. +- Patch compare instructions and a status string in a raw binary with Ghidra. +- Export and UF2-convert a corrected image, then verify it on real hardware. +- Capture derived state with GDB and read UART console output. + +Students must use only Weeks 1-3 concepts: ARM registers and stack behavior, +UART output, GDB, Ghidra static analysis and binary patching, vector tables, +reset startup, XIP, and Thumb addressing. + +--- + +## Deliverables Checklist + +| # | Deliverable | Format | Criterion | +|---|-------------|--------|-----------| +| 1 | Ghidra project screenshot (project name, processor, base address) | PNG/JPG | 1.1 | +| 2 | `main()` and status-loop addresses | Inside `CTF-01-Answers.md` | 1.2 | +| 3 | Vector table base, initial SP, reset pointer | Inside `CTF-01-Answers.md` | 1.3 | +| 4 | Thumb bit explanation | Inside `CTF-01-Answers.md` | 1.4 | +| 5 | Bug #1 evidence and patches (both compare sites) | Inside `CTF-01-Answers.md` | 2.1-2.6 | +| 6 | Bug #2 evidence and patch (six characters) | Inside `CTF-01-Answers.md` | 3.1-3.4 | +| 7 | Recovered dispatch frame and address | Inside `CTF-01-Answers.md` | 4.1-4.2 | +| 8 | `CTF-01_fixed.bin` | BIN file | 5.1 | +| 9 | `CTF-01_fixed.uf2` | UF2 file | 5.2 | +| 10 | Corrected console transcript | Inside `CTF-01-Answers.md` | 5.3 | +| 11 | Summary table of all patches | Inside `CTF-01-Answers.md` | 5.4 | +| 12 | Written reflection | Inside `CTF-01-Answers.md` | 6.1-6.2 | + +--- + +## Required Tools and Equipment + +| Tool | Purpose | +|------|---------| +| Raspberry Pi Pico 2 | Isolated target | +| 3.3 V USB-UART adapter | UART capture on GPIO 0 (TX) / GPIO 1 (RX) | +| Serial monitor | Observe output | +| Ghidra | Static analysis and binary patching | +| Python (`uf2conv.py`) | UF2 conversion | +| `CTF-01.bin` and `CTF-01.uf2` | Supplied artifacts | + +UART settings: **115200 baud, 8 data bits, no parity, 1 stop bit**. + +--- + +## Artifact Identity + +The instructor-issued artifact hashes are: + +```text +CTF-01.bin 425591AC17FF4C22206286EE6F40B06A89523483804850A41854A9B6F89D7B70 +CTF-01.uf2 B1552EE3BB5763D96C65D8DF1C86984EE842EF1A823FDF5D94132B1E10FF9D16 +``` + +--- + +## Grading Rubric - Detailed Breakdown + +### Task 1: Setup and Initial Analysis (15 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 1.1: Ghidra Project Setup | 3 | Correct project name, `ARM:LE:32:Cortex` (ARM Cortex 32-bit little endian), base `0x10000000` | One item off | Not set up | +| Criterion 1.2: main() and Status-Loop Addresses | 4 | Both addresses correct | One correct | Neither found | +| Criterion 1.3: Vector Table Decoding | 4 | Correct base, initial SP, reset pointer | One missing | Not found | +| Criterion 1.4: Thumb Addressing | 4 | Correctly clears bit 0 and identifies `main()` | General explanation | Incorrect | + +### Task 2: Find and Patch Bug #1: The Miscalibrated Safety Threshold (30 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 2.1: Locate Compare Site A | 5 | Correct address and original bytes | Address off | Not found | +| Criterion 2.2: Locate Compare Site B | 5 | Correct address and original bytes | Address off | Not found | +| Criterion 2.3: Correct Immediate-Value Reasoning | 8 | Explains the `<` to `<=` transform and gives `0x3B` | Correct value, no reasoning | Wrong value | +| Criterion 2.4: Patch Compare Site A | 4 | Byte change verified | Wrong byte | Not patched | +| Criterion 2.5: Patch Compare Site B | 4 | Byte change verified | Wrong byte | Not patched | +| Criterion 2.6: Explain Why Both Sites Must Be Patched | 4 | Clear explanation of the two independent comparisons | Vague | Missing | + +### Task 3: Find and Patch Bug #2: The False Signal Banner (20 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 3.1: Locate the Banner String | 5 | Correct address | Approximate | Not found | +| Criterion 3.2: Patch Six Characters | 8 | All six bytes changed, length preserved | Correct text, wrong bytes documented | Wrong length | +| Criterion 3.3: Character-by-Character Documentation | 4 | Original vs patched byte for all six characters | Partial | Missing | +| Criterion 3.4: Explain the Danger of a Hardcoded Status Word | 3 | Clear, specific reasoning | Generic | Missing | + +### Task 4: Recover the Quarantined Dispatch Frame (10 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 4.1: Recover the Dispatch Frame | 6 | Correct address and full text | Partial text | Not found | +| Criterion 4.2: Explain Why It Is Never Transmitted | 4 | Clear static-analysis explanation | Vague | Missing | + +### Task 5: Export and Verify (20 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 5.1: Export CTF-01_fixed.bin | 4 | Valid patched binary | Corrupted | Not submitted | +| Criterion 5.2: Convert to CTF-01_fixed.uf2 | 4 | Correct base and family flags | Wrong flags | Not submitted | +| Criterion 5.3: Hardware Verification | 8 | Corrected console output confirmed (CRITICAL/HELD in 1s stream; DANGER at boot/Ghidra) | Some lines corrected | No verification | +| Criterion 5.4: Summary Table of All Patches | 4 | Complete address and before/after table | Missing entries | No table | + +### Task 6: Written Reflection (5 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 6.1: "Rushed Build" Is Not an Excuse | 2 | Specific, grounded reasoning | Generic | Missing | +| Criterion 6.2: One Engineering Practice per Bug | 3 | Concrete practice for each bug | One bug only | Missing | + +--- + +## Common Pitfalls + +| Pitfall | Consequence | Avoidance | +|---------|-------------|-----------| +| Patching only one threshold site | One status line still lies | Patch both `0x100001FC` and `0x1000020A` | +| Assuming the immediate equals the limit | Off-by-one, wrong boundary | Use `0x3B` (59), not `0x3C` (60) | +| Using Patch Instruction before IT block | Re-disassembler context conflict swallows Site B | In Listing press `C` -> edit byte in Bytes window (pencil) -> press `D` | +| Missing boot banner in serial terminal | PuTTY misses one-time 5ms boot banner | Pulse RUN to GND while connected to capture | +| Replacing a string with a different length | Corrupts adjacent flash | `NORMAL` and `DANGER` are both 6 bytes | +| Treating an odd vector address as invalid | Thumb analysis fails | Clear bit 0 | +| Modifying the quarantined dispatch frame | Destroys evidence | Recover it, do not patch it | + +--- + +## How To Breadboard + +- **Raspberry Pi Pico 2** powered over USB. +- **3.3 V USB-UART adapter**: + - Adapter RX to Pico GP0 (UART0 TX) + - Adapter TX to Pico GP1 (UART0 RX) + - Adapter GND to Pico GND + - Do not connect the adapter VCC while the Pico is USB powered. +- **Serial monitor:** 115200 baud, 8 data bits, no parity, 1 stop bit. +- No other peripherals are required; all evidence is obtained from the console. + +--- + +## Memory Map Reference + +| Region | Address | Purpose | +|--------|---------|---------| +| Bootrom | `0x00000000` | Immutable boot code | +| Flash/XIP | `0x10000000` | Vector table, code, constants, strings | +| SRAM | `0x20000000` | Stack and writable state | + +--- + +## Deadline & Submission + +- Create a folder containing the Ghidra screenshot, `CTF-01_fixed.bin`, and + `CTF-01_fixed.uf2`. +- Write all written answers in a single file named `CTF-01-Answers.md` inside that + folder. +- ZIP the folder as `lastname-firstname-CTF-01.zip`. +- Submit the ZIP before the posted deadline; late submissions lose 10 percent + per day. + +--- + +## Grade Scale + +| Grade | Percentage | Points | +|-------|------------|--------| +| A+ | 97-100% | 97-100 | +| A | 93-96% | 93-96 | +| A- | 90-92% | 90-92 | +| B+ | 87-89% | 87-89 | +| B | 84-86% | 84-86 | +| B- | 80-83% | 80-83 | +| C | 70-79% | 70-79 | +| F | 0-69% | 0-69 | + +--- + +## Academic Integrity + +Use only the supplied Pico 2 and firmware. Do not connect the exercise to an +operational grid, water plant, public network, military system, or third-party +device. This is a controlled, isolated educational exercise. All analysis and +patches must be your own work; sharing binaries, addresses, or answers is a +violation of the academic integrity policy. + +--- + +## Reference Material + +| Topic | Reference | +|-------|-----------| +| ARM Cortex-M33 registers and stack | Week 1 | +| UART output and console capture | Week 2 | +| Vector tables, reset startup, and XIP | Week 2 | +| Ghidra static analysis and binary patching | Week 3 | +| Thumb addressing | Week 3 | diff --git a/WEEK04/0x0001b_ctf/CTF-01-R.pdf b/WEEK04/0x0001b_ctf/CTF-01-R.pdf new file mode 100644 index 0000000..01ca3d8 Binary files /dev/null and b/WEEK04/0x0001b_ctf/CTF-01-R.pdf differ diff --git a/WEEK04/0x0001b_ctf/CTF-01-S.md b/WEEK04/0x0001b_ctf/CTF-01-S.md new file mode 100644 index 0000000..6d19d05 --- /dev/null +++ b/WEEK04/0x0001b_ctf/CTF-01-S.md @@ -0,0 +1,467 @@ +# Operation Black Start - Instructor Solution Key + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N B L A C K S T A R T | +| | +| *** INSTRUCTOR SOLUTION KEY - RESTRICTED *** | +| | ++----------------------------------------------------------------------------------------+ +``` + +> The task and criterion headings in this key are word-for-word identical to +> `CTF-01-R.md`, so a student can match each criterion one-to-one. + +--- + +## Artifact Identity + +| Artifact | Value | +|----------|-------| +| Student image | `CTF-01.bin` | +| Flash image | `CTF-01.uf2` | +| Target | Raspberry Pi Pico 2 / RP2350 ARM Cortex-M33 | +| Image base | `0x10000000` | +| Console | UART0, GPIO 0 TX / GPIO 1 RX, 115200 8N1 | + +```text +CTF-01.bin 425591AC17FF4C22206286EE6F40B06A89523483804850A41854A9B6F89D7B70 +CTF-01.uf2 B1552EE3BB5763D96C65D8DF1C86984EE842EF1A823FDF5D94132B1E10FF9D16 +``` + +Proof tool: `python3 scripts/verify_ctf.py` returns `11/11 checks passed` against +`CTF-01.bin`. + +--- + +## Task 1: Setup and Initial Analysis (15 points) + +### Solution + +**Criterion 1.1: Ghidra Project Setup (3 points).** Import `CTF-01.bin` as +`Raw Binary`, language `ARM:LE:32:Cortex`, base address `0x10000000`, then run +auto-analysis. + +**Criterion 1.2: main() and Status-Loop Addresses (4 points).** + +| Element | Address | +|---------|---------| +| `main()` | `0x100001E0` | +| Recurring status loop start | `0x10000234` | +| Loop back-edge (`b.n 0x10000234`) | `0x10000266` | + +The back-edge instruction at `0x10000266` is `b.n 0x10000234`, encoded as bytes +`E5 E7`. + +**Criterion 1.3: Vector Table Decoding (4 points).** +First 32 bytes of `CTF-01.bin`: + +```text +00 20 08 20 5B 01 00 10 1B 01 00 10 1D 01 00 10 +11 01 00 10 11 01 00 10 11 01 00 10 11 01 00 10 +``` + +| Evidence | Answer | +|----------|--------| +| Vector table base | `0x10000000` | +| Initial SP | `0x20082000` | +| Reset pointer (as stored) | `0x1000015B` | +| Reset instruction address | `0x1000015A` | + +**Criterion 1.4: Thumb Addressing (4 points).** +The stored reset pointer `0x1000015B` has bit 0 set to 1, which selects Thumb +mode. Clearing bit 0 (`0x1000015B & ~1`) gives the real instruction address +`0x1000015A`. The equally odd interrupt vectors (`0x1000011B`, `0x1000011D`, +`0x10000111`) are handled the same way. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 1.1: Ghidra Project Setup | 3 | Correct project name, `ARM:LE:32:Cortex` (ARM Cortex 32-bit little endian), base `0x10000000` | One item off | Not set up | +| Criterion 1.2: main() and Status-Loop Addresses | 4 | Both addresses correct | One correct | Neither found | +| Criterion 1.3: Vector Table Decoding | 4 | Correct base, initial SP, reset pointer | One missing | Not found | +| Criterion 1.4: Thumb Addressing | 4 | Correctly clears bit 0 and identifies `main()` | General explanation | Incorrect | + +### Instructor Notes & Assembly + +- Confirm the Ghidra import used `Raw Binary`, `ARM:LE:32:Cortex`, base + `0x10000000`, and that auto-analysis completed before any address was read. +- Verify `main()` is `0x100001E0`, the loop head is `0x10000234`, and the + back-edge bytes `E5 E7` sit at `0x10000266`. +- The reset vector is stored as `0x1000015B`; the real Thumb entry is + `0x1000015A`. Do not accept the un-cleared `0x1000015B` as an instruction + address. + +--- + +## Task 2: Find and Patch Bug #1: The Miscalibrated Safety Threshold (30 points) + +### Solution + +`grid_deviation` is `volatile`, so the compiler emits two independent compares: +one for the operator status and one for the automated dispatch decision. + +**Criterion 2.1: Locate Compare Site A (5 points).** + +```text +100001fc: 2b5e cmp r3, #94 @ 0x5e +``` + +| Item | Value | +|------|-------| +| Address | `0x100001FC` | +| File offset | `0x1FC` | +| Original bytes | `5E 2B` | +| Original instruction | `cmp r3, #94` | + +**Criterion 2.2: Locate Compare Site B (5 points).** + +```text +1000020a: 2b5e cmp r3, #94 @ 0x5e +``` + +| Item | Value | +|------|-------| +| Address | `0x1000020A` | +| File offset | `0x20A` | +| Original bytes | `5E 2B` | +| Original instruction | `cmp r3, #94` | + +**Criterion 2.3: Correct Immediate-Value Reasoning (8 points).** +The source constant is `SAFE_THRESHOLD = 95` and the test is `x < 95`. For an +unsigned value, `x < 95` is exactly `x <= 94`, which the compiler emits as +`cmp r3, #94` plus `ite hi`. The correct engineering limit is `60`, so the test +is `x < 60`, which is `x <= 59`. The correct patched immediate is therefore +**`0x3B` (59)**, not `0x3C` (60). Patching to `0x3C` would wrongly accept a +reading of exactly 60. + +**Criterion 2.4: Patch Compare Site A (4 points).** + +| Address | File Offset | Original | Patched | Before | After | +|---------|-------------|----------|---------|--------|-------| +| `0x100001FC` | `0x1FC` | `5E 2B` | `3B 2B` | `cmp r3, #94` | `cmp r3, #59` | + +**Criterion 2.5: Patch Compare Site B (4 points).** + +| Address | File Offset | Original | Patched | Before | After | +|---------|-------------|----------|---------|--------|-------| +| `0x1000020A` | `0x20A` | `5E 2B` | `3B 2B` | `cmp r3, #94` | `cmp r3, #59` | + +**Criterion 2.6: Explain Why Both Sites Must Be Patched (4 points).** +`operator_state` (`0x20000844`) and `dispatch_state` (`0x20000834`) are each +computed from their own read of `grid_deviation`. Patching only site A fixes the +displayed text while the automated dispatch at site B still authorizes on the +dangerous reading. Frozen reading `87`: `87 <= 94` is true (STABLE/AUTHORIZED, +wrong); `87 <= 59` is false (CRITICAL/HELD, correct). + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 2.1: Locate Compare Site A | 5 | Correct address and original bytes | Address off | Not found | +| Criterion 2.2: Locate Compare Site B | 5 | Correct address and original bytes | Address off | Not found | +| Criterion 2.3: Correct Immediate-Value Reasoning | 8 | Explains the `<` to `<=` transform and gives `0x3B` | Correct value, no reasoning | Wrong value | +| Criterion 2.4: Patch Compare Site A | 4 | Byte change verified | Wrong byte | Not patched | +| Criterion 2.5: Patch Compare Site B | 4 | Byte change verified | Wrong byte | Not patched | +| Criterion 2.6: Explain Why Both Sites Must Be Patched | 4 | Clear explanation of the two independent comparisons | Vague | Missing | + +### Instructor Notes & Assembly + +- Both sites must be patched: `0x100001FC` for operator status and + `0x1000020A` for the automated dispatch decision. +- The correct immediate is `0x3B` (59), not `0x3C` (60); the source test is a + strict `<`, compiled as `<= 94`. +- Verify the byte changes on hardware: after patching, `operator_state` + (`0x20000844`) and `dispatch_state` (`0x20000834`) read `0` and `0`. +- **Ghidra ARM/Thumb Context Note:** In raw `.bin` files, patching an instruction + that precedes an `IT` block (`ite hi`) using the GUI *Patch Instruction* action + triggers Ghidra's `ReDisassembleCommand`. The re-disassembler encounters an + internal context register conflict when trying to re-declare the `ITBlock` + context over existing instructions, collapsing Thumb decoding into 32-bit ARM + mode and swallowing Site B (`0x1000020A`). Students must patch using the Bytes + window workflow (Clear `C` -> edit byte `5E` -> `3B` in Bytes window with pencil + icon -> Disassemble `D`) to keep Site B visible and cleanly aligned. + +--- + +## Task 3: Find and Patch Bug #2: The False Signal Banner (20 points) + +### Solution + +**Criterion 3.1: Locate the Banner String (5 points).** + +| String | Address | +|--------|---------| +| `"SIGNAL: NORMAL\r"` | `0x10003678` | +| `"NORMAL"` substring to patch | `0x10003680` | + +The string is loaded at call site `0x10000224` (`ldr r0, [pc, #92]` -> +`0x10003678`) and printed by `bl __wrap_puts` at `0x10000226`. It is printed +once at boot and never recomputed. + +**Criterion 3.2: Patch Six Characters (8 points).** +`NORMAL` and `DANGER` are both six ASCII characters, so the patch preserves the +string length. + +| Address Range | Original Bytes | Patched Bytes | +|---------------|----------------|---------------| +| `0x10003680` - `0x10003685` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | + +**Criterion 3.3: Character-by-Character Documentation (4 points).** + +| Address | Original Char | Original Byte | Patched Char | Patched Byte | +|---------|---------------|---------------|--------------|--------------| +| `0x10003680` | N | `4E` | D | `44` | +| `0x10003681` | O | `4F` | A | `41` | +| `0x10003682` | R | `52` | N | `4E` | +| `0x10003683` | M | `4D` | G | `47` | +| `0x10003684` | A | `41` | E | `45` | +| `0x10003685` | L | `4C` | R | `52` | + +**Criterion 3.4: Explain the Danger of a Hardcoded Status Word (3 points).** +The banner never consults the reading, so it reports a healthy line even while +the frozen reading is dangerous. Operators trust supervisory banners, so a +hardcoded `NORMAL` masks the hazard and prevents manual intervention. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 3.1: Locate the Banner String | 5 | Correct address | Approximate | Not found | +| Criterion 3.2: Patch Six Characters | 8 | All six bytes changed, length preserved | Correct text, wrong bytes documented | Wrong length | +| Criterion 3.3: Character-by-Character Documentation | 4 | Original vs patched byte for all six characters | Partial | Missing | +| Criterion 3.4: Explain the Danger of a Hardcoded Status Word | 3 | Clear, specific reasoning | Generic | Missing | + +### Instructor Notes & Assembly + +- `NORMAL` and `DANGER` are both six characters; the patch must not change the + string length or overwrite adjacent flash. +- The banner is printed once at boot and never recomputed, so it is a separate + defect from the threshold and must be graded independently. +- Confirm the patch covers `0x10003680` through `0x10003685` exactly. + +--- + +## Task 4: Recover the Quarantined Dispatch Frame (10 points) + +### Solution + +**Criterion 4.1: Recover the Dispatch Frame (6 points).** +Address `0x100037A0` in flash `.rodata`: + +```text +WORLDGRID:BLACKSTART:GRID-7:WATER-3 +``` + +**Criterion 4.2: Explain Why It Is Never Transmitted (4 points).** +`retain_dispatch_frame()` reads only the first character into a `volatile` local +so the linker keeps the string, but the pointer is never passed to any print or +UART routine. The frame is evidence only and must not be patched. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 4.1: Recover the Dispatch Frame | 6 | Correct address and full text | Partial text | Not found | +| Criterion 4.2: Explain Why It Is Never Transmitted | 4 | Clear static-analysis explanation | Vague | Missing | + +### Instructor Notes & Assembly + +- Accept the full string `WORLDGRID:BLACKSTART:GRID-7:WATER-3` at `0x100037A0` + in flash `.rodata`. +- The frame is evidence only. Penalize any submission that patches or rewrites + it instead of recovering it. + +--- + +## Task 5: Export and Verify (20 points) + +### Solution + +**Criterion 5.1: Export CTF-01_fixed.bin (4 points).** +Export the patched program from Ghidra (`File -> Export Program...`, `Binary +Format`) as `CTF-01_fixed.bin`. + +**Criterion 5.2: Convert to CTF-01_fixed.uf2 (4 points).** + +```bash +python uf2conv.py CTF-01_fixed.bin --base 0x10000000 --family 0xe48bff59 --output CTF-01_fixed.uf2 +``` + +**Criterion 5.3: Hardware Verification (8 points).** + +Before patching: + +```text +GLOBAL EMBEDDED RESPONSE NETWORK +BLACK START WINDOW: 27 MINUTES +UART0 115200 8N1 | AUTHORIZED LAB CONSOLE +SIGNAL: NORMAL +RESPONSE> GRID STATUS: STABLE +DISPATCH PATH: AUTHORIZED +LAST FRAME: QUARANTINED +RESPONSE> +``` + +After all three patches: + +```text +GLOBAL EMBEDDED RESPONSE NETWORK +BLACK START WINDOW: 27 MINUTES +UART0 115200 8N1 | AUTHORIZED LAB CONSOLE +SIGNAL: DANGER +RESPONSE> GRID STATUS: CRITICAL +DISPATCH PATH: HELD +LAST FRAME: QUARANTINED +RESPONSE> +``` + +If the console is not wired, the same proof is read over SWD: after reset, +`operator_state` (`0x20000844`) and `dispatch_state` (`0x20000834`) are `1` and +`1` for the shipped image, and `0` and `0` for the patched image. This has been +confirmed on real hardware. + +**Criterion 5.4: Summary Table of All Patches (4 points).** + +| # | What | Address(es) | Original | Patched | +|---|------|-------------|----------|---------| +| 1a | Operator threshold | `0x100001FC` | `5E 2B` | `3B 2B` | +| 1b | Dispatch threshold | `0x1000020A` | `5E 2B` | `3B 2B` | +| 2 | Signal banner | `0x10003680`-`0x10003685` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | + +Total: **8 bytes actually change** (one immediate byte at each compare site and +six string bytes). + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 5.1: Export CTF-01_fixed.bin | 4 | Valid patched binary | Corrupted | Not submitted | +| Criterion 5.2: Convert to CTF-01_fixed.uf2 | 4 | Correct base and family flags | Wrong flags | Not submitted | +| Criterion 5.3: Hardware Verification | 8 | Corrected console output confirmed on hardware | Some lines corrected | No verification | +| Criterion 5.4: Summary Table of All Patches | 4 | Complete address and before/after table | Missing entries | No table | + +### Instructor Notes & Assembly + +- Verify the exported image with `python3 scripts/verify_ctf.py`; the shipped + check expects `11/11 checks passed` against `CTF-01.bin`. +- Confirm the UF2 conversion used base `0x10000000` and family `0xe48bff59`. +- **Serial Terminal Timing:** Note that `print_boot_banner()` (`SIGNAL: DANGER`) + fires within the first 5 milliseconds of boot. In normal lab usage, PuTTY + attaches after boot and will display the continuous 1-second status loop + (`GRID STATUS: CRITICAL`, `DISPATCH PATH: HELD`). To see `SIGNAL: DANGER`, + the student must pulse `RUN` to `GND` while PuTTY is open, or demonstrate + the string change at `0x10003680` via Ghidra static analysis. +- If no console is available, accept the SWD capture showing `operator_state` + and `dispatch_state` at `0` and `0` on the patched image. + +--- + +## Task 6: Written Reflection (5 points) + +### Solution + +**Criterion 6.1: "Rushed Build" Is Not an Excuse (2 points).** +The missed review step is exactly what shipped the false-safe report; pressure +explains why the safeguard was skipped, not why it should be skipped. + +**Criterion 6.2: One Engineering Practice per Bug (3 points).** +- Bug #1 (duplicated threshold): a unit test or static-analysis rule that + requires every comparison against `SAFE_THRESHOLD` to use one shared source of + truth. +- Bug #2 (hardcoded banner): a hardware-in-the-loop smoke test that checks the + boot banner against the latched reading. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 6.1: "Rushed Build" Is Not an Excuse | 2 | Specific, grounded reasoning | Generic | Missing | +| Criterion 6.2: One Engineering Practice per Bug | 3 | Concrete practice for each bug | One bug only | Missing | + +### Instructor Notes & Assembly + +- Grade the specificity of the reasoning, not the length of the prose. +- Require one concrete engineering practice for each of the two bugs. + +--- + +## How To Breadboard + +- **Raspberry Pi Pico 2** powered over USB. +- **3.3 V USB-UART adapter**: + - Adapter RX to Pico GP0 (UART0 TX) + - Adapter TX to Pico GP1 (UART0 RX) + - Adapter GND to Pico GND + - Do not connect the adapter VCC while the Pico is USB powered. +- **Serial monitor:** 115200 baud, 8 data bits, no parity, 1 stop bit. +- No other peripherals are required; all evidence is obtained from the console. + +--- + +## Complete Grading Summary + +| Task | Title | Points | +|------|-------|--------| +| Task 1 | Setup and Initial Analysis | 15 | +| Task 2 | Find and Patch Bug #1: The Miscalibrated Safety Threshold | 30 | +| Task 3 | Find and Patch Bug #2: The False Signal Banner | 20 | +| Task 4 | Recover the Quarantined Dispatch Frame | 10 | +| Task 5 | Export and Verify | 20 | +| Task 6 | Written Reflection | 5 | +| **TOTAL** | | **100** | + +--- + +## Instructor Notes + +Safety: Use only the supplied Pico 2, 3.3 V UART adapter, and firmware. Never +connect the exercise to an operational grid, water plant, public network, +military system, or third-party device. + +### Common Student Mistakes + +- Patching only one threshold site (`0x100001FC` or `0x1000020A`), which leaves + one status line lying. +- Assuming the immediate equals the limit, producing an off-by-one boundary; + the correct byte is `0x3B` (59), not `0x3C` (60). +- Replacing the banner string with a different length, corrupting adjacent + flash; `NORMAL` and `DANGER` are both 6 bytes. +- Treating the odd vector address `0x1000015B` as invalid instead of clearing + bit 0 to get `0x1000015A`. +- Modifying the quarantined dispatch frame at `0x100037A0`, which destroys + evidence. + +### Partial Credit Guidelines + +- Award partial credit for one correct threshold site out of two, or for a + correct immediate value without the `<` to `<=` reasoning. +- Award partial credit for a correct banner text with incorrectly documented + bytes, or for partial character-by-character documentation. +- Accept an SWD read of `operator_state` and `dispatch_state` as equivalent + proof when no UART console is available. +- Award no credit for patches that change string length or overwrite adjacent + flash. + +--- + +## Appendix: Expected Binary Diff + +| # | What | File Offset(s) | Address(es) | Original Bytes | Patched Bytes | +|---|------|----------------|-------------|----------------|---------------| +| 1a | Operator threshold | `0x1FC` | `0x100001FC` | `5E 2B` | `3B 2B` | +| 1b | Dispatch threshold | `0x20A` | `0x1000020A` | `5E 2B` | `3B 2B` | +| 2 | Signal banner | `0x3680` - `0x3685` | `0x10003680` - `0x10003685` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | + +Total: **8 bytes actually change** (one immediate byte at each compare site and +six string bytes). diff --git a/WEEK04/0x0001b_ctf/CTF-01-S.pdf b/WEEK04/0x0001b_ctf/CTF-01-S.pdf new file mode 100644 index 0000000..1180fbe Binary files /dev/null and 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b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.bin differ diff --git a/WEEK04/0x0001b_ctf/build/0x0001b_ctf.dis b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.dis new file mode 100644 index 0000000..9e431d2 --- /dev/null +++ b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.dis @@ -0,0 +1,5918 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001b_ctf/build/0x0001b_ctf.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00003618 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000002b8 10003618 10003618 00004618 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100038d0 100038d0 000048d0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 100038d8 100038d8 000048d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .psram_load 00000000 11000000 11000000 00005e68 2**0 + CONTENTS + 5 .psram_noload 00000000 11000000 11000000 00005e68 2**0 + CONTENTS + 6 .xip_ram 00000000 13ffc000 13ffc000 00005e68 2**0 + CONTENTS + 7 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 8 .uninitialized_data 00000000 20000110 20000110 00005e68 2**0 + CONTENTS + 9 .data 00000550 20000110 10003904 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 10 .tdata 00000000 20000660 20000660 00005e68 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 11 .tbss 00000000 20000660 20000660 00000000 2**0 + ALLOC, THREAD_LOCAL + 12 .tbss_space 00000000 20000660 20000660 00005e68 2**0 + CONTENTS + 13 .bss 00000214 20000660 10003e54 00006660 2**3 + ALLOC + 14 .tls0 00000000 20000874 20000874 00005e68 2**0 + CONTENTS + 15 .tls1 00000000 20000874 20000874 00005e68 2**0 + CONTENTS + 16 .persistent_data 00000000 20000874 20000874 00005e68 2**0 + CONTENTS + 17 .dummy_pre_heap 00000000 20000874 20000874 00005e68 2**0 + CONTENTS + 18 .heap 00000800 20000874 20000874 00006000 2**2 + ALLOC, READONLY + 19 .scratch_x 00000000 20080000 20080000 00005e68 2**0 + CONTENTS + 20 .scratch_y 00000000 20081000 20081000 00005e68 2**0 + CONTENTS + 21 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 22 .flash_end 00000014 10003e54 10003e54 00005e54 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 23 .debug_info 00020d94 00000000 00000000 00005e68 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_abbrev 000057a8 00000000 00000000 00026bfc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_aranges 00000c70 00000000 00000000 0002c3a8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 26 .debug_rnglists 00003038 00000000 00000000 0002d018 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 27 .debug_line 000164bf 00000000 00000000 00030050 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 28 .debug_str 00005e57 00000000 00000000 0004650f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 29 .comment 00000045 00000000 00000000 0004c366 2**0 + CONTENTS, READONLY + 30 .ARM.attributes 00000036 00000000 00000000 0004c3ab 2**0 + CONTENTS, READONLY + 31 .debug_frame 00001f7c 00000000 00000000 0004c3e4 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 32 .debug_loclists 000101df 00000000 00000000 0004e360 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 33 .debug_line_str 000002b2 00000000 00000000 0005e53f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0001b_ctf/build/0x0001b_ctf.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015b .word 0x1000015b +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100038d8 .word 0x100038d8 +1000012c: 10003904 .word 0x10003904 +10000130: 1000019c .word 0x1000019c +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003d1c .word 0x00003d1c +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: 2000 movs r0, #0 + +1000014e <_enter_vtable_in_r0>: +1000014e: 491e ldr r1, [pc, #120] @ (100001c8 ) +10000150: 6008 str r0, [r1, #0] +10000152: c806 ldmia r0!, {r1, r2} +10000154: f381 8808 msr MSP, r1 +10000158: 4710 bx r2 + +1000015a <_reset_handler>: +1000015a: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +1000015e: 6800 ldr r0, [r0, #0] +10000160: b108 cbz r0, 10000166 + +10000162 : +10000162: 2000 movs r0, #0 +10000164: e7f3 b.n 1000014e <_enter_vtable_in_r0> +10000166: a40d add r4, pc, #52 @ (adr r4, 1000019c ) +10000168: cc0e ldmia r4!, {r1, r2, r3} +1000016a: 2900 cmp r1, #0 +1000016c: d002 beq.n 10000174 +1000016e: f000 f812 bl 10000196 +10000172: e7f9 b.n 10000168 +10000174: 4915 ldr r1, [pc, #84] @ (100001cc ) +10000176: 4a16 ldr r2, [pc, #88] @ (100001d0 ) +10000178: 2000 movs r0, #0 +1000017a: e000 b.n 1000017e + +1000017c : +1000017c: c101 stmia r1!, {r0} + +1000017e : +1000017e: 4291 cmp r1, r2 +10000180: d1fc bne.n 1000017c + +10000182 : +10000182: 4914 ldr r1, [pc, #80] @ (100001d4 ) +10000184: 4788 blx r1 +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: be00 bkpt 0x0000 +10000190: e7fd b.n 1000018e + +10000192 : +10000192: c901 ldmia r1!, {r0} +10000194: c201 stmia r2!, {r0} + +10000196 : +10000196: 429a cmp r2, r3 +10000198: d3fb bcc.n 10000192 + +1000019a : +1000019a: 4770 bx lr + +1000019c : +1000019c: 10003904 .word 0x10003904 +100001a0: 20000110 .word 0x20000110 +100001a4: 20000660 .word 0x20000660 +100001a8: 10003e54 .word 0x10003e54 +100001ac: 20080000 .word 0x20080000 +100001b0: 20080000 .word 0x20080000 +100001b4: 10003e54 .word 0x10003e54 +100001b8: 20081000 .word 0x20081000 +100001bc: 20081000 .word 0x20081000 +100001c0: 00000000 .word 0x00000000 +100001c4: 4770 bx lr +100001c6: 0000 .short 0x0000 +100001c8: e000ed08 .word 0xe000ed08 +100001cc: 20000660 .word 0x20000660 +100001d0: 20000874 .word 0x20000874 +100001d4: 10002e71 .word 0x10002e71 +100001d8: 100001e1 .word 0x100001e1 +100001dc: 10002e69 .word 0x10002e69 + +100001e0
: +100001e0: b508 push {r3, lr} +100001e2: f002 ff6f bl 100030c4 +100001e6: f000 f80b bl 10000200 +100001ea: f000 f815 bl 10000218 +100001ee: f000 f829 bl 10000244 +100001f2: f000 f843 bl 1000027c +100001f6: f44f 707a mov.w r0, #1000 @ 0x3e8 +100001fa: f000 fd7d bl 10000cf8 +100001fe: e7f8 b.n 100001f2 + +10000200 : +10000200: 4b04 ldr r3, [pc, #16] @ (10000214 ) +10000202: b082 sub sp, #8 +10000204: 781b ldrb r3, [r3, #0] +10000206: f88d 3007 strb.w r3, [sp, #7] +1000020a: f89d 3007 ldrb.w r3, [sp, #7] +1000020e: b002 add sp, #8 +10000210: 4770 bx lr +10000212: bf00 nop +10000214: 10003618 .word 0x10003618 + +10000218 : +10000218: 4a07 ldr r2, [pc, #28] @ (10000238 ) +1000021a: 4808 ldr r0, [pc, #32] @ (1000023c ) +1000021c: 6813 ldr r3, [r2, #0] +1000021e: 4908 ldr r1, [pc, #32] @ (10000240 ) +10000220: 2b5e cmp r3, #94 @ 0x5e +10000222: bf8c ite hi +10000224: 2300 movhi r3, #0 +10000226: 2301 movls r3, #1 +10000228: 6003 str r3, [r0, #0] +1000022a: 6813 ldr r3, [r2, #0] +1000022c: 2b5e cmp r3, #94 @ 0x5e +1000022e: bf8c ite hi +10000230: 2300 movhi r3, #0 +10000232: 2301 movls r3, #1 +10000234: 600b str r3, [r1, #0] +10000236: 4770 bx lr +10000238: 200005d8 .word 0x200005d8 +1000023c: 20000844 .word 0x20000844 +10000240: 20000834 .word 0x20000834 + +10000244 : +10000244: b508 push {r3, lr} +10000246: 4808 ldr r0, [pc, #32] @ (10000268 ) +10000248: f002 ff84 bl 10003154 <__wrap_puts> +1000024c: 4807 ldr r0, [pc, #28] @ (1000026c ) +1000024e: f002 ff81 bl 10003154 <__wrap_puts> +10000252: 4807 ldr r0, [pc, #28] @ (10000270 ) +10000254: f002 ff7e bl 10003154 <__wrap_puts> +10000258: 4806 ldr r0, [pc, #24] @ (10000274 ) +1000025a: f002 ff7b bl 10003154 <__wrap_puts> +1000025e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000262: 4805 ldr r0, [pc, #20] @ (10000278 ) +10000264: f002 bff4 b.w 10003250 <__wrap_printf> +10000268: 1000363c .word 0x1000363c +1000026c: 10003660 .word 0x10003660 +10000270: 10003680 .word 0x10003680 +10000274: 100036ac .word 0x100036ac +10000278: 100036bc .word 0x100036bc + +1000027c : +1000027c: b508 push {r3, lr} +1000027e: 4b0d ldr r3, [pc, #52] @ (100002b4 ) +10000280: 681b ldr r3, [r3, #0] +10000282: b193 cbz r3, 100002aa +10000284: 490c ldr r1, [pc, #48] @ (100002b8 ) +10000286: 480d ldr r0, [pc, #52] @ (100002bc ) +10000288: f002 ffe2 bl 10003250 <__wrap_printf> +1000028c: 4b0c ldr r3, [pc, #48] @ (100002c0 ) +1000028e: 681b ldr r3, [r3, #0] +10000290: b16b cbz r3, 100002ae +10000292: 490c ldr r1, [pc, #48] @ (100002c4 ) +10000294: 480c ldr r0, [pc, #48] @ (100002c8 ) +10000296: f002 ffdb bl 10003250 <__wrap_printf> +1000029a: 480c ldr r0, [pc, #48] @ (100002cc ) +1000029c: f002 ff5a bl 10003154 <__wrap_puts> +100002a0: e8bd 4008 ldmia.w sp!, {r3, lr} +100002a4: 480a ldr r0, [pc, #40] @ (100002d0 ) +100002a6: f002 bfd3 b.w 10003250 <__wrap_printf> +100002aa: 490a ldr r1, [pc, #40] @ (100002d4 ) +100002ac: e7eb b.n 10000286 +100002ae: 490a ldr r1, [pc, #40] @ (100002d8 ) +100002b0: e7f0 b.n 10000294 +100002b2: bf00 nop +100002b4: 20000844 .word 0x20000844 +100002b8: 100036c8 .word 0x100036c8 +100002bc: 100036f0 .word 0x100036f0 +100002c0: 20000834 .word 0x20000834 +100002c4: 100036dc .word 0x100036dc +100002c8: 10003704 .word 0x10003704 +100002cc: 10003718 .word 0x10003718 +100002d0: 100036bc .word 0x100036bc +100002d4: 100036d0 .word 0x100036d0 +100002d8: 100036e8 .word 0x100036e8 + +100002dc : +100002dc: f44f 7c80 mov.w ip, #256 @ 0x100 +100002e0: 4b0c ldr r3, [pc, #48] @ (10000314 ) +100002e2: b500 push {lr} +100002e4: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100002e8: eb03 0380 add.w r3, r3, r0, lsl #2 +100002ec: 00c0 lsls r0, r0, #3 +100002ee: f082 0240 eor.w r2, r2, #64 @ 0x40 +100002f2: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100002f6: f503 5e80 add.w lr, r3, #4096 @ 0x1000 +100002fa: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100002fe: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000302: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000306: f8ce 2000 str.w r2, [lr] +1000030a: 6041 str r1, [r0, #4] +1000030c: f8c3 c000 str.w ip, [r3] +10000310: bd00 pop {pc} +10000312: bf00 nop +10000314: 40038004 .word 0x40038004 + +10000318 : +10000318: b40f push {r0, r1, r2, r3} +1000031a: b500 push {lr} +1000031c: 4808 ldr r0, [pc, #32] @ (10000340 ) +1000031e: b083 sub sp, #12 +10000320: f002 ff18 bl 10003154 <__wrap_puts> +10000324: 9b04 ldr r3, [sp, #16] +10000326: b13b cbz r3, 10000338 +10000328: a905 add r1, sp, #20 +1000032a: 4618 mov r0, r3 +1000032c: 9101 str r1, [sp, #4] +1000032e: f002 fd7f bl 10002e30 +10000332: 4804 ldr r0, [pc, #16] @ (10000344 ) +10000334: f002 ff0e bl 10003154 <__wrap_puts> +10000338: 2001 movs r0, #1 +1000033a: f002 fd91 bl 10002e60 <_exit> +1000033e: bf00 nop +10000340: 10003734 .word 0x10003734 +10000344: 10003730 .word 0x10003730 + +10000348 : +10000348: b570 push {r4, r5, r6, lr} +1000034a: 4616 mov r6, r2 +1000034c: f3ef 8410 mrs r4, PRIMASK +10000350: b672 cpsid i +10000352: f8df e048 ldr.w lr, [pc, #72] @ 1000039c +10000356: e8de 2fcf ldaexb r2, [lr] +1000035a: 2301 movs r3, #1 +1000035c: 2a00 cmp r2, #0 +1000035e: d1fa bne.n 10000356 +10000360: e8ce 3f42 strexb r2, r3, [lr] +10000364: 2a00 cmp r2, #0 +10000366: d1f6 bne.n 10000356 +10000368: f3bf 8f5f dmb sy +1000036c: 2301 movs r3, #1 +1000036e: f001 0c07 and.w ip, r1, #7 +10000372: 08ca lsrs r2, r1, #3 +10000374: fa03 f30c lsl.w r3, r3, ip +10000378: f810 c002 ldrb.w ip, [r0, r2] +1000037c: ea1c 0503 ands.w r5, ip, r3 +10000380: d108 bne.n 10000394 +10000382: ea4c 0c03 orr.w ip, ip, r3 +10000386: f800 c002 strb.w ip, [r0, r2] +1000038a: e8ce 5f8f stlb r5, [lr] +1000038e: f384 8810 msr PRIMASK, r4 +10000392: bd70 pop {r4, r5, r6, pc} +10000394: 4630 mov r0, r6 +10000396: f7ff ffbf bl 10000318 +1000039a: bf00 nop +1000039c: 200007eb .word 0x200007eb + +100003a0 : +100003a0: 4a04 ldr r2, [pc, #16] @ (100003b4 ) +100003a2: 7810 ldrb r0, [r2, #0] +100003a4: 1c43 adds r3, r0, #1 +100003a6: b2db uxtb r3, r3 +100003a8: 2b18 cmp r3, #24 +100003aa: bf28 it cs +100003ac: 2310 movcs r3, #16 +100003ae: 7013 strb r3, [r2, #0] +100003b0: 4770 bx lr +100003b2: bf00 nop +100003b4: 200005dc .word 0x200005dc + +100003b8 : +100003b8: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100003bc: 6893 ldr r3, [r2, #8] +100003be: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100003c2: 6093 str r3, [r2, #8] +100003c4: 4770 bx lr +100003c6: bf00 nop + +100003c8 : +100003c8: 2100 movs r1, #0 +100003ca: 4b04 ldr r3, [pc, #16] @ (100003dc ) +100003cc: f103 0220 add.w r2, r3, #32 +100003d0: e8c3 1f8f stlb r1, [r3] +100003d4: 3301 adds r3, #1 +100003d6: 4293 cmp r3, r2 +100003d8: d1fa bne.n 100003d0 +100003da: 4770 bx lr +100003dc: 200007e0 .word 0x200007e0 + +100003e0 : +100003e0: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100003e4: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100003e8: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100003ec: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100003f0: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100003f4: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100003f8: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100003fc: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000400: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000404: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000408: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000040c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000410: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000414: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000418: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000041c: b662 cpsie i +1000041e: 4770 bx lr + +10000420 : +10000420: 2301 movs r3, #1 +10000422: f000 021f and.w r2, r0, #31 +10000426: 4093 lsls r3, r2 +10000428: 0940 lsrs r0, r0, #5 +1000042a: b141 cbz r1, 1000043e +1000042c: 0080 lsls r0, r0, #2 +1000042e: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000432: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000436: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000043a: 6003 str r3, [r0, #0] +1000043c: 4770 bx lr +1000043e: 4a02 ldr r2, [pc, #8] @ (10000448 ) +10000440: 3020 adds r0, #32 +10000442: f842 3020 str.w r3, [r2, r0, lsl #2] +10000446: 4770 bx lr +10000448: e000e100 .word 0xe000e100 + +1000044c : +1000044c: b508 push {r3, lr} +1000044e: f3ef 8e10 mrs lr, PRIMASK +10000452: b672 cpsid i +10000454: 4b13 ldr r3, [pc, #76] @ (100004a4 ) +10000456: e8d3 cfcf ldaexb ip, [r3] +1000045a: 2201 movs r2, #1 +1000045c: f1bc 0f00 cmp.w ip, #0 +10000460: d1f9 bne.n 10000456 +10000462: e8c3 2f4c strexb ip, r2, [r3] +10000466: f1bc 0f00 cmp.w ip, #0 +1000046a: d1f4 bne.n 10000456 +1000046c: f3bf 8f5f dmb sy +10000470: 4a0d ldr r2, [pc, #52] @ (100004a8 ) +10000472: 3010 adds r0, #16 +10000474: 6892 ldr r2, [r2, #8] +10000476: f8df c034 ldr.w ip, [pc, #52] @ 100004ac +1000047a: f852 2020 ldr.w r2, [r2, r0, lsl #2] +1000047e: 4562 cmp r2, ip +10000480: d001 beq.n 10000486 +10000482: 4291 cmp r1, r2 +10000484: d10b bne.n 1000049e +10000486: 4a08 ldr r2, [pc, #32] @ (100004a8 ) +10000488: 6892 ldr r2, [r2, #8] +1000048a: f842 1020 str.w r1, [r2, r0, lsl #2] +1000048e: f3bf 8f5f dmb sy +10000492: 2200 movs r2, #0 +10000494: e8c3 2f8f stlb r2, [r3] +10000498: f38e 8810 msr PRIMASK, lr +1000049c: bd08 pop {r3, pc} +1000049e: f000 fef9 bl 10001294 +100004a2: bf00 nop +100004a4: 200007e9 .word 0x200007e9 +100004a8: e000ed00 .word 0xe000ed00 +100004ac: 10000111 .word 0x10000111 + +100004b0 : +100004b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100004b4: b082 sub sp, #8 +100004b6: f3ef 8510 mrs r5, PRIMASK +100004ba: b672 cpsid i +100004bc: f8df c1a8 ldr.w ip, [pc, #424] @ 10000668 +100004c0: e8dc 2fcf ldaexb r2, [ip] +100004c4: 2301 movs r3, #1 +100004c6: 2a00 cmp r2, #0 +100004c8: d1fa bne.n 100004c0 +100004ca: e8cc 3f42 strexb r2, r3, [ip] +100004ce: 2a00 cmp r2, #0 +100004d0: d1f6 bne.n 100004c0 +100004d2: f3bf 8f5f dmb sy +100004d6: 4b5e ldr r3, [pc, #376] @ (10000650 ) +100004d8: f100 0410 add.w r4, r0, #16 +100004dc: 689b ldr r3, [r3, #8] +100004de: f853 2024 ldr.w r2, [r3, r4, lsl #2] +100004e2: 4b5c ldr r3, [pc, #368] @ (10000654 ) +100004e4: 429a cmp r2, r3 +100004e6: d03d beq.n 10000564 +100004e8: 428a cmp r2, r1 +100004ea: d049 beq.n 10000580 +100004ec: f8df e17c ldr.w lr, [pc, #380] @ 1000066c +100004f0: eba2 030e sub.w r3, r2, lr +100004f4: 2b2f cmp r3, #47 @ 0x2f +100004f6: d835 bhi.n 10000564 +100004f8: 2701 movs r7, #1 +100004fa: 0943 lsrs r3, r0, #5 +100004fc: 009b lsls r3, r3, #2 +100004fe: f000 001f and.w r0, r0, #31 +10000502: f103 4360 add.w r3, r3, #3758096384 @ 0xe0000000 +10000506: f503 4361 add.w r3, r3, #57600 @ 0xe100 +1000050a: 4087 lsls r7, r0 +1000050c: 681e ldr r6, [r3, #0] +1000050e: 469a mov sl, r3 +10000510: 46b9 mov r9, r7 +10000512: f8c3 7080 str.w r7, [r3, #128] @ 0x80 +10000516: f3bf 8f5f dmb sy +1000051a: f3ef 8305 mrs r3, IPSR +1000051e: b2db uxtb r3, r3 +10000520: 461f mov r7, r3 +10000522: bb7b cbnz r3, 10000584 +10000524: 2301 movs r3, #1 +10000526: 4083 lsls r3, r0 +10000528: f022 0001 bic.w r0, r2, #1 +1000052c: ea03 0806 and.w r8, r3, r6 +10000530: 6886 ldr r6, [r0, #8] +10000532: 42b1 cmp r1, r6 +10000534: d108 bne.n 10000548 +10000536: e081 b.n 1000063c +10000538: eb03 0343 add.w r3, r3, r3, lsl #1 +1000053c: eb0e 0383 add.w r3, lr, r3, lsl #2 +10000540: 689e ldr r6, [r3, #8] +10000542: 42b1 cmp r1, r6 +10000544: d025 beq.n 10000592 +10000546: 4618 mov r0, r3 +10000548: f990 3006 ldrsb.w r3, [r0, #6] +1000054c: 2b00 cmp r3, #0 +1000054e: daf3 bge.n 10000538 +10000550: 42b1 cmp r1, r6 +10000552: d04e beq.n 100005f2 +10000554: 4653 mov r3, sl +10000556: f1b8 0f00 cmp.w r8, #0 +1000055a: d017 beq.n 1000058c +1000055c: f8c3 9180 str.w r9, [r3, #384] @ 0x180 +10000560: f8c3 9000 str.w r9, [r3] +10000564: 4b3a ldr r3, [pc, #232] @ (10000650 ) +10000566: 689b ldr r3, [r3, #8] +10000568: f843 2024 str.w r2, [r3, r4, lsl #2] +1000056c: f3bf 8f5f dmb sy +10000570: 2300 movs r3, #0 +10000572: e8cc 3f8f stlb r3, [ip] +10000576: f385 8810 msr PRIMASK, r5 +1000057a: b002 add sp, #8 +1000057c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10000580: 461a mov r2, r3 +10000582: e7ef b.n 10000564 +10000584: 429c cmp r4, r3 +10000586: d0cd beq.n 10000524 +10000588: f000 fe84 bl 10001294 +1000058c: f8c3 9080 str.w r9, [r3, #128] @ 0x80 +10000590: e7e8 b.n 10000564 +10000592: f993 6006 ldrsb.w r6, [r3, #6] +10000596: 2e00 cmp r6, #0 +10000598: db2c blt.n 100005f4 +1000059a: eb06 0046 add.w r0, r6, r6, lsl #1 +1000059e: eb0e 0180 add.w r1, lr, r0, lsl #2 +100005a2: 0080 lsls r0, r0, #2 +100005a4: 9001 str r0, [sp, #4] +100005a6: 79c8 ldrb r0, [r1, #7] +100005a8: 688f ldr r7, [r1, #8] +100005aa: 71d8 strb r0, [r3, #7] +100005ac: f991 0006 ldrsb.w r0, [r1, #6] +100005b0: 609f str r7, [r3, #8] +100005b2: 2800 cmp r0, #0 +100005b4: 7198 strb r0, [r3, #6] +100005b6: ea4f 0746 mov.w r7, r6, lsl #1 +100005ba: db2e blt.n 1000061a +100005bc: 8889 ldrh r1, [r1, #4] +100005be: 9801 ldr r0, [sp, #4] +100005c0: f341 010a sbfx r1, r1, #0, #11 +100005c4: eb00 0141 add.w r1, r0, r1, lsl #1 +100005c8: f06f 0007 mvn.w r0, #7 +100005cc: 3108 adds r1, #8 +100005ce: 4471 add r1, lr +100005d0: 1ac0 subs r0, r0, r3 +100005d2: 4401 add r1, r0 +100005d4: f3c1 014a ubfx r1, r1, #1, #11 +100005d8: ea6f 41c1 mvn.w r1, r1, lsl #19 +100005dc: ea6f 41d1 mvn.w r1, r1, lsr #19 +100005e0: 8099 strh r1, [r3, #4] +100005e2: 491d ldr r1, [pc, #116] @ (10000658 ) +100005e4: 19bb adds r3, r7, r6 +100005e6: 7808 ldrb r0, [r1, #0] +100005e8: eb0e 0383 add.w r3, lr, r3, lsl #2 +100005ec: 700e strb r6, [r1, #0] +100005ee: 7198 strb r0, [r3, #6] +100005f0: e7b0 b.n 10000554 +100005f2: 4603 mov r3, r0 +100005f4: b99f cbnz r7, 1000061e +100005f6: 21ff movs r1, #255 @ 0xff +100005f8: 7181 strb r1, [r0, #6] +100005fa: f64b 5101 movw r1, #48385 @ 0xbd01 +100005fe: 8081 strh r1, [r0, #4] +10000600: 4e15 ldr r6, [pc, #84] @ (10000658 ) +10000602: 4618 mov r0, r3 +10000604: 7837 ldrb r7, [r6, #0] +10000606: f64a 21aa movw r1, #43690 @ 0xaaaa +1000060a: 719f strb r7, [r3, #6] +1000060c: 4673 mov r3, lr +1000060e: 1ac0 subs r0, r0, r3 +10000610: 4140 adcs r0, r0 +10000612: 4341 muls r1, r0 +10000614: 0d09 lsrs r1, r1, #20 +10000616: 7031 strb r1, [r6, #0] +10000618: e79c b.n 10000554 +1000061a: 4910 ldr r1, [pc, #64] @ (1000065c ) +1000061c: e7e0 b.n 100005e0 +1000061e: 4910 ldr r1, [pc, #64] @ (10000660 ) +10000620: 4e10 ldr r6, [pc, #64] @ (10000664 ) +10000622: 1ac9 subs r1, r1, r3 +10000624: 3908 subs r1, #8 +10000626: f3c1 300a ubfx r0, r1, #12, #11 +1000062a: ea6f 5000 mvn.w r0, r0, lsl #20 +1000062e: ea6f 5010 mvn.w r0, r0, lsr #20 +10000632: ea46 0151 orr.w r1, r6, r1, lsr #1 +10000636: 80d9 strh r1, [r3, #6] +10000638: 8098 strh r0, [r3, #4] +1000063a: e78b b.n 10000554 +1000063c: f990 6006 ldrsb.w r6, [r0, #6] +10000640: 4603 mov r3, r0 +10000642: 2e00 cmp r6, #0 +10000644: daa9 bge.n 1000059a +10000646: 2f00 cmp r7, #0 +10000648: d1e9 bne.n 1000061e +1000064a: 4a02 ldr r2, [pc, #8] @ (10000654 ) +1000064c: e7d8 b.n 10000600 +1000064e: bf00 nop +10000650: e000ed00 .word 0xe000ed00 +10000654: 10000111 .word 0x10000111 +10000658: 20000870 .word 0x20000870 +1000065c: ffffbd01 .word 0xffffbd01 +10000660: 2000061a .word 0x2000061a +10000664: fffff800 .word 0xfffff800 +10000668: 200007e9 .word 0x200007e9 +1000066c: 200005e0 .word 0x200005e0 + +10000670 : +10000670: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000674: f3ef 8305 mrs r3, IPSR +10000678: b2db uxtb r3, r3 +1000067a: 469e mov lr, r3 +1000067c: f3ef 8510 mrs r5, PRIMASK +10000680: b672 cpsid i +10000682: 4929 ldr r1, [pc, #164] @ (10000728 ) +10000684: e8d1 2fcf ldaexb r2, [r1] +10000688: 2301 movs r3, #1 +1000068a: 2a00 cmp r2, #0 +1000068c: d1fa bne.n 10000684 +1000068e: e8c1 3f42 strexb r2, r3, [r1] +10000692: 2a00 cmp r2, #0 +10000694: d1f6 bne.n 10000684 +10000696: f3bf 8f5f dmb sy +1000069a: f8df 809c ldr.w r8, [pc, #156] @ 10000738 +1000069e: f040 0601 orr.w r6, r0, #1 +100006a2: f8d8 7008 ldr.w r7, [r8, #8] +100006a6: f64a 23aa movw r3, #43690 @ 0xaaaa +100006aa: f857 702e ldr.w r7, [r7, lr, lsl #2] +100006ae: 4604 mov r4, r0 +100006b0: 4a1e ldr r2, [pc, #120] @ (1000072c ) +100006b2: 1aa4 subs r4, r4, r2 +100006b4: 4164 adcs r4, r4 +100006b6: 4363 muls r3, r4 +100006b8: 0d1b lsrs r3, r3, #20 +100006ba: 42b7 cmp r7, r6 +100006bc: b25b sxtb r3, r3 +100006be: d01e beq.n 100006fe +100006c0: f992 4006 ldrsb.w r4, [r2, #6] +100006c4: 429c cmp r4, r3 +100006c6: d020 beq.n 1000070a +100006c8: f992 4012 ldrsb.w r4, [r2, #18] +100006cc: 429c cmp r4, r3 +100006ce: d027 beq.n 10000720 +100006d0: f992 401e ldrsb.w r4, [r2, #30] +100006d4: 429c cmp r4, r3 +100006d6: d025 beq.n 10000724 +100006d8: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100006dc: 429c cmp r4, r3 +100006de: bf08 it eq +100006e0: 2403 moveq r4, #3 +100006e2: d013 beq.n 1000070c +100006e4: 4a12 ldr r2, [pc, #72] @ (10000730 ) +100006e6: 2400 movs r4, #0 +100006e8: f892 c000 ldrb.w ip, [r2] +100006ec: 7013 strb r3, [r2, #0] +100006ee: f880 c006 strb.w ip, [r0, #6] +100006f2: e8c1 4f8f stlb r4, [r1] +100006f6: f385 8810 msr PRIMASK, r5 +100006fa: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100006fe: f8d8 2008 ldr.w r2, [r8, #8] +10000702: 4c0c ldr r4, [pc, #48] @ (10000734 ) +10000704: f842 402e str.w r4, [r2, lr, lsl #2] +10000708: e7ec b.n 100006e4 +1000070a: 2400 movs r4, #0 +1000070c: eb04 0444 add.w r4, r4, r4, lsl #1 +10000710: eb02 0284 add.w r2, r2, r4, lsl #2 +10000714: 24ff movs r4, #255 @ 0xff +10000716: 7194 strb r4, [r2, #6] +10000718: f64b 5401 movw r4, #48385 @ 0xbd01 +1000071c: 8094 strh r4, [r2, #4] +1000071e: e7e1 b.n 100006e4 +10000720: 2401 movs r4, #1 +10000722: e7f3 b.n 1000070c +10000724: 2402 movs r4, #2 +10000726: e7f1 b.n 1000070c +10000728: 200007e9 .word 0x200007e9 +1000072c: 200005e0 .word 0x200005e0 +10000730: 20000870 .word 0x20000870 +10000734: 10000111 .word 0x10000111 +10000738: e000ed00 .word 0xe000ed00 + +1000073c : +1000073c: 4b01 ldr r3, [pc, #4] @ (10000744 ) +1000073e: 440b add r3, r1 +10000740: 6003 str r3, [r0, #0] +10000742: 4770 bx lr +10000744: 200007e0 .word 0x200007e0 + +10000748 : +10000748: b570 push {r4, r5, r6, lr} +1000074a: 4c10 ldr r4, [pc, #64] @ (1000078c ) +1000074c: 4d10 ldr r5, [pc, #64] @ (10000790 ) +1000074e: 42ac cmp r4, r5 +10000750: d20e bcs.n 10000770 +10000752: 26ff movs r6, #255 @ 0xff +10000754: 6823 ldr r3, [r4, #0] +10000756: b163 cbz r3, 10000772 +10000758: f7ff fe22 bl 100003a0 +1000075c: 4601 mov r1, r0 +1000075e: 4620 mov r0, r4 +10000760: f7ff ffec bl 1000073c +10000764: 80a6 strh r6, [r4, #4] +10000766: f3bf 8f5f dmb sy +1000076a: 3408 adds r4, #8 +1000076c: 42ac cmp r4, r5 +1000076e: d3f1 bcc.n 10000754 +10000770: bd70 pop {r4, r5, r6, pc} +10000772: f7ff fe15 bl 100003a0 +10000776: 4601 mov r1, r0 +10000778: 4620 mov r0, r4 +1000077a: f7ff ffdf bl 1000073c +1000077e: 7126 strb r6, [r4, #4] +10000780: f3bf 8f5f dmb sy +10000784: 3408 adds r4, #8 +10000786: 42ac cmp r4, r5 +10000788: d3e4 bcc.n 10000754 +1000078a: bd70 pop {r4, r5, r6, pc} +1000078c: 20000658 .word 0x20000658 +10000790: 20000660 .word 0x20000660 + +10000794 : +10000794: bf40 sev +10000796: 2000 movs r0, #0 +10000798: 2100 movs r1, #0 +1000079a: 4770 bx lr + +1000079c : +1000079c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007a0: b085 sub sp, #20 +100007a2: f3ef 8305 mrs r3, IPSR +100007a6: b2db uxtb r3, r3 +100007a8: 3b10 subs r3, #16 +100007aa: 089a lsrs r2, r3, #2 +100007ac: bf1a itte ne +100007ae: 2201 movne r2, #1 +100007b0: 4999 ldrne r1, [pc, #612] @ (10000a18 ) +100007b2: 499a ldreq r1, [pc, #616] @ (10000a1c ) +100007b4: f003 0a03 and.w sl, r3, #3 +100007b8: 9100 str r1, [sp, #0] +100007ba: 2101 movs r1, #1 +100007bc: 4b98 ldr r3, [pc, #608] @ (10000a20 ) +100007be: eb0a 0282 add.w r2, sl, r2, lsl #2 +100007c2: f853 4022 ldr.w r4, [r3, r2, lsl #2] +100007c6: 9b00 ldr r3, [sp, #0] +100007c8: fa01 f20a lsl.w r2, r1, sl +100007cc: f503 5341 add.w r3, r3, #12352 @ 0x3040 +100007d0: f104 0b08 add.w fp, r4, #8 +100007d4: 9201 str r2, [sp, #4] +100007d6: 605a str r2, [r3, #4] +100007d8: f9b4 6008 ldrsh.w r6, [r4, #8] +100007dc: e9dd 0300 ldrd r0, r3, [sp] +100007e0: 2e00 cmp r6, #0 +100007e2: 63c3 str r3, [r0, #60] @ 0x3c +100007e4: da72 bge.n 100008cc +100007e6: 88a3 ldrh r3, [r4, #4] +100007e8: 041b lsls r3, r3, #16 +100007ea: f100 811b bmi.w 10000a24 +100007ee: 6923 ldr r3, [r4, #16] +100007f0: f3ef 8210 mrs r2, PRIMASK +100007f4: b672 cpsid i +100007f6: e8d3 0fcf ldaexb r0, [r3] +100007fa: 2101 movs r1, #1 +100007fc: 2800 cmp r0, #0 +100007fe: d1fa bne.n 100007f6 +10000800: e8c3 1f40 strexb r0, r1, [r3] +10000804: 2800 cmp r0, #0 +10000806: d1f6 bne.n 100007f6 +10000808: f3bf 8f5f dmb sy +1000080c: f64f 76ff movw r6, #65535 @ 0xffff +10000810: 88a0 ldrh r0, [r4, #4] +10000812: 2100 movs r1, #0 +10000814: 6923 ldr r3, [r4, #16] +10000816: b200 sxth r0, r0 +10000818: 80a6 strh r6, [r4, #4] +1000081a: e8c3 1f8f stlb r1, [r3] +1000081e: f382 8810 msr PRIMASK, r2 +10000822: 4288 cmp r0, r1 +10000824: db28 blt.n 10000878 +10000826: 46a6 mov lr, r4 +10000828: 4605 mov r5, r0 +1000082a: 6967 ldr r7, [r4, #20] +1000082c: f9be 3008 ldrsh.w r3, [lr, #8] +10000830: eb05 0645 add.w r6, r5, r5, lsl #1 +10000834: 2b00 cmp r3, #0 +10000836: 46dc mov ip, fp +10000838: eb07 02c6 add.w r2, r7, r6, lsl #3 +1000083c: db13 blt.n 10000866 +1000083e: e9d2 4002 ldrd r4, r0, [r2, #8] +10000842: 46a9 mov r9, r5 +10000844: e004 b.n 10000850 +10000846: f937 3038 ldrsh.w r3, [r7, r8, lsl #3] +1000084a: 4694 mov ip, r2 +1000084c: 2b00 cmp r3, #0 +1000084e: db09 blt.n 10000864 +10000850: eb03 0843 add.w r8, r3, r3, lsl #1 +10000854: eb07 02c8 add.w r2, r7, r8, lsl #3 +10000858: e9d2 5102 ldrd r5, r1, [r2, #8] +1000085c: 42ac cmp r4, r5 +1000085e: eb70 0101 sbcs.w r1, r0, r1 +10000862: daf0 bge.n 10000846 +10000864: 464d mov r5, r9 +10000866: f8ac 5000 strh.w r5, [ip] +1000086a: f937 5036 ldrsh.w r5, [r7, r6, lsl #3] +1000086e: f827 3036 strh.w r3, [r7, r6, lsl #3] +10000872: 2d00 cmp r5, #0 +10000874: dada bge.n 1000082c +10000876: 4674 mov r4, lr +10000878: f9b4 3008 ldrsh.w r3, [r4, #8] +1000087c: 2b00 cmp r3, #0 +1000087e: f2c0 811b blt.w 10000ab8 +10000882: 6962 ldr r2, [r4, #20] +10000884: 9d00 ldr r5, [sp, #0] +10000886: eb03 0343 add.w r3, r3, r3, lsl #1 +1000088a: eb02 03c3 add.w r3, r2, r3, lsl #3 +1000088e: eb05 008a add.w r0, r5, sl, lsl #2 +10000892: 6aa9 ldr r1, [r5, #40] @ 0x28 +10000894: 689e ldr r6, [r3, #8] +10000896: 6902 ldr r2, [r0, #16] +10000898: eba6 0c01 sub.w ip, r6, r1 +1000089c: 1a52 subs r2, r2, r1 +1000089e: 4594 cmp ip, r2 +100008a0: 68df ldr r7, [r3, #12] +100008a2: d305 bcc.n 100008b0 +100008a4: 2301 movs r3, #1 +100008a6: 6a2a ldr r2, [r5, #32] +100008a8: fa03 f30a lsl.w r3, r3, sl +100008ac: 4213 tst r3, r2 +100008ae: d100 bne.n 100008b2 +100008b0: 6106 str r6, [r0, #16] +100008b2: 79a3 ldrb r3, [r4, #6] +100008b4: 2b00 cmp r3, #0 +100008b6: d149 bne.n 1000094c +100008b8: 9800 ldr r0, [sp, #0] +100008ba: f000 fb0b bl 10000ed4 +100008be: 42b0 cmp r0, r6 +100008c0: 41b9 sbcs r1, r7 +100008c2: da89 bge.n 100007d8 +100008c4: bf40 sev +100008c6: b005 add sp, #20 +100008c8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100008cc: f8d4 9014 ldr.w r9, [r4, #20] +100008d0: eb06 0846 add.w r8, r6, r6, lsl #1 +100008d4: eb09 07c8 add.w r7, r9, r8, lsl #3 +100008d8: 68bb ldr r3, [r7, #8] +100008da: 68fd ldr r5, [r7, #12] +100008dc: 9302 str r3, [sp, #8] +100008de: f000 faf9 bl 10000ed4 +100008e2: 9b02 ldr r3, [sp, #8] +100008e4: 4298 cmp r0, r3 +100008e6: 41a9 sbcs r1, r5 +100008e8: db2b blt.n 10000942 +100008ea: e9d7 3104 ldrd r3, r1, [r7, #16] +100008ee: 2b02 cmp r3, #2 +100008f0: d06b beq.n 100009ca +100008f2: 887a ldrh r2, [r7, #2] +100008f4: f9b4 0008 ldrsh.w r0, [r4, #8] +100008f8: b292 uxth r2, r2 +100008fa: ea42 4000 orr.w r0, r2, r0, lsl #16 +100008fe: 4798 blx r3 +10000900: 4602 mov r2, r0 +10000902: 460b mov r3, r1 +10000904: ea52 0103 orrs.w r1, r2, r3 +10000908: d065 beq.n 100009d6 +1000090a: 2b00 cmp r3, #0 +1000090c: f280 80aa bge.w 10000a64 +10000910: 9902 ldr r1, [sp, #8] +10000912: ebb1 0c02 subs.w ip, r1, r2 +10000916: eb65 0e03 sbc.w lr, r5, r3 +1000091a: f939 3038 ldrsh.w r3, [r9, r8, lsl #3] +1000091e: e9c7 ce02 strd ip, lr, [r7, #8] +10000922: 2b00 cmp r3, #0 +10000924: db0d blt.n 10000942 +10000926: 6960 ldr r0, [r4, #20] +10000928: eb03 0243 add.w r2, r3, r3, lsl #1 +1000092c: eb00 02c2 add.w r2, r0, r2, lsl #3 +10000930: e9d2 7102 ldrd r7, r1, [r2, #8] +10000934: 45bc cmp ip, r7 +10000936: eb7e 0501 sbcs.w r5, lr, r1 +1000093a: ea4f 0243 mov.w r2, r3, lsl #1 +1000093e: f280 809d bge.w 10000a7c +10000942: 88a3 ldrh r3, [r4, #4] +10000944: 0418 lsls r0, r3, #16 +10000946: f57f af52 bpl.w 100007ee +1000094a: e795 b.n 10000878 +1000094c: f04f 0800 mov.w r8, #0 +10000950: f884 8006 strb.w r8, [r4, #6] +10000954: f9b4 3008 ldrsh.w r3, [r4, #8] +10000958: 1c59 adds r1, r3, #1 +1000095a: d0ad beq.n 100008b8 +1000095c: 46dc mov ip, fp +1000095e: f8cd a008 str.w sl, [sp, #8] +10000962: e002 b.n 1000096a +10000964: 1c5a adds r2, r3, #1 +10000966: 46ac mov ip, r5 +10000968: d02c beq.n 100009c4 +1000096a: 6962 ldr r2, [r4, #20] +1000096c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000970: eb02 05c1 add.w r5, r2, r1, lsl #3 +10000974: f8b5 e002 ldrh.w lr, [r5, #2] +10000978: 4618 mov r0, r3 +1000097a: f41e 4f00 tst.w lr, #32768 @ 0x8000 +1000097e: f932 3031 ldrsh.w r3, [r2, r1, lsl #3] +10000982: d0ef beq.n 10000964 +10000984: 6925 ldr r5, [r4, #16] +10000986: f8ac 3000 strh.w r3, [ip] +1000098a: f3ef 8e10 mrs lr, PRIMASK +1000098e: b672 cpsid i +10000990: e8d5 afcf ldaexb sl, [r5] +10000994: f05f 0901 movs.w r9, #1 +10000998: f1ba 0f00 cmp.w sl, #0 +1000099c: d1f8 bne.n 10000990 +1000099e: e8c5 9f4a strexb sl, r9, [r5] +100009a2: f1ba 0f00 cmp.w sl, #0 +100009a6: d1f3 bne.n 10000990 +100009a8: f3bf 8f5f dmb sy +100009ac: f8b4 9002 ldrh.w r9, [r4, #2] +100009b0: 6925 ldr r5, [r4, #16] +100009b2: f822 9031 strh.w r9, [r2, r1, lsl #3] +100009b6: 8060 strh r0, [r4, #2] +100009b8: e8c5 8f8f stlb r8, [r5] +100009bc: f38e 8810 msr PRIMASK, lr +100009c0: 1c5a adds r2, r3, #1 +100009c2: d1d2 bne.n 1000096a +100009c4: f8dd a008 ldr.w sl, [sp, #8] +100009c8: e776 b.n 100008b8 +100009ca: 4608 mov r0, r1 +100009cc: 690b ldr r3, [r1, #16] +100009ce: 9103 str r1, [sp, #12] +100009d0: 4798 blx r3 +100009d2: 2800 cmp r0, #0 +100009d4: d139 bne.n 10000a4a +100009d6: f839 3038 ldrh.w r3, [r9, r8, lsl #3] +100009da: 8123 strh r3, [r4, #8] +100009dc: 6923 ldr r3, [r4, #16] +100009de: f3ef 8210 mrs r2, PRIMASK +100009e2: b672 cpsid i +100009e4: e8d3 0fcf ldaexb r0, [r3] +100009e8: 2101 movs r1, #1 +100009ea: 2800 cmp r0, #0 +100009ec: d1fa bne.n 100009e4 +100009ee: e8c3 1f40 strexb r0, r1, [r3] +100009f2: 2800 cmp r0, #0 +100009f4: d1f6 bne.n 100009e4 +100009f6: f3bf 8f5f dmb sy +100009fa: 8863 ldrh r3, [r4, #2] +100009fc: 6921 ldr r1, [r4, #16] +100009fe: f829 3038 strh.w r3, [r9, r8, lsl #3] +10000a02: 2300 movs r3, #0 +10000a04: 8066 strh r6, [r4, #2] +10000a06: e8c1 3f8f stlb r3, [r1] +10000a0a: f382 8810 msr PRIMASK, r2 +10000a0e: 88a3 ldrh r3, [r4, #4] +10000a10: 0418 lsls r0, r3, #16 +10000a12: f57f aeec bpl.w 100007ee +10000a16: e72f b.n 10000878 +10000a18: 400b8000 .word 0x400b8000 +10000a1c: 400b0000 .word 0x400b0000 +10000a20: 20000848 .word 0x20000848 +10000a24: 4604 mov r4, r0 +10000a26: 4620 mov r0, r4 +10000a28: f000 fa54 bl 10000ed4 +10000a2c: f100 4200 add.w r2, r0, #2147483648 @ 0x80000000 +10000a30: eb04 008a add.w r0, r4, sl, lsl #2 +10000a34: 6aa3 ldr r3, [r4, #40] @ 0x28 +10000a36: 6901 ldr r1, [r0, #16] +10000a38: 1ac9 subs r1, r1, r3 +10000a3a: 1ad3 subs r3, r2, r3 +10000a3c: 428b cmp r3, r1 +10000a3e: d208 bcs.n 10000a52 +10000a40: 6102 str r2, [r0, #16] +10000a42: bf40 sev +10000a44: b005 add sp, #20 +10000a46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a4a: 9903 ldr r1, [sp, #12] +10000a4c: e9d1 2300 ldrd r2, r3, [r1] +10000a50: e758 b.n 10000904 +10000a52: 2301 movs r3, #1 +10000a54: 6a21 ldr r1, [r4, #32] +10000a56: fa03 f30a lsl.w r3, r3, sl +10000a5a: 420b tst r3, r1 +10000a5c: f47f af32 bne.w 100008c4 +10000a60: 6102 str r2, [r0, #16] +10000a62: e7ee b.n 10000a42 +10000a64: 9800 ldr r0, [sp, #0] +10000a66: e9cd 2302 strd r2, r3, [sp, #8] +10000a6a: f000 fa33 bl 10000ed4 +10000a6e: 9a02 ldr r2, [sp, #8] +10000a70: 9b03 ldr r3, [sp, #12] +10000a72: eb10 0c02 adds.w ip, r0, r2 +10000a76: eb43 0e01 adc.w lr, r3, r1 +10000a7a: e74e b.n 1000091a +10000a7c: 4625 mov r5, r4 +10000a7e: f825 3f08 strh.w r3, [r5, #8]! +10000a82: e006 b.n 10000a92 +10000a84: eb03 0243 add.w r2, r3, r3, lsl #1 +10000a88: eb00 02c2 add.w r2, r0, r2, lsl #3 +10000a8c: e9d2 7102 ldrd r7, r1, [r2, #8] +10000a90: 005a lsls r2, r3, #1 +10000a92: 45bc cmp ip, r7 +10000a94: eb7e 0101 sbcs.w r1, lr, r1 +10000a98: 441a add r2, r3 +10000a9a: db05 blt.n 10000aa8 +10000a9c: f930 3032 ldrsh.w r3, [r0, r2, lsl #3] +10000aa0: eb00 05c2 add.w r5, r0, r2, lsl #3 +10000aa4: 2b00 cmp r3, #0 +10000aa6: daed bge.n 10000a84 +10000aa8: f829 3038 strh.w r3, [r9, r8, lsl #3] +10000aac: 802e strh r6, [r5, #0] +10000aae: 88a3 ldrh r3, [r4, #4] +10000ab0: 0418 lsls r0, r3, #16 +10000ab2: f57f ae9c bpl.w 100007ee +10000ab6: e6df b.n 10000878 +10000ab8: 9c00 ldr r4, [sp, #0] +10000aba: e7b4 b.n 10000a26 + +10000abc : +10000abc: b538 push {r3, r4, r5, lr} +10000abe: 4b33 ldr r3, [pc, #204] @ (10000b8c ) +10000ac0: 691c ldr r4, [r3, #16] +10000ac2: b104 cbz r4, 10000ac6 +10000ac4: bd38 pop {r3, r4, r5, pc} +10000ac6: 2103 movs r1, #3 +10000ac8: 4831 ldr r0, [pc, #196] @ (10000b90 ) +10000aca: f000 f9f1 bl 10000eb0 +10000ace: 4d30 ldr r5, [pc, #192] @ (10000b90 ) +10000ad0: 4b2e ldr r3, [pc, #184] @ (10000b8c ) +10000ad2: 60dd str r5, [r3, #12] +10000ad4: f7ff fc64 bl 100003a0 +10000ad8: 4a2e ldr r2, [pc, #184] @ (10000b94 ) +10000ada: f04f 4e50 mov.w lr, #3489660928 @ 0xd0000000 +10000ade: 4402 add r2, r0 +10000ae0: 2003 movs r0, #3 +10000ae2: 4b2a ldr r3, [pc, #168] @ (10000b8c ) +10000ae4: f04f 0c0f mov.w ip, #15 +10000ae8: 7018 strb r0, [r3, #0] +10000aea: 611a str r2, [r3, #16] +10000aec: f8de 2000 ldr.w r2, [lr] +10000af0: f64f 71ff movw r1, #65535 @ 0xffff +10000af4: 705a strb r2, [r3, #1] +10000af6: 695a ldr r2, [r3, #20] +10000af8: f8a3 c002 strh.w ip, [r3, #2] +10000afc: 8314 strh r4, [r2, #24] +10000afe: f04f 0402 mov.w r4, #2 +10000b02: f8a2 4048 strh.w r4, [r2, #72] @ 0x48 +10000b06: f04f 0404 mov.w r4, #4 +10000b0a: f8a2 4078 strh.w r4, [r2, #120] @ 0x78 +10000b0e: f04f 0405 mov.w r4, #5 +10000b12: f8a2 4090 strh.w r4, [r2, #144] @ 0x90 +10000b16: f04f 0406 mov.w r4, #6 +10000b1a: f8a2 40a8 strh.w r4, [r2, #168] @ 0xa8 +10000b1e: f04f 0407 mov.w r4, #7 +10000b22: f8a2 40c0 strh.w r4, [r2, #192] @ 0xc0 +10000b26: f04f 0409 mov.w r4, #9 +10000b2a: f8a2 40f0 strh.w r4, [r2, #240] @ 0xf0 +10000b2e: f04f 040a mov.w r4, #10 +10000b32: f8a2 4108 strh.w r4, [r2, #264] @ 0x108 +10000b36: f04f 040b mov.w r4, #11 +10000b3a: f8a2 4120 strh.w r4, [r2, #288] @ 0x120 +10000b3e: f04f 040c mov.w r4, #12 +10000b42: f8a2 4138 strh.w r4, [r2, #312] @ 0x138 +10000b46: f04f 0401 mov.w r4, #1 +10000b4a: 8614 strh r4, [r2, #48] @ 0x30 +10000b4c: f04f 0408 mov.w r4, #8 +10000b50: f8a2 40d8 strh.w r4, [r2, #216] @ 0xd8 +10000b54: 4c10 ldr r4, [pc, #64] @ (10000b98 ) +10000b56: f04f 0e0d mov.w lr, #13 +10000b5a: f04f 0c0e mov.w ip, #14 +10000b5e: 609c str r4, [r3, #8] +10000b60: 2408 movs r4, #8 +10000b62: 8099 strh r1, [r3, #4] +10000b64: f8a2 e150 strh.w lr, [r2, #336] @ 0x150 +10000b68: f8a2 c168 strh.w ip, [r2, #360] @ 0x168 +10000b6c: f8a2 0060 strh.w r0, [r2, #96] @ 0x60 +10000b70: 8011 strh r1, [r2, #0] +10000b72: 4a0a ldr r2, [pc, #40] @ (10000b9c ) +10000b74: 490a ldr r1, [pc, #40] @ (10000ba0 ) +10000b76: 622c str r4, [r5, #32] +10000b78: 60d3 str r3, [r2, #12] +10000b7a: f7ff fc67 bl 1000044c +10000b7e: 2101 movs r1, #1 +10000b80: 2003 movs r0, #3 +10000b82: f7ff fc4d bl 10000420 +10000b86: 4b07 ldr r3, [pc, #28] @ (10000ba4 ) +10000b88: 641c str r4, [r3, #64] @ 0x40 +10000b8a: bd38 pop {r3, r4, r5, pc} +10000b8c: 20000628 .word 0x20000628 +10000b90: 400b0000 .word 0x400b0000 +10000b94: 200007e0 .word 0x200007e0 +10000b98: 0010ffff .word 0x0010ffff +10000b9c: 20000848 .word 0x20000848 +10000ba0: 1000079d .word 0x1000079d +10000ba4: 400b2000 .word 0x400b2000 + +10000ba8 : +10000ba8: b5f0 push {r4, r5, r6, r7, lr} +10000baa: 4616 mov r6, r2 +10000bac: 461f mov r7, r3 +10000bae: 6902 ldr r2, [r0, #16] +10000bb0: 4603 mov r3, r0 +10000bb2: f3ef 8010 mrs r0, PRIMASK +10000bb6: b672 cpsid i +10000bb8: e8d2 4fcf ldaexb r4, [r2] +10000bbc: 2101 movs r1, #1 +10000bbe: 2c00 cmp r4, #0 +10000bc0: d1fa bne.n 10000bb8 +10000bc2: e8c2 1f44 strexb r4, r1, [r2] +10000bc6: 2c00 cmp r4, #0 +10000bc8: d1f6 bne.n 10000bb8 +10000bca: f3bf 8f5f dmb sy +10000bce: f9b3 1002 ldrsh.w r1, [r3, #2] +10000bd2: 691d ldr r5, [r3, #16] +10000bd4: 2900 cmp r1, #0 +10000bd6: db45 blt.n 10000c64 +10000bd8: f8d3 e014 ldr.w lr, [r3, #20] +10000bdc: eb01 0241 add.w r2, r1, r1, lsl #1 +10000be0: f83e 4032 ldrh.w r4, [lr, r2, lsl #3] +10000be4: eb0e 0cc2 add.w ip, lr, r2, lsl #3 +10000be8: 805c strh r4, [r3, #2] +10000bea: 2400 movs r4, #0 +10000bec: e8c5 4f8f stlb r4, [r5] +10000bf0: f380 8810 msr PRIMASK, r0 +10000bf4: 9805 ldr r0, [sp, #20] +10000bf6: 4635 mov r5, r6 +10000bf8: f8cc 0010 str.w r0, [ip, #16] +10000bfc: 9806 ldr r0, [sp, #24] +10000bfe: 463e mov r6, r7 +10000c00: f8cc 0014 str.w r0, [ip, #20] +10000c04: f8bc 0002 ldrh.w r0, [ip, #2] +10000c08: e9cc 5602 strd r5, r6, [ip, #8] +10000c0c: 3001 adds r0, #1 +10000c0e: f3c0 000e ubfx r0, r0, #0, #15 +10000c12: 2801 cmp r0, #1 +10000c14: bf38 it cc +10000c16: 2001 movcc r0, #1 +10000c18: f8ac 0002 strh.w r0, [ip, #2] +10000c1c: ea40 4001 orr.w r0, r0, r1, lsl #16 +10000c20: f8d3 c010 ldr.w ip, [r3, #16] +10000c24: f3ef 8510 mrs r5, PRIMASK +10000c28: b672 cpsid i +10000c2a: e8dc 7fcf ldaexb r7, [ip] +10000c2e: 2601 movs r6, #1 +10000c30: 2f00 cmp r7, #0 +10000c32: d1fa bne.n 10000c2a +10000c34: e8cc 6f47 strexb r7, r6, [ip] +10000c38: 2f00 cmp r7, #0 +10000c3a: d1f6 bne.n 10000c2a +10000c3c: f3bf 8f5f dmb sy +10000c40: f8b3 c004 ldrh.w ip, [r3, #4] +10000c44: f82e c032 strh.w ip, [lr, r2, lsl #3] +10000c48: 8099 strh r1, [r3, #4] +10000c4a: 691a ldr r2, [r3, #16] +10000c4c: e8c2 4f8f stlb r4, [r2] +10000c50: f385 8810 msr PRIMASK, r5 +10000c54: 2101 movs r1, #1 +10000c56: 781c ldrb r4, [r3, #0] +10000c58: 68da ldr r2, [r3, #12] +10000c5a: 40a1 lsls r1, r4 +10000c5c: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c60: 6059 str r1, [r3, #4] +10000c62: bdf0 pop {r4, r5, r6, r7, pc} +10000c64: 2300 movs r3, #0 +10000c66: e8c5 3f8f stlb r3, [r5] +10000c6a: f380 8810 msr PRIMASK, r0 +10000c6e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c72: bdf0 pop {r4, r5, r6, r7, pc} + +10000c74 : +10000c74: 4603 mov r3, r0 +10000c76: 8940 ldrh r0, [r0, #10] +10000c78: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c7c: dd3a ble.n 10000cf4 +10000c7e: 6958 ldr r0, [r3, #20] +10000c80: 140a asrs r2, r1, #16 +10000c82: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c86: b510 push {r4, lr} +10000c88: f8d3 c010 ldr.w ip, [r3, #16] +10000c8c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c90: f3ef 8e10 mrs lr, PRIMASK +10000c94: b672 cpsid i +10000c96: e8dc 4fcf ldaexb r4, [ip] +10000c9a: 2201 movs r2, #1 +10000c9c: 2c00 cmp r4, #0 +10000c9e: d1fa bne.n 10000c96 +10000ca0: e8cc 2f44 strexb r4, r2, [ip] +10000ca4: 2c00 cmp r4, #0 +10000ca6: d1f6 bne.n 10000c96 +10000ca8: f3bf 8f5f dmb sy +10000cac: 8842 ldrh r2, [r0, #2] +10000cae: b289 uxth r1, r1 +10000cb0: b292 uxth r2, r2 +10000cb2: 428a cmp r2, r1 +10000cb4: d007 beq.n 10000cc6 +10000cb6: 2200 movs r2, #0 +10000cb8: 691b ldr r3, [r3, #16] +10000cba: e8c3 2f8f stlb r2, [r3] +10000cbe: f38e 8810 msr PRIMASK, lr +10000cc2: 2000 movs r0, #0 +10000cc4: bd10 pop {r4, pc} +10000cc6: ea6f 4242 mvn.w r2, r2, lsl #17 +10000cca: ea6f 4252 mvn.w r2, r2, lsr #17 +10000cce: 8042 strh r2, [r0, #2] +10000cd0: 2101 movs r1, #1 +10000cd2: 2200 movs r2, #0 +10000cd4: 6918 ldr r0, [r3, #16] +10000cd6: 7199 strb r1, [r3, #6] +10000cd8: e8c0 2f8f stlb r2, [r0] +10000cdc: f38e 8810 msr PRIMASK, lr +10000ce0: f893 c000 ldrb.w ip, [r3] +10000ce4: 68da ldr r2, [r3, #12] +10000ce6: 4608 mov r0, r1 +10000ce8: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000cec: fa01 f10c lsl.w r1, r1, ip +10000cf0: 6059 str r1, [r3, #4] +10000cf2: bd10 pop {r4, pc} +10000cf4: 2000 movs r0, #0 +10000cf6: 4770 bx lr + +10000cf8 : +10000cf8: b5f0 push {r4, r5, r6, r7, lr} +10000cfa: b083 sub sp, #12 +10000cfc: 4606 mov r6, r0 +10000cfe: f000 f8f1 bl 10000ee4 +10000d02: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000d06: 4604 mov r4, r0 +10000d08: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000d0c: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000d10: fbe6 4103 umlal r4, r1, r6, r3 +10000d14: 42a0 cmp r0, r4 +10000d16: eb72 0301 sbcs.w r3, r2, r1 +10000d1a: bf3a itte cc +10000d1c: 4604 movcc r4, r0 +10000d1e: 4615 movcc r5, r2 +10000d20: 460d movcs r5, r1 +10000d22: 1fa6 subs r6, r4, #6 +10000d24: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000d28: 42b4 cmp r4, r6 +10000d2a: eb75 0307 sbcs.w r3, r5, r7 +10000d2e: bf3c itt cc +10000d30: 2600 movcc r6, #0 +10000d32: 4637 movcc r7, r6 +10000d34: f000 f8d6 bl 10000ee4 +10000d38: 1a30 subs r0, r6, r0 +10000d3a: eb67 0101 sbc.w r1, r7, r1 +10000d3e: 2801 cmp r0, #1 +10000d40: f171 0100 sbcs.w r1, r1, #0 +10000d44: da06 bge.n 10000d54 +10000d46: 4620 mov r0, r4 +10000d48: 4629 mov r1, r5 +10000d4a: b003 add sp, #12 +10000d4c: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} +10000d50: f000 b902 b.w 10000f58 +10000d54: f000 f8c6 bl 10000ee4 +10000d58: 4286 cmp r6, r0 +10000d5a: eb67 0101 sbc.w r1, r7, r1 +10000d5e: 2900 cmp r1, #0 +10000d60: db0a blt.n 10000d78 +10000d62: 2100 movs r1, #0 +10000d64: 4b0a ldr r3, [pc, #40] @ (10000d90 ) +10000d66: 4632 mov r2, r6 +10000d68: 9300 str r3, [sp, #0] +10000d6a: 480a ldr r0, [pc, #40] @ (10000d94 ) +10000d6c: 463b mov r3, r7 +10000d6e: 9101 str r1, [sp, #4] +10000d70: f7ff ff1a bl 10000ba8 +10000d74: 3001 adds r0, #1 +10000d76: d0e6 beq.n 10000d46 +10000d78: 4a07 ldr r2, [pc, #28] @ (10000d98 ) +10000d7a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000d7c: 429f cmp r7, r3 +10000d7e: d804 bhi.n 10000d8a +10000d80: 6a91 ldr r1, [r2, #40] @ 0x28 +10000d82: 42b1 cmp r1, r6 +10000d84: d2df bcs.n 10000d46 +10000d86: 429f cmp r7, r3 +10000d88: d1dd bne.n 10000d46 +10000d8a: bf20 wfe +10000d8c: e7f5 b.n 10000d7a +10000d8e: bf00 nop +10000d90: 10000795 .word 0x10000795 +10000d94: 20000628 .word 0x20000628 +10000d98: 400b0000 .word 0x400b0000 + +10000d9c : +10000d9c: f3ef 8205 mrs r2, IPSR +10000da0: b2d2 uxtb r2, r2 +10000da2: b17a cbz r2, 10000dc4 +10000da4: 4a3f ldr r2, [pc, #252] @ (10000ea4 ) +10000da6: 6a53 ldr r3, [r2, #36] @ 0x24 +10000da8: 428b cmp r3, r1 +10000daa: d309 bcc.n 10000dc0 +10000dac: bf14 ite ne +10000dae: 2301 movne r3, #1 +10000db0: 2300 moveq r3, #0 +10000db2: 6a92 ldr r2, [r2, #40] @ 0x28 +10000db4: 4282 cmp r2, r0 +10000db6: bf34 ite cc +10000db8: 4618 movcc r0, r3 +10000dba: f043 0001 orrcs.w r0, r3, #1 +10000dbe: 4770 bx lr +10000dc0: 2000 movs r0, #0 +10000dc2: 4770 bx lr +10000dc4: b570 push {r4, r5, r6, lr} +10000dc6: 4b38 ldr r3, [pc, #224] @ (10000ea8 ) +10000dc8: b084 sub sp, #16 +10000dca: 68dd ldr r5, [r3, #12] +10000dcc: 4606 mov r6, r0 +10000dce: 4628 mov r0, r5 +10000dd0: 781c ldrb r4, [r3, #0] +10000dd2: e9cd 1202 strd r1, r2, [sp, #8] +10000dd6: f000 f87d bl 10000ed4 +10000dda: f104 0c04 add.w ip, r4, #4 +10000dde: f855 c02c ldr.w ip, [r5, ip, lsl #2] +10000de2: 9b02 ldr r3, [sp, #8] +10000de4: ebac 0c00 sub.w ip, ip, r0 +10000de8: 1a30 subs r0, r6, r0 +10000dea: eb63 0101 sbc.w r1, r3, r1 +10000dee: 4560 cmp r0, ip +10000df0: f171 0100 sbcs.w r1, r1, #0 +10000df4: 9a03 ldr r2, [sp, #12] +10000df6: db1a blt.n 10000e2e +10000df8: 4a2a ldr r2, [pc, #168] @ (10000ea4 ) +10000dfa: 6a51 ldr r1, [r2, #36] @ 0x24 +10000dfc: 4299 cmp r1, r3 +10000dfe: d307 bcc.n 10000e10 +10000e00: 6a92 ldr r2, [r2, #40] @ 0x28 +10000e02: 42b2 cmp r2, r6 +10000e04: d201 bcs.n 10000e0a +10000e06: 4299 cmp r1, r3 +10000e08: d002 beq.n 10000e10 +10000e0a: 2001 movs r0, #1 +10000e0c: b004 add sp, #16 +10000e0e: bd70 pop {r4, r5, r6, pc} +10000e10: bf20 wfe +10000e12: 4a24 ldr r2, [pc, #144] @ (10000ea4 ) +10000e14: 6a51 ldr r1, [r2, #36] @ 0x24 +10000e16: 4299 cmp r1, r3 +10000e18: d32d bcc.n 10000e76 +10000e1a: bf14 ite ne +10000e1c: 2001 movne r0, #1 +10000e1e: 2000 moveq r0, #0 +10000e20: 6a93 ldr r3, [r2, #40] @ 0x28 +10000e22: 42b3 cmp r3, r6 +10000e24: bf28 it cs +10000e26: f040 0001 orrcs.w r0, r0, #1 +10000e2a: b004 add sp, #16 +10000e2c: bd70 pop {r4, r5, r6, pc} +10000e2e: e9cd 2302 strd r2, r3, [sp, #8] +10000e32: f000 f857 bl 10000ee4 +10000e36: 9b03 ldr r3, [sp, #12] +10000e38: 4286 cmp r6, r0 +10000e3a: eb63 0101 sbc.w r1, r3, r1 +10000e3e: 2900 cmp r1, #0 +10000e40: 9a02 ldr r2, [sp, #8] +10000e42: db1b blt.n 10000e7c +10000e44: 4919 ldr r1, [pc, #100] @ (10000eac ) +10000e46: 4818 ldr r0, [pc, #96] @ (10000ea8 ) +10000e48: e9cd 1200 strd r1, r2, [sp] +10000e4c: 4632 mov r2, r6 +10000e4e: 9302 str r3, [sp, #8] +10000e50: f7ff feaa bl 10000ba8 +10000e54: 1e01 subs r1, r0, #0 +10000e56: 9b02 ldr r3, [sp, #8] +10000e58: dd10 ble.n 10000e7c +10000e5a: 4a12 ldr r2, [pc, #72] @ (10000ea4 ) +10000e5c: 6a50 ldr r0, [r2, #36] @ 0x24 +10000e5e: 4298 cmp r0, r3 +10000e60: d219 bcs.n 10000e96 +10000e62: bf20 wfe +10000e64: 4810 ldr r0, [pc, #64] @ (10000ea8 ) +10000e66: 9302 str r3, [sp, #8] +10000e68: f7ff ff04 bl 10000c74 +10000e6c: 4a0d ldr r2, [pc, #52] @ (10000ea4 ) +10000e6e: 9b02 ldr r3, [sp, #8] +10000e70: 6a51 ldr r1, [r2, #36] @ 0x24 +10000e72: 4299 cmp r1, r3 +10000e74: d2d1 bcs.n 10000e1a +10000e76: 2000 movs r0, #0 +10000e78: b004 add sp, #16 +10000e7a: bd70 pop {r4, r5, r6, pc} +10000e7c: 4a09 ldr r2, [pc, #36] @ (10000ea4 ) +10000e7e: 6a50 ldr r0, [r2, #36] @ 0x24 +10000e80: 4298 cmp r0, r3 +10000e82: d3f8 bcc.n 10000e76 +10000e84: 1ac0 subs r0, r0, r3 +10000e86: bf18 it ne +10000e88: 2001 movne r0, #1 +10000e8a: 6a93 ldr r3, [r2, #40] @ 0x28 +10000e8c: 42b3 cmp r3, r6 +10000e8e: bf28 it cs +10000e90: f040 0001 orrcs.w r0, r0, #1 +10000e94: e7c9 b.n 10000e2a +10000e96: 6a92 ldr r2, [r2, #40] @ 0x28 +10000e98: 42b2 cmp r2, r6 +10000e9a: d2e3 bcs.n 10000e64 +10000e9c: 4298 cmp r0, r3 +10000e9e: d1e1 bne.n 10000e64 +10000ea0: e7df b.n 10000e62 +10000ea2: bf00 nop +10000ea4: 400b0000 .word 0x400b0000 +10000ea8: 20000628 .word 0x20000628 +10000eac: 10000795 .word 0x10000795 + +10000eb0 : +10000eb0: b410 push {r4} +10000eb2: 4b05 ldr r3, [pc, #20] @ (10000ec8 ) +10000eb4: 4c05 ldr r4, [pc, #20] @ (10000ecc ) +10000eb6: 4a06 ldr r2, [pc, #24] @ (10000ed0 ) +10000eb8: 42a0 cmp r0, r4 +10000eba: bf14 ite ne +10000ebc: 4618 movne r0, r3 +10000ebe: 1c58 addeq r0, r3, #1 +10000ec0: bc10 pop {r4} +10000ec2: f7ff ba41 b.w 10000348 +10000ec6: bf00 nop +10000ec8: 20000808 .word 0x20000808 +10000ecc: 400b8000 .word 0x400b8000 +10000ed0: 10003744 .word 0x10003744 + +10000ed4 : +10000ed4: 4603 mov r3, r0 +10000ed6: 6a41 ldr r1, [r0, #36] @ 0x24 +10000ed8: 460a mov r2, r1 +10000eda: 6a98 ldr r0, [r3, #40] @ 0x28 +10000edc: 6a59 ldr r1, [r3, #36] @ 0x24 +10000ede: 428a cmp r2, r1 +10000ee0: d1fa bne.n 10000ed8 +10000ee2: 4770 bx lr + +10000ee4 : +10000ee4: 4b03 ldr r3, [pc, #12] @ (10000ef4 ) +10000ee6: 6a59 ldr r1, [r3, #36] @ 0x24 +10000ee8: 460a mov r2, r1 +10000eea: 6a98 ldr r0, [r3, #40] @ 0x28 +10000eec: 6a59 ldr r1, [r3, #36] @ 0x24 +10000eee: 4291 cmp r1, r2 +10000ef0: d1fa bne.n 10000ee8 +10000ef2: 4770 bx lr +10000ef4: 400b0000 .word 0x400b0000 + +10000ef8 : +10000ef8: b500 push {lr} +10000efa: 468e mov lr, r1 +10000efc: 4a15 ldr r2, [pc, #84] @ (10000f54 ) +10000efe: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f00: 469c mov ip, r3 +10000f02: 6a91 ldr r1, [r2, #40] @ 0x28 +10000f04: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f06: 4563 cmp r3, ip +10000f08: d1fa bne.n 10000f00 +10000f0a: 1840 adds r0, r0, r1 +10000f0c: eb53 030e adcs.w r3, r3, lr +10000f10: f04f 0200 mov.w r2, #0 +10000f14: bf28 it cs +10000f16: 2201 movcs r2, #1 +10000f18: b1ba cbz r2, 10000f4a +10000f1a: 4b0e ldr r3, [pc, #56] @ (10000f54 ) +10000f1c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f1e: 1c53 adds r3, r2, #1 +10000f20: bf08 it eq +10000f22: 4610 moveq r0, r2 +10000f24: d008 beq.n 10000f38 +10000f26: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10000f2a: 4618 mov r0, r3 +10000f2c: 4909 ldr r1, [pc, #36] @ (10000f54 ) +10000f2e: 6a4a ldr r2, [r1, #36] @ 0x24 +10000f30: 429a cmp r2, r3 +10000f32: d3fc bcc.n 10000f2e +10000f34: 429a cmp r2, r3 +10000f36: d107 bne.n 10000f48 +10000f38: 4b06 ldr r3, [pc, #24] @ (10000f54 ) +10000f3a: e002 b.n 10000f42 +10000f3c: 6a59 ldr r1, [r3, #36] @ 0x24 +10000f3e: 4291 cmp r1, r2 +10000f40: d102 bne.n 10000f48 +10000f42: 6a99 ldr r1, [r3, #40] @ 0x28 +10000f44: 4281 cmp r1, r0 +10000f46: d3f9 bcc.n 10000f3c +10000f48: bd00 pop {pc} +10000f4a: 4a02 ldr r2, [pc, #8] @ (10000f54 ) +10000f4c: 6a52 ldr r2, [r2, #36] @ 0x24 +10000f4e: 4293 cmp r3, r2 +10000f50: d8ec bhi.n 10000f2c +10000f52: e7ef b.n 10000f34 +10000f54: 400b0000 .word 0x400b0000 + +10000f58 : +10000f58: 4a07 ldr r2, [pc, #28] @ (10000f78 ) +10000f5a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f5c: 4299 cmp r1, r3 +10000f5e: d8fc bhi.n 10000f5a +10000f60: 4299 cmp r1, r3 +10000f62: d107 bne.n 10000f74 +10000f64: 4b04 ldr r3, [pc, #16] @ (10000f78 ) +10000f66: e002 b.n 10000f6e +10000f68: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f6a: 4291 cmp r1, r2 +10000f6c: d102 bne.n 10000f74 +10000f6e: 6a9a ldr r2, [r3, #40] @ 0x28 +10000f70: 4290 cmp r0, r2 +10000f72: d8f9 bhi.n 10000f68 +10000f74: 4770 bx lr +10000f76: bf00 nop +10000f78: 400b0000 .word 0x400b0000 + +10000f7c : +10000f7c: b570 push {r4, r5, r6, lr} +10000f7e: 4604 mov r4, r0 +10000f80: b082 sub sp, #8 +10000f82: 2006 movs r0, #6 +10000f84: 460e mov r6, r1 +10000f86: f000 f8ef bl 10001168 +10000f8a: 2800 cmp r0, #0 +10000f8c: d044 beq.n 10001018 +10000f8e: 4a38 ldr r2, [pc, #224] @ (10001070 ) +10000f90: 4838 ldr r0, [pc, #224] @ (10001074 ) +10000f92: 4294 cmp r4, r2 +10000f94: bf14 ite ne +10000f96: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000f9a: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000f9e: 4b36 ldr r3, [pc, #216] @ (10001078 ) +10000fa0: 4936 ldr r1, [pc, #216] @ (1000107c ) +10000fa2: 6002 str r2, [r0, #0] +10000fa4: 601a str r2, [r3, #0] +10000fa6: 688d ldr r5, [r1, #8] +10000fa8: ea32 0505 bics.w r5, r2, r5 +10000fac: d1fb bne.n 10000fa6 +10000fae: 4a30 ldr r2, [pc, #192] @ (10001070 ) +10000fb0: f44f 7080 mov.w r0, #256 @ 0x100 +10000fb4: 1aa2 subs r2, r4, r2 +10000fb6: fab2 f282 clz r2, r2 +10000fba: 4931 ldr r1, [pc, #196] @ (10001080 ) +10000fbc: 0952 lsrs r2, r2, #5 +10000fbe: f821 0012 strh.w r0, [r1, r2, lsl #1] +10000fc2: 2006 movs r0, #6 +10000fc4: f000 f8d0 bl 10001168 +10000fc8: 00c2 lsls r2, r0, #3 +10000fca: fbb2 f2f6 udiv r2, r2, r6 +10000fce: 3201 adds r2, #1 +10000fd0: 09d1 lsrs r1, r2, #7 +10000fd2: d123 bne.n 1000101c +10000fd4: 2640 movs r6, #64 @ 0x40 +10000fd6: 2301 movs r3, #1 +10000fd8: 6263 str r3, [r4, #36] @ 0x24 +10000fda: 62a1 str r1, [r4, #40] @ 0x28 +10000fdc: 6b25 ldr r5, [r4, #48] @ 0x30 +10000fde: 07eb lsls r3, r5, #31 +10000fe0: d425 bmi.n 1000102e +10000fe2: 4623 mov r3, r4 +10000fe4: 2100 movs r1, #0 +10000fe6: f853 2f2c ldr.w r2, [r3, #44]! +10000fea: 2006 movs r0, #6 +10000fec: f503 5280 add.w r2, r3, #4096 @ 0x1000 +10000ff0: 6011 str r1, [r2, #0] +10000ff2: 6325 str r5, [r4, #48] @ 0x30 +10000ff4: 9201 str r2, [sp, #4] +10000ff6: f000 f8b7 bl 10001168 +10000ffa: f240 3501 movw r5, #769 @ 0x301 +10000ffe: 2103 movs r1, #3 +10001000: 0080 lsls r0, r0, #2 +10001002: fbb0 f0f6 udiv r0, r0, r6 +10001006: 6ae3 ldr r3, [r4, #44] @ 0x2c +10001008: 9a01 ldr r2, [sp, #4] +1000100a: f083 0370 eor.w r3, r3, #112 @ 0x70 +1000100e: f003 037e and.w r3, r3, #126 @ 0x7e +10001012: 6013 str r3, [r2, #0] +10001014: 6325 str r5, [r4, #48] @ 0x30 +10001016: 64a1 str r1, [r4, #72] @ 0x48 +10001018: b002 add sp, #8 +1000101a: bd70 pop {r4, r5, r6, pc} +1000101c: f64f 70fe movw r0, #65534 @ 0xfffe +10001020: 4281 cmp r1, r0 +10001022: d91d bls.n 10001060 +10001024: 4629 mov r1, r5 +10001026: f64f 73ff movw r3, #65535 @ 0xffff +1000102a: 4e16 ldr r6, [pc, #88] @ (10001084 ) +1000102c: e7d4 b.n 10000fd8 +1000102e: f240 3201 movw r2, #769 @ 0x301 +10001032: f504 5340 add.w r3, r4, #12288 @ 0x3000 +10001036: 631a str r2, [r3, #48] @ 0x30 +10001038: 6a63 ldr r3, [r4, #36] @ 0x24 +1000103a: 6aa2 ldr r2, [r4, #40] @ 0x28 +1000103c: 2006 movs r0, #6 +1000103e: eb02 1283 add.w r2, r2, r3, lsl #6 +10001042: 9201 str r2, [sp, #4] +10001044: f000 f890 bl 10001168 +10001048: 4b0f ldr r3, [pc, #60] @ (10001088 ) +1000104a: 9a01 ldr r2, [sp, #4] +1000104c: fba3 1300 umull r1, r3, r3, r0 +10001050: 0290 lsls r0, r2, #10 +10001052: 0adb lsrs r3, r3, #11 +10001054: fbb0 f0f3 udiv r0, r0, r3 +10001058: 2100 movs r1, #0 +1000105a: f7ff ff4d bl 10000ef8 +1000105e: e7c0 b.n 10000fe2 +10001060: f3c2 0245 ubfx r2, r2, #1, #6 +10001064: 460b mov r3, r1 +10001066: eb02 1681 add.w r6, r2, r1, lsl #6 +1000106a: 4611 mov r1, r2 +1000106c: e7b4 b.n 10000fd8 +1000106e: bf00 nop +10001070: 40078000 .word 0x40078000 +10001074: 40022000 .word 0x40022000 +10001078: 40023000 .word 0x40023000 +1000107c: 40020000 .word 0x40020000 +10001080: 20000868 .word 0x20000868 +10001084: 003fffc0 .word 0x003fffc0 +10001088: 8f2b7b75 .word 0x8f2b7b75 + +1000108c : +1000108c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001090: ea4f 0c8c mov.w ip, ip, lsl #2 +10001094: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001098: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +1000109c: b570 push {r4, r5, r6, lr} +1000109e: 461e mov r6, r3 +100010a0: f8dc 3004 ldr.w r3, [ip, #4] +100010a4: 1f04 subs r4, r0, #4 +100010a6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 +100010aa: bf38 it cc +100010ac: f44f 3380 movcc.w r3, #65536 @ 0x10000 +100010b0: b2e4 uxtb r4, r4 +100010b2: bf38 it cc +100010b4: f8cc 3004 strcc.w r3, [ip, #4] +100010b8: 2c01 cmp r4, #1 +100010ba: d92e bls.n 1000111a +100010bc: f44f 6500 mov.w r5, #2048 @ 0x800 +100010c0: 4b28 ldr r3, [pc, #160] @ (10001164 ) +100010c2: f50c 5e40 add.w lr, ip, #12288 @ 0x3000 +100010c6: f8ce 5000 str.w r5, [lr] +100010ca: f853 e020 ldr.w lr, [r3, r0, lsl #2] +100010ce: f1be 0f00 cmp.w lr, #0 +100010d2: d117 bne.n 10001104 +100010d4: f8dc e000 ldr.w lr, [ip] +100010d8: 2c01 cmp r4, #1 +100010da: ea8e 1242 eor.w r2, lr, r2, lsl #5 +100010de: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100010e2: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +100010e6: f8ce 2000 str.w r2, [lr] +100010ea: d92b bls.n 10001144 +100010ec: f44f 6100 mov.w r1, #2048 @ 0x800 +100010f0: f843 6020 str.w r6, [r3, r0, lsl #2] +100010f4: f44f 3380 mov.w r3, #65536 @ 0x10000 +100010f8: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100010fc: 6011 str r1, [r2, #0] +100010fe: f8cc 3004 str.w r3, [ip, #4] +10001102: bd70 pop {r4, r5, r6, pc} +10001104: 695d ldr r5, [r3, #20] +10001106: fbb5 fefe udiv lr, r5, lr +1000110a: f10e 0e01 add.w lr, lr, #1 +1000110e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10001112: f1be 0e03 subs.w lr, lr, #3 +10001116: d2fc bcs.n 10001112 +10001118: e7dc b.n 100010d4 +1000111a: 2901 cmp r1, #1 +1000111c: d1ce bne.n 100010bc +1000111e: 2403 movs r4, #3 +10001120: f50c 5340 add.w r3, ip, #12288 @ 0x3000 +10001124: 601c str r4, [r3, #0] +10001126: f8dc 3008 ldr.w r3, [ip, #8] +1000112a: 07db lsls r3, r3, #31 +1000112c: d5fb bpl.n 10001126 +1000112e: f8dc 3000 ldr.w r3, [ip] +10001132: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +10001136: ea83 1342 eor.w r3, r3, r2, lsl #5 +1000113a: f003 03e0 and.w r3, r3, #224 @ 0xe0 +1000113e: f8ce 3000 str.w r3, [lr] +10001142: 4b08 ldr r3, [pc, #32] @ (10001164 ) +10001144: 2201 movs r2, #1 +10001146: f8dc 4000 ldr.w r4, [ip] +1000114a: 404c eors r4, r1 +1000114c: f004 0403 and.w r4, r4, #3 +10001150: f8ce 4000 str.w r4, [lr] +10001154: fa02 f101 lsl.w r1, r2, r1 +10001158: f8dc 2008 ldr.w r2, [ip, #8] +1000115c: 420a tst r2, r1 +1000115e: d0fb beq.n 10001158 +10001160: e7c4 b.n 100010ec +10001162: bf00 nop +10001164: 2000080c .word 0x2000080c + +10001168 : +10001168: 4b01 ldr r3, [pc, #4] @ (10001170 ) +1000116a: f853 0020 ldr.w r0, [r3, r0, lsl #2] +1000116e: 4770 bx lr +10001170: 2000080c .word 0x2000080c + +10001174 : +10001174: b510 push {r4, lr} +10001176: 9c02 ldr r4, [sp, #8] +10001178: 468e mov lr, r1 +1000117a: ea4f 3c04 mov.w ip, r4, lsl #12 +1000117e: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +10001182: 4b1c ldr r3, [pc, #112] @ (100011f4 ) +10001184: fbb3 f3f1 udiv r3, r3, r1 +10001188: 6801 ldr r1, [r0, #0] +1000118a: fbb2 f4f3 udiv r4, r2, r3 +1000118e: 2900 cmp r1, #0 +10001190: db20 blt.n 100011d4 +10001192: 4a19 ldr r2, [pc, #100] @ (100011f8 ) +10001194: 4b19 ldr r3, [pc, #100] @ (100011fc ) +10001196: 4290 cmp r0, r2 +10001198: bf14 ite ne +1000119a: f44f 4280 movne.w r2, #16384 @ 0x4000 +1000119e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +100011a2: 4917 ldr r1, [pc, #92] @ (10001200 ) +100011a4: 601a str r2, [r3, #0] +100011a6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100011aa: 601a str r2, [r3, #0] +100011ac: 688b ldr r3, [r1, #8] +100011ae: ea32 0303 bics.w r3, r2, r3 +100011b2: d1fb bne.n 100011ac +100011b4: 2221 movs r2, #33 @ 0x21 +100011b6: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100011ba: 3304 adds r3, #4 +100011bc: f8c0 e000 str.w lr, [r0] +100011c0: 6084 str r4, [r0, #8] +100011c2: 601a str r2, [r3, #0] +100011c4: 6802 ldr r2, [r0, #0] +100011c6: 2a00 cmp r2, #0 +100011c8: dafc bge.n 100011c4 +100011ca: 2208 movs r2, #8 +100011cc: f8c0 c00c str.w ip, [r0, #12] +100011d0: 601a str r2, [r3, #0] +100011d2: bd10 pop {r4, pc} +100011d4: 6803 ldr r3, [r0, #0] +100011d6: f003 033f and.w r3, r3, #63 @ 0x3f +100011da: 4573 cmp r3, lr +100011dc: d1d9 bne.n 10001192 +100011de: 6883 ldr r3, [r0, #8] +100011e0: f3c3 030b ubfx r3, r3, #0, #12 +100011e4: 42a3 cmp r3, r4 +100011e6: d1d4 bne.n 10001192 +100011e8: 68c3 ldr r3, [r0, #12] +100011ea: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100011ee: 4563 cmp r3, ip +100011f0: d1cf bne.n 10001192 +100011f2: bd10 pop {r4, pc} +100011f4: 00b71b00 .word 0x00b71b00 +100011f8: 40058000 .word 0x40058000 +100011fc: 40022000 .word 0x40022000 +10001200: 40020000 .word 0x40020000 + +10001204 : +10001204: 2301 movs r3, #1 +10001206: eb00 0040 add.w r0, r0, r0, lsl #1 +1000120a: 0080 lsls r0, r0, #2 +1000120c: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001210: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001214: 6041 str r1, [r0, #4] +10001216: 6003 str r3, [r0, #0] +10001218: 4770 bx lr +1000121a: bf00 nop + +1000121c : +1000121c: 2300 movs r3, #0 +1000121e: 8adb ldrh r3, [r3, #22] +10001220: 2200 movs r2, #0 +10001222: e842 f200 tt r2, r2 +10001226: 0252 lsls r2, r2, #9 +10001228: d401 bmi.n 1000122e +1000122a: 2110 movs r1, #16 +1000122c: 4718 bx r3 +1000122e: 2104 movs r1, #4 +10001230: 4718 bx r3 +10001232: bf00 nop + +10001234 : +10001234: 4a03 ldr r2, [pc, #12] @ (10001244 ) +10001236: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +1000123a: 2b00 cmp r3, #0 +1000123c: d0fb beq.n 10001236 +1000123e: f3bf 8f5f dmb sy +10001242: 4770 bx lr +10001244: 400e0000 .word 0x400e0000 + +10001248 : +10001248: 2100 movs r1, #0 +1000124a: 4b04 ldr r3, [pc, #16] @ (1000125c ) +1000124c: 4a04 ldr r2, [pc, #16] @ (10001260 ) +1000124e: f3bf 8f5f dmb sy +10001252: f843 1b04 str.w r1, [r3], #4 +10001256: 4293 cmp r3, r2 +10001258: d1f9 bne.n 1000124e +1000125a: 4770 bx lr +1000125c: 400e080c .word 0x400e080c +10001260: 400e082c .word 0x400e082c + +10001264 : +10001264: f44f 6c2a mov.w ip, #2720 @ 0xaa0 +10001268: f44f 708d mov.w r0, #282 @ 0x11a +1000126c: 4a05 ldr r2, [pc, #20] @ (10001284 ) +1000126e: 4b06 ldr r3, [pc, #24] @ (10001288 ) +10001270: 4906 ldr r1, [pc, #24] @ (1000128c ) +10001272: f8c2 c000 str.w ip, [r2] +10001276: 60d0 str r0, [r2, #12] +10001278: 6019 str r1, [r3, #0] +1000127a: 6853 ldr r3, [r2, #4] +1000127c: 2b00 cmp r3, #0 +1000127e: dafc bge.n 1000127a +10001280: 4770 bx lr +10001282: bf00 nop +10001284: 40048000 .word 0x40048000 +10001288: 4004a000 .word 0x4004a000 +1000128c: 00fab000 .word 0x00fab000 + +10001290 : +10001290: 4770 bx lr +10001292: bf00 nop + +10001294 : +10001294: b508 push {r3, lr} +10001296: 4801 ldr r0, [pc, #4] @ (1000129c ) +10001298: f7ff f83e bl 10000318 +1000129c: 10003768 .word 0x10003768 + +100012a0 : +100012a0: b538 push {r3, r4, r5, lr} +100012a2: 4c05 ldr r4, [pc, #20] @ (100012b8 ) +100012a4: 4d05 ldr r5, [pc, #20] @ (100012bc ) +100012a6: 42ac cmp r4, r5 +100012a8: d204 bcs.n 100012b4 +100012aa: f854 3b04 ldr.w r3, [r4], #4 +100012ae: 4798 blx r3 +100012b0: 42ac cmp r4, r5 +100012b2: d3fa bcc.n 100012aa +100012b4: bd38 pop {r3, r4, r5, pc} +100012b6: bf00 nop +100012b8: 100035d8 .word 0x100035d8 +100012bc: 10003618 .word 0x10003618 + +100012c0 : +100012c0: 4806 ldr r0, [pc, #24] @ (100012dc ) +100012c2: f8df c028 ldr.w ip, [pc, #40] @ 100012ec +100012c6: 4b06 ldr r3, [pc, #24] @ (100012e0 ) +100012c8: 4a06 ldr r2, [pc, #24] @ (100012e4 ) +100012ca: 4907 ldr r1, [pc, #28] @ (100012e8 ) +100012cc: f8c0 c000 str.w ip, [r0] +100012d0: 601a str r2, [r3, #0] +100012d2: 688b ldr r3, [r1, #8] +100012d4: ea32 0303 bics.w r3, r2, r3 +100012d8: d1fb bne.n 100012d2 +100012da: 4770 bx lr +100012dc: 40022000 .word 0x40022000 +100012e0: 40023000 .word 0x40023000 +100012e4: 03f3fff6 .word 0x03f3fff6 +100012e8: 40020000 .word 0x40020000 +100012ec: efef3b7f .word 0xefef3b7f + +100012f0 : +100012f0: 4b04 ldr r3, [pc, #16] @ (10001304 ) +100012f2: 6cdb ldr r3, [r3, #76] @ 0x4c +100012f4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100012f8: d103 bne.n 10001302 +100012fa: f44f 2280 mov.w r2, #262144 @ 0x40000 +100012fe: 4b02 ldr r3, [pc, #8] @ (10001308 ) +10001300: 64da str r2, [r3, #76] @ 0x4c +10001302: 4770 bx lr +10001304: 50110000 .word 0x50110000 +10001308: 50112000 .word 0x50112000 + +1000130c : +1000130c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001310: 4b04 ldr r3, [pc, #16] @ (10001324 ) +10001312: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001316: 430b orrs r3, r1 +10001318: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000131c: ee10 0430 dcp_rcmp r0 +10001320: 4770 bx lr +10001322: bf00 nop +10001324: 00300303 .word 0x00300303 + +10001328 : +10001328: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +1000132c: 4b04 ldr r3, [pc, #16] @ (10001340 ) +1000132e: 4a05 ldr r2, [pc, #20] @ (10001344 ) +10001330: 6019 str r1, [r3, #0] +10001332: 6893 ldr r3, [r2, #8] +10001334: 43db mvns r3, r3 +10001336: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +1000133a: d1fa bne.n 10001332 +1000133c: 4770 bx lr +1000133e: bf00 nop +10001340: 40023000 .word 0x40023000 +10001344: 40020000 .word 0x40020000 + +10001348 : +10001348: b510 push {r4, lr} +1000134a: f245 2053 movw r0, #21075 @ 0x5253 +1000134e: f7ff ff65 bl 1000121c +10001352: e8bd 4010 ldmia.w sp!, {r4, lr} +10001356: 4603 mov r3, r0 +10001358: 2004 movs r0, #4 +1000135a: 4718 bx r3 + +1000135c : +1000135c: b510 push {r4, lr} +1000135e: f245 2053 movw r0, #21075 @ 0x5253 +10001362: f7ff ff5b bl 1000121c +10001366: e8bd 4010 ldmia.w sp!, {r4, lr} +1000136a: 4603 mov r3, r0 +1000136c: 2001 movs r0, #1 +1000136e: 4718 bx r3 + +10001370 : +10001370: f7ff b82a b.w 100003c8 + +10001374 : +10001374: 4913 ldr r1, [pc, #76] @ (100013c4 ) +10001376: 4b14 ldr r3, [pc, #80] @ (100013c8 ) +10001378: b570 push {r4, r5, r6, lr} +1000137a: 1a5c subs r4, r3, r1 +1000137c: 08a5 lsrs r5, r4, #2 +1000137e: 2d44 cmp r5, #68 @ 0x44 +10001380: 462a mov r2, r5 +10001382: bf28 it cs +10001384: 2244 movcs r2, #68 @ 0x44 +10001386: 4e11 ldr r6, [pc, #68] @ (100013cc ) +10001388: 0092 lsls r2, r2, #2 +1000138a: 4630 mov r0, r6 +1000138c: f002 f874 bl 10003478 +10001390: 2d43 cmp r5, #67 @ 0x43 +10001392: d813 bhi.n 100013bc +10001394: 4a0e ldr r2, [pc, #56] @ (100013d0 ) +10001396: d00f beq.n 100013b8 +10001398: f1c5 0044 rsb r0, r5, #68 @ 0x44 +1000139c: 1933 adds r3, r6, r4 +1000139e: 0841 lsrs r1, r0, #1 +100013a0: eb03 01c1 add.w r1, r3, r1, lsl #3 +100013a4: e9c3 2200 strd r2, r2, [r3] +100013a8: 3308 adds r3, #8 +100013aa: 428b cmp r3, r1 +100013ac: d1fa bne.n 100013a4 +100013ae: 07c3 lsls r3, r0, #31 +100013b0: d504 bpl.n 100013bc +100013b2: f020 0001 bic.w r0, r0, #1 +100013b6: 4405 add r5, r0 +100013b8: f846 2025 str.w r2, [r6, r5, lsl #2] +100013bc: 4b05 ldr r3, [pc, #20] @ (100013d4 ) +100013be: 609e str r6, [r3, #8] +100013c0: bd70 pop {r4, r5, r6, pc} +100013c2: bf00 nop +100013c4: 10000000 .word 0x10000000 +100013c8: 10000110 .word 0x10000110 +100013cc: 20000000 .word 0x20000000 +100013d0: 10000111 .word 0x10000111 +100013d4: e000ed00 .word 0xe000ed00 + +100013d8 : +100013d8: 2300 movs r3, #0 +100013da: b570 push {r4, r5, r6, lr} +100013dc: 4c2b ldr r4, [pc, #172] @ (1000148c ) +100013de: b082 sub sp, #8 +100013e0: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100013e4: f7ff ff3e bl 10001264 +100013e8: 2201 movs r2, #1 +100013ea: 4b29 ldr r3, [pc, #164] @ (10001490 ) +100013ec: 63da str r2, [r3, #60] @ 0x3c +100013ee: 6c63 ldr r3, [r4, #68] @ 0x44 +100013f0: 2b01 cmp r3, #1 +100013f2: d1fc bne.n 100013ee +100013f4: 2103 movs r1, #3 +100013f6: 4a26 ldr r2, [pc, #152] @ (10001490 ) +100013f8: 4b24 ldr r3, [pc, #144] @ (1000148c ) +100013fa: 6311 str r1, [r2, #48] @ 0x30 +100013fc: 6b9c ldr r4, [r3, #56] @ 0x38 +100013fe: 2c01 cmp r4, #1 +10001400: d1fc bne.n 100013fc +10001402: 2602 movs r6, #2 +10001404: 2505 movs r5, #5 +10001406: 4621 mov r1, r4 +10001408: 2305 movs r3, #5 +1000140a: 4a22 ldr r2, [pc, #136] @ (10001494 ) +1000140c: 4822 ldr r0, [pc, #136] @ (10001498 ) +1000140e: 9600 str r6, [sp, #0] +10001410: f7ff feb0 bl 10001174 +10001414: 4621 mov r1, r4 +10001416: 462b mov r3, r5 +10001418: 4a20 ldr r2, [pc, #128] @ (1000149c ) +1000141a: 4821 ldr r0, [pc, #132] @ (100014a0 ) +1000141c: 9500 str r5, [sp, #0] +1000141e: f7ff fea9 bl 10001174 +10001422: 2200 movs r2, #0 +10001424: 2004 movs r0, #4 +10001426: 4631 mov r1, r6 +10001428: 4b1e ldr r3, [pc, #120] @ (100014a4 ) +1000142a: f7ff fe2f bl 1000108c +1000142e: 4621 mov r1, r4 +10001430: 4628 mov r0, r5 +10001432: 2200 movs r2, #0 +10001434: 4b1c ldr r3, [pc, #112] @ (100014a8 ) +10001436: f7ff fe29 bl 1000108c +1000143a: 2200 movs r2, #0 +1000143c: 2008 movs r0, #8 +1000143e: 4611 mov r1, r2 +10001440: 4b1a ldr r3, [pc, #104] @ (100014ac ) +10001442: f7ff fe23 bl 1000108c +10001446: 2200 movs r2, #0 +10001448: 2009 movs r0, #9 +1000144a: 4611 mov r1, r2 +1000144c: 4b17 ldr r3, [pc, #92] @ (100014ac ) +1000144e: f7ff fe1d bl 1000108c +10001452: 2200 movs r2, #0 +10001454: 2006 movs r0, #6 +10001456: 4611 mov r1, r2 +10001458: 4b13 ldr r3, [pc, #76] @ (100014a8 ) +1000145a: f7ff fe17 bl 1000108c +1000145e: 2200 movs r2, #0 +10001460: 4b11 ldr r3, [pc, #68] @ (100014a8 ) +10001462: 2007 movs r0, #7 +10001464: 4611 mov r1, r2 +10001466: f7ff fe11 bl 1000108c +1000146a: 2004 movs r0, #4 +1000146c: f7ff fe7c bl 10001168 +10001470: 2400 movs r4, #0 +10001472: 4b0f ldr r3, [pc, #60] @ (100014b0 ) +10001474: fba3 3500 umull r3, r5, r3, r0 +10001478: 0cad lsrs r5, r5, #18 +1000147a: b2e0 uxtb r0, r4 +1000147c: 4629 mov r1, r5 +1000147e: 3401 adds r4, #1 +10001480: f7ff fec0 bl 10001204 +10001484: 2c06 cmp r4, #6 +10001486: d1f8 bne.n 1000147a +10001488: b002 add sp, #8 +1000148a: bd70 pop {r4, r5, r6, pc} +1000148c: 40010000 .word 0x40010000 +10001490: 40013000 .word 0x40013000 +10001494: 59682f00 .word 0x59682f00 +10001498: 40050000 .word 0x40050000 +1000149c: 47868c00 .word 0x47868c00 +100014a0: 40058000 .word 0x40058000 +100014a4: 00b71b00 .word 0x00b71b00 +100014a8: 08f0d180 .word 0x08f0d180 +100014ac: 02dc6c00 .word 0x02dc6c00 +100014b0: 431bde83 .word 0x431bde83 + +100014b4 : +100014b4: b086 sub sp, #24 +100014b6: b403 push {r0, r1} +100014b8: fc51 0408 dcp_pxmd r0, r1 +100014bc: e9cd 0102 strd r0, r1, [sp, #8] +100014c0: fc51 0409 dcp_pymd r0, r1 +100014c4: e9cd 0104 strd r0, r1, [sp, #16] +100014c8: ec51 040a dcp_refd r0, r1 +100014cc: e9cd 0106 strd r0, r1, [sp, #24] +100014d0: bc03 pop {r0, r1} +100014d2: 47f0 blx lr + +100014d4 : +100014d4: e8bd 5000 ldmia.w sp!, {ip, lr} +100014d8: ec4e c400 dcp_wxmd ip, lr +100014dc: e8bd 5000 ldmia.w sp!, {ip, lr} +100014e0: ec4e c401 dcp_wymd ip, lr +100014e4: e8bd 5000 ldmia.w sp!, {ip, lr} +100014e8: ec4e c402 dcp_wefd ip, lr +100014ec: bd00 pop {pc} +100014ee: 0000 movs r0, r0 +100014f0: b500 push {lr} +100014f2: f7ff ffdf bl 100014b4 +100014f6: e002 b.n 100014fe <__wrap___aeabi_dadd+0x6> + +100014f8 <__wrap___aeabi_dadd>: +100014f8: fe10 f430 dcp_pcmp APSR_nzcv +100014fc: d4f8 bmi.n 100014f0 +100014fe: ec41 0410 dcp_wxup r0, r1 +10001502: ec43 2411 dcp_wyup r2, r3 +10001506: ee00 0401 dcp_add0 +1000150a: ee10 0401 dcp_add1 +1000150e: ee80 0420 dcp_nrdd +10001512: ec51 0410 dcp_rdda r0, r1 +10001516: 4770 bx lr +10001518: b500 push {lr} +1000151a: f7ff ffcb bl 100014b4 +1000151e: e002 b.n 10001526 <__wrap___aeabi_dsub+0x6> + +10001520 <__wrap___aeabi_dsub>: +10001520: fe10 f430 dcp_pcmp APSR_nzcv +10001524: d4f8 bmi.n 10001518 <__wrap___aeabi_dadd+0x20> +10001526: ec41 0410 dcp_wxup r0, r1 +1000152a: ec43 2411 dcp_wyup r2, r3 +1000152e: ee00 0401 dcp_add0 +10001532: ee10 0421 dcp_sub1 +10001536: ee80 0420 dcp_nrdd +1000153a: ec51 0430 dcp_rdds r0, r1 +1000153e: 4770 bx lr +10001540: b500 push {lr} +10001542: f7ff ffb7 bl 100014b4 +10001546: e002 b.n 1000154e <__wrap___aeabi_dmul+0x6> + +10001548 <__wrap___aeabi_dmul>: +10001548: fe10 f430 dcp_pcmp APSR_nzcv +1000154c: d4f8 bmi.n 10001540 <__wrap___aeabi_dsub+0x20> +1000154e: b510 push {r4, lr} +10001550: ec41 0410 dcp_wxup r0, r1 +10001554: ec43 2411 dcp_wyup r2, r3 +10001558: ec51 0404 dcp_rxms r0, r1, #0x0 +1000155c: ec53 2405 dcp_ryms r2, r3, #0x0 +10001560: fba0 4c02 umull r4, ip, r0, r2 +10001564: f05f 0e00 movs.w lr, #0 +10001568: fbe0 ce03 umlal ip, lr, r0, r3 +1000156c: fbe1 ce02 umlal ip, lr, r1, r2 +10001570: ec4c 4420 dcp_wxms r4, ip +10001574: 2400 movs r4, #0 +10001576: fbe1 e403 umlal lr, r4, r1, r3 +1000157a: ec44 e430 dcp_wxmo lr, r4 +1000157e: ee80 0420 dcp_nrdd +10001582: ec51 0450 dcp_rddm r0, r1 +10001586: bd10 pop {r4, pc} +10001588: b500 push {lr} +1000158a: f7ff ff93 bl 100014b4 +1000158e: e002 b.n 10001596 <__wrap___aeabi_ddiv+0x6> + +10001590 <__wrap___aeabi_ddiv>: +10001590: fe10 f430 dcp_pcmp APSR_nzcv +10001594: d4f8 bmi.n 10001588 <__wrap___aeabi_dmul+0x40> +10001596: ec41 0410 dcp_wxup r0, r1 +1000159a: ec43 2411 dcp_wyup r2, r3 +1000159e: ec51 0421 dcp_rymr r0, r1 +100015a2: fba0 1201 umull r1, r2, r0, r1 +100015a6: ea6f 0282 mvn.w r2, r2, lsl #2 +100015aa: fb52 0010 smmlar r0, r2, r0, r0 +100015ae: fb52 f212 smmulr r2, r2, r2 +100015b2: fb52 0010 smmlar r0, r2, r0, r0 +100015b6: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +100015ba: ec53 2404 dcp_rxms r2, r3, #0x0 +100015be: fb5c f113 smmulr r1, ip, r3 +100015c2: ec53 2415 dcp_ryms r2, r3, #0x1 +100015c6: fba1 2002 umull r2, r0, r1, r2 +100015ca: fb01 0003 mla r0, r1, r3, r0 +100015ce: ec53 2444 dcp_rxms r2, r3, #0x4 +100015d2: eba2 0000 sub.w r0, r2, r0 +100015d6: fb50 f21c smmulr r2, r0, ip +100015da: ea4f 1311 mov.w r3, r1, lsr #4 +100015de: eb12 7001 adds.w r0, r2, r1, lsl #28 +100015e2: eb43 71e2 adc.w r1, r3, r2, asr #31 +100015e6: ea40 5051 orr.w r0, r0, r1, lsr #21 +100015ea: ea20 5091 bic.w r0, r0, r1, lsr #22 +100015ee: f020 0007 bic.w r0, r0, #7 +100015f2: ec53 2475 dcp_ryms r2, r3, #0x7 +100015f6: fba0 3c02 umull r3, ip, r0, r2 +100015fa: ec53 2475 dcp_ryms r2, r3, #0x7 +100015fe: fb00 cc03 mla ip, r0, r3, ip +10001602: fb01 cc02 mla ip, r1, r2, ip +10001606: ec53 2404 dcp_rxms r2, r3, #0x0 +1000160a: ebac 4c82 sub.w ip, ip, r2, lsl #18 +1000160e: ea40 705c orr.w r0, r0, ip, lsr #29 +10001612: f1a0 0001 sub.w r0, r0, #1 +10001616: ec41 0440 dcp_wxdd r0, r1 +1000161a: ee80 0420 dcp_nrdd +1000161e: ec51 0470 dcp_rddd r0, r1 +10001622: 4770 bx lr +10001624: b500 push {lr} +10001626: f7ff ff45 bl 100014b4 +1000162a: e002 b.n 10001632 <__wrap___aeabi_i2d+0x6> + +1000162c <__wrap___aeabi_i2d>: +1000162c: fe10 f430 dcp_pcmp APSR_nzcv +10001630: d4f8 bmi.n 10001624 <__wrap___aeabi_ddiv+0x94> +10001632: ec40 0470 dcp_wxic r0, r0 +10001636: ee00 0401 dcp_add0 +1000163a: ee10 0421 dcp_sub1 +1000163e: ee80 0420 dcp_nrdd +10001642: ec51 0430 dcp_rdds r0, r1 +10001646: 4770 bx lr +10001648: b500 push {lr} +1000164a: f7ff ff33 bl 100014b4 +1000164e: e002 b.n 10001656 <__wrap___aeabi_ui2d+0x6> + +10001650 <__wrap___aeabi_ui2d>: +10001650: fe10 f430 dcp_pcmp APSR_nzcv +10001654: d4f8 bmi.n 10001648 <__wrap___aeabi_i2d+0x1c> +10001656: ec40 0460 dcp_wxuc r0, r0 +1000165a: ee00 0401 dcp_add0 +1000165e: ee10 0421 dcp_sub1 +10001662: ee80 0420 dcp_nrdd +10001666: ec51 0430 dcp_rdds r0, r1 +1000166a: 4770 bx lr +1000166c: b500 push {lr} +1000166e: f7ff ff21 bl 100014b4 +10001672: e002 b.n 1000167a + +10001674 <__wrap___aeabi_d2iz>: +10001674: fe10 f430 dcp_pcmp APSR_nzcv +10001678: d4f8 bmi.n 1000166c <__wrap___aeabi_ui2d+0x1c> + +1000167a : +1000167a: ec41 0480 dcp_wxdc r0, r1 +1000167e: ee00 0401 dcp_add0 +10001682: ee10 0401 dcp_add1 +10001686: ee80 0440 dcp_ntdc +1000168a: ee10 0413 dcp_rdic r0 +1000168e: 4770 bx lr +10001690: b500 push {lr} +10001692: f7ff ff0f bl 100014b4 +10001696: e002 b.n 1000169e + +10001698 <__wrap___aeabi_d2uiz>: +10001698: fe10 f430 dcp_pcmp APSR_nzcv +1000169c: d4f8 bmi.n 10001690 + +1000169e : +1000169e: ec41 0480 dcp_wxdc r0, r1 +100016a2: ee00 0401 dcp_add0 +100016a6: ee10 0401 dcp_add1 +100016aa: ee80 0440 dcp_ntdc +100016ae: ee10 0433 dcp_rduc r0 +100016b2: 4770 bx lr +100016b4: b500 push {lr} +100016b6: f7ff fefd bl 100014b4 +100016ba: e002 b.n 100016c2 <__wrap___aeabi_dcmpun+0x6> + +100016bc <__wrap___aeabi_dcmpun>: +100016bc: fe10 f430 dcp_pcmp APSR_nzcv +100016c0: d4f8 bmi.n 100016b4 +100016c2: ec41 0410 dcp_wxup r0, r1 +100016c6: ec43 2411 dcp_wyup r2, r3 +100016ca: ee00 0401 dcp_add0 +100016ce: ee10 0430 dcp_rcmp r0 +100016d2: f3c0 7000 ubfx r0, r0, #28, #1 +100016d6: 4770 bx lr +100016d8: b500 push {lr} +100016da: f7ff feeb bl 100014b4 +100016de: e002 b.n 100016e6 <__wrap___aeabi_dcmplt+0x6> + +100016e0 <__wrap___aeabi_dcmplt>: +100016e0: fe10 f430 dcp_pcmp APSR_nzcv +100016e4: d4f8 bmi.n 100016d8 <__wrap___aeabi_dcmpun+0x1c> +100016e6: ec43 2410 dcp_wxup r2, r3 +100016ea: ec41 0411 dcp_wyup r0, r1 +100016ee: ee00 0401 dcp_add0 +100016f2: ee10 f430 dcp_rcmp APSR_nzcv +100016f6: bf8c ite hi +100016f8: 2001 movhi r0, #1 +100016fa: 2000 movls r0, #0 +100016fc: 4770 bx lr +100016fe: bf00 nop +10001700: b500 push {lr} +10001702: f7ff fed7 bl 100014b4 +10001706: e002 b.n 1000170e <__wrap___aeabi_dcmple+0x6> + +10001708 <__wrap___aeabi_dcmple>: +10001708: fe10 f430 dcp_pcmp APSR_nzcv +1000170c: d4f8 bmi.n 10001700 <__wrap___aeabi_dcmplt+0x20> +1000170e: ec43 2410 dcp_wxup r2, r3 +10001712: ec41 0411 dcp_wyup r0, r1 +10001716: ee00 0401 dcp_add0 +1000171a: ee10 f430 dcp_rcmp APSR_nzcv +1000171e: bf2c ite cs +10001720: 2001 movcs r0, #1 +10001722: 2000 movcc r0, #0 +10001724: 4770 bx lr +10001726: bf00 nop +10001728: b500 push {lr} +1000172a: f7ff fec3 bl 100014b4 +1000172e: e002 b.n 10001736 <__wrap___aeabi_dcmpge+0x6> + +10001730 <__wrap___aeabi_dcmpge>: +10001730: fe10 f430 dcp_pcmp APSR_nzcv +10001734: d4f8 bmi.n 10001728 <__wrap___aeabi_dcmple+0x20> +10001736: ec41 0410 dcp_wxup r0, r1 +1000173a: ec43 2411 dcp_wyup r2, r3 +1000173e: ee00 0401 dcp_add0 +10001742: ee10 f430 dcp_rcmp APSR_nzcv +10001746: bf2c ite cs +10001748: 2001 movcs r0, #1 +1000174a: 2000 movcc r0, #0 +1000174c: 4770 bx lr +1000174e: bf00 nop +10001750: b500 push {lr} +10001752: f7ff feaf bl 100014b4 +10001756: e002 b.n 1000175e <__wrap___aeabi_dcmpgt+0x6> + +10001758 <__wrap___aeabi_dcmpgt>: +10001758: fe10 f430 dcp_pcmp APSR_nzcv +1000175c: d4f8 bmi.n 10001750 <__wrap___aeabi_dcmpge+0x20> +1000175e: ec41 0410 dcp_wxup r0, r1 +10001762: ec43 2411 dcp_wyup r2, r3 +10001766: ee00 0401 dcp_add0 +1000176a: ee10 f430 dcp_rcmp APSR_nzcv +1000176e: bf8c ite hi +10001770: 2001 movhi r0, #1 +10001772: 2000 movls r0, #0 +10001774: 4770 bx lr +10001776: bf00 nop + +10001778 <_out_null>: +10001778: 4770 bx lr +1000177a: bf00 nop + +1000177c <_out_rev>: +1000177c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001780: b083 sub sp, #12 +10001782: 460f mov r7, r1 +10001784: 4611 mov r1, r2 +10001786: e9dd b20e ldrd fp, r2, [sp, #56] @ 0x38 +1000178a: 0792 lsls r2, r2, #30 +1000178c: 4698 mov r8, r3 +1000178e: e9dd 930c ldrd r9, r3, [sp, #48] @ 0x30 +10001792: 4606 mov r6, r0 +10001794: d029 beq.n 100017ea <_out_rev+0x6e> +10001796: 460d mov r5, r1 +10001798: b19b cbz r3, 100017c2 <_out_rev+0x46> +1000179a: eb09 0403 add.w r4, r9, r3 +1000179e: eb05 0a04 add.w sl, r5, r4 +100017a2: 9501 str r5, [sp, #4] +100017a4: 460d mov r5, r1 +100017a6: 930d str r3, [sp, #52] @ 0x34 +100017a8: ebaa 0204 sub.w r2, sl, r4 +100017ac: f814 0d01 ldrb.w r0, [r4, #-1]! +100017b0: 4643 mov r3, r8 +100017b2: 4639 mov r1, r7 +100017b4: 47b0 blx r6 +100017b6: 45a1 cmp r9, r4 +100017b8: d1f6 bne.n 100017a8 <_out_rev+0x2c> +100017ba: 4629 mov r1, r5 +100017bc: 9b0d ldr r3, [sp, #52] @ 0x34 +100017be: 9d01 ldr r5, [sp, #4] +100017c0: 441d add r5, r3 +100017c2: 9b0f ldr r3, [sp, #60] @ 0x3c +100017c4: 079b lsls r3, r3, #30 +100017c6: d50c bpl.n 100017e2 <_out_rev+0x66> +100017c8: 1a6c subs r4, r5, r1 +100017ca: 45a3 cmp fp, r4 +100017cc: d909 bls.n 100017e2 <_out_rev+0x66> +100017ce: 462a mov r2, r5 +100017d0: 4643 mov r3, r8 +100017d2: 4639 mov r1, r7 +100017d4: 2020 movs r0, #32 +100017d6: 3401 adds r4, #1 +100017d8: 47b0 blx r6 +100017da: 455c cmp r4, fp +100017dc: f105 0501 add.w r5, r5, #1 +100017e0: d3f5 bcc.n 100017ce <_out_rev+0x52> +100017e2: 4628 mov r0, r5 +100017e4: b003 add sp, #12 +100017e6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100017ea: 455b cmp r3, fp +100017ec: d215 bcs.n 1000181a <_out_rev+0x9e> +100017ee: 468a mov sl, r1 +100017f0: 461c mov r4, r3 +100017f2: 4689 mov r9, r1 +100017f4: ebab 0503 sub.w r5, fp, r3 +100017f8: 440d add r5, r1 +100017fa: 4652 mov r2, sl +100017fc: 4643 mov r3, r8 +100017fe: 4639 mov r1, r7 +10001800: 2020 movs r0, #32 +10001802: f10a 0a01 add.w sl, sl, #1 +10001806: 47b0 blx r6 +10001808: 45aa cmp sl, r5 +1000180a: d1f6 bne.n 100017fa <_out_rev+0x7e> +1000180c: 4649 mov r1, r9 +1000180e: 4623 mov r3, r4 +10001810: f8dd 9030 ldr.w r9, [sp, #48] @ 0x30 +10001814: 2c00 cmp r4, #0 +10001816: d1c0 bne.n 1000179a <_out_rev+0x1e> +10001818: e7e3 b.n 100017e2 <_out_rev+0x66> +1000181a: 460d mov r5, r1 +1000181c: 2b00 cmp r3, #0 +1000181e: d1bc bne.n 1000179a <_out_rev+0x1e> +10001820: e7df b.n 100017e2 <_out_rev+0x66> +10001822: bf00 nop + +10001824 <_ntoa_format>: +10001824: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001828: 460f mov r7, r1 +1000182a: 990f ldr r1, [sp, #60] @ 0x3c +1000182c: 4606 mov r6, r0 +1000182e: f89d 002c ldrb.w r0, [sp, #44] @ 0x2c +10001832: 078d lsls r5, r1, #30 +10001834: 4690 mov r8, r2 +10001836: e9dd a20c ldrd sl, r2, [sp, #48] @ 0x30 +1000183a: 4699 mov r9, r3 +1000183c: 4683 mov fp, r0 +1000183e: 9c09 ldr r4, [sp, #36] @ 0x24 +10001840: f8dd c028 ldr.w ip, [sp, #40] @ 0x28 +10001844: 9b0e ldr r3, [sp, #56] @ 0x38 +10001846: d449 bmi.n 100018dc <_ntoa_format+0xb8> +10001848: 2b00 cmp r3, #0 +1000184a: d142 bne.n 100018d2 <_ntoa_format+0xae> +1000184c: 4594 cmp ip, r2 +1000184e: d245 bcs.n 100018dc <_ntoa_format+0xb8> +10001850: f001 0501 and.w r5, r1, #1 +10001854: f104 3eff add.w lr, r4, #4294967295 @ 0xffffffff +10001858: 2030 movs r0, #48 @ 0x30 +1000185a: 44e6 add lr, ip +1000185c: e005 b.n 1000186a <_ntoa_format+0x46> +1000185e: f10c 0c01 add.w ip, ip, #1 +10001862: 4562 cmp r2, ip +10001864: f80e 0f01 strb.w r0, [lr, #1]! +10001868: d902 bls.n 10001870 <_ntoa_format+0x4c> +1000186a: f1bc 0f20 cmp.w ip, #32 +1000186e: d1f6 bne.n 1000185e <_ntoa_format+0x3a> +10001870: 2d00 cmp r5, #0 +10001872: f000 8087 beq.w 10001984 <_ntoa_format+0x160> +10001876: 4563 cmp r3, ip +10001878: d930 bls.n 100018dc <_ntoa_format+0xb8> +1000187a: 1e60 subs r0, r4, #1 +1000187c: f04f 0e30 mov.w lr, #48 @ 0x30 +10001880: 4460 add r0, ip +10001882: e005 b.n 10001890 <_ntoa_format+0x6c> +10001884: f10c 0c01 add.w ip, ip, #1 +10001888: 459c cmp ip, r3 +1000188a: f800 ef01 strb.w lr, [r0, #1]! +1000188e: d025 beq.n 100018dc <_ntoa_format+0xb8> +10001890: f1bc 0f20 cmp.w ip, #32 +10001894: d1f6 bne.n 10001884 <_ntoa_format+0x60> +10001896: 06cd lsls r5, r1, #27 +10001898: d50e bpl.n 100018b8 <_ntoa_format+0x94> +1000189a: 0548 lsls r0, r1, #21 +1000189c: d451 bmi.n 10001942 <_ntoa_format+0x11e> +1000189e: 4562 cmp r2, ip +100018a0: d064 beq.n 1000196c <_ntoa_format+0x148> +100018a2: 4563 cmp r3, ip +100018a4: d062 beq.n 1000196c <_ntoa_format+0x148> +100018a6: f1ba 0f10 cmp.w sl, #16 +100018aa: d04d beq.n 10001948 <_ntoa_format+0x124> +100018ac: f1ba 0f02 cmp.w sl, #2 +100018b0: d055 beq.n 1000195e <_ntoa_format+0x13a> +100018b2: f1bc 0f20 cmp.w ip, #32 +100018b6: d12d bne.n 10001914 <_ntoa_format+0xf0> +100018b8: 2220 movs r2, #32 +100018ba: e9cd 310b strd r3, r1, [sp, #44] @ 0x2c +100018be: 920a str r2, [sp, #40] @ 0x28 +100018c0: 464b mov r3, r9 +100018c2: 4642 mov r2, r8 +100018c4: 4639 mov r1, r7 +100018c6: 4630 mov r0, r6 +100018c8: 9409 str r4, [sp, #36] @ 0x24 +100018ca: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100018ce: f7ff bf55 b.w 1000177c <_out_rev> +100018d2: f011 0501 ands.w r5, r1, #1 +100018d6: d12e bne.n 10001936 <_ntoa_format+0x112> +100018d8: 4594 cmp ip, r2 +100018da: d3bb bcc.n 10001854 <_ntoa_format+0x30> +100018dc: 06cd lsls r5, r1, #27 +100018de: d51e bpl.n 1000191e <_ntoa_format+0xfa> +100018e0: 0548 lsls r0, r1, #21 +100018e2: d4e0 bmi.n 100018a6 <_ntoa_format+0x82> +100018e4: f1bc 0f00 cmp.w ip, #0 +100018e8: d1d9 bne.n 1000189e <_ntoa_format+0x7a> +100018ea: f1ba 0f10 cmp.w sl, #16 +100018ee: d05f beq.n 100019b0 <_ntoa_format+0x18c> +100018f0: f1ba 0f02 cmp.w sl, #2 +100018f4: d074 beq.n 100019e0 <_ntoa_format+0x1bc> +100018f6: 2230 movs r2, #48 @ 0x30 +100018f8: f04f 0c01 mov.w ip, #1 +100018fc: 7022 strb r2, [r4, #0] +100018fe: f1bb 0f00 cmp.w fp, #0 +10001902: d112 bne.n 1000192a <_ntoa_format+0x106> +10001904: 0748 lsls r0, r1, #29 +10001906: d542 bpl.n 1000198e <_ntoa_format+0x16a> +10001908: 222b movs r2, #43 @ 0x2b +1000190a: f804 200c strb.w r2, [r4, ip] +1000190e: f10c 0201 add.w r2, ip, #1 +10001912: e7d2 b.n 100018ba <_ntoa_format+0x96> +10001914: 4662 mov r2, ip +10001916: f10c 0c01 add.w ip, ip, #1 +1000191a: 2030 movs r0, #48 @ 0x30 +1000191c: 54a0 strb r0, [r4, r2] +1000191e: f1bc 0f20 cmp.w ip, #32 +10001922: d0c9 beq.n 100018b8 <_ntoa_format+0x94> +10001924: f1bb 0f00 cmp.w fp, #0 +10001928: d0ec beq.n 10001904 <_ntoa_format+0xe0> +1000192a: 222d movs r2, #45 @ 0x2d +1000192c: f804 200c strb.w r2, [r4, ip] +10001930: f10c 0201 add.w r2, ip, #1 +10001934: e7c1 b.n 100018ba <_ntoa_format+0x96> +10001936: b398 cbz r0, 100019a0 <_ntoa_format+0x17c> +10001938: 4594 cmp ip, r2 +1000193a: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff +1000193e: d389 bcc.n 10001854 <_ntoa_format+0x30> +10001940: e799 b.n 10001876 <_ntoa_format+0x52> +10001942: f1ba 0f10 cmp.w sl, #16 +10001946: d1b7 bne.n 100018b8 <_ntoa_format+0x94> +10001948: 068d lsls r5, r1, #26 +1000194a: d53d bpl.n 100019c8 <_ntoa_format+0x1a4> +1000194c: f1bc 0f20 cmp.w ip, #32 +10001950: d0b2 beq.n 100018b8 <_ntoa_format+0x94> +10001952: 2258 movs r2, #88 @ 0x58 +10001954: f804 200c strb.w r2, [r4, ip] +10001958: f10c 0c01 add.w ip, ip, #1 +1000195c: e7a9 b.n 100018b2 <_ntoa_format+0x8e> +1000195e: f1bc 0f20 cmp.w ip, #32 +10001962: d0a9 beq.n 100018b8 <_ntoa_format+0x94> +10001964: 4662 mov r2, ip +10001966: f10c 0c01 add.w ip, ip, #1 +1000196a: e008 b.n 1000197e <_ntoa_format+0x15a> +1000196c: f1bc 0201 subs.w r2, ip, #1 +10001970: d0bb beq.n 100018ea <_ntoa_format+0xc6> +10001972: f1ba 0f10 cmp.w sl, #16 +10001976: d035 beq.n 100019e4 <_ntoa_format+0x1c0> +10001978: f1ba 0f02 cmp.w sl, #2 +1000197c: d1cd bne.n 1000191a <_ntoa_format+0xf6> +1000197e: 2062 movs r0, #98 @ 0x62 +10001980: 54a0 strb r0, [r4, r2] +10001982: e796 b.n 100018b2 <_ntoa_format+0x8e> +10001984: 06cd lsls r5, r1, #27 +10001986: d5ca bpl.n 1000191e <_ntoa_format+0xfa> +10001988: 0548 lsls r0, r1, #21 +1000198a: d588 bpl.n 1000189e <_ntoa_format+0x7a> +1000198c: e78b b.n 100018a6 <_ntoa_format+0x82> +1000198e: 070a lsls r2, r1, #28 +10001990: bf49 itett mi +10001992: 2220 movmi r2, #32 +10001994: 4662 movpl r2, ip +10001996: f804 200c strbmi.w r2, [r4, ip] +1000199a: f10c 0201 addmi.w r2, ip, #1 +1000199e: e78c b.n 100018ba <_ntoa_format+0x96> +100019a0: f011 0f0c tst.w r1, #12 +100019a4: d000 beq.n 100019a8 <_ntoa_format+0x184> +100019a6: 3b01 subs r3, #1 +100019a8: 4594 cmp ip, r2 +100019aa: f4ff af53 bcc.w 10001854 <_ntoa_format+0x30> +100019ae: e762 b.n 10001876 <_ntoa_format+0x52> +100019b0: 068a lsls r2, r1, #26 +100019b2: d413 bmi.n 100019dc <_ntoa_format+0x1b8> +100019b4: 2278 movs r2, #120 @ 0x78 +100019b6: 7022 strb r2, [r4, #0] +100019b8: 2230 movs r2, #48 @ 0x30 +100019ba: f04f 0c02 mov.w ip, #2 +100019be: 7062 strb r2, [r4, #1] +100019c0: f1bb 0f00 cmp.w fp, #0 +100019c4: d09e beq.n 10001904 <_ntoa_format+0xe0> +100019c6: e7b0 b.n 1000192a <_ntoa_format+0x106> +100019c8: f1bc 0f20 cmp.w ip, #32 +100019cc: f43f af74 beq.w 100018b8 <_ntoa_format+0x94> +100019d0: 2278 movs r2, #120 @ 0x78 +100019d2: f804 200c strb.w r2, [r4, ip] +100019d6: f10c 0c01 add.w ip, ip, #1 +100019da: e76a b.n 100018b2 <_ntoa_format+0x8e> +100019dc: 2258 movs r2, #88 @ 0x58 +100019de: e7ea b.n 100019b6 <_ntoa_format+0x192> +100019e0: 2262 movs r2, #98 @ 0x62 +100019e2: e7e8 b.n 100019b6 <_ntoa_format+0x192> +100019e4: 068d lsls r5, r1, #26 +100019e6: f1ac 0002 sub.w r0, ip, #2 +100019ea: d504 bpl.n 100019f6 <_ntoa_format+0x1d2> +100019ec: f04f 0e58 mov.w lr, #88 @ 0x58 +100019f0: f804 e000 strb.w lr, [r4, r0] +100019f4: e791 b.n 1000191a <_ntoa_format+0xf6> +100019f6: f04f 0e78 mov.w lr, #120 @ 0x78 +100019fa: f804 e000 strb.w lr, [r4, r0] +100019fe: e78c b.n 1000191a <_ntoa_format+0xf6> + +10001a00 <_out_char>: +10001a00: b900 cbnz r0, 10001a04 <_out_char+0x4> +10001a02: 4770 bx lr +10001a04: f001 bb64 b.w 100030d0 <__wrap_putchar> + +10001a08 <_out_fct>: +10001a08: b110 cbz r0, 10001a10 <_out_fct+0x8> +10001a0a: e9d1 3100 ldrd r3, r1, [r1] +10001a0e: 4718 bx r3 +10001a10: 4770 bx lr +10001a12: bf00 nop +10001a14: 0000 movs r0, r0 + ... + +10001a18 <_ftoa>: +10001a18: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a1c: b097 sub sp, #92 @ 0x5c +10001a1e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001a22: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001a26: 4680 mov r8, r0 +10001a28: 4689 mov r9, r1 +10001a2a: ec51 0b17 vmov r0, r1, d7 +10001a2e: 469a mov sl, r3 +10001a30: 9b24 ldr r3, [sp, #144] @ 0x90 +10001a32: 920c str r2, [sp, #48] @ 0x30 +10001a34: 9307 str r3, [sp, #28] +10001a36: 4602 mov r2, r0 +10001a38: 460b mov r3, r1 +10001a3a: ed8d 7b04 vstr d7, [sp, #16] +10001a3e: f7ff fe3d bl 100016bc <__wrap___aeabi_dcmpun> +10001a42: 2800 cmp r0, #0 +10001a44: f040 81e3 bne.w 10001e0e <_ftoa+0x3f6> +10001a48: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a4c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a50: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001a54: f7ff fe44 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a58: 2800 cmp r0, #0 +10001a5a: f040 80cb bne.w 10001bf4 <_ftoa+0x1dc> +10001a5e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a62: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a66: 4bb2 ldr r3, [pc, #712] @ (10001d30 <_ftoa+0x318>) +10001a68: f7ff fe76 bl 10001758 <__wrap___aeabi_dcmpgt> +10001a6c: 2800 cmp r0, #0 +10001a6e: f040 809f bne.w 10001bb0 <_ftoa+0x198> +10001a72: e9dd 6704 ldrd r6, r7, [sp, #16] +10001a76: a3aa add r3, pc, #680 @ (adr r3, 10001d20 <_ftoa+0x308>) +10001a78: e9d3 2300 ldrd r2, r3, [r3] +10001a7c: 4630 mov r0, r6 +10001a7e: 4639 mov r1, r7 +10001a80: f7ff fe6a bl 10001758 <__wrap___aeabi_dcmpgt> +10001a84: 2800 cmp r0, #0 +10001a86: f040 8082 bne.w 10001b8e <_ftoa+0x176> +10001a8a: a3a7 add r3, pc, #668 @ (adr r3, 10001d28 <_ftoa+0x310>) +10001a8c: e9d3 2300 ldrd r2, r3, [r3] +10001a90: 4630 mov r0, r6 +10001a92: 4639 mov r1, r7 +10001a94: f7ff fe24 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a98: 2800 cmp r0, #0 +10001a9a: d178 bne.n 10001b8e <_ftoa+0x176> +10001a9c: 4630 mov r0, r6 +10001a9e: 4639 mov r1, r7 +10001aa0: 2200 movs r2, #0 +10001aa2: 2300 movs r3, #0 +10001aa4: f7ff fe1c bl 100016e0 <__wrap___aeabi_dcmplt> +10001aa8: 2800 cmp r0, #0 +10001aaa: f040 8098 bne.w 10001bde <_ftoa+0x1c6> +10001aae: 900d str r0, [sp, #52] @ 0x34 +10001ab0: 9b07 ldr r3, [sp, #28] +10001ab2: 2130 movs r1, #48 @ 0x30 +10001ab4: f413 6f80 tst.w r3, #1024 @ 0x400 +10001ab8: bf08 it eq +10001aba: 2506 moveq r5, #6 +10001abc: aa0e add r2, sp, #56 @ 0x38 +10001abe: 462b mov r3, r5 +10001ac0: f1a5 0620 sub.w r6, r5, #32 +10001ac4: e005 b.n 10001ad2 <_ftoa+0xba> +10001ac6: 3b01 subs r3, #1 +10001ac8: 42b3 cmp r3, r6 +10001aca: f802 1b01 strb.w r1, [r2], #1 +10001ace: f000 8165 beq.w 10001d9c <_ftoa+0x384> +10001ad2: 2b09 cmp r3, #9 +10001ad4: d8f7 bhi.n 10001ac6 <_ftoa+0xae> +10001ad6: 461e mov r6, r3 +10001ad8: 1aed subs r5, r5, r3 +10001ada: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ade: f7ff fdc9 bl 10001674 <__wrap___aeabi_d2iz> +10001ae2: 4b94 ldr r3, [pc, #592] @ (10001d34 <_ftoa+0x31c>) +10001ae4: 4604 mov r4, r0 +10001ae6: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001aea: ed93 7b00 vldr d7, [r3] +10001aee: ed8d 7b08 vstr d7, [sp, #32] +10001af2: f7ff fd9b bl 1000162c <__wrap___aeabi_i2d> +10001af6: 4602 mov r2, r0 +10001af8: 460b mov r3, r1 +10001afa: e9dd 0104 ldrd r0, r1, [sp, #16] +10001afe: f7ff fd0f bl 10001520 <__wrap___aeabi_dsub> +10001b02: e9dd 2308 ldrd r2, r3, [sp, #32] +10001b06: f7ff fd1f bl 10001548 <__wrap___aeabi_dmul> +10001b0a: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10001b0e: f7ff fdc3 bl 10001698 <__wrap___aeabi_d2uiz> +10001b12: 4607 mov r7, r0 +10001b14: f7ff fd9c bl 10001650 <__wrap___aeabi_ui2d> +10001b18: 4602 mov r2, r0 +10001b1a: 460b mov r3, r1 +10001b1c: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001b20: f7ff fcfe bl 10001520 <__wrap___aeabi_dsub> +10001b24: 2200 movs r2, #0 +10001b26: 4b84 ldr r3, [pc, #528] @ (10001d38 <_ftoa+0x320>) +10001b28: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10001b2c: f7ff fe14 bl 10001758 <__wrap___aeabi_dcmpgt> +10001b30: 2800 cmp r0, #0 +10001b32: f000 8088 beq.w 10001c46 <_ftoa+0x22e> +10001b36: 3701 adds r7, #1 +10001b38: 4638 mov r0, r7 +10001b3a: f7ff fd89 bl 10001650 <__wrap___aeabi_ui2d> +10001b3e: 4602 mov r2, r0 +10001b40: 460b mov r3, r1 +10001b42: e9dd 0108 ldrd r0, r1, [sp, #32] +10001b46: f7ff fddf bl 10001708 <__wrap___aeabi_dcmple> +10001b4a: b108 cbz r0, 10001b50 <_ftoa+0x138> +10001b4c: 2700 movs r7, #0 +10001b4e: 3401 adds r4, #1 +10001b50: 2e00 cmp r6, #0 +10001b52: f000 8088 beq.w 10001c66 <_ftoa+0x24e> +10001b56: f10d 0337 add.w r3, sp, #55 @ 0x37 +10001b5a: f8df c1f0 ldr.w ip, [pc, #496] @ 10001d4c <_ftoa+0x334> +10001b5e: 1958 adds r0, r3, r5 +10001b60: e00d b.n 10001b7e <_ftoa+0x166> +10001b62: fbac 2107 umull r2, r1, ip, r7 +10001b66: 08c9 lsrs r1, r1, #3 +10001b68: eb01 0281 add.w r2, r1, r1, lsl #2 +10001b6c: eba7 0242 sub.w r2, r7, r2, lsl #1 +10001b70: 3230 adds r2, #48 @ 0x30 +10001b72: 2f09 cmp r7, #9 +10001b74: f800 2f01 strb.w r2, [r0, #1]! +10001b78: f240 80fb bls.w 10001d72 <_ftoa+0x35a> +10001b7c: 460f mov r7, r1 +10001b7e: 2d20 cmp r5, #32 +10001b80: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001b84: f105 0501 add.w r5, r5, #1 +10001b88: d1eb bne.n 10001b62 <_ftoa+0x14a> +10001b8a: 2520 movs r5, #32 +10001b8c: e086 b.n 10001c9c <_ftoa+0x284> +10001b8e: 9b07 ldr r3, [sp, #28] +10001b90: ed9d 7b04 vldr d7, [sp, #16] +10001b94: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001b98: 4649 mov r1, r9 +10001b9a: 4653 mov r3, sl +10001b9c: 4640 mov r0, r8 +10001b9e: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ba0: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001ba4: 9522 str r5, [sp, #136] @ 0x88 +10001ba6: b017 add sp, #92 @ 0x5c +10001ba8: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001bac: f000 b980 b.w 10001eb0 <_etoa> +10001bb0: 9b07 ldr r3, [sp, #28] +10001bb2: 4649 mov r1, r9 +10001bb4: 0758 lsls r0, r3, #29 +10001bb6: bf4c ite mi +10001bb8: 2304 movmi r3, #4 +10001bba: 2303 movpl r3, #3 +10001bbc: 4640 mov r0, r8 +10001bbe: 9321 str r3, [sp, #132] @ 0x84 +10001bc0: 4653 mov r3, sl +10001bc2: 9a07 ldr r2, [sp, #28] +10001bc4: bf48 it mi +10001bc6: 4c5d ldrmi r4, [pc, #372] @ (10001d3c <_ftoa+0x324>) +10001bc8: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001bcc: bf58 it pl +10001bce: 4c5c ldrpl r4, [pc, #368] @ (10001d40 <_ftoa+0x328>) +10001bd0: 9a0c ldr r2, [sp, #48] @ 0x30 +10001bd2: 9420 str r4, [sp, #128] @ 0x80 +10001bd4: b017 add sp, #92 @ 0x5c +10001bd6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001bda: f7ff bdcf b.w 1000177c <_out_rev> +10001bde: 463b mov r3, r7 +10001be0: 4632 mov r2, r6 +10001be2: 2000 movs r0, #0 +10001be4: 2100 movs r1, #0 +10001be6: f7ff fc9b bl 10001520 <__wrap___aeabi_dsub> +10001bea: 2301 movs r3, #1 +10001bec: e9cd 0104 strd r0, r1, [sp, #16] +10001bf0: 930d str r3, [sp, #52] @ 0x34 +10001bf2: e75d b.n 10001ab0 <_ftoa+0x98> +10001bf4: 9b07 ldr r3, [sp, #28] +10001bf6: f003 0202 and.w r2, r3, #2 +10001bfa: 079c lsls r4, r3, #30 +10001bfc: 9204 str r2, [sp, #16] +10001bfe: f000 80f4 beq.w 10001dea <_ftoa+0x3d2> +10001c02: 9f0c ldr r7, [sp, #48] @ 0x30 +10001c04: 463d mov r5, r7 +10001c06: 4e4f ldr r6, [pc, #316] @ (10001d44 <_ftoa+0x32c>) +10001c08: 1d34 adds r4, r6, #4 +10001c0a: f814 0d01 ldrb.w r0, [r4, #-1]! +10001c0e: 462a mov r2, r5 +10001c10: 4653 mov r3, sl +10001c12: 4649 mov r1, r9 +10001c14: 47c0 blx r8 +10001c16: 42a6 cmp r6, r4 +10001c18: f105 0501 add.w r5, r5, #1 +10001c1c: d1f5 bne.n 10001c0a <_ftoa+0x1f2> +10001c1e: 9b04 ldr r3, [sp, #16] +10001c20: 1d3c adds r4, r7, #4 +10001c22: b163 cbz r3, 10001c3e <_ftoa+0x226> +10001c24: 9d0c ldr r5, [sp, #48] @ 0x30 +10001c26: 1b63 subs r3, r4, r5 +10001c28: 459b cmp fp, r3 +10001c2a: d908 bls.n 10001c3e <_ftoa+0x226> +10001c2c: 4622 mov r2, r4 +10001c2e: 4653 mov r3, sl +10001c30: 4649 mov r1, r9 +10001c32: 2020 movs r0, #32 +10001c34: 3401 adds r4, #1 +10001c36: 47c0 blx r8 +10001c38: 1b63 subs r3, r4, r5 +10001c3a: 459b cmp fp, r3 +10001c3c: d8f6 bhi.n 10001c2c <_ftoa+0x214> +10001c3e: 4620 mov r0, r4 +10001c40: b017 add sp, #92 @ 0x5c +10001c42: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001c46: 2200 movs r2, #0 +10001c48: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001c4c: 4b3a ldr r3, [pc, #232] @ (10001d38 <_ftoa+0x320>) +10001c4e: f7ff fd47 bl 100016e0 <__wrap___aeabi_dcmplt> +10001c52: 2800 cmp r0, #0 +10001c54: f47f af7c bne.w 10001b50 <_ftoa+0x138> +10001c58: 2f00 cmp r7, #0 +10001c5a: f040 80c2 bne.w 10001de2 <_ftoa+0x3ca> +10001c5e: 3701 adds r7, #1 +10001c60: 2e00 cmp r6, #0 +10001c62: f47f af78 bne.w 10001b56 <_ftoa+0x13e> +10001c66: 4620 mov r0, r4 +10001c68: f7ff fce0 bl 1000162c <__wrap___aeabi_i2d> +10001c6c: 4602 mov r2, r0 +10001c6e: 460b mov r3, r1 +10001c70: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c74: f7ff fc54 bl 10001520 <__wrap___aeabi_dsub> +10001c78: 2200 movs r2, #0 +10001c7a: 4b2f ldr r3, [pc, #188] @ (10001d38 <_ftoa+0x320>) +10001c7c: 4606 mov r6, r0 +10001c7e: 460f mov r7, r1 +10001c80: f7ff fd2e bl 100016e0 <__wrap___aeabi_dcmplt> +10001c84: b940 cbnz r0, 10001c98 <_ftoa+0x280> +10001c86: 4630 mov r0, r6 +10001c88: 4639 mov r1, r7 +10001c8a: 2200 movs r2, #0 +10001c8c: 4b2a ldr r3, [pc, #168] @ (10001d38 <_ftoa+0x320>) +10001c8e: f7ff fd63 bl 10001758 <__wrap___aeabi_dcmpgt> +10001c92: 2800 cmp r0, #0 +10001c94: f000 80a1 beq.w 10001dda <_ftoa+0x3c2> +10001c98: f10d 0337 add.w r3, sp, #55 @ 0x37 +10001c9c: 482a ldr r0, [pc, #168] @ (10001d48 <_ftoa+0x330>) +10001c9e: 1959 adds r1, r3, r5 +10001ca0: e00e b.n 10001cc0 <_ftoa+0x2a8> +10001ca2: fb80 7604 smull r7, r6, r0, r4 +10001ca6: ebc2 02a6 rsb r2, r2, r6, asr #2 +10001caa: eb02 0682 add.w r6, r2, r2, lsl #2 +10001cae: eba4 0646 sub.w r6, r4, r6, lsl #1 +10001cb2: 3630 adds r6, #48 @ 0x30 +10001cb4: 4614 mov r4, r2 +10001cb6: 3501 adds r5, #1 +10001cb8: f801 6f01 strb.w r6, [r1, #1]! +10001cbc: 2a00 cmp r2, #0 +10001cbe: d047 beq.n 10001d50 <_ftoa+0x338> +10001cc0: 2d20 cmp r5, #32 +10001cc2: ea4f 72e4 mov.w r2, r4, asr #31 +10001cc6: d1ec bne.n 10001ca2 <_ftoa+0x28a> +10001cc8: 9a07 ldr r2, [sp, #28] +10001cca: f002 0203 and.w r2, r2, #3 +10001cce: 2a01 cmp r2, #1 +10001cd0: d114 bne.n 10001cfc <_ftoa+0x2e4> +10001cd2: f1bb 0f00 cmp.w fp, #0 +10001cd6: d011 beq.n 10001cfc <_ftoa+0x2e4> +10001cd8: 9a0d ldr r2, [sp, #52] @ 0x34 +10001cda: 2a00 cmp r2, #0 +10001cdc: d060 beq.n 10001da0 <_ftoa+0x388> +10001cde: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001ce2: f1bb 0f20 cmp.w fp, #32 +10001ce6: d909 bls.n 10001cfc <_ftoa+0x2e4> +10001ce8: 2230 movs r2, #48 @ 0x30 +10001cea: 442b add r3, r5 +10001cec: e004 b.n 10001cf8 <_ftoa+0x2e0> +10001cee: 3501 adds r5, #1 +10001cf0: 455d cmp r5, fp +10001cf2: f803 2f01 strb.w r2, [r3, #1]! +10001cf6: d231 bcs.n 10001d5c <_ftoa+0x344> +10001cf8: 2d20 cmp r5, #32 +10001cfa: d1f8 bne.n 10001cee <_ftoa+0x2d6> +10001cfc: 9b07 ldr r3, [sp, #28] +10001cfe: ac0e add r4, sp, #56 @ 0x38 +10001d00: e9cd b302 strd fp, r3, [sp, #8] +10001d04: 9400 str r4, [sp, #0] +10001d06: 4653 mov r3, sl +10001d08: 4649 mov r1, r9 +10001d0a: 4640 mov r0, r8 +10001d0c: 9a0c ldr r2, [sp, #48] @ 0x30 +10001d0e: 9501 str r5, [sp, #4] +10001d10: f7ff fd34 bl 1000177c <_out_rev> +10001d14: 4604 mov r4, r0 +10001d16: 4620 mov r0, r4 +10001d18: b017 add sp, #92 @ 0x5c +10001d1a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001d1e: bf00 nop +10001d20: 00000000 .word 0x00000000 +10001d24: 41cdcd65 .word 0x41cdcd65 +10001d28: 00000000 .word 0x00000000 +10001d2c: c1cdcd65 .word 0xc1cdcd65 +10001d30: 7fefffff .word 0x7fefffff +10001d34: 10003860 .word 0x10003860 +10001d38: 3fe00000 .word 0x3fe00000 +10001d3c: 100037b8 .word 0x100037b8 +10001d40: 100037c0 .word 0x100037c0 +10001d44: 100037c8 .word 0x100037c8 +10001d48: 66666667 .word 0x66666667 +10001d4c: cccccccd .word 0xcccccccd +10001d50: 9a07 ldr r2, [sp, #28] +10001d52: f002 0203 and.w r2, r2, #3 +10001d56: 2a01 cmp r2, #1 +10001d58: f000 8096 beq.w 10001e88 <_ftoa+0x470> +10001d5c: 2d20 cmp r5, #32 +10001d5e: d0cd beq.n 10001cfc <_ftoa+0x2e4> +10001d60: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d62: b33b cbz r3, 10001db4 <_ftoa+0x39c> +10001d64: 222d movs r2, #45 @ 0x2d +10001d66: eb0d 0305 add.w r3, sp, r5 +10001d6a: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001d6e: 3501 adds r5, #1 +10001d70: e7c4 b.n 10001cfc <_ftoa+0x2e4> +10001d72: 2d20 cmp r5, #32 +10001d74: f43f af09 beq.w 10001b8a <_ftoa+0x172> +10001d78: 2130 movs r1, #48 @ 0x30 +10001d7a: 442e add r6, r5 +10001d7c: 195a adds r2, r3, r5 +10001d7e: e005 b.n 10001d8c <_ftoa+0x374> +10001d80: 3501 adds r5, #1 +10001d82: 2d20 cmp r5, #32 +10001d84: f802 1f01 strb.w r1, [r2, #1]! +10001d88: f43f aeff beq.w 10001b8a <_ftoa+0x172> +10001d8c: 42ae cmp r6, r5 +10001d8e: d1f7 bne.n 10001d80 <_ftoa+0x368> +10001d90: 222e movs r2, #46 @ 0x2e +10001d92: 446e add r6, sp +10001d94: 3501 adds r5, #1 +10001d96: f886 2038 strb.w r2, [r6, #56] @ 0x38 +10001d9a: e77f b.n 10001c9c <_ftoa+0x284> +10001d9c: 2520 movs r5, #32 +10001d9e: e69c b.n 10001ada <_ftoa+0xc2> +10001da0: 9a07 ldr r2, [sp, #28] +10001da2: f012 0f0c tst.w r2, #12 +10001da6: d05a beq.n 10001e5e <_ftoa+0x446> +10001da8: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001dac: 45ab cmp fp, r5 +10001dae: d89b bhi.n 10001ce8 <_ftoa+0x2d0> +10001db0: 2d20 cmp r5, #32 +10001db2: d0a3 beq.n 10001cfc <_ftoa+0x2e4> +10001db4: 9b07 ldr r3, [sp, #28] +10001db6: 075a lsls r2, r3, #29 +10001db8: d506 bpl.n 10001dc8 <_ftoa+0x3b0> +10001dba: 222b movs r2, #43 @ 0x2b +10001dbc: eb0d 0305 add.w r3, sp, r5 +10001dc0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001dc4: 3501 adds r5, #1 +10001dc6: e799 b.n 10001cfc <_ftoa+0x2e4> +10001dc8: 071b lsls r3, r3, #28 +10001dca: d597 bpl.n 10001cfc <_ftoa+0x2e4> +10001dcc: 2220 movs r2, #32 +10001dce: eb0d 0305 add.w r3, sp, r5 +10001dd2: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001dd6: 3501 adds r5, #1 +10001dd8: e790 b.n 10001cfc <_ftoa+0x2e4> +10001dda: 3401 adds r4, #1 +10001ddc: f024 0401 bic.w r4, r4, #1 +10001de0: e75a b.n 10001c98 <_ftoa+0x280> +10001de2: 07f9 lsls r1, r7, #31 +10001de4: f57f aeb4 bpl.w 10001b50 <_ftoa+0x138> +10001de8: e739 b.n 10001c5e <_ftoa+0x246> +10001dea: f1bb 0f04 cmp.w fp, #4 +10001dee: f67f af08 bls.w 10001c02 <_ftoa+0x1ea> +10001df2: 9b0c ldr r3, [sp, #48] @ 0x30 +10001df4: 461d mov r5, r3 +10001df6: 3b04 subs r3, #4 +10001df8: eb03 070b add.w r7, r3, fp +10001dfc: 462a mov r2, r5 +10001dfe: 4653 mov r3, sl +10001e00: 4649 mov r1, r9 +10001e02: 2020 movs r0, #32 +10001e04: 3501 adds r5, #1 +10001e06: 47c0 blx r8 +10001e08: 42af cmp r7, r5 +10001e0a: d1f7 bne.n 10001dfc <_ftoa+0x3e4> +10001e0c: e6fa b.n 10001c04 <_ftoa+0x1ec> +10001e0e: 9b07 ldr r3, [sp, #28] +10001e10: f003 0202 and.w r2, r3, #2 +10001e14: 079d lsls r5, r3, #30 +10001e16: 9204 str r2, [sp, #16] +10001e18: d025 beq.n 10001e66 <_ftoa+0x44e> +10001e1a: 9f0c ldr r7, [sp, #48] @ 0x30 +10001e1c: 463d mov r5, r7 +10001e1e: 4e22 ldr r6, [pc, #136] @ (10001ea8 <_ftoa+0x490>) +10001e20: 1cf4 adds r4, r6, #3 +10001e22: f814 0d01 ldrb.w r0, [r4, #-1]! +10001e26: 462a mov r2, r5 +10001e28: 4653 mov r3, sl +10001e2a: 4649 mov r1, r9 +10001e2c: 47c0 blx r8 +10001e2e: 42a6 cmp r6, r4 +10001e30: f105 0501 add.w r5, r5, #1 +10001e34: d1f5 bne.n 10001e22 <_ftoa+0x40a> +10001e36: 9b04 ldr r3, [sp, #16] +10001e38: 1cfc adds r4, r7, #3 +10001e3a: 2b00 cmp r3, #0 +10001e3c: f43f aeff beq.w 10001c3e <_ftoa+0x226> +10001e40: 9d0c ldr r5, [sp, #48] @ 0x30 +10001e42: 1b63 subs r3, r4, r5 +10001e44: 459b cmp fp, r3 +10001e46: f67f aefa bls.w 10001c3e <_ftoa+0x226> +10001e4a: 4622 mov r2, r4 +10001e4c: 4653 mov r3, sl +10001e4e: 4649 mov r1, r9 +10001e50: 2020 movs r0, #32 +10001e52: 3401 adds r4, #1 +10001e54: 47c0 blx r8 +10001e56: 1b63 subs r3, r4, r5 +10001e58: 459b cmp fp, r3 +10001e5a: d8f6 bhi.n 10001e4a <_ftoa+0x432> +10001e5c: e6ef b.n 10001c3e <_ftoa+0x226> +10001e5e: 45ab cmp fp, r5 +10001e60: f63f af42 bhi.w 10001ce8 <_ftoa+0x2d0> +10001e64: e74a b.n 10001cfc <_ftoa+0x2e4> +10001e66: f1bb 0f03 cmp.w fp, #3 +10001e6a: d9d6 bls.n 10001e1a <_ftoa+0x402> +10001e6c: 9b0c ldr r3, [sp, #48] @ 0x30 +10001e6e: 461d mov r5, r3 +10001e70: 3b03 subs r3, #3 +10001e72: eb03 070b add.w r7, r3, fp +10001e76: 462a mov r2, r5 +10001e78: 4653 mov r3, sl +10001e7a: 4649 mov r1, r9 +10001e7c: 2020 movs r0, #32 +10001e7e: 3501 adds r5, #1 +10001e80: 47c0 blx r8 +10001e82: 42bd cmp r5, r7 +10001e84: d1f7 bne.n 10001e76 <_ftoa+0x45e> +10001e86: e7c9 b.n 10001e1c <_ftoa+0x404> +10001e88: f1bb 0f00 cmp.w fp, #0 +10001e8c: f43f af66 beq.w 10001d5c <_ftoa+0x344> +10001e90: 9a0d ldr r2, [sp, #52] @ 0x34 +10001e92: 2a00 cmp r2, #0 +10001e94: d084 beq.n 10001da0 <_ftoa+0x388> +10001e96: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001e9a: 455d cmp r5, fp +10001e9c: f4ff af24 bcc.w 10001ce8 <_ftoa+0x2d0> +10001ea0: 2d20 cmp r5, #32 +10001ea2: f47f af5f bne.w 10001d64 <_ftoa+0x34c> +10001ea6: e729 b.n 10001cfc <_ftoa+0x2e4> +10001ea8: 100037c4 .word 0x100037c4 +10001eac: 00000000 .word 0x00000000 + +10001eb0 <_etoa>: +10001eb0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001eb4: b09f sub sp, #124 @ 0x7c +10001eb6: 461e mov r6, r3 +10001eb8: e9dd ab28 ldrd sl, fp, [sp, #160] @ 0xa0 +10001ebc: e9dd 982b ldrd r9, r8, [sp, #172] @ 0xac +10001ec0: 9b2a ldr r3, [sp, #168] @ 0xa8 +10001ec2: 4604 mov r4, r0 +10001ec4: 460d mov r5, r1 +10001ec6: 920b str r2, [sp, #44] @ 0x2c +10001ec8: 930a str r3, [sp, #40] @ 0x28 +10001eca: 4652 mov r2, sl +10001ecc: 465b mov r3, fp +10001ece: 4650 mov r0, sl +10001ed0: 4659 mov r1, fp +10001ed2: f7ff fbf3 bl 100016bc <__wrap___aeabi_dcmpun> +10001ed6: 2800 cmp r0, #0 +10001ed8: f040 80c6 bne.w 10002068 <_etoa+0x1b8> +10001edc: 4650 mov r0, sl +10001ede: 4659 mov r1, fp +10001ee0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001ee4: 4b7b ldr r3, [pc, #492] @ (100020d4 <_etoa+0x224>) +10001ee6: f7ff fc37 bl 10001758 <__wrap___aeabi_dcmpgt> +10001eea: 2800 cmp r0, #0 +10001eec: f040 80bc bne.w 10002068 <_etoa+0x1b8> +10001ef0: 4650 mov r0, sl +10001ef2: 4659 mov r1, fp +10001ef4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001ef8: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001efc: f7ff fbf0 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f00: 2800 cmp r0, #0 +10001f02: f040 80b1 bne.w 10002068 <_etoa+0x1b8> +10001f06: 4650 mov r0, sl +10001f08: 4659 mov r1, fp +10001f0a: 2200 movs r2, #0 +10001f0c: 2300 movs r3, #0 +10001f0e: f7ff fbe7 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f12: 2800 cmp r0, #0 +10001f14: f040 81dd bne.w 100022d2 <_etoa+0x422> +10001f18: e9cd ab08 strd sl, fp, [sp, #32] +10001f1c: e9dd 1208 ldrd r1, r2, [sp, #32] +10001f20: f418 6080 ands.w r0, r8, #1024 @ 0x400 +10001f24: 460b mov r3, r1 +10001f26: 460f mov r7, r1 +10001f28: f408 6100 and.w r1, r8, #2048 @ 0x800 +10001f2c: 920c str r2, [sp, #48] @ 0x30 +10001f2e: 9114 str r1, [sp, #80] @ 0x50 +10001f30: 9015 str r0, [sp, #84] @ 0x54 +10001f32: f040 80a8 bne.w 10002086 <_etoa+0x1d6> +10001f36: 4313 orrs r3, r2 +10001f38: f040 80d0 bne.w 100020dc <_etoa+0x22c> +10001f3c: 2900 cmp r1, #0 +10001f3e: f040 81ec bne.w 1000231a <_etoa+0x46a> +10001f42: 2306 movs r3, #6 +10001f44: 930a str r3, [sp, #40] @ 0x28 +10001f46: f018 0202 ands.w r2, r8, #2 +10001f4a: 9210 str r2, [sp, #64] @ 0x40 +10001f4c: f040 81dd bne.w 1000230a <_etoa+0x45a> +10001f50: 464b mov r3, r9 +10001f52: 2b04 cmp r3, #4 +10001f54: bf38 it cc +10001f56: 2304 movcc r3, #4 +10001f58: 920e str r2, [sp, #56] @ 0x38 +10001f5a: 2204 movs r2, #4 +10001f5c: 3b04 subs r3, #4 +10001f5e: 9212 str r2, [sp, #72] @ 0x48 +10001f60: 9314 str r3, [sp, #80] @ 0x50 +10001f62: 4650 mov r0, sl +10001f64: 4659 mov r1, fp +10001f66: 2200 movs r2, #0 +10001f68: 2300 movs r3, #0 +10001f6a: f7ff fbb9 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f6e: 2800 cmp r0, #0 +10001f70: f040 822a bne.w 100023c8 <_etoa+0x518> +10001f74: ed9d 7b08 vldr d7, [sp, #32] +10001f78: 9b14 ldr r3, [sp, #80] @ 0x50 +10001f7a: 9a0b ldr r2, [sp, #44] @ 0x2c +10001f7c: 9303 str r3, [sp, #12] +10001f7e: 9b0a ldr r3, [sp, #40] @ 0x28 +10001f80: ed8d 7b00 vstr d7, [sp] +10001f84: 9302 str r3, [sp, #8] +10001f86: f428 6300 bic.w r3, r8, #2048 @ 0x800 +10001f8a: 9304 str r3, [sp, #16] +10001f8c: 4629 mov r1, r5 +10001f8e: 4633 mov r3, r6 +10001f90: 4620 mov r0, r4 +10001f92: f7ff fd41 bl 10001a18 <_ftoa> +10001f96: 4602 mov r2, r0 +10001f98: f018 0f20 tst.w r8, #32 +10001f9c: 4633 mov r3, r6 +10001f9e: 4629 mov r1, r5 +10001fa0: bf0c ite eq +10001fa2: 2065 moveq r0, #101 @ 0x65 +10001fa4: 2045 movne r0, #69 @ 0x45 +10001fa6: f102 0801 add.w r8, r2, #1 +10001faa: 47a0 blx r4 +10001fac: 9b12 ldr r3, [sp, #72] @ 0x48 +10001fae: f10d 0a58 add.w sl, sp, #88 @ 0x58 +10001fb2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff +10001fb6: 9b0e ldr r3, [sp, #56] @ 0x38 +10001fb8: 2200 movs r2, #0 +10001fba: ea83 7ce3 eor.w ip, r3, r3, asr #31 +10001fbe: 4650 mov r0, sl +10001fc0: f8df e114 ldr.w lr, [pc, #276] @ 100020d8 <_etoa+0x228> +10001fc4: 9f0b ldr r7, [sp, #44] @ 0x2c +10001fc6: ebac 7ce3 sub.w ip, ip, r3, asr #31 +10001fca: 0fd9 lsrs r1, r3, #31 +10001fcc: f8cd 8020 str.w r8, [sp, #32] +10001fd0: e002 b.n 10001fd8 <_etoa+0x128> +10001fd2: 2a20 cmp r2, #32 +10001fd4: 46c4 mov ip, r8 +10001fd6: d010 beq.n 10001ffa <_etoa+0x14a> +10001fd8: fbae 380c umull r3, r8, lr, ip +10001fdc: ea4f 08d8 mov.w r8, r8, lsr #3 +10001fe0: eb08 0388 add.w r3, r8, r8, lsl #2 +10001fe4: ebac 0343 sub.w r3, ip, r3, lsl #1 +10001fe8: 3001 adds r0, #1 +10001fea: 3330 adds r3, #48 @ 0x30 +10001fec: f1bc 0f09 cmp.w ip, #9 +10001ff0: f102 0201 add.w r2, r2, #1 +10001ff4: f800 3c01 strb.w r3, [r0, #-1] +10001ff8: d8eb bhi.n 10001fd2 <_etoa+0x122> +10001ffa: 2305 movs r3, #5 +10001ffc: f04f 0c00 mov.w ip, #0 +10002000: 9306 str r3, [sp, #24] +10002002: 230a movs r3, #10 +10002004: f8dd 8020 ldr.w r8, [sp, #32] +10002008: e9cd 2101 strd r2, r1, [sp, #4] +1000200c: e9cd 3c03 strd r3, ip, [sp, #12] +10002010: f8cd a000 str.w sl, [sp] +10002014: 4633 mov r3, r6 +10002016: 4642 mov r2, r8 +10002018: 4629 mov r1, r5 +1000201a: 4620 mov r0, r4 +1000201c: f8cd b014 str.w fp, [sp, #20] +10002020: f7ff fc00 bl 10001824 <_ntoa_format> +10002024: 9b10 ldr r3, [sp, #64] @ 0x40 +10002026: 4682 mov sl, r0 +10002028: b1d3 cbz r3, 10002060 <_etoa+0x1b0> +1000202a: eba0 0807 sub.w r8, r0, r7 +1000202e: 45c1 cmp r9, r8 +10002030: d916 bls.n 10002060 <_etoa+0x1b0> +10002032: eb07 0208 add.w r2, r7, r8 +10002036: 4633 mov r3, r6 +10002038: 4629 mov r1, r5 +1000203a: 2020 movs r0, #32 +1000203c: f108 0801 add.w r8, r8, #1 +10002040: 47a0 blx r4 +10002042: 45c1 cmp r9, r8 +10002044: d8f5 bhi.n 10002032 <_etoa+0x182> +10002046: 1e7b subs r3, r7, #1 +10002048: 444b add r3, r9 +1000204a: f1c7 0201 rsb r2, r7, #1 +1000204e: eba3 030a sub.w r3, r3, sl +10002052: 4452 add r2, sl +10002054: 4591 cmp r9, r2 +10002056: bf38 it cc +10002058: 2300 movcc r3, #0 +1000205a: f10a 0a01 add.w sl, sl, #1 +1000205e: 449a add sl, r3 +10002060: 4650 mov r0, sl +10002062: b01f add sp, #124 @ 0x7c +10002064: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002068: 4633 mov r3, r6 +1000206a: 4629 mov r1, r5 +1000206c: 4620 mov r0, r4 +1000206e: e9cd ab28 strd sl, fp, [sp, #160] @ 0xa0 +10002072: 9c0a ldr r4, [sp, #40] @ 0x28 +10002074: e9cd 982b strd r9, r8, [sp, #172] @ 0xac +10002078: 9a0b ldr r2, [sp, #44] @ 0x2c +1000207a: 942a str r4, [sp, #168] @ 0xa8 +1000207c: b01f add sp, #124 @ 0x7c +1000207e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002082: f7ff bcc9 b.w 10001a18 <_ftoa> +10002086: ea57 0302 orrs.w r3, r7, r2 +1000208a: d129 bne.n 100020e0 <_etoa+0x230> +1000208c: 2900 cmp r1, #0 +1000208e: f43f af5a beq.w 10001f46 <_etoa+0x96> +10002092: 2300 movs r3, #0 +10002094: 930e str r3, [sp, #56] @ 0x38 +10002096: 9b0a ldr r3, [sp, #40] @ 0x28 +10002098: 9a0e ldr r2, [sp, #56] @ 0x38 +1000209a: 4293 cmp r3, r2 +1000209c: f300 81ba bgt.w 10002414 <_etoa+0x564> +100020a0: 2700 movs r7, #0 +100020a2: 4650 mov r0, sl +100020a4: 4659 mov r1, fp +100020a6: 2200 movs r2, #0 +100020a8: 2300 movs r3, #0 +100020aa: f7ff fb19 bl 100016e0 <__wrap___aeabi_dcmplt> +100020ae: 2800 cmp r0, #0 +100020b0: f040 8115 bne.w 100022de <_etoa+0x42e> +100020b4: ed9d 7b08 vldr d7, [sp, #32] +100020b8: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100020bc: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100020c0: 932c str r3, [sp, #176] @ 0xb0 +100020c2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100020c6: 4633 mov r3, r6 +100020c8: 4629 mov r1, r5 +100020ca: 4620 mov r0, r4 +100020cc: e9cd 792a strd r7, r9, [sp, #168] @ 0xa8 +100020d0: 9a0b ldr r2, [sp, #44] @ 0x2c +100020d2: e7d3 b.n 1000207c <_etoa+0x1cc> +100020d4: 7fefffff .word 0x7fefffff +100020d8: cccccccd .word 0xcccccccd +100020dc: 2306 movs r3, #6 +100020de: 930a str r3, [sp, #40] @ 0x28 +100020e0: 9b0c ldr r3, [sp, #48] @ 0x30 +100020e2: f3c3 500a ubfx r0, r3, #20, #11 +100020e6: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100020ea: f7ff fa9f bl 1000162c <__wrap___aeabi_i2d> +100020ee: a3b2 add r3, pc, #712 @ (adr r3, 100023b8 <_etoa+0x508>) +100020f0: e9d3 2300 ldrd r2, r3, [r3] +100020f4: f7ff fa28 bl 10001548 <__wrap___aeabi_dmul> +100020f8: a3b1 add r3, pc, #708 @ (adr r3, 100023c0 <_etoa+0x510>) +100020fa: e9d3 2300 ldrd r2, r3, [r3] +100020fe: f7ff f9fb bl 100014f8 <__wrap___aeabi_dadd> +10002102: 9b0c ldr r3, [sp, #48] @ 0x30 +10002104: e9cd 010e strd r0, r1, [sp, #56] @ 0x38 +10002108: f3c3 0313 ubfx r3, r3, #0, #20 +1000210c: f043 517f orr.w r1, r3, #1069547520 @ 0x3fc00000 +10002110: 4638 mov r0, r7 +10002112: 2200 movs r2, #0 +10002114: 4ba2 ldr r3, [pc, #648] @ (100023a0 <_etoa+0x4f0>) +10002116: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +1000211a: f7ff fa01 bl 10001520 <__wrap___aeabi_dsub> +1000211e: a394 add r3, pc, #592 @ (adr r3, 10002370 <_etoa+0x4c0>) +10002120: e9d3 2300 ldrd r2, r3, [r3] +10002124: f7ff fa10 bl 10001548 <__wrap___aeabi_dmul> +10002128: 4602 mov r2, r0 +1000212a: 460b mov r3, r1 +1000212c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38 +10002130: f7ff f9e2 bl 100014f8 <__wrap___aeabi_dadd> +10002134: f7ff fa9e bl 10001674 <__wrap___aeabi_d2iz> +10002138: 900e str r0, [sp, #56] @ 0x38 +1000213a: f7ff fa77 bl 1000162c <__wrap___aeabi_i2d> +1000213e: a38e add r3, pc, #568 @ (adr r3, 10002378 <_etoa+0x4c8>) +10002140: e9d3 2300 ldrd r2, r3, [r3] +10002144: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002148: f7ff f9fe bl 10001548 <__wrap___aeabi_dmul> +1000214c: 2200 movs r2, #0 +1000214e: 4b95 ldr r3, [pc, #596] @ (100023a4 <_etoa+0x4f4>) +10002150: f7ff f9d2 bl 100014f8 <__wrap___aeabi_dadd> +10002154: f7ff fa8e bl 10001674 <__wrap___aeabi_d2iz> +10002158: a389 add r3, pc, #548 @ (adr r3, 10002380 <_etoa+0x4d0>) +1000215a: e9d3 2300 ldrd r2, r3, [r3] +1000215e: 4607 mov r7, r0 +10002160: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002164: f7ff f9f0 bl 10001548 <__wrap___aeabi_dmul> +10002168: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +1000216c: 4638 mov r0, r7 +1000216e: f7ff fa5d bl 1000162c <__wrap___aeabi_i2d> +10002172: a385 add r3, pc, #532 @ (adr r3, 10002388 <_etoa+0x4d8>) +10002174: e9d3 2300 ldrd r2, r3, [r3] +10002178: f7ff f9e6 bl 10001548 <__wrap___aeabi_dmul> +1000217c: 4602 mov r2, r0 +1000217e: 460b mov r3, r1 +10002180: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002184: f7ff f9cc bl 10001520 <__wrap___aeabi_dsub> +10002188: 4602 mov r2, r0 +1000218a: 460b mov r3, r1 +1000218c: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 +10002190: f7ff f9da bl 10001548 <__wrap___aeabi_dmul> +10002194: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002198: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +1000219c: 4602 mov r2, r0 +1000219e: 460b mov r3, r1 +100021a0: f7ff f9aa bl 100014f8 <__wrap___aeabi_dadd> +100021a4: 2200 movs r2, #0 +100021a6: e9cd 0112 strd r0, r1, [sp, #72] @ 0x48 +100021aa: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021ae: 4b7e ldr r3, [pc, #504] @ (100023a8 <_etoa+0x4f8>) +100021b0: f7ff f9ee bl 10001590 <__wrap___aeabi_ddiv> +100021b4: 2200 movs r2, #0 +100021b6: 4b7d ldr r3, [pc, #500] @ (100023ac <_etoa+0x4fc>) +100021b8: f7ff f99e bl 100014f8 <__wrap___aeabi_dadd> +100021bc: 4602 mov r2, r0 +100021be: 460b mov r3, r1 +100021c0: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021c4: f7ff f9e4 bl 10001590 <__wrap___aeabi_ddiv> +100021c8: 2200 movs r2, #0 +100021ca: 4b79 ldr r3, [pc, #484] @ (100023b0 <_etoa+0x500>) +100021cc: f7ff f994 bl 100014f8 <__wrap___aeabi_dadd> +100021d0: 4602 mov r2, r0 +100021d2: 460b mov r3, r1 +100021d4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021d8: f7ff f9da bl 10001590 <__wrap___aeabi_ddiv> +100021dc: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +100021e0: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 +100021e4: 2000 movs r0, #0 +100021e6: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100021ea: f7ff f999 bl 10001520 <__wrap___aeabi_dsub> +100021ee: 4602 mov r2, r0 +100021f0: 460b mov r3, r1 +100021f2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021f6: f7ff f97f bl 100014f8 <__wrap___aeabi_dadd> +100021fa: 4602 mov r2, r0 +100021fc: 460b mov r3, r1 +100021fe: e9dd 0112 ldrd r0, r1, [sp, #72] @ 0x48 +10002202: f7ff f9c5 bl 10001590 <__wrap___aeabi_ddiv> +10002206: 2200 movs r2, #0 +10002208: 4b6a ldr r3, [pc, #424] @ (100023b4 <_etoa+0x504>) +1000220a: f7ff f975 bl 100014f8 <__wrap___aeabi_dadd> +1000220e: f207 3cff addw ip, r7, #1023 @ 0x3ff +10002212: 2200 movs r2, #0 +10002214: ea4f 530c mov.w r3, ip, lsl #20 +10002218: f7ff f996 bl 10001548 <__wrap___aeabi_dmul> +1000221c: 4602 mov r2, r0 +1000221e: 460b mov r3, r1 +10002220: e9dd 0108 ldrd r0, r1, [sp, #32] +10002224: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 +10002228: f7ff fa5a bl 100016e0 <__wrap___aeabi_dcmplt> +1000222c: b150 cbz r0, 10002244 <_etoa+0x394> +1000222e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002232: 9b0e ldr r3, [sp, #56] @ 0x38 +10002234: 2200 movs r2, #0 +10002236: 3b01 subs r3, #1 +10002238: 930e str r3, [sp, #56] @ 0x38 +1000223a: 4b5c ldr r3, [pc, #368] @ (100023ac <_etoa+0x4fc>) +1000223c: f7ff f9a8 bl 10001590 <__wrap___aeabi_ddiv> +10002240: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002244: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002248: 9b0e ldr r3, [sp, #56] @ 0x38 +1000224a: 4602 mov r2, r0 +1000224c: 3363 adds r3, #99 @ 0x63 +1000224e: 2bc6 cmp r3, #198 @ 0xc6 +10002250: f008 0302 and.w r3, r8, #2 +10002254: 9310 str r3, [sp, #64] @ 0x40 +10002256: 9b14 ldr r3, [sp, #80] @ 0x50 +10002258: d82d bhi.n 100022b6 <_etoa+0x406> +1000225a: 2b00 cmp r3, #0 +1000225c: d05f beq.n 1000231e <_etoa+0x46e> +1000225e: 2304 movs r3, #4 +10002260: 9312 str r3, [sp, #72] @ 0x48 +10002262: 430a orrs r2, r1 +10002264: f43f af17 beq.w 10002096 <_etoa+0x1e6> +10002268: e9dd 0108 ldrd r0, r1, [sp, #32] +1000226c: a348 add r3, pc, #288 @ (adr r3, 10002390 <_etoa+0x4e0>) +1000226e: e9d3 2300 ldrd r2, r3, [r3] +10002272: f7ff fa5d bl 10001730 <__wrap___aeabi_dcmpge> +10002276: b148 cbz r0, 1000228c <_etoa+0x3dc> +10002278: e9dd 0108 ldrd r0, r1, [sp, #32] +1000227c: a346 add r3, pc, #280 @ (adr r3, 10002398 <_etoa+0x4e8>) +1000227e: e9d3 2300 ldrd r2, r3, [r3] +10002282: f7ff fa2d bl 100016e0 <__wrap___aeabi_dcmplt> +10002286: 2800 cmp r0, #0 +10002288: f47f af05 bne.w 10002096 <_etoa+0x1e6> +1000228c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000228e: 2b00 cmp r3, #0 +10002290: d051 beq.n 10002336 <_etoa+0x486> +10002292: 9a15 ldr r2, [sp, #84] @ 0x54 +10002294: 2a00 cmp r2, #0 +10002296: f000 80ac beq.w 100023f2 <_etoa+0x542> +1000229a: 3b01 subs r3, #1 +1000229c: 930a str r3, [sp, #40] @ 0x28 +1000229e: 9b12 ldr r3, [sp, #72] @ 0x48 +100022a0: 4599 cmp r9, r3 +100022a2: d905 bls.n 100022b0 <_etoa+0x400> +100022a4: 9b10 ldr r3, [sp, #64] @ 0x40 +100022a6: 2b00 cmp r3, #0 +100022a8: f000 80af beq.w 1000240a <_etoa+0x55a> +100022ac: 2302 movs r3, #2 +100022ae: 9310 str r3, [sp, #64] @ 0x40 +100022b0: 2300 movs r3, #0 +100022b2: 9314 str r3, [sp, #80] @ 0x50 +100022b4: e044 b.n 10002340 <_etoa+0x490> +100022b6: bb2b cbnz r3, 10002304 <_etoa+0x454> +100022b8: f1b9 0f05 cmp.w r9, #5 +100022bc: d94f bls.n 1000235e <_etoa+0x4ae> +100022be: f008 0302 and.w r3, r8, #2 +100022c2: 2b00 cmp r3, #0 +100022c4: d149 bne.n 1000235a <_etoa+0x4aa> +100022c6: 2305 movs r3, #5 +100022c8: 9312 str r3, [sp, #72] @ 0x48 +100022ca: f1a9 0305 sub.w r3, r9, #5 +100022ce: 9314 str r3, [sp, #80] @ 0x50 +100022d0: e03a b.n 10002348 <_etoa+0x498> +100022d2: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000 +100022d6: f8cd a020 str.w sl, [sp, #32] +100022da: 9309 str r3, [sp, #36] @ 0x24 +100022dc: e61e b.n 10001f1c <_etoa+0x6c> +100022de: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100022e2: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100022e6: 4620 mov r0, r4 +100022e8: e9cd 792a strd r7, r9, [sp, #168] @ 0xa8 +100022ec: 932c str r3, [sp, #176] @ 0xb0 +100022ee: 4633 mov r3, r6 +100022f0: e9dd 6708 ldrd r6, r7, [sp, #32] +100022f4: 4634 mov r4, r6 +100022f6: 4629 mov r1, r5 +100022f8: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100022fc: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002300: 9a0b ldr r2, [sp, #44] @ 0x2c +10002302: e6bb b.n 1000207c <_etoa+0x1cc> +10002304: 2305 movs r3, #5 +10002306: 9312 str r3, [sp, #72] @ 0x48 +10002308: e7ab b.n 10002262 <_etoa+0x3b2> +1000230a: 2202 movs r2, #2 +1000230c: 2300 movs r3, #0 +1000230e: 9210 str r2, [sp, #64] @ 0x40 +10002310: 2204 movs r2, #4 +10002312: 9314 str r3, [sp, #80] @ 0x50 +10002314: 9212 str r2, [sp, #72] @ 0x48 +10002316: 930e str r3, [sp, #56] @ 0x38 +10002318: e623 b.n 10001f62 <_etoa+0xb2> +1000231a: 2705 movs r7, #5 +1000231c: e6c1 b.n 100020a2 <_etoa+0x1f2> +1000231e: f1b9 0f04 cmp.w r9, #4 +10002322: d91f bls.n 10002364 <_etoa+0x4b4> +10002324: 9b10 ldr r3, [sp, #64] @ 0x40 +10002326: 2b00 cmp r3, #0 +10002328: d177 bne.n 1000241a <_etoa+0x56a> +1000232a: 2304 movs r3, #4 +1000232c: 9312 str r3, [sp, #72] @ 0x48 +1000232e: f1a9 0304 sub.w r3, r9, #4 +10002332: 9314 str r3, [sp, #80] @ 0x50 +10002334: e004 b.n 10002340 <_etoa+0x490> +10002336: 9b12 ldr r3, [sp, #72] @ 0x48 +10002338: 4599 cmp r9, r3 +1000233a: d85f bhi.n 100023fc <_etoa+0x54c> +1000233c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000233e: 9314 str r3, [sp, #80] @ 0x50 +10002340: 9b0e ldr r3, [sp, #56] @ 0x38 +10002342: 2b00 cmp r3, #0 +10002344: f43f ae0d beq.w 10001f62 <_etoa+0xb2> +10002348: e9dd 0108 ldrd r0, r1, [sp, #32] +1000234c: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 +10002350: f7ff f91e bl 10001590 <__wrap___aeabi_ddiv> +10002354: e9cd 0108 strd r0, r1, [sp, #32] +10002358: e603 b.n 10001f62 <_etoa+0xb2> +1000235a: 2302 movs r3, #2 +1000235c: 9310 str r3, [sp, #64] @ 0x40 +1000235e: 2305 movs r3, #5 +10002360: 9312 str r3, [sp, #72] @ 0x48 +10002362: e7f1 b.n 10002348 <_etoa+0x498> +10002364: 2304 movs r3, #4 +10002366: 9312 str r3, [sp, #72] @ 0x48 +10002368: e7ea b.n 10002340 <_etoa+0x490> +1000236a: bf00 nop +1000236c: f3af 8000 nop.w +10002370: 636f4361 .word 0x636f4361 +10002374: 3fd287a7 .word 0x3fd287a7 +10002378: 0979a371 .word 0x0979a371 +1000237c: 400a934f .word 0x400a934f +10002380: bbb55516 .word 0xbbb55516 +10002384: 40026bb1 .word 0x40026bb1 +10002388: fefa39ef .word 0xfefa39ef +1000238c: 3fe62e42 .word 0x3fe62e42 +10002390: eb1c432d .word 0xeb1c432d +10002394: 3f1a36e2 .word 0x3f1a36e2 +10002398: 00000000 .word 0x00000000 +1000239c: 412e8480 .word 0x412e8480 +100023a0: 3ff80000 .word 0x3ff80000 +100023a4: 3fe00000 .word 0x3fe00000 +100023a8: 402c0000 .word 0x402c0000 +100023ac: 40240000 .word 0x40240000 +100023b0: 40180000 .word 0x40180000 +100023b4: 3ff00000 .word 0x3ff00000 +100023b8: 509f79fb .word 0x509f79fb +100023bc: 3fd34413 .word 0x3fd34413 +100023c0: 8b60c8b3 .word 0x8b60c8b3 +100023c4: 3fc68a28 .word 0x3fc68a28 +100023c8: 9b14 ldr r3, [sp, #80] @ 0x50 +100023ca: e9dd a708 ldrd sl, r7, [sp, #32] +100023ce: 9303 str r3, [sp, #12] +100023d0: 9b0a ldr r3, [sp, #40] @ 0x28 +100023d2: f107 4b00 add.w fp, r7, #2147483648 @ 0x80000000 +100023d6: 9302 str r3, [sp, #8] +100023d8: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100023dc: 9a0b ldr r2, [sp, #44] @ 0x2c +100023de: 9304 str r3, [sp, #16] +100023e0: 4629 mov r1, r5 +100023e2: 4633 mov r3, r6 +100023e4: 4620 mov r0, r4 +100023e6: e9cd ab00 strd sl, fp, [sp] +100023ea: f7ff fb15 bl 10001a18 <_ftoa> +100023ee: 4602 mov r2, r0 +100023f0: e5d2 b.n 10001f98 <_etoa+0xe8> +100023f2: 9b12 ldr r3, [sp, #72] @ 0x48 +100023f4: 4599 cmp r9, r3 +100023f6: d815 bhi.n 10002424 <_etoa+0x574> +100023f8: 9214 str r2, [sp, #80] @ 0x50 +100023fa: e7a1 b.n 10002340 <_etoa+0x490> +100023fc: 9b10 ldr r3, [sp, #64] @ 0x40 +100023fe: b123 cbz r3, 1000240a <_etoa+0x55a> +10002400: 9b0a ldr r3, [sp, #40] @ 0x28 +10002402: 9314 str r3, [sp, #80] @ 0x50 +10002404: 2302 movs r3, #2 +10002406: 9310 str r3, [sp, #64] @ 0x40 +10002408: e79a b.n 10002340 <_etoa+0x490> +1000240a: 9b12 ldr r3, [sp, #72] @ 0x48 +1000240c: eba9 0303 sub.w r3, r9, r3 +10002410: 9314 str r3, [sp, #80] @ 0x50 +10002412: e795 b.n 10002340 <_etoa+0x490> +10002414: 1a9b subs r3, r3, r2 +10002416: 1e5f subs r7, r3, #1 +10002418: e643 b.n 100020a2 <_etoa+0x1f2> +1000241a: 2304 movs r3, #4 +1000241c: 9312 str r3, [sp, #72] @ 0x48 +1000241e: 2302 movs r3, #2 +10002420: 9310 str r3, [sp, #64] @ 0x40 +10002422: e78d b.n 10002340 <_etoa+0x490> +10002424: 9b10 ldr r3, [sp, #64] @ 0x40 +10002426: 2b00 cmp r3, #0 +10002428: d0ef beq.n 1000240a <_etoa+0x55a> +1000242a: 2302 movs r3, #2 +1000242c: 9214 str r2, [sp, #80] @ 0x50 +1000242e: 9310 str r3, [sp, #64] @ 0x40 +10002430: e786 b.n 10002340 <_etoa+0x490> +10002432: bf00 nop + +10002434 <_vsnprintf>: +10002434: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002438: 4691 mov r9, r2 +1000243a: 4c9a ldr r4, [pc, #616] @ (100026a4 <_vsnprintf+0x270>) +1000243c: 4a9a ldr r2, [pc, #616] @ (100026a8 <_vsnprintf+0x274>) +1000243e: f1b1 0a00 subs.w sl, r1, #0 +10002442: b09b sub sp, #108 @ 0x6c +10002444: bf18 it ne +10002446: 4683 movne fp, r0 +10002448: 6014 str r4, [r2, #0] +1000244a: 7818 ldrb r0, [r3, #0] +1000244c: 4a97 ldr r2, [pc, #604] @ (100026ac <_vsnprintf+0x278>) +1000244e: f8dd 8090 ldr.w r8, [sp, #144] @ 0x90 +10002452: bf08 it eq +10002454: 4693 moveq fp, r2 +10002456: 2800 cmp r0, #0 +10002458: f000 828a beq.w 10002970 <_vsnprintf+0x53c> +1000245c: 461d mov r5, r3 +1000245e: 2600 movs r6, #0 +10002460: f8cd 9020 str.w r9, [sp, #32] +10002464: e008 b.n 10002478 <_vsnprintf+0x44> +10002466: 4632 mov r2, r6 +10002468: 4651 mov r1, sl +1000246a: 9b08 ldr r3, [sp, #32] +1000246c: 47d8 blx fp +1000246e: 3601 adds r6, #1 +10002470: 7828 ldrb r0, [r5, #0] +10002472: 2800 cmp r0, #0 +10002474: f000 80c7 beq.w 10002606 <_vsnprintf+0x1d2> +10002478: 2825 cmp r0, #37 @ 0x25 +1000247a: f105 0501 add.w r5, r5, #1 +1000247e: d1f2 bne.n 10002466 <_vsnprintf+0x32> +10002480: 2200 movs r2, #0 +10002482: 462b mov r3, r5 +10002484: f813 1b01 ldrb.w r1, [r3], #1 +10002488: f1a1 0020 sub.w r0, r1, #32 +1000248c: 2810 cmp r0, #16 +1000248e: d80a bhi.n 100024a6 <_vsnprintf+0x72> +10002490: e8df f000 tbb [pc, r0] +10002494: 3b09093f .word 0x3b09093f +10002498: 09090909 .word 0x09090909 +1000249c: 37090909 .word 0x37090909 +100024a0: 09093309 .word 0x09093309 +100024a4: 2f .byte 0x2f +100024a5: 00 .byte 0x00 +100024a6: f1a1 0030 sub.w r0, r1, #48 @ 0x30 +100024aa: 2809 cmp r0, #9 +100024ac: f240 8089 bls.w 100025c2 <_vsnprintf+0x18e> +100024b0: 292a cmp r1, #42 @ 0x2a +100024b2: f000 80e9 beq.w 10002688 <_vsnprintf+0x254> +100024b6: 2400 movs r4, #0 +100024b8: 292e cmp r1, #46 @ 0x2e +100024ba: f000 8094 beq.w 100025e6 <_vsnprintf+0x1b2> +100024be: 2700 movs r7, #0 +100024c0: f1a1 0068 sub.w r0, r1, #104 @ 0x68 +100024c4: 2812 cmp r0, #18 +100024c6: d82c bhi.n 10002522 <_vsnprintf+0xee> +100024c8: e8df f010 tbh [pc, r0, lsl #1] +100024cc: 002b014e .word 0x002b014e +100024d0: 002b0149 .word 0x002b0149 +100024d4: 002b0140 .word 0x002b0140 +100024d8: 002b002b .word 0x002b002b +100024dc: 002b002b .word 0x002b002b +100024e0: 002b002b .word 0x002b002b +100024e4: 002b0027 .word 0x002b0027 +100024e8: 002b002b .word 0x002b002b +100024ec: 002b002b .word 0x002b002b +100024f0: 0027 .short 0x0027 +100024f2: 461d mov r5, r3 +100024f4: f042 0201 orr.w r2, r2, #1 +100024f8: e7c3 b.n 10002482 <_vsnprintf+0x4e> +100024fa: 461d mov r5, r3 +100024fc: f042 0202 orr.w r2, r2, #2 +10002500: e7bf b.n 10002482 <_vsnprintf+0x4e> +10002502: 461d mov r5, r3 +10002504: f042 0204 orr.w r2, r2, #4 +10002508: e7bb b.n 10002482 <_vsnprintf+0x4e> +1000250a: 461d mov r5, r3 +1000250c: f042 0210 orr.w r2, r2, #16 +10002510: e7b7 b.n 10002482 <_vsnprintf+0x4e> +10002512: 461d mov r5, r3 +10002514: f042 0208 orr.w r2, r2, #8 +10002518: e7b3 b.n 10002482 <_vsnprintf+0x4e> +1000251a: 7869 ldrb r1, [r5, #1] +1000251c: f442 7280 orr.w r2, r2, #256 @ 0x100 +10002520: 3301 adds r3, #1 +10002522: 2967 cmp r1, #103 @ 0x67 +10002524: 461d mov r5, r3 +10002526: d87e bhi.n 10002626 <_vsnprintf+0x1f2> +10002528: 2924 cmp r1, #36 @ 0x24 +1000252a: f240 80b8 bls.w 1000269e <_vsnprintf+0x26a> +1000252e: f1a1 0325 sub.w r3, r1, #37 @ 0x25 +10002532: 2b42 cmp r3, #66 @ 0x42 +10002534: f200 80b3 bhi.w 1000269e <_vsnprintf+0x26a> +10002538: e8df f013 tbh [pc, r3, lsl #1] +1000253c: 00b10151 .word 0x00b10151 +10002540: 00b100b1 .word 0x00b100b1 +10002544: 00b100b1 .word 0x00b100b1 +10002548: 00b100b1 .word 0x00b100b1 +1000254c: 00b100b1 .word 0x00b100b1 +10002550: 00b100b1 .word 0x00b100b1 +10002554: 00b100b1 .word 0x00b100b1 +10002558: 00b100b1 .word 0x00b100b1 +1000255c: 00b100b1 .word 0x00b100b1 +10002560: 00b100b1 .word 0x00b100b1 +10002564: 00b100b1 .word 0x00b100b1 +10002568: 00b100b1 .word 0x00b100b1 +1000256c: 00b100b1 .word 0x00b100b1 +10002570: 00b100b1 .word 0x00b100b1 +10002574: 00b100b1 .word 0x00b100b1 +10002578: 00b100b1 .word 0x00b100b1 +1000257c: 013a011e .word 0x013a011e +10002580: 00b1011e .word 0x00b1011e +10002584: 00b100b1 .word 0x00b100b1 +10002588: 00b100b1 .word 0x00b100b1 +1000258c: 00b100b1 .word 0x00b100b1 +10002590: 00b100b1 .word 0x00b100b1 +10002594: 00b100b1 .word 0x00b100b1 +10002598: 00b100b1 .word 0x00b100b1 +1000259c: 00b100b1 .word 0x00b100b1 +100025a0: 01b400b1 .word 0x01b400b1 +100025a4: 00b100b1 .word 0x00b100b1 +100025a8: 00b100b1 .word 0x00b100b1 +100025ac: 00b100b1 .word 0x00b100b1 +100025b0: 00b100b1 .word 0x00b100b1 +100025b4: 01b400b1 .word 0x01b400b1 +100025b8: 01b40158 .word 0x01b40158 +100025bc: 013a011e .word 0x013a011e +100025c0: 011e .short 0x011e +100025c2: 2400 movs r4, #0 +100025c4: eb04 0484 add.w r4, r4, r4, lsl #2 +100025c8: eb01 0444 add.w r4, r1, r4, lsl #1 +100025cc: 7819 ldrb r1, [r3, #0] +100025ce: 461d mov r5, r3 +100025d0: f1a1 0030 sub.w r0, r1, #48 @ 0x30 +100025d4: 2809 cmp r0, #9 +100025d6: f1a4 0430 sub.w r4, r4, #48 @ 0x30 +100025da: f103 0301 add.w r3, r3, #1 +100025de: d9f1 bls.n 100025c4 <_vsnprintf+0x190> +100025e0: 292e cmp r1, #46 @ 0x2e +100025e2: f47f af6c bne.w 100024be <_vsnprintf+0x8a> +100025e6: 7869 ldrb r1, [r5, #1] +100025e8: 4618 mov r0, r3 +100025ea: f1a1 0730 sub.w r7, r1, #48 @ 0x30 +100025ee: 2f09 cmp r7, #9 +100025f0: f442 6280 orr.w r2, r2, #1024 @ 0x400 +100025f4: f240 8125 bls.w 10002842 <_vsnprintf+0x40e> +100025f8: 292a cmp r1, #42 @ 0x2a +100025fa: f000 8132 beq.w 10002862 <_vsnprintf+0x42e> +100025fe: 461d mov r5, r3 +10002600: 2700 movs r7, #0 +10002602: 3301 adds r3, #1 +10002604: e75c b.n 100024c0 <_vsnprintf+0x8c> +10002606: 4634 mov r4, r6 +10002608: f8dd 9020 ldr.w r9, [sp, #32] +1000260c: 45b1 cmp r9, r6 +1000260e: d801 bhi.n 10002614 <_vsnprintf+0x1e0> +10002610: f109 36ff add.w r6, r9, #4294967295 @ 0xffffffff +10002614: 464b mov r3, r9 +10002616: 4632 mov r2, r6 +10002618: 4651 mov r1, sl +1000261a: 2000 movs r0, #0 +1000261c: 47d8 blx fp +1000261e: 4620 mov r0, r4 +10002620: b01b add sp, #108 @ 0x6c +10002622: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002626: f1a1 0369 sub.w r3, r1, #105 @ 0x69 +1000262a: b2db uxtb r3, r3 +1000262c: 2b0f cmp r3, #15 +1000262e: d836 bhi.n 1000269e <_vsnprintf+0x26a> +10002630: 2001 movs r0, #1 +10002632: f249 0c41 movw ip, #36929 @ 0x9041 +10002636: 4098 lsls r0, r3 +10002638: ea10 000c ands.w r0, r0, ip +1000263c: f040 80f4 bne.w 10002828 <_vsnprintf+0x3f4> +10002640: 2b0a cmp r3, #10 +10002642: d035 beq.n 100026b0 <_vsnprintf+0x27c> +10002644: 2b07 cmp r3, #7 +10002646: d12a bne.n 1000269e <_vsnprintf+0x26a> +10002648: f858 1b04 ldr.w r1, [r8], #4 +1000264c: 2900 cmp r1, #0 +1000264e: f040 8110 bne.w 10002872 <_vsnprintf+0x43e> +10002652: f022 0410 bic.w r4, r2, #16 +10002656: f412 6180 ands.w r1, r2, #1024 @ 0x400 +1000265a: f044 0421 orr.w r4, r4, #33 @ 0x21 +1000265e: f000 810a beq.w 10002876 <_vsnprintf+0x442> +10002662: aa12 add r2, sp, #72 @ 0x48 +10002664: 2308 movs r3, #8 +10002666: 9305 str r3, [sp, #20] +10002668: 2310 movs r3, #16 +1000266a: e9cd 2000 strd r2, r0, [sp] +1000266e: 4632 mov r2, r6 +10002670: 9406 str r4, [sp, #24] +10002672: 9704 str r7, [sp, #16] +10002674: 9303 str r3, [sp, #12] +10002676: 2300 movs r3, #0 +10002678: 9302 str r3, [sp, #8] +1000267a: 4651 mov r1, sl +1000267c: 4658 mov r0, fp +1000267e: 9b08 ldr r3, [sp, #32] +10002680: f7ff f8d0 bl 10001824 <_ntoa_format> +10002684: 4606 mov r6, r0 +10002686: e6f3 b.n 10002470 <_vsnprintf+0x3c> +10002688: f858 4b04 ldr.w r4, [r8], #4 +1000268c: 7869 ldrb r1, [r5, #1] +1000268e: 2c00 cmp r4, #0 +10002690: 461d mov r5, r3 +10002692: bfbc itt lt +10002694: f042 0202 orrlt.w r2, r2, #2 +10002698: 4264 neglt r4, r4 +1000269a: 3301 adds r3, #1 +1000269c: e70c b.n 100024b8 <_vsnprintf+0x84> +1000269e: 4608 mov r0, r1 +100026a0: e6e1 b.n 10002466 <_vsnprintf+0x32> +100026a2: bf00 nop +100026a4: 10002435 .word 0x10002435 +100026a8: 20000840 .word 0x20000840 +100026ac: 10001779 .word 0x10001779 +100026b0: f858 9b04 ldr.w r9, [r8], #4 +100026b4: 2f00 cmp r7, #0 +100026b6: f899 0000 ldrb.w r0, [r9] +100026ba: bf14 ite ne +100026bc: 463b movne r3, r7 +100026be: f04f 33ff moveq.w r3, #4294967295 @ 0xffffffff +100026c2: 2800 cmp r0, #0 +100026c4: f000 8382 beq.w 10002dcc <_vsnprintf+0x998> +100026c8: 4649 mov r1, r9 +100026ca: eb03 0c09 add.w ip, r3, r9 +100026ce: e004 b.n 100026da <_vsnprintf+0x2a6> +100026d0: f811 3f01 ldrb.w r3, [r1, #1]! +100026d4: 2b00 cmp r3, #0 +100026d6: f000 8143 beq.w 10002960 <_vsnprintf+0x52c> +100026da: 458c cmp ip, r1 +100026dc: d1f8 bne.n 100026d0 <_vsnprintf+0x29c> +100026de: ebac 0109 sub.w r1, ip, r9 +100026e2: 0553 lsls r3, r2, #21 +100026e4: f140 8120 bpl.w 10002928 <_vsnprintf+0x4f4> +100026e8: 42b9 cmp r1, r7 +100026ea: bf28 it cs +100026ec: 4639 movcs r1, r7 +100026ee: f012 0302 ands.w r3, r2, #2 +100026f2: f000 8283 beq.w 10002bfc <_vsnprintf+0x7c8> +100026f6: 2302 movs r3, #2 +100026f8: e9cd 4809 strd r4, r8, [sp, #36] @ 0x24 +100026fc: 4632 mov r2, r6 +100026fe: 4688 mov r8, r1 +10002700: 9c08 ldr r4, [sp, #32] +10002702: 4437 add r7, r6 +10002704: 930b str r3, [sp, #44] @ 0x2c +10002706: e007 b.n 10002718 <_vsnprintf+0x2e4> +10002708: 4623 mov r3, r4 +1000270a: 4651 mov r1, sl +1000270c: 47d8 blx fp +1000270e: f819 0f01 ldrb.w r0, [r9, #1]! +10002712: 3601 adds r6, #1 +10002714: b110 cbz r0, 1000271c <_vsnprintf+0x2e8> +10002716: 4632 mov r2, r6 +10002718: 42b7 cmp r7, r6 +1000271a: d1f5 bne.n 10002708 <_vsnprintf+0x2d4> +1000271c: 9b0b ldr r3, [sp, #44] @ 0x2c +1000271e: 4641 mov r1, r8 +10002720: 9c09 ldr r4, [sp, #36] @ 0x24 +10002722: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +10002726: 2b00 cmp r3, #0 +10002728: f43f aea2 beq.w 10002470 <_vsnprintf+0x3c> +1000272c: 4637 mov r7, r6 +1000272e: 428c cmp r4, r1 +10002730: f67f ae9e bls.w 10002470 <_vsnprintf+0x3c> +10002734: 4426 add r6, r4 +10002736: 9c08 ldr r4, [sp, #32] +10002738: 1a76 subs r6, r6, r1 +1000273a: 463a mov r2, r7 +1000273c: 4623 mov r3, r4 +1000273e: 4651 mov r1, sl +10002740: 2020 movs r0, #32 +10002742: 3701 adds r7, #1 +10002744: 47d8 blx fp +10002746: 42b7 cmp r7, r6 +10002748: d1f7 bne.n 1000273a <_vsnprintf+0x306> +1000274a: e691 b.n 10002470 <_vsnprintf+0x3c> +1000274c: 7869 ldrb r1, [r5, #1] +1000274e: 296c cmp r1, #108 @ 0x6c +10002750: f47f aee4 bne.w 1000251c <_vsnprintf+0xe8> +10002754: 78a9 ldrb r1, [r5, #2] +10002756: f442 7240 orr.w r2, r2, #768 @ 0x300 +1000275a: 1ceb adds r3, r5, #3 +1000275c: e6e1 b.n 10002522 <_vsnprintf+0xee> +1000275e: 7869 ldrb r1, [r5, #1] +10002760: f442 7200 orr.w r2, r2, #512 @ 0x200 +10002764: 3301 adds r3, #1 +10002766: e6dc b.n 10002522 <_vsnprintf+0xee> +10002768: 7869 ldrb r1, [r5, #1] +1000276a: 2968 cmp r1, #104 @ 0x68 +1000276c: f000 80fb beq.w 10002966 <_vsnprintf+0x532> +10002770: f042 0280 orr.w r2, r2, #128 @ 0x80 +10002774: 3301 adds r3, #1 +10002776: e6d4 b.n 10002522 <_vsnprintf+0xee> +10002778: 2967 cmp r1, #103 @ 0x67 +1000277a: f000 80c9 beq.w 10002910 <_vsnprintf+0x4dc> +1000277e: 2947 cmp r1, #71 @ 0x47 +10002780: f000 80cd beq.w 1000291e <_vsnprintf+0x4ea> +10002784: 2945 cmp r1, #69 @ 0x45 +10002786: f000 80cc beq.w 10002922 <_vsnprintf+0x4ee> +1000278a: e9cd 4203 strd r4, r2, [sp, #12] +1000278e: f108 0807 add.w r8, r8, #7 +10002792: 9702 str r7, [sp, #8] +10002794: f028 0807 bic.w r8, r8, #7 +10002798: 4632 mov r2, r6 +1000279a: e8f8 6702 ldrd r6, r7, [r8], #8 +1000279e: 4651 mov r1, sl +100027a0: e9cd 6700 strd r6, r7, [sp] +100027a4: 4658 mov r0, fp +100027a6: 9b08 ldr r3, [sp, #32] +100027a8: f7ff fb82 bl 10001eb0 <_etoa> +100027ac: 4606 mov r6, r0 +100027ae: e65f b.n 10002470 <_vsnprintf+0x3c> +100027b0: 2946 cmp r1, #70 @ 0x46 +100027b2: bf08 it eq +100027b4: f042 0220 orreq.w r2, r2, #32 +100027b8: e9cd 4203 strd r4, r2, [sp, #12] +100027bc: f108 0807 add.w r8, r8, #7 +100027c0: 9702 str r7, [sp, #8] +100027c2: f028 0807 bic.w r8, r8, #7 +100027c6: 4632 mov r2, r6 +100027c8: e8f8 6702 ldrd r6, r7, [r8], #8 +100027cc: 4651 mov r1, sl +100027ce: e9cd 6700 strd r6, r7, [sp] +100027d2: 4658 mov r0, fp +100027d4: 9b08 ldr r3, [sp, #32] +100027d6: f7ff f91f bl 10001a18 <_ftoa> +100027da: 4606 mov r6, r0 +100027dc: e648 b.n 10002470 <_vsnprintf+0x3c> +100027de: 4632 mov r2, r6 +100027e0: 4651 mov r1, sl +100027e2: 2025 movs r0, #37 @ 0x25 +100027e4: 9b08 ldr r3, [sp, #32] +100027e6: 47d8 blx fp +100027e8: 3601 adds r6, #1 +100027ea: e641 b.n 10002470 <_vsnprintf+0x3c> +100027ec: f108 0304 add.w r3, r8, #4 +100027f0: 0792 lsls r2, r2, #30 +100027f2: 9309 str r3, [sp, #36] @ 0x24 +100027f4: f106 0701 add.w r7, r6, #1 +100027f8: f140 80c3 bpl.w 10002982 <_vsnprintf+0x54e> +100027fc: 4632 mov r2, r6 +100027fe: 4651 mov r1, sl +10002800: f898 0000 ldrb.w r0, [r8] +10002804: 9b08 ldr r3, [sp, #32] +10002806: 47d8 blx fp +10002808: 2c01 cmp r4, #1 +1000280a: f240 81b4 bls.w 10002b76 <_vsnprintf+0x742> +1000280e: 4426 add r6, r4 +10002810: 9c08 ldr r4, [sp, #32] +10002812: 463a mov r2, r7 +10002814: 4623 mov r3, r4 +10002816: 4651 mov r1, sl +10002818: 2020 movs r0, #32 +1000281a: 3701 adds r7, #1 +1000281c: 47d8 blx fp +1000281e: 42b7 cmp r7, r6 +10002820: d1f7 bne.n 10002812 <_vsnprintf+0x3de> +10002822: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10002826: e623 b.n 10002470 <_vsnprintf+0x3c> +10002828: 296f cmp r1, #111 @ 0x6f +1000282a: d074 beq.n 10002916 <_vsnprintf+0x4e2> +1000282c: f240 8241 bls.w 10002cb2 <_vsnprintf+0x87e> +10002830: 2978 cmp r1, #120 @ 0x78 +10002832: f000 8186 beq.w 10002b42 <_vsnprintf+0x70e> +10002836: f04f 090a mov.w r9, #10 +1000283a: f022 0210 bic.w r2, r2, #16 +1000283e: 464b mov r3, r9 +10002840: e038 b.n 100028b4 <_vsnprintf+0x480> +10002842: 2700 movs r7, #0 +10002844: eb07 0787 add.w r7, r7, r7, lsl #2 +10002848: eb01 0147 add.w r1, r1, r7, lsl #1 +1000284c: f1a1 0730 sub.w r7, r1, #48 @ 0x30 +10002850: f810 1f01 ldrb.w r1, [r0, #1]! +10002854: f1a1 0330 sub.w r3, r1, #48 @ 0x30 +10002858: 2b09 cmp r3, #9 +1000285a: d9f3 bls.n 10002844 <_vsnprintf+0x410> +1000285c: 4605 mov r5, r0 +1000285e: 1c43 adds r3, r0, #1 +10002860: e62e b.n 100024c0 <_vsnprintf+0x8c> +10002862: f858 7b04 ldr.w r7, [r8], #4 +10002866: 78a9 ldrb r1, [r5, #2] +10002868: 3502 adds r5, #2 +1000286a: 1c6b adds r3, r5, #1 +1000286c: ea27 77e7 bic.w r7, r7, r7, asr #31 +10002870: e626 b.n 100024c0 <_vsnprintf+0x8c> +10002872: f042 0421 orr.w r4, r2, #33 @ 0x21 +10002876: aa12 add r2, sp, #72 @ 0x48 +10002878: 4694 mov ip, r2 +1000287a: e002 b.n 10002882 <_vsnprintf+0x44e> +1000287c: 2820 cmp r0, #32 +1000287e: f43f aef1 beq.w 10002664 <_vsnprintf+0x230> +10002882: f001 030f and.w r3, r1, #15 +10002886: 2b09 cmp r3, #9 +10002888: bf94 ite ls +1000288a: 3330 addls r3, #48 @ 0x30 +1000288c: 3337 addhi r3, #55 @ 0x37 +1000288e: 290f cmp r1, #15 +10002890: f88c 3000 strb.w r3, [ip] +10002894: f100 0001 add.w r0, r0, #1 +10002898: f10c 0c01 add.w ip, ip, #1 +1000289c: ea4f 1111 mov.w r1, r1, lsr #4 +100028a0: d8ec bhi.n 1000287c <_vsnprintf+0x448> +100028a2: e6df b.n 10002664 <_vsnprintf+0x230> +100028a4: 2958 cmp r1, #88 @ 0x58 +100028a6: d066 beq.n 10002976 <_vsnprintf+0x542> +100028a8: 2962 cmp r1, #98 @ 0x62 +100028aa: f040 8089 bne.w 100029c0 <_vsnprintf+0x58c> +100028ae: f04f 0902 mov.w r9, #2 +100028b2: 464b mov r3, r9 +100028b4: f412 6c80 ands.w ip, r2, #1024 @ 0x400 +100028b8: f000 80d4 beq.w 10002a64 <_vsnprintf+0x630> +100028bc: f022 020d bic.w r2, r2, #13 +100028c0: 9209 str r2, [sp, #36] @ 0x24 +100028c2: f412 7100 ands.w r1, r2, #512 @ 0x200 +100028c6: f040 817b bne.w 10002bc0 <_vsnprintf+0x78c> +100028ca: f412 7080 ands.w r0, r2, #256 @ 0x100 +100028ce: f108 0904 add.w r9, r8, #4 +100028d2: f040 8238 bne.w 10002d46 <_vsnprintf+0x912> +100028d6: 0651 lsls r1, r2, #25 +100028d8: f140 813a bpl.w 10002b50 <_vsnprintf+0x71c> +100028dc: f898 1000 ldrb.w r1, [r8] +100028e0: 2900 cmp r1, #0 +100028e2: f040 814a bne.w 10002b7a <_vsnprintf+0x746> +100028e6: 9a09 ldr r2, [sp, #36] @ 0x24 +100028e8: f022 0210 bic.w r2, r2, #16 +100028ec: 9209 str r2, [sp, #36] @ 0x24 +100028ee: f1bc 0f00 cmp.w ip, #0 +100028f2: f000 8142 beq.w 10002b7a <_vsnprintf+0x746> +100028f6: 4608 mov r0, r1 +100028f8: aa12 add r2, sp, #72 @ 0x48 +100028fa: 9909 ldr r1, [sp, #36] @ 0x24 +100028fc: e9cd 3703 strd r3, r7, [sp, #12] +10002900: e9cd 4105 strd r4, r1, [sp, #20] +10002904: 9001 str r0, [sp, #4] +10002906: 2300 movs r3, #0 +10002908: 9200 str r2, [sp, #0] +1000290a: 9302 str r3, [sp, #8] +1000290c: 4632 mov r2, r6 +1000290e: e0a1 b.n 10002a54 <_vsnprintf+0x620> +10002910: f442 6200 orr.w r2, r2, #2048 @ 0x800 +10002914: e739 b.n 1000278a <_vsnprintf+0x356> +10002916: f04f 0908 mov.w r9, #8 +1000291a: 464b mov r3, r9 +1000291c: e7ca b.n 100028b4 <_vsnprintf+0x480> +1000291e: f442 6200 orr.w r2, r2, #2048 @ 0x800 +10002922: f042 0220 orr.w r2, r2, #32 +10002926: e730 b.n 1000278a <_vsnprintf+0x356> +10002928: f012 0302 ands.w r3, r2, #2 +1000292c: f000 818c beq.w 10002c48 <_vsnprintf+0x814> +10002930: 2302 movs r3, #2 +10002932: e9cd 4809 strd r4, r8, [sp, #36] @ 0x24 +10002936: 461f mov r7, r3 +10002938: 4688 mov r8, r1 +1000293a: 9c08 ldr r4, [sp, #32] +1000293c: 4632 mov r2, r6 +1000293e: 4623 mov r3, r4 +10002940: 4651 mov r1, sl +10002942: 47d8 blx fp +10002944: f819 0f01 ldrb.w r0, [r9, #1]! +10002948: 3601 adds r6, #1 +1000294a: 2800 cmp r0, #0 +1000294c: d1f6 bne.n 1000293c <_vsnprintf+0x508> +1000294e: 463b mov r3, r7 +10002950: 4641 mov r1, r8 +10002952: 9c09 ldr r4, [sp, #36] @ 0x24 +10002954: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +10002958: 2b00 cmp r3, #0 +1000295a: f43f ad89 beq.w 10002470 <_vsnprintf+0x3c> +1000295e: e6e5 b.n 1000272c <_vsnprintf+0x2f8> +10002960: eba1 0109 sub.w r1, r1, r9 +10002964: e6bd b.n 100026e2 <_vsnprintf+0x2ae> +10002966: 78a9 ldrb r1, [r5, #2] +10002968: f042 02c0 orr.w r2, r2, #192 @ 0xc0 +1000296c: 1ceb adds r3, r5, #3 +1000296e: e5d8 b.n 10002522 <_vsnprintf+0xee> +10002970: 4604 mov r4, r0 +10002972: 4606 mov r6, r0 +10002974: e64a b.n 1000260c <_vsnprintf+0x1d8> +10002976: f04f 0910 mov.w r9, #16 +1000297a: f042 0220 orr.w r2, r2, #32 +1000297e: 464b mov r3, r9 +10002980: e798 b.n 100028b4 <_vsnprintf+0x480> +10002982: 2c01 cmp r4, #1 +10002984: f240 80f1 bls.w 10002b6a <_vsnprintf+0x736> +10002988: 4637 mov r7, r6 +1000298a: f106 39ff add.w r9, r6, #4294967295 @ 0xffffffff +1000298e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10002992: f8dd 8020 ldr.w r8, [sp, #32] +10002996: 44a1 add r9, r4 +10002998: 463a mov r2, r7 +1000299a: 4643 mov r3, r8 +1000299c: 4651 mov r1, sl +1000299e: 2020 movs r0, #32 +100029a0: 3701 adds r7, #1 +100029a2: 47d8 blx fp +100029a4: 454f cmp r7, r9 +100029a6: d1f7 bne.n 10002998 <_vsnprintf+0x564> +100029a8: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +100029ac: 463a mov r2, r7 +100029ae: f898 0000 ldrb.w r0, [r8] +100029b2: 4651 mov r1, sl +100029b4: 9b08 ldr r3, [sp, #32] +100029b6: 47d8 blx fp +100029b8: 4426 add r6, r4 +100029ba: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +100029be: e557 b.n 10002470 <_vsnprintf+0x3c> +100029c0: f412 6380 ands.w r3, r2, #1024 @ 0x400 +100029c4: f000 80c1 beq.w 10002b4a <_vsnprintf+0x716> +100029c8: f44f 6380 mov.w r3, #1024 @ 0x400 +100029cc: f022 0011 bic.w r0, r2, #17 +100029d0: f410 7e00 ands.w lr, r0, #512 @ 0x200 +100029d4: d14a bne.n 10002a6c <_vsnprintf+0x638> +100029d6: f410 7c80 ands.w ip, r0, #256 @ 0x100 +100029da: f108 0904 add.w r9, r8, #4 +100029de: f040 8137 bne.w 10002c50 <_vsnprintf+0x81c> +100029e2: 0641 lsls r1, r0, #25 +100029e4: f100 80a9 bmi.w 10002b3a <_vsnprintf+0x706> +100029e8: 0602 lsls r2, r0, #24 +100029ea: f140 81e3 bpl.w 10002db4 <_vsnprintf+0x980> +100029ee: f9b8 2000 ldrsh.w r2, [r8] +100029f2: ea82 71e2 eor.w r1, r2, r2, asr #31 +100029f6: eba1 71e2 sub.w r1, r1, r2, asr #31 +100029fa: fa1f fe81 uxth.w lr, r1 +100029fe: 0fd1 lsrs r1, r2, #31 +10002a00: 9109 str r1, [sp, #36] @ 0x24 +10002a02: 2a00 cmp r2, #0 +10002a04: f000 815f beq.w 10002cc6 <_vsnprintf+0x892> +10002a08: 4673 mov r3, lr +10002a0a: aa12 add r2, sp, #72 @ 0x48 +10002a0c: 4696 mov lr, r2 +10002a0e: f8df 83a0 ldr.w r8, [pc, #928] @ 10002db0 <_vsnprintf+0x97c> +10002a12: 940a str r4, [sp, #40] @ 0x28 +10002a14: e003 b.n 10002a1e <_vsnprintf+0x5ea> +10002a16: f1bc 0f20 cmp.w ip, #32 +10002a1a: 4623 mov r3, r4 +10002a1c: d00f beq.n 10002a3e <_vsnprintf+0x60a> +10002a1e: fba8 1403 umull r1, r4, r8, r3 +10002a22: 08e4 lsrs r4, r4, #3 +10002a24: eb04 0184 add.w r1, r4, r4, lsl #2 +10002a28: eba3 0141 sub.w r1, r3, r1, lsl #1 +10002a2c: f10e 0e01 add.w lr, lr, #1 +10002a30: 3130 adds r1, #48 @ 0x30 +10002a32: 2b09 cmp r3, #9 +10002a34: f10c 0c01 add.w ip, ip, #1 +10002a38: f80e 1c01 strb.w r1, [lr, #-1] +10002a3c: d8eb bhi.n 10002a16 <_vsnprintf+0x5e2> +10002a3e: 9c0a ldr r4, [sp, #40] @ 0x28 +10002a40: 9b09 ldr r3, [sp, #36] @ 0x24 +10002a42: 9200 str r2, [sp, #0] +10002a44: e9cd c301 strd ip, r3, [sp, #4] +10002a48: 230a movs r3, #10 +10002a4a: 4632 mov r2, r6 +10002a4c: e9cd 4005 strd r4, r0, [sp, #20] +10002a50: 9704 str r7, [sp, #16] +10002a52: 9303 str r3, [sp, #12] +10002a54: 4651 mov r1, sl +10002a56: 4658 mov r0, fp +10002a58: 9b08 ldr r3, [sp, #32] +10002a5a: f7fe fee3 bl 10001824 <_ntoa_format> +10002a5e: 46c8 mov r8, r9 +10002a60: 4606 mov r6, r0 +10002a62: e505 b.n 10002470 <_vsnprintf+0x3c> +10002a64: f022 020c bic.w r2, r2, #12 +10002a68: 9209 str r2, [sp, #36] @ 0x24 +10002a6a: e72a b.n 100028c2 <_vsnprintf+0x48e> +10002a6c: f108 0807 add.w r8, r8, #7 +10002a70: f028 0807 bic.w r8, r8, #7 +10002a74: f8d8 2004 ldr.w r2, [r8, #4] +10002a78: f858 cb08 ldr.w ip, [r8], #8 +10002a7c: 0fd1 lsrs r1, r2, #31 +10002a7e: ea5c 0e02 orrs.w lr, ip, r2 +10002a82: d06c beq.n 10002b5e <_vsnprintf+0x72a> +10002a84: 2a00 cmp r2, #0 +10002a86: 4663 mov r3, ip +10002a88: da02 bge.n 10002a90 <_vsnprintf+0x65c> +10002a8a: 425b negs r3, r3 +10002a8c: eb62 0242 sbc.w r2, r2, r2, lsl #1 +10002a90: 4691 mov r9, r2 +10002a92: 9309 str r3, [sp, #36] @ 0x24 +10002a94: aa12 add r2, sp, #72 @ 0x48 +10002a96: 4694 mov ip, r2 +10002a98: f04f 0e00 mov.w lr, #0 +10002a9c: e9cd 180a strd r1, r8, [sp, #40] @ 0x28 +10002aa0: e9cd 470c strd r4, r7, [sp, #48] @ 0x30 +10002aa4: 960e str r6, [sp, #56] @ 0x38 +10002aa6: 920f str r2, [sp, #60] @ 0x3c +10002aa8: e003 b.n 10002ab2 <_vsnprintf+0x67e> +10002aaa: f1be 0f20 cmp.w lr, #32 +10002aae: 463b mov r3, r7 +10002ab0: d030 beq.n 10002b14 <_vsnprintf+0x6e0> +10002ab2: f04f 32cc mov.w r2, #3435973836 @ 0xcccccccc +10002ab6: eb13 0109 adds.w r1, r3, r9 +10002aba: 4fbd ldr r7, [pc, #756] @ (10002db0 <_vsnprintf+0x97c>) +10002abc: f141 0100 adc.w r1, r1, #0 +10002ac0: fba7 4601 umull r4, r6, r7, r1 +10002ac4: f026 0403 bic.w r4, r6, #3 +10002ac8: eb04 0496 add.w r4, r4, r6, lsr #2 +10002acc: 1b09 subs r1, r1, r4 +10002ace: 1a5c subs r4, r3, r1 +10002ad0: fb02 f604 mul.w r6, r2, r4 +10002ad4: 463a mov r2, r7 +10002ad6: f169 0800 sbc.w r8, r9, #0 +10002ada: fb02 6608 mla r6, r2, r8, r6 +10002ade: 2205 movs r2, #5 +10002ae0: fba4 7407 umull r7, r4, r4, r7 +10002ae4: f007 0801 and.w r8, r7, #1 +10002ae8: 4426 add r6, r4 +10002aea: fba8 4802 umull r4, r8, r8, r2 +10002aee: 1864 adds r4, r4, r1 +10002af0: 2b0a cmp r3, #10 +10002af2: f10c 0c01 add.w ip, ip, #1 +10002af6: ea4f 0757 mov.w r7, r7, lsr #1 +10002afa: f104 0430 add.w r4, r4, #48 @ 0x30 +10002afe: f179 0900 sbcs.w r9, r9, #0 +10002b02: f10e 0e01 add.w lr, lr, #1 +10002b06: f80c 4c01 strb.w r4, [ip, #-1] +10002b0a: ea47 77c6 orr.w r7, r7, r6, lsl #31 +10002b0e: ea4f 0956 mov.w r9, r6, lsr #1 +10002b12: d2ca bcs.n 10002aaa <_vsnprintf+0x676> +10002b14: 4673 mov r3, lr +10002b16: e9dd 180a ldrd r1, r8, [sp, #40] @ 0x28 +10002b1a: e9dd 470c ldrd r4, r7, [sp, #48] @ 0x30 +10002b1e: 9e0e ldr r6, [sp, #56] @ 0x38 +10002b20: 9a0f ldr r2, [sp, #60] @ 0x3c +10002b22: f8cd e024 str.w lr, [sp, #36] @ 0x24 +10002b26: e9cd 3101 strd r3, r1, [sp, #4] +10002b2a: 230a movs r3, #10 +10002b2c: 9200 str r2, [sp, #0] +10002b2e: e9cd 4005 strd r4, r0, [sp, #20] +10002b32: 4632 mov r2, r6 +10002b34: 9704 str r7, [sp, #16] +10002b36: 9303 str r3, [sp, #12] +10002b38: e59f b.n 1000267a <_vsnprintf+0x246> +10002b3a: f898 2000 ldrb.w r2, [r8] +10002b3e: 4696 mov lr, r2 +10002b40: e75d b.n 100029fe <_vsnprintf+0x5ca> +10002b42: f04f 0910 mov.w r9, #16 +10002b46: 464b mov r3, r9 +10002b48: e6b4 b.n 100028b4 <_vsnprintf+0x480> +10002b4a: f022 0010 bic.w r0, r2, #16 +10002b4e: e73f b.n 100029d0 <_vsnprintf+0x59c> +10002b50: 0611 lsls r1, r2, #24 +10002b52: bf4c ite mi +10002b54: f8b8 1000 ldrhmi.w r1, [r8] +10002b58: f8d8 1000 ldrpl.w r1, [r8] +10002b5c: e6c0 b.n 100028e0 <_vsnprintf+0x4ac> +10002b5e: 2b00 cmp r3, #0 +10002b60: f040 8142 bne.w 10002de8 <_vsnprintf+0x9b4> +10002b64: 4699 mov r9, r3 +10002b66: 9309 str r3, [sp, #36] @ 0x24 +10002b68: e794 b.n 10002a94 <_vsnprintf+0x660> +10002b6a: 4632 mov r2, r6 +10002b6c: 4651 mov r1, sl +10002b6e: f898 0000 ldrb.w r0, [r8] +10002b72: 9b08 ldr r3, [sp, #32] +10002b74: 47d8 blx fp +10002b76: 463e mov r6, r7 +10002b78: e653 b.n 10002822 <_vsnprintf+0x3ee> +10002b7a: 9a09 ldr r2, [sp, #36] @ 0x24 +10002b7c: 940a str r4, [sp, #40] @ 0x28 +10002b7e: f012 0f20 tst.w r2, #32 +10002b82: bf14 ite ne +10002b84: f04f 0841 movne.w r8, #65 @ 0x41 +10002b88: f04f 0861 moveq.w r8, #97 @ 0x61 +10002b8c: aa12 add r2, sp, #72 @ 0x48 +10002b8e: 4694 mov ip, r2 +10002b90: f1a8 080a sub.w r8, r8, #10 +10002b94: e002 b.n 10002b9c <_vsnprintf+0x768> +10002b96: 2820 cmp r0, #32 +10002b98: 4671 mov r1, lr +10002b9a: d00f beq.n 10002bbc <_vsnprintf+0x788> +10002b9c: fbb1 fef3 udiv lr, r1, r3 +10002ba0: fb03 141e mls r4, r3, lr, r1 +10002ba4: 2c09 cmp r4, #9 +10002ba6: bf94 ite ls +10002ba8: 3430 addls r4, #48 @ 0x30 +10002baa: 4444 addhi r4, r8 +10002bac: 4299 cmp r1, r3 +10002bae: f88c 4000 strb.w r4, [ip] +10002bb2: f100 0001 add.w r0, r0, #1 +10002bb6: f10c 0c01 add.w ip, ip, #1 +10002bba: d2ec bcs.n 10002b96 <_vsnprintf+0x762> +10002bbc: 9c0a ldr r4, [sp, #40] @ 0x28 +10002bbe: e69c b.n 100028fa <_vsnprintf+0x4c6> +10002bc0: f108 0807 add.w r8, r8, #7 +10002bc4: f028 0807 bic.w r8, r8, #7 +10002bc8: f8d8 2004 ldr.w r2, [r8, #4] +10002bcc: f858 1b08 ldr.w r1, [r8], #8 +10002bd0: 920a str r2, [sp, #40] @ 0x28 +10002bd2: 430a orrs r2, r1 +10002bd4: 468e mov lr, r1 +10002bd6: d17b bne.n 10002cd0 <_vsnprintf+0x89c> +10002bd8: 9a09 ldr r2, [sp, #36] @ 0x24 +10002bda: f022 0210 bic.w r2, r2, #16 +10002bde: 9209 str r2, [sp, #36] @ 0x24 +10002be0: f1bc 0f00 cmp.w ip, #0 +10002be4: d074 beq.n 10002cd0 <_vsnprintf+0x89c> +10002be6: 2000 movs r0, #0 +10002be8: aa12 add r2, sp, #72 @ 0x48 +10002bea: 9909 ldr r1, [sp, #36] @ 0x24 +10002bec: e9cd 2000 strd r2, r0, [sp] +10002bf0: e9cd 4105 strd r4, r1, [sp, #20] +10002bf4: 4632 mov r2, r6 +10002bf6: e9cd 3703 strd r3, r7, [sp, #12] +10002bfa: e53c b.n 10002676 <_vsnprintf+0x242> +10002bfc: 428c cmp r4, r1 +10002bfe: bf98 it ls +10002c00: 3101 addls r1, #1 +10002c02: f67f ad79 bls.w 100026f8 <_vsnprintf+0x2c4> +10002c06: f44f 6380 mov.w r3, #1024 @ 0x400 +10002c0a: e9cd 9409 strd r9, r4, [sp, #36] @ 0x24 +10002c0e: 4699 mov r9, r3 +10002c10: 19a2 adds r2, r4, r6 +10002c12: 970b str r7, [sp, #44] @ 0x2c +10002c14: 9f08 ldr r7, [sp, #32] +10002c16: 1a54 subs r4, r2, r1 +10002c18: 4632 mov r2, r6 +10002c1a: 463b mov r3, r7 +10002c1c: 4651 mov r1, sl +10002c1e: 2020 movs r0, #32 +10002c20: 3601 adds r6, #1 +10002c22: 47d8 blx fp +10002c24: 42a6 cmp r6, r4 +10002c26: d1f7 bne.n 10002c18 <_vsnprintf+0x7e4> +10002c28: e9dd 470a ldrd r4, r7, [sp, #40] @ 0x28 +10002c2c: 464b mov r3, r9 +10002c2e: f8dd 9024 ldr.w r9, [sp, #36] @ 0x24 +10002c32: f899 0000 ldrb.w r0, [r9] +10002c36: 2800 cmp r0, #0 +10002c38: f43f ac1a beq.w 10002470 <_vsnprintf+0x3c> +10002c3c: 1c61 adds r1, r4, #1 +10002c3e: 2b00 cmp r3, #0 +10002c40: f43f ae77 beq.w 10002932 <_vsnprintf+0x4fe> +10002c44: 2300 movs r3, #0 +10002c46: e557 b.n 100026f8 <_vsnprintf+0x2c4> +10002c48: 428c cmp r4, r1 +10002c4a: d8de bhi.n 10002c0a <_vsnprintf+0x7d6> +10002c4c: 3101 adds r1, #1 +10002c4e: e670 b.n 10002932 <_vsnprintf+0x4fe> +10002c50: f8d8 2000 ldr.w r2, [r8] +10002c54: 0fd1 lsrs r1, r2, #31 +10002c56: 2a00 cmp r2, #0 +10002c58: f000 80b3 beq.w 10002dc2 <_vsnprintf+0x98e> +10002c5c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10002c60: eba3 73e2 sub.w r3, r3, r2, asr #31 +10002c64: aa12 add r2, sp, #72 @ 0x48 +10002c66: 4694 mov ip, r2 +10002c68: e9cd 1409 strd r1, r4, [sp, #36] @ 0x24 +10002c6c: f8df 8140 ldr.w r8, [pc, #320] @ 10002db0 <_vsnprintf+0x97c> +10002c70: e003 b.n 10002c7a <_vsnprintf+0x846> +10002c72: f1be 0f20 cmp.w lr, #32 +10002c76: 4623 mov r3, r4 +10002c78: d00f beq.n 10002c9a <_vsnprintf+0x866> +10002c7a: fba8 1403 umull r1, r4, r8, r3 +10002c7e: 08e4 lsrs r4, r4, #3 +10002c80: eb04 0184 add.w r1, r4, r4, lsl #2 +10002c84: eba3 0141 sub.w r1, r3, r1, lsl #1 +10002c88: f10c 0c01 add.w ip, ip, #1 +10002c8c: 3130 adds r1, #48 @ 0x30 +10002c8e: 2b09 cmp r3, #9 +10002c90: f10e 0e01 add.w lr, lr, #1 +10002c94: f80c 1c01 strb.w r1, [ip, #-1] +10002c98: d8eb bhi.n 10002c72 <_vsnprintf+0x83e> +10002c9a: e9dd 1409 ldrd r1, r4, [sp, #36] @ 0x24 +10002c9e: 230a movs r3, #10 +10002ca0: 9200 str r2, [sp, #0] +10002ca2: e9cd 4005 strd r4, r0, [sp, #20] +10002ca6: 4632 mov r2, r6 +10002ca8: e9cd e101 strd lr, r1, [sp, #4] +10002cac: 9704 str r7, [sp, #16] +10002cae: 9303 str r3, [sp, #12] +10002cb0: e6d0 b.n 10002a54 <_vsnprintf+0x620> +10002cb2: 2969 cmp r1, #105 @ 0x69 +10002cb4: f022 0010 bic.w r0, r2, #16 +10002cb8: f040 8091 bne.w 10002dde <_vsnprintf+0x9aa> +10002cbc: f412 6380 ands.w r3, r2, #1024 @ 0x400 +10002cc0: f43f ae86 beq.w 100029d0 <_vsnprintf+0x59c> +10002cc4: e680 b.n 100029c8 <_vsnprintf+0x594> +10002cc6: 2b00 cmp r3, #0 +10002cc8: f43f ae9f beq.w 10002a0a <_vsnprintf+0x5d6> +10002ccc: aa12 add r2, sp, #72 @ 0x48 +10002cce: e6b7 b.n 10002a40 <_vsnprintf+0x60c> +10002cd0: 9a09 ldr r2, [sp, #36] @ 0x24 +10002cd2: e9cd 840b strd r8, r4, [sp, #44] @ 0x2c +10002cd6: f012 0f20 tst.w r2, #32 +10002cda: bf14 ite ne +10002cdc: 2141 movne r1, #65 @ 0x41 +10002cde: 2161 moveq r1, #97 @ 0x61 +10002ce0: e9cd 760d strd r7, r6, [sp, #52] @ 0x34 +10002ce4: e9cd 3b0f strd r3, fp, [sp, #60] @ 0x3c +10002ce8: f8cd a044 str.w sl, [sp, #68] @ 0x44 +10002cec: 2700 movs r7, #0 +10002cee: 46f0 mov r8, lr +10002cf0: 9c0a ldr r4, [sp, #40] @ 0x28 +10002cf2: ae12 add r6, sp, #72 @ 0x48 +10002cf4: f10d 0b48 add.w fp, sp, #72 @ 0x48 +10002cf8: f1a1 0a0a sub.w sl, r1, #10 +10002cfc: e003 b.n 10002d06 <_vsnprintf+0x8d2> +10002cfe: 2f20 cmp r7, #32 +10002d00: 4680 mov r8, r0 +10002d02: 460c mov r4, r1 +10002d04: d013 beq.n 10002d2e <_vsnprintf+0x8fa> +10002d06: 4621 mov r1, r4 +10002d08: 464a mov r2, r9 +10002d0a: 2300 movs r3, #0 +10002d0c: 4640 mov r0, r8 +10002d0e: f000 fc5f bl 100035d0 <____aeabi_uldivmod_veneer> +10002d12: b2d2 uxtb r2, r2 +10002d14: 2a09 cmp r2, #9 +10002d16: bf94 ite ls +10002d18: 3230 addls r2, #48 @ 0x30 +10002d1a: 4452 addhi r2, sl +10002d1c: 45c8 cmp r8, r9 +10002d1e: f174 0400 sbcs.w r4, r4, #0 +10002d22: 7032 strb r2, [r6, #0] +10002d24: f107 0701 add.w r7, r7, #1 +10002d28: f106 0601 add.w r6, r6, #1 +10002d2c: d2e7 bcs.n 10002cfe <_vsnprintf+0x8ca> +10002d2e: 4638 mov r0, r7 +10002d30: e9dd 840b ldrd r8, r4, [sp, #44] @ 0x2c +10002d34: 465a mov r2, fp +10002d36: 9e0e ldr r6, [sp, #56] @ 0x38 +10002d38: 9f0d ldr r7, [sp, #52] @ 0x34 +10002d3a: 9b0f ldr r3, [sp, #60] @ 0x3c +10002d3c: f8dd a044 ldr.w sl, [sp, #68] @ 0x44 +10002d40: f8dd b040 ldr.w fp, [sp, #64] @ 0x40 +10002d44: e751 b.n 10002bea <_vsnprintf+0x7b6> +10002d46: f8d8 e000 ldr.w lr, [r8] +10002d4a: f1be 0f00 cmp.w lr, #0 +10002d4e: d10d bne.n 10002d6c <_vsnprintf+0x938> +10002d50: f022 0210 bic.w r2, r2, #16 +10002d54: 9209 str r2, [sp, #36] @ 0x24 +10002d56: f1bc 0f00 cmp.w ip, #0 +10002d5a: d007 beq.n 10002d6c <_vsnprintf+0x938> +10002d5c: aa12 add r2, sp, #72 @ 0x48 +10002d5e: 9809 ldr r0, [sp, #36] @ 0x24 +10002d60: e9cd 3703 strd r3, r7, [sp, #12] +10002d64: e9cd 4005 strd r4, r0, [sp, #20] +10002d68: 9101 str r1, [sp, #4] +10002d6a: e5cc b.n 10002906 <_vsnprintf+0x4d2> +10002d6c: 9a09 ldr r2, [sp, #36] @ 0x24 +10002d6e: f012 0f20 tst.w r2, #32 +10002d72: bf14 ite ne +10002d74: 2041 movne r0, #65 @ 0x41 +10002d76: 2061 moveq r0, #97 @ 0x61 +10002d78: aa12 add r2, sp, #72 @ 0x48 +10002d7a: 4694 mov ip, r2 +10002d7c: 920a str r2, [sp, #40] @ 0x28 +10002d7e: f1a0 020a sub.w r2, r0, #10 +10002d82: e002 b.n 10002d8a <_vsnprintf+0x956> +10002d84: 2920 cmp r1, #32 +10002d86: 46c6 mov lr, r8 +10002d88: d00f beq.n 10002daa <_vsnprintf+0x976> +10002d8a: fbbe f8f3 udiv r8, lr, r3 +10002d8e: fb03 e018 mls r0, r3, r8, lr +10002d92: 2809 cmp r0, #9 +10002d94: bf94 ite ls +10002d96: 3030 addls r0, #48 @ 0x30 +10002d98: 1880 addhi r0, r0, r2 +10002d9a: 459e cmp lr, r3 +10002d9c: f88c 0000 strb.w r0, [ip] +10002da0: f101 0101 add.w r1, r1, #1 +10002da4: f10c 0c01 add.w ip, ip, #1 +10002da8: d2ec bcs.n 10002d84 <_vsnprintf+0x950> +10002daa: 9a0a ldr r2, [sp, #40] @ 0x28 +10002dac: e7d7 b.n 10002d5e <_vsnprintf+0x92a> +10002dae: bf00 nop +10002db0: cccccccd .word 0xcccccccd +10002db4: f8d8 2000 ldr.w r2, [r8] +10002db8: ea82 7ee2 eor.w lr, r2, r2, asr #31 +10002dbc: ebae 7ee2 sub.w lr, lr, r2, asr #31 +10002dc0: e61d b.n 100029fe <_vsnprintf+0x5ca> +10002dc2: 2b00 cmp r3, #0 +10002dc4: f43f af4e beq.w 10002c64 <_vsnprintf+0x830> +10002dc8: aa12 add r2, sp, #72 @ 0x48 +10002dca: e768 b.n 10002c9e <_vsnprintf+0x86a> +10002dcc: f412 6180 ands.w r1, r2, #1024 @ 0x400 +10002dd0: d00e beq.n 10002df0 <_vsnprintf+0x9bc> +10002dd2: f012 0102 ands.w r1, r2, #2 +10002dd6: d014 beq.n 10002e02 <_vsnprintf+0x9ce> +10002dd8: 4601 mov r1, r0 +10002dda: 4637 mov r7, r6 +10002ddc: e4a7 b.n 1000272e <_vsnprintf+0x2fa> +10002dde: f04f 090a mov.w r9, #10 +10002de2: 4602 mov r2, r0 +10002de4: 464b mov r3, r9 +10002de6: e565 b.n 100028b4 <_vsnprintf+0x480> +10002de8: 2300 movs r3, #0 +10002dea: aa12 add r2, sp, #72 @ 0x48 +10002dec: 9309 str r3, [sp, #36] @ 0x24 +10002dee: e69a b.n 10002b26 <_vsnprintf+0x6f2> +10002df0: f012 0302 ands.w r3, r2, #2 +10002df4: f47f ac9a bne.w 1000272c <_vsnprintf+0x2f8> +10002df8: 2c00 cmp r4, #0 +10002dfa: f47f af06 bne.w 10002c0a <_vsnprintf+0x7d6> +10002dfe: f7ff bb37 b.w 10002470 <_vsnprintf+0x3c> +10002e02: 2c00 cmp r4, #0 +10002e04: f47f aeff bne.w 10002c06 <_vsnprintf+0x7d2> +10002e08: f7ff bb32 b.w 10002470 <_vsnprintf+0x3c> + +10002e0c : +10002e0c: 468c mov ip, r1 +10002e0e: b510 push {r4, lr} +10002e10: b084 sub sp, #16 +10002e12: 9300 str r3, [sp, #0] +10002e14: 9002 str r0, [sp, #8] +10002e16: 4613 mov r3, r2 +10002e18: a902 add r1, sp, #8 +10002e1a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e1e: 4803 ldr r0, [pc, #12] @ (10002e2c ) +10002e20: f8cd c00c str.w ip, [sp, #12] +10002e24: f7ff fb06 bl 10002434 <_vsnprintf> +10002e28: b004 add sp, #16 +10002e2a: bd10 pop {r4, pc} +10002e2c: 10001a09 .word 0x10001a09 + +10002e30 : +10002e30: b510 push {r4, lr} +10002e32: 4a09 ldr r2, [pc, #36] @ (10002e58 ) +10002e34: b084 sub sp, #16 +10002e36: 6814 ldr r4, [r2, #0] +10002e38: b14c cbz r4, 10002e4e +10002e3a: 4603 mov r3, r0 +10002e3c: 9100 str r1, [sp, #0] +10002e3e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e42: a903 add r1, sp, #12 +10002e44: 4805 ldr r0, [pc, #20] @ (10002e5c ) +10002e46: 47a0 blx r4 +10002e48: 2001 movs r0, #1 +10002e4a: b004 add sp, #16 +10002e4c: bd10 pop {r4, pc} +10002e4e: f000 f981 bl 10003154 <__wrap_puts> +10002e52: 4620 mov r0, r4 +10002e54: b004 add sp, #16 +10002e56: bd10 pop {r4, pc} +10002e58: 20000840 .word 0x20000840 +10002e5c: 10001a01 .word 0x10001a01 + +10002e60 <_exit>: +10002e60: be00 bkpt 0x0000 +10002e62: e7fd b.n 10002e60 <_exit> + +10002e64 <_fini>: +10002e64: 4770 bx lr +10002e66: bf00 nop + +10002e68 : +10002e68: b508 push {r3, lr} +10002e6a: f7ff fff9 bl 10002e60 <_exit> +10002e6e: bf00 nop + +10002e70 : +10002e70: b538 push {r3, r4, r5, lr} +10002e72: 4c06 ldr r4, [pc, #24] @ (10002e8c ) +10002e74: 4d06 ldr r5, [pc, #24] @ (10002e90 ) +10002e76: f7fe fa13 bl 100012a0 +10002e7a: 42ac cmp r4, r5 +10002e7c: d204 bcs.n 10002e88 +10002e7e: f854 3b04 ldr.w r3, [r4], #4 +10002e82: 4798 blx r3 +10002e84: 42ac cmp r4, r5 +10002e86: d3fa bcc.n 10002e7e +10002e88: bd38 pop {r3, r4, r5, pc} +10002e8a: bf00 nop +10002e8c: 10003618 .word 0x10003618 +10002e90: 10003618 .word 0x10003618 + +10002e94 : +10002e94: 6803 ldr r3, [r0, #0] +10002e96: 4608 mov r0, r1 +10002e98: 4611 mov r1, r2 +10002e9a: 4718 bx r3 + +10002e9c : +10002e9c: b570 push {r4, r5, r6, lr} +10002e9e: 4605 mov r5, r0 +10002ea0: 4608 mov r0, r1 +10002ea2: 7d69 ldrb r1, [r5, #21] +10002ea4: b082 sub sp, #8 +10002ea6: 2900 cmp r1, #0 +10002ea8: d04f beq.n 10002f4a +10002eaa: 2a00 cmp r2, #0 +10002eac: dd25 ble.n 10002efa +10002eae: 7803 ldrb r3, [r0, #0] +10002eb0: 4614 mov r4, r2 +10002eb2: 2b0a cmp r3, #10 +10002eb4: 4606 mov r6, r0 +10002eb6: d022 beq.n 10002efe +10002eb8: 2c01 cmp r4, #1 +10002eba: f04f 0e00 mov.w lr, #0 +10002ebe: d00d beq.n 10002edc +10002ec0: 4632 mov r2, r6 +10002ec2: 2301 movs r3, #1 +10002ec4: f812 cf01 ldrb.w ip, [r2, #1]! +10002ec8: 4619 mov r1, r3 +10002eca: f1bc 0f0a cmp.w ip, #10 +10002ece: f103 0301 add.w r3, r3, #1 +10002ed2: d020 beq.n 10002f16 +10002ed4: 429c cmp r4, r3 +10002ed6: d1f5 bne.n 10002ec4 +10002ed8: 4574 cmp r4, lr +10002eda: dd05 ble.n 10002ee8 +10002edc: 682b ldr r3, [r5, #0] +10002ede: eba4 010e sub.w r1, r4, lr +10002ee2: eb06 000e add.w r0, r6, lr +10002ee6: 4798 blx r3 +10002ee8: 1931 adds r1, r6, r4 +10002eea: f811 3c01 ldrb.w r3, [r1, #-1] +10002eee: f1a3 030d sub.w r3, r3, #13 +10002ef2: fab3 f383 clz r3, r3 +10002ef6: 095b lsrs r3, r3, #5 +10002ef8: 752b strb r3, [r5, #20] +10002efa: b002 add sp, #8 +10002efc: bd70 pop {r4, r5, r6, pc} +10002efe: 7d2b ldrb r3, [r5, #20] +10002f00: 2b00 cmp r3, #0 +10002f02: d1d9 bne.n 10002eb8 +10002f04: 2102 movs r1, #2 +10002f06: 682b ldr r3, [r5, #0] +10002f08: 4813 ldr r0, [pc, #76] @ (10002f58 ) +10002f0a: 4798 blx r3 +10002f0c: 2c01 cmp r4, #1 +10002f0e: d0eb beq.n 10002ee8 +10002f10: f04f 0e01 mov.w lr, #1 +10002f14: e7d4 b.n 10002ec0 +10002f16: f812 0c01 ldrb.w r0, [r2, #-1] +10002f1a: 280d cmp r0, #13 +10002f1c: d0da beq.n 10002ed4 +10002f1e: 458e cmp lr, r1 +10002f20: eb06 000e add.w r0, r6, lr +10002f24: eba1 010e sub.w r1, r1, lr +10002f28: da05 bge.n 10002f36 +10002f2a: e9cd 3200 strd r3, r2, [sp] +10002f2e: 682b ldr r3, [r5, #0] +10002f30: 4798 blx r3 +10002f32: e9dd 3200 ldrd r3, r2, [sp] +10002f36: e9cd 3200 strd r3, r2, [sp] +10002f3a: 2102 movs r1, #2 +10002f3c: 682b ldr r3, [r5, #0] +10002f3e: 4806 ldr r0, [pc, #24] @ (10002f58 ) +10002f40: 4798 blx r3 +10002f42: 9b00 ldr r3, [sp, #0] +10002f44: 9a01 ldr r2, [sp, #4] +10002f46: 469e mov lr, r3 +10002f48: e7c4 b.n 10002ed4 +10002f4a: 4611 mov r1, r2 +10002f4c: 682b ldr r3, [r5, #0] +10002f4e: b002 add sp, #8 +10002f50: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +10002f54: 4718 bx r3 +10002f56: bf00 nop +10002f58: 100038b0 .word 0x100038b0 + +10002f5c : +10002f5c: 680b ldr r3, [r1, #0] +10002f5e: 1c5a adds r2, r3, #1 +10002f60: 2a80 cmp r2, #128 @ 0x80 +10002f62: 440b add r3, r1 +10002f64: 600a str r2, [r1, #0] +10002f66: 7118 strb r0, [r3, #4] +10002f68: d000 beq.n 10002f6c +10002f6a: 4770 bx lr +10002f6c: b530 push {r4, r5, lr} +10002f6e: 4b0e ldr r3, [pc, #56] @ (10002fa8 ) +10002f70: 460c mov r4, r1 +10002f72: 6818 ldr r0, [r3, #0] +10002f74: b083 sub sp, #12 +10002f76: b1a0 cbz r0, 10002fa2 +10002f78: 1d0d adds r5, r1, #4 +10002f7a: e001 b.n 10002f80 +10002f7c: 6900 ldr r0, [r0, #16] +10002f7e: b180 cbz r0, 10002fa2 +10002f80: 6803 ldr r3, [r0, #0] +10002f82: 2b00 cmp r3, #0 +10002f84: d0fa beq.n 10002f7c +10002f86: 4b09 ldr r3, [pc, #36] @ (10002fac ) +10002f88: 681b ldr r3, [r3, #0] +10002f8a: b10b cbz r3, 10002f90 +10002f8c: 4283 cmp r3, r0 +10002f8e: d1f5 bne.n 10002f7c +10002f90: 4629 mov r1, r5 +10002f92: 6822 ldr r2, [r4, #0] +10002f94: 9001 str r0, [sp, #4] +10002f96: f7ff ff81 bl 10002e9c +10002f9a: 9801 ldr r0, [sp, #4] +10002f9c: 6900 ldr r0, [r0, #16] +10002f9e: 2800 cmp r0, #0 +10002fa0: d1ee bne.n 10002f80 +10002fa2: 6020 str r0, [r4, #0] +10002fa4: b003 add sp, #12 +10002fa6: bd30 pop {r4, r5, pc} +10002fa8: 20000838 .word 0x20000838 +10002fac: 2000083c .word 0x2000083c + +10002fb0 : +10002fb0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002fb4: b082 sub sp, #8 +10002fb6: 4690 mov r8, r2 +10002fb8: 461c mov r4, r3 +10002fba: 460d mov r5, r1 +10002fbc: 4607 mov r7, r0 +10002fbe: f7fd ff91 bl 10000ee4 +10002fc2: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002fc6: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10002fca: 4a2e ldr r2, [pc, #184] @ (10003084 ) +10002fcc: 1882 adds r2, r0, r2 +10002fce: f141 0300 adc.w r3, r1, #0 +10002fd2: 4594 cmp ip, r2 +10002fd4: eb76 0103 sbcs.w r1, r6, r3 +10002fd8: bf3c itt cc +10002fda: 4662 movcc r2, ip +10002fdc: 4633 movcc r3, r6 +10002fde: 482a ldr r0, [pc, #168] @ (10003088 ) +10002fe0: f000 faf2 bl 100035c8 <__mutex_try_enter_block_until_veneer> +10002fe4: 1c6b adds r3, r5, #1 +10002fe6: 4682 mov sl, r0 +10002fe8: d040 beq.n 1000306c +10002fea: b30c cbz r4, 10003030 +10002fec: 4e27 ldr r6, [pc, #156] @ (1000308c ) +10002fee: 4b28 ldr r3, [pc, #160] @ (10003090 ) +10002ff0: 681c ldr r4, [r3, #0] +10002ff2: b1b4 cbz r4, 10003022 +10002ff4: f1b8 0f00 cmp.w r8, #0 +10002ff8: d11c bne.n 10003034 +10002ffa: f8df 809c ldr.w r8, [pc, #156] @ 10003098 +10002ffe: e001 b.n 10003004 +10003000: 6924 ldr r4, [r4, #16] +10003002: b174 cbz r4, 10003022 +10003004: 6823 ldr r3, [r4, #0] +10003006: 2b00 cmp r3, #0 +10003008: d0fa beq.n 10003000 +1000300a: f8d8 3000 ldr.w r3, [r8] +1000300e: b10b cbz r3, 10003014 +10003010: 429c cmp r4, r3 +10003012: d1f5 bne.n 10003000 +10003014: 4620 mov r0, r4 +10003016: 462a mov r2, r5 +10003018: 4639 mov r1, r7 +1000301a: 47b0 blx r6 +1000301c: 6924 ldr r4, [r4, #16] +1000301e: 2c00 cmp r4, #0 +10003020: d1f0 bne.n 10003004 +10003022: f1ba 0f00 cmp.w sl, #0 +10003026: d126 bne.n 10003076 +10003028: 4628 mov r0, r5 +1000302a: b002 add sp, #8 +1000302c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003030: 4e18 ldr r6, [pc, #96] @ (10003094 ) +10003032: e7dc b.n 10002fee +10003034: f04f 090a mov.w r9, #10 +10003038: f8df 805c ldr.w r8, [pc, #92] @ 10003098 +1000303c: e002 b.n 10003044 +1000303e: 6924 ldr r4, [r4, #16] +10003040: 2c00 cmp r4, #0 +10003042: d0ee beq.n 10003022 +10003044: 6823 ldr r3, [r4, #0] +10003046: 2b00 cmp r3, #0 +10003048: d0f9 beq.n 1000303e +1000304a: f8d8 3000 ldr.w r3, [r8] +1000304e: b10b cbz r3, 10003054 +10003050: 42a3 cmp r3, r4 +10003052: d1f4 bne.n 1000303e +10003054: 462a mov r2, r5 +10003056: 4639 mov r1, r7 +10003058: 4620 mov r0, r4 +1000305a: 47b0 blx r6 +1000305c: 2201 movs r2, #1 +1000305e: 4620 mov r0, r4 +10003060: f10d 0107 add.w r1, sp, #7 +10003064: f88d 9007 strb.w r9, [sp, #7] +10003068: 47b0 blx r6 +1000306a: e7e8 b.n 1000303e +1000306c: 4638 mov r0, r7 +1000306e: f000 fa79 bl 10003564 +10003072: 4605 mov r5, r0 +10003074: e7b9 b.n 10002fea +10003076: 4804 ldr r0, [pc, #16] @ (10003088 ) +10003078: f000 faa2 bl 100035c0 <__mutex_exit_veneer> +1000307c: 4628 mov r0, r5 +1000307e: b002 add sp, #8 +10003080: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003084: 000f4240 .word 0x000f4240 +10003088: 20000658 .word 0x20000658 +1000308c: 10002e9d .word 0x10002e9d +10003090: 20000838 .word 0x20000838 +10003094: 10002e95 .word 0x10002e95 +10003098: 2000083c .word 0x2000083c + +1000309c : +1000309c: 4a08 ldr r2, [pc, #32] @ (100030c0 ) +1000309e: 6813 ldr r3, [r2, #0] +100030a0: b923 cbnz r3, 100030ac +100030a2: e00a b.n 100030ba +100030a4: f103 0210 add.w r2, r3, #16 +100030a8: 691b ldr r3, [r3, #16] +100030aa: b133 cbz r3, 100030ba +100030ac: 4283 cmp r3, r0 +100030ae: d1f9 bne.n 100030a4 +100030b0: b929 cbnz r1, 100030be +100030b2: 6918 ldr r0, [r3, #16] +100030b4: 6010 str r0, [r2, #0] +100030b6: 6119 str r1, [r3, #16] +100030b8: 4770 bx lr +100030ba: b101 cbz r1, 100030be +100030bc: 6010 str r0, [r2, #0] +100030be: 4770 bx lr +100030c0: 20000838 .word 0x20000838 + +100030c4 : +100030c4: b508 push {r3, lr} +100030c6: f000 f9ad bl 10003424 +100030ca: 2001 movs r0, #1 +100030cc: bd08 pop {r3, pc} +100030ce: bf00 nop + +100030d0 <__wrap_putchar>: +100030d0: b5f0 push {r4, r5, r6, r7, lr} +100030d2: b083 sub sp, #12 +100030d4: 4606 mov r6, r0 +100030d6: f88d 0007 strb.w r0, [sp, #7] +100030da: f7fd ff03 bl 10000ee4 +100030de: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100030e2: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100030e6: 4a17 ldr r2, [pc, #92] @ (10003144 <__wrap_putchar+0x74>) +100030e8: 1882 adds r2, r0, r2 +100030ea: f141 0300 adc.w r3, r1, #0 +100030ee: 4295 cmp r5, r2 +100030f0: eb74 0103 sbcs.w r1, r4, r3 +100030f4: bf3c itt cc +100030f6: 4623 movcc r3, r4 +100030f8: 462a movcc r2, r5 +100030fa: 4813 ldr r0, [pc, #76] @ (10003148 <__wrap_putchar+0x78>) +100030fc: f000 fa64 bl 100035c8 <__mutex_try_enter_block_until_veneer> +10003100: 4b12 ldr r3, [pc, #72] @ (1000314c <__wrap_putchar+0x7c>) +10003102: 4607 mov r7, r0 +10003104: 681c ldr r4, [r3, #0] +10003106: b19c cbz r4, 10003130 <__wrap_putchar+0x60> +10003108: 4d11 ldr r5, [pc, #68] @ (10003150 <__wrap_putchar+0x80>) +1000310a: e001 b.n 10003110 <__wrap_putchar+0x40> +1000310c: 6924 ldr r4, [r4, #16] +1000310e: b17c cbz r4, 10003130 <__wrap_putchar+0x60> +10003110: 6823 ldr r3, [r4, #0] +10003112: 2b00 cmp r3, #0 +10003114: d0fa beq.n 1000310c <__wrap_putchar+0x3c> +10003116: 682b ldr r3, [r5, #0] +10003118: b10b cbz r3, 1000311e <__wrap_putchar+0x4e> +1000311a: 429c cmp r4, r3 +1000311c: d1f6 bne.n 1000310c <__wrap_putchar+0x3c> +1000311e: 4620 mov r0, r4 +10003120: 2201 movs r2, #1 +10003122: f10d 0107 add.w r1, sp, #7 +10003126: f7ff feb9 bl 10002e9c +1000312a: 6924 ldr r4, [r4, #16] +1000312c: 2c00 cmp r4, #0 +1000312e: d1ef bne.n 10003110 <__wrap_putchar+0x40> +10003130: b917 cbnz r7, 10003138 <__wrap_putchar+0x68> +10003132: 4630 mov r0, r6 +10003134: b003 add sp, #12 +10003136: bdf0 pop {r4, r5, r6, r7, pc} +10003138: 4803 ldr r0, [pc, #12] @ (10003148 <__wrap_putchar+0x78>) +1000313a: f000 fa41 bl 100035c0 <__mutex_exit_veneer> +1000313e: 4630 mov r0, r6 +10003140: b003 add sp, #12 +10003142: bdf0 pop {r4, r5, r6, r7, pc} +10003144: 000f4240 .word 0x000f4240 +10003148: 20000658 .word 0x20000658 +1000314c: 20000838 .word 0x20000838 +10003150: 2000083c .word 0x2000083c + +10003154 <__wrap_puts>: +10003154: b538 push {r3, r4, r5, lr} +10003156: 4604 mov r4, r0 +10003158: f000 fa04 bl 10003564 +1000315c: 2301 movs r3, #1 +1000315e: 4605 mov r5, r0 +10003160: 461a mov r2, r3 +10003162: 4620 mov r0, r4 +10003164: 4629 mov r1, r5 +10003166: f7ff ff23 bl 10002fb0 +1000316a: 4b08 ldr r3, [pc, #32] @ (1000318c <__wrap_puts+0x38>) +1000316c: 681c ldr r4, [r3, #0] +1000316e: b12c cbz r4, 1000317c <__wrap_puts+0x28> +10003170: 6863 ldr r3, [r4, #4] +10003172: b12b cbz r3, 10003180 <__wrap_puts+0x2c> +10003174: 4798 blx r3 +10003176: 6924 ldr r4, [r4, #16] +10003178: 2c00 cmp r4, #0 +1000317a: d1f9 bne.n 10003170 <__wrap_puts+0x1c> +1000317c: 4628 mov r0, r5 +1000317e: bd38 pop {r3, r4, r5, pc} +10003180: 6924 ldr r4, [r4, #16] +10003182: 2c00 cmp r4, #0 +10003184: d1f4 bne.n 10003170 <__wrap_puts+0x1c> +10003186: 4628 mov r0, r5 +10003188: bd38 pop {r3, r4, r5, pc} +1000318a: bf00 nop +1000318c: 20000838 .word 0x20000838 + +10003190 <__wrap_vprintf>: +10003190: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003194: b0a2 sub sp, #136 @ 0x88 +10003196: 460e mov r6, r1 +10003198: 4605 mov r5, r0 +1000319a: f7fd fea3 bl 10000ee4 +1000319e: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +100031a2: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100031a6: 4a25 ldr r2, [pc, #148] @ (1000323c <__wrap_vprintf+0xac>) +100031a8: 1882 adds r2, r0, r2 +100031aa: f141 0300 adc.w r3, r1, #0 +100031ae: 4594 cmp ip, r2 +100031b0: eb74 0103 sbcs.w r1, r4, r3 +100031b4: bf3c itt cc +100031b6: 4623 movcc r3, r4 +100031b8: 4662 movcc r2, ip +100031ba: 4821 ldr r0, [pc, #132] @ (10003240 <__wrap_vprintf+0xb0>) +100031bc: f000 fa04 bl 100035c8 <__mutex_try_enter_block_until_veneer> +100031c0: 2400 movs r4, #0 +100031c2: 4633 mov r3, r6 +100031c4: 4607 mov r7, r0 +100031c6: 462a mov r2, r5 +100031c8: 481e ldr r0, [pc, #120] @ (10003244 <__wrap_vprintf+0xb4>) +100031ca: a901 add r1, sp, #4 +100031cc: 9401 str r4, [sp, #4] +100031ce: f7ff fe1d bl 10002e0c +100031d2: 4e1d ldr r6, [pc, #116] @ (10003248 <__wrap_vprintf+0xb8>) +100031d4: 9b01 ldr r3, [sp, #4] +100031d6: 4680 mov r8, r0 +100031d8: 6834 ldr r4, [r6, #0] +100031da: b1bb cbz r3, 1000320c <__wrap_vprintf+0x7c> +100031dc: 2c00 cmp r4, #0 +100031de: d02a beq.n 10003236 <__wrap_vprintf+0xa6> +100031e0: 4d1a ldr r5, [pc, #104] @ (1000324c <__wrap_vprintf+0xbc>) +100031e2: e001 b.n 100031e8 <__wrap_vprintf+0x58> +100031e4: 6924 ldr r4, [r4, #16] +100031e6: b174 cbz r4, 10003206 <__wrap_vprintf+0x76> +100031e8: 6823 ldr r3, [r4, #0] +100031ea: 2b00 cmp r3, #0 +100031ec: d0fa beq.n 100031e4 <__wrap_vprintf+0x54> +100031ee: 682b ldr r3, [r5, #0] +100031f0: b10b cbz r3, 100031f6 <__wrap_vprintf+0x66> +100031f2: 42a3 cmp r3, r4 +100031f4: d1f6 bne.n 100031e4 <__wrap_vprintf+0x54> +100031f6: 4620 mov r0, r4 +100031f8: 9a01 ldr r2, [sp, #4] +100031fa: a902 add r1, sp, #8 +100031fc: f7ff fe4e bl 10002e9c +10003200: 6924 ldr r4, [r4, #16] +10003202: 2c00 cmp r4, #0 +10003204: d1f0 bne.n 100031e8 <__wrap_vprintf+0x58> +10003206: 4623 mov r3, r4 +10003208: 6834 ldr r4, [r6, #0] +1000320a: 9301 str r3, [sp, #4] +1000320c: b12c cbz r4, 1000321a <__wrap_vprintf+0x8a> +1000320e: 6863 ldr r3, [r4, #4] +10003210: b143 cbz r3, 10003224 <__wrap_vprintf+0x94> +10003212: 4798 blx r3 +10003214: 6924 ldr r4, [r4, #16] +10003216: 2c00 cmp r4, #0 +10003218: d1f9 bne.n 1000320e <__wrap_vprintf+0x7e> +1000321a: b92f cbnz r7, 10003228 <__wrap_vprintf+0x98> +1000321c: 4640 mov r0, r8 +1000321e: b022 add sp, #136 @ 0x88 +10003220: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003224: 6924 ldr r4, [r4, #16] +10003226: e7f1 b.n 1000320c <__wrap_vprintf+0x7c> +10003228: 4805 ldr r0, [pc, #20] @ (10003240 <__wrap_vprintf+0xb0>) +1000322a: f000 f9c9 bl 100035c0 <__mutex_exit_veneer> +1000322e: 4640 mov r0, r8 +10003230: b022 add sp, #136 @ 0x88 +10003232: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003236: 9401 str r4, [sp, #4] +10003238: e7ef b.n 1000321a <__wrap_vprintf+0x8a> +1000323a: bf00 nop +1000323c: 000f4240 .word 0x000f4240 +10003240: 20000658 .word 0x20000658 +10003244: 10002f5d .word 0x10002f5d +10003248: 20000838 .word 0x20000838 +1000324c: 2000083c .word 0x2000083c + +10003250 <__wrap_printf>: +10003250: b40f push {r0, r1, r2, r3} +10003252: b500 push {lr} +10003254: b083 sub sp, #12 +10003256: a904 add r1, sp, #16 +10003258: f851 0b04 ldr.w r0, [r1], #4 +1000325c: 9101 str r1, [sp, #4] +1000325e: f7ff ff97 bl 10003190 <__wrap_vprintf> +10003262: b003 add sp, #12 +10003264: f85d eb04 ldr.w lr, [sp], #4 +10003268: b004 add sp, #16 +1000326a: 4770 bx lr + +1000326c : +1000326c: f1b1 0c00 subs.w ip, r1, #0 +10003270: dd1e ble.n 100032b0 +10003272: 4a10 ldr r2, [pc, #64] @ (100032b4 ) +10003274: 4b10 ldr r3, [pc, #64] @ (100032b8 ) +10003276: 6812 ldr r2, [r2, #0] +10003278: b510 push {r4, lr} +1000327a: 1ad3 subs r3, r2, r3 +1000327c: fab3 f383 clz r3, r3 +10003280: 240d movs r4, #13 +10003282: f8df e038 ldr.w lr, [pc, #56] @ 100032bc +10003286: 095b lsrs r3, r3, #5 +10003288: 1e41 subs r1, r0, #1 +1000328a: f93e e013 ldrsh.w lr, [lr, r3, lsl #1] +1000328e: 448c add ip, r1 +10003290: f811 0f01 ldrb.w r0, [r1, #1]! +10003294: 4586 cmp lr, r0 +10003296: d006 beq.n 100032a6 +10003298: 6993 ldr r3, [r2, #24] +1000329a: 069b lsls r3, r3, #26 +1000329c: d4fc bmi.n 10003298 +1000329e: 4561 cmp r1, ip +100032a0: 6010 str r0, [r2, #0] +100032a2: d1f5 bne.n 10003290 +100032a4: bd10 pop {r4, pc} +100032a6: 6993 ldr r3, [r2, #24] +100032a8: 069b lsls r3, r3, #26 +100032aa: d4fc bmi.n 100032a6 +100032ac: 6014 str r4, [r2, #0] +100032ae: e7f3 b.n 10003298 +100032b0: 4770 bx lr +100032b2: bf00 nop +100032b4: 2000086c .word 0x2000086c +100032b8: 40078000 .word 0x40078000 +100032bc: 20000868 .word 0x20000868 + +100032c0 : +100032c0: 4b24 ldr r3, [pc, #144] @ (10003354 ) +100032c2: f1b1 0c00 subs.w ip, r1, #0 +100032c6: b500 push {lr} +100032c8: f8d3 e000 ldr.w lr, [r3] +100032cc: dd2f ble.n 1000332e +100032ce: 2100 movs r1, #0 +100032d0: 4b21 ldr r3, [pc, #132] @ (10003358 ) +100032d2: 3801 subs r0, #1 +100032d4: 681a ldr r2, [r3, #0] +100032d6: 6993 ldr r3, [r2, #24] +100032d8: 06db lsls r3, r3, #27 +100032da: d418 bmi.n 1000330e +100032dc: 3101 adds r1, #1 +100032de: 6993 ldr r3, [r2, #24] +100032e0: 06db lsls r3, r3, #27 +100032e2: d4fc bmi.n 100032de +100032e4: 6813 ldr r3, [r2, #0] +100032e6: 458c cmp ip, r1 +100032e8: f800 3f01 strb.w r3, [r0, #1]! +100032ec: d1f3 bne.n 100032d6 +100032ee: f1be 0f00 cmp.w lr, #0 +100032f2: d009 beq.n 10003308 +100032f4: 2150 movs r1, #80 @ 0x50 +100032f6: 4613 mov r3, r2 +100032f8: 6391 str r1, [r2, #56] @ 0x38 +100032fa: f853 2f34 ldr.w r2, [r3, #52]! +100032fe: f002 0238 and.w r2, r2, #56 @ 0x38 +10003302: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003306: 601a str r2, [r3, #0] +10003308: 4661 mov r1, ip +1000330a: 4608 mov r0, r1 +1000330c: bd00 pop {pc} +1000330e: f1be 0f00 cmp.w lr, #0 +10003312: d009 beq.n 10003328 +10003314: 2050 movs r0, #80 @ 0x50 +10003316: 4613 mov r3, r2 +10003318: 6390 str r0, [r2, #56] @ 0x38 +1000331a: f853 2f34 ldr.w r2, [r3, #52]! +1000331e: f002 0238 and.w r2, r2, #56 @ 0x38 +10003322: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003326: 601a str r2, [r3, #0] +10003328: b181 cbz r1, 1000334c +1000332a: 4608 mov r0, r1 +1000332c: bd00 pop {pc} +1000332e: f1be 0f00 cmp.w lr, #0 +10003332: d00b beq.n 1000334c +10003334: 4b08 ldr r3, [pc, #32] @ (10003358 ) +10003336: 2150 movs r1, #80 @ 0x50 +10003338: 681a ldr r2, [r3, #0] +1000333a: 4613 mov r3, r2 +1000333c: 6391 str r1, [r2, #56] @ 0x38 +1000333e: f853 2f34 ldr.w r2, [r3, #52]! +10003342: f002 0238 and.w r2, r2, #56 @ 0x38 +10003346: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000334a: 601a str r2, [r3, #0] +1000334c: f06f 0102 mvn.w r1, #2 +10003350: e7db b.n 1000330a +10003352: bf00 nop +10003354: 20000800 .word 0x20000800 +10003358: 2000086c .word 0x2000086c + +1000335c : +1000335c: 4b05 ldr r3, [pc, #20] @ (10003374 ) +1000335e: 681b ldr r3, [r3, #0] +10003360: b133 cbz r3, 10003370 +10003362: 2100 movs r1, #0 +10003364: 4a04 ldr r2, [pc, #16] @ (10003378 ) +10003366: 4805 ldr r0, [pc, #20] @ (1000337c ) +10003368: 6812 ldr r2, [r2, #0] +1000336a: 6800 ldr r0, [r0, #0] +1000336c: 6391 str r1, [r2, #56] @ 0x38 +1000336e: 4718 bx r3 +10003370: 4770 bx lr +10003372: bf00 nop +10003374: 20000800 .word 0x20000800 +10003378: 2000086c .word 0x2000086c +1000337c: 20000804 .word 0x20000804 + +10003380 : +10003380: 4b02 ldr r3, [pc, #8] @ (1000338c ) +10003382: 681a ldr r2, [r3, #0] +10003384: 6993 ldr r3, [r2, #24] +10003386: 071b lsls r3, r3, #28 +10003388: d4fc bmi.n 10003384 +1000338a: 4770 bx lr +1000338c: 2000086c .word 0x2000086c + +10003390 : +10003390: b530 push {r4, r5, lr} +10003392: 4d1f ldr r5, [pc, #124] @ (10003410 ) +10003394: 4a1f ldr r2, [pc, #124] @ (10003414 ) +10003396: f8d5 c000 ldr.w ip, [r5] +1000339a: 4c1f ldr r4, [pc, #124] @ (10003418 ) +1000339c: 468e mov lr, r1 +1000339e: 4594 cmp ip, r2 +100033a0: bf14 ite ne +100033a2: 2221 movne r2, #33 @ 0x21 +100033a4: 2222 moveq r2, #34 @ 0x22 +100033a6: 6821 ldr r1, [r4, #0] +100033a8: b083 sub sp, #12 +100033aa: b110 cbz r0, 100033b2 +100033ac: b1a9 cbz r1, 100033da +100033ae: b003 add sp, #12 +100033b0: bd30 pop {r4, r5, pc} +100033b2: 2900 cmp r1, #0 +100033b4: d0fb beq.n 100033ae +100033b6: f8cc 0038 str.w r0, [ip, #56] @ 0x38 +100033ba: 4601 mov r1, r0 +100033bc: 9001 str r0, [sp, #4] +100033be: 4610 mov r0, r2 +100033c0: 9200 str r2, [sp, #0] +100033c2: f7fd f82d bl 10000420 +100033c6: 4915 ldr r1, [pc, #84] @ (1000341c ) +100033c8: 9800 ldr r0, [sp, #0] +100033ca: f7fd f871 bl 100004b0 +100033ce: 9b01 ldr r3, [sp, #4] +100033d0: 4a13 ldr r2, [pc, #76] @ (10003420 ) +100033d2: 6023 str r3, [r4, #0] +100033d4: 6013 str r3, [r2, #0] +100033d6: b003 add sp, #12 +100033d8: bd30 pop {r4, r5, pc} +100033da: 4b11 ldr r3, [pc, #68] @ (10003420 ) +100033dc: 6020 str r0, [r4, #0] +100033de: 490f ldr r1, [pc, #60] @ (1000341c ) +100033e0: 4610 mov r0, r2 +100033e2: 9200 str r2, [sp, #0] +100033e4: f8c3 e000 str.w lr, [r3] +100033e8: f7fd f830 bl 1000044c +100033ec: 2101 movs r1, #1 +100033ee: 9800 ldr r0, [sp, #0] +100033f0: f7fd f816 bl 10000420 +100033f4: 682a ldr r2, [r5, #0] +100033f6: 2150 movs r1, #80 @ 0x50 +100033f8: 4613 mov r3, r2 +100033fa: 6391 str r1, [r2, #56] @ 0x38 +100033fc: f853 2f34 ldr.w r2, [r3, #52]! +10003400: f002 0238 and.w r2, r2, #56 @ 0x38 +10003404: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003408: 601a str r2, [r3, #0] +1000340a: b003 add sp, #12 +1000340c: bd30 pop {r4, r5, pc} +1000340e: bf00 nop +10003410: 2000086c .word 0x2000086c +10003414: 40078000 .word 0x40078000 +10003418: 20000800 .word 0x20000800 +1000341c: 1000335d .word 0x1000335d +10003420: 20000804 .word 0x20000804 + +10003424 : +10003424: b510 push {r4, lr} +10003426: 490e ldr r1, [pc, #56] @ (10003460 ) +10003428: 4c0e ldr r4, [pc, #56] @ (10003464 ) +1000342a: 480f ldr r0, [pc, #60] @ (10003468 ) +1000342c: 4a0f ldr r2, [pc, #60] @ (1000346c ) +1000342e: 4b10 ldr r3, [pc, #64] @ (10003470 ) +10003430: 7800 ldrb r0, [r0, #0] +10003432: 6021 str r1, [r4, #0] +10003434: 2000 movs r0, #0 +10003436: 2102 movs r1, #2 +10003438: 7812 ldrb r2, [r2, #0] +1000343a: 781b ldrb r3, [r3, #0] +1000343c: f7fc ff4e bl 100002dc +10003440: 2102 movs r1, #2 +10003442: 2001 movs r0, #1 +10003444: f7fc ff4a bl 100002dc +10003448: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +1000344c: 6820 ldr r0, [r4, #0] +1000344e: f7fd fd95 bl 10000f7c +10003452: e8bd 4010 ldmia.w sp!, {r4, lr} +10003456: 2101 movs r1, #1 +10003458: 4806 ldr r0, [pc, #24] @ (10003474 ) +1000345a: f7ff be1f b.w 1000309c +1000345e: bf00 nop +10003460: 40070000 .word 0x40070000 +10003464: 2000086c .word 0x2000086c +10003468: 10003900 .word 0x10003900 +1000346c: 100038fc .word 0x100038fc +10003470: 100038f8 .word 0x100038f8 +10003474: 20000640 .word 0x20000640 + +10003478 : +10003478: 4684 mov ip, r0 +1000347a: ea41 0300 orr.w r3, r1, r0 +1000347e: f013 0303 ands.w r3, r3, #3 +10003482: d149 bne.n 10003518 +10003484: 3a40 subs r2, #64 @ 0x40 +10003486: d323 bcc.n 100034d0 +10003488: 680b ldr r3, [r1, #0] +1000348a: 6003 str r3, [r0, #0] +1000348c: 684b ldr r3, [r1, #4] +1000348e: 6043 str r3, [r0, #4] +10003490: 688b ldr r3, [r1, #8] +10003492: 6083 str r3, [r0, #8] +10003494: 68cb ldr r3, [r1, #12] +10003496: 60c3 str r3, [r0, #12] +10003498: 690b ldr r3, [r1, #16] +1000349a: 6103 str r3, [r0, #16] +1000349c: 694b ldr r3, [r1, #20] +1000349e: 6143 str r3, [r0, #20] +100034a0: 698b ldr r3, [r1, #24] +100034a2: 6183 str r3, [r0, #24] +100034a4: 69cb ldr r3, [r1, #28] +100034a6: 61c3 str r3, [r0, #28] +100034a8: 6a0b ldr r3, [r1, #32] +100034aa: 6203 str r3, [r0, #32] +100034ac: 6a4b ldr r3, [r1, #36] @ 0x24 +100034ae: 6243 str r3, [r0, #36] @ 0x24 +100034b0: 6a8b ldr r3, [r1, #40] @ 0x28 +100034b2: 6283 str r3, [r0, #40] @ 0x28 +100034b4: 6acb ldr r3, [r1, #44] @ 0x2c +100034b6: 62c3 str r3, [r0, #44] @ 0x2c +100034b8: 6b0b ldr r3, [r1, #48] @ 0x30 +100034ba: 6303 str r3, [r0, #48] @ 0x30 +100034bc: 6b4b ldr r3, [r1, #52] @ 0x34 +100034be: 6343 str r3, [r0, #52] @ 0x34 +100034c0: 6b8b ldr r3, [r1, #56] @ 0x38 +100034c2: 6383 str r3, [r0, #56] @ 0x38 +100034c4: 6bcb ldr r3, [r1, #60] @ 0x3c +100034c6: 63c3 str r3, [r0, #60] @ 0x3c +100034c8: 3040 adds r0, #64 @ 0x40 +100034ca: 3140 adds r1, #64 @ 0x40 +100034cc: 3a40 subs r2, #64 @ 0x40 +100034ce: d2db bcs.n 10003488 +100034d0: 3230 adds r2, #48 @ 0x30 +100034d2: d30b bcc.n 100034ec +100034d4: 680b ldr r3, [r1, #0] +100034d6: 6003 str r3, [r0, #0] +100034d8: 684b ldr r3, [r1, #4] +100034da: 6043 str r3, [r0, #4] +100034dc: 688b ldr r3, [r1, #8] +100034de: 6083 str r3, [r0, #8] +100034e0: 68cb ldr r3, [r1, #12] +100034e2: 60c3 str r3, [r0, #12] +100034e4: 3010 adds r0, #16 +100034e6: 3110 adds r1, #16 +100034e8: 3a10 subs r2, #16 +100034ea: d2f3 bcs.n 100034d4 +100034ec: 320c adds r2, #12 +100034ee: d305 bcc.n 100034fc +100034f0: f851 3b04 ldr.w r3, [r1], #4 +100034f4: f840 3b04 str.w r3, [r0], #4 +100034f8: 3a04 subs r2, #4 +100034fa: d2f9 bcs.n 100034f0 +100034fc: 3204 adds r2, #4 +100034fe: d008 beq.n 10003512 +10003500: 07d2 lsls r2, r2, #31 +10003502: bf1c itt ne +10003504: f811 3b01 ldrbne.w r3, [r1], #1 +10003508: f800 3b01 strbne.w r3, [r0], #1 +1000350c: d301 bcc.n 10003512 +1000350e: 880b ldrh r3, [r1, #0] +10003510: 8003 strh r3, [r0, #0] +10003512: 4660 mov r0, ip +10003514: 4770 bx lr +10003516: bf00 nop +10003518: 2a08 cmp r2, #8 +1000351a: d313 bcc.n 10003544 +1000351c: 078b lsls r3, r1, #30 +1000351e: d0b1 beq.n 10003484 +10003520: f010 0303 ands.w r3, r0, #3 +10003524: d0ae beq.n 10003484 +10003526: f1c3 0304 rsb r3, r3, #4 +1000352a: 1ad2 subs r2, r2, r3 +1000352c: 07db lsls r3, r3, #31 +1000352e: bf1c itt ne +10003530: f811 3b01 ldrbne.w r3, [r1], #1 +10003534: f800 3b01 strbne.w r3, [r0], #1 +10003538: d3a4 bcc.n 10003484 +1000353a: f831 3b02 ldrh.w r3, [r1], #2 +1000353e: f820 3b02 strh.w r3, [r0], #2 +10003542: e79f b.n 10003484 +10003544: 3a04 subs r2, #4 +10003546: d3d9 bcc.n 100034fc +10003548: 3a01 subs r2, #1 +1000354a: f811 3b01 ldrb.w r3, [r1], #1 +1000354e: f800 3b01 strb.w r3, [r0], #1 +10003552: d2f9 bcs.n 10003548 +10003554: 780b ldrb r3, [r1, #0] +10003556: 7003 strb r3, [r0, #0] +10003558: 784b ldrb r3, [r1, #1] +1000355a: 7043 strb r3, [r0, #1] +1000355c: 788b ldrb r3, [r1, #2] +1000355e: 7083 strb r3, [r0, #2] +10003560: 4660 mov r0, ip +10003562: 4770 bx lr + +10003564 : +10003564: f020 0103 bic.w r1, r0, #3 +10003568: f010 0003 ands.w r0, r0, #3 +1000356c: f1c0 0000 rsb r0, r0, #0 +10003570: f851 3b04 ldr.w r3, [r1], #4 +10003574: f100 0c04 add.w ip, r0, #4 +10003578: ea4f 0ccc mov.w ip, ip, lsl #3 +1000357c: f06f 0200 mvn.w r2, #0 +10003580: bf1c itt ne +10003582: fa22 f20c lsrne.w r2, r2, ip +10003586: 4313 orrne r3, r2 +10003588: f04f 0c01 mov.w ip, #1 +1000358c: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003590: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003594: eba3 020c sub.w r2, r3, ip +10003598: ea22 0203 bic.w r2, r2, r3 +1000359c: ea12 12cc ands.w r2, r2, ip, lsl #7 +100035a0: bf04 itt eq +100035a2: f851 3b04 ldreq.w r3, [r1], #4 +100035a6: 3004 addeq r0, #4 +100035a8: d0f4 beq.n 10003594 +100035aa: f1c2 0100 rsb r1, r2, #0 +100035ae: ea02 0201 and.w r2, r2, r1 +100035b2: fab2 f282 clz r2, r2 +100035b6: f1c2 021f rsb r2, r2, #31 +100035ba: eb00 00d2 add.w r0, r0, r2, lsr #3 +100035be: 4770 bx lr + +100035c0 <__mutex_exit_veneer>: +100035c0: f85f f000 ldr.w pc, [pc] @ 100035c4 <__mutex_exit_veneer+0x4> +100035c4: 20000211 .word 0x20000211 + +100035c8 <__mutex_try_enter_block_until_veneer>: +100035c8: f85f f000 ldr.w pc, [pc] @ 100035cc <__mutex_try_enter_block_until_veneer+0x4> +100035cc: 200001a9 .word 0x200001a9 + +100035d0 <____aeabi_uldivmod_veneer>: +100035d0: f85f f000 ldr.w pc, [pc] @ 100035d4 <____aeabi_uldivmod_veneer+0x4> +100035d4: 20000259 .word 0x20000259 + +100035d8 <__pre_init_runtime_init_bootrom_reset>: +100035d8: 10001349 I... + +100035dc <__pre_init_runtime_init_early_resets>: +100035dc: 100012c1 .... + +100035e0 <__pre_init_runtime_init_usb_power_down>: +100035e0: 100012f1 .... + +100035e4 <__pre_init_runtime_init_clocks>: +100035e4: 100013d9 .... + +100035e8 <__pre_init_runtime_init_post_clock_resets>: +100035e8: 10001329 )... + +100035ec <__pre_init_runtime_init_boot_locks_reset>: +100035ec: 10001249 I... + +100035f0 <__pre_init_runtime_init_spin_locks_reset>: +100035f0: 10001371 q... + +100035f4 <__pre_init_runtime_init_bootrom_locking_enable>: +100035f4: 10001235 5... + +100035f8 <__pre_init_runtime_init_mutex>: +100035f8: 10000749 I... + +100035fc <__pre_init_runtime_init_install_ram_vector_table>: +100035fc: 10001375 u... + +10003600 <__pre_init_runtime_init_default_alarm_pool>: +10003600: 10000abd .... + +10003604 <__pre_init_first_per_core_initializer>: +10003604: 10001291 .... + +10003608 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003608: 1000135d ]... + +1000360c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000360c: 1000130d .... + +10003610 <__pre_init_spinlock_set_extexclall>: +10003610: 100003b9 .... + +10003614 <__pre_init_runtime_init_per_core_irq_priorities>: +10003614: 100003e1 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +20000118: 4699 mov r9, r3 +2000011a: 680b ldr r3, [r1, #0] +2000011c: 4604 mov r4, r0 +2000011e: 4617 mov r7, r2 +20000120: f04f 0800 mov.w r8, #0 +20000124: 469a mov sl, r3 +20000126: 4d1e ldr r5, [pc, #120] @ (200001a0 ) +20000128: 4e1e ldr r6, [pc, #120] @ (200001a4 ) +2000012a: 6820 ldr r0, [r4, #0] +2000012c: f3ef 8c10 mrs ip, PRIMASK +20000130: b672 cpsid i +20000132: e8d0 2fcf ldaexb r2, [r0] +20000136: 2301 movs r3, #1 +20000138: 2a00 cmp r2, #0 +2000013a: d1fa bne.n 20000132 +2000013c: e8c0 3f42 strexb r2, r3, [r0] +20000140: 2a00 cmp r2, #0 +20000142: d1f6 bne.n 20000132 +20000144: f3bf 8f5f dmb sy +20000148: f994 2004 ldrsb.w r2, [r4, #4] +2000014c: 6823 ldr r3, [r4, #0] +2000014e: 2a00 cmp r2, #0 +20000150: db1b blt.n 2000018a +20000152: 7828 ldrb r0, [r5, #0] +20000154: b2c0 uxtb r0, r0 +20000156: e8c3 8f8f stlb r8, [r3] +2000015a: bf20 wfe +2000015c: f38c 8810 msr PRIMASK, ip +20000160: 782b ldrb r3, [r5, #0] +20000162: 4283 cmp r3, r0 +20000164: d00a beq.n 2000017c +20000166: 6a73 ldr r3, [r6, #36] @ 0x24 +20000168: 4599 cmp r9, r3 +2000016a: d8de bhi.n 2000012a +2000016c: 6ab2 ldr r2, [r6, #40] @ 0x28 +2000016e: 42ba cmp r2, r7 +20000170: d201 bcs.n 20000176 +20000172: 4599 cmp r9, r3 +20000174: d0d9 beq.n 2000012a +20000176: 2000 movs r0, #0 +20000178: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +2000017c: 4638 mov r0, r7 +2000017e: 4649 mov r1, r9 +20000180: f000 fa26 bl 200005d0 <__best_effort_wfe_or_timeout_veneer> +20000184: 2800 cmp r0, #0 +20000186: d0d0 beq.n 2000012a +20000188: e7f5 b.n 20000176 +2000018a: 2200 movs r2, #0 +2000018c: f884 a004 strb.w sl, [r4, #4] +20000190: e8c3 2f8f stlb r2, [r3] +20000194: f38c 8810 msr PRIMASK, ip +20000198: 2001 movs r0, #1 +2000019a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +2000019e: bf00 nop +200001a0: 20000871 .word 0x20000871 +200001a4: 400b0000 .word 0x400b0000 + +200001a8 : +200001a8: b510 push {r4, lr} +200001aa: 6801 ldr r1, [r0, #0] +200001ac: f3ef 8e10 mrs lr, PRIMASK +200001b0: b672 cpsid i +200001b2: e8d1 cfcf ldaexb ip, [r1] +200001b6: 2401 movs r4, #1 +200001b8: f1bc 0f00 cmp.w ip, #0 +200001bc: d1f9 bne.n 200001b2 +200001be: e8c1 4f4c strexb ip, r4, [r1] +200001c2: f1bc 0f00 cmp.w ip, #0 +200001c6: d1f4 bne.n 200001b2 +200001c8: f3bf 8f5f dmb sy +200001cc: f990 c004 ldrsb.w ip, [r0, #4] +200001d0: 6804 ldr r4, [r0, #0] +200001d2: f1bc 0f00 cmp.w ip, #0 +200001d6: db10 blt.n 200001fa +200001d8: 2100 movs r1, #0 +200001da: e8c4 1f8f stlb r1, [r4] +200001de: f38e 8810 msr PRIMASK, lr +200001e2: f04f 4450 mov.w r4, #3489660928 @ 0xd0000000 +200001e6: f994 4000 ldrsb.w r4, [r4] +200001ea: 4564 cmp r4, ip +200001ec: d101 bne.n 200001f2 +200001ee: 4608 mov r0, r1 +200001f0: bd10 pop {r4, pc} +200001f2: e8bd 4010 ldmia.w sp!, {r4, lr} +200001f6: f7ff bf8b b.w 20000110 +200001fa: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001fe: 6812 ldr r2, [r2, #0] +20000200: 2300 movs r3, #0 +20000202: 7102 strb r2, [r0, #4] +20000204: e8c4 3f8f stlb r3, [r4] +20000208: f38e 8810 msr PRIMASK, lr +2000020c: 2001 movs r0, #1 +2000020e: bd10 pop {r4, pc} + +20000210 : +20000210: 6803 ldr r3, [r0, #0] +20000212: f3ef 8110 mrs r1, PRIMASK +20000216: b672 cpsid i +20000218: e8d3 cfcf ldaexb ip, [r3] +2000021c: 2201 movs r2, #1 +2000021e: f1bc 0f00 cmp.w ip, #0 +20000222: d1f9 bne.n 20000218 +20000224: e8c3 2f4c strexb ip, r2, [r3] +20000228: f1bc 0f00 cmp.w ip, #0 +2000022c: d1f4 bne.n 20000218 +2000022e: f3bf 8f5f dmb sy +20000232: f04f 0cff mov.w ip, #255 @ 0xff +20000236: 4a07 ldr r2, [pc, #28] @ (20000254 ) +20000238: f880 c004 strb.w ip, [r0, #4] +2000023c: 7813 ldrb r3, [r2, #0] +2000023e: 3301 adds r3, #1 +20000240: 7013 strb r3, [r2, #0] +20000242: 2300 movs r3, #0 +20000244: 6802 ldr r2, [r0, #0] +20000246: e8c2 3f8f stlb r3, [r2] +2000024a: f381 8810 msr PRIMASK, r1 +2000024e: bf40 sev +20000250: 4770 bx lr +20000252: bf00 nop +20000254: 20000871 .word 0x20000871 + +20000258 <__aeabi_uldivmod>: +20000258: b953 cbnz r3, 20000270 <__aeabi_uldivmod+0x18> +2000025a: b94a cbnz r2, 20000270 <__aeabi_uldivmod+0x18> +2000025c: 2900 cmp r1, #0 +2000025e: bf08 it eq +20000260: 2800 cmpeq r0, #0 +20000262: bf1c itt ne +20000264: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000268: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +2000026c: f000 b9ac b.w 200005c8 <__aeabi_idiv0> +20000270: f1ad 0c08 sub.w ip, sp, #8 +20000274: e96d ce04 strd ip, lr, [sp, #-16]! +20000278: f000 f806 bl 20000288 <__udivmoddi4> +2000027c: f8dd e004 ldr.w lr, [sp, #4] +20000280: e9dd 2302 ldrd r2, r3, [sp, #8] +20000284: b004 add sp, #16 +20000286: 4770 bx lr + +20000288 <__udivmoddi4>: +20000288: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +2000028c: 4606 mov r6, r0 +2000028e: b082 sub sp, #8 +20000290: 4617 mov r7, r2 +20000292: 4608 mov r0, r1 +20000294: 9a0a ldr r2, [sp, #40] @ 0x28 +20000296: 46b4 mov ip, r6 +20000298: 460d mov r5, r1 +2000029a: 2b00 cmp r3, #0 +2000029c: d14d bne.n 2000033a <__udivmoddi4+0xb2> +2000029e: 428f cmp r7, r1 +200002a0: 46be mov lr, r7 +200002a2: d965 bls.n 20000370 <__udivmoddi4+0xe8> +200002a4: fab7 f187 clz r1, r7 +200002a8: b149 cbz r1, 200002be <__udivmoddi4+0x36> +200002aa: f1c1 0320 rsb r3, r1, #32 +200002ae: 408d lsls r5, r1 +200002b0: fa07 fe01 lsl.w lr, r7, r1 +200002b4: fa06 fc01 lsl.w ip, r6, r1 +200002b8: fa26 f303 lsr.w r3, r6, r3 +200002bc: 431d orrs r5, r3 +200002be: ea4f 461e mov.w r6, lr, lsr #16 +200002c2: fa1f f08e uxth.w r0, lr +200002c6: ea4f 431c mov.w r3, ip, lsr #16 +200002ca: fbb5 f4f6 udiv r4, r5, r6 +200002ce: fb06 5514 mls r5, r6, r4, r5 +200002d2: ea43 4305 orr.w r3, r3, r5, lsl #16 +200002d6: fb04 f500 mul.w r5, r4, r0 +200002da: 429d cmp r5, r3 +200002dc: d906 bls.n 200002ec <__udivmoddi4+0x64> +200002de: eb1e 0303 adds.w r3, lr, r3 +200002e2: d202 bcs.n 200002ea <__udivmoddi4+0x62> +200002e4: 429d cmp r5, r3 +200002e6: f200 814c bhi.w 20000582 <__udivmoddi4+0x2fa> +200002ea: 3c01 subs r4, #1 +200002ec: 1b5b subs r3, r3, r5 +200002ee: fa1f fc8c uxth.w ip, ip +200002f2: fbb3 f5f6 udiv r5, r3, r6 +200002f6: fb06 3315 mls r3, r6, r5, r3 +200002fa: fb05 f000 mul.w r0, r5, r0 +200002fe: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +20000302: 4560 cmp r0, ip +20000304: d90a bls.n 2000031c <__udivmoddi4+0x94> +20000306: eb1e 0c0c adds.w ip, lr, ip +2000030a: bf2c ite cs +2000030c: 2301 movcs r3, #1 +2000030e: 2300 movcc r3, #0 +20000310: 4560 cmp r0, ip +20000312: d902 bls.n 2000031a <__udivmoddi4+0x92> +20000314: 2b00 cmp r3, #0 +20000316: f000 8137 beq.w 20000588 <__udivmoddi4+0x300> +2000031a: 3d01 subs r5, #1 +2000031c: ebac 0c00 sub.w ip, ip, r0 +20000320: ea45 4004 orr.w r0, r5, r4, lsl #16 +20000324: 2400 movs r4, #0 +20000326: b122 cbz r2, 20000332 <__udivmoddi4+0xaa> +20000328: fa2c f301 lsr.w r3, ip, r1 +2000032c: 2100 movs r1, #0 +2000032e: e9c2 3100 strd r3, r1, [r2] +20000332: 4621 mov r1, r4 +20000334: b002 add sp, #8 +20000336: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +2000033a: 428b cmp r3, r1 +2000033c: d908 bls.n 20000350 <__udivmoddi4+0xc8> +2000033e: b10a cbz r2, 20000344 <__udivmoddi4+0xbc> +20000340: e9c2 6100 strd r6, r1, [r2] +20000344: 2400 movs r4, #0 +20000346: 4620 mov r0, r4 +20000348: 4621 mov r1, r4 +2000034a: b002 add sp, #8 +2000034c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +20000350: fab3 f483 clz r4, r3 +20000354: 2c00 cmp r4, #0 +20000356: d14d bne.n 200003f4 <__udivmoddi4+0x16c> +20000358: 428b cmp r3, r1 +2000035a: f0c0 8105 bcc.w 20000568 <__udivmoddi4+0x2e0> +2000035e: 42b7 cmp r7, r6 +20000360: f240 8102 bls.w 20000568 <__udivmoddi4+0x2e0> +20000364: 4620 mov r0, r4 +20000366: 2a00 cmp r2, #0 +20000368: d0e3 beq.n 20000332 <__udivmoddi4+0xaa> +2000036a: e9c2 c500 strd ip, r5, [r2] +2000036e: e7e0 b.n 20000332 <__udivmoddi4+0xaa> +20000370: 2f00 cmp r7, #0 +20000372: f000 80a2 beq.w 200004ba <__udivmoddi4+0x232> +20000376: 4619 mov r1, r3 +20000378: fab7 f387 clz r3, r7 +2000037c: 2b00 cmp r3, #0 +2000037e: f040 80b4 bne.w 200004ea <__udivmoddi4+0x262> +20000382: 1bc3 subs r3, r0, r7 +20000384: fa1f f88e uxth.w r8, lr +20000388: 0c3f lsrs r7, r7, #16 +2000038a: 2401 movs r4, #1 +2000038c: ea4f 401c mov.w r0, ip, lsr #16 +20000390: fbb3 f5f7 udiv r5, r3, r7 +20000394: fb07 3315 mls r3, r7, r5, r3 +20000398: ea40 4303 orr.w r3, r0, r3, lsl #16 +2000039c: fb08 f005 mul.w r0, r8, r5 +200003a0: 4298 cmp r0, r3 +200003a2: d90a bls.n 200003ba <__udivmoddi4+0x132> +200003a4: eb1e 0303 adds.w r3, lr, r3 +200003a8: bf2c ite cs +200003aa: 2601 movcs r6, #1 +200003ac: 2600 movcc r6, #0 +200003ae: 4298 cmp r0, r3 +200003b0: d902 bls.n 200003b8 <__udivmoddi4+0x130> +200003b2: 2e00 cmp r6, #0 +200003b4: f000 80e2 beq.w 2000057c <__udivmoddi4+0x2f4> +200003b8: 3d01 subs r5, #1 +200003ba: 1a1b subs r3, r3, r0 +200003bc: fa1f fc8c uxth.w ip, ip +200003c0: fbb3 f0f7 udiv r0, r3, r7 +200003c4: fb07 3310 mls r3, r7, r0, r3 +200003c8: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +200003cc: fb08 f300 mul.w r3, r8, r0 +200003d0: 4563 cmp r3, ip +200003d2: d90a bls.n 200003ea <__udivmoddi4+0x162> +200003d4: eb1e 0c0c adds.w ip, lr, ip +200003d8: bf2c ite cs +200003da: 2601 movcs r6, #1 +200003dc: 2600 movcc r6, #0 +200003de: 4563 cmp r3, ip +200003e0: d902 bls.n 200003e8 <__udivmoddi4+0x160> +200003e2: 2e00 cmp r6, #0 +200003e4: f000 80c7 beq.w 20000576 <__udivmoddi4+0x2ee> +200003e8: 3801 subs r0, #1 +200003ea: ebac 0c03 sub.w ip, ip, r3 +200003ee: ea40 4005 orr.w r0, r0, r5, lsl #16 +200003f2: e798 b.n 20000326 <__udivmoddi4+0x9e> +200003f4: f1c4 0820 rsb r8, r4, #32 +200003f8: 40a3 lsls r3, r4 +200003fa: fa06 fa04 lsl.w sl, r6, r4 +200003fe: 40a1 lsls r1, r4 +20000400: fa27 fc08 lsr.w ip, r7, r8 +20000404: fa20 f008 lsr.w r0, r0, r8 +20000408: fa07 f904 lsl.w r9, r7, r4 +2000040c: ea4c 0c03 orr.w ip, ip, r3 +20000410: fa26 f308 lsr.w r3, r6, r8 +20000414: ea4f 461c mov.w r6, ip, lsr #16 +20000418: 430b orrs r3, r1 +2000041a: fa1f fe8c uxth.w lr, ip +2000041e: 0c19 lsrs r1, r3, #16 +20000420: fbb0 f7f6 udiv r7, r0, r6 +20000424: fb06 0017 mls r0, r6, r7, r0 +20000428: ea41 4100 orr.w r1, r1, r0, lsl #16 +2000042c: fb07 f00e mul.w r0, r7, lr +20000430: 4288 cmp r0, r1 +20000432: d90a bls.n 2000044a <__udivmoddi4+0x1c2> +20000434: eb1c 0101 adds.w r1, ip, r1 +20000438: bf2c ite cs +2000043a: 2501 movcs r5, #1 +2000043c: 2500 movcc r5, #0 +2000043e: 4288 cmp r0, r1 +20000440: d902 bls.n 20000448 <__udivmoddi4+0x1c0> +20000442: 2d00 cmp r5, #0 +20000444: f000 80b2 beq.w 200005ac <__udivmoddi4+0x324> +20000448: 3f01 subs r7, #1 +2000044a: 1a09 subs r1, r1, r0 +2000044c: b29b uxth r3, r3 +2000044e: fbb1 f0f6 udiv r0, r1, r6 +20000452: fb06 1110 mls r1, r6, r0, r1 +20000456: fb00 fe0e mul.w lr, r0, lr +2000045a: ea43 4301 orr.w r3, r3, r1, lsl #16 +2000045e: 459e cmp lr, r3 +20000460: d90a bls.n 20000478 <__udivmoddi4+0x1f0> +20000462: eb1c 0303 adds.w r3, ip, r3 +20000466: bf2c ite cs +20000468: 2101 movcs r1, #1 +2000046a: 2100 movcc r1, #0 +2000046c: 459e cmp lr, r3 +2000046e: d902 bls.n 20000476 <__udivmoddi4+0x1ee> +20000470: 2900 cmp r1, #0 +20000472: f000 809e beq.w 200005b2 <__udivmoddi4+0x32a> +20000476: 3801 subs r0, #1 +20000478: ea40 4007 orr.w r0, r0, r7, lsl #16 +2000047c: eba3 030e sub.w r3, r3, lr +20000480: fba0 e109 umull lr, r1, r0, r9 +20000484: 428b cmp r3, r1 +20000486: 4676 mov r6, lr +20000488: 460f mov r7, r1 +2000048a: d302 bcc.n 20000492 <__udivmoddi4+0x20a> +2000048c: d107 bne.n 2000049e <__udivmoddi4+0x216> +2000048e: 45f2 cmp sl, lr +20000490: d205 bcs.n 2000049e <__udivmoddi4+0x216> +20000492: ebbe 0609 subs.w r6, lr, r9 +20000496: eb61 010c sbc.w r1, r1, ip +2000049a: 3801 subs r0, #1 +2000049c: 460f mov r7, r1 +2000049e: b152 cbz r2, 200004b6 <__udivmoddi4+0x22e> +200004a0: ebba 0106 subs.w r1, sl, r6 +200004a4: eb63 0307 sbc.w r3, r3, r7 +200004a8: fa03 f508 lsl.w r5, r3, r8 +200004ac: 40e1 lsrs r1, r4 +200004ae: 40e3 lsrs r3, r4 +200004b0: 430d orrs r5, r1 +200004b2: e9c2 5300 strd r5, r3, [r2] +200004b6: 2400 movs r4, #0 +200004b8: e73b b.n 20000332 <__udivmoddi4+0xaa> +200004ba: 0873 lsrs r3, r6, #1 +200004bc: 46b8 mov r8, r7 +200004be: 0849 lsrs r1, r1, #1 +200004c0: 9701 str r7, [sp, #4] +200004c2: ea43 73c0 orr.w r3, r3, r0, lsl #31 +200004c6: ea4f 7cc6 mov.w ip, r6, lsl #31 +200004ca: 0c1c lsrs r4, r3, #16 +200004cc: b29b uxth r3, r3 +200004ce: ea44 4401 orr.w r4, r4, r1, lsl #16 +200004d2: ea43 4304 orr.w r3, r3, r4, lsl #16 +200004d6: fbb4 f4f7 udiv r4, r4, r7 +200004da: fbb1 f5f7 udiv r5, r1, r7 +200004de: 211f movs r1, #31 +200004e0: 9801 ldr r0, [sp, #4] +200004e2: ea44 4405 orr.w r4, r4, r5, lsl #16 +200004e6: 1a1b subs r3, r3, r0 +200004e8: e750 b.n 2000038c <__udivmoddi4+0x104> +200004ea: 4619 mov r1, r3 +200004ec: fa07 fe03 lsl.w lr, r7, r3 +200004f0: f1c3 0320 rsb r3, r3, #32 +200004f4: fa00 f401 lsl.w r4, r0, r1 +200004f8: ea4f 471e mov.w r7, lr, lsr #16 +200004fc: 40d8 lsrs r0, r3 +200004fe: fa26 f303 lsr.w r3, r6, r3 +20000502: fa1f f88e uxth.w r8, lr +20000506: fa06 fc01 lsl.w ip, r6, r1 +2000050a: 4323 orrs r3, r4 +2000050c: fbb0 f5f7 udiv r5, r0, r7 +20000510: 0c1c lsrs r4, r3, #16 +20000512: fb07 0015 mls r0, r7, r5, r0 +20000516: ea44 4000 orr.w r0, r4, r0, lsl #16 +2000051a: fb05 f408 mul.w r4, r5, r8 +2000051e: 4284 cmp r4, r0 +20000520: d94a bls.n 200005b8 <__udivmoddi4+0x330> +20000522: eb1e 0000 adds.w r0, lr, r0 +20000526: bf2c ite cs +20000528: 2601 movcs r6, #1 +2000052a: 2600 movcc r6, #0 +2000052c: 4284 cmp r4, r0 +2000052e: d900 bls.n 20000532 <__udivmoddi4+0x2aa> +20000530: b38e cbz r6, 20000596 <__udivmoddi4+0x30e> +20000532: 1b00 subs r0, r0, r4 +20000534: 3d01 subs r5, #1 +20000536: fbb0 f4f7 udiv r4, r0, r7 +2000053a: fb04 f608 mul.w r6, r4, r8 +2000053e: 46a1 mov r9, r4 +20000540: 9601 str r6, [sp, #4] +20000542: fb07 0019 mls r0, r7, r9, r0 +20000546: b29b uxth r3, r3 +20000548: 9e01 ldr r6, [sp, #4] +2000054a: ea43 4300 orr.w r3, r3, r0, lsl #16 +2000054e: 42b3 cmp r3, r6 +20000550: d2c6 bcs.n 200004e0 <__udivmoddi4+0x258> +20000552: eb1e 0303 adds.w r3, lr, r3 +20000556: bf2c ite cs +20000558: 2001 movcs r0, #1 +2000055a: 2000 movcc r0, #0 +2000055c: 42b3 cmp r3, r6 +2000055e: d200 bcs.n 20000562 <__udivmoddi4+0x2da> +20000560: b1a8 cbz r0, 2000058e <__udivmoddi4+0x306> +20000562: f109 34ff add.w r4, r9, #4294967295 @ 0xffffffff +20000566: e7bb b.n 200004e0 <__udivmoddi4+0x258> +20000568: ebb6 0c07 subs.w ip, r6, r7 +2000056c: eb60 0303 sbc.w r3, r0, r3 +20000570: 2001 movs r0, #1 +20000572: 461d mov r5, r3 +20000574: e6f7 b.n 20000366 <__udivmoddi4+0xde> +20000576: 44f4 add ip, lr +20000578: 3802 subs r0, #2 +2000057a: e736 b.n 200003ea <__udivmoddi4+0x162> +2000057c: 3d02 subs r5, #2 +2000057e: 4473 add r3, lr +20000580: e71b b.n 200003ba <__udivmoddi4+0x132> +20000582: 3c02 subs r4, #2 +20000584: 4473 add r3, lr +20000586: e6b1 b.n 200002ec <__udivmoddi4+0x64> +20000588: 44f4 add ip, lr +2000058a: 3d02 subs r5, #2 +2000058c: e6c6 b.n 2000031c <__udivmoddi4+0x94> +2000058e: f1a9 0402 sub.w r4, r9, #2 +20000592: 4473 add r3, lr +20000594: e7a4 b.n 200004e0 <__udivmoddi4+0x258> +20000596: ebae 0404 sub.w r4, lr, r4 +2000059a: 3d02 subs r5, #2 +2000059c: 4420 add r0, r4 +2000059e: fbb0 f4f7 udiv r4, r0, r7 +200005a2: fb04 f608 mul.w r6, r4, r8 +200005a6: 46a1 mov r9, r4 +200005a8: 9601 str r6, [sp, #4] +200005aa: e7ca b.n 20000542 <__udivmoddi4+0x2ba> +200005ac: 3f02 subs r7, #2 +200005ae: 4461 add r1, ip +200005b0: e74b b.n 2000044a <__udivmoddi4+0x1c2> +200005b2: 3802 subs r0, #2 +200005b4: 4463 add r3, ip +200005b6: e75f b.n 20000478 <__udivmoddi4+0x1f0> +200005b8: 1b00 subs r0, r0, r4 +200005ba: fbb0 f4f7 udiv r4, r0, r7 +200005be: fb04 f608 mul.w r6, r4, r8 +200005c2: 46a1 mov r9, r4 +200005c4: 9601 str r6, [sp, #4] +200005c6: e7bc b.n 20000542 <__udivmoddi4+0x2ba> + +200005c8 <__aeabi_idiv0>: +200005c8: 4770 bx lr +200005ca: bf00 nop +200005cc: 0000 movs r0, r0 + ... + +200005d0 <__best_effort_wfe_or_timeout_veneer>: +200005d0: f85f f000 ldr.w pc, [pc] @ 200005d4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005d4: 10000d9d .word 0x10000d9d + +200005d8 : +200005d8: 00000057 W... + +200005dc : +200005dc: 00000010 .... + +200005e0 : +200005e0: 00000000 .word 0x00000000 +200005e4: 00010000 .word 0x00010000 + ... +200005f0: 00020000 .word 0x00020000 + ... +200005fc: 00030000 .word 0x00030000 + ... +20000608: 00ff0000 .word 0x00ff0000 +2000060c: 00000000 .word 0x00000000 + +20000610 : +20000610: b501 push {r0, lr} +20000612: 6848 ldr r0, [r1, #4] +20000614: 3101 adds r1, #1 +20000616: 468e mov lr, r1 +20000618: 4700 bx r0 + +2000061a : +2000061a: 4670 mov r0, lr +2000061c: 3809 subs r0, #9 +2000061e: 4901 ldr r1, [pc, #4] @ (20000624 ) +20000620: 4788 blx r1 +20000622: bd01 pop {r0, pc} +20000624: 10000671 .word 0x10000671 + +20000628 : + ... +2000063c: 20000660 `.. + +20000640 : +20000640: 1000326d 10003381 100032c1 10003391 m2...3...2...3.. +20000650: 00000000 00000100 ........ + +20000658 : + ... diff --git a/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf new file mode 100755 index 0000000..7f84175 Binary files /dev/null and b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf differ diff --git a/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf.map b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf.map new file mode 100644 index 0000000..21a81f4 --- /dev/null +++ b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.elf.map @@ -0,0 +1,3886 @@ +Archive member included to satisfy reference by file (symbol) + +/Users/kevinthomas/.pico-sdk/toolchain/15_2_Rel1/bin/../lib/gcc/arm-none-eabi/15.2.1/thumb/v8-m.main+fp/softfp/libgcc.a(_arm_addsubdf3.o) + CMakeFiles/0x0001b_ctf.dir/Users/kevinthomas/.pico-sdk/sdk/2.3.1/src/rp2_common/pico_float/float_math.c.o (__aeabi_f2d) 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b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.uf2 new file mode 100644 index 0000000..52d6f52 Binary files /dev/null and b/WEEK04/0x0001b_ctf/build/0x0001b_ctf.uf2 differ diff --git a/WEEK04/0x0001b_ctf/include/console.h b/WEEK04/0x0001b_ctf/include/console.h new file mode 100644 index 0000000..b5a6502 --- /dev/null +++ b/WEEK04/0x0001b_ctf/include/console.h @@ -0,0 +1,72 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: console.h +// Desc: Declares the UART console banner and status reporting interface +// for Operation Black Start. +// Created: 2026 + +#ifndef CONSOLE_H +#define CONSOLE_H + +#include "grid.h" +#include + +/** + * @brief Print the response controller's boot identity and unconditional signal line. + * + * Emits the boot banner, operation window, serial configuration banner, + * unconditional signal quality line, and the interactive command prompt. + * + * @param None. + * @return None. + */ +static inline void print_boot_banner(void) +{ + printf("GLOBAL EMBEDDED RESPONSE NETWORK\r\n"); + printf("BLACK START WINDOW: 27 MINUTES\r\n"); + printf("UART0 115200 8N1 | AUTHORIZED LAB CONSOLE\r\n"); + printf("SIGNAL: NORMAL\r\n"); + printf("RESPONSE> "); +} + +/** + * @brief Print the recurring grid classification and dispatch authorization report. + * + * Evaluates the current operator state and dispatch state flags and transmits + * the formatted status report over UART0 with the quarantined frame notification. + * + * @param None. + * @return None. + */ +static inline void print_status(void) +{ + printf("GRID STATUS: %s\r\n", operator_state ? "STABLE" : "CRITICAL"); + printf("DISPATCH PATH: %s\r\n", dispatch_state ? "AUTHORIZED" : "HELD"); + printf("LAST FRAME: QUARANTINED\r\n"); + printf("RESPONSE> "); +} + +#endif // CONSOLE_H diff --git a/WEEK04/0x0001b_ctf/include/grid.h b/WEEK04/0x0001b_ctf/include/grid.h new file mode 100644 index 0000000..c1444c8 --- /dev/null +++ b/WEEK04/0x0001b_ctf/include/grid.h @@ -0,0 +1,85 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: grid.h +// Desc: Declares the grid telemetry and safety evaluation interface for +// Operation Black Start. +// Created: 2026 + +#ifndef GRID_H +#define GRID_H + +#include + +// Safety margin (Hz deviation x100) below which grid frequency is tolerable. +// BUG: emergency build miscompiled this far too permissive; correct value is 60. +#define SAFE_THRESHOLD 95 + +// Frozen grid frequency deviation reading latched when comms were severed. +extern volatile uint32_t grid_deviation; + +// Operator-facing classification of the frozen reading (drives GRID STATUS). +extern volatile uint32_t operator_state; + +// Automated dispatch authorization decision (drives DISPATCH PATH). +extern volatile uint32_t dispatch_state; + +// Quarantined black-start authorization frame, retained in flash, never sent. +static volatile const char dispatch_frame[] = + "WORLDGRID:BLACKSTART:GRID-7:WATER-3"; + +static inline void retain_dispatch_frame(void) +{ + volatile char frame_marker = dispatch_frame[0]; + (void)frame_marker; +} + +static inline void evaluate_grid(void) +{ + operator_state = (grid_deviation < SAFE_THRESHOLD) ? 1 : 0; + dispatch_state = (grid_deviation < SAFE_THRESHOLD) ? 1 : 0; +} + +/** + * @brief Anchor the hidden dispatch frame in flash without transmitting it. + * + * Reads the first character of the quarantined black-start authorization + * frame into a volatile local marker to prevent the compiler from optimizing + * out the string literal from .rodata flash storage. + * + * @param None. + * @return None. + */ +/** + * @brief Classify the frozen telemetry reading against the compiled threshold. + * + * Evaluates the frozen grid deviation reading against SAFE_THRESHOLD twice, + * once for the operator-facing status line and once for the automated + * dispatch decision, mirroring the duplicated immediate comparison site. + * + * @param None. + * @return None. + */ +#endif // GRID_H diff --git a/WEEK04/0x0001b_ctf/pico_sdk_import.cmake b/WEEK04/0x0001b_ctf/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0001b_ctf/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0001b_ctf/scripts/verify_ctf.py b/WEEK04/0x0001b_ctf/scripts/verify_ctf.py new file mode 100644 index 0000000..357eff9 --- /dev/null +++ b/WEEK04/0x0001b_ctf/scripts/verify_ctf.py @@ -0,0 +1,82 @@ +#!/usr/bin/env python3 +"""Verify every technical claim of Operation Black Start against CTF-01.bin. + +Exits 0 only when every address, byte, and hash in CTF-R.md and CTF-S.md +matches the shipped image. +""" +import hashlib +import struct +import sys +from pathlib import Path + +BASE = 0x10000000 +ROOT = Path(__file__).resolve().parent.parent +BIN = ROOT / "CTF-01.bin" +UF2 = ROOT / "CTF-01.uf2" + +EXPECTED_BIN_SHA = "425591ac17ff4c22206286ee6f40b06a89523483804850a41854a9b6f89d7b70" +EXPECTED_UF2_SHA = "b1552ee3bb5763d96c65d8df1c86984ee842ef1a823fdf5d94132b1e10ff9d16" + +CMP_A = 0x100001FC +CMP_B = 0x1000020A +STRING_SIGNAL = 0x10003678 +STRING_FRAME = 0x100037A0 +LOOP_BACK = 0x10000266 + +RESULTS = [] + + +def check(label, ok, detail=""): + """Record one verification result. + + Parameters + ---------- + label : str + Human-readable check name. + ok : bool + Whether the check passed. + detail : str + Extra context printed with the result. + + Returns + ------- + None + """ + RESULTS.append(ok) + print(f"[{'PASS' if ok else 'FAIL'}] {label} {detail}") + + +def main(): + """Run all verification checks. + + Returns + ------- + int + Zero when every check passes, else one. + """ + data = BIN.read_bytes() + check("CTF-01.bin SHA-256", hashlib.sha256(data).hexdigest() == EXPECTED_BIN_SHA) + check("CTF-01.uf2 SHA-256", + hashlib.sha256(UF2.read_bytes()).hexdigest() == EXPECTED_UF2_SHA) + check("vector table", data[0:32].hex() == + "002008205b0100101b0100101d01001011010010110100101101001011010010") + check("initial SP", struct.unpack(" + +volatile uint32_t grid_deviation = 87; +volatile uint32_t operator_state = 0; +volatile uint32_t dispatch_state = 0; diff --git a/WEEK04/0x0001b_ctf/src/main.c b/WEEK04/0x0001b_ctf/src/main.c new file mode 100644 index 0000000..87671bd --- /dev/null +++ b/WEEK04/0x0001b_ctf/src/main.c @@ -0,0 +1,56 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: main.c +// Desc: Main entry point for the Operation Black Start CTF relay firmware. +// Created: 2026 + +#include "console.h" +#include "grid.h" +#include "pico/stdlib.h" + +/** + * @brief Run the recurring UART evidence stream for the isolated CTF image. + * + * Initializes the standard I/O subsystems, anchors the quarantined dispatch + * frame in flash memory, evaluates the frozen telemetry against the compiled + * safety threshold, prints the startup banner, and repeatedly emits the + * system status report every second. + * + * @param None. + * @return int Standard exit code (never reached in normal firmware execution). + */ +int main(void) +{ + stdio_init_all(); + retain_dispatch_frame(); + evaluate_grid(); + print_boot_banner(); + while (true) { + print_status(); + sleep_ms(1000); + } + return 0; +} diff --git a/WEEK04/0x0001b_ctf/uf2families.json b/WEEK04/0x0001b_ctf/uf2families.json new file mode 100644 index 0000000..91d99ad --- /dev/null +++ b/WEEK04/0x0001b_ctf/uf2families.json @@ -0,0 +1,22 @@ +[ + { + "short_name": "RP2040", + "id": "0xe48bff56", + "description": "Raspberry Pi RP2040" + }, + { + "short_name": "RP2350-ARM-S", + "id": "0xe48bff59", + "description": "Raspberry Pi RP2350, ARM, Secure" + }, + { + "short_name": "RP2350-ARM-NS", + "id": "0xe48bff5a", + "description": "Raspberry Pi RP2350, ARM, Non-Secure" + }, + { + "short_name": "RP2350-RISCV", + "id": "0xe48bff5b", + "description": "Raspberry Pi RP2350, RISC-V" + } +] diff --git a/WEEK04/0x0005_intro-to-variables/.gitignore b/WEEK04/0x0005_intro-to-variables/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/c_cpp_properties.json b/WEEK04/0x0005_intro-to-variables/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/cmake-kits.json b/WEEK04/0x0005_intro-to-variables/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/extensions.json b/WEEK04/0x0005_intro-to-variables/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/launch.json b/WEEK04/0x0005_intro-to-variables/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/settings.json b/WEEK04/0x0005_intro-to-variables/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0005_intro-to-variables/.vscode/tasks.json b/WEEK04/0x0005_intro-to-variables/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0005_intro-to-variables/0x0005_intro-to-variables.c b/WEEK04/0x0005_intro-to-variables/0x0005_intro-to-variables.c new file mode 100644 index 0000000..7b2b3ae --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/0x0005_intro-to-variables.c @@ -0,0 +1,13 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + uint8_t age = 42; + + age = 43; + + stdio_init_all(); + + while (true) + printf("age: %d\r\n", age); +} diff --git a/WEEK04/0x0005_intro-to-variables/CMakeLists.txt b/WEEK04/0x0005_intro-to-variables/CMakeLists.txt new file mode 100644 index 0000000..673ff61 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0005_intro-to-variables C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0005_intro-to-variables 0x0005_intro-to-variables.c ) + +pico_set_program_name(0x0005_intro-to-variables "0x0005_intro-to-variables") +pico_set_program_version(0x0005_intro-to-variables "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0005_intro-to-variables 1) +pico_enable_stdio_usb(0x0005_intro-to-variables 0) + +# Add the standard library to the build +target_link_libraries(0x0005_intro-to-variables + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0005_intro-to-variables PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0005_intro-to-variables) + diff --git a/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables-h.bin b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables-h.bin new file mode 100644 index 0000000..3b71788 Binary files /dev/null and b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables-h.bin differ diff --git a/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin new file mode 100755 index 0000000..32060c4 Binary files /dev/null and b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin differ diff --git a/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bndb b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bndb new file mode 100644 index 0000000..57f7b59 Binary files /dev/null and b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bndb differ diff --git a/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.dis b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.dis new file mode 100644 index 0000000..a5e2707 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.dis @@ -0,0 +1,5737 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0005_intro-to-variables/build/0x0005_intro-to-variables.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000349c 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001b8 100034a0 100034a0 000044a0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003658 10003658 00004658 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003660 10003660 00004660 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005bbc 2**0 + CONTENTS + 6 .data 0000051c 20000110 1000368c 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005bbc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003ba8 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003ba8 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005bbc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005bbc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003ba8 10003ba8 00005ba8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005bbc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005bf0 2**0 + CONTENTS, READONLY + 17 .debug_info 00020702 00000000 00000000 00005c35 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005554 00000000 00000000 00026337 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0000fff5 00000000 00000000 0002b88b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000be8 00000000 00000000 0003b880 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 0000303d 00000000 00000000 0003c468 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000159cb 00000000 00000000 0003f4a5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005719 00000000 00000000 00054e70 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f38 00000000 00000000 0005a58c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c0 00000000 00000000 0005c4c4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0005_intro-to-variables/build/0x0005_intro-to-variables.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003660 .word 0x10003660 +1000012c: 1000368c .word 0x1000368c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003a70 .word 0x00003a70 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 1000368c .word 0x1000368c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003ba8 .word 0x10003ba8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003ba8 .word 0x10003ba8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002d05 .word 0x10002d05 +100001dc: 10000235 .word 0x10000235 +100001e0: 10002cfd .word 0x10002cfd + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 1000349c .word 0x1000349c + +10000234
: +10000234: b508 push {r3, lr} +10000236: f002 fe8d bl 10002f54 +1000023a: 212b movs r1, #43 @ 0x2b +1000023c: 4801 ldr r0, [pc, #4] @ (10000244 ) +1000023e: f002 ff51 bl 100030e4 <__wrap_printf> +10000242: e7fa b.n 1000023a +10000244: 100034a0 .word 0x100034a0 + +10000248 : +10000248: b410 push {r4} +1000024a: f44f 7480 mov.w r4, #256 @ 0x100 +1000024e: 4b0c ldr r3, [pc, #48] @ (10000280 ) +10000250: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000254: eb03 0380 add.w r3, r3, r0, lsl #2 +10000258: 00c0 lsls r0, r0, #3 +1000025a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000025e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000262: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000266: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000026a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000026e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000272: f8cc 2000 str.w r2, [ip] +10000276: 6041 str r1, [r0, #4] +10000278: 601c str r4, [r3, #0] +1000027a: f85d 4b04 ldr.w r4, [sp], #4 +1000027e: 4770 bx lr +10000280: 40038004 .word 0x40038004 + +10000284 : +10000284: b40f push {r0, r1, r2, r3} +10000286: b500 push {lr} +10000288: b083 sub sp, #12 +1000028a: 9c04 ldr r4, [sp, #16] +1000028c: 4807 ldr r0, [pc, #28] @ (100002ac ) +1000028e: f002 fea9 bl 10002fe4 <__wrap_puts> +10000292: b13c cbz r4, 100002a4 +10000294: a905 add r1, sp, #20 +10000296: 4620 mov r0, r4 +10000298: 9101 str r1, [sp, #4] +1000029a: f002 fd15 bl 10002cc8 +1000029e: 4804 ldr r0, [pc, #16] @ (100002b0 ) +100002a0: f002 fea0 bl 10002fe4 <__wrap_puts> +100002a4: 2001 movs r0, #1 +100002a6: f002 fd27 bl 10002cf8 <_exit> +100002aa: bf00 nop +100002ac: 100034ac .word 0x100034ac +100002b0: 100034a8 .word 0x100034a8 + +100002b4 : +100002b4: b570 push {r4, r5, r6, lr} +100002b6: 4686 mov lr, r0 +100002b8: f3ef 8510 mrs r5, PRIMASK +100002bc: b672 cpsid i +100002be: 4c12 ldr r4, [pc, #72] @ (10000308 ) +100002c0: e8d4 6fcf ldaexb r6, [r4] +100002c4: 2001 movs r0, #1 +100002c6: 2e00 cmp r6, #0 +100002c8: d1fa bne.n 100002c0 +100002ca: e8c4 0f46 strexb r6, r0, [r4] +100002ce: 2e00 cmp r6, #0 +100002d0: d1f6 bne.n 100002c0 +100002d2: f3bf 8f5f dmb sy +100002d6: f04f 0c01 mov.w ip, #1 +100002da: 08c8 lsrs r0, r1, #3 +100002dc: f001 0307 and.w r3, r1, #7 +100002e0: fa0c f303 lsl.w r3, ip, r3 +100002e4: f81e c000 ldrb.w ip, [lr, r0] +100002e8: ea1c 0603 ands.w r6, ip, r3 +100002ec: d108 bne.n 10000300 +100002ee: ea4c 0c03 orr.w ip, ip, r3 +100002f2: f80e c000 strb.w ip, [lr, r0] +100002f6: e8c4 6f8f stlb r6, [r4] +100002fa: f385 8810 msr PRIMASK, r5 +100002fe: bd70 pop {r4, r5, r6, pc} +10000300: 4610 mov r0, r2 +10000302: f7ff ffbf bl 10000284 +10000306: bf00 nop +10000308: 200007bb .word 0x200007bb + +1000030c : +1000030c: 4a04 ldr r2, [pc, #16] @ (10000320 ) +1000030e: 7810 ldrb r0, [r2, #0] +10000310: 1c43 adds r3, r0, #1 +10000312: b2db uxtb r3, r3 +10000314: 2b18 cmp r3, #24 +10000316: bf28 it cs +10000318: 2310 movcs r3, #16 +1000031a: 7013 strb r3, [r2, #0] +1000031c: 4770 bx lr +1000031e: bf00 nop +10000320: 200005a8 .word 0x200005a8 + +10000324 : +10000324: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000328: 6893 ldr r3, [r2, #8] +1000032a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000032e: 6093 str r3, [r2, #8] +10000330: 4770 bx lr +10000332: bf00 nop + +10000334 : +10000334: 2100 movs r1, #0 +10000336: 4b04 ldr r3, [pc, #16] @ (10000348 ) +10000338: f103 0220 add.w r2, r3, #32 +1000033c: e8c3 1f8f stlb r1, [r3] +10000340: 3301 adds r3, #1 +10000342: 4293 cmp r3, r2 +10000344: d1fa bne.n 1000033c +10000346: 4770 bx lr +10000348: 200007b0 .word 0x200007b0 + +1000034c : +1000034c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000350: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000354: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000358: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000035c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000360: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000364: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000368: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000036c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000370: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000374: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000378: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000037c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000380: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000384: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000388: b662 cpsie i +1000038a: 4770 bx lr + +1000038c : +1000038c: 2301 movs r3, #1 +1000038e: f000 021f and.w r2, r0, #31 +10000392: 4093 lsls r3, r2 +10000394: 0940 lsrs r0, r0, #5 +10000396: b141 cbz r1, 100003aa +10000398: 0080 lsls r0, r0, #2 +1000039a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000039e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003a2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003a6: 6003 str r3, [r0, #0] +100003a8: 4770 bx lr +100003aa: 4a02 ldr r2, [pc, #8] @ (100003b4 ) +100003ac: 3020 adds r0, #32 +100003ae: f842 3020 str.w r3, [r2, r0, lsl #2] +100003b2: 4770 bx lr +100003b4: e000e100 .word 0xe000e100 + +100003b8 : +100003b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ba: 460d mov r5, r1 +100003bc: f3ef 8710 mrs r7, PRIMASK +100003c0: b672 cpsid i +100003c2: 4e12 ldr r6, [pc, #72] @ (1000040c ) +100003c4: e8d6 2fcf ldaexb r2, [r6] +100003c8: 2301 movs r3, #1 +100003ca: 2a00 cmp r2, #0 +100003cc: d1fa bne.n 100003c4 +100003ce: e8c6 3f42 strexb r2, r3, [r6] +100003d2: 2a00 cmp r2, #0 +100003d4: d1f6 bne.n 100003c4 +100003d6: f3bf 8f5f dmb sy +100003da: 4b0d ldr r3, [pc, #52] @ (10000410 ) +100003dc: f100 0410 add.w r4, r0, #16 +100003e0: 689b ldr r3, [r3, #8] +100003e2: 4a0c ldr r2, [pc, #48] @ (10000414 ) +100003e4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003e8: 4293 cmp r3, r2 +100003ea: d003 beq.n 100003f4 +100003ec: 4299 cmp r1, r3 +100003ee: d001 beq.n 100003f4 +100003f0: f000 fe8e bl 10001110 +100003f4: 4b06 ldr r3, [pc, #24] @ (10000410 ) +100003f6: 689b ldr r3, [r3, #8] +100003f8: f843 5024 str.w r5, [r3, r4, lsl #2] +100003fc: f3bf 8f5f dmb sy +10000400: 2300 movs r3, #0 +10000402: e8c6 3f8f stlb r3, [r6] +10000406: f387 8810 msr PRIMASK, r7 +1000040a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000040c: 200007b9 .word 0x200007b9 +10000410: e000ed00 .word 0xe000ed00 +10000414: 10000111 .word 0x10000111 + +10000418 : +10000418: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000041c: b083 sub sp, #12 +1000041e: f3ef 8a10 mrs sl, PRIMASK +10000422: b672 cpsid i +10000424: 4e71 ldr r6, [pc, #452] @ (100005ec ) +10000426: e8d6 2fcf ldaexb r2, [r6] +1000042a: 2301 movs r3, #1 +1000042c: 2a00 cmp r2, #0 +1000042e: d1fa bne.n 10000426 +10000430: e8c6 3f42 strexb r2, r3, [r6] +10000434: 2a00 cmp r2, #0 +10000436: d1f6 bne.n 10000426 +10000438: f3bf 8f5f dmb sy +1000043c: 4b6c ldr r3, [pc, #432] @ (100005f0 ) +1000043e: f100 0810 add.w r8, r0, #16 +10000442: 689b ldr r3, [r3, #8] +10000444: 4a6b ldr r2, [pc, #428] @ (100005f4 ) +10000446: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000044a: 4295 cmp r5, r2 +1000044c: d045 beq.n 100004da +1000044e: 428d cmp r5, r1 +10000450: 460c mov r4, r1 +10000452: d050 beq.n 100004f6 +10000454: 4f68 ldr r7, [pc, #416] @ (100005f8 ) +10000456: 1beb subs r3, r5, r7 +10000458: 2b2f cmp r3, #47 @ 0x2f +1000045a: d83e bhi.n 100004da +1000045c: 2101 movs r1, #1 +1000045e: ea4f 1950 mov.w r9, r0, lsr #5 +10000462: ea4f 0989 mov.w r9, r9, lsl #2 +10000466: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000046a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000046e: f000 031f and.w r3, r0, #31 +10000472: fa01 f003 lsl.w r0, r1, r3 +10000476: f8d9 3000 ldr.w r3, [r9] +1000047a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000047e: ea00 0b03 and.w fp, r0, r3 +10000482: f3bf 8f5f dmb sy +10000486: f3ef 8105 mrs r1, IPSR +1000048a: b2c9 uxtb r1, r1 +1000048c: 2900 cmp r1, #0 +1000048e: d034 beq.n 100004fa +10000490: 4588 cmp r8, r1 +10000492: d005 beq.n 100004a0 +10000494: e9cd 1000 strd r1, r0, [sp] +10000498: f000 fe3a bl 10001110 +1000049c: e9dd 1000 ldrd r1, r0, [sp] +100004a0: f025 0e01 bic.w lr, r5, #1 +100004a4: f8de c008 ldr.w ip, [lr, #8] +100004a8: 4564 cmp r4, ip +100004aa: d105 bne.n 100004b8 +100004ac: e089 b.n 100005c2 +100004ae: f8d3 c008 ldr.w ip, [r3, #8] +100004b2: 4564 cmp r4, ip +100004b4: d031 beq.n 1000051a +100004b6: 469e mov lr, r3 +100004b8: f99e 2006 ldrsb.w r2, [lr, #6] +100004bc: eb02 0342 add.w r3, r2, r2, lsl #1 +100004c0: 2a00 cmp r2, #0 +100004c2: eb07 0383 add.w r3, r7, r3, lsl #2 +100004c6: daf2 bge.n 100004ae +100004c8: 4564 cmp r4, ip +100004ca: d061 beq.n 10000590 +100004cc: f1bb 0f00 cmp.w fp, #0 +100004d0: d020 beq.n 10000514 +100004d2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004d6: f8c9 0000 str.w r0, [r9] +100004da: 4b45 ldr r3, [pc, #276] @ (100005f0 ) +100004dc: 689b ldr r3, [r3, #8] +100004de: f843 5028 str.w r5, [r3, r8, lsl #2] +100004e2: f3bf 8f5f dmb sy +100004e6: 2300 movs r3, #0 +100004e8: e8c6 3f8f stlb r3, [r6] +100004ec: f38a 8810 msr PRIMASK, sl +100004f0: b003 add sp, #12 +100004f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100004f6: 4615 mov r5, r2 +100004f8: e7ef b.n 100004da +100004fa: f025 0e01 bic.w lr, r5, #1 +100004fe: f8de c008 ldr.w ip, [lr, #8] +10000502: 4564 cmp r4, ip +10000504: d1d8 bne.n 100004b8 +10000506: f99e 4006 ldrsb.w r4, [lr, #6] +1000050a: 4673 mov r3, lr +1000050c: 2c00 cmp r4, #0 +1000050e: da08 bge.n 10000522 +10000510: 4615 mov r5, r2 +10000512: e046 b.n 100005a2 +10000514: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000518: e7df b.n 100004da +1000051a: f993 4006 ldrsb.w r4, [r3, #6] +1000051e: 2c00 cmp r4, #0 +10000520: db37 blt.n 10000592 +10000522: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000526: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000052a: f89c 1007 ldrb.w r1, [ip, #7] +1000052e: f8dc 2008 ldr.w r2, [ip, #8] +10000532: 71d9 strb r1, [r3, #7] +10000534: 609a str r2, [r3, #8] +10000536: f99c 2006 ldrsb.w r2, [ip, #6] +1000053a: 0061 lsls r1, r4, #1 +1000053c: 2a00 cmp r2, #0 +1000053e: 719a strb r2, [r3, #6] +10000540: db3d blt.n 100005be +10000542: f8bc e004 ldrh.w lr, [ip, #4] +10000546: ea5f 5e4e movs.w lr, lr, lsl #21 +1000054a: d505 bpl.n 10000558 +1000054c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000550: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000554: f10e 0e1f add.w lr, lr, #31 +10000558: f06f 0c07 mvn.w ip, #7 +1000055c: 190a adds r2, r1, r4 +1000055e: ea4f 5e6e mov.w lr, lr, asr #21 +10000562: 0092 lsls r2, r2, #2 +10000564: eb02 024e add.w r2, r2, lr, lsl #1 +10000568: 3208 adds r2, #8 +1000056a: 443a add r2, r7 +1000056c: ebac 0c03 sub.w ip, ip, r3 +10000570: 4462 add r2, ip +10000572: f3c2 024a ubfx r2, r2, #1, #11 +10000576: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000057a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000057e: 809a strh r2, [r3, #4] +10000580: 4b1e ldr r3, [pc, #120] @ (100005fc ) +10000582: 4421 add r1, r4 +10000584: 781a ldrb r2, [r3, #0] +10000586: eb07 0181 add.w r1, r7, r1, lsl #2 +1000058a: 701c strb r4, [r3, #0] +1000058c: 718a strb r2, [r1, #6] +1000058e: e79d b.n 100004cc +10000590: 4673 mov r3, lr +10000592: b9d9 cbnz r1, 100005cc +10000594: 22ff movs r2, #255 @ 0xff +10000596: f88e 2006 strb.w r2, [lr, #6] +1000059a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000059e: f8ae 2004 strh.w r2, [lr, #4] +100005a2: 4c16 ldr r4, [pc, #88] @ (100005fc ) +100005a4: f64a 22aa movw r2, #43690 @ 0xaaaa +100005a8: f894 c000 ldrb.w ip, [r4] +100005ac: 4619 mov r1, r3 +100005ae: 1bc9 subs r1, r1, r7 +100005b0: 4149 adcs r1, r1 +100005b2: 434a muls r2, r1 +100005b4: 0d12 lsrs r2, r2, #20 +100005b6: f883 c006 strb.w ip, [r3, #6] +100005ba: 7022 strb r2, [r4, #0] +100005bc: e786 b.n 100004cc +100005be: 4a10 ldr r2, [pc, #64] @ (10000600 ) +100005c0: e7dd b.n 1000057e +100005c2: f99e 4006 ldrsb.w r4, [lr, #6] +100005c6: 4673 mov r3, lr +100005c8: 2c00 cmp r4, #0 +100005ca: daaa bge.n 10000522 +100005cc: 4a0d ldr r2, [pc, #52] @ (10000604 ) +100005ce: 4c0e ldr r4, [pc, #56] @ (10000608 ) +100005d0: 1ad2 subs r2, r2, r3 +100005d2: 3a08 subs r2, #8 +100005d4: f3c2 310a ubfx r1, r2, #12, #11 +100005d8: ea6f 5101 mvn.w r1, r1, lsl #20 +100005dc: ea6f 5111 mvn.w r1, r1, lsr #20 +100005e0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005e4: 80da strh r2, [r3, #6] +100005e6: 8099 strh r1, [r3, #4] +100005e8: e770 b.n 100004cc +100005ea: bf00 nop +100005ec: 200007b9 .word 0x200007b9 +100005f0: e000ed00 .word 0xe000ed00 +100005f4: 10000111 .word 0x10000111 +100005f8: 200005ac .word 0x200005ac +100005fc: 20000854 .word 0x20000854 +10000600: ffffbd01 .word 0xffffbd01 +10000604: 200005e6 .word 0x200005e6 +10000608: fffff800 .word 0xfffff800 + +1000060c : +1000060c: b5f0 push {r4, r5, r6, r7, lr} +1000060e: f3ef 8505 mrs r5, IPSR +10000612: b2ed uxtb r5, r5 +10000614: f3ef 8c10 mrs ip, PRIMASK +10000618: b672 cpsid i +1000061a: 4926 ldr r1, [pc, #152] @ (100006b4 ) +1000061c: e8d1 2fcf ldaexb r2, [r1] +10000620: 2301 movs r3, #1 +10000622: 2a00 cmp r2, #0 +10000624: d1fa bne.n 1000061c +10000626: e8c1 3f42 strexb r2, r3, [r1] +1000062a: 2a00 cmp r2, #0 +1000062c: d1f6 bne.n 1000061c +1000062e: f3bf 8f5f dmb sy +10000632: 4e21 ldr r6, [pc, #132] @ (100006b8 ) +10000634: f040 0e01 orr.w lr, r0, #1 +10000638: 68b4 ldr r4, [r6, #8] +1000063a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000063e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000642: 4a1e ldr r2, [pc, #120] @ (100006bc ) +10000644: 4604 mov r4, r0 +10000646: 1aa4 subs r4, r4, r2 +10000648: 4164 adcs r4, r4 +1000064a: 4363 muls r3, r4 +1000064c: 0d1b lsrs r3, r3, #20 +1000064e: 4577 cmp r7, lr +10000650: b25b sxtb r3, r3 +10000652: d01b beq.n 1000068c +10000654: f992 4006 ldrsb.w r4, [r2, #6] +10000658: 429c cmp r4, r3 +1000065a: d01c beq.n 10000696 +1000065c: f992 4012 ldrsb.w r4, [r2, #18] +10000660: 429c cmp r4, r3 +10000662: d023 beq.n 100006ac +10000664: f992 401e ldrsb.w r4, [r2, #30] +10000668: 429c cmp r4, r3 +1000066a: d021 beq.n 100006b0 +1000066c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000670: 429c cmp r4, r3 +10000672: bf08 it eq +10000674: 2403 moveq r4, #3 +10000676: d00f beq.n 10000698 +10000678: 4a11 ldr r2, [pc, #68] @ (100006c0 ) +1000067a: 2400 movs r4, #0 +1000067c: 7815 ldrb r5, [r2, #0] +1000067e: 7013 strb r3, [r2, #0] +10000680: 7185 strb r5, [r0, #6] +10000682: e8c1 4f8f stlb r4, [r1] +10000686: f38c 8810 msr PRIMASK, ip +1000068a: bdf0 pop {r4, r5, r6, r7, pc} +1000068c: 68b2 ldr r2, [r6, #8] +1000068e: 4c0d ldr r4, [pc, #52] @ (100006c4 ) +10000690: f842 4025 str.w r4, [r2, r5, lsl #2] +10000694: e7f0 b.n 10000678 +10000696: 2400 movs r4, #0 +10000698: eb04 0444 add.w r4, r4, r4, lsl #1 +1000069c: eb02 0284 add.w r2, r2, r4, lsl #2 +100006a0: 24ff movs r4, #255 @ 0xff +100006a2: 7194 strb r4, [r2, #6] +100006a4: f64b 5401 movw r4, #48385 @ 0xbd01 +100006a8: 8094 strh r4, [r2, #4] +100006aa: e7e5 b.n 10000678 +100006ac: 2401 movs r4, #1 +100006ae: e7f3 b.n 10000698 +100006b0: 2402 movs r4, #2 +100006b2: e7f1 b.n 10000698 +100006b4: 200007b9 .word 0x200007b9 +100006b8: e000ed00 .word 0xe000ed00 +100006bc: 200005ac .word 0x200005ac +100006c0: 20000854 .word 0x20000854 +100006c4: 10000111 .word 0x10000111 + +100006c8 : +100006c8: 4b01 ldr r3, [pc, #4] @ (100006d0 ) +100006ca: 440b add r3, r1 +100006cc: 6003 str r3, [r0, #0] +100006ce: 4770 bx lr +100006d0: 200007b0 .word 0x200007b0 + +100006d4 : +100006d4: b570 push {r4, r5, r6, lr} +100006d6: 4c10 ldr r4, [pc, #64] @ (10000718 ) +100006d8: 4d10 ldr r5, [pc, #64] @ (1000071c ) +100006da: 42ac cmp r4, r5 +100006dc: d20e bcs.n 100006fc +100006de: 26ff movs r6, #255 @ 0xff +100006e0: 6823 ldr r3, [r4, #0] +100006e2: b163 cbz r3, 100006fe +100006e4: f7ff fe12 bl 1000030c +100006e8: 4601 mov r1, r0 +100006ea: 4620 mov r0, r4 +100006ec: f7ff ffec bl 100006c8 +100006f0: 80a6 strh r6, [r4, #4] +100006f2: f3bf 8f5f dmb sy +100006f6: 3408 adds r4, #8 +100006f8: 42ac cmp r4, r5 +100006fa: d3f1 bcc.n 100006e0 +100006fc: bd70 pop {r4, r5, r6, pc} +100006fe: f7ff fe05 bl 1000030c +10000702: 4601 mov r1, r0 +10000704: 4620 mov r0, r4 +10000706: f7ff ffdf bl 100006c8 +1000070a: 7126 strb r6, [r4, #4] +1000070c: f3bf 8f5f dmb sy +10000710: 3408 adds r4, #8 +10000712: 42ac cmp r4, r5 +10000714: d3e4 bcc.n 100006e0 +10000716: bd70 pop {r4, r5, r6, pc} +10000718: 20000624 .word 0x20000624 +1000071c: 2000062c .word 0x2000062c + +10000720 : +10000720: 4b0d ldr r3, [pc, #52] @ (10000758 ) +10000722: 681a ldr r2, [r3, #0] +10000724: f3ef 8110 mrs r1, PRIMASK +10000728: b672 cpsid i +1000072a: e8d2 cfcf ldaexb ip, [r2] +1000072e: 2001 movs r0, #1 +10000730: f1bc 0f00 cmp.w ip, #0 +10000734: d1f9 bne.n 1000072a +10000736: e8c2 0f4c strexb ip, r0, [r2] +1000073a: f1bc 0f00 cmp.w ip, #0 +1000073e: d1f4 bne.n 1000072a +10000740: f3bf 8f5f dmb sy +10000744: 2200 movs r2, #0 +10000746: 681b ldr r3, [r3, #0] +10000748: e8c3 2f8f stlb r2, [r3] +1000074c: f381 8810 msr PRIMASK, r1 +10000750: bf40 sev +10000752: 2000 movs r0, #0 +10000754: 2100 movs r1, #0 +10000756: 4770 bx lr +10000758: 20000848 .word 0x20000848 +1000075c: 00000000 .word 0x00000000 + +10000760 : +10000760: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000764: ed2d 8b02 vpush {d8} +10000768: b085 sub sp, #20 +1000076a: f3ef 8305 mrs r3, IPSR +1000076e: b2db uxtb r3, r3 +10000770: 3b10 subs r3, #16 +10000772: 089a lsrs r2, r3, #2 +10000774: bf18 it ne +10000776: 2201 movne r2, #1 +10000778: f04f 0101 mov.w r1, #1 +1000077c: f003 0b03 and.w fp, r3, #3 +10000780: bf18 it ne +10000782: 4daf ldrne r5, [pc, #700] @ (10000a40 ) +10000784: 4baf ldr r3, [pc, #700] @ (10000a44 ) +10000786: bf08 it eq +10000788: 4daf ldreq r5, [pc, #700] @ (10000a48 ) +1000078a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000078e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000792: fa01 f20b lsl.w r2, r1, fp +10000796: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000079a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a38 +1000079e: 9201 str r2, [sp, #4] +100007a0: 605a str r2, [r3, #4] +100007a2: e02f b.n 10000804 +100007a4: 88b3 ldrh r3, [r6, #4] +100007a6: 041c lsls r4, r3, #16 +100007a8: f140 8093 bpl.w 100008d2 +100007ac: 79b3 ldrb r3, [r6, #6] +100007ae: 2b00 cmp r3, #0 +100007b0: f040 80dd bne.w 1000096e +100007b4: f9b6 2008 ldrsh.w r2, [r6, #8] +100007b8: 2a00 cmp r2, #0 +100007ba: f2c0 811e blt.w 100009fa +100007be: 6973 ldr r3, [r6, #20] +100007c0: eb02 0242 add.w r2, r2, r2, lsl #1 +100007c4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007c8: e9d3 4702 ldrd r4, r7, [r3, #8] +100007cc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007d0: bf08 it eq +100007d2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007d6: d00e beq.n 100007f6 +100007d8: eb05 018b add.w r1, r5, fp, lsl #2 +100007dc: 6aab ldr r3, [r5, #40] @ 0x28 +100007de: 690a ldr r2, [r1, #16] +100007e0: 1ad2 subs r2, r2, r3 +100007e2: 1ae3 subs r3, r4, r3 +100007e4: 4293 cmp r3, r2 +100007e6: d305 bcc.n 100007f4 +100007e8: 2301 movs r3, #1 +100007ea: 6a2a ldr r2, [r5, #32] +100007ec: fa03 f30b lsl.w r3, r3, fp +100007f0: 4213 tst r3, r2 +100007f2: d100 bne.n 100007f6 +100007f4: 610c str r4, [r1, #16] +100007f6: 4628 mov r0, r5 +100007f8: f000 faca bl 10000d90 +100007fc: 42a0 cmp r0, r4 +100007fe: 41b9 sbcs r1, r7 +10000800: f2c0 80fb blt.w 100009fa +10000804: f9b6 3008 ldrsh.w r3, [r6, #8] +10000808: 9a01 ldr r2, [sp, #4] +1000080a: 2b00 cmp r3, #0 +1000080c: 9300 str r3, [sp, #0] +1000080e: 63ea str r2, [r5, #60] @ 0x3c +10000810: dbc8 blt.n 100007a4 +10000812: f8d6 8014 ldr.w r8, [r6, #20] +10000816: eb03 0943 add.w r9, r3, r3, lsl #1 +1000081a: 4628 mov r0, r5 +1000081c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000820: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000824: f000 fab4 bl 10000d90 +10000828: 42a0 cmp r0, r4 +1000082a: eb71 010a sbcs.w r1, r1, sl +1000082e: dbb9 blt.n 100007a4 +10000830: f1ba 0f00 cmp.w sl, #0 +10000834: f2c0 80c3 blt.w 100009be +10000838: e9d7 3104 ldrd r3, r1, [r7, #16] +1000083c: 4a83 ldr r2, [pc, #524] @ (10000a4c ) +1000083e: 4293 cmp r3, r2 +10000840: f000 80ed beq.w 10000a1e +10000844: 887a ldrh r2, [r7, #2] +10000846: f9b6 0008 ldrsh.w r0, [r6, #8] +1000084a: b292 uxth r2, r2 +1000084c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000850: 4798 blx r3 +10000852: 4602 mov r2, r0 +10000854: 460b mov r3, r1 +10000856: ea52 0103 orrs.w r1, r2, r3 +1000085a: f000 80b0 beq.w 100009be +1000085e: 2b00 cmp r3, #0 +10000860: f280 80d1 bge.w 10000a06 +10000864: ebb4 0e02 subs.w lr, r4, r2 +10000868: eb6a 0a03 sbc.w sl, sl, r3 +1000086c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000870: e9c7 ea02 strd lr, sl, [r7, #8] +10000874: 2b00 cmp r3, #0 +10000876: db95 blt.n 100007a4 +10000878: 6971 ldr r1, [r6, #20] +1000087a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000087e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000882: e9d2 7002 ldrd r7, r0, [r2, #8] +10000886: 45be cmp lr, r7 +10000888: eb7a 0c00 sbcs.w ip, sl, r0 +1000088c: ea4f 0243 mov.w r2, r3, lsl #1 +10000890: db88 blt.n 100007a4 +10000892: 46b4 mov ip, r6 +10000894: f82c 3f08 strh.w r3, [ip, #8]! +10000898: e006 b.n 100008a8 +1000089a: eb03 0043 add.w r0, r3, r3, lsl #1 +1000089e: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008a2: 005a lsls r2, r3, #1 +100008a4: e9d0 7002 ldrd r7, r0, [r0, #8] +100008a8: 45be cmp lr, r7 +100008aa: 441a add r2, r3 +100008ac: eb7a 0000 sbcs.w r0, sl, r0 +100008b0: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008b4: db04 blt.n 100008c0 +100008b6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008ba: 46a4 mov ip, r4 +100008bc: 2b00 cmp r3, #0 +100008be: daec bge.n 1000089a +100008c0: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008c4: 9b00 ldr r3, [sp, #0] +100008c6: f8ac 3000 strh.w r3, [ip] +100008ca: 88b3 ldrh r3, [r6, #4] +100008cc: 041c lsls r4, r3, #16 +100008ce: f53f af6d bmi.w 100007ac +100008d2: 6933 ldr r3, [r6, #16] +100008d4: f3ef 8210 mrs r2, PRIMASK +100008d8: b672 cpsid i +100008da: e8d3 0fcf ldaexb r0, [r3] +100008de: 2101 movs r1, #1 +100008e0: 2800 cmp r0, #0 +100008e2: d1fa bne.n 100008da +100008e4: e8c3 1f40 strexb r0, r1, [r3] +100008e8: 2800 cmp r0, #0 +100008ea: d1f6 bne.n 100008da +100008ec: f3bf 8f5f dmb sy +100008f0: f64f 74ff movw r4, #65535 @ 0xffff +100008f4: 88b0 ldrh r0, [r6, #4] +100008f6: 2300 movs r3, #0 +100008f8: 6931 ldr r1, [r6, #16] +100008fa: b200 sxth r0, r0 +100008fc: 80b4 strh r4, [r6, #4] +100008fe: e8c1 3f8f stlb r3, [r1] +10000902: f382 8810 msr PRIMASK, r2 +10000906: 4298 cmp r0, r3 +10000908: f6ff af50 blt.w 100007ac +1000090c: 4607 mov r7, r0 +1000090e: 46a9 mov r9, r5 +10000910: 6974 ldr r4, [r6, #20] +10000912: f106 0808 add.w r8, r6, #8 +10000916: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000091a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000091e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000922: f9b6 3008 ldrsh.w r3, [r6, #8] +10000926: 46c4 mov ip, r8 +10000928: 2b00 cmp r3, #0 +1000092a: db13 blt.n 10000954 +1000092c: 46b2 mov sl, r6 +1000092e: 9700 str r7, [sp, #0] +10000930: e004 b.n 1000093c +10000932: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000936: 4694 mov ip, r2 +10000938: 2b00 cmp r3, #0 +1000093a: db09 blt.n 10000950 +1000093c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000940: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000944: e9d2 7102 ldrd r7, r1, [r2, #8] +10000948: 42bd cmp r5, r7 +1000094a: eb70 0101 sbcs.w r1, r0, r1 +1000094e: daf0 bge.n 10000932 +10000950: 4656 mov r6, sl +10000952: 9f00 ldr r7, [sp, #0] +10000954: f8ac 7000 strh.w r7, [ip] +10000958: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000095c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000960: 2f00 cmp r7, #0 +10000962: dad8 bge.n 10000916 +10000964: 79b3 ldrb r3, [r6, #6] +10000966: 464d mov r5, r9 +10000968: 2b00 cmp r3, #0 +1000096a: f43f af23 beq.w 100007b4 +1000096e: 2300 movs r3, #0 +10000970: 71b3 strb r3, [r6, #6] +10000972: f9b6 3008 ldrsh.w r3, [r6, #8] +10000976: f106 0808 add.w r8, r6, #8 +1000097a: 1c58 adds r0, r3, #1 +1000097c: d03d beq.n 100009fa +1000097e: 461a mov r2, r3 +10000980: 6977 ldr r7, [r6, #20] +10000982: e003 b.n 1000098c +10000984: 4680 mov r8, r0 +10000986: 1c59 adds r1, r3, #1 +10000988: f43f af16 beq.w 100007b8 +1000098c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000990: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000994: f8b0 c002 ldrh.w ip, [r0, #2] +10000998: 461c mov r4, r3 +1000099a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +1000099e: 469e mov lr, r3 +100009a0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009a4: d0ee beq.n 10000984 +100009a6: 4294 cmp r4, r2 +100009a8: ed80 8b02 vstr d8, [r0, #8] +100009ac: d005 beq.n 100009ba +100009ae: f8a8 3000 strh.w r3, [r8] +100009b2: 8932 ldrh r2, [r6, #8] +100009b4: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009b8: 8134 strh r4, [r6, #8] +100009ba: 4672 mov r2, lr +100009bc: e7e3 b.n 10000986 +100009be: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009c2: 8133 strh r3, [r6, #8] +100009c4: 6933 ldr r3, [r6, #16] +100009c6: f3ef 8210 mrs r2, PRIMASK +100009ca: b672 cpsid i +100009cc: e8d3 0fcf ldaexb r0, [r3] +100009d0: 2101 movs r1, #1 +100009d2: 2800 cmp r0, #0 +100009d4: d1fa bne.n 100009cc +100009d6: e8c3 1f40 strexb r0, r1, [r3] +100009da: 2800 cmp r0, #0 +100009dc: d1f6 bne.n 100009cc +100009de: f3bf 8f5f dmb sy +100009e2: 8873 ldrh r3, [r6, #2] +100009e4: 6931 ldr r1, [r6, #16] +100009e6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009ea: 9b00 ldr r3, [sp, #0] +100009ec: 8073 strh r3, [r6, #2] +100009ee: 2300 movs r3, #0 +100009f0: e8c1 3f8f stlb r3, [r1] +100009f4: f382 8810 msr PRIMASK, r2 +100009f8: e6d4 b.n 100007a4 +100009fa: bf40 sev +100009fc: b005 add sp, #20 +100009fe: ecbd 8b02 vpop {d8} +10000a02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a06: 4628 mov r0, r5 +10000a08: e9cd 2302 strd r2, r3, [sp, #8] +10000a0c: f000 f9c0 bl 10000d90 +10000a10: 9a02 ldr r2, [sp, #8] +10000a12: 9b03 ldr r3, [sp, #12] +10000a14: eb10 0e02 adds.w lr, r0, r2 +10000a18: eb43 0a01 adc.w sl, r3, r1 +10000a1c: e726 b.n 1000086c +10000a1e: 4608 mov r0, r1 +10000a20: 690b ldr r3, [r1, #16] +10000a22: 9102 str r1, [sp, #8] +10000a24: 4798 blx r3 +10000a26: 2800 cmp r0, #0 +10000a28: d0c9 beq.n 100009be +10000a2a: 9902 ldr r1, [sp, #8] +10000a2c: e9d1 2300 ldrd r2, r3, [r1] +10000a30: e711 b.n 10000856 +10000a32: bf00 nop +10000a34: f3af 8000 nop.w +10000a38: ffffffff .word 0xffffffff +10000a3c: ffffffff .word 0xffffffff +10000a40: 400b8000 .word 0x400b8000 +10000a44: 20000828 .word 0x20000828 +10000a48: 400b0000 .word 0x400b0000 +10000a4c: 10000761 .word 0x10000761 + +10000a50 : +10000a50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a54: 4c36 ldr r4, [pc, #216] @ (10000b30 ) +10000a56: 6925 ldr r5, [r4, #16] +10000a58: b12d cbz r5, 10000a66 +10000a5a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a5e: 210a movs r1, #10 +10000a60: 4834 ldr r0, [pc, #208] @ (10000b34 ) +10000a62: f7ff be31 b.w 100006c8 +10000a66: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b4c +10000a6a: 2103 movs r1, #3 +10000a6c: 4640 mov r0, r8 +10000a6e: f000 f97d bl 10000d6c +10000a72: 2603 movs r6, #3 +10000a74: f8c4 800c str.w r8, [r4, #12] +10000a78: f7ff fc48 bl 1000030c +10000a7c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a80: 4b2d ldr r3, [pc, #180] @ (10000b38 ) +10000a82: 7026 strb r6, [r4, #0] +10000a84: 4403 add r3, r0 +10000a86: 6123 str r3, [r4, #16] +10000a88: f8dc 3000 ldr.w r3, [ip] +10000a8c: 210f movs r1, #15 +10000a8e: 7063 strb r3, [r4, #1] +10000a90: 6963 ldr r3, [r4, #20] +10000a92: 8061 strh r1, [r4, #2] +10000a94: 831d strh r5, [r3, #24] +10000a96: f04f 0504 mov.w r5, #4 +10000a9a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000a9e: f04f 0505 mov.w r5, #5 +10000aa2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000aa6: f04f 0506 mov.w r5, #6 +10000aaa: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000aae: f04f 0507 mov.w r5, #7 +10000ab2: 210e movs r1, #14 +10000ab4: f64f 72ff movw r2, #65535 @ 0xffff +10000ab8: 2708 movs r7, #8 +10000aba: f04f 0e0a mov.w lr, #10 +10000abe: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000ac2: f04f 0901 mov.w r9, #1 +10000ac6: f04f 0c0c mov.w ip, #12 +10000aca: f04f 0b02 mov.w fp, #2 +10000ace: f04f 0a09 mov.w sl, #9 +10000ad2: 200d movs r0, #13 +10000ad4: f04f 050b mov.w r5, #11 +10000ad8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000adc: 4917 ldr r1, [pc, #92] @ (10000b3c ) +10000ade: 80a2 strh r2, [r4, #4] +10000ae0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000ae4: 60a1 str r1, [r4, #8] +10000ae6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000aea: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000aee: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000af2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000af6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000afa: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000afe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b02: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b06: 801a strh r2, [r3, #0] +10000b08: 4b0d ldr r3, [pc, #52] @ (10000b40 ) +10000b0a: 4630 mov r0, r6 +10000b0c: f8c8 7020 str.w r7, [r8, #32] +10000b10: 490c ldr r1, [pc, #48] @ (10000b44 ) +10000b12: 60dc str r4, [r3, #12] +10000b14: f7ff fc50 bl 100003b8 +10000b18: 4649 mov r1, r9 +10000b1a: 4630 mov r0, r6 +10000b1c: f7ff fc36 bl 1000038c +10000b20: 4b09 ldr r3, [pc, #36] @ (10000b48 ) +10000b22: 210a movs r1, #10 +10000b24: 641f str r7, [r3, #64] @ 0x40 +10000b26: 4803 ldr r0, [pc, #12] @ (10000b34 ) +10000b28: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b2c: f7ff bdcc b.w 100006c8 +10000b30: 200005f4 .word 0x200005f4 +10000b34: 20000848 .word 0x20000848 +10000b38: 200007b0 .word 0x200007b0 +10000b3c: 0010ffff .word 0x0010ffff +10000b40: 20000828 .word 0x20000828 +10000b44: 10000761 .word 0x10000761 +10000b48: 400b2000 .word 0x400b2000 +10000b4c: 400b0000 .word 0x400b0000 + +10000b50 : +10000b50: 4601 mov r1, r0 +10000b52: b5f0 push {r4, r5, r6, r7, lr} +10000b54: 6900 ldr r0, [r0, #16] +10000b56: f3ef 8710 mrs r7, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d0 5fcf ldaexb r5, [r0] +10000b60: 2401 movs r4, #1 +10000b62: 2d00 cmp r5, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c0 4f45 strexb r5, r4, [r0] +10000b6a: 2d00 cmp r5, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b76: 694c ldr r4, [r1, #20] +10000b78: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b7c: f1be 0f00 cmp.w lr, #0 +10000b80: ea4f 05cc mov.w r5, ip, lsl #3 +10000b84: 6908 ldr r0, [r1, #16] +10000b86: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b8a: db3c blt.n 10000c06 +10000b8c: 5b66 ldrh r6, [r4, r5] +10000b8e: 804e strh r6, [r1, #2] +10000b90: 2600 movs r6, #0 +10000b92: e8c0 6f8f stlb r6, [r0] +10000b96: f387 8810 msr PRIMASK, r7 +10000b9a: f8bc 0002 ldrh.w r0, [ip, #2] +10000b9e: e9cc 2302 strd r2, r3, [ip, #8] +10000ba2: 3001 adds r0, #1 +10000ba4: f3c0 000e ubfx r0, r0, #0, #15 +10000ba8: 2801 cmp r0, #1 +10000baa: bf38 it cc +10000bac: 2001 movcc r0, #1 +10000bae: 9b05 ldr r3, [sp, #20] +10000bb0: f8ac 0002 strh.w r0, [ip, #2] +10000bb4: f8cc 3010 str.w r3, [ip, #16] +10000bb8: 9b06 ldr r3, [sp, #24] +10000bba: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bbe: f8cc 3014 str.w r3, [ip, #20] +10000bc2: 690b ldr r3, [r1, #16] +10000bc4: f3ef 8210 mrs r2, PRIMASK +10000bc8: b672 cpsid i +10000bca: e8d3 cfcf ldaexb ip, [r3] +10000bce: 2701 movs r7, #1 +10000bd0: f1bc 0f00 cmp.w ip, #0 +10000bd4: d1f9 bne.n 10000bca +10000bd6: e8c3 7f4c strexb ip, r7, [r3] +10000bda: f1bc 0f00 cmp.w ip, #0 +10000bde: d1f4 bne.n 10000bca +10000be0: f3bf 8f5f dmb sy +10000be4: 888b ldrh r3, [r1, #4] +10000be6: 5363 strh r3, [r4, r5] +10000be8: f8a1 e004 strh.w lr, [r1, #4] +10000bec: 690b ldr r3, [r1, #16] +10000bee: e8c3 6f8f stlb r6, [r3] +10000bf2: f382 8810 msr PRIMASK, r2 +10000bf6: 2201 movs r2, #1 +10000bf8: 68cb ldr r3, [r1, #12] +10000bfa: 7809 ldrb r1, [r1, #0] +10000bfc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c00: 408a lsls r2, r1 +10000c02: 605a str r2, [r3, #4] +10000c04: bdf0 pop {r4, r5, r6, r7, pc} +10000c06: 2300 movs r3, #0 +10000c08: e8c0 3f8f stlb r3, [r0] +10000c0c: f387 8810 msr PRIMASK, r7 +10000c10: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c14: bdf0 pop {r4, r5, r6, r7, pc} +10000c16: bf00 nop + +10000c18 : +10000c18: 4603 mov r3, r0 +10000c1a: 8940 ldrh r0, [r0, #10] +10000c1c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c20: dd37 ble.n 10000c92 +10000c22: 6958 ldr r0, [r3, #20] +10000c24: 140a asrs r2, r1, #16 +10000c26: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c2a: b510 push {r4, lr} +10000c2c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c30: 691c ldr r4, [r3, #16] +10000c32: f3ef 8c10 mrs ip, PRIMASK +10000c36: b672 cpsid i +10000c38: e8d4 efcf ldaexb lr, [r4] +10000c3c: 2201 movs r2, #1 +10000c3e: f1be 0f00 cmp.w lr, #0 +10000c42: d1f9 bne.n 10000c38 +10000c44: e8c4 2f4e strexb lr, r2, [r4] +10000c48: f1be 0f00 cmp.w lr, #0 +10000c4c: d1f4 bne.n 10000c38 +10000c4e: f3bf 8f5f dmb sy +10000c52: 8842 ldrh r2, [r0, #2] +10000c54: b289 uxth r1, r1 +10000c56: b292 uxth r2, r2 +10000c58: 428a cmp r2, r1 +10000c5a: d007 beq.n 10000c6c +10000c5c: 2200 movs r2, #0 +10000c5e: 691b ldr r3, [r3, #16] +10000c60: e8c3 2f8f stlb r2, [r3] +10000c64: f38c 8810 msr PRIMASK, ip +10000c68: 2000 movs r0, #0 +10000c6a: bd10 pop {r4, pc} +10000c6c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c70: 8042 strh r2, [r0, #2] +10000c72: 2101 movs r1, #1 +10000c74: 2200 movs r2, #0 +10000c76: 6918 ldr r0, [r3, #16] +10000c78: 7199 strb r1, [r3, #6] +10000c7a: e8c0 2f8f stlb r2, [r0] +10000c7e: f38c 8810 msr PRIMASK, ip +10000c82: 781c ldrb r4, [r3, #0] +10000c84: 68da ldr r2, [r3, #12] +10000c86: 4608 mov r0, r1 +10000c88: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c8c: 40a1 lsls r1, r4 +10000c8e: 6059 str r1, [r3, #4] +10000c90: bd10 pop {r4, pc} +10000c92: 2000 movs r0, #0 +10000c94: 4770 bx lr +10000c96: bf00 nop + +10000c98 : +10000c98: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000c9c: 4606 mov r6, r0 +10000c9e: 460d mov r5, r1 +10000ca0: b083 sub sp, #12 +10000ca2: f3ef 8405 mrs r4, IPSR +10000ca6: b2e4 uxtb r4, r4 +10000ca8: b13c cbz r4, 10000cba +10000caa: 4b2d ldr r3, [pc, #180] @ (10000d60 ) +10000cac: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cae: 42aa cmp r2, r5 +10000cb0: d21c bcs.n 10000cec +10000cb2: 2000 movs r0, #0 +10000cb4: b003 add sp, #12 +10000cb6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cba: 4f2a ldr r7, [pc, #168] @ (10000d64 ) +10000cbc: f8d7 900c ldr.w r9, [r7, #12] +10000cc0: f897 8000 ldrb.w r8, [r7] +10000cc4: 4648 mov r0, r9 +10000cc6: f000 f863 bl 10000d90 +10000cca: f108 0804 add.w r8, r8, #4 +10000cce: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000cd2: 1a1b subs r3, r3, r0 +10000cd4: 1a30 subs r0, r6, r0 +10000cd6: eb65 0101 sbc.w r1, r5, r1 +10000cda: 4298 cmp r0, r3 +10000cdc: f171 0100 sbcs.w r1, r1, #0 +10000ce0: db10 blt.n 10000d04 +10000ce2: bf20 wfe +10000ce4: 4b1e ldr r3, [pc, #120] @ (10000d60 ) +10000ce6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ce8: 42aa cmp r2, r5 +10000cea: d3e2 bcc.n 10000cb2 +10000cec: bf14 ite ne +10000cee: 2401 movne r4, #1 +10000cf0: 2400 moveq r4, #0 +10000cf2: 6a9b ldr r3, [r3, #40] @ 0x28 +10000cf4: 42b3 cmp r3, r6 +10000cf6: bf34 ite cc +10000cf8: 4620 movcc r0, r4 +10000cfa: f044 0001 orrcs.w r0, r4, #1 +10000cfe: b003 add sp, #12 +10000d00: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d04: f000 f84c bl 10000da0 +10000d08: 4286 cmp r6, r0 +10000d0a: eb65 0101 sbc.w r1, r5, r1 +10000d0e: 2900 cmp r1, #0 +10000d10: db14 blt.n 10000d3c +10000d12: 4b15 ldr r3, [pc, #84] @ (10000d68 ) +10000d14: 4638 mov r0, r7 +10000d16: e9cd 3400 strd r3, r4, [sp] +10000d1a: 4632 mov r2, r6 +10000d1c: 462b mov r3, r5 +10000d1e: f7ff ff17 bl 10000b50 +10000d22: 1e01 subs r1, r0, #0 +10000d24: dd0a ble.n 10000d3c +10000d26: 4b0e ldr r3, [pc, #56] @ (10000d60 ) +10000d28: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d2a: 42aa cmp r2, r5 +10000d2c: d316 bcc.n 10000d5c +10000d2e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d30: 42b3 cmp r3, r6 +10000d32: d311 bcc.n 10000d58 +10000d34: 480b ldr r0, [pc, #44] @ (10000d64 ) +10000d36: f7ff ff6f bl 10000c18 +10000d3a: e7b6 b.n 10000caa +10000d3c: 4b08 ldr r3, [pc, #32] @ (10000d60 ) +10000d3e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d40: 42ac cmp r4, r5 +10000d42: d3b6 bcc.n 10000cb2 +10000d44: 1b64 subs r4, r4, r5 +10000d46: bf18 it ne +10000d48: 2401 movne r4, #1 +10000d4a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d4c: 42b3 cmp r3, r6 +10000d4e: bf34 ite cc +10000d50: 4620 movcc r0, r4 +10000d52: f044 0001 orrcs.w r0, r4, #1 +10000d56: e7ad b.n 10000cb4 +10000d58: 42aa cmp r2, r5 +10000d5a: d1eb bne.n 10000d34 +10000d5c: bf20 wfe +10000d5e: e7e9 b.n 10000d34 +10000d60: 400b0000 .word 0x400b0000 +10000d64: 200005f4 .word 0x200005f4 +10000d68: 10000721 .word 0x10000721 + +10000d6c : +10000d6c: b410 push {r4} +10000d6e: 4b05 ldr r3, [pc, #20] @ (10000d84 ) +10000d70: 4c05 ldr r4, [pc, #20] @ (10000d88 ) +10000d72: 4a06 ldr r2, [pc, #24] @ (10000d8c ) +10000d74: 42a0 cmp r0, r4 +10000d76: bf14 ite ne +10000d78: 4618 movne r0, r3 +10000d7a: 1c58 addeq r0, r3, #1 +10000d7c: f85d 4b04 ldr.w r4, [sp], #4 +10000d80: f7ff ba98 b.w 100002b4 +10000d84: 200007d8 .word 0x200007d8 +10000d88: 400b8000 .word 0x400b8000 +10000d8c: 100034bc .word 0x100034bc + +10000d90 : +10000d90: 4603 mov r3, r0 +10000d92: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d94: 460a mov r2, r1 +10000d96: 6a98 ldr r0, [r3, #40] @ 0x28 +10000d98: 6a59 ldr r1, [r3, #36] @ 0x24 +10000d9a: 428a cmp r2, r1 +10000d9c: d1fa bne.n 10000d94 +10000d9e: 4770 bx lr + +10000da0 : +10000da0: 4b03 ldr r3, [pc, #12] @ (10000db0 ) +10000da2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 4291 cmp r1, r2 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr +10000db0: 400b0000 .word 0x400b0000 + +10000db4 : +10000db4: b430 push {r4, r5} +10000db6: 4a15 ldr r2, [pc, #84] @ (10000e0c ) +10000db8: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dba: 469c mov ip, r3 +10000dbc: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dbe: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc0: 4563 cmp r3, ip +10000dc2: d1fa bne.n 10000dba +10000dc4: 1902 adds r2, r0, r4 +10000dc6: 4159 adcs r1, r3 +10000dc8: f04f 0500 mov.w r5, #0 +10000dcc: bf28 it cs +10000dce: 2501 movcs r5, #1 +10000dd0: 4b0e ldr r3, [pc, #56] @ (10000e0c ) +10000dd2: 6a5b ldr r3, [r3, #36] @ 0x24 +10000dd4: b1b5 cbz r5, 10000e04 +10000dd6: 1c5a adds r2, r3, #1 +10000dd8: bf08 it eq +10000dda: 461a moveq r2, r3 +10000ddc: d008 beq.n 10000df0 +10000dde: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000de2: 460a mov r2, r1 +10000de4: 4809 ldr r0, [pc, #36] @ (10000e0c ) +10000de6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000de8: 428b cmp r3, r1 +10000dea: d3fc bcc.n 10000de6 +10000dec: 428b cmp r3, r1 +10000dee: d107 bne.n 10000e00 +10000df0: 4906 ldr r1, [pc, #24] @ (10000e0c ) +10000df2: e002 b.n 10000dfa +10000df4: 6a48 ldr r0, [r1, #36] @ 0x24 +10000df6: 4298 cmp r0, r3 +10000df8: d102 bne.n 10000e00 +10000dfa: 6a88 ldr r0, [r1, #40] @ 0x28 +10000dfc: 4290 cmp r0, r2 +10000dfe: d3f9 bcc.n 10000df4 +10000e00: bc30 pop {r4, r5} +10000e02: 4770 bx lr +10000e04: 4299 cmp r1, r3 +10000e06: d8ed bhi.n 10000de4 +10000e08: e7f0 b.n 10000dec +10000e0a: bf00 nop +10000e0c: 400b0000 .word 0x400b0000 + +10000e10 : +10000e10: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e12: 4605 mov r5, r0 +10000e14: 2006 movs r0, #6 +10000e16: 460e mov r6, r1 +10000e18: f000 f8e4 bl 10000fe4 +10000e1c: 2800 cmp r0, #0 +10000e1e: d042 beq.n 10000ea6 +10000e20: 4a35 ldr r2, [pc, #212] @ (10000ef8 ) +10000e22: 4836 ldr r0, [pc, #216] @ (10000efc ) +10000e24: 4295 cmp r5, r2 +10000e26: bf14 ite ne +10000e28: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e2c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e30: 4b33 ldr r3, [pc, #204] @ (10000f00 ) +10000e32: 4934 ldr r1, [pc, #208] @ (10000f04 ) +10000e34: 6002 str r2, [r0, #0] +10000e36: 601a str r2, [r3, #0] +10000e38: 688c ldr r4, [r1, #8] +10000e3a: ea32 0404 bics.w r4, r2, r4 +10000e3e: d1fb bne.n 10000e38 +10000e40: 4b2d ldr r3, [pc, #180] @ (10000ef8 ) +10000e42: f44f 7180 mov.w r1, #256 @ 0x100 +10000e46: 1aeb subs r3, r5, r3 +10000e48: fab3 f383 clz r3, r3 +10000e4c: 4a2e ldr r2, [pc, #184] @ (10000f08 ) +10000e4e: 095b lsrs r3, r3, #5 +10000e50: 2006 movs r0, #6 +10000e52: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e56: f000 f8c5 bl 10000fe4 +10000e5a: 00c3 lsls r3, r0, #3 +10000e5c: fbb3 f3f6 udiv r3, r3, r6 +10000e60: 3301 adds r3, #1 +10000e62: 09da lsrs r2, r3, #7 +10000e64: d120 bne.n 10000ea8 +10000e66: 2640 movs r6, #64 @ 0x40 +10000e68: 2101 movs r1, #1 +10000e6a: 6269 str r1, [r5, #36] @ 0x24 +10000e6c: 62aa str r2, [r5, #40] @ 0x28 +10000e6e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e70: 07fb lsls r3, r7, #31 +10000e72: d422 bmi.n 10000eba +10000e74: 462b mov r3, r5 +10000e76: 2200 movs r2, #0 +10000e78: f853 1f2c ldr.w r1, [r3, #44]! +10000e7c: 2006 movs r0, #6 +10000e7e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e82: 6022 str r2, [r4, #0] +10000e84: 632f str r7, [r5, #48] @ 0x30 +10000e86: f000 f8ad bl 10000fe4 +10000e8a: f240 3101 movw r1, #769 @ 0x301 +10000e8e: 2203 movs r2, #3 +10000e90: 0080 lsls r0, r0, #2 +10000e92: fbb0 f0f6 udiv r0, r0, r6 +10000e96: 6aeb ldr r3, [r5, #44] @ 0x2c +10000e98: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000e9c: f003 037e and.w r3, r3, #126 @ 0x7e +10000ea0: 6023 str r3, [r4, #0] +10000ea2: 6329 str r1, [r5, #48] @ 0x30 +10000ea4: 64aa str r2, [r5, #72] @ 0x48 +10000ea6: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000ea8: f64f 71fe movw r1, #65534 @ 0xfffe +10000eac: 428a cmp r2, r1 +10000eae: d91b bls.n 10000ee8 +10000eb0: 4622 mov r2, r4 +10000eb2: f64f 71ff movw r1, #65535 @ 0xffff +10000eb6: 4e15 ldr r6, [pc, #84] @ (10000f0c ) +10000eb8: e7d7 b.n 10000e6a +10000eba: f240 3201 movw r2, #769 @ 0x301 +10000ebe: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000ec2: 631a str r2, [r3, #48] @ 0x30 +10000ec4: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ec6: 6aac ldr r4, [r5, #40] @ 0x28 +10000ec8: 2006 movs r0, #6 +10000eca: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ece: f000 f889 bl 10000fe4 +10000ed2: 4b0f ldr r3, [pc, #60] @ (10000f10 ) +10000ed4: 02a4 lsls r4, r4, #10 +10000ed6: fba3 2300 umull r2, r3, r3, r0 +10000eda: 0adb lsrs r3, r3, #11 +10000edc: 2100 movs r1, #0 +10000ede: fbb4 f0f3 udiv r0, r4, r3 +10000ee2: f7ff ff67 bl 10000db4 +10000ee6: e7c5 b.n 10000e74 +10000ee8: f3c3 0345 ubfx r3, r3, #1, #6 +10000eec: 4611 mov r1, r2 +10000eee: eb03 1682 add.w r6, r3, r2, lsl #6 +10000ef2: 461a mov r2, r3 +10000ef4: e7b9 b.n 10000e6a +10000ef6: bf00 nop +10000ef8: 40078000 .word 0x40078000 +10000efc: 40022000 .word 0x40022000 +10000f00: 40023000 .word 0x40023000 +10000f04: 40020000 .word 0x40020000 +10000f08: 2000084c .word 0x2000084c +10000f0c: 003fffc0 .word 0x003fffc0 +10000f10: 8f2b7b75 .word 0x8f2b7b75 + +10000f14 : +10000f14: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f18: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f1c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f20: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f24: b5f0 push {r4, r5, r6, r7, lr} +10000f26: 4616 mov r6, r2 +10000f28: f8dc 2004 ldr.w r2, [ip, #4] +10000f2c: 1f05 subs r5, r0, #4 +10000f2e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f32: bf38 it cc +10000f34: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f38: b2ed uxtb r5, r5 +10000f3a: bf38 it cc +10000f3c: f8cc 2004 strcc.w r2, [ip, #4] +10000f40: 2d01 cmp r5, #1 +10000f42: d92a bls.n 10000f9a +10000f44: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f48: 4c25 ldr r4, [pc, #148] @ (10000fe0 ) +10000f4a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f4e: 6017 str r7, [r2, #0] +10000f50: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f54: b9b2 cbnz r2, 10000f84 +10000f56: f8dc 2000 ldr.w r2, [ip] +10000f5a: 2d01 cmp r5, #1 +10000f5c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f60: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f64: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f68: 6032 str r2, [r6, #0] +10000f6a: d92a bls.n 10000fc2 +10000f6c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f70: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f74: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f78: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f7c: 6011 str r1, [r2, #0] +10000f7e: f8cc 3004 str.w r3, [ip, #4] +10000f82: bdf0 pop {r4, r5, r6, r7, pc} +10000f84: 6967 ldr r7, [r4, #20] +10000f86: fbb7 fef2 udiv lr, r7, r2 +10000f8a: f10e 0e01 add.w lr, lr, #1 +10000f8e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000f92: f1be 0e03 subs.w lr, lr, #3 +10000f96: d2fc bcs.n 10000f92 +10000f98: e7dd b.n 10000f56 +10000f9a: 2901 cmp r1, #1 +10000f9c: d1d2 bne.n 10000f44 +10000f9e: 2403 movs r4, #3 +10000fa0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fa4: 6014 str r4, [r2, #0] +10000fa6: f8dc 2008 ldr.w r2, [ip, #8] +10000faa: 07d2 lsls r2, r2, #31 +10000fac: d5fb bpl.n 10000fa6 +10000fae: f8dc 2000 ldr.w r2, [ip] +10000fb2: 4c0b ldr r4, [pc, #44] @ (10000fe0 ) +10000fb4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fb8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fbc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fc0: 6032 str r2, [r6, #0] +10000fc2: 2201 movs r2, #1 +10000fc4: f8dc 5000 ldr.w r5, [ip] +10000fc8: 404d eors r5, r1 +10000fca: f005 0503 and.w r5, r5, #3 +10000fce: 6035 str r5, [r6, #0] +10000fd0: fa02 f101 lsl.w r1, r2, r1 +10000fd4: f8dc 2008 ldr.w r2, [ip, #8] +10000fd8: 420a tst r2, r1 +10000fda: d0fb beq.n 10000fd4 +10000fdc: e7c6 b.n 10000f6c +10000fde: bf00 nop +10000fe0: 200007dc .word 0x200007dc + +10000fe4 : +10000fe4: 4b01 ldr r3, [pc, #4] @ (10000fec ) +10000fe6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000fea: 4770 bx lr +10000fec: 200007dc .word 0x200007dc + +10000ff0 : +10000ff0: b470 push {r4, r5, r6} +10000ff2: 9d03 ldr r5, [sp, #12] +10000ff4: 6804 ldr r4, [r0, #0] +10000ff6: 032d lsls r5, r5, #12 +10000ff8: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000ffc: 4b1b ldr r3, [pc, #108] @ (1000106c ) +10000ffe: 2c00 cmp r4, #0 +10001000: fbb3 f3f1 udiv r3, r3, r1 +10001004: fbb2 f6f3 udiv r6, r2, r3 +10001008: db1f blt.n 1000104a +1000100a: 4a19 ldr r2, [pc, #100] @ (10001070 ) +1000100c: 4b19 ldr r3, [pc, #100] @ (10001074 ) +1000100e: 4290 cmp r0, r2 +10001010: bf14 ite ne +10001012: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001016: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000101a: 4c17 ldr r4, [pc, #92] @ (10001078 ) +1000101c: 601a str r2, [r3, #0] +1000101e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001022: 601a str r2, [r3, #0] +10001024: 68a3 ldr r3, [r4, #8] +10001026: ea32 0303 bics.w r3, r2, r3 +1000102a: d1fb bne.n 10001024 +1000102c: 2221 movs r2, #33 @ 0x21 +1000102e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001032: 3304 adds r3, #4 +10001034: 6001 str r1, [r0, #0] +10001036: 6086 str r6, [r0, #8] +10001038: 601a str r2, [r3, #0] +1000103a: 6802 ldr r2, [r0, #0] +1000103c: 2a00 cmp r2, #0 +1000103e: dafc bge.n 1000103a +10001040: 2208 movs r2, #8 +10001042: 60c5 str r5, [r0, #12] +10001044: 601a str r2, [r3, #0] +10001046: bc70 pop {r4, r5, r6} +10001048: 4770 bx lr +1000104a: 6803 ldr r3, [r0, #0] +1000104c: f003 033f and.w r3, r3, #63 @ 0x3f +10001050: 428b cmp r3, r1 +10001052: d1da bne.n 1000100a +10001054: 6883 ldr r3, [r0, #8] +10001056: f3c3 030b ubfx r3, r3, #0, #12 +1000105a: 42b3 cmp r3, r6 +1000105c: d1d5 bne.n 1000100a +1000105e: 68c3 ldr r3, [r0, #12] +10001060: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001064: 42ab cmp r3, r5 +10001066: d1d0 bne.n 1000100a +10001068: e7ed b.n 10001046 +1000106a: bf00 nop +1000106c: 00b71b00 .word 0x00b71b00 +10001070: 40058000 .word 0x40058000 +10001074: 40022000 .word 0x40022000 +10001078: 40020000 .word 0x40020000 + +1000107c : +1000107c: 2301 movs r3, #1 +1000107e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001082: 0080 lsls r0, r0, #2 +10001084: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001088: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000108c: 6041 str r1, [r0, #4] +1000108e: 6003 str r3, [r0, #0] +10001090: 4770 bx lr +10001092: bf00 nop + +10001094 : +10001094: 2300 movs r3, #0 +10001096: 8adb ldrh r3, [r3, #22] +10001098: 2200 movs r2, #0 +1000109a: e842 f200 tt r2, r2 +1000109e: 0252 lsls r2, r2, #9 +100010a0: d401 bmi.n 100010a6 +100010a2: 2110 movs r1, #16 +100010a4: 4718 bx r3 +100010a6: 2104 movs r1, #4 +100010a8: 4718 bx r3 +100010aa: bf00 nop + +100010ac : +100010ac: 4a03 ldr r2, [pc, #12] @ (100010bc ) +100010ae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010b2: 2b00 cmp r3, #0 +100010b4: d0fb beq.n 100010ae +100010b6: f3bf 8f5f dmb sy +100010ba: 4770 bx lr +100010bc: 400e0000 .word 0x400e0000 + +100010c0 : +100010c0: 2100 movs r1, #0 +100010c2: 4b04 ldr r3, [pc, #16] @ (100010d4 ) +100010c4: 4a04 ldr r2, [pc, #16] @ (100010d8 ) +100010c6: f3bf 8f5f dmb sy +100010ca: f843 1b04 str.w r1, [r3], #4 +100010ce: 4293 cmp r3, r2 +100010d0: d1f9 bne.n 100010c6 +100010d2: 4770 bx lr +100010d4: 400e080c .word 0x400e080c +100010d8: 400e082c .word 0x400e082c + +100010dc : +100010dc: b410 push {r4} +100010de: f44f 708d mov.w r0, #282 @ 0x11a +100010e2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010e6: 4a06 ldr r2, [pc, #24] @ (10001100 ) +100010e8: 4b06 ldr r3, [pc, #24] @ (10001104 ) +100010ea: 4907 ldr r1, [pc, #28] @ (10001108 ) +100010ec: 6014 str r4, [r2, #0] +100010ee: 60d0 str r0, [r2, #12] +100010f0: 6019 str r1, [r3, #0] +100010f2: 6853 ldr r3, [r2, #4] +100010f4: 2b00 cmp r3, #0 +100010f6: dafc bge.n 100010f2 +100010f8: f85d 4b04 ldr.w r4, [sp], #4 +100010fc: 4770 bx lr +100010fe: bf00 nop +10001100: 40048000 .word 0x40048000 +10001104: 4004a000 .word 0x4004a000 +10001108: 00fab000 .word 0x00fab000 + +1000110c : +1000110c: 4770 bx lr +1000110e: bf00 nop + +10001110 : +10001110: b508 push {r3, lr} +10001112: 4801 ldr r0, [pc, #4] @ (10001118 ) +10001114: f7ff f8b6 bl 10000284 +10001118: 100034e0 .word 0x100034e0 + +1000111c : +1000111c: b538 push {r3, r4, r5, lr} +1000111e: 4c05 ldr r4, [pc, #20] @ (10001134 ) +10001120: 4d05 ldr r5, [pc, #20] @ (10001138 ) +10001122: 42ac cmp r4, r5 +10001124: d204 bcs.n 10001130 +10001126: f854 3b04 ldr.w r3, [r4], #4 +1000112a: 4798 blx r3 +1000112c: 42ac cmp r4, r5 +1000112e: d3fa bcc.n 10001126 +10001130: bd38 pop {r3, r4, r5, pc} +10001132: bf00 nop +10001134: 10003458 .word 0x10003458 +10001138: 10003498 .word 0x10003498 + +1000113c : +1000113c: b410 push {r4} +1000113e: 4807 ldr r0, [pc, #28] @ (1000115c ) +10001140: 4c07 ldr r4, [pc, #28] @ (10001160 ) +10001142: 4b08 ldr r3, [pc, #32] @ (10001164 ) +10001144: 4a08 ldr r2, [pc, #32] @ (10001168 ) +10001146: 4909 ldr r1, [pc, #36] @ (1000116c ) +10001148: 6004 str r4, [r0, #0] +1000114a: 601a str r2, [r3, #0] +1000114c: 688b ldr r3, [r1, #8] +1000114e: ea32 0303 bics.w r3, r2, r3 +10001152: d1fb bne.n 1000114c +10001154: f85d 4b04 ldr.w r4, [sp], #4 +10001158: 4770 bx lr +1000115a: bf00 nop +1000115c: 40022000 .word 0x40022000 +10001160: efef3b7f .word 0xefef3b7f +10001164: 40023000 .word 0x40023000 +10001168: 03f3fff6 .word 0x03f3fff6 +1000116c: 40020000 .word 0x40020000 + +10001170 : +10001170: 4b04 ldr r3, [pc, #16] @ (10001184 ) +10001172: 6cdb ldr r3, [r3, #76] @ 0x4c +10001174: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001178: d103 bne.n 10001182 +1000117a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000117e: 4b02 ldr r3, [pc, #8] @ (10001188 ) +10001180: 64da str r2, [r3, #76] @ 0x4c +10001182: 4770 bx lr +10001184: 50110000 .word 0x50110000 +10001188: 50112000 .word 0x50112000 + +1000118c : +1000118c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001190: 4b04 ldr r3, [pc, #16] @ (100011a4 ) +10001192: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001196: 430b orrs r3, r1 +10001198: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000119c: ee10 0430 dcp_rcmp r0 +100011a0: 4770 bx lr +100011a2: bf00 nop +100011a4: 00300303 .word 0x00300303 + +100011a8 : +100011a8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011ac: 4b04 ldr r3, [pc, #16] @ (100011c0 ) +100011ae: 4a05 ldr r2, [pc, #20] @ (100011c4 ) +100011b0: 6019 str r1, [r3, #0] +100011b2: 6893 ldr r3, [r2, #8] +100011b4: 43db mvns r3, r3 +100011b6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011ba: d1fa bne.n 100011b2 +100011bc: 4770 bx lr +100011be: bf00 nop +100011c0: 40023000 .word 0x40023000 +100011c4: 40020000 .word 0x40020000 + +100011c8 : +100011c8: b510 push {r4, lr} +100011ca: f245 2053 movw r0, #21075 @ 0x5253 +100011ce: f7ff ff61 bl 10001094 +100011d2: e8bd 4010 ldmia.w sp!, {r4, lr} +100011d6: 4603 mov r3, r0 +100011d8: 2004 movs r0, #4 +100011da: 4718 bx r3 + +100011dc : +100011dc: b510 push {r4, lr} +100011de: f245 2053 movw r0, #21075 @ 0x5253 +100011e2: f7ff ff57 bl 10001094 +100011e6: e8bd 4010 ldmia.w sp!, {r4, lr} +100011ea: 4603 mov r3, r0 +100011ec: 2001 movs r0, #1 +100011ee: 4718 bx r3 + +100011f0 : +100011f0: f7ff b8a0 b.w 10000334 + +100011f4 : +100011f4: 4914 ldr r1, [pc, #80] @ (10001248 ) +100011f6: 4b15 ldr r3, [pc, #84] @ (1000124c ) +100011f8: b570 push {r4, r5, r6, lr} +100011fa: 1a5c subs r4, r3, r1 +100011fc: 10a6 asrs r6, r4, #2 +100011fe: 2e44 cmp r6, #68 @ 0x44 +10001200: 4632 mov r2, r6 +10001202: bf28 it cs +10001204: 2244 movcs r2, #68 @ 0x44 +10001206: 4d12 ldr r5, [pc, #72] @ (10001250 ) +10001208: 0092 lsls r2, r2, #2 +1000120a: 4628 mov r0, r5 +1000120c: f002 f872 bl 100032f4 +10001210: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001214: d813 bhi.n 1000123e +10001216: 4a0f ldr r2, [pc, #60] @ (10001254 ) +10001218: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000121c: d012 beq.n 10001244 +1000121e: 192b adds r3, r5, r4 +10001220: 0841 lsrs r1, r0, #1 +10001222: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001226: e9c3 2200 strd r2, r2, [r3] +1000122a: 3308 adds r3, #8 +1000122c: 428b cmp r3, r1 +1000122e: d1fa bne.n 10001226 +10001230: 07c3 lsls r3, r0, #31 +10001232: d504 bpl.n 1000123e +10001234: f020 0001 bic.w r0, r0, #1 +10001238: 4430 add r0, r6 +1000123a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000123e: 4b06 ldr r3, [pc, #24] @ (10001258 ) +10001240: 609d str r5, [r3, #8] +10001242: bd70 pop {r4, r5, r6, pc} +10001244: 2043 movs r0, #67 @ 0x43 +10001246: e7f8 b.n 1000123a +10001248: 10000000 .word 0x10000000 +1000124c: 10000110 .word 0x10000110 +10001250: 20000000 .word 0x20000000 +10001254: 10000111 .word 0x10000111 +10001258: e000ed00 .word 0xe000ed00 + +1000125c : +1000125c: 2300 movs r3, #0 +1000125e: b570 push {r4, r5, r6, lr} +10001260: 4c2b ldr r4, [pc, #172] @ (10001310 ) +10001262: b082 sub sp, #8 +10001264: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001268: f7ff ff38 bl 100010dc +1000126c: 2201 movs r2, #1 +1000126e: 4b29 ldr r3, [pc, #164] @ (10001314 ) +10001270: 63da str r2, [r3, #60] @ 0x3c +10001272: 6c63 ldr r3, [r4, #68] @ 0x44 +10001274: 2b01 cmp r3, #1 +10001276: d1fc bne.n 10001272 +10001278: 2103 movs r1, #3 +1000127a: 4a26 ldr r2, [pc, #152] @ (10001314 ) +1000127c: 4b24 ldr r3, [pc, #144] @ (10001310 ) +1000127e: 6311 str r1, [r2, #48] @ 0x30 +10001280: 6b9c ldr r4, [r3, #56] @ 0x38 +10001282: 2c01 cmp r4, #1 +10001284: d1fc bne.n 10001280 +10001286: 2602 movs r6, #2 +10001288: 2505 movs r5, #5 +1000128a: 4621 mov r1, r4 +1000128c: 2305 movs r3, #5 +1000128e: 4a22 ldr r2, [pc, #136] @ (10001318 ) +10001290: 4822 ldr r0, [pc, #136] @ (1000131c ) +10001292: 9600 str r6, [sp, #0] +10001294: f7ff feac bl 10000ff0 +10001298: 4621 mov r1, r4 +1000129a: 462b mov r3, r5 +1000129c: 4a20 ldr r2, [pc, #128] @ (10001320 ) +1000129e: 4821 ldr r0, [pc, #132] @ (10001324 ) +100012a0: 9500 str r5, [sp, #0] +100012a2: f7ff fea5 bl 10000ff0 +100012a6: 2200 movs r2, #0 +100012a8: 2004 movs r0, #4 +100012aa: 4631 mov r1, r6 +100012ac: 4b1e ldr r3, [pc, #120] @ (10001328 ) +100012ae: f7ff fe31 bl 10000f14 +100012b2: 4621 mov r1, r4 +100012b4: 4628 mov r0, r5 +100012b6: 2200 movs r2, #0 +100012b8: 4b1c ldr r3, [pc, #112] @ (1000132c ) +100012ba: f7ff fe2b bl 10000f14 +100012be: 2200 movs r2, #0 +100012c0: 2008 movs r0, #8 +100012c2: 4611 mov r1, r2 +100012c4: 4b1a ldr r3, [pc, #104] @ (10001330 ) +100012c6: f7ff fe25 bl 10000f14 +100012ca: 2200 movs r2, #0 +100012cc: 2009 movs r0, #9 +100012ce: 4611 mov r1, r2 +100012d0: 4b17 ldr r3, [pc, #92] @ (10001330 ) +100012d2: f7ff fe1f bl 10000f14 +100012d6: 2200 movs r2, #0 +100012d8: 2006 movs r0, #6 +100012da: 4611 mov r1, r2 +100012dc: 4b13 ldr r3, [pc, #76] @ (1000132c ) +100012de: f7ff fe19 bl 10000f14 +100012e2: 2200 movs r2, #0 +100012e4: 4b11 ldr r3, [pc, #68] @ (1000132c ) +100012e6: 2007 movs r0, #7 +100012e8: 4611 mov r1, r2 +100012ea: f7ff fe13 bl 10000f14 +100012ee: 2004 movs r0, #4 +100012f0: f7ff fe78 bl 10000fe4 +100012f4: 2400 movs r4, #0 +100012f6: 4b0f ldr r3, [pc, #60] @ (10001334 ) +100012f8: fba3 3500 umull r3, r5, r3, r0 +100012fc: 0cad lsrs r5, r5, #18 +100012fe: b2e0 uxtb r0, r4 +10001300: 4629 mov r1, r5 +10001302: 3401 adds r4, #1 +10001304: f7ff feba bl 1000107c +10001308: 2c06 cmp r4, #6 +1000130a: d1f8 bne.n 100012fe +1000130c: b002 add sp, #8 +1000130e: bd70 pop {r4, r5, r6, pc} +10001310: 40010000 .word 0x40010000 +10001314: 40013000 .word 0x40013000 +10001318: 59682f00 .word 0x59682f00 +1000131c: 40050000 .word 0x40050000 +10001320: 47868c00 .word 0x47868c00 +10001324: 40058000 .word 0x40058000 +10001328: 00b71b00 .word 0x00b71b00 +1000132c: 08f0d180 .word 0x08f0d180 +10001330: 02dc6c00 .word 0x02dc6c00 +10001334: 431bde83 .word 0x431bde83 + +10001338 : +10001338: b086 sub sp, #24 +1000133a: b403 push {r0, r1} +1000133c: fc51 0408 dcp_pxmd r0, r1 +10001340: e9cd 0102 strd r0, r1, [sp, #8] +10001344: fc51 0409 dcp_pymd r0, r1 +10001348: e9cd 0104 strd r0, r1, [sp, #16] +1000134c: ec51 040a dcp_refd r0, r1 +10001350: e9cd 0106 strd r0, r1, [sp, #24] +10001354: bc03 pop {r0, r1} +10001356: 47f0 blx lr + +10001358 : +10001358: e8bd 5000 ldmia.w sp!, {ip, lr} +1000135c: ec4e c400 dcp_wxmd ip, lr +10001360: e8bd 5000 ldmia.w sp!, {ip, lr} +10001364: ec4e c401 dcp_wymd ip, lr +10001368: e8bd 5000 ldmia.w sp!, {ip, lr} +1000136c: ec4e c402 dcp_wefd ip, lr +10001370: bd00 pop {pc} +10001372: 0000 movs r0, r0 +10001374: b500 push {lr} +10001376: f7ff ffdf bl 10001338 +1000137a: e002 b.n 10001382 <__wrap___aeabi_dadd+0x6> + +1000137c <__wrap___aeabi_dadd>: +1000137c: fe10 f430 dcp_pcmp APSR_nzcv +10001380: d4f8 bmi.n 10001374 +10001382: ec41 0410 dcp_wxup r0, r1 +10001386: ec43 2411 dcp_wyup r2, r3 +1000138a: ee00 0401 dcp_add0 +1000138e: ee10 0401 dcp_add1 +10001392: ee80 0420 dcp_nrdd +10001396: ec51 0410 dcp_rdda r0, r1 +1000139a: 4770 bx lr +1000139c: b500 push {lr} +1000139e: f7ff ffcb bl 10001338 +100013a2: e002 b.n 100013aa <__wrap___aeabi_dsub+0x6> + +100013a4 <__wrap___aeabi_dsub>: +100013a4: fe10 f430 dcp_pcmp APSR_nzcv +100013a8: d4f8 bmi.n 1000139c <__wrap___aeabi_dadd+0x20> +100013aa: ec41 0410 dcp_wxup r0, r1 +100013ae: ec43 2411 dcp_wyup r2, r3 +100013b2: ee00 0401 dcp_add0 +100013b6: ee10 0421 dcp_sub1 +100013ba: ee80 0420 dcp_nrdd +100013be: ec51 0430 dcp_rdds r0, r1 +100013c2: 4770 bx lr +100013c4: b500 push {lr} +100013c6: f7ff ffb7 bl 10001338 +100013ca: e002 b.n 100013d2 <__wrap___aeabi_dmul+0x6> + +100013cc <__wrap___aeabi_dmul>: +100013cc: fe10 f430 dcp_pcmp APSR_nzcv +100013d0: d4f8 bmi.n 100013c4 <__wrap___aeabi_dsub+0x20> +100013d2: b510 push {r4, lr} +100013d4: ec41 0410 dcp_wxup r0, r1 +100013d8: ec43 2411 dcp_wyup r2, r3 +100013dc: ec51 0404 dcp_rxms r0, r1, #0x0 +100013e0: ec53 2405 dcp_ryms r2, r3, #0x0 +100013e4: fba0 4c02 umull r4, ip, r0, r2 +100013e8: f05f 0e00 movs.w lr, #0 +100013ec: fbe0 ce03 umlal ip, lr, r0, r3 +100013f0: fbe1 ce02 umlal ip, lr, r1, r2 +100013f4: ec4c 4420 dcp_wxms r4, ip +100013f8: 2400 movs r4, #0 +100013fa: fbe1 e403 umlal lr, r4, r1, r3 +100013fe: ec44 e430 dcp_wxmo lr, r4 +10001402: ee80 0420 dcp_nrdd +10001406: ec51 0450 dcp_rddm r0, r1 +1000140a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000140e: 4770 bx lr +10001410: b500 push {lr} +10001412: f7ff ff91 bl 10001338 +10001416: e002 b.n 1000141e <__wrap___aeabi_ddiv+0x6> + +10001418 <__wrap___aeabi_ddiv>: +10001418: fe10 f430 dcp_pcmp APSR_nzcv +1000141c: d4f8 bmi.n 10001410 <__wrap___aeabi_dmul+0x44> +1000141e: ec41 0410 dcp_wxup r0, r1 +10001422: ec43 2411 dcp_wyup r2, r3 +10001426: ec51 0421 dcp_rymr r0, r1 +1000142a: fba0 1201 umull r1, r2, r0, r1 +1000142e: ea6f 0282 mvn.w r2, r2, lsl #2 +10001432: fb52 0010 smmlar r0, r2, r0, r0 +10001436: fb52 f212 smmulr r2, r2, r2 +1000143a: fb52 0010 smmlar r0, r2, r0, r0 +1000143e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001442: ec53 2404 dcp_rxms r2, r3, #0x0 +10001446: fb5c f113 smmulr r1, ip, r3 +1000144a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000144e: fba1 2002 umull r2, r0, r1, r2 +10001452: fb01 0003 mla r0, r1, r3, r0 +10001456: ec53 2444 dcp_rxms r2, r3, #0x4 +1000145a: eba2 0000 sub.w r0, r2, r0 +1000145e: fb50 f21c smmulr r2, r0, ip +10001462: ea4f 1311 mov.w r3, r1, lsr #4 +10001466: eb12 7001 adds.w r0, r2, r1, lsl #28 +1000146a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1000146e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001472: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001476: f020 0007 bic.w r0, r0, #7 +1000147a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000147e: fba0 3c02 umull r3, ip, r0, r2 +10001482: ec53 2475 dcp_ryms r2, r3, #0x7 +10001486: fb00 cc03 mla ip, r0, r3, ip +1000148a: fb01 cc02 mla ip, r1, r2, ip +1000148e: ec53 2404 dcp_rxms r2, r3, #0x0 +10001492: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001496: ea40 705c orr.w r0, r0, ip, lsr #29 +1000149a: f1a0 0001 sub.w r0, r0, #1 +1000149e: ec41 0440 dcp_wxdd r0, r1 +100014a2: ee80 0420 dcp_nrdd +100014a6: ec51 0470 dcp_rddd r0, r1 +100014aa: 4770 bx lr +100014ac: b500 push {lr} +100014ae: f7ff ff43 bl 10001338 +100014b2: e002 b.n 100014ba <__wrap___aeabi_i2d+0x6> + +100014b4 <__wrap___aeabi_i2d>: +100014b4: fe10 f430 dcp_pcmp APSR_nzcv +100014b8: d4f8 bmi.n 100014ac <__wrap___aeabi_ddiv+0x94> +100014ba: ec40 0470 dcp_wxic r0, r0 +100014be: ee00 0401 dcp_add0 +100014c2: ee10 0421 dcp_sub1 +100014c6: ee80 0420 dcp_nrdd +100014ca: ec51 0430 dcp_rdds r0, r1 +100014ce: 4770 bx lr +100014d0: b500 push {lr} +100014d2: f7ff ff31 bl 10001338 +100014d6: e002 b.n 100014de <__wrap___aeabi_ui2d+0x6> + +100014d8 <__wrap___aeabi_ui2d>: +100014d8: fe10 f430 dcp_pcmp APSR_nzcv +100014dc: d4f8 bmi.n 100014d0 <__wrap___aeabi_i2d+0x1c> +100014de: ec40 0460 dcp_wxuc r0, r0 +100014e2: ee00 0401 dcp_add0 +100014e6: ee10 0421 dcp_sub1 +100014ea: ee80 0420 dcp_nrdd +100014ee: ec51 0430 dcp_rdds r0, r1 +100014f2: 4770 bx lr +100014f4: b500 push {lr} +100014f6: f7ff ff1f bl 10001338 +100014fa: e002 b.n 10001502 + +100014fc <__wrap___aeabi_d2iz>: +100014fc: fe10 f430 dcp_pcmp APSR_nzcv +10001500: d4f8 bmi.n 100014f4 <__wrap___aeabi_ui2d+0x1c> + +10001502 : +10001502: ec41 0480 dcp_wxdc r0, r1 +10001506: ee00 0401 dcp_add0 +1000150a: ee10 0401 dcp_add1 +1000150e: ee80 0440 dcp_ntdc +10001512: ee10 0413 dcp_rdic r0 +10001516: 4770 bx lr +10001518: b500 push {lr} +1000151a: f7ff ff0d bl 10001338 +1000151e: e002 b.n 10001526 + +10001520 <__wrap___aeabi_d2uiz>: +10001520: fe10 f430 dcp_pcmp APSR_nzcv +10001524: d4f8 bmi.n 10001518 + +10001526 : +10001526: ec41 0480 dcp_wxdc r0, r1 +1000152a: ee00 0401 dcp_add0 +1000152e: ee10 0401 dcp_add1 +10001532: ee80 0440 dcp_ntdc +10001536: ee10 0433 dcp_rduc r0 +1000153a: 4770 bx lr +1000153c: b500 push {lr} +1000153e: f7ff fefb bl 10001338 +10001542: e002 b.n 1000154a <__wrap___aeabi_dcmpun+0x6> + +10001544 <__wrap___aeabi_dcmpun>: +10001544: fe10 f430 dcp_pcmp APSR_nzcv +10001548: d4f8 bmi.n 1000153c +1000154a: ec41 0410 dcp_wxup r0, r1 +1000154e: ec43 2411 dcp_wyup r2, r3 +10001552: ee00 0401 dcp_add0 +10001556: ee10 0430 dcp_rcmp r0 +1000155a: f3c0 7000 ubfx r0, r0, #28, #1 +1000155e: 4770 bx lr +10001560: b500 push {lr} +10001562: f7ff fee9 bl 10001338 +10001566: e002 b.n 1000156e <__wrap___aeabi_dcmplt+0x6> + +10001568 <__wrap___aeabi_dcmplt>: +10001568: fe10 f430 dcp_pcmp APSR_nzcv +1000156c: d4f8 bmi.n 10001560 <__wrap___aeabi_dcmpun+0x1c> +1000156e: ec43 2410 dcp_wxup r2, r3 +10001572: ec41 0411 dcp_wyup r0, r1 +10001576: ee00 0401 dcp_add0 +1000157a: ee10 f430 dcp_rcmp APSR_nzcv +1000157e: bf8c ite hi +10001580: 2001 movhi r0, #1 +10001582: 2000 movls r0, #0 +10001584: 4770 bx lr +10001586: bf00 nop +10001588: b500 push {lr} +1000158a: f7ff fed5 bl 10001338 +1000158e: e002 b.n 10001596 <__wrap___aeabi_dcmple+0x6> + +10001590 <__wrap___aeabi_dcmple>: +10001590: fe10 f430 dcp_pcmp APSR_nzcv +10001594: d4f8 bmi.n 10001588 <__wrap___aeabi_dcmplt+0x20> +10001596: ec43 2410 dcp_wxup r2, r3 +1000159a: ec41 0411 dcp_wyup r0, r1 +1000159e: ee00 0401 dcp_add0 +100015a2: ee10 f430 dcp_rcmp APSR_nzcv +100015a6: bf2c ite cs +100015a8: 2001 movcs r0, #1 +100015aa: 2000 movcc r0, #0 +100015ac: 4770 bx lr +100015ae: bf00 nop +100015b0: b500 push {lr} +100015b2: f7ff fec1 bl 10001338 +100015b6: e002 b.n 100015be <__wrap___aeabi_dcmpge+0x6> + +100015b8 <__wrap___aeabi_dcmpge>: +100015b8: fe10 f430 dcp_pcmp APSR_nzcv +100015bc: d4f8 bmi.n 100015b0 <__wrap___aeabi_dcmple+0x20> +100015be: ec41 0410 dcp_wxup r0, r1 +100015c2: ec43 2411 dcp_wyup r2, r3 +100015c6: ee00 0401 dcp_add0 +100015ca: ee10 f430 dcp_rcmp APSR_nzcv +100015ce: bf2c ite cs +100015d0: 2001 movcs r0, #1 +100015d2: 2000 movcc r0, #0 +100015d4: 4770 bx lr +100015d6: bf00 nop +100015d8: b500 push {lr} +100015da: f7ff fead bl 10001338 +100015de: e002 b.n 100015e6 <__wrap___aeabi_dcmpgt+0x6> + +100015e0 <__wrap___aeabi_dcmpgt>: +100015e0: fe10 f430 dcp_pcmp APSR_nzcv +100015e4: d4f8 bmi.n 100015d8 <__wrap___aeabi_dcmpge+0x20> +100015e6: ec41 0410 dcp_wxup r0, r1 +100015ea: ec43 2411 dcp_wyup r2, r3 +100015ee: ee00 0401 dcp_add0 +100015f2: ee10 f430 dcp_rcmp APSR_nzcv +100015f6: bf8c ite hi +100015f8: 2001 movhi r0, #1 +100015fa: 2000 movls r0, #0 +100015fc: 4770 bx lr +100015fe: bf00 nop + +10001600 <_out_null>: +10001600: 4770 bx lr +10001602: bf00 nop + +10001604 <_out_rev>: +10001604: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001608: b083 sub sp, #12 +1000160a: 4699 mov r9, r3 +1000160c: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001610: 9b0f ldr r3, [sp, #60] @ 0x3c +10001612: 4688 mov r8, r1 +10001614: 4611 mov r1, r2 +10001616: 079a lsls r2, r3, #30 +10001618: 4607 mov r7, r0 +1000161a: d116 bne.n 1000164a <_out_rev+0x46> +1000161c: 45da cmp sl, fp +1000161e: d23a bcs.n 10001696 <_out_rev+0x92> +10001620: 460c mov r4, r1 +10001622: 460d mov r5, r1 +10001624: ebab 060a sub.w r6, fp, sl +10001628: 440e add r6, r1 +1000162a: 4622 mov r2, r4 +1000162c: 464b mov r3, r9 +1000162e: 4641 mov r1, r8 +10001630: 2020 movs r0, #32 +10001632: 3401 adds r4, #1 +10001634: 47b8 blx r7 +10001636: 42b4 cmp r4, r6 +10001638: d1f7 bne.n 1000162a <_out_rev+0x26> +1000163a: 4629 mov r1, r5 +1000163c: f1ba 0f00 cmp.w sl, #0 +10001640: d108 bne.n 10001654 <_out_rev+0x50> +10001642: 4620 mov r0, r4 +10001644: b003 add sp, #12 +10001646: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000164a: 460c mov r4, r1 +1000164c: f1ba 0f00 cmp.w sl, #0 +10001650: d010 beq.n 10001674 <_out_rev+0x70> +10001652: 460e mov r6, r1 +10001654: 4655 mov r5, sl +10001656: 9b0c ldr r3, [sp, #48] @ 0x30 +10001658: 442e add r6, r5 +1000165a: 449a add sl, r3 +1000165c: 9101 str r1, [sp, #4] +1000165e: 1b72 subs r2, r6, r5 +10001660: 464b mov r3, r9 +10001662: 3d01 subs r5, #1 +10001664: 4641 mov r1, r8 +10001666: f81a 0d01 ldrb.w r0, [sl, #-1]! +1000166a: 4634 mov r4, r6 +1000166c: 47b8 blx r7 +1000166e: 2d00 cmp r5, #0 +10001670: d1f5 bne.n 1000165e <_out_rev+0x5a> +10001672: 9901 ldr r1, [sp, #4] +10001674: 9b0f ldr r3, [sp, #60] @ 0x3c +10001676: 079b lsls r3, r3, #30 +10001678: d5e3 bpl.n 10001642 <_out_rev+0x3e> +1000167a: 1a65 subs r5, r4, r1 +1000167c: 45ab cmp fp, r5 +1000167e: d9e0 bls.n 10001642 <_out_rev+0x3e> +10001680: 4622 mov r2, r4 +10001682: 464b mov r3, r9 +10001684: 4641 mov r1, r8 +10001686: 2020 movs r0, #32 +10001688: 3501 adds r5, #1 +1000168a: 47b8 blx r7 +1000168c: 455d cmp r5, fp +1000168e: f104 0401 add.w r4, r4, #1 +10001692: d3f5 bcc.n 10001680 <_out_rev+0x7c> +10001694: e7d5 b.n 10001642 <_out_rev+0x3e> +10001696: 460c mov r4, r1 +10001698: f1ba 0f00 cmp.w sl, #0 +1000169c: d1d9 bne.n 10001652 <_out_rev+0x4e> +1000169e: e7d0 b.n 10001642 <_out_rev+0x3e> + +100016a0 <_ntoa_format>: +100016a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100016a4: 9f0f ldr r7, [sp, #60] @ 0x3c +100016a6: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +100016aa: f017 0f02 tst.w r7, #2 +100016ae: 9c0a ldr r4, [sp, #40] @ 0x28 +100016b0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +100016b4: 9d0e ldr r5, [sp, #56] @ 0x38 +100016b6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +100016ba: d144 bne.n 10001746 <_ntoa_format+0xa6> +100016bc: bbf5 cbnz r5, 1000173c <_ntoa_format+0x9c> +100016be: 42b4 cmp r4, r6 +100016c0: d241 bcs.n 10001746 <_ntoa_format+0xa6> +100016c2: f007 0b01 and.w fp, r7, #1 +100016c6: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100016ca: f04f 0e30 mov.w lr, #48 @ 0x30 +100016ce: 44c4 add ip, r8 +100016d0: e004 b.n 100016dc <_ntoa_format+0x3c> +100016d2: 3401 adds r4, #1 +100016d4: 42a6 cmp r6, r4 +100016d6: f80c ef01 strb.w lr, [ip, #1]! +100016da: d901 bls.n 100016e0 <_ntoa_format+0x40> +100016dc: 2c20 cmp r4, #32 +100016de: d1f8 bne.n 100016d2 <_ntoa_format+0x32> +100016e0: f1bb 0f00 cmp.w fp, #0 +100016e4: f000 8088 beq.w 100017f8 <_ntoa_format+0x158> +100016e8: 42a5 cmp r5, r4 +100016ea: d92c bls.n 10001746 <_ntoa_format+0xa6> +100016ec: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100016f0: f04f 0e30 mov.w lr, #48 @ 0x30 +100016f4: 44c4 add ip, r8 +100016f6: e004 b.n 10001702 <_ntoa_format+0x62> +100016f8: 3401 adds r4, #1 +100016fa: 42ac cmp r4, r5 +100016fc: f80c ef01 strb.w lr, [ip, #1]! +10001700: d021 beq.n 10001746 <_ntoa_format+0xa6> +10001702: 2c20 cmp r4, #32 +10001704: d1f8 bne.n 100016f8 <_ntoa_format+0x58> +10001706: f017 0f10 tst.w r7, #16 +1000170a: d00e beq.n 1000172a <_ntoa_format+0x8a> +1000170c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001710: d154 bne.n 100017bc <_ntoa_format+0x11c> +10001712: 42a6 cmp r6, r4 +10001714: d063 beq.n 100017de <_ntoa_format+0x13e> +10001716: 42a5 cmp r5, r4 +10001718: d061 beq.n 100017de <_ntoa_format+0x13e> +1000171a: f1b9 0f10 cmp.w r9, #16 +1000171e: d050 beq.n 100017c2 <_ntoa_format+0x122> +10001720: f1b9 0f02 cmp.w r9, #2 +10001724: d056 beq.n 100017d4 <_ntoa_format+0x134> +10001726: 2c20 cmp r4, #32 +10001728: d129 bne.n 1000177e <_ntoa_format+0xde> +1000172a: 2420 movs r4, #32 +1000172c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001730: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001734: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001738: f7ff bf64 b.w 10001604 <_out_rev> +1000173c: f017 0b01 ands.w fp, r7, #1 +10001740: d134 bne.n 100017ac <_ntoa_format+0x10c> +10001742: 42b4 cmp r4, r6 +10001744: d3bf bcc.n 100016c6 <_ntoa_format+0x26> +10001746: f017 0f10 tst.w r7, #16 +1000174a: d01e beq.n 1000178a <_ntoa_format+0xea> +1000174c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001750: d1e3 bne.n 1000171a <_ntoa_format+0x7a> +10001752: 2c00 cmp r4, #0 +10001754: d1dd bne.n 10001712 <_ntoa_format+0x72> +10001756: f1b9 0f10 cmp.w r9, #16 +1000175a: d063 beq.n 10001824 <_ntoa_format+0x184> +1000175c: f1b9 0f02 cmp.w r9, #2 +10001760: d077 beq.n 10001852 <_ntoa_format+0x1b2> +10001762: 2430 movs r4, #48 @ 0x30 +10001764: f888 4000 strb.w r4, [r8] +10001768: 2401 movs r4, #1 +1000176a: f1ba 0f00 cmp.w sl, #0 +1000176e: d111 bne.n 10001794 <_ntoa_format+0xf4> +10001770: 077e lsls r6, r7, #29 +10001772: d548 bpl.n 10001806 <_ntoa_format+0x166> +10001774: 262b movs r6, #43 @ 0x2b +10001776: f808 6004 strb.w r6, [r8, r4] +1000177a: 3401 adds r4, #1 +1000177c: e7d6 b.n 1000172c <_ntoa_format+0x8c> +1000177e: 4626 mov r6, r4 +10001780: 3401 adds r4, #1 +10001782: f04f 0c30 mov.w ip, #48 @ 0x30 +10001786: f808 c006 strb.w ip, [r8, r6] +1000178a: 2c20 cmp r4, #32 +1000178c: d0cd beq.n 1000172a <_ntoa_format+0x8a> +1000178e: f1ba 0f00 cmp.w sl, #0 +10001792: d0ed beq.n 10001770 <_ntoa_format+0xd0> +10001794: 262d movs r6, #45 @ 0x2d +10001796: f808 6004 strb.w r6, [r8, r4] +1000179a: 3401 adds r4, #1 +1000179c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100017a0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100017a4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100017a8: f7ff bf2c b.w 10001604 <_out_rev> +100017ac: f1ba 0f00 cmp.w sl, #0 +100017b0: d030 beq.n 10001814 <_ntoa_format+0x174> +100017b2: 42b4 cmp r4, r6 +100017b4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +100017b8: d385 bcc.n 100016c6 <_ntoa_format+0x26> +100017ba: e795 b.n 100016e8 <_ntoa_format+0x48> +100017bc: f1b9 0f10 cmp.w r9, #16 +100017c0: d1b3 bne.n 1000172a <_ntoa_format+0x8a> +100017c2: 06be lsls r6, r7, #26 +100017c4: d53b bpl.n 1000183e <_ntoa_format+0x19e> +100017c6: 2c20 cmp r4, #32 +100017c8: d0af beq.n 1000172a <_ntoa_format+0x8a> +100017ca: 2658 movs r6, #88 @ 0x58 +100017cc: f808 6004 strb.w r6, [r8, r4] +100017d0: 3401 adds r4, #1 +100017d2: e7a8 b.n 10001726 <_ntoa_format+0x86> +100017d4: 2c20 cmp r4, #32 +100017d6: d0a8 beq.n 1000172a <_ntoa_format+0x8a> +100017d8: 4626 mov r6, r4 +100017da: 3401 adds r4, #1 +100017dc: e007 b.n 100017ee <_ntoa_format+0x14e> +100017de: 1e66 subs r6, r4, #1 +100017e0: d0b9 beq.n 10001756 <_ntoa_format+0xb6> +100017e2: f1b9 0f10 cmp.w r9, #16 +100017e6: d036 beq.n 10001856 <_ntoa_format+0x1b6> +100017e8: f1b9 0f02 cmp.w r9, #2 +100017ec: d1c9 bne.n 10001782 <_ntoa_format+0xe2> +100017ee: f04f 0c62 mov.w ip, #98 @ 0x62 +100017f2: f808 c006 strb.w ip, [r8, r6] +100017f6: e796 b.n 10001726 <_ntoa_format+0x86> +100017f8: f017 0f10 tst.w r7, #16 +100017fc: d0c5 beq.n 1000178a <_ntoa_format+0xea> +100017fe: f417 6f80 tst.w r7, #1024 @ 0x400 +10001802: d086 beq.n 10001712 <_ntoa_format+0x72> +10001804: e789 b.n 1000171a <_ntoa_format+0x7a> +10001806: 073e lsls r6, r7, #28 +10001808: d590 bpl.n 1000172c <_ntoa_format+0x8c> +1000180a: 2620 movs r6, #32 +1000180c: f808 6004 strb.w r6, [r8, r4] +10001810: 3401 adds r4, #1 +10001812: e78b b.n 1000172c <_ntoa_format+0x8c> +10001814: f017 0f0c tst.w r7, #12 +10001818: d000 beq.n 1000181c <_ntoa_format+0x17c> +1000181a: 3d01 subs r5, #1 +1000181c: 42b4 cmp r4, r6 +1000181e: f4ff af52 bcc.w 100016c6 <_ntoa_format+0x26> +10001822: e761 b.n 100016e8 <_ntoa_format+0x48> +10001824: 06bc lsls r4, r7, #26 +10001826: d412 bmi.n 1000184e <_ntoa_format+0x1ae> +10001828: 2478 movs r4, #120 @ 0x78 +1000182a: f888 4000 strb.w r4, [r8] +1000182e: 2430 movs r4, #48 @ 0x30 +10001830: f888 4001 strb.w r4, [r8, #1] +10001834: 2402 movs r4, #2 +10001836: f1ba 0f00 cmp.w sl, #0 +1000183a: d099 beq.n 10001770 <_ntoa_format+0xd0> +1000183c: e7aa b.n 10001794 <_ntoa_format+0xf4> +1000183e: 2c20 cmp r4, #32 +10001840: f43f af73 beq.w 1000172a <_ntoa_format+0x8a> +10001844: 2678 movs r6, #120 @ 0x78 +10001846: f808 6004 strb.w r6, [r8, r4] +1000184a: 3401 adds r4, #1 +1000184c: e76b b.n 10001726 <_ntoa_format+0x86> +1000184e: 2458 movs r4, #88 @ 0x58 +10001850: e7eb b.n 1000182a <_ntoa_format+0x18a> +10001852: 2462 movs r4, #98 @ 0x62 +10001854: e7e9 b.n 1000182a <_ntoa_format+0x18a> +10001856: f017 0f20 tst.w r7, #32 +1000185a: f1a4 0c02 sub.w ip, r4, #2 +1000185e: d004 beq.n 1000186a <_ntoa_format+0x1ca> +10001860: f04f 0e58 mov.w lr, #88 @ 0x58 +10001864: f808 e00c strb.w lr, [r8, ip] +10001868: e78b b.n 10001782 <_ntoa_format+0xe2> +1000186a: f04f 0e78 mov.w lr, #120 @ 0x78 +1000186e: f808 e00c strb.w lr, [r8, ip] +10001872: e786 b.n 10001782 <_ntoa_format+0xe2> + +10001874 <_out_char>: +10001874: b900 cbnz r0, 10001878 <_out_char+0x4> +10001876: 4770 bx lr +10001878: f001 bb72 b.w 10002f60 <__wrap_putchar> + +1000187c <_out_fct>: +1000187c: b110 cbz r0, 10001884 <_out_fct+0x8> +1000187e: e9d1 3100 ldrd r3, r1, [r1] +10001882: 4718 bx r3 +10001884: 4770 bx lr +10001886: bf00 nop + +10001888 <_ftoa>: +10001888: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000188c: b097 sub sp, #92 @ 0x5c +1000188e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001892: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001896: 4607 mov r7, r0 +10001898: 4688 mov r8, r1 +1000189a: ec51 0b17 vmov r0, r1, d7 +1000189e: 9c24 ldr r4, [sp, #144] @ 0x90 +100018a0: 4699 mov r9, r3 +100018a2: 920c str r2, [sp, #48] @ 0x30 +100018a4: 460b mov r3, r1 +100018a6: 4602 mov r2, r0 +100018a8: ed8d 7b04 vstr d7, [sp, #16] +100018ac: 9407 str r4, [sp, #28] +100018ae: f7ff fe49 bl 10001544 <__wrap___aeabi_dcmpun> +100018b2: 2800 cmp r0, #0 +100018b4: f040 81f4 bne.w 10001ca0 <_ftoa+0x418> +100018b8: e9dd 0104 ldrd r0, r1, [sp, #16] +100018bc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018c0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100018c4: f7ff fe50 bl 10001568 <__wrap___aeabi_dcmplt> +100018c8: 2800 cmp r0, #0 +100018ca: f040 811b bne.w 10001b04 <_ftoa+0x27c> +100018ce: e9dd 0104 ldrd r0, r1, [sp, #16] +100018d2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018d6: 4bac ldr r3, [pc, #688] @ (10001b88 <_ftoa+0x300>) +100018d8: f7ff fe82 bl 100015e0 <__wrap___aeabi_dcmpgt> +100018dc: 2800 cmp r0, #0 +100018de: f040 80ee bne.w 10001abe <_ftoa+0x236> +100018e2: e9dd 0104 ldrd r0, r1, [sp, #16] +100018e6: a3a4 add r3, pc, #656 @ (adr r3, 10001b78 <_ftoa+0x2f0>) +100018e8: e9d3 2300 ldrd r2, r3, [r3] +100018ec: f7ff fe78 bl 100015e0 <__wrap___aeabi_dcmpgt> +100018f0: 2800 cmp r0, #0 +100018f2: f040 80d3 bne.w 10001a9c <_ftoa+0x214> +100018f6: e9dd 0104 ldrd r0, r1, [sp, #16] +100018fa: a3a1 add r3, pc, #644 @ (adr r3, 10001b80 <_ftoa+0x2f8>) +100018fc: e9d3 2300 ldrd r2, r3, [r3] +10001900: f7ff fe32 bl 10001568 <__wrap___aeabi_dcmplt> +10001904: 2800 cmp r0, #0 +10001906: f040 80c9 bne.w 10001a9c <_ftoa+0x214> +1000190a: e9dd 0104 ldrd r0, r1, [sp, #16] +1000190e: 2200 movs r2, #0 +10001910: 2300 movs r3, #0 +10001912: f7ff fe29 bl 10001568 <__wrap___aeabi_dcmplt> +10001916: 2800 cmp r0, #0 +10001918: f040 80e8 bne.w 10001aec <_ftoa+0x264> +1000191c: 4623 mov r3, r4 +1000191e: 900d str r0, [sp, #52] @ 0x34 +10001920: f413 6f80 tst.w r3, #1024 @ 0x400 +10001924: bf08 it eq +10001926: 2506 moveq r5, #6 +10001928: 2130 movs r1, #48 @ 0x30 +1000192a: 462b mov r3, r5 +1000192c: aa0e add r2, sp, #56 @ 0x38 +1000192e: f1a5 0620 sub.w r6, r5, #32 +10001932: e005 b.n 10001940 <_ftoa+0xb8> +10001934: 3b01 subs r3, #1 +10001936: 42b3 cmp r3, r6 +10001938: f802 1b01 strb.w r1, [r2], #1 +1000193c: f000 8193 beq.w 10001c66 <_ftoa+0x3de> +10001940: 2b09 cmp r3, #9 +10001942: d8f7 bhi.n 10001934 <_ftoa+0xac> +10001944: 461e mov r6, r3 +10001946: 1aed subs r5, r5, r3 +10001948: e9dd 0104 ldrd r0, r1, [sp, #16] +1000194c: f7ff fdd6 bl 100014fc <__wrap___aeabi_d2iz> +10001950: 4b8e ldr r3, [pc, #568] @ (10001b8c <_ftoa+0x304>) +10001952: 4604 mov r4, r0 +10001954: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001958: ed93 7b00 vldr d7, [r3] +1000195c: ed8d 7b08 vstr d7, [sp, #32] +10001960: f7ff fda8 bl 100014b4 <__wrap___aeabi_i2d> +10001964: 4602 mov r2, r0 +10001966: 460b mov r3, r1 +10001968: e9dd 0104 ldrd r0, r1, [sp, #16] +1000196c: f7ff fd1a bl 100013a4 <__wrap___aeabi_dsub> +10001970: e9dd 2308 ldrd r2, r3, [sp, #32] +10001974: f7ff fd2a bl 100013cc <__wrap___aeabi_dmul> +10001978: 4602 mov r2, r0 +1000197a: 460b mov r3, r1 +1000197c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001980: f7ff fdce bl 10001520 <__wrap___aeabi_d2uiz> +10001984: 4682 mov sl, r0 +10001986: f7ff fda7 bl 100014d8 <__wrap___aeabi_ui2d> +1000198a: 4602 mov r2, r0 +1000198c: 460b mov r3, r1 +1000198e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001992: f7ff fd07 bl 100013a4 <__wrap___aeabi_dsub> +10001996: 4602 mov r2, r0 +10001998: 460b mov r3, r1 +1000199a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +1000199e: 2200 movs r2, #0 +100019a0: 4b7b ldr r3, [pc, #492] @ (10001b90 <_ftoa+0x308>) +100019a2: f7ff fe1d bl 100015e0 <__wrap___aeabi_dcmpgt> +100019a6: 2800 cmp r0, #0 +100019a8: f000 80fe beq.w 10001ba8 <_ftoa+0x320> +100019ac: f10a 0a01 add.w sl, sl, #1 +100019b0: 4650 mov r0, sl +100019b2: f7ff fd91 bl 100014d8 <__wrap___aeabi_ui2d> +100019b6: 4602 mov r2, r0 +100019b8: 460b mov r3, r1 +100019ba: e9dd 0108 ldrd r0, r1, [sp, #32] +100019be: f7ff fde7 bl 10001590 <__wrap___aeabi_dcmple> +100019c2: b110 cbz r0, 100019ca <_ftoa+0x142> +100019c4: f04f 0a00 mov.w sl, #0 +100019c8: 3401 adds r4, #1 +100019ca: 2e00 cmp r6, #0 +100019cc: f000 80fd beq.w 10001bca <_ftoa+0x342> +100019d0: 1e68 subs r0, r5, #1 +100019d2: ab0e add r3, sp, #56 @ 0x38 +100019d4: f8df c1cc ldr.w ip, [pc, #460] @ 10001ba4 <_ftoa+0x31c> +100019d8: 4418 add r0, r3 +100019da: e00f b.n 100019fc <_ftoa+0x174> +100019dc: fbac 210a umull r2, r1, ip, sl +100019e0: 08c9 lsrs r1, r1, #3 +100019e2: eb01 0281 add.w r2, r1, r1, lsl #2 +100019e6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +100019ea: 3230 adds r2, #48 @ 0x30 +100019ec: f1ba 0f09 cmp.w sl, #9 +100019f0: f800 2f01 strb.w r2, [r0, #1]! +100019f4: f240 811c bls.w 10001c30 <_ftoa+0x3a8> +100019f8: 468a mov sl, r1 +100019fa: 461d mov r5, r3 +100019fc: 2d20 cmp r5, #32 +100019fe: f105 0301 add.w r3, r5, #1 +10001a02: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001a06: d1e9 bne.n 100019dc <_ftoa+0x154> +10001a08: 2520 movs r5, #32 +10001a0a: 1e69 subs r1, r5, #1 +10001a0c: ab0e add r3, sp, #56 @ 0x38 +10001a0e: 4861 ldr r0, [pc, #388] @ (10001b94 <_ftoa+0x30c>) +10001a10: 4419 add r1, r3 +10001a12: e010 b.n 10001a36 <_ftoa+0x1ae> +10001a14: fb80 6204 smull r6, r2, r0, r4 +10001a18: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001a1c: eb03 0283 add.w r2, r3, r3, lsl #2 +10001a20: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001a24: f104 0230 add.w r2, r4, #48 @ 0x30 +10001a28: 3501 adds r5, #1 +10001a2a: 461c mov r4, r3 +10001a2c: f801 2f01 strb.w r2, [r1, #1]! +10001a30: 2b00 cmp r3, #0 +10001a32: f000 80eb beq.w 10001c0c <_ftoa+0x384> +10001a36: 2d20 cmp r5, #32 +10001a38: ea4f 73e4 mov.w r3, r4, asr #31 +10001a3c: d1ea bne.n 10001a14 <_ftoa+0x18c> +10001a3e: 9b07 ldr r3, [sp, #28] +10001a40: f003 0303 and.w r3, r3, #3 +10001a44: 2b01 cmp r3, #1 +10001a46: d118 bne.n 10001a7a <_ftoa+0x1f2> +10001a48: f1bb 0f00 cmp.w fp, #0 +10001a4c: d015 beq.n 10001a7a <_ftoa+0x1f2> +10001a4e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001a50: 2b00 cmp r3, #0 +10001a52: f000 810a beq.w 10001c6a <_ftoa+0x3e2> +10001a56: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001a5a: f1bb 0f20 cmp.w fp, #32 +10001a5e: d90c bls.n 10001a7a <_ftoa+0x1f2> +10001a60: 1e6b subs r3, r5, #1 +10001a62: a90e add r1, sp, #56 @ 0x38 +10001a64: 2230 movs r2, #48 @ 0x30 +10001a66: 440b add r3, r1 +10001a68: e005 b.n 10001a76 <_ftoa+0x1ee> +10001a6a: 3501 adds r5, #1 +10001a6c: 455d cmp r5, fp +10001a6e: f803 2f01 strb.w r2, [r3, #1]! +10001a72: f080 80d1 bcs.w 10001c18 <_ftoa+0x390> +10001a76: 2d20 cmp r5, #32 +10001a78: d1f7 bne.n 10001a6a <_ftoa+0x1e2> +10001a7a: 9b07 ldr r3, [sp, #28] +10001a7c: ac0e add r4, sp, #56 @ 0x38 +10001a7e: e9cd b302 strd fp, r3, [sp, #8] +10001a82: 4641 mov r1, r8 +10001a84: 464b mov r3, r9 +10001a86: 4638 mov r0, r7 +10001a88: 9a0c ldr r2, [sp, #48] @ 0x30 +10001a8a: 9501 str r5, [sp, #4] +10001a8c: 9400 str r4, [sp, #0] +10001a8e: f7ff fdb9 bl 10001604 <_out_rev> +10001a92: 4682 mov sl, r0 +10001a94: 4650 mov r0, sl +10001a96: b017 add sp, #92 @ 0x5c +10001a98: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001a9c: 9b07 ldr r3, [sp, #28] +10001a9e: ed9d 7b04 vldr d7, [sp, #16] +10001aa2: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001aa6: 4641 mov r1, r8 +10001aa8: 464b mov r3, r9 +10001aaa: 4638 mov r0, r7 +10001aac: 9a0c ldr r2, [sp, #48] @ 0x30 +10001aae: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001ab2: 9522 str r5, [sp, #136] @ 0x88 +10001ab4: b017 add sp, #92 @ 0x5c +10001ab6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001aba: f000 b945 b.w 10001d48 <_etoa> +10001abe: 0761 lsls r1, r4, #29 +10001ac0: 4623 mov r3, r4 +10001ac2: bf4c ite mi +10001ac4: 2304 movmi r3, #4 +10001ac6: 2303 movpl r3, #3 +10001ac8: 4641 mov r1, r8 +10001aca: 9321 str r3, [sp, #132] @ 0x84 +10001acc: 4638 mov r0, r7 +10001ace: 464b mov r3, r9 +10001ad0: 9a07 ldr r2, [sp, #28] +10001ad2: bf48 it mi +10001ad4: 4c30 ldrmi r4, [pc, #192] @ (10001b98 <_ftoa+0x310>) +10001ad6: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001ada: bf58 it pl +10001adc: 4c2f ldrpl r4, [pc, #188] @ (10001b9c <_ftoa+0x314>) +10001ade: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ae0: 9420 str r4, [sp, #128] @ 0x80 +10001ae2: b017 add sp, #92 @ 0x5c +10001ae4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ae8: f7ff bd8c b.w 10001604 <_out_rev> +10001aec: e9dd 2304 ldrd r2, r3, [sp, #16] +10001af0: 2000 movs r0, #0 +10001af2: 2100 movs r1, #0 +10001af4: f7ff fc56 bl 100013a4 <__wrap___aeabi_dsub> +10001af8: 2301 movs r3, #1 +10001afa: e9cd 0104 strd r0, r1, [sp, #16] +10001afe: 930d str r3, [sp, #52] @ 0x34 +10001b00: 4623 mov r3, r4 +10001b02: e70d b.n 10001920 <_ftoa+0x98> +10001b04: 4623 mov r3, r4 +10001b06: 079c lsls r4, r3, #30 +10001b08: f040 80aa bne.w 10001c60 <_ftoa+0x3d8> +10001b0c: f1bb 0f04 cmp.w fp, #4 +10001b10: f240 80a6 bls.w 10001c60 <_ftoa+0x3d8> +10001b14: 9b0c ldr r3, [sp, #48] @ 0x30 +10001b16: 461d mov r5, r3 +10001b18: 1f1c subs r4, r3, #4 +10001b1a: eb04 0a0b add.w sl, r4, fp +10001b1e: 462a mov r2, r5 +10001b20: 464b mov r3, r9 +10001b22: 4641 mov r1, r8 +10001b24: 2020 movs r0, #32 +10001b26: 3501 adds r5, #1 +10001b28: 47b8 blx r7 +10001b2a: 45aa cmp sl, r5 +10001b2c: d1f7 bne.n 10001b1e <_ftoa+0x296> +10001b2e: 4655 mov r5, sl +10001b30: 4c1b ldr r4, [pc, #108] @ (10001ba0 <_ftoa+0x318>) +10001b32: 1f26 subs r6, r4, #4 +10001b34: f814 0d01 ldrb.w r0, [r4, #-1]! +10001b38: 462a mov r2, r5 +10001b3a: 464b mov r3, r9 +10001b3c: 4641 mov r1, r8 +10001b3e: 47b8 blx r7 +10001b40: 42b4 cmp r4, r6 +10001b42: f105 0501 add.w r5, r5, #1 +10001b46: d1f5 bne.n 10001b34 <_ftoa+0x2ac> +10001b48: 9b07 ldr r3, [sp, #28] +10001b4a: f10a 0a04 add.w sl, sl, #4 +10001b4e: 0798 lsls r0, r3, #30 +10001b50: d5a0 bpl.n 10001a94 <_ftoa+0x20c> +10001b52: 9c0c ldr r4, [sp, #48] @ 0x30 +10001b54: ebaa 0304 sub.w r3, sl, r4 +10001b58: 459b cmp fp, r3 +10001b5a: d99b bls.n 10001a94 <_ftoa+0x20c> +10001b5c: 4652 mov r2, sl +10001b5e: 464b mov r3, r9 +10001b60: 4641 mov r1, r8 +10001b62: 2020 movs r0, #32 +10001b64: f10a 0a01 add.w sl, sl, #1 +10001b68: 47b8 blx r7 +10001b6a: ebaa 0304 sub.w r3, sl, r4 +10001b6e: 455b cmp r3, fp +10001b70: d3f4 bcc.n 10001b5c <_ftoa+0x2d4> +10001b72: e78f b.n 10001a94 <_ftoa+0x20c> +10001b74: f3af 8000 nop.w +10001b78: 00000000 .word 0x00000000 +10001b7c: 41cdcd65 .word 0x41cdcd65 +10001b80: 00000000 .word 0x00000000 +10001b84: c1cdcd65 .word 0xc1cdcd65 +10001b88: 7fefffff .word 0x7fefffff +10001b8c: 100035e8 .word 0x100035e8 +10001b90: 3fe00000 .word 0x3fe00000 +10001b94: 66666667 .word 0x66666667 +10001b98: 10003540 .word 0x10003540 +10001b9c: 10003548 .word 0x10003548 +10001ba0: 10003554 .word 0x10003554 +10001ba4: cccccccd .word 0xcccccccd +10001ba8: 2200 movs r2, #0 +10001baa: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001bae: 4b63 ldr r3, [pc, #396] @ (10001d3c <_ftoa+0x4b4>) +10001bb0: f7ff fcda bl 10001568 <__wrap___aeabi_dcmplt> +10001bb4: 2800 cmp r0, #0 +10001bb6: f47f af08 bne.w 100019ca <_ftoa+0x142> +10001bba: f1ba 0f00 cmp.w sl, #0 +10001bbe: d16a bne.n 10001c96 <_ftoa+0x40e> +10001bc0: f10a 0a01 add.w sl, sl, #1 +10001bc4: 2e00 cmp r6, #0 +10001bc6: f47f af03 bne.w 100019d0 <_ftoa+0x148> +10001bca: 4620 mov r0, r4 +10001bcc: f7ff fc72 bl 100014b4 <__wrap___aeabi_i2d> +10001bd0: 4602 mov r2, r0 +10001bd2: 460b mov r3, r1 +10001bd4: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bd8: f7ff fbe4 bl 100013a4 <__wrap___aeabi_dsub> +10001bdc: 4602 mov r2, r0 +10001bde: 460b mov r3, r1 +10001be0: e9cd 2304 strd r2, r3, [sp, #16] +10001be4: 2200 movs r2, #0 +10001be6: 4b55 ldr r3, [pc, #340] @ (10001d3c <_ftoa+0x4b4>) +10001be8: f7ff fcbe bl 10001568 <__wrap___aeabi_dcmplt> +10001bec: 2800 cmp r0, #0 +10001bee: f47f af0c bne.w 10001a0a <_ftoa+0x182> +10001bf2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bf6: 2200 movs r2, #0 +10001bf8: 4b50 ldr r3, [pc, #320] @ (10001d3c <_ftoa+0x4b4>) +10001bfa: f7ff fcf1 bl 100015e0 <__wrap___aeabi_dcmpgt> +10001bfe: 2800 cmp r0, #0 +10001c00: f47f af03 bne.w 10001a0a <_ftoa+0x182> +10001c04: 3401 adds r4, #1 +10001c06: f024 0401 bic.w r4, r4, #1 +10001c0a: e6fe b.n 10001a0a <_ftoa+0x182> +10001c0c: 9b07 ldr r3, [sp, #28] +10001c0e: f003 0303 and.w r3, r3, #3 +10001c12: 2b01 cmp r3, #1 +10001c14: f000 8082 beq.w 10001d1c <_ftoa+0x494> +10001c18: 2d20 cmp r5, #32 +10001c1a: f43f af2e beq.w 10001a7a <_ftoa+0x1f2> +10001c1e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001c20: b37b cbz r3, 10001c82 <_ftoa+0x3fa> +10001c22: 222d movs r2, #45 @ 0x2d +10001c24: eb0d 0305 add.w r3, sp, r5 +10001c28: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c2c: 3501 adds r5, #1 +10001c2e: e724 b.n 10001a7a <_ftoa+0x1f2> +10001c30: 2b20 cmp r3, #32 +10001c32: f43f aee9 beq.w 10001a08 <_ftoa+0x180> +10001c36: aa0e add r2, sp, #56 @ 0x38 +10001c38: 4415 add r5, r2 +10001c3a: 441e add r6, r3 +10001c3c: 2230 movs r2, #48 @ 0x30 +10001c3e: e004 b.n 10001c4a <_ftoa+0x3c2> +10001c40: 2b20 cmp r3, #32 +10001c42: f805 2f01 strb.w r2, [r5, #1]! +10001c46: f43f aedf beq.w 10001a08 <_ftoa+0x180> +10001c4a: 429e cmp r6, r3 +10001c4c: f103 0301 add.w r3, r3, #1 +10001c50: d1f6 bne.n 10001c40 <_ftoa+0x3b8> +10001c52: 222e movs r2, #46 @ 0x2e +10001c54: eb0d 0306 add.w r3, sp, r6 +10001c58: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c5c: 1c75 adds r5, r6, #1 +10001c5e: e6d4 b.n 10001a0a <_ftoa+0x182> +10001c60: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001c64: e763 b.n 10001b2e <_ftoa+0x2a6> +10001c66: 2520 movs r5, #32 +10001c68: e66e b.n 10001948 <_ftoa+0xc0> +10001c6a: 9b07 ldr r3, [sp, #28] +10001c6c: f013 0f0c tst.w r3, #12 +10001c70: d050 beq.n 10001d14 <_ftoa+0x48c> +10001c72: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001c76: 45ab cmp fp, r5 +10001c78: f63f aef2 bhi.w 10001a60 <_ftoa+0x1d8> +10001c7c: 2d20 cmp r5, #32 +10001c7e: f43f aefc beq.w 10001a7a <_ftoa+0x1f2> +10001c82: 9b07 ldr r3, [sp, #28] +10001c84: 075a lsls r2, r3, #29 +10001c86: d501 bpl.n 10001c8c <_ftoa+0x404> +10001c88: 222b movs r2, #43 @ 0x2b +10001c8a: e7cb b.n 10001c24 <_ftoa+0x39c> +10001c8c: 071b lsls r3, r3, #28 +10001c8e: f57f aef4 bpl.w 10001a7a <_ftoa+0x1f2> +10001c92: 2220 movs r2, #32 +10001c94: e7c6 b.n 10001c24 <_ftoa+0x39c> +10001c96: f01a 0f01 tst.w sl, #1 +10001c9a: f43f ae96 beq.w 100019ca <_ftoa+0x142> +10001c9e: e78f b.n 10001bc0 <_ftoa+0x338> +10001ca0: 07a6 lsls r6, r4, #30 +10001ca2: d134 bne.n 10001d0e <_ftoa+0x486> +10001ca4: f1bb 0f03 cmp.w fp, #3 +10001ca8: d931 bls.n 10001d0e <_ftoa+0x486> +10001caa: 9b0c ldr r3, [sp, #48] @ 0x30 +10001cac: 461d mov r5, r3 +10001cae: 1edc subs r4, r3, #3 +10001cb0: eb04 0a0b add.w sl, r4, fp +10001cb4: 462a mov r2, r5 +10001cb6: 464b mov r3, r9 +10001cb8: 4641 mov r1, r8 +10001cba: 2020 movs r0, #32 +10001cbc: 3501 adds r5, #1 +10001cbe: 47b8 blx r7 +10001cc0: 4555 cmp r5, sl +10001cc2: d1f7 bne.n 10001cb4 <_ftoa+0x42c> +10001cc4: 4655 mov r5, sl +10001cc6: 4c1e ldr r4, [pc, #120] @ (10001d40 <_ftoa+0x4b8>) +10001cc8: 1ee6 subs r6, r4, #3 +10001cca: f814 0d01 ldrb.w r0, [r4, #-1]! +10001cce: 462a mov r2, r5 +10001cd0: 464b mov r3, r9 +10001cd2: 4641 mov r1, r8 +10001cd4: 47b8 blx r7 +10001cd6: 42a6 cmp r6, r4 +10001cd8: f105 0501 add.w r5, r5, #1 +10001cdc: d1f5 bne.n 10001cca <_ftoa+0x442> +10001cde: 9b07 ldr r3, [sp, #28] +10001ce0: f10a 0a03 add.w sl, sl, #3 +10001ce4: 079d lsls r5, r3, #30 +10001ce6: f57f aed5 bpl.w 10001a94 <_ftoa+0x20c> +10001cea: 9c0c ldr r4, [sp, #48] @ 0x30 +10001cec: ebaa 0304 sub.w r3, sl, r4 +10001cf0: 459b cmp fp, r3 +10001cf2: f67f aecf bls.w 10001a94 <_ftoa+0x20c> +10001cf6: 4652 mov r2, sl +10001cf8: 464b mov r3, r9 +10001cfa: 4641 mov r1, r8 +10001cfc: 2020 movs r0, #32 +10001cfe: f10a 0a01 add.w sl, sl, #1 +10001d02: 47b8 blx r7 +10001d04: ebaa 0304 sub.w r3, sl, r4 +10001d08: 459b cmp fp, r3 +10001d0a: d8f4 bhi.n 10001cf6 <_ftoa+0x46e> +10001d0c: e6c2 b.n 10001a94 <_ftoa+0x20c> +10001d0e: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001d12: e7d7 b.n 10001cc4 <_ftoa+0x43c> +10001d14: 45ab cmp fp, r5 +10001d16: f63f aea3 bhi.w 10001a60 <_ftoa+0x1d8> +10001d1a: e6ae b.n 10001a7a <_ftoa+0x1f2> +10001d1c: f1bb 0f00 cmp.w fp, #0 +10001d20: f43f af7a beq.w 10001c18 <_ftoa+0x390> +10001d24: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d26: 2b00 cmp r3, #0 +10001d28: d09f beq.n 10001c6a <_ftoa+0x3e2> +10001d2a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d2e: 455d cmp r5, fp +10001d30: f4ff ae96 bcc.w 10001a60 <_ftoa+0x1d8> +10001d34: 2d20 cmp r5, #32 +10001d36: f47f af74 bne.w 10001c22 <_ftoa+0x39a> +10001d3a: e69e b.n 10001a7a <_ftoa+0x1f2> +10001d3c: 3fe00000 .word 0x3fe00000 +10001d40: 1000354f .word 0x1000354f +10001d44: 00000000 .word 0x00000000 + +10001d48 <_etoa>: +10001d48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001d4c: b09f sub sp, #124 @ 0x7c +10001d4e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001d50: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001d54: 4607 mov r7, r0 +10001d56: 4693 mov fp, r2 +10001d58: 9108 str r1, [sp, #32] +10001d5a: 9309 str r3, [sp, #36] @ 0x24 +10001d5c: 4622 mov r2, r4 +10001d5e: 462b mov r3, r5 +10001d60: 4620 mov r0, r4 +10001d62: 4629 mov r1, r5 +10001d64: 960e str r6, [sp, #56] @ 0x38 +10001d66: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001d6a: f7ff fbeb bl 10001544 <__wrap___aeabi_dcmpun> +10001d6e: 2800 cmp r0, #0 +10001d70: f040 80be bne.w 10001ef0 <_etoa+0x1a8> +10001d74: 4620 mov r0, r4 +10001d76: 4629 mov r1, r5 +10001d78: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d7c: 4b78 ldr r3, [pc, #480] @ (10001f60 <_etoa+0x218>) +10001d7e: f7ff fc2f bl 100015e0 <__wrap___aeabi_dcmpgt> +10001d82: 2800 cmp r0, #0 +10001d84: f040 80b4 bne.w 10001ef0 <_etoa+0x1a8> +10001d88: 4620 mov r0, r4 +10001d8a: 4629 mov r1, r5 +10001d8c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d90: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001d94: f7ff fbe8 bl 10001568 <__wrap___aeabi_dcmplt> +10001d98: 2800 cmp r0, #0 +10001d9a: f040 80a9 bne.w 10001ef0 <_etoa+0x1a8> +10001d9e: 4620 mov r0, r4 +10001da0: 4629 mov r1, r5 +10001da2: 2200 movs r2, #0 +10001da4: 2300 movs r3, #0 +10001da6: f7ff fbdf bl 10001568 <__wrap___aeabi_dcmplt> +10001daa: 2800 cmp r0, #0 +10001dac: f040 81d5 bne.w 1000215a <_etoa+0x412> +10001db0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001db4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001db8: 4690 mov r8, r2 +10001dba: 4699 mov r9, r3 +10001dbc: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001dc0: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001dc4: 920f str r2, [sp, #60] @ 0x3c +10001dc6: 9313 str r3, [sp, #76] @ 0x4c +10001dc8: f040 80a1 bne.w 10001f0e <_etoa+0x1c6> +10001dcc: ea58 0309 orrs.w r3, r8, r9 +10001dd0: f040 80ca bne.w 10001f68 <_etoa+0x220> +10001dd4: 2a00 cmp r2, #0 +10001dd6: f040 81e3 bne.w 100021a0 <_etoa+0x458> +10001dda: 2306 movs r3, #6 +10001ddc: 930e str r3, [sp, #56] @ 0x38 +10001dde: f016 0202 ands.w r2, r6, #2 +10001de2: 9210 str r2, [sp, #64] @ 0x40 +10001de4: f040 81d4 bne.w 10002190 <_etoa+0x448> +10001de8: 4653 mov r3, sl +10001dea: 2b04 cmp r3, #4 +10001dec: bf38 it cc +10001dee: 2304 movcc r3, #4 +10001df0: 920c str r2, [sp, #48] @ 0x30 +10001df2: 2204 movs r2, #4 +10001df4: 3b04 subs r3, #4 +10001df6: 9212 str r2, [sp, #72] @ 0x48 +10001df8: 930f str r3, [sp, #60] @ 0x3c +10001dfa: 4620 mov r0, r4 +10001dfc: 4629 mov r1, r5 +10001dfe: 2200 movs r2, #0 +10001e00: 2300 movs r3, #0 +10001e02: f7ff fbb1 bl 10001568 <__wrap___aeabi_dcmplt> +10001e06: 2800 cmp r0, #0 +10001e08: f040 81f3 bne.w 100021f2 <_etoa+0x4aa> +10001e0c: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001e10: 9b0f ldr r3, [sp, #60] @ 0x3c +10001e12: 465a mov r2, fp +10001e14: 9303 str r3, [sp, #12] +10001e16: 9b0e ldr r3, [sp, #56] @ 0x38 +10001e18: ed8d 7b00 vstr d7, [sp] +10001e1c: 9302 str r3, [sp, #8] +10001e1e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001e22: 9304 str r3, [sp, #16] +10001e24: 4638 mov r0, r7 +10001e26: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e28: 9908 ldr r1, [sp, #32] +10001e2a: f7ff fd2d bl 10001888 <_ftoa> +10001e2e: 4602 mov r2, r0 +10001e30: f016 0f20 tst.w r6, #32 +10001e34: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e36: 9908 ldr r1, [sp, #32] +10001e38: bf0c ite eq +10001e3a: 2065 moveq r0, #101 @ 0x65 +10001e3c: 2045 movne r0, #69 @ 0x45 +10001e3e: f102 0801 add.w r8, r2, #1 +10001e42: 47b8 blx r7 +10001e44: 9a0c ldr r2, [sp, #48] @ 0x30 +10001e46: 9b12 ldr r3, [sp, #72] @ 0x48 +10001e48: ac16 add r4, sp, #88 @ 0x58 +10001e4a: 1e5d subs r5, r3, #1 +10001e4c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001e50: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001e54: 0fd1 lsrs r1, r2, #31 +10001e56: 2600 movs r6, #0 +10001e58: 4622 mov r2, r4 +10001e5a: 4699 mov r9, r3 +10001e5c: f8df c104 ldr.w ip, [pc, #260] @ 10001f64 <_etoa+0x21c> +10001e60: e001 b.n 10001e66 <_etoa+0x11e> +10001e62: 2e20 cmp r6, #32 +10001e64: d010 beq.n 10001e88 <_etoa+0x140> +10001e66: 46ce mov lr, r9 +10001e68: fbac 3009 umull r3, r0, ip, r9 +10001e6c: 08c0 lsrs r0, r0, #3 +10001e6e: eb00 0380 add.w r3, r0, r0, lsl #2 +10001e72: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001e76: 3330 adds r3, #48 @ 0x30 +10001e78: f1be 0f09 cmp.w lr, #9 +10001e7c: 4681 mov r9, r0 +10001e7e: f106 0601 add.w r6, r6, #1 +10001e82: f802 3b01 strb.w r3, [r2], #1 +10001e86: d8ec bhi.n 10001e62 <_etoa+0x11a> +10001e88: 2305 movs r3, #5 +10001e8a: 2000 movs r0, #0 +10001e8c: 9306 str r3, [sp, #24] +10001e8e: 230a movs r3, #10 +10001e90: 9505 str r5, [sp, #20] +10001e92: 9400 str r4, [sp, #0] +10001e94: 9d09 ldr r5, [sp, #36] @ 0x24 +10001e96: 9c08 ldr r4, [sp, #32] +10001e98: 4642 mov r2, r8 +10001e9a: e9cd 3003 strd r3, r0, [sp, #12] +10001e9e: e9cd 6101 strd r6, r1, [sp, #4] +10001ea2: 462b mov r3, r5 +10001ea4: 4621 mov r1, r4 +10001ea6: 4638 mov r0, r7 +10001ea8: f7ff fbfa bl 100016a0 <_ntoa_format> +10001eac: 9a10 ldr r2, [sp, #64] @ 0x40 +10001eae: 4680 mov r8, r0 +10001eb0: b1d2 cbz r2, 10001ee8 <_etoa+0x1a0> +10001eb2: eba0 060b sub.w r6, r0, fp +10001eb6: 45b2 cmp sl, r6 +10001eb8: d916 bls.n 10001ee8 <_etoa+0x1a0> +10001eba: eb0b 0206 add.w r2, fp, r6 +10001ebe: 462b mov r3, r5 +10001ec0: 4621 mov r1, r4 +10001ec2: 2020 movs r0, #32 +10001ec4: 3601 adds r6, #1 +10001ec6: 47b8 blx r7 +10001ec8: 45b2 cmp sl, r6 +10001eca: d8f6 bhi.n 10001eba <_etoa+0x172> +10001ecc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10001ed0: 4453 add r3, sl +10001ed2: f1cb 0201 rsb r2, fp, #1 +10001ed6: eba3 0308 sub.w r3, r3, r8 +10001eda: 4442 add r2, r8 +10001edc: 4592 cmp sl, r2 +10001ede: bf38 it cc +10001ee0: 2300 movcc r3, #0 +10001ee2: f108 0801 add.w r8, r8, #1 +10001ee6: 4498 add r8, r3 +10001ee8: 4640 mov r0, r8 +10001eea: b01f add sp, #124 @ 0x7c +10001eec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001ef0: 465a mov r2, fp +10001ef2: 4638 mov r0, r7 +10001ef4: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10001ef8: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10001efc: 9c0e ldr r4, [sp, #56] @ 0x38 +10001efe: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f00: 9908 ldr r1, [sp, #32] +10001f02: 942a str r4, [sp, #168] @ 0xa8 +10001f04: b01f add sp, #124 @ 0x7c +10001f06: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f0a: f7ff bcbd b.w 10001888 <_ftoa> +10001f0e: ea58 0309 orrs.w r3, r8, r9 +10001f12: d12b bne.n 10001f6c <_etoa+0x224> +10001f14: 2a00 cmp r2, #0 +10001f16: f43f af62 beq.w 10001dde <_etoa+0x96> +10001f1a: 2300 movs r3, #0 +10001f1c: 930c str r3, [sp, #48] @ 0x30 +10001f1e: 9b0e ldr r3, [sp, #56] @ 0x38 +10001f20: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f22: 4293 cmp r3, r2 +10001f24: f300 81b9 bgt.w 1000229a <_etoa+0x552> +10001f28: f04f 0800 mov.w r8, #0 +10001f2c: 4620 mov r0, r4 +10001f2e: 4629 mov r1, r5 +10001f30: 2200 movs r2, #0 +10001f32: 2300 movs r3, #0 +10001f34: f7ff fb18 bl 10001568 <__wrap___aeabi_dcmplt> +10001f38: 2800 cmp r0, #0 +10001f3a: f040 8113 bne.w 10002164 <_etoa+0x41c> +10001f3e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001f42: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10001f46: f446 6680 orr.w r6, r6, #1024 @ 0x400 +10001f4a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +10001f4e: 465a mov r2, fp +10001f50: 4638 mov r0, r7 +10001f52: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10001f56: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f58: 9908 ldr r1, [sp, #32] +10001f5a: 962c str r6, [sp, #176] @ 0xb0 +10001f5c: e7d2 b.n 10001f04 <_etoa+0x1bc> +10001f5e: bf00 nop +10001f60: 7fefffff .word 0x7fefffff +10001f64: cccccccd .word 0xcccccccd +10001f68: 2306 movs r3, #6 +10001f6a: 930e str r3, [sp, #56] @ 0x38 +10001f6c: f3c9 500a ubfx r0, r9, #20, #11 +10001f70: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10001f74: f7ff fa9e bl 100014b4 <__wrap___aeabi_i2d> +10001f78: a3c1 add r3, pc, #772 @ (adr r3, 10002280 <_etoa+0x538>) +10001f7a: e9d3 2300 ldrd r2, r3, [r3] +10001f7e: f7ff fa25 bl 100013cc <__wrap___aeabi_dmul> +10001f82: a3c1 add r3, pc, #772 @ (adr r3, 10002288 <_etoa+0x540>) +10001f84: e9d3 2300 ldrd r2, r3, [r3] +10001f88: f7ff f9f8 bl 1000137c <__wrap___aeabi_dadd> +10001f8c: f3c9 0913 ubfx r9, r9, #0, #20 +10001f90: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10001f94: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10001f98: 4640 mov r0, r8 +10001f9a: 2200 movs r2, #0 +10001f9c: 4bb2 ldr r3, [pc, #712] @ (10002268 <_etoa+0x520>) +10001f9e: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10001fa2: f7ff f9ff bl 100013a4 <__wrap___aeabi_dsub> +10001fa6: a3a4 add r3, pc, #656 @ (adr r3, 10002238 <_etoa+0x4f0>) +10001fa8: e9d3 2300 ldrd r2, r3, [r3] +10001fac: f7ff fa0e bl 100013cc <__wrap___aeabi_dmul> +10001fb0: 4602 mov r2, r0 +10001fb2: 460b mov r3, r1 +10001fb4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10001fb8: f7ff f9e0 bl 1000137c <__wrap___aeabi_dadd> +10001fbc: f7ff fa9e bl 100014fc <__wrap___aeabi_d2iz> +10001fc0: 900c str r0, [sp, #48] @ 0x30 +10001fc2: f7ff fa77 bl 100014b4 <__wrap___aeabi_i2d> +10001fc6: a39e add r3, pc, #632 @ (adr r3, 10002240 <_etoa+0x4f8>) +10001fc8: e9d3 2300 ldrd r2, r3, [r3] +10001fcc: 4680 mov r8, r0 +10001fce: 4689 mov r9, r1 +10001fd0: f7ff f9fc bl 100013cc <__wrap___aeabi_dmul> +10001fd4: 2200 movs r2, #0 +10001fd6: 4ba5 ldr r3, [pc, #660] @ (1000226c <_etoa+0x524>) +10001fd8: f7ff f9d0 bl 1000137c <__wrap___aeabi_dadd> +10001fdc: f7ff fa8e bl 100014fc <__wrap___aeabi_d2iz> +10001fe0: 4603 mov r3, r0 +10001fe2: 4649 mov r1, r9 +10001fe4: 4640 mov r0, r8 +10001fe6: 9312 str r3, [sp, #72] @ 0x48 +10001fe8: a397 add r3, pc, #604 @ (adr r3, 10002248 <_etoa+0x500>) +10001fea: e9d3 2300 ldrd r2, r3, [r3] +10001fee: f7ff f9ed bl 100013cc <__wrap___aeabi_dmul> +10001ff2: 4680 mov r8, r0 +10001ff4: 9812 ldr r0, [sp, #72] @ 0x48 +10001ff6: 4689 mov r9, r1 +10001ff8: f7ff fa5c bl 100014b4 <__wrap___aeabi_i2d> +10001ffc: a394 add r3, pc, #592 @ (adr r3, 10002250 <_etoa+0x508>) +10001ffe: e9d3 2300 ldrd r2, r3, [r3] +10002002: f7ff f9e3 bl 100013cc <__wrap___aeabi_dmul> +10002006: 4602 mov r2, r0 +10002008: 460b mov r3, r1 +1000200a: 4640 mov r0, r8 +1000200c: 4649 mov r1, r9 +1000200e: f7ff f9c9 bl 100013a4 <__wrap___aeabi_dsub> +10002012: 4602 mov r2, r0 +10002014: 460b mov r3, r1 +10002016: 4680 mov r8, r0 +10002018: 4689 mov r9, r1 +1000201a: f7ff f9d7 bl 100013cc <__wrap___aeabi_dmul> +1000201e: 4642 mov r2, r8 +10002020: 464b mov r3, r9 +10002022: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002026: 4640 mov r0, r8 +10002028: 4649 mov r1, r9 +1000202a: f7ff f9a7 bl 1000137c <__wrap___aeabi_dadd> +1000202e: 2200 movs r2, #0 +10002030: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10002034: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002038: 4b8d ldr r3, [pc, #564] @ (10002270 <_etoa+0x528>) +1000203a: f7ff f9ed bl 10001418 <__wrap___aeabi_ddiv> +1000203e: 2200 movs r2, #0 +10002040: 4b8c ldr r3, [pc, #560] @ (10002274 <_etoa+0x52c>) +10002042: f7ff f99b bl 1000137c <__wrap___aeabi_dadd> +10002046: 4602 mov r2, r0 +10002048: 460b mov r3, r1 +1000204a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000204e: f7ff f9e3 bl 10001418 <__wrap___aeabi_ddiv> +10002052: 2200 movs r2, #0 +10002054: 4b88 ldr r3, [pc, #544] @ (10002278 <_etoa+0x530>) +10002056: f7ff f991 bl 1000137c <__wrap___aeabi_dadd> +1000205a: 4602 mov r2, r0 +1000205c: 460b mov r3, r1 +1000205e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002062: f7ff f9d9 bl 10001418 <__wrap___aeabi_ddiv> +10002066: 4642 mov r2, r8 +10002068: 464b mov r3, r9 +1000206a: 4680 mov r8, r0 +1000206c: 4689 mov r9, r1 +1000206e: 2000 movs r0, #0 +10002070: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002074: f7ff f996 bl 100013a4 <__wrap___aeabi_dsub> +10002078: 4602 mov r2, r0 +1000207a: 460b mov r3, r1 +1000207c: 4640 mov r0, r8 +1000207e: 4649 mov r1, r9 +10002080: f7ff f97c bl 1000137c <__wrap___aeabi_dadd> +10002084: 4602 mov r2, r0 +10002086: 460b mov r3, r1 +10002088: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000208c: f7ff f9c4 bl 10001418 <__wrap___aeabi_ddiv> +10002090: 2200 movs r2, #0 +10002092: 4b7a ldr r3, [pc, #488] @ (1000227c <_etoa+0x534>) +10002094: f7ff f972 bl 1000137c <__wrap___aeabi_dadd> +10002098: 9b12 ldr r3, [sp, #72] @ 0x48 +1000209a: 2200 movs r2, #0 +1000209c: f203 3cff addw ip, r3, #1023 @ 0x3ff +100020a0: ea4f 530c mov.w r3, ip, lsl #20 +100020a4: f7ff f992 bl 100013cc <__wrap___aeabi_dmul> +100020a8: 4680 mov r8, r0 +100020aa: 4689 mov r9, r1 +100020ac: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100020b0: 4642 mov r2, r8 +100020b2: 464b mov r3, r9 +100020b4: f7ff fa58 bl 10001568 <__wrap___aeabi_dcmplt> +100020b8: b150 cbz r0, 100020d0 <_etoa+0x388> +100020ba: 9b0c ldr r3, [sp, #48] @ 0x30 +100020bc: 4640 mov r0, r8 +100020be: 3b01 subs r3, #1 +100020c0: 4649 mov r1, r9 +100020c2: 930c str r3, [sp, #48] @ 0x30 +100020c4: 2200 movs r2, #0 +100020c6: 4b6b ldr r3, [pc, #428] @ (10002274 <_etoa+0x52c>) +100020c8: f7ff f9a6 bl 10001418 <__wrap___aeabi_ddiv> +100020cc: 4680 mov r8, r0 +100020ce: 4689 mov r9, r1 +100020d0: 9a0c ldr r2, [sp, #48] @ 0x30 +100020d2: 4643 mov r3, r8 +100020d4: 3263 adds r2, #99 @ 0x63 +100020d6: 2ac6 cmp r2, #198 @ 0xc6 +100020d8: f006 0202 and.w r2, r6, #2 +100020dc: 9210 str r2, [sp, #64] @ 0x40 +100020de: 4649 mov r1, r9 +100020e0: 9a0f ldr r2, [sp, #60] @ 0x3c +100020e2: d82c bhi.n 1000213e <_etoa+0x3f6> +100020e4: 2a00 cmp r2, #0 +100020e6: d05e beq.n 100021a6 <_etoa+0x45e> +100020e8: 2204 movs r2, #4 +100020ea: 9212 str r2, [sp, #72] @ 0x48 +100020ec: 430b orrs r3, r1 +100020ee: f43f af16 beq.w 10001f1e <_etoa+0x1d6> +100020f2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100020f6: a358 add r3, pc, #352 @ (adr r3, 10002258 <_etoa+0x510>) +100020f8: e9d3 2300 ldrd r2, r3, [r3] +100020fc: f7ff fa5c bl 100015b8 <__wrap___aeabi_dcmpge> +10002100: b148 cbz r0, 10002116 <_etoa+0x3ce> +10002102: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002106: a356 add r3, pc, #344 @ (adr r3, 10002260 <_etoa+0x518>) +10002108: e9d3 2300 ldrd r2, r3, [r3] +1000210c: f7ff fa2c bl 10001568 <__wrap___aeabi_dcmplt> +10002110: 2800 cmp r0, #0 +10002112: f47f af04 bne.w 10001f1e <_etoa+0x1d6> +10002116: 9b0e ldr r3, [sp, #56] @ 0x38 +10002118: 2b00 cmp r3, #0 +1000211a: d050 beq.n 100021be <_etoa+0x476> +1000211c: 9a13 ldr r2, [sp, #76] @ 0x4c +1000211e: 2a00 cmp r2, #0 +10002120: d07d beq.n 1000221e <_etoa+0x4d6> +10002122: 3b01 subs r3, #1 +10002124: 930e str r3, [sp, #56] @ 0x38 +10002126: 9b12 ldr r3, [sp, #72] @ 0x48 +10002128: 459a cmp sl, r3 +1000212a: d905 bls.n 10002138 <_etoa+0x3f0> +1000212c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000212e: 2b00 cmp r3, #0 +10002130: f000 80ae beq.w 10002290 <_etoa+0x548> +10002134: 2302 movs r3, #2 +10002136: 9310 str r3, [sp, #64] @ 0x40 +10002138: 2300 movs r3, #0 +1000213a: 930f str r3, [sp, #60] @ 0x3c +1000213c: e044 b.n 100021c8 <_etoa+0x480> +1000213e: bb22 cbnz r2, 1000218a <_etoa+0x442> +10002140: f1ba 0f05 cmp.w sl, #5 +10002144: d94f bls.n 100021e6 <_etoa+0x49e> +10002146: f006 0302 and.w r3, r6, #2 +1000214a: 2b00 cmp r3, #0 +1000214c: d149 bne.n 100021e2 <_etoa+0x49a> +1000214e: 2305 movs r3, #5 +10002150: 9312 str r3, [sp, #72] @ 0x48 +10002152: f1aa 0305 sub.w r3, sl, #5 +10002156: 930f str r3, [sp, #60] @ 0x3c +10002158: e03a b.n 100021d0 <_etoa+0x488> +1000215a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000215e: 940a str r4, [sp, #40] @ 0x28 +10002160: 930b str r3, [sp, #44] @ 0x2c +10002162: e627 b.n 10001db4 <_etoa+0x6c> +10002164: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002168: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000216c: 4638 mov r0, r7 +1000216e: 962c str r6, [sp, #176] @ 0xb0 +10002170: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002174: 4634 mov r4, r6 +10002176: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000217a: 465a mov r2, fp +1000217c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002180: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002184: 9b09 ldr r3, [sp, #36] @ 0x24 +10002186: 9908 ldr r1, [sp, #32] +10002188: e6bc b.n 10001f04 <_etoa+0x1bc> +1000218a: 2205 movs r2, #5 +1000218c: 9212 str r2, [sp, #72] @ 0x48 +1000218e: e7ad b.n 100020ec <_etoa+0x3a4> +10002190: 2300 movs r3, #0 +10002192: 2202 movs r2, #2 +10002194: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002198: 2204 movs r2, #4 +1000219a: 930c str r3, [sp, #48] @ 0x30 +1000219c: 9212 str r2, [sp, #72] @ 0x48 +1000219e: e62c b.n 10001dfa <_etoa+0xb2> +100021a0: f04f 0805 mov.w r8, #5 +100021a4: e6c2 b.n 10001f2c <_etoa+0x1e4> +100021a6: f1ba 0f04 cmp.w sl, #4 +100021aa: d91f bls.n 100021ec <_etoa+0x4a4> +100021ac: 9b10 ldr r3, [sp, #64] @ 0x40 +100021ae: 2b00 cmp r3, #0 +100021b0: d178 bne.n 100022a4 <_etoa+0x55c> +100021b2: 2304 movs r3, #4 +100021b4: 9312 str r3, [sp, #72] @ 0x48 +100021b6: f1aa 0304 sub.w r3, sl, #4 +100021ba: 930f str r3, [sp, #60] @ 0x3c +100021bc: e004 b.n 100021c8 <_etoa+0x480> +100021be: 9b12 ldr r3, [sp, #72] @ 0x48 +100021c0: 459a cmp sl, r3 +100021c2: d831 bhi.n 10002228 <_etoa+0x4e0> +100021c4: 9b0e ldr r3, [sp, #56] @ 0x38 +100021c6: 930f str r3, [sp, #60] @ 0x3c +100021c8: 9b0c ldr r3, [sp, #48] @ 0x30 +100021ca: 2b00 cmp r3, #0 +100021cc: f43f ae15 beq.w 10001dfa <_etoa+0xb2> +100021d0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100021d4: 4642 mov r2, r8 +100021d6: 464b mov r3, r9 +100021d8: f7ff f91e bl 10001418 <__wrap___aeabi_ddiv> +100021dc: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100021e0: e60b b.n 10001dfa <_etoa+0xb2> +100021e2: 2302 movs r3, #2 +100021e4: 9310 str r3, [sp, #64] @ 0x40 +100021e6: 2305 movs r3, #5 +100021e8: 9312 str r3, [sp, #72] @ 0x48 +100021ea: e7f1 b.n 100021d0 <_etoa+0x488> +100021ec: 2304 movs r3, #4 +100021ee: 9312 str r3, [sp, #72] @ 0x48 +100021f0: e7ea b.n 100021c8 <_etoa+0x480> +100021f2: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100021f6: 46a0 mov r8, r4 +100021f8: 9b0f ldr r3, [sp, #60] @ 0x3c +100021fa: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +100021fe: 9303 str r3, [sp, #12] +10002200: 9b0e ldr r3, [sp, #56] @ 0x38 +10002202: 465a mov r2, fp +10002204: 9302 str r3, [sp, #8] +10002206: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1000220a: 9304 str r3, [sp, #16] +1000220c: 4638 mov r0, r7 +1000220e: e9cd 8900 strd r8, r9, [sp] +10002212: 9b09 ldr r3, [sp, #36] @ 0x24 +10002214: 9908 ldr r1, [sp, #32] +10002216: f7ff fb37 bl 10001888 <_ftoa> +1000221a: 4602 mov r2, r0 +1000221c: e608 b.n 10001e30 <_etoa+0xe8> +1000221e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002220: 459a cmp sl, r3 +10002222: d844 bhi.n 100022ae <_etoa+0x566> +10002224: 920f str r2, [sp, #60] @ 0x3c +10002226: e7cf b.n 100021c8 <_etoa+0x480> +10002228: 9b10 ldr r3, [sp, #64] @ 0x40 +1000222a: b38b cbz r3, 10002290 <_etoa+0x548> +1000222c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000222e: 930f str r3, [sp, #60] @ 0x3c +10002230: 2302 movs r3, #2 +10002232: 9310 str r3, [sp, #64] @ 0x40 +10002234: e7c8 b.n 100021c8 <_etoa+0x480> +10002236: bf00 nop +10002238: 636f4361 .word 0x636f4361 +1000223c: 3fd287a7 .word 0x3fd287a7 +10002240: 0979a371 .word 0x0979a371 +10002244: 400a934f .word 0x400a934f +10002248: bbb55516 .word 0xbbb55516 +1000224c: 40026bb1 .word 0x40026bb1 +10002250: fefa39ef .word 0xfefa39ef +10002254: 3fe62e42 .word 0x3fe62e42 +10002258: eb1c432d .word 0xeb1c432d +1000225c: 3f1a36e2 .word 0x3f1a36e2 +10002260: 00000000 .word 0x00000000 +10002264: 412e8480 .word 0x412e8480 +10002268: 3ff80000 .word 0x3ff80000 +1000226c: 3fe00000 .word 0x3fe00000 +10002270: 402c0000 .word 0x402c0000 +10002274: 40240000 .word 0x40240000 +10002278: 40180000 .word 0x40180000 +1000227c: 3ff00000 .word 0x3ff00000 +10002280: 509f79fb .word 0x509f79fb +10002284: 3fd34413 .word 0x3fd34413 +10002288: 8b60c8b3 .word 0x8b60c8b3 +1000228c: 3fc68a28 .word 0x3fc68a28 +10002290: 9b12 ldr r3, [sp, #72] @ 0x48 +10002292: ebaa 0303 sub.w r3, sl, r3 +10002296: 930f str r3, [sp, #60] @ 0x3c +10002298: e796 b.n 100021c8 <_etoa+0x480> +1000229a: eba3 0802 sub.w r8, r3, r2 +1000229e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100022a2: e643 b.n 10001f2c <_etoa+0x1e4> +100022a4: 2304 movs r3, #4 +100022a6: 9312 str r3, [sp, #72] @ 0x48 +100022a8: 2302 movs r3, #2 +100022aa: 9310 str r3, [sp, #64] @ 0x40 +100022ac: e78c b.n 100021c8 <_etoa+0x480> +100022ae: 9b10 ldr r3, [sp, #64] @ 0x40 +100022b0: 2b00 cmp r3, #0 +100022b2: d0ed beq.n 10002290 <_etoa+0x548> +100022b4: 2302 movs r3, #2 +100022b6: 920f str r2, [sp, #60] @ 0x3c +100022b8: 9310 str r3, [sp, #64] @ 0x40 +100022ba: e785 b.n 100021c8 <_etoa+0x480> + +100022bc <_vsnprintf>: +100022bc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100022c0: b09b sub sp, #108 @ 0x6c +100022c2: 9c24 ldr r4, [sp, #144] @ 0x90 +100022c4: 4d95 ldr r5, [pc, #596] @ (1000251c <_vsnprintf+0x260>) +100022c6: 940a str r4, [sp, #40] @ 0x28 +100022c8: 4c95 ldr r4, [pc, #596] @ (10002520 <_vsnprintf+0x264>) +100022ca: f1b1 0a00 subs.w sl, r1, #0 +100022ce: bf18 it ne +100022d0: 4683 movne fp, r0 +100022d2: 6025 str r5, [r4, #0] +100022d4: 7818 ldrb r0, [r3, #0] +100022d6: 4c93 ldr r4, [pc, #588] @ (10002524 <_vsnprintf+0x268>) +100022d8: 4691 mov r9, r2 +100022da: bf08 it eq +100022dc: 46a3 moveq fp, r4 +100022de: 9309 str r3, [sp, #36] @ 0x24 +100022e0: 2800 cmp r0, #0 +100022e2: f000 8293 beq.w 1000280c <_vsnprintf+0x550> +100022e6: f04f 0800 mov.w r8, #0 +100022ea: e00a b.n 10002302 <_vsnprintf+0x46> +100022ec: 4642 mov r2, r8 +100022ee: 464b mov r3, r9 +100022f0: 4651 mov r1, sl +100022f2: f108 0801 add.w r8, r8, #1 +100022f6: 47d8 blx fp +100022f8: 9b09 ldr r3, [sp, #36] @ 0x24 +100022fa: 7818 ldrb r0, [r3, #0] +100022fc: 2800 cmp r0, #0 +100022fe: f000 80ce beq.w 1000249e <_vsnprintf+0x1e2> +10002302: 9b09 ldr r3, [sp, #36] @ 0x24 +10002304: 2825 cmp r0, #37 @ 0x25 +10002306: f103 0301 add.w r3, r3, #1 +1000230a: 9309 str r3, [sp, #36] @ 0x24 +1000230c: d1ee bne.n 100022ec <_vsnprintf+0x30> +1000230e: 461c mov r4, r3 +10002310: 2300 movs r3, #0 +10002312: 4622 mov r2, r4 +10002314: f812 0b01 ldrb.w r0, [r2], #1 +10002318: f1a0 0120 sub.w r1, r0, #32 +1000231c: 2910 cmp r1, #16 +1000231e: d80a bhi.n 10002336 <_vsnprintf+0x7a> +10002320: e8df f001 tbb [pc, r1] +10002324: 3c090940 .word 0x3c090940 +10002328: 09090909 .word 0x09090909 +1000232c: 38090909 .word 0x38090909 +10002330: 09093409 .word 0x09093409 +10002334: 30 .byte 0x30 +10002335: 00 .byte 0x00 +10002336: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000233a: 2909 cmp r1, #9 +1000233c: 9409 str r4, [sp, #36] @ 0x24 +1000233e: f240 808a bls.w 10002456 <_vsnprintf+0x19a> +10002342: 282a cmp r0, #42 @ 0x2a +10002344: f000 80f0 beq.w 10002528 <_vsnprintf+0x26c> +10002348: 2500 movs r5, #0 +1000234a: 282e cmp r0, #46 @ 0x2e +1000234c: f000 8096 beq.w 1000247c <_vsnprintf+0x1c0> +10002350: 2600 movs r6, #0 +10002352: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002356: 2912 cmp r1, #18 +10002358: d82d bhi.n 100023b6 <_vsnprintf+0xfa> +1000235a: e8df f011 tbh [pc, r1, lsl #1] +1000235e: 0149 .short 0x0149 +10002360: 0143002c .word 0x0143002c +10002364: 0138002c .word 0x0138002c +10002368: 002c002c .word 0x002c002c +1000236c: 002c002c .word 0x002c002c +10002370: 002c002c .word 0x002c002c +10002374: 0027002c .word 0x0027002c +10002378: 002c002c .word 0x002c002c +1000237c: 002c002c .word 0x002c002c +10002380: 0027002c .word 0x0027002c +10002384: 4614 mov r4, r2 +10002386: f043 0301 orr.w r3, r3, #1 +1000238a: e7c2 b.n 10002312 <_vsnprintf+0x56> +1000238c: 4614 mov r4, r2 +1000238e: f043 0302 orr.w r3, r3, #2 +10002392: e7be b.n 10002312 <_vsnprintf+0x56> +10002394: 4614 mov r4, r2 +10002396: f043 0304 orr.w r3, r3, #4 +1000239a: e7ba b.n 10002312 <_vsnprintf+0x56> +1000239c: 4614 mov r4, r2 +1000239e: f043 0310 orr.w r3, r3, #16 +100023a2: e7b6 b.n 10002312 <_vsnprintf+0x56> +100023a4: 4614 mov r4, r2 +100023a6: f043 0308 orr.w r3, r3, #8 +100023aa: e7b2 b.n 10002312 <_vsnprintf+0x56> +100023ac: 9909 ldr r1, [sp, #36] @ 0x24 +100023ae: 7848 ldrb r0, [r1, #1] +100023b0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100023b4: 3201 adds r2, #1 +100023b6: 2867 cmp r0, #103 @ 0x67 +100023b8: 9209 str r2, [sp, #36] @ 0x24 +100023ba: d87e bhi.n 100024ba <_vsnprintf+0x1fe> +100023bc: 2824 cmp r0, #36 @ 0x24 +100023be: f240 80c1 bls.w 10002544 <_vsnprintf+0x288> +100023c2: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100023c6: 2a42 cmp r2, #66 @ 0x42 +100023c8: f200 80bc bhi.w 10002544 <_vsnprintf+0x288> +100023cc: e8df f012 tbh [pc, r2, lsl #1] +100023d0: 00ba0150 .word 0x00ba0150 +100023d4: 00ba00ba .word 0x00ba00ba +100023d8: 00ba00ba .word 0x00ba00ba +100023dc: 00ba00ba .word 0x00ba00ba +100023e0: 00ba00ba .word 0x00ba00ba +100023e4: 00ba00ba .word 0x00ba00ba +100023e8: 00ba00ba .word 0x00ba00ba +100023ec: 00ba00ba .word 0x00ba00ba +100023f0: 00ba00ba .word 0x00ba00ba +100023f4: 00ba00ba .word 0x00ba00ba +100023f8: 00ba00ba .word 0x00ba00ba +100023fc: 00ba00ba .word 0x00ba00ba +10002400: 00ba00ba .word 0x00ba00ba +10002404: 00ba00ba .word 0x00ba00ba +10002408: 00ba00ba .word 0x00ba00ba +1000240c: 00ba00ba .word 0x00ba00ba +10002410: 01370119 .word 0x01370119 +10002414: 00ba0119 .word 0x00ba0119 +10002418: 00ba00ba .word 0x00ba00ba +1000241c: 00ba00ba .word 0x00ba00ba +10002420: 00ba00ba .word 0x00ba00ba +10002424: 00ba00ba .word 0x00ba00ba +10002428: 00ba00ba .word 0x00ba00ba +1000242c: 00ba00ba .word 0x00ba00ba +10002430: 00ba00ba .word 0x00ba00ba +10002434: 01bc00ba .word 0x01bc00ba +10002438: 00ba00ba .word 0x00ba00ba +1000243c: 00ba00ba .word 0x00ba00ba +10002440: 00ba00ba .word 0x00ba00ba +10002444: 00ba00ba .word 0x00ba00ba +10002448: 01bc00ba .word 0x01bc00ba +1000244c: 01bc0158 .word 0x01bc0158 +10002450: 01370119 .word 0x01370119 +10002454: 0119 .short 0x0119 +10002456: 2500 movs r5, #0 +10002458: e000 b.n 1000245c <_vsnprintf+0x1a0> +1000245a: 3201 adds r2, #1 +1000245c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002460: eb00 0545 add.w r5, r0, r5, lsl #1 +10002464: 7810 ldrb r0, [r2, #0] +10002466: 3d30 subs r5, #48 @ 0x30 +10002468: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000246c: 2909 cmp r1, #9 +1000246e: d9f4 bls.n 1000245a <_vsnprintf+0x19e> +10002470: 282e cmp r0, #46 @ 0x2e +10002472: 9209 str r2, [sp, #36] @ 0x24 +10002474: f102 0201 add.w r2, r2, #1 +10002478: f47f af6a bne.w 10002350 <_vsnprintf+0x94> +1000247c: 9909 ldr r1, [sp, #36] @ 0x24 +1000247e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002482: 7848 ldrb r0, [r1, #1] +10002484: 4611 mov r1, r2 +10002486: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000248a: 2e09 cmp r6, #9 +1000248c: f240 8121 bls.w 100026d2 <_vsnprintf+0x416> +10002490: 282a cmp r0, #42 @ 0x2a +10002492: f000 812f beq.w 100026f4 <_vsnprintf+0x438> +10002496: 9209 str r2, [sp, #36] @ 0x24 +10002498: 2600 movs r6, #0 +1000249a: 3201 adds r2, #1 +1000249c: e759 b.n 10002352 <_vsnprintf+0x96> +1000249e: 4644 mov r4, r8 +100024a0: 45c1 cmp r9, r8 +100024a2: d801 bhi.n 100024a8 <_vsnprintf+0x1ec> +100024a4: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100024a8: 464b mov r3, r9 +100024aa: 4642 mov r2, r8 +100024ac: 4651 mov r1, sl +100024ae: 2000 movs r0, #0 +100024b0: 47d8 blx fp +100024b2: 4620 mov r0, r4 +100024b4: b01b add sp, #108 @ 0x6c +100024b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100024ba: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100024be: b2d2 uxtb r2, r2 +100024c0: 2a0f cmp r2, #15 +100024c2: d83f bhi.n 10002544 <_vsnprintf+0x288> +100024c4: 2101 movs r1, #1 +100024c6: f249 0741 movw r7, #36929 @ 0x9041 +100024ca: 4091 lsls r1, r2 +100024cc: 4039 ands r1, r7 +100024ce: f040 80f3 bne.w 100026b8 <_vsnprintf+0x3fc> +100024d2: 2a0a cmp r2, #10 +100024d4: d03d beq.n 10002552 <_vsnprintf+0x296> +100024d6: 2a07 cmp r2, #7 +100024d8: d134 bne.n 10002544 <_vsnprintf+0x288> +100024da: 9d0a ldr r5, [sp, #40] @ 0x28 +100024dc: f855 2b04 ldr.w r2, [r5], #4 +100024e0: 2a00 cmp r2, #0 +100024e2: f000 8113 beq.w 1000270c <_vsnprintf+0x450> +100024e6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100024ea: ab12 add r3, sp, #72 @ 0x48 +100024ec: 461f mov r7, r3 +100024ee: 930b str r3, [sp, #44] @ 0x2c +100024f0: e003 b.n 100024fa <_vsnprintf+0x23e> +100024f2: 2920 cmp r1, #32 +100024f4: f000 8114 beq.w 10002720 <_vsnprintf+0x464> +100024f8: 461a mov r2, r3 +100024fa: f002 040f and.w r4, r2, #15 +100024fe: 4623 mov r3, r4 +10002500: 2c09 cmp r4, #9 +10002502: bf94 ite ls +10002504: 3330 addls r3, #48 @ 0x30 +10002506: 3337 addhi r3, #55 @ 0x37 +10002508: 2a0f cmp r2, #15 +1000250a: f807 3b01 strb.w r3, [r7], #1 +1000250e: f101 0101 add.w r1, r1, #1 +10002512: ea4f 1312 mov.w r3, r2, lsr #4 +10002516: d8ec bhi.n 100024f2 <_vsnprintf+0x236> +10002518: e102 b.n 10002720 <_vsnprintf+0x464> +1000251a: bf00 nop +1000251c: 100022bd .word 0x100022bd +10002520: 2000080c .word 0x2000080c +10002524: 10001601 .word 0x10001601 +10002528: 990a ldr r1, [sp, #40] @ 0x28 +1000252a: 9809 ldr r0, [sp, #36] @ 0x24 +1000252c: f851 5b04 ldr.w r5, [r1], #4 +10002530: 7840 ldrb r0, [r0, #1] +10002532: 2d00 cmp r5, #0 +10002534: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002538: bfbc itt lt +1000253a: f043 0302 orrlt.w r3, r3, #2 +1000253e: 426d neglt r5, r5 +10002540: 3201 adds r2, #1 +10002542: e702 b.n 1000234a <_vsnprintf+0x8e> +10002544: 4642 mov r2, r8 +10002546: 464b mov r3, r9 +10002548: 4651 mov r1, sl +1000254a: f108 0801 add.w r8, r8, #1 +1000254e: 47d8 blx fp +10002550: e6d2 b.n 100022f8 <_vsnprintf+0x3c> +10002552: 990a ldr r1, [sp, #40] @ 0x28 +10002554: 2e00 cmp r6, #0 +10002556: f851 7b04 ldr.w r7, [r1], #4 +1000255a: bf18 it ne +1000255c: 4632 movne r2, r6 +1000255e: 7838 ldrb r0, [r7, #0] +10002560: bf08 it eq +10002562: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002566: 2800 cmp r0, #0 +10002568: f000 837b beq.w 10002c62 <_vsnprintf+0x9a6> +1000256c: 18bc adds r4, r7, r2 +1000256e: 46a4 mov ip, r4 +10002570: 463a mov r2, r7 +10002572: e004 b.n 1000257e <_vsnprintf+0x2c2> +10002574: f812 4f01 ldrb.w r4, [r2, #1]! +10002578: 2c00 cmp r4, #0 +1000257a: f000 813f beq.w 100027fc <_vsnprintf+0x540> +1000257e: 4594 cmp ip, r2 +10002580: d1f8 bne.n 10002574 <_vsnprintf+0x2b8> +10002582: 4664 mov r4, ip +10002584: 1be4 subs r4, r4, r7 +10002586: 055a lsls r2, r3, #21 +10002588: f140 8122 bpl.w 100027d0 <_vsnprintf+0x514> +1000258c: 42b4 cmp r4, r6 +1000258e: bf28 it cs +10002590: 4634 movcs r4, r6 +10002592: f013 0302 ands.w r3, r3, #2 +10002596: f000 8288 beq.w 10002aaa <_vsnprintf+0x7ee> +1000259a: 2302 movs r3, #2 +1000259c: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100025a0: 4642 mov r2, r8 +100025a2: 461d mov r5, r3 +100025a4: 4446 add r6, r8 +100025a6: e008 b.n 100025ba <_vsnprintf+0x2fe> +100025a8: 464b mov r3, r9 +100025aa: 4651 mov r1, sl +100025ac: 47d8 blx fp +100025ae: f817 0f01 ldrb.w r0, [r7, #1]! +100025b2: f108 0801 add.w r8, r8, #1 +100025b6: b110 cbz r0, 100025be <_vsnprintf+0x302> +100025b8: 4642 mov r2, r8 +100025ba: 4546 cmp r6, r8 +100025bc: d1f4 bne.n 100025a8 <_vsnprintf+0x2ec> +100025be: 462b mov r3, r5 +100025c0: 990b ldr r1, [sp, #44] @ 0x2c +100025c2: 9d0a ldr r5, [sp, #40] @ 0x28 +100025c4: 2b00 cmp r3, #0 +100025c6: f040 8141 bne.w 1000284c <_vsnprintf+0x590> +100025ca: 910a str r1, [sp, #40] @ 0x28 +100025cc: e694 b.n 100022f8 <_vsnprintf+0x3c> +100025ce: 9909 ldr r1, [sp, #36] @ 0x24 +100025d0: 7848 ldrb r0, [r1, #1] +100025d2: 286c cmp r0, #108 @ 0x6c +100025d4: f47f aeec bne.w 100023b0 <_vsnprintf+0xf4> +100025d8: 460a mov r2, r1 +100025da: 7888 ldrb r0, [r1, #2] +100025dc: f443 7340 orr.w r3, r3, #768 @ 0x300 +100025e0: 3203 adds r2, #3 +100025e2: e6e8 b.n 100023b6 <_vsnprintf+0xfa> +100025e4: 9909 ldr r1, [sp, #36] @ 0x24 +100025e6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100025ea: 7848 ldrb r0, [r1, #1] +100025ec: 3201 adds r2, #1 +100025ee: e6e2 b.n 100023b6 <_vsnprintf+0xfa> +100025f0: 9909 ldr r1, [sp, #36] @ 0x24 +100025f2: 7848 ldrb r0, [r1, #1] +100025f4: 2868 cmp r0, #104 @ 0x68 +100025f6: f000 8103 beq.w 10002800 <_vsnprintf+0x544> +100025fa: f043 0380 orr.w r3, r3, #128 @ 0x80 +100025fe: 3201 adds r2, #1 +10002600: e6d9 b.n 100023b6 <_vsnprintf+0xfa> +10002602: 2867 cmp r0, #103 @ 0x67 +10002604: f000 80d9 beq.w 100027ba <_vsnprintf+0x4fe> +10002608: 2847 cmp r0, #71 @ 0x47 +1000260a: f000 80dc beq.w 100027c6 <_vsnprintf+0x50a> +1000260e: 2845 cmp r0, #69 @ 0x45 +10002610: f000 80db beq.w 100027ca <_vsnprintf+0x50e> +10002614: e9cd 5303 strd r5, r3, [sp, #12] +10002618: 9b0a ldr r3, [sp, #40] @ 0x28 +1000261a: 9602 str r6, [sp, #8] +1000261c: 3307 adds r3, #7 +1000261e: f023 0307 bic.w r3, r3, #7 +10002622: 461c mov r4, r3 +10002624: 4642 mov r2, r8 +10002626: e8f4 6702 ldrd r6, r7, [r4], #8 +1000262a: 464b mov r3, r9 +1000262c: 4651 mov r1, sl +1000262e: 4658 mov r0, fp +10002630: e9cd 6700 strd r6, r7, [sp] +10002634: 940a str r4, [sp, #40] @ 0x28 +10002636: f7ff fb87 bl 10001d48 <_etoa> +1000263a: 4680 mov r8, r0 +1000263c: e65c b.n 100022f8 <_vsnprintf+0x3c> +1000263e: 2846 cmp r0, #70 @ 0x46 +10002640: bf08 it eq +10002642: f043 0320 orreq.w r3, r3, #32 +10002646: e9cd 5303 strd r5, r3, [sp, #12] +1000264a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000264c: 9602 str r6, [sp, #8] +1000264e: 3307 adds r3, #7 +10002650: f023 0307 bic.w r3, r3, #7 +10002654: 461c mov r4, r3 +10002656: 4642 mov r2, r8 +10002658: e8f4 6702 ldrd r6, r7, [r4], #8 +1000265c: 464b mov r3, r9 +1000265e: 4651 mov r1, sl +10002660: 4658 mov r0, fp +10002662: e9cd 6700 strd r6, r7, [sp] +10002666: 940a str r4, [sp, #40] @ 0x28 +10002668: f7ff f90e bl 10001888 <_ftoa> +1000266c: 4680 mov r8, r0 +1000266e: e643 b.n 100022f8 <_vsnprintf+0x3c> +10002670: 4642 mov r2, r8 +10002672: 464b mov r3, r9 +10002674: 4651 mov r1, sl +10002676: 2025 movs r0, #37 @ 0x25 +10002678: f108 0801 add.w r8, r8, #1 +1000267c: 47d8 blx fp +1000267e: e63b b.n 100022f8 <_vsnprintf+0x3c> +10002680: 9a0a ldr r2, [sp, #40] @ 0x28 +10002682: 0799 lsls r1, r3, #30 +10002684: f102 0404 add.w r4, r2, #4 +10002688: f108 0601 add.w r6, r8, #1 +1000268c: f140 80c6 bpl.w 1000281c <_vsnprintf+0x560> +10002690: 7810 ldrb r0, [r2, #0] +10002692: 464b mov r3, r9 +10002694: 4642 mov r2, r8 +10002696: 4651 mov r1, sl +10002698: 47d8 blx fp +1000269a: 2d01 cmp r5, #1 +1000269c: bf88 it hi +1000269e: 44a8 addhi r8, r5 +100026a0: f240 81bd bls.w 10002a1e <_vsnprintf+0x762> +100026a4: 4632 mov r2, r6 +100026a6: 464b mov r3, r9 +100026a8: 4651 mov r1, sl +100026aa: 2020 movs r0, #32 +100026ac: 3601 adds r6, #1 +100026ae: 47d8 blx fp +100026b0: 4546 cmp r6, r8 +100026b2: d1f7 bne.n 100026a4 <_vsnprintf+0x3e8> +100026b4: 940a str r4, [sp, #40] @ 0x28 +100026b6: e61f b.n 100022f8 <_vsnprintf+0x3c> +100026b8: 286f cmp r0, #111 @ 0x6f +100026ba: f000 8081 beq.w 100027c0 <_vsnprintf+0x504> +100026be: f240 8248 bls.w 10002b52 <_vsnprintf+0x896> +100026c2: 2878 cmp r0, #120 @ 0x78 +100026c4: f000 8190 beq.w 100029e8 <_vsnprintf+0x72c> +100026c8: 270a movs r7, #10 +100026ca: f023 0310 bic.w r3, r3, #16 +100026ce: 46bc mov ip, r7 +100026d0: e041 b.n 10002756 <_vsnprintf+0x49a> +100026d2: 2600 movs r6, #0 +100026d4: eb06 0686 add.w r6, r6, r6, lsl #2 +100026d8: eb00 0046 add.w r0, r0, r6, lsl #1 +100026dc: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100026e0: f811 0f01 ldrb.w r0, [r1, #1]! +100026e4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100026e8: 2a09 cmp r2, #9 +100026ea: d9f3 bls.n 100026d4 <_vsnprintf+0x418> +100026ec: 460a mov r2, r1 +100026ee: 9109 str r1, [sp, #36] @ 0x24 +100026f0: 3201 adds r2, #1 +100026f2: e62e b.n 10002352 <_vsnprintf+0x96> +100026f4: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +100026f8: f851 6b04 ldr.w r6, [r1], #4 +100026fc: 7890 ldrb r0, [r2, #2] +100026fe: 3202 adds r2, #2 +10002700: 9209 str r2, [sp, #36] @ 0x24 +10002702: 910a str r1, [sp, #40] @ 0x28 +10002704: 3201 adds r2, #1 +10002706: ea26 76e6 bic.w r6, r6, r6, asr #31 +1000270a: e622 b.n 10002352 <_vsnprintf+0x96> +1000270c: f023 0010 bic.w r0, r3, #16 +10002710: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002714: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002718: f43f aee7 beq.w 100024ea <_vsnprintf+0x22e> +1000271c: ab12 add r3, sp, #72 @ 0x48 +1000271e: 930b str r3, [sp, #44] @ 0x2c +10002720: 9b0b ldr r3, [sp, #44] @ 0x2c +10002722: 9006 str r0, [sp, #24] +10002724: 9300 str r3, [sp, #0] +10002726: 2308 movs r3, #8 +10002728: 2010 movs r0, #16 +1000272a: 9305 str r3, [sp, #20] +1000272c: 2300 movs r3, #0 +1000272e: 4642 mov r2, r8 +10002730: e9cd 3002 strd r3, r0, [sp, #8] +10002734: 9101 str r1, [sp, #4] +10002736: 464b mov r3, r9 +10002738: 4651 mov r1, sl +1000273a: 4658 mov r0, fp +1000273c: 9604 str r6, [sp, #16] +1000273e: f7fe ffaf bl 100016a0 <_ntoa_format> +10002742: 950a str r5, [sp, #40] @ 0x28 +10002744: 4680 mov r8, r0 +10002746: e5d7 b.n 100022f8 <_vsnprintf+0x3c> +10002748: 2858 cmp r0, #88 @ 0x58 +1000274a: d062 beq.n 10002812 <_vsnprintf+0x556> +1000274c: 2862 cmp r0, #98 @ 0x62 +1000274e: f040 808f bne.w 10002870 <_vsnprintf+0x5b4> +10002752: 2702 movs r7, #2 +10002754: 46bc mov ip, r7 +10002756: f413 6080 ands.w r0, r3, #1024 @ 0x400 +1000275a: f000 80dd beq.w 10002918 <_vsnprintf+0x65c> +1000275e: f023 030d bic.w r3, r3, #13 +10002762: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002766: f040 8181 bne.w 10002a6c <_vsnprintf+0x7b0> +1000276a: 990a ldr r1, [sp, #40] @ 0x28 +1000276c: 1d0f adds r7, r1, #4 +1000276e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002772: f040 8237 bne.w 10002be4 <_vsnprintf+0x928> +10002776: 065c lsls r4, r3, #25 +10002778: 9a0a ldr r2, [sp, #40] @ 0x28 +1000277a: f140 813b bpl.w 100029f4 <_vsnprintf+0x738> +1000277e: 7812 ldrb r2, [r2, #0] +10002780: 2a00 cmp r2, #0 +10002782: f040 814e bne.w 10002a22 <_vsnprintf+0x766> +10002786: f023 0310 bic.w r3, r3, #16 +1000278a: 2800 cmp r0, #0 +1000278c: f000 8149 beq.w 10002a22 <_vsnprintf+0x766> +10002790: 4611 mov r1, r2 +10002792: aa12 add r2, sp, #72 @ 0x48 +10002794: 920b str r2, [sp, #44] @ 0x2c +10002796: e9cd 5305 strd r5, r3, [sp, #20] +1000279a: e9cd c603 strd ip, r6, [sp, #12] +1000279e: 9101 str r1, [sp, #4] +100027a0: 9b0b ldr r3, [sp, #44] @ 0x2c +100027a2: 4642 mov r2, r8 +100027a4: 9300 str r3, [sp, #0] +100027a6: 2300 movs r3, #0 +100027a8: 4651 mov r1, sl +100027aa: 9302 str r3, [sp, #8] +100027ac: 4658 mov r0, fp +100027ae: 464b mov r3, r9 +100027b0: f7fe ff76 bl 100016a0 <_ntoa_format> +100027b4: 970a str r7, [sp, #40] @ 0x28 +100027b6: 4680 mov r8, r0 +100027b8: e59e b.n 100022f8 <_vsnprintf+0x3c> +100027ba: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027be: e729 b.n 10002614 <_vsnprintf+0x358> +100027c0: 2708 movs r7, #8 +100027c2: 46bc mov ip, r7 +100027c4: e7c7 b.n 10002756 <_vsnprintf+0x49a> +100027c6: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027ca: f043 0320 orr.w r3, r3, #32 +100027ce: e721 b.n 10002614 <_vsnprintf+0x358> +100027d0: f013 0302 ands.w r3, r3, #2 +100027d4: f000 818e beq.w 10002af4 <_vsnprintf+0x838> +100027d8: 2302 movs r3, #2 +100027da: 950a str r5, [sp, #40] @ 0x28 +100027dc: 461e mov r6, r3 +100027de: 460d mov r5, r1 +100027e0: 4642 mov r2, r8 +100027e2: 464b mov r3, r9 +100027e4: 4651 mov r1, sl +100027e6: 47d8 blx fp +100027e8: f817 0f01 ldrb.w r0, [r7, #1]! +100027ec: f108 0801 add.w r8, r8, #1 +100027f0: 2800 cmp r0, #0 +100027f2: d1f5 bne.n 100027e0 <_vsnprintf+0x524> +100027f4: 4629 mov r1, r5 +100027f6: 4633 mov r3, r6 +100027f8: 9d0a ldr r5, [sp, #40] @ 0x28 +100027fa: e6e3 b.n 100025c4 <_vsnprintf+0x308> +100027fc: 1bd4 subs r4, r2, r7 +100027fe: e6c2 b.n 10002586 <_vsnprintf+0x2ca> +10002800: 460a mov r2, r1 +10002802: 7888 ldrb r0, [r1, #2] +10002804: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002808: 3203 adds r2, #3 +1000280a: e5d4 b.n 100023b6 <_vsnprintf+0xfa> +1000280c: 4604 mov r4, r0 +1000280e: 4680 mov r8, r0 +10002810: e646 b.n 100024a0 <_vsnprintf+0x1e4> +10002812: 2710 movs r7, #16 +10002814: f043 0320 orr.w r3, r3, #32 +10002818: 46bc mov ip, r7 +1000281a: e79c b.n 10002756 <_vsnprintf+0x49a> +1000281c: 2d01 cmp r5, #1 +1000281e: f240 80f8 bls.w 10002a12 <_vsnprintf+0x756> +10002822: 4646 mov r6, r8 +10002824: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002828: 442f add r7, r5 +1000282a: 4632 mov r2, r6 +1000282c: 464b mov r3, r9 +1000282e: 4651 mov r1, sl +10002830: 2020 movs r0, #32 +10002832: 3601 adds r6, #1 +10002834: 47d8 blx fp +10002836: 42be cmp r6, r7 +10002838: d1f7 bne.n 1000282a <_vsnprintf+0x56e> +1000283a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000283c: 4632 mov r2, r6 +1000283e: 7818 ldrb r0, [r3, #0] +10002840: 4651 mov r1, sl +10002842: 464b mov r3, r9 +10002844: 47d8 blx fp +10002846: 44a8 add r8, r5 +10002848: 940a str r4, [sp, #40] @ 0x28 +1000284a: e555 b.n 100022f8 <_vsnprintf+0x3c> +1000284c: 4646 mov r6, r8 +1000284e: 42a5 cmp r5, r4 +10002850: f67f aebb bls.w 100025ca <_vsnprintf+0x30e> +10002854: 44a8 add r8, r5 +10002856: eba8 0804 sub.w r8, r8, r4 +1000285a: 460c mov r4, r1 +1000285c: 4632 mov r2, r6 +1000285e: 464b mov r3, r9 +10002860: 4651 mov r1, sl +10002862: 2020 movs r0, #32 +10002864: 3601 adds r6, #1 +10002866: 47d8 blx fp +10002868: 4546 cmp r6, r8 +1000286a: d1f7 bne.n 1000285c <_vsnprintf+0x5a0> +1000286c: 4621 mov r1, r4 +1000286e: e6ac b.n 100025ca <_vsnprintf+0x30e> +10002870: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002874: f000 80bb beq.w 100029ee <_vsnprintf+0x732> +10002878: f44f 6280 mov.w r2, #1024 @ 0x400 +1000287c: f023 0c11 bic.w ip, r3, #17 +10002880: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002884: 9b0a ldr r3, [sp, #40] @ 0x28 +10002886: d14a bne.n 1000291e <_vsnprintf+0x662> +10002888: f41c 7080 ands.w r0, ip, #256 @ 0x100 +1000288c: f103 0404 add.w r4, r3, #4 +10002890: f040 8134 bne.w 10002afc <_vsnprintf+0x840> +10002894: f01c 0f40 tst.w ip, #64 @ 0x40 +10002898: f040 80a3 bne.w 100029e2 <_vsnprintf+0x726> +1000289c: f01c 0f80 tst.w ip, #128 @ 0x80 +100028a0: f000 81d3 beq.w 10002c4a <_vsnprintf+0x98e> +100028a4: f9b3 1000 ldrsh.w r1, [r3] +100028a8: ea81 77e1 eor.w r7, r1, r1, asr #31 +100028ac: eba7 77e1 sub.w r7, r7, r1, asr #31 +100028b0: b2bf uxth r7, r7 +100028b2: 0fcb lsrs r3, r1, #31 +100028b4: 2900 cmp r1, #0 +100028b6: f000 8156 beq.w 10002b66 <_vsnprintf+0x8aa> +100028ba: 463a mov r2, r7 +100028bc: a912 add r1, sp, #72 @ 0x48 +100028be: 460f mov r7, r1 +100028c0: f8df e3d8 ldr.w lr, [pc, #984] @ 10002c9c <_vsnprintf+0x9e0> +100028c4: 910b str r1, [sp, #44] @ 0x2c +100028c6: 930a str r3, [sp, #40] @ 0x28 +100028c8: 950c str r5, [sp, #48] @ 0x30 +100028ca: e001 b.n 100028d0 <_vsnprintf+0x614> +100028cc: 2820 cmp r0, #32 +100028ce: d00f beq.n 100028f0 <_vsnprintf+0x634> +100028d0: 4615 mov r5, r2 +100028d2: fbae 1302 umull r1, r3, lr, r2 +100028d6: 08db lsrs r3, r3, #3 +100028d8: eb03 0183 add.w r1, r3, r3, lsl #2 +100028dc: eba2 0141 sub.w r1, r2, r1, lsl #1 +100028e0: 3130 adds r1, #48 @ 0x30 +100028e2: 2d09 cmp r5, #9 +100028e4: 461a mov r2, r3 +100028e6: f100 0001 add.w r0, r0, #1 +100028ea: f807 1b01 strb.w r1, [r7], #1 +100028ee: d8ed bhi.n 100028cc <_vsnprintf+0x610> +100028f0: 9b0a ldr r3, [sp, #40] @ 0x28 +100028f2: 9d0c ldr r5, [sp, #48] @ 0x30 +100028f4: e9cd 5c05 strd r5, ip, [sp, #20] +100028f8: e9cd 0301 strd r0, r3, [sp, #4] +100028fc: 9604 str r6, [sp, #16] +100028fe: 9b0b ldr r3, [sp, #44] @ 0x2c +10002900: 4642 mov r2, r8 +10002902: 9300 str r3, [sp, #0] +10002904: 230a movs r3, #10 +10002906: 4651 mov r1, sl +10002908: 9303 str r3, [sp, #12] +1000290a: 4658 mov r0, fp +1000290c: 464b mov r3, r9 +1000290e: f7fe fec7 bl 100016a0 <_ntoa_format> +10002912: 940a str r4, [sp, #40] @ 0x28 +10002914: 4680 mov r8, r0 +10002916: e4ef b.n 100022f8 <_vsnprintf+0x3c> +10002918: f023 030c bic.w r3, r3, #12 +1000291c: e721 b.n 10002762 <_vsnprintf+0x4a6> +1000291e: 3307 adds r3, #7 +10002920: f023 0307 bic.w r3, r3, #7 +10002924: 4619 mov r1, r3 +10002926: 4608 mov r0, r1 +10002928: 685b ldr r3, [r3, #4] +1000292a: f850 1b08 ldr.w r1, [r0], #8 +1000292e: 0fdf lsrs r7, r3, #31 +10002930: 900a str r0, [sp, #40] @ 0x28 +10002932: ea51 0003 orrs.w r0, r1, r3 +10002936: d162 bne.n 100029fe <_vsnprintf+0x742> +10002938: 2a00 cmp r2, #0 +1000293a: f040 819f bne.w 10002c7c <_vsnprintf+0x9c0> +1000293e: 4613 mov r3, r2 +10002940: 4611 mov r1, r2 +10002942: aa12 add r2, sp, #72 @ 0x48 +10002944: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002948: 2000 movs r0, #0 +1000294a: 4615 mov r5, r2 +1000294c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002950: f8df e348 ldr.w lr, [pc, #840] @ 10002c9c <_vsnprintf+0x9e0> +10002954: 920b str r2, [sp, #44] @ 0x2c +10002956: e001 b.n 1000295c <_vsnprintf+0x6a0> +10002958: 2820 cmp r0, #32 +1000295a: d02d beq.n 100029b8 <_vsnprintf+0x6fc> +1000295c: 185a adds r2, r3, r1 +1000295e: f142 0200 adc.w r2, r2, #0 +10002962: fbae 7802 umull r7, r8, lr, r2 +10002966: f028 0703 bic.w r7, r8, #3 +1000296a: eb07 0798 add.w r7, r7, r8, lsr #2 +1000296e: 1bd2 subs r2, r2, r7 +10002970: 461e mov r6, r3 +10002972: 1a9b subs r3, r3, r2 +10002974: f161 0700 sbc.w r7, r1, #0 +10002978: 460c mov r4, r1 +1000297a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +1000297e: fb01 f103 mul.w r1, r1, r3 +10002982: fb0e 1107 mla r1, lr, r7, r1 +10002986: fba3 730e umull r7, r3, r3, lr +1000298a: 4419 add r1, r3 +1000298c: 2305 movs r3, #5 +1000298e: f007 0801 and.w r8, r7, #1 +10002992: fba8 3803 umull r3, r8, r8, r3 +10002996: 189b adds r3, r3, r2 +10002998: 2e0a cmp r6, #10 +1000299a: f103 0330 add.w r3, r3, #48 @ 0x30 +1000299e: ea4f 0757 mov.w r7, r7, lsr #1 +100029a2: f174 0400 sbcs.w r4, r4, #0 +100029a6: f805 3b01 strb.w r3, [r5], #1 +100029aa: f100 0001 add.w r0, r0, #1 +100029ae: ea47 73c1 orr.w r3, r7, r1, lsl #31 +100029b2: ea4f 0151 mov.w r1, r1, lsr #1 +100029b6: d2cf bcs.n 10002958 <_vsnprintf+0x69c> +100029b8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +100029bc: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +100029c0: 9b0b ldr r3, [sp, #44] @ 0x2c +100029c2: 4642 mov r2, r8 +100029c4: 9300 str r3, [sp, #0] +100029c6: 230a movs r3, #10 +100029c8: e9cd 5c05 strd r5, ip, [sp, #20] +100029cc: e9cd 0701 strd r0, r7, [sp, #4] +100029d0: 9604 str r6, [sp, #16] +100029d2: 9303 str r3, [sp, #12] +100029d4: 464b mov r3, r9 +100029d6: 4651 mov r1, sl +100029d8: 4658 mov r0, fp +100029da: f7fe fe61 bl 100016a0 <_ntoa_format> +100029de: 4680 mov r8, r0 +100029e0: e48a b.n 100022f8 <_vsnprintf+0x3c> +100029e2: 7819 ldrb r1, [r3, #0] +100029e4: 460f mov r7, r1 +100029e6: e764 b.n 100028b2 <_vsnprintf+0x5f6> +100029e8: 2710 movs r7, #16 +100029ea: 46bc mov ip, r7 +100029ec: e6b3 b.n 10002756 <_vsnprintf+0x49a> +100029ee: f023 0c10 bic.w ip, r3, #16 +100029f2: e745 b.n 10002880 <_vsnprintf+0x5c4> +100029f4: 061c lsls r4, r3, #24 +100029f6: bf4c ite mi +100029f8: 8812 ldrhmi r2, [r2, #0] +100029fa: 6812 ldrpl r2, [r2, #0] +100029fc: e6c0 b.n 10002780 <_vsnprintf+0x4c4> +100029fe: 460a mov r2, r1 +10002a00: 1e19 subs r1, r3, #0 +10002a02: db01 blt.n 10002a08 <_vsnprintf+0x74c> +10002a04: 4613 mov r3, r2 +10002a06: e79c b.n 10002942 <_vsnprintf+0x686> +10002a08: 4252 negs r2, r2 +10002a0a: 4613 mov r3, r2 +10002a0c: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002a10: e797 b.n 10002942 <_vsnprintf+0x686> +10002a12: 4613 mov r3, r2 +10002a14: 4651 mov r1, sl +10002a16: 7818 ldrb r0, [r3, #0] +10002a18: 4642 mov r2, r8 +10002a1a: 464b mov r3, r9 +10002a1c: 47d8 blx fp +10002a1e: 46b0 mov r8, r6 +10002a20: e648 b.n 100026b4 <_vsnprintf+0x3f8> +10002a22: f013 0f20 tst.w r3, #32 +10002a26: bf14 ite ne +10002a28: 2041 movne r0, #65 @ 0x41 +10002a2a: 2061 moveq r0, #97 @ 0x61 +10002a2c: ac12 add r4, sp, #72 @ 0x48 +10002a2e: 46a6 mov lr, r4 +10002a30: 940b str r4, [sp, #44] @ 0x2c +10002a32: 930a str r3, [sp, #40] @ 0x28 +10002a34: f1a0 040a sub.w r4, r0, #10 +10002a38: 950c str r5, [sp, #48] @ 0x30 +10002a3a: e002 b.n 10002a42 <_vsnprintf+0x786> +10002a3c: 2920 cmp r1, #32 +10002a3e: d012 beq.n 10002a66 <_vsnprintf+0x7aa> +10002a40: 462a mov r2, r5 +10002a42: fbb2 f5fc udiv r5, r2, ip +10002a46: fb0c 2015 mls r0, ip, r5, r2 +10002a4a: b2c3 uxtb r3, r0 +10002a4c: 2809 cmp r0, #9 +10002a4e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002a52: bf8a itet hi +10002a54: 191b addhi r3, r3, r4 +10002a56: b2c3 uxtbls r3, r0 +10002a58: b2db uxtbhi r3, r3 +10002a5a: 4562 cmp r2, ip +10002a5c: f80e 3b01 strb.w r3, [lr], #1 +10002a60: f101 0101 add.w r1, r1, #1 +10002a64: d2ea bcs.n 10002a3c <_vsnprintf+0x780> +10002a66: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a68: 9d0c ldr r5, [sp, #48] @ 0x30 +10002a6a: e694 b.n 10002796 <_vsnprintf+0x4da> +10002a6c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a6e: 3207 adds r2, #7 +10002a70: f022 0207 bic.w r2, r2, #7 +10002a74: 6851 ldr r1, [r2, #4] +10002a76: f852 4b08 ldr.w r4, [r2], #8 +10002a7a: 468e mov lr, r1 +10002a7c: 920a str r2, [sp, #40] @ 0x28 +10002a7e: ea54 0201 orrs.w r2, r4, r1 +10002a82: d176 bne.n 10002b72 <_vsnprintf+0x8b6> +10002a84: f023 0310 bic.w r3, r3, #16 +10002a88: 2800 cmp r0, #0 +10002a8a: d072 beq.n 10002b72 <_vsnprintf+0x8b6> +10002a8c: 2200 movs r2, #0 +10002a8e: 4611 mov r1, r2 +10002a90: aa12 add r2, sp, #72 @ 0x48 +10002a92: 920b str r2, [sp, #44] @ 0x2c +10002a94: e9cd 5305 strd r5, r3, [sp, #20] +10002a98: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a9a: 4642 mov r2, r8 +10002a9c: 9300 str r3, [sp, #0] +10002a9e: 2300 movs r3, #0 +10002aa0: e9cd c603 strd ip, r6, [sp, #12] +10002aa4: 9101 str r1, [sp, #4] +10002aa6: 9302 str r3, [sp, #8] +10002aa8: e794 b.n 100029d4 <_vsnprintf+0x718> +10002aaa: 42a5 cmp r5, r4 +10002aac: bf98 it ls +10002aae: 3401 addls r4, #1 +10002ab0: f67f ad74 bls.w 1000259c <_vsnprintf+0x2e0> +10002ab4: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ab8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002abc: eb05 0208 add.w r2, r5, r8 +10002ac0: 461f mov r7, r3 +10002ac2: 460d mov r5, r1 +10002ac4: 1b14 subs r4, r2, r4 +10002ac6: 4642 mov r2, r8 +10002ac8: 464b mov r3, r9 +10002aca: 4651 mov r1, sl +10002acc: 2020 movs r0, #32 +10002ace: f108 0801 add.w r8, r8, #1 +10002ad2: 47d8 blx fp +10002ad4: 45a0 cmp r8, r4 +10002ad6: d1f6 bne.n 10002ac6 <_vsnprintf+0x80a> +10002ad8: 463b mov r3, r7 +10002ada: 9f0a ldr r7, [sp, #40] @ 0x28 +10002adc: 4629 mov r1, r5 +10002ade: 7838 ldrb r0, [r7, #0] +10002ae0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002ae2: 1c6c adds r4, r5, #1 +10002ae4: 2800 cmp r0, #0 +10002ae6: f43f ad70 beq.w 100025ca <_vsnprintf+0x30e> +10002aea: 2b00 cmp r3, #0 +10002aec: f43f ae75 beq.w 100027da <_vsnprintf+0x51e> +10002af0: 2300 movs r3, #0 +10002af2: e553 b.n 1000259c <_vsnprintf+0x2e0> +10002af4: 42a5 cmp r5, r4 +10002af6: d8df bhi.n 10002ab8 <_vsnprintf+0x7fc> +10002af8: 3401 adds r4, #1 +10002afa: e66e b.n 100027da <_vsnprintf+0x51e> +10002afc: 6819 ldr r1, [r3, #0] +10002afe: 0fcb lsrs r3, r1, #31 +10002b00: 2900 cmp r1, #0 +10002b02: f000 80a8 beq.w 10002c56 <_vsnprintf+0x99a> +10002b06: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002b0a: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002b0e: a912 add r1, sp, #72 @ 0x48 +10002b10: 4608 mov r0, r1 +10002b12: f8df e188 ldr.w lr, [pc, #392] @ 10002c9c <_vsnprintf+0x9e0> +10002b16: 910b str r1, [sp, #44] @ 0x2c +10002b18: 930a str r3, [sp, #40] @ 0x28 +10002b1a: 950c str r5, [sp, #48] @ 0x30 +10002b1c: e001 b.n 10002b22 <_vsnprintf+0x866> +10002b1e: 2f20 cmp r7, #32 +10002b20: d00f beq.n 10002b42 <_vsnprintf+0x886> +10002b22: 4615 mov r5, r2 +10002b24: fbae 1302 umull r1, r3, lr, r2 +10002b28: 08db lsrs r3, r3, #3 +10002b2a: eb03 0183 add.w r1, r3, r3, lsl #2 +10002b2e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002b32: 3130 adds r1, #48 @ 0x30 +10002b34: 2d09 cmp r5, #9 +10002b36: 461a mov r2, r3 +10002b38: f107 0701 add.w r7, r7, #1 +10002b3c: f800 1b01 strb.w r1, [r0], #1 +10002b40: d8ed bhi.n 10002b1e <_vsnprintf+0x862> +10002b42: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b44: 9d0c ldr r5, [sp, #48] @ 0x30 +10002b46: e9cd 5c05 strd r5, ip, [sp, #20] +10002b4a: e9cd 7301 strd r7, r3, [sp, #4] +10002b4e: 9604 str r6, [sp, #16] +10002b50: e6d5 b.n 100028fe <_vsnprintf+0x642> +10002b52: 2869 cmp r0, #105 @ 0x69 +10002b54: f023 0c10 bic.w ip, r3, #16 +10002b58: f040 808c bne.w 10002c74 <_vsnprintf+0x9b8> +10002b5c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b60: f43f ae8e beq.w 10002880 <_vsnprintf+0x5c4> +10002b64: e688 b.n 10002878 <_vsnprintf+0x5bc> +10002b66: 2a00 cmp r2, #0 +10002b68: f43f aea8 beq.w 100028bc <_vsnprintf+0x600> +10002b6c: aa12 add r2, sp, #72 @ 0x48 +10002b6e: 920b str r2, [sp, #44] @ 0x2c +10002b70: e6c0 b.n 100028f4 <_vsnprintf+0x638> +10002b72: f013 0f20 tst.w r3, #32 +10002b76: bf14 ite ne +10002b78: 2241 movne r2, #65 @ 0x41 +10002b7a: 2261 moveq r2, #97 @ 0x61 +10002b7c: 2000 movs r0, #0 +10002b7e: a912 add r1, sp, #72 @ 0x48 +10002b80: 3a0a subs r2, #10 +10002b82: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002b86: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002b8a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002b8e: 4606 mov r6, r0 +10002b90: 4688 mov r8, r1 +10002b92: 4675 mov r5, lr +10002b94: 4693 mov fp, r2 +10002b96: 910b str r1, [sp, #44] @ 0x2c +10002b98: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002b9c: e003 b.n 10002ba6 <_vsnprintf+0x8ea> +10002b9e: 2e20 cmp r6, #32 +10002ba0: d017 beq.n 10002bd2 <_vsnprintf+0x916> +10002ba2: 4604 mov r4, r0 +10002ba4: 460d mov r5, r1 +10002ba6: 4629 mov r1, r5 +10002ba8: 463a mov r2, r7 +10002baa: 2300 movs r3, #0 +10002bac: 4620 mov r0, r4 +10002bae: f000 fc47 bl 10003440 <____aeabi_uldivmod_veneer> +10002bb2: b2d2 uxtb r2, r2 +10002bb4: 2a09 cmp r2, #9 +10002bb6: f102 0330 add.w r3, r2, #48 @ 0x30 +10002bba: bf88 it hi +10002bbc: eb02 030b addhi.w r3, r2, fp +10002bc0: 42bc cmp r4, r7 +10002bc2: b2db uxtb r3, r3 +10002bc4: f175 0500 sbcs.w r5, r5, #0 +10002bc8: f808 3b01 strb.w r3, [r8], #1 +10002bcc: f106 0601 add.w r6, r6, #1 +10002bd0: d2e5 bcs.n 10002b9e <_vsnprintf+0x8e2> +10002bd2: 4631 mov r1, r6 +10002bd4: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002bd8: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002bdc: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002be0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002be2: e757 b.n 10002a94 <_vsnprintf+0x7d8> +10002be4: 990a ldr r1, [sp, #40] @ 0x28 +10002be6: 6809 ldr r1, [r1, #0] +10002be8: b951 cbnz r1, 10002c00 <_vsnprintf+0x944> +10002bea: f023 0310 bic.w r3, r3, #16 +10002bee: b138 cbz r0, 10002c00 <_vsnprintf+0x944> +10002bf0: a912 add r1, sp, #72 @ 0x48 +10002bf2: 910b str r1, [sp, #44] @ 0x2c +10002bf4: e9cd 5305 strd r5, r3, [sp, #20] +10002bf8: e9cd c603 strd ip, r6, [sp, #12] +10002bfc: 9201 str r2, [sp, #4] +10002bfe: e5cf b.n 100027a0 <_vsnprintf+0x4e4> +10002c00: f013 0f20 tst.w r3, #32 +10002c04: bf14 ite ne +10002c06: 2041 movne r0, #65 @ 0x41 +10002c08: 2061 moveq r0, #97 @ 0x61 +10002c0a: ac12 add r4, sp, #72 @ 0x48 +10002c0c: 46a6 mov lr, r4 +10002c0e: 940b str r4, [sp, #44] @ 0x2c +10002c10: 930a str r3, [sp, #40] @ 0x28 +10002c12: f1a0 040a sub.w r4, r0, #10 +10002c16: 950c str r5, [sp, #48] @ 0x30 +10002c18: e002 b.n 10002c20 <_vsnprintf+0x964> +10002c1a: 2a20 cmp r2, #32 +10002c1c: d012 beq.n 10002c44 <_vsnprintf+0x988> +10002c1e: 4629 mov r1, r5 +10002c20: fbb1 f5fc udiv r5, r1, ip +10002c24: fb0c 1015 mls r0, ip, r5, r1 +10002c28: b2c3 uxtb r3, r0 +10002c2a: 2809 cmp r0, #9 +10002c2c: f103 0030 add.w r0, r3, #48 @ 0x30 +10002c30: bf8a itet hi +10002c32: 191b addhi r3, r3, r4 +10002c34: b2c3 uxtbls r3, r0 +10002c36: b2db uxtbhi r3, r3 +10002c38: 4561 cmp r1, ip +10002c3a: f80e 3b01 strb.w r3, [lr], #1 +10002c3e: f102 0201 add.w r2, r2, #1 +10002c42: d2ea bcs.n 10002c1a <_vsnprintf+0x95e> +10002c44: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c46: 9d0c ldr r5, [sp, #48] @ 0x30 +10002c48: e7d4 b.n 10002bf4 <_vsnprintf+0x938> +10002c4a: 6819 ldr r1, [r3, #0] +10002c4c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002c50: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002c54: e62d b.n 100028b2 <_vsnprintf+0x5f6> +10002c56: 2a00 cmp r2, #0 +10002c58: f43f af59 beq.w 10002b0e <_vsnprintf+0x852> +10002c5c: aa12 add r2, sp, #72 @ 0x48 +10002c5e: 920b str r2, [sp, #44] @ 0x2c +10002c60: e771 b.n 10002b46 <_vsnprintf+0x88a> +10002c62: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002c66: d00d beq.n 10002c84 <_vsnprintf+0x9c8> +10002c68: f013 0402 ands.w r4, r3, #2 +10002c6c: d012 beq.n 10002c94 <_vsnprintf+0x9d8> +10002c6e: 4604 mov r4, r0 +10002c70: 4646 mov r6, r8 +10002c72: e5ec b.n 1000284e <_vsnprintf+0x592> +10002c74: 270a movs r7, #10 +10002c76: 4663 mov r3, ip +10002c78: 46bc mov ip, r7 +10002c7a: e56c b.n 10002756 <_vsnprintf+0x49a> +10002c7c: ab12 add r3, sp, #72 @ 0x48 +10002c7e: 2000 movs r0, #0 +10002c80: 930b str r3, [sp, #44] @ 0x2c +10002c82: e69d b.n 100029c0 <_vsnprintf+0x704> +10002c84: f013 0302 ands.w r3, r3, #2 +10002c88: f47f ade0 bne.w 1000284c <_vsnprintf+0x590> +10002c8c: 2d00 cmp r5, #0 +10002c8e: f47f af13 bne.w 10002ab8 <_vsnprintf+0x7fc> +10002c92: e49a b.n 100025ca <_vsnprintf+0x30e> +10002c94: 2d00 cmp r5, #0 +10002c96: f47f af0d bne.w 10002ab4 <_vsnprintf+0x7f8> +10002c9a: e496 b.n 100025ca <_vsnprintf+0x30e> +10002c9c: cccccccd .word 0xcccccccd + +10002ca0 : +10002ca0: b570 push {r4, r5, r6, lr} +10002ca2: 4694 mov ip, r2 +10002ca4: 461e mov r6, r3 +10002ca6: 4605 mov r5, r0 +10002ca8: 460c mov r4, r1 +10002caa: b084 sub sp, #16 +10002cac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002cb0: 4663 mov r3, ip +10002cb2: a902 add r1, sp, #8 +10002cb4: 9600 str r6, [sp, #0] +10002cb6: 4803 ldr r0, [pc, #12] @ (10002cc4 ) +10002cb8: e9cd 5402 strd r5, r4, [sp, #8] +10002cbc: f7ff fafe bl 100022bc <_vsnprintf> +10002cc0: b004 add sp, #16 +10002cc2: bd70 pop {r4, r5, r6, pc} +10002cc4: 1000187d .word 0x1000187d + +10002cc8 : +10002cc8: b510 push {r4, lr} +10002cca: 4b09 ldr r3, [pc, #36] @ (10002cf0 ) +10002ccc: b084 sub sp, #16 +10002cce: 681c ldr r4, [r3, #0] +10002cd0: b14c cbz r4, 10002ce6 +10002cd2: 4603 mov r3, r0 +10002cd4: 9100 str r1, [sp, #0] +10002cd6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002cda: a903 add r1, sp, #12 +10002cdc: 4805 ldr r0, [pc, #20] @ (10002cf4 ) +10002cde: 47a0 blx r4 +10002ce0: 2001 movs r0, #1 +10002ce2: b004 add sp, #16 +10002ce4: bd10 pop {r4, pc} +10002ce6: f000 f97d bl 10002fe4 <__wrap_puts> +10002cea: 4620 mov r0, r4 +10002cec: b004 add sp, #16 +10002cee: bd10 pop {r4, pc} +10002cf0: 2000080c .word 0x2000080c +10002cf4: 10001875 .word 0x10001875 + +10002cf8 <_exit>: +10002cf8: be00 bkpt 0x0000 +10002cfa: e7fd b.n 10002cf8 <_exit> + +10002cfc : +10002cfc: b508 push {r3, lr} +10002cfe: f7ff fffb bl 10002cf8 <_exit> +10002d02: bf00 nop + +10002d04 : +10002d04: b538 push {r3, r4, r5, lr} +10002d06: 4c06 ldr r4, [pc, #24] @ (10002d20 ) +10002d08: 4d06 ldr r5, [pc, #24] @ (10002d24 ) +10002d0a: f7fe fa07 bl 1000111c +10002d0e: 42ac cmp r4, r5 +10002d10: d204 bcs.n 10002d1c +10002d12: f854 3b04 ldr.w r3, [r4], #4 +10002d16: 4798 blx r3 +10002d18: 42ac cmp r4, r5 +10002d1a: d3fa bcc.n 10002d12 +10002d1c: bd38 pop {r3, r4, r5, pc} +10002d1e: bf00 nop +10002d20: 10003498 .word 0x10003498 +10002d24: 1000349c .word 0x1000349c + +10002d28 : +10002d28: 6803 ldr r3, [r0, #0] +10002d2a: 4608 mov r0, r1 +10002d2c: 4611 mov r1, r2 +10002d2e: 4718 bx r3 + +10002d30 : +10002d30: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002d34: 4615 mov r5, r2 +10002d36: 7d42 ldrb r2, [r0, #21] +10002d38: 4607 mov r7, r0 +10002d3a: 4688 mov r8, r1 +10002d3c: 2a00 cmp r2, #0 +10002d3e: d046 beq.n 10002dce +10002d40: 2d00 cmp r5, #0 +10002d42: dd1d ble.n 10002d80 +10002d44: 780b ldrb r3, [r1, #0] +10002d46: 2b0a cmp r3, #10 +10002d48: d023 beq.n 10002d92 +10002d4a: 2d01 cmp r5, #1 +10002d4c: f04f 0c00 mov.w ip, #0 +10002d50: d018 beq.n 10002d84 +10002d52: 4646 mov r6, r8 +10002d54: 2401 movs r4, #1 +10002d56: f816 2f01 ldrb.w r2, [r6, #1]! +10002d5a: 4621 mov r1, r4 +10002d5c: 2a0a cmp r2, #10 +10002d5e: f104 0401 add.w r4, r4, #1 +10002d62: d022 beq.n 10002daa +10002d64: 42a5 cmp r5, r4 +10002d66: d1f6 bne.n 10002d56 +10002d68: 4565 cmp r5, ip +10002d6a: dc0b bgt.n 10002d84 +10002d6c: eb08 0305 add.w r3, r8, r5 +10002d70: f813 3c01 ldrb.w r3, [r3, #-1] +10002d74: f1a3 030d sub.w r3, r3, #13 +10002d78: fab3 f383 clz r3, r3 +10002d7c: 095b lsrs r3, r3, #5 +10002d7e: 753b strb r3, [r7, #20] +10002d80: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002d84: 683b ldr r3, [r7, #0] +10002d86: eba5 010c sub.w r1, r5, ip +10002d8a: eb08 000c add.w r0, r8, ip +10002d8e: 4798 blx r3 +10002d90: e7ec b.n 10002d6c +10002d92: 7d03 ldrb r3, [r0, #20] +10002d94: 2b00 cmp r3, #0 +10002d96: d1d8 bne.n 10002d4a +10002d98: 6803 ldr r3, [r0, #0] +10002d9a: 2102 movs r1, #2 +10002d9c: 480f ldr r0, [pc, #60] @ (10002ddc ) +10002d9e: 4798 blx r3 +10002da0: 2d01 cmp r5, #1 +10002da2: d0e3 beq.n 10002d6c +10002da4: f04f 0c01 mov.w ip, #1 +10002da8: e7d3 b.n 10002d52 +10002daa: f816 3c01 ldrb.w r3, [r6, #-1] +10002dae: 2b0d cmp r3, #13 +10002db0: d0d8 beq.n 10002d64 +10002db2: 458c cmp ip, r1 +10002db4: eb08 000c add.w r0, r8, ip +10002db8: eba1 010c sub.w r1, r1, ip +10002dbc: da01 bge.n 10002dc2 +10002dbe: 683b ldr r3, [r7, #0] +10002dc0: 4798 blx r3 +10002dc2: 2102 movs r1, #2 +10002dc4: 4805 ldr r0, [pc, #20] @ (10002ddc ) +10002dc6: 683b ldr r3, [r7, #0] +10002dc8: 4798 blx r3 +10002dca: 46a4 mov ip, r4 +10002dcc: e7ca b.n 10002d64 +10002dce: 4629 mov r1, r5 +10002dd0: 4640 mov r0, r8 +10002dd2: 683b ldr r3, [r7, #0] +10002dd4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002dd8: 4718 bx r3 +10002dda: bf00 nop +10002ddc: 10003638 .word 0x10003638 + +10002de0 : +10002de0: 680b ldr r3, [r1, #0] +10002de2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002de6: 2b80 cmp r3, #128 @ 0x80 +10002de8: 460d mov r5, r1 +10002dea: 4606 mov r6, r0 +10002dec: d005 beq.n 10002dfa +10002dee: 1c5a adds r2, r3, #1 +10002df0: 442b add r3, r5 +10002df2: 602a str r2, [r5, #0] +10002df4: 711e strb r6, [r3, #4] +10002df6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002dfa: 4b0f ldr r3, [pc, #60] @ (10002e38 ) +10002dfc: 681c ldr r4, [r3, #0] +10002dfe: b1a4 cbz r4, 10002e2a +10002e00: 4f0e ldr r7, [pc, #56] @ (10002e3c ) +10002e02: f101 0804 add.w r8, r1, #4 +10002e06: e001 b.n 10002e0c +10002e08: 6924 ldr r4, [r4, #16] +10002e0a: b174 cbz r4, 10002e2a +10002e0c: 6823 ldr r3, [r4, #0] +10002e0e: 2b00 cmp r3, #0 +10002e10: d0fa beq.n 10002e08 +10002e12: 683b ldr r3, [r7, #0] +10002e14: b10b cbz r3, 10002e1a +10002e16: 42a3 cmp r3, r4 +10002e18: d1f6 bne.n 10002e08 +10002e1a: 4620 mov r0, r4 +10002e1c: 4641 mov r1, r8 +10002e1e: 682a ldr r2, [r5, #0] +10002e20: f7ff ff86 bl 10002d30 +10002e24: 6924 ldr r4, [r4, #16] +10002e26: 2c00 cmp r4, #0 +10002e28: d1f0 bne.n 10002e0c +10002e2a: 2300 movs r3, #0 +10002e2c: 2201 movs r2, #1 +10002e2e: 442b add r3, r5 +10002e30: 602a str r2, [r5, #0] +10002e32: 711e strb r6, [r3, #4] +10002e34: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e38: 20000804 .word 0x20000804 +10002e3c: 20000808 .word 0x20000808 + +10002e40 : +10002e40: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002e44: b082 sub sp, #8 +10002e46: 460d mov r5, r1 +10002e48: 4691 mov r9, r2 +10002e4a: 461c mov r4, r3 +10002e4c: 4606 mov r6, r0 +10002e4e: f7fd ffa7 bl 10000da0 +10002e52: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002e56: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002e5a: 4a2e ldr r2, [pc, #184] @ (10002f14 ) +10002e5c: 1882 adds r2, r0, r2 +10002e5e: f141 0300 adc.w r3, r1, #0 +10002e62: 4594 cmp ip, r2 +10002e64: eb77 0103 sbcs.w r1, r7, r3 +10002e68: bf3c itt cc +10002e6a: 4662 movcc r2, ip +10002e6c: 463b movcc r3, r7 +10002e6e: 482a ldr r0, [pc, #168] @ (10002f18 ) +10002e70: f000 faee bl 10003450 <__mutex_try_enter_block_until_veneer> +10002e74: 1c6b adds r3, r5, #1 +10002e76: 4680 mov r8, r0 +10002e78: d040 beq.n 10002efc +10002e7a: b30c cbz r4, 10002ec0 +10002e7c: 4f27 ldr r7, [pc, #156] @ (10002f1c ) +10002e7e: 4b28 ldr r3, [pc, #160] @ (10002f20 ) +10002e80: 681c ldr r4, [r3, #0] +10002e82: b1b4 cbz r4, 10002eb2 +10002e84: f1b9 0f00 cmp.w r9, #0 +10002e88: d11c bne.n 10002ec4 +10002e8a: f8df 909c ldr.w r9, [pc, #156] @ 10002f28 +10002e8e: e001 b.n 10002e94 +10002e90: 6924 ldr r4, [r4, #16] +10002e92: b174 cbz r4, 10002eb2 +10002e94: 6823 ldr r3, [r4, #0] +10002e96: 2b00 cmp r3, #0 +10002e98: d0fa beq.n 10002e90 +10002e9a: f8d9 3000 ldr.w r3, [r9] +10002e9e: b10b cbz r3, 10002ea4 +10002ea0: 429c cmp r4, r3 +10002ea2: d1f5 bne.n 10002e90 +10002ea4: 4620 mov r0, r4 +10002ea6: 462a mov r2, r5 +10002ea8: 4631 mov r1, r6 +10002eaa: 47b8 blx r7 +10002eac: 6924 ldr r4, [r4, #16] +10002eae: 2c00 cmp r4, #0 +10002eb0: d1f0 bne.n 10002e94 +10002eb2: f1b8 0f00 cmp.w r8, #0 +10002eb6: d126 bne.n 10002f06 +10002eb8: 4628 mov r0, r5 +10002eba: b002 add sp, #8 +10002ebc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002ec0: 4f18 ldr r7, [pc, #96] @ (10002f24 ) +10002ec2: e7dc b.n 10002e7e +10002ec4: f04f 0a0a mov.w sl, #10 +10002ec8: f8df 905c ldr.w r9, [pc, #92] @ 10002f28 +10002ecc: e002 b.n 10002ed4 +10002ece: 6924 ldr r4, [r4, #16] +10002ed0: 2c00 cmp r4, #0 +10002ed2: d0ee beq.n 10002eb2 +10002ed4: 6823 ldr r3, [r4, #0] +10002ed6: 2b00 cmp r3, #0 +10002ed8: d0f9 beq.n 10002ece +10002eda: f8d9 3000 ldr.w r3, [r9] +10002ede: b10b cbz r3, 10002ee4 +10002ee0: 42a3 cmp r3, r4 +10002ee2: d1f4 bne.n 10002ece +10002ee4: 462a mov r2, r5 +10002ee6: 4631 mov r1, r6 +10002ee8: 4620 mov r0, r4 +10002eea: 47b8 blx r7 +10002eec: 2201 movs r2, #1 +10002eee: 4620 mov r0, r4 +10002ef0: f10d 0107 add.w r1, sp, #7 +10002ef4: f88d a007 strb.w sl, [sp, #7] +10002ef8: 47b8 blx r7 +10002efa: e7e8 b.n 10002ece +10002efc: 4630 mov r0, r6 +10002efe: f000 fa6f bl 100033e0 +10002f02: 4605 mov r5, r0 +10002f04: e7b9 b.n 10002e7a +10002f06: 4804 ldr r0, [pc, #16] @ (10002f18 ) +10002f08: f000 fa9e bl 10003448 <__mutex_exit_veneer> +10002f0c: 4628 mov r0, r5 +10002f0e: b002 add sp, #8 +10002f10: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002f14: 000f4240 .word 0x000f4240 +10002f18: 20000624 .word 0x20000624 +10002f1c: 10002d31 .word 0x10002d31 +10002f20: 20000804 .word 0x20000804 +10002f24: 10002d29 .word 0x10002d29 +10002f28: 20000808 .word 0x20000808 + +10002f2c : +10002f2c: 4a08 ldr r2, [pc, #32] @ (10002f50 ) +10002f2e: 6813 ldr r3, [r2, #0] +10002f30: b923 cbnz r3, 10002f3c +10002f32: e00a b.n 10002f4a +10002f34: f103 0210 add.w r2, r3, #16 +10002f38: 691b ldr r3, [r3, #16] +10002f3a: b133 cbz r3, 10002f4a +10002f3c: 4283 cmp r3, r0 +10002f3e: d1f9 bne.n 10002f34 +10002f40: b929 cbnz r1, 10002f4e +10002f42: 6918 ldr r0, [r3, #16] +10002f44: 6010 str r0, [r2, #0] +10002f46: 6119 str r1, [r3, #16] +10002f48: 4770 bx lr +10002f4a: b101 cbz r1, 10002f4e +10002f4c: 6010 str r0, [r2, #0] +10002f4e: 4770 bx lr +10002f50: 20000804 .word 0x20000804 + +10002f54 : +10002f54: b508 push {r3, lr} +10002f56: f000 f9a3 bl 100032a0 +10002f5a: 2001 movs r0, #1 +10002f5c: bd08 pop {r3, pc} +10002f5e: bf00 nop + +10002f60 <__wrap_putchar>: +10002f60: b5f0 push {r4, r5, r6, r7, lr} +10002f62: b083 sub sp, #12 +10002f64: 4606 mov r6, r0 +10002f66: f88d 0007 strb.w r0, [sp, #7] +10002f6a: f7fd ff19 bl 10000da0 +10002f6e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10002f72: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10002f76: 4a17 ldr r2, [pc, #92] @ (10002fd4 <__wrap_putchar+0x74>) +10002f78: 1882 adds r2, r0, r2 +10002f7a: f141 0300 adc.w r3, r1, #0 +10002f7e: 4295 cmp r5, r2 +10002f80: eb74 0103 sbcs.w r1, r4, r3 +10002f84: bf3c itt cc +10002f86: 4623 movcc r3, r4 +10002f88: 462a movcc r2, r5 +10002f8a: 4813 ldr r0, [pc, #76] @ (10002fd8 <__wrap_putchar+0x78>) +10002f8c: f000 fa60 bl 10003450 <__mutex_try_enter_block_until_veneer> +10002f90: 4b12 ldr r3, [pc, #72] @ (10002fdc <__wrap_putchar+0x7c>) +10002f92: 4607 mov r7, r0 +10002f94: 681c ldr r4, [r3, #0] +10002f96: b19c cbz r4, 10002fc0 <__wrap_putchar+0x60> +10002f98: 4d11 ldr r5, [pc, #68] @ (10002fe0 <__wrap_putchar+0x80>) +10002f9a: e001 b.n 10002fa0 <__wrap_putchar+0x40> +10002f9c: 6924 ldr r4, [r4, #16] +10002f9e: b17c cbz r4, 10002fc0 <__wrap_putchar+0x60> +10002fa0: 6823 ldr r3, [r4, #0] +10002fa2: 2b00 cmp r3, #0 +10002fa4: d0fa beq.n 10002f9c <__wrap_putchar+0x3c> +10002fa6: 682b ldr r3, [r5, #0] +10002fa8: b10b cbz r3, 10002fae <__wrap_putchar+0x4e> +10002faa: 429c cmp r4, r3 +10002fac: d1f6 bne.n 10002f9c <__wrap_putchar+0x3c> +10002fae: 4620 mov r0, r4 +10002fb0: 2201 movs r2, #1 +10002fb2: f10d 0107 add.w r1, sp, #7 +10002fb6: f7ff febb bl 10002d30 +10002fba: 6924 ldr r4, [r4, #16] +10002fbc: 2c00 cmp r4, #0 +10002fbe: d1ef bne.n 10002fa0 <__wrap_putchar+0x40> +10002fc0: b917 cbnz r7, 10002fc8 <__wrap_putchar+0x68> +10002fc2: 4630 mov r0, r6 +10002fc4: b003 add sp, #12 +10002fc6: bdf0 pop {r4, r5, r6, r7, pc} +10002fc8: 4803 ldr r0, [pc, #12] @ (10002fd8 <__wrap_putchar+0x78>) +10002fca: f000 fa3d bl 10003448 <__mutex_exit_veneer> +10002fce: 4630 mov r0, r6 +10002fd0: b003 add sp, #12 +10002fd2: bdf0 pop {r4, r5, r6, r7, pc} +10002fd4: 000f4240 .word 0x000f4240 +10002fd8: 20000624 .word 0x20000624 +10002fdc: 20000804 .word 0x20000804 +10002fe0: 20000808 .word 0x20000808 + +10002fe4 <__wrap_puts>: +10002fe4: b538 push {r3, r4, r5, lr} +10002fe6: 4604 mov r4, r0 +10002fe8: f000 f9fa bl 100033e0 +10002fec: 2301 movs r3, #1 +10002fee: 4605 mov r5, r0 +10002ff0: 461a mov r2, r3 +10002ff2: 4620 mov r0, r4 +10002ff4: 4629 mov r1, r5 +10002ff6: f7ff ff23 bl 10002e40 +10002ffa: 4b08 ldr r3, [pc, #32] @ (1000301c <__wrap_puts+0x38>) +10002ffc: 681c ldr r4, [r3, #0] +10002ffe: b12c cbz r4, 1000300c <__wrap_puts+0x28> +10003000: 6863 ldr r3, [r4, #4] +10003002: b12b cbz r3, 10003010 <__wrap_puts+0x2c> +10003004: 4798 blx r3 +10003006: 6924 ldr r4, [r4, #16] +10003008: 2c00 cmp r4, #0 +1000300a: d1f9 bne.n 10003000 <__wrap_puts+0x1c> +1000300c: 4628 mov r0, r5 +1000300e: bd38 pop {r3, r4, r5, pc} +10003010: 6924 ldr r4, [r4, #16] +10003012: 2c00 cmp r4, #0 +10003014: d1f4 bne.n 10003000 <__wrap_puts+0x1c> +10003016: 4628 mov r0, r5 +10003018: bd38 pop {r3, r4, r5, pc} +1000301a: bf00 nop +1000301c: 20000804 .word 0x20000804 + +10003020 <__wrap_vprintf>: +10003020: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003024: b0a2 sub sp, #136 @ 0x88 +10003026: 4604 mov r4, r0 +10003028: 460d mov r5, r1 +1000302a: f7fd feb9 bl 10000da0 +1000302e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10003032: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003036: 4a26 ldr r2, [pc, #152] @ (100030d0 <__wrap_vprintf+0xb0>) +10003038: f8df 80a4 ldr.w r8, [pc, #164] @ 100030e0 <__wrap_vprintf+0xc0> +1000303c: 1882 adds r2, r0, r2 +1000303e: f141 0300 adc.w r3, r1, #0 +10003042: 4297 cmp r7, r2 +10003044: eb76 0103 sbcs.w r1, r6, r3 +10003048: bf3c itt cc +1000304a: 463a movcc r2, r7 +1000304c: 4633 movcc r3, r6 +1000304e: 4821 ldr r0, [pc, #132] @ (100030d4 <__wrap_vprintf+0xb4>) +10003050: f000 f9fe bl 10003450 <__mutex_try_enter_block_until_veneer> +10003054: 2700 movs r7, #0 +10003056: 462b mov r3, r5 +10003058: 4622 mov r2, r4 +1000305a: 4606 mov r6, r0 +1000305c: a901 add r1, sp, #4 +1000305e: 481e ldr r0, [pc, #120] @ (100030d8 <__wrap_vprintf+0xb8>) +10003060: 9701 str r7, [sp, #4] +10003062: f7ff fe1d bl 10002ca0 +10003066: 9b01 ldr r3, [sp, #4] +10003068: 4605 mov r5, r0 +1000306a: f8d8 4000 ldr.w r4, [r8] +1000306e: b1c3 cbz r3, 100030a2 <__wrap_vprintf+0x82> +10003070: 2c00 cmp r4, #0 +10003072: d02b beq.n 100030cc <__wrap_vprintf+0xac> +10003074: 4f19 ldr r7, [pc, #100] @ (100030dc <__wrap_vprintf+0xbc>) +10003076: e001 b.n 1000307c <__wrap_vprintf+0x5c> +10003078: 6924 ldr r4, [r4, #16] +1000307a: b174 cbz r4, 1000309a <__wrap_vprintf+0x7a> +1000307c: 6823 ldr r3, [r4, #0] +1000307e: 2b00 cmp r3, #0 +10003080: d0fa beq.n 10003078 <__wrap_vprintf+0x58> +10003082: 683b ldr r3, [r7, #0] +10003084: b10b cbz r3, 1000308a <__wrap_vprintf+0x6a> +10003086: 42a3 cmp r3, r4 +10003088: d1f6 bne.n 10003078 <__wrap_vprintf+0x58> +1000308a: 4620 mov r0, r4 +1000308c: 9a01 ldr r2, [sp, #4] +1000308e: a902 add r1, sp, #8 +10003090: f7ff fe4e bl 10002d30 +10003094: 6924 ldr r4, [r4, #16] +10003096: 2c00 cmp r4, #0 +10003098: d1f0 bne.n 1000307c <__wrap_vprintf+0x5c> +1000309a: 2300 movs r3, #0 +1000309c: f8d8 4000 ldr.w r4, [r8] +100030a0: 9301 str r3, [sp, #4] +100030a2: b12c cbz r4, 100030b0 <__wrap_vprintf+0x90> +100030a4: 6863 ldr r3, [r4, #4] +100030a6: b143 cbz r3, 100030ba <__wrap_vprintf+0x9a> +100030a8: 4798 blx r3 +100030aa: 6924 ldr r4, [r4, #16] +100030ac: 2c00 cmp r4, #0 +100030ae: d1f9 bne.n 100030a4 <__wrap_vprintf+0x84> +100030b0: b92e cbnz r6, 100030be <__wrap_vprintf+0x9e> +100030b2: 4628 mov r0, r5 +100030b4: b022 add sp, #136 @ 0x88 +100030b6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030ba: 6924 ldr r4, [r4, #16] +100030bc: e7f1 b.n 100030a2 <__wrap_vprintf+0x82> +100030be: 4805 ldr r0, [pc, #20] @ (100030d4 <__wrap_vprintf+0xb4>) +100030c0: f000 f9c2 bl 10003448 <__mutex_exit_veneer> +100030c4: 4628 mov r0, r5 +100030c6: b022 add sp, #136 @ 0x88 +100030c8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030cc: 9401 str r4, [sp, #4] +100030ce: e7ef b.n 100030b0 <__wrap_vprintf+0x90> +100030d0: 000f4240 .word 0x000f4240 +100030d4: 20000624 .word 0x20000624 +100030d8: 10002de1 .word 0x10002de1 +100030dc: 20000808 .word 0x20000808 +100030e0: 20000804 .word 0x20000804 + +100030e4 <__wrap_printf>: +100030e4: b40f push {r0, r1, r2, r3} +100030e6: b500 push {lr} +100030e8: b083 sub sp, #12 +100030ea: a904 add r1, sp, #16 +100030ec: f851 0b04 ldr.w r0, [r1], #4 +100030f0: 9101 str r1, [sp, #4] +100030f2: f7ff ff95 bl 10003020 <__wrap_vprintf> +100030f6: b003 add sp, #12 +100030f8: f85d eb04 ldr.w lr, [sp], #4 +100030fc: b004 add sp, #16 +100030fe: 4770 bx lr + +10003100 : +10003100: f1b1 0c00 subs.w ip, r1, #0 +10003104: dd1d ble.n 10003142 +10003106: 4a0f ldr r2, [pc, #60] @ (10003144 ) +10003108: 4b0f ldr r3, [pc, #60] @ (10003148 ) +1000310a: 6812 ldr r2, [r2, #0] +1000310c: b530 push {r4, r5, lr} +1000310e: 1ad3 subs r3, r2, r3 +10003110: fab3 f383 clz r3, r3 +10003114: 240d movs r4, #13 +10003116: 4d0d ldr r5, [pc, #52] @ (1000314c ) +10003118: 095b lsrs r3, r3, #5 +1000311a: 1e41 subs r1, r0, #1 +1000311c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003120: 448c add ip, r1 +10003122: f811 0f01 ldrb.w r0, [r1, #1]! +10003126: 4586 cmp lr, r0 +10003128: d006 beq.n 10003138 +1000312a: 6993 ldr r3, [r2, #24] +1000312c: 069b lsls r3, r3, #26 +1000312e: d4fc bmi.n 1000312a +10003130: 4561 cmp r1, ip +10003132: 6010 str r0, [r2, #0] +10003134: d1f5 bne.n 10003122 +10003136: bd30 pop {r4, r5, pc} +10003138: 6993 ldr r3, [r2, #24] +1000313a: 069d lsls r5, r3, #26 +1000313c: d4fc bmi.n 10003138 +1000313e: 6014 str r4, [r2, #0] +10003140: e7f3 b.n 1000312a +10003142: 4770 bx lr +10003144: 20000850 .word 0x20000850 +10003148: 40078000 .word 0x40078000 +1000314c: 2000084c .word 0x2000084c + +10003150 : +10003150: 4b22 ldr r3, [pc, #136] @ (100031dc ) +10003152: f1b1 0c00 subs.w ip, r1, #0 +10003156: b410 push {r4} +10003158: 681c ldr r4, [r3, #0] +1000315a: dd2e ble.n 100031ba +1000315c: 4603 mov r3, r0 +1000315e: 2000 movs r0, #0 +10003160: 4a1f ldr r2, [pc, #124] @ (100031e0 ) +10003162: 1e59 subs r1, r3, #1 +10003164: 6812 ldr r2, [r2, #0] +10003166: 6993 ldr r3, [r2, #24] +10003168: 06db lsls r3, r3, #27 +1000316a: d417 bmi.n 1000319c +1000316c: 3001 adds r0, #1 +1000316e: 6993 ldr r3, [r2, #24] +10003170: 06db lsls r3, r3, #27 +10003172: d4fc bmi.n 1000316e +10003174: 6813 ldr r3, [r2, #0] +10003176: 4584 cmp ip, r0 +10003178: f801 3f01 strb.w r3, [r1, #1]! +1000317c: d1f3 bne.n 10003166 +1000317e: b14c cbz r4, 10003194 +10003180: 2150 movs r1, #80 @ 0x50 +10003182: 4613 mov r3, r2 +10003184: 6391 str r1, [r2, #56] @ 0x38 +10003186: f853 2f34 ldr.w r2, [r3, #52]! +1000318a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000318e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003192: 601a str r2, [r3, #0] +10003194: 4660 mov r0, ip +10003196: f85d 4b04 ldr.w r4, [sp], #4 +1000319a: 4770 bx lr +1000319c: b14c cbz r4, 100031b2 +1000319e: 2150 movs r1, #80 @ 0x50 +100031a0: 4613 mov r3, r2 +100031a2: 6391 str r1, [r2, #56] @ 0x38 +100031a4: f853 2f34 ldr.w r2, [r3, #52]! +100031a8: f002 0238 and.w r2, r2, #56 @ 0x38 +100031ac: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031b0: 601a str r2, [r3, #0] +100031b2: b178 cbz r0, 100031d4 +100031b4: f85d 4b04 ldr.w r4, [sp], #4 +100031b8: 4770 bx lr +100031ba: b15c cbz r4, 100031d4 +100031bc: 4b08 ldr r3, [pc, #32] @ (100031e0 ) +100031be: 2150 movs r1, #80 @ 0x50 +100031c0: 681a ldr r2, [r3, #0] +100031c2: 4613 mov r3, r2 +100031c4: 6391 str r1, [r2, #56] @ 0x38 +100031c6: f853 2f34 ldr.w r2, [r3, #52]! +100031ca: f002 0238 and.w r2, r2, #56 @ 0x38 +100031ce: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031d2: 601a str r2, [r3, #0] +100031d4: f06f 0002 mvn.w r0, #2 +100031d8: e7dd b.n 10003196 +100031da: bf00 nop +100031dc: 200007d0 .word 0x200007d0 +100031e0: 20000850 .word 0x20000850 + +100031e4 : +100031e4: 4b05 ldr r3, [pc, #20] @ (100031fc ) +100031e6: 681b ldr r3, [r3, #0] +100031e8: b133 cbz r3, 100031f8 +100031ea: 2100 movs r1, #0 +100031ec: 4a04 ldr r2, [pc, #16] @ (10003200 ) +100031ee: 4805 ldr r0, [pc, #20] @ (10003204 ) +100031f0: 6812 ldr r2, [r2, #0] +100031f2: 6800 ldr r0, [r0, #0] +100031f4: 6391 str r1, [r2, #56] @ 0x38 +100031f6: 4718 bx r3 +100031f8: 4770 bx lr +100031fa: bf00 nop +100031fc: 200007d0 .word 0x200007d0 +10003200: 20000850 .word 0x20000850 +10003204: 200007d4 .word 0x200007d4 + +10003208 : +10003208: 4b02 ldr r3, [pc, #8] @ (10003214 ) +1000320a: 681a ldr r2, [r3, #0] +1000320c: 6993 ldr r3, [r2, #24] +1000320e: 071b lsls r3, r3, #28 +10003210: d4fc bmi.n 1000320c +10003212: 4770 bx lr +10003214: 20000850 .word 0x20000850 + +10003218 : +10003218: b5f8 push {r3, r4, r5, r6, r7, lr} +1000321a: 4f1c ldr r7, [pc, #112] @ (1000328c ) +1000321c: 4d1c ldr r5, [pc, #112] @ (10003290 ) +1000321e: 683a ldr r2, [r7, #0] +10003220: 4e1c ldr r6, [pc, #112] @ (10003294 ) +10003222: 42aa cmp r2, r5 +10003224: bf14 ite ne +10003226: 2521 movne r5, #33 @ 0x21 +10003228: 2522 moveq r5, #34 @ 0x22 +1000322a: 4604 mov r4, r0 +1000322c: f8d6 c000 ldr.w ip, [r6] +10003230: b118 cbz r0, 1000323a +10003232: f1bc 0f00 cmp.w ip, #0 +10003236: d010 beq.n 1000325a +10003238: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000323a: f1bc 0f00 cmp.w ip, #0 +1000323e: d0fb beq.n 10003238 +10003240: 4601 mov r1, r0 +10003242: 6390 str r0, [r2, #56] @ 0x38 +10003244: 4628 mov r0, r5 +10003246: f7fd f8a1 bl 1000038c +1000324a: 4628 mov r0, r5 +1000324c: 4912 ldr r1, [pc, #72] @ (10003298 ) +1000324e: f7fd f8e3 bl 10000418 +10003252: 4b12 ldr r3, [pc, #72] @ (1000329c ) +10003254: 6034 str r4, [r6, #0] +10003256: 601c str r4, [r3, #0] +10003258: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000325a: 460b mov r3, r1 +1000325c: 4a0f ldr r2, [pc, #60] @ (1000329c ) +1000325e: 490e ldr r1, [pc, #56] @ (10003298 ) +10003260: 6030 str r0, [r6, #0] +10003262: 4628 mov r0, r5 +10003264: 6013 str r3, [r2, #0] +10003266: f7fd f8a7 bl 100003b8 +1000326a: 2101 movs r1, #1 +1000326c: 4628 mov r0, r5 +1000326e: f7fd f88d bl 1000038c +10003272: 683a ldr r2, [r7, #0] +10003274: 2150 movs r1, #80 @ 0x50 +10003276: 4613 mov r3, r2 +10003278: 6391 str r1, [r2, #56] @ 0x38 +1000327a: f853 2f34 ldr.w r2, [r3, #52]! +1000327e: f002 0238 and.w r2, r2, #56 @ 0x38 +10003282: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003286: 601a str r2, [r3, #0] +10003288: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000328a: bf00 nop +1000328c: 20000850 .word 0x20000850 +10003290: 40078000 .word 0x40078000 +10003294: 200007d0 .word 0x200007d0 +10003298: 100031e5 .word 0x100031e5 +1000329c: 200007d4 .word 0x200007d4 + +100032a0 : +100032a0: b510 push {r4, lr} +100032a2: 490e ldr r1, [pc, #56] @ (100032dc ) +100032a4: 4c0e ldr r4, [pc, #56] @ (100032e0 ) +100032a6: 480f ldr r0, [pc, #60] @ (100032e4 ) +100032a8: 4a0f ldr r2, [pc, #60] @ (100032e8 ) +100032aa: 4b10 ldr r3, [pc, #64] @ (100032ec ) +100032ac: 7800 ldrb r0, [r0, #0] +100032ae: 6021 str r1, [r4, #0] +100032b0: 2000 movs r0, #0 +100032b2: 2102 movs r1, #2 +100032b4: 7812 ldrb r2, [r2, #0] +100032b6: 781b ldrb r3, [r3, #0] +100032b8: f7fc ffc6 bl 10000248 +100032bc: 2102 movs r1, #2 +100032be: 2001 movs r0, #1 +100032c0: f7fc ffc2 bl 10000248 +100032c4: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100032c8: 6820 ldr r0, [r4, #0] +100032ca: f7fd fda1 bl 10000e10 +100032ce: e8bd 4010 ldmia.w sp!, {r4, lr} +100032d2: 2101 movs r1, #1 +100032d4: 4806 ldr r0, [pc, #24] @ (100032f0 ) +100032d6: f7ff be29 b.w 10002f2c +100032da: bf00 nop +100032dc: 40070000 .word 0x40070000 +100032e0: 20000850 .word 0x20000850 +100032e4: 10003688 .word 0x10003688 +100032e8: 10003684 .word 0x10003684 +100032ec: 10003680 .word 0x10003680 +100032f0: 2000060c .word 0x2000060c + +100032f4 : +100032f4: 4684 mov ip, r0 +100032f6: ea41 0300 orr.w r3, r1, r0 +100032fa: f013 0303 ands.w r3, r3, #3 +100032fe: d149 bne.n 10003394 +10003300: 3a40 subs r2, #64 @ 0x40 +10003302: d323 bcc.n 1000334c +10003304: 680b ldr r3, [r1, #0] +10003306: 6003 str r3, [r0, #0] +10003308: 684b ldr r3, [r1, #4] +1000330a: 6043 str r3, [r0, #4] +1000330c: 688b ldr r3, [r1, #8] +1000330e: 6083 str r3, [r0, #8] +10003310: 68cb ldr r3, [r1, #12] +10003312: 60c3 str r3, [r0, #12] +10003314: 690b ldr r3, [r1, #16] +10003316: 6103 str r3, [r0, #16] +10003318: 694b ldr r3, [r1, #20] +1000331a: 6143 str r3, [r0, #20] +1000331c: 698b ldr r3, [r1, #24] +1000331e: 6183 str r3, [r0, #24] +10003320: 69cb ldr r3, [r1, #28] +10003322: 61c3 str r3, [r0, #28] +10003324: 6a0b ldr r3, [r1, #32] +10003326: 6203 str r3, [r0, #32] +10003328: 6a4b ldr r3, [r1, #36] @ 0x24 +1000332a: 6243 str r3, [r0, #36] @ 0x24 +1000332c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000332e: 6283 str r3, [r0, #40] @ 0x28 +10003330: 6acb ldr r3, [r1, #44] @ 0x2c +10003332: 62c3 str r3, [r0, #44] @ 0x2c +10003334: 6b0b ldr r3, [r1, #48] @ 0x30 +10003336: 6303 str r3, [r0, #48] @ 0x30 +10003338: 6b4b ldr r3, [r1, #52] @ 0x34 +1000333a: 6343 str r3, [r0, #52] @ 0x34 +1000333c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000333e: 6383 str r3, [r0, #56] @ 0x38 +10003340: 6bcb ldr r3, [r1, #60] @ 0x3c +10003342: 63c3 str r3, [r0, #60] @ 0x3c +10003344: 3040 adds r0, #64 @ 0x40 +10003346: 3140 adds r1, #64 @ 0x40 +10003348: 3a40 subs r2, #64 @ 0x40 +1000334a: d2db bcs.n 10003304 +1000334c: 3230 adds r2, #48 @ 0x30 +1000334e: d30b bcc.n 10003368 +10003350: 680b ldr r3, [r1, #0] +10003352: 6003 str r3, [r0, #0] +10003354: 684b ldr r3, [r1, #4] +10003356: 6043 str r3, [r0, #4] +10003358: 688b ldr r3, [r1, #8] +1000335a: 6083 str r3, [r0, #8] +1000335c: 68cb ldr r3, [r1, #12] +1000335e: 60c3 str r3, [r0, #12] +10003360: 3010 adds r0, #16 +10003362: 3110 adds r1, #16 +10003364: 3a10 subs r2, #16 +10003366: d2f3 bcs.n 10003350 +10003368: 320c adds r2, #12 +1000336a: d305 bcc.n 10003378 +1000336c: f851 3b04 ldr.w r3, [r1], #4 +10003370: f840 3b04 str.w r3, [r0], #4 +10003374: 3a04 subs r2, #4 +10003376: d2f9 bcs.n 1000336c +10003378: 3204 adds r2, #4 +1000337a: d008 beq.n 1000338e +1000337c: 07d2 lsls r2, r2, #31 +1000337e: bf1c itt ne +10003380: f811 3b01 ldrbne.w r3, [r1], #1 +10003384: f800 3b01 strbne.w r3, [r0], #1 +10003388: d301 bcc.n 1000338e +1000338a: 880b ldrh r3, [r1, #0] +1000338c: 8003 strh r3, [r0, #0] +1000338e: 4660 mov r0, ip +10003390: 4770 bx lr +10003392: bf00 nop +10003394: 2a08 cmp r2, #8 +10003396: d313 bcc.n 100033c0 +10003398: 078b lsls r3, r1, #30 +1000339a: d0b1 beq.n 10003300 +1000339c: f010 0303 ands.w r3, r0, #3 +100033a0: d0ae beq.n 10003300 +100033a2: f1c3 0304 rsb r3, r3, #4 +100033a6: 1ad2 subs r2, r2, r3 +100033a8: 07db lsls r3, r3, #31 +100033aa: bf1c itt ne +100033ac: f811 3b01 ldrbne.w r3, [r1], #1 +100033b0: f800 3b01 strbne.w r3, [r0], #1 +100033b4: d3a4 bcc.n 10003300 +100033b6: f831 3b02 ldrh.w r3, [r1], #2 +100033ba: f820 3b02 strh.w r3, [r0], #2 +100033be: e79f b.n 10003300 +100033c0: 3a04 subs r2, #4 +100033c2: d3d9 bcc.n 10003378 +100033c4: 3a01 subs r2, #1 +100033c6: f811 3b01 ldrb.w r3, [r1], #1 +100033ca: f800 3b01 strb.w r3, [r0], #1 +100033ce: d2f9 bcs.n 100033c4 +100033d0: 780b ldrb r3, [r1, #0] +100033d2: 7003 strb r3, [r0, #0] +100033d4: 784b ldrb r3, [r1, #1] +100033d6: 7043 strb r3, [r0, #1] +100033d8: 788b ldrb r3, [r1, #2] +100033da: 7083 strb r3, [r0, #2] +100033dc: 4660 mov r0, ip +100033de: 4770 bx lr + +100033e0 : +100033e0: f020 0103 bic.w r1, r0, #3 +100033e4: f010 0003 ands.w r0, r0, #3 +100033e8: f1c0 0000 rsb r0, r0, #0 +100033ec: f851 3b04 ldr.w r3, [r1], #4 +100033f0: f100 0c04 add.w ip, r0, #4 +100033f4: ea4f 0ccc mov.w ip, ip, lsl #3 +100033f8: f06f 0200 mvn.w r2, #0 +100033fc: bf1c itt ne +100033fe: fa22 f20c lsrne.w r2, r2, ip +10003402: 4313 orrne r3, r2 +10003404: f04f 0c01 mov.w ip, #1 +10003408: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000340c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003410: eba3 020c sub.w r2, r3, ip +10003414: ea22 0203 bic.w r2, r2, r3 +10003418: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000341c: bf04 itt eq +1000341e: f851 3b04 ldreq.w r3, [r1], #4 +10003422: 3004 addeq r0, #4 +10003424: d0f4 beq.n 10003410 +10003426: f1c2 0100 rsb r1, r2, #0 +1000342a: ea02 0201 and.w r2, r2, r1 +1000342e: fab2 f282 clz r2, r2 +10003432: f1c2 021f rsb r2, r2, #31 +10003436: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000343a: 4770 bx lr + +1000343c <_fini>: +1000343c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000343e: bf00 nop + +10003440 <____aeabi_uldivmod_veneer>: +10003440: f85f f000 ldr.w pc, [pc] @ 10003444 <____aeabi_uldivmod_veneer+0x4> +10003444: 20000221 .word 0x20000221 + +10003448 <__mutex_exit_veneer>: +10003448: f85f f000 ldr.w pc, [pc] @ 1000344c <__mutex_exit_veneer+0x4> +1000344c: 200001e5 .word 0x200001e5 + +10003450 <__mutex_try_enter_block_until_veneer>: +10003450: f85f f000 ldr.w pc, [pc] @ 10003454 <__mutex_try_enter_block_until_veneer+0x4> +10003454: 2000017d .word 0x2000017d + +10003458 <__pre_init_runtime_init_bootrom_reset>: +10003458: 100011c9 .... + +1000345c <__pre_init_runtime_init_early_resets>: +1000345c: 1000113d =... + +10003460 <__pre_init_runtime_init_usb_power_down>: +10003460: 10001171 q... + +10003464 <__pre_init_runtime_init_clocks>: +10003464: 1000125d ]... + +10003468 <__pre_init_runtime_init_post_clock_resets>: +10003468: 100011a9 .... + +1000346c <__pre_init_runtime_init_boot_locks_reset>: +1000346c: 100010c1 .... + +10003470 <__pre_init_runtime_init_spin_locks_reset>: +10003470: 100011f1 .... + +10003474 <__pre_init_runtime_init_bootrom_locking_enable>: +10003474: 100010ad .... + +10003478 <__pre_init_runtime_init_mutex>: +10003478: 100006d5 .... + +1000347c <__pre_init_runtime_init_install_ram_vector_table>: +1000347c: 100011f5 .... + +10003480 <__pre_init_runtime_init_default_alarm_pool>: +10003480: 10000a51 Q... + +10003484 <__pre_init_first_per_core_initializer>: +10003484: 1000110d .... + +10003488 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003488: 100011dd .... + +1000348c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000348c: 1000118d .... + +10003490 <__pre_init_spinlock_set_extexclall>: +10003490: 10000325 %... + +10003494 <__pre_init_runtime_init_per_core_irq_priorities>: +10003494: 1000034d M... + +10003498 <__frame_dummy_init_array_entry>: +10003498: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000c99 .word 0x10000c99 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 1000060d .word 0x1000060d + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003101 10003209 10003151 10003219 .1...2..Q1...2.. +2000061c: 00000000 00000100 ........ + +20000624 : + ... diff --git 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b/WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.uf2 differ diff --git a/WEEK04/0x0005_intro-to-variables/build/hacked.uf2 b/WEEK04/0x0005_intro-to-variables/build/hacked.uf2 new file mode 100644 index 0000000..aead397 Binary files /dev/null and b/WEEK04/0x0005_intro-to-variables/build/hacked.uf2 differ diff --git a/WEEK04/0x0005_intro-to-variables/build/pico_flash_region.ld b/WEEK04/0x0005_intro-to-variables/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0005_intro-to-variables/pico_sdk_import.cmake b/WEEK04/0x0005_intro-to-variables/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0005_intro-to-variables/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables-a/.gitignore b/WEEK04/0x0008_uninitialized-variables-a/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..27d83bd --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/c_cpp_properties.json @@ -0,0 +1,21 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0008_uninitialized-variables-a/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables-a/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-a/0x0008_uninitialized-variables-a.c b/WEEK04/0x0008_uninitialized-variables-a/0x0008_uninitialized-variables-a.c new file mode 100644 index 0000000..656a992 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/0x0008_uninitialized-variables-a.c @@ -0,0 +1,18 @@ +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) +{ + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + + while (true) { + gpio_put(LED_PIN, 1); + sleep_ms(500); + + gpio_put(LED_PIN, 0); + sleep_ms(500); + } +} diff --git a/WEEK04/0x0008_uninitialized-variables-a/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables-a/CMakeLists.txt new file mode 100644 index 0000000..347375d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables-a C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables-a 0x0008_uninitialized-variables-a.c ) + +pico_set_program_name(0x0008_uninitialized-variables-a "0x0008_uninitialized-variables-a") +pico_set_program_version(0x0008_uninitialized-variables-a "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables-a 0) +pico_enable_stdio_usb(0x0008_uninitialized-variables-a 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables-a + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables-a PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables-a) + diff --git a/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.bin b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.bin new file mode 100755 index 0000000..db9be2d Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.bin differ diff --git a/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.dis b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.dis new file mode 100644 index 0000000..15c8e3f --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.dis @@ -0,0 +1,2292 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000014bc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000104 100014bc 100014bc 000024bc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100015c0 100015c0 000025c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000020 100015c8 100015c8 000025c8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003738 2**0 + CONTENTS + 6 .data 0000013c 20000110 100015e8 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000024c 2000024c 00003738 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000024c 2000024c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000214 20000250 10001724 00004250 2**3 + ALLOC + 10 .heap 00000800 20000464 10001724 00004464 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003738 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003738 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001724 10001724 00003724 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003738 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 0000376c 2**0 + CONTENTS, READONLY + 17 .debug_info 0001d45b 00000000 00000000 000037b1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00004df7 00000000 00000000 00020c0c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0000eb36 00000000 00000000 00025a03 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000a18 00000000 00000000 00034540 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00002b5f 00000000 00000000 00034f58 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00013910 00000000 00000000 00037ab7 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00004d08 00000000 00000000 0004b3c7 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001c60 00000000 00000000 000500d0 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 0000018e 00000000 00000000 00051d30 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100015c8 .word 0x100015c8 +1000012c: 100015e8 .word 0x100015e8 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 000015ec .word 0x000015ec +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100015e8 .word 0x100015e8 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000024c .word 0x2000024c +100001ac: 10001724 .word 0x10001724 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001724 .word 0x10001724 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000024c .word 0x2000024c +100001d4: 20000464 .word 0x20000464 +100001d8: 10001095 .word 0x10001095 +100001dc: 10000235 .word 0x10000235 +100001e0: 1000108d .word 0x1000108d + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000024c .word 0x2000024c +10000208: 2000024c .word 0x2000024c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000428 .word 0x20000428 +10000230: 100014bc .word 0x100014bc + +10000234
: +10000234: b508 push {r3, lr} +10000236: 2010 movs r0, #16 +10000238: f000 f816 bl 10000268 +1000023c: f04f 0501 mov.w r5, #1 +10000240: 2310 movs r3, #16 +10000242: ec45 3044 gpioc_bit_oe_put r3, r5 +10000246: f04f 0600 mov.w r6, #0 +1000024a: 2410 movs r4, #16 +1000024c: ec45 4040 gpioc_bit_out_put r4, r5 +10000250: f44f 70fa mov.w r0, #500 @ 0x1f4 +10000254: f000 fbdc bl 10000a10 +10000258: ec46 4040 gpioc_bit_out_put r4, r6 +1000025c: f44f 70fa mov.w r0, #500 @ 0x1f4 +10000260: f000 fbd6 bl 10000a10 +10000264: e7f1 b.n 1000024a +10000266: bf00 nop + +10000268 : +10000268: b430 push {r4, r5} +1000026a: f04f 0300 mov.w r3, #0 +1000026e: ec43 0044 gpioc_bit_oe_put r0, r3 +10000272: ec43 0040 gpioc_bit_out_put r0, r3 +10000276: 2505 movs r5, #5 +10000278: f44f 7480 mov.w r4, #256 @ 0x100 +1000027c: 4b0b ldr r3, [pc, #44] @ (100002ac ) +1000027e: 00c2 lsls r2, r0, #3 +10000280: f853 1020 ldr.w r1, [r3, r0, lsl #2] +10000284: eb03 0080 add.w r0, r3, r0, lsl #2 +10000288: f081 0140 eor.w r1, r1, #64 @ 0x40 +1000028c: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +10000290: f503 3320 add.w r3, r3, #163840 @ 0x28000 +10000294: f001 02c0 and.w r2, r1, #192 @ 0xc0 +10000298: f500 5180 add.w r1, r0, #4096 @ 0x1000 +1000029c: f500 5040 add.w r0, r0, #12288 @ 0x3000 +100002a0: 600a str r2, [r1, #0] +100002a2: 605d str r5, [r3, #4] +100002a4: 6004 str r4, [r0, #0] +100002a6: bc30 pop {r4, r5} +100002a8: 4770 bx lr +100002aa: bf00 nop +100002ac: 40038004 .word 0x40038004 + +100002b0 : +100002b0: b40f push {r0, r1, r2, r3} +100002b2: b500 push {lr} +100002b4: b083 sub sp, #12 +100002b6: 9c04 ldr r4, [sp, #16] +100002b8: 4807 ldr r0, [pc, #28] @ (100002d8 ) +100002ba: f001 f811 bl 100012e0 <__wrap_puts> +100002be: b13c cbz r4, 100002d0 +100002c0: a905 add r1, sp, #20 +100002c2: 4620 mov r0, r4 +100002c4: 9101 str r1, [sp, #4] +100002c6: f000 fec7 bl 10001058 +100002ca: 4804 ldr r0, [pc, #16] @ (100002dc ) +100002cc: f001 f808 bl 100012e0 <__wrap_puts> +100002d0: 2001 movs r0, #1 +100002d2: f000 fed9 bl 10001088 <_exit> +100002d6: bf00 nop +100002d8: 100014bc .word 0x100014bc +100002dc: 100014cc .word 0x100014cc + +100002e0 : +100002e0: b570 push {r4, r5, r6, lr} +100002e2: 4686 mov lr, r0 +100002e4: f3ef 8510 mrs r5, PRIMASK +100002e8: b672 cpsid i +100002ea: 4c12 ldr r4, [pc, #72] @ (10000334 ) +100002ec: e8d4 6fcf ldaexb r6, [r4] +100002f0: 2001 movs r0, #1 +100002f2: 2e00 cmp r6, #0 +100002f4: d1fa bne.n 100002ec +100002f6: e8c4 0f46 strexb r6, r0, [r4] +100002fa: 2e00 cmp r6, #0 +100002fc: d1f6 bne.n 100002ec +100002fe: f3bf 8f5f dmb sy +10000302: f04f 0c01 mov.w ip, #1 +10000306: 08c8 lsrs r0, r1, #3 +10000308: f001 0307 and.w r3, r1, #7 +1000030c: fa0c f303 lsl.w r3, ip, r3 +10000310: f81e c000 ldrb.w ip, [lr, r0] +10000314: ea1c 0603 ands.w r6, ip, r3 +10000318: d108 bne.n 1000032c +1000031a: ea4c 0c03 orr.w ip, ip, r3 +1000031e: f80e c000 strb.w ip, [lr, r0] +10000322: e8c4 6f8f stlb r6, [r4] +10000326: f385 8810 msr PRIMASK, r5 +1000032a: bd70 pop {r4, r5, r6, pc} +1000032c: 4610 mov r0, r2 +1000032e: f7ff ffbf bl 100002b0 +10000332: bf00 nop +10000334: 200003db .word 0x200003db + +10000338 : +10000338: 4a04 ldr r2, [pc, #16] @ (1000034c ) +1000033a: 7810 ldrb r0, [r2, #0] +1000033c: 1c43 adds r3, r0, #1 +1000033e: b2db uxtb r3, r3 +10000340: 2b18 cmp r3, #24 +10000342: bf28 it cs +10000344: 2310 movcs r3, #16 +10000346: 7013 strb r3, [r2, #0] +10000348: 4770 bx lr +1000034a: bf00 nop +1000034c: 20000228 .word 0x20000228 + +10000350 : +10000350: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000354: 6893 ldr r3, [r2, #8] +10000356: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000035a: 6093 str r3, [r2, #8] +1000035c: 4770 bx lr +1000035e: bf00 nop + +10000360 : +10000360: 2100 movs r1, #0 +10000362: 4b04 ldr r3, [pc, #16] @ (10000374 ) +10000364: f103 0220 add.w r2, r3, #32 +10000368: e8c3 1f8f stlb r1, [r3] +1000036c: 3301 adds r3, #1 +1000036e: 4293 cmp r3, r2 +10000370: d1fa bne.n 10000368 +10000372: 4770 bx lr +10000374: 200003d0 .word 0x200003d0 + +10000378 : +10000378: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000037c: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000380: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000384: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000388: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +1000038c: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000390: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000394: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000398: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +1000039c: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100003a0: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100003a4: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100003a8: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100003ac: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100003b0: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100003b4: b662 cpsie i +100003b6: 4770 bx lr + +100003b8 : +100003b8: 2301 movs r3, #1 +100003ba: f000 021f and.w r2, r0, #31 +100003be: 4093 lsls r3, r2 +100003c0: 0940 lsrs r0, r0, #5 +100003c2: b141 cbz r1, 100003d6 +100003c4: 0080 lsls r0, r0, #2 +100003c6: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003ca: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003ce: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003d2: 6003 str r3, [r0, #0] +100003d4: 4770 bx lr +100003d6: 4a02 ldr r2, [pc, #8] @ (100003e0 ) +100003d8: 3020 adds r0, #32 +100003da: f842 3020 str.w r3, [r2, r0, lsl #2] +100003de: 4770 bx lr +100003e0: e000e100 .word 0xe000e100 + +100003e4 : +100003e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100003e6: 460d mov r5, r1 +100003e8: f3ef 8710 mrs r7, PRIMASK +100003ec: b672 cpsid i +100003ee: 4e12 ldr r6, [pc, #72] @ (10000438 ) +100003f0: e8d6 2fcf ldaexb r2, [r6] +100003f4: 2301 movs r3, #1 +100003f6: 2a00 cmp r2, #0 +100003f8: d1fa bne.n 100003f0 +100003fa: e8c6 3f42 strexb r2, r3, [r6] +100003fe: 2a00 cmp r2, #0 +10000400: d1f6 bne.n 100003f0 +10000402: f3bf 8f5f dmb sy +10000406: 4b0d ldr r3, [pc, #52] @ (1000043c ) +10000408: f100 0410 add.w r4, r0, #16 +1000040c: 689b ldr r3, [r3, #8] +1000040e: 4a0c ldr r2, [pc, #48] @ (10000440 ) +10000410: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000414: 4293 cmp r3, r2 +10000416: d003 beq.n 10000420 +10000418: 4299 cmp r1, r3 +1000041a: d001 beq.n 10000420 +1000041c: f000 fd04 bl 10000e28 +10000420: 4b06 ldr r3, [pc, #24] @ (1000043c ) +10000422: 689b ldr r3, [r3, #8] +10000424: f843 5024 str.w r5, [r3, r4, lsl #2] +10000428: f3bf 8f5f dmb sy +1000042c: 2300 movs r3, #0 +1000042e: e8c6 3f8f stlb r3, [r6] +10000432: f387 8810 msr PRIMASK, r7 +10000436: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000438: 200003d9 .word 0x200003d9 +1000043c: e000ed00 .word 0xe000ed00 +10000440: 10000111 .word 0x10000111 + +10000444 : +10000444: 4b01 ldr r3, [pc, #4] @ (1000044c ) +10000446: 440b add r3, r1 +10000448: 6003 str r3, [r0, #0] +1000044a: 4770 bx lr +1000044c: 200003d0 .word 0x200003d0 + +10000450 : +10000450: b570 push {r4, r5, r6, lr} +10000452: 4c10 ldr r4, [pc, #64] @ (10000494 ) +10000454: 4d10 ldr r5, [pc, #64] @ (10000498 ) +10000456: 42ac cmp r4, r5 +10000458: d20e bcs.n 10000478 +1000045a: 26ff movs r6, #255 @ 0xff +1000045c: 6823 ldr r3, [r4, #0] +1000045e: b163 cbz r3, 1000047a +10000460: f7ff ff6a bl 10000338 +10000464: 4601 mov r1, r0 +10000466: 4620 mov r0, r4 +10000468: f7ff ffec bl 10000444 +1000046c: 80a6 strh r6, [r4, #4] +1000046e: f3bf 8f5f dmb sy +10000472: 3408 adds r4, #8 +10000474: 42ac cmp r4, r5 +10000476: d3f1 bcc.n 1000045c +10000478: bd70 pop {r4, r5, r6, pc} +1000047a: f7ff ff5d bl 10000338 +1000047e: 4601 mov r1, r0 +10000480: 4620 mov r0, r4 +10000482: f7ff ffdf bl 10000444 +10000486: 7126 strb r6, [r4, #4] +10000488: f3bf 8f5f dmb sy +1000048c: 3408 adds r4, #8 +1000048e: 42ac cmp r4, r5 +10000490: d3e4 bcc.n 1000045c +10000492: bd70 pop {r4, r5, r6, pc} +10000494: 20000244 .word 0x20000244 +10000498: 2000024c .word 0x2000024c + +1000049c : +1000049c: 4b0d ldr r3, [pc, #52] @ (100004d4 ) +1000049e: 681a ldr r2, [r3, #0] +100004a0: f3ef 8110 mrs r1, PRIMASK +100004a4: b672 cpsid i +100004a6: e8d2 cfcf ldaexb ip, [r2] +100004aa: 2001 movs r0, #1 +100004ac: f1bc 0f00 cmp.w ip, #0 +100004b0: d1f9 bne.n 100004a6 +100004b2: e8c2 0f4c strexb ip, r0, [r2] +100004b6: f1bc 0f00 cmp.w ip, #0 +100004ba: d1f4 bne.n 100004a6 +100004bc: f3bf 8f5f dmb sy +100004c0: 2200 movs r2, #0 +100004c2: 681b ldr r3, [r3, #0] +100004c4: e8c3 2f8f stlb r2, [r3] +100004c8: f381 8810 msr PRIMASK, r1 +100004cc: bf40 sev +100004ce: 2000 movs r0, #0 +100004d0: 2100 movs r1, #0 +100004d2: 4770 bx lr +100004d4: 20000460 .word 0x20000460 + +100004d8 : +100004d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004dc: ed2d 8b02 vpush {d8} +100004e0: b085 sub sp, #20 +100004e2: f3ef 8305 mrs r3, IPSR +100004e6: b2db uxtb r3, r3 +100004e8: 3b10 subs r3, #16 +100004ea: 089a lsrs r2, r3, #2 +100004ec: bf18 it ne +100004ee: 2201 movne r2, #1 +100004f0: f04f 0101 mov.w r1, #1 +100004f4: f003 0b03 and.w fp, r3, #3 +100004f8: bf18 it ne +100004fa: 4daf ldrne r5, [pc, #700] @ (100007b8 ) +100004fc: 4baf ldr r3, [pc, #700] @ (100007bc ) +100004fe: bf08 it eq +10000500: 4daf ldreq r5, [pc, #700] @ (100007c0 ) +10000502: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000506: f853 6022 ldr.w r6, [r3, r2, lsl #2] +1000050a: fa01 f20b lsl.w r2, r1, fp +1000050e: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000512: ed9f 8ba7 vldr d8, [pc, #668] @ 100007b0 +10000516: 9201 str r2, [sp, #4] +10000518: 605a str r2, [r3, #4] +1000051a: e02f b.n 1000057c +1000051c: 88b3 ldrh r3, [r6, #4] +1000051e: 041c lsls r4, r3, #16 +10000520: f140 8093 bpl.w 1000064a +10000524: 79b3 ldrb r3, [r6, #6] +10000526: 2b00 cmp r3, #0 +10000528: f040 80dd bne.w 100006e6 +1000052c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000530: 2a00 cmp r2, #0 +10000532: f2c0 811e blt.w 10000772 +10000536: 6973 ldr r3, [r6, #20] +10000538: eb02 0242 add.w r2, r2, r2, lsl #1 +1000053c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000540: e9d3 4702 ldrd r4, r7, [r3, #8] +10000544: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000548: bf08 it eq +1000054a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +1000054e: d00e beq.n 1000056e +10000550: eb05 018b add.w r1, r5, fp, lsl #2 +10000554: 6aab ldr r3, [r5, #40] @ 0x28 +10000556: 690a ldr r2, [r1, #16] +10000558: 1ad2 subs r2, r2, r3 +1000055a: 1ae3 subs r3, r4, r3 +1000055c: 4293 cmp r3, r2 +1000055e: d305 bcc.n 1000056c +10000560: 2301 movs r3, #1 +10000562: 6a2a ldr r2, [r5, #32] +10000564: fa03 f30b lsl.w r3, r3, fp +10000568: 4213 tst r3, r2 +1000056a: d100 bne.n 1000056e +1000056c: 610c str r4, [r1, #16] +1000056e: 4628 mov r0, r5 +10000570: f000 fb38 bl 10000be4 +10000574: 42a0 cmp r0, r4 +10000576: 41b9 sbcs r1, r7 +10000578: f2c0 80fb blt.w 10000772 +1000057c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000580: 9a01 ldr r2, [sp, #4] +10000582: 2b00 cmp r3, #0 +10000584: 9300 str r3, [sp, #0] +10000586: 63ea str r2, [r5, #60] @ 0x3c +10000588: dbc8 blt.n 1000051c +1000058a: f8d6 8014 ldr.w r8, [r6, #20] +1000058e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000592: 4628 mov r0, r5 +10000594: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000598: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000059c: f000 fb22 bl 10000be4 +100005a0: 42a0 cmp r0, r4 +100005a2: eb71 010a sbcs.w r1, r1, sl +100005a6: dbb9 blt.n 1000051c +100005a8: f1ba 0f00 cmp.w sl, #0 +100005ac: f2c0 80c3 blt.w 10000736 +100005b0: e9d7 3104 ldrd r3, r1, [r7, #16] +100005b4: 4a83 ldr r2, [pc, #524] @ (100007c4 ) +100005b6: 4293 cmp r3, r2 +100005b8: f000 80ed beq.w 10000796 +100005bc: 887a ldrh r2, [r7, #2] +100005be: f9b6 0008 ldrsh.w r0, [r6, #8] +100005c2: b292 uxth r2, r2 +100005c4: ea42 4000 orr.w r0, r2, r0, lsl #16 +100005c8: 4798 blx r3 +100005ca: 4602 mov r2, r0 +100005cc: 460b mov r3, r1 +100005ce: ea52 0103 orrs.w r1, r2, r3 +100005d2: f000 80b0 beq.w 10000736 +100005d6: 2b00 cmp r3, #0 +100005d8: f280 80d1 bge.w 1000077e +100005dc: ebb4 0e02 subs.w lr, r4, r2 +100005e0: eb6a 0a03 sbc.w sl, sl, r3 +100005e4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100005e8: e9c7 ea02 strd lr, sl, [r7, #8] +100005ec: 2b00 cmp r3, #0 +100005ee: db95 blt.n 1000051c +100005f0: 6971 ldr r1, [r6, #20] +100005f2: eb03 0243 add.w r2, r3, r3, lsl #1 +100005f6: eb01 02c2 add.w r2, r1, r2, lsl #3 +100005fa: e9d2 7002 ldrd r7, r0, [r2, #8] +100005fe: 45be cmp lr, r7 +10000600: eb7a 0c00 sbcs.w ip, sl, r0 +10000604: ea4f 0243 mov.w r2, r3, lsl #1 +10000608: db88 blt.n 1000051c +1000060a: 46b4 mov ip, r6 +1000060c: f82c 3f08 strh.w r3, [ip, #8]! +10000610: e006 b.n 10000620 +10000612: eb03 0043 add.w r0, r3, r3, lsl #1 +10000616: eb01 00c0 add.w r0, r1, r0, lsl #3 +1000061a: 005a lsls r2, r3, #1 +1000061c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000620: 45be cmp lr, r7 +10000622: 441a add r2, r3 +10000624: eb7a 0000 sbcs.w r0, sl, r0 +10000628: eb01 04c2 add.w r4, r1, r2, lsl #3 +1000062c: db04 blt.n 10000638 +1000062e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000632: 46a4 mov ip, r4 +10000634: 2b00 cmp r3, #0 +10000636: daec bge.n 10000612 +10000638: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000063c: 9b00 ldr r3, [sp, #0] +1000063e: f8ac 3000 strh.w r3, [ip] +10000642: 88b3 ldrh r3, [r6, #4] +10000644: 041c lsls r4, r3, #16 +10000646: f53f af6d bmi.w 10000524 +1000064a: 6933 ldr r3, [r6, #16] +1000064c: f3ef 8210 mrs r2, PRIMASK +10000650: b672 cpsid i +10000652: e8d3 0fcf ldaexb r0, [r3] +10000656: 2101 movs r1, #1 +10000658: 2800 cmp r0, #0 +1000065a: d1fa bne.n 10000652 +1000065c: e8c3 1f40 strexb r0, r1, [r3] +10000660: 2800 cmp r0, #0 +10000662: d1f6 bne.n 10000652 +10000664: f3bf 8f5f dmb sy +10000668: f64f 74ff movw r4, #65535 @ 0xffff +1000066c: 88b0 ldrh r0, [r6, #4] +1000066e: 2300 movs r3, #0 +10000670: 6931 ldr r1, [r6, #16] +10000672: b200 sxth r0, r0 +10000674: 80b4 strh r4, [r6, #4] +10000676: e8c1 3f8f stlb r3, [r1] +1000067a: f382 8810 msr PRIMASK, r2 +1000067e: 4298 cmp r0, r3 +10000680: f6ff af50 blt.w 10000524 +10000684: 4607 mov r7, r0 +10000686: 46a9 mov r9, r5 +10000688: 6974 ldr r4, [r6, #20] +1000068a: f106 0808 add.w r8, r6, #8 +1000068e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000692: eb04 03ce add.w r3, r4, lr, lsl #3 +10000696: e9d3 5002 ldrd r5, r0, [r3, #8] +1000069a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000069e: 46c4 mov ip, r8 +100006a0: 2b00 cmp r3, #0 +100006a2: db13 blt.n 100006cc +100006a4: 46b2 mov sl, r6 +100006a6: 9700 str r7, [sp, #0] +100006a8: e004 b.n 100006b4 +100006aa: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +100006ae: 4694 mov ip, r2 +100006b0: 2b00 cmp r3, #0 +100006b2: db09 blt.n 100006c8 +100006b4: eb03 0643 add.w r6, r3, r3, lsl #1 +100006b8: eb04 02c6 add.w r2, r4, r6, lsl #3 +100006bc: e9d2 7102 ldrd r7, r1, [r2, #8] +100006c0: 42bd cmp r5, r7 +100006c2: eb70 0101 sbcs.w r1, r0, r1 +100006c6: daf0 bge.n 100006aa +100006c8: 4656 mov r6, sl +100006ca: 9f00 ldr r7, [sp, #0] +100006cc: f8ac 7000 strh.w r7, [ip] +100006d0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100006d4: f824 303e strh.w r3, [r4, lr, lsl #3] +100006d8: 2f00 cmp r7, #0 +100006da: dad8 bge.n 1000068e +100006dc: 79b3 ldrb r3, [r6, #6] +100006de: 464d mov r5, r9 +100006e0: 2b00 cmp r3, #0 +100006e2: f43f af23 beq.w 1000052c +100006e6: 2300 movs r3, #0 +100006e8: 71b3 strb r3, [r6, #6] +100006ea: f9b6 3008 ldrsh.w r3, [r6, #8] +100006ee: f106 0808 add.w r8, r6, #8 +100006f2: 1c58 adds r0, r3, #1 +100006f4: d03d beq.n 10000772 +100006f6: 461a mov r2, r3 +100006f8: 6977 ldr r7, [r6, #20] +100006fa: e003 b.n 10000704 +100006fc: 4680 mov r8, r0 +100006fe: 1c59 adds r1, r3, #1 +10000700: f43f af16 beq.w 10000530 +10000704: eb03 0143 add.w r1, r3, r3, lsl #1 +10000708: eb07 00c1 add.w r0, r7, r1, lsl #3 +1000070c: f8b0 c002 ldrh.w ip, [r0, #2] +10000710: 461c mov r4, r3 +10000712: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000716: 469e mov lr, r3 +10000718: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +1000071c: d0ee beq.n 100006fc +1000071e: 4294 cmp r4, r2 +10000720: ed80 8b02 vstr d8, [r0, #8] +10000724: d005 beq.n 10000732 +10000726: f8a8 3000 strh.w r3, [r8] +1000072a: 8932 ldrh r2, [r6, #8] +1000072c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000730: 8134 strh r4, [r6, #8] +10000732: 4672 mov r2, lr +10000734: e7e3 b.n 100006fe +10000736: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +1000073a: 8133 strh r3, [r6, #8] +1000073c: 6933 ldr r3, [r6, #16] +1000073e: f3ef 8210 mrs r2, PRIMASK +10000742: b672 cpsid i +10000744: e8d3 0fcf ldaexb r0, [r3] +10000748: 2101 movs r1, #1 +1000074a: 2800 cmp r0, #0 +1000074c: d1fa bne.n 10000744 +1000074e: e8c3 1f40 strexb r0, r1, [r3] +10000752: 2800 cmp r0, #0 +10000754: d1f6 bne.n 10000744 +10000756: f3bf 8f5f dmb sy +1000075a: 8873 ldrh r3, [r6, #2] +1000075c: 6931 ldr r1, [r6, #16] +1000075e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000762: 9b00 ldr r3, [sp, #0] +10000764: 8073 strh r3, [r6, #2] +10000766: 2300 movs r3, #0 +10000768: e8c1 3f8f stlb r3, [r1] +1000076c: f382 8810 msr PRIMASK, r2 +10000770: e6d4 b.n 1000051c +10000772: bf40 sev +10000774: b005 add sp, #20 +10000776: ecbd 8b02 vpop {d8} +1000077a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000077e: 4628 mov r0, r5 +10000780: e9cd 2302 strd r2, r3, [sp, #8] +10000784: f000 fa2e bl 10000be4 +10000788: 9a02 ldr r2, [sp, #8] +1000078a: 9b03 ldr r3, [sp, #12] +1000078c: eb10 0e02 adds.w lr, r0, r2 +10000790: eb43 0a01 adc.w sl, r3, r1 +10000794: e726 b.n 100005e4 +10000796: 4608 mov r0, r1 +10000798: 690b ldr r3, [r1, #16] +1000079a: 9102 str r1, [sp, #8] +1000079c: 4798 blx r3 +1000079e: 2800 cmp r0, #0 +100007a0: d0c9 beq.n 10000736 +100007a2: 9902 ldr r1, [sp, #8] +100007a4: e9d1 2300 ldrd r2, r3, [r1] +100007a8: e711 b.n 100005ce +100007aa: bf00 nop +100007ac: f3af 8000 nop.w +100007b0: ffffffff .word 0xffffffff +100007b4: ffffffff .word 0xffffffff +100007b8: 400b8000 .word 0x400b8000 +100007bc: 20000440 .word 0x20000440 +100007c0: 400b0000 .word 0x400b0000 +100007c4: 100004d9 .word 0x100004d9 + +100007c8 : +100007c8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007cc: 4c36 ldr r4, [pc, #216] @ (100008a8 ) +100007ce: 6925 ldr r5, [r4, #16] +100007d0: b12d cbz r5, 100007de +100007d2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007d6: 210a movs r1, #10 +100007d8: 4834 ldr r0, [pc, #208] @ (100008ac ) +100007da: f7ff be33 b.w 10000444 +100007de: f8df 80e4 ldr.w r8, [pc, #228] @ 100008c4 +100007e2: 2103 movs r1, #3 +100007e4: 4640 mov r0, r8 +100007e6: f000 f9eb bl 10000bc0 +100007ea: 2603 movs r6, #3 +100007ec: f8c4 800c str.w r8, [r4, #12] +100007f0: f7ff fda2 bl 10000338 +100007f4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +100007f8: 4b2d ldr r3, [pc, #180] @ (100008b0 ) +100007fa: 7026 strb r6, [r4, #0] +100007fc: 4403 add r3, r0 +100007fe: 6123 str r3, [r4, #16] +10000800: f8dc 3000 ldr.w r3, [ip] +10000804: 210f movs r1, #15 +10000806: 7063 strb r3, [r4, #1] +10000808: 6963 ldr r3, [r4, #20] +1000080a: 8061 strh r1, [r4, #2] +1000080c: 831d strh r5, [r3, #24] +1000080e: f04f 0504 mov.w r5, #4 +10000812: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000816: f04f 0505 mov.w r5, #5 +1000081a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +1000081e: f04f 0506 mov.w r5, #6 +10000822: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000826: f04f 0507 mov.w r5, #7 +1000082a: 210e movs r1, #14 +1000082c: f64f 72ff movw r2, #65535 @ 0xffff +10000830: 2708 movs r7, #8 +10000832: f04f 0e0a mov.w lr, #10 +10000836: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +1000083a: f04f 0901 mov.w r9, #1 +1000083e: f04f 0c0c mov.w ip, #12 +10000842: f04f 0b02 mov.w fp, #2 +10000846: f04f 0a09 mov.w sl, #9 +1000084a: 200d movs r0, #13 +1000084c: f04f 050b mov.w r5, #11 +10000850: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000854: 4917 ldr r1, [pc, #92] @ (100008b4 ) +10000856: 80a2 strh r2, [r4, #4] +10000858: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +1000085c: 60a1 str r1, [r4, #8] +1000085e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000862: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000866: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +1000086a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +1000086e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000872: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000876: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +1000087a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +1000087e: 801a strh r2, [r3, #0] +10000880: 4b0d ldr r3, [pc, #52] @ (100008b8 ) +10000882: 4630 mov r0, r6 +10000884: f8c8 7020 str.w r7, [r8, #32] +10000888: 490c ldr r1, [pc, #48] @ (100008bc ) +1000088a: 60dc str r4, [r3, #12] +1000088c: f7ff fdaa bl 100003e4 +10000890: 4649 mov r1, r9 +10000892: 4630 mov r0, r6 +10000894: f7ff fd90 bl 100003b8 +10000898: 4b09 ldr r3, [pc, #36] @ (100008c0 ) +1000089a: 210a movs r1, #10 +1000089c: 641f str r7, [r3, #64] @ 0x40 +1000089e: 4803 ldr r0, [pc, #12] @ (100008ac ) +100008a0: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100008a4: f7ff bdce b.w 10000444 +100008a8: 2000022c .word 0x2000022c +100008ac: 20000460 .word 0x20000460 +100008b0: 200003d0 .word 0x200003d0 +100008b4: 0010ffff .word 0x0010ffff +100008b8: 20000440 .word 0x20000440 +100008bc: 100004d9 .word 0x100004d9 +100008c0: 400b2000 .word 0x400b2000 +100008c4: 400b0000 .word 0x400b0000 + +100008c8 : +100008c8: 4601 mov r1, r0 +100008ca: b5f0 push {r4, r5, r6, r7, lr} +100008cc: 6900 ldr r0, [r0, #16] +100008ce: f3ef 8710 mrs r7, PRIMASK +100008d2: b672 cpsid i +100008d4: e8d0 5fcf ldaexb r5, [r0] +100008d8: 2401 movs r4, #1 +100008da: 2d00 cmp r5, #0 +100008dc: d1fa bne.n 100008d4 +100008de: e8c0 4f45 strexb r5, r4, [r0] +100008e2: 2d00 cmp r5, #0 +100008e4: d1f6 bne.n 100008d4 +100008e6: f3bf 8f5f dmb sy +100008ea: f9b1 e002 ldrsh.w lr, [r1, #2] +100008ee: 694c ldr r4, [r1, #20] +100008f0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +100008f4: f1be 0f00 cmp.w lr, #0 +100008f8: ea4f 05cc mov.w r5, ip, lsl #3 +100008fc: 6908 ldr r0, [r1, #16] +100008fe: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000902: db3c blt.n 1000097e +10000904: 5b66 ldrh r6, [r4, r5] +10000906: 804e strh r6, [r1, #2] +10000908: 2600 movs r6, #0 +1000090a: e8c0 6f8f stlb r6, [r0] +1000090e: f387 8810 msr PRIMASK, r7 +10000912: f8bc 0002 ldrh.w r0, [ip, #2] +10000916: e9cc 2302 strd r2, r3, [ip, #8] +1000091a: 3001 adds r0, #1 +1000091c: f3c0 000e ubfx r0, r0, #0, #15 +10000920: 2801 cmp r0, #1 +10000922: bf38 it cc +10000924: 2001 movcc r0, #1 +10000926: 9b05 ldr r3, [sp, #20] +10000928: f8ac 0002 strh.w r0, [ip, #2] +1000092c: f8cc 3010 str.w r3, [ip, #16] +10000930: 9b06 ldr r3, [sp, #24] +10000932: ea40 400e orr.w r0, r0, lr, lsl #16 +10000936: f8cc 3014 str.w r3, [ip, #20] +1000093a: 690b ldr r3, [r1, #16] +1000093c: f3ef 8210 mrs r2, PRIMASK +10000940: b672 cpsid i +10000942: e8d3 cfcf ldaexb ip, [r3] +10000946: 2701 movs r7, #1 +10000948: f1bc 0f00 cmp.w ip, #0 +1000094c: d1f9 bne.n 10000942 +1000094e: e8c3 7f4c strexb ip, r7, [r3] +10000952: f1bc 0f00 cmp.w ip, #0 +10000956: d1f4 bne.n 10000942 +10000958: f3bf 8f5f dmb sy +1000095c: 888b ldrh r3, [r1, #4] +1000095e: 5363 strh r3, [r4, r5] +10000960: f8a1 e004 strh.w lr, [r1, #4] +10000964: 690b ldr r3, [r1, #16] +10000966: e8c3 6f8f stlb r6, [r3] +1000096a: f382 8810 msr PRIMASK, r2 +1000096e: 2201 movs r2, #1 +10000970: 68cb ldr r3, [r1, #12] +10000972: 7809 ldrb r1, [r1, #0] +10000974: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000978: 408a lsls r2, r1 +1000097a: 605a str r2, [r3, #4] +1000097c: bdf0 pop {r4, r5, r6, r7, pc} +1000097e: 2300 movs r3, #0 +10000980: e8c0 3f8f stlb r3, [r0] +10000984: f387 8810 msr PRIMASK, r7 +10000988: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000098c: bdf0 pop {r4, r5, r6, r7, pc} +1000098e: bf00 nop + +10000990 : +10000990: 4603 mov r3, r0 +10000992: 8940 ldrh r0, [r0, #10] +10000994: ebb0 4f21 cmp.w r0, r1, asr #16 +10000998: dd37 ble.n 10000a0a +1000099a: 6958 ldr r0, [r3, #20] +1000099c: 140a asrs r2, r1, #16 +1000099e: eb02 0242 add.w r2, r2, r2, lsl #1 +100009a2: b510 push {r4, lr} +100009a4: eb00 00c2 add.w r0, r0, r2, lsl #3 +100009a8: 691c ldr r4, [r3, #16] +100009aa: f3ef 8c10 mrs ip, PRIMASK +100009ae: b672 cpsid i +100009b0: e8d4 efcf ldaexb lr, [r4] +100009b4: 2201 movs r2, #1 +100009b6: f1be 0f00 cmp.w lr, #0 +100009ba: d1f9 bne.n 100009b0 +100009bc: e8c4 2f4e strexb lr, r2, [r4] +100009c0: f1be 0f00 cmp.w lr, #0 +100009c4: d1f4 bne.n 100009b0 +100009c6: f3bf 8f5f dmb sy +100009ca: 8842 ldrh r2, [r0, #2] +100009cc: b289 uxth r1, r1 +100009ce: b292 uxth r2, r2 +100009d0: 428a cmp r2, r1 +100009d2: d007 beq.n 100009e4 +100009d4: 2200 movs r2, #0 +100009d6: 691b ldr r3, [r3, #16] +100009d8: e8c3 2f8f stlb r2, [r3] +100009dc: f38c 8810 msr PRIMASK, ip +100009e0: 2000 movs r0, #0 +100009e2: bd10 pop {r4, pc} +100009e4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +100009e8: 8042 strh r2, [r0, #2] +100009ea: 2101 movs r1, #1 +100009ec: 2200 movs r2, #0 +100009ee: 6918 ldr r0, [r3, #16] +100009f0: 7199 strb r1, [r3, #6] +100009f2: e8c0 2f8f stlb r2, [r0] +100009f6: f38c 8810 msr PRIMASK, ip +100009fa: 781c ldrb r4, [r3, #0] +100009fc: 68da ldr r2, [r3, #12] +100009fe: 4608 mov r0, r1 +10000a00: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000a04: 40a1 lsls r1, r4 +10000a06: 6059 str r1, [r3, #4] +10000a08: bd10 pop {r4, pc} +10000a0a: 2000 movs r0, #0 +10000a0c: 4770 bx lr +10000a0e: bf00 nop + +10000a10 : +10000a10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000a14: b082 sub sp, #8 +10000a16: 4606 mov r6, r0 +10000a18: f000 f8ec bl 10000bf4 +10000a1c: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000a20: 4604 mov r4, r0 +10000a22: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000a26: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000a2a: fbe6 4103 umlal r4, r1, r6, r3 +10000a2e: 42a0 cmp r0, r4 +10000a30: eb72 0301 sbcs.w r3, r2, r1 +10000a34: bf3a itte cc +10000a36: 4604 movcc r4, r0 +10000a38: 4615 movcc r5, r2 +10000a3a: 460d movcs r5, r1 +10000a3c: 1fa6 subs r6, r4, #6 +10000a3e: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000a42: 42b4 cmp r4, r6 +10000a44: eb75 0307 sbcs.w r3, r5, r7 +10000a48: bf3c itt cc +10000a4a: 2600 movcc r6, #0 +10000a4c: 4637 movcc r7, r6 +10000a4e: f000 f8d1 bl 10000bf4 +10000a52: 1a30 subs r0, r6, r0 +10000a54: eb67 0101 sbc.w r1, r7, r1 +10000a58: 2801 cmp r0, #1 +10000a5a: f171 0100 sbcs.w r1, r1, #0 +10000a5e: da06 bge.n 10000a6e +10000a60: 4620 mov r0, r4 +10000a62: 4629 mov r1, r5 +10000a64: b002 add sp, #8 +10000a66: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000a6a: f000 b8cd b.w 10000c08 +10000a6e: f000 f8c1 bl 10000bf4 +10000a72: 4286 cmp r6, r0 +10000a74: eb67 0101 sbc.w r1, r7, r1 +10000a78: 2900 cmp r1, #0 +10000a7a: db0a blt.n 10000a92 +10000a7c: 2100 movs r1, #0 +10000a7e: 4b17 ldr r3, [pc, #92] @ (10000adc ) +10000a80: 4632 mov r2, r6 +10000a82: 9300 str r3, [sp, #0] +10000a84: 4816 ldr r0, [pc, #88] @ (10000ae0 ) +10000a86: 463b mov r3, r7 +10000a88: 9101 str r1, [sp, #4] +10000a8a: f7ff ff1d bl 100008c8 +10000a8e: 3001 adds r0, #1 +10000a90: d0e6 beq.n 10000a60 +10000a92: f04f 0c00 mov.w ip, #0 +10000a96: 4a13 ldr r2, [pc, #76] @ (10000ae4 ) +10000a98: 4913 ldr r1, [pc, #76] @ (10000ae8 ) +10000a9a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000a9c: 429f cmp r7, r3 +10000a9e: d804 bhi.n 10000aaa +10000aa0: 6a90 ldr r0, [r2, #40] @ 0x28 +10000aa2: 42b0 cmp r0, r6 +10000aa4: d2dc bcs.n 10000a60 +10000aa6: 429f cmp r7, r3 +10000aa8: d1da bne.n 10000a60 +10000aaa: 680b ldr r3, [r1, #0] +10000aac: f3ef 8010 mrs r0, PRIMASK +10000ab0: b672 cpsid i +10000ab2: e8d3 8fcf ldaexb r8, [r3] +10000ab6: f05f 0e01 movs.w lr, #1 +10000aba: f1b8 0f00 cmp.w r8, #0 +10000abe: d1f8 bne.n 10000ab2 +10000ac0: e8c3 ef48 strexb r8, lr, [r3] +10000ac4: f1b8 0f00 cmp.w r8, #0 +10000ac8: d1f3 bne.n 10000ab2 +10000aca: f3bf 8f5f dmb sy +10000ace: 680b ldr r3, [r1, #0] +10000ad0: e8c3 cf8f stlb ip, [r3] +10000ad4: f380 8810 msr PRIMASK, r0 +10000ad8: bf20 wfe +10000ada: e7de b.n 10000a9a +10000adc: 1000049d .word 0x1000049d +10000ae0: 2000022c .word 0x2000022c +10000ae4: 400b0000 .word 0x400b0000 +10000ae8: 20000460 .word 0x20000460 + +10000aec : +10000aec: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000af0: 4606 mov r6, r0 +10000af2: 460d mov r5, r1 +10000af4: b083 sub sp, #12 +10000af6: f3ef 8405 mrs r4, IPSR +10000afa: b2e4 uxtb r4, r4 +10000afc: b13c cbz r4, 10000b0e +10000afe: 4b2d ldr r3, [pc, #180] @ (10000bb4 ) +10000b00: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b02: 42aa cmp r2, r5 +10000b04: d21c bcs.n 10000b40 +10000b06: 2000 movs r0, #0 +10000b08: b003 add sp, #12 +10000b0a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b0e: 4f2a ldr r7, [pc, #168] @ (10000bb8 ) +10000b10: f8d7 900c ldr.w r9, [r7, #12] +10000b14: f897 8000 ldrb.w r8, [r7] +10000b18: 4648 mov r0, r9 +10000b1a: f000 f863 bl 10000be4 +10000b1e: f108 0804 add.w r8, r8, #4 +10000b22: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000b26: 1a1b subs r3, r3, r0 +10000b28: 1a30 subs r0, r6, r0 +10000b2a: eb65 0101 sbc.w r1, r5, r1 +10000b2e: 4298 cmp r0, r3 +10000b30: f171 0100 sbcs.w r1, r1, #0 +10000b34: db10 blt.n 10000b58 +10000b36: bf20 wfe +10000b38: 4b1e ldr r3, [pc, #120] @ (10000bb4 ) +10000b3a: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b3c: 42aa cmp r2, r5 +10000b3e: d3e2 bcc.n 10000b06 +10000b40: bf14 ite ne +10000b42: 2401 movne r4, #1 +10000b44: 2400 moveq r4, #0 +10000b46: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b48: 42b3 cmp r3, r6 +10000b4a: bf34 ite cc +10000b4c: 4620 movcc r0, r4 +10000b4e: f044 0001 orrcs.w r0, r4, #1 +10000b52: b003 add sp, #12 +10000b54: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b58: f000 f84c bl 10000bf4 +10000b5c: 4286 cmp r6, r0 +10000b5e: eb65 0101 sbc.w r1, r5, r1 +10000b62: 2900 cmp r1, #0 +10000b64: db14 blt.n 10000b90 +10000b66: 4b15 ldr r3, [pc, #84] @ (10000bbc ) +10000b68: 4638 mov r0, r7 +10000b6a: e9cd 3400 strd r3, r4, [sp] +10000b6e: 4632 mov r2, r6 +10000b70: 462b mov r3, r5 +10000b72: f7ff fea9 bl 100008c8 +10000b76: 1e01 subs r1, r0, #0 +10000b78: dd0a ble.n 10000b90 +10000b7a: 4b0e ldr r3, [pc, #56] @ (10000bb4 ) +10000b7c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b7e: 42aa cmp r2, r5 +10000b80: d316 bcc.n 10000bb0 +10000b82: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b84: 42b3 cmp r3, r6 +10000b86: d311 bcc.n 10000bac +10000b88: 480b ldr r0, [pc, #44] @ (10000bb8 ) +10000b8a: f7ff ff01 bl 10000990 +10000b8e: e7b6 b.n 10000afe +10000b90: 4b08 ldr r3, [pc, #32] @ (10000bb4 ) +10000b92: 6a5c ldr r4, [r3, #36] @ 0x24 +10000b94: 42ac cmp r4, r5 +10000b96: d3b6 bcc.n 10000b06 +10000b98: 1b64 subs r4, r4, r5 +10000b9a: bf18 it ne +10000b9c: 2401 movne r4, #1 +10000b9e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000ba0: 42b3 cmp r3, r6 +10000ba2: bf34 ite cc +10000ba4: 4620 movcc r0, r4 +10000ba6: f044 0001 orrcs.w r0, r4, #1 +10000baa: e7ad b.n 10000b08 +10000bac: 42aa cmp r2, r5 +10000bae: d1eb bne.n 10000b88 +10000bb0: bf20 wfe +10000bb2: e7e9 b.n 10000b88 +10000bb4: 400b0000 .word 0x400b0000 +10000bb8: 2000022c .word 0x2000022c +10000bbc: 1000049d .word 0x1000049d + +10000bc0 : +10000bc0: b410 push {r4} +10000bc2: 4b05 ldr r3, [pc, #20] @ (10000bd8 ) +10000bc4: 4c05 ldr r4, [pc, #20] @ (10000bdc ) +10000bc6: 4a06 ldr r2, [pc, #24] @ (10000be0 ) +10000bc8: 42a0 cmp r0, r4 +10000bca: bf14 ite ne +10000bcc: 4618 movne r0, r3 +10000bce: 1c58 addeq r0, r3, #1 +10000bd0: f85d 4b04 ldr.w r4, [sp], #4 +10000bd4: f7ff bb84 b.w 100002e0 +10000bd8: 200003f0 .word 0x200003f0 +10000bdc: 400b8000 .word 0x400b8000 +10000be0: 100014d0 .word 0x100014d0 + +10000be4 : +10000be4: 4603 mov r3, r0 +10000be6: 6a41 ldr r1, [r0, #36] @ 0x24 +10000be8: 460a mov r2, r1 +10000bea: 6a98 ldr r0, [r3, #40] @ 0x28 +10000bec: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bee: 428a cmp r2, r1 +10000bf0: d1fa bne.n 10000be8 +10000bf2: 4770 bx lr + +10000bf4 : +10000bf4: 4b03 ldr r3, [pc, #12] @ (10000c04 ) +10000bf6: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bf8: 460a mov r2, r1 +10000bfa: 6a98 ldr r0, [r3, #40] @ 0x28 +10000bfc: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bfe: 4291 cmp r1, r2 +10000c00: d1fa bne.n 10000bf8 +10000c02: 4770 bx lr +10000c04: 400b0000 .word 0x400b0000 + +10000c08 : +10000c08: 4a07 ldr r2, [pc, #28] @ (10000c28 ) +10000c0a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000c0c: 4299 cmp r1, r3 +10000c0e: d8fc bhi.n 10000c0a +10000c10: 4299 cmp r1, r3 +10000c12: d107 bne.n 10000c24 +10000c14: 4b04 ldr r3, [pc, #16] @ (10000c28 ) +10000c16: e002 b.n 10000c1e +10000c18: 6a5a ldr r2, [r3, #36] @ 0x24 +10000c1a: 4291 cmp r1, r2 +10000c1c: d102 bne.n 10000c24 +10000c1e: 6a9a ldr r2, [r3, #40] @ 0x28 +10000c20: 4290 cmp r0, r2 +10000c22: d8f9 bhi.n 10000c18 +10000c24: 4770 bx lr +10000c26: bf00 nop +10000c28: 400b0000 .word 0x400b0000 + +10000c2c : +10000c2c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000c30: ea4f 0c8c mov.w ip, ip, lsl #2 +10000c34: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000c38: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000c3c: b5f0 push {r4, r5, r6, r7, lr} +10000c3e: 4616 mov r6, r2 +10000c40: f8dc 2004 ldr.w r2, [ip, #4] +10000c44: 1f05 subs r5, r0, #4 +10000c46: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000c4a: bf38 it cc +10000c4c: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000c50: b2ed uxtb r5, r5 +10000c52: bf38 it cc +10000c54: f8cc 2004 strcc.w r2, [ip, #4] +10000c58: 2d01 cmp r5, #1 +10000c5a: d92a bls.n 10000cb2 +10000c5c: f44f 6700 mov.w r7, #2048 @ 0x800 +10000c60: 4c25 ldr r4, [pc, #148] @ (10000cf8 ) +10000c62: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000c66: 6017 str r7, [r2, #0] +10000c68: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000c6c: b9b2 cbnz r2, 10000c9c +10000c6e: f8dc 2000 ldr.w r2, [ip] +10000c72: 2d01 cmp r5, #1 +10000c74: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000c78: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000c7c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000c80: 6032 str r2, [r6, #0] +10000c82: d92a bls.n 10000cda +10000c84: f44f 6100 mov.w r1, #2048 @ 0x800 +10000c88: f844 3020 str.w r3, [r4, r0, lsl #2] +10000c8c: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000c90: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000c94: 6011 str r1, [r2, #0] +10000c96: f8cc 3004 str.w r3, [ip, #4] +10000c9a: bdf0 pop {r4, r5, r6, r7, pc} +10000c9c: 6967 ldr r7, [r4, #20] +10000c9e: fbb7 fef2 udiv lr, r7, r2 +10000ca2: f10e 0e01 add.w lr, lr, #1 +10000ca6: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000caa: f1be 0e03 subs.w lr, lr, #3 +10000cae: d2fc bcs.n 10000caa +10000cb0: e7dd b.n 10000c6e +10000cb2: 2901 cmp r1, #1 +10000cb4: d1d2 bne.n 10000c5c +10000cb6: 2403 movs r4, #3 +10000cb8: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000cbc: 6014 str r4, [r2, #0] +10000cbe: f8dc 2008 ldr.w r2, [ip, #8] +10000cc2: 07d2 lsls r2, r2, #31 +10000cc4: d5fb bpl.n 10000cbe +10000cc6: f8dc 2000 ldr.w r2, [ip] +10000cca: 4c0b ldr r4, [pc, #44] @ (10000cf8 ) +10000ccc: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000cd0: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000cd4: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000cd8: 6032 str r2, [r6, #0] +10000cda: 2201 movs r2, #1 +10000cdc: f8dc 5000 ldr.w r5, [ip] +10000ce0: 404d eors r5, r1 +10000ce2: f005 0503 and.w r5, r5, #3 +10000ce6: 6035 str r5, [r6, #0] +10000ce8: fa02 f101 lsl.w r1, r2, r1 +10000cec: f8dc 2008 ldr.w r2, [ip, #8] +10000cf0: 420a tst r2, r1 +10000cf2: d0fb beq.n 10000cec +10000cf4: e7c6 b.n 10000c84 +10000cf6: bf00 nop +10000cf8: 200003f4 .word 0x200003f4 + +10000cfc : +10000cfc: 4b01 ldr r3, [pc, #4] @ (10000d04 ) +10000cfe: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000d02: 4770 bx lr +10000d04: 200003f4 .word 0x200003f4 + +10000d08 : +10000d08: b470 push {r4, r5, r6} +10000d0a: 9d03 ldr r5, [sp, #12] +10000d0c: 6804 ldr r4, [r0, #0] +10000d0e: 032d lsls r5, r5, #12 +10000d10: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000d14: 4b1b ldr r3, [pc, #108] @ (10000d84 ) +10000d16: 2c00 cmp r4, #0 +10000d18: fbb3 f3f1 udiv r3, r3, r1 +10000d1c: fbb2 f6f3 udiv r6, r2, r3 +10000d20: db1f blt.n 10000d62 +10000d22: 4a19 ldr r2, [pc, #100] @ (10000d88 ) +10000d24: 4b19 ldr r3, [pc, #100] @ (10000d8c ) +10000d26: 4290 cmp r0, r2 +10000d28: bf14 ite ne +10000d2a: f44f 4280 movne.w r2, #16384 @ 0x4000 +10000d2e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10000d32: 4c17 ldr r4, [pc, #92] @ (10000d90 ) +10000d34: 601a str r2, [r3, #0] +10000d36: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000d3a: 601a str r2, [r3, #0] +10000d3c: 68a3 ldr r3, [r4, #8] +10000d3e: ea32 0303 bics.w r3, r2, r3 +10000d42: d1fb bne.n 10000d3c +10000d44: 2221 movs r2, #33 @ 0x21 +10000d46: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10000d4a: 3304 adds r3, #4 +10000d4c: 6001 str r1, [r0, #0] +10000d4e: 6086 str r6, [r0, #8] +10000d50: 601a str r2, [r3, #0] +10000d52: 6802 ldr r2, [r0, #0] +10000d54: 2a00 cmp r2, #0 +10000d56: dafc bge.n 10000d52 +10000d58: 2208 movs r2, #8 +10000d5a: 60c5 str r5, [r0, #12] +10000d5c: 601a str r2, [r3, #0] +10000d5e: bc70 pop {r4, r5, r6} +10000d60: 4770 bx lr +10000d62: 6803 ldr r3, [r0, #0] +10000d64: f003 033f and.w r3, r3, #63 @ 0x3f +10000d68: 428b cmp r3, r1 +10000d6a: d1da bne.n 10000d22 +10000d6c: 6883 ldr r3, [r0, #8] +10000d6e: f3c3 030b ubfx r3, r3, #0, #12 +10000d72: 42b3 cmp r3, r6 +10000d74: d1d5 bne.n 10000d22 +10000d76: 68c3 ldr r3, [r0, #12] +10000d78: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10000d7c: 42ab cmp r3, r5 +10000d7e: d1d0 bne.n 10000d22 +10000d80: e7ed b.n 10000d5e +10000d82: bf00 nop +10000d84: 00b71b00 .word 0x00b71b00 +10000d88: 40058000 .word 0x40058000 +10000d8c: 40022000 .word 0x40022000 +10000d90: 40020000 .word 0x40020000 + +10000d94 : +10000d94: 2301 movs r3, #1 +10000d96: eb00 0040 add.w r0, r0, r0, lsl #1 +10000d9a: 0080 lsls r0, r0, #2 +10000d9c: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000da0: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10000da4: 6041 str r1, [r0, #4] +10000da6: 6003 str r3, [r0, #0] +10000da8: 4770 bx lr +10000daa: bf00 nop + +10000dac : +10000dac: 2300 movs r3, #0 +10000dae: 8adb ldrh r3, [r3, #22] +10000db0: 2200 movs r2, #0 +10000db2: e842 f200 tt r2, r2 +10000db6: 0252 lsls r2, r2, #9 +10000db8: d401 bmi.n 10000dbe +10000dba: 2110 movs r1, #16 +10000dbc: 4718 bx r3 +10000dbe: 2104 movs r1, #4 +10000dc0: 4718 bx r3 +10000dc2: bf00 nop + +10000dc4 : +10000dc4: 4a03 ldr r2, [pc, #12] @ (10000dd4 ) +10000dc6: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10000dca: 2b00 cmp r3, #0 +10000dcc: d0fb beq.n 10000dc6 +10000dce: f3bf 8f5f dmb sy +10000dd2: 4770 bx lr +10000dd4: 400e0000 .word 0x400e0000 + +10000dd8 : +10000dd8: 2100 movs r1, #0 +10000dda: 4b04 ldr r3, [pc, #16] @ (10000dec ) +10000ddc: 4a04 ldr r2, [pc, #16] @ (10000df0 ) +10000dde: f3bf 8f5f dmb sy +10000de2: f843 1b04 str.w r1, [r3], #4 +10000de6: 4293 cmp r3, r2 +10000de8: d1f9 bne.n 10000dde +10000dea: 4770 bx lr +10000dec: 400e080c .word 0x400e080c +10000df0: 400e082c .word 0x400e082c + +10000df4 : +10000df4: b410 push {r4} +10000df6: f44f 708d mov.w r0, #282 @ 0x11a +10000dfa: f44f 642a mov.w r4, #2720 @ 0xaa0 +10000dfe: 4a06 ldr r2, [pc, #24] @ (10000e18 ) +10000e00: 4b06 ldr r3, [pc, #24] @ (10000e1c ) +10000e02: 4907 ldr r1, [pc, #28] @ (10000e20 ) +10000e04: 6014 str r4, [r2, #0] +10000e06: 60d0 str r0, [r2, #12] +10000e08: 6019 str r1, [r3, #0] +10000e0a: 6853 ldr r3, [r2, #4] +10000e0c: 2b00 cmp r3, #0 +10000e0e: dafc bge.n 10000e0a +10000e10: f85d 4b04 ldr.w r4, [sp], #4 +10000e14: 4770 bx lr +10000e16: bf00 nop +10000e18: 40048000 .word 0x40048000 +10000e1c: 4004a000 .word 0x4004a000 +10000e20: 00fab000 .word 0x00fab000 + +10000e24 : +10000e24: 4770 bx lr +10000e26: bf00 nop + +10000e28 : +10000e28: b508 push {r3, lr} +10000e2a: 4801 ldr r0, [pc, #4] @ (10000e30 ) +10000e2c: f7ff fa40 bl 100002b0 +10000e30: 100014f4 .word 0x100014f4 + +10000e34 : +10000e34: b538 push {r3, r4, r5, lr} +10000e36: 4c05 ldr r4, [pc, #20] @ (10000e4c ) +10000e38: 4d05 ldr r5, [pc, #20] @ (10000e50 ) +10000e3a: 42ac cmp r4, r5 +10000e3c: d204 bcs.n 10000e48 +10000e3e: f854 3b04 ldr.w r3, [r4], #4 +10000e42: 4798 blx r3 +10000e44: 42ac cmp r4, r5 +10000e46: d3fa bcc.n 10000e3e +10000e48: bd38 pop {r3, r4, r5, pc} +10000e4a: bf00 nop +10000e4c: 10001478 .word 0x10001478 +10000e50: 100014b8 .word 0x100014b8 + +10000e54 : +10000e54: b410 push {r4} +10000e56: 4807 ldr r0, [pc, #28] @ (10000e74 ) +10000e58: 4c07 ldr r4, [pc, #28] @ (10000e78 ) +10000e5a: 4b08 ldr r3, [pc, #32] @ (10000e7c ) +10000e5c: 4a08 ldr r2, [pc, #32] @ (10000e80 ) +10000e5e: 4909 ldr r1, [pc, #36] @ (10000e84 ) +10000e60: 6004 str r4, [r0, #0] +10000e62: 601a str r2, [r3, #0] +10000e64: 688b ldr r3, [r1, #8] +10000e66: ea32 0303 bics.w r3, r2, r3 +10000e6a: d1fb bne.n 10000e64 +10000e6c: f85d 4b04 ldr.w r4, [sp], #4 +10000e70: 4770 bx lr +10000e72: bf00 nop +10000e74: 40022000 .word 0x40022000 +10000e78: efef3b7f .word 0xefef3b7f +10000e7c: 40023000 .word 0x40023000 +10000e80: 03f3fff6 .word 0x03f3fff6 +10000e84: 40020000 .word 0x40020000 + +10000e88 : +10000e88: 4b04 ldr r3, [pc, #16] @ (10000e9c ) +10000e8a: 6cdb ldr r3, [r3, #76] @ 0x4c +10000e8c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10000e90: d103 bne.n 10000e9a +10000e92: f44f 2280 mov.w r2, #262144 @ 0x40000 +10000e96: 4b02 ldr r3, [pc, #8] @ (10000ea0 ) +10000e98: 64da str r2, [r3, #76] @ 0x4c +10000e9a: 4770 bx lr +10000e9c: 50110000 .word 0x50110000 +10000ea0: 50112000 .word 0x50112000 + +10000ea4 : +10000ea4: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000ea8: 4b04 ldr r3, [pc, #16] @ (10000ebc ) +10000eaa: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10000eae: 430b orrs r3, r1 +10000eb0: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10000eb4: ee10 0430 dcp_rcmp r0 +10000eb8: 4770 bx lr +10000eba: bf00 nop +10000ebc: 00300303 .word 0x00300303 + +10000ec0 : +10000ec0: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10000ec4: 4b04 ldr r3, [pc, #16] @ (10000ed8 ) +10000ec6: 4a05 ldr r2, [pc, #20] @ (10000edc ) +10000ec8: 6019 str r1, [r3, #0] +10000eca: 6893 ldr r3, [r2, #8] +10000ecc: 43db mvns r3, r3 +10000ece: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10000ed2: d1fa bne.n 10000eca +10000ed4: 4770 bx lr +10000ed6: bf00 nop +10000ed8: 40023000 .word 0x40023000 +10000edc: 40020000 .word 0x40020000 + +10000ee0 : +10000ee0: b510 push {r4, lr} +10000ee2: f245 2053 movw r0, #21075 @ 0x5253 +10000ee6: f7ff ff61 bl 10000dac +10000eea: e8bd 4010 ldmia.w sp!, {r4, lr} +10000eee: 4603 mov r3, r0 +10000ef0: 2004 movs r0, #4 +10000ef2: 4718 bx r3 + +10000ef4 : +10000ef4: b510 push {r4, lr} +10000ef6: f245 2053 movw r0, #21075 @ 0x5253 +10000efa: f7ff ff57 bl 10000dac +10000efe: e8bd 4010 ldmia.w sp!, {r4, lr} +10000f02: 4603 mov r3, r0 +10000f04: 2001 movs r0, #1 +10000f06: 4718 bx r3 + +10000f08 : +10000f08: f7ff ba2a b.w 10000360 + +10000f0c : +10000f0c: 4914 ldr r1, [pc, #80] @ (10000f60 ) +10000f0e: 4b15 ldr r3, [pc, #84] @ (10000f64 ) +10000f10: b570 push {r4, r5, r6, lr} +10000f12: 1a5c subs r4, r3, r1 +10000f14: 10a6 asrs r6, r4, #2 +10000f16: 2e44 cmp r6, #68 @ 0x44 +10000f18: 4632 mov r2, r6 +10000f1a: bf28 it cs +10000f1c: 2244 movcs r2, #68 @ 0x44 +10000f1e: 4d12 ldr r5, [pc, #72] @ (10000f68 ) +10000f20: 0092 lsls r2, r2, #2 +10000f22: 4628 mov r0, r5 +10000f24: f000 f9fa bl 1000131c +10000f28: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10000f2c: d813 bhi.n 10000f56 +10000f2e: 4a0f ldr r2, [pc, #60] @ (10000f6c ) +10000f30: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10000f34: d012 beq.n 10000f5c +10000f36: 192b adds r3, r5, r4 +10000f38: 0841 lsrs r1, r0, #1 +10000f3a: eb03 01c1 add.w r1, r3, r1, lsl #3 +10000f3e: e9c3 2200 strd r2, r2, [r3] +10000f42: 3308 adds r3, #8 +10000f44: 428b cmp r3, r1 +10000f46: d1fa bne.n 10000f3e +10000f48: 07c3 lsls r3, r0, #31 +10000f4a: d504 bpl.n 10000f56 +10000f4c: f020 0001 bic.w r0, r0, #1 +10000f50: 4430 add r0, r6 +10000f52: f845 2020 str.w r2, [r5, r0, lsl #2] +10000f56: 4b06 ldr r3, [pc, #24] @ (10000f70 ) +10000f58: 609d str r5, [r3, #8] +10000f5a: bd70 pop {r4, r5, r6, pc} +10000f5c: 2043 movs r0, #67 @ 0x43 +10000f5e: e7f8 b.n 10000f52 +10000f60: 10000000 .word 0x10000000 +10000f64: 10000110 .word 0x10000110 +10000f68: 20000000 .word 0x20000000 +10000f6c: 10000111 .word 0x10000111 +10000f70: e000ed00 .word 0xe000ed00 + +10000f74 : +10000f74: 2300 movs r3, #0 +10000f76: b570 push {r4, r5, r6, lr} +10000f78: 4c2b ldr r4, [pc, #172] @ (10001028 ) +10000f7a: b082 sub sp, #8 +10000f7c: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10000f80: f7ff ff38 bl 10000df4 +10000f84: 2201 movs r2, #1 +10000f86: 4b29 ldr r3, [pc, #164] @ (1000102c ) +10000f88: 63da str r2, [r3, #60] @ 0x3c +10000f8a: 6c63 ldr r3, [r4, #68] @ 0x44 +10000f8c: 2b01 cmp r3, #1 +10000f8e: d1fc bne.n 10000f8a +10000f90: 2103 movs r1, #3 +10000f92: 4a26 ldr r2, [pc, #152] @ (1000102c ) +10000f94: 4b24 ldr r3, [pc, #144] @ (10001028 ) +10000f96: 6311 str r1, [r2, #48] @ 0x30 +10000f98: 6b9c ldr r4, [r3, #56] @ 0x38 +10000f9a: 2c01 cmp r4, #1 +10000f9c: d1fc bne.n 10000f98 +10000f9e: 2602 movs r6, #2 +10000fa0: 2505 movs r5, #5 +10000fa2: 4621 mov r1, r4 +10000fa4: 2305 movs r3, #5 +10000fa6: 4a22 ldr r2, [pc, #136] @ (10001030 ) +10000fa8: 4822 ldr r0, [pc, #136] @ (10001034 ) +10000faa: 9600 str r6, [sp, #0] +10000fac: f7ff feac bl 10000d08 +10000fb0: 4621 mov r1, r4 +10000fb2: 462b mov r3, r5 +10000fb4: 4a20 ldr r2, [pc, #128] @ (10001038 ) +10000fb6: 4821 ldr r0, [pc, #132] @ (1000103c ) +10000fb8: 9500 str r5, [sp, #0] +10000fba: f7ff fea5 bl 10000d08 +10000fbe: 2200 movs r2, #0 +10000fc0: 2004 movs r0, #4 +10000fc2: 4631 mov r1, r6 +10000fc4: 4b1e ldr r3, [pc, #120] @ (10001040 ) +10000fc6: f7ff fe31 bl 10000c2c +10000fca: 4621 mov r1, r4 +10000fcc: 4628 mov r0, r5 +10000fce: 2200 movs r2, #0 +10000fd0: 4b1c ldr r3, [pc, #112] @ (10001044 ) +10000fd2: f7ff fe2b bl 10000c2c +10000fd6: 2200 movs r2, #0 +10000fd8: 2008 movs r0, #8 +10000fda: 4611 mov r1, r2 +10000fdc: 4b1a ldr r3, [pc, #104] @ (10001048 ) +10000fde: f7ff fe25 bl 10000c2c +10000fe2: 2200 movs r2, #0 +10000fe4: 2009 movs r0, #9 +10000fe6: 4611 mov r1, r2 +10000fe8: 4b17 ldr r3, [pc, #92] @ (10001048 ) +10000fea: f7ff fe1f bl 10000c2c +10000fee: 2200 movs r2, #0 +10000ff0: 2006 movs r0, #6 +10000ff2: 4611 mov r1, r2 +10000ff4: 4b13 ldr r3, [pc, #76] @ (10001044 ) +10000ff6: f7ff fe19 bl 10000c2c +10000ffa: 2200 movs r2, #0 +10000ffc: 4b11 ldr r3, [pc, #68] @ (10001044 ) +10000ffe: 2007 movs r0, #7 +10001000: 4611 mov r1, r2 +10001002: f7ff fe13 bl 10000c2c +10001006: 2004 movs r0, #4 +10001008: f7ff fe78 bl 10000cfc +1000100c: 2400 movs r4, #0 +1000100e: 4b0f ldr r3, [pc, #60] @ (1000104c ) +10001010: fba3 3500 umull r3, r5, r3, r0 +10001014: 0cad lsrs r5, r5, #18 +10001016: b2e0 uxtb r0, r4 +10001018: 4629 mov r1, r5 +1000101a: 3401 adds r4, #1 +1000101c: f7ff feba bl 10000d94 +10001020: 2c06 cmp r4, #6 +10001022: d1f8 bne.n 10001016 +10001024: b002 add sp, #8 +10001026: bd70 pop {r4, r5, r6, pc} +10001028: 40010000 .word 0x40010000 +1000102c: 40013000 .word 0x40013000 +10001030: 59682f00 .word 0x59682f00 +10001034: 40050000 .word 0x40050000 +10001038: 47868c00 .word 0x47868c00 +1000103c: 40058000 .word 0x40058000 +10001040: 00b71b00 .word 0x00b71b00 +10001044: 08f0d180 .word 0x08f0d180 +10001048: 02dc6c00 .word 0x02dc6c00 +1000104c: 431bde83 .word 0x431bde83 + +10001050 <_out_char>: +10001050: b900 cbnz r0, 10001054 <_out_char+0x4> +10001052: 4770 bx lr +10001054: f000 b902 b.w 1000125c <__wrap_putchar> + +10001058 : +10001058: b510 push {r4, lr} +1000105a: 4b09 ldr r3, [pc, #36] @ (10001080 ) +1000105c: b084 sub sp, #16 +1000105e: 681c ldr r4, [r3, #0] +10001060: b14c cbz r4, 10001076 +10001062: 4603 mov r3, r0 +10001064: 9100 str r1, [sp, #0] +10001066: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000106a: a903 add r1, sp, #12 +1000106c: 4805 ldr r0, [pc, #20] @ (10001084 ) +1000106e: 47a0 blx r4 +10001070: 2001 movs r0, #1 +10001072: b004 add sp, #16 +10001074: bd10 pop {r4, pc} +10001076: f000 f933 bl 100012e0 <__wrap_puts> +1000107a: 4620 mov r0, r4 +1000107c: b004 add sp, #16 +1000107e: bd10 pop {r4, pc} +10001080: 20000424 .word 0x20000424 +10001084: 10001051 .word 0x10001051 + +10001088 <_exit>: +10001088: be00 bkpt 0x0000 +1000108a: e7fd b.n 10001088 <_exit> + +1000108c : +1000108c: b508 push {r3, lr} +1000108e: f7ff fffb bl 10001088 <_exit> +10001092: bf00 nop + +10001094 : +10001094: b538 push {r3, r4, r5, lr} +10001096: 4c06 ldr r4, [pc, #24] @ (100010b0 ) +10001098: 4d06 ldr r5, [pc, #24] @ (100010b4 ) +1000109a: f7ff fecb bl 10000e34 +1000109e: 42ac cmp r4, r5 +100010a0: d204 bcs.n 100010ac +100010a2: f854 3b04 ldr.w r3, [r4], #4 +100010a6: 4798 blx r3 +100010a8: 42ac cmp r4, r5 +100010aa: d3fa bcc.n 100010a2 +100010ac: bd38 pop {r3, r4, r5, pc} +100010ae: bf00 nop +100010b0: 100014b8 .word 0x100014b8 +100010b4: 100014bc .word 0x100014bc + +100010b8 : +100010b8: 6803 ldr r3, [r0, #0] +100010ba: 4608 mov r0, r1 +100010bc: 4611 mov r1, r2 +100010be: 4718 bx r3 + +100010c0 : +100010c0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100010c4: 4615 mov r5, r2 +100010c6: 7d42 ldrb r2, [r0, #21] +100010c8: 4607 mov r7, r0 +100010ca: 4688 mov r8, r1 +100010cc: 2a00 cmp r2, #0 +100010ce: d046 beq.n 1000115e +100010d0: 2d00 cmp r5, #0 +100010d2: dd1d ble.n 10001110 +100010d4: 780b ldrb r3, [r1, #0] +100010d6: 2b0a cmp r3, #10 +100010d8: d023 beq.n 10001122 +100010da: 2d01 cmp r5, #1 +100010dc: f04f 0c00 mov.w ip, #0 +100010e0: d018 beq.n 10001114 +100010e2: 4646 mov r6, r8 +100010e4: 2401 movs r4, #1 +100010e6: f816 2f01 ldrb.w r2, [r6, #1]! +100010ea: 4621 mov r1, r4 +100010ec: 2a0a cmp r2, #10 +100010ee: f104 0401 add.w r4, r4, #1 +100010f2: d022 beq.n 1000113a +100010f4: 42a5 cmp r5, r4 +100010f6: d1f6 bne.n 100010e6 +100010f8: 4565 cmp r5, ip +100010fa: dc0b bgt.n 10001114 +100010fc: eb08 0305 add.w r3, r8, r5 +10001100: f813 3c01 ldrb.w r3, [r3, #-1] +10001104: f1a3 030d sub.w r3, r3, #13 +10001108: fab3 f383 clz r3, r3 +1000110c: 095b lsrs r3, r3, #5 +1000110e: 753b strb r3, [r7, #20] +10001110: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10001114: 683b ldr r3, [r7, #0] +10001116: eba5 010c sub.w r1, r5, ip +1000111a: eb08 000c add.w r0, r8, ip +1000111e: 4798 blx r3 +10001120: e7ec b.n 100010fc +10001122: 7d03 ldrb r3, [r0, #20] +10001124: 2b00 cmp r3, #0 +10001126: d1d8 bne.n 100010da +10001128: 6803 ldr r3, [r0, #0] +1000112a: 2102 movs r1, #2 +1000112c: 480f ldr r0, [pc, #60] @ (1000116c ) +1000112e: 4798 blx r3 +10001130: 2d01 cmp r5, #1 +10001132: d0e3 beq.n 100010fc +10001134: f04f 0c01 mov.w ip, #1 +10001138: e7d3 b.n 100010e2 +1000113a: f816 3c01 ldrb.w r3, [r6, #-1] +1000113e: 2b0d cmp r3, #13 +10001140: d0d8 beq.n 100010f4 +10001142: 458c cmp ip, r1 +10001144: eb08 000c add.w r0, r8, ip +10001148: eba1 010c sub.w r1, r1, ip +1000114c: da01 bge.n 10001152 +1000114e: 683b ldr r3, [r7, #0] +10001150: 4798 blx r3 +10001152: 2102 movs r1, #2 +10001154: 4805 ldr r0, [pc, #20] @ (1000116c ) +10001156: 683b ldr r3, [r7, #0] +10001158: 4798 blx r3 +1000115a: 46a4 mov ip, r4 +1000115c: e7ca b.n 100010f4 +1000115e: 4629 mov r1, r5 +10001160: 4640 mov r0, r8 +10001162: 683b ldr r3, [r7, #0] +10001164: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001168: 4718 bx r3 +1000116a: bf00 nop +1000116c: 100015bc .word 0x100015bc + +10001170 : +10001170: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10001174: b082 sub sp, #8 +10001176: 460d mov r5, r1 +10001178: 4691 mov r9, r2 +1000117a: 461c mov r4, r3 +1000117c: 4606 mov r6, r0 +1000117e: f7ff fd39 bl 10000bf4 +10001182: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10001186: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1000118a: 4a2e ldr r2, [pc, #184] @ (10001244 ) +1000118c: 1882 adds r2, r0, r2 +1000118e: f141 0300 adc.w r3, r1, #0 +10001192: 4594 cmp ip, r2 +10001194: eb77 0103 sbcs.w r1, r7, r3 +10001198: bf3c itt cc +1000119a: 4662 movcc r2, ip +1000119c: 463b movcc r3, r7 +1000119e: 482a ldr r0, [pc, #168] @ (10001248 ) +100011a0: f000 f966 bl 10001470 <__mutex_try_enter_block_until_veneer> +100011a4: 1c6b adds r3, r5, #1 +100011a6: 4680 mov r8, r0 +100011a8: d040 beq.n 1000122c +100011aa: b30c cbz r4, 100011f0 +100011ac: 4f27 ldr r7, [pc, #156] @ (1000124c ) +100011ae: 4b28 ldr r3, [pc, #160] @ (10001250 ) +100011b0: 681c ldr r4, [r3, #0] +100011b2: b1b4 cbz r4, 100011e2 +100011b4: f1b9 0f00 cmp.w r9, #0 +100011b8: d11c bne.n 100011f4 +100011ba: f8df 909c ldr.w r9, [pc, #156] @ 10001258 +100011be: e001 b.n 100011c4 +100011c0: 6924 ldr r4, [r4, #16] +100011c2: b174 cbz r4, 100011e2 +100011c4: 6823 ldr r3, [r4, #0] +100011c6: 2b00 cmp r3, #0 +100011c8: d0fa beq.n 100011c0 +100011ca: f8d9 3000 ldr.w r3, [r9] +100011ce: b10b cbz r3, 100011d4 +100011d0: 429c cmp r4, r3 +100011d2: d1f5 bne.n 100011c0 +100011d4: 4620 mov r0, r4 +100011d6: 462a mov r2, r5 +100011d8: 4631 mov r1, r6 +100011da: 47b8 blx r7 +100011dc: 6924 ldr r4, [r4, #16] +100011de: 2c00 cmp r4, #0 +100011e0: d1f0 bne.n 100011c4 +100011e2: f1b8 0f00 cmp.w r8, #0 +100011e6: d126 bne.n 10001236 +100011e8: 4628 mov r0, r5 +100011ea: b002 add sp, #8 +100011ec: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100011f0: 4f18 ldr r7, [pc, #96] @ (10001254 ) +100011f2: e7dc b.n 100011ae +100011f4: f04f 0a0a mov.w sl, #10 +100011f8: f8df 905c ldr.w r9, [pc, #92] @ 10001258 +100011fc: e002 b.n 10001204 +100011fe: 6924 ldr r4, [r4, #16] +10001200: 2c00 cmp r4, #0 +10001202: d0ee beq.n 100011e2 +10001204: 6823 ldr r3, [r4, #0] +10001206: 2b00 cmp r3, #0 +10001208: d0f9 beq.n 100011fe +1000120a: f8d9 3000 ldr.w r3, [r9] +1000120e: b10b cbz r3, 10001214 +10001210: 42a3 cmp r3, r4 +10001212: d1f4 bne.n 100011fe +10001214: 462a mov r2, r5 +10001216: 4631 mov r1, r6 +10001218: 4620 mov r0, r4 +1000121a: 47b8 blx r7 +1000121c: 2201 movs r2, #1 +1000121e: 4620 mov r0, r4 +10001220: f10d 0107 add.w r1, sp, #7 +10001224: f88d a007 strb.w sl, [sp, #7] +10001228: 47b8 blx r7 +1000122a: e7e8 b.n 100011fe +1000122c: 4630 mov r0, r6 +1000122e: f000 f8eb bl 10001408 +10001232: 4605 mov r5, r0 +10001234: e7b9 b.n 100011aa +10001236: 4804 ldr r0, [pc, #16] @ (10001248 ) +10001238: f000 f916 bl 10001468 <__mutex_exit_veneer> +1000123c: 4628 mov r0, r5 +1000123e: b002 add sp, #8 +10001240: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001244: 000f4240 .word 0x000f4240 +10001248: 20000244 .word 0x20000244 +1000124c: 100010c1 .word 0x100010c1 +10001250: 2000041c .word 0x2000041c +10001254: 100010b9 .word 0x100010b9 +10001258: 20000420 .word 0x20000420 + +1000125c <__wrap_putchar>: +1000125c: b5f0 push {r4, r5, r6, r7, lr} +1000125e: b083 sub sp, #12 +10001260: 4606 mov r6, r0 +10001262: f88d 0007 strb.w r0, [sp, #7] +10001266: f7ff fcc5 bl 10000bf4 +1000126a: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000126e: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10001272: 4a17 ldr r2, [pc, #92] @ (100012d0 <__wrap_putchar+0x74>) +10001274: 1882 adds r2, r0, r2 +10001276: f141 0300 adc.w r3, r1, #0 +1000127a: 4295 cmp r5, r2 +1000127c: eb74 0103 sbcs.w r1, r4, r3 +10001280: bf3c itt cc +10001282: 4623 movcc r3, r4 +10001284: 462a movcc r2, r5 +10001286: 4813 ldr r0, [pc, #76] @ (100012d4 <__wrap_putchar+0x78>) +10001288: f000 f8f2 bl 10001470 <__mutex_try_enter_block_until_veneer> +1000128c: 4b12 ldr r3, [pc, #72] @ (100012d8 <__wrap_putchar+0x7c>) +1000128e: 4607 mov r7, r0 +10001290: 681c ldr r4, [r3, #0] +10001292: b19c cbz r4, 100012bc <__wrap_putchar+0x60> +10001294: 4d11 ldr r5, [pc, #68] @ (100012dc <__wrap_putchar+0x80>) +10001296: e001 b.n 1000129c <__wrap_putchar+0x40> +10001298: 6924 ldr r4, [r4, #16] +1000129a: b17c cbz r4, 100012bc <__wrap_putchar+0x60> +1000129c: 6823 ldr r3, [r4, #0] +1000129e: 2b00 cmp r3, #0 +100012a0: d0fa beq.n 10001298 <__wrap_putchar+0x3c> +100012a2: 682b ldr r3, [r5, #0] +100012a4: b10b cbz r3, 100012aa <__wrap_putchar+0x4e> +100012a6: 429c cmp r4, r3 +100012a8: d1f6 bne.n 10001298 <__wrap_putchar+0x3c> +100012aa: 4620 mov r0, r4 +100012ac: 2201 movs r2, #1 +100012ae: f10d 0107 add.w r1, sp, #7 +100012b2: f7ff ff05 bl 100010c0 +100012b6: 6924 ldr r4, [r4, #16] +100012b8: 2c00 cmp r4, #0 +100012ba: d1ef bne.n 1000129c <__wrap_putchar+0x40> +100012bc: b917 cbnz r7, 100012c4 <__wrap_putchar+0x68> +100012be: 4630 mov r0, r6 +100012c0: b003 add sp, #12 +100012c2: bdf0 pop {r4, r5, r6, r7, pc} +100012c4: 4803 ldr r0, [pc, #12] @ (100012d4 <__wrap_putchar+0x78>) +100012c6: f000 f8cf bl 10001468 <__mutex_exit_veneer> +100012ca: 4630 mov r0, r6 +100012cc: b003 add sp, #12 +100012ce: bdf0 pop {r4, r5, r6, r7, pc} +100012d0: 000f4240 .word 0x000f4240 +100012d4: 20000244 .word 0x20000244 +100012d8: 2000041c .word 0x2000041c +100012dc: 20000420 .word 0x20000420 + +100012e0 <__wrap_puts>: +100012e0: b538 push {r3, r4, r5, lr} +100012e2: 4604 mov r4, r0 +100012e4: f000 f890 bl 10001408 +100012e8: 2301 movs r3, #1 +100012ea: 4605 mov r5, r0 +100012ec: 461a mov r2, r3 +100012ee: 4620 mov r0, r4 +100012f0: 4629 mov r1, r5 +100012f2: f7ff ff3d bl 10001170 +100012f6: 4b08 ldr r3, [pc, #32] @ (10001318 <__wrap_puts+0x38>) +100012f8: 681c ldr r4, [r3, #0] +100012fa: b12c cbz r4, 10001308 <__wrap_puts+0x28> +100012fc: 6863 ldr r3, [r4, #4] +100012fe: b12b cbz r3, 1000130c <__wrap_puts+0x2c> +10001300: 4798 blx r3 +10001302: 6924 ldr r4, [r4, #16] +10001304: 2c00 cmp r4, #0 +10001306: d1f9 bne.n 100012fc <__wrap_puts+0x1c> +10001308: 4628 mov r0, r5 +1000130a: bd38 pop {r3, r4, r5, pc} +1000130c: 6924 ldr r4, [r4, #16] +1000130e: 2c00 cmp r4, #0 +10001310: d1f4 bne.n 100012fc <__wrap_puts+0x1c> +10001312: 4628 mov r0, r5 +10001314: bd38 pop {r3, r4, r5, pc} +10001316: bf00 nop +10001318: 2000041c .word 0x2000041c + +1000131c : +1000131c: 4684 mov ip, r0 +1000131e: ea41 0300 orr.w r3, r1, r0 +10001322: f013 0303 ands.w r3, r3, #3 +10001326: d149 bne.n 100013bc +10001328: 3a40 subs r2, #64 @ 0x40 +1000132a: d323 bcc.n 10001374 +1000132c: 680b ldr r3, [r1, #0] +1000132e: 6003 str r3, [r0, #0] +10001330: 684b ldr r3, [r1, #4] +10001332: 6043 str r3, [r0, #4] +10001334: 688b ldr r3, [r1, #8] +10001336: 6083 str r3, [r0, #8] +10001338: 68cb ldr r3, [r1, #12] +1000133a: 60c3 str r3, [r0, #12] +1000133c: 690b ldr r3, [r1, #16] +1000133e: 6103 str r3, [r0, #16] +10001340: 694b ldr r3, [r1, #20] +10001342: 6143 str r3, [r0, #20] +10001344: 698b ldr r3, [r1, #24] +10001346: 6183 str r3, [r0, #24] +10001348: 69cb ldr r3, [r1, #28] +1000134a: 61c3 str r3, [r0, #28] +1000134c: 6a0b ldr r3, [r1, #32] +1000134e: 6203 str r3, [r0, #32] +10001350: 6a4b ldr r3, [r1, #36] @ 0x24 +10001352: 6243 str r3, [r0, #36] @ 0x24 +10001354: 6a8b ldr r3, [r1, #40] @ 0x28 +10001356: 6283 str r3, [r0, #40] @ 0x28 +10001358: 6acb ldr r3, [r1, #44] @ 0x2c +1000135a: 62c3 str r3, [r0, #44] @ 0x2c +1000135c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000135e: 6303 str r3, [r0, #48] @ 0x30 +10001360: 6b4b ldr r3, [r1, #52] @ 0x34 +10001362: 6343 str r3, [r0, #52] @ 0x34 +10001364: 6b8b ldr r3, [r1, #56] @ 0x38 +10001366: 6383 str r3, [r0, #56] @ 0x38 +10001368: 6bcb ldr r3, [r1, #60] @ 0x3c +1000136a: 63c3 str r3, [r0, #60] @ 0x3c +1000136c: 3040 adds r0, #64 @ 0x40 +1000136e: 3140 adds r1, #64 @ 0x40 +10001370: 3a40 subs r2, #64 @ 0x40 +10001372: d2db bcs.n 1000132c +10001374: 3230 adds r2, #48 @ 0x30 +10001376: d30b bcc.n 10001390 +10001378: 680b ldr r3, [r1, #0] +1000137a: 6003 str r3, [r0, #0] +1000137c: 684b ldr r3, [r1, #4] +1000137e: 6043 str r3, [r0, #4] +10001380: 688b ldr r3, [r1, #8] +10001382: 6083 str r3, [r0, #8] +10001384: 68cb ldr r3, [r1, #12] +10001386: 60c3 str r3, [r0, #12] +10001388: 3010 adds r0, #16 +1000138a: 3110 adds r1, #16 +1000138c: 3a10 subs r2, #16 +1000138e: d2f3 bcs.n 10001378 +10001390: 320c adds r2, #12 +10001392: d305 bcc.n 100013a0 +10001394: f851 3b04 ldr.w r3, [r1], #4 +10001398: f840 3b04 str.w r3, [r0], #4 +1000139c: 3a04 subs r2, #4 +1000139e: d2f9 bcs.n 10001394 +100013a0: 3204 adds r2, #4 +100013a2: d008 beq.n 100013b6 +100013a4: 07d2 lsls r2, r2, #31 +100013a6: bf1c itt ne +100013a8: f811 3b01 ldrbne.w r3, [r1], #1 +100013ac: f800 3b01 strbne.w r3, [r0], #1 +100013b0: d301 bcc.n 100013b6 +100013b2: 880b ldrh r3, [r1, #0] +100013b4: 8003 strh r3, [r0, #0] +100013b6: 4660 mov r0, ip +100013b8: 4770 bx lr +100013ba: bf00 nop +100013bc: 2a08 cmp r2, #8 +100013be: d313 bcc.n 100013e8 +100013c0: 078b lsls r3, r1, #30 +100013c2: d0b1 beq.n 10001328 +100013c4: f010 0303 ands.w r3, r0, #3 +100013c8: d0ae beq.n 10001328 +100013ca: f1c3 0304 rsb r3, r3, #4 +100013ce: 1ad2 subs r2, r2, r3 +100013d0: 07db lsls r3, r3, #31 +100013d2: bf1c itt ne +100013d4: f811 3b01 ldrbne.w r3, [r1], #1 +100013d8: f800 3b01 strbne.w r3, [r0], #1 +100013dc: d3a4 bcc.n 10001328 +100013de: f831 3b02 ldrh.w r3, [r1], #2 +100013e2: f820 3b02 strh.w r3, [r0], #2 +100013e6: e79f b.n 10001328 +100013e8: 3a04 subs r2, #4 +100013ea: d3d9 bcc.n 100013a0 +100013ec: 3a01 subs r2, #1 +100013ee: f811 3b01 ldrb.w r3, [r1], #1 +100013f2: f800 3b01 strb.w r3, [r0], #1 +100013f6: d2f9 bcs.n 100013ec +100013f8: 780b ldrb r3, [r1, #0] +100013fa: 7003 strb r3, [r0, #0] +100013fc: 784b ldrb r3, [r1, #1] +100013fe: 7043 strb r3, [r0, #1] +10001400: 788b ldrb r3, [r1, #2] +10001402: 7083 strb r3, [r0, #2] +10001404: 4660 mov r0, ip +10001406: 4770 bx lr + +10001408 : +10001408: f020 0103 bic.w r1, r0, #3 +1000140c: f010 0003 ands.w r0, r0, #3 +10001410: f1c0 0000 rsb r0, r0, #0 +10001414: f851 3b04 ldr.w r3, [r1], #4 +10001418: f100 0c04 add.w ip, r0, #4 +1000141c: ea4f 0ccc mov.w ip, ip, lsl #3 +10001420: f06f 0200 mvn.w r2, #0 +10001424: bf1c itt ne +10001426: fa22 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<__mutex_try_enter_block_until_veneer+0x4> +10001474: 2000017d .word 0x2000017d + +10001478 <__pre_init_runtime_init_bootrom_reset>: +10001478: 10000ee1 .... + +1000147c <__pre_init_runtime_init_early_resets>: +1000147c: 10000e55 U... + +10001480 <__pre_init_runtime_init_usb_power_down>: +10001480: 10000e89 .... + +10001484 <__pre_init_runtime_init_clocks>: +10001484: 10000f75 u... + +10001488 <__pre_init_runtime_init_post_clock_resets>: +10001488: 10000ec1 .... + +1000148c <__pre_init_runtime_init_boot_locks_reset>: +1000148c: 10000dd9 .... + +10001490 <__pre_init_runtime_init_spin_locks_reset>: +10001490: 10000f09 .... + +10001494 <__pre_init_runtime_init_bootrom_locking_enable>: +10001494: 10000dc5 .... + +10001498 <__pre_init_runtime_init_mutex>: +10001498: 10000451 Q... + +1000149c <__pre_init_runtime_init_install_ram_vector_table>: +1000149c: 10000f0d .... + +100014a0 <__pre_init_runtime_init_default_alarm_pool>: +100014a0: 100007c9 .... + +100014a4 <__pre_init_first_per_core_initializer>: +100014a4: 10000e25 %... + +100014a8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100014a8: 10000ef5 .... + +100014ac <__pre_init_runtime_init_per_core_enable_coprocessors>: +100014ac: 10000ea5 .... + +100014b0 <__pre_init_spinlock_set_extexclall>: +100014b0: 10000351 Q... + +100014b4 <__pre_init_runtime_init_per_core_irq_priorities>: +100014b4: 10000379 y... + +100014b8 <__frame_dummy_init_array_entry>: +100014b8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__best_effort_wfe_or_timeout_veneer>: +20000220: f85f f000 ldr.w pc, [pc] @ 20000224 <__best_effort_wfe_or_timeout_veneer+0x4> +20000224: 10000aed .word 0x10000aed + +20000228 : +20000228: 00000010 .... + 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+:0C17180050020020000000000000000053 +:10172400D3DEFFFFFE010000FF01000014EAFFFF0B +:04173400793512AB46 +:040000051000014D99 +:00000001FF diff --git a/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.uf2 b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.uf2 new file mode 100644 index 0000000..e13ae13 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-a/build/0x0008_uninitialized-variables-a.uf2 differ diff --git a/WEEK04/0x0008_uninitialized-variables-a/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables-a/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables-a/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables-a/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-a/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables-b/.gitignore b/WEEK04/0x0008_uninitialized-variables-b/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0008_uninitialized-variables-b/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables-b/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-b/0x0008_uninitialized-variables-b.c b/WEEK04/0x0008_uninitialized-variables-b/0x0008_uninitialized-variables-b.c new file mode 100644 index 0000000..365d7eb --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/0x0008_uninitialized-variables-b.c @@ -0,0 +1,27 @@ +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) +{ + // gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_IN); + gpio_put(LED_PIN, 0); + gpio_set_function(LED_PIN, GPIO_FUNC_SIO); + + // gpio_set_dir(LED_PIN, GPIO_OUT); + gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + + while (true) { + // gpio_put(LED_PIN, 1); + gpioc_bit_out_put(LED_PIN, 1); + // sleep_ms(500); + sleep_us(500 * 1000ull); + + // gpio_put(LED_PIN, 0); + gpioc_bit_out_put(LED_PIN, 0); + // sleep_ms(500); + sleep_us(500 * 1000ull); + } +} diff --git a/WEEK04/0x0008_uninitialized-variables-b/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables-b/CMakeLists.txt new file mode 100644 index 0000000..24d559f --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables-b C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables-b 0x0008_uninitialized-variables-b.c ) + +pico_set_program_name(0x0008_uninitialized-variables-b "0x0008_uninitialized-variables-b") +pico_set_program_version(0x0008_uninitialized-variables-b "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables-b 0) +pico_enable_stdio_usb(0x0008_uninitialized-variables-b 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables-b + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables-b PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables-b) + diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.bin b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.bin new file mode 100755 index 0000000..24a8e1f Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.bin differ diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.dis b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.dis new file mode 100644 index 0000000..b1df847 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.dis @@ -0,0 +1,2293 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000014bc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000104 100014bc 100014bc 000024bc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100015c0 100015c0 000025c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000020 100015c8 100015c8 000025c8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003738 2**0 + CONTENTS + 6 .data 0000013c 20000110 100015e8 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000024c 2000024c 00003738 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000024c 2000024c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000214 20000250 10001724 00004250 2**3 + ALLOC + 10 .heap 00000800 20000464 10001724 00004464 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003738 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003738 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001724 10001724 00003724 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003738 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 0000376c 2**0 + CONTENTS, READONLY + 17 .debug_info 0001d52d 00000000 00000000 000037b1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00004e36 00000000 00000000 00020cde 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0000eb4e 00000000 00000000 00025b14 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000a18 00000000 00000000 00034668 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00002b6b 00000000 00000000 00035080 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000139a9 00000000 00000000 00037beb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00004d2a 00000000 00000000 0004b594 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001c60 00000000 00000000 000502c0 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 0000018e 00000000 00000000 00051f20 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100015c8 .word 0x100015c8 +1000012c: 100015e8 .word 0x100015e8 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 000015ec .word 0x000015ec +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100015e8 .word 0x100015e8 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000024c .word 0x2000024c +100001ac: 10001724 .word 0x10001724 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001724 .word 0x10001724 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000024c .word 0x2000024c +100001d4: 20000464 .word 0x20000464 +100001d8: 10001091 .word 0x10001091 +100001dc: 10000235 .word 0x10000235 +100001e0: 10001089 .word 0x10001089 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000024c .word 0x2000024c +10000208: 2000024c .word 0x2000024c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000428 .word 0x20000428 +10000230: 100014bc .word 0x100014bc + +10000234
: +10000234: b508 push {r3, lr} +10000236: 2410 movs r4, #16 +10000238: f04f 0500 mov.w r5, #0 +1000023c: ec45 4044 gpioc_bit_oe_put r4, r5 +10000240: ec45 4040 gpioc_bit_out_put r4, r5 +10000244: 2105 movs r1, #5 +10000246: 4620 mov r0, r4 +10000248: f000 f814 bl 10000274 +1000024c: f04f 0601 mov.w r6, #1 +10000250: ec46 4044 gpioc_bit_oe_put r4, r6 +10000254: 2410 movs r4, #16 +10000256: ec46 4040 gpioc_bit_out_put r4, r6 +1000025a: 2100 movs r1, #0 +1000025c: 4804 ldr r0, [pc, #16] @ (10000270 ) +1000025e: f000 fbd7 bl 10000a10 +10000262: ec45 4040 gpioc_bit_out_put r4, r5 +10000266: 2100 movs r1, #0 +10000268: 4801 ldr r0, [pc, #4] @ (10000270 ) +1000026a: f000 fbd1 bl 10000a10 +1000026e: e7f1 b.n 10000254 +10000270: 0007a120 .word 0x0007a120 + +10000274 : +10000274: b410 push {r4} +10000276: f44f 7480 mov.w r4, #256 @ 0x100 +1000027a: 4b0c ldr r3, [pc, #48] @ (100002ac ) +1000027c: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000280: eb03 0380 add.w r3, r3, r0, lsl #2 +10000284: 00c0 lsls r0, r0, #3 +10000286: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000028a: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +1000028e: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000292: f002 02c0 and.w r2, r2, #192 @ 0xc0 +10000296: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000029a: f503 5340 add.w r3, r3, #12288 @ 0x3000 +1000029e: f8cc 2000 str.w r2, [ip] +100002a2: 6041 str r1, [r0, #4] +100002a4: 601c str r4, [r3, #0] +100002a6: f85d 4b04 ldr.w r4, [sp], #4 +100002aa: 4770 bx lr +100002ac: 40038004 .word 0x40038004 + +100002b0 : +100002b0: b40f push {r0, r1, r2, r3} +100002b2: b500 push {lr} +100002b4: b083 sub sp, #12 +100002b6: 9c04 ldr r4, [sp, #16] +100002b8: 4807 ldr r0, [pc, #28] @ (100002d8 ) +100002ba: f001 f80f bl 100012dc <__wrap_puts> +100002be: b13c cbz r4, 100002d0 +100002c0: a905 add r1, sp, #20 +100002c2: 4620 mov r0, r4 +100002c4: 9101 str r1, [sp, #4] +100002c6: f000 fec5 bl 10001054 +100002ca: 4804 ldr r0, [pc, #16] @ (100002dc ) +100002cc: f001 f806 bl 100012dc <__wrap_puts> +100002d0: 2001 movs r0, #1 +100002d2: f000 fed7 bl 10001084 <_exit> +100002d6: bf00 nop +100002d8: 100014bc .word 0x100014bc +100002dc: 100014cc .word 0x100014cc + +100002e0 : +100002e0: b570 push {r4, r5, r6, lr} +100002e2: 4686 mov lr, r0 +100002e4: f3ef 8510 mrs r5, PRIMASK +100002e8: b672 cpsid i +100002ea: 4c12 ldr r4, [pc, #72] @ (10000334 ) +100002ec: e8d4 6fcf ldaexb r6, [r4] +100002f0: 2001 movs r0, #1 +100002f2: 2e00 cmp r6, #0 +100002f4: d1fa bne.n 100002ec +100002f6: e8c4 0f46 strexb r6, r0, [r4] +100002fa: 2e00 cmp r6, #0 +100002fc: d1f6 bne.n 100002ec +100002fe: f3bf 8f5f dmb sy +10000302: f04f 0c01 mov.w ip, #1 +10000306: 08c8 lsrs r0, r1, #3 +10000308: f001 0307 and.w r3, r1, #7 +1000030c: fa0c f303 lsl.w r3, ip, r3 +10000310: f81e c000 ldrb.w ip, [lr, r0] +10000314: ea1c 0603 ands.w r6, ip, r3 +10000318: d108 bne.n 1000032c +1000031a: ea4c 0c03 orr.w ip, ip, r3 +1000031e: f80e c000 strb.w ip, [lr, r0] +10000322: e8c4 6f8f stlb r6, [r4] +10000326: f385 8810 msr PRIMASK, r5 +1000032a: bd70 pop {r4, r5, r6, pc} +1000032c: 4610 mov r0, r2 +1000032e: f7ff ffbf bl 100002b0 +10000332: bf00 nop +10000334: 200003db .word 0x200003db + +10000338 : +10000338: 4a04 ldr r2, [pc, #16] @ (1000034c ) +1000033a: 7810 ldrb r0, [r2, #0] +1000033c: 1c43 adds r3, r0, #1 +1000033e: b2db uxtb r3, r3 +10000340: 2b18 cmp r3, #24 +10000342: bf28 it cs +10000344: 2310 movcs r3, #16 +10000346: 7013 strb r3, [r2, #0] +10000348: 4770 bx lr +1000034a: bf00 nop +1000034c: 20000228 .word 0x20000228 + +10000350 : +10000350: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000354: 6893 ldr r3, [r2, #8] +10000356: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000035a: 6093 str r3, [r2, #8] +1000035c: 4770 bx lr +1000035e: bf00 nop + +10000360 : +10000360: 2100 movs r1, #0 +10000362: 4b04 ldr r3, [pc, #16] @ (10000374 ) +10000364: f103 0220 add.w r2, r3, #32 +10000368: e8c3 1f8f stlb r1, [r3] +1000036c: 3301 adds r3, #1 +1000036e: 4293 cmp r3, r2 +10000370: d1fa bne.n 10000368 +10000372: 4770 bx lr +10000374: 200003d0 .word 0x200003d0 + +10000378 : +10000378: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000037c: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000380: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000384: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000388: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +1000038c: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000390: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000394: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000398: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +1000039c: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100003a0: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100003a4: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100003a8: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100003ac: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100003b0: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100003b4: b662 cpsie i +100003b6: 4770 bx lr + +100003b8 : +100003b8: 2301 movs r3, #1 +100003ba: f000 021f and.w r2, r0, #31 +100003be: 4093 lsls r3, r2 +100003c0: 0940 lsrs r0, r0, #5 +100003c2: b141 cbz r1, 100003d6 +100003c4: 0080 lsls r0, r0, #2 +100003c6: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003ca: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003ce: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003d2: 6003 str r3, [r0, #0] +100003d4: 4770 bx lr +100003d6: 4a02 ldr r2, [pc, #8] @ (100003e0 ) +100003d8: 3020 adds r0, #32 +100003da: f842 3020 str.w r3, [r2, r0, lsl #2] +100003de: 4770 bx lr +100003e0: e000e100 .word 0xe000e100 + +100003e4 : +100003e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100003e6: 460d mov r5, r1 +100003e8: f3ef 8710 mrs r7, PRIMASK +100003ec: b672 cpsid i +100003ee: 4e12 ldr r6, [pc, #72] @ (10000438 ) +100003f0: e8d6 2fcf ldaexb r2, [r6] +100003f4: 2301 movs r3, #1 +100003f6: 2a00 cmp r2, #0 +100003f8: d1fa bne.n 100003f0 +100003fa: e8c6 3f42 strexb r2, r3, [r6] +100003fe: 2a00 cmp r2, #0 +10000400: d1f6 bne.n 100003f0 +10000402: f3bf 8f5f dmb sy +10000406: 4b0d ldr r3, [pc, #52] @ (1000043c ) +10000408: f100 0410 add.w r4, r0, #16 +1000040c: 689b ldr r3, [r3, #8] +1000040e: 4a0c ldr r2, [pc, #48] @ (10000440 ) +10000410: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000414: 4293 cmp r3, r2 +10000416: d003 beq.n 10000420 +10000418: 4299 cmp r1, r3 +1000041a: d001 beq.n 10000420 +1000041c: f000 fd02 bl 10000e24 +10000420: 4b06 ldr r3, [pc, #24] @ (1000043c ) +10000422: 689b ldr r3, [r3, #8] +10000424: f843 5024 str.w r5, [r3, r4, lsl #2] +10000428: f3bf 8f5f dmb sy +1000042c: 2300 movs r3, #0 +1000042e: e8c6 3f8f stlb r3, [r6] +10000432: f387 8810 msr PRIMASK, r7 +10000436: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000438: 200003d9 .word 0x200003d9 +1000043c: e000ed00 .word 0xe000ed00 +10000440: 10000111 .word 0x10000111 + +10000444 : +10000444: 4b01 ldr r3, [pc, #4] @ (1000044c ) +10000446: 440b add r3, r1 +10000448: 6003 str r3, [r0, #0] +1000044a: 4770 bx lr +1000044c: 200003d0 .word 0x200003d0 + +10000450 : +10000450: b570 push {r4, r5, r6, lr} +10000452: 4c10 ldr r4, [pc, #64] @ (10000494 ) +10000454: 4d10 ldr r5, [pc, #64] @ (10000498 ) +10000456: 42ac cmp r4, r5 +10000458: d20e bcs.n 10000478 +1000045a: 26ff movs r6, #255 @ 0xff +1000045c: 6823 ldr r3, [r4, #0] +1000045e: b163 cbz r3, 1000047a +10000460: f7ff ff6a bl 10000338 +10000464: 4601 mov r1, r0 +10000466: 4620 mov r0, r4 +10000468: f7ff ffec bl 10000444 +1000046c: 80a6 strh r6, [r4, #4] +1000046e: f3bf 8f5f dmb sy +10000472: 3408 adds r4, #8 +10000474: 42ac cmp r4, r5 +10000476: d3f1 bcc.n 1000045c +10000478: bd70 pop {r4, r5, r6, pc} +1000047a: f7ff ff5d bl 10000338 +1000047e: 4601 mov r1, r0 +10000480: 4620 mov r0, r4 +10000482: f7ff ffdf bl 10000444 +10000486: 7126 strb r6, [r4, #4] +10000488: f3bf 8f5f dmb sy +1000048c: 3408 adds r4, #8 +1000048e: 42ac cmp r4, r5 +10000490: d3e4 bcc.n 1000045c +10000492: bd70 pop {r4, r5, r6, pc} +10000494: 20000244 .word 0x20000244 +10000498: 2000024c .word 0x2000024c + +1000049c : +1000049c: 4b0d ldr r3, [pc, #52] @ (100004d4 ) +1000049e: 681a ldr r2, [r3, #0] +100004a0: f3ef 8110 mrs r1, PRIMASK +100004a4: b672 cpsid i +100004a6: e8d2 cfcf ldaexb ip, [r2] +100004aa: 2001 movs r0, #1 +100004ac: f1bc 0f00 cmp.w ip, #0 +100004b0: d1f9 bne.n 100004a6 +100004b2: e8c2 0f4c strexb ip, r0, [r2] +100004b6: f1bc 0f00 cmp.w ip, #0 +100004ba: d1f4 bne.n 100004a6 +100004bc: f3bf 8f5f dmb sy +100004c0: 2200 movs r2, #0 +100004c2: 681b ldr r3, [r3, #0] +100004c4: e8c3 2f8f stlb r2, [r3] +100004c8: f381 8810 msr PRIMASK, r1 +100004cc: bf40 sev +100004ce: 2000 movs r0, #0 +100004d0: 2100 movs r1, #0 +100004d2: 4770 bx lr +100004d4: 20000460 .word 0x20000460 + +100004d8 : +100004d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004dc: ed2d 8b02 vpush {d8} +100004e0: b085 sub sp, #20 +100004e2: f3ef 8305 mrs r3, IPSR +100004e6: b2db uxtb r3, r3 +100004e8: 3b10 subs r3, #16 +100004ea: 089a lsrs r2, r3, #2 +100004ec: bf18 it ne +100004ee: 2201 movne r2, #1 +100004f0: f04f 0101 mov.w r1, #1 +100004f4: f003 0b03 and.w fp, r3, #3 +100004f8: bf18 it ne +100004fa: 4daf ldrne r5, [pc, #700] @ (100007b8 ) +100004fc: 4baf ldr r3, [pc, #700] @ (100007bc ) +100004fe: bf08 it eq +10000500: 4daf ldreq r5, [pc, #700] @ (100007c0 ) +10000502: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000506: f853 6022 ldr.w r6, [r3, r2, lsl #2] +1000050a: fa01 f20b lsl.w r2, r1, fp +1000050e: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000512: ed9f 8ba7 vldr d8, [pc, #668] @ 100007b0 +10000516: 9201 str r2, [sp, #4] +10000518: 605a str r2, [r3, #4] +1000051a: e02f b.n 1000057c +1000051c: 88b3 ldrh r3, [r6, #4] +1000051e: 041c lsls r4, r3, #16 +10000520: f140 8093 bpl.w 1000064a +10000524: 79b3 ldrb r3, [r6, #6] +10000526: 2b00 cmp r3, #0 +10000528: f040 80dd bne.w 100006e6 +1000052c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000530: 2a00 cmp r2, #0 +10000532: f2c0 811e blt.w 10000772 +10000536: 6973 ldr r3, [r6, #20] +10000538: eb02 0242 add.w r2, r2, r2, lsl #1 +1000053c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000540: e9d3 4702 ldrd r4, r7, [r3, #8] +10000544: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000548: bf08 it eq +1000054a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +1000054e: d00e beq.n 1000056e +10000550: eb05 018b add.w r1, r5, fp, lsl #2 +10000554: 6aab ldr r3, [r5, #40] @ 0x28 +10000556: 690a ldr r2, [r1, #16] +10000558: 1ad2 subs r2, r2, r3 +1000055a: 1ae3 subs r3, r4, r3 +1000055c: 4293 cmp r3, r2 +1000055e: d305 bcc.n 1000056c +10000560: 2301 movs r3, #1 +10000562: 6a2a ldr r2, [r5, #32] +10000564: fa03 f30b lsl.w r3, r3, fp +10000568: 4213 tst r3, r2 +1000056a: d100 bne.n 1000056e +1000056c: 610c str r4, [r1, #16] +1000056e: 4628 mov r0, r5 +10000570: f000 fb36 bl 10000be0 +10000574: 42a0 cmp r0, r4 +10000576: 41b9 sbcs r1, r7 +10000578: f2c0 80fb blt.w 10000772 +1000057c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000580: 9a01 ldr r2, [sp, #4] +10000582: 2b00 cmp r3, #0 +10000584: 9300 str r3, [sp, #0] +10000586: 63ea str r2, [r5, #60] @ 0x3c +10000588: dbc8 blt.n 1000051c +1000058a: f8d6 8014 ldr.w r8, [r6, #20] +1000058e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000592: 4628 mov r0, r5 +10000594: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000598: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000059c: f000 fb20 bl 10000be0 +100005a0: 42a0 cmp r0, r4 +100005a2: eb71 010a sbcs.w r1, r1, sl +100005a6: dbb9 blt.n 1000051c +100005a8: f1ba 0f00 cmp.w sl, #0 +100005ac: f2c0 80c3 blt.w 10000736 +100005b0: e9d7 3104 ldrd r3, r1, [r7, #16] +100005b4: 4a83 ldr r2, [pc, #524] @ (100007c4 ) +100005b6: 4293 cmp r3, r2 +100005b8: f000 80ed beq.w 10000796 +100005bc: 887a ldrh r2, [r7, #2] +100005be: f9b6 0008 ldrsh.w r0, [r6, #8] +100005c2: b292 uxth r2, r2 +100005c4: ea42 4000 orr.w r0, r2, r0, lsl #16 +100005c8: 4798 blx r3 +100005ca: 4602 mov r2, r0 +100005cc: 460b mov r3, r1 +100005ce: ea52 0103 orrs.w r1, r2, r3 +100005d2: f000 80b0 beq.w 10000736 +100005d6: 2b00 cmp r3, #0 +100005d8: f280 80d1 bge.w 1000077e +100005dc: ebb4 0e02 subs.w lr, r4, r2 +100005e0: eb6a 0a03 sbc.w sl, sl, r3 +100005e4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100005e8: e9c7 ea02 strd lr, sl, [r7, #8] +100005ec: 2b00 cmp r3, #0 +100005ee: db95 blt.n 1000051c +100005f0: 6971 ldr r1, [r6, #20] +100005f2: eb03 0243 add.w r2, r3, r3, lsl #1 +100005f6: eb01 02c2 add.w r2, r1, r2, lsl #3 +100005fa: e9d2 7002 ldrd r7, r0, [r2, #8] +100005fe: 45be cmp lr, r7 +10000600: eb7a 0c00 sbcs.w ip, sl, r0 +10000604: ea4f 0243 mov.w r2, r3, lsl #1 +10000608: db88 blt.n 1000051c +1000060a: 46b4 mov ip, r6 +1000060c: f82c 3f08 strh.w r3, [ip, #8]! +10000610: e006 b.n 10000620 +10000612: eb03 0043 add.w r0, r3, r3, lsl #1 +10000616: eb01 00c0 add.w r0, r1, r0, lsl #3 +1000061a: 005a lsls r2, r3, #1 +1000061c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000620: 45be cmp lr, r7 +10000622: 441a add r2, r3 +10000624: eb7a 0000 sbcs.w r0, sl, r0 +10000628: eb01 04c2 add.w r4, r1, r2, lsl #3 +1000062c: db04 blt.n 10000638 +1000062e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000632: 46a4 mov ip, r4 +10000634: 2b00 cmp r3, #0 +10000636: daec bge.n 10000612 +10000638: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000063c: 9b00 ldr r3, [sp, #0] +1000063e: f8ac 3000 strh.w r3, [ip] +10000642: 88b3 ldrh r3, [r6, #4] +10000644: 041c lsls r4, r3, #16 +10000646: f53f af6d bmi.w 10000524 +1000064a: 6933 ldr r3, [r6, #16] +1000064c: f3ef 8210 mrs r2, PRIMASK +10000650: b672 cpsid i +10000652: e8d3 0fcf ldaexb r0, [r3] +10000656: 2101 movs r1, #1 +10000658: 2800 cmp r0, #0 +1000065a: d1fa bne.n 10000652 +1000065c: e8c3 1f40 strexb r0, r1, [r3] +10000660: 2800 cmp r0, #0 +10000662: d1f6 bne.n 10000652 +10000664: f3bf 8f5f dmb sy +10000668: f64f 74ff movw r4, #65535 @ 0xffff +1000066c: 88b0 ldrh r0, [r6, #4] +1000066e: 2300 movs r3, #0 +10000670: 6931 ldr r1, [r6, #16] +10000672: b200 sxth r0, r0 +10000674: 80b4 strh r4, [r6, #4] +10000676: e8c1 3f8f stlb r3, [r1] +1000067a: f382 8810 msr PRIMASK, r2 +1000067e: 4298 cmp r0, r3 +10000680: f6ff af50 blt.w 10000524 +10000684: 4607 mov r7, r0 +10000686: 46a9 mov r9, r5 +10000688: 6974 ldr r4, [r6, #20] +1000068a: f106 0808 add.w r8, r6, #8 +1000068e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000692: eb04 03ce add.w r3, r4, lr, lsl #3 +10000696: e9d3 5002 ldrd r5, r0, [r3, #8] +1000069a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000069e: 46c4 mov ip, r8 +100006a0: 2b00 cmp r3, #0 +100006a2: db13 blt.n 100006cc +100006a4: 46b2 mov sl, r6 +100006a6: 9700 str r7, [sp, #0] +100006a8: e004 b.n 100006b4 +100006aa: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +100006ae: 4694 mov ip, r2 +100006b0: 2b00 cmp r3, #0 +100006b2: db09 blt.n 100006c8 +100006b4: eb03 0643 add.w r6, r3, r3, lsl #1 +100006b8: eb04 02c6 add.w r2, r4, r6, lsl #3 +100006bc: e9d2 7102 ldrd r7, r1, [r2, #8] +100006c0: 42bd cmp r5, r7 +100006c2: eb70 0101 sbcs.w r1, r0, r1 +100006c6: daf0 bge.n 100006aa +100006c8: 4656 mov r6, sl +100006ca: 9f00 ldr r7, [sp, #0] +100006cc: f8ac 7000 strh.w r7, [ip] +100006d0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100006d4: f824 303e strh.w r3, [r4, lr, lsl #3] +100006d8: 2f00 cmp r7, #0 +100006da: dad8 bge.n 1000068e +100006dc: 79b3 ldrb r3, [r6, #6] +100006de: 464d mov r5, r9 +100006e0: 2b00 cmp r3, #0 +100006e2: f43f af23 beq.w 1000052c +100006e6: 2300 movs r3, #0 +100006e8: 71b3 strb r3, [r6, #6] +100006ea: f9b6 3008 ldrsh.w r3, [r6, #8] +100006ee: f106 0808 add.w r8, r6, #8 +100006f2: 1c58 adds r0, r3, #1 +100006f4: d03d beq.n 10000772 +100006f6: 461a mov r2, r3 +100006f8: 6977 ldr r7, [r6, #20] +100006fa: e003 b.n 10000704 +100006fc: 4680 mov r8, r0 +100006fe: 1c59 adds r1, r3, #1 +10000700: f43f af16 beq.w 10000530 +10000704: eb03 0143 add.w r1, r3, r3, lsl #1 +10000708: eb07 00c1 add.w r0, r7, r1, lsl #3 +1000070c: f8b0 c002 ldrh.w ip, [r0, #2] +10000710: 461c mov r4, r3 +10000712: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000716: 469e mov lr, r3 +10000718: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +1000071c: d0ee beq.n 100006fc +1000071e: 4294 cmp r4, r2 +10000720: ed80 8b02 vstr d8, [r0, #8] +10000724: d005 beq.n 10000732 +10000726: f8a8 3000 strh.w r3, [r8] +1000072a: 8932 ldrh r2, [r6, #8] +1000072c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000730: 8134 strh r4, [r6, #8] +10000732: 4672 mov r2, lr +10000734: e7e3 b.n 100006fe +10000736: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +1000073a: 8133 strh r3, [r6, #8] +1000073c: 6933 ldr r3, [r6, #16] +1000073e: f3ef 8210 mrs r2, PRIMASK +10000742: b672 cpsid i +10000744: e8d3 0fcf ldaexb r0, [r3] +10000748: 2101 movs r1, #1 +1000074a: 2800 cmp r0, #0 +1000074c: d1fa bne.n 10000744 +1000074e: e8c3 1f40 strexb r0, r1, [r3] +10000752: 2800 cmp r0, #0 +10000754: d1f6 bne.n 10000744 +10000756: f3bf 8f5f dmb sy +1000075a: 8873 ldrh r3, [r6, #2] +1000075c: 6931 ldr r1, [r6, #16] +1000075e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000762: 9b00 ldr r3, [sp, #0] +10000764: 8073 strh r3, [r6, #2] +10000766: 2300 movs r3, #0 +10000768: e8c1 3f8f stlb r3, [r1] +1000076c: f382 8810 msr PRIMASK, r2 +10000770: e6d4 b.n 1000051c +10000772: bf40 sev +10000774: b005 add sp, #20 +10000776: ecbd 8b02 vpop {d8} +1000077a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000077e: 4628 mov r0, r5 +10000780: e9cd 2302 strd r2, r3, [sp, #8] +10000784: f000 fa2c bl 10000be0 +10000788: 9a02 ldr r2, [sp, #8] +1000078a: 9b03 ldr r3, [sp, #12] +1000078c: eb10 0e02 adds.w lr, r0, r2 +10000790: eb43 0a01 adc.w sl, r3, r1 +10000794: e726 b.n 100005e4 +10000796: 4608 mov r0, r1 +10000798: 690b ldr r3, [r1, #16] +1000079a: 9102 str r1, [sp, #8] +1000079c: 4798 blx r3 +1000079e: 2800 cmp r0, #0 +100007a0: d0c9 beq.n 10000736 +100007a2: 9902 ldr r1, [sp, #8] +100007a4: e9d1 2300 ldrd r2, r3, [r1] +100007a8: e711 b.n 100005ce +100007aa: bf00 nop +100007ac: f3af 8000 nop.w +100007b0: ffffffff .word 0xffffffff +100007b4: ffffffff .word 0xffffffff +100007b8: 400b8000 .word 0x400b8000 +100007bc: 20000440 .word 0x20000440 +100007c0: 400b0000 .word 0x400b0000 +100007c4: 100004d9 .word 0x100004d9 + +100007c8 : +100007c8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007cc: 4c36 ldr r4, [pc, #216] @ (100008a8 ) +100007ce: 6925 ldr r5, [r4, #16] +100007d0: b12d cbz r5, 100007de +100007d2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007d6: 210a movs r1, #10 +100007d8: 4834 ldr r0, [pc, #208] @ (100008ac ) +100007da: f7ff be33 b.w 10000444 +100007de: f8df 80e4 ldr.w r8, [pc, #228] @ 100008c4 +100007e2: 2103 movs r1, #3 +100007e4: 4640 mov r0, r8 +100007e6: f000 f9e9 bl 10000bbc +100007ea: 2603 movs r6, #3 +100007ec: f8c4 800c str.w r8, [r4, #12] +100007f0: f7ff fda2 bl 10000338 +100007f4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +100007f8: 4b2d ldr r3, [pc, #180] @ (100008b0 ) +100007fa: 7026 strb r6, [r4, #0] +100007fc: 4403 add r3, r0 +100007fe: 6123 str r3, [r4, #16] +10000800: f8dc 3000 ldr.w r3, [ip] +10000804: 210f movs r1, #15 +10000806: 7063 strb r3, [r4, #1] +10000808: 6963 ldr r3, [r4, #20] +1000080a: 8061 strh r1, [r4, #2] +1000080c: 831d strh r5, [r3, #24] +1000080e: f04f 0504 mov.w r5, #4 +10000812: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000816: f04f 0505 mov.w r5, #5 +1000081a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +1000081e: f04f 0506 mov.w r5, #6 +10000822: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000826: f04f 0507 mov.w r5, #7 +1000082a: 210e movs r1, #14 +1000082c: f64f 72ff movw r2, #65535 @ 0xffff +10000830: 2708 movs r7, #8 +10000832: f04f 0e0a mov.w lr, #10 +10000836: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +1000083a: f04f 0901 mov.w r9, #1 +1000083e: f04f 0c0c mov.w ip, #12 +10000842: f04f 0b02 mov.w fp, #2 +10000846: f04f 0a09 mov.w sl, #9 +1000084a: 200d movs r0, #13 +1000084c: f04f 050b mov.w r5, #11 +10000850: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000854: 4917 ldr r1, [pc, #92] @ (100008b4 ) +10000856: 80a2 strh r2, [r4, #4] +10000858: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +1000085c: 60a1 str r1, [r4, #8] +1000085e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000862: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000866: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +1000086a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +1000086e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000872: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000876: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +1000087a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +1000087e: 801a strh r2, [r3, #0] +10000880: 4b0d ldr r3, [pc, #52] @ (100008b8 ) +10000882: 4630 mov r0, r6 +10000884: f8c8 7020 str.w r7, [r8, #32] +10000888: 490c ldr r1, [pc, #48] @ (100008bc ) +1000088a: 60dc str r4, [r3, #12] +1000088c: f7ff fdaa bl 100003e4 +10000890: 4649 mov r1, r9 +10000892: 4630 mov r0, r6 +10000894: f7ff fd90 bl 100003b8 +10000898: 4b09 ldr r3, [pc, #36] @ (100008c0 ) +1000089a: 210a movs r1, #10 +1000089c: 641f str r7, [r3, #64] @ 0x40 +1000089e: 4803 ldr r0, [pc, #12] @ (100008ac ) +100008a0: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100008a4: f7ff bdce b.w 10000444 +100008a8: 2000022c .word 0x2000022c +100008ac: 20000460 .word 0x20000460 +100008b0: 200003d0 .word 0x200003d0 +100008b4: 0010ffff .word 0x0010ffff +100008b8: 20000440 .word 0x20000440 +100008bc: 100004d9 .word 0x100004d9 +100008c0: 400b2000 .word 0x400b2000 +100008c4: 400b0000 .word 0x400b0000 + +100008c8 : +100008c8: 4601 mov r1, r0 +100008ca: b5f0 push {r4, r5, r6, r7, lr} +100008cc: 6900 ldr r0, [r0, #16] +100008ce: f3ef 8710 mrs r7, PRIMASK +100008d2: b672 cpsid i +100008d4: e8d0 5fcf ldaexb r5, [r0] +100008d8: 2401 movs r4, #1 +100008da: 2d00 cmp r5, #0 +100008dc: d1fa bne.n 100008d4 +100008de: e8c0 4f45 strexb r5, r4, [r0] +100008e2: 2d00 cmp r5, #0 +100008e4: d1f6 bne.n 100008d4 +100008e6: f3bf 8f5f dmb sy +100008ea: f9b1 e002 ldrsh.w lr, [r1, #2] +100008ee: 694c ldr r4, [r1, #20] +100008f0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +100008f4: f1be 0f00 cmp.w lr, #0 +100008f8: ea4f 05cc mov.w r5, ip, lsl #3 +100008fc: 6908 ldr r0, [r1, #16] +100008fe: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000902: db3c blt.n 1000097e +10000904: 5b66 ldrh r6, [r4, r5] +10000906: 804e strh r6, [r1, #2] +10000908: 2600 movs r6, #0 +1000090a: e8c0 6f8f stlb r6, [r0] +1000090e: f387 8810 msr PRIMASK, r7 +10000912: f8bc 0002 ldrh.w r0, [ip, #2] +10000916: e9cc 2302 strd r2, r3, [ip, #8] +1000091a: 3001 adds r0, #1 +1000091c: f3c0 000e ubfx r0, r0, #0, #15 +10000920: 2801 cmp r0, #1 +10000922: bf38 it cc +10000924: 2001 movcc r0, #1 +10000926: 9b05 ldr r3, [sp, #20] +10000928: f8ac 0002 strh.w r0, [ip, #2] +1000092c: f8cc 3010 str.w r3, [ip, #16] +10000930: 9b06 ldr r3, [sp, #24] +10000932: ea40 400e orr.w r0, r0, lr, lsl #16 +10000936: f8cc 3014 str.w r3, [ip, #20] +1000093a: 690b ldr r3, [r1, #16] +1000093c: f3ef 8210 mrs r2, PRIMASK +10000940: b672 cpsid i +10000942: e8d3 cfcf ldaexb ip, [r3] +10000946: 2701 movs r7, #1 +10000948: f1bc 0f00 cmp.w ip, #0 +1000094c: d1f9 bne.n 10000942 +1000094e: e8c3 7f4c strexb ip, r7, [r3] +10000952: f1bc 0f00 cmp.w ip, #0 +10000956: d1f4 bne.n 10000942 +10000958: f3bf 8f5f dmb sy +1000095c: 888b ldrh r3, [r1, #4] +1000095e: 5363 strh r3, [r4, r5] +10000960: f8a1 e004 strh.w lr, [r1, #4] +10000964: 690b ldr r3, [r1, #16] +10000966: e8c3 6f8f stlb r6, [r3] +1000096a: f382 8810 msr PRIMASK, r2 +1000096e: 2201 movs r2, #1 +10000970: 68cb ldr r3, [r1, #12] +10000972: 7809 ldrb r1, [r1, #0] +10000974: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000978: 408a lsls r2, r1 +1000097a: 605a str r2, [r3, #4] +1000097c: bdf0 pop {r4, r5, r6, r7, pc} +1000097e: 2300 movs r3, #0 +10000980: e8c0 3f8f stlb r3, [r0] +10000984: f387 8810 msr PRIMASK, r7 +10000988: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000098c: bdf0 pop {r4, r5, r6, r7, pc} +1000098e: bf00 nop + +10000990 : +10000990: 4603 mov r3, r0 +10000992: 8940 ldrh r0, [r0, #10] +10000994: ebb0 4f21 cmp.w r0, r1, asr #16 +10000998: dd37 ble.n 10000a0a +1000099a: 6958 ldr r0, [r3, #20] +1000099c: 140a asrs r2, r1, #16 +1000099e: eb02 0242 add.w r2, r2, r2, lsl #1 +100009a2: b510 push {r4, lr} +100009a4: eb00 00c2 add.w r0, r0, r2, lsl #3 +100009a8: 691c ldr r4, [r3, #16] +100009aa: f3ef 8c10 mrs ip, PRIMASK +100009ae: b672 cpsid i +100009b0: e8d4 efcf ldaexb lr, [r4] +100009b4: 2201 movs r2, #1 +100009b6: f1be 0f00 cmp.w lr, #0 +100009ba: d1f9 bne.n 100009b0 +100009bc: e8c4 2f4e strexb lr, r2, [r4] +100009c0: f1be 0f00 cmp.w lr, #0 +100009c4: d1f4 bne.n 100009b0 +100009c6: f3bf 8f5f dmb sy +100009ca: 8842 ldrh r2, [r0, #2] +100009cc: b289 uxth r1, r1 +100009ce: b292 uxth r2, r2 +100009d0: 428a cmp r2, r1 +100009d2: d007 beq.n 100009e4 +100009d4: 2200 movs r2, #0 +100009d6: 691b ldr r3, [r3, #16] +100009d8: e8c3 2f8f stlb r2, [r3] +100009dc: f38c 8810 msr PRIMASK, ip +100009e0: 2000 movs r0, #0 +100009e2: bd10 pop {r4, pc} +100009e4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +100009e8: 8042 strh r2, [r0, #2] +100009ea: 2101 movs r1, #1 +100009ec: 2200 movs r2, #0 +100009ee: 6918 ldr r0, [r3, #16] +100009f0: 7199 strb r1, [r3, #6] +100009f2: e8c0 2f8f stlb r2, [r0] +100009f6: f38c 8810 msr PRIMASK, ip +100009fa: 781c ldrb r4, [r3, #0] +100009fc: 68da ldr r2, [r3, #12] +100009fe: 4608 mov r0, r1 +10000a00: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000a04: 40a1 lsls r1, r4 +10000a06: 6059 str r1, [r3, #4] +10000a08: bd10 pop {r4, pc} +10000a0a: 2000 movs r0, #0 +10000a0c: 4770 bx lr +10000a0e: bf00 nop + +10000a10 : +10000a10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000a14: b082 sub sp, #8 +10000a16: 4604 mov r4, r0 +10000a18: 460e mov r6, r1 +10000a1a: f000 f8e9 bl 10000bf0 +10000a1e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10000a22: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +10000a26: 1824 adds r4, r4, r0 +10000a28: eb46 0601 adc.w r6, r6, r1 +10000a2c: 42a2 cmp r2, r4 +10000a2e: eb73 0106 sbcs.w r1, r3, r6 +10000a32: bf3c itt cc +10000a34: 4614 movcc r4, r2 +10000a36: 461e movcc r6, r3 +10000a38: 1fa5 subs r5, r4, #6 +10000a3a: f146 37ff adc.w r7, r6, #4294967295 @ 0xffffffff +10000a3e: 42ac cmp r4, r5 +10000a40: eb76 0307 sbcs.w r3, r6, r7 +10000a44: bf3c itt cc +10000a46: 2500 movcc r5, #0 +10000a48: 462f movcc r7, r5 +10000a4a: f000 f8d1 bl 10000bf0 +10000a4e: 1a28 subs r0, r5, r0 +10000a50: eb67 0c01 sbc.w ip, r7, r1 +10000a54: 2801 cmp r0, #1 +10000a56: f17c 0c00 sbcs.w ip, ip, #0 +10000a5a: da06 bge.n 10000a6a +10000a5c: 4620 mov r0, r4 +10000a5e: 4631 mov r1, r6 +10000a60: b002 add sp, #8 +10000a62: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000a66: f000 b8cd b.w 10000c04 +10000a6a: f000 f8c1 bl 10000bf0 +10000a6e: 4285 cmp r5, r0 +10000a70: eb67 0101 sbc.w r1, r7, r1 +10000a74: 2900 cmp r1, #0 +10000a76: db0a blt.n 10000a8e +10000a78: 2100 movs r1, #0 +10000a7a: 4b17 ldr r3, [pc, #92] @ (10000ad8 ) +10000a7c: 462a mov r2, r5 +10000a7e: 9300 str r3, [sp, #0] +10000a80: 4816 ldr r0, [pc, #88] @ (10000adc ) +10000a82: 463b mov r3, r7 +10000a84: 9101 str r1, [sp, #4] +10000a86: f7ff ff1f bl 100008c8 +10000a8a: 3001 adds r0, #1 +10000a8c: d0e6 beq.n 10000a5c +10000a8e: f04f 0c00 mov.w ip, #0 +10000a92: 4a13 ldr r2, [pc, #76] @ (10000ae0 ) +10000a94: 4913 ldr r1, [pc, #76] @ (10000ae4 ) +10000a96: 6a53 ldr r3, [r2, #36] @ 0x24 +10000a98: 429f cmp r7, r3 +10000a9a: d804 bhi.n 10000aa6 +10000a9c: 6a90 ldr r0, [r2, #40] @ 0x28 +10000a9e: 42a8 cmp r0, r5 +10000aa0: d2dc bcs.n 10000a5c +10000aa2: 429f cmp r7, r3 +10000aa4: d1da bne.n 10000a5c +10000aa6: 680b ldr r3, [r1, #0] +10000aa8: f3ef 8010 mrs r0, PRIMASK +10000aac: b672 cpsid i +10000aae: e8d3 8fcf ldaexb r8, [r3] +10000ab2: f05f 0e01 movs.w lr, #1 +10000ab6: f1b8 0f00 cmp.w r8, #0 +10000aba: d1f8 bne.n 10000aae +10000abc: e8c3 ef48 strexb r8, lr, [r3] +10000ac0: f1b8 0f00 cmp.w r8, #0 +10000ac4: d1f3 bne.n 10000aae +10000ac6: f3bf 8f5f dmb sy +10000aca: 680b ldr r3, [r1, #0] +10000acc: e8c3 cf8f stlb ip, [r3] +10000ad0: f380 8810 msr PRIMASK, r0 +10000ad4: bf20 wfe +10000ad6: e7de b.n 10000a96 +10000ad8: 1000049d .word 0x1000049d +10000adc: 2000022c .word 0x2000022c +10000ae0: 400b0000 .word 0x400b0000 +10000ae4: 20000460 .word 0x20000460 + +10000ae8 : +10000ae8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000aec: 4606 mov r6, r0 +10000aee: 460d mov r5, r1 +10000af0: b083 sub sp, #12 +10000af2: f3ef 8405 mrs r4, IPSR +10000af6: b2e4 uxtb r4, r4 +10000af8: b13c cbz r4, 10000b0a +10000afa: 4b2d ldr r3, [pc, #180] @ (10000bb0 ) +10000afc: 6a5a ldr r2, [r3, #36] @ 0x24 +10000afe: 42aa cmp r2, r5 +10000b00: d21c bcs.n 10000b3c +10000b02: 2000 movs r0, #0 +10000b04: b003 add sp, #12 +10000b06: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b0a: 4f2a ldr r7, [pc, #168] @ (10000bb4 ) +10000b0c: f8d7 900c ldr.w r9, [r7, #12] +10000b10: f897 8000 ldrb.w r8, [r7] +10000b14: 4648 mov r0, r9 +10000b16: f000 f863 bl 10000be0 +10000b1a: f108 0804 add.w r8, r8, #4 +10000b1e: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000b22: 1a1b subs r3, r3, r0 +10000b24: 1a30 subs r0, r6, r0 +10000b26: eb65 0101 sbc.w r1, r5, r1 +10000b2a: 4298 cmp r0, r3 +10000b2c: f171 0100 sbcs.w r1, r1, #0 +10000b30: db10 blt.n 10000b54 +10000b32: bf20 wfe +10000b34: 4b1e ldr r3, [pc, #120] @ (10000bb0 ) +10000b36: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b38: 42aa cmp r2, r5 +10000b3a: d3e2 bcc.n 10000b02 +10000b3c: bf14 ite ne +10000b3e: 2401 movne r4, #1 +10000b40: 2400 moveq r4, #0 +10000b42: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b44: 42b3 cmp r3, r6 +10000b46: bf34 ite cc +10000b48: 4620 movcc r0, r4 +10000b4a: f044 0001 orrcs.w r0, r4, #1 +10000b4e: b003 add sp, #12 +10000b50: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b54: f000 f84c bl 10000bf0 +10000b58: 4286 cmp r6, r0 +10000b5a: eb65 0101 sbc.w r1, r5, r1 +10000b5e: 2900 cmp r1, #0 +10000b60: db14 blt.n 10000b8c +10000b62: 4b15 ldr r3, [pc, #84] @ (10000bb8 ) +10000b64: 4638 mov r0, r7 +10000b66: e9cd 3400 strd r3, r4, [sp] +10000b6a: 4632 mov r2, r6 +10000b6c: 462b mov r3, r5 +10000b6e: f7ff feab bl 100008c8 +10000b72: 1e01 subs r1, r0, #0 +10000b74: dd0a ble.n 10000b8c +10000b76: 4b0e ldr r3, [pc, #56] @ (10000bb0 ) +10000b78: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b7a: 42aa cmp r2, r5 +10000b7c: d316 bcc.n 10000bac +10000b7e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b80: 42b3 cmp r3, r6 +10000b82: d311 bcc.n 10000ba8 +10000b84: 480b ldr r0, [pc, #44] @ (10000bb4 ) +10000b86: f7ff ff03 bl 10000990 +10000b8a: e7b6 b.n 10000afa +10000b8c: 4b08 ldr r3, [pc, #32] @ (10000bb0 ) +10000b8e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000b90: 42ac cmp r4, r5 +10000b92: d3b6 bcc.n 10000b02 +10000b94: 1b64 subs r4, r4, r5 +10000b96: bf18 it ne +10000b98: 2401 movne r4, #1 +10000b9a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b9c: 42b3 cmp r3, r6 +10000b9e: bf34 ite cc +10000ba0: 4620 movcc r0, r4 +10000ba2: f044 0001 orrcs.w r0, r4, #1 +10000ba6: e7ad b.n 10000b04 +10000ba8: 42aa cmp r2, r5 +10000baa: d1eb bne.n 10000b84 +10000bac: bf20 wfe +10000bae: e7e9 b.n 10000b84 +10000bb0: 400b0000 .word 0x400b0000 +10000bb4: 2000022c .word 0x2000022c +10000bb8: 1000049d .word 0x1000049d + +10000bbc : +10000bbc: b410 push {r4} +10000bbe: 4b05 ldr r3, [pc, #20] @ (10000bd4 ) +10000bc0: 4c05 ldr r4, [pc, #20] @ (10000bd8 ) +10000bc2: 4a06 ldr r2, [pc, #24] @ (10000bdc ) +10000bc4: 42a0 cmp r0, r4 +10000bc6: bf14 ite ne +10000bc8: 4618 movne r0, r3 +10000bca: 1c58 addeq r0, r3, #1 +10000bcc: f85d 4b04 ldr.w r4, [sp], #4 +10000bd0: f7ff bb86 b.w 100002e0 +10000bd4: 200003f0 .word 0x200003f0 +10000bd8: 400b8000 .word 0x400b8000 +10000bdc: 100014d0 .word 0x100014d0 + +10000be0 : +10000be0: 4603 mov r3, r0 +10000be2: 6a41 ldr r1, [r0, #36] @ 0x24 +10000be4: 460a mov r2, r1 +10000be6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000be8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bea: 428a cmp r2, r1 +10000bec: d1fa bne.n 10000be4 +10000bee: 4770 bx lr + +10000bf0 : +10000bf0: 4b03 ldr r3, [pc, #12] @ (10000c00 ) +10000bf2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bf4: 460a mov r2, r1 +10000bf6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000bf8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bfa: 4291 cmp r1, r2 +10000bfc: d1fa bne.n 10000bf4 +10000bfe: 4770 bx lr +10000c00: 400b0000 .word 0x400b0000 + +10000c04 : +10000c04: 4a07 ldr r2, [pc, #28] @ (10000c24 ) +10000c06: 6a53 ldr r3, [r2, #36] @ 0x24 +10000c08: 4299 cmp r1, r3 +10000c0a: d8fc bhi.n 10000c06 +10000c0c: 4299 cmp r1, r3 +10000c0e: d107 bne.n 10000c20 +10000c10: 4b04 ldr r3, [pc, #16] @ (10000c24 ) +10000c12: e002 b.n 10000c1a +10000c14: 6a5a ldr r2, [r3, #36] @ 0x24 +10000c16: 4291 cmp r1, r2 +10000c18: d102 bne.n 10000c20 +10000c1a: 6a9a ldr r2, [r3, #40] @ 0x28 +10000c1c: 4290 cmp r0, r2 +10000c1e: d8f9 bhi.n 10000c14 +10000c20: 4770 bx lr +10000c22: bf00 nop +10000c24: 400b0000 .word 0x400b0000 + +10000c28 : +10000c28: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000c2c: ea4f 0c8c mov.w ip, ip, lsl #2 +10000c30: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000c34: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000c38: b5f0 push {r4, r5, r6, r7, lr} +10000c3a: 4616 mov r6, r2 +10000c3c: f8dc 2004 ldr.w r2, [ip, #4] +10000c40: 1f05 subs r5, r0, #4 +10000c42: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000c46: bf38 it cc +10000c48: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000c4c: b2ed uxtb r5, r5 +10000c4e: bf38 it cc +10000c50: f8cc 2004 strcc.w r2, [ip, #4] +10000c54: 2d01 cmp r5, #1 +10000c56: d92a bls.n 10000cae +10000c58: f44f 6700 mov.w r7, #2048 @ 0x800 +10000c5c: 4c25 ldr r4, [pc, #148] @ (10000cf4 ) +10000c5e: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000c62: 6017 str r7, [r2, #0] +10000c64: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000c68: b9b2 cbnz r2, 10000c98 +10000c6a: f8dc 2000 ldr.w r2, [ip] +10000c6e: 2d01 cmp r5, #1 +10000c70: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000c74: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000c78: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000c7c: 6032 str r2, [r6, #0] +10000c7e: d92a bls.n 10000cd6 +10000c80: f44f 6100 mov.w r1, #2048 @ 0x800 +10000c84: f844 3020 str.w r3, [r4, r0, lsl #2] +10000c88: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000c8c: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000c90: 6011 str r1, [r2, #0] +10000c92: f8cc 3004 str.w r3, [ip, #4] +10000c96: bdf0 pop {r4, r5, r6, r7, pc} +10000c98: 6967 ldr r7, [r4, #20] +10000c9a: fbb7 fef2 udiv lr, r7, r2 +10000c9e: f10e 0e01 add.w lr, lr, #1 +10000ca2: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000ca6: f1be 0e03 subs.w lr, lr, #3 +10000caa: d2fc bcs.n 10000ca6 +10000cac: e7dd b.n 10000c6a +10000cae: 2901 cmp r1, #1 +10000cb0: d1d2 bne.n 10000c58 +10000cb2: 2403 movs r4, #3 +10000cb4: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000cb8: 6014 str r4, [r2, #0] +10000cba: f8dc 2008 ldr.w r2, [ip, #8] +10000cbe: 07d2 lsls r2, r2, #31 +10000cc0: d5fb bpl.n 10000cba +10000cc2: f8dc 2000 ldr.w r2, [ip] +10000cc6: 4c0b ldr r4, [pc, #44] @ (10000cf4 ) +10000cc8: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000ccc: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000cd0: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000cd4: 6032 str r2, [r6, #0] +10000cd6: 2201 movs r2, #1 +10000cd8: f8dc 5000 ldr.w r5, [ip] +10000cdc: 404d eors r5, r1 +10000cde: f005 0503 and.w r5, r5, #3 +10000ce2: 6035 str r5, [r6, #0] +10000ce4: fa02 f101 lsl.w r1, r2, r1 +10000ce8: f8dc 2008 ldr.w r2, [ip, #8] +10000cec: 420a tst r2, r1 +10000cee: d0fb beq.n 10000ce8 +10000cf0: e7c6 b.n 10000c80 +10000cf2: bf00 nop +10000cf4: 200003f4 .word 0x200003f4 + +10000cf8 : +10000cf8: 4b01 ldr r3, [pc, #4] @ (10000d00 ) +10000cfa: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000cfe: 4770 bx lr +10000d00: 200003f4 .word 0x200003f4 + +10000d04 : +10000d04: b470 push {r4, r5, r6} +10000d06: 9d03 ldr r5, [sp, #12] +10000d08: 6804 ldr r4, [r0, #0] +10000d0a: 032d lsls r5, r5, #12 +10000d0c: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000d10: 4b1b ldr r3, [pc, #108] @ (10000d80 ) +10000d12: 2c00 cmp r4, #0 +10000d14: fbb3 f3f1 udiv r3, r3, r1 +10000d18: fbb2 f6f3 udiv r6, r2, r3 +10000d1c: db1f blt.n 10000d5e +10000d1e: 4a19 ldr r2, [pc, #100] @ (10000d84 ) +10000d20: 4b19 ldr r3, [pc, #100] @ (10000d88 ) +10000d22: 4290 cmp r0, r2 +10000d24: bf14 ite ne +10000d26: f44f 4280 movne.w r2, #16384 @ 0x4000 +10000d2a: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10000d2e: 4c17 ldr r4, [pc, #92] @ (10000d8c ) +10000d30: 601a str r2, [r3, #0] +10000d32: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000d36: 601a str r2, [r3, #0] +10000d38: 68a3 ldr r3, [r4, #8] +10000d3a: ea32 0303 bics.w r3, r2, r3 +10000d3e: d1fb bne.n 10000d38 +10000d40: 2221 movs r2, #33 @ 0x21 +10000d42: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10000d46: 3304 adds r3, #4 +10000d48: 6001 str r1, [r0, #0] +10000d4a: 6086 str r6, [r0, #8] +10000d4c: 601a str r2, [r3, #0] +10000d4e: 6802 ldr r2, [r0, #0] +10000d50: 2a00 cmp r2, #0 +10000d52: dafc bge.n 10000d4e +10000d54: 2208 movs r2, #8 +10000d56: 60c5 str r5, [r0, #12] +10000d58: 601a str r2, [r3, #0] +10000d5a: bc70 pop {r4, r5, r6} +10000d5c: 4770 bx lr +10000d5e: 6803 ldr r3, [r0, #0] +10000d60: f003 033f and.w r3, r3, #63 @ 0x3f +10000d64: 428b cmp r3, r1 +10000d66: d1da bne.n 10000d1e +10000d68: 6883 ldr r3, [r0, #8] +10000d6a: f3c3 030b ubfx r3, r3, #0, #12 +10000d6e: 42b3 cmp r3, r6 +10000d70: d1d5 bne.n 10000d1e +10000d72: 68c3 ldr r3, [r0, #12] +10000d74: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10000d78: 42ab cmp r3, r5 +10000d7a: d1d0 bne.n 10000d1e +10000d7c: e7ed b.n 10000d5a +10000d7e: bf00 nop +10000d80: 00b71b00 .word 0x00b71b00 +10000d84: 40058000 .word 0x40058000 +10000d88: 40022000 .word 0x40022000 +10000d8c: 40020000 .word 0x40020000 + +10000d90 : +10000d90: 2301 movs r3, #1 +10000d92: eb00 0040 add.w r0, r0, r0, lsl #1 +10000d96: 0080 lsls r0, r0, #2 +10000d98: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000d9c: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10000da0: 6041 str r1, [r0, #4] +10000da2: 6003 str r3, [r0, #0] +10000da4: 4770 bx lr +10000da6: bf00 nop + +10000da8 : +10000da8: 2300 movs r3, #0 +10000daa: 8adb ldrh r3, [r3, #22] +10000dac: 2200 movs r2, #0 +10000dae: e842 f200 tt r2, r2 +10000db2: 0252 lsls r2, r2, #9 +10000db4: d401 bmi.n 10000dba +10000db6: 2110 movs r1, #16 +10000db8: 4718 bx r3 +10000dba: 2104 movs r1, #4 +10000dbc: 4718 bx r3 +10000dbe: bf00 nop + +10000dc0 : +10000dc0: 4a03 ldr r2, [pc, #12] @ (10000dd0 ) +10000dc2: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10000dc6: 2b00 cmp r3, #0 +10000dc8: d0fb beq.n 10000dc2 +10000dca: f3bf 8f5f dmb sy +10000dce: 4770 bx lr +10000dd0: 400e0000 .word 0x400e0000 + +10000dd4 : +10000dd4: 2100 movs r1, #0 +10000dd6: 4b04 ldr r3, [pc, #16] @ (10000de8 ) +10000dd8: 4a04 ldr r2, [pc, #16] @ (10000dec ) +10000dda: f3bf 8f5f dmb sy +10000dde: f843 1b04 str.w r1, [r3], #4 +10000de2: 4293 cmp r3, r2 +10000de4: d1f9 bne.n 10000dda +10000de6: 4770 bx lr +10000de8: 400e080c .word 0x400e080c +10000dec: 400e082c .word 0x400e082c + +10000df0 : +10000df0: b410 push {r4} +10000df2: f44f 708d mov.w r0, #282 @ 0x11a +10000df6: f44f 642a mov.w r4, #2720 @ 0xaa0 +10000dfa: 4a06 ldr r2, [pc, #24] @ (10000e14 ) +10000dfc: 4b06 ldr r3, [pc, #24] @ (10000e18 ) +10000dfe: 4907 ldr r1, [pc, #28] @ (10000e1c ) +10000e00: 6014 str r4, [r2, #0] +10000e02: 60d0 str r0, [r2, #12] +10000e04: 6019 str r1, [r3, #0] +10000e06: 6853 ldr r3, [r2, #4] +10000e08: 2b00 cmp r3, #0 +10000e0a: dafc bge.n 10000e06 +10000e0c: f85d 4b04 ldr.w r4, [sp], #4 +10000e10: 4770 bx lr +10000e12: bf00 nop +10000e14: 40048000 .word 0x40048000 +10000e18: 4004a000 .word 0x4004a000 +10000e1c: 00fab000 .word 0x00fab000 + +10000e20 : +10000e20: 4770 bx lr +10000e22: bf00 nop + +10000e24 : +10000e24: b508 push {r3, lr} +10000e26: 4801 ldr r0, [pc, #4] @ (10000e2c ) +10000e28: f7ff fa42 bl 100002b0 +10000e2c: 100014f4 .word 0x100014f4 + +10000e30 : +10000e30: b538 push {r3, r4, r5, lr} +10000e32: 4c05 ldr r4, [pc, #20] @ (10000e48 ) +10000e34: 4d05 ldr r5, [pc, #20] @ (10000e4c ) +10000e36: 42ac cmp r4, r5 +10000e38: d204 bcs.n 10000e44 +10000e3a: f854 3b04 ldr.w r3, [r4], #4 +10000e3e: 4798 blx r3 +10000e40: 42ac cmp r4, r5 +10000e42: d3fa bcc.n 10000e3a +10000e44: bd38 pop {r3, r4, r5, pc} +10000e46: bf00 nop +10000e48: 10001478 .word 0x10001478 +10000e4c: 100014b8 .word 0x100014b8 + +10000e50 : +10000e50: b410 push {r4} +10000e52: 4807 ldr r0, [pc, #28] @ (10000e70 ) +10000e54: 4c07 ldr r4, [pc, #28] @ (10000e74 ) +10000e56: 4b08 ldr r3, [pc, #32] @ (10000e78 ) +10000e58: 4a08 ldr r2, [pc, #32] @ (10000e7c ) +10000e5a: 4909 ldr r1, [pc, #36] @ (10000e80 ) +10000e5c: 6004 str r4, [r0, #0] +10000e5e: 601a str r2, [r3, #0] +10000e60: 688b ldr r3, [r1, #8] +10000e62: ea32 0303 bics.w r3, r2, r3 +10000e66: d1fb bne.n 10000e60 +10000e68: f85d 4b04 ldr.w r4, [sp], #4 +10000e6c: 4770 bx lr +10000e6e: bf00 nop +10000e70: 40022000 .word 0x40022000 +10000e74: efef3b7f .word 0xefef3b7f +10000e78: 40023000 .word 0x40023000 +10000e7c: 03f3fff6 .word 0x03f3fff6 +10000e80: 40020000 .word 0x40020000 + +10000e84 : +10000e84: 4b04 ldr r3, [pc, #16] @ (10000e98 ) +10000e86: 6cdb ldr r3, [r3, #76] @ 0x4c +10000e88: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10000e8c: d103 bne.n 10000e96 +10000e8e: f44f 2280 mov.w r2, #262144 @ 0x40000 +10000e92: 4b02 ldr r3, [pc, #8] @ (10000e9c ) +10000e94: 64da str r2, [r3, #76] @ 0x4c +10000e96: 4770 bx lr +10000e98: 50110000 .word 0x50110000 +10000e9c: 50112000 .word 0x50112000 + +10000ea0 : +10000ea0: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000ea4: 4b04 ldr r3, [pc, #16] @ (10000eb8 ) +10000ea6: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10000eaa: 430b orrs r3, r1 +10000eac: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10000eb0: ee10 0430 dcp_rcmp r0 +10000eb4: 4770 bx lr +10000eb6: bf00 nop +10000eb8: 00300303 .word 0x00300303 + +10000ebc : +10000ebc: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10000ec0: 4b04 ldr r3, [pc, #16] @ (10000ed4 ) +10000ec2: 4a05 ldr r2, [pc, #20] @ (10000ed8 ) +10000ec4: 6019 str r1, [r3, #0] +10000ec6: 6893 ldr r3, [r2, #8] +10000ec8: 43db mvns r3, r3 +10000eca: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10000ece: d1fa bne.n 10000ec6 +10000ed0: 4770 bx lr +10000ed2: bf00 nop +10000ed4: 40023000 .word 0x40023000 +10000ed8: 40020000 .word 0x40020000 + +10000edc : +10000edc: b510 push {r4, lr} +10000ede: f245 2053 movw r0, #21075 @ 0x5253 +10000ee2: f7ff ff61 bl 10000da8 +10000ee6: e8bd 4010 ldmia.w sp!, {r4, lr} +10000eea: 4603 mov r3, r0 +10000eec: 2004 movs r0, #4 +10000eee: 4718 bx r3 + +10000ef0 : +10000ef0: b510 push {r4, lr} +10000ef2: f245 2053 movw r0, #21075 @ 0x5253 +10000ef6: f7ff ff57 bl 10000da8 +10000efa: e8bd 4010 ldmia.w sp!, {r4, lr} +10000efe: 4603 mov r3, r0 +10000f00: 2001 movs r0, #1 +10000f02: 4718 bx r3 + +10000f04 : +10000f04: f7ff ba2c b.w 10000360 + +10000f08 : +10000f08: 4914 ldr r1, [pc, #80] @ (10000f5c ) +10000f0a: 4b15 ldr r3, [pc, #84] @ (10000f60 ) +10000f0c: b570 push {r4, r5, r6, lr} +10000f0e: 1a5c subs r4, r3, r1 +10000f10: 10a6 asrs r6, r4, #2 +10000f12: 2e44 cmp r6, #68 @ 0x44 +10000f14: 4632 mov r2, r6 +10000f16: bf28 it cs +10000f18: 2244 movcs r2, #68 @ 0x44 +10000f1a: 4d12 ldr r5, [pc, #72] @ (10000f64 ) +10000f1c: 0092 lsls r2, r2, #2 +10000f1e: 4628 mov r0, r5 +10000f20: f000 f9fa bl 10001318 +10000f24: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10000f28: d813 bhi.n 10000f52 +10000f2a: 4a0f ldr r2, [pc, #60] @ (10000f68 ) +10000f2c: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10000f30: d012 beq.n 10000f58 +10000f32: 192b adds r3, r5, r4 +10000f34: 0841 lsrs r1, r0, #1 +10000f36: eb03 01c1 add.w r1, r3, r1, lsl #3 +10000f3a: e9c3 2200 strd r2, r2, [r3] +10000f3e: 3308 adds r3, #8 +10000f40: 428b cmp r3, r1 +10000f42: d1fa bne.n 10000f3a +10000f44: 07c3 lsls r3, r0, #31 +10000f46: d504 bpl.n 10000f52 +10000f48: f020 0001 bic.w r0, r0, #1 +10000f4c: 4430 add r0, r6 +10000f4e: f845 2020 str.w r2, [r5, r0, lsl #2] +10000f52: 4b06 ldr r3, [pc, #24] @ (10000f6c ) +10000f54: 609d str r5, [r3, #8] +10000f56: bd70 pop {r4, r5, r6, pc} +10000f58: 2043 movs r0, #67 @ 0x43 +10000f5a: e7f8 b.n 10000f4e +10000f5c: 10000000 .word 0x10000000 +10000f60: 10000110 .word 0x10000110 +10000f64: 20000000 .word 0x20000000 +10000f68: 10000111 .word 0x10000111 +10000f6c: e000ed00 .word 0xe000ed00 + +10000f70 : +10000f70: 2300 movs r3, #0 +10000f72: b570 push {r4, r5, r6, lr} +10000f74: 4c2b ldr r4, [pc, #172] @ (10001024 ) +10000f76: b082 sub sp, #8 +10000f78: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10000f7c: f7ff ff38 bl 10000df0 +10000f80: 2201 movs r2, #1 +10000f82: 4b29 ldr r3, [pc, #164] @ (10001028 ) +10000f84: 63da str r2, [r3, #60] @ 0x3c +10000f86: 6c63 ldr r3, [r4, #68] @ 0x44 +10000f88: 2b01 cmp r3, #1 +10000f8a: d1fc bne.n 10000f86 +10000f8c: 2103 movs r1, #3 +10000f8e: 4a26 ldr r2, [pc, #152] @ (10001028 ) +10000f90: 4b24 ldr r3, [pc, #144] @ (10001024 ) +10000f92: 6311 str r1, [r2, #48] @ 0x30 +10000f94: 6b9c ldr r4, [r3, #56] @ 0x38 +10000f96: 2c01 cmp r4, #1 +10000f98: d1fc bne.n 10000f94 +10000f9a: 2602 movs r6, #2 +10000f9c: 2505 movs r5, #5 +10000f9e: 4621 mov r1, r4 +10000fa0: 2305 movs r3, #5 +10000fa2: 4a22 ldr r2, [pc, #136] @ (1000102c ) +10000fa4: 4822 ldr r0, [pc, #136] @ (10001030 ) +10000fa6: 9600 str r6, [sp, #0] +10000fa8: f7ff feac bl 10000d04 +10000fac: 4621 mov r1, r4 +10000fae: 462b mov r3, r5 +10000fb0: 4a20 ldr r2, [pc, #128] @ (10001034 ) +10000fb2: 4821 ldr r0, [pc, #132] @ (10001038 ) +10000fb4: 9500 str r5, [sp, #0] +10000fb6: f7ff fea5 bl 10000d04 +10000fba: 2200 movs r2, #0 +10000fbc: 2004 movs r0, #4 +10000fbe: 4631 mov r1, r6 +10000fc0: 4b1e ldr r3, [pc, #120] @ (1000103c ) +10000fc2: f7ff fe31 bl 10000c28 +10000fc6: 4621 mov r1, r4 +10000fc8: 4628 mov r0, r5 +10000fca: 2200 movs r2, #0 +10000fcc: 4b1c ldr r3, [pc, #112] @ (10001040 ) +10000fce: f7ff fe2b bl 10000c28 +10000fd2: 2200 movs r2, #0 +10000fd4: 2008 movs r0, #8 +10000fd6: 4611 mov r1, r2 +10000fd8: 4b1a ldr r3, [pc, #104] @ (10001044 ) +10000fda: f7ff fe25 bl 10000c28 +10000fde: 2200 movs r2, #0 +10000fe0: 2009 movs r0, #9 +10000fe2: 4611 mov r1, r2 +10000fe4: 4b17 ldr r3, [pc, #92] @ (10001044 ) +10000fe6: f7ff fe1f bl 10000c28 +10000fea: 2200 movs r2, #0 +10000fec: 2006 movs r0, #6 +10000fee: 4611 mov r1, r2 +10000ff0: 4b13 ldr r3, [pc, #76] @ (10001040 ) +10000ff2: f7ff fe19 bl 10000c28 +10000ff6: 2200 movs r2, #0 +10000ff8: 4b11 ldr r3, [pc, #68] @ (10001040 ) +10000ffa: 2007 movs r0, #7 +10000ffc: 4611 mov r1, r2 +10000ffe: f7ff fe13 bl 10000c28 +10001002: 2004 movs r0, #4 +10001004: f7ff fe78 bl 10000cf8 +10001008: 2400 movs r4, #0 +1000100a: 4b0f ldr r3, [pc, #60] @ (10001048 ) +1000100c: fba3 3500 umull r3, r5, r3, r0 +10001010: 0cad lsrs r5, r5, #18 +10001012: b2e0 uxtb r0, r4 +10001014: 4629 mov r1, r5 +10001016: 3401 adds r4, #1 +10001018: f7ff feba bl 10000d90 +1000101c: 2c06 cmp r4, #6 +1000101e: d1f8 bne.n 10001012 +10001020: b002 add sp, #8 +10001022: bd70 pop {r4, r5, r6, pc} +10001024: 40010000 .word 0x40010000 +10001028: 40013000 .word 0x40013000 +1000102c: 59682f00 .word 0x59682f00 +10001030: 40050000 .word 0x40050000 +10001034: 47868c00 .word 0x47868c00 +10001038: 40058000 .word 0x40058000 +1000103c: 00b71b00 .word 0x00b71b00 +10001040: 08f0d180 .word 0x08f0d180 +10001044: 02dc6c00 .word 0x02dc6c00 +10001048: 431bde83 .word 0x431bde83 + +1000104c <_out_char>: +1000104c: b900 cbnz r0, 10001050 <_out_char+0x4> +1000104e: 4770 bx lr +10001050: f000 b902 b.w 10001258 <__wrap_putchar> + +10001054 : +10001054: b510 push {r4, lr} +10001056: 4b09 ldr r3, [pc, #36] @ (1000107c ) +10001058: b084 sub sp, #16 +1000105a: 681c ldr r4, [r3, #0] +1000105c: b14c cbz r4, 10001072 +1000105e: 4603 mov r3, r0 +10001060: 9100 str r1, [sp, #0] +10001062: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001066: a903 add r1, sp, #12 +10001068: 4805 ldr r0, [pc, #20] @ (10001080 ) +1000106a: 47a0 blx r4 +1000106c: 2001 movs r0, #1 +1000106e: b004 add sp, #16 +10001070: bd10 pop {r4, pc} +10001072: f000 f933 bl 100012dc <__wrap_puts> +10001076: 4620 mov r0, r4 +10001078: b004 add sp, #16 +1000107a: bd10 pop {r4, pc} +1000107c: 20000424 .word 0x20000424 +10001080: 1000104d .word 0x1000104d + +10001084 <_exit>: +10001084: be00 bkpt 0x0000 +10001086: e7fd b.n 10001084 <_exit> + +10001088 : +10001088: b508 push {r3, lr} +1000108a: f7ff fffb bl 10001084 <_exit> +1000108e: bf00 nop + +10001090 : +10001090: b538 push {r3, r4, r5, lr} +10001092: 4c06 ldr r4, [pc, #24] @ (100010ac ) +10001094: 4d06 ldr r5, [pc, #24] @ (100010b0 ) +10001096: f7ff fecb bl 10000e30 +1000109a: 42ac cmp r4, r5 +1000109c: d204 bcs.n 100010a8 +1000109e: f854 3b04 ldr.w r3, [r4], #4 +100010a2: 4798 blx r3 +100010a4: 42ac cmp r4, r5 +100010a6: d3fa bcc.n 1000109e +100010a8: bd38 pop {r3, r4, r5, pc} +100010aa: bf00 nop +100010ac: 100014b8 .word 0x100014b8 +100010b0: 100014bc .word 0x100014bc + +100010b4 : +100010b4: 6803 ldr r3, [r0, #0] +100010b6: 4608 mov r0, r1 +100010b8: 4611 mov r1, r2 +100010ba: 4718 bx r3 + +100010bc : +100010bc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100010c0: 4615 mov r5, r2 +100010c2: 7d42 ldrb r2, [r0, #21] +100010c4: 4607 mov r7, r0 +100010c6: 4688 mov r8, r1 +100010c8: 2a00 cmp r2, #0 +100010ca: d046 beq.n 1000115a +100010cc: 2d00 cmp r5, #0 +100010ce: dd1d ble.n 1000110c +100010d0: 780b ldrb r3, [r1, #0] +100010d2: 2b0a cmp r3, #10 +100010d4: d023 beq.n 1000111e +100010d6: 2d01 cmp r5, #1 +100010d8: f04f 0c00 mov.w ip, #0 +100010dc: d018 beq.n 10001110 +100010de: 4646 mov r6, r8 +100010e0: 2401 movs r4, #1 +100010e2: f816 2f01 ldrb.w r2, [r6, #1]! +100010e6: 4621 mov r1, r4 +100010e8: 2a0a cmp r2, #10 +100010ea: f104 0401 add.w r4, r4, #1 +100010ee: d022 beq.n 10001136 +100010f0: 42a5 cmp r5, r4 +100010f2: d1f6 bne.n 100010e2 +100010f4: 4565 cmp r5, ip +100010f6: dc0b bgt.n 10001110 +100010f8: eb08 0305 add.w r3, r8, r5 +100010fc: f813 3c01 ldrb.w r3, [r3, #-1] +10001100: f1a3 030d sub.w r3, r3, #13 +10001104: fab3 f383 clz r3, r3 +10001108: 095b lsrs r3, r3, #5 +1000110a: 753b strb r3, [r7, #20] +1000110c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10001110: 683b ldr r3, [r7, #0] +10001112: eba5 010c sub.w r1, r5, ip +10001116: eb08 000c add.w r0, r8, ip +1000111a: 4798 blx r3 +1000111c: e7ec b.n 100010f8 +1000111e: 7d03 ldrb r3, [r0, #20] +10001120: 2b00 cmp r3, #0 +10001122: d1d8 bne.n 100010d6 +10001124: 6803 ldr r3, [r0, #0] +10001126: 2102 movs r1, #2 +10001128: 480f ldr r0, [pc, #60] @ (10001168 ) +1000112a: 4798 blx r3 +1000112c: 2d01 cmp r5, #1 +1000112e: d0e3 beq.n 100010f8 +10001130: f04f 0c01 mov.w ip, #1 +10001134: e7d3 b.n 100010de +10001136: f816 3c01 ldrb.w r3, [r6, #-1] +1000113a: 2b0d cmp r3, #13 +1000113c: d0d8 beq.n 100010f0 +1000113e: 458c cmp ip, r1 +10001140: eb08 000c add.w r0, r8, ip +10001144: eba1 010c sub.w r1, r1, ip +10001148: da01 bge.n 1000114e +1000114a: 683b ldr r3, [r7, #0] +1000114c: 4798 blx r3 +1000114e: 2102 movs r1, #2 +10001150: 4805 ldr r0, [pc, #20] @ (10001168 ) +10001152: 683b ldr r3, [r7, #0] +10001154: 4798 blx r3 +10001156: 46a4 mov ip, r4 +10001158: e7ca b.n 100010f0 +1000115a: 4629 mov r1, r5 +1000115c: 4640 mov r0, r8 +1000115e: 683b ldr r3, [r7, #0] +10001160: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001164: 4718 bx r3 +10001166: bf00 nop +10001168: 100015bc .word 0x100015bc + +1000116c : +1000116c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10001170: b082 sub sp, #8 +10001172: 460d mov r5, r1 +10001174: 4691 mov r9, r2 +10001176: 461c mov r4, r3 +10001178: 4606 mov r6, r0 +1000117a: f7ff fd39 bl 10000bf0 +1000117e: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10001182: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001186: 4a2e ldr r2, [pc, #184] @ (10001240 ) +10001188: 1882 adds r2, r0, r2 +1000118a: f141 0300 adc.w r3, r1, #0 +1000118e: 4594 cmp ip, r2 +10001190: eb77 0103 sbcs.w r1, r7, r3 +10001194: bf3c itt cc +10001196: 4662 movcc r2, ip +10001198: 463b movcc r3, r7 +1000119a: 482a ldr r0, [pc, #168] @ (10001244 ) +1000119c: f000 f968 bl 10001470 <__mutex_try_enter_block_until_veneer> +100011a0: 1c6b adds r3, r5, #1 +100011a2: 4680 mov r8, r0 +100011a4: d040 beq.n 10001228 +100011a6: b30c cbz r4, 100011ec +100011a8: 4f27 ldr r7, [pc, #156] @ (10001248 ) +100011aa: 4b28 ldr r3, [pc, #160] @ (1000124c ) +100011ac: 681c ldr r4, [r3, #0] +100011ae: b1b4 cbz r4, 100011de +100011b0: f1b9 0f00 cmp.w r9, #0 +100011b4: d11c bne.n 100011f0 +100011b6: f8df 909c ldr.w r9, [pc, #156] @ 10001254 +100011ba: e001 b.n 100011c0 +100011bc: 6924 ldr r4, [r4, #16] +100011be: b174 cbz r4, 100011de +100011c0: 6823 ldr r3, [r4, #0] +100011c2: 2b00 cmp r3, #0 +100011c4: d0fa beq.n 100011bc +100011c6: f8d9 3000 ldr.w r3, [r9] +100011ca: b10b cbz r3, 100011d0 +100011cc: 429c cmp r4, r3 +100011ce: d1f5 bne.n 100011bc +100011d0: 4620 mov r0, r4 +100011d2: 462a mov r2, r5 +100011d4: 4631 mov r1, r6 +100011d6: 47b8 blx r7 +100011d8: 6924 ldr r4, [r4, #16] +100011da: 2c00 cmp r4, #0 +100011dc: d1f0 bne.n 100011c0 +100011de: f1b8 0f00 cmp.w r8, #0 +100011e2: d126 bne.n 10001232 +100011e4: 4628 mov r0, r5 +100011e6: b002 add sp, #8 +100011e8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100011ec: 4f18 ldr r7, [pc, #96] @ (10001250 ) +100011ee: e7dc b.n 100011aa +100011f0: f04f 0a0a mov.w sl, #10 +100011f4: f8df 905c ldr.w r9, [pc, #92] @ 10001254 +100011f8: e002 b.n 10001200 +100011fa: 6924 ldr r4, [r4, #16] +100011fc: 2c00 cmp r4, #0 +100011fe: d0ee beq.n 100011de +10001200: 6823 ldr r3, [r4, #0] +10001202: 2b00 cmp r3, #0 +10001204: d0f9 beq.n 100011fa +10001206: f8d9 3000 ldr.w r3, [r9] +1000120a: b10b cbz r3, 10001210 +1000120c: 42a3 cmp r3, r4 +1000120e: d1f4 bne.n 100011fa +10001210: 462a mov r2, r5 +10001212: 4631 mov r1, r6 +10001214: 4620 mov r0, r4 +10001216: 47b8 blx r7 +10001218: 2201 movs r2, #1 +1000121a: 4620 mov r0, r4 +1000121c: f10d 0107 add.w r1, sp, #7 +10001220: f88d a007 strb.w sl, [sp, #7] +10001224: 47b8 blx r7 +10001226: e7e8 b.n 100011fa +10001228: 4630 mov r0, r6 +1000122a: f000 f8eb bl 10001404 +1000122e: 4605 mov r5, r0 +10001230: e7b9 b.n 100011a6 +10001232: 4804 ldr r0, [pc, #16] @ (10001244 ) +10001234: f000 f918 bl 10001468 <__mutex_exit_veneer> +10001238: 4628 mov r0, r5 +1000123a: b002 add sp, #8 +1000123c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001240: 000f4240 .word 0x000f4240 +10001244: 20000244 .word 0x20000244 +10001248: 100010bd .word 0x100010bd +1000124c: 2000041c .word 0x2000041c +10001250: 100010b5 .word 0x100010b5 +10001254: 20000420 .word 0x20000420 + +10001258 <__wrap_putchar>: +10001258: b5f0 push {r4, r5, r6, r7, lr} +1000125a: b083 sub sp, #12 +1000125c: 4606 mov r6, r0 +1000125e: f88d 0007 strb.w r0, [sp, #7] +10001262: f7ff fcc5 bl 10000bf0 +10001266: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000126a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000126e: 4a17 ldr r2, [pc, #92] @ (100012cc <__wrap_putchar+0x74>) +10001270: 1882 adds r2, r0, r2 +10001272: f141 0300 adc.w r3, r1, #0 +10001276: 4295 cmp r5, r2 +10001278: eb74 0103 sbcs.w r1, r4, r3 +1000127c: bf3c itt cc +1000127e: 4623 movcc r3, r4 +10001280: 462a movcc r2, r5 +10001282: 4813 ldr r0, [pc, #76] @ (100012d0 <__wrap_putchar+0x78>) +10001284: f000 f8f4 bl 10001470 <__mutex_try_enter_block_until_veneer> +10001288: 4b12 ldr r3, [pc, #72] @ (100012d4 <__wrap_putchar+0x7c>) +1000128a: 4607 mov r7, r0 +1000128c: 681c ldr r4, [r3, #0] +1000128e: b19c cbz r4, 100012b8 <__wrap_putchar+0x60> +10001290: 4d11 ldr r5, [pc, #68] @ (100012d8 <__wrap_putchar+0x80>) +10001292: e001 b.n 10001298 <__wrap_putchar+0x40> +10001294: 6924 ldr r4, [r4, #16] +10001296: b17c cbz r4, 100012b8 <__wrap_putchar+0x60> +10001298: 6823 ldr r3, [r4, #0] +1000129a: 2b00 cmp r3, #0 +1000129c: d0fa beq.n 10001294 <__wrap_putchar+0x3c> +1000129e: 682b ldr r3, [r5, #0] +100012a0: b10b cbz r3, 100012a6 <__wrap_putchar+0x4e> +100012a2: 429c cmp r4, r3 +100012a4: d1f6 bne.n 10001294 <__wrap_putchar+0x3c> +100012a6: 4620 mov r0, r4 +100012a8: 2201 movs r2, #1 +100012aa: f10d 0107 add.w r1, sp, #7 +100012ae: f7ff ff05 bl 100010bc +100012b2: 6924 ldr r4, [r4, #16] +100012b4: 2c00 cmp r4, #0 +100012b6: d1ef bne.n 10001298 <__wrap_putchar+0x40> +100012b8: b917 cbnz r7, 100012c0 <__wrap_putchar+0x68> +100012ba: 4630 mov r0, r6 +100012bc: b003 add sp, #12 +100012be: bdf0 pop {r4, r5, r6, r7, pc} +100012c0: 4803 ldr r0, [pc, #12] @ (100012d0 <__wrap_putchar+0x78>) +100012c2: f000 f8d1 bl 10001468 <__mutex_exit_veneer> +100012c6: 4630 mov r0, r6 +100012c8: b003 add sp, #12 +100012ca: bdf0 pop {r4, r5, r6, r7, pc} +100012cc: 000f4240 .word 0x000f4240 +100012d0: 20000244 .word 0x20000244 +100012d4: 2000041c .word 0x2000041c +100012d8: 20000420 .word 0x20000420 + +100012dc <__wrap_puts>: +100012dc: b538 push {r3, r4, r5, lr} +100012de: 4604 mov r4, r0 +100012e0: f000 f890 bl 10001404 +100012e4: 2301 movs r3, #1 +100012e6: 4605 mov r5, r0 +100012e8: 461a mov r2, r3 +100012ea: 4620 mov r0, r4 +100012ec: 4629 mov r1, r5 +100012ee: f7ff ff3d bl 1000116c +100012f2: 4b08 ldr r3, [pc, #32] @ (10001314 <__wrap_puts+0x38>) +100012f4: 681c ldr r4, [r3, #0] +100012f6: b12c cbz r4, 10001304 <__wrap_puts+0x28> +100012f8: 6863 ldr r3, [r4, #4] +100012fa: b12b cbz r3, 10001308 <__wrap_puts+0x2c> +100012fc: 4798 blx r3 +100012fe: 6924 ldr r4, [r4, #16] +10001300: 2c00 cmp r4, #0 +10001302: d1f9 bne.n 100012f8 <__wrap_puts+0x1c> +10001304: 4628 mov r0, r5 +10001306: bd38 pop {r3, r4, r5, pc} +10001308: 6924 ldr r4, [r4, #16] +1000130a: 2c00 cmp r4, #0 +1000130c: d1f4 bne.n 100012f8 <__wrap_puts+0x1c> +1000130e: 4628 mov r0, r5 +10001310: bd38 pop {r3, r4, r5, pc} +10001312: bf00 nop +10001314: 2000041c .word 0x2000041c + +10001318 : +10001318: 4684 mov ip, r0 +1000131a: ea41 0300 orr.w r3, r1, r0 +1000131e: f013 0303 ands.w r3, r3, #3 +10001322: d149 bne.n 100013b8 +10001324: 3a40 subs r2, #64 @ 0x40 +10001326: d323 bcc.n 10001370 +10001328: 680b ldr r3, [r1, #0] +1000132a: 6003 str r3, [r0, #0] +1000132c: 684b ldr r3, [r1, #4] +1000132e: 6043 str r3, [r0, #4] +10001330: 688b ldr r3, [r1, #8] +10001332: 6083 str r3, [r0, #8] +10001334: 68cb ldr r3, [r1, #12] +10001336: 60c3 str r3, [r0, #12] +10001338: 690b ldr r3, [r1, #16] +1000133a: 6103 str r3, [r0, #16] +1000133c: 694b ldr r3, [r1, #20] +1000133e: 6143 str r3, [r0, #20] +10001340: 698b ldr r3, [r1, #24] +10001342: 6183 str r3, [r0, #24] +10001344: 69cb ldr r3, [r1, #28] +10001346: 61c3 str r3, [r0, #28] +10001348: 6a0b ldr r3, [r1, #32] +1000134a: 6203 str r3, [r0, #32] +1000134c: 6a4b ldr r3, [r1, #36] @ 0x24 +1000134e: 6243 str r3, [r0, #36] @ 0x24 +10001350: 6a8b ldr r3, [r1, #40] @ 0x28 +10001352: 6283 str r3, [r0, #40] @ 0x28 +10001354: 6acb ldr r3, [r1, #44] @ 0x2c +10001356: 62c3 str r3, [r0, #44] @ 0x2c +10001358: 6b0b ldr r3, [r1, #48] @ 0x30 +1000135a: 6303 str r3, [r0, #48] @ 0x30 +1000135c: 6b4b ldr r3, [r1, #52] @ 0x34 +1000135e: 6343 str r3, [r0, #52] @ 0x34 +10001360: 6b8b ldr r3, [r1, #56] @ 0x38 +10001362: 6383 str r3, [r0, #56] @ 0x38 +10001364: 6bcb ldr r3, [r1, #60] @ 0x3c +10001366: 63c3 str r3, [r0, #60] @ 0x3c +10001368: 3040 adds r0, #64 @ 0x40 +1000136a: 3140 adds r1, #64 @ 0x40 +1000136c: 3a40 subs r2, #64 @ 0x40 +1000136e: d2db bcs.n 10001328 +10001370: 3230 adds r2, #48 @ 0x30 +10001372: d30b bcc.n 1000138c +10001374: 680b ldr r3, [r1, #0] +10001376: 6003 str r3, [r0, #0] +10001378: 684b ldr r3, [r1, #4] +1000137a: 6043 str r3, [r0, #4] +1000137c: 688b ldr r3, [r1, #8] +1000137e: 6083 str r3, [r0, #8] +10001380: 68cb ldr r3, [r1, #12] +10001382: 60c3 str r3, [r0, #12] +10001384: 3010 adds r0, #16 +10001386: 3110 adds r1, #16 +10001388: 3a10 subs r2, #16 +1000138a: d2f3 bcs.n 10001374 +1000138c: 320c adds r2, #12 +1000138e: d305 bcc.n 1000139c +10001390: f851 3b04 ldr.w r3, [r1], #4 +10001394: f840 3b04 str.w r3, [r0], #4 +10001398: 3a04 subs r2, #4 +1000139a: d2f9 bcs.n 10001390 +1000139c: 3204 adds r2, #4 +1000139e: d008 beq.n 100013b2 +100013a0: 07d2 lsls r2, r2, #31 +100013a2: bf1c itt ne +100013a4: f811 3b01 ldrbne.w r3, [r1], #1 +100013a8: f800 3b01 strbne.w r3, [r0], #1 +100013ac: d301 bcc.n 100013b2 +100013ae: 880b ldrh r3, [r1, #0] +100013b0: 8003 strh r3, [r0, #0] +100013b2: 4660 mov r0, ip +100013b4: 4770 bx lr +100013b6: bf00 nop +100013b8: 2a08 cmp r2, #8 +100013ba: d313 bcc.n 100013e4 +100013bc: 078b lsls r3, r1, #30 +100013be: d0b1 beq.n 10001324 +100013c0: f010 0303 ands.w r3, r0, #3 +100013c4: d0ae beq.n 10001324 +100013c6: f1c3 0304 rsb r3, r3, #4 +100013ca: 1ad2 subs r2, r2, r3 +100013cc: 07db lsls r3, r3, #31 +100013ce: bf1c itt ne +100013d0: f811 3b01 ldrbne.w r3, [r1], #1 +100013d4: f800 3b01 strbne.w r3, [r0], #1 +100013d8: d3a4 bcc.n 10001324 +100013da: f831 3b02 ldrh.w r3, [r1], #2 +100013de: f820 3b02 strh.w r3, [r0], #2 +100013e2: e79f b.n 10001324 +100013e4: 3a04 subs r2, #4 +100013e6: d3d9 bcc.n 1000139c +100013e8: 3a01 subs r2, #1 +100013ea: f811 3b01 ldrb.w r3, [r1], #1 +100013ee: f800 3b01 strb.w r3, [r0], #1 +100013f2: d2f9 bcs.n 100013e8 +100013f4: 780b ldrb r3, [r1, #0] +100013f6: 7003 strb r3, [r0, #0] +100013f8: 784b ldrb r3, [r1, #1] +100013fa: 7043 strb r3, [r0, #1] +100013fc: 788b ldrb r3, [r1, #2] +100013fe: 7083 strb r3, [r0, #2] +10001400: 4660 mov r0, ip +10001402: 4770 bx lr + +10001404 : +10001404: f020 0103 bic.w r1, r0, #3 +10001408: f010 0003 ands.w r0, r0, #3 +1000140c: f1c0 0000 rsb r0, r0, #0 +10001410: f851 3b04 ldr.w r3, [r1], #4 +10001414: f100 0c04 add.w ip, r0, #4 +10001418: ea4f 0ccc mov.w ip, ip, lsl #3 +1000141c: f06f 0200 mvn.w r2, #0 +10001420: bf1c itt ne +10001422: fa22 f20c lsrne.w r2, r2, ip +10001426: 4313 orrne r3, r2 +10001428: f04f 0c01 mov.w ip, #1 +1000142c: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001430: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001434: eba3 020c sub.w r2, r3, ip +10001438: ea22 0203 bic.w r2, r2, r3 +1000143c: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001440: bf04 itt eq +10001442: f851 3b04 ldreq.w r3, [r1], #4 +10001446: 3004 addeq r0, #4 +10001448: d0f4 beq.n 10001434 +1000144a: f1c2 0100 rsb r1, r2, #0 +1000144e: ea02 0201 and.w r2, r2, r1 +10001452: fab2 f282 clz r2, r2 +10001456: f1c2 021f rsb r2, r2, #31 +1000145a: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000145e: 4770 bx lr + +10001460 <_fini>: +10001460: b5f8 push {r3, r4, r5, r6, r7, lr} +10001462: bf00 nop +10001464: 0000 movs r0, r0 + ... + +10001468 <__mutex_exit_veneer>: +10001468: f85f f000 ldr.w pc, [pc] @ 1000146c <__mutex_exit_veneer+0x4> +1000146c: 200001e5 .word 0x200001e5 + +10001470 <__mutex_try_enter_block_until_veneer>: +10001470: f85f f000 ldr.w pc, [pc] @ 10001474 <__mutex_try_enter_block_until_veneer+0x4> +10001474: 2000017d .word 0x2000017d + +10001478 <__pre_init_runtime_init_bootrom_reset>: +10001478: 10000edd .... + +1000147c <__pre_init_runtime_init_early_resets>: +1000147c: 10000e51 Q... + +10001480 <__pre_init_runtime_init_usb_power_down>: +10001480: 10000e85 .... + +10001484 <__pre_init_runtime_init_clocks>: +10001484: 10000f71 q... + +10001488 <__pre_init_runtime_init_post_clock_resets>: +10001488: 10000ebd .... + +1000148c <__pre_init_runtime_init_boot_locks_reset>: +1000148c: 10000dd5 .... + +10001490 <__pre_init_runtime_init_spin_locks_reset>: +10001490: 10000f05 .... + +10001494 <__pre_init_runtime_init_bootrom_locking_enable>: +10001494: 10000dc1 .... + +10001498 <__pre_init_runtime_init_mutex>: +10001498: 10000451 Q... + +1000149c <__pre_init_runtime_init_install_ram_vector_table>: +1000149c: 10000f09 .... + +100014a0 <__pre_init_runtime_init_default_alarm_pool>: +100014a0: 100007c9 .... + +100014a4 <__pre_init_first_per_core_initializer>: +100014a4: 10000e21 !... + +100014a8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100014a8: 10000ef1 .... + +100014ac <__pre_init_runtime_init_per_core_enable_coprocessors>: +100014ac: 10000ea1 .... + +100014b0 <__pre_init_spinlock_set_extexclall>: +100014b0: 10000351 Q... + +100014b4 <__pre_init_runtime_init_per_core_irq_priorities>: +100014b4: 10000379 y... + +100014b8 <__frame_dummy_init_array_entry>: +100014b8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__best_effort_wfe_or_timeout_veneer>: +20000220: f85f f000 ldr.w pc, [pc] @ 20000224 <__best_effort_wfe_or_timeout_veneer+0x4> +20000224: 10000ae9 .word 0x10000ae9 + +20000228 : +20000228: 00000010 .... + +2000022c : + ... +20000240: 20000250 P.. + +20000244 : + ... diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf new file mode 100755 index 0000000..ba72e60 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf differ diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf.map b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf.map new file mode 100644 index 0000000..d3c342b --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.elf.map @@ -0,0 +1,3535 @@ +Archive member included to satisfy reference by file (symbol) + +/Users/kevinthomas/.pico-sdk/toolchain/14_2_Rel1/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a(libm_a-wf_sqrt.o) + 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+:0C17180050020020000000000000000053 +:10172400D3DEFFFFFE010000FF01000014EAFFFF0B +:04173400793512AB46 +:040000051000014D99 +:00000001FF diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.uf2 b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.uf2 new file mode 100644 index 0000000..b3412a8 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-b/build/0x0008_uninitialized-variables-b.uf2 differ diff --git a/WEEK04/0x0008_uninitialized-variables-b/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables-b/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables-b/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables-b/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-b/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables-c/.gitignore b/WEEK04/0x0008_uninitialized-variables-c/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0008_uninitialized-variables-c/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables-c/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-c/0x0008_uninitialized-variables-c.c b/WEEK04/0x0008_uninitialized-variables-c/0x0008_uninitialized-variables-c.c new file mode 100644 index 0000000..5136c35 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/0x0008_uninitialized-variables-c.c @@ -0,0 +1,35 @@ +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) +{ + // gpio_init(LED_PIN); + /// gpio_set_dir(LED_PIN, GPIO_IN); + gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + /// gpio_put(LED_PIN, 0); + gpioc_bit_out_put(LED_PIN, 0); + /// gpio_set_function(LED_PIN, GPIO_FUNC_SIO); + hw_write_masked(&pads_bank0_hw->io[LED_PIN], + PADS_BANK0_GPIO0_IE_BITS, + PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS + ); + io_bank0_hw->io[LED_PIN].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; + hw_clear_bits(&pads_bank0_hw->io[LED_PIN], PADS_BANK0_GPIO0_ISO_BITS); + + // gpio_set_dir(LED_PIN, GPIO_OUT); + gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + + while (true) { + // gpio_put(LED_PIN, 1); + gpioc_bit_out_put(LED_PIN, 1); + // sleep_ms(500); + sleep_us(500 * 1000ull); + + // gpio_put(LED_PIN, 0); + gpioc_bit_out_put(LED_PIN, 0); + // sleep_ms(500); + sleep_us(500 * 1000ull); + } +} diff --git a/WEEK04/0x0008_uninitialized-variables-c/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables-c/CMakeLists.txt new file mode 100644 index 0000000..b7e1991 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables-c C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables-c 0x0008_uninitialized-variables-c.c ) + +pico_set_program_name(0x0008_uninitialized-variables-c "0x0008_uninitialized-variables-c") +pico_set_program_version(0x0008_uninitialized-variables-c "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables-c 0) +pico_enable_stdio_usb(0x0008_uninitialized-variables-c 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables-c + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables-c PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables-c) + diff --git a/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.bin b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.bin new file mode 100755 index 0000000..34b7d18 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.bin differ diff --git a/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.dis b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.dis new file mode 100644 index 0000000..0f80dcd --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.dis @@ -0,0 +1,2287 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000014ac 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000104 100014ac 100014ac 000024ac 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100015b0 100015b0 000025b0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000020 100015b8 100015b8 000025b8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003728 2**0 + CONTENTS + 6 .data 0000013c 20000110 100015d8 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000024c 2000024c 00003728 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000024c 2000024c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000214 20000250 10001714 00004250 2**3 + ALLOC + 10 .heap 00000800 20000464 10001714 00004464 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003728 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003728 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001714 10001714 00003714 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003728 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 0000375c 2**0 + CONTENTS, READONLY + 17 .debug_info 0001b3a5 00000000 00000000 000037a1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00004975 00000000 00000000 0001eb46 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0000d3ac 00000000 00000000 000234bb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000900 00000000 00000000 00030868 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00002569 00000000 00000000 00031168 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00011e9b 00000000 00000000 000336d1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00004846 00000000 00000000 0004556c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 000018ec 00000000 00000000 00049db4 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 0000018e 00000000 00000000 0004b6a0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 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bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100015d8 .word 0x100015d8 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000024c .word 0x2000024c +100001ac: 10001714 .word 0x10001714 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001714 .word 0x10001714 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000024c .word 0x2000024c +100001d4: 20000464 .word 0x20000464 +100001d8: 10001081 .word 0x10001081 +100001dc: 10000235 .word 0x10000235 +100001e0: 10001079 .word 0x10001079 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000024c .word 0x2000024c +10000208: 2000024c .word 0x2000024c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000428 .word 0x20000428 +10000230: 100014ac .word 0x100014ac + +10000234
: +10000234: b508 push {r3, lr} +10000236: 2210 movs r2, #16 +10000238: f04f 0501 mov.w r5, #1 +1000023c: ec45 2044 gpioc_bit_oe_put r2, r5 +10000240: f04f 0600 mov.w r6, #0 +10000244: ec46 2040 gpioc_bit_out_put r2, r6 +10000248: 4b10 ldr r3, [pc, #64] @ (1000028c ) +1000024a: 4911 ldr r1, [pc, #68] @ (10000290 ) +1000024c: 6c5b ldr r3, [r3, #68] @ 0x44 +1000024e: 2005 movs r0, #5 +10000250: f083 0340 eor.w r3, r3, #64 @ 0x40 +10000254: f003 03c0 and.w r3, r3, #192 @ 0xc0 +10000258: 644b str r3, [r1, #68] @ 0x44 +1000025a: f44f 7180 mov.w r1, #256 @ 0x100 +1000025e: 4b0d ldr r3, [pc, #52] @ (10000294 ) +10000260: f8c3 0084 str.w r0, [r3, #132] @ 0x84 +10000264: f503 3398 add.w r3, r3, #77824 @ 0x13000 +10000268: 6459 str r1, [r3, #68] @ 0x44 +1000026a: ec45 2044 gpioc_bit_oe_put r2, r5 +1000026e: 2410 movs r4, #16 +10000270: ec45 4040 gpioc_bit_out_put r4, r5 +10000274: 2100 movs r1, #0 +10000276: 4808 ldr r0, [pc, #32] @ (10000298 ) +10000278: f000 fbc2 bl 10000a00 +1000027c: ec46 4040 gpioc_bit_out_put r4, r6 +10000280: 2100 movs r1, #0 +10000282: 4805 ldr r0, [pc, #20] @ (10000298 ) +10000284: f000 fbbc bl 10000a00 +10000288: e7f1 b.n 1000026e +1000028a: bf00 nop +1000028c: 40038000 .word 0x40038000 +10000290: 40039000 .word 0x40039000 +10000294: 40028000 .word 0x40028000 +10000298: 0007a120 .word 0x0007a120 + +1000029c : +1000029c: b40f push {r0, r1, r2, r3} +1000029e: b500 push {lr} +100002a0: b083 sub sp, #12 +100002a2: 9c04 ldr r4, [sp, #16] +100002a4: 4807 ldr r0, [pc, #28] @ (100002c4 ) +100002a6: f001 f811 bl 100012cc <__wrap_puts> +100002aa: b13c cbz r4, 100002bc +100002ac: a905 add r1, sp, #20 +100002ae: 4620 mov r0, r4 +100002b0: 9101 str r1, [sp, #4] +100002b2: f000 fec7 bl 10001044 +100002b6: 4804 ldr r0, [pc, #16] @ (100002c8 ) +100002b8: f001 f808 bl 100012cc <__wrap_puts> +100002bc: 2001 movs r0, #1 +100002be: f000 fed9 bl 10001074 <_exit> +100002c2: bf00 nop +100002c4: 100014ac .word 0x100014ac +100002c8: 100014bc .word 0x100014bc + +100002cc : +100002cc: b570 push {r4, r5, r6, lr} +100002ce: 4686 mov lr, r0 +100002d0: f3ef 8510 mrs r5, PRIMASK +100002d4: b672 cpsid i +100002d6: 4c12 ldr r4, [pc, #72] @ (10000320 ) +100002d8: e8d4 6fcf ldaexb r6, [r4] +100002dc: 2001 movs r0, #1 +100002de: 2e00 cmp r6, #0 +100002e0: d1fa bne.n 100002d8 +100002e2: e8c4 0f46 strexb r6, r0, [r4] +100002e6: 2e00 cmp r6, #0 +100002e8: d1f6 bne.n 100002d8 +100002ea: f3bf 8f5f dmb sy +100002ee: f04f 0c01 mov.w ip, #1 +100002f2: 08c8 lsrs r0, r1, #3 +100002f4: f001 0307 and.w r3, r1, #7 +100002f8: fa0c f303 lsl.w r3, ip, r3 +100002fc: f81e c000 ldrb.w ip, [lr, r0] +10000300: ea1c 0603 ands.w r6, ip, r3 +10000304: d108 bne.n 10000318 +10000306: ea4c 0c03 orr.w ip, ip, r3 +1000030a: f80e c000 strb.w ip, [lr, r0] +1000030e: e8c4 6f8f stlb r6, [r4] +10000312: f385 8810 msr PRIMASK, r5 +10000316: bd70 pop {r4, r5, r6, pc} +10000318: 4610 mov r0, r2 +1000031a: f7ff ffbf bl 1000029c +1000031e: bf00 nop +10000320: 200003db .word 0x200003db + +10000324 : +10000324: 4a04 ldr r2, [pc, #16] @ (10000338 ) +10000326: 7810 ldrb r0, [r2, #0] +10000328: 1c43 adds r3, r0, #1 +1000032a: b2db uxtb r3, r3 +1000032c: 2b18 cmp r3, #24 +1000032e: bf28 it cs +10000330: 2310 movcs r3, #16 +10000332: 7013 strb r3, [r2, #0] +10000334: 4770 bx lr +10000336: bf00 nop +10000338: 20000228 .word 0x20000228 + +1000033c : +1000033c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000340: 6893 ldr r3, [r2, #8] +10000342: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +10000346: 6093 str r3, [r2, #8] +10000348: 4770 bx lr +1000034a: bf00 nop + +1000034c : +1000034c: 2100 movs r1, #0 +1000034e: 4b04 ldr r3, [pc, #16] @ (10000360 ) +10000350: f103 0220 add.w r2, r3, #32 +10000354: e8c3 1f8f stlb r1, [r3] +10000358: 3301 adds r3, #1 +1000035a: 4293 cmp r3, r2 +1000035c: d1fa bne.n 10000354 +1000035e: 4770 bx lr +10000360: 200003d0 .word 0x200003d0 + +10000364 : +10000364: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000368: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +1000036c: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000370: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000374: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000378: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +1000037c: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000380: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000384: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000388: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +1000038c: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000390: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000394: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000398: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +1000039c: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100003a0: b662 cpsie i +100003a2: 4770 bx lr + +100003a4 : +100003a4: 2301 movs r3, #1 +100003a6: f000 021f and.w r2, r0, #31 +100003aa: 4093 lsls r3, r2 +100003ac: 0940 lsrs r0, r0, #5 +100003ae: b141 cbz r1, 100003c2 +100003b0: 0080 lsls r0, r0, #2 +100003b2: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003b6: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003ba: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003be: 6003 str r3, [r0, #0] +100003c0: 4770 bx lr +100003c2: 4a02 ldr r2, [pc, #8] @ (100003cc ) +100003c4: 3020 adds r0, #32 +100003c6: f842 3020 str.w r3, [r2, r0, lsl #2] +100003ca: 4770 bx lr +100003cc: e000e100 .word 0xe000e100 + +100003d0 : +100003d0: b5f8 push {r3, r4, r5, r6, r7, lr} +100003d2: 460d mov r5, r1 +100003d4: f3ef 8710 mrs r7, PRIMASK +100003d8: b672 cpsid i +100003da: 4e12 ldr r6, [pc, #72] @ (10000424 ) +100003dc: e8d6 2fcf ldaexb r2, [r6] +100003e0: 2301 movs r3, #1 +100003e2: 2a00 cmp r2, #0 +100003e4: d1fa bne.n 100003dc +100003e6: e8c6 3f42 strexb r2, r3, [r6] +100003ea: 2a00 cmp r2, #0 +100003ec: d1f6 bne.n 100003dc +100003ee: f3bf 8f5f dmb sy +100003f2: 4b0d ldr r3, [pc, #52] @ (10000428 ) +100003f4: f100 0410 add.w r4, r0, #16 +100003f8: 689b ldr r3, [r3, #8] +100003fa: 4a0c ldr r2, [pc, #48] @ (1000042c ) +100003fc: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000400: 4293 cmp r3, r2 +10000402: d003 beq.n 1000040c +10000404: 4299 cmp r1, r3 +10000406: d001 beq.n 1000040c +10000408: f000 fd04 bl 10000e14 +1000040c: 4b06 ldr r3, [pc, #24] @ (10000428 ) +1000040e: 689b ldr r3, [r3, #8] +10000410: f843 5024 str.w r5, [r3, r4, lsl #2] +10000414: f3bf 8f5f dmb sy +10000418: 2300 movs r3, #0 +1000041a: e8c6 3f8f stlb r3, [r6] +1000041e: f387 8810 msr PRIMASK, r7 +10000422: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000424: 200003d9 .word 0x200003d9 +10000428: e000ed00 .word 0xe000ed00 +1000042c: 10000111 .word 0x10000111 + +10000430 : +10000430: 4b01 ldr r3, [pc, #4] @ (10000438 ) +10000432: 440b add r3, r1 +10000434: 6003 str r3, [r0, #0] +10000436: 4770 bx lr +10000438: 200003d0 .word 0x200003d0 + +1000043c : +1000043c: b570 push {r4, r5, r6, lr} +1000043e: 4c10 ldr r4, [pc, #64] @ (10000480 ) +10000440: 4d10 ldr r5, [pc, #64] @ (10000484 ) +10000442: 42ac cmp r4, r5 +10000444: d20e bcs.n 10000464 +10000446: 26ff movs r6, #255 @ 0xff +10000448: 6823 ldr r3, [r4, #0] +1000044a: b163 cbz r3, 10000466 +1000044c: f7ff ff6a bl 10000324 +10000450: 4601 mov r1, r0 +10000452: 4620 mov r0, r4 +10000454: f7ff ffec bl 10000430 +10000458: 80a6 strh r6, [r4, #4] +1000045a: f3bf 8f5f dmb sy +1000045e: 3408 adds r4, #8 +10000460: 42ac cmp r4, r5 +10000462: d3f1 bcc.n 10000448 +10000464: bd70 pop {r4, r5, r6, pc} +10000466: f7ff ff5d bl 10000324 +1000046a: 4601 mov r1, r0 +1000046c: 4620 mov r0, r4 +1000046e: f7ff ffdf bl 10000430 +10000472: 7126 strb r6, [r4, #4] +10000474: f3bf 8f5f dmb sy +10000478: 3408 adds r4, #8 +1000047a: 42ac cmp r4, r5 +1000047c: d3e4 bcc.n 10000448 +1000047e: bd70 pop {r4, r5, r6, pc} +10000480: 20000244 .word 0x20000244 +10000484: 2000024c .word 0x2000024c + +10000488 : +10000488: 4b0d ldr r3, [pc, #52] @ (100004c0 ) +1000048a: 681a ldr r2, [r3, #0] +1000048c: f3ef 8110 mrs r1, PRIMASK +10000490: b672 cpsid i +10000492: e8d2 cfcf ldaexb ip, [r2] +10000496: 2001 movs r0, #1 +10000498: f1bc 0f00 cmp.w ip, #0 +1000049c: d1f9 bne.n 10000492 +1000049e: e8c2 0f4c strexb ip, r0, [r2] +100004a2: f1bc 0f00 cmp.w ip, #0 +100004a6: d1f4 bne.n 10000492 +100004a8: f3bf 8f5f dmb sy +100004ac: 2200 movs r2, #0 +100004ae: 681b ldr r3, [r3, #0] +100004b0: e8c3 2f8f stlb r2, [r3] +100004b4: f381 8810 msr PRIMASK, r1 +100004b8: bf40 sev +100004ba: 2000 movs r0, #0 +100004bc: 2100 movs r1, #0 +100004be: 4770 bx lr +100004c0: 20000460 .word 0x20000460 +100004c4: 00000000 .word 0x00000000 + +100004c8 : +100004c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004cc: ed2d 8b02 vpush {d8} +100004d0: b085 sub sp, #20 +100004d2: f3ef 8305 mrs r3, IPSR +100004d6: b2db uxtb r3, r3 +100004d8: 3b10 subs r3, #16 +100004da: 089a lsrs r2, r3, #2 +100004dc: bf18 it ne +100004de: 2201 movne r2, #1 +100004e0: f04f 0101 mov.w r1, #1 +100004e4: f003 0b03 and.w fp, r3, #3 +100004e8: bf18 it ne +100004ea: 4daf ldrne r5, [pc, #700] @ (100007a8 ) +100004ec: 4baf ldr r3, [pc, #700] @ (100007ac ) +100004ee: bf08 it eq +100004f0: 4daf ldreq r5, [pc, #700] @ (100007b0 ) +100004f2: eb0b 0282 add.w r2, fp, r2, lsl #2 +100004f6: f853 6022 ldr.w r6, [r3, r2, lsl #2] +100004fa: fa01 f20b lsl.w r2, r1, fp +100004fe: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000502: ed9f 8ba7 vldr d8, [pc, #668] @ 100007a0 +10000506: 9201 str r2, [sp, #4] +10000508: 605a str r2, [r3, #4] +1000050a: e02f b.n 1000056c +1000050c: 88b3 ldrh r3, [r6, #4] +1000050e: 041c lsls r4, r3, #16 +10000510: f140 8093 bpl.w 1000063a +10000514: 79b3 ldrb r3, [r6, #6] +10000516: 2b00 cmp r3, #0 +10000518: f040 80dd bne.w 100006d6 +1000051c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000520: 2a00 cmp r2, #0 +10000522: f2c0 811e blt.w 10000762 +10000526: 6973 ldr r3, [r6, #20] +10000528: eb02 0242 add.w r2, r2, r2, lsl #1 +1000052c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000530: e9d3 4702 ldrd r4, r7, [r3, #8] +10000534: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000538: bf08 it eq +1000053a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +1000053e: d00e beq.n 1000055e +10000540: eb05 018b add.w r1, r5, fp, lsl #2 +10000544: 6aab ldr r3, [r5, #40] @ 0x28 +10000546: 690a ldr r2, [r1, #16] +10000548: 1ad2 subs r2, r2, r3 +1000054a: 1ae3 subs r3, r4, r3 +1000054c: 4293 cmp r3, r2 +1000054e: d305 bcc.n 1000055c +10000550: 2301 movs r3, #1 +10000552: 6a2a ldr r2, [r5, #32] +10000554: fa03 f30b lsl.w r3, r3, fp +10000558: 4213 tst r3, r2 +1000055a: d100 bne.n 1000055e +1000055c: 610c str r4, [r1, #16] +1000055e: 4628 mov r0, r5 +10000560: f000 fb36 bl 10000bd0 +10000564: 42a0 cmp r0, r4 +10000566: 41b9 sbcs r1, r7 +10000568: f2c0 80fb blt.w 10000762 +1000056c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000570: 9a01 ldr r2, [sp, #4] +10000572: 2b00 cmp r3, #0 +10000574: 9300 str r3, [sp, #0] +10000576: 63ea str r2, [r5, #60] @ 0x3c +10000578: dbc8 blt.n 1000050c +1000057a: f8d6 8014 ldr.w r8, [r6, #20] +1000057e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000582: 4628 mov r0, r5 +10000584: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000588: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000058c: f000 fb20 bl 10000bd0 +10000590: 42a0 cmp r0, r4 +10000592: eb71 010a sbcs.w r1, r1, sl +10000596: dbb9 blt.n 1000050c +10000598: f1ba 0f00 cmp.w sl, #0 +1000059c: f2c0 80c3 blt.w 10000726 +100005a0: e9d7 3104 ldrd r3, r1, [r7, #16] +100005a4: 4a83 ldr r2, [pc, #524] @ (100007b4 ) +100005a6: 4293 cmp r3, r2 +100005a8: f000 80ed beq.w 10000786 +100005ac: 887a ldrh r2, [r7, #2] +100005ae: f9b6 0008 ldrsh.w r0, [r6, #8] +100005b2: b292 uxth r2, r2 +100005b4: ea42 4000 orr.w r0, r2, r0, lsl #16 +100005b8: 4798 blx r3 +100005ba: 4602 mov r2, r0 +100005bc: 460b mov r3, r1 +100005be: ea52 0103 orrs.w r1, r2, r3 +100005c2: f000 80b0 beq.w 10000726 +100005c6: 2b00 cmp r3, #0 +100005c8: f280 80d1 bge.w 1000076e +100005cc: ebb4 0e02 subs.w lr, r4, r2 +100005d0: eb6a 0a03 sbc.w sl, sl, r3 +100005d4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100005d8: e9c7 ea02 strd lr, sl, [r7, #8] +100005dc: 2b00 cmp r3, #0 +100005de: db95 blt.n 1000050c +100005e0: 6971 ldr r1, [r6, #20] +100005e2: eb03 0243 add.w r2, r3, r3, lsl #1 +100005e6: eb01 02c2 add.w r2, r1, r2, lsl #3 +100005ea: e9d2 7002 ldrd r7, r0, [r2, #8] +100005ee: 45be cmp lr, r7 +100005f0: eb7a 0c00 sbcs.w ip, sl, r0 +100005f4: ea4f 0243 mov.w r2, r3, lsl #1 +100005f8: db88 blt.n 1000050c +100005fa: 46b4 mov ip, r6 +100005fc: f82c 3f08 strh.w r3, [ip, #8]! +10000600: e006 b.n 10000610 +10000602: eb03 0043 add.w r0, r3, r3, lsl #1 +10000606: eb01 00c0 add.w r0, r1, r0, lsl #3 +1000060a: 005a lsls r2, r3, #1 +1000060c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000610: 45be cmp lr, r7 +10000612: 441a add r2, r3 +10000614: eb7a 0000 sbcs.w r0, sl, r0 +10000618: eb01 04c2 add.w r4, r1, r2, lsl #3 +1000061c: db04 blt.n 10000628 +1000061e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000622: 46a4 mov ip, r4 +10000624: 2b00 cmp r3, #0 +10000626: daec bge.n 10000602 +10000628: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000062c: 9b00 ldr r3, [sp, #0] +1000062e: f8ac 3000 strh.w r3, [ip] +10000632: 88b3 ldrh r3, [r6, #4] +10000634: 041c lsls r4, r3, #16 +10000636: f53f af6d bmi.w 10000514 +1000063a: 6933 ldr r3, [r6, #16] +1000063c: f3ef 8210 mrs r2, PRIMASK +10000640: b672 cpsid i +10000642: e8d3 0fcf ldaexb r0, [r3] +10000646: 2101 movs r1, #1 +10000648: 2800 cmp r0, #0 +1000064a: d1fa bne.n 10000642 +1000064c: e8c3 1f40 strexb r0, r1, [r3] +10000650: 2800 cmp r0, #0 +10000652: d1f6 bne.n 10000642 +10000654: f3bf 8f5f dmb sy +10000658: f64f 74ff movw r4, #65535 @ 0xffff +1000065c: 88b0 ldrh r0, [r6, #4] +1000065e: 2300 movs r3, #0 +10000660: 6931 ldr r1, [r6, #16] +10000662: b200 sxth r0, r0 +10000664: 80b4 strh r4, [r6, #4] +10000666: e8c1 3f8f stlb r3, [r1] +1000066a: f382 8810 msr PRIMASK, r2 +1000066e: 4298 cmp r0, r3 +10000670: f6ff af50 blt.w 10000514 +10000674: 4607 mov r7, r0 +10000676: 46a9 mov r9, r5 +10000678: 6974 ldr r4, [r6, #20] +1000067a: f106 0808 add.w r8, r6, #8 +1000067e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000682: eb04 03ce add.w r3, r4, lr, lsl #3 +10000686: e9d3 5002 ldrd r5, r0, [r3, #8] +1000068a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000068e: 46c4 mov ip, r8 +10000690: 2b00 cmp r3, #0 +10000692: db13 blt.n 100006bc +10000694: 46b2 mov sl, r6 +10000696: 9700 str r7, [sp, #0] +10000698: e004 b.n 100006a4 +1000069a: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +1000069e: 4694 mov ip, r2 +100006a0: 2b00 cmp r3, #0 +100006a2: db09 blt.n 100006b8 +100006a4: eb03 0643 add.w r6, r3, r3, lsl #1 +100006a8: eb04 02c6 add.w r2, r4, r6, lsl #3 +100006ac: e9d2 7102 ldrd r7, r1, [r2, #8] +100006b0: 42bd cmp r5, r7 +100006b2: eb70 0101 sbcs.w r1, r0, r1 +100006b6: daf0 bge.n 1000069a +100006b8: 4656 mov r6, sl +100006ba: 9f00 ldr r7, [sp, #0] +100006bc: f8ac 7000 strh.w r7, [ip] +100006c0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100006c4: f824 303e strh.w r3, [r4, lr, lsl #3] +100006c8: 2f00 cmp r7, #0 +100006ca: dad8 bge.n 1000067e +100006cc: 79b3 ldrb r3, [r6, #6] +100006ce: 464d mov r5, r9 +100006d0: 2b00 cmp r3, #0 +100006d2: f43f af23 beq.w 1000051c +100006d6: 2300 movs r3, #0 +100006d8: 71b3 strb r3, [r6, #6] +100006da: f9b6 3008 ldrsh.w r3, [r6, #8] +100006de: f106 0808 add.w r8, r6, #8 +100006e2: 1c58 adds r0, r3, #1 +100006e4: d03d beq.n 10000762 +100006e6: 461a mov r2, r3 +100006e8: 6977 ldr r7, [r6, #20] +100006ea: e003 b.n 100006f4 +100006ec: 4680 mov r8, r0 +100006ee: 1c59 adds r1, r3, #1 +100006f0: f43f af16 beq.w 10000520 +100006f4: eb03 0143 add.w r1, r3, r3, lsl #1 +100006f8: eb07 00c1 add.w r0, r7, r1, lsl #3 +100006fc: f8b0 c002 ldrh.w ip, [r0, #2] +10000700: 461c mov r4, r3 +10000702: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000706: 469e mov lr, r3 +10000708: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +1000070c: d0ee beq.n 100006ec +1000070e: 4294 cmp r4, r2 +10000710: ed80 8b02 vstr d8, [r0, #8] +10000714: d005 beq.n 10000722 +10000716: f8a8 3000 strh.w r3, [r8] +1000071a: 8932 ldrh r2, [r6, #8] +1000071c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000720: 8134 strh r4, [r6, #8] +10000722: 4672 mov r2, lr +10000724: e7e3 b.n 100006ee +10000726: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +1000072a: 8133 strh r3, [r6, #8] +1000072c: 6933 ldr r3, [r6, #16] +1000072e: f3ef 8210 mrs r2, PRIMASK +10000732: b672 cpsid i +10000734: e8d3 0fcf ldaexb r0, [r3] +10000738: 2101 movs r1, #1 +1000073a: 2800 cmp r0, #0 +1000073c: d1fa bne.n 10000734 +1000073e: e8c3 1f40 strexb r0, r1, [r3] +10000742: 2800 cmp r0, #0 +10000744: d1f6 bne.n 10000734 +10000746: f3bf 8f5f dmb sy +1000074a: 8873 ldrh r3, [r6, #2] +1000074c: 6931 ldr r1, [r6, #16] +1000074e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000752: 9b00 ldr r3, [sp, #0] +10000754: 8073 strh r3, [r6, #2] +10000756: 2300 movs r3, #0 +10000758: e8c1 3f8f stlb r3, [r1] +1000075c: f382 8810 msr PRIMASK, r2 +10000760: e6d4 b.n 1000050c +10000762: bf40 sev +10000764: b005 add sp, #20 +10000766: ecbd 8b02 vpop {d8} +1000076a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000076e: 4628 mov r0, r5 +10000770: e9cd 2302 strd r2, r3, [sp, #8] +10000774: f000 fa2c bl 10000bd0 +10000778: 9a02 ldr r2, [sp, #8] +1000077a: 9b03 ldr r3, [sp, #12] +1000077c: eb10 0e02 adds.w lr, r0, r2 +10000780: eb43 0a01 adc.w sl, r3, r1 +10000784: e726 b.n 100005d4 +10000786: 4608 mov r0, r1 +10000788: 690b ldr r3, [r1, #16] +1000078a: 9102 str r1, [sp, #8] +1000078c: 4798 blx r3 +1000078e: 2800 cmp r0, #0 +10000790: d0c9 beq.n 10000726 +10000792: 9902 ldr r1, [sp, #8] +10000794: e9d1 2300 ldrd r2, r3, [r1] +10000798: e711 b.n 100005be +1000079a: bf00 nop +1000079c: f3af 8000 nop.w +100007a0: ffffffff .word 0xffffffff +100007a4: ffffffff .word 0xffffffff +100007a8: 400b8000 .word 0x400b8000 +100007ac: 20000440 .word 0x20000440 +100007b0: 400b0000 .word 0x400b0000 +100007b4: 100004c9 .word 0x100004c9 + +100007b8 : +100007b8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007bc: 4c36 ldr r4, [pc, #216] @ (10000898 ) +100007be: 6925 ldr r5, [r4, #16] +100007c0: b12d cbz r5, 100007ce +100007c2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007c6: 210a movs r1, #10 +100007c8: 4834 ldr r0, [pc, #208] @ (1000089c ) +100007ca: f7ff be31 b.w 10000430 +100007ce: f8df 80e4 ldr.w r8, [pc, #228] @ 100008b4 +100007d2: 2103 movs r1, #3 +100007d4: 4640 mov r0, r8 +100007d6: f000 f9e9 bl 10000bac +100007da: 2603 movs r6, #3 +100007dc: f8c4 800c str.w r8, [r4, #12] +100007e0: f7ff fda0 bl 10000324 +100007e4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +100007e8: 4b2d ldr r3, [pc, #180] @ (100008a0 ) +100007ea: 7026 strb r6, [r4, #0] +100007ec: 4403 add r3, r0 +100007ee: 6123 str r3, [r4, #16] +100007f0: f8dc 3000 ldr.w r3, [ip] +100007f4: 210f movs r1, #15 +100007f6: 7063 strb r3, [r4, #1] +100007f8: 6963 ldr r3, [r4, #20] +100007fa: 8061 strh r1, [r4, #2] +100007fc: 831d strh r5, [r3, #24] +100007fe: f04f 0504 mov.w r5, #4 +10000802: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000806: f04f 0505 mov.w r5, #5 +1000080a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +1000080e: f04f 0506 mov.w r5, #6 +10000812: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000816: f04f 0507 mov.w r5, #7 +1000081a: 210e movs r1, #14 +1000081c: f64f 72ff movw r2, #65535 @ 0xffff +10000820: 2708 movs r7, #8 +10000822: f04f 0e0a mov.w lr, #10 +10000826: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +1000082a: f04f 0901 mov.w r9, #1 +1000082e: f04f 0c0c mov.w ip, #12 +10000832: f04f 0b02 mov.w fp, #2 +10000836: f04f 0a09 mov.w sl, #9 +1000083a: 200d movs r0, #13 +1000083c: f04f 050b mov.w r5, #11 +10000840: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000844: 4917 ldr r1, [pc, #92] @ (100008a4 ) +10000846: 80a2 strh r2, [r4, #4] +10000848: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +1000084c: 60a1 str r1, [r4, #8] +1000084e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000852: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000856: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +1000085a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +1000085e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000862: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000866: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +1000086a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +1000086e: 801a strh r2, [r3, #0] +10000870: 4b0d ldr r3, [pc, #52] @ (100008a8 ) +10000872: 4630 mov r0, r6 +10000874: f8c8 7020 str.w r7, [r8, #32] +10000878: 490c ldr r1, [pc, #48] @ (100008ac ) +1000087a: 60dc str r4, [r3, #12] +1000087c: f7ff fda8 bl 100003d0 +10000880: 4649 mov r1, r9 +10000882: 4630 mov r0, r6 +10000884: f7ff fd8e bl 100003a4 +10000888: 4b09 ldr r3, [pc, #36] @ (100008b0 ) +1000088a: 210a movs r1, #10 +1000088c: 641f str r7, [r3, #64] @ 0x40 +1000088e: 4803 ldr r0, [pc, #12] @ (1000089c ) +10000890: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000894: f7ff bdcc b.w 10000430 +10000898: 2000022c .word 0x2000022c +1000089c: 20000460 .word 0x20000460 +100008a0: 200003d0 .word 0x200003d0 +100008a4: 0010ffff .word 0x0010ffff +100008a8: 20000440 .word 0x20000440 +100008ac: 100004c9 .word 0x100004c9 +100008b0: 400b2000 .word 0x400b2000 +100008b4: 400b0000 .word 0x400b0000 + +100008b8 : +100008b8: 4601 mov r1, r0 +100008ba: b5f0 push {r4, r5, r6, r7, lr} +100008bc: 6900 ldr r0, [r0, #16] +100008be: f3ef 8710 mrs r7, PRIMASK +100008c2: b672 cpsid i +100008c4: e8d0 5fcf ldaexb r5, [r0] +100008c8: 2401 movs r4, #1 +100008ca: 2d00 cmp r5, #0 +100008cc: d1fa bne.n 100008c4 +100008ce: e8c0 4f45 strexb r5, r4, [r0] +100008d2: 2d00 cmp r5, #0 +100008d4: d1f6 bne.n 100008c4 +100008d6: f3bf 8f5f dmb sy +100008da: f9b1 e002 ldrsh.w lr, [r1, #2] +100008de: 694c ldr r4, [r1, #20] +100008e0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +100008e4: f1be 0f00 cmp.w lr, #0 +100008e8: ea4f 05cc mov.w r5, ip, lsl #3 +100008ec: 6908 ldr r0, [r1, #16] +100008ee: eb04 0ccc add.w ip, r4, ip, lsl #3 +100008f2: db3c blt.n 1000096e +100008f4: 5b66 ldrh r6, [r4, r5] +100008f6: 804e strh r6, [r1, #2] +100008f8: 2600 movs r6, #0 +100008fa: e8c0 6f8f stlb r6, [r0] +100008fe: f387 8810 msr PRIMASK, r7 +10000902: f8bc 0002 ldrh.w r0, [ip, #2] +10000906: e9cc 2302 strd r2, r3, [ip, #8] +1000090a: 3001 adds r0, #1 +1000090c: f3c0 000e ubfx r0, r0, #0, #15 +10000910: 2801 cmp r0, #1 +10000912: bf38 it cc +10000914: 2001 movcc r0, #1 +10000916: 9b05 ldr r3, [sp, #20] +10000918: f8ac 0002 strh.w r0, [ip, #2] +1000091c: f8cc 3010 str.w r3, [ip, #16] +10000920: 9b06 ldr r3, [sp, #24] +10000922: ea40 400e orr.w r0, r0, lr, lsl #16 +10000926: f8cc 3014 str.w r3, [ip, #20] +1000092a: 690b ldr r3, [r1, #16] +1000092c: f3ef 8210 mrs r2, PRIMASK +10000930: b672 cpsid i +10000932: e8d3 cfcf ldaexb ip, [r3] +10000936: 2701 movs r7, #1 +10000938: f1bc 0f00 cmp.w ip, #0 +1000093c: d1f9 bne.n 10000932 +1000093e: e8c3 7f4c strexb ip, r7, [r3] +10000942: f1bc 0f00 cmp.w ip, #0 +10000946: d1f4 bne.n 10000932 +10000948: f3bf 8f5f dmb sy +1000094c: 888b ldrh r3, [r1, #4] +1000094e: 5363 strh r3, [r4, r5] +10000950: f8a1 e004 strh.w lr, [r1, #4] +10000954: 690b ldr r3, [r1, #16] +10000956: e8c3 6f8f stlb r6, [r3] +1000095a: f382 8810 msr PRIMASK, r2 +1000095e: 2201 movs r2, #1 +10000960: 68cb ldr r3, [r1, #12] +10000962: 7809 ldrb r1, [r1, #0] +10000964: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000968: 408a lsls r2, r1 +1000096a: 605a str r2, [r3, #4] +1000096c: bdf0 pop {r4, r5, r6, r7, pc} +1000096e: 2300 movs r3, #0 +10000970: e8c0 3f8f stlb r3, [r0] +10000974: f387 8810 msr PRIMASK, r7 +10000978: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000097c: bdf0 pop {r4, r5, r6, r7, pc} +1000097e: bf00 nop + +10000980 : +10000980: 4603 mov r3, r0 +10000982: 8940 ldrh r0, [r0, #10] +10000984: ebb0 4f21 cmp.w r0, r1, asr #16 +10000988: dd37 ble.n 100009fa +1000098a: 6958 ldr r0, [r3, #20] +1000098c: 140a asrs r2, r1, #16 +1000098e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000992: b510 push {r4, lr} +10000994: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000998: 691c ldr r4, [r3, #16] +1000099a: f3ef 8c10 mrs ip, PRIMASK +1000099e: b672 cpsid i +100009a0: e8d4 efcf ldaexb lr, [r4] +100009a4: 2201 movs r2, #1 +100009a6: f1be 0f00 cmp.w lr, #0 +100009aa: d1f9 bne.n 100009a0 +100009ac: e8c4 2f4e strexb lr, r2, [r4] +100009b0: f1be 0f00 cmp.w lr, #0 +100009b4: d1f4 bne.n 100009a0 +100009b6: f3bf 8f5f dmb sy +100009ba: 8842 ldrh r2, [r0, #2] +100009bc: b289 uxth r1, r1 +100009be: b292 uxth r2, r2 +100009c0: 428a cmp r2, r1 +100009c2: d007 beq.n 100009d4 +100009c4: 2200 movs r2, #0 +100009c6: 691b ldr r3, [r3, #16] +100009c8: e8c3 2f8f stlb r2, [r3] +100009cc: f38c 8810 msr PRIMASK, ip +100009d0: 2000 movs r0, #0 +100009d2: bd10 pop {r4, pc} +100009d4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +100009d8: 8042 strh r2, [r0, #2] +100009da: 2101 movs r1, #1 +100009dc: 2200 movs r2, #0 +100009de: 6918 ldr r0, [r3, #16] +100009e0: 7199 strb r1, [r3, #6] +100009e2: e8c0 2f8f stlb r2, [r0] +100009e6: f38c 8810 msr PRIMASK, ip +100009ea: 781c ldrb r4, [r3, #0] +100009ec: 68da ldr r2, [r3, #12] +100009ee: 4608 mov r0, r1 +100009f0: f502 5301 add.w r3, r2, #8256 @ 0x2040 +100009f4: 40a1 lsls r1, r4 +100009f6: 6059 str r1, [r3, #4] +100009f8: bd10 pop {r4, pc} +100009fa: 2000 movs r0, #0 +100009fc: 4770 bx lr +100009fe: bf00 nop + +10000a00 : +10000a00: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000a04: b082 sub sp, #8 +10000a06: 4604 mov r4, r0 +10000a08: 460e mov r6, r1 +10000a0a: f000 f8e9 bl 10000be0 +10000a0e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10000a12: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +10000a16: 1824 adds r4, r4, r0 +10000a18: eb46 0601 adc.w r6, r6, r1 +10000a1c: 42a2 cmp r2, r4 +10000a1e: eb73 0106 sbcs.w r1, r3, r6 +10000a22: bf3c itt cc +10000a24: 4614 movcc r4, r2 +10000a26: 461e movcc r6, r3 +10000a28: 1fa5 subs r5, r4, #6 +10000a2a: f146 37ff adc.w r7, r6, #4294967295 @ 0xffffffff +10000a2e: 42ac cmp r4, r5 +10000a30: eb76 0307 sbcs.w r3, r6, r7 +10000a34: bf3c itt cc +10000a36: 2500 movcc r5, #0 +10000a38: 462f movcc r7, r5 +10000a3a: f000 f8d1 bl 10000be0 +10000a3e: 1a28 subs r0, r5, r0 +10000a40: eb67 0c01 sbc.w ip, r7, r1 +10000a44: 2801 cmp r0, #1 +10000a46: f17c 0c00 sbcs.w ip, ip, #0 +10000a4a: da06 bge.n 10000a5a +10000a4c: 4620 mov r0, r4 +10000a4e: 4631 mov r1, r6 +10000a50: b002 add sp, #8 +10000a52: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000a56: f000 b8cd b.w 10000bf4 +10000a5a: f000 f8c1 bl 10000be0 +10000a5e: 4285 cmp r5, r0 +10000a60: eb67 0101 sbc.w r1, r7, r1 +10000a64: 2900 cmp r1, #0 +10000a66: db0a blt.n 10000a7e +10000a68: 2100 movs r1, #0 +10000a6a: 4b17 ldr r3, [pc, #92] @ (10000ac8 ) +10000a6c: 462a mov r2, r5 +10000a6e: 9300 str r3, [sp, #0] +10000a70: 4816 ldr r0, [pc, #88] @ (10000acc ) +10000a72: 463b mov r3, r7 +10000a74: 9101 str r1, [sp, #4] +10000a76: f7ff ff1f bl 100008b8 +10000a7a: 3001 adds r0, #1 +10000a7c: d0e6 beq.n 10000a4c +10000a7e: f04f 0c00 mov.w ip, #0 +10000a82: 4a13 ldr r2, [pc, #76] @ (10000ad0 ) +10000a84: 4913 ldr r1, [pc, #76] @ (10000ad4 ) +10000a86: 6a53 ldr r3, [r2, #36] @ 0x24 +10000a88: 429f cmp r7, r3 +10000a8a: d804 bhi.n 10000a96 +10000a8c: 6a90 ldr r0, [r2, #40] @ 0x28 +10000a8e: 42a8 cmp r0, r5 +10000a90: d2dc bcs.n 10000a4c +10000a92: 429f cmp r7, r3 +10000a94: d1da bne.n 10000a4c +10000a96: 680b ldr r3, [r1, #0] +10000a98: f3ef 8010 mrs r0, PRIMASK +10000a9c: b672 cpsid i +10000a9e: e8d3 8fcf ldaexb r8, [r3] +10000aa2: f05f 0e01 movs.w lr, #1 +10000aa6: f1b8 0f00 cmp.w r8, #0 +10000aaa: d1f8 bne.n 10000a9e +10000aac: e8c3 ef48 strexb r8, lr, [r3] +10000ab0: f1b8 0f00 cmp.w r8, #0 +10000ab4: d1f3 bne.n 10000a9e +10000ab6: f3bf 8f5f dmb sy +10000aba: 680b ldr r3, [r1, #0] +10000abc: e8c3 cf8f stlb ip, [r3] +10000ac0: f380 8810 msr PRIMASK, r0 +10000ac4: bf20 wfe +10000ac6: e7de b.n 10000a86 +10000ac8: 10000489 .word 0x10000489 +10000acc: 2000022c .word 0x2000022c +10000ad0: 400b0000 .word 0x400b0000 +10000ad4: 20000460 .word 0x20000460 + +10000ad8 : +10000ad8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000adc: 4606 mov r6, r0 +10000ade: 460d mov r5, r1 +10000ae0: b083 sub sp, #12 +10000ae2: f3ef 8405 mrs r4, IPSR +10000ae6: b2e4 uxtb r4, r4 +10000ae8: b13c cbz r4, 10000afa +10000aea: 4b2d ldr r3, [pc, #180] @ (10000ba0 ) +10000aec: 6a5a ldr r2, [r3, #36] @ 0x24 +10000aee: 42aa cmp r2, r5 +10000af0: d21c bcs.n 10000b2c +10000af2: 2000 movs r0, #0 +10000af4: b003 add sp, #12 +10000af6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000afa: 4f2a ldr r7, [pc, #168] @ (10000ba4 ) +10000afc: f8d7 900c ldr.w r9, [r7, #12] +10000b00: f897 8000 ldrb.w r8, [r7] +10000b04: 4648 mov r0, r9 +10000b06: f000 f863 bl 10000bd0 +10000b0a: f108 0804 add.w r8, r8, #4 +10000b0e: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000b12: 1a1b subs r3, r3, r0 +10000b14: 1a30 subs r0, r6, r0 +10000b16: eb65 0101 sbc.w r1, r5, r1 +10000b1a: 4298 cmp r0, r3 +10000b1c: f171 0100 sbcs.w r1, r1, #0 +10000b20: db10 blt.n 10000b44 +10000b22: bf20 wfe +10000b24: 4b1e ldr r3, [pc, #120] @ (10000ba0 ) +10000b26: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b28: 42aa cmp r2, r5 +10000b2a: d3e2 bcc.n 10000af2 +10000b2c: bf14 ite ne +10000b2e: 2401 movne r4, #1 +10000b30: 2400 moveq r4, #0 +10000b32: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b34: 42b3 cmp r3, r6 +10000b36: bf34 ite cc +10000b38: 4620 movcc r0, r4 +10000b3a: f044 0001 orrcs.w r0, r4, #1 +10000b3e: b003 add sp, #12 +10000b40: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b44: f000 f84c bl 10000be0 +10000b48: 4286 cmp r6, r0 +10000b4a: eb65 0101 sbc.w r1, r5, r1 +10000b4e: 2900 cmp r1, #0 +10000b50: db14 blt.n 10000b7c +10000b52: 4b15 ldr r3, [pc, #84] @ (10000ba8 ) +10000b54: 4638 mov r0, r7 +10000b56: e9cd 3400 strd r3, r4, [sp] +10000b5a: 4632 mov r2, r6 +10000b5c: 462b mov r3, r5 +10000b5e: f7ff feab bl 100008b8 +10000b62: 1e01 subs r1, r0, #0 +10000b64: dd0a ble.n 10000b7c +10000b66: 4b0e ldr r3, [pc, #56] @ (10000ba0 ) +10000b68: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b6a: 42aa cmp r2, r5 +10000b6c: d316 bcc.n 10000b9c +10000b6e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b70: 42b3 cmp r3, r6 +10000b72: d311 bcc.n 10000b98 +10000b74: 480b ldr r0, [pc, #44] @ (10000ba4 ) +10000b76: f7ff ff03 bl 10000980 +10000b7a: e7b6 b.n 10000aea +10000b7c: 4b08 ldr r3, [pc, #32] @ (10000ba0 ) +10000b7e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000b80: 42ac cmp r4, r5 +10000b82: d3b6 bcc.n 10000af2 +10000b84: 1b64 subs r4, r4, r5 +10000b86: bf18 it ne +10000b88: 2401 movne r4, #1 +10000b8a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b8c: 42b3 cmp r3, r6 +10000b8e: bf34 ite cc +10000b90: 4620 movcc r0, r4 +10000b92: f044 0001 orrcs.w r0, r4, #1 +10000b96: e7ad b.n 10000af4 +10000b98: 42aa cmp r2, r5 +10000b9a: d1eb bne.n 10000b74 +10000b9c: bf20 wfe +10000b9e: e7e9 b.n 10000b74 +10000ba0: 400b0000 .word 0x400b0000 +10000ba4: 2000022c .word 0x2000022c +10000ba8: 10000489 .word 0x10000489 + +10000bac : +10000bac: b410 push {r4} +10000bae: 4b05 ldr r3, [pc, #20] @ (10000bc4 ) +10000bb0: 4c05 ldr r4, [pc, #20] @ (10000bc8 ) +10000bb2: 4a06 ldr r2, [pc, #24] @ (10000bcc ) +10000bb4: 42a0 cmp r0, r4 +10000bb6: bf14 ite ne +10000bb8: 4618 movne r0, r3 +10000bba: 1c58 addeq r0, r3, #1 +10000bbc: f85d 4b04 ldr.w r4, [sp], #4 +10000bc0: f7ff bb84 b.w 100002cc +10000bc4: 200003f0 .word 0x200003f0 +10000bc8: 400b8000 .word 0x400b8000 +10000bcc: 100014c0 .word 0x100014c0 + +10000bd0 : +10000bd0: 4603 mov r3, r0 +10000bd2: 6a41 ldr r1, [r0, #36] @ 0x24 +10000bd4: 460a mov r2, r1 +10000bd6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000bd8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bda: 428a cmp r2, r1 +10000bdc: d1fa bne.n 10000bd4 +10000bde: 4770 bx lr + +10000be0 : +10000be0: 4b03 ldr r3, [pc, #12] @ (10000bf0 ) +10000be2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000be4: 460a mov r2, r1 +10000be6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000be8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bea: 4291 cmp r1, r2 +10000bec: d1fa bne.n 10000be4 +10000bee: 4770 bx lr +10000bf0: 400b0000 .word 0x400b0000 + +10000bf4 : +10000bf4: 4a07 ldr r2, [pc, #28] @ (10000c14 ) +10000bf6: 6a53 ldr r3, [r2, #36] @ 0x24 +10000bf8: 4299 cmp r1, r3 +10000bfa: d8fc bhi.n 10000bf6 +10000bfc: 4299 cmp r1, r3 +10000bfe: d107 bne.n 10000c10 +10000c00: 4b04 ldr r3, [pc, #16] @ (10000c14 ) +10000c02: e002 b.n 10000c0a +10000c04: 6a5a ldr r2, [r3, #36] @ 0x24 +10000c06: 4291 cmp r1, r2 +10000c08: d102 bne.n 10000c10 +10000c0a: 6a9a ldr r2, [r3, #40] @ 0x28 +10000c0c: 4290 cmp r0, r2 +10000c0e: d8f9 bhi.n 10000c04 +10000c10: 4770 bx lr +10000c12: bf00 nop +10000c14: 400b0000 .word 0x400b0000 + +10000c18 : +10000c18: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000c1c: ea4f 0c8c mov.w ip, ip, lsl #2 +10000c20: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000c24: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000c28: b5f0 push {r4, r5, r6, r7, lr} +10000c2a: 4616 mov r6, r2 +10000c2c: f8dc 2004 ldr.w r2, [ip, #4] +10000c30: 1f05 subs r5, r0, #4 +10000c32: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000c36: bf38 it cc +10000c38: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000c3c: b2ed uxtb r5, r5 +10000c3e: bf38 it cc +10000c40: f8cc 2004 strcc.w r2, [ip, #4] +10000c44: 2d01 cmp r5, #1 +10000c46: d92a bls.n 10000c9e +10000c48: f44f 6700 mov.w r7, #2048 @ 0x800 +10000c4c: 4c25 ldr r4, [pc, #148] @ (10000ce4 ) +10000c4e: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000c52: 6017 str r7, [r2, #0] +10000c54: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000c58: b9b2 cbnz r2, 10000c88 +10000c5a: f8dc 2000 ldr.w r2, [ip] +10000c5e: 2d01 cmp r5, #1 +10000c60: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000c64: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000c68: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000c6c: 6032 str r2, [r6, #0] +10000c6e: d92a bls.n 10000cc6 +10000c70: f44f 6100 mov.w r1, #2048 @ 0x800 +10000c74: f844 3020 str.w r3, [r4, r0, lsl #2] +10000c78: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000c7c: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000c80: 6011 str r1, [r2, #0] +10000c82: f8cc 3004 str.w r3, [ip, #4] +10000c86: bdf0 pop {r4, r5, r6, r7, pc} +10000c88: 6967 ldr r7, [r4, #20] +10000c8a: fbb7 fef2 udiv lr, r7, r2 +10000c8e: f10e 0e01 add.w lr, lr, #1 +10000c92: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000c96: f1be 0e03 subs.w lr, lr, #3 +10000c9a: d2fc bcs.n 10000c96 +10000c9c: e7dd b.n 10000c5a +10000c9e: 2901 cmp r1, #1 +10000ca0: d1d2 bne.n 10000c48 +10000ca2: 2403 movs r4, #3 +10000ca4: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000ca8: 6014 str r4, [r2, #0] +10000caa: f8dc 2008 ldr.w r2, [ip, #8] +10000cae: 07d2 lsls r2, r2, #31 +10000cb0: d5fb bpl.n 10000caa +10000cb2: f8dc 2000 ldr.w r2, [ip] +10000cb6: 4c0b ldr r4, [pc, #44] @ (10000ce4 ) +10000cb8: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000cbc: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000cc0: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000cc4: 6032 str r2, [r6, #0] +10000cc6: 2201 movs r2, #1 +10000cc8: f8dc 5000 ldr.w r5, [ip] +10000ccc: 404d eors r5, r1 +10000cce: f005 0503 and.w r5, r5, #3 +10000cd2: 6035 str r5, [r6, #0] +10000cd4: fa02 f101 lsl.w r1, r2, r1 +10000cd8: f8dc 2008 ldr.w r2, [ip, #8] +10000cdc: 420a tst r2, r1 +10000cde: d0fb beq.n 10000cd8 +10000ce0: e7c6 b.n 10000c70 +10000ce2: bf00 nop +10000ce4: 200003f4 .word 0x200003f4 + +10000ce8 : +10000ce8: 4b01 ldr r3, [pc, #4] @ (10000cf0 ) +10000cea: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000cee: 4770 bx lr +10000cf0: 200003f4 .word 0x200003f4 + +10000cf4 : +10000cf4: b470 push {r4, r5, r6} +10000cf6: 9d03 ldr r5, [sp, #12] +10000cf8: 6804 ldr r4, [r0, #0] +10000cfa: 032d lsls r5, r5, #12 +10000cfc: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000d00: 4b1b ldr r3, [pc, #108] @ (10000d70 ) +10000d02: 2c00 cmp r4, #0 +10000d04: fbb3 f3f1 udiv r3, r3, r1 +10000d08: fbb2 f6f3 udiv r6, r2, r3 +10000d0c: db1f blt.n 10000d4e +10000d0e: 4a19 ldr r2, [pc, #100] @ (10000d74 ) +10000d10: 4b19 ldr r3, [pc, #100] @ (10000d78 ) +10000d12: 4290 cmp r0, r2 +10000d14: bf14 ite ne +10000d16: f44f 4280 movne.w r2, #16384 @ 0x4000 +10000d1a: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10000d1e: 4c17 ldr r4, [pc, #92] @ (10000d7c ) +10000d20: 601a str r2, [r3, #0] +10000d22: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000d26: 601a str r2, [r3, #0] +10000d28: 68a3 ldr r3, [r4, #8] +10000d2a: ea32 0303 bics.w r3, r2, r3 +10000d2e: d1fb bne.n 10000d28 +10000d30: 2221 movs r2, #33 @ 0x21 +10000d32: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10000d36: 3304 adds r3, #4 +10000d38: 6001 str r1, [r0, #0] +10000d3a: 6086 str r6, [r0, #8] +10000d3c: 601a str r2, [r3, #0] +10000d3e: 6802 ldr r2, [r0, #0] +10000d40: 2a00 cmp r2, #0 +10000d42: dafc bge.n 10000d3e +10000d44: 2208 movs r2, #8 +10000d46: 60c5 str r5, [r0, #12] +10000d48: 601a str r2, [r3, #0] +10000d4a: bc70 pop {r4, r5, r6} +10000d4c: 4770 bx lr +10000d4e: 6803 ldr r3, [r0, #0] +10000d50: f003 033f and.w r3, r3, #63 @ 0x3f +10000d54: 428b cmp r3, r1 +10000d56: d1da bne.n 10000d0e +10000d58: 6883 ldr r3, [r0, #8] +10000d5a: f3c3 030b ubfx r3, r3, #0, #12 +10000d5e: 42b3 cmp r3, r6 +10000d60: d1d5 bne.n 10000d0e +10000d62: 68c3 ldr r3, [r0, #12] +10000d64: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10000d68: 42ab cmp r3, r5 +10000d6a: d1d0 bne.n 10000d0e +10000d6c: e7ed b.n 10000d4a +10000d6e: bf00 nop +10000d70: 00b71b00 .word 0x00b71b00 +10000d74: 40058000 .word 0x40058000 +10000d78: 40022000 .word 0x40022000 +10000d7c: 40020000 .word 0x40020000 + +10000d80 : +10000d80: 2301 movs r3, #1 +10000d82: eb00 0040 add.w r0, r0, r0, lsl #1 +10000d86: 0080 lsls r0, r0, #2 +10000d88: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000d8c: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10000d90: 6041 str r1, [r0, #4] +10000d92: 6003 str r3, [r0, #0] +10000d94: 4770 bx lr +10000d96: bf00 nop + +10000d98 : +10000d98: 2300 movs r3, #0 +10000d9a: 8adb ldrh r3, [r3, #22] +10000d9c: 2200 movs r2, #0 +10000d9e: e842 f200 tt r2, r2 +10000da2: 0252 lsls r2, r2, #9 +10000da4: d401 bmi.n 10000daa +10000da6: 2110 movs r1, #16 +10000da8: 4718 bx r3 +10000daa: 2104 movs r1, #4 +10000dac: 4718 bx r3 +10000dae: bf00 nop + +10000db0 : +10000db0: 4a03 ldr r2, [pc, #12] @ (10000dc0 ) +10000db2: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10000db6: 2b00 cmp r3, #0 +10000db8: d0fb beq.n 10000db2 +10000dba: f3bf 8f5f dmb sy +10000dbe: 4770 bx lr +10000dc0: 400e0000 .word 0x400e0000 + +10000dc4 : +10000dc4: 2100 movs r1, #0 +10000dc6: 4b04 ldr r3, [pc, #16] @ (10000dd8 ) +10000dc8: 4a04 ldr r2, [pc, #16] @ (10000ddc ) +10000dca: f3bf 8f5f dmb sy +10000dce: f843 1b04 str.w r1, [r3], #4 +10000dd2: 4293 cmp r3, r2 +10000dd4: d1f9 bne.n 10000dca +10000dd6: 4770 bx lr +10000dd8: 400e080c .word 0x400e080c +10000ddc: 400e082c .word 0x400e082c + +10000de0 : +10000de0: b410 push {r4} +10000de2: f44f 708d mov.w r0, #282 @ 0x11a +10000de6: f44f 642a mov.w r4, #2720 @ 0xaa0 +10000dea: 4a06 ldr r2, [pc, #24] @ (10000e04 ) +10000dec: 4b06 ldr r3, [pc, #24] @ (10000e08 ) +10000dee: 4907 ldr r1, [pc, #28] @ (10000e0c ) +10000df0: 6014 str r4, [r2, #0] +10000df2: 60d0 str r0, [r2, #12] +10000df4: 6019 str r1, [r3, #0] +10000df6: 6853 ldr r3, [r2, #4] +10000df8: 2b00 cmp r3, #0 +10000dfa: dafc bge.n 10000df6 +10000dfc: f85d 4b04 ldr.w r4, [sp], #4 +10000e00: 4770 bx lr +10000e02: bf00 nop +10000e04: 40048000 .word 0x40048000 +10000e08: 4004a000 .word 0x4004a000 +10000e0c: 00fab000 .word 0x00fab000 + +10000e10 : +10000e10: 4770 bx lr +10000e12: bf00 nop + +10000e14 : +10000e14: b508 push {r3, lr} +10000e16: 4801 ldr r0, [pc, #4] @ (10000e1c ) +10000e18: f7ff fa40 bl 1000029c +10000e1c: 100014e4 .word 0x100014e4 + +10000e20 : +10000e20: b538 push {r3, r4, r5, lr} +10000e22: 4c05 ldr r4, [pc, #20] @ (10000e38 ) +10000e24: 4d05 ldr r5, [pc, #20] @ (10000e3c ) +10000e26: 42ac cmp r4, r5 +10000e28: d204 bcs.n 10000e34 +10000e2a: f854 3b04 ldr.w r3, [r4], #4 +10000e2e: 4798 blx r3 +10000e30: 42ac cmp r4, r5 +10000e32: d3fa bcc.n 10000e2a +10000e34: bd38 pop {r3, r4, r5, pc} +10000e36: bf00 nop +10000e38: 10001468 .word 0x10001468 +10000e3c: 100014a8 .word 0x100014a8 + +10000e40 : +10000e40: b410 push {r4} +10000e42: 4807 ldr r0, [pc, #28] @ (10000e60 ) +10000e44: 4c07 ldr r4, [pc, #28] @ (10000e64 ) +10000e46: 4b08 ldr r3, [pc, #32] @ (10000e68 ) +10000e48: 4a08 ldr r2, [pc, #32] @ (10000e6c ) +10000e4a: 4909 ldr r1, [pc, #36] @ (10000e70 ) +10000e4c: 6004 str r4, [r0, #0] +10000e4e: 601a str r2, [r3, #0] +10000e50: 688b ldr r3, [r1, #8] +10000e52: ea32 0303 bics.w r3, r2, r3 +10000e56: d1fb bne.n 10000e50 +10000e58: f85d 4b04 ldr.w r4, [sp], #4 +10000e5c: 4770 bx lr +10000e5e: bf00 nop +10000e60: 40022000 .word 0x40022000 +10000e64: efef3b7f .word 0xefef3b7f +10000e68: 40023000 .word 0x40023000 +10000e6c: 03f3fff6 .word 0x03f3fff6 +10000e70: 40020000 .word 0x40020000 + +10000e74 : +10000e74: 4b04 ldr r3, [pc, #16] @ (10000e88 ) +10000e76: 6cdb ldr r3, [r3, #76] @ 0x4c +10000e78: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10000e7c: d103 bne.n 10000e86 +10000e7e: f44f 2280 mov.w r2, #262144 @ 0x40000 +10000e82: 4b02 ldr r3, [pc, #8] @ (10000e8c ) +10000e84: 64da str r2, [r3, #76] @ 0x4c +10000e86: 4770 bx lr +10000e88: 50110000 .word 0x50110000 +10000e8c: 50112000 .word 0x50112000 + +10000e90 : +10000e90: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000e94: 4b04 ldr r3, [pc, #16] @ (10000ea8 ) +10000e96: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10000e9a: 430b orrs r3, r1 +10000e9c: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10000ea0: ee10 0430 dcp_rcmp r0 +10000ea4: 4770 bx lr +10000ea6: bf00 nop +10000ea8: 00300303 .word 0x00300303 + +10000eac : +10000eac: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10000eb0: 4b04 ldr r3, [pc, #16] @ (10000ec4 ) +10000eb2: 4a05 ldr r2, [pc, #20] @ (10000ec8 ) +10000eb4: 6019 str r1, [r3, #0] +10000eb6: 6893 ldr r3, [r2, #8] +10000eb8: 43db mvns r3, r3 +10000eba: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10000ebe: d1fa bne.n 10000eb6 +10000ec0: 4770 bx lr +10000ec2: bf00 nop +10000ec4: 40023000 .word 0x40023000 +10000ec8: 40020000 .word 0x40020000 + +10000ecc : +10000ecc: b510 push {r4, lr} +10000ece: f245 2053 movw r0, #21075 @ 0x5253 +10000ed2: f7ff ff61 bl 10000d98 +10000ed6: e8bd 4010 ldmia.w sp!, {r4, lr} +10000eda: 4603 mov r3, r0 +10000edc: 2004 movs r0, #4 +10000ede: 4718 bx r3 + +10000ee0 : +10000ee0: b510 push {r4, lr} +10000ee2: f245 2053 movw r0, #21075 @ 0x5253 +10000ee6: f7ff ff57 bl 10000d98 +10000eea: e8bd 4010 ldmia.w sp!, {r4, lr} +10000eee: 4603 mov r3, r0 +10000ef0: 2001 movs r0, #1 +10000ef2: 4718 bx r3 + +10000ef4 : +10000ef4: f7ff ba2a b.w 1000034c + +10000ef8 : +10000ef8: 4914 ldr r1, [pc, #80] @ (10000f4c ) +10000efa: 4b15 ldr r3, [pc, #84] @ (10000f50 ) +10000efc: b570 push {r4, r5, r6, lr} +10000efe: 1a5c subs r4, r3, r1 +10000f00: 10a6 asrs r6, r4, #2 +10000f02: 2e44 cmp r6, #68 @ 0x44 +10000f04: 4632 mov r2, r6 +10000f06: bf28 it cs +10000f08: 2244 movcs r2, #68 @ 0x44 +10000f0a: 4d12 ldr r5, [pc, #72] @ (10000f54 ) +10000f0c: 0092 lsls r2, r2, #2 +10000f0e: 4628 mov r0, r5 +10000f10: f000 f9fa bl 10001308 +10000f14: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10000f18: d813 bhi.n 10000f42 +10000f1a: 4a0f ldr r2, [pc, #60] @ (10000f58 ) +10000f1c: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10000f20: d012 beq.n 10000f48 +10000f22: 192b adds r3, r5, r4 +10000f24: 0841 lsrs r1, r0, #1 +10000f26: eb03 01c1 add.w r1, r3, r1, lsl #3 +10000f2a: e9c3 2200 strd r2, r2, [r3] +10000f2e: 3308 adds r3, #8 +10000f30: 428b cmp r3, r1 +10000f32: d1fa bne.n 10000f2a +10000f34: 07c3 lsls r3, r0, #31 +10000f36: d504 bpl.n 10000f42 +10000f38: f020 0001 bic.w r0, r0, #1 +10000f3c: 4430 add r0, r6 +10000f3e: f845 2020 str.w r2, [r5, r0, lsl #2] +10000f42: 4b06 ldr r3, [pc, #24] @ (10000f5c ) +10000f44: 609d str r5, [r3, #8] +10000f46: bd70 pop {r4, r5, r6, pc} +10000f48: 2043 movs r0, #67 @ 0x43 +10000f4a: e7f8 b.n 10000f3e +10000f4c: 10000000 .word 0x10000000 +10000f50: 10000110 .word 0x10000110 +10000f54: 20000000 .word 0x20000000 +10000f58: 10000111 .word 0x10000111 +10000f5c: e000ed00 .word 0xe000ed00 + +10000f60 : +10000f60: 2300 movs r3, #0 +10000f62: b570 push {r4, r5, r6, lr} +10000f64: 4c2b ldr r4, [pc, #172] @ (10001014 ) +10000f66: b082 sub sp, #8 +10000f68: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10000f6c: f7ff ff38 bl 10000de0 +10000f70: 2201 movs r2, #1 +10000f72: 4b29 ldr r3, [pc, #164] @ (10001018 ) +10000f74: 63da str r2, [r3, #60] @ 0x3c +10000f76: 6c63 ldr r3, [r4, #68] @ 0x44 +10000f78: 2b01 cmp r3, #1 +10000f7a: d1fc bne.n 10000f76 +10000f7c: 2103 movs r1, #3 +10000f7e: 4a26 ldr r2, [pc, #152] @ (10001018 ) +10000f80: 4b24 ldr r3, [pc, #144] @ (10001014 ) +10000f82: 6311 str r1, [r2, #48] @ 0x30 +10000f84: 6b9c ldr r4, [r3, #56] @ 0x38 +10000f86: 2c01 cmp r4, #1 +10000f88: d1fc bne.n 10000f84 +10000f8a: 2602 movs r6, #2 +10000f8c: 2505 movs r5, #5 +10000f8e: 4621 mov r1, r4 +10000f90: 2305 movs r3, #5 +10000f92: 4a22 ldr r2, [pc, #136] @ (1000101c ) +10000f94: 4822 ldr r0, [pc, #136] @ (10001020 ) +10000f96: 9600 str r6, [sp, #0] +10000f98: f7ff feac bl 10000cf4 +10000f9c: 4621 mov r1, r4 +10000f9e: 462b mov r3, r5 +10000fa0: 4a20 ldr r2, [pc, #128] @ (10001024 ) +10000fa2: 4821 ldr r0, [pc, #132] @ (10001028 ) +10000fa4: 9500 str r5, [sp, #0] +10000fa6: f7ff fea5 bl 10000cf4 +10000faa: 2200 movs r2, #0 +10000fac: 2004 movs r0, #4 +10000fae: 4631 mov r1, r6 +10000fb0: 4b1e ldr r3, [pc, #120] @ (1000102c ) +10000fb2: f7ff fe31 bl 10000c18 +10000fb6: 4621 mov r1, r4 +10000fb8: 4628 mov r0, r5 +10000fba: 2200 movs r2, #0 +10000fbc: 4b1c ldr r3, [pc, #112] @ (10001030 ) +10000fbe: f7ff fe2b bl 10000c18 +10000fc2: 2200 movs r2, #0 +10000fc4: 2008 movs r0, #8 +10000fc6: 4611 mov r1, r2 +10000fc8: 4b1a ldr r3, [pc, #104] @ (10001034 ) +10000fca: f7ff fe25 bl 10000c18 +10000fce: 2200 movs r2, #0 +10000fd0: 2009 movs r0, #9 +10000fd2: 4611 mov r1, r2 +10000fd4: 4b17 ldr r3, [pc, #92] @ (10001034 ) +10000fd6: f7ff fe1f bl 10000c18 +10000fda: 2200 movs r2, #0 +10000fdc: 2006 movs r0, #6 +10000fde: 4611 mov r1, r2 +10000fe0: 4b13 ldr r3, [pc, #76] @ (10001030 ) +10000fe2: f7ff fe19 bl 10000c18 +10000fe6: 2200 movs r2, #0 +10000fe8: 4b11 ldr r3, [pc, #68] @ (10001030 ) +10000fea: 2007 movs r0, #7 +10000fec: 4611 mov r1, r2 +10000fee: f7ff fe13 bl 10000c18 +10000ff2: 2004 movs r0, #4 +10000ff4: f7ff fe78 bl 10000ce8 +10000ff8: 2400 movs r4, #0 +10000ffa: 4b0f ldr r3, [pc, #60] @ (10001038 ) +10000ffc: fba3 3500 umull r3, r5, r3, r0 +10001000: 0cad lsrs r5, r5, #18 +10001002: b2e0 uxtb r0, r4 +10001004: 4629 mov r1, r5 +10001006: 3401 adds r4, #1 +10001008: f7ff feba bl 10000d80 +1000100c: 2c06 cmp r4, #6 +1000100e: d1f8 bne.n 10001002 +10001010: b002 add sp, #8 +10001012: bd70 pop {r4, r5, r6, pc} +10001014: 40010000 .word 0x40010000 +10001018: 40013000 .word 0x40013000 +1000101c: 59682f00 .word 0x59682f00 +10001020: 40050000 .word 0x40050000 +10001024: 47868c00 .word 0x47868c00 +10001028: 40058000 .word 0x40058000 +1000102c: 00b71b00 .word 0x00b71b00 +10001030: 08f0d180 .word 0x08f0d180 +10001034: 02dc6c00 .word 0x02dc6c00 +10001038: 431bde83 .word 0x431bde83 + +1000103c <_out_char>: +1000103c: b900 cbnz r0, 10001040 <_out_char+0x4> +1000103e: 4770 bx lr +10001040: f000 b902 b.w 10001248 <__wrap_putchar> + +10001044 : +10001044: b510 push {r4, lr} +10001046: 4b09 ldr r3, [pc, #36] @ (1000106c ) +10001048: b084 sub sp, #16 +1000104a: 681c ldr r4, [r3, #0] +1000104c: b14c cbz r4, 10001062 +1000104e: 4603 mov r3, r0 +10001050: 9100 str r1, [sp, #0] +10001052: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001056: a903 add r1, sp, #12 +10001058: 4805 ldr r0, [pc, #20] @ (10001070 ) +1000105a: 47a0 blx r4 +1000105c: 2001 movs r0, #1 +1000105e: b004 add sp, #16 +10001060: bd10 pop {r4, pc} +10001062: f000 f933 bl 100012cc <__wrap_puts> +10001066: 4620 mov r0, r4 +10001068: b004 add sp, #16 +1000106a: bd10 pop {r4, pc} +1000106c: 20000424 .word 0x20000424 +10001070: 1000103d .word 0x1000103d + +10001074 <_exit>: +10001074: be00 bkpt 0x0000 +10001076: e7fd b.n 10001074 <_exit> + +10001078 : +10001078: b508 push {r3, lr} +1000107a: f7ff fffb bl 10001074 <_exit> +1000107e: bf00 nop + +10001080 : +10001080: b538 push {r3, r4, r5, lr} +10001082: 4c06 ldr r4, [pc, #24] @ (1000109c ) +10001084: 4d06 ldr r5, [pc, #24] @ (100010a0 ) +10001086: f7ff fecb bl 10000e20 +1000108a: 42ac cmp r4, r5 +1000108c: d204 bcs.n 10001098 +1000108e: f854 3b04 ldr.w r3, [r4], #4 +10001092: 4798 blx r3 +10001094: 42ac cmp r4, r5 +10001096: d3fa bcc.n 1000108e +10001098: bd38 pop {r3, r4, r5, pc} +1000109a: bf00 nop +1000109c: 100014a8 .word 0x100014a8 +100010a0: 100014ac .word 0x100014ac + +100010a4 : +100010a4: 6803 ldr r3, [r0, #0] +100010a6: 4608 mov r0, r1 +100010a8: 4611 mov r1, r2 +100010aa: 4718 bx r3 + +100010ac : +100010ac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100010b0: 4615 mov r5, r2 +100010b2: 7d42 ldrb r2, [r0, #21] +100010b4: 4607 mov r7, r0 +100010b6: 4688 mov r8, r1 +100010b8: 2a00 cmp r2, #0 +100010ba: d046 beq.n 1000114a +100010bc: 2d00 cmp r5, #0 +100010be: dd1d ble.n 100010fc +100010c0: 780b ldrb r3, [r1, #0] +100010c2: 2b0a cmp r3, #10 +100010c4: d023 beq.n 1000110e +100010c6: 2d01 cmp r5, #1 +100010c8: f04f 0c00 mov.w ip, #0 +100010cc: d018 beq.n 10001100 +100010ce: 4646 mov r6, r8 +100010d0: 2401 movs r4, #1 +100010d2: f816 2f01 ldrb.w r2, [r6, #1]! +100010d6: 4621 mov r1, r4 +100010d8: 2a0a cmp r2, #10 +100010da: f104 0401 add.w r4, r4, #1 +100010de: d022 beq.n 10001126 +100010e0: 42a5 cmp r5, r4 +100010e2: d1f6 bne.n 100010d2 +100010e4: 4565 cmp r5, ip +100010e6: dc0b bgt.n 10001100 +100010e8: eb08 0305 add.w r3, r8, r5 +100010ec: f813 3c01 ldrb.w r3, [r3, #-1] +100010f0: f1a3 030d sub.w r3, r3, #13 +100010f4: fab3 f383 clz r3, r3 +100010f8: 095b lsrs r3, r3, #5 +100010fa: 753b strb r3, [r7, #20] +100010fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10001100: 683b ldr r3, [r7, #0] +10001102: eba5 010c sub.w r1, r5, ip +10001106: eb08 000c add.w r0, r8, ip +1000110a: 4798 blx r3 +1000110c: e7ec b.n 100010e8 +1000110e: 7d03 ldrb r3, [r0, #20] +10001110: 2b00 cmp r3, #0 +10001112: d1d8 bne.n 100010c6 +10001114: 6803 ldr r3, [r0, #0] +10001116: 2102 movs r1, #2 +10001118: 480f ldr r0, [pc, #60] @ (10001158 ) +1000111a: 4798 blx r3 +1000111c: 2d01 cmp r5, #1 +1000111e: d0e3 beq.n 100010e8 +10001120: f04f 0c01 mov.w ip, #1 +10001124: e7d3 b.n 100010ce +10001126: f816 3c01 ldrb.w r3, [r6, #-1] +1000112a: 2b0d cmp r3, #13 +1000112c: d0d8 beq.n 100010e0 +1000112e: 458c cmp ip, r1 +10001130: eb08 000c add.w r0, r8, ip +10001134: eba1 010c sub.w r1, r1, ip +10001138: da01 bge.n 1000113e +1000113a: 683b ldr r3, [r7, #0] +1000113c: 4798 blx r3 +1000113e: 2102 movs r1, #2 +10001140: 4805 ldr r0, [pc, #20] @ (10001158 ) +10001142: 683b ldr r3, [r7, #0] +10001144: 4798 blx r3 +10001146: 46a4 mov ip, r4 +10001148: e7ca b.n 100010e0 +1000114a: 4629 mov r1, r5 +1000114c: 4640 mov r0, r8 +1000114e: 683b ldr r3, [r7, #0] +10001150: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001154: 4718 bx r3 +10001156: bf00 nop +10001158: 100015ac .word 0x100015ac + +1000115c : +1000115c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10001160: b082 sub sp, #8 +10001162: 460d mov r5, r1 +10001164: 4691 mov r9, r2 +10001166: 461c mov r4, r3 +10001168: 4606 mov r6, r0 +1000116a: f7ff fd39 bl 10000be0 +1000116e: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10001172: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001176: 4a2e ldr r2, [pc, #184] @ (10001230 ) +10001178: 1882 adds r2, r0, r2 +1000117a: f141 0300 adc.w r3, r1, #0 +1000117e: 4594 cmp ip, r2 +10001180: eb77 0103 sbcs.w r1, r7, r3 +10001184: bf3c itt cc +10001186: 4662 movcc r2, ip +10001188: 463b movcc r3, r7 +1000118a: 482a ldr r0, [pc, #168] @ (10001234 ) +1000118c: f000 f968 bl 10001460 <__mutex_try_enter_block_until_veneer> +10001190: 1c6b adds r3, r5, #1 +10001192: 4680 mov r8, r0 +10001194: d040 beq.n 10001218 +10001196: b30c cbz r4, 100011dc +10001198: 4f27 ldr r7, [pc, #156] @ (10001238 ) +1000119a: 4b28 ldr r3, [pc, #160] @ (1000123c ) +1000119c: 681c ldr r4, [r3, #0] +1000119e: b1b4 cbz r4, 100011ce +100011a0: f1b9 0f00 cmp.w r9, #0 +100011a4: d11c bne.n 100011e0 +100011a6: f8df 909c ldr.w r9, [pc, #156] @ 10001244 +100011aa: e001 b.n 100011b0 +100011ac: 6924 ldr r4, [r4, #16] +100011ae: b174 cbz r4, 100011ce +100011b0: 6823 ldr r3, [r4, #0] +100011b2: 2b00 cmp r3, #0 +100011b4: d0fa beq.n 100011ac +100011b6: f8d9 3000 ldr.w r3, [r9] +100011ba: b10b cbz r3, 100011c0 +100011bc: 429c cmp r4, r3 +100011be: d1f5 bne.n 100011ac +100011c0: 4620 mov r0, r4 +100011c2: 462a mov r2, r5 +100011c4: 4631 mov r1, r6 +100011c6: 47b8 blx r7 +100011c8: 6924 ldr r4, [r4, #16] +100011ca: 2c00 cmp r4, #0 +100011cc: d1f0 bne.n 100011b0 +100011ce: f1b8 0f00 cmp.w r8, #0 +100011d2: d126 bne.n 10001222 +100011d4: 4628 mov r0, r5 +100011d6: b002 add sp, #8 +100011d8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100011dc: 4f18 ldr r7, [pc, #96] @ (10001240 ) +100011de: e7dc b.n 1000119a +100011e0: f04f 0a0a mov.w sl, #10 +100011e4: f8df 905c ldr.w r9, [pc, #92] @ 10001244 +100011e8: e002 b.n 100011f0 +100011ea: 6924 ldr r4, [r4, #16] +100011ec: 2c00 cmp r4, #0 +100011ee: d0ee beq.n 100011ce +100011f0: 6823 ldr r3, [r4, #0] +100011f2: 2b00 cmp r3, #0 +100011f4: d0f9 beq.n 100011ea +100011f6: f8d9 3000 ldr.w r3, [r9] +100011fa: b10b cbz r3, 10001200 +100011fc: 42a3 cmp r3, r4 +100011fe: d1f4 bne.n 100011ea +10001200: 462a mov r2, r5 +10001202: 4631 mov r1, r6 +10001204: 4620 mov r0, r4 +10001206: 47b8 blx r7 +10001208: 2201 movs r2, #1 +1000120a: 4620 mov r0, r4 +1000120c: f10d 0107 add.w r1, sp, #7 +10001210: f88d a007 strb.w sl, [sp, #7] +10001214: 47b8 blx r7 +10001216: e7e8 b.n 100011ea +10001218: 4630 mov r0, r6 +1000121a: f000 f8eb bl 100013f4 +1000121e: 4605 mov r5, r0 +10001220: e7b9 b.n 10001196 +10001222: 4804 ldr r0, [pc, #16] @ (10001234 ) +10001224: f000 f918 bl 10001458 <__mutex_exit_veneer> +10001228: 4628 mov r0, r5 +1000122a: b002 add sp, #8 +1000122c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001230: 000f4240 .word 0x000f4240 +10001234: 20000244 .word 0x20000244 +10001238: 100010ad .word 0x100010ad +1000123c: 2000041c .word 0x2000041c +10001240: 100010a5 .word 0x100010a5 +10001244: 20000420 .word 0x20000420 + +10001248 <__wrap_putchar>: +10001248: b5f0 push {r4, r5, r6, r7, lr} +1000124a: b083 sub sp, #12 +1000124c: 4606 mov r6, r0 +1000124e: f88d 0007 strb.w r0, [sp, #7] +10001252: f7ff fcc5 bl 10000be0 +10001256: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000125a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000125e: 4a17 ldr r2, [pc, #92] @ (100012bc <__wrap_putchar+0x74>) +10001260: 1882 adds r2, r0, r2 +10001262: f141 0300 adc.w r3, r1, #0 +10001266: 4295 cmp r5, r2 +10001268: eb74 0103 sbcs.w r1, r4, r3 +1000126c: bf3c itt cc +1000126e: 4623 movcc r3, r4 +10001270: 462a movcc r2, r5 +10001272: 4813 ldr r0, [pc, #76] @ (100012c0 <__wrap_putchar+0x78>) +10001274: f000 f8f4 bl 10001460 <__mutex_try_enter_block_until_veneer> +10001278: 4b12 ldr r3, [pc, #72] @ (100012c4 <__wrap_putchar+0x7c>) +1000127a: 4607 mov r7, r0 +1000127c: 681c ldr r4, [r3, #0] +1000127e: b19c cbz r4, 100012a8 <__wrap_putchar+0x60> +10001280: 4d11 ldr r5, [pc, #68] @ (100012c8 <__wrap_putchar+0x80>) +10001282: e001 b.n 10001288 <__wrap_putchar+0x40> +10001284: 6924 ldr r4, [r4, #16] +10001286: b17c cbz r4, 100012a8 <__wrap_putchar+0x60> +10001288: 6823 ldr r3, [r4, #0] +1000128a: 2b00 cmp r3, #0 +1000128c: d0fa beq.n 10001284 <__wrap_putchar+0x3c> +1000128e: 682b ldr r3, [r5, #0] +10001290: b10b cbz r3, 10001296 <__wrap_putchar+0x4e> +10001292: 429c cmp r4, r3 +10001294: d1f6 bne.n 10001284 <__wrap_putchar+0x3c> +10001296: 4620 mov r0, r4 +10001298: 2201 movs r2, #1 +1000129a: f10d 0107 add.w r1, sp, #7 +1000129e: f7ff ff05 bl 100010ac +100012a2: 6924 ldr r4, [r4, #16] +100012a4: 2c00 cmp r4, #0 +100012a6: d1ef bne.n 10001288 <__wrap_putchar+0x40> +100012a8: b917 cbnz r7, 100012b0 <__wrap_putchar+0x68> +100012aa: 4630 mov r0, r6 +100012ac: b003 add sp, #12 +100012ae: bdf0 pop {r4, r5, r6, r7, pc} +100012b0: 4803 ldr r0, [pc, #12] @ (100012c0 <__wrap_putchar+0x78>) +100012b2: f000 f8d1 bl 10001458 <__mutex_exit_veneer> +100012b6: 4630 mov r0, r6 +100012b8: b003 add sp, #12 +100012ba: bdf0 pop {r4, r5, r6, r7, pc} +100012bc: 000f4240 .word 0x000f4240 +100012c0: 20000244 .word 0x20000244 +100012c4: 2000041c .word 0x2000041c +100012c8: 20000420 .word 0x20000420 + +100012cc <__wrap_puts>: +100012cc: b538 push {r3, r4, r5, lr} +100012ce: 4604 mov r4, r0 +100012d0: f000 f890 bl 100013f4 +100012d4: 2301 movs r3, #1 +100012d6: 4605 mov r5, r0 +100012d8: 461a mov r2, r3 +100012da: 4620 mov r0, r4 +100012dc: 4629 mov r1, r5 +100012de: f7ff ff3d bl 1000115c +100012e2: 4b08 ldr r3, [pc, #32] @ (10001304 <__wrap_puts+0x38>) +100012e4: 681c ldr r4, [r3, #0] +100012e6: b12c cbz r4, 100012f4 <__wrap_puts+0x28> +100012e8: 6863 ldr r3, [r4, #4] +100012ea: b12b cbz r3, 100012f8 <__wrap_puts+0x2c> +100012ec: 4798 blx r3 +100012ee: 6924 ldr r4, [r4, #16] +100012f0: 2c00 cmp r4, #0 +100012f2: d1f9 bne.n 100012e8 <__wrap_puts+0x1c> +100012f4: 4628 mov r0, r5 +100012f6: bd38 pop {r3, r4, r5, pc} +100012f8: 6924 ldr r4, [r4, #16] +100012fa: 2c00 cmp r4, #0 +100012fc: d1f4 bne.n 100012e8 <__wrap_puts+0x1c> +100012fe: 4628 mov r0, r5 +10001300: bd38 pop {r3, r4, r5, pc} +10001302: bf00 nop +10001304: 2000041c .word 0x2000041c + +10001308 : +10001308: 4684 mov ip, r0 +1000130a: ea41 0300 orr.w r3, r1, r0 +1000130e: f013 0303 ands.w r3, r3, #3 +10001312: d149 bne.n 100013a8 +10001314: 3a40 subs r2, #64 @ 0x40 +10001316: d323 bcc.n 10001360 +10001318: 680b ldr r3, [r1, #0] +1000131a: 6003 str r3, [r0, #0] +1000131c: 684b ldr r3, [r1, #4] +1000131e: 6043 str r3, [r0, #4] +10001320: 688b ldr r3, [r1, #8] +10001322: 6083 str r3, [r0, #8] +10001324: 68cb ldr r3, [r1, #12] +10001326: 60c3 str r3, [r0, #12] +10001328: 690b ldr r3, [r1, #16] +1000132a: 6103 str r3, [r0, #16] +1000132c: 694b ldr r3, [r1, #20] +1000132e: 6143 str r3, [r0, #20] +10001330: 698b ldr r3, [r1, #24] +10001332: 6183 str r3, [r0, #24] +10001334: 69cb ldr r3, [r1, #28] +10001336: 61c3 str r3, [r0, #28] +10001338: 6a0b ldr r3, [r1, #32] +1000133a: 6203 str r3, [r0, #32] +1000133c: 6a4b ldr r3, [r1, #36] @ 0x24 +1000133e: 6243 str r3, [r0, #36] @ 0x24 +10001340: 6a8b ldr r3, [r1, #40] @ 0x28 +10001342: 6283 str r3, [r0, #40] @ 0x28 +10001344: 6acb ldr r3, [r1, #44] @ 0x2c +10001346: 62c3 str r3, [r0, #44] @ 0x2c +10001348: 6b0b ldr r3, [r1, #48] @ 0x30 +1000134a: 6303 str r3, [r0, #48] @ 0x30 +1000134c: 6b4b ldr r3, [r1, #52] @ 0x34 +1000134e: 6343 str r3, [r0, #52] @ 0x34 +10001350: 6b8b ldr r3, [r1, #56] @ 0x38 +10001352: 6383 str r3, [r0, #56] @ 0x38 +10001354: 6bcb ldr r3, [r1, #60] @ 0x3c +10001356: 63c3 str r3, [r0, #60] @ 0x3c +10001358: 3040 adds r0, #64 @ 0x40 +1000135a: 3140 adds r1, #64 @ 0x40 +1000135c: 3a40 subs r2, #64 @ 0x40 +1000135e: d2db bcs.n 10001318 +10001360: 3230 adds r2, #48 @ 0x30 +10001362: d30b bcc.n 1000137c +10001364: 680b ldr r3, [r1, #0] +10001366: 6003 str r3, [r0, #0] +10001368: 684b ldr r3, [r1, #4] +1000136a: 6043 str r3, [r0, #4] +1000136c: 688b ldr r3, [r1, #8] +1000136e: 6083 str r3, [r0, #8] +10001370: 68cb ldr r3, [r1, #12] +10001372: 60c3 str r3, [r0, #12] +10001374: 3010 adds r0, #16 +10001376: 3110 adds r1, #16 +10001378: 3a10 subs r2, #16 +1000137a: d2f3 bcs.n 10001364 +1000137c: 320c adds r2, #12 +1000137e: d305 bcc.n 1000138c +10001380: f851 3b04 ldr.w r3, [r1], #4 +10001384: f840 3b04 str.w r3, [r0], #4 +10001388: 3a04 subs r2, #4 +1000138a: d2f9 bcs.n 10001380 +1000138c: 3204 adds r2, #4 +1000138e: d008 beq.n 100013a2 +10001390: 07d2 lsls r2, r2, #31 +10001392: bf1c itt ne +10001394: f811 3b01 ldrbne.w r3, [r1], #1 +10001398: f800 3b01 strbne.w r3, [r0], #1 +1000139c: d301 bcc.n 100013a2 +1000139e: 880b ldrh r3, [r1, #0] +100013a0: 8003 strh r3, [r0, #0] +100013a2: 4660 mov r0, ip +100013a4: 4770 bx lr +100013a6: bf00 nop +100013a8: 2a08 cmp r2, #8 +100013aa: d313 bcc.n 100013d4 +100013ac: 078b lsls r3, r1, #30 +100013ae: d0b1 beq.n 10001314 +100013b0: f010 0303 ands.w r3, r0, #3 +100013b4: d0ae beq.n 10001314 +100013b6: f1c3 0304 rsb r3, r3, #4 +100013ba: 1ad2 subs r2, r2, r3 +100013bc: 07db lsls r3, r3, #31 +100013be: bf1c itt ne +100013c0: f811 3b01 ldrbne.w r3, [r1], #1 +100013c4: f800 3b01 strbne.w r3, [r0], #1 +100013c8: d3a4 bcc.n 10001314 +100013ca: f831 3b02 ldrh.w r3, [r1], #2 +100013ce: f820 3b02 strh.w r3, [r0], #2 +100013d2: e79f b.n 10001314 +100013d4: 3a04 subs r2, #4 +100013d6: d3d9 bcc.n 1000138c +100013d8: 3a01 subs r2, #1 +100013da: f811 3b01 ldrb.w r3, [r1], #1 +100013de: f800 3b01 strb.w r3, [r0], #1 +100013e2: d2f9 bcs.n 100013d8 +100013e4: 780b ldrb r3, [r1, #0] +100013e6: 7003 strb r3, [r0, #0] +100013e8: 784b ldrb r3, [r1, #1] +100013ea: 7043 strb r3, [r0, #1] +100013ec: 788b ldrb r3, [r1, #2] +100013ee: 7083 strb r3, [r0, #2] +100013f0: 4660 mov r0, ip +100013f2: 4770 bx lr + +100013f4 : +100013f4: f020 0103 bic.w r1, r0, #3 +100013f8: f010 0003 ands.w r0, r0, #3 +100013fc: f1c0 0000 rsb r0, r0, #0 +10001400: f851 3b04 ldr.w r3, [r1], #4 +10001404: f100 0c04 add.w ip, r0, #4 +10001408: ea4f 0ccc mov.w ip, ip, lsl #3 +1000140c: f06f 0200 mvn.w r2, #0 +10001410: bf1c itt ne +10001412: fa22 f20c lsrne.w r2, r2, ip +10001416: 4313 orrne r3, r2 +10001418: f04f 0c01 mov.w ip, #1 +1000141c: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001420: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001424: eba3 020c sub.w r2, r3, ip +10001428: ea22 0203 bic.w r2, r2, r3 +1000142c: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001430: bf04 itt eq +10001432: f851 3b04 ldreq.w r3, [r1], #4 +10001436: 3004 addeq r0, #4 +10001438: d0f4 beq.n 10001424 +1000143a: f1c2 0100 rsb r1, r2, #0 +1000143e: ea02 0201 and.w r2, r2, r1 +10001442: fab2 f282 clz r2, r2 +10001446: f1c2 021f rsb r2, r2, #31 +1000144a: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000144e: 4770 bx lr + +10001450 <_fini>: +10001450: b5f8 push {r3, r4, r5, r6, r7, lr} +10001452: bf00 nop +10001454: 0000 movs r0, r0 + ... + +10001458 <__mutex_exit_veneer>: +10001458: f85f f000 ldr.w pc, [pc] @ 1000145c <__mutex_exit_veneer+0x4> +1000145c: 200001e5 .word 0x200001e5 + +10001460 <__mutex_try_enter_block_until_veneer>: +10001460: f85f f000 ldr.w pc, [pc] @ 10001464 <__mutex_try_enter_block_until_veneer+0x4> +10001464: 2000017d .word 0x2000017d + +10001468 <__pre_init_runtime_init_bootrom_reset>: +10001468: 10000ecd .... + +1000146c <__pre_init_runtime_init_early_resets>: +1000146c: 10000e41 A... + +10001470 <__pre_init_runtime_init_usb_power_down>: +10001470: 10000e75 u... + +10001474 <__pre_init_runtime_init_clocks>: +10001474: 10000f61 a... + +10001478 <__pre_init_runtime_init_post_clock_resets>: +10001478: 10000ead .... + +1000147c <__pre_init_runtime_init_boot_locks_reset>: +1000147c: 10000dc5 .... + +10001480 <__pre_init_runtime_init_spin_locks_reset>: +10001480: 10000ef5 .... + +10001484 <__pre_init_runtime_init_bootrom_locking_enable>: +10001484: 10000db1 .... + +10001488 <__pre_init_runtime_init_mutex>: +10001488: 1000043d =... + +1000148c <__pre_init_runtime_init_install_ram_vector_table>: +1000148c: 10000ef9 .... + +10001490 <__pre_init_runtime_init_default_alarm_pool>: +10001490: 100007b9 .... + +10001494 <__pre_init_first_per_core_initializer>: +10001494: 10000e11 .... + +10001498 <__pre_init_runtime_init_per_core_bootrom_reset>: +10001498: 10000ee1 .... + +1000149c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000149c: 10000e91 .... + +100014a0 <__pre_init_spinlock_set_extexclall>: +100014a0: 1000033d =... + +100014a4 <__pre_init_runtime_init_per_core_irq_priorities>: +100014a4: 10000365 e... + +100014a8 <__frame_dummy_init_array_entry>: +100014a8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 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+:10169800126800230271C5E88F3F8CF3108801207F +:1016A80030BD00BF0368EFF3108272B6D3E8CFCF26 +:1016B8000121BCF1000FF9D1C3E84C1FBCF1000FA8 +:1016C800F4D1BFF35F8F4FF0FF0C0023016880F85F +:1016D80004C0C1E88F3F82F3108840BF704700BF45 +:1016E8005FF800F0D90A00101000000000000000A8 +:1016F80000000000000000000000000000000000E2 +:0C17080050020020000000000000000063 +:10171400D3DEFFFFFE010000FF01000024EAFFFF0B +:04172400793512AB56 +:040000051000014D99 +:00000001FF diff --git a/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.uf2 b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.uf2 new file mode 100644 index 0000000..47a2a55 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-c/build/0x0008_uninitialized-variables-c.uf2 differ diff --git a/WEEK04/0x0008_uninitialized-variables-c/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables-c/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables-c/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables-c/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-c/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables-d/.gitignore b/WEEK04/0x0008_uninitialized-variables-d/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0008_uninitialized-variables-d/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables-d/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-d/0x0008_uninitialized-variables-d.c b/WEEK04/0x0008_uninitialized-variables-d/0x0008_uninitialized-variables-d.c new file mode 100644 index 0000000..457ed9a --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/0x0008_uninitialized-variables-d.c @@ -0,0 +1,70 @@ +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) +{ + // gpio_init(LED_PIN); + /// gpio_set_dir(LED_PIN, GPIO_IN); + //// gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (LED_PIN), "r" (GPIO_OUT)); + /// gpio_put(LED_PIN, 0); + //// gpioc_bit_out_put(LED_PIN, 0); + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (LED_PIN), "r" (GPIO_OUT)); + /// gpio_set_function(LED_PIN, GPIO_FUNC_SIO); + //// hw_write_masked(&pads_bank0_hw->io[LED_PIN], + //// PADS_BANK0_GPIO0_IE_BITS, + //// PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS + //// ); + //// hw_xor_bits(addr, (*addr ^ values) & write_mask); + pico_default_asm_volatile ( + "ldr r2, [%0]\n" // load current pad register + "eor r2, r2, %1\n" // xor with IE bit + "and r2, r2, %2\n" // mask with (IE|OD) + "eor r2, r2, %1\n" // recombine (hw_xor_bits logic) + "str r2, [%0]\n" // write back + : + : "r" (&pads_bank0_hw->io[LED_PIN]), + "r" (PADS_BANK0_GPIO0_IE_BITS), + "r" (PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS) + : "r2", "memory" + ); + + /// io_bank0_hw->io[LED_PIN].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; + pico_default_asm_volatile ( + "str %1, [%0]\n" + : + : "r" (&io_bank0_hw->io[LED_PIN].ctrl), + "r" (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) + : "memory" + ); + /// hw_clear_bits(&pads_bank0_hw->io[LED_PIN], PADS_BANK0_GPIO0_ISO_BITS); + pico_default_asm_volatile ( + "ldr r2, [%0]\n" // load current register value + "bic r2, r2, %1\n" // clear the ISO bits (bit clear) + "str r2, [%0]\n" // write back + : + : "r" (&pads_bank0_hw->io[LED_PIN]), + "r" (PADS_BANK0_GPIO0_ISO_BITS) + : "r2", "memory" + ); + + // gpio_set_dir(LED_PIN, GPIO_OUT); + /// gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c4" : : "r" (LED_PIN), "r" (GPIO_OUT)); + + while (true) { + // gpio_put(LED_PIN, 1); + /// gpioc_bit_out_put(LED_PIN, 1); + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c0" : : "r" (LED_PIN), "r" (1)); + /// sleep_ms(500); + sleep_us(500 * 1000ull); + + // gpio_put(LED_PIN, 0); + /// gpioc_bit_out_put(LED_PIN, 0); + pico_default_asm_volatile ("mcrr p0, #4, %0, %1, c0" : : "r" (LED_PIN), "r" (0)); + /// sleep_ms(500); + sleep_us(500 * 1000ull); + } +} diff --git a/WEEK04/0x0008_uninitialized-variables-d/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables-d/CMakeLists.txt new file mode 100644 index 0000000..9e88754 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables-d C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables-d 0x0008_uninitialized-variables-d.c ) + +pico_set_program_name(0x0008_uninitialized-variables-d "0x0008_uninitialized-variables-d") +pico_set_program_version(0x0008_uninitialized-variables-d "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables-d 0) +pico_enable_stdio_usb(0x0008_uninitialized-variables-d 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables-d + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables-d PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables-d) + diff --git a/WEEK04/0x0008_uninitialized-variables-d/build/0x0008_uninitialized-variables-d.bin b/WEEK04/0x0008_uninitialized-variables-d/build/0x0008_uninitialized-variables-d.bin new file mode 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+10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100015b0 .word 0x100015b0 +1000012c: 100015d0 .word 0x100015d0 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 000015d4 .word 0x000015d4 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100015d0 .word 0x100015d0 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000024c .word 0x2000024c +100001ac: 1000170c .word 0x1000170c +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 1000170c .word 0x1000170c +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000024c .word 0x2000024c +100001d4: 20000464 .word 0x20000464 +100001d8: 10001079 .word 0x10001079 +100001dc: 10000235 .word 0x10000235 +100001e0: 10001071 .word 0x10001071 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000024c .word 0x2000024c +10000208: 2000024c .word 0x2000024c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000428 .word 0x20000428 +10000230: 100014a4 .word 0x100014a4 + +10000234
: +10000234: b508 push {r3, lr} +10000236: 2410 movs r4, #16 +10000238: 2501 movs r5, #1 +1000023a: ec45 4044 gpioc_bit_oe_put r4, r5 +1000023e: ec45 4044 gpioc_bit_oe_put r4, r5 +10000242: 4b12 ldr r3, [pc, #72] @ (1000028c ) +10000244: 2140 movs r1, #64 @ 0x40 +10000246: 20c0 movs r0, #192 @ 0xc0 +10000248: 681a ldr r2, [r3, #0] +1000024a: ea82 0201 eor.w r2, r2, r1 +1000024e: ea02 0200 and.w r2, r2, r0 +10000252: ea82 0201 eor.w r2, r2, r1 +10000256: 601a str r2, [r3, #0] +10000258: 4a0d ldr r2, [pc, #52] @ (10000290 ) +1000025a: 2105 movs r1, #5 +1000025c: 6011 str r1, [r2, #0] +1000025e: f44f 7180 mov.w r1, #256 @ 0x100 +10000262: 681a ldr r2, [r3, #0] +10000264: ea22 0201 bic.w r2, r2, r1 +10000268: 601a str r2, [r3, #0] +1000026a: ec45 4044 gpioc_bit_oe_put r4, r5 +1000026e: ec45 4040 gpioc_bit_out_put r4, r5 +10000272: 2100 movs r1, #0 +10000274: 4807 ldr r0, [pc, #28] @ (10000294 ) +10000276: f000 fbbf bl 100009f8 +1000027a: 2300 movs r3, #0 +1000027c: ec43 4040 gpioc_bit_out_put r4, r3 +10000280: 2100 movs r1, #0 +10000282: 4804 ldr r0, [pc, #16] @ (10000294 ) +10000284: f000 fbb8 bl 100009f8 +10000288: e7f1 b.n 1000026e +1000028a: bf00 nop +1000028c: 40038044 .word 0x40038044 +10000290: 40028084 .word 0x40028084 +10000294: 0007a120 .word 0x0007a120 + +10000298 : +10000298: b40f push {r0, r1, r2, r3} +1000029a: b500 push {lr} +1000029c: b083 sub sp, #12 +1000029e: 9c04 ldr r4, [sp, #16] +100002a0: 4807 ldr r0, [pc, #28] @ (100002c0 ) +100002a2: f001 f80f bl 100012c4 <__wrap_puts> +100002a6: b13c cbz r4, 100002b8 +100002a8: a905 add r1, sp, #20 +100002aa: 4620 mov r0, r4 +100002ac: 9101 str r1, [sp, #4] +100002ae: f000 fec5 bl 1000103c +100002b2: 4804 ldr r0, [pc, #16] @ (100002c4 ) +100002b4: f001 f806 bl 100012c4 <__wrap_puts> +100002b8: 2001 movs r0, #1 +100002ba: f000 fed7 bl 1000106c <_exit> +100002be: bf00 nop +100002c0: 100014a4 .word 0x100014a4 +100002c4: 100014b4 .word 0x100014b4 + +100002c8 : +100002c8: b570 push {r4, r5, r6, lr} +100002ca: 4686 mov lr, r0 +100002cc: f3ef 8510 mrs r5, PRIMASK +100002d0: b672 cpsid i +100002d2: 4c12 ldr r4, [pc, #72] @ (1000031c ) +100002d4: e8d4 6fcf ldaexb r6, [r4] +100002d8: 2001 movs r0, #1 +100002da: 2e00 cmp r6, #0 +100002dc: d1fa bne.n 100002d4 +100002de: e8c4 0f46 strexb r6, r0, [r4] +100002e2: 2e00 cmp r6, #0 +100002e4: d1f6 bne.n 100002d4 +100002e6: f3bf 8f5f dmb sy +100002ea: f04f 0c01 mov.w ip, #1 +100002ee: 08c8 lsrs r0, r1, #3 +100002f0: f001 0307 and.w r3, r1, #7 +100002f4: fa0c f303 lsl.w r3, ip, r3 +100002f8: f81e c000 ldrb.w ip, [lr, r0] +100002fc: ea1c 0603 ands.w r6, ip, r3 +10000300: d108 bne.n 10000314 +10000302: ea4c 0c03 orr.w ip, ip, r3 +10000306: f80e c000 strb.w ip, [lr, r0] +1000030a: e8c4 6f8f stlb r6, [r4] +1000030e: f385 8810 msr PRIMASK, r5 +10000312: bd70 pop {r4, r5, r6, pc} +10000314: 4610 mov r0, r2 +10000316: f7ff ffbf bl 10000298 +1000031a: bf00 nop +1000031c: 200003db .word 0x200003db + +10000320 : +10000320: 4a04 ldr r2, [pc, #16] @ (10000334 ) +10000322: 7810 ldrb r0, [r2, #0] +10000324: 1c43 adds r3, r0, #1 +10000326: b2db uxtb r3, r3 +10000328: 2b18 cmp r3, #24 +1000032a: bf28 it cs +1000032c: 2310 movcs r3, #16 +1000032e: 7013 strb r3, [r2, #0] +10000330: 4770 bx lr +10000332: bf00 nop +10000334: 20000228 .word 0x20000228 + +10000338 : +10000338: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +1000033c: 6893 ldr r3, [r2, #8] +1000033e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +10000342: 6093 str r3, [r2, #8] +10000344: 4770 bx lr +10000346: bf00 nop + +10000348 : +10000348: 2100 movs r1, #0 +1000034a: 4b04 ldr r3, [pc, #16] @ (1000035c ) +1000034c: f103 0220 add.w r2, r3, #32 +10000350: e8c3 1f8f stlb r1, [r3] +10000354: 3301 adds r3, #1 +10000356: 4293 cmp r3, r2 +10000358: d1fa bne.n 10000350 +1000035a: 4770 bx lr +1000035c: 200003d0 .word 0x200003d0 + +10000360 : +10000360: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000364: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000368: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +1000036c: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000370: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000374: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000378: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +1000037c: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000380: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000384: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000388: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000038c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000390: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000394: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000398: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000039c: b662 cpsie i +1000039e: 4770 bx lr + +100003a0 : +100003a0: 2301 movs r3, #1 +100003a2: f000 021f and.w r2, r0, #31 +100003a6: 4093 lsls r3, r2 +100003a8: 0940 lsrs r0, r0, #5 +100003aa: b141 cbz r1, 100003be +100003ac: 0080 lsls r0, r0, #2 +100003ae: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003b2: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003b6: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003ba: 6003 str r3, [r0, #0] +100003bc: 4770 bx lr +100003be: 4a02 ldr r2, [pc, #8] @ (100003c8 ) +100003c0: 3020 adds r0, #32 +100003c2: f842 3020 str.w r3, [r2, r0, lsl #2] +100003c6: 4770 bx lr +100003c8: e000e100 .word 0xe000e100 + +100003cc : +100003cc: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ce: 460d mov r5, r1 +100003d0: f3ef 8710 mrs r7, PRIMASK +100003d4: b672 cpsid i +100003d6: 4e12 ldr r6, [pc, #72] @ (10000420 ) +100003d8: e8d6 2fcf ldaexb r2, [r6] +100003dc: 2301 movs r3, #1 +100003de: 2a00 cmp r2, #0 +100003e0: d1fa bne.n 100003d8 +100003e2: e8c6 3f42 strexb r2, r3, [r6] +100003e6: 2a00 cmp r2, #0 +100003e8: d1f6 bne.n 100003d8 +100003ea: f3bf 8f5f dmb sy +100003ee: 4b0d ldr r3, [pc, #52] @ (10000424 ) +100003f0: f100 0410 add.w r4, r0, #16 +100003f4: 689b ldr r3, [r3, #8] +100003f6: 4a0c ldr r2, [pc, #48] @ (10000428 ) +100003f8: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003fc: 4293 cmp r3, r2 +100003fe: d003 beq.n 10000408 +10000400: 4299 cmp r1, r3 +10000402: d001 beq.n 10000408 +10000404: f000 fd02 bl 10000e0c +10000408: 4b06 ldr r3, [pc, #24] @ (10000424 ) +1000040a: 689b ldr r3, [r3, #8] +1000040c: f843 5024 str.w r5, [r3, r4, lsl #2] +10000410: f3bf 8f5f dmb sy +10000414: 2300 movs r3, #0 +10000416: e8c6 3f8f stlb r3, [r6] +1000041a: f387 8810 msr PRIMASK, r7 +1000041e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000420: 200003d9 .word 0x200003d9 +10000424: e000ed00 .word 0xe000ed00 +10000428: 10000111 .word 0x10000111 + +1000042c : +1000042c: 4b01 ldr r3, [pc, #4] @ (10000434 ) +1000042e: 440b add r3, r1 +10000430: 6003 str r3, [r0, #0] +10000432: 4770 bx lr +10000434: 200003d0 .word 0x200003d0 + +10000438 : +10000438: b570 push {r4, r5, r6, lr} +1000043a: 4c10 ldr r4, [pc, #64] @ (1000047c ) +1000043c: 4d10 ldr r5, [pc, #64] @ (10000480 ) +1000043e: 42ac cmp r4, r5 +10000440: d20e bcs.n 10000460 +10000442: 26ff movs r6, #255 @ 0xff +10000444: 6823 ldr r3, [r4, #0] +10000446: b163 cbz r3, 10000462 +10000448: f7ff ff6a bl 10000320 +1000044c: 4601 mov r1, r0 +1000044e: 4620 mov r0, r4 +10000450: f7ff ffec bl 1000042c +10000454: 80a6 strh r6, [r4, #4] +10000456: f3bf 8f5f dmb sy +1000045a: 3408 adds r4, #8 +1000045c: 42ac cmp r4, r5 +1000045e: d3f1 bcc.n 10000444 +10000460: bd70 pop {r4, r5, r6, pc} +10000462: f7ff ff5d bl 10000320 +10000466: 4601 mov r1, r0 +10000468: 4620 mov r0, r4 +1000046a: f7ff ffdf bl 1000042c +1000046e: 7126 strb r6, [r4, #4] +10000470: f3bf 8f5f dmb sy +10000474: 3408 adds r4, #8 +10000476: 42ac cmp r4, r5 +10000478: d3e4 bcc.n 10000444 +1000047a: bd70 pop {r4, r5, r6, pc} +1000047c: 20000244 .word 0x20000244 +10000480: 2000024c .word 0x2000024c + +10000484 : +10000484: 4b0d ldr r3, [pc, #52] @ (100004bc ) +10000486: 681a ldr r2, [r3, #0] +10000488: f3ef 8110 mrs r1, PRIMASK +1000048c: b672 cpsid i +1000048e: e8d2 cfcf ldaexb ip, [r2] +10000492: 2001 movs r0, #1 +10000494: f1bc 0f00 cmp.w ip, #0 +10000498: d1f9 bne.n 1000048e +1000049a: e8c2 0f4c strexb ip, r0, [r2] +1000049e: f1bc 0f00 cmp.w ip, #0 +100004a2: d1f4 bne.n 1000048e +100004a4: f3bf 8f5f dmb sy +100004a8: 2200 movs r2, #0 +100004aa: 681b ldr r3, [r3, #0] +100004ac: e8c3 2f8f stlb r2, [r3] +100004b0: f381 8810 msr PRIMASK, r1 +100004b4: bf40 sev +100004b6: 2000 movs r0, #0 +100004b8: 2100 movs r1, #0 +100004ba: 4770 bx lr +100004bc: 20000460 .word 0x20000460 + +100004c0 : +100004c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004c4: ed2d 8b02 vpush {d8} +100004c8: b085 sub sp, #20 +100004ca: f3ef 8305 mrs r3, IPSR +100004ce: b2db uxtb r3, r3 +100004d0: 3b10 subs r3, #16 +100004d2: 089a lsrs r2, r3, #2 +100004d4: bf18 it ne +100004d6: 2201 movne r2, #1 +100004d8: f04f 0101 mov.w r1, #1 +100004dc: f003 0b03 and.w fp, r3, #3 +100004e0: bf18 it ne +100004e2: 4daf ldrne r5, [pc, #700] @ (100007a0 ) +100004e4: 4baf ldr r3, [pc, #700] @ (100007a4 ) +100004e6: bf08 it eq +100004e8: 4daf ldreq r5, [pc, #700] @ (100007a8 ) +100004ea: eb0b 0282 add.w r2, fp, r2, lsl #2 +100004ee: f853 6022 ldr.w r6, [r3, r2, lsl #2] +100004f2: fa01 f20b lsl.w r2, r1, fp +100004f6: f505 5341 add.w r3, r5, #12352 @ 0x3040 +100004fa: ed9f 8ba7 vldr d8, [pc, #668] @ 10000798 +100004fe: 9201 str r2, [sp, #4] +10000500: 605a str r2, [r3, #4] +10000502: e02f b.n 10000564 +10000504: 88b3 ldrh r3, [r6, #4] +10000506: 041c lsls r4, r3, #16 +10000508: f140 8093 bpl.w 10000632 +1000050c: 79b3 ldrb r3, [r6, #6] +1000050e: 2b00 cmp r3, #0 +10000510: f040 80dd bne.w 100006ce +10000514: f9b6 2008 ldrsh.w r2, [r6, #8] +10000518: 2a00 cmp r2, #0 +1000051a: f2c0 811e blt.w 1000075a +1000051e: 6973 ldr r3, [r6, #20] +10000520: eb02 0242 add.w r2, r2, r2, lsl #1 +10000524: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000528: e9d3 4702 ldrd r4, r7, [r3, #8] +1000052c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000530: bf08 it eq +10000532: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000536: d00e beq.n 10000556 +10000538: eb05 018b add.w r1, r5, fp, lsl #2 +1000053c: 6aab ldr r3, [r5, #40] @ 0x28 +1000053e: 690a ldr r2, [r1, #16] +10000540: 1ad2 subs r2, r2, r3 +10000542: 1ae3 subs r3, r4, r3 +10000544: 4293 cmp r3, r2 +10000546: d305 bcc.n 10000554 +10000548: 2301 movs r3, #1 +1000054a: 6a2a ldr r2, [r5, #32] +1000054c: fa03 f30b lsl.w r3, r3, fp +10000550: 4213 tst r3, r2 +10000552: d100 bne.n 10000556 +10000554: 610c str r4, [r1, #16] +10000556: 4628 mov r0, r5 +10000558: f000 fb36 bl 10000bc8 +1000055c: 42a0 cmp r0, r4 +1000055e: 41b9 sbcs r1, r7 +10000560: f2c0 80fb blt.w 1000075a +10000564: f9b6 3008 ldrsh.w r3, [r6, #8] +10000568: 9a01 ldr r2, [sp, #4] +1000056a: 2b00 cmp r3, #0 +1000056c: 9300 str r3, [sp, #0] +1000056e: 63ea str r2, [r5, #60] @ 0x3c +10000570: dbc8 blt.n 10000504 +10000572: f8d6 8014 ldr.w r8, [r6, #20] +10000576: eb03 0943 add.w r9, r3, r3, lsl #1 +1000057a: 4628 mov r0, r5 +1000057c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000580: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000584: f000 fb20 bl 10000bc8 +10000588: 42a0 cmp r0, r4 +1000058a: eb71 010a sbcs.w r1, r1, sl +1000058e: dbb9 blt.n 10000504 +10000590: f1ba 0f00 cmp.w sl, #0 +10000594: f2c0 80c3 blt.w 1000071e +10000598: e9d7 3104 ldrd r3, r1, [r7, #16] +1000059c: 4a83 ldr r2, [pc, #524] @ (100007ac ) +1000059e: 4293 cmp r3, r2 +100005a0: f000 80ed beq.w 1000077e +100005a4: 887a ldrh r2, [r7, #2] +100005a6: f9b6 0008 ldrsh.w r0, [r6, #8] +100005aa: b292 uxth r2, r2 +100005ac: ea42 4000 orr.w r0, r2, r0, lsl #16 +100005b0: 4798 blx r3 +100005b2: 4602 mov r2, r0 +100005b4: 460b mov r3, r1 +100005b6: ea52 0103 orrs.w r1, r2, r3 +100005ba: f000 80b0 beq.w 1000071e +100005be: 2b00 cmp r3, #0 +100005c0: f280 80d1 bge.w 10000766 +100005c4: ebb4 0e02 subs.w lr, r4, r2 +100005c8: eb6a 0a03 sbc.w sl, sl, r3 +100005cc: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100005d0: e9c7 ea02 strd lr, sl, [r7, #8] +100005d4: 2b00 cmp r3, #0 +100005d6: db95 blt.n 10000504 +100005d8: 6971 ldr r1, [r6, #20] +100005da: eb03 0243 add.w r2, r3, r3, lsl #1 +100005de: eb01 02c2 add.w r2, r1, r2, lsl #3 +100005e2: e9d2 7002 ldrd r7, r0, [r2, #8] +100005e6: 45be cmp lr, r7 +100005e8: eb7a 0c00 sbcs.w ip, sl, r0 +100005ec: ea4f 0243 mov.w r2, r3, lsl #1 +100005f0: db88 blt.n 10000504 +100005f2: 46b4 mov ip, r6 +100005f4: f82c 3f08 strh.w r3, [ip, #8]! +100005f8: e006 b.n 10000608 +100005fa: eb03 0043 add.w r0, r3, r3, lsl #1 +100005fe: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000602: 005a lsls r2, r3, #1 +10000604: e9d0 7002 ldrd r7, r0, [r0, #8] +10000608: 45be cmp lr, r7 +1000060a: 441a add r2, r3 +1000060c: eb7a 0000 sbcs.w r0, sl, r0 +10000610: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000614: db04 blt.n 10000620 +10000616: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +1000061a: 46a4 mov ip, r4 +1000061c: 2b00 cmp r3, #0 +1000061e: daec bge.n 100005fa +10000620: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000624: 9b00 ldr r3, [sp, #0] +10000626: f8ac 3000 strh.w r3, [ip] +1000062a: 88b3 ldrh r3, [r6, #4] +1000062c: 041c lsls r4, r3, #16 +1000062e: f53f af6d bmi.w 1000050c +10000632: 6933 ldr r3, [r6, #16] +10000634: f3ef 8210 mrs r2, PRIMASK +10000638: b672 cpsid i +1000063a: e8d3 0fcf ldaexb r0, [r3] +1000063e: 2101 movs r1, #1 +10000640: 2800 cmp r0, #0 +10000642: d1fa bne.n 1000063a +10000644: e8c3 1f40 strexb r0, r1, [r3] +10000648: 2800 cmp r0, #0 +1000064a: d1f6 bne.n 1000063a +1000064c: f3bf 8f5f dmb sy +10000650: f64f 74ff movw r4, #65535 @ 0xffff +10000654: 88b0 ldrh r0, [r6, #4] +10000656: 2300 movs r3, #0 +10000658: 6931 ldr r1, [r6, #16] +1000065a: b200 sxth r0, r0 +1000065c: 80b4 strh r4, [r6, #4] +1000065e: e8c1 3f8f stlb r3, [r1] +10000662: f382 8810 msr PRIMASK, r2 +10000666: 4298 cmp r0, r3 +10000668: f6ff af50 blt.w 1000050c +1000066c: 4607 mov r7, r0 +1000066e: 46a9 mov r9, r5 +10000670: 6974 ldr r4, [r6, #20] +10000672: f106 0808 add.w r8, r6, #8 +10000676: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000067a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000067e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000682: f9b6 3008 ldrsh.w r3, [r6, #8] +10000686: 46c4 mov ip, r8 +10000688: 2b00 cmp r3, #0 +1000068a: db13 blt.n 100006b4 +1000068c: 46b2 mov sl, r6 +1000068e: 9700 str r7, [sp, #0] +10000690: e004 b.n 1000069c +10000692: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000696: 4694 mov ip, r2 +10000698: 2b00 cmp r3, #0 +1000069a: db09 blt.n 100006b0 +1000069c: eb03 0643 add.w r6, r3, r3, lsl #1 +100006a0: eb04 02c6 add.w r2, r4, r6, lsl #3 +100006a4: e9d2 7102 ldrd r7, r1, [r2, #8] +100006a8: 42bd cmp r5, r7 +100006aa: eb70 0101 sbcs.w r1, r0, r1 +100006ae: daf0 bge.n 10000692 +100006b0: 4656 mov r6, sl +100006b2: 9f00 ldr r7, [sp, #0] +100006b4: f8ac 7000 strh.w r7, [ip] +100006b8: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100006bc: f824 303e strh.w r3, [r4, lr, lsl #3] +100006c0: 2f00 cmp r7, #0 +100006c2: dad8 bge.n 10000676 +100006c4: 79b3 ldrb r3, [r6, #6] +100006c6: 464d mov r5, r9 +100006c8: 2b00 cmp r3, #0 +100006ca: f43f af23 beq.w 10000514 +100006ce: 2300 movs r3, #0 +100006d0: 71b3 strb r3, [r6, #6] +100006d2: f9b6 3008 ldrsh.w r3, [r6, #8] +100006d6: f106 0808 add.w r8, r6, #8 +100006da: 1c58 adds r0, r3, #1 +100006dc: d03d beq.n 1000075a +100006de: 461a mov r2, r3 +100006e0: 6977 ldr r7, [r6, #20] +100006e2: e003 b.n 100006ec +100006e4: 4680 mov r8, r0 +100006e6: 1c59 adds r1, r3, #1 +100006e8: f43f af16 beq.w 10000518 +100006ec: eb03 0143 add.w r1, r3, r3, lsl #1 +100006f0: eb07 00c1 add.w r0, r7, r1, lsl #3 +100006f4: f8b0 c002 ldrh.w ip, [r0, #2] +100006f8: 461c mov r4, r3 +100006fa: f41c 4f00 tst.w ip, #32768 @ 0x8000 +100006fe: 469e mov lr, r3 +10000700: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000704: d0ee beq.n 100006e4 +10000706: 4294 cmp r4, r2 +10000708: ed80 8b02 vstr d8, [r0, #8] +1000070c: d005 beq.n 1000071a +1000070e: f8a8 3000 strh.w r3, [r8] +10000712: 8932 ldrh r2, [r6, #8] +10000714: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000718: 8134 strh r4, [r6, #8] +1000071a: 4672 mov r2, lr +1000071c: e7e3 b.n 100006e6 +1000071e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000722: 8133 strh r3, [r6, #8] +10000724: 6933 ldr r3, [r6, #16] +10000726: f3ef 8210 mrs r2, PRIMASK +1000072a: b672 cpsid i +1000072c: e8d3 0fcf ldaexb r0, [r3] +10000730: 2101 movs r1, #1 +10000732: 2800 cmp r0, #0 +10000734: d1fa bne.n 1000072c +10000736: e8c3 1f40 strexb r0, r1, [r3] +1000073a: 2800 cmp r0, #0 +1000073c: d1f6 bne.n 1000072c +1000073e: f3bf 8f5f dmb sy +10000742: 8873 ldrh r3, [r6, #2] +10000744: 6931 ldr r1, [r6, #16] +10000746: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000074a: 9b00 ldr r3, [sp, #0] +1000074c: 8073 strh r3, [r6, #2] +1000074e: 2300 movs r3, #0 +10000750: e8c1 3f8f stlb r3, [r1] +10000754: f382 8810 msr PRIMASK, r2 +10000758: e6d4 b.n 10000504 +1000075a: bf40 sev +1000075c: b005 add sp, #20 +1000075e: ecbd 8b02 vpop {d8} +10000762: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000766: 4628 mov r0, r5 +10000768: e9cd 2302 strd r2, r3, [sp, #8] +1000076c: f000 fa2c bl 10000bc8 +10000770: 9a02 ldr r2, [sp, #8] +10000772: 9b03 ldr r3, [sp, #12] +10000774: eb10 0e02 adds.w lr, r0, r2 +10000778: eb43 0a01 adc.w sl, r3, r1 +1000077c: e726 b.n 100005cc +1000077e: 4608 mov r0, r1 +10000780: 690b ldr r3, [r1, #16] +10000782: 9102 str r1, [sp, #8] +10000784: 4798 blx r3 +10000786: 2800 cmp r0, #0 +10000788: d0c9 beq.n 1000071e +1000078a: 9902 ldr r1, [sp, #8] +1000078c: e9d1 2300 ldrd r2, r3, [r1] +10000790: e711 b.n 100005b6 +10000792: bf00 nop +10000794: f3af 8000 nop.w +10000798: ffffffff .word 0xffffffff +1000079c: ffffffff .word 0xffffffff +100007a0: 400b8000 .word 0x400b8000 +100007a4: 20000440 .word 0x20000440 +100007a8: 400b0000 .word 0x400b0000 +100007ac: 100004c1 .word 0x100004c1 + +100007b0 : +100007b0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007b4: 4c36 ldr r4, [pc, #216] @ (10000890 ) +100007b6: 6925 ldr r5, [r4, #16] +100007b8: b12d cbz r5, 100007c6 +100007ba: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007be: 210a movs r1, #10 +100007c0: 4834 ldr r0, [pc, #208] @ (10000894 ) +100007c2: f7ff be33 b.w 1000042c +100007c6: f8df 80e4 ldr.w r8, [pc, #228] @ 100008ac +100007ca: 2103 movs r1, #3 +100007cc: 4640 mov r0, r8 +100007ce: f000 f9e9 bl 10000ba4 +100007d2: 2603 movs r6, #3 +100007d4: f8c4 800c str.w r8, [r4, #12] +100007d8: f7ff fda2 bl 10000320 +100007dc: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +100007e0: 4b2d ldr r3, [pc, #180] @ (10000898 ) +100007e2: 7026 strb r6, [r4, #0] +100007e4: 4403 add r3, r0 +100007e6: 6123 str r3, [r4, #16] +100007e8: f8dc 3000 ldr.w r3, [ip] +100007ec: 210f movs r1, #15 +100007ee: 7063 strb r3, [r4, #1] +100007f0: 6963 ldr r3, [r4, #20] +100007f2: 8061 strh r1, [r4, #2] +100007f4: 831d strh r5, [r3, #24] +100007f6: f04f 0504 mov.w r5, #4 +100007fa: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +100007fe: f04f 0505 mov.w r5, #5 +10000802: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000806: f04f 0506 mov.w r5, #6 +1000080a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +1000080e: f04f 0507 mov.w r5, #7 +10000812: 210e movs r1, #14 +10000814: f64f 72ff movw r2, #65535 @ 0xffff +10000818: 2708 movs r7, #8 +1000081a: f04f 0e0a mov.w lr, #10 +1000081e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000822: f04f 0901 mov.w r9, #1 +10000826: f04f 0c0c mov.w ip, #12 +1000082a: f04f 0b02 mov.w fp, #2 +1000082e: f04f 0a09 mov.w sl, #9 +10000832: 200d movs r0, #13 +10000834: f04f 050b mov.w r5, #11 +10000838: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +1000083c: 4917 ldr r1, [pc, #92] @ (1000089c ) +1000083e: 80a2 strh r2, [r4, #4] +10000840: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000844: 60a1 str r1, [r4, #8] +10000846: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +1000084a: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +1000084e: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000852: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000856: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +1000085a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +1000085e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000862: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000866: 801a strh r2, [r3, #0] +10000868: 4b0d ldr r3, [pc, #52] @ (100008a0 ) +1000086a: 4630 mov r0, r6 +1000086c: f8c8 7020 str.w r7, [r8, #32] +10000870: 490c ldr r1, [pc, #48] @ (100008a4 ) +10000872: 60dc str r4, [r3, #12] +10000874: f7ff fdaa bl 100003cc +10000878: 4649 mov r1, r9 +1000087a: 4630 mov r0, r6 +1000087c: f7ff fd90 bl 100003a0 +10000880: 4b09 ldr r3, [pc, #36] @ (100008a8 ) +10000882: 210a movs r1, #10 +10000884: 641f str r7, [r3, #64] @ 0x40 +10000886: 4803 ldr r0, [pc, #12] @ (10000894 ) +10000888: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000088c: f7ff bdce b.w 1000042c +10000890: 2000022c .word 0x2000022c +10000894: 20000460 .word 0x20000460 +10000898: 200003d0 .word 0x200003d0 +1000089c: 0010ffff .word 0x0010ffff +100008a0: 20000440 .word 0x20000440 +100008a4: 100004c1 .word 0x100004c1 +100008a8: 400b2000 .word 0x400b2000 +100008ac: 400b0000 .word 0x400b0000 + +100008b0 : +100008b0: 4601 mov r1, r0 +100008b2: b5f0 push {r4, r5, r6, r7, lr} +100008b4: 6900 ldr r0, [r0, #16] +100008b6: f3ef 8710 mrs r7, PRIMASK +100008ba: b672 cpsid i +100008bc: e8d0 5fcf ldaexb r5, [r0] +100008c0: 2401 movs r4, #1 +100008c2: 2d00 cmp r5, #0 +100008c4: d1fa bne.n 100008bc +100008c6: e8c0 4f45 strexb r5, r4, [r0] +100008ca: 2d00 cmp r5, #0 +100008cc: d1f6 bne.n 100008bc +100008ce: f3bf 8f5f dmb sy +100008d2: f9b1 e002 ldrsh.w lr, [r1, #2] +100008d6: 694c ldr r4, [r1, #20] +100008d8: eb0e 0c4e add.w ip, lr, lr, lsl #1 +100008dc: f1be 0f00 cmp.w lr, #0 +100008e0: ea4f 05cc mov.w r5, ip, lsl #3 +100008e4: 6908 ldr r0, [r1, #16] +100008e6: eb04 0ccc add.w ip, r4, ip, lsl #3 +100008ea: db3c blt.n 10000966 +100008ec: 5b66 ldrh r6, [r4, r5] +100008ee: 804e strh r6, [r1, #2] +100008f0: 2600 movs r6, #0 +100008f2: e8c0 6f8f stlb r6, [r0] +100008f6: f387 8810 msr PRIMASK, r7 +100008fa: f8bc 0002 ldrh.w r0, [ip, #2] +100008fe: e9cc 2302 strd r2, r3, [ip, #8] +10000902: 3001 adds r0, #1 +10000904: f3c0 000e ubfx r0, r0, #0, #15 +10000908: 2801 cmp r0, #1 +1000090a: bf38 it cc +1000090c: 2001 movcc r0, #1 +1000090e: 9b05 ldr r3, [sp, #20] +10000910: f8ac 0002 strh.w r0, [ip, #2] +10000914: f8cc 3010 str.w r3, [ip, #16] +10000918: 9b06 ldr r3, [sp, #24] +1000091a: ea40 400e orr.w r0, r0, lr, lsl #16 +1000091e: f8cc 3014 str.w r3, [ip, #20] +10000922: 690b ldr r3, [r1, #16] +10000924: f3ef 8210 mrs r2, PRIMASK +10000928: b672 cpsid i +1000092a: e8d3 cfcf ldaexb ip, [r3] +1000092e: 2701 movs r7, #1 +10000930: f1bc 0f00 cmp.w ip, #0 +10000934: d1f9 bne.n 1000092a +10000936: e8c3 7f4c strexb ip, r7, [r3] +1000093a: f1bc 0f00 cmp.w ip, #0 +1000093e: d1f4 bne.n 1000092a +10000940: f3bf 8f5f dmb sy +10000944: 888b ldrh r3, [r1, #4] +10000946: 5363 strh r3, [r4, r5] +10000948: f8a1 e004 strh.w lr, [r1, #4] +1000094c: 690b ldr r3, [r1, #16] +1000094e: e8c3 6f8f stlb r6, [r3] +10000952: f382 8810 msr PRIMASK, r2 +10000956: 2201 movs r2, #1 +10000958: 68cb ldr r3, [r1, #12] +1000095a: 7809 ldrb r1, [r1, #0] +1000095c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000960: 408a lsls r2, r1 +10000962: 605a str r2, [r3, #4] +10000964: bdf0 pop {r4, r5, r6, r7, pc} +10000966: 2300 movs r3, #0 +10000968: e8c0 3f8f stlb r3, [r0] +1000096c: f387 8810 msr PRIMASK, r7 +10000970: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000974: bdf0 pop {r4, r5, r6, r7, pc} +10000976: bf00 nop + +10000978 : +10000978: 4603 mov r3, r0 +1000097a: 8940 ldrh r0, [r0, #10] +1000097c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000980: dd37 ble.n 100009f2 +10000982: 6958 ldr r0, [r3, #20] +10000984: 140a asrs r2, r1, #16 +10000986: eb02 0242 add.w r2, r2, r2, lsl #1 +1000098a: b510 push {r4, lr} +1000098c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000990: 691c ldr r4, [r3, #16] +10000992: f3ef 8c10 mrs ip, PRIMASK +10000996: b672 cpsid i +10000998: e8d4 efcf ldaexb lr, [r4] +1000099c: 2201 movs r2, #1 +1000099e: f1be 0f00 cmp.w lr, #0 +100009a2: d1f9 bne.n 10000998 +100009a4: e8c4 2f4e strexb lr, r2, [r4] +100009a8: f1be 0f00 cmp.w lr, #0 +100009ac: d1f4 bne.n 10000998 +100009ae: f3bf 8f5f dmb sy +100009b2: 8842 ldrh r2, [r0, #2] +100009b4: b289 uxth r1, r1 +100009b6: b292 uxth r2, r2 +100009b8: 428a cmp r2, r1 +100009ba: d007 beq.n 100009cc +100009bc: 2200 movs r2, #0 +100009be: 691b ldr r3, [r3, #16] +100009c0: e8c3 2f8f stlb r2, [r3] +100009c4: f38c 8810 msr PRIMASK, ip +100009c8: 2000 movs r0, #0 +100009ca: bd10 pop {r4, pc} +100009cc: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +100009d0: 8042 strh r2, [r0, #2] +100009d2: 2101 movs r1, #1 +100009d4: 2200 movs r2, #0 +100009d6: 6918 ldr r0, [r3, #16] +100009d8: 7199 strb r1, [r3, #6] +100009da: e8c0 2f8f stlb r2, [r0] +100009de: f38c 8810 msr PRIMASK, ip +100009e2: 781c ldrb r4, [r3, #0] +100009e4: 68da ldr r2, [r3, #12] +100009e6: 4608 mov r0, r1 +100009e8: f502 5301 add.w r3, r2, #8256 @ 0x2040 +100009ec: 40a1 lsls r1, r4 +100009ee: 6059 str r1, [r3, #4] +100009f0: bd10 pop {r4, pc} +100009f2: 2000 movs r0, #0 +100009f4: 4770 bx lr +100009f6: bf00 nop + +100009f8 : +100009f8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100009fc: b082 sub sp, #8 +100009fe: 4604 mov r4, r0 +10000a00: 460e mov r6, r1 +10000a02: f000 f8e9 bl 10000bd8 +10000a06: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10000a0a: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +10000a0e: 1824 adds r4, r4, r0 +10000a10: eb46 0601 adc.w r6, r6, r1 +10000a14: 42a2 cmp r2, r4 +10000a16: eb73 0106 sbcs.w r1, r3, r6 +10000a1a: bf3c itt cc +10000a1c: 4614 movcc r4, r2 +10000a1e: 461e movcc r6, r3 +10000a20: 1fa5 subs r5, r4, #6 +10000a22: f146 37ff adc.w r7, r6, #4294967295 @ 0xffffffff +10000a26: 42ac cmp r4, r5 +10000a28: eb76 0307 sbcs.w r3, r6, r7 +10000a2c: bf3c itt cc +10000a2e: 2500 movcc r5, #0 +10000a30: 462f movcc r7, r5 +10000a32: f000 f8d1 bl 10000bd8 +10000a36: 1a28 subs r0, r5, r0 +10000a38: eb67 0c01 sbc.w ip, r7, r1 +10000a3c: 2801 cmp r0, #1 +10000a3e: f17c 0c00 sbcs.w ip, ip, #0 +10000a42: da06 bge.n 10000a52 +10000a44: 4620 mov r0, r4 +10000a46: 4631 mov r1, r6 +10000a48: b002 add sp, #8 +10000a4a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000a4e: f000 b8cd b.w 10000bec +10000a52: f000 f8c1 bl 10000bd8 +10000a56: 4285 cmp r5, r0 +10000a58: eb67 0101 sbc.w r1, r7, r1 +10000a5c: 2900 cmp r1, #0 +10000a5e: db0a blt.n 10000a76 +10000a60: 2100 movs r1, #0 +10000a62: 4b17 ldr r3, [pc, #92] @ (10000ac0 ) +10000a64: 462a mov r2, r5 +10000a66: 9300 str r3, [sp, #0] +10000a68: 4816 ldr r0, [pc, #88] @ (10000ac4 ) +10000a6a: 463b mov r3, r7 +10000a6c: 9101 str r1, [sp, #4] +10000a6e: f7ff ff1f bl 100008b0 +10000a72: 3001 adds r0, #1 +10000a74: d0e6 beq.n 10000a44 +10000a76: f04f 0c00 mov.w ip, #0 +10000a7a: 4a13 ldr r2, [pc, #76] @ (10000ac8 ) +10000a7c: 4913 ldr r1, [pc, #76] @ (10000acc ) +10000a7e: 6a53 ldr r3, [r2, #36] @ 0x24 +10000a80: 429f cmp r7, r3 +10000a82: d804 bhi.n 10000a8e +10000a84: 6a90 ldr r0, [r2, #40] @ 0x28 +10000a86: 42a8 cmp r0, r5 +10000a88: d2dc bcs.n 10000a44 +10000a8a: 429f cmp r7, r3 +10000a8c: d1da bne.n 10000a44 +10000a8e: 680b ldr r3, [r1, #0] +10000a90: f3ef 8010 mrs r0, PRIMASK +10000a94: b672 cpsid i +10000a96: e8d3 8fcf ldaexb r8, [r3] +10000a9a: f05f 0e01 movs.w lr, #1 +10000a9e: f1b8 0f00 cmp.w r8, #0 +10000aa2: d1f8 bne.n 10000a96 +10000aa4: e8c3 ef48 strexb r8, lr, [r3] +10000aa8: f1b8 0f00 cmp.w r8, #0 +10000aac: d1f3 bne.n 10000a96 +10000aae: f3bf 8f5f dmb sy +10000ab2: 680b ldr r3, [r1, #0] +10000ab4: e8c3 cf8f stlb ip, [r3] +10000ab8: f380 8810 msr PRIMASK, r0 +10000abc: bf20 wfe +10000abe: e7de b.n 10000a7e +10000ac0: 10000485 .word 0x10000485 +10000ac4: 2000022c .word 0x2000022c +10000ac8: 400b0000 .word 0x400b0000 +10000acc: 20000460 .word 0x20000460 + +10000ad0 : +10000ad0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000ad4: 4606 mov r6, r0 +10000ad6: 460d mov r5, r1 +10000ad8: b083 sub sp, #12 +10000ada: f3ef 8405 mrs r4, IPSR +10000ade: b2e4 uxtb r4, r4 +10000ae0: b13c cbz r4, 10000af2 +10000ae2: 4b2d ldr r3, [pc, #180] @ (10000b98 ) +10000ae4: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ae6: 42aa cmp r2, r5 +10000ae8: d21c bcs.n 10000b24 +10000aea: 2000 movs r0, #0 +10000aec: b003 add sp, #12 +10000aee: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000af2: 4f2a ldr r7, [pc, #168] @ (10000b9c ) +10000af4: f8d7 900c ldr.w r9, [r7, #12] +10000af8: f897 8000 ldrb.w r8, [r7] +10000afc: 4648 mov r0, r9 +10000afe: f000 f863 bl 10000bc8 +10000b02: f108 0804 add.w r8, r8, #4 +10000b06: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000b0a: 1a1b subs r3, r3, r0 +10000b0c: 1a30 subs r0, r6, r0 +10000b0e: eb65 0101 sbc.w r1, r5, r1 +10000b12: 4298 cmp r0, r3 +10000b14: f171 0100 sbcs.w r1, r1, #0 +10000b18: db10 blt.n 10000b3c +10000b1a: bf20 wfe +10000b1c: 4b1e ldr r3, [pc, #120] @ (10000b98 ) +10000b1e: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b20: 42aa cmp r2, r5 +10000b22: d3e2 bcc.n 10000aea +10000b24: bf14 ite ne +10000b26: 2401 movne r4, #1 +10000b28: 2400 moveq r4, #0 +10000b2a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b2c: 42b3 cmp r3, r6 +10000b2e: bf34 ite cc +10000b30: 4620 movcc r0, r4 +10000b32: f044 0001 orrcs.w r0, r4, #1 +10000b36: b003 add sp, #12 +10000b38: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000b3c: f000 f84c bl 10000bd8 +10000b40: 4286 cmp r6, r0 +10000b42: eb65 0101 sbc.w r1, r5, r1 +10000b46: 2900 cmp r1, #0 +10000b48: db14 blt.n 10000b74 +10000b4a: 4b15 ldr r3, [pc, #84] @ (10000ba0 ) +10000b4c: 4638 mov r0, r7 +10000b4e: e9cd 3400 strd r3, r4, [sp] +10000b52: 4632 mov r2, r6 +10000b54: 462b mov r3, r5 +10000b56: f7ff feab bl 100008b0 +10000b5a: 1e01 subs r1, r0, #0 +10000b5c: dd0a ble.n 10000b74 +10000b5e: 4b0e ldr r3, [pc, #56] @ (10000b98 ) +10000b60: 6a5a ldr r2, [r3, #36] @ 0x24 +10000b62: 42aa cmp r2, r5 +10000b64: d316 bcc.n 10000b94 +10000b66: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b68: 42b3 cmp r3, r6 +10000b6a: d311 bcc.n 10000b90 +10000b6c: 480b ldr r0, [pc, #44] @ (10000b9c ) +10000b6e: f7ff ff03 bl 10000978 +10000b72: e7b6 b.n 10000ae2 +10000b74: 4b08 ldr r3, [pc, #32] @ (10000b98 ) +10000b76: 6a5c ldr r4, [r3, #36] @ 0x24 +10000b78: 42ac cmp r4, r5 +10000b7a: d3b6 bcc.n 10000aea +10000b7c: 1b64 subs r4, r4, r5 +10000b7e: bf18 it ne +10000b80: 2401 movne r4, #1 +10000b82: 6a9b ldr r3, [r3, #40] @ 0x28 +10000b84: 42b3 cmp r3, r6 +10000b86: bf34 ite cc +10000b88: 4620 movcc r0, r4 +10000b8a: f044 0001 orrcs.w r0, r4, #1 +10000b8e: e7ad b.n 10000aec +10000b90: 42aa cmp r2, r5 +10000b92: d1eb bne.n 10000b6c +10000b94: bf20 wfe +10000b96: e7e9 b.n 10000b6c +10000b98: 400b0000 .word 0x400b0000 +10000b9c: 2000022c .word 0x2000022c +10000ba0: 10000485 .word 0x10000485 + +10000ba4 : +10000ba4: b410 push {r4} +10000ba6: 4b05 ldr r3, [pc, #20] @ (10000bbc ) +10000ba8: 4c05 ldr r4, [pc, #20] @ (10000bc0 ) +10000baa: 4a06 ldr r2, [pc, #24] @ (10000bc4 ) +10000bac: 42a0 cmp r0, r4 +10000bae: bf14 ite ne +10000bb0: 4618 movne r0, r3 +10000bb2: 1c58 addeq r0, r3, #1 +10000bb4: f85d 4b04 ldr.w r4, [sp], #4 +10000bb8: f7ff bb86 b.w 100002c8 +10000bbc: 200003f0 .word 0x200003f0 +10000bc0: 400b8000 .word 0x400b8000 +10000bc4: 100014b8 .word 0x100014b8 + +10000bc8 : +10000bc8: 4603 mov r3, r0 +10000bca: 6a41 ldr r1, [r0, #36] @ 0x24 +10000bcc: 460a mov r2, r1 +10000bce: 6a98 ldr r0, [r3, #40] @ 0x28 +10000bd0: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bd2: 428a cmp r2, r1 +10000bd4: d1fa bne.n 10000bcc +10000bd6: 4770 bx lr + +10000bd8 : +10000bd8: 4b03 ldr r3, [pc, #12] @ (10000be8 ) +10000bda: 6a59 ldr r1, [r3, #36] @ 0x24 +10000bdc: 460a mov r2, r1 +10000bde: 6a98 ldr r0, [r3, #40] @ 0x28 +10000be0: 6a59 ldr r1, [r3, #36] @ 0x24 +10000be2: 4291 cmp r1, r2 +10000be4: d1fa bne.n 10000bdc +10000be6: 4770 bx lr +10000be8: 400b0000 .word 0x400b0000 + +10000bec : +10000bec: 4a07 ldr r2, [pc, #28] @ (10000c0c ) +10000bee: 6a53 ldr r3, [r2, #36] @ 0x24 +10000bf0: 4299 cmp r1, r3 +10000bf2: d8fc bhi.n 10000bee +10000bf4: 4299 cmp r1, r3 +10000bf6: d107 bne.n 10000c08 +10000bf8: 4b04 ldr r3, [pc, #16] @ (10000c0c ) +10000bfa: e002 b.n 10000c02 +10000bfc: 6a5a ldr r2, [r3, #36] @ 0x24 +10000bfe: 4291 cmp r1, r2 +10000c00: d102 bne.n 10000c08 +10000c02: 6a9a ldr r2, [r3, #40] @ 0x28 +10000c04: 4290 cmp r0, r2 +10000c06: d8f9 bhi.n 10000bfc +10000c08: 4770 bx lr +10000c0a: bf00 nop +10000c0c: 400b0000 .word 0x400b0000 + +10000c10 : +10000c10: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000c14: ea4f 0c8c mov.w ip, ip, lsl #2 +10000c18: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000c1c: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000c20: b5f0 push {r4, r5, r6, r7, lr} +10000c22: 4616 mov r6, r2 +10000c24: f8dc 2004 ldr.w r2, [ip, #4] +10000c28: 1f05 subs r5, r0, #4 +10000c2a: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000c2e: bf38 it cc +10000c30: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000c34: b2ed uxtb r5, r5 +10000c36: bf38 it cc +10000c38: f8cc 2004 strcc.w r2, [ip, #4] +10000c3c: 2d01 cmp r5, #1 +10000c3e: d92a bls.n 10000c96 +10000c40: f44f 6700 mov.w r7, #2048 @ 0x800 +10000c44: 4c25 ldr r4, [pc, #148] @ (10000cdc ) +10000c46: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000c4a: 6017 str r7, [r2, #0] +10000c4c: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000c50: b9b2 cbnz r2, 10000c80 +10000c52: f8dc 2000 ldr.w r2, [ip] +10000c56: 2d01 cmp r5, #1 +10000c58: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000c5c: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000c60: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000c64: 6032 str r2, [r6, #0] +10000c66: d92a bls.n 10000cbe +10000c68: f44f 6100 mov.w r1, #2048 @ 0x800 +10000c6c: f844 3020 str.w r3, [r4, r0, lsl #2] +10000c70: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000c74: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000c78: 6011 str r1, [r2, #0] +10000c7a: f8cc 3004 str.w r3, [ip, #4] +10000c7e: bdf0 pop {r4, r5, r6, r7, pc} +10000c80: 6967 ldr r7, [r4, #20] +10000c82: fbb7 fef2 udiv lr, r7, r2 +10000c86: f10e 0e01 add.w lr, lr, #1 +10000c8a: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000c8e: f1be 0e03 subs.w lr, lr, #3 +10000c92: d2fc bcs.n 10000c8e +10000c94: e7dd b.n 10000c52 +10000c96: 2901 cmp r1, #1 +10000c98: d1d2 bne.n 10000c40 +10000c9a: 2403 movs r4, #3 +10000c9c: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000ca0: 6014 str r4, [r2, #0] +10000ca2: f8dc 2008 ldr.w r2, [ip, #8] +10000ca6: 07d2 lsls r2, r2, #31 +10000ca8: d5fb bpl.n 10000ca2 +10000caa: f8dc 2000 ldr.w r2, [ip] +10000cae: 4c0b ldr r4, [pc, #44] @ (10000cdc ) +10000cb0: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000cb4: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000cb8: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000cbc: 6032 str r2, [r6, #0] +10000cbe: 2201 movs r2, #1 +10000cc0: f8dc 5000 ldr.w r5, [ip] +10000cc4: 404d eors r5, r1 +10000cc6: f005 0503 and.w r5, r5, #3 +10000cca: 6035 str r5, [r6, #0] +10000ccc: fa02 f101 lsl.w r1, r2, r1 +10000cd0: f8dc 2008 ldr.w r2, [ip, #8] +10000cd4: 420a tst r2, r1 +10000cd6: d0fb beq.n 10000cd0 +10000cd8: e7c6 b.n 10000c68 +10000cda: bf00 nop +10000cdc: 200003f4 .word 0x200003f4 + +10000ce0 : +10000ce0: 4b01 ldr r3, [pc, #4] @ (10000ce8 ) +10000ce2: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000ce6: 4770 bx lr +10000ce8: 200003f4 .word 0x200003f4 + +10000cec : +10000cec: b470 push {r4, r5, r6} +10000cee: 9d03 ldr r5, [sp, #12] +10000cf0: 6804 ldr r4, [r0, #0] +10000cf2: 032d lsls r5, r5, #12 +10000cf4: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000cf8: 4b1b ldr r3, [pc, #108] @ (10000d68 ) +10000cfa: 2c00 cmp r4, #0 +10000cfc: fbb3 f3f1 udiv r3, r3, r1 +10000d00: fbb2 f6f3 udiv r6, r2, r3 +10000d04: db1f blt.n 10000d46 +10000d06: 4a19 ldr r2, [pc, #100] @ (10000d6c ) +10000d08: 4b19 ldr r3, [pc, #100] @ (10000d70 ) +10000d0a: 4290 cmp r0, r2 +10000d0c: bf14 ite ne +10000d0e: f44f 4280 movne.w r2, #16384 @ 0x4000 +10000d12: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10000d16: 4c17 ldr r4, [pc, #92] @ (10000d74 ) +10000d18: 601a str r2, [r3, #0] +10000d1a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000d1e: 601a str r2, [r3, #0] +10000d20: 68a3 ldr r3, [r4, #8] +10000d22: ea32 0303 bics.w r3, r2, r3 +10000d26: d1fb bne.n 10000d20 +10000d28: 2221 movs r2, #33 @ 0x21 +10000d2a: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10000d2e: 3304 adds r3, #4 +10000d30: 6001 str r1, [r0, #0] +10000d32: 6086 str r6, [r0, #8] +10000d34: 601a str r2, [r3, #0] +10000d36: 6802 ldr r2, [r0, #0] +10000d38: 2a00 cmp r2, #0 +10000d3a: dafc bge.n 10000d36 +10000d3c: 2208 movs r2, #8 +10000d3e: 60c5 str r5, [r0, #12] +10000d40: 601a str r2, [r3, #0] +10000d42: bc70 pop {r4, r5, r6} +10000d44: 4770 bx lr +10000d46: 6803 ldr r3, [r0, #0] +10000d48: f003 033f and.w r3, r3, #63 @ 0x3f +10000d4c: 428b cmp r3, r1 +10000d4e: d1da bne.n 10000d06 +10000d50: 6883 ldr r3, [r0, #8] +10000d52: f3c3 030b ubfx r3, r3, #0, #12 +10000d56: 42b3 cmp r3, r6 +10000d58: d1d5 bne.n 10000d06 +10000d5a: 68c3 ldr r3, [r0, #12] +10000d5c: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10000d60: 42ab cmp r3, r5 +10000d62: d1d0 bne.n 10000d06 +10000d64: e7ed b.n 10000d42 +10000d66: bf00 nop +10000d68: 00b71b00 .word 0x00b71b00 +10000d6c: 40058000 .word 0x40058000 +10000d70: 40022000 .word 0x40022000 +10000d74: 40020000 .word 0x40020000 + +10000d78 : +10000d78: 2301 movs r3, #1 +10000d7a: eb00 0040 add.w r0, r0, r0, lsl #1 +10000d7e: 0080 lsls r0, r0, #2 +10000d80: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000d84: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10000d88: 6041 str r1, [r0, #4] +10000d8a: 6003 str r3, [r0, #0] +10000d8c: 4770 bx lr +10000d8e: bf00 nop + +10000d90 : +10000d90: 2300 movs r3, #0 +10000d92: 8adb ldrh r3, [r3, #22] +10000d94: 2200 movs r2, #0 +10000d96: e842 f200 tt r2, r2 +10000d9a: 0252 lsls r2, r2, #9 +10000d9c: d401 bmi.n 10000da2 +10000d9e: 2110 movs r1, #16 +10000da0: 4718 bx r3 +10000da2: 2104 movs r1, #4 +10000da4: 4718 bx r3 +10000da6: bf00 nop + +10000da8 : +10000da8: 4a03 ldr r2, [pc, #12] @ (10000db8 ) +10000daa: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10000dae: 2b00 cmp r3, #0 +10000db0: d0fb beq.n 10000daa +10000db2: f3bf 8f5f dmb sy +10000db6: 4770 bx lr +10000db8: 400e0000 .word 0x400e0000 + +10000dbc : +10000dbc: 2100 movs r1, #0 +10000dbe: 4b04 ldr r3, [pc, #16] @ (10000dd0 ) +10000dc0: 4a04 ldr r2, [pc, #16] @ (10000dd4 ) +10000dc2: f3bf 8f5f dmb sy +10000dc6: f843 1b04 str.w r1, [r3], #4 +10000dca: 4293 cmp r3, r2 +10000dcc: d1f9 bne.n 10000dc2 +10000dce: 4770 bx lr +10000dd0: 400e080c .word 0x400e080c +10000dd4: 400e082c .word 0x400e082c + +10000dd8 : +10000dd8: b410 push {r4} +10000dda: f44f 708d mov.w r0, #282 @ 0x11a +10000dde: f44f 642a mov.w r4, #2720 @ 0xaa0 +10000de2: 4a06 ldr r2, [pc, #24] @ (10000dfc ) +10000de4: 4b06 ldr r3, [pc, #24] @ (10000e00 ) +10000de6: 4907 ldr r1, [pc, #28] @ (10000e04 ) +10000de8: 6014 str r4, [r2, #0] +10000dea: 60d0 str r0, [r2, #12] +10000dec: 6019 str r1, [r3, #0] +10000dee: 6853 ldr r3, [r2, #4] +10000df0: 2b00 cmp r3, #0 +10000df2: dafc bge.n 10000dee +10000df4: f85d 4b04 ldr.w r4, [sp], #4 +10000df8: 4770 bx lr +10000dfa: bf00 nop +10000dfc: 40048000 .word 0x40048000 +10000e00: 4004a000 .word 0x4004a000 +10000e04: 00fab000 .word 0x00fab000 + +10000e08 : +10000e08: 4770 bx lr +10000e0a: bf00 nop + +10000e0c : +10000e0c: b508 push {r3, lr} +10000e0e: 4801 ldr r0, [pc, #4] @ (10000e14 ) +10000e10: f7ff fa42 bl 10000298 +10000e14: 100014dc .word 0x100014dc + +10000e18 : +10000e18: b538 push {r3, r4, r5, lr} +10000e1a: 4c05 ldr r4, [pc, #20] @ (10000e30 ) +10000e1c: 4d05 ldr r5, [pc, #20] @ (10000e34 ) +10000e1e: 42ac cmp r4, r5 +10000e20: d204 bcs.n 10000e2c +10000e22: f854 3b04 ldr.w r3, [r4], #4 +10000e26: 4798 blx r3 +10000e28: 42ac cmp r4, r5 +10000e2a: d3fa bcc.n 10000e22 +10000e2c: bd38 pop {r3, r4, r5, pc} +10000e2e: bf00 nop +10000e30: 10001460 .word 0x10001460 +10000e34: 100014a0 .word 0x100014a0 + +10000e38 : +10000e38: b410 push {r4} +10000e3a: 4807 ldr r0, [pc, #28] @ (10000e58 ) +10000e3c: 4c07 ldr r4, [pc, #28] @ (10000e5c ) +10000e3e: 4b08 ldr r3, [pc, #32] @ (10000e60 ) +10000e40: 4a08 ldr r2, [pc, #32] @ (10000e64 ) +10000e42: 4909 ldr r1, [pc, #36] @ (10000e68 ) +10000e44: 6004 str r4, [r0, #0] +10000e46: 601a str r2, [r3, #0] +10000e48: 688b ldr r3, [r1, #8] +10000e4a: ea32 0303 bics.w r3, r2, r3 +10000e4e: d1fb bne.n 10000e48 +10000e50: f85d 4b04 ldr.w r4, [sp], #4 +10000e54: 4770 bx lr +10000e56: bf00 nop +10000e58: 40022000 .word 0x40022000 +10000e5c: efef3b7f .word 0xefef3b7f +10000e60: 40023000 .word 0x40023000 +10000e64: 03f3fff6 .word 0x03f3fff6 +10000e68: 40020000 .word 0x40020000 + +10000e6c : +10000e6c: 4b04 ldr r3, [pc, #16] @ (10000e80 ) +10000e6e: 6cdb ldr r3, [r3, #76] @ 0x4c +10000e70: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10000e74: d103 bne.n 10000e7e +10000e76: f44f 2280 mov.w r2, #262144 @ 0x40000 +10000e7a: 4b02 ldr r3, [pc, #8] @ (10000e84 ) +10000e7c: 64da str r2, [r3, #76] @ 0x4c +10000e7e: 4770 bx lr +10000e80: 50110000 .word 0x50110000 +10000e84: 50112000 .word 0x50112000 + +10000e88 : +10000e88: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000e8c: 4b04 ldr r3, [pc, #16] @ (10000ea0 ) +10000e8e: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10000e92: 430b orrs r3, r1 +10000e94: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10000e98: ee10 0430 dcp_rcmp r0 +10000e9c: 4770 bx lr +10000e9e: bf00 nop +10000ea0: 00300303 .word 0x00300303 + +10000ea4 : +10000ea4: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10000ea8: 4b04 ldr r3, [pc, #16] @ (10000ebc ) +10000eaa: 4a05 ldr r2, [pc, #20] @ (10000ec0 ) +10000eac: 6019 str r1, [r3, #0] +10000eae: 6893 ldr r3, [r2, #8] +10000eb0: 43db mvns r3, r3 +10000eb2: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10000eb6: d1fa bne.n 10000eae +10000eb8: 4770 bx lr +10000eba: bf00 nop +10000ebc: 40023000 .word 0x40023000 +10000ec0: 40020000 .word 0x40020000 + +10000ec4 : +10000ec4: b510 push {r4, lr} +10000ec6: f245 2053 movw r0, #21075 @ 0x5253 +10000eca: f7ff ff61 bl 10000d90 +10000ece: e8bd 4010 ldmia.w sp!, {r4, lr} +10000ed2: 4603 mov r3, r0 +10000ed4: 2004 movs r0, #4 +10000ed6: 4718 bx r3 + +10000ed8 : +10000ed8: b510 push {r4, lr} +10000eda: f245 2053 movw r0, #21075 @ 0x5253 +10000ede: f7ff ff57 bl 10000d90 +10000ee2: e8bd 4010 ldmia.w sp!, {r4, lr} +10000ee6: 4603 mov r3, r0 +10000ee8: 2001 movs r0, #1 +10000eea: 4718 bx r3 + +10000eec : +10000eec: f7ff ba2c b.w 10000348 + +10000ef0 : +10000ef0: 4914 ldr r1, [pc, #80] @ (10000f44 ) +10000ef2: 4b15 ldr r3, [pc, #84] @ (10000f48 ) +10000ef4: b570 push {r4, r5, r6, lr} +10000ef6: 1a5c subs r4, r3, r1 +10000ef8: 10a6 asrs r6, r4, #2 +10000efa: 2e44 cmp r6, #68 @ 0x44 +10000efc: 4632 mov r2, r6 +10000efe: bf28 it cs +10000f00: 2244 movcs r2, #68 @ 0x44 +10000f02: 4d12 ldr r5, [pc, #72] @ (10000f4c ) +10000f04: 0092 lsls r2, r2, #2 +10000f06: 4628 mov r0, r5 +10000f08: f000 f9fa bl 10001300 +10000f0c: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10000f10: d813 bhi.n 10000f3a +10000f12: 4a0f ldr r2, [pc, #60] @ (10000f50 ) +10000f14: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10000f18: d012 beq.n 10000f40 +10000f1a: 192b adds r3, r5, r4 +10000f1c: 0841 lsrs r1, r0, #1 +10000f1e: eb03 01c1 add.w r1, r3, r1, lsl #3 +10000f22: e9c3 2200 strd r2, r2, [r3] +10000f26: 3308 adds r3, #8 +10000f28: 428b cmp r3, r1 +10000f2a: d1fa bne.n 10000f22 +10000f2c: 07c3 lsls r3, r0, #31 +10000f2e: d504 bpl.n 10000f3a +10000f30: f020 0001 bic.w r0, r0, #1 +10000f34: 4430 add r0, r6 +10000f36: f845 2020 str.w r2, [r5, r0, lsl #2] +10000f3a: 4b06 ldr r3, [pc, #24] @ (10000f54 ) +10000f3c: 609d str r5, [r3, #8] +10000f3e: bd70 pop {r4, r5, r6, pc} +10000f40: 2043 movs r0, #67 @ 0x43 +10000f42: e7f8 b.n 10000f36 +10000f44: 10000000 .word 0x10000000 +10000f48: 10000110 .word 0x10000110 +10000f4c: 20000000 .word 0x20000000 +10000f50: 10000111 .word 0x10000111 +10000f54: e000ed00 .word 0xe000ed00 + +10000f58 : +10000f58: 2300 movs r3, #0 +10000f5a: b570 push {r4, r5, r6, lr} +10000f5c: 4c2b ldr r4, [pc, #172] @ (1000100c ) +10000f5e: b082 sub sp, #8 +10000f60: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10000f64: f7ff ff38 bl 10000dd8 +10000f68: 2201 movs r2, #1 +10000f6a: 4b29 ldr r3, [pc, #164] @ (10001010 ) +10000f6c: 63da str r2, [r3, #60] @ 0x3c +10000f6e: 6c63 ldr r3, [r4, #68] @ 0x44 +10000f70: 2b01 cmp r3, #1 +10000f72: d1fc bne.n 10000f6e +10000f74: 2103 movs r1, #3 +10000f76: 4a26 ldr r2, [pc, #152] @ (10001010 ) +10000f78: 4b24 ldr r3, [pc, #144] @ (1000100c ) +10000f7a: 6311 str r1, [r2, #48] @ 0x30 +10000f7c: 6b9c ldr r4, [r3, #56] @ 0x38 +10000f7e: 2c01 cmp r4, #1 +10000f80: d1fc bne.n 10000f7c +10000f82: 2602 movs r6, #2 +10000f84: 2505 movs r5, #5 +10000f86: 4621 mov r1, r4 +10000f88: 2305 movs r3, #5 +10000f8a: 4a22 ldr r2, [pc, #136] @ (10001014 ) +10000f8c: 4822 ldr r0, [pc, #136] @ (10001018 ) +10000f8e: 9600 str r6, [sp, #0] +10000f90: f7ff feac bl 10000cec +10000f94: 4621 mov r1, r4 +10000f96: 462b mov r3, r5 +10000f98: 4a20 ldr r2, [pc, #128] @ (1000101c ) +10000f9a: 4821 ldr r0, [pc, #132] @ (10001020 ) +10000f9c: 9500 str r5, [sp, #0] +10000f9e: f7ff fea5 bl 10000cec +10000fa2: 2200 movs r2, #0 +10000fa4: 2004 movs r0, #4 +10000fa6: 4631 mov r1, r6 +10000fa8: 4b1e ldr r3, [pc, #120] @ (10001024 ) +10000faa: f7ff fe31 bl 10000c10 +10000fae: 4621 mov r1, r4 +10000fb0: 4628 mov r0, r5 +10000fb2: 2200 movs r2, #0 +10000fb4: 4b1c ldr r3, [pc, #112] @ (10001028 ) +10000fb6: f7ff fe2b bl 10000c10 +10000fba: 2200 movs r2, #0 +10000fbc: 2008 movs r0, #8 +10000fbe: 4611 mov r1, r2 +10000fc0: 4b1a ldr r3, [pc, #104] @ (1000102c ) +10000fc2: f7ff fe25 bl 10000c10 +10000fc6: 2200 movs r2, #0 +10000fc8: 2009 movs r0, #9 +10000fca: 4611 mov r1, r2 +10000fcc: 4b17 ldr r3, [pc, #92] @ (1000102c ) +10000fce: f7ff fe1f bl 10000c10 +10000fd2: 2200 movs r2, #0 +10000fd4: 2006 movs r0, #6 +10000fd6: 4611 mov r1, r2 +10000fd8: 4b13 ldr r3, [pc, #76] @ (10001028 ) +10000fda: f7ff fe19 bl 10000c10 +10000fde: 2200 movs r2, #0 +10000fe0: 4b11 ldr r3, [pc, #68] @ (10001028 ) +10000fe2: 2007 movs r0, #7 +10000fe4: 4611 mov r1, r2 +10000fe6: f7ff fe13 bl 10000c10 +10000fea: 2004 movs r0, #4 +10000fec: f7ff fe78 bl 10000ce0 +10000ff0: 2400 movs r4, #0 +10000ff2: 4b0f ldr r3, [pc, #60] @ (10001030 ) +10000ff4: fba3 3500 umull r3, r5, r3, r0 +10000ff8: 0cad lsrs r5, r5, #18 +10000ffa: b2e0 uxtb r0, r4 +10000ffc: 4629 mov r1, r5 +10000ffe: 3401 adds r4, #1 +10001000: f7ff feba bl 10000d78 +10001004: 2c06 cmp r4, #6 +10001006: d1f8 bne.n 10000ffa +10001008: b002 add sp, #8 +1000100a: bd70 pop {r4, r5, r6, pc} +1000100c: 40010000 .word 0x40010000 +10001010: 40013000 .word 0x40013000 +10001014: 59682f00 .word 0x59682f00 +10001018: 40050000 .word 0x40050000 +1000101c: 47868c00 .word 0x47868c00 +10001020: 40058000 .word 0x40058000 +10001024: 00b71b00 .word 0x00b71b00 +10001028: 08f0d180 .word 0x08f0d180 +1000102c: 02dc6c00 .word 0x02dc6c00 +10001030: 431bde83 .word 0x431bde83 + +10001034 <_out_char>: +10001034: b900 cbnz r0, 10001038 <_out_char+0x4> +10001036: 4770 bx lr +10001038: f000 b902 b.w 10001240 <__wrap_putchar> + +1000103c : +1000103c: b510 push {r4, lr} +1000103e: 4b09 ldr r3, [pc, #36] @ (10001064 ) +10001040: b084 sub sp, #16 +10001042: 681c ldr r4, [r3, #0] +10001044: b14c cbz r4, 1000105a +10001046: 4603 mov r3, r0 +10001048: 9100 str r1, [sp, #0] +1000104a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000104e: a903 add r1, sp, #12 +10001050: 4805 ldr r0, [pc, #20] @ (10001068 ) +10001052: 47a0 blx r4 +10001054: 2001 movs r0, #1 +10001056: b004 add sp, #16 +10001058: bd10 pop {r4, pc} +1000105a: f000 f933 bl 100012c4 <__wrap_puts> +1000105e: 4620 mov r0, r4 +10001060: b004 add sp, #16 +10001062: bd10 pop {r4, pc} +10001064: 20000424 .word 0x20000424 +10001068: 10001035 .word 0x10001035 + +1000106c <_exit>: +1000106c: be00 bkpt 0x0000 +1000106e: e7fd b.n 1000106c <_exit> + +10001070 : +10001070: b508 push {r3, lr} +10001072: f7ff fffb bl 1000106c <_exit> +10001076: bf00 nop + +10001078 : +10001078: b538 push {r3, r4, r5, lr} +1000107a: 4c06 ldr r4, [pc, #24] @ (10001094 ) +1000107c: 4d06 ldr r5, [pc, #24] @ (10001098 ) +1000107e: f7ff fecb bl 10000e18 +10001082: 42ac cmp r4, r5 +10001084: d204 bcs.n 10001090 +10001086: f854 3b04 ldr.w r3, [r4], #4 +1000108a: 4798 blx r3 +1000108c: 42ac cmp r4, r5 +1000108e: d3fa bcc.n 10001086 +10001090: bd38 pop {r3, r4, r5, pc} +10001092: bf00 nop +10001094: 100014a0 .word 0x100014a0 +10001098: 100014a4 .word 0x100014a4 + +1000109c : +1000109c: 6803 ldr r3, [r0, #0] +1000109e: 4608 mov r0, r1 +100010a0: 4611 mov r1, r2 +100010a2: 4718 bx r3 + +100010a4 : +100010a4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100010a8: 4615 mov r5, r2 +100010aa: 7d42 ldrb r2, [r0, #21] +100010ac: 4607 mov r7, r0 +100010ae: 4688 mov r8, r1 +100010b0: 2a00 cmp r2, #0 +100010b2: d046 beq.n 10001142 +100010b4: 2d00 cmp r5, #0 +100010b6: dd1d ble.n 100010f4 +100010b8: 780b ldrb r3, [r1, #0] +100010ba: 2b0a cmp r3, #10 +100010bc: d023 beq.n 10001106 +100010be: 2d01 cmp r5, #1 +100010c0: f04f 0c00 mov.w ip, #0 +100010c4: d018 beq.n 100010f8 +100010c6: 4646 mov r6, r8 +100010c8: 2401 movs r4, #1 +100010ca: f816 2f01 ldrb.w r2, [r6, #1]! +100010ce: 4621 mov r1, r4 +100010d0: 2a0a cmp r2, #10 +100010d2: f104 0401 add.w r4, r4, #1 +100010d6: d022 beq.n 1000111e +100010d8: 42a5 cmp r5, r4 +100010da: d1f6 bne.n 100010ca +100010dc: 4565 cmp r5, ip +100010de: dc0b bgt.n 100010f8 +100010e0: eb08 0305 add.w r3, r8, r5 +100010e4: f813 3c01 ldrb.w r3, [r3, #-1] +100010e8: f1a3 030d sub.w r3, r3, #13 +100010ec: fab3 f383 clz r3, r3 +100010f0: 095b lsrs r3, r3, #5 +100010f2: 753b strb r3, [r7, #20] +100010f4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100010f8: 683b ldr r3, [r7, #0] +100010fa: eba5 010c sub.w r1, r5, ip +100010fe: eb08 000c add.w r0, r8, ip +10001102: 4798 blx r3 +10001104: e7ec b.n 100010e0 +10001106: 7d03 ldrb r3, [r0, #20] +10001108: 2b00 cmp r3, #0 +1000110a: d1d8 bne.n 100010be +1000110c: 6803 ldr r3, [r0, #0] +1000110e: 2102 movs r1, #2 +10001110: 480f ldr r0, [pc, #60] @ (10001150 ) +10001112: 4798 blx r3 +10001114: 2d01 cmp r5, #1 +10001116: d0e3 beq.n 100010e0 +10001118: f04f 0c01 mov.w ip, #1 +1000111c: e7d3 b.n 100010c6 +1000111e: f816 3c01 ldrb.w r3, [r6, #-1] +10001122: 2b0d cmp r3, #13 +10001124: d0d8 beq.n 100010d8 +10001126: 458c cmp ip, r1 +10001128: eb08 000c add.w r0, r8, ip +1000112c: eba1 010c sub.w r1, r1, ip +10001130: da01 bge.n 10001136 +10001132: 683b ldr r3, [r7, #0] +10001134: 4798 blx r3 +10001136: 2102 movs r1, #2 +10001138: 4805 ldr r0, [pc, #20] @ (10001150 ) +1000113a: 683b ldr r3, [r7, #0] +1000113c: 4798 blx r3 +1000113e: 46a4 mov ip, r4 +10001140: e7ca b.n 100010d8 +10001142: 4629 mov r1, r5 +10001144: 4640 mov r0, r8 +10001146: 683b ldr r3, [r7, #0] +10001148: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +1000114c: 4718 bx r3 +1000114e: bf00 nop +10001150: 100015a4 .word 0x100015a4 + +10001154 : +10001154: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10001158: b082 sub sp, #8 +1000115a: 460d mov r5, r1 +1000115c: 4691 mov r9, r2 +1000115e: 461c mov r4, r3 +10001160: 4606 mov r6, r0 +10001162: f7ff fd39 bl 10000bd8 +10001166: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +1000116a: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1000116e: 4a2e ldr r2, [pc, #184] @ (10001228 ) +10001170: 1882 adds r2, r0, r2 +10001172: f141 0300 adc.w r3, r1, #0 +10001176: 4594 cmp ip, r2 +10001178: eb77 0103 sbcs.w r1, r7, r3 +1000117c: bf3c itt cc +1000117e: 4662 movcc r2, ip +10001180: 463b movcc r3, r7 +10001182: 482a ldr r0, [pc, #168] @ (1000122c ) +10001184: f000 f968 bl 10001458 <__mutex_try_enter_block_until_veneer> +10001188: 1c6b adds r3, r5, #1 +1000118a: 4680 mov r8, r0 +1000118c: d040 beq.n 10001210 +1000118e: b30c cbz r4, 100011d4 +10001190: 4f27 ldr r7, [pc, #156] @ (10001230 ) +10001192: 4b28 ldr r3, [pc, #160] @ (10001234 ) +10001194: 681c ldr r4, [r3, #0] +10001196: b1b4 cbz r4, 100011c6 +10001198: f1b9 0f00 cmp.w r9, #0 +1000119c: d11c bne.n 100011d8 +1000119e: f8df 909c ldr.w r9, [pc, #156] @ 1000123c +100011a2: e001 b.n 100011a8 +100011a4: 6924 ldr r4, [r4, #16] +100011a6: b174 cbz r4, 100011c6 +100011a8: 6823 ldr r3, [r4, #0] +100011aa: 2b00 cmp r3, #0 +100011ac: d0fa beq.n 100011a4 +100011ae: f8d9 3000 ldr.w r3, [r9] +100011b2: b10b cbz r3, 100011b8 +100011b4: 429c cmp r4, r3 +100011b6: d1f5 bne.n 100011a4 +100011b8: 4620 mov r0, r4 +100011ba: 462a mov r2, r5 +100011bc: 4631 mov r1, r6 +100011be: 47b8 blx r7 +100011c0: 6924 ldr r4, [r4, #16] +100011c2: 2c00 cmp r4, #0 +100011c4: d1f0 bne.n 100011a8 +100011c6: f1b8 0f00 cmp.w r8, #0 +100011ca: d126 bne.n 1000121a +100011cc: 4628 mov r0, r5 +100011ce: b002 add sp, #8 +100011d0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100011d4: 4f18 ldr r7, [pc, #96] @ (10001238 ) +100011d6: e7dc b.n 10001192 +100011d8: f04f 0a0a mov.w sl, #10 +100011dc: f8df 905c ldr.w r9, [pc, #92] @ 1000123c +100011e0: e002 b.n 100011e8 +100011e2: 6924 ldr r4, [r4, #16] +100011e4: 2c00 cmp r4, #0 +100011e6: d0ee beq.n 100011c6 +100011e8: 6823 ldr r3, [r4, #0] +100011ea: 2b00 cmp r3, #0 +100011ec: d0f9 beq.n 100011e2 +100011ee: f8d9 3000 ldr.w r3, [r9] +100011f2: b10b cbz r3, 100011f8 +100011f4: 42a3 cmp r3, r4 +100011f6: d1f4 bne.n 100011e2 +100011f8: 462a mov r2, r5 +100011fa: 4631 mov r1, r6 +100011fc: 4620 mov r0, r4 +100011fe: 47b8 blx r7 +10001200: 2201 movs r2, #1 +10001202: 4620 mov r0, r4 +10001204: f10d 0107 add.w r1, sp, #7 +10001208: f88d a007 strb.w sl, [sp, #7] +1000120c: 47b8 blx r7 +1000120e: e7e8 b.n 100011e2 +10001210: 4630 mov r0, r6 +10001212: f000 f8eb bl 100013ec +10001216: 4605 mov r5, r0 +10001218: e7b9 b.n 1000118e +1000121a: 4804 ldr r0, [pc, #16] @ (1000122c ) +1000121c: f000 f918 bl 10001450 <__mutex_exit_veneer> +10001220: 4628 mov r0, r5 +10001222: b002 add sp, #8 +10001224: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001228: 000f4240 .word 0x000f4240 +1000122c: 20000244 .word 0x20000244 +10001230: 100010a5 .word 0x100010a5 +10001234: 2000041c .word 0x2000041c +10001238: 1000109d .word 0x1000109d +1000123c: 20000420 .word 0x20000420 + +10001240 <__wrap_putchar>: +10001240: b5f0 push {r4, r5, r6, r7, lr} +10001242: b083 sub sp, #12 +10001244: 4606 mov r6, r0 +10001246: f88d 0007 strb.w r0, [sp, #7] +1000124a: f7ff fcc5 bl 10000bd8 +1000124e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10001252: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10001256: 4a17 ldr r2, [pc, #92] @ (100012b4 <__wrap_putchar+0x74>) +10001258: 1882 adds r2, r0, r2 +1000125a: f141 0300 adc.w r3, r1, #0 +1000125e: 4295 cmp r5, r2 +10001260: eb74 0103 sbcs.w r1, r4, r3 +10001264: bf3c itt cc +10001266: 4623 movcc r3, r4 +10001268: 462a movcc r2, r5 +1000126a: 4813 ldr r0, [pc, #76] @ (100012b8 <__wrap_putchar+0x78>) +1000126c: f000 f8f4 bl 10001458 <__mutex_try_enter_block_until_veneer> +10001270: 4b12 ldr r3, [pc, #72] @ (100012bc <__wrap_putchar+0x7c>) +10001272: 4607 mov r7, r0 +10001274: 681c ldr r4, [r3, #0] +10001276: b19c cbz r4, 100012a0 <__wrap_putchar+0x60> +10001278: 4d11 ldr r5, [pc, #68] @ (100012c0 <__wrap_putchar+0x80>) +1000127a: e001 b.n 10001280 <__wrap_putchar+0x40> +1000127c: 6924 ldr r4, [r4, #16] +1000127e: b17c cbz r4, 100012a0 <__wrap_putchar+0x60> +10001280: 6823 ldr r3, [r4, #0] +10001282: 2b00 cmp r3, #0 +10001284: d0fa beq.n 1000127c <__wrap_putchar+0x3c> +10001286: 682b ldr r3, [r5, #0] +10001288: b10b cbz r3, 1000128e <__wrap_putchar+0x4e> +1000128a: 429c cmp r4, r3 +1000128c: d1f6 bne.n 1000127c <__wrap_putchar+0x3c> +1000128e: 4620 mov r0, r4 +10001290: 2201 movs r2, #1 +10001292: f10d 0107 add.w r1, sp, #7 +10001296: f7ff ff05 bl 100010a4 +1000129a: 6924 ldr r4, [r4, #16] +1000129c: 2c00 cmp r4, #0 +1000129e: d1ef bne.n 10001280 <__wrap_putchar+0x40> +100012a0: b917 cbnz r7, 100012a8 <__wrap_putchar+0x68> +100012a2: 4630 mov r0, r6 +100012a4: b003 add sp, #12 +100012a6: bdf0 pop {r4, r5, r6, r7, pc} +100012a8: 4803 ldr r0, [pc, #12] @ (100012b8 <__wrap_putchar+0x78>) +100012aa: f000 f8d1 bl 10001450 <__mutex_exit_veneer> +100012ae: 4630 mov r0, r6 +100012b0: b003 add sp, #12 +100012b2: bdf0 pop {r4, r5, r6, r7, pc} +100012b4: 000f4240 .word 0x000f4240 +100012b8: 20000244 .word 0x20000244 +100012bc: 2000041c .word 0x2000041c +100012c0: 20000420 .word 0x20000420 + +100012c4 <__wrap_puts>: +100012c4: b538 push {r3, r4, r5, lr} +100012c6: 4604 mov r4, r0 +100012c8: f000 f890 bl 100013ec +100012cc: 2301 movs r3, #1 +100012ce: 4605 mov r5, r0 +100012d0: 461a mov r2, r3 +100012d2: 4620 mov r0, r4 +100012d4: 4629 mov r1, r5 +100012d6: f7ff ff3d bl 10001154 +100012da: 4b08 ldr r3, [pc, #32] @ (100012fc <__wrap_puts+0x38>) +100012dc: 681c ldr r4, [r3, #0] +100012de: b12c cbz r4, 100012ec <__wrap_puts+0x28> +100012e0: 6863 ldr r3, [r4, #4] +100012e2: b12b cbz r3, 100012f0 <__wrap_puts+0x2c> +100012e4: 4798 blx r3 +100012e6: 6924 ldr r4, [r4, #16] +100012e8: 2c00 cmp r4, #0 +100012ea: d1f9 bne.n 100012e0 <__wrap_puts+0x1c> +100012ec: 4628 mov r0, r5 +100012ee: bd38 pop {r3, r4, r5, pc} +100012f0: 6924 ldr r4, [r4, #16] +100012f2: 2c00 cmp r4, #0 +100012f4: d1f4 bne.n 100012e0 <__wrap_puts+0x1c> +100012f6: 4628 mov r0, r5 +100012f8: bd38 pop {r3, r4, r5, pc} +100012fa: bf00 nop +100012fc: 2000041c .word 0x2000041c + +10001300 : +10001300: 4684 mov ip, r0 +10001302: ea41 0300 orr.w r3, r1, r0 +10001306: f013 0303 ands.w r3, r3, #3 +1000130a: d149 bne.n 100013a0 +1000130c: 3a40 subs r2, #64 @ 0x40 +1000130e: d323 bcc.n 10001358 +10001310: 680b ldr r3, [r1, #0] +10001312: 6003 str r3, [r0, #0] +10001314: 684b ldr r3, [r1, #4] +10001316: 6043 str r3, [r0, #4] +10001318: 688b ldr r3, [r1, #8] +1000131a: 6083 str r3, [r0, #8] +1000131c: 68cb ldr r3, [r1, #12] +1000131e: 60c3 str r3, [r0, #12] +10001320: 690b ldr r3, [r1, #16] +10001322: 6103 str r3, [r0, #16] +10001324: 694b ldr r3, [r1, #20] +10001326: 6143 str r3, [r0, #20] +10001328: 698b ldr r3, [r1, #24] +1000132a: 6183 str r3, [r0, #24] +1000132c: 69cb ldr r3, [r1, #28] +1000132e: 61c3 str r3, [r0, #28] +10001330: 6a0b ldr r3, [r1, #32] +10001332: 6203 str r3, [r0, #32] +10001334: 6a4b ldr r3, [r1, #36] @ 0x24 +10001336: 6243 str r3, [r0, #36] @ 0x24 +10001338: 6a8b ldr r3, [r1, #40] @ 0x28 +1000133a: 6283 str r3, [r0, #40] @ 0x28 +1000133c: 6acb ldr r3, [r1, #44] @ 0x2c +1000133e: 62c3 str r3, [r0, #44] @ 0x2c +10001340: 6b0b ldr r3, [r1, #48] @ 0x30 +10001342: 6303 str r3, [r0, #48] @ 0x30 +10001344: 6b4b ldr r3, [r1, #52] @ 0x34 +10001346: 6343 str r3, [r0, #52] @ 0x34 +10001348: 6b8b ldr r3, [r1, #56] @ 0x38 +1000134a: 6383 str r3, [r0, #56] @ 0x38 +1000134c: 6bcb ldr r3, [r1, #60] @ 0x3c +1000134e: 63c3 str r3, [r0, #60] @ 0x3c +10001350: 3040 adds r0, #64 @ 0x40 +10001352: 3140 adds r1, #64 @ 0x40 +10001354: 3a40 subs r2, #64 @ 0x40 +10001356: d2db bcs.n 10001310 +10001358: 3230 adds r2, #48 @ 0x30 +1000135a: d30b bcc.n 10001374 +1000135c: 680b ldr r3, [r1, #0] +1000135e: 6003 str r3, [r0, #0] +10001360: 684b ldr r3, [r1, #4] +10001362: 6043 str r3, [r0, #4] +10001364: 688b ldr r3, [r1, #8] +10001366: 6083 str r3, [r0, #8] +10001368: 68cb ldr r3, [r1, #12] +1000136a: 60c3 str r3, [r0, #12] +1000136c: 3010 adds r0, #16 +1000136e: 3110 adds r1, #16 +10001370: 3a10 subs r2, #16 +10001372: d2f3 bcs.n 1000135c +10001374: 320c adds r2, #12 +10001376: d305 bcc.n 10001384 +10001378: f851 3b04 ldr.w r3, [r1], #4 +1000137c: f840 3b04 str.w r3, [r0], #4 +10001380: 3a04 subs r2, #4 +10001382: d2f9 bcs.n 10001378 +10001384: 3204 adds r2, #4 +10001386: d008 beq.n 1000139a +10001388: 07d2 lsls r2, r2, #31 +1000138a: bf1c itt ne +1000138c: f811 3b01 ldrbne.w r3, [r1], #1 +10001390: f800 3b01 strbne.w r3, [r0], #1 +10001394: d301 bcc.n 1000139a +10001396: 880b ldrh r3, [r1, #0] +10001398: 8003 strh r3, [r0, #0] +1000139a: 4660 mov r0, ip +1000139c: 4770 bx lr +1000139e: bf00 nop +100013a0: 2a08 cmp r2, #8 +100013a2: d313 bcc.n 100013cc +100013a4: 078b lsls r3, r1, #30 +100013a6: d0b1 beq.n 1000130c +100013a8: f010 0303 ands.w r3, r0, #3 +100013ac: d0ae beq.n 1000130c +100013ae: f1c3 0304 rsb r3, r3, #4 +100013b2: 1ad2 subs r2, r2, r3 +100013b4: 07db lsls r3, r3, #31 +100013b6: bf1c itt ne +100013b8: f811 3b01 ldrbne.w r3, [r1], #1 +100013bc: f800 3b01 strbne.w r3, [r0], #1 +100013c0: d3a4 bcc.n 1000130c +100013c2: f831 3b02 ldrh.w r3, [r1], #2 +100013c6: f820 3b02 strh.w r3, [r0], #2 +100013ca: e79f b.n 1000130c +100013cc: 3a04 subs r2, #4 +100013ce: d3d9 bcc.n 10001384 +100013d0: 3a01 subs r2, #1 +100013d2: f811 3b01 ldrb.w r3, [r1], #1 +100013d6: f800 3b01 strb.w r3, [r0], #1 +100013da: d2f9 bcs.n 100013d0 +100013dc: 780b ldrb r3, [r1, #0] +100013de: 7003 strb r3, [r0, #0] +100013e0: 784b ldrb r3, [r1, #1] +100013e2: 7043 strb r3, [r0, #1] +100013e4: 788b ldrb r3, [r1, #2] +100013e6: 7083 strb r3, [r0, #2] +100013e8: 4660 mov r0, ip +100013ea: 4770 bx lr + +100013ec : +100013ec: f020 0103 bic.w r1, r0, #3 +100013f0: f010 0003 ands.w r0, r0, #3 +100013f4: f1c0 0000 rsb r0, r0, #0 +100013f8: f851 3b04 ldr.w r3, [r1], #4 +100013fc: f100 0c04 add.w ip, r0, #4 +10001400: ea4f 0ccc mov.w ip, ip, lsl #3 +10001404: f06f 0200 mvn.w r2, #0 +10001408: bf1c itt ne +1000140a: fa22 f20c lsrne.w r2, r2, ip +1000140e: 4313 orrne r3, r2 +10001410: f04f 0c01 mov.w ip, #1 +10001414: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001418: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +1000141c: eba3 020c sub.w r2, r3, ip +10001420: ea22 0203 bic.w r2, r2, r3 +10001424: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001428: bf04 itt eq +1000142a: f851 3b04 ldreq.w r3, [r1], #4 +1000142e: 3004 addeq r0, #4 +10001430: d0f4 beq.n 1000141c +10001432: f1c2 0100 rsb r1, r2, #0 +10001436: ea02 0201 and.w r2, r2, r1 +1000143a: fab2 f282 clz r2, r2 +1000143e: f1c2 021f rsb r2, r2, #31 +10001442: eb00 00d2 add.w r0, r0, r2, lsr #3 +10001446: 4770 bx lr + +10001448 <_fini>: +10001448: b5f8 push {r3, r4, r5, r6, r7, lr} +1000144a: bf00 nop +1000144c: 0000 movs r0, r0 + ... + +10001450 <__mutex_exit_veneer>: +10001450: f85f f000 ldr.w pc, [pc] @ 10001454 <__mutex_exit_veneer+0x4> +10001454: 200001e5 .word 0x200001e5 + +10001458 <__mutex_try_enter_block_until_veneer>: +10001458: f85f f000 ldr.w pc, [pc] @ 1000145c <__mutex_try_enter_block_until_veneer+0x4> +1000145c: 2000017d .word 0x2000017d + +10001460 <__pre_init_runtime_init_bootrom_reset>: +10001460: 10000ec5 .... + +10001464 <__pre_init_runtime_init_early_resets>: +10001464: 10000e39 9... + +10001468 <__pre_init_runtime_init_usb_power_down>: +10001468: 10000e6d m... + +1000146c <__pre_init_runtime_init_clocks>: +1000146c: 10000f59 Y... + +10001470 <__pre_init_runtime_init_post_clock_resets>: +10001470: 10000ea5 .... + +10001474 <__pre_init_runtime_init_boot_locks_reset>: +10001474: 10000dbd .... + +10001478 <__pre_init_runtime_init_spin_locks_reset>: +10001478: 10000eed .... + +1000147c <__pre_init_runtime_init_bootrom_locking_enable>: +1000147c: 10000da9 .... + +10001480 <__pre_init_runtime_init_mutex>: +10001480: 10000439 9... + +10001484 <__pre_init_runtime_init_install_ram_vector_table>: +10001484: 10000ef1 .... + +10001488 <__pre_init_runtime_init_default_alarm_pool>: +10001488: 100007b1 .... + +1000148c <__pre_init_first_per_core_initializer>: +1000148c: 10000e09 .... + +10001490 <__pre_init_runtime_init_per_core_bootrom_reset>: +10001490: 10000ed9 .... + +10001494 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10001494: 10000e89 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a/WEEK04/0x0008_uninitialized-variables-d/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables-d/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables-d/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables-d/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-d/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables-e/.gitignore b/WEEK04/0x0008_uninitialized-variables-e/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK04/0x0008_uninitialized-variables-e/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables-e/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables-e/0x0008_uninitialized-variables-e.c b/WEEK04/0x0008_uninitialized-variables-e/0x0008_uninitialized-variables-e.c new file mode 100644 index 0000000..5dba746 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/0x0008_uninitialized-variables-e.c @@ -0,0 +1,69 @@ +int main(void) { + __asm__ volatile ( + // gpio_init(LED_PIN); + /// gpio_set_dir(LED_PIN, GPIO_IN); + //// gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + "movs r4, #0x10\n" // GPIO16 + "movs r5, #0x01\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c4\n" // gpioc_bit_oe_put(16, 1); p102 + + // gpio_set_function(LED_PIN, GPIO_FUNC_SIO); + /// hw_write_masked(&pads_bank0_hw->io[LED_PIN], + /// PADS_BANK0_GPIO0_IE_BITS, + /// PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS + /// ); + //// hw_xor_bits(addr, (*addr ^ values) & write_mask); + "ldr r3, =0x40038044\n" // &pads_bank0_hw->io[16]; p785, p796 + "ldr r2, [r3]\n" // load current config + "bic r2, r2, #0x80\n" // clear OD; output disable + "orr r2, r2, #0x40\n" // set IE; enable input buffer + "str r2, [r3]\n" // store updated config + /// io_bank0_hw->io[LED_PIN].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; + "ldr r3, =0x40028084\n" // &io_bank0_hw->io[16].ctrl; p603, p637 + "ldr r2, [r3]\n" // load current config + "bic r2, r2, #0x1f\n" // clear FUNCSEL bits [4:0] + "orr r2, r2, #5\n" // set FUNCSEL = 5 (SIO) + "str r2, [r3]\n" // store updated config + /// hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS); + "ldr r3, =0x40038044\n" // &pads_bank0_hw->io[16]; p785, p796 + "ldr r2, [r3]\n" // load current config + "bic r2, r2, #0x100\n" // clear ISO bit (bit 8) un‑isolate pad + "str r2, [r3]\n" // store updated config + + // gpio_set_dir(LED_PIN, GPIO_OUT); + /// gpioc_bit_oe_put(LED_PIN, GPIO_OUT); + "movs r4, #0x10\n" // GPIO16 + "movs r5, #0x01\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c4\n" // gpioc_bit_oe_put(16, 1); p102 + + // while (true) + "1:\n" // loop start + + // gpio_put(LED_PIN, 1); + /// gpioc_bit_out_put(LED_PIN, 1); + "movs r4, #0x10\n" // GPIO16 + "movs r5, #0x01\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c0\n" // gpioc_bit_out_put(16, 1) + // sleep_ms(500); + /// sleep_us(500 * 1000ull); + "ldr r2, =0x17D7840\n" // r2 = ~8.4M cycles + "2:\n" // delay loop + "subs r2, r2, #1\n" // decrement counter + "bne 2b\n" // repeat until zero + + // gpio_put(LED_PIN, 1); + /// gpioc_bit_out_put(LED_PIN, 1); + "movs r4, #0x10\n" // GPIO16 + "movs r5, #0x00\n" // bit 0; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c0\n" // gpioc_bit_out_put(16, 0) + // sleep_ms(500); + /// sleep_us(500 * 1000ull); + "ldr r2, =0x17D7840\n" // r2 = ~8.4M cycles + "3:\n" // delay loop + "subs r2, r2, #1\n" // decrement counter + "bne 3b\n" // repeat until zero + + // jmp + "b 1b\n" // repeat forever + ); +} diff --git a/WEEK04/0x0008_uninitialized-variables-e/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables-e/CMakeLists.txt new file mode 100644 index 0000000..bfc1c28 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables-e C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables-e 0x0008_uninitialized-variables-e.c ) + +pico_set_program_name(0x0008_uninitialized-variables-e "0x0008_uninitialized-variables-e") +pico_set_program_version(0x0008_uninitialized-variables-e "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables-e 0) +pico_enable_stdio_usb(0x0008_uninitialized-variables-e 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables-e + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables-e PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables-e) + diff --git a/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.bin b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.bin new file mode 100755 index 0000000..035e5c8 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.bin differ diff --git a/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.dis b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.dis new file mode 100644 index 0000000..55f87d5 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.dis @@ -0,0 +1,2189 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000013a4 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000104 100013a4 100013a4 000023a4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100014a8 100014a8 000024a8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000020 100014b0 100014b0 000024b0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003620 2**0 + CONTENTS + 6 .data 0000013c 20000110 100014d0 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000024c 2000024c 00003620 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000024c 2000024c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000214 20000250 1000160c 00004250 2**3 + ALLOC + 10 .heap 00000800 20000464 1000160c 00004464 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003620 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003620 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 1000160c 1000160c 0000360c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003620 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00003654 2**0 + CONTENTS, READONLY + 17 .debug_info 0001ad9e 00000000 00000000 00003699 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 0000475b 00000000 00000000 0001e437 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000900 00000000 00000000 00022b98 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 0000252d 00000000 00000000 00023498 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 00011ae6 00000000 00000000 000259c5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 000046ab 00000000 00000000 000374ab 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 000018e4 00000000 00000000 0003bb58 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000d2c5 00000000 00000000 0003d43c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 0000018e 00000000 00000000 0004a701 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100014b0 .word 0x100014b0 +1000012c: 100014d0 .word 0x100014d0 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 000014d4 .word 0x000014d4 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100014d0 .word 0x100014d0 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000024c .word 0x2000024c +100001ac: 1000160c .word 0x1000160c +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 1000160c .word 0x1000160c +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000024c .word 0x2000024c +100001d4: 20000464 .word 0x20000464 +100001d8: 10000f7d .word 0x10000f7d +100001dc: 10000235 .word 0x10000235 +100001e0: 10000f75 .word 0x10000f75 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000024c .word 0x2000024c +10000208: 2000024c .word 0x2000024c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000428 .word 0x20000428 +10000230: 100013a4 .word 0x100013a4 + +10000234
: +10000234: 2410 movs r4, #16 +10000236: 2501 movs r5, #1 +10000238: ec45 4044 gpioc_bit_oe_put r4, r5 +1000023c: 4b13 ldr r3, [pc, #76] @ (1000028c ) +1000023e: 681a ldr r2, [r3, #0] +10000240: f022 0280 bic.w r2, r2, #128 @ 0x80 +10000244: f042 0240 orr.w r2, r2, #64 @ 0x40 +10000248: 601a str r2, [r3, #0] +1000024a: 4b11 ldr r3, [pc, #68] @ (10000290 ) +1000024c: 681a ldr r2, [r3, #0] +1000024e: f022 021f bic.w r2, r2, #31 +10000252: f042 0205 orr.w r2, r2, #5 +10000256: 601a str r2, [r3, #0] +10000258: 4b0c ldr r3, [pc, #48] @ (1000028c ) +1000025a: 681a ldr r2, [r3, #0] +1000025c: f422 7280 bic.w r2, r2, #256 @ 0x100 +10000260: 601a str r2, [r3, #0] +10000262: 2410 movs r4, #16 +10000264: 2501 movs r5, #1 +10000266: ec45 4044 gpioc_bit_oe_put r4, r5 +1000026a: 2410 movs r4, #16 +1000026c: 2501 movs r5, #1 +1000026e: ec45 4040 gpioc_bit_out_put r4, r5 +10000272: 4a08 ldr r2, [pc, #32] @ (10000294 ) +10000274: 3a01 subs r2, #1 +10000276: d1fd bne.n 10000274 +10000278: 2410 movs r4, #16 +1000027a: 2500 movs r5, #0 +1000027c: ec45 4040 gpioc_bit_out_put r4, r5 +10000280: 4a04 ldr r2, [pc, #16] @ (10000294 ) +10000282: 3a01 subs r2, #1 +10000284: d1fd bne.n 10000282 +10000286: e7f0 b.n 1000026a +10000288: 2000 movs r0, #0 +1000028a: 4770 bx lr +1000028c: 40038044 .word 0x40038044 +10000290: 40028084 .word 0x40028084 +10000294: 017d7840 .word 0x017d7840 + +10000298 : +10000298: b40f push {r0, r1, r2, r3} +1000029a: b500 push {lr} +1000029c: b083 sub sp, #12 +1000029e: 9c04 ldr r4, [sp, #16] +100002a0: 4807 ldr r0, [pc, #28] @ (100002c0 ) +100002a2: f000 ff91 bl 100011c8 <__wrap_puts> +100002a6: b13c cbz r4, 100002b8 +100002a8: a905 add r1, sp, #20 +100002aa: 4620 mov r0, r4 +100002ac: 9101 str r1, [sp, #4] +100002ae: f000 fe47 bl 10000f40 +100002b2: 4804 ldr r0, [pc, #16] @ (100002c4 ) +100002b4: f000 ff88 bl 100011c8 <__wrap_puts> +100002b8: 2001 movs r0, #1 +100002ba: f000 fe59 bl 10000f70 <_exit> +100002be: bf00 nop +100002c0: 100013a4 .word 0x100013a4 +100002c4: 100013b4 .word 0x100013b4 + +100002c8 : +100002c8: b570 push {r4, r5, r6, lr} +100002ca: 4686 mov lr, r0 +100002cc: f3ef 8510 mrs r5, PRIMASK +100002d0: b672 cpsid i +100002d2: 4c12 ldr r4, [pc, #72] @ (1000031c ) +100002d4: e8d4 6fcf ldaexb r6, [r4] +100002d8: 2001 movs r0, #1 +100002da: 2e00 cmp r6, #0 +100002dc: d1fa bne.n 100002d4 +100002de: e8c4 0f46 strexb r6, r0, [r4] +100002e2: 2e00 cmp r6, #0 +100002e4: d1f6 bne.n 100002d4 +100002e6: f3bf 8f5f dmb sy +100002ea: f04f 0c01 mov.w ip, #1 +100002ee: 08c8 lsrs r0, r1, #3 +100002f0: f001 0307 and.w r3, r1, #7 +100002f4: fa0c f303 lsl.w r3, ip, r3 +100002f8: f81e c000 ldrb.w ip, [lr, r0] +100002fc: ea1c 0603 ands.w r6, ip, r3 +10000300: d108 bne.n 10000314 +10000302: ea4c 0c03 orr.w ip, ip, r3 +10000306: f80e c000 strb.w ip, [lr, r0] +1000030a: e8c4 6f8f stlb r6, [r4] +1000030e: f385 8810 msr PRIMASK, r5 +10000312: bd70 pop {r4, r5, r6, pc} +10000314: 4610 mov r0, r2 +10000316: f7ff ffbf bl 10000298 +1000031a: bf00 nop +1000031c: 200003db .word 0x200003db + +10000320 : +10000320: 4a04 ldr r2, [pc, #16] @ (10000334 ) +10000322: 7810 ldrb r0, [r2, #0] +10000324: 1c43 adds r3, r0, #1 +10000326: b2db uxtb r3, r3 +10000328: 2b18 cmp r3, #24 +1000032a: bf28 it cs +1000032c: 2310 movcs r3, #16 +1000032e: 7013 strb r3, [r2, #0] +10000330: 4770 bx lr +10000332: bf00 nop +10000334: 20000228 .word 0x20000228 + +10000338 : +10000338: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +1000033c: 6893 ldr r3, [r2, #8] +1000033e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +10000342: 6093 str r3, [r2, #8] +10000344: 4770 bx lr +10000346: bf00 nop + +10000348 : +10000348: 2100 movs r1, #0 +1000034a: 4b04 ldr r3, [pc, #16] @ (1000035c ) +1000034c: f103 0220 add.w r2, r3, #32 +10000350: e8c3 1f8f stlb r1, [r3] +10000354: 3301 adds r3, #1 +10000356: 4293 cmp r3, r2 +10000358: d1fa bne.n 10000350 +1000035a: 4770 bx lr +1000035c: 200003d0 .word 0x200003d0 + +10000360 : +10000360: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000364: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000368: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +1000036c: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000370: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000374: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000378: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +1000037c: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000380: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000384: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000388: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000038c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000390: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000394: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000398: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000039c: b662 cpsie i +1000039e: 4770 bx lr + +100003a0 : +100003a0: 2301 movs r3, #1 +100003a2: f000 021f and.w r2, r0, #31 +100003a6: 4093 lsls r3, r2 +100003a8: 0940 lsrs r0, r0, #5 +100003aa: b141 cbz r1, 100003be +100003ac: 0080 lsls r0, r0, #2 +100003ae: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003b2: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003b6: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003ba: 6003 str r3, [r0, #0] +100003bc: 4770 bx lr +100003be: 4a02 ldr r2, [pc, #8] @ (100003c8 ) +100003c0: 3020 adds r0, #32 +100003c2: f842 3020 str.w r3, [r2, r0, lsl #2] +100003c6: 4770 bx lr +100003c8: e000e100 .word 0xe000e100 + +100003cc : +100003cc: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ce: 460d mov r5, r1 +100003d0: f3ef 8710 mrs r7, PRIMASK +100003d4: b672 cpsid i +100003d6: 4e12 ldr r6, [pc, #72] @ (10000420 ) +100003d8: e8d6 2fcf ldaexb r2, [r6] +100003dc: 2301 movs r3, #1 +100003de: 2a00 cmp r2, #0 +100003e0: d1fa bne.n 100003d8 +100003e2: e8c6 3f42 strexb r2, r3, [r6] +100003e6: 2a00 cmp r2, #0 +100003e8: d1f6 bne.n 100003d8 +100003ea: f3bf 8f5f dmb sy +100003ee: 4b0d ldr r3, [pc, #52] @ (10000424 ) +100003f0: f100 0410 add.w r4, r0, #16 +100003f4: 689b ldr r3, [r3, #8] +100003f6: 4a0c ldr r2, [pc, #48] @ (10000428 ) +100003f8: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003fc: 4293 cmp r3, r2 +100003fe: d003 beq.n 10000408 +10000400: 4299 cmp r1, r3 +10000402: d001 beq.n 10000408 +10000404: f000 fc84 bl 10000d10 +10000408: 4b06 ldr r3, [pc, #24] @ (10000424 ) +1000040a: 689b ldr r3, [r3, #8] +1000040c: f843 5024 str.w r5, [r3, r4, lsl #2] +10000410: f3bf 8f5f dmb sy +10000414: 2300 movs r3, #0 +10000416: e8c6 3f8f stlb r3, [r6] +1000041a: f387 8810 msr PRIMASK, r7 +1000041e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000420: 200003d9 .word 0x200003d9 +10000424: e000ed00 .word 0xe000ed00 +10000428: 10000111 .word 0x10000111 + +1000042c : +1000042c: 4b01 ldr r3, [pc, #4] @ (10000434 ) +1000042e: 440b add r3, r1 +10000430: 6003 str r3, [r0, #0] +10000432: 4770 bx lr +10000434: 200003d0 .word 0x200003d0 + +10000438 : +10000438: b570 push {r4, r5, r6, lr} +1000043a: 4c10 ldr r4, [pc, #64] @ (1000047c ) +1000043c: 4d10 ldr r5, [pc, #64] @ (10000480 ) +1000043e: 42ac cmp r4, r5 +10000440: d20e bcs.n 10000460 +10000442: 26ff movs r6, #255 @ 0xff +10000444: 6823 ldr r3, [r4, #0] +10000446: b163 cbz r3, 10000462 +10000448: f7ff ff6a bl 10000320 +1000044c: 4601 mov r1, r0 +1000044e: 4620 mov r0, r4 +10000450: f7ff ffec bl 1000042c +10000454: 80a6 strh r6, [r4, #4] +10000456: f3bf 8f5f dmb sy +1000045a: 3408 adds r4, #8 +1000045c: 42ac cmp r4, r5 +1000045e: d3f1 bcc.n 10000444 +10000460: bd70 pop {r4, r5, r6, pc} +10000462: f7ff ff5d bl 10000320 +10000466: 4601 mov r1, r0 +10000468: 4620 mov r0, r4 +1000046a: f7ff ffdf bl 1000042c +1000046e: 7126 strb r6, [r4, #4] +10000470: f3bf 8f5f dmb sy +10000474: 3408 adds r4, #8 +10000476: 42ac cmp r4, r5 +10000478: d3e4 bcc.n 10000444 +1000047a: bd70 pop {r4, r5, r6, pc} +1000047c: 20000244 .word 0x20000244 +10000480: 2000024c .word 0x2000024c + +10000484 : +10000484: 4b0d ldr r3, [pc, #52] @ (100004bc ) +10000486: 681a ldr r2, [r3, #0] +10000488: f3ef 8110 mrs r1, PRIMASK +1000048c: b672 cpsid i +1000048e: e8d2 cfcf ldaexb ip, [r2] +10000492: 2001 movs r0, #1 +10000494: f1bc 0f00 cmp.w ip, #0 +10000498: d1f9 bne.n 1000048e +1000049a: e8c2 0f4c strexb ip, r0, [r2] +1000049e: f1bc 0f00 cmp.w ip, #0 +100004a2: d1f4 bne.n 1000048e +100004a4: f3bf 8f5f dmb sy +100004a8: 2200 movs r2, #0 +100004aa: 681b ldr r3, [r3, #0] +100004ac: e8c3 2f8f stlb r2, [r3] +100004b0: f381 8810 msr PRIMASK, r1 +100004b4: bf40 sev +100004b6: 2000 movs r0, #0 +100004b8: 2100 movs r1, #0 +100004ba: 4770 bx lr +100004bc: 20000460 .word 0x20000460 + +100004c0 : +100004c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004c4: ed2d 8b02 vpush {d8} +100004c8: b085 sub sp, #20 +100004ca: f3ef 8305 mrs r3, IPSR +100004ce: b2db uxtb r3, r3 +100004d0: 3b10 subs r3, #16 +100004d2: 089a lsrs r2, r3, #2 +100004d4: bf18 it ne +100004d6: 2201 movne r2, #1 +100004d8: f04f 0101 mov.w r1, #1 +100004dc: f003 0b03 and.w fp, r3, #3 +100004e0: bf18 it ne +100004e2: 4daf ldrne r5, [pc, #700] @ (100007a0 ) +100004e4: 4baf ldr r3, [pc, #700] @ (100007a4 ) +100004e6: bf08 it eq +100004e8: 4daf ldreq r5, [pc, #700] @ (100007a8 ) +100004ea: eb0b 0282 add.w r2, fp, r2, lsl #2 +100004ee: f853 6022 ldr.w r6, [r3, r2, lsl #2] +100004f2: fa01 f20b lsl.w r2, r1, fp +100004f6: f505 5341 add.w r3, r5, #12352 @ 0x3040 +100004fa: ed9f 8ba7 vldr d8, [pc, #668] @ 10000798 +100004fe: 9201 str r2, [sp, #4] +10000500: 605a str r2, [r3, #4] +10000502: e02f b.n 10000564 +10000504: 88b3 ldrh r3, [r6, #4] +10000506: 041c lsls r4, r3, #16 +10000508: f140 8093 bpl.w 10000632 +1000050c: 79b3 ldrb r3, [r6, #6] +1000050e: 2b00 cmp r3, #0 +10000510: f040 80dd bne.w 100006ce +10000514: f9b6 2008 ldrsh.w r2, [r6, #8] +10000518: 2a00 cmp r2, #0 +1000051a: f2c0 811e blt.w 1000075a +1000051e: 6973 ldr r3, [r6, #20] +10000520: eb02 0242 add.w r2, r2, r2, lsl #1 +10000524: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000528: e9d3 4702 ldrd r4, r7, [r3, #8] +1000052c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000530: bf08 it eq +10000532: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000536: d00e beq.n 10000556 +10000538: eb05 018b add.w r1, r5, fp, lsl #2 +1000053c: 6aab ldr r3, [r5, #40] @ 0x28 +1000053e: 690a ldr r2, [r1, #16] +10000540: 1ad2 subs r2, r2, r3 +10000542: 1ae3 subs r3, r4, r3 +10000544: 4293 cmp r3, r2 +10000546: d305 bcc.n 10000554 +10000548: 2301 movs r3, #1 +1000054a: 6a2a ldr r2, [r5, #32] +1000054c: fa03 f30b lsl.w r3, r3, fp +10000550: 4213 tst r3, r2 +10000552: d100 bne.n 10000556 +10000554: 610c str r4, [r1, #16] +10000556: 4628 mov r0, r5 +10000558: f000 faca bl 10000af0 +1000055c: 42a0 cmp r0, r4 +1000055e: 41b9 sbcs r1, r7 +10000560: f2c0 80fb blt.w 1000075a +10000564: f9b6 3008 ldrsh.w r3, [r6, #8] +10000568: 9a01 ldr r2, [sp, #4] +1000056a: 2b00 cmp r3, #0 +1000056c: 9300 str r3, [sp, #0] +1000056e: 63ea str r2, [r5, #60] @ 0x3c +10000570: dbc8 blt.n 10000504 +10000572: f8d6 8014 ldr.w r8, [r6, #20] +10000576: eb03 0943 add.w r9, r3, r3, lsl #1 +1000057a: 4628 mov r0, r5 +1000057c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000580: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000584: f000 fab4 bl 10000af0 +10000588: 42a0 cmp r0, r4 +1000058a: eb71 010a sbcs.w r1, r1, sl +1000058e: dbb9 blt.n 10000504 +10000590: f1ba 0f00 cmp.w sl, #0 +10000594: f2c0 80c3 blt.w 1000071e +10000598: e9d7 3104 ldrd r3, r1, [r7, #16] +1000059c: 4a83 ldr r2, [pc, #524] @ (100007ac ) +1000059e: 4293 cmp r3, r2 +100005a0: f000 80ed beq.w 1000077e +100005a4: 887a ldrh r2, [r7, #2] +100005a6: f9b6 0008 ldrsh.w r0, [r6, #8] +100005aa: b292 uxth r2, r2 +100005ac: ea42 4000 orr.w r0, r2, r0, lsl #16 +100005b0: 4798 blx r3 +100005b2: 4602 mov r2, r0 +100005b4: 460b mov r3, r1 +100005b6: ea52 0103 orrs.w r1, r2, r3 +100005ba: f000 80b0 beq.w 1000071e +100005be: 2b00 cmp r3, #0 +100005c0: f280 80d1 bge.w 10000766 +100005c4: ebb4 0e02 subs.w lr, r4, r2 +100005c8: eb6a 0a03 sbc.w sl, sl, r3 +100005cc: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100005d0: e9c7 ea02 strd lr, sl, [r7, #8] +100005d4: 2b00 cmp r3, #0 +100005d6: db95 blt.n 10000504 +100005d8: 6971 ldr r1, [r6, #20] +100005da: eb03 0243 add.w r2, r3, r3, lsl #1 +100005de: eb01 02c2 add.w r2, r1, r2, lsl #3 +100005e2: e9d2 7002 ldrd r7, r0, [r2, #8] +100005e6: 45be cmp lr, r7 +100005e8: eb7a 0c00 sbcs.w ip, sl, r0 +100005ec: ea4f 0243 mov.w r2, r3, lsl #1 +100005f0: db88 blt.n 10000504 +100005f2: 46b4 mov ip, r6 +100005f4: f82c 3f08 strh.w r3, [ip, #8]! +100005f8: e006 b.n 10000608 +100005fa: eb03 0043 add.w r0, r3, r3, lsl #1 +100005fe: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000602: 005a lsls r2, r3, #1 +10000604: e9d0 7002 ldrd r7, r0, [r0, #8] +10000608: 45be cmp lr, r7 +1000060a: 441a add r2, r3 +1000060c: eb7a 0000 sbcs.w r0, sl, r0 +10000610: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000614: db04 blt.n 10000620 +10000616: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +1000061a: 46a4 mov ip, r4 +1000061c: 2b00 cmp r3, #0 +1000061e: daec bge.n 100005fa +10000620: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000624: 9b00 ldr r3, [sp, #0] +10000626: f8ac 3000 strh.w r3, [ip] +1000062a: 88b3 ldrh r3, [r6, #4] +1000062c: 041c lsls r4, r3, #16 +1000062e: f53f af6d bmi.w 1000050c +10000632: 6933 ldr r3, [r6, #16] +10000634: f3ef 8210 mrs r2, PRIMASK +10000638: b672 cpsid i +1000063a: e8d3 0fcf ldaexb r0, [r3] +1000063e: 2101 movs r1, #1 +10000640: 2800 cmp r0, #0 +10000642: d1fa bne.n 1000063a +10000644: e8c3 1f40 strexb r0, r1, [r3] +10000648: 2800 cmp r0, #0 +1000064a: d1f6 bne.n 1000063a +1000064c: f3bf 8f5f dmb sy +10000650: f64f 74ff movw r4, #65535 @ 0xffff +10000654: 88b0 ldrh r0, [r6, #4] +10000656: 2300 movs r3, #0 +10000658: 6931 ldr r1, [r6, #16] +1000065a: b200 sxth r0, r0 +1000065c: 80b4 strh r4, [r6, #4] +1000065e: e8c1 3f8f stlb r3, [r1] +10000662: f382 8810 msr PRIMASK, r2 +10000666: 4298 cmp r0, r3 +10000668: f6ff af50 blt.w 1000050c +1000066c: 4607 mov r7, r0 +1000066e: 46a9 mov r9, r5 +10000670: 6974 ldr r4, [r6, #20] +10000672: f106 0808 add.w r8, r6, #8 +10000676: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000067a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000067e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000682: f9b6 3008 ldrsh.w r3, [r6, #8] +10000686: 46c4 mov ip, r8 +10000688: 2b00 cmp r3, #0 +1000068a: db13 blt.n 100006b4 +1000068c: 46b2 mov sl, r6 +1000068e: 9700 str r7, [sp, #0] +10000690: e004 b.n 1000069c +10000692: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000696: 4694 mov ip, r2 +10000698: 2b00 cmp r3, #0 +1000069a: db09 blt.n 100006b0 +1000069c: eb03 0643 add.w r6, r3, r3, lsl #1 +100006a0: eb04 02c6 add.w r2, r4, r6, lsl #3 +100006a4: e9d2 7102 ldrd r7, r1, [r2, #8] +100006a8: 42bd cmp r5, r7 +100006aa: eb70 0101 sbcs.w r1, r0, r1 +100006ae: daf0 bge.n 10000692 +100006b0: 4656 mov r6, sl +100006b2: 9f00 ldr r7, [sp, #0] +100006b4: f8ac 7000 strh.w r7, [ip] +100006b8: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100006bc: f824 303e strh.w r3, [r4, lr, lsl #3] +100006c0: 2f00 cmp r7, #0 +100006c2: dad8 bge.n 10000676 +100006c4: 79b3 ldrb r3, [r6, #6] +100006c6: 464d mov r5, r9 +100006c8: 2b00 cmp r3, #0 +100006ca: f43f af23 beq.w 10000514 +100006ce: 2300 movs r3, #0 +100006d0: 71b3 strb r3, [r6, #6] +100006d2: f9b6 3008 ldrsh.w r3, [r6, #8] +100006d6: f106 0808 add.w r8, r6, #8 +100006da: 1c58 adds r0, r3, #1 +100006dc: d03d beq.n 1000075a +100006de: 461a mov r2, r3 +100006e0: 6977 ldr r7, [r6, #20] +100006e2: e003 b.n 100006ec +100006e4: 4680 mov r8, r0 +100006e6: 1c59 adds r1, r3, #1 +100006e8: f43f af16 beq.w 10000518 +100006ec: eb03 0143 add.w r1, r3, r3, lsl #1 +100006f0: eb07 00c1 add.w r0, r7, r1, lsl #3 +100006f4: f8b0 c002 ldrh.w ip, [r0, #2] +100006f8: 461c mov r4, r3 +100006fa: f41c 4f00 tst.w ip, #32768 @ 0x8000 +100006fe: 469e mov lr, r3 +10000700: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000704: d0ee beq.n 100006e4 +10000706: 4294 cmp r4, r2 +10000708: ed80 8b02 vstr d8, [r0, #8] +1000070c: d005 beq.n 1000071a +1000070e: f8a8 3000 strh.w r3, [r8] +10000712: 8932 ldrh r2, [r6, #8] +10000714: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000718: 8134 strh r4, [r6, #8] +1000071a: 4672 mov r2, lr +1000071c: e7e3 b.n 100006e6 +1000071e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000722: 8133 strh r3, [r6, #8] +10000724: 6933 ldr r3, [r6, #16] +10000726: f3ef 8210 mrs r2, PRIMASK +1000072a: b672 cpsid i +1000072c: e8d3 0fcf ldaexb r0, [r3] +10000730: 2101 movs r1, #1 +10000732: 2800 cmp r0, #0 +10000734: d1fa bne.n 1000072c +10000736: e8c3 1f40 strexb r0, r1, [r3] +1000073a: 2800 cmp r0, #0 +1000073c: d1f6 bne.n 1000072c +1000073e: f3bf 8f5f dmb sy +10000742: 8873 ldrh r3, [r6, #2] +10000744: 6931 ldr r1, [r6, #16] +10000746: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000074a: 9b00 ldr r3, [sp, #0] +1000074c: 8073 strh r3, [r6, #2] +1000074e: 2300 movs r3, #0 +10000750: e8c1 3f8f stlb r3, [r1] +10000754: f382 8810 msr PRIMASK, r2 +10000758: e6d4 b.n 10000504 +1000075a: bf40 sev +1000075c: b005 add sp, #20 +1000075e: ecbd 8b02 vpop {d8} +10000762: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000766: 4628 mov r0, r5 +10000768: e9cd 2302 strd r2, r3, [sp, #8] +1000076c: f000 f9c0 bl 10000af0 +10000770: 9a02 ldr r2, [sp, #8] +10000772: 9b03 ldr r3, [sp, #12] +10000774: eb10 0e02 adds.w lr, r0, r2 +10000778: eb43 0a01 adc.w sl, r3, r1 +1000077c: e726 b.n 100005cc +1000077e: 4608 mov r0, r1 +10000780: 690b ldr r3, [r1, #16] +10000782: 9102 str r1, [sp, #8] +10000784: 4798 blx r3 +10000786: 2800 cmp r0, #0 +10000788: d0c9 beq.n 1000071e +1000078a: 9902 ldr r1, [sp, #8] +1000078c: e9d1 2300 ldrd r2, r3, [r1] +10000790: e711 b.n 100005b6 +10000792: bf00 nop +10000794: f3af 8000 nop.w +10000798: ffffffff .word 0xffffffff +1000079c: ffffffff .word 0xffffffff +100007a0: 400b8000 .word 0x400b8000 +100007a4: 20000440 .word 0x20000440 +100007a8: 400b0000 .word 0x400b0000 +100007ac: 100004c1 .word 0x100004c1 + +100007b0 : +100007b0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007b4: 4c36 ldr r4, [pc, #216] @ (10000890 ) +100007b6: 6925 ldr r5, [r4, #16] +100007b8: b12d cbz r5, 100007c6 +100007ba: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007be: 210a movs r1, #10 +100007c0: 4834 ldr r0, [pc, #208] @ (10000894 ) +100007c2: f7ff be33 b.w 1000042c +100007c6: f8df 80e4 ldr.w r8, [pc, #228] @ 100008ac +100007ca: 2103 movs r1, #3 +100007cc: 4640 mov r0, r8 +100007ce: f000 f97d bl 10000acc +100007d2: 2603 movs r6, #3 +100007d4: f8c4 800c str.w r8, [r4, #12] +100007d8: f7ff fda2 bl 10000320 +100007dc: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +100007e0: 4b2d ldr r3, [pc, #180] @ (10000898 ) +100007e2: 7026 strb r6, [r4, #0] +100007e4: 4403 add r3, r0 +100007e6: 6123 str r3, [r4, #16] +100007e8: f8dc 3000 ldr.w r3, [ip] +100007ec: 210f movs r1, #15 +100007ee: 7063 strb r3, [r4, #1] +100007f0: 6963 ldr r3, [r4, #20] +100007f2: 8061 strh r1, [r4, #2] +100007f4: 831d strh r5, [r3, #24] +100007f6: f04f 0504 mov.w r5, #4 +100007fa: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +100007fe: f04f 0505 mov.w r5, #5 +10000802: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000806: f04f 0506 mov.w r5, #6 +1000080a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +1000080e: f04f 0507 mov.w r5, #7 +10000812: 210e movs r1, #14 +10000814: f64f 72ff movw r2, #65535 @ 0xffff +10000818: 2708 movs r7, #8 +1000081a: f04f 0e0a mov.w lr, #10 +1000081e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000822: f04f 0901 mov.w r9, #1 +10000826: f04f 0c0c mov.w ip, #12 +1000082a: f04f 0b02 mov.w fp, #2 +1000082e: f04f 0a09 mov.w sl, #9 +10000832: 200d movs r0, #13 +10000834: f04f 050b mov.w r5, #11 +10000838: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +1000083c: 4917 ldr r1, [pc, #92] @ (1000089c ) +1000083e: 80a2 strh r2, [r4, #4] +10000840: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000844: 60a1 str r1, [r4, #8] +10000846: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +1000084a: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +1000084e: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000852: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000856: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +1000085a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +1000085e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000862: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000866: 801a strh r2, [r3, #0] +10000868: 4b0d ldr r3, [pc, #52] @ (100008a0 ) +1000086a: 4630 mov r0, r6 +1000086c: f8c8 7020 str.w r7, [r8, #32] +10000870: 490c ldr r1, [pc, #48] @ (100008a4 ) +10000872: 60dc str r4, [r3, #12] +10000874: f7ff fdaa bl 100003cc +10000878: 4649 mov r1, r9 +1000087a: 4630 mov r0, r6 +1000087c: f7ff fd90 bl 100003a0 +10000880: 4b09 ldr r3, [pc, #36] @ (100008a8 ) +10000882: 210a movs r1, #10 +10000884: 641f str r7, [r3, #64] @ 0x40 +10000886: 4803 ldr r0, [pc, #12] @ (10000894 ) +10000888: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000088c: f7ff bdce b.w 1000042c +10000890: 2000022c .word 0x2000022c +10000894: 20000460 .word 0x20000460 +10000898: 200003d0 .word 0x200003d0 +1000089c: 0010ffff .word 0x0010ffff +100008a0: 20000440 .word 0x20000440 +100008a4: 100004c1 .word 0x100004c1 +100008a8: 400b2000 .word 0x400b2000 +100008ac: 400b0000 .word 0x400b0000 + +100008b0 : +100008b0: 4601 mov r1, r0 +100008b2: b5f0 push {r4, r5, r6, r7, lr} +100008b4: 6900 ldr r0, [r0, #16] +100008b6: f3ef 8710 mrs r7, PRIMASK +100008ba: b672 cpsid i +100008bc: e8d0 5fcf ldaexb r5, [r0] +100008c0: 2401 movs r4, #1 +100008c2: 2d00 cmp r5, #0 +100008c4: d1fa bne.n 100008bc +100008c6: e8c0 4f45 strexb r5, r4, [r0] +100008ca: 2d00 cmp r5, #0 +100008cc: d1f6 bne.n 100008bc +100008ce: f3bf 8f5f dmb sy +100008d2: f9b1 e002 ldrsh.w lr, [r1, #2] +100008d6: 694c ldr r4, [r1, #20] +100008d8: eb0e 0c4e add.w ip, lr, lr, lsl #1 +100008dc: f1be 0f00 cmp.w lr, #0 +100008e0: ea4f 05cc mov.w r5, ip, lsl #3 +100008e4: 6908 ldr r0, [r1, #16] +100008e6: eb04 0ccc add.w ip, r4, ip, lsl #3 +100008ea: db3c blt.n 10000966 +100008ec: 5b66 ldrh r6, [r4, r5] +100008ee: 804e strh r6, [r1, #2] +100008f0: 2600 movs r6, #0 +100008f2: e8c0 6f8f stlb r6, [r0] +100008f6: f387 8810 msr PRIMASK, r7 +100008fa: f8bc 0002 ldrh.w r0, [ip, #2] +100008fe: e9cc 2302 strd r2, r3, [ip, #8] +10000902: 3001 adds r0, #1 +10000904: f3c0 000e ubfx r0, r0, #0, #15 +10000908: 2801 cmp r0, #1 +1000090a: bf38 it cc +1000090c: 2001 movcc r0, #1 +1000090e: 9b05 ldr r3, [sp, #20] +10000910: f8ac 0002 strh.w r0, [ip, #2] +10000914: f8cc 3010 str.w r3, [ip, #16] +10000918: 9b06 ldr r3, [sp, #24] +1000091a: ea40 400e orr.w r0, r0, lr, lsl #16 +1000091e: f8cc 3014 str.w r3, [ip, #20] +10000922: 690b ldr r3, [r1, #16] +10000924: f3ef 8210 mrs r2, PRIMASK +10000928: b672 cpsid i +1000092a: e8d3 cfcf ldaexb ip, [r3] +1000092e: 2701 movs r7, #1 +10000930: f1bc 0f00 cmp.w ip, #0 +10000934: d1f9 bne.n 1000092a +10000936: e8c3 7f4c strexb ip, r7, [r3] +1000093a: f1bc 0f00 cmp.w ip, #0 +1000093e: d1f4 bne.n 1000092a +10000940: f3bf 8f5f dmb sy +10000944: 888b ldrh r3, [r1, #4] +10000946: 5363 strh r3, [r4, r5] +10000948: f8a1 e004 strh.w lr, [r1, #4] +1000094c: 690b ldr r3, [r1, #16] +1000094e: e8c3 6f8f stlb r6, [r3] +10000952: f382 8810 msr PRIMASK, r2 +10000956: 2201 movs r2, #1 +10000958: 68cb ldr r3, [r1, #12] +1000095a: 7809 ldrb r1, [r1, #0] +1000095c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000960: 408a lsls r2, r1 +10000962: 605a str r2, [r3, #4] +10000964: bdf0 pop {r4, r5, r6, r7, pc} +10000966: 2300 movs r3, #0 +10000968: e8c0 3f8f stlb r3, [r0] +1000096c: f387 8810 msr PRIMASK, r7 +10000970: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000974: bdf0 pop {r4, r5, r6, r7, pc} +10000976: bf00 nop + +10000978 : +10000978: 4603 mov r3, r0 +1000097a: 8940 ldrh r0, [r0, #10] +1000097c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000980: dd37 ble.n 100009f2 +10000982: 6958 ldr r0, [r3, #20] +10000984: 140a asrs r2, r1, #16 +10000986: eb02 0242 add.w r2, r2, r2, lsl #1 +1000098a: b510 push {r4, lr} +1000098c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000990: 691c ldr r4, [r3, #16] +10000992: f3ef 8c10 mrs ip, PRIMASK +10000996: b672 cpsid i +10000998: e8d4 efcf ldaexb lr, [r4] +1000099c: 2201 movs r2, #1 +1000099e: f1be 0f00 cmp.w lr, #0 +100009a2: d1f9 bne.n 10000998 +100009a4: e8c4 2f4e strexb lr, r2, [r4] +100009a8: f1be 0f00 cmp.w lr, #0 +100009ac: d1f4 bne.n 10000998 +100009ae: f3bf 8f5f dmb sy +100009b2: 8842 ldrh r2, [r0, #2] +100009b4: b289 uxth r1, r1 +100009b6: b292 uxth r2, r2 +100009b8: 428a cmp r2, r1 +100009ba: d007 beq.n 100009cc +100009bc: 2200 movs r2, #0 +100009be: 691b ldr r3, [r3, #16] +100009c0: e8c3 2f8f stlb r2, [r3] +100009c4: f38c 8810 msr PRIMASK, ip +100009c8: 2000 movs r0, #0 +100009ca: bd10 pop {r4, pc} +100009cc: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +100009d0: 8042 strh r2, [r0, #2] +100009d2: 2101 movs r1, #1 +100009d4: 2200 movs r2, #0 +100009d6: 6918 ldr r0, [r3, #16] +100009d8: 7199 strb r1, [r3, #6] +100009da: e8c0 2f8f stlb r2, [r0] +100009de: f38c 8810 msr PRIMASK, ip +100009e2: 781c ldrb r4, [r3, #0] +100009e4: 68da ldr r2, [r3, #12] +100009e6: 4608 mov r0, r1 +100009e8: f502 5301 add.w r3, r2, #8256 @ 0x2040 +100009ec: 40a1 lsls r1, r4 +100009ee: 6059 str r1, [r3, #4] +100009f0: bd10 pop {r4, pc} +100009f2: 2000 movs r0, #0 +100009f4: 4770 bx lr +100009f6: bf00 nop + +100009f8 : +100009f8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100009fc: 4606 mov r6, r0 +100009fe: 460d mov r5, r1 +10000a00: b083 sub sp, #12 +10000a02: f3ef 8405 mrs r4, IPSR +10000a06: b2e4 uxtb r4, r4 +10000a08: b13c cbz r4, 10000a1a +10000a0a: 4b2d ldr r3, [pc, #180] @ (10000ac0 ) +10000a0c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000a0e: 42aa cmp r2, r5 +10000a10: d21c bcs.n 10000a4c +10000a12: 2000 movs r0, #0 +10000a14: b003 add sp, #12 +10000a16: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000a1a: 4f2a ldr r7, [pc, #168] @ (10000ac4 ) +10000a1c: f8d7 900c ldr.w r9, [r7, #12] +10000a20: f897 8000 ldrb.w r8, [r7] +10000a24: 4648 mov r0, r9 +10000a26: f000 f863 bl 10000af0 +10000a2a: f108 0804 add.w r8, r8, #4 +10000a2e: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000a32: 1a1b subs r3, r3, r0 +10000a34: 1a30 subs r0, r6, r0 +10000a36: eb65 0101 sbc.w r1, r5, r1 +10000a3a: 4298 cmp r0, r3 +10000a3c: f171 0100 sbcs.w r1, r1, #0 +10000a40: db10 blt.n 10000a64 +10000a42: bf20 wfe +10000a44: 4b1e ldr r3, [pc, #120] @ (10000ac0 ) +10000a46: 6a5a ldr r2, [r3, #36] @ 0x24 +10000a48: 42aa cmp r2, r5 +10000a4a: d3e2 bcc.n 10000a12 +10000a4c: bf14 ite ne +10000a4e: 2401 movne r4, #1 +10000a50: 2400 moveq r4, #0 +10000a52: 6a9b ldr r3, [r3, #40] @ 0x28 +10000a54: 42b3 cmp r3, r6 +10000a56: bf34 ite cc +10000a58: 4620 movcc r0, r4 +10000a5a: f044 0001 orrcs.w r0, r4, #1 +10000a5e: b003 add sp, #12 +10000a60: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000a64: f000 f84c bl 10000b00 +10000a68: 4286 cmp r6, r0 +10000a6a: eb65 0101 sbc.w r1, r5, r1 +10000a6e: 2900 cmp r1, #0 +10000a70: db14 blt.n 10000a9c +10000a72: 4b15 ldr r3, [pc, #84] @ (10000ac8 ) +10000a74: 4638 mov r0, r7 +10000a76: e9cd 3400 strd r3, r4, [sp] +10000a7a: 4632 mov r2, r6 +10000a7c: 462b mov r3, r5 +10000a7e: f7ff ff17 bl 100008b0 +10000a82: 1e01 subs r1, r0, #0 +10000a84: dd0a ble.n 10000a9c +10000a86: 4b0e ldr r3, [pc, #56] @ (10000ac0 ) +10000a88: 6a5a ldr r2, [r3, #36] @ 0x24 +10000a8a: 42aa cmp r2, r5 +10000a8c: d316 bcc.n 10000abc +10000a8e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000a90: 42b3 cmp r3, r6 +10000a92: d311 bcc.n 10000ab8 +10000a94: 480b ldr r0, [pc, #44] @ (10000ac4 ) +10000a96: f7ff ff6f bl 10000978 +10000a9a: e7b6 b.n 10000a0a +10000a9c: 4b08 ldr r3, [pc, #32] @ (10000ac0 ) +10000a9e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000aa0: 42ac cmp r4, r5 +10000aa2: d3b6 bcc.n 10000a12 +10000aa4: 1b64 subs r4, r4, r5 +10000aa6: bf18 it ne +10000aa8: 2401 movne r4, #1 +10000aaa: 6a9b ldr r3, [r3, #40] @ 0x28 +10000aac: 42b3 cmp r3, r6 +10000aae: bf34 ite cc +10000ab0: 4620 movcc r0, r4 +10000ab2: f044 0001 orrcs.w r0, r4, #1 +10000ab6: e7ad b.n 10000a14 +10000ab8: 42aa cmp r2, r5 +10000aba: d1eb bne.n 10000a94 +10000abc: bf20 wfe +10000abe: e7e9 b.n 10000a94 +10000ac0: 400b0000 .word 0x400b0000 +10000ac4: 2000022c .word 0x2000022c +10000ac8: 10000485 .word 0x10000485 + +10000acc : +10000acc: b410 push {r4} +10000ace: 4b05 ldr r3, [pc, #20] @ (10000ae4 ) +10000ad0: 4c05 ldr r4, [pc, #20] @ (10000ae8 ) +10000ad2: 4a06 ldr r2, [pc, #24] @ (10000aec ) +10000ad4: 42a0 cmp r0, r4 +10000ad6: bf14 ite ne +10000ad8: 4618 movne r0, r3 +10000ada: 1c58 addeq r0, r3, #1 +10000adc: f85d 4b04 ldr.w r4, [sp], #4 +10000ae0: f7ff bbf2 b.w 100002c8 +10000ae4: 200003f0 .word 0x200003f0 +10000ae8: 400b8000 .word 0x400b8000 +10000aec: 100013b8 .word 0x100013b8 + +10000af0 : +10000af0: 4603 mov r3, r0 +10000af2: 6a41 ldr r1, [r0, #36] @ 0x24 +10000af4: 460a mov r2, r1 +10000af6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000af8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000afa: 428a cmp r2, r1 +10000afc: d1fa bne.n 10000af4 +10000afe: 4770 bx lr + +10000b00 : +10000b00: 4b03 ldr r3, [pc, #12] @ (10000b10 ) +10000b02: 6a59 ldr r1, [r3, #36] @ 0x24 +10000b04: 460a mov r2, r1 +10000b06: 6a98 ldr r0, [r3, #40] @ 0x28 +10000b08: 6a59 ldr r1, [r3, #36] @ 0x24 +10000b0a: 4291 cmp r1, r2 +10000b0c: d1fa bne.n 10000b04 +10000b0e: 4770 bx lr +10000b10: 400b0000 .word 0x400b0000 + +10000b14 : +10000b14: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000b18: ea4f 0c8c mov.w ip, ip, lsl #2 +10000b1c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000b20: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000b24: b5f0 push {r4, r5, r6, r7, lr} +10000b26: 4616 mov r6, r2 +10000b28: f8dc 2004 ldr.w r2, [ip, #4] +10000b2c: 1f05 subs r5, r0, #4 +10000b2e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000b32: bf38 it cc +10000b34: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000b38: b2ed uxtb r5, r5 +10000b3a: bf38 it cc +10000b3c: f8cc 2004 strcc.w r2, [ip, #4] +10000b40: 2d01 cmp r5, #1 +10000b42: d92a bls.n 10000b9a +10000b44: f44f 6700 mov.w r7, #2048 @ 0x800 +10000b48: 4c25 ldr r4, [pc, #148] @ (10000be0 ) +10000b4a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000b4e: 6017 str r7, [r2, #0] +10000b50: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000b54: b9b2 cbnz r2, 10000b84 +10000b56: f8dc 2000 ldr.w r2, [ip] +10000b5a: 2d01 cmp r5, #1 +10000b5c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000b60: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000b64: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000b68: 6032 str r2, [r6, #0] +10000b6a: d92a bls.n 10000bc2 +10000b6c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000b70: f844 3020 str.w r3, [r4, r0, lsl #2] +10000b74: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000b78: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000b7c: 6011 str r1, [r2, #0] +10000b7e: f8cc 3004 str.w r3, [ip, #4] +10000b82: bdf0 pop {r4, r5, r6, r7, pc} +10000b84: 6967 ldr r7, [r4, #20] +10000b86: fbb7 fef2 udiv lr, r7, r2 +10000b8a: f10e 0e01 add.w lr, lr, #1 +10000b8e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000b92: f1be 0e03 subs.w lr, lr, #3 +10000b96: d2fc bcs.n 10000b92 +10000b98: e7dd b.n 10000b56 +10000b9a: 2901 cmp r1, #1 +10000b9c: d1d2 bne.n 10000b44 +10000b9e: 2403 movs r4, #3 +10000ba0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000ba4: 6014 str r4, [r2, #0] +10000ba6: f8dc 2008 ldr.w r2, [ip, #8] +10000baa: 07d2 lsls r2, r2, #31 +10000bac: d5fb bpl.n 10000ba6 +10000bae: f8dc 2000 ldr.w r2, [ip] +10000bb2: 4c0b ldr r4, [pc, #44] @ (10000be0 ) +10000bb4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000bb8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000bbc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000bc0: 6032 str r2, [r6, #0] +10000bc2: 2201 movs r2, #1 +10000bc4: f8dc 5000 ldr.w r5, [ip] +10000bc8: 404d eors r5, r1 +10000bca: f005 0503 and.w r5, r5, #3 +10000bce: 6035 str r5, [r6, #0] +10000bd0: fa02 f101 lsl.w r1, r2, r1 +10000bd4: f8dc 2008 ldr.w r2, [ip, #8] +10000bd8: 420a tst r2, r1 +10000bda: d0fb beq.n 10000bd4 +10000bdc: e7c6 b.n 10000b6c +10000bde: bf00 nop +10000be0: 200003f4 .word 0x200003f4 + +10000be4 : +10000be4: 4b01 ldr r3, [pc, #4] @ (10000bec ) +10000be6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000bea: 4770 bx lr +10000bec: 200003f4 .word 0x200003f4 + +10000bf0 : +10000bf0: b470 push {r4, r5, r6} +10000bf2: 9d03 ldr r5, [sp, #12] +10000bf4: 6804 ldr r4, [r0, #0] +10000bf6: 032d lsls r5, r5, #12 +10000bf8: ea45 4503 orr.w r5, r5, r3, lsl #16 +10000bfc: 4b1b ldr r3, [pc, #108] @ (10000c6c ) +10000bfe: 2c00 cmp r4, #0 +10000c00: fbb3 f3f1 udiv r3, r3, r1 +10000c04: fbb2 f6f3 udiv r6, r2, r3 +10000c08: db1f blt.n 10000c4a +10000c0a: 4a19 ldr r2, [pc, #100] @ (10000c70 ) +10000c0c: 4b19 ldr r3, [pc, #100] @ (10000c74 ) +10000c0e: 4290 cmp r0, r2 +10000c10: bf14 ite ne +10000c12: f44f 4280 movne.w r2, #16384 @ 0x4000 +10000c16: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10000c1a: 4c17 ldr r4, [pc, #92] @ (10000c78 ) +10000c1c: 601a str r2, [r3, #0] +10000c1e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000c22: 601a str r2, [r3, #0] +10000c24: 68a3 ldr r3, [r4, #8] +10000c26: ea32 0303 bics.w r3, r2, r3 +10000c2a: d1fb bne.n 10000c24 +10000c2c: 2221 movs r2, #33 @ 0x21 +10000c2e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10000c32: 3304 adds r3, #4 +10000c34: 6001 str r1, [r0, #0] +10000c36: 6086 str r6, [r0, #8] +10000c38: 601a str r2, [r3, #0] +10000c3a: 6802 ldr r2, [r0, #0] +10000c3c: 2a00 cmp r2, #0 +10000c3e: dafc bge.n 10000c3a +10000c40: 2208 movs r2, #8 +10000c42: 60c5 str r5, [r0, #12] +10000c44: 601a str r2, [r3, #0] +10000c46: bc70 pop {r4, r5, r6} +10000c48: 4770 bx lr +10000c4a: 6803 ldr r3, [r0, #0] +10000c4c: f003 033f and.w r3, r3, #63 @ 0x3f +10000c50: 428b cmp r3, r1 +10000c52: d1da bne.n 10000c0a +10000c54: 6883 ldr r3, [r0, #8] +10000c56: f3c3 030b ubfx r3, r3, #0, #12 +10000c5a: 42b3 cmp r3, r6 +10000c5c: d1d5 bne.n 10000c0a +10000c5e: 68c3 ldr r3, [r0, #12] +10000c60: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10000c64: 42ab cmp r3, r5 +10000c66: d1d0 bne.n 10000c0a +10000c68: e7ed b.n 10000c46 +10000c6a: bf00 nop +10000c6c: 00b71b00 .word 0x00b71b00 +10000c70: 40058000 .word 0x40058000 +10000c74: 40022000 .word 0x40022000 +10000c78: 40020000 .word 0x40020000 + +10000c7c : +10000c7c: 2301 movs r3, #1 +10000c7e: eb00 0040 add.w r0, r0, r0, lsl #1 +10000c82: 0080 lsls r0, r0, #2 +10000c84: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000c88: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10000c8c: 6041 str r1, [r0, #4] +10000c8e: 6003 str r3, [r0, #0] +10000c90: 4770 bx lr +10000c92: bf00 nop + +10000c94 : +10000c94: 2300 movs r3, #0 +10000c96: 8adb ldrh r3, [r3, #22] +10000c98: 2200 movs r2, #0 +10000c9a: e842 f200 tt r2, r2 +10000c9e: 0252 lsls r2, r2, #9 +10000ca0: d401 bmi.n 10000ca6 +10000ca2: 2110 movs r1, #16 +10000ca4: 4718 bx r3 +10000ca6: 2104 movs r1, #4 +10000ca8: 4718 bx r3 +10000caa: bf00 nop + +10000cac : +10000cac: 4a03 ldr r2, [pc, #12] @ (10000cbc ) +10000cae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10000cb2: 2b00 cmp r3, #0 +10000cb4: d0fb beq.n 10000cae +10000cb6: f3bf 8f5f dmb sy +10000cba: 4770 bx lr +10000cbc: 400e0000 .word 0x400e0000 + +10000cc0 : +10000cc0: 2100 movs r1, #0 +10000cc2: 4b04 ldr r3, [pc, #16] @ (10000cd4 ) +10000cc4: 4a04 ldr r2, [pc, #16] @ (10000cd8 ) +10000cc6: f3bf 8f5f dmb sy +10000cca: f843 1b04 str.w r1, [r3], #4 +10000cce: 4293 cmp r3, r2 +10000cd0: d1f9 bne.n 10000cc6 +10000cd2: 4770 bx lr +10000cd4: 400e080c .word 0x400e080c +10000cd8: 400e082c .word 0x400e082c + +10000cdc : +10000cdc: b410 push {r4} +10000cde: f44f 708d mov.w r0, #282 @ 0x11a +10000ce2: f44f 642a mov.w r4, #2720 @ 0xaa0 +10000ce6: 4a06 ldr r2, [pc, #24] @ (10000d00 ) +10000ce8: 4b06 ldr r3, [pc, #24] @ (10000d04 ) +10000cea: 4907 ldr r1, [pc, #28] @ (10000d08 ) +10000cec: 6014 str r4, [r2, #0] +10000cee: 60d0 str r0, [r2, #12] +10000cf0: 6019 str r1, [r3, #0] +10000cf2: 6853 ldr r3, [r2, #4] +10000cf4: 2b00 cmp r3, #0 +10000cf6: dafc bge.n 10000cf2 +10000cf8: f85d 4b04 ldr.w r4, [sp], #4 +10000cfc: 4770 bx lr +10000cfe: bf00 nop +10000d00: 40048000 .word 0x40048000 +10000d04: 4004a000 .word 0x4004a000 +10000d08: 00fab000 .word 0x00fab000 + +10000d0c : +10000d0c: 4770 bx lr +10000d0e: bf00 nop + +10000d10 : +10000d10: b508 push {r3, lr} +10000d12: 4801 ldr r0, [pc, #4] @ (10000d18 ) +10000d14: f7ff fac0 bl 10000298 +10000d18: 100013dc .word 0x100013dc + +10000d1c : +10000d1c: b538 push {r3, r4, r5, lr} +10000d1e: 4c05 ldr r4, [pc, #20] @ (10000d34 ) +10000d20: 4d05 ldr r5, [pc, #20] @ (10000d38 ) +10000d22: 42ac cmp r4, r5 +10000d24: d204 bcs.n 10000d30 +10000d26: f854 3b04 ldr.w r3, [r4], #4 +10000d2a: 4798 blx r3 +10000d2c: 42ac cmp r4, r5 +10000d2e: d3fa bcc.n 10000d26 +10000d30: bd38 pop {r3, r4, r5, pc} +10000d32: bf00 nop +10000d34: 10001360 .word 0x10001360 +10000d38: 100013a0 .word 0x100013a0 + +10000d3c : +10000d3c: b410 push {r4} +10000d3e: 4807 ldr r0, [pc, #28] @ (10000d5c ) +10000d40: 4c07 ldr r4, [pc, #28] @ (10000d60 ) +10000d42: 4b08 ldr r3, [pc, #32] @ (10000d64 ) +10000d44: 4a08 ldr r2, [pc, #32] @ (10000d68 ) +10000d46: 4909 ldr r1, [pc, #36] @ (10000d6c ) +10000d48: 6004 str r4, [r0, #0] +10000d4a: 601a str r2, [r3, #0] +10000d4c: 688b ldr r3, [r1, #8] +10000d4e: ea32 0303 bics.w r3, r2, r3 +10000d52: d1fb bne.n 10000d4c +10000d54: f85d 4b04 ldr.w r4, [sp], #4 +10000d58: 4770 bx lr +10000d5a: bf00 nop +10000d5c: 40022000 .word 0x40022000 +10000d60: efef3b7f .word 0xefef3b7f +10000d64: 40023000 .word 0x40023000 +10000d68: 03f3fff6 .word 0x03f3fff6 +10000d6c: 40020000 .word 0x40020000 + +10000d70 : +10000d70: 4b04 ldr r3, [pc, #16] @ (10000d84 ) +10000d72: 6cdb ldr r3, [r3, #76] @ 0x4c +10000d74: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10000d78: d103 bne.n 10000d82 +10000d7a: f44f 2280 mov.w r2, #262144 @ 0x40000 +10000d7e: 4b02 ldr r3, [pc, #8] @ (10000d88 ) +10000d80: 64da str r2, [r3, #76] @ 0x4c +10000d82: 4770 bx lr +10000d84: 50110000 .word 0x50110000 +10000d88: 50112000 .word 0x50112000 + +10000d8c : +10000d8c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000d90: 4b04 ldr r3, [pc, #16] @ (10000da4 ) +10000d92: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10000d96: 430b orrs r3, r1 +10000d98: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10000d9c: ee10 0430 dcp_rcmp r0 +10000da0: 4770 bx lr +10000da2: bf00 nop +10000da4: 00300303 .word 0x00300303 + +10000da8 : +10000da8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10000dac: 4b04 ldr r3, [pc, #16] @ (10000dc0 ) +10000dae: 4a05 ldr r2, [pc, #20] @ (10000dc4 ) +10000db0: 6019 str r1, [r3, #0] +10000db2: 6893 ldr r3, [r2, #8] +10000db4: 43db mvns r3, r3 +10000db6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10000dba: d1fa bne.n 10000db2 +10000dbc: 4770 bx lr +10000dbe: bf00 nop +10000dc0: 40023000 .word 0x40023000 +10000dc4: 40020000 .word 0x40020000 + +10000dc8 : +10000dc8: b510 push {r4, lr} +10000dca: f245 2053 movw r0, #21075 @ 0x5253 +10000dce: f7ff ff61 bl 10000c94 +10000dd2: e8bd 4010 ldmia.w sp!, {r4, lr} +10000dd6: 4603 mov r3, r0 +10000dd8: 2004 movs r0, #4 +10000dda: 4718 bx r3 + +10000ddc : +10000ddc: b510 push {r4, lr} +10000dde: f245 2053 movw r0, #21075 @ 0x5253 +10000de2: f7ff ff57 bl 10000c94 +10000de6: e8bd 4010 ldmia.w sp!, {r4, lr} +10000dea: 4603 mov r3, r0 +10000dec: 2001 movs r0, #1 +10000dee: 4718 bx r3 + +10000df0 : +10000df0: f7ff baaa b.w 10000348 + +10000df4 : +10000df4: 4914 ldr r1, [pc, #80] @ (10000e48 ) +10000df6: 4b15 ldr r3, [pc, #84] @ (10000e4c ) +10000df8: b570 push {r4, r5, r6, lr} +10000dfa: 1a5c subs r4, r3, r1 +10000dfc: 10a6 asrs r6, r4, #2 +10000dfe: 2e44 cmp r6, #68 @ 0x44 +10000e00: 4632 mov r2, r6 +10000e02: bf28 it cs +10000e04: 2244 movcs r2, #68 @ 0x44 +10000e06: 4d12 ldr r5, [pc, #72] @ (10000e50 ) +10000e08: 0092 lsls r2, r2, #2 +10000e0a: 4628 mov r0, r5 +10000e0c: f000 f9fa bl 10001204 +10000e10: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10000e14: d813 bhi.n 10000e3e +10000e16: 4a0f ldr r2, [pc, #60] @ (10000e54 ) +10000e18: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10000e1c: d012 beq.n 10000e44 +10000e1e: 192b adds r3, r5, r4 +10000e20: 0841 lsrs r1, r0, #1 +10000e22: eb03 01c1 add.w r1, r3, r1, lsl #3 +10000e26: e9c3 2200 strd r2, r2, [r3] +10000e2a: 3308 adds r3, #8 +10000e2c: 428b cmp r3, r1 +10000e2e: d1fa bne.n 10000e26 +10000e30: 07c3 lsls r3, r0, #31 +10000e32: d504 bpl.n 10000e3e +10000e34: f020 0001 bic.w r0, r0, #1 +10000e38: 4430 add r0, r6 +10000e3a: f845 2020 str.w r2, [r5, r0, lsl #2] +10000e3e: 4b06 ldr r3, [pc, #24] @ (10000e58 ) +10000e40: 609d str r5, [r3, #8] +10000e42: bd70 pop {r4, r5, r6, pc} +10000e44: 2043 movs r0, #67 @ 0x43 +10000e46: e7f8 b.n 10000e3a +10000e48: 10000000 .word 0x10000000 +10000e4c: 10000110 .word 0x10000110 +10000e50: 20000000 .word 0x20000000 +10000e54: 10000111 .word 0x10000111 +10000e58: e000ed00 .word 0xe000ed00 + +10000e5c : +10000e5c: 2300 movs r3, #0 +10000e5e: b570 push {r4, r5, r6, lr} +10000e60: 4c2b ldr r4, [pc, #172] @ (10000f10 ) +10000e62: b082 sub sp, #8 +10000e64: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10000e68: f7ff ff38 bl 10000cdc +10000e6c: 2201 movs r2, #1 +10000e6e: 4b29 ldr r3, [pc, #164] @ (10000f14 ) +10000e70: 63da str r2, [r3, #60] @ 0x3c +10000e72: 6c63 ldr r3, [r4, #68] @ 0x44 +10000e74: 2b01 cmp r3, #1 +10000e76: d1fc bne.n 10000e72 +10000e78: 2103 movs r1, #3 +10000e7a: 4a26 ldr r2, [pc, #152] @ (10000f14 ) +10000e7c: 4b24 ldr r3, [pc, #144] @ (10000f10 ) +10000e7e: 6311 str r1, [r2, #48] @ 0x30 +10000e80: 6b9c ldr r4, [r3, #56] @ 0x38 +10000e82: 2c01 cmp r4, #1 +10000e84: d1fc bne.n 10000e80 +10000e86: 2602 movs r6, #2 +10000e88: 2505 movs r5, #5 +10000e8a: 4621 mov r1, r4 +10000e8c: 2305 movs r3, #5 +10000e8e: 4a22 ldr r2, [pc, #136] @ (10000f18 ) +10000e90: 4822 ldr r0, [pc, #136] @ (10000f1c ) +10000e92: 9600 str r6, [sp, #0] +10000e94: f7ff feac bl 10000bf0 +10000e98: 4621 mov r1, r4 +10000e9a: 462b mov r3, r5 +10000e9c: 4a20 ldr r2, [pc, #128] @ (10000f20 ) +10000e9e: 4821 ldr r0, [pc, #132] @ (10000f24 ) +10000ea0: 9500 str r5, [sp, #0] +10000ea2: f7ff fea5 bl 10000bf0 +10000ea6: 2200 movs r2, #0 +10000ea8: 2004 movs r0, #4 +10000eaa: 4631 mov r1, r6 +10000eac: 4b1e ldr r3, [pc, #120] @ (10000f28 ) +10000eae: f7ff fe31 bl 10000b14 +10000eb2: 4621 mov r1, r4 +10000eb4: 4628 mov r0, r5 +10000eb6: 2200 movs r2, #0 +10000eb8: 4b1c ldr r3, [pc, #112] @ (10000f2c ) +10000eba: f7ff fe2b bl 10000b14 +10000ebe: 2200 movs r2, #0 +10000ec0: 2008 movs r0, #8 +10000ec2: 4611 mov r1, r2 +10000ec4: 4b1a ldr r3, [pc, #104] @ (10000f30 ) +10000ec6: f7ff fe25 bl 10000b14 +10000eca: 2200 movs r2, #0 +10000ecc: 2009 movs r0, #9 +10000ece: 4611 mov r1, r2 +10000ed0: 4b17 ldr r3, [pc, #92] @ (10000f30 ) +10000ed2: f7ff fe1f bl 10000b14 +10000ed6: 2200 movs r2, #0 +10000ed8: 2006 movs r0, #6 +10000eda: 4611 mov r1, r2 +10000edc: 4b13 ldr r3, [pc, #76] @ (10000f2c ) +10000ede: f7ff fe19 bl 10000b14 +10000ee2: 2200 movs r2, #0 +10000ee4: 4b11 ldr r3, [pc, #68] @ (10000f2c ) +10000ee6: 2007 movs r0, #7 +10000ee8: 4611 mov r1, r2 +10000eea: f7ff fe13 bl 10000b14 +10000eee: 2004 movs r0, #4 +10000ef0: f7ff fe78 bl 10000be4 +10000ef4: 2400 movs r4, #0 +10000ef6: 4b0f ldr r3, [pc, #60] @ (10000f34 ) +10000ef8: fba3 3500 umull r3, r5, r3, r0 +10000efc: 0cad lsrs r5, r5, #18 +10000efe: b2e0 uxtb r0, r4 +10000f00: 4629 mov r1, r5 +10000f02: 3401 adds r4, #1 +10000f04: f7ff feba bl 10000c7c +10000f08: 2c06 cmp r4, #6 +10000f0a: d1f8 bne.n 10000efe +10000f0c: b002 add sp, #8 +10000f0e: bd70 pop {r4, r5, r6, pc} +10000f10: 40010000 .word 0x40010000 +10000f14: 40013000 .word 0x40013000 +10000f18: 59682f00 .word 0x59682f00 +10000f1c: 40050000 .word 0x40050000 +10000f20: 47868c00 .word 0x47868c00 +10000f24: 40058000 .word 0x40058000 +10000f28: 00b71b00 .word 0x00b71b00 +10000f2c: 08f0d180 .word 0x08f0d180 +10000f30: 02dc6c00 .word 0x02dc6c00 +10000f34: 431bde83 .word 0x431bde83 + +10000f38 <_out_char>: +10000f38: b900 cbnz r0, 10000f3c <_out_char+0x4> +10000f3a: 4770 bx lr +10000f3c: f000 b902 b.w 10001144 <__wrap_putchar> + +10000f40 : +10000f40: b510 push {r4, lr} +10000f42: 4b09 ldr r3, [pc, #36] @ (10000f68 ) +10000f44: b084 sub sp, #16 +10000f46: 681c ldr r4, [r3, #0] +10000f48: b14c cbz r4, 10000f5e +10000f4a: 4603 mov r3, r0 +10000f4c: 9100 str r1, [sp, #0] +10000f4e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10000f52: a903 add r1, sp, #12 +10000f54: 4805 ldr r0, [pc, #20] @ (10000f6c ) +10000f56: 47a0 blx r4 +10000f58: 2001 movs r0, #1 +10000f5a: b004 add sp, #16 +10000f5c: bd10 pop {r4, pc} +10000f5e: f000 f933 bl 100011c8 <__wrap_puts> +10000f62: 4620 mov r0, r4 +10000f64: b004 add sp, #16 +10000f66: bd10 pop {r4, pc} +10000f68: 20000424 .word 0x20000424 +10000f6c: 10000f39 .word 0x10000f39 + +10000f70 <_exit>: +10000f70: be00 bkpt 0x0000 +10000f72: e7fd b.n 10000f70 <_exit> + +10000f74 : +10000f74: b508 push {r3, lr} +10000f76: f7ff fffb bl 10000f70 <_exit> +10000f7a: bf00 nop + +10000f7c : +10000f7c: b538 push {r3, r4, r5, lr} +10000f7e: 4c06 ldr r4, [pc, #24] @ (10000f98 ) +10000f80: 4d06 ldr r5, [pc, #24] @ (10000f9c ) +10000f82: f7ff fecb bl 10000d1c +10000f86: 42ac cmp r4, r5 +10000f88: d204 bcs.n 10000f94 +10000f8a: f854 3b04 ldr.w r3, [r4], #4 +10000f8e: 4798 blx r3 +10000f90: 42ac cmp r4, r5 +10000f92: d3fa bcc.n 10000f8a +10000f94: bd38 pop {r3, r4, r5, pc} +10000f96: bf00 nop +10000f98: 100013a0 .word 0x100013a0 +10000f9c: 100013a4 .word 0x100013a4 + +10000fa0 : +10000fa0: 6803 ldr r3, [r0, #0] +10000fa2: 4608 mov r0, r1 +10000fa4: 4611 mov r1, r2 +10000fa6: 4718 bx r3 + +10000fa8 : +10000fa8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000fac: 4615 mov r5, r2 +10000fae: 7d42 ldrb r2, [r0, #21] +10000fb0: 4607 mov r7, r0 +10000fb2: 4688 mov r8, r1 +10000fb4: 2a00 cmp r2, #0 +10000fb6: d046 beq.n 10001046 +10000fb8: 2d00 cmp r5, #0 +10000fba: dd1d ble.n 10000ff8 +10000fbc: 780b ldrb r3, [r1, #0] +10000fbe: 2b0a cmp r3, #10 +10000fc0: d023 beq.n 1000100a +10000fc2: 2d01 cmp r5, #1 +10000fc4: f04f 0c00 mov.w ip, #0 +10000fc8: d018 beq.n 10000ffc +10000fca: 4646 mov r6, r8 +10000fcc: 2401 movs r4, #1 +10000fce: f816 2f01 ldrb.w r2, [r6, #1]! +10000fd2: 4621 mov r1, r4 +10000fd4: 2a0a cmp r2, #10 +10000fd6: f104 0401 add.w r4, r4, #1 +10000fda: d022 beq.n 10001022 +10000fdc: 42a5 cmp r5, r4 +10000fde: d1f6 bne.n 10000fce +10000fe0: 4565 cmp r5, ip +10000fe2: dc0b bgt.n 10000ffc +10000fe4: eb08 0305 add.w r3, r8, r5 +10000fe8: f813 3c01 ldrb.w r3, [r3, #-1] +10000fec: f1a3 030d sub.w r3, r3, #13 +10000ff0: fab3 f383 clz r3, r3 +10000ff4: 095b lsrs r3, r3, #5 +10000ff6: 753b strb r3, [r7, #20] +10000ff8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10000ffc: 683b ldr r3, [r7, #0] +10000ffe: eba5 010c sub.w r1, r5, ip +10001002: eb08 000c add.w r0, r8, ip +10001006: 4798 blx r3 +10001008: e7ec b.n 10000fe4 +1000100a: 7d03 ldrb r3, [r0, #20] +1000100c: 2b00 cmp r3, #0 +1000100e: d1d8 bne.n 10000fc2 +10001010: 6803 ldr r3, [r0, #0] +10001012: 2102 movs r1, #2 +10001014: 480f ldr r0, [pc, #60] @ (10001054 ) +10001016: 4798 blx r3 +10001018: 2d01 cmp r5, #1 +1000101a: d0e3 beq.n 10000fe4 +1000101c: f04f 0c01 mov.w ip, #1 +10001020: e7d3 b.n 10000fca +10001022: f816 3c01 ldrb.w r3, [r6, #-1] +10001026: 2b0d cmp r3, #13 +10001028: d0d8 beq.n 10000fdc +1000102a: 458c cmp ip, r1 +1000102c: eb08 000c add.w r0, r8, ip +10001030: eba1 010c sub.w r1, r1, ip +10001034: da01 bge.n 1000103a +10001036: 683b ldr r3, [r7, #0] +10001038: 4798 blx r3 +1000103a: 2102 movs r1, #2 +1000103c: 4805 ldr r0, [pc, #20] @ (10001054 ) +1000103e: 683b ldr r3, [r7, #0] +10001040: 4798 blx r3 +10001042: 46a4 mov ip, r4 +10001044: e7ca b.n 10000fdc +10001046: 4629 mov r1, r5 +10001048: 4640 mov r0, r8 +1000104a: 683b ldr r3, [r7, #0] +1000104c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001050: 4718 bx r3 +10001052: bf00 nop +10001054: 100014a4 .word 0x100014a4 + +10001058 : +10001058: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +1000105c: b082 sub sp, #8 +1000105e: 460d mov r5, r1 +10001060: 4691 mov r9, r2 +10001062: 461c mov r4, r3 +10001064: 4606 mov r6, r0 +10001066: f7ff fd4b bl 10000b00 +1000106a: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +1000106e: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001072: 4a2e ldr r2, [pc, #184] @ (1000112c ) +10001074: 1882 adds r2, r0, r2 +10001076: f141 0300 adc.w r3, r1, #0 +1000107a: 4594 cmp ip, r2 +1000107c: eb77 0103 sbcs.w r1, r7, r3 +10001080: bf3c itt cc +10001082: 4662 movcc r2, ip +10001084: 463b movcc r3, r7 +10001086: 482a ldr r0, [pc, #168] @ (10001130 ) +10001088: f000 f966 bl 10001358 <__mutex_try_enter_block_until_veneer> +1000108c: 1c6b adds r3, r5, #1 +1000108e: 4680 mov r8, r0 +10001090: d040 beq.n 10001114 +10001092: b30c cbz r4, 100010d8 +10001094: 4f27 ldr r7, [pc, #156] @ (10001134 ) +10001096: 4b28 ldr r3, [pc, #160] @ (10001138 ) +10001098: 681c ldr r4, [r3, #0] +1000109a: b1b4 cbz r4, 100010ca +1000109c: f1b9 0f00 cmp.w r9, #0 +100010a0: d11c bne.n 100010dc +100010a2: f8df 909c ldr.w r9, [pc, #156] @ 10001140 +100010a6: e001 b.n 100010ac +100010a8: 6924 ldr r4, [r4, #16] +100010aa: b174 cbz r4, 100010ca +100010ac: 6823 ldr r3, [r4, #0] +100010ae: 2b00 cmp r3, #0 +100010b0: d0fa beq.n 100010a8 +100010b2: f8d9 3000 ldr.w r3, [r9] +100010b6: b10b cbz r3, 100010bc +100010b8: 429c cmp r4, r3 +100010ba: d1f5 bne.n 100010a8 +100010bc: 4620 mov r0, r4 +100010be: 462a mov r2, r5 +100010c0: 4631 mov r1, r6 +100010c2: 47b8 blx r7 +100010c4: 6924 ldr r4, [r4, #16] +100010c6: 2c00 cmp r4, #0 +100010c8: d1f0 bne.n 100010ac +100010ca: f1b8 0f00 cmp.w r8, #0 +100010ce: d126 bne.n 1000111e +100010d0: 4628 mov r0, r5 +100010d2: b002 add sp, #8 +100010d4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100010d8: 4f18 ldr r7, [pc, #96] @ (1000113c ) +100010da: e7dc b.n 10001096 +100010dc: f04f 0a0a mov.w sl, #10 +100010e0: f8df 905c ldr.w r9, [pc, #92] @ 10001140 +100010e4: e002 b.n 100010ec +100010e6: 6924 ldr r4, [r4, #16] +100010e8: 2c00 cmp r4, #0 +100010ea: d0ee beq.n 100010ca +100010ec: 6823 ldr r3, [r4, #0] +100010ee: 2b00 cmp r3, #0 +100010f0: d0f9 beq.n 100010e6 +100010f2: f8d9 3000 ldr.w r3, [r9] +100010f6: b10b cbz r3, 100010fc +100010f8: 42a3 cmp r3, r4 +100010fa: d1f4 bne.n 100010e6 +100010fc: 462a mov r2, r5 +100010fe: 4631 mov r1, r6 +10001100: 4620 mov r0, r4 +10001102: 47b8 blx r7 +10001104: 2201 movs r2, #1 +10001106: 4620 mov r0, r4 +10001108: f10d 0107 add.w r1, sp, #7 +1000110c: f88d a007 strb.w sl, [sp, #7] +10001110: 47b8 blx r7 +10001112: e7e8 b.n 100010e6 +10001114: 4630 mov r0, r6 +10001116: f000 f8eb bl 100012f0 +1000111a: 4605 mov r5, r0 +1000111c: e7b9 b.n 10001092 +1000111e: 4804 ldr r0, [pc, #16] @ (10001130 ) +10001120: f000 f916 bl 10001350 <__mutex_exit_veneer> +10001124: 4628 mov r0, r5 +10001126: b002 add sp, #8 +10001128: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000112c: 000f4240 .word 0x000f4240 +10001130: 20000244 .word 0x20000244 +10001134: 10000fa9 .word 0x10000fa9 +10001138: 2000041c .word 0x2000041c +1000113c: 10000fa1 .word 0x10000fa1 +10001140: 20000420 .word 0x20000420 + +10001144 <__wrap_putchar>: +10001144: b5f0 push {r4, r5, r6, r7, lr} +10001146: b083 sub sp, #12 +10001148: 4606 mov r6, r0 +1000114a: f88d 0007 strb.w r0, [sp, #7] +1000114e: f7ff fcd7 bl 10000b00 +10001152: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10001156: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000115a: 4a17 ldr r2, [pc, #92] @ (100011b8 <__wrap_putchar+0x74>) +1000115c: 1882 adds r2, r0, r2 +1000115e: f141 0300 adc.w r3, r1, #0 +10001162: 4295 cmp r5, r2 +10001164: eb74 0103 sbcs.w r1, r4, r3 +10001168: bf3c itt cc +1000116a: 4623 movcc r3, r4 +1000116c: 462a movcc r2, r5 +1000116e: 4813 ldr r0, [pc, #76] @ (100011bc <__wrap_putchar+0x78>) +10001170: f000 f8f2 bl 10001358 <__mutex_try_enter_block_until_veneer> +10001174: 4b12 ldr r3, [pc, #72] @ (100011c0 <__wrap_putchar+0x7c>) +10001176: 4607 mov r7, r0 +10001178: 681c ldr r4, [r3, #0] +1000117a: b19c cbz r4, 100011a4 <__wrap_putchar+0x60> +1000117c: 4d11 ldr r5, [pc, #68] @ (100011c4 <__wrap_putchar+0x80>) +1000117e: e001 b.n 10001184 <__wrap_putchar+0x40> +10001180: 6924 ldr r4, [r4, #16] +10001182: b17c cbz r4, 100011a4 <__wrap_putchar+0x60> +10001184: 6823 ldr r3, [r4, #0] +10001186: 2b00 cmp r3, #0 +10001188: d0fa beq.n 10001180 <__wrap_putchar+0x3c> +1000118a: 682b ldr r3, [r5, #0] +1000118c: b10b cbz r3, 10001192 <__wrap_putchar+0x4e> +1000118e: 429c cmp r4, r3 +10001190: d1f6 bne.n 10001180 <__wrap_putchar+0x3c> +10001192: 4620 mov r0, r4 +10001194: 2201 movs r2, #1 +10001196: f10d 0107 add.w r1, sp, #7 +1000119a: f7ff ff05 bl 10000fa8 +1000119e: 6924 ldr r4, [r4, #16] +100011a0: 2c00 cmp r4, #0 +100011a2: d1ef bne.n 10001184 <__wrap_putchar+0x40> +100011a4: b917 cbnz r7, 100011ac <__wrap_putchar+0x68> +100011a6: 4630 mov r0, r6 +100011a8: b003 add sp, #12 +100011aa: bdf0 pop {r4, r5, r6, r7, pc} +100011ac: 4803 ldr r0, [pc, #12] @ (100011bc <__wrap_putchar+0x78>) +100011ae: f000 f8cf bl 10001350 <__mutex_exit_veneer> +100011b2: 4630 mov r0, r6 +100011b4: b003 add sp, #12 +100011b6: bdf0 pop {r4, r5, r6, r7, pc} +100011b8: 000f4240 .word 0x000f4240 +100011bc: 20000244 .word 0x20000244 +100011c0: 2000041c .word 0x2000041c +100011c4: 20000420 .word 0x20000420 + +100011c8 <__wrap_puts>: +100011c8: b538 push {r3, r4, r5, lr} +100011ca: 4604 mov r4, r0 +100011cc: f000 f890 bl 100012f0 +100011d0: 2301 movs r3, #1 +100011d2: 4605 mov r5, r0 +100011d4: 461a mov r2, r3 +100011d6: 4620 mov r0, r4 +100011d8: 4629 mov r1, r5 +100011da: f7ff ff3d bl 10001058 +100011de: 4b08 ldr r3, [pc, #32] @ (10001200 <__wrap_puts+0x38>) +100011e0: 681c ldr r4, [r3, #0] +100011e2: b12c cbz r4, 100011f0 <__wrap_puts+0x28> +100011e4: 6863 ldr r3, [r4, #4] +100011e6: b12b cbz r3, 100011f4 <__wrap_puts+0x2c> +100011e8: 4798 blx r3 +100011ea: 6924 ldr r4, [r4, #16] +100011ec: 2c00 cmp r4, #0 +100011ee: d1f9 bne.n 100011e4 <__wrap_puts+0x1c> +100011f0: 4628 mov r0, r5 +100011f2: bd38 pop {r3, r4, r5, pc} +100011f4: 6924 ldr r4, [r4, #16] +100011f6: 2c00 cmp r4, #0 +100011f8: d1f4 bne.n 100011e4 <__wrap_puts+0x1c> +100011fa: 4628 mov r0, r5 +100011fc: bd38 pop {r3, r4, r5, pc} +100011fe: bf00 nop +10001200: 2000041c .word 0x2000041c + +10001204 : +10001204: 4684 mov ip, r0 +10001206: ea41 0300 orr.w r3, r1, r0 +1000120a: f013 0303 ands.w r3, r3, #3 +1000120e: d149 bne.n 100012a4 +10001210: 3a40 subs r2, #64 @ 0x40 +10001212: d323 bcc.n 1000125c +10001214: 680b ldr r3, [r1, #0] +10001216: 6003 str r3, [r0, #0] +10001218: 684b ldr r3, [r1, #4] +1000121a: 6043 str r3, [r0, #4] +1000121c: 688b ldr r3, [r1, #8] +1000121e: 6083 str r3, [r0, #8] +10001220: 68cb ldr r3, [r1, #12] +10001222: 60c3 str r3, [r0, #12] +10001224: 690b ldr r3, [r1, #16] +10001226: 6103 str r3, [r0, #16] +10001228: 694b ldr r3, [r1, #20] +1000122a: 6143 str r3, [r0, #20] +1000122c: 698b ldr r3, [r1, #24] +1000122e: 6183 str r3, [r0, #24] +10001230: 69cb ldr r3, [r1, #28] +10001232: 61c3 str r3, [r0, #28] +10001234: 6a0b ldr r3, [r1, #32] +10001236: 6203 str r3, [r0, #32] +10001238: 6a4b ldr r3, [r1, #36] @ 0x24 +1000123a: 6243 str r3, [r0, #36] @ 0x24 +1000123c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000123e: 6283 str r3, [r0, #40] @ 0x28 +10001240: 6acb ldr r3, [r1, #44] @ 0x2c +10001242: 62c3 str r3, [r0, #44] @ 0x2c +10001244: 6b0b ldr r3, [r1, #48] @ 0x30 +10001246: 6303 str r3, [r0, #48] @ 0x30 +10001248: 6b4b ldr r3, [r1, #52] @ 0x34 +1000124a: 6343 str r3, [r0, #52] @ 0x34 +1000124c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000124e: 6383 str r3, [r0, #56] @ 0x38 +10001250: 6bcb ldr r3, [r1, #60] @ 0x3c +10001252: 63c3 str r3, [r0, #60] @ 0x3c +10001254: 3040 adds r0, #64 @ 0x40 +10001256: 3140 adds r1, #64 @ 0x40 +10001258: 3a40 subs r2, #64 @ 0x40 +1000125a: d2db bcs.n 10001214 +1000125c: 3230 adds r2, #48 @ 0x30 +1000125e: d30b bcc.n 10001278 +10001260: 680b ldr r3, [r1, #0] +10001262: 6003 str r3, [r0, #0] +10001264: 684b ldr r3, [r1, #4] +10001266: 6043 str r3, [r0, #4] +10001268: 688b ldr r3, [r1, #8] +1000126a: 6083 str r3, [r0, #8] +1000126c: 68cb ldr r3, [r1, #12] +1000126e: 60c3 str r3, [r0, #12] +10001270: 3010 adds r0, #16 +10001272: 3110 adds r1, #16 +10001274: 3a10 subs r2, #16 +10001276: d2f3 bcs.n 10001260 +10001278: 320c adds r2, #12 +1000127a: d305 bcc.n 10001288 +1000127c: f851 3b04 ldr.w r3, [r1], #4 +10001280: f840 3b04 str.w r3, [r0], #4 +10001284: 3a04 subs r2, #4 +10001286: d2f9 bcs.n 1000127c +10001288: 3204 adds r2, #4 +1000128a: d008 beq.n 1000129e +1000128c: 07d2 lsls r2, r2, #31 +1000128e: bf1c itt ne +10001290: f811 3b01 ldrbne.w r3, [r1], #1 +10001294: f800 3b01 strbne.w r3, [r0], #1 +10001298: d301 bcc.n 1000129e +1000129a: 880b ldrh r3, [r1, #0] +1000129c: 8003 strh r3, [r0, #0] +1000129e: 4660 mov r0, ip +100012a0: 4770 bx lr +100012a2: bf00 nop +100012a4: 2a08 cmp r2, #8 +100012a6: d313 bcc.n 100012d0 +100012a8: 078b lsls r3, r1, #30 +100012aa: d0b1 beq.n 10001210 +100012ac: f010 0303 ands.w r3, r0, #3 +100012b0: d0ae beq.n 10001210 +100012b2: f1c3 0304 rsb r3, r3, #4 +100012b6: 1ad2 subs r2, r2, r3 +100012b8: 07db lsls r3, r3, #31 +100012ba: bf1c itt ne +100012bc: f811 3b01 ldrbne.w r3, [r1], #1 +100012c0: f800 3b01 strbne.w r3, [r0], #1 +100012c4: d3a4 bcc.n 10001210 +100012c6: f831 3b02 ldrh.w r3, [r1], #2 +100012ca: f820 3b02 strh.w r3, [r0], #2 +100012ce: e79f b.n 10001210 +100012d0: 3a04 subs r2, #4 +100012d2: d3d9 bcc.n 10001288 +100012d4: 3a01 subs r2, #1 +100012d6: f811 3b01 ldrb.w r3, [r1], #1 +100012da: f800 3b01 strb.w r3, [r0], #1 +100012de: d2f9 bcs.n 100012d4 +100012e0: 780b ldrb r3, [r1, #0] +100012e2: 7003 strb r3, [r0, #0] +100012e4: 784b ldrb r3, [r1, #1] +100012e6: 7043 strb r3, [r0, #1] +100012e8: 788b ldrb r3, [r1, #2] +100012ea: 7083 strb r3, [r0, #2] +100012ec: 4660 mov r0, ip +100012ee: 4770 bx lr + +100012f0 : +100012f0: f020 0103 bic.w r1, r0, #3 +100012f4: f010 0003 ands.w r0, r0, #3 +100012f8: f1c0 0000 rsb r0, r0, #0 +100012fc: f851 3b04 ldr.w r3, [r1], #4 +10001300: f100 0c04 add.w ip, r0, #4 +10001304: ea4f 0ccc mov.w ip, ip, lsl #3 +10001308: f06f 0200 mvn.w r2, #0 +1000130c: bf1c itt ne +1000130e: fa22 f20c lsrne.w r2, r2, ip +10001312: 4313 orrne r3, r2 +10001314: f04f 0c01 mov.w ip, #1 +10001318: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000131c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001320: eba3 020c sub.w r2, r3, ip +10001324: ea22 0203 bic.w r2, r2, r3 +10001328: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000132c: bf04 itt eq +1000132e: f851 3b04 ldreq.w r3, [r1], #4 +10001332: 3004 addeq r0, #4 +10001334: d0f4 beq.n 10001320 +10001336: f1c2 0100 rsb r1, r2, #0 +1000133a: ea02 0201 and.w r2, r2, r1 +1000133e: fab2 f282 clz r2, r2 +10001342: f1c2 021f rsb r2, r2, #31 +10001346: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000134a: 4770 bx lr + +1000134c <_fini>: +1000134c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000134e: bf00 nop + +10001350 <__mutex_exit_veneer>: +10001350: f85f f000 ldr.w pc, [pc] @ 10001354 <__mutex_exit_veneer+0x4> +10001354: 200001e5 .word 0x200001e5 + +10001358 <__mutex_try_enter_block_until_veneer>: +10001358: f85f f000 ldr.w pc, [pc] @ 1000135c <__mutex_try_enter_block_until_veneer+0x4> +1000135c: 2000017d .word 0x2000017d + +10001360 <__pre_init_runtime_init_bootrom_reset>: +10001360: 10000dc9 .... + +10001364 <__pre_init_runtime_init_early_resets>: +10001364: 10000d3d =... + +10001368 <__pre_init_runtime_init_usb_power_down>: +10001368: 10000d71 q... + +1000136c <__pre_init_runtime_init_clocks>: +1000136c: 10000e5d ]... + +10001370 <__pre_init_runtime_init_post_clock_resets>: +10001370: 10000da9 .... + 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section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 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a/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.uf2 b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.uf2 new file mode 100644 index 0000000..8a0eec1 Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables-e/build/0x0008_uninitialized-variables-e.uf2 differ diff --git a/WEEK04/0x0008_uninitialized-variables-e/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables-e/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables-e/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables-e/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables-e/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/0x0008_uninitialized-variables/.gitignore b/WEEK04/0x0008_uninitialized-variables/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/c_cpp_properties.json b/WEEK04/0x0008_uninitialized-variables/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/cmake-kits.json b/WEEK04/0x0008_uninitialized-variables/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/extensions.json b/WEEK04/0x0008_uninitialized-variables/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/launch.json b/WEEK04/0x0008_uninitialized-variables/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/settings.json b/WEEK04/0x0008_uninitialized-variables/.vscode/settings.json new file mode 100644 index 0000000..4e5d7b6 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/settings.json @@ -0,0 +1,45 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja", + "files.associations": { + "addressmap.h": "c", + "resets.h": "c", + "pads_bank0.h": "c" + } +} diff --git a/WEEK04/0x0008_uninitialized-variables/.vscode/tasks.json b/WEEK04/0x0008_uninitialized-variables/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK04/0x0008_uninitialized-variables/0x0008_uninitialized-variables.c b/WEEK04/0x0008_uninitialized-variables/0x0008_uninitialized-variables.c new file mode 100644 index 0000000..0c94677 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/0x0008_uninitialized-variables.c @@ -0,0 +1,23 @@ +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) { + uint8_t age; + + stdio_init_all(); + + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + + while (true) { + printf("age: %d\r\n", age); + + gpio_put(LED_PIN, 1); + sleep_ms(500); + + gpio_put(LED_PIN, 0); + sleep_ms(500); + } +} diff --git a/WEEK04/0x0008_uninitialized-variables/CMakeLists.txt b/WEEK04/0x0008_uninitialized-variables/CMakeLists.txt new file mode 100644 index 0000000..c2ac591 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0008_uninitialized-variables C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0008_uninitialized-variables 0x0008_uninitialized-variables.c ) + +pico_set_program_name(0x0008_uninitialized-variables "0x0008_uninitialized-variables") +pico_set_program_version(0x0008_uninitialized-variables "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0008_uninitialized-variables 1) +pico_enable_stdio_usb(0x0008_uninitialized-variables 0) + +# Add the standard library to the build +target_link_libraries(0x0008_uninitialized-variables + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0008_uninitialized-variables PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0008_uninitialized-variables) + diff --git a/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables-h.bin b/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables-h.bin new file mode 100644 index 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0000000..5db7384 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.dis @@ -0,0 +1,5876 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00003614 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001b8 10003618 10003618 00004618 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100037d0 100037d0 000047d0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 100037d8 100037d8 000047d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005d34 2**0 + CONTENTS + 6 .data 0000051c 20000110 10003804 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005d34 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003d20 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003d20 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005d34 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005d34 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003d20 10003d20 00005d20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005d34 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005d68 2**0 + CONTENTS, READONLY + 17 .debug_info 0002098c 00000000 00000000 00005dad 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 0000563c 00000000 00000000 00026739 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0001006d 00000000 00000000 0002bd75 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000be8 00000000 00000000 0003bde8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 0000303d 00000000 00000000 0003c9d0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00015b5b 00000000 00000000 0003fa0d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005738 00000000 00000000 00055568 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f3c 00000000 00000000 0005aca0 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c5 00000000 00000000 0005cbdc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100037d8 .word 0x100037d8 +1000012c: 10003804 .word 0x10003804 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003be8 .word 0x00003be8 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10003804 .word 0x10003804 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003d20 .word 0x10003d20 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003d20 .word 0x10003d20 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002e7d .word 0x10002e7d +100001dc: 10000235 .word 0x10000235 +100001e0: 10002e75 .word 0x10002e75 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 10003614 .word 0x10003614 + +10000234
: +10000234: b538 push {r3, r4, r5, lr} +10000236: f002 ff49 bl 100030cc +1000023a: 2010 movs r0, #16 +1000023c: f000 f83a bl 100002b4 +10000240: f04f 0501 mov.w r5, #1 +10000244: 2310 movs r3, #16 +10000246: ec45 3044 gpioc_bit_oe_put r3, r5 +1000024a: 2100 movs r1, #0 +1000024c: 4809 ldr r0, [pc, #36] @ (10000274 ) +1000024e: f003 f805 bl 1000325c <__wrap_printf> +10000252: 2410 movs r4, #16 +10000254: ec45 4040 gpioc_bit_out_put r4, r5 +10000258: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000025c: f000 fd58 bl 10000d10 +10000260: f04f 0300 mov.w r3, #0 +10000264: ec43 4040 gpioc_bit_out_put r4, r3 +10000268: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000026c: f000 fd50 bl 10000d10 +10000270: e7eb b.n 1000024a +10000272: bf00 nop +10000274: 10003618 .word 0x10003618 + +10000278 : +10000278: b410 push {r4} +1000027a: f44f 7480 mov.w r4, #256 @ 0x100 +1000027e: 4b0c ldr r3, [pc, #48] @ (100002b0 ) +10000280: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000284: eb03 0380 add.w r3, r3, r0, lsl #2 +10000288: 00c0 lsls r0, r0, #3 +1000028a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000028e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000292: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000296: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000029a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000029e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +100002a2: f8cc 2000 str.w r2, [ip] +100002a6: 6041 str r1, [r0, #4] +100002a8: 601c str r4, [r3, #0] +100002aa: f85d 4b04 ldr.w r4, [sp], #4 +100002ae: 4770 bx lr +100002b0: 40038004 .word 0x40038004 + +100002b4 : +100002b4: b430 push {r4, r5} +100002b6: f04f 0300 mov.w r3, #0 +100002ba: ec43 0044 gpioc_bit_oe_put r0, r3 +100002be: ec43 0040 gpioc_bit_out_put r0, r3 +100002c2: 2505 movs r5, #5 +100002c4: f44f 7480 mov.w r4, #256 @ 0x100 +100002c8: 4b0b ldr r3, [pc, #44] @ (100002f8 ) +100002ca: 00c2 lsls r2, r0, #3 +100002cc: f853 1020 ldr.w r1, [r3, r0, lsl #2] +100002d0: eb03 0080 add.w r0, r3, r0, lsl #2 +100002d4: f081 0140 eor.w r1, r1, #64 @ 0x40 +100002d8: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +100002dc: f503 3320 add.w r3, r3, #163840 @ 0x28000 +100002e0: f001 02c0 and.w r2, r1, #192 @ 0xc0 +100002e4: f500 5180 add.w r1, r0, #4096 @ 0x1000 +100002e8: f500 5040 add.w r0, r0, #12288 @ 0x3000 +100002ec: 600a str r2, [r1, #0] +100002ee: 605d str r5, [r3, #4] +100002f0: 6004 str r4, [r0, #0] +100002f2: bc30 pop {r4, r5} +100002f4: 4770 bx lr +100002f6: bf00 nop +100002f8: 40038004 .word 0x40038004 + +100002fc : +100002fc: b40f push {r0, r1, r2, r3} +100002fe: b500 push {lr} +10000300: b083 sub sp, #12 +10000302: 9c04 ldr r4, [sp, #16] +10000304: 4807 ldr r0, [pc, #28] @ (10000324 ) +10000306: f002 ff29 bl 1000315c <__wrap_puts> +1000030a: b13c cbz r4, 1000031c +1000030c: a905 add r1, sp, #20 +1000030e: 4620 mov r0, r4 +10000310: 9101 str r1, [sp, #4] +10000312: f002 fd95 bl 10002e40 +10000316: 4804 ldr r0, [pc, #16] @ (10000328 ) +10000318: f002 ff20 bl 1000315c <__wrap_puts> +1000031c: 2001 movs r0, #1 +1000031e: f002 fda7 bl 10002e70 <_exit> +10000322: bf00 nop +10000324: 10003624 .word 0x10003624 +10000328: 10003620 .word 0x10003620 + +1000032c : +1000032c: b570 push {r4, r5, r6, lr} +1000032e: 4686 mov lr, r0 +10000330: f3ef 8510 mrs r5, PRIMASK +10000334: b672 cpsid i +10000336: 4c12 ldr r4, [pc, #72] @ (10000380 ) +10000338: e8d4 6fcf ldaexb r6, [r4] +1000033c: 2001 movs r0, #1 +1000033e: 2e00 cmp r6, #0 +10000340: d1fa bne.n 10000338 +10000342: e8c4 0f46 strexb r6, r0, [r4] +10000346: 2e00 cmp r6, #0 +10000348: d1f6 bne.n 10000338 +1000034a: f3bf 8f5f dmb sy +1000034e: f04f 0c01 mov.w ip, #1 +10000352: 08c8 lsrs r0, r1, #3 +10000354: f001 0307 and.w r3, r1, #7 +10000358: fa0c f303 lsl.w r3, ip, r3 +1000035c: f81e c000 ldrb.w ip, [lr, r0] +10000360: ea1c 0603 ands.w r6, ip, r3 +10000364: d108 bne.n 10000378 +10000366: ea4c 0c03 orr.w ip, ip, r3 +1000036a: f80e c000 strb.w ip, [lr, r0] +1000036e: e8c4 6f8f stlb r6, [r4] +10000372: f385 8810 msr PRIMASK, r5 +10000376: bd70 pop {r4, r5, r6, pc} +10000378: 4610 mov r0, r2 +1000037a: f7ff ffbf bl 100002fc +1000037e: bf00 nop +10000380: 200007bb .word 0x200007bb + +10000384 : +10000384: 4a04 ldr r2, [pc, #16] @ (10000398 ) +10000386: 7810 ldrb r0, [r2, #0] +10000388: 1c43 adds r3, r0, #1 +1000038a: b2db uxtb r3, r3 +1000038c: 2b18 cmp r3, #24 +1000038e: bf28 it cs +10000390: 2310 movcs r3, #16 +10000392: 7013 strb r3, [r2, #0] +10000394: 4770 bx lr +10000396: bf00 nop +10000398: 200005a8 .word 0x200005a8 + +1000039c : +1000039c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100003a0: 6893 ldr r3, [r2, #8] +100003a2: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100003a6: 6093 str r3, [r2, #8] +100003a8: 4770 bx lr +100003aa: bf00 nop + +100003ac : +100003ac: 2100 movs r1, #0 +100003ae: 4b04 ldr r3, [pc, #16] @ (100003c0 ) +100003b0: f103 0220 add.w r2, r3, #32 +100003b4: e8c3 1f8f stlb r1, [r3] +100003b8: 3301 adds r3, #1 +100003ba: 4293 cmp r3, r2 +100003bc: d1fa bne.n 100003b4 +100003be: 4770 bx lr +100003c0: 200007b0 .word 0x200007b0 + +100003c4 : +100003c4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100003c8: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100003cc: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100003d0: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100003d4: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100003d8: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100003dc: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100003e0: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100003e4: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +100003e8: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100003ec: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100003f0: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100003f4: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100003f8: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100003fc: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000400: b662 cpsie i +10000402: 4770 bx lr + +10000404 : +10000404: 2301 movs r3, #1 +10000406: f000 021f and.w r2, r0, #31 +1000040a: 4093 lsls r3, r2 +1000040c: 0940 lsrs r0, r0, #5 +1000040e: b141 cbz r1, 10000422 +10000410: 0080 lsls r0, r0, #2 +10000412: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000416: f500 4061 add.w r0, r0, #57600 @ 0xe100 +1000041a: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000041e: 6003 str r3, [r0, #0] +10000420: 4770 bx lr +10000422: 4a02 ldr r2, [pc, #8] @ (1000042c ) +10000424: 3020 adds r0, #32 +10000426: f842 3020 str.w r3, [r2, r0, lsl #2] +1000042a: 4770 bx lr +1000042c: e000e100 .word 0xe000e100 + +10000430 : +10000430: b5f8 push {r3, r4, r5, r6, r7, lr} +10000432: 460d mov r5, r1 +10000434: f3ef 8710 mrs r7, PRIMASK +10000438: b672 cpsid i +1000043a: 4e12 ldr r6, [pc, #72] @ (10000484 ) +1000043c: e8d6 2fcf ldaexb r2, [r6] +10000440: 2301 movs r3, #1 +10000442: 2a00 cmp r2, #0 +10000444: d1fa bne.n 1000043c +10000446: e8c6 3f42 strexb r2, r3, [r6] +1000044a: 2a00 cmp r2, #0 +1000044c: d1f6 bne.n 1000043c +1000044e: f3bf 8f5f dmb sy +10000452: 4b0d ldr r3, [pc, #52] @ (10000488 ) +10000454: f100 0410 add.w r4, r0, #16 +10000458: 689b ldr r3, [r3, #8] +1000045a: 4a0c ldr r2, [pc, #48] @ (1000048c ) +1000045c: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000460: 4293 cmp r3, r2 +10000462: d003 beq.n 1000046c +10000464: 4299 cmp r1, r3 +10000466: d001 beq.n 1000046c +10000468: f000 ff0e bl 10001288 +1000046c: 4b06 ldr r3, [pc, #24] @ (10000488 ) +1000046e: 689b ldr r3, [r3, #8] +10000470: f843 5024 str.w r5, [r3, r4, lsl #2] +10000474: f3bf 8f5f dmb sy +10000478: 2300 movs r3, #0 +1000047a: e8c6 3f8f stlb r3, [r6] +1000047e: f387 8810 msr PRIMASK, r7 +10000482: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000484: 200007b9 .word 0x200007b9 +10000488: e000ed00 .word 0xe000ed00 +1000048c: 10000111 .word 0x10000111 + +10000490 : +10000490: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000494: b083 sub sp, #12 +10000496: f3ef 8a10 mrs sl, PRIMASK +1000049a: b672 cpsid i +1000049c: 4e71 ldr r6, [pc, #452] @ (10000664 ) +1000049e: e8d6 2fcf ldaexb r2, [r6] +100004a2: 2301 movs r3, #1 +100004a4: 2a00 cmp r2, #0 +100004a6: d1fa bne.n 1000049e +100004a8: e8c6 3f42 strexb r2, r3, [r6] +100004ac: 2a00 cmp r2, #0 +100004ae: d1f6 bne.n 1000049e +100004b0: f3bf 8f5f dmb sy +100004b4: 4b6c ldr r3, [pc, #432] @ (10000668 ) +100004b6: f100 0810 add.w r8, r0, #16 +100004ba: 689b ldr r3, [r3, #8] +100004bc: 4a6b ldr r2, [pc, #428] @ (1000066c ) +100004be: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100004c2: 4295 cmp r5, r2 +100004c4: d045 beq.n 10000552 +100004c6: 428d cmp r5, r1 +100004c8: 460c mov r4, r1 +100004ca: d050 beq.n 1000056e +100004cc: 4f68 ldr r7, [pc, #416] @ (10000670 ) +100004ce: 1beb subs r3, r5, r7 +100004d0: 2b2f cmp r3, #47 @ 0x2f +100004d2: d83e bhi.n 10000552 +100004d4: 2101 movs r1, #1 +100004d6: ea4f 1950 mov.w r9, r0, lsr #5 +100004da: ea4f 0989 mov.w r9, r9, lsl #2 +100004de: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100004e2: f509 4961 add.w r9, r9, #57600 @ 0xe100 +100004e6: f000 031f and.w r3, r0, #31 +100004ea: fa01 f003 lsl.w r0, r1, r3 +100004ee: f8d9 3000 ldr.w r3, [r9] +100004f2: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100004f6: ea00 0b03 and.w fp, r0, r3 +100004fa: f3bf 8f5f dmb sy +100004fe: f3ef 8105 mrs r1, IPSR +10000502: b2c9 uxtb r1, r1 +10000504: 2900 cmp r1, #0 +10000506: d034 beq.n 10000572 +10000508: 4588 cmp r8, r1 +1000050a: d005 beq.n 10000518 +1000050c: e9cd 1000 strd r1, r0, [sp] +10000510: f000 feba bl 10001288 +10000514: e9dd 1000 ldrd r1, r0, [sp] +10000518: f025 0e01 bic.w lr, r5, #1 +1000051c: f8de c008 ldr.w ip, [lr, #8] +10000520: 4564 cmp r4, ip +10000522: d105 bne.n 10000530 +10000524: e089 b.n 1000063a +10000526: f8d3 c008 ldr.w ip, [r3, #8] +1000052a: 4564 cmp r4, ip +1000052c: d031 beq.n 10000592 +1000052e: 469e mov lr, r3 +10000530: f99e 2006 ldrsb.w r2, [lr, #6] +10000534: eb02 0342 add.w r3, r2, r2, lsl #1 +10000538: 2a00 cmp r2, #0 +1000053a: eb07 0383 add.w r3, r7, r3, lsl #2 +1000053e: daf2 bge.n 10000526 +10000540: 4564 cmp r4, ip +10000542: d061 beq.n 10000608 +10000544: f1bb 0f00 cmp.w fp, #0 +10000548: d020 beq.n 1000058c +1000054a: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +1000054e: f8c9 0000 str.w r0, [r9] +10000552: 4b45 ldr r3, [pc, #276] @ (10000668 ) +10000554: 689b ldr r3, [r3, #8] +10000556: f843 5028 str.w r5, [r3, r8, lsl #2] +1000055a: f3bf 8f5f dmb sy +1000055e: 2300 movs r3, #0 +10000560: e8c6 3f8f stlb r3, [r6] +10000564: f38a 8810 msr PRIMASK, sl +10000568: b003 add sp, #12 +1000056a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000056e: 4615 mov r5, r2 +10000570: e7ef b.n 10000552 +10000572: f025 0e01 bic.w lr, r5, #1 +10000576: f8de c008 ldr.w ip, [lr, #8] +1000057a: 4564 cmp r4, ip +1000057c: d1d8 bne.n 10000530 +1000057e: f99e 4006 ldrsb.w r4, [lr, #6] +10000582: 4673 mov r3, lr +10000584: 2c00 cmp r4, #0 +10000586: da08 bge.n 1000059a +10000588: 4615 mov r5, r2 +1000058a: e046 b.n 1000061a +1000058c: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000590: e7df b.n 10000552 +10000592: f993 4006 ldrsb.w r4, [r3, #6] +10000596: 2c00 cmp r4, #0 +10000598: db37 blt.n 1000060a +1000059a: eb04 0c44 add.w ip, r4, r4, lsl #1 +1000059e: eb07 0c8c add.w ip, r7, ip, lsl #2 +100005a2: f89c 1007 ldrb.w r1, [ip, #7] +100005a6: f8dc 2008 ldr.w r2, [ip, #8] +100005aa: 71d9 strb r1, [r3, #7] +100005ac: 609a str r2, [r3, #8] +100005ae: f99c 2006 ldrsb.w r2, [ip, #6] +100005b2: 0061 lsls r1, r4, #1 +100005b4: 2a00 cmp r2, #0 +100005b6: 719a strb r2, [r3, #6] +100005b8: db3d blt.n 10000636 +100005ba: f8bc e004 ldrh.w lr, [ip, #4] +100005be: ea5f 5e4e movs.w lr, lr, lsl #21 +100005c2: d505 bpl.n 100005d0 +100005c4: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100005c8: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100005cc: f10e 0e1f add.w lr, lr, #31 +100005d0: f06f 0c07 mvn.w ip, #7 +100005d4: 190a adds r2, r1, r4 +100005d6: ea4f 5e6e mov.w lr, lr, asr #21 +100005da: 0092 lsls r2, r2, #2 +100005dc: eb02 024e add.w r2, r2, lr, lsl #1 +100005e0: 3208 adds r2, #8 +100005e2: 443a add r2, r7 +100005e4: ebac 0c03 sub.w ip, ip, r3 +100005e8: 4462 add r2, ip +100005ea: f3c2 024a ubfx r2, r2, #1, #11 +100005ee: ea6f 42c2 mvn.w r2, r2, lsl #19 +100005f2: ea6f 42d2 mvn.w r2, r2, lsr #19 +100005f6: 809a strh r2, [r3, #4] +100005f8: 4b1e ldr r3, [pc, #120] @ (10000674 ) +100005fa: 4421 add r1, r4 +100005fc: 781a ldrb r2, [r3, #0] +100005fe: eb07 0181 add.w r1, r7, r1, lsl #2 +10000602: 701c strb r4, [r3, #0] +10000604: 718a strb r2, [r1, #6] +10000606: e79d b.n 10000544 +10000608: 4673 mov r3, lr +1000060a: b9d9 cbnz r1, 10000644 +1000060c: 22ff movs r2, #255 @ 0xff +1000060e: f88e 2006 strb.w r2, [lr, #6] +10000612: f64b 5201 movw r2, #48385 @ 0xbd01 +10000616: f8ae 2004 strh.w r2, [lr, #4] +1000061a: 4c16 ldr r4, [pc, #88] @ (10000674 ) +1000061c: f64a 22aa movw r2, #43690 @ 0xaaaa +10000620: f894 c000 ldrb.w ip, [r4] +10000624: 4619 mov r1, r3 +10000626: 1bc9 subs r1, r1, r7 +10000628: 4149 adcs r1, r1 +1000062a: 434a muls r2, r1 +1000062c: 0d12 lsrs r2, r2, #20 +1000062e: f883 c006 strb.w ip, [r3, #6] +10000632: 7022 strb r2, [r4, #0] +10000634: e786 b.n 10000544 +10000636: 4a10 ldr r2, [pc, #64] @ (10000678 ) +10000638: e7dd b.n 100005f6 +1000063a: f99e 4006 ldrsb.w r4, [lr, #6] +1000063e: 4673 mov r3, lr +10000640: 2c00 cmp r4, #0 +10000642: daaa bge.n 1000059a +10000644: 4a0d ldr r2, [pc, #52] @ (1000067c ) +10000646: 4c0e ldr r4, [pc, #56] @ (10000680 ) +10000648: 1ad2 subs r2, r2, r3 +1000064a: 3a08 subs r2, #8 +1000064c: f3c2 310a ubfx r1, r2, #12, #11 +10000650: ea6f 5101 mvn.w r1, r1, lsl #20 +10000654: ea6f 5111 mvn.w r1, r1, lsr #20 +10000658: ea44 0252 orr.w r2, r4, r2, lsr #1 +1000065c: 80da strh r2, [r3, #6] +1000065e: 8099 strh r1, [r3, #4] +10000660: e770 b.n 10000544 +10000662: bf00 nop +10000664: 200007b9 .word 0x200007b9 +10000668: e000ed00 .word 0xe000ed00 +1000066c: 10000111 .word 0x10000111 +10000670: 200005ac .word 0x200005ac +10000674: 20000854 .word 0x20000854 +10000678: ffffbd01 .word 0xffffbd01 +1000067c: 200005e6 .word 0x200005e6 +10000680: fffff800 .word 0xfffff800 + +10000684 : +10000684: b5f0 push {r4, r5, r6, r7, lr} +10000686: f3ef 8505 mrs r5, IPSR +1000068a: b2ed uxtb r5, r5 +1000068c: f3ef 8c10 mrs ip, PRIMASK +10000690: b672 cpsid i +10000692: 4926 ldr r1, [pc, #152] @ (1000072c ) +10000694: e8d1 2fcf ldaexb r2, [r1] +10000698: 2301 movs r3, #1 +1000069a: 2a00 cmp r2, #0 +1000069c: d1fa bne.n 10000694 +1000069e: e8c1 3f42 strexb r2, r3, [r1] +100006a2: 2a00 cmp r2, #0 +100006a4: d1f6 bne.n 10000694 +100006a6: f3bf 8f5f dmb sy +100006aa: 4e21 ldr r6, [pc, #132] @ (10000730 ) +100006ac: f040 0e01 orr.w lr, r0, #1 +100006b0: 68b4 ldr r4, [r6, #8] +100006b2: f64a 23aa movw r3, #43690 @ 0xaaaa +100006b6: f854 7025 ldr.w r7, [r4, r5, lsl #2] +100006ba: 4a1e ldr r2, [pc, #120] @ (10000734 ) +100006bc: 4604 mov r4, r0 +100006be: 1aa4 subs r4, r4, r2 +100006c0: 4164 adcs r4, r4 +100006c2: 4363 muls r3, r4 +100006c4: 0d1b lsrs r3, r3, #20 +100006c6: 4577 cmp r7, lr +100006c8: b25b sxtb r3, r3 +100006ca: d01b beq.n 10000704 +100006cc: f992 4006 ldrsb.w r4, [r2, #6] +100006d0: 429c cmp r4, r3 +100006d2: d01c beq.n 1000070e +100006d4: f992 4012 ldrsb.w r4, [r2, #18] +100006d8: 429c cmp r4, r3 +100006da: d023 beq.n 10000724 +100006dc: f992 401e ldrsb.w r4, [r2, #30] +100006e0: 429c cmp r4, r3 +100006e2: d021 beq.n 10000728 +100006e4: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100006e8: 429c cmp r4, r3 +100006ea: bf08 it eq +100006ec: 2403 moveq r4, #3 +100006ee: d00f beq.n 10000710 +100006f0: 4a11 ldr r2, [pc, #68] @ (10000738 ) +100006f2: 2400 movs r4, #0 +100006f4: 7815 ldrb r5, [r2, #0] +100006f6: 7013 strb r3, [r2, #0] +100006f8: 7185 strb r5, [r0, #6] +100006fa: e8c1 4f8f stlb r4, [r1] +100006fe: f38c 8810 msr PRIMASK, ip +10000702: bdf0 pop {r4, r5, r6, r7, pc} +10000704: 68b2 ldr r2, [r6, #8] +10000706: 4c0d ldr r4, [pc, #52] @ (1000073c ) +10000708: f842 4025 str.w r4, [r2, r5, lsl #2] +1000070c: e7f0 b.n 100006f0 +1000070e: 2400 movs r4, #0 +10000710: eb04 0444 add.w r4, r4, r4, lsl #1 +10000714: eb02 0284 add.w r2, r2, r4, lsl #2 +10000718: 24ff movs r4, #255 @ 0xff +1000071a: 7194 strb r4, [r2, #6] +1000071c: f64b 5401 movw r4, #48385 @ 0xbd01 +10000720: 8094 strh r4, [r2, #4] +10000722: e7e5 b.n 100006f0 +10000724: 2401 movs r4, #1 +10000726: e7f3 b.n 10000710 +10000728: 2402 movs r4, #2 +1000072a: e7f1 b.n 10000710 +1000072c: 200007b9 .word 0x200007b9 +10000730: e000ed00 .word 0xe000ed00 +10000734: 200005ac .word 0x200005ac +10000738: 20000854 .word 0x20000854 +1000073c: 10000111 .word 0x10000111 + +10000740 : +10000740: 4b01 ldr r3, [pc, #4] @ (10000748 ) +10000742: 440b add r3, r1 +10000744: 6003 str r3, [r0, #0] +10000746: 4770 bx lr +10000748: 200007b0 .word 0x200007b0 + +1000074c : +1000074c: b570 push {r4, r5, r6, lr} +1000074e: 4c10 ldr r4, [pc, #64] @ (10000790 ) +10000750: 4d10 ldr r5, [pc, #64] @ (10000794 ) +10000752: 42ac cmp r4, r5 +10000754: d20e bcs.n 10000774 +10000756: 26ff movs r6, #255 @ 0xff +10000758: 6823 ldr r3, [r4, #0] +1000075a: b163 cbz r3, 10000776 +1000075c: f7ff fe12 bl 10000384 +10000760: 4601 mov r1, r0 +10000762: 4620 mov r0, r4 +10000764: f7ff ffec bl 10000740 +10000768: 80a6 strh r6, [r4, #4] +1000076a: f3bf 8f5f dmb sy +1000076e: 3408 adds r4, #8 +10000770: 42ac cmp r4, r5 +10000772: d3f1 bcc.n 10000758 +10000774: bd70 pop {r4, r5, r6, pc} +10000776: f7ff fe05 bl 10000384 +1000077a: 4601 mov r1, r0 +1000077c: 4620 mov r0, r4 +1000077e: f7ff ffdf bl 10000740 +10000782: 7126 strb r6, [r4, #4] +10000784: f3bf 8f5f dmb sy +10000788: 3408 adds r4, #8 +1000078a: 42ac cmp r4, r5 +1000078c: d3e4 bcc.n 10000758 +1000078e: bd70 pop {r4, r5, r6, pc} +10000790: 20000624 .word 0x20000624 +10000794: 2000062c .word 0x2000062c + +10000798 : +10000798: 4b0d ldr r3, [pc, #52] @ (100007d0 ) +1000079a: 681a ldr r2, [r3, #0] +1000079c: f3ef 8110 mrs r1, PRIMASK +100007a0: b672 cpsid i +100007a2: e8d2 cfcf ldaexb ip, [r2] +100007a6: 2001 movs r0, #1 +100007a8: f1bc 0f00 cmp.w ip, #0 +100007ac: d1f9 bne.n 100007a2 +100007ae: e8c2 0f4c strexb ip, r0, [r2] +100007b2: f1bc 0f00 cmp.w ip, #0 +100007b6: d1f4 bne.n 100007a2 +100007b8: f3bf 8f5f dmb sy +100007bc: 2200 movs r2, #0 +100007be: 681b ldr r3, [r3, #0] +100007c0: e8c3 2f8f stlb r2, [r3] +100007c4: f381 8810 msr PRIMASK, r1 +100007c8: bf40 sev +100007ca: 2000 movs r0, #0 +100007cc: 2100 movs r1, #0 +100007ce: 4770 bx lr +100007d0: 20000848 .word 0x20000848 +100007d4: 00000000 .word 0x00000000 + +100007d8 : +100007d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007dc: ed2d 8b02 vpush {d8} +100007e0: b085 sub sp, #20 +100007e2: f3ef 8305 mrs r3, IPSR +100007e6: b2db uxtb r3, r3 +100007e8: 3b10 subs r3, #16 +100007ea: 089a lsrs r2, r3, #2 +100007ec: bf18 it ne +100007ee: 2201 movne r2, #1 +100007f0: f04f 0101 mov.w r1, #1 +100007f4: f003 0b03 and.w fp, r3, #3 +100007f8: bf18 it ne +100007fa: 4daf ldrne r5, [pc, #700] @ (10000ab8 ) +100007fc: 4baf ldr r3, [pc, #700] @ (10000abc ) +100007fe: bf08 it eq +10000800: 4daf ldreq r5, [pc, #700] @ (10000ac0 ) +10000802: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000806: f853 6022 ldr.w r6, [r3, r2, lsl #2] +1000080a: fa01 f20b lsl.w r2, r1, fp +1000080e: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000812: ed9f 8ba7 vldr d8, [pc, #668] @ 10000ab0 +10000816: 9201 str r2, [sp, #4] +10000818: 605a str r2, [r3, #4] +1000081a: e02f b.n 1000087c +1000081c: 88b3 ldrh r3, [r6, #4] +1000081e: 041c lsls r4, r3, #16 +10000820: f140 8093 bpl.w 1000094a +10000824: 79b3 ldrb r3, [r6, #6] +10000826: 2b00 cmp r3, #0 +10000828: f040 80dd bne.w 100009e6 +1000082c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000830: 2a00 cmp r2, #0 +10000832: f2c0 811e blt.w 10000a72 +10000836: 6973 ldr r3, [r6, #20] +10000838: eb02 0242 add.w r2, r2, r2, lsl #1 +1000083c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000840: e9d3 4702 ldrd r4, r7, [r3, #8] +10000844: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000848: bf08 it eq +1000084a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +1000084e: d00e beq.n 1000086e +10000850: eb05 018b add.w r1, r5, fp, lsl #2 +10000854: 6aab ldr r3, [r5, #40] @ 0x28 +10000856: 690a ldr r2, [r1, #16] +10000858: 1ad2 subs r2, r2, r3 +1000085a: 1ae3 subs r3, r4, r3 +1000085c: 4293 cmp r3, r2 +1000085e: d305 bcc.n 1000086c +10000860: 2301 movs r3, #1 +10000862: 6a2a ldr r2, [r5, #32] +10000864: fa03 f30b lsl.w r3, r3, fp +10000868: 4213 tst r3, r2 +1000086a: d100 bne.n 1000086e +1000086c: 610c str r4, [r1, #16] +1000086e: 4628 mov r0, r5 +10000870: f000 fb38 bl 10000ee4 +10000874: 42a0 cmp r0, r4 +10000876: 41b9 sbcs r1, r7 +10000878: f2c0 80fb blt.w 10000a72 +1000087c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000880: 9a01 ldr r2, [sp, #4] +10000882: 2b00 cmp r3, #0 +10000884: 9300 str r3, [sp, #0] +10000886: 63ea str r2, [r5, #60] @ 0x3c +10000888: dbc8 blt.n 1000081c +1000088a: f8d6 8014 ldr.w r8, [r6, #20] +1000088e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000892: 4628 mov r0, r5 +10000894: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000898: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000089c: f000 fb22 bl 10000ee4 +100008a0: 42a0 cmp r0, r4 +100008a2: eb71 010a sbcs.w r1, r1, sl +100008a6: dbb9 blt.n 1000081c +100008a8: f1ba 0f00 cmp.w sl, #0 +100008ac: f2c0 80c3 blt.w 10000a36 +100008b0: e9d7 3104 ldrd r3, r1, [r7, #16] +100008b4: 4a83 ldr r2, [pc, #524] @ (10000ac4 ) +100008b6: 4293 cmp r3, r2 +100008b8: f000 80ed beq.w 10000a96 +100008bc: 887a ldrh r2, [r7, #2] +100008be: f9b6 0008 ldrsh.w r0, [r6, #8] +100008c2: b292 uxth r2, r2 +100008c4: ea42 4000 orr.w r0, r2, r0, lsl #16 +100008c8: 4798 blx r3 +100008ca: 4602 mov r2, r0 +100008cc: 460b mov r3, r1 +100008ce: ea52 0103 orrs.w r1, r2, r3 +100008d2: f000 80b0 beq.w 10000a36 +100008d6: 2b00 cmp r3, #0 +100008d8: f280 80d1 bge.w 10000a7e +100008dc: ebb4 0e02 subs.w lr, r4, r2 +100008e0: eb6a 0a03 sbc.w sl, sl, r3 +100008e4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100008e8: e9c7 ea02 strd lr, sl, [r7, #8] +100008ec: 2b00 cmp r3, #0 +100008ee: db95 blt.n 1000081c +100008f0: 6971 ldr r1, [r6, #20] +100008f2: eb03 0243 add.w r2, r3, r3, lsl #1 +100008f6: eb01 02c2 add.w r2, r1, r2, lsl #3 +100008fa: e9d2 7002 ldrd r7, r0, [r2, #8] +100008fe: 45be cmp lr, r7 +10000900: eb7a 0c00 sbcs.w ip, sl, r0 +10000904: ea4f 0243 mov.w r2, r3, lsl #1 +10000908: db88 blt.n 1000081c +1000090a: 46b4 mov ip, r6 +1000090c: f82c 3f08 strh.w r3, [ip, #8]! +10000910: e006 b.n 10000920 +10000912: eb03 0043 add.w r0, r3, r3, lsl #1 +10000916: eb01 00c0 add.w r0, r1, r0, lsl #3 +1000091a: 005a lsls r2, r3, #1 +1000091c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000920: 45be cmp lr, r7 +10000922: 441a add r2, r3 +10000924: eb7a 0000 sbcs.w r0, sl, r0 +10000928: eb01 04c2 add.w r4, r1, r2, lsl #3 +1000092c: db04 blt.n 10000938 +1000092e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000932: 46a4 mov ip, r4 +10000934: 2b00 cmp r3, #0 +10000936: daec bge.n 10000912 +10000938: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000093c: 9b00 ldr r3, [sp, #0] +1000093e: f8ac 3000 strh.w r3, [ip] +10000942: 88b3 ldrh r3, [r6, #4] +10000944: 041c lsls r4, r3, #16 +10000946: f53f af6d bmi.w 10000824 +1000094a: 6933 ldr r3, [r6, #16] +1000094c: f3ef 8210 mrs r2, PRIMASK +10000950: b672 cpsid i +10000952: e8d3 0fcf ldaexb r0, [r3] +10000956: 2101 movs r1, #1 +10000958: 2800 cmp r0, #0 +1000095a: d1fa bne.n 10000952 +1000095c: e8c3 1f40 strexb r0, r1, [r3] +10000960: 2800 cmp r0, #0 +10000962: d1f6 bne.n 10000952 +10000964: f3bf 8f5f dmb sy +10000968: f64f 74ff movw r4, #65535 @ 0xffff +1000096c: 88b0 ldrh r0, [r6, #4] +1000096e: 2300 movs r3, #0 +10000970: 6931 ldr r1, [r6, #16] +10000972: b200 sxth r0, r0 +10000974: 80b4 strh r4, [r6, #4] +10000976: e8c1 3f8f stlb r3, [r1] +1000097a: f382 8810 msr PRIMASK, r2 +1000097e: 4298 cmp r0, r3 +10000980: f6ff af50 blt.w 10000824 +10000984: 4607 mov r7, r0 +10000986: 46a9 mov r9, r5 +10000988: 6974 ldr r4, [r6, #20] +1000098a: f106 0808 add.w r8, r6, #8 +1000098e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000992: eb04 03ce add.w r3, r4, lr, lsl #3 +10000996: e9d3 5002 ldrd r5, r0, [r3, #8] +1000099a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000099e: 46c4 mov ip, r8 +100009a0: 2b00 cmp r3, #0 +100009a2: db13 blt.n 100009cc +100009a4: 46b2 mov sl, r6 +100009a6: 9700 str r7, [sp, #0] +100009a8: e004 b.n 100009b4 +100009aa: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +100009ae: 4694 mov ip, r2 +100009b0: 2b00 cmp r3, #0 +100009b2: db09 blt.n 100009c8 +100009b4: eb03 0643 add.w r6, r3, r3, lsl #1 +100009b8: eb04 02c6 add.w r2, r4, r6, lsl #3 +100009bc: e9d2 7102 ldrd r7, r1, [r2, #8] +100009c0: 42bd cmp r5, r7 +100009c2: eb70 0101 sbcs.w r1, r0, r1 +100009c6: daf0 bge.n 100009aa +100009c8: 4656 mov r6, sl +100009ca: 9f00 ldr r7, [sp, #0] +100009cc: f8ac 7000 strh.w r7, [ip] +100009d0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100009d4: f824 303e strh.w r3, [r4, lr, lsl #3] +100009d8: 2f00 cmp r7, #0 +100009da: dad8 bge.n 1000098e +100009dc: 79b3 ldrb r3, [r6, #6] +100009de: 464d mov r5, r9 +100009e0: 2b00 cmp r3, #0 +100009e2: f43f af23 beq.w 1000082c +100009e6: 2300 movs r3, #0 +100009e8: 71b3 strb r3, [r6, #6] +100009ea: f9b6 3008 ldrsh.w r3, [r6, #8] +100009ee: f106 0808 add.w r8, r6, #8 +100009f2: 1c58 adds r0, r3, #1 +100009f4: d03d beq.n 10000a72 +100009f6: 461a mov r2, r3 +100009f8: 6977 ldr r7, [r6, #20] +100009fa: e003 b.n 10000a04 +100009fc: 4680 mov r8, r0 +100009fe: 1c59 adds r1, r3, #1 +10000a00: f43f af16 beq.w 10000830 +10000a04: eb03 0143 add.w r1, r3, r3, lsl #1 +10000a08: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000a0c: f8b0 c002 ldrh.w ip, [r0, #2] +10000a10: 461c mov r4, r3 +10000a12: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000a16: 469e mov lr, r3 +10000a18: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000a1c: d0ee beq.n 100009fc +10000a1e: 4294 cmp r4, r2 +10000a20: ed80 8b02 vstr d8, [r0, #8] +10000a24: d005 beq.n 10000a32 +10000a26: f8a8 3000 strh.w r3, [r8] +10000a2a: 8932 ldrh r2, [r6, #8] +10000a2c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000a30: 8134 strh r4, [r6, #8] +10000a32: 4672 mov r2, lr +10000a34: e7e3 b.n 100009fe +10000a36: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000a3a: 8133 strh r3, [r6, #8] +10000a3c: 6933 ldr r3, [r6, #16] +10000a3e: f3ef 8210 mrs r2, PRIMASK +10000a42: b672 cpsid i +10000a44: e8d3 0fcf ldaexb r0, [r3] +10000a48: 2101 movs r1, #1 +10000a4a: 2800 cmp r0, #0 +10000a4c: d1fa bne.n 10000a44 +10000a4e: e8c3 1f40 strexb r0, r1, [r3] +10000a52: 2800 cmp r0, #0 +10000a54: d1f6 bne.n 10000a44 +10000a56: f3bf 8f5f dmb sy +10000a5a: 8873 ldrh r3, [r6, #2] +10000a5c: 6931 ldr r1, [r6, #16] +10000a5e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000a62: 9b00 ldr r3, [sp, #0] +10000a64: 8073 strh r3, [r6, #2] +10000a66: 2300 movs r3, #0 +10000a68: e8c1 3f8f stlb r3, [r1] +10000a6c: f382 8810 msr PRIMASK, r2 +10000a70: e6d4 b.n 1000081c +10000a72: bf40 sev +10000a74: b005 add sp, #20 +10000a76: ecbd 8b02 vpop {d8} +10000a7a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a7e: 4628 mov r0, r5 +10000a80: e9cd 2302 strd r2, r3, [sp, #8] +10000a84: f000 fa2e bl 10000ee4 +10000a88: 9a02 ldr r2, [sp, #8] +10000a8a: 9b03 ldr r3, [sp, #12] +10000a8c: eb10 0e02 adds.w lr, r0, r2 +10000a90: eb43 0a01 adc.w sl, r3, r1 +10000a94: e726 b.n 100008e4 +10000a96: 4608 mov r0, r1 +10000a98: 690b ldr r3, [r1, #16] +10000a9a: 9102 str r1, [sp, #8] +10000a9c: 4798 blx r3 +10000a9e: 2800 cmp r0, #0 +10000aa0: d0c9 beq.n 10000a36 +10000aa2: 9902 ldr r1, [sp, #8] +10000aa4: e9d1 2300 ldrd r2, r3, [r1] +10000aa8: e711 b.n 100008ce +10000aaa: bf00 nop +10000aac: f3af 8000 nop.w +10000ab0: ffffffff .word 0xffffffff +10000ab4: ffffffff .word 0xffffffff +10000ab8: 400b8000 .word 0x400b8000 +10000abc: 20000828 .word 0x20000828 +10000ac0: 400b0000 .word 0x400b0000 +10000ac4: 100007d9 .word 0x100007d9 + +10000ac8 : +10000ac8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000acc: 4c36 ldr r4, [pc, #216] @ (10000ba8 ) +10000ace: 6925 ldr r5, [r4, #16] +10000ad0: b12d cbz r5, 10000ade +10000ad2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000ad6: 210a movs r1, #10 +10000ad8: 4834 ldr r0, [pc, #208] @ (10000bac ) +10000ada: f7ff be31 b.w 10000740 +10000ade: f8df 80e4 ldr.w r8, [pc, #228] @ 10000bc4 +10000ae2: 2103 movs r1, #3 +10000ae4: 4640 mov r0, r8 +10000ae6: f000 f9eb bl 10000ec0 +10000aea: 2603 movs r6, #3 +10000aec: f8c4 800c str.w r8, [r4, #12] +10000af0: f7ff fc48 bl 10000384 +10000af4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000af8: 4b2d ldr r3, [pc, #180] @ (10000bb0 ) +10000afa: 7026 strb r6, [r4, #0] +10000afc: 4403 add r3, r0 +10000afe: 6123 str r3, [r4, #16] +10000b00: f8dc 3000 ldr.w r3, [ip] +10000b04: 210f movs r1, #15 +10000b06: 7063 strb r3, [r4, #1] +10000b08: 6963 ldr r3, [r4, #20] +10000b0a: 8061 strh r1, [r4, #2] +10000b0c: 831d strh r5, [r3, #24] +10000b0e: f04f 0504 mov.w r5, #4 +10000b12: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000b16: f04f 0505 mov.w r5, #5 +10000b1a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000b1e: f04f 0506 mov.w r5, #6 +10000b22: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000b26: f04f 0507 mov.w r5, #7 +10000b2a: 210e movs r1, #14 +10000b2c: f64f 72ff movw r2, #65535 @ 0xffff +10000b30: 2708 movs r7, #8 +10000b32: f04f 0e0a mov.w lr, #10 +10000b36: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000b3a: f04f 0901 mov.w r9, #1 +10000b3e: f04f 0c0c mov.w ip, #12 +10000b42: f04f 0b02 mov.w fp, #2 +10000b46: f04f 0a09 mov.w sl, #9 +10000b4a: 200d movs r0, #13 +10000b4c: f04f 050b mov.w r5, #11 +10000b50: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000b54: 4917 ldr r1, [pc, #92] @ (10000bb4 ) +10000b56: 80a2 strh r2, [r4, #4] +10000b58: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000b5c: 60a1 str r1, [r4, #8] +10000b5e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000b62: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000b66: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000b6a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000b6e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000b72: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000b76: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b7a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b7e: 801a strh r2, [r3, #0] +10000b80: 4b0d ldr r3, [pc, #52] @ (10000bb8 ) +10000b82: 4630 mov r0, r6 +10000b84: f8c8 7020 str.w r7, [r8, #32] +10000b88: 490c ldr r1, [pc, #48] @ (10000bbc ) +10000b8a: 60dc str r4, [r3, #12] +10000b8c: f7ff fc50 bl 10000430 +10000b90: 4649 mov r1, r9 +10000b92: 4630 mov r0, r6 +10000b94: f7ff fc36 bl 10000404 +10000b98: 4b09 ldr r3, [pc, #36] @ (10000bc0 ) +10000b9a: 210a movs r1, #10 +10000b9c: 641f str r7, [r3, #64] @ 0x40 +10000b9e: 4803 ldr r0, [pc, #12] @ (10000bac ) +10000ba0: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000ba4: f7ff bdcc b.w 10000740 +10000ba8: 200005f4 .word 0x200005f4 +10000bac: 20000848 .word 0x20000848 +10000bb0: 200007b0 .word 0x200007b0 +10000bb4: 0010ffff .word 0x0010ffff +10000bb8: 20000828 .word 0x20000828 +10000bbc: 100007d9 .word 0x100007d9 +10000bc0: 400b2000 .word 0x400b2000 +10000bc4: 400b0000 .word 0x400b0000 + +10000bc8 : +10000bc8: 4601 mov r1, r0 +10000bca: b5f0 push {r4, r5, r6, r7, lr} +10000bcc: 6900 ldr r0, [r0, #16] +10000bce: f3ef 8710 mrs r7, PRIMASK +10000bd2: b672 cpsid i +10000bd4: e8d0 5fcf ldaexb r5, [r0] +10000bd8: 2401 movs r4, #1 +10000bda: 2d00 cmp r5, #0 +10000bdc: d1fa bne.n 10000bd4 +10000bde: e8c0 4f45 strexb r5, r4, [r0] +10000be2: 2d00 cmp r5, #0 +10000be4: d1f6 bne.n 10000bd4 +10000be6: f3bf 8f5f dmb sy +10000bea: f9b1 e002 ldrsh.w lr, [r1, #2] +10000bee: 694c ldr r4, [r1, #20] +10000bf0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000bf4: f1be 0f00 cmp.w lr, #0 +10000bf8: ea4f 05cc mov.w r5, ip, lsl #3 +10000bfc: 6908 ldr r0, [r1, #16] +10000bfe: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000c02: db3c blt.n 10000c7e +10000c04: 5b66 ldrh r6, [r4, r5] +10000c06: 804e strh r6, [r1, #2] +10000c08: 2600 movs r6, #0 +10000c0a: e8c0 6f8f stlb r6, [r0] +10000c0e: f387 8810 msr PRIMASK, r7 +10000c12: f8bc 0002 ldrh.w r0, [ip, #2] +10000c16: e9cc 2302 strd r2, r3, [ip, #8] +10000c1a: 3001 adds r0, #1 +10000c1c: f3c0 000e ubfx r0, r0, #0, #15 +10000c20: 2801 cmp r0, #1 +10000c22: bf38 it cc +10000c24: 2001 movcc r0, #1 +10000c26: 9b05 ldr r3, [sp, #20] +10000c28: f8ac 0002 strh.w r0, [ip, #2] +10000c2c: f8cc 3010 str.w r3, [ip, #16] +10000c30: 9b06 ldr r3, [sp, #24] +10000c32: ea40 400e orr.w r0, r0, lr, lsl #16 +10000c36: f8cc 3014 str.w r3, [ip, #20] +10000c3a: 690b ldr r3, [r1, #16] +10000c3c: f3ef 8210 mrs r2, PRIMASK +10000c40: b672 cpsid i +10000c42: e8d3 cfcf ldaexb ip, [r3] +10000c46: 2701 movs r7, #1 +10000c48: f1bc 0f00 cmp.w ip, #0 +10000c4c: d1f9 bne.n 10000c42 +10000c4e: e8c3 7f4c strexb ip, r7, [r3] +10000c52: f1bc 0f00 cmp.w ip, #0 +10000c56: d1f4 bne.n 10000c42 +10000c58: f3bf 8f5f dmb sy +10000c5c: 888b ldrh r3, [r1, #4] +10000c5e: 5363 strh r3, [r4, r5] +10000c60: f8a1 e004 strh.w lr, [r1, #4] +10000c64: 690b ldr r3, [r1, #16] +10000c66: e8c3 6f8f stlb r6, [r3] +10000c6a: f382 8810 msr PRIMASK, r2 +10000c6e: 2201 movs r2, #1 +10000c70: 68cb ldr r3, [r1, #12] +10000c72: 7809 ldrb r1, [r1, #0] +10000c74: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c78: 408a lsls r2, r1 +10000c7a: 605a str r2, [r3, #4] +10000c7c: bdf0 pop {r4, r5, r6, r7, pc} +10000c7e: 2300 movs r3, #0 +10000c80: e8c0 3f8f stlb r3, [r0] +10000c84: f387 8810 msr PRIMASK, r7 +10000c88: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c8c: bdf0 pop {r4, r5, r6, r7, pc} +10000c8e: bf00 nop + +10000c90 : +10000c90: 4603 mov r3, r0 +10000c92: 8940 ldrh r0, [r0, #10] +10000c94: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c98: dd37 ble.n 10000d0a +10000c9a: 6958 ldr r0, [r3, #20] +10000c9c: 140a asrs r2, r1, #16 +10000c9e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000ca2: b510 push {r4, lr} +10000ca4: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000ca8: 691c ldr r4, [r3, #16] +10000caa: f3ef 8c10 mrs ip, PRIMASK +10000cae: b672 cpsid i +10000cb0: e8d4 efcf ldaexb lr, [r4] +10000cb4: 2201 movs r2, #1 +10000cb6: f1be 0f00 cmp.w lr, #0 +10000cba: d1f9 bne.n 10000cb0 +10000cbc: e8c4 2f4e strexb lr, r2, [r4] +10000cc0: f1be 0f00 cmp.w lr, #0 +10000cc4: d1f4 bne.n 10000cb0 +10000cc6: f3bf 8f5f dmb sy +10000cca: 8842 ldrh r2, [r0, #2] +10000ccc: b289 uxth r1, r1 +10000cce: b292 uxth r2, r2 +10000cd0: 428a cmp r2, r1 +10000cd2: d007 beq.n 10000ce4 +10000cd4: 2200 movs r2, #0 +10000cd6: 691b ldr r3, [r3, #16] +10000cd8: e8c3 2f8f stlb r2, [r3] +10000cdc: f38c 8810 msr PRIMASK, ip +10000ce0: 2000 movs r0, #0 +10000ce2: bd10 pop {r4, pc} +10000ce4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000ce8: 8042 strh r2, [r0, #2] +10000cea: 2101 movs r1, #1 +10000cec: 2200 movs r2, #0 +10000cee: 6918 ldr r0, [r3, #16] +10000cf0: 7199 strb r1, [r3, #6] +10000cf2: e8c0 2f8f stlb r2, [r0] +10000cf6: f38c 8810 msr PRIMASK, ip +10000cfa: 781c ldrb r4, [r3, #0] +10000cfc: 68da ldr r2, [r3, #12] +10000cfe: 4608 mov r0, r1 +10000d00: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000d04: 40a1 lsls r1, r4 +10000d06: 6059 str r1, [r3, #4] +10000d08: bd10 pop {r4, pc} +10000d0a: 2000 movs r0, #0 +10000d0c: 4770 bx lr +10000d0e: bf00 nop + +10000d10 : +10000d10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000d14: b082 sub sp, #8 +10000d16: 4606 mov r6, r0 +10000d18: f000 f8ec bl 10000ef4 +10000d1c: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000d20: 4604 mov r4, r0 +10000d22: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000d26: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000d2a: fbe6 4103 umlal r4, r1, r6, r3 +10000d2e: 42a0 cmp r0, r4 +10000d30: eb72 0301 sbcs.w r3, r2, r1 +10000d34: bf3a itte cc +10000d36: 4604 movcc r4, r0 +10000d38: 4615 movcc r5, r2 +10000d3a: 460d movcs r5, r1 +10000d3c: 1fa6 subs r6, r4, #6 +10000d3e: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000d42: 42b4 cmp r4, r6 +10000d44: eb75 0307 sbcs.w r3, r5, r7 +10000d48: bf3c itt cc +10000d4a: 2600 movcc r6, #0 +10000d4c: 4637 movcc r7, r6 +10000d4e: f000 f8d1 bl 10000ef4 +10000d52: 1a30 subs r0, r6, r0 +10000d54: eb67 0101 sbc.w r1, r7, r1 +10000d58: 2801 cmp r0, #1 +10000d5a: f171 0100 sbcs.w r1, r1, #0 +10000d5e: da06 bge.n 10000d6e +10000d60: 4620 mov r0, r4 +10000d62: 4629 mov r1, r5 +10000d64: b002 add sp, #8 +10000d66: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000d6a: f000 b8fb b.w 10000f64 +10000d6e: f000 f8c1 bl 10000ef4 +10000d72: 4286 cmp r6, r0 +10000d74: eb67 0101 sbc.w r1, r7, r1 +10000d78: 2900 cmp r1, #0 +10000d7a: db0a blt.n 10000d92 +10000d7c: 2100 movs r1, #0 +10000d7e: 4b17 ldr r3, [pc, #92] @ (10000ddc ) +10000d80: 4632 mov r2, r6 +10000d82: 9300 str r3, [sp, #0] +10000d84: 4816 ldr r0, [pc, #88] @ (10000de0 ) +10000d86: 463b mov r3, r7 +10000d88: 9101 str r1, [sp, #4] +10000d8a: f7ff ff1d bl 10000bc8 +10000d8e: 3001 adds r0, #1 +10000d90: d0e6 beq.n 10000d60 +10000d92: f04f 0c00 mov.w ip, #0 +10000d96: 4a13 ldr r2, [pc, #76] @ (10000de4 ) +10000d98: 4913 ldr r1, [pc, #76] @ (10000de8 ) +10000d9a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000d9c: 429f cmp r7, r3 +10000d9e: d804 bhi.n 10000daa +10000da0: 6a90 ldr r0, [r2, #40] @ 0x28 +10000da2: 42b0 cmp r0, r6 +10000da4: d2dc bcs.n 10000d60 +10000da6: 429f cmp r7, r3 +10000da8: d1da bne.n 10000d60 +10000daa: 680b ldr r3, [r1, #0] +10000dac: f3ef 8010 mrs r0, PRIMASK +10000db0: b672 cpsid i +10000db2: e8d3 8fcf ldaexb r8, [r3] +10000db6: f05f 0e01 movs.w lr, #1 +10000dba: f1b8 0f00 cmp.w r8, #0 +10000dbe: d1f8 bne.n 10000db2 +10000dc0: e8c3 ef48 strexb r8, lr, [r3] +10000dc4: f1b8 0f00 cmp.w r8, #0 +10000dc8: d1f3 bne.n 10000db2 +10000dca: f3bf 8f5f dmb sy +10000dce: 680b ldr r3, [r1, #0] +10000dd0: e8c3 cf8f stlb ip, [r3] +10000dd4: f380 8810 msr PRIMASK, r0 +10000dd8: bf20 wfe +10000dda: e7de b.n 10000d9a +10000ddc: 10000799 .word 0x10000799 +10000de0: 200005f4 .word 0x200005f4 +10000de4: 400b0000 .word 0x400b0000 +10000de8: 20000848 .word 0x20000848 + +10000dec : +10000dec: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000df0: 4606 mov r6, r0 +10000df2: 460d mov r5, r1 +10000df4: b083 sub sp, #12 +10000df6: f3ef 8405 mrs r4, IPSR +10000dfa: b2e4 uxtb r4, r4 +10000dfc: b13c cbz r4, 10000e0e +10000dfe: 4b2d ldr r3, [pc, #180] @ (10000eb4 ) +10000e00: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e02: 42aa cmp r2, r5 +10000e04: d21c bcs.n 10000e40 +10000e06: 2000 movs r0, #0 +10000e08: b003 add sp, #12 +10000e0a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000e0e: 4f2a ldr r7, [pc, #168] @ (10000eb8 ) +10000e10: f8d7 900c ldr.w r9, [r7, #12] +10000e14: f897 8000 ldrb.w r8, [r7] +10000e18: 4648 mov r0, r9 +10000e1a: f000 f863 bl 10000ee4 +10000e1e: f108 0804 add.w r8, r8, #4 +10000e22: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000e26: 1a1b subs r3, r3, r0 +10000e28: 1a30 subs r0, r6, r0 +10000e2a: eb65 0101 sbc.w r1, r5, r1 +10000e2e: 4298 cmp r0, r3 +10000e30: f171 0100 sbcs.w r1, r1, #0 +10000e34: db10 blt.n 10000e58 +10000e36: bf20 wfe +10000e38: 4b1e ldr r3, [pc, #120] @ (10000eb4 ) +10000e3a: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e3c: 42aa cmp r2, r5 +10000e3e: d3e2 bcc.n 10000e06 +10000e40: bf14 ite ne +10000e42: 2401 movne r4, #1 +10000e44: 2400 moveq r4, #0 +10000e46: 6a9b ldr r3, [r3, #40] @ 0x28 +10000e48: 42b3 cmp r3, r6 +10000e4a: bf34 ite cc +10000e4c: 4620 movcc r0, r4 +10000e4e: f044 0001 orrcs.w r0, r4, #1 +10000e52: b003 add sp, #12 +10000e54: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000e58: f000 f84c bl 10000ef4 +10000e5c: 4286 cmp r6, r0 +10000e5e: eb65 0101 sbc.w r1, r5, r1 +10000e62: 2900 cmp r1, #0 +10000e64: db14 blt.n 10000e90 +10000e66: 4b15 ldr r3, [pc, #84] @ (10000ebc ) +10000e68: 4638 mov r0, r7 +10000e6a: e9cd 3400 strd r3, r4, [sp] +10000e6e: 4632 mov r2, r6 +10000e70: 462b mov r3, r5 +10000e72: f7ff fea9 bl 10000bc8 +10000e76: 1e01 subs r1, r0, #0 +10000e78: dd0a ble.n 10000e90 +10000e7a: 4b0e ldr r3, [pc, #56] @ (10000eb4 ) +10000e7c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e7e: 42aa cmp r2, r5 +10000e80: d316 bcc.n 10000eb0 +10000e82: 6a9b ldr r3, [r3, #40] @ 0x28 +10000e84: 42b3 cmp r3, r6 +10000e86: d311 bcc.n 10000eac +10000e88: 480b ldr r0, [pc, #44] @ (10000eb8 ) +10000e8a: f7ff ff01 bl 10000c90 +10000e8e: e7b6 b.n 10000dfe +10000e90: 4b08 ldr r3, [pc, #32] @ (10000eb4 ) +10000e92: 6a5c ldr r4, [r3, #36] @ 0x24 +10000e94: 42ac cmp r4, r5 +10000e96: d3b6 bcc.n 10000e06 +10000e98: 1b64 subs r4, r4, r5 +10000e9a: bf18 it ne +10000e9c: 2401 movne r4, #1 +10000e9e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000ea0: 42b3 cmp r3, r6 +10000ea2: bf34 ite cc +10000ea4: 4620 movcc r0, r4 +10000ea6: f044 0001 orrcs.w r0, r4, #1 +10000eaa: e7ad b.n 10000e08 +10000eac: 42aa cmp r2, r5 +10000eae: d1eb bne.n 10000e88 +10000eb0: bf20 wfe +10000eb2: e7e9 b.n 10000e88 +10000eb4: 400b0000 .word 0x400b0000 +10000eb8: 200005f4 .word 0x200005f4 +10000ebc: 10000799 .word 0x10000799 + +10000ec0 : +10000ec0: b410 push {r4} +10000ec2: 4b05 ldr r3, [pc, #20] @ (10000ed8 ) +10000ec4: 4c05 ldr r4, [pc, #20] @ (10000edc ) +10000ec6: 4a06 ldr r2, [pc, #24] @ (10000ee0 ) +10000ec8: 42a0 cmp r0, r4 +10000eca: bf14 ite ne +10000ecc: 4618 movne r0, r3 +10000ece: 1c58 addeq r0, r3, #1 +10000ed0: f85d 4b04 ldr.w r4, [sp], #4 +10000ed4: f7ff ba2a b.w 1000032c +10000ed8: 200007d8 .word 0x200007d8 +10000edc: 400b8000 .word 0x400b8000 +10000ee0: 10003634 .word 0x10003634 + +10000ee4 : +10000ee4: 4603 mov r3, r0 +10000ee6: 6a41 ldr r1, [r0, #36] @ 0x24 +10000ee8: 460a mov r2, r1 +10000eea: 6a98 ldr r0, [r3, #40] @ 0x28 +10000eec: 6a59 ldr r1, [r3, #36] @ 0x24 +10000eee: 428a cmp r2, r1 +10000ef0: d1fa bne.n 10000ee8 +10000ef2: 4770 bx lr + +10000ef4 : +10000ef4: 4b03 ldr r3, [pc, #12] @ (10000f04 ) +10000ef6: 6a59 ldr r1, [r3, #36] @ 0x24 +10000ef8: 460a mov r2, r1 +10000efa: 6a98 ldr r0, [r3, #40] @ 0x28 +10000efc: 6a59 ldr r1, [r3, #36] @ 0x24 +10000efe: 4291 cmp r1, r2 +10000f00: d1fa bne.n 10000ef8 +10000f02: 4770 bx lr +10000f04: 400b0000 .word 0x400b0000 + +10000f08 : +10000f08: b430 push {r4, r5} +10000f0a: 4a15 ldr r2, [pc, #84] @ (10000f60 ) +10000f0c: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f0e: 469c mov ip, r3 +10000f10: 6a94 ldr r4, [r2, #40] @ 0x28 +10000f12: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f14: 4563 cmp r3, ip +10000f16: d1fa bne.n 10000f0e +10000f18: 1902 adds r2, r0, r4 +10000f1a: 4159 adcs r1, r3 +10000f1c: f04f 0500 mov.w r5, #0 +10000f20: bf28 it cs +10000f22: 2501 movcs r5, #1 +10000f24: 4b0e ldr r3, [pc, #56] @ (10000f60 ) +10000f26: 6a5b ldr r3, [r3, #36] @ 0x24 +10000f28: b1b5 cbz r5, 10000f58 +10000f2a: 1c5a adds r2, r3, #1 +10000f2c: bf08 it eq +10000f2e: 461a moveq r2, r3 +10000f30: d008 beq.n 10000f44 +10000f32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000f36: 460a mov r2, r1 +10000f38: 4809 ldr r0, [pc, #36] @ (10000f60 ) +10000f3a: 6a43 ldr r3, [r0, #36] @ 0x24 +10000f3c: 428b cmp r3, r1 +10000f3e: d3fc bcc.n 10000f3a +10000f40: 428b cmp r3, r1 +10000f42: d107 bne.n 10000f54 +10000f44: 4906 ldr r1, [pc, #24] @ (10000f60 ) +10000f46: e002 b.n 10000f4e +10000f48: 6a48 ldr r0, [r1, #36] @ 0x24 +10000f4a: 4298 cmp r0, r3 +10000f4c: d102 bne.n 10000f54 +10000f4e: 6a88 ldr r0, [r1, #40] @ 0x28 +10000f50: 4290 cmp r0, r2 +10000f52: d3f9 bcc.n 10000f48 +10000f54: bc30 pop {r4, r5} +10000f56: 4770 bx lr +10000f58: 4299 cmp r1, r3 +10000f5a: d8ed bhi.n 10000f38 +10000f5c: e7f0 b.n 10000f40 +10000f5e: bf00 nop +10000f60: 400b0000 .word 0x400b0000 + +10000f64 : +10000f64: 4a07 ldr r2, [pc, #28] @ (10000f84 ) +10000f66: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f68: 4299 cmp r1, r3 +10000f6a: d8fc bhi.n 10000f66 +10000f6c: 4299 cmp r1, r3 +10000f6e: d107 bne.n 10000f80 +10000f70: 4b04 ldr r3, [pc, #16] @ (10000f84 ) +10000f72: e002 b.n 10000f7a +10000f74: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f76: 4291 cmp r1, r2 +10000f78: d102 bne.n 10000f80 +10000f7a: 6a9a ldr r2, [r3, #40] @ 0x28 +10000f7c: 4290 cmp r0, r2 +10000f7e: d8f9 bhi.n 10000f74 +10000f80: 4770 bx lr +10000f82: bf00 nop +10000f84: 400b0000 .word 0x400b0000 + +10000f88 : +10000f88: b5f8 push {r3, r4, r5, r6, r7, lr} +10000f8a: 4605 mov r5, r0 +10000f8c: 2006 movs r0, #6 +10000f8e: 460e mov r6, r1 +10000f90: f000 f8e4 bl 1000115c +10000f94: 2800 cmp r0, #0 +10000f96: d042 beq.n 1000101e +10000f98: 4a35 ldr r2, [pc, #212] @ (10001070 ) +10000f9a: 4836 ldr r0, [pc, #216] @ (10001074 ) +10000f9c: 4295 cmp r5, r2 +10000f9e: bf14 ite ne +10000fa0: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000fa4: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000fa8: 4b33 ldr r3, [pc, #204] @ (10001078 ) +10000faa: 4934 ldr r1, [pc, #208] @ (1000107c ) +10000fac: 6002 str r2, [r0, #0] +10000fae: 601a str r2, [r3, #0] +10000fb0: 688c ldr r4, [r1, #8] +10000fb2: ea32 0404 bics.w r4, r2, r4 +10000fb6: d1fb bne.n 10000fb0 +10000fb8: 4b2d ldr r3, [pc, #180] @ (10001070 ) +10000fba: f44f 7180 mov.w r1, #256 @ 0x100 +10000fbe: 1aeb subs r3, r5, r3 +10000fc0: fab3 f383 clz r3, r3 +10000fc4: 4a2e ldr r2, [pc, #184] @ (10001080 ) +10000fc6: 095b lsrs r3, r3, #5 +10000fc8: 2006 movs r0, #6 +10000fca: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000fce: f000 f8c5 bl 1000115c +10000fd2: 00c3 lsls r3, r0, #3 +10000fd4: fbb3 f3f6 udiv r3, r3, r6 +10000fd8: 3301 adds r3, #1 +10000fda: 09da lsrs r2, r3, #7 +10000fdc: d120 bne.n 10001020 +10000fde: 2640 movs r6, #64 @ 0x40 +10000fe0: 2101 movs r1, #1 +10000fe2: 6269 str r1, [r5, #36] @ 0x24 +10000fe4: 62aa str r2, [r5, #40] @ 0x28 +10000fe6: 6b2f ldr r7, [r5, #48] @ 0x30 +10000fe8: 07fb lsls r3, r7, #31 +10000fea: d422 bmi.n 10001032 +10000fec: 462b mov r3, r5 +10000fee: 2200 movs r2, #0 +10000ff0: f853 1f2c ldr.w r1, [r3, #44]! +10000ff4: 2006 movs r0, #6 +10000ff6: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000ffa: 6022 str r2, [r4, #0] +10000ffc: 632f str r7, [r5, #48] @ 0x30 +10000ffe: f000 f8ad bl 1000115c +10001002: f240 3101 movw r1, #769 @ 0x301 +10001006: 2203 movs r2, #3 +10001008: 0080 lsls r0, r0, #2 +1000100a: fbb0 f0f6 udiv r0, r0, r6 +1000100e: 6aeb ldr r3, [r5, #44] @ 0x2c +10001010: f083 0370 eor.w r3, r3, #112 @ 0x70 +10001014: f003 037e and.w r3, r3, #126 @ 0x7e +10001018: 6023 str r3, [r4, #0] +1000101a: 6329 str r1, [r5, #48] @ 0x30 +1000101c: 64aa str r2, [r5, #72] @ 0x48 +1000101e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001020: f64f 71fe movw r1, #65534 @ 0xfffe +10001024: 428a cmp r2, r1 +10001026: d91b bls.n 10001060 +10001028: 4622 mov r2, r4 +1000102a: f64f 71ff movw r1, #65535 @ 0xffff +1000102e: 4e15 ldr r6, [pc, #84] @ (10001084 ) +10001030: e7d7 b.n 10000fe2 +10001032: f240 3201 movw r2, #769 @ 0x301 +10001036: f505 5340 add.w r3, r5, #12288 @ 0x3000 +1000103a: 631a str r2, [r3, #48] @ 0x30 +1000103c: 6a6b ldr r3, [r5, #36] @ 0x24 +1000103e: 6aac ldr r4, [r5, #40] @ 0x28 +10001040: 2006 movs r0, #6 +10001042: eb04 1483 add.w r4, r4, r3, lsl #6 +10001046: f000 f889 bl 1000115c +1000104a: 4b0f ldr r3, [pc, #60] @ (10001088 ) +1000104c: 02a4 lsls r4, r4, #10 +1000104e: fba3 2300 umull r2, r3, r3, r0 +10001052: 0adb lsrs r3, r3, #11 +10001054: 2100 movs r1, #0 +10001056: fbb4 f0f3 udiv r0, r4, r3 +1000105a: f7ff ff55 bl 10000f08 +1000105e: e7c5 b.n 10000fec +10001060: f3c3 0345 ubfx r3, r3, #1, #6 +10001064: 4611 mov r1, r2 +10001066: eb03 1682 add.w r6, r3, r2, lsl #6 +1000106a: 461a mov r2, r3 +1000106c: e7b9 b.n 10000fe2 +1000106e: bf00 nop +10001070: 40078000 .word 0x40078000 +10001074: 40022000 .word 0x40022000 +10001078: 40023000 .word 0x40023000 +1000107c: 40020000 .word 0x40020000 +10001080: 2000084c .word 0x2000084c +10001084: 003fffc0 .word 0x003fffc0 +10001088: 8f2b7b75 .word 0x8f2b7b75 + +1000108c : +1000108c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001090: ea4f 0c8c mov.w ip, ip, lsl #2 +10001094: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001098: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +1000109c: b5f0 push {r4, r5, r6, r7, lr} +1000109e: 4616 mov r6, r2 +100010a0: f8dc 2004 ldr.w r2, [ip, #4] +100010a4: 1f05 subs r5, r0, #4 +100010a6: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +100010aa: bf38 it cc +100010ac: f44f 3280 movcc.w r2, #65536 @ 0x10000 +100010b0: b2ed uxtb r5, r5 +100010b2: bf38 it cc +100010b4: f8cc 2004 strcc.w r2, [ip, #4] +100010b8: 2d01 cmp r5, #1 +100010ba: d92a bls.n 10001112 +100010bc: f44f 6700 mov.w r7, #2048 @ 0x800 +100010c0: 4c25 ldr r4, [pc, #148] @ (10001158 ) +100010c2: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100010c6: 6017 str r7, [r2, #0] +100010c8: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100010cc: b9b2 cbnz r2, 100010fc +100010ce: f8dc 2000 ldr.w r2, [ip] +100010d2: 2d01 cmp r5, #1 +100010d4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100010d8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100010dc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100010e0: 6032 str r2, [r6, #0] +100010e2: d92a bls.n 1000113a +100010e4: f44f 6100 mov.w r1, #2048 @ 0x800 +100010e8: f844 3020 str.w r3, [r4, r0, lsl #2] +100010ec: f44f 3380 mov.w r3, #65536 @ 0x10000 +100010f0: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100010f4: 6011 str r1, [r2, #0] +100010f6: f8cc 3004 str.w r3, [ip, #4] +100010fa: bdf0 pop {r4, r5, r6, r7, pc} +100010fc: 6967 ldr r7, [r4, #20] +100010fe: fbb7 fef2 udiv lr, r7, r2 +10001102: f10e 0e01 add.w lr, lr, #1 +10001106: eb0e 0e4e add.w lr, lr, lr, lsl #1 +1000110a: f1be 0e03 subs.w lr, lr, #3 +1000110e: d2fc bcs.n 1000110a +10001110: e7dd b.n 100010ce +10001112: 2901 cmp r1, #1 +10001114: d1d2 bne.n 100010bc +10001116: 2403 movs r4, #3 +10001118: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000111c: 6014 str r4, [r2, #0] +1000111e: f8dc 2008 ldr.w r2, [ip, #8] +10001122: 07d2 lsls r2, r2, #31 +10001124: d5fb bpl.n 1000111e +10001126: f8dc 2000 ldr.w r2, [ip] +1000112a: 4c0b ldr r4, [pc, #44] @ (10001158 ) +1000112c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001130: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001134: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001138: 6032 str r2, [r6, #0] +1000113a: 2201 movs r2, #1 +1000113c: f8dc 5000 ldr.w r5, [ip] +10001140: 404d eors r5, r1 +10001142: f005 0503 and.w r5, r5, #3 +10001146: 6035 str r5, [r6, #0] +10001148: fa02 f101 lsl.w r1, r2, r1 +1000114c: f8dc 2008 ldr.w r2, [ip, #8] +10001150: 420a tst r2, r1 +10001152: d0fb beq.n 1000114c +10001154: e7c6 b.n 100010e4 +10001156: bf00 nop +10001158: 200007dc .word 0x200007dc + +1000115c : +1000115c: 4b01 ldr r3, [pc, #4] @ (10001164 ) +1000115e: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001162: 4770 bx lr +10001164: 200007dc .word 0x200007dc + +10001168 : +10001168: b470 push {r4, r5, r6} +1000116a: 9d03 ldr r5, [sp, #12] +1000116c: 6804 ldr r4, [r0, #0] +1000116e: 032d lsls r5, r5, #12 +10001170: ea45 4503 orr.w r5, r5, r3, lsl #16 +10001174: 4b1b ldr r3, [pc, #108] @ (100011e4 ) +10001176: 2c00 cmp r4, #0 +10001178: fbb3 f3f1 udiv r3, r3, r1 +1000117c: fbb2 f6f3 udiv r6, r2, r3 +10001180: db1f blt.n 100011c2 +10001182: 4a19 ldr r2, [pc, #100] @ (100011e8 ) +10001184: 4b19 ldr r3, [pc, #100] @ (100011ec ) +10001186: 4290 cmp r0, r2 +10001188: bf14 ite ne +1000118a: f44f 4280 movne.w r2, #16384 @ 0x4000 +1000118e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10001192: 4c17 ldr r4, [pc, #92] @ (100011f0 ) +10001194: 601a str r2, [r3, #0] +10001196: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000119a: 601a str r2, [r3, #0] +1000119c: 68a3 ldr r3, [r4, #8] +1000119e: ea32 0303 bics.w r3, r2, r3 +100011a2: d1fb bne.n 1000119c +100011a4: 2221 movs r2, #33 @ 0x21 +100011a6: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100011aa: 3304 adds r3, #4 +100011ac: 6001 str r1, [r0, #0] +100011ae: 6086 str r6, [r0, #8] +100011b0: 601a str r2, [r3, #0] +100011b2: 6802 ldr r2, [r0, #0] +100011b4: 2a00 cmp r2, #0 +100011b6: dafc bge.n 100011b2 +100011b8: 2208 movs r2, #8 +100011ba: 60c5 str r5, [r0, #12] +100011bc: 601a str r2, [r3, #0] +100011be: bc70 pop {r4, r5, r6} +100011c0: 4770 bx lr +100011c2: 6803 ldr r3, [r0, #0] +100011c4: f003 033f and.w r3, r3, #63 @ 0x3f +100011c8: 428b cmp r3, r1 +100011ca: d1da bne.n 10001182 +100011cc: 6883 ldr r3, [r0, #8] +100011ce: f3c3 030b ubfx r3, r3, #0, #12 +100011d2: 42b3 cmp r3, r6 +100011d4: d1d5 bne.n 10001182 +100011d6: 68c3 ldr r3, [r0, #12] +100011d8: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100011dc: 42ab cmp r3, r5 +100011de: d1d0 bne.n 10001182 +100011e0: e7ed b.n 100011be +100011e2: bf00 nop +100011e4: 00b71b00 .word 0x00b71b00 +100011e8: 40058000 .word 0x40058000 +100011ec: 40022000 .word 0x40022000 +100011f0: 40020000 .word 0x40020000 + +100011f4 : +100011f4: 2301 movs r3, #1 +100011f6: eb00 0040 add.w r0, r0, r0, lsl #1 +100011fa: 0080 lsls r0, r0, #2 +100011fc: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001200: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001204: 6041 str r1, [r0, #4] +10001206: 6003 str r3, [r0, #0] +10001208: 4770 bx lr +1000120a: bf00 nop + +1000120c : +1000120c: 2300 movs r3, #0 +1000120e: 8adb ldrh r3, [r3, #22] +10001210: 2200 movs r2, #0 +10001212: e842 f200 tt r2, r2 +10001216: 0252 lsls r2, r2, #9 +10001218: d401 bmi.n 1000121e +1000121a: 2110 movs r1, #16 +1000121c: 4718 bx r3 +1000121e: 2104 movs r1, #4 +10001220: 4718 bx r3 +10001222: bf00 nop + +10001224 : +10001224: 4a03 ldr r2, [pc, #12] @ (10001234 ) +10001226: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +1000122a: 2b00 cmp r3, #0 +1000122c: d0fb beq.n 10001226 +1000122e: f3bf 8f5f dmb sy +10001232: 4770 bx lr +10001234: 400e0000 .word 0x400e0000 + +10001238 : +10001238: 2100 movs r1, #0 +1000123a: 4b04 ldr r3, [pc, #16] @ (1000124c ) +1000123c: 4a04 ldr r2, [pc, #16] @ (10001250 ) +1000123e: f3bf 8f5f dmb sy +10001242: f843 1b04 str.w r1, [r3], #4 +10001246: 4293 cmp r3, r2 +10001248: d1f9 bne.n 1000123e +1000124a: 4770 bx lr +1000124c: 400e080c .word 0x400e080c +10001250: 400e082c .word 0x400e082c + +10001254 : +10001254: b410 push {r4} +10001256: f44f 708d mov.w r0, #282 @ 0x11a +1000125a: f44f 642a mov.w r4, #2720 @ 0xaa0 +1000125e: 4a06 ldr r2, [pc, #24] @ (10001278 ) +10001260: 4b06 ldr r3, [pc, #24] @ (1000127c ) +10001262: 4907 ldr r1, [pc, #28] @ (10001280 ) +10001264: 6014 str r4, [r2, #0] +10001266: 60d0 str r0, [r2, #12] +10001268: 6019 str r1, [r3, #0] +1000126a: 6853 ldr r3, [r2, #4] +1000126c: 2b00 cmp r3, #0 +1000126e: dafc bge.n 1000126a +10001270: f85d 4b04 ldr.w r4, [sp], #4 +10001274: 4770 bx lr +10001276: bf00 nop +10001278: 40048000 .word 0x40048000 +1000127c: 4004a000 .word 0x4004a000 +10001280: 00fab000 .word 0x00fab000 + +10001284 : +10001284: 4770 bx lr +10001286: bf00 nop + +10001288 : +10001288: b508 push {r3, lr} +1000128a: 4801 ldr r0, [pc, #4] @ (10001290 ) +1000128c: f7ff f836 bl 100002fc +10001290: 10003658 .word 0x10003658 + +10001294 : +10001294: b538 push {r3, r4, r5, lr} +10001296: 4c05 ldr r4, [pc, #20] @ (100012ac ) +10001298: 4d05 ldr r5, [pc, #20] @ (100012b0 ) +1000129a: 42ac cmp r4, r5 +1000129c: d204 bcs.n 100012a8 +1000129e: f854 3b04 ldr.w r3, [r4], #4 +100012a2: 4798 blx r3 +100012a4: 42ac cmp r4, r5 +100012a6: d3fa bcc.n 1000129e +100012a8: bd38 pop {r3, r4, r5, pc} +100012aa: bf00 nop +100012ac: 100035d0 .word 0x100035d0 +100012b0: 10003610 .word 0x10003610 + +100012b4 : +100012b4: b410 push {r4} +100012b6: 4807 ldr r0, [pc, #28] @ (100012d4 ) +100012b8: 4c07 ldr r4, [pc, #28] @ (100012d8 ) +100012ba: 4b08 ldr r3, [pc, #32] @ (100012dc ) +100012bc: 4a08 ldr r2, [pc, #32] @ (100012e0 ) +100012be: 4909 ldr r1, [pc, #36] @ (100012e4 ) +100012c0: 6004 str r4, [r0, #0] +100012c2: 601a str r2, [r3, #0] +100012c4: 688b ldr r3, [r1, #8] +100012c6: ea32 0303 bics.w r3, r2, r3 +100012ca: d1fb bne.n 100012c4 +100012cc: f85d 4b04 ldr.w r4, [sp], #4 +100012d0: 4770 bx lr +100012d2: bf00 nop +100012d4: 40022000 .word 0x40022000 +100012d8: efef3b7f .word 0xefef3b7f +100012dc: 40023000 .word 0x40023000 +100012e0: 03f3fff6 .word 0x03f3fff6 +100012e4: 40020000 .word 0x40020000 + +100012e8 : +100012e8: 4b04 ldr r3, [pc, #16] @ (100012fc ) +100012ea: 6cdb ldr r3, [r3, #76] @ 0x4c +100012ec: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100012f0: d103 bne.n 100012fa +100012f2: f44f 2280 mov.w r2, #262144 @ 0x40000 +100012f6: 4b02 ldr r3, [pc, #8] @ (10001300 ) +100012f8: 64da str r2, [r3, #76] @ 0x4c +100012fa: 4770 bx lr +100012fc: 50110000 .word 0x50110000 +10001300: 50112000 .word 0x50112000 + +10001304 : +10001304: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001308: 4b04 ldr r3, [pc, #16] @ (1000131c ) +1000130a: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +1000130e: 430b orrs r3, r1 +10001310: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10001314: ee10 0430 dcp_rcmp r0 +10001318: 4770 bx lr +1000131a: bf00 nop +1000131c: 00300303 .word 0x00300303 + +10001320 : +10001320: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10001324: 4b04 ldr r3, [pc, #16] @ (10001338 ) +10001326: 4a05 ldr r2, [pc, #20] @ (1000133c ) +10001328: 6019 str r1, [r3, #0] +1000132a: 6893 ldr r3, [r2, #8] +1000132c: 43db mvns r3, r3 +1000132e: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10001332: d1fa bne.n 1000132a +10001334: 4770 bx lr +10001336: bf00 nop +10001338: 40023000 .word 0x40023000 +1000133c: 40020000 .word 0x40020000 + +10001340 : +10001340: b510 push {r4, lr} +10001342: f245 2053 movw r0, #21075 @ 0x5253 +10001346: f7ff ff61 bl 1000120c +1000134a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000134e: 4603 mov r3, r0 +10001350: 2004 movs r0, #4 +10001352: 4718 bx r3 + +10001354 : +10001354: b510 push {r4, lr} +10001356: f245 2053 movw r0, #21075 @ 0x5253 +1000135a: f7ff ff57 bl 1000120c +1000135e: e8bd 4010 ldmia.w sp!, {r4, lr} +10001362: 4603 mov r3, r0 +10001364: 2001 movs r0, #1 +10001366: 4718 bx r3 + +10001368 : +10001368: f7ff b820 b.w 100003ac + +1000136c : +1000136c: 4914 ldr r1, [pc, #80] @ (100013c0 ) +1000136e: 4b15 ldr r3, [pc, #84] @ (100013c4 ) +10001370: b570 push {r4, r5, r6, lr} +10001372: 1a5c subs r4, r3, r1 +10001374: 10a6 asrs r6, r4, #2 +10001376: 2e44 cmp r6, #68 @ 0x44 +10001378: 4632 mov r2, r6 +1000137a: bf28 it cs +1000137c: 2244 movcs r2, #68 @ 0x44 +1000137e: 4d12 ldr r5, [pc, #72] @ (100013c8 ) +10001380: 0092 lsls r2, r2, #2 +10001382: 4628 mov r0, r5 +10001384: f002 f872 bl 1000346c +10001388: f5b4 7f86 cmp.w r4, #268 @ 0x10c +1000138c: d813 bhi.n 100013b6 +1000138e: 4a0f ldr r2, [pc, #60] @ (100013cc ) +10001390: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10001394: d012 beq.n 100013bc +10001396: 192b adds r3, r5, r4 +10001398: 0841 lsrs r1, r0, #1 +1000139a: eb03 01c1 add.w r1, r3, r1, lsl #3 +1000139e: e9c3 2200 strd r2, r2, [r3] +100013a2: 3308 adds r3, #8 +100013a4: 428b cmp r3, r1 +100013a6: d1fa bne.n 1000139e +100013a8: 07c3 lsls r3, r0, #31 +100013aa: d504 bpl.n 100013b6 +100013ac: f020 0001 bic.w r0, r0, #1 +100013b0: 4430 add r0, r6 +100013b2: f845 2020 str.w r2, [r5, r0, lsl #2] +100013b6: 4b06 ldr r3, [pc, #24] @ (100013d0 ) +100013b8: 609d str r5, [r3, #8] +100013ba: bd70 pop {r4, r5, r6, pc} +100013bc: 2043 movs r0, #67 @ 0x43 +100013be: e7f8 b.n 100013b2 +100013c0: 10000000 .word 0x10000000 +100013c4: 10000110 .word 0x10000110 +100013c8: 20000000 .word 0x20000000 +100013cc: 10000111 .word 0x10000111 +100013d0: e000ed00 .word 0xe000ed00 + +100013d4 : +100013d4: 2300 movs r3, #0 +100013d6: b570 push {r4, r5, r6, lr} +100013d8: 4c2b ldr r4, [pc, #172] @ (10001488 ) +100013da: b082 sub sp, #8 +100013dc: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100013e0: f7ff ff38 bl 10001254 +100013e4: 2201 movs r2, #1 +100013e6: 4b29 ldr r3, [pc, #164] @ (1000148c ) +100013e8: 63da str r2, [r3, #60] @ 0x3c +100013ea: 6c63 ldr r3, [r4, #68] @ 0x44 +100013ec: 2b01 cmp r3, #1 +100013ee: d1fc bne.n 100013ea +100013f0: 2103 movs r1, #3 +100013f2: 4a26 ldr r2, [pc, #152] @ (1000148c ) +100013f4: 4b24 ldr r3, [pc, #144] @ (10001488 ) +100013f6: 6311 str r1, [r2, #48] @ 0x30 +100013f8: 6b9c ldr r4, [r3, #56] @ 0x38 +100013fa: 2c01 cmp r4, #1 +100013fc: d1fc bne.n 100013f8 +100013fe: 2602 movs r6, #2 +10001400: 2505 movs r5, #5 +10001402: 4621 mov r1, r4 +10001404: 2305 movs r3, #5 +10001406: 4a22 ldr r2, [pc, #136] @ (10001490 ) +10001408: 4822 ldr r0, [pc, #136] @ (10001494 ) +1000140a: 9600 str r6, [sp, #0] +1000140c: f7ff feac bl 10001168 +10001410: 4621 mov r1, r4 +10001412: 462b mov r3, r5 +10001414: 4a20 ldr r2, [pc, #128] @ (10001498 ) +10001416: 4821 ldr r0, [pc, #132] @ (1000149c ) +10001418: 9500 str r5, [sp, #0] +1000141a: f7ff fea5 bl 10001168 +1000141e: 2200 movs r2, #0 +10001420: 2004 movs r0, #4 +10001422: 4631 mov r1, r6 +10001424: 4b1e ldr r3, [pc, #120] @ (100014a0 ) +10001426: f7ff fe31 bl 1000108c +1000142a: 4621 mov r1, r4 +1000142c: 4628 mov r0, r5 +1000142e: 2200 movs r2, #0 +10001430: 4b1c ldr r3, [pc, #112] @ (100014a4 ) +10001432: f7ff fe2b bl 1000108c +10001436: 2200 movs r2, #0 +10001438: 2008 movs r0, #8 +1000143a: 4611 mov r1, r2 +1000143c: 4b1a ldr r3, [pc, #104] @ (100014a8 ) +1000143e: f7ff fe25 bl 1000108c +10001442: 2200 movs r2, #0 +10001444: 2009 movs r0, #9 +10001446: 4611 mov r1, r2 +10001448: 4b17 ldr r3, [pc, #92] @ (100014a8 ) +1000144a: f7ff fe1f bl 1000108c +1000144e: 2200 movs r2, #0 +10001450: 2006 movs r0, #6 +10001452: 4611 mov r1, r2 +10001454: 4b13 ldr r3, [pc, #76] @ (100014a4 ) +10001456: f7ff fe19 bl 1000108c +1000145a: 2200 movs r2, #0 +1000145c: 4b11 ldr r3, [pc, #68] @ (100014a4 ) +1000145e: 2007 movs r0, #7 +10001460: 4611 mov r1, r2 +10001462: f7ff fe13 bl 1000108c +10001466: 2004 movs r0, #4 +10001468: f7ff fe78 bl 1000115c +1000146c: 2400 movs r4, #0 +1000146e: 4b0f ldr r3, [pc, #60] @ (100014ac ) +10001470: fba3 3500 umull r3, r5, r3, r0 +10001474: 0cad lsrs r5, r5, #18 +10001476: b2e0 uxtb r0, r4 +10001478: 4629 mov r1, r5 +1000147a: 3401 adds r4, #1 +1000147c: f7ff feba bl 100011f4 +10001480: 2c06 cmp r4, #6 +10001482: d1f8 bne.n 10001476 +10001484: b002 add sp, #8 +10001486: bd70 pop {r4, r5, r6, pc} +10001488: 40010000 .word 0x40010000 +1000148c: 40013000 .word 0x40013000 +10001490: 59682f00 .word 0x59682f00 +10001494: 40050000 .word 0x40050000 +10001498: 47868c00 .word 0x47868c00 +1000149c: 40058000 .word 0x40058000 +100014a0: 00b71b00 .word 0x00b71b00 +100014a4: 08f0d180 .word 0x08f0d180 +100014a8: 02dc6c00 .word 0x02dc6c00 +100014ac: 431bde83 .word 0x431bde83 + +100014b0 : +100014b0: b086 sub sp, #24 +100014b2: b403 push {r0, r1} +100014b4: fc51 0408 dcp_pxmd r0, r1 +100014b8: e9cd 0102 strd r0, r1, [sp, #8] +100014bc: fc51 0409 dcp_pymd r0, r1 +100014c0: e9cd 0104 strd r0, r1, [sp, #16] +100014c4: ec51 040a dcp_refd r0, r1 +100014c8: e9cd 0106 strd r0, r1, [sp, #24] +100014cc: bc03 pop {r0, r1} +100014ce: 47f0 blx lr + +100014d0 : +100014d0: e8bd 5000 ldmia.w sp!, {ip, lr} +100014d4: ec4e c400 dcp_wxmd ip, lr +100014d8: e8bd 5000 ldmia.w sp!, {ip, lr} +100014dc: ec4e c401 dcp_wymd ip, lr +100014e0: e8bd 5000 ldmia.w sp!, {ip, lr} +100014e4: ec4e c402 dcp_wefd ip, lr +100014e8: bd00 pop {pc} +100014ea: 0000 movs r0, r0 +100014ec: b500 push {lr} +100014ee: f7ff ffdf bl 100014b0 +100014f2: e002 b.n 100014fa <__wrap___aeabi_dadd+0x6> + +100014f4 <__wrap___aeabi_dadd>: +100014f4: fe10 f430 dcp_pcmp APSR_nzcv +100014f8: d4f8 bmi.n 100014ec +100014fa: ec41 0410 dcp_wxup r0, r1 +100014fe: ec43 2411 dcp_wyup r2, r3 +10001502: ee00 0401 dcp_add0 +10001506: ee10 0401 dcp_add1 +1000150a: ee80 0420 dcp_nrdd +1000150e: ec51 0410 dcp_rdda r0, r1 +10001512: 4770 bx lr +10001514: b500 push {lr} +10001516: f7ff ffcb bl 100014b0 +1000151a: e002 b.n 10001522 <__wrap___aeabi_dsub+0x6> + +1000151c <__wrap___aeabi_dsub>: +1000151c: fe10 f430 dcp_pcmp APSR_nzcv +10001520: d4f8 bmi.n 10001514 <__wrap___aeabi_dadd+0x20> +10001522: ec41 0410 dcp_wxup r0, r1 +10001526: ec43 2411 dcp_wyup r2, r3 +1000152a: ee00 0401 dcp_add0 +1000152e: ee10 0421 dcp_sub1 +10001532: ee80 0420 dcp_nrdd +10001536: ec51 0430 dcp_rdds r0, r1 +1000153a: 4770 bx lr +1000153c: b500 push {lr} +1000153e: f7ff ffb7 bl 100014b0 +10001542: e002 b.n 1000154a <__wrap___aeabi_dmul+0x6> + +10001544 <__wrap___aeabi_dmul>: +10001544: fe10 f430 dcp_pcmp APSR_nzcv +10001548: d4f8 bmi.n 1000153c <__wrap___aeabi_dsub+0x20> +1000154a: b510 push {r4, lr} +1000154c: ec41 0410 dcp_wxup r0, r1 +10001550: ec43 2411 dcp_wyup r2, r3 +10001554: ec51 0404 dcp_rxms r0, r1, #0x0 +10001558: ec53 2405 dcp_ryms r2, r3, #0x0 +1000155c: fba0 4c02 umull r4, ip, r0, r2 +10001560: f05f 0e00 movs.w lr, #0 +10001564: fbe0 ce03 umlal ip, lr, r0, r3 +10001568: fbe1 ce02 umlal ip, lr, r1, r2 +1000156c: ec4c 4420 dcp_wxms r4, ip +10001570: 2400 movs r4, #0 +10001572: fbe1 e403 umlal lr, r4, r1, r3 +10001576: ec44 e430 dcp_wxmo lr, r4 +1000157a: ee80 0420 dcp_nrdd +1000157e: ec51 0450 dcp_rddm r0, r1 +10001582: e8bd 4010 ldmia.w sp!, {r4, lr} +10001586: 4770 bx lr +10001588: b500 push {lr} +1000158a: f7ff ff91 bl 100014b0 +1000158e: e002 b.n 10001596 <__wrap___aeabi_ddiv+0x6> + +10001590 <__wrap___aeabi_ddiv>: +10001590: fe10 f430 dcp_pcmp APSR_nzcv +10001594: d4f8 bmi.n 10001588 <__wrap___aeabi_dmul+0x44> +10001596: ec41 0410 dcp_wxup r0, r1 +1000159a: ec43 2411 dcp_wyup r2, r3 +1000159e: ec51 0421 dcp_rymr r0, r1 +100015a2: fba0 1201 umull r1, r2, r0, r1 +100015a6: ea6f 0282 mvn.w r2, r2, lsl #2 +100015aa: fb52 0010 smmlar r0, r2, r0, r0 +100015ae: fb52 f212 smmulr r2, r2, r2 +100015b2: fb52 0010 smmlar r0, r2, r0, r0 +100015b6: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +100015ba: ec53 2404 dcp_rxms r2, r3, #0x0 +100015be: fb5c f113 smmulr r1, ip, r3 +100015c2: ec53 2415 dcp_ryms r2, r3, #0x1 +100015c6: fba1 2002 umull r2, r0, r1, r2 +100015ca: fb01 0003 mla r0, r1, r3, r0 +100015ce: ec53 2444 dcp_rxms r2, r3, #0x4 +100015d2: eba2 0000 sub.w r0, r2, r0 +100015d6: fb50 f21c smmulr r2, r0, ip +100015da: ea4f 1311 mov.w r3, r1, lsr #4 +100015de: eb12 7001 adds.w r0, r2, r1, lsl #28 +100015e2: eb43 71e2 adc.w r1, r3, r2, asr #31 +100015e6: ea40 5051 orr.w r0, r0, r1, lsr #21 +100015ea: ea20 5091 bic.w r0, r0, r1, lsr #22 +100015ee: f020 0007 bic.w r0, r0, #7 +100015f2: ec53 2475 dcp_ryms r2, r3, #0x7 +100015f6: fba0 3c02 umull r3, ip, r0, r2 +100015fa: ec53 2475 dcp_ryms r2, r3, #0x7 +100015fe: fb00 cc03 mla ip, r0, r3, ip +10001602: fb01 cc02 mla ip, r1, r2, ip +10001606: ec53 2404 dcp_rxms r2, r3, #0x0 +1000160a: ebac 4c82 sub.w ip, ip, r2, lsl #18 +1000160e: ea40 705c orr.w r0, r0, ip, lsr #29 +10001612: f1a0 0001 sub.w r0, r0, #1 +10001616: ec41 0440 dcp_wxdd r0, r1 +1000161a: ee80 0420 dcp_nrdd +1000161e: ec51 0470 dcp_rddd r0, r1 +10001622: 4770 bx lr +10001624: b500 push {lr} +10001626: f7ff ff43 bl 100014b0 +1000162a: e002 b.n 10001632 <__wrap___aeabi_i2d+0x6> + +1000162c <__wrap___aeabi_i2d>: +1000162c: fe10 f430 dcp_pcmp APSR_nzcv +10001630: d4f8 bmi.n 10001624 <__wrap___aeabi_ddiv+0x94> +10001632: ec40 0470 dcp_wxic r0, r0 +10001636: ee00 0401 dcp_add0 +1000163a: ee10 0421 dcp_sub1 +1000163e: ee80 0420 dcp_nrdd +10001642: ec51 0430 dcp_rdds r0, r1 +10001646: 4770 bx lr +10001648: b500 push {lr} +1000164a: f7ff ff31 bl 100014b0 +1000164e: e002 b.n 10001656 <__wrap___aeabi_ui2d+0x6> + +10001650 <__wrap___aeabi_ui2d>: +10001650: fe10 f430 dcp_pcmp APSR_nzcv +10001654: d4f8 bmi.n 10001648 <__wrap___aeabi_i2d+0x1c> +10001656: ec40 0460 dcp_wxuc r0, r0 +1000165a: ee00 0401 dcp_add0 +1000165e: ee10 0421 dcp_sub1 +10001662: ee80 0420 dcp_nrdd +10001666: ec51 0430 dcp_rdds r0, r1 +1000166a: 4770 bx lr +1000166c: b500 push {lr} +1000166e: f7ff ff1f bl 100014b0 +10001672: e002 b.n 1000167a + +10001674 <__wrap___aeabi_d2iz>: +10001674: fe10 f430 dcp_pcmp APSR_nzcv +10001678: d4f8 bmi.n 1000166c <__wrap___aeabi_ui2d+0x1c> + +1000167a : +1000167a: ec41 0480 dcp_wxdc r0, r1 +1000167e: ee00 0401 dcp_add0 +10001682: ee10 0401 dcp_add1 +10001686: ee80 0440 dcp_ntdc +1000168a: ee10 0413 dcp_rdic r0 +1000168e: 4770 bx lr +10001690: b500 push {lr} +10001692: f7ff ff0d bl 100014b0 +10001696: e002 b.n 1000169e + +10001698 <__wrap___aeabi_d2uiz>: +10001698: fe10 f430 dcp_pcmp APSR_nzcv +1000169c: d4f8 bmi.n 10001690 + +1000169e : +1000169e: ec41 0480 dcp_wxdc r0, r1 +100016a2: ee00 0401 dcp_add0 +100016a6: ee10 0401 dcp_add1 +100016aa: ee80 0440 dcp_ntdc +100016ae: ee10 0433 dcp_rduc r0 +100016b2: 4770 bx lr +100016b4: b500 push {lr} +100016b6: f7ff fefb bl 100014b0 +100016ba: e002 b.n 100016c2 <__wrap___aeabi_dcmpun+0x6> + +100016bc <__wrap___aeabi_dcmpun>: +100016bc: fe10 f430 dcp_pcmp APSR_nzcv +100016c0: d4f8 bmi.n 100016b4 +100016c2: ec41 0410 dcp_wxup r0, r1 +100016c6: ec43 2411 dcp_wyup r2, r3 +100016ca: ee00 0401 dcp_add0 +100016ce: ee10 0430 dcp_rcmp r0 +100016d2: f3c0 7000 ubfx r0, r0, #28, #1 +100016d6: 4770 bx lr +100016d8: b500 push {lr} +100016da: f7ff fee9 bl 100014b0 +100016de: e002 b.n 100016e6 <__wrap___aeabi_dcmplt+0x6> + +100016e0 <__wrap___aeabi_dcmplt>: +100016e0: fe10 f430 dcp_pcmp APSR_nzcv +100016e4: d4f8 bmi.n 100016d8 <__wrap___aeabi_dcmpun+0x1c> +100016e6: ec43 2410 dcp_wxup r2, r3 +100016ea: ec41 0411 dcp_wyup r0, r1 +100016ee: ee00 0401 dcp_add0 +100016f2: ee10 f430 dcp_rcmp APSR_nzcv +100016f6: bf8c ite hi +100016f8: 2001 movhi r0, #1 +100016fa: 2000 movls r0, #0 +100016fc: 4770 bx lr +100016fe: bf00 nop +10001700: b500 push {lr} +10001702: f7ff fed5 bl 100014b0 +10001706: e002 b.n 1000170e <__wrap___aeabi_dcmple+0x6> + +10001708 <__wrap___aeabi_dcmple>: +10001708: fe10 f430 dcp_pcmp APSR_nzcv +1000170c: d4f8 bmi.n 10001700 <__wrap___aeabi_dcmplt+0x20> +1000170e: ec43 2410 dcp_wxup r2, r3 +10001712: ec41 0411 dcp_wyup r0, r1 +10001716: ee00 0401 dcp_add0 +1000171a: ee10 f430 dcp_rcmp APSR_nzcv +1000171e: bf2c ite cs +10001720: 2001 movcs r0, #1 +10001722: 2000 movcc r0, #0 +10001724: 4770 bx lr +10001726: bf00 nop +10001728: b500 push {lr} +1000172a: f7ff fec1 bl 100014b0 +1000172e: e002 b.n 10001736 <__wrap___aeabi_dcmpge+0x6> + +10001730 <__wrap___aeabi_dcmpge>: +10001730: fe10 f430 dcp_pcmp APSR_nzcv +10001734: d4f8 bmi.n 10001728 <__wrap___aeabi_dcmple+0x20> +10001736: ec41 0410 dcp_wxup r0, r1 +1000173a: ec43 2411 dcp_wyup r2, r3 +1000173e: ee00 0401 dcp_add0 +10001742: ee10 f430 dcp_rcmp APSR_nzcv +10001746: bf2c ite cs +10001748: 2001 movcs r0, #1 +1000174a: 2000 movcc r0, #0 +1000174c: 4770 bx lr +1000174e: bf00 nop +10001750: b500 push {lr} +10001752: f7ff fead bl 100014b0 +10001756: e002 b.n 1000175e <__wrap___aeabi_dcmpgt+0x6> + +10001758 <__wrap___aeabi_dcmpgt>: +10001758: fe10 f430 dcp_pcmp APSR_nzcv +1000175c: d4f8 bmi.n 10001750 <__wrap___aeabi_dcmpge+0x20> +1000175e: ec41 0410 dcp_wxup r0, r1 +10001762: ec43 2411 dcp_wyup r2, r3 +10001766: ee00 0401 dcp_add0 +1000176a: ee10 f430 dcp_rcmp APSR_nzcv +1000176e: bf8c ite hi +10001770: 2001 movhi r0, #1 +10001772: 2000 movls r0, #0 +10001774: 4770 bx lr +10001776: bf00 nop + +10001778 <_out_null>: +10001778: 4770 bx lr +1000177a: bf00 nop + +1000177c <_out_rev>: +1000177c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001780: b083 sub sp, #12 +10001782: 4699 mov r9, r3 +10001784: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001788: 9b0f ldr r3, [sp, #60] @ 0x3c +1000178a: 4688 mov r8, r1 +1000178c: 4611 mov r1, r2 +1000178e: 079a lsls r2, r3, #30 +10001790: 4607 mov r7, r0 +10001792: d116 bne.n 100017c2 <_out_rev+0x46> +10001794: 45da cmp sl, fp +10001796: d23a bcs.n 1000180e <_out_rev+0x92> +10001798: 460c mov r4, r1 +1000179a: 460d mov r5, r1 +1000179c: ebab 060a sub.w r6, fp, sl +100017a0: 440e add r6, r1 +100017a2: 4622 mov r2, r4 +100017a4: 464b mov r3, r9 +100017a6: 4641 mov r1, r8 +100017a8: 2020 movs r0, #32 +100017aa: 3401 adds r4, #1 +100017ac: 47b8 blx r7 +100017ae: 42b4 cmp r4, r6 +100017b0: d1f7 bne.n 100017a2 <_out_rev+0x26> +100017b2: 4629 mov r1, r5 +100017b4: f1ba 0f00 cmp.w sl, #0 +100017b8: d108 bne.n 100017cc <_out_rev+0x50> +100017ba: 4620 mov r0, r4 +100017bc: b003 add sp, #12 +100017be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100017c2: 460c mov r4, r1 +100017c4: f1ba 0f00 cmp.w sl, #0 +100017c8: d010 beq.n 100017ec <_out_rev+0x70> +100017ca: 460e mov r6, r1 +100017cc: 4655 mov r5, sl +100017ce: 9b0c ldr r3, [sp, #48] @ 0x30 +100017d0: 442e add r6, r5 +100017d2: 449a add sl, r3 +100017d4: 9101 str r1, [sp, #4] +100017d6: 1b72 subs r2, r6, r5 +100017d8: 464b mov r3, r9 +100017da: 3d01 subs r5, #1 +100017dc: 4641 mov r1, r8 +100017de: f81a 0d01 ldrb.w r0, [sl, #-1]! +100017e2: 4634 mov r4, r6 +100017e4: 47b8 blx r7 +100017e6: 2d00 cmp r5, #0 +100017e8: d1f5 bne.n 100017d6 <_out_rev+0x5a> +100017ea: 9901 ldr r1, [sp, #4] +100017ec: 9b0f ldr r3, [sp, #60] @ 0x3c +100017ee: 079b lsls r3, r3, #30 +100017f0: d5e3 bpl.n 100017ba <_out_rev+0x3e> +100017f2: 1a65 subs r5, r4, r1 +100017f4: 45ab cmp fp, r5 +100017f6: d9e0 bls.n 100017ba <_out_rev+0x3e> +100017f8: 4622 mov r2, r4 +100017fa: 464b mov r3, r9 +100017fc: 4641 mov r1, r8 +100017fe: 2020 movs r0, #32 +10001800: 3501 adds r5, #1 +10001802: 47b8 blx r7 +10001804: 455d cmp r5, fp +10001806: f104 0401 add.w r4, r4, #1 +1000180a: d3f5 bcc.n 100017f8 <_out_rev+0x7c> +1000180c: e7d5 b.n 100017ba <_out_rev+0x3e> +1000180e: 460c mov r4, r1 +10001810: f1ba 0f00 cmp.w sl, #0 +10001814: d1d9 bne.n 100017ca <_out_rev+0x4e> +10001816: e7d0 b.n 100017ba <_out_rev+0x3e> + +10001818 <_ntoa_format>: +10001818: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000181c: 9f0f ldr r7, [sp, #60] @ 0x3c +1000181e: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001822: f017 0f02 tst.w r7, #2 +10001826: 9c0a ldr r4, [sp, #40] @ 0x28 +10001828: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +1000182c: 9d0e ldr r5, [sp, #56] @ 0x38 +1000182e: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001832: d144 bne.n 100018be <_ntoa_format+0xa6> +10001834: bbf5 cbnz r5, 100018b4 <_ntoa_format+0x9c> +10001836: 42b4 cmp r4, r6 +10001838: d241 bcs.n 100018be <_ntoa_format+0xa6> +1000183a: f007 0b01 and.w fp, r7, #1 +1000183e: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001842: f04f 0e30 mov.w lr, #48 @ 0x30 +10001846: 44c4 add ip, r8 +10001848: e004 b.n 10001854 <_ntoa_format+0x3c> +1000184a: 3401 adds r4, #1 +1000184c: 42a6 cmp r6, r4 +1000184e: f80c ef01 strb.w lr, [ip, #1]! +10001852: d901 bls.n 10001858 <_ntoa_format+0x40> +10001854: 2c20 cmp r4, #32 +10001856: d1f8 bne.n 1000184a <_ntoa_format+0x32> +10001858: f1bb 0f00 cmp.w fp, #0 +1000185c: f000 8088 beq.w 10001970 <_ntoa_format+0x158> +10001860: 42a5 cmp r5, r4 +10001862: d92c bls.n 100018be <_ntoa_format+0xa6> +10001864: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001868: f04f 0e30 mov.w lr, #48 @ 0x30 +1000186c: 44c4 add ip, r8 +1000186e: e004 b.n 1000187a <_ntoa_format+0x62> +10001870: 3401 adds r4, #1 +10001872: 42ac cmp r4, r5 +10001874: f80c ef01 strb.w lr, [ip, #1]! +10001878: d021 beq.n 100018be <_ntoa_format+0xa6> +1000187a: 2c20 cmp r4, #32 +1000187c: d1f8 bne.n 10001870 <_ntoa_format+0x58> +1000187e: f017 0f10 tst.w r7, #16 +10001882: d00e beq.n 100018a2 <_ntoa_format+0x8a> +10001884: f417 6f80 tst.w r7, #1024 @ 0x400 +10001888: d154 bne.n 10001934 <_ntoa_format+0x11c> +1000188a: 42a6 cmp r6, r4 +1000188c: d063 beq.n 10001956 <_ntoa_format+0x13e> +1000188e: 42a5 cmp r5, r4 +10001890: d061 beq.n 10001956 <_ntoa_format+0x13e> +10001892: f1b9 0f10 cmp.w r9, #16 +10001896: d050 beq.n 1000193a <_ntoa_format+0x122> +10001898: f1b9 0f02 cmp.w r9, #2 +1000189c: d056 beq.n 1000194c <_ntoa_format+0x134> +1000189e: 2c20 cmp r4, #32 +100018a0: d129 bne.n 100018f6 <_ntoa_format+0xde> +100018a2: 2420 movs r4, #32 +100018a4: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100018a8: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100018ac: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100018b0: f7ff bf64 b.w 1000177c <_out_rev> +100018b4: f017 0b01 ands.w fp, r7, #1 +100018b8: d134 bne.n 10001924 <_ntoa_format+0x10c> +100018ba: 42b4 cmp r4, r6 +100018bc: d3bf bcc.n 1000183e <_ntoa_format+0x26> +100018be: f017 0f10 tst.w r7, #16 +100018c2: d01e beq.n 10001902 <_ntoa_format+0xea> +100018c4: f417 6f80 tst.w r7, #1024 @ 0x400 +100018c8: d1e3 bne.n 10001892 <_ntoa_format+0x7a> +100018ca: 2c00 cmp r4, #0 +100018cc: d1dd bne.n 1000188a <_ntoa_format+0x72> +100018ce: f1b9 0f10 cmp.w r9, #16 +100018d2: d063 beq.n 1000199c <_ntoa_format+0x184> +100018d4: f1b9 0f02 cmp.w r9, #2 +100018d8: d077 beq.n 100019ca <_ntoa_format+0x1b2> +100018da: 2430 movs r4, #48 @ 0x30 +100018dc: f888 4000 strb.w r4, [r8] +100018e0: 2401 movs r4, #1 +100018e2: f1ba 0f00 cmp.w sl, #0 +100018e6: d111 bne.n 1000190c <_ntoa_format+0xf4> +100018e8: 077e lsls r6, r7, #29 +100018ea: d548 bpl.n 1000197e <_ntoa_format+0x166> +100018ec: 262b movs r6, #43 @ 0x2b +100018ee: f808 6004 strb.w r6, [r8, r4] +100018f2: 3401 adds r4, #1 +100018f4: e7d6 b.n 100018a4 <_ntoa_format+0x8c> +100018f6: 4626 mov r6, r4 +100018f8: 3401 adds r4, #1 +100018fa: f04f 0c30 mov.w ip, #48 @ 0x30 +100018fe: f808 c006 strb.w ip, [r8, r6] +10001902: 2c20 cmp r4, #32 +10001904: d0cd beq.n 100018a2 <_ntoa_format+0x8a> +10001906: f1ba 0f00 cmp.w sl, #0 +1000190a: d0ed beq.n 100018e8 <_ntoa_format+0xd0> +1000190c: 262d movs r6, #45 @ 0x2d +1000190e: f808 6004 strb.w r6, [r8, r4] +10001912: 3401 adds r4, #1 +10001914: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001918: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +1000191c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001920: f7ff bf2c b.w 1000177c <_out_rev> +10001924: f1ba 0f00 cmp.w sl, #0 +10001928: d030 beq.n 1000198c <_ntoa_format+0x174> +1000192a: 42b4 cmp r4, r6 +1000192c: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001930: d385 bcc.n 1000183e <_ntoa_format+0x26> +10001932: e795 b.n 10001860 <_ntoa_format+0x48> +10001934: f1b9 0f10 cmp.w r9, #16 +10001938: d1b3 bne.n 100018a2 <_ntoa_format+0x8a> +1000193a: 06be lsls r6, r7, #26 +1000193c: d53b bpl.n 100019b6 <_ntoa_format+0x19e> +1000193e: 2c20 cmp r4, #32 +10001940: d0af beq.n 100018a2 <_ntoa_format+0x8a> +10001942: 2658 movs r6, #88 @ 0x58 +10001944: f808 6004 strb.w r6, [r8, r4] +10001948: 3401 adds r4, #1 +1000194a: e7a8 b.n 1000189e <_ntoa_format+0x86> +1000194c: 2c20 cmp r4, #32 +1000194e: d0a8 beq.n 100018a2 <_ntoa_format+0x8a> +10001950: 4626 mov r6, r4 +10001952: 3401 adds r4, #1 +10001954: e007 b.n 10001966 <_ntoa_format+0x14e> +10001956: 1e66 subs r6, r4, #1 +10001958: d0b9 beq.n 100018ce <_ntoa_format+0xb6> +1000195a: f1b9 0f10 cmp.w r9, #16 +1000195e: d036 beq.n 100019ce <_ntoa_format+0x1b6> +10001960: f1b9 0f02 cmp.w r9, #2 +10001964: d1c9 bne.n 100018fa <_ntoa_format+0xe2> +10001966: f04f 0c62 mov.w ip, #98 @ 0x62 +1000196a: f808 c006 strb.w ip, [r8, r6] +1000196e: e796 b.n 1000189e <_ntoa_format+0x86> +10001970: f017 0f10 tst.w r7, #16 +10001974: d0c5 beq.n 10001902 <_ntoa_format+0xea> +10001976: f417 6f80 tst.w r7, #1024 @ 0x400 +1000197a: d086 beq.n 1000188a <_ntoa_format+0x72> +1000197c: e789 b.n 10001892 <_ntoa_format+0x7a> +1000197e: 073e lsls r6, r7, #28 +10001980: d590 bpl.n 100018a4 <_ntoa_format+0x8c> +10001982: 2620 movs r6, #32 +10001984: f808 6004 strb.w r6, [r8, r4] +10001988: 3401 adds r4, #1 +1000198a: e78b b.n 100018a4 <_ntoa_format+0x8c> +1000198c: f017 0f0c tst.w r7, #12 +10001990: d000 beq.n 10001994 <_ntoa_format+0x17c> +10001992: 3d01 subs r5, #1 +10001994: 42b4 cmp r4, r6 +10001996: f4ff af52 bcc.w 1000183e <_ntoa_format+0x26> +1000199a: e761 b.n 10001860 <_ntoa_format+0x48> +1000199c: 06bc lsls r4, r7, #26 +1000199e: d412 bmi.n 100019c6 <_ntoa_format+0x1ae> +100019a0: 2478 movs r4, #120 @ 0x78 +100019a2: f888 4000 strb.w r4, [r8] +100019a6: 2430 movs r4, #48 @ 0x30 +100019a8: f888 4001 strb.w r4, [r8, #1] +100019ac: 2402 movs r4, #2 +100019ae: f1ba 0f00 cmp.w sl, #0 +100019b2: d099 beq.n 100018e8 <_ntoa_format+0xd0> +100019b4: e7aa b.n 1000190c <_ntoa_format+0xf4> +100019b6: 2c20 cmp r4, #32 +100019b8: f43f af73 beq.w 100018a2 <_ntoa_format+0x8a> +100019bc: 2678 movs r6, #120 @ 0x78 +100019be: f808 6004 strb.w r6, [r8, r4] +100019c2: 3401 adds r4, #1 +100019c4: e76b b.n 1000189e <_ntoa_format+0x86> +100019c6: 2458 movs r4, #88 @ 0x58 +100019c8: e7eb b.n 100019a2 <_ntoa_format+0x18a> +100019ca: 2462 movs r4, #98 @ 0x62 +100019cc: e7e9 b.n 100019a2 <_ntoa_format+0x18a> +100019ce: f017 0f20 tst.w r7, #32 +100019d2: f1a4 0c02 sub.w ip, r4, #2 +100019d6: d004 beq.n 100019e2 <_ntoa_format+0x1ca> +100019d8: f04f 0e58 mov.w lr, #88 @ 0x58 +100019dc: f808 e00c strb.w lr, [r8, ip] +100019e0: e78b b.n 100018fa <_ntoa_format+0xe2> +100019e2: f04f 0e78 mov.w lr, #120 @ 0x78 +100019e6: f808 e00c strb.w lr, [r8, ip] +100019ea: e786 b.n 100018fa <_ntoa_format+0xe2> + +100019ec <_out_char>: +100019ec: b900 cbnz r0, 100019f0 <_out_char+0x4> +100019ee: 4770 bx lr +100019f0: f001 bb72 b.w 100030d8 <__wrap_putchar> + +100019f4 <_out_fct>: +100019f4: b110 cbz r0, 100019fc <_out_fct+0x8> +100019f6: e9d1 3100 ldrd r3, r1, [r1] +100019fa: 4718 bx r3 +100019fc: 4770 bx lr +100019fe: bf00 nop + +10001a00 <_ftoa>: +10001a00: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a04: b097 sub sp, #92 @ 0x5c +10001a06: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001a0a: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001a0e: 4607 mov r7, r0 +10001a10: 4688 mov r8, r1 +10001a12: ec51 0b17 vmov r0, r1, d7 +10001a16: 9c24 ldr r4, [sp, #144] @ 0x90 +10001a18: 4699 mov r9, r3 +10001a1a: 920c str r2, [sp, #48] @ 0x30 +10001a1c: 460b mov r3, r1 +10001a1e: 4602 mov r2, r0 +10001a20: ed8d 7b04 vstr d7, [sp, #16] +10001a24: 9407 str r4, [sp, #28] +10001a26: f7ff fe49 bl 100016bc <__wrap___aeabi_dcmpun> +10001a2a: 2800 cmp r0, #0 +10001a2c: f040 81f4 bne.w 10001e18 <_ftoa+0x418> +10001a30: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a34: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a38: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001a3c: f7ff fe50 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a40: 2800 cmp r0, #0 +10001a42: f040 811b bne.w 10001c7c <_ftoa+0x27c> +10001a46: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a4a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a4e: 4bac ldr r3, [pc, #688] @ (10001d00 <_ftoa+0x300>) +10001a50: f7ff fe82 bl 10001758 <__wrap___aeabi_dcmpgt> +10001a54: 2800 cmp r0, #0 +10001a56: f040 80ee bne.w 10001c36 <_ftoa+0x236> +10001a5a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a5e: a3a4 add r3, pc, #656 @ (adr r3, 10001cf0 <_ftoa+0x2f0>) +10001a60: e9d3 2300 ldrd r2, r3, [r3] +10001a64: f7ff fe78 bl 10001758 <__wrap___aeabi_dcmpgt> +10001a68: 2800 cmp r0, #0 +10001a6a: f040 80d3 bne.w 10001c14 <_ftoa+0x214> +10001a6e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a72: a3a1 add r3, pc, #644 @ (adr r3, 10001cf8 <_ftoa+0x2f8>) +10001a74: e9d3 2300 ldrd r2, r3, [r3] +10001a78: f7ff fe32 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a7c: 2800 cmp r0, #0 +10001a7e: f040 80c9 bne.w 10001c14 <_ftoa+0x214> +10001a82: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a86: 2200 movs r2, #0 +10001a88: 2300 movs r3, #0 +10001a8a: f7ff fe29 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a8e: 2800 cmp r0, #0 +10001a90: f040 80e8 bne.w 10001c64 <_ftoa+0x264> +10001a94: 4623 mov r3, r4 +10001a96: 900d str r0, [sp, #52] @ 0x34 +10001a98: f413 6f80 tst.w r3, #1024 @ 0x400 +10001a9c: bf08 it eq +10001a9e: 2506 moveq r5, #6 +10001aa0: 2130 movs r1, #48 @ 0x30 +10001aa2: 462b mov r3, r5 +10001aa4: aa0e add r2, sp, #56 @ 0x38 +10001aa6: f1a5 0620 sub.w r6, r5, #32 +10001aaa: e005 b.n 10001ab8 <_ftoa+0xb8> +10001aac: 3b01 subs r3, #1 +10001aae: 42b3 cmp r3, r6 +10001ab0: f802 1b01 strb.w r1, [r2], #1 +10001ab4: f000 8193 beq.w 10001dde <_ftoa+0x3de> +10001ab8: 2b09 cmp r3, #9 +10001aba: d8f7 bhi.n 10001aac <_ftoa+0xac> +10001abc: 461e mov r6, r3 +10001abe: 1aed subs r5, r5, r3 +10001ac0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ac4: f7ff fdd6 bl 10001674 <__wrap___aeabi_d2iz> +10001ac8: 4b8e ldr r3, [pc, #568] @ (10001d04 <_ftoa+0x304>) +10001aca: 4604 mov r4, r0 +10001acc: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001ad0: ed93 7b00 vldr d7, [r3] +10001ad4: ed8d 7b08 vstr d7, [sp, #32] +10001ad8: f7ff fda8 bl 1000162c <__wrap___aeabi_i2d> +10001adc: 4602 mov r2, r0 +10001ade: 460b mov r3, r1 +10001ae0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ae4: f7ff fd1a bl 1000151c <__wrap___aeabi_dsub> +10001ae8: e9dd 2308 ldrd r2, r3, [sp, #32] +10001aec: f7ff fd2a bl 10001544 <__wrap___aeabi_dmul> +10001af0: 4602 mov r2, r0 +10001af2: 460b mov r3, r1 +10001af4: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001af8: f7ff fdce bl 10001698 <__wrap___aeabi_d2uiz> +10001afc: 4682 mov sl, r0 +10001afe: f7ff fda7 bl 10001650 <__wrap___aeabi_ui2d> +10001b02: 4602 mov r2, r0 +10001b04: 460b mov r3, r1 +10001b06: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001b0a: f7ff fd07 bl 1000151c <__wrap___aeabi_dsub> +10001b0e: 4602 mov r2, r0 +10001b10: 460b mov r3, r1 +10001b12: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001b16: 2200 movs r2, #0 +10001b18: 4b7b ldr r3, [pc, #492] @ (10001d08 <_ftoa+0x308>) +10001b1a: f7ff fe1d bl 10001758 <__wrap___aeabi_dcmpgt> +10001b1e: 2800 cmp r0, #0 +10001b20: f000 80fe beq.w 10001d20 <_ftoa+0x320> +10001b24: f10a 0a01 add.w sl, sl, #1 +10001b28: 4650 mov r0, sl +10001b2a: f7ff fd91 bl 10001650 <__wrap___aeabi_ui2d> +10001b2e: 4602 mov r2, r0 +10001b30: 460b mov r3, r1 +10001b32: e9dd 0108 ldrd r0, r1, [sp, #32] +10001b36: f7ff fde7 bl 10001708 <__wrap___aeabi_dcmple> +10001b3a: b110 cbz r0, 10001b42 <_ftoa+0x142> +10001b3c: f04f 0a00 mov.w sl, #0 +10001b40: 3401 adds r4, #1 +10001b42: 2e00 cmp r6, #0 +10001b44: f000 80fd beq.w 10001d42 <_ftoa+0x342> +10001b48: 1e68 subs r0, r5, #1 +10001b4a: ab0e add r3, sp, #56 @ 0x38 +10001b4c: f8df c1cc ldr.w ip, [pc, #460] @ 10001d1c <_ftoa+0x31c> +10001b50: 4418 add r0, r3 +10001b52: e00f b.n 10001b74 <_ftoa+0x174> +10001b54: fbac 210a umull r2, r1, ip, sl +10001b58: 08c9 lsrs r1, r1, #3 +10001b5a: eb01 0281 add.w r2, r1, r1, lsl #2 +10001b5e: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001b62: 3230 adds r2, #48 @ 0x30 +10001b64: f1ba 0f09 cmp.w sl, #9 +10001b68: f800 2f01 strb.w r2, [r0, #1]! +10001b6c: f240 811c bls.w 10001da8 <_ftoa+0x3a8> +10001b70: 468a mov sl, r1 +10001b72: 461d mov r5, r3 +10001b74: 2d20 cmp r5, #32 +10001b76: f105 0301 add.w r3, r5, #1 +10001b7a: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001b7e: d1e9 bne.n 10001b54 <_ftoa+0x154> +10001b80: 2520 movs r5, #32 +10001b82: 1e69 subs r1, r5, #1 +10001b84: ab0e add r3, sp, #56 @ 0x38 +10001b86: 4861 ldr r0, [pc, #388] @ (10001d0c <_ftoa+0x30c>) +10001b88: 4419 add r1, r3 +10001b8a: e010 b.n 10001bae <_ftoa+0x1ae> +10001b8c: fb80 6204 smull r6, r2, r0, r4 +10001b90: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001b94: eb03 0283 add.w r2, r3, r3, lsl #2 +10001b98: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001b9c: f104 0230 add.w r2, r4, #48 @ 0x30 +10001ba0: 3501 adds r5, #1 +10001ba2: 461c mov r4, r3 +10001ba4: f801 2f01 strb.w r2, [r1, #1]! +10001ba8: 2b00 cmp r3, #0 +10001baa: f000 80eb beq.w 10001d84 <_ftoa+0x384> +10001bae: 2d20 cmp r5, #32 +10001bb0: ea4f 73e4 mov.w r3, r4, asr #31 +10001bb4: d1ea bne.n 10001b8c <_ftoa+0x18c> +10001bb6: 9b07 ldr r3, [sp, #28] +10001bb8: f003 0303 and.w r3, r3, #3 +10001bbc: 2b01 cmp r3, #1 +10001bbe: d118 bne.n 10001bf2 <_ftoa+0x1f2> +10001bc0: f1bb 0f00 cmp.w fp, #0 +10001bc4: d015 beq.n 10001bf2 <_ftoa+0x1f2> +10001bc6: 9b0d ldr r3, [sp, #52] @ 0x34 +10001bc8: 2b00 cmp r3, #0 +10001bca: f000 810a beq.w 10001de2 <_ftoa+0x3e2> +10001bce: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001bd2: f1bb 0f20 cmp.w fp, #32 +10001bd6: d90c bls.n 10001bf2 <_ftoa+0x1f2> +10001bd8: 1e6b subs r3, r5, #1 +10001bda: a90e add r1, sp, #56 @ 0x38 +10001bdc: 2230 movs r2, #48 @ 0x30 +10001bde: 440b add r3, r1 +10001be0: e005 b.n 10001bee <_ftoa+0x1ee> +10001be2: 3501 adds r5, #1 +10001be4: 455d cmp r5, fp +10001be6: f803 2f01 strb.w r2, [r3, #1]! +10001bea: f080 80d1 bcs.w 10001d90 <_ftoa+0x390> +10001bee: 2d20 cmp r5, #32 +10001bf0: d1f7 bne.n 10001be2 <_ftoa+0x1e2> +10001bf2: 9b07 ldr r3, [sp, #28] +10001bf4: ac0e add r4, sp, #56 @ 0x38 +10001bf6: e9cd b302 strd fp, r3, [sp, #8] +10001bfa: 4641 mov r1, r8 +10001bfc: 464b mov r3, r9 +10001bfe: 4638 mov r0, r7 +10001c00: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c02: 9501 str r5, [sp, #4] +10001c04: 9400 str r4, [sp, #0] +10001c06: f7ff fdb9 bl 1000177c <_out_rev> +10001c0a: 4682 mov sl, r0 +10001c0c: 4650 mov r0, sl +10001c0e: b017 add sp, #92 @ 0x5c +10001c10: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001c14: 9b07 ldr r3, [sp, #28] +10001c16: ed9d 7b04 vldr d7, [sp, #16] +10001c1a: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001c1e: 4641 mov r1, r8 +10001c20: 464b mov r3, r9 +10001c22: 4638 mov r0, r7 +10001c24: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c26: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001c2a: 9522 str r5, [sp, #136] @ 0x88 +10001c2c: b017 add sp, #92 @ 0x5c +10001c2e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c32: f000 b945 b.w 10001ec0 <_etoa> +10001c36: 0761 lsls r1, r4, #29 +10001c38: 4623 mov r3, r4 +10001c3a: bf4c ite mi +10001c3c: 2304 movmi r3, #4 +10001c3e: 2303 movpl r3, #3 +10001c40: 4641 mov r1, r8 +10001c42: 9321 str r3, [sp, #132] @ 0x84 +10001c44: 4638 mov r0, r7 +10001c46: 464b mov r3, r9 +10001c48: 9a07 ldr r2, [sp, #28] +10001c4a: bf48 it mi +10001c4c: 4c30 ldrmi r4, [pc, #192] @ (10001d10 <_ftoa+0x310>) +10001c4e: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001c52: bf58 it pl +10001c54: 4c2f ldrpl r4, [pc, #188] @ (10001d14 <_ftoa+0x314>) +10001c56: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c58: 9420 str r4, [sp, #128] @ 0x80 +10001c5a: b017 add sp, #92 @ 0x5c +10001c5c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c60: f7ff bd8c b.w 1000177c <_out_rev> +10001c64: e9dd 2304 ldrd r2, r3, [sp, #16] +10001c68: 2000 movs r0, #0 +10001c6a: 2100 movs r1, #0 +10001c6c: f7ff fc56 bl 1000151c <__wrap___aeabi_dsub> +10001c70: 2301 movs r3, #1 +10001c72: e9cd 0104 strd r0, r1, [sp, #16] +10001c76: 930d str r3, [sp, #52] @ 0x34 +10001c78: 4623 mov r3, r4 +10001c7a: e70d b.n 10001a98 <_ftoa+0x98> +10001c7c: 4623 mov r3, r4 +10001c7e: 079c lsls r4, r3, #30 +10001c80: f040 80aa bne.w 10001dd8 <_ftoa+0x3d8> +10001c84: f1bb 0f04 cmp.w fp, #4 +10001c88: f240 80a6 bls.w 10001dd8 <_ftoa+0x3d8> +10001c8c: 9b0c ldr r3, [sp, #48] @ 0x30 +10001c8e: 461d mov r5, r3 +10001c90: 1f1c subs r4, r3, #4 +10001c92: eb04 0a0b add.w sl, r4, fp +10001c96: 462a mov r2, r5 +10001c98: 464b mov r3, r9 +10001c9a: 4641 mov r1, r8 +10001c9c: 2020 movs r0, #32 +10001c9e: 3501 adds r5, #1 +10001ca0: 47b8 blx r7 +10001ca2: 45aa cmp sl, r5 +10001ca4: d1f7 bne.n 10001c96 <_ftoa+0x296> +10001ca6: 4655 mov r5, sl +10001ca8: 4c1b ldr r4, [pc, #108] @ (10001d18 <_ftoa+0x318>) +10001caa: 1f26 subs r6, r4, #4 +10001cac: f814 0d01 ldrb.w r0, [r4, #-1]! +10001cb0: 462a mov r2, r5 +10001cb2: 464b mov r3, r9 +10001cb4: 4641 mov r1, r8 +10001cb6: 47b8 blx r7 +10001cb8: 42b4 cmp r4, r6 +10001cba: f105 0501 add.w r5, r5, #1 +10001cbe: d1f5 bne.n 10001cac <_ftoa+0x2ac> +10001cc0: 9b07 ldr r3, [sp, #28] +10001cc2: f10a 0a04 add.w sl, sl, #4 +10001cc6: 0798 lsls r0, r3, #30 +10001cc8: d5a0 bpl.n 10001c0c <_ftoa+0x20c> +10001cca: 9c0c ldr r4, [sp, #48] @ 0x30 +10001ccc: ebaa 0304 sub.w r3, sl, r4 +10001cd0: 459b cmp fp, r3 +10001cd2: d99b bls.n 10001c0c <_ftoa+0x20c> +10001cd4: 4652 mov r2, sl +10001cd6: 464b mov r3, r9 +10001cd8: 4641 mov r1, r8 +10001cda: 2020 movs r0, #32 +10001cdc: f10a 0a01 add.w sl, sl, #1 +10001ce0: 47b8 blx r7 +10001ce2: ebaa 0304 sub.w r3, sl, r4 +10001ce6: 455b cmp r3, fp +10001ce8: d3f4 bcc.n 10001cd4 <_ftoa+0x2d4> +10001cea: e78f b.n 10001c0c <_ftoa+0x20c> +10001cec: f3af 8000 nop.w +10001cf0: 00000000 .word 0x00000000 +10001cf4: 41cdcd65 .word 0x41cdcd65 +10001cf8: 00000000 .word 0x00000000 +10001cfc: c1cdcd65 .word 0xc1cdcd65 +10001d00: 7fefffff .word 0x7fefffff +10001d04: 10003760 .word 0x10003760 +10001d08: 3fe00000 .word 0x3fe00000 +10001d0c: 66666667 .word 0x66666667 +10001d10: 100036bc .word 0x100036bc +10001d14: 100036c4 .word 0x100036c4 +10001d18: 100036d0 .word 0x100036d0 +10001d1c: cccccccd .word 0xcccccccd +10001d20: 2200 movs r2, #0 +10001d22: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001d26: 4b63 ldr r3, [pc, #396] @ (10001eb4 <_ftoa+0x4b4>) +10001d28: f7ff fcda bl 100016e0 <__wrap___aeabi_dcmplt> +10001d2c: 2800 cmp r0, #0 +10001d2e: f47f af08 bne.w 10001b42 <_ftoa+0x142> +10001d32: f1ba 0f00 cmp.w sl, #0 +10001d36: d16a bne.n 10001e0e <_ftoa+0x40e> +10001d38: f10a 0a01 add.w sl, sl, #1 +10001d3c: 2e00 cmp r6, #0 +10001d3e: f47f af03 bne.w 10001b48 <_ftoa+0x148> +10001d42: 4620 mov r0, r4 +10001d44: f7ff fc72 bl 1000162c <__wrap___aeabi_i2d> +10001d48: 4602 mov r2, r0 +10001d4a: 460b mov r3, r1 +10001d4c: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d50: f7ff fbe4 bl 1000151c <__wrap___aeabi_dsub> +10001d54: 4602 mov r2, r0 +10001d56: 460b mov r3, r1 +10001d58: e9cd 2304 strd r2, r3, [sp, #16] +10001d5c: 2200 movs r2, #0 +10001d5e: 4b55 ldr r3, [pc, #340] @ (10001eb4 <_ftoa+0x4b4>) +10001d60: f7ff fcbe bl 100016e0 <__wrap___aeabi_dcmplt> +10001d64: 2800 cmp r0, #0 +10001d66: f47f af0c bne.w 10001b82 <_ftoa+0x182> +10001d6a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d6e: 2200 movs r2, #0 +10001d70: 4b50 ldr r3, [pc, #320] @ (10001eb4 <_ftoa+0x4b4>) +10001d72: f7ff fcf1 bl 10001758 <__wrap___aeabi_dcmpgt> +10001d76: 2800 cmp r0, #0 +10001d78: f47f af03 bne.w 10001b82 <_ftoa+0x182> +10001d7c: 3401 adds r4, #1 +10001d7e: f024 0401 bic.w r4, r4, #1 +10001d82: e6fe b.n 10001b82 <_ftoa+0x182> +10001d84: 9b07 ldr r3, [sp, #28] +10001d86: f003 0303 and.w r3, r3, #3 +10001d8a: 2b01 cmp r3, #1 +10001d8c: f000 8082 beq.w 10001e94 <_ftoa+0x494> +10001d90: 2d20 cmp r5, #32 +10001d92: f43f af2e beq.w 10001bf2 <_ftoa+0x1f2> +10001d96: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d98: b37b cbz r3, 10001dfa <_ftoa+0x3fa> +10001d9a: 222d movs r2, #45 @ 0x2d +10001d9c: eb0d 0305 add.w r3, sp, r5 +10001da0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001da4: 3501 adds r5, #1 +10001da6: e724 b.n 10001bf2 <_ftoa+0x1f2> +10001da8: 2b20 cmp r3, #32 +10001daa: f43f aee9 beq.w 10001b80 <_ftoa+0x180> +10001dae: aa0e add r2, sp, #56 @ 0x38 +10001db0: 4415 add r5, r2 +10001db2: 441e add r6, r3 +10001db4: 2230 movs r2, #48 @ 0x30 +10001db6: e004 b.n 10001dc2 <_ftoa+0x3c2> +10001db8: 2b20 cmp r3, #32 +10001dba: f805 2f01 strb.w r2, [r5, #1]! +10001dbe: f43f aedf beq.w 10001b80 <_ftoa+0x180> +10001dc2: 429e cmp r6, r3 +10001dc4: f103 0301 add.w r3, r3, #1 +10001dc8: d1f6 bne.n 10001db8 <_ftoa+0x3b8> +10001dca: 222e movs r2, #46 @ 0x2e +10001dcc: eb0d 0306 add.w r3, sp, r6 +10001dd0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001dd4: 1c75 adds r5, r6, #1 +10001dd6: e6d4 b.n 10001b82 <_ftoa+0x182> +10001dd8: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001ddc: e763 b.n 10001ca6 <_ftoa+0x2a6> +10001dde: 2520 movs r5, #32 +10001de0: e66e b.n 10001ac0 <_ftoa+0xc0> +10001de2: 9b07 ldr r3, [sp, #28] +10001de4: f013 0f0c tst.w r3, #12 +10001de8: d050 beq.n 10001e8c <_ftoa+0x48c> +10001dea: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001dee: 45ab cmp fp, r5 +10001df0: f63f aef2 bhi.w 10001bd8 <_ftoa+0x1d8> +10001df4: 2d20 cmp r5, #32 +10001df6: f43f aefc beq.w 10001bf2 <_ftoa+0x1f2> +10001dfa: 9b07 ldr r3, [sp, #28] +10001dfc: 075a lsls r2, r3, #29 +10001dfe: d501 bpl.n 10001e04 <_ftoa+0x404> +10001e00: 222b movs r2, #43 @ 0x2b +10001e02: e7cb b.n 10001d9c <_ftoa+0x39c> +10001e04: 071b lsls r3, r3, #28 +10001e06: f57f aef4 bpl.w 10001bf2 <_ftoa+0x1f2> +10001e0a: 2220 movs r2, #32 +10001e0c: e7c6 b.n 10001d9c <_ftoa+0x39c> +10001e0e: f01a 0f01 tst.w sl, #1 +10001e12: f43f ae96 beq.w 10001b42 <_ftoa+0x142> +10001e16: e78f b.n 10001d38 <_ftoa+0x338> +10001e18: 07a6 lsls r6, r4, #30 +10001e1a: d134 bne.n 10001e86 <_ftoa+0x486> +10001e1c: f1bb 0f03 cmp.w fp, #3 +10001e20: d931 bls.n 10001e86 <_ftoa+0x486> +10001e22: 9b0c ldr r3, [sp, #48] @ 0x30 +10001e24: 461d mov r5, r3 +10001e26: 1edc subs r4, r3, #3 +10001e28: eb04 0a0b add.w sl, r4, fp +10001e2c: 462a mov r2, r5 +10001e2e: 464b mov r3, r9 +10001e30: 4641 mov r1, r8 +10001e32: 2020 movs r0, #32 +10001e34: 3501 adds r5, #1 +10001e36: 47b8 blx r7 +10001e38: 4555 cmp r5, sl +10001e3a: d1f7 bne.n 10001e2c <_ftoa+0x42c> +10001e3c: 4655 mov r5, sl +10001e3e: 4c1e ldr r4, [pc, #120] @ (10001eb8 <_ftoa+0x4b8>) +10001e40: 1ee6 subs r6, r4, #3 +10001e42: f814 0d01 ldrb.w r0, [r4, #-1]! +10001e46: 462a mov r2, r5 +10001e48: 464b mov r3, r9 +10001e4a: 4641 mov r1, r8 +10001e4c: 47b8 blx r7 +10001e4e: 42a6 cmp r6, r4 +10001e50: f105 0501 add.w r5, r5, #1 +10001e54: d1f5 bne.n 10001e42 <_ftoa+0x442> +10001e56: 9b07 ldr r3, [sp, #28] +10001e58: f10a 0a03 add.w sl, sl, #3 +10001e5c: 079d lsls r5, r3, #30 +10001e5e: f57f aed5 bpl.w 10001c0c <_ftoa+0x20c> +10001e62: 9c0c ldr r4, [sp, #48] @ 0x30 +10001e64: ebaa 0304 sub.w r3, sl, r4 +10001e68: 459b cmp fp, r3 +10001e6a: f67f aecf bls.w 10001c0c <_ftoa+0x20c> +10001e6e: 4652 mov r2, sl +10001e70: 464b mov r3, r9 +10001e72: 4641 mov r1, r8 +10001e74: 2020 movs r0, #32 +10001e76: f10a 0a01 add.w sl, sl, #1 +10001e7a: 47b8 blx r7 +10001e7c: ebaa 0304 sub.w r3, sl, r4 +10001e80: 459b cmp fp, r3 +10001e82: d8f4 bhi.n 10001e6e <_ftoa+0x46e> +10001e84: e6c2 b.n 10001c0c <_ftoa+0x20c> +10001e86: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001e8a: e7d7 b.n 10001e3c <_ftoa+0x43c> +10001e8c: 45ab cmp fp, r5 +10001e8e: f63f aea3 bhi.w 10001bd8 <_ftoa+0x1d8> +10001e92: e6ae b.n 10001bf2 <_ftoa+0x1f2> +10001e94: f1bb 0f00 cmp.w fp, #0 +10001e98: f43f af7a beq.w 10001d90 <_ftoa+0x390> +10001e9c: 9b0d ldr r3, [sp, #52] @ 0x34 +10001e9e: 2b00 cmp r3, #0 +10001ea0: d09f beq.n 10001de2 <_ftoa+0x3e2> +10001ea2: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001ea6: 455d cmp r5, fp +10001ea8: f4ff ae96 bcc.w 10001bd8 <_ftoa+0x1d8> +10001eac: 2d20 cmp r5, #32 +10001eae: f47f af74 bne.w 10001d9a <_ftoa+0x39a> +10001eb2: e69e b.n 10001bf2 <_ftoa+0x1f2> +10001eb4: 3fe00000 .word 0x3fe00000 +10001eb8: 100036cb .word 0x100036cb +10001ebc: 00000000 .word 0x00000000 + +10001ec0 <_etoa>: +10001ec0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ec4: b09f sub sp, #124 @ 0x7c +10001ec6: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001ec8: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001ecc: 4607 mov r7, r0 +10001ece: 4693 mov fp, r2 +10001ed0: 9108 str r1, [sp, #32] +10001ed2: 9309 str r3, [sp, #36] @ 0x24 +10001ed4: 4622 mov r2, r4 +10001ed6: 462b mov r3, r5 +10001ed8: 4620 mov r0, r4 +10001eda: 4629 mov r1, r5 +10001edc: 960e str r6, [sp, #56] @ 0x38 +10001ede: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001ee2: f7ff fbeb bl 100016bc <__wrap___aeabi_dcmpun> +10001ee6: 2800 cmp r0, #0 +10001ee8: f040 80be bne.w 10002068 <_etoa+0x1a8> +10001eec: 4620 mov r0, r4 +10001eee: 4629 mov r1, r5 +10001ef0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001ef4: 4b78 ldr r3, [pc, #480] @ (100020d8 <_etoa+0x218>) +10001ef6: f7ff fc2f bl 10001758 <__wrap___aeabi_dcmpgt> +10001efa: 2800 cmp r0, #0 +10001efc: f040 80b4 bne.w 10002068 <_etoa+0x1a8> +10001f00: 4620 mov r0, r4 +10001f02: 4629 mov r1, r5 +10001f04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001f08: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001f0c: f7ff fbe8 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f10: 2800 cmp r0, #0 +10001f12: f040 80a9 bne.w 10002068 <_etoa+0x1a8> +10001f16: 4620 mov r0, r4 +10001f18: 4629 mov r1, r5 +10001f1a: 2200 movs r2, #0 +10001f1c: 2300 movs r3, #0 +10001f1e: f7ff fbdf bl 100016e0 <__wrap___aeabi_dcmplt> +10001f22: 2800 cmp r0, #0 +10001f24: f040 81d5 bne.w 100022d2 <_etoa+0x412> +10001f28: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001f2c: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001f30: 4690 mov r8, r2 +10001f32: 4699 mov r9, r3 +10001f34: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001f38: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001f3c: 920f str r2, [sp, #60] @ 0x3c +10001f3e: 9313 str r3, [sp, #76] @ 0x4c +10001f40: f040 80a1 bne.w 10002086 <_etoa+0x1c6> +10001f44: ea58 0309 orrs.w r3, r8, r9 +10001f48: f040 80ca bne.w 100020e0 <_etoa+0x220> +10001f4c: 2a00 cmp r2, #0 +10001f4e: f040 81e3 bne.w 10002318 <_etoa+0x458> +10001f52: 2306 movs r3, #6 +10001f54: 930e str r3, [sp, #56] @ 0x38 +10001f56: f016 0202 ands.w r2, r6, #2 +10001f5a: 9210 str r2, [sp, #64] @ 0x40 +10001f5c: f040 81d4 bne.w 10002308 <_etoa+0x448> +10001f60: 4653 mov r3, sl +10001f62: 2b04 cmp r3, #4 +10001f64: bf38 it cc +10001f66: 2304 movcc r3, #4 +10001f68: 920c str r2, [sp, #48] @ 0x30 +10001f6a: 2204 movs r2, #4 +10001f6c: 3b04 subs r3, #4 +10001f6e: 9212 str r2, [sp, #72] @ 0x48 +10001f70: 930f str r3, [sp, #60] @ 0x3c +10001f72: 4620 mov r0, r4 +10001f74: 4629 mov r1, r5 +10001f76: 2200 movs r2, #0 +10001f78: 2300 movs r3, #0 +10001f7a: f7ff fbb1 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f7e: 2800 cmp r0, #0 +10001f80: f040 81f3 bne.w 1000236a <_etoa+0x4aa> +10001f84: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001f88: 9b0f ldr r3, [sp, #60] @ 0x3c +10001f8a: 465a mov r2, fp +10001f8c: 9303 str r3, [sp, #12] +10001f8e: 9b0e ldr r3, [sp, #56] @ 0x38 +10001f90: ed8d 7b00 vstr d7, [sp] +10001f94: 9302 str r3, [sp, #8] +10001f96: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001f9a: 9304 str r3, [sp, #16] +10001f9c: 4638 mov r0, r7 +10001f9e: 9b09 ldr r3, [sp, #36] @ 0x24 +10001fa0: 9908 ldr r1, [sp, #32] +10001fa2: f7ff fd2d bl 10001a00 <_ftoa> +10001fa6: 4602 mov r2, r0 +10001fa8: f016 0f20 tst.w r6, #32 +10001fac: 9b09 ldr r3, [sp, #36] @ 0x24 +10001fae: 9908 ldr r1, [sp, #32] +10001fb0: bf0c ite eq +10001fb2: 2065 moveq r0, #101 @ 0x65 +10001fb4: 2045 movne r0, #69 @ 0x45 +10001fb6: f102 0801 add.w r8, r2, #1 +10001fba: 47b8 blx r7 +10001fbc: 9a0c ldr r2, [sp, #48] @ 0x30 +10001fbe: 9b12 ldr r3, [sp, #72] @ 0x48 +10001fc0: ac16 add r4, sp, #88 @ 0x58 +10001fc2: 1e5d subs r5, r3, #1 +10001fc4: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001fc8: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001fcc: 0fd1 lsrs r1, r2, #31 +10001fce: 2600 movs r6, #0 +10001fd0: 4622 mov r2, r4 +10001fd2: 4699 mov r9, r3 +10001fd4: f8df c104 ldr.w ip, [pc, #260] @ 100020dc <_etoa+0x21c> +10001fd8: e001 b.n 10001fde <_etoa+0x11e> +10001fda: 2e20 cmp r6, #32 +10001fdc: d010 beq.n 10002000 <_etoa+0x140> +10001fde: 46ce mov lr, r9 +10001fe0: fbac 3009 umull r3, r0, ip, r9 +10001fe4: 08c0 lsrs r0, r0, #3 +10001fe6: eb00 0380 add.w r3, r0, r0, lsl #2 +10001fea: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001fee: 3330 adds r3, #48 @ 0x30 +10001ff0: f1be 0f09 cmp.w lr, #9 +10001ff4: 4681 mov r9, r0 +10001ff6: f106 0601 add.w r6, r6, #1 +10001ffa: f802 3b01 strb.w r3, [r2], #1 +10001ffe: d8ec bhi.n 10001fda <_etoa+0x11a> +10002000: 2305 movs r3, #5 +10002002: 2000 movs r0, #0 +10002004: 9306 str r3, [sp, #24] +10002006: 230a movs r3, #10 +10002008: 9505 str r5, [sp, #20] +1000200a: 9400 str r4, [sp, #0] +1000200c: 9d09 ldr r5, [sp, #36] @ 0x24 +1000200e: 9c08 ldr r4, [sp, #32] +10002010: 4642 mov r2, r8 +10002012: e9cd 3003 strd r3, r0, [sp, #12] +10002016: e9cd 6101 strd r6, r1, [sp, #4] +1000201a: 462b mov r3, r5 +1000201c: 4621 mov r1, r4 +1000201e: 4638 mov r0, r7 +10002020: f7ff fbfa bl 10001818 <_ntoa_format> +10002024: 9a10 ldr r2, [sp, #64] @ 0x40 +10002026: 4680 mov r8, r0 +10002028: b1d2 cbz r2, 10002060 <_etoa+0x1a0> +1000202a: eba0 060b sub.w r6, r0, fp +1000202e: 45b2 cmp sl, r6 +10002030: d916 bls.n 10002060 <_etoa+0x1a0> +10002032: eb0b 0206 add.w r2, fp, r6 +10002036: 462b mov r3, r5 +10002038: 4621 mov r1, r4 +1000203a: 2020 movs r0, #32 +1000203c: 3601 adds r6, #1 +1000203e: 47b8 blx r7 +10002040: 45b2 cmp sl, r6 +10002042: d8f6 bhi.n 10002032 <_etoa+0x172> +10002044: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002048: 4453 add r3, sl +1000204a: f1cb 0201 rsb r2, fp, #1 +1000204e: eba3 0308 sub.w r3, r3, r8 +10002052: 4442 add r2, r8 +10002054: 4592 cmp sl, r2 +10002056: bf38 it cc +10002058: 2300 movcc r3, #0 +1000205a: f108 0801 add.w r8, r8, #1 +1000205e: 4498 add r8, r3 +10002060: 4640 mov r0, r8 +10002062: b01f add sp, #124 @ 0x7c +10002064: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002068: 465a mov r2, fp +1000206a: 4638 mov r0, r7 +1000206c: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002070: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10002074: 9c0e ldr r4, [sp, #56] @ 0x38 +10002076: 9b09 ldr r3, [sp, #36] @ 0x24 +10002078: 9908 ldr r1, [sp, #32] +1000207a: 942a str r4, [sp, #168] @ 0xa8 +1000207c: b01f add sp, #124 @ 0x7c +1000207e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002082: f7ff bcbd b.w 10001a00 <_ftoa> +10002086: ea58 0309 orrs.w r3, r8, r9 +1000208a: d12b bne.n 100020e4 <_etoa+0x224> +1000208c: 2a00 cmp r2, #0 +1000208e: f43f af62 beq.w 10001f56 <_etoa+0x96> +10002092: 2300 movs r3, #0 +10002094: 930c str r3, [sp, #48] @ 0x30 +10002096: 9b0e ldr r3, [sp, #56] @ 0x38 +10002098: 9a0c ldr r2, [sp, #48] @ 0x30 +1000209a: 4293 cmp r3, r2 +1000209c: f300 81b9 bgt.w 10002412 <_etoa+0x552> +100020a0: f04f 0800 mov.w r8, #0 +100020a4: 4620 mov r0, r4 +100020a6: 4629 mov r1, r5 +100020a8: 2200 movs r2, #0 +100020aa: 2300 movs r3, #0 +100020ac: f7ff fb18 bl 100016e0 <__wrap___aeabi_dcmplt> +100020b0: 2800 cmp r0, #0 +100020b2: f040 8113 bne.w 100022dc <_etoa+0x41c> +100020b6: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +100020ba: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100020be: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100020c2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100020c6: 465a mov r2, fp +100020c8: 4638 mov r0, r7 +100020ca: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100020ce: 9b09 ldr r3, [sp, #36] @ 0x24 +100020d0: 9908 ldr r1, [sp, #32] +100020d2: 962c str r6, [sp, #176] @ 0xb0 +100020d4: e7d2 b.n 1000207c <_etoa+0x1bc> +100020d6: bf00 nop +100020d8: 7fefffff .word 0x7fefffff +100020dc: cccccccd .word 0xcccccccd +100020e0: 2306 movs r3, #6 +100020e2: 930e str r3, [sp, #56] @ 0x38 +100020e4: f3c9 500a ubfx r0, r9, #20, #11 +100020e8: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100020ec: f7ff fa9e bl 1000162c <__wrap___aeabi_i2d> +100020f0: a3c1 add r3, pc, #772 @ (adr r3, 100023f8 <_etoa+0x538>) +100020f2: e9d3 2300 ldrd r2, r3, [r3] +100020f6: f7ff fa25 bl 10001544 <__wrap___aeabi_dmul> +100020fa: a3c1 add r3, pc, #772 @ (adr r3, 10002400 <_etoa+0x540>) +100020fc: e9d3 2300 ldrd r2, r3, [r3] +10002100: f7ff f9f8 bl 100014f4 <__wrap___aeabi_dadd> +10002104: f3c9 0913 ubfx r9, r9, #0, #20 +10002108: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +1000210c: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002110: 4640 mov r0, r8 +10002112: 2200 movs r2, #0 +10002114: 4bb2 ldr r3, [pc, #712] @ (100023e0 <_etoa+0x520>) +10002116: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +1000211a: f7ff f9ff bl 1000151c <__wrap___aeabi_dsub> +1000211e: a3a4 add r3, pc, #656 @ (adr r3, 100023b0 <_etoa+0x4f0>) +10002120: e9d3 2300 ldrd r2, r3, [r3] +10002124: f7ff fa0e bl 10001544 <__wrap___aeabi_dmul> +10002128: 4602 mov r2, r0 +1000212a: 460b mov r3, r1 +1000212c: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002130: f7ff f9e0 bl 100014f4 <__wrap___aeabi_dadd> +10002134: f7ff fa9e bl 10001674 <__wrap___aeabi_d2iz> +10002138: 900c str r0, [sp, #48] @ 0x30 +1000213a: f7ff fa77 bl 1000162c <__wrap___aeabi_i2d> +1000213e: a39e add r3, pc, #632 @ (adr r3, 100023b8 <_etoa+0x4f8>) +10002140: e9d3 2300 ldrd r2, r3, [r3] +10002144: 4680 mov r8, r0 +10002146: 4689 mov r9, r1 +10002148: f7ff f9fc bl 10001544 <__wrap___aeabi_dmul> +1000214c: 2200 movs r2, #0 +1000214e: 4ba5 ldr r3, [pc, #660] @ (100023e4 <_etoa+0x524>) +10002150: f7ff f9d0 bl 100014f4 <__wrap___aeabi_dadd> +10002154: f7ff fa8e bl 10001674 <__wrap___aeabi_d2iz> +10002158: 4603 mov r3, r0 +1000215a: 4649 mov r1, r9 +1000215c: 4640 mov r0, r8 +1000215e: 9312 str r3, [sp, #72] @ 0x48 +10002160: a397 add r3, pc, #604 @ (adr r3, 100023c0 <_etoa+0x500>) +10002162: e9d3 2300 ldrd r2, r3, [r3] +10002166: f7ff f9ed bl 10001544 <__wrap___aeabi_dmul> +1000216a: 4680 mov r8, r0 +1000216c: 9812 ldr r0, [sp, #72] @ 0x48 +1000216e: 4689 mov r9, r1 +10002170: f7ff fa5c bl 1000162c <__wrap___aeabi_i2d> +10002174: a394 add r3, pc, #592 @ (adr r3, 100023c8 <_etoa+0x508>) +10002176: e9d3 2300 ldrd r2, r3, [r3] +1000217a: f7ff f9e3 bl 10001544 <__wrap___aeabi_dmul> +1000217e: 4602 mov r2, r0 +10002180: 460b mov r3, r1 +10002182: 4640 mov r0, r8 +10002184: 4649 mov r1, r9 +10002186: f7ff f9c9 bl 1000151c <__wrap___aeabi_dsub> +1000218a: 4602 mov r2, r0 +1000218c: 460b mov r3, r1 +1000218e: 4680 mov r8, r0 +10002190: 4689 mov r9, r1 +10002192: f7ff f9d7 bl 10001544 <__wrap___aeabi_dmul> +10002196: 4642 mov r2, r8 +10002198: 464b mov r3, r9 +1000219a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +1000219e: 4640 mov r0, r8 +100021a0: 4649 mov r1, r9 +100021a2: f7ff f9a7 bl 100014f4 <__wrap___aeabi_dadd> +100021a6: 2200 movs r2, #0 +100021a8: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +100021ac: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021b0: 4b8d ldr r3, [pc, #564] @ (100023e8 <_etoa+0x528>) +100021b2: f7ff f9ed bl 10001590 <__wrap___aeabi_ddiv> +100021b6: 2200 movs r2, #0 +100021b8: 4b8c ldr r3, [pc, #560] @ (100023ec <_etoa+0x52c>) +100021ba: f7ff f99b bl 100014f4 <__wrap___aeabi_dadd> +100021be: 4602 mov r2, r0 +100021c0: 460b mov r3, r1 +100021c2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021c6: f7ff f9e3 bl 10001590 <__wrap___aeabi_ddiv> +100021ca: 2200 movs r2, #0 +100021cc: 4b88 ldr r3, [pc, #544] @ (100023f0 <_etoa+0x530>) +100021ce: f7ff f991 bl 100014f4 <__wrap___aeabi_dadd> +100021d2: 4602 mov r2, r0 +100021d4: 460b mov r3, r1 +100021d6: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021da: f7ff f9d9 bl 10001590 <__wrap___aeabi_ddiv> +100021de: 4642 mov r2, r8 +100021e0: 464b mov r3, r9 +100021e2: 4680 mov r8, r0 +100021e4: 4689 mov r9, r1 +100021e6: 2000 movs r0, #0 +100021e8: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100021ec: f7ff f996 bl 1000151c <__wrap___aeabi_dsub> +100021f0: 4602 mov r2, r0 +100021f2: 460b mov r3, r1 +100021f4: 4640 mov r0, r8 +100021f6: 4649 mov r1, r9 +100021f8: f7ff f97c bl 100014f4 <__wrap___aeabi_dadd> +100021fc: 4602 mov r2, r0 +100021fe: 460b mov r3, r1 +10002200: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +10002204: f7ff f9c4 bl 10001590 <__wrap___aeabi_ddiv> +10002208: 2200 movs r2, #0 +1000220a: 4b7a ldr r3, [pc, #488] @ (100023f4 <_etoa+0x534>) +1000220c: f7ff f972 bl 100014f4 <__wrap___aeabi_dadd> +10002210: 9b12 ldr r3, [sp, #72] @ 0x48 +10002212: 2200 movs r2, #0 +10002214: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002218: ea4f 530c mov.w r3, ip, lsl #20 +1000221c: f7ff f992 bl 10001544 <__wrap___aeabi_dmul> +10002220: 4680 mov r8, r0 +10002222: 4689 mov r9, r1 +10002224: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002228: 4642 mov r2, r8 +1000222a: 464b mov r3, r9 +1000222c: f7ff fa58 bl 100016e0 <__wrap___aeabi_dcmplt> +10002230: b150 cbz r0, 10002248 <_etoa+0x388> +10002232: 9b0c ldr r3, [sp, #48] @ 0x30 +10002234: 4640 mov r0, r8 +10002236: 3b01 subs r3, #1 +10002238: 4649 mov r1, r9 +1000223a: 930c str r3, [sp, #48] @ 0x30 +1000223c: 2200 movs r2, #0 +1000223e: 4b6b ldr r3, [pc, #428] @ (100023ec <_etoa+0x52c>) +10002240: f7ff f9a6 bl 10001590 <__wrap___aeabi_ddiv> +10002244: 4680 mov r8, r0 +10002246: 4689 mov r9, r1 +10002248: 9a0c ldr r2, [sp, #48] @ 0x30 +1000224a: 4643 mov r3, r8 +1000224c: 3263 adds r2, #99 @ 0x63 +1000224e: 2ac6 cmp r2, #198 @ 0xc6 +10002250: f006 0202 and.w r2, r6, #2 +10002254: 9210 str r2, [sp, #64] @ 0x40 +10002256: 4649 mov r1, r9 +10002258: 9a0f ldr r2, [sp, #60] @ 0x3c +1000225a: d82c bhi.n 100022b6 <_etoa+0x3f6> +1000225c: 2a00 cmp r2, #0 +1000225e: d05e beq.n 1000231e <_etoa+0x45e> +10002260: 2204 movs r2, #4 +10002262: 9212 str r2, [sp, #72] @ 0x48 +10002264: 430b orrs r3, r1 +10002266: f43f af16 beq.w 10002096 <_etoa+0x1d6> +1000226a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000226e: a358 add r3, pc, #352 @ (adr r3, 100023d0 <_etoa+0x510>) +10002270: e9d3 2300 ldrd r2, r3, [r3] +10002274: f7ff fa5c bl 10001730 <__wrap___aeabi_dcmpge> +10002278: b148 cbz r0, 1000228e <_etoa+0x3ce> +1000227a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000227e: a356 add r3, pc, #344 @ (adr r3, 100023d8 <_etoa+0x518>) +10002280: e9d3 2300 ldrd r2, r3, [r3] +10002284: f7ff fa2c bl 100016e0 <__wrap___aeabi_dcmplt> +10002288: 2800 cmp r0, #0 +1000228a: f47f af04 bne.w 10002096 <_etoa+0x1d6> +1000228e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002290: 2b00 cmp r3, #0 +10002292: d050 beq.n 10002336 <_etoa+0x476> +10002294: 9a13 ldr r2, [sp, #76] @ 0x4c +10002296: 2a00 cmp r2, #0 +10002298: d07d beq.n 10002396 <_etoa+0x4d6> +1000229a: 3b01 subs r3, #1 +1000229c: 930e str r3, [sp, #56] @ 0x38 +1000229e: 9b12 ldr r3, [sp, #72] @ 0x48 +100022a0: 459a cmp sl, r3 +100022a2: d905 bls.n 100022b0 <_etoa+0x3f0> +100022a4: 9b10 ldr r3, [sp, #64] @ 0x40 +100022a6: 2b00 cmp r3, #0 +100022a8: f000 80ae beq.w 10002408 <_etoa+0x548> +100022ac: 2302 movs r3, #2 +100022ae: 9310 str r3, [sp, #64] @ 0x40 +100022b0: 2300 movs r3, #0 +100022b2: 930f str r3, [sp, #60] @ 0x3c +100022b4: e044 b.n 10002340 <_etoa+0x480> +100022b6: bb22 cbnz r2, 10002302 <_etoa+0x442> +100022b8: f1ba 0f05 cmp.w sl, #5 +100022bc: d94f bls.n 1000235e <_etoa+0x49e> +100022be: f006 0302 and.w r3, r6, #2 +100022c2: 2b00 cmp r3, #0 +100022c4: d149 bne.n 1000235a <_etoa+0x49a> +100022c6: 2305 movs r3, #5 +100022c8: 9312 str r3, [sp, #72] @ 0x48 +100022ca: f1aa 0305 sub.w r3, sl, #5 +100022ce: 930f str r3, [sp, #60] @ 0x3c +100022d0: e03a b.n 10002348 <_etoa+0x488> +100022d2: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +100022d6: 940a str r4, [sp, #40] @ 0x28 +100022d8: 930b str r3, [sp, #44] @ 0x2c +100022da: e627 b.n 10001f2c <_etoa+0x6c> +100022dc: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100022e0: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100022e4: 4638 mov r0, r7 +100022e6: 962c str r6, [sp, #176] @ 0xb0 +100022e8: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +100022ec: 4634 mov r4, r6 +100022ee: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100022f2: 465a mov r2, fp +100022f4: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100022f8: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100022fc: 9b09 ldr r3, [sp, #36] @ 0x24 +100022fe: 9908 ldr r1, [sp, #32] +10002300: e6bc b.n 1000207c <_etoa+0x1bc> +10002302: 2205 movs r2, #5 +10002304: 9212 str r2, [sp, #72] @ 0x48 +10002306: e7ad b.n 10002264 <_etoa+0x3a4> +10002308: 2300 movs r3, #0 +1000230a: 2202 movs r2, #2 +1000230c: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002310: 2204 movs r2, #4 +10002312: 930c str r3, [sp, #48] @ 0x30 +10002314: 9212 str r2, [sp, #72] @ 0x48 +10002316: e62c b.n 10001f72 <_etoa+0xb2> +10002318: f04f 0805 mov.w r8, #5 +1000231c: e6c2 b.n 100020a4 <_etoa+0x1e4> +1000231e: f1ba 0f04 cmp.w sl, #4 +10002322: d91f bls.n 10002364 <_etoa+0x4a4> +10002324: 9b10 ldr r3, [sp, #64] @ 0x40 +10002326: 2b00 cmp r3, #0 +10002328: d178 bne.n 1000241c <_etoa+0x55c> +1000232a: 2304 movs r3, #4 +1000232c: 9312 str r3, [sp, #72] @ 0x48 +1000232e: f1aa 0304 sub.w r3, sl, #4 +10002332: 930f str r3, [sp, #60] @ 0x3c +10002334: e004 b.n 10002340 <_etoa+0x480> +10002336: 9b12 ldr r3, [sp, #72] @ 0x48 +10002338: 459a cmp sl, r3 +1000233a: d831 bhi.n 100023a0 <_etoa+0x4e0> +1000233c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000233e: 930f str r3, [sp, #60] @ 0x3c +10002340: 9b0c ldr r3, [sp, #48] @ 0x30 +10002342: 2b00 cmp r3, #0 +10002344: f43f ae15 beq.w 10001f72 <_etoa+0xb2> +10002348: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000234c: 4642 mov r2, r8 +1000234e: 464b mov r3, r9 +10002350: f7ff f91e bl 10001590 <__wrap___aeabi_ddiv> +10002354: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10002358: e60b b.n 10001f72 <_etoa+0xb2> +1000235a: 2302 movs r3, #2 +1000235c: 9310 str r3, [sp, #64] @ 0x40 +1000235e: 2305 movs r3, #5 +10002360: 9312 str r3, [sp, #72] @ 0x48 +10002362: e7f1 b.n 10002348 <_etoa+0x488> +10002364: 2304 movs r3, #4 +10002366: 9312 str r3, [sp, #72] @ 0x48 +10002368: e7ea b.n 10002340 <_etoa+0x480> +1000236a: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +1000236e: 46a0 mov r8, r4 +10002370: 9b0f ldr r3, [sp, #60] @ 0x3c +10002372: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +10002376: 9303 str r3, [sp, #12] +10002378: 9b0e ldr r3, [sp, #56] @ 0x38 +1000237a: 465a mov r2, fp +1000237c: 9302 str r3, [sp, #8] +1000237e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002382: 9304 str r3, [sp, #16] +10002384: 4638 mov r0, r7 +10002386: e9cd 8900 strd r8, r9, [sp] +1000238a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000238c: 9908 ldr r1, [sp, #32] +1000238e: f7ff fb37 bl 10001a00 <_ftoa> +10002392: 4602 mov r2, r0 +10002394: e608 b.n 10001fa8 <_etoa+0xe8> +10002396: 9b12 ldr r3, [sp, #72] @ 0x48 +10002398: 459a cmp sl, r3 +1000239a: d844 bhi.n 10002426 <_etoa+0x566> +1000239c: 920f str r2, [sp, #60] @ 0x3c +1000239e: e7cf b.n 10002340 <_etoa+0x480> +100023a0: 9b10 ldr r3, [sp, #64] @ 0x40 +100023a2: b38b cbz r3, 10002408 <_etoa+0x548> +100023a4: 9b0e ldr r3, [sp, #56] @ 0x38 +100023a6: 930f str r3, [sp, #60] @ 0x3c +100023a8: 2302 movs r3, #2 +100023aa: 9310 str r3, [sp, #64] @ 0x40 +100023ac: e7c8 b.n 10002340 <_etoa+0x480> +100023ae: bf00 nop +100023b0: 636f4361 .word 0x636f4361 +100023b4: 3fd287a7 .word 0x3fd287a7 +100023b8: 0979a371 .word 0x0979a371 +100023bc: 400a934f .word 0x400a934f +100023c0: bbb55516 .word 0xbbb55516 +100023c4: 40026bb1 .word 0x40026bb1 +100023c8: fefa39ef .word 0xfefa39ef +100023cc: 3fe62e42 .word 0x3fe62e42 +100023d0: eb1c432d .word 0xeb1c432d +100023d4: 3f1a36e2 .word 0x3f1a36e2 +100023d8: 00000000 .word 0x00000000 +100023dc: 412e8480 .word 0x412e8480 +100023e0: 3ff80000 .word 0x3ff80000 +100023e4: 3fe00000 .word 0x3fe00000 +100023e8: 402c0000 .word 0x402c0000 +100023ec: 40240000 .word 0x40240000 +100023f0: 40180000 .word 0x40180000 +100023f4: 3ff00000 .word 0x3ff00000 +100023f8: 509f79fb .word 0x509f79fb +100023fc: 3fd34413 .word 0x3fd34413 +10002400: 8b60c8b3 .word 0x8b60c8b3 +10002404: 3fc68a28 .word 0x3fc68a28 +10002408: 9b12 ldr r3, [sp, #72] @ 0x48 +1000240a: ebaa 0303 sub.w r3, sl, r3 +1000240e: 930f str r3, [sp, #60] @ 0x3c +10002410: e796 b.n 10002340 <_etoa+0x480> +10002412: eba3 0802 sub.w r8, r3, r2 +10002416: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +1000241a: e643 b.n 100020a4 <_etoa+0x1e4> +1000241c: 2304 movs r3, #4 +1000241e: 9312 str r3, [sp, #72] @ 0x48 +10002420: 2302 movs r3, #2 +10002422: 9310 str r3, [sp, #64] @ 0x40 +10002424: e78c b.n 10002340 <_etoa+0x480> +10002426: 9b10 ldr r3, [sp, #64] @ 0x40 +10002428: 2b00 cmp r3, #0 +1000242a: d0ed beq.n 10002408 <_etoa+0x548> +1000242c: 2302 movs r3, #2 +1000242e: 920f str r2, [sp, #60] @ 0x3c +10002430: 9310 str r3, [sp, #64] @ 0x40 +10002432: e785 b.n 10002340 <_etoa+0x480> + +10002434 <_vsnprintf>: +10002434: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002438: b09b sub sp, #108 @ 0x6c +1000243a: 9c24 ldr r4, [sp, #144] @ 0x90 +1000243c: 4d95 ldr r5, [pc, #596] @ (10002694 <_vsnprintf+0x260>) +1000243e: 940a str r4, [sp, #40] @ 0x28 +10002440: 4c95 ldr r4, [pc, #596] @ (10002698 <_vsnprintf+0x264>) +10002442: f1b1 0a00 subs.w sl, r1, #0 +10002446: bf18 it ne +10002448: 4683 movne fp, r0 +1000244a: 6025 str r5, [r4, #0] +1000244c: 7818 ldrb r0, [r3, #0] +1000244e: 4c93 ldr r4, [pc, #588] @ (1000269c <_vsnprintf+0x268>) +10002450: 4691 mov r9, r2 +10002452: bf08 it eq +10002454: 46a3 moveq fp, r4 +10002456: 9309 str r3, [sp, #36] @ 0x24 +10002458: 2800 cmp r0, #0 +1000245a: f000 8293 beq.w 10002984 <_vsnprintf+0x550> +1000245e: f04f 0800 mov.w r8, #0 +10002462: e00a b.n 1000247a <_vsnprintf+0x46> +10002464: 4642 mov r2, r8 +10002466: 464b mov r3, r9 +10002468: 4651 mov r1, sl +1000246a: f108 0801 add.w r8, r8, #1 +1000246e: 47d8 blx fp +10002470: 9b09 ldr r3, [sp, #36] @ 0x24 +10002472: 7818 ldrb r0, [r3, #0] +10002474: 2800 cmp r0, #0 +10002476: f000 80ce beq.w 10002616 <_vsnprintf+0x1e2> +1000247a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000247c: 2825 cmp r0, #37 @ 0x25 +1000247e: f103 0301 add.w r3, r3, #1 +10002482: 9309 str r3, [sp, #36] @ 0x24 +10002484: d1ee bne.n 10002464 <_vsnprintf+0x30> +10002486: 461c mov r4, r3 +10002488: 2300 movs r3, #0 +1000248a: 4622 mov r2, r4 +1000248c: f812 0b01 ldrb.w r0, [r2], #1 +10002490: f1a0 0120 sub.w r1, r0, #32 +10002494: 2910 cmp r1, #16 +10002496: d80a bhi.n 100024ae <_vsnprintf+0x7a> +10002498: e8df f001 tbb [pc, r1] +1000249c: 3c090940 .word 0x3c090940 +100024a0: 09090909 .word 0x09090909 +100024a4: 38090909 .word 0x38090909 +100024a8: 09093409 .word 0x09093409 +100024ac: 30 .byte 0x30 +100024ad: 00 .byte 0x00 +100024ae: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100024b2: 2909 cmp r1, #9 +100024b4: 9409 str r4, [sp, #36] @ 0x24 +100024b6: f240 808a bls.w 100025ce <_vsnprintf+0x19a> +100024ba: 282a cmp r0, #42 @ 0x2a +100024bc: f000 80f0 beq.w 100026a0 <_vsnprintf+0x26c> +100024c0: 2500 movs r5, #0 +100024c2: 282e cmp r0, #46 @ 0x2e +100024c4: f000 8096 beq.w 100025f4 <_vsnprintf+0x1c0> +100024c8: 2600 movs r6, #0 +100024ca: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +100024ce: 2912 cmp r1, #18 +100024d0: d82d bhi.n 1000252e <_vsnprintf+0xfa> +100024d2: e8df f011 tbh [pc, r1, lsl #1] +100024d6: 0149 .short 0x0149 +100024d8: 0143002c .word 0x0143002c +100024dc: 0138002c .word 0x0138002c +100024e0: 002c002c .word 0x002c002c +100024e4: 002c002c .word 0x002c002c +100024e8: 002c002c .word 0x002c002c +100024ec: 0027002c .word 0x0027002c +100024f0: 002c002c .word 0x002c002c +100024f4: 002c002c .word 0x002c002c +100024f8: 0027002c .word 0x0027002c +100024fc: 4614 mov r4, r2 +100024fe: f043 0301 orr.w r3, r3, #1 +10002502: e7c2 b.n 1000248a <_vsnprintf+0x56> +10002504: 4614 mov r4, r2 +10002506: f043 0302 orr.w r3, r3, #2 +1000250a: e7be b.n 1000248a <_vsnprintf+0x56> +1000250c: 4614 mov r4, r2 +1000250e: f043 0304 orr.w r3, r3, #4 +10002512: e7ba b.n 1000248a <_vsnprintf+0x56> +10002514: 4614 mov r4, r2 +10002516: f043 0310 orr.w r3, r3, #16 +1000251a: e7b6 b.n 1000248a <_vsnprintf+0x56> +1000251c: 4614 mov r4, r2 +1000251e: f043 0308 orr.w r3, r3, #8 +10002522: e7b2 b.n 1000248a <_vsnprintf+0x56> +10002524: 9909 ldr r1, [sp, #36] @ 0x24 +10002526: 7848 ldrb r0, [r1, #1] +10002528: f443 7380 orr.w r3, r3, #256 @ 0x100 +1000252c: 3201 adds r2, #1 +1000252e: 2867 cmp r0, #103 @ 0x67 +10002530: 9209 str r2, [sp, #36] @ 0x24 +10002532: d87e bhi.n 10002632 <_vsnprintf+0x1fe> +10002534: 2824 cmp r0, #36 @ 0x24 +10002536: f240 80c1 bls.w 100026bc <_vsnprintf+0x288> +1000253a: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +1000253e: 2a42 cmp r2, #66 @ 0x42 +10002540: f200 80bc bhi.w 100026bc <_vsnprintf+0x288> +10002544: e8df f012 tbh [pc, r2, lsl #1] +10002548: 00ba0150 .word 0x00ba0150 +1000254c: 00ba00ba .word 0x00ba00ba +10002550: 00ba00ba .word 0x00ba00ba +10002554: 00ba00ba .word 0x00ba00ba +10002558: 00ba00ba .word 0x00ba00ba +1000255c: 00ba00ba .word 0x00ba00ba +10002560: 00ba00ba .word 0x00ba00ba +10002564: 00ba00ba .word 0x00ba00ba +10002568: 00ba00ba .word 0x00ba00ba +1000256c: 00ba00ba .word 0x00ba00ba +10002570: 00ba00ba .word 0x00ba00ba +10002574: 00ba00ba .word 0x00ba00ba +10002578: 00ba00ba .word 0x00ba00ba +1000257c: 00ba00ba .word 0x00ba00ba +10002580: 00ba00ba .word 0x00ba00ba +10002584: 00ba00ba .word 0x00ba00ba +10002588: 01370119 .word 0x01370119 +1000258c: 00ba0119 .word 0x00ba0119 +10002590: 00ba00ba .word 0x00ba00ba +10002594: 00ba00ba .word 0x00ba00ba +10002598: 00ba00ba .word 0x00ba00ba +1000259c: 00ba00ba .word 0x00ba00ba +100025a0: 00ba00ba .word 0x00ba00ba +100025a4: 00ba00ba .word 0x00ba00ba +100025a8: 00ba00ba .word 0x00ba00ba +100025ac: 01bc00ba .word 0x01bc00ba +100025b0: 00ba00ba .word 0x00ba00ba +100025b4: 00ba00ba .word 0x00ba00ba +100025b8: 00ba00ba .word 0x00ba00ba +100025bc: 00ba00ba .word 0x00ba00ba +100025c0: 01bc00ba .word 0x01bc00ba +100025c4: 01bc0158 .word 0x01bc0158 +100025c8: 01370119 .word 0x01370119 +100025cc: 0119 .short 0x0119 +100025ce: 2500 movs r5, #0 +100025d0: e000 b.n 100025d4 <_vsnprintf+0x1a0> +100025d2: 3201 adds r2, #1 +100025d4: eb05 0585 add.w r5, r5, r5, lsl #2 +100025d8: eb00 0545 add.w r5, r0, r5, lsl #1 +100025dc: 7810 ldrb r0, [r2, #0] +100025de: 3d30 subs r5, #48 @ 0x30 +100025e0: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100025e4: 2909 cmp r1, #9 +100025e6: d9f4 bls.n 100025d2 <_vsnprintf+0x19e> +100025e8: 282e cmp r0, #46 @ 0x2e +100025ea: 9209 str r2, [sp, #36] @ 0x24 +100025ec: f102 0201 add.w r2, r2, #1 +100025f0: f47f af6a bne.w 100024c8 <_vsnprintf+0x94> +100025f4: 9909 ldr r1, [sp, #36] @ 0x24 +100025f6: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100025fa: 7848 ldrb r0, [r1, #1] +100025fc: 4611 mov r1, r2 +100025fe: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002602: 2e09 cmp r6, #9 +10002604: f240 8121 bls.w 1000284a <_vsnprintf+0x416> +10002608: 282a cmp r0, #42 @ 0x2a +1000260a: f000 812f beq.w 1000286c <_vsnprintf+0x438> +1000260e: 9209 str r2, [sp, #36] @ 0x24 +10002610: 2600 movs r6, #0 +10002612: 3201 adds r2, #1 +10002614: e759 b.n 100024ca <_vsnprintf+0x96> +10002616: 4644 mov r4, r8 +10002618: 45c1 cmp r9, r8 +1000261a: d801 bhi.n 10002620 <_vsnprintf+0x1ec> +1000261c: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002620: 464b mov r3, r9 +10002622: 4642 mov r2, r8 +10002624: 4651 mov r1, sl +10002626: 2000 movs r0, #0 +10002628: 47d8 blx fp +1000262a: 4620 mov r0, r4 +1000262c: b01b add sp, #108 @ 0x6c +1000262e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002632: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +10002636: b2d2 uxtb r2, r2 +10002638: 2a0f cmp r2, #15 +1000263a: d83f bhi.n 100026bc <_vsnprintf+0x288> +1000263c: 2101 movs r1, #1 +1000263e: f249 0741 movw r7, #36929 @ 0x9041 +10002642: 4091 lsls r1, r2 +10002644: 4039 ands r1, r7 +10002646: f040 80f3 bne.w 10002830 <_vsnprintf+0x3fc> +1000264a: 2a0a cmp r2, #10 +1000264c: d03d beq.n 100026ca <_vsnprintf+0x296> +1000264e: 2a07 cmp r2, #7 +10002650: d134 bne.n 100026bc <_vsnprintf+0x288> +10002652: 9d0a ldr r5, [sp, #40] @ 0x28 +10002654: f855 2b04 ldr.w r2, [r5], #4 +10002658: 2a00 cmp r2, #0 +1000265a: f000 8113 beq.w 10002884 <_vsnprintf+0x450> +1000265e: f043 0021 orr.w r0, r3, #33 @ 0x21 +10002662: ab12 add r3, sp, #72 @ 0x48 +10002664: 461f mov r7, r3 +10002666: 930b str r3, [sp, #44] @ 0x2c +10002668: e003 b.n 10002672 <_vsnprintf+0x23e> +1000266a: 2920 cmp r1, #32 +1000266c: f000 8114 beq.w 10002898 <_vsnprintf+0x464> +10002670: 461a mov r2, r3 +10002672: f002 040f and.w r4, r2, #15 +10002676: 4623 mov r3, r4 +10002678: 2c09 cmp r4, #9 +1000267a: bf94 ite ls +1000267c: 3330 addls r3, #48 @ 0x30 +1000267e: 3337 addhi r3, #55 @ 0x37 +10002680: 2a0f cmp r2, #15 +10002682: f807 3b01 strb.w r3, [r7], #1 +10002686: f101 0101 add.w r1, r1, #1 +1000268a: ea4f 1312 mov.w r3, r2, lsr #4 +1000268e: d8ec bhi.n 1000266a <_vsnprintf+0x236> +10002690: e102 b.n 10002898 <_vsnprintf+0x464> +10002692: bf00 nop +10002694: 10002435 .word 0x10002435 +10002698: 2000080c .word 0x2000080c +1000269c: 10001779 .word 0x10001779 +100026a0: 990a ldr r1, [sp, #40] @ 0x28 +100026a2: 9809 ldr r0, [sp, #36] @ 0x24 +100026a4: f851 5b04 ldr.w r5, [r1], #4 +100026a8: 7840 ldrb r0, [r0, #1] +100026aa: 2d00 cmp r5, #0 +100026ac: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +100026b0: bfbc itt lt +100026b2: f043 0302 orrlt.w r3, r3, #2 +100026b6: 426d neglt r5, r5 +100026b8: 3201 adds r2, #1 +100026ba: e702 b.n 100024c2 <_vsnprintf+0x8e> +100026bc: 4642 mov r2, r8 +100026be: 464b mov r3, r9 +100026c0: 4651 mov r1, sl +100026c2: f108 0801 add.w r8, r8, #1 +100026c6: 47d8 blx fp +100026c8: e6d2 b.n 10002470 <_vsnprintf+0x3c> +100026ca: 990a ldr r1, [sp, #40] @ 0x28 +100026cc: 2e00 cmp r6, #0 +100026ce: f851 7b04 ldr.w r7, [r1], #4 +100026d2: bf18 it ne +100026d4: 4632 movne r2, r6 +100026d6: 7838 ldrb r0, [r7, #0] +100026d8: bf08 it eq +100026da: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +100026de: 2800 cmp r0, #0 +100026e0: f000 837b beq.w 10002dda <_vsnprintf+0x9a6> +100026e4: 18bc adds r4, r7, r2 +100026e6: 46a4 mov ip, r4 +100026e8: 463a mov r2, r7 +100026ea: e004 b.n 100026f6 <_vsnprintf+0x2c2> +100026ec: f812 4f01 ldrb.w r4, [r2, #1]! +100026f0: 2c00 cmp r4, #0 +100026f2: f000 813f beq.w 10002974 <_vsnprintf+0x540> +100026f6: 4594 cmp ip, r2 +100026f8: d1f8 bne.n 100026ec <_vsnprintf+0x2b8> +100026fa: 4664 mov r4, ip +100026fc: 1be4 subs r4, r4, r7 +100026fe: 055a lsls r2, r3, #21 +10002700: f140 8122 bpl.w 10002948 <_vsnprintf+0x514> +10002704: 42b4 cmp r4, r6 +10002706: bf28 it cs +10002708: 4634 movcs r4, r6 +1000270a: f013 0302 ands.w r3, r3, #2 +1000270e: f000 8288 beq.w 10002c22 <_vsnprintf+0x7ee> +10002712: 2302 movs r3, #2 +10002714: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002718: 4642 mov r2, r8 +1000271a: 461d mov r5, r3 +1000271c: 4446 add r6, r8 +1000271e: e008 b.n 10002732 <_vsnprintf+0x2fe> +10002720: 464b mov r3, r9 +10002722: 4651 mov r1, sl +10002724: 47d8 blx fp +10002726: f817 0f01 ldrb.w r0, [r7, #1]! +1000272a: f108 0801 add.w r8, r8, #1 +1000272e: b110 cbz r0, 10002736 <_vsnprintf+0x302> +10002730: 4642 mov r2, r8 +10002732: 4546 cmp r6, r8 +10002734: d1f4 bne.n 10002720 <_vsnprintf+0x2ec> +10002736: 462b mov r3, r5 +10002738: 990b ldr r1, [sp, #44] @ 0x2c +1000273a: 9d0a ldr r5, [sp, #40] @ 0x28 +1000273c: 2b00 cmp r3, #0 +1000273e: f040 8141 bne.w 100029c4 <_vsnprintf+0x590> +10002742: 910a str r1, [sp, #40] @ 0x28 +10002744: e694 b.n 10002470 <_vsnprintf+0x3c> +10002746: 9909 ldr r1, [sp, #36] @ 0x24 +10002748: 7848 ldrb r0, [r1, #1] +1000274a: 286c cmp r0, #108 @ 0x6c +1000274c: f47f aeec bne.w 10002528 <_vsnprintf+0xf4> +10002750: 460a mov r2, r1 +10002752: 7888 ldrb r0, [r1, #2] +10002754: f443 7340 orr.w r3, r3, #768 @ 0x300 +10002758: 3203 adds r2, #3 +1000275a: e6e8 b.n 1000252e <_vsnprintf+0xfa> +1000275c: 9909 ldr r1, [sp, #36] @ 0x24 +1000275e: f443 7300 orr.w r3, r3, #512 @ 0x200 +10002762: 7848 ldrb r0, [r1, #1] +10002764: 3201 adds r2, #1 +10002766: e6e2 b.n 1000252e <_vsnprintf+0xfa> +10002768: 9909 ldr r1, [sp, #36] @ 0x24 +1000276a: 7848 ldrb r0, [r1, #1] +1000276c: 2868 cmp r0, #104 @ 0x68 +1000276e: f000 8103 beq.w 10002978 <_vsnprintf+0x544> +10002772: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002776: 3201 adds r2, #1 +10002778: e6d9 b.n 1000252e <_vsnprintf+0xfa> +1000277a: 2867 cmp r0, #103 @ 0x67 +1000277c: f000 80d9 beq.w 10002932 <_vsnprintf+0x4fe> +10002780: 2847 cmp r0, #71 @ 0x47 +10002782: f000 80dc beq.w 1000293e <_vsnprintf+0x50a> +10002786: 2845 cmp r0, #69 @ 0x45 +10002788: f000 80db beq.w 10002942 <_vsnprintf+0x50e> +1000278c: e9cd 5303 strd r5, r3, [sp, #12] +10002790: 9b0a ldr r3, [sp, #40] @ 0x28 +10002792: 9602 str r6, [sp, #8] +10002794: 3307 adds r3, #7 +10002796: f023 0307 bic.w r3, r3, #7 +1000279a: 461c mov r4, r3 +1000279c: 4642 mov r2, r8 +1000279e: e8f4 6702 ldrd r6, r7, [r4], #8 +100027a2: 464b mov r3, r9 +100027a4: 4651 mov r1, sl +100027a6: 4658 mov r0, fp +100027a8: e9cd 6700 strd r6, r7, [sp] +100027ac: 940a str r4, [sp, #40] @ 0x28 +100027ae: f7ff fb87 bl 10001ec0 <_etoa> +100027b2: 4680 mov r8, r0 +100027b4: e65c b.n 10002470 <_vsnprintf+0x3c> +100027b6: 2846 cmp r0, #70 @ 0x46 +100027b8: bf08 it eq +100027ba: f043 0320 orreq.w r3, r3, #32 +100027be: e9cd 5303 strd r5, r3, [sp, #12] +100027c2: 9b0a ldr r3, [sp, #40] @ 0x28 +100027c4: 9602 str r6, [sp, #8] +100027c6: 3307 adds r3, #7 +100027c8: f023 0307 bic.w r3, r3, #7 +100027cc: 461c mov r4, r3 +100027ce: 4642 mov r2, r8 +100027d0: e8f4 6702 ldrd r6, r7, [r4], #8 +100027d4: 464b mov r3, r9 +100027d6: 4651 mov r1, sl +100027d8: 4658 mov r0, fp +100027da: e9cd 6700 strd r6, r7, [sp] +100027de: 940a str r4, [sp, #40] @ 0x28 +100027e0: f7ff f90e bl 10001a00 <_ftoa> +100027e4: 4680 mov r8, r0 +100027e6: e643 b.n 10002470 <_vsnprintf+0x3c> +100027e8: 4642 mov r2, r8 +100027ea: 464b mov r3, r9 +100027ec: 4651 mov r1, sl +100027ee: 2025 movs r0, #37 @ 0x25 +100027f0: f108 0801 add.w r8, r8, #1 +100027f4: 47d8 blx fp +100027f6: e63b b.n 10002470 <_vsnprintf+0x3c> +100027f8: 9a0a ldr r2, [sp, #40] @ 0x28 +100027fa: 0799 lsls r1, r3, #30 +100027fc: f102 0404 add.w r4, r2, #4 +10002800: f108 0601 add.w r6, r8, #1 +10002804: f140 80c6 bpl.w 10002994 <_vsnprintf+0x560> +10002808: 7810 ldrb r0, [r2, #0] +1000280a: 464b mov r3, r9 +1000280c: 4642 mov r2, r8 +1000280e: 4651 mov r1, sl +10002810: 47d8 blx fp +10002812: 2d01 cmp r5, #1 +10002814: bf88 it hi +10002816: 44a8 addhi r8, r5 +10002818: f240 81bd bls.w 10002b96 <_vsnprintf+0x762> +1000281c: 4632 mov r2, r6 +1000281e: 464b mov r3, r9 +10002820: 4651 mov r1, sl +10002822: 2020 movs r0, #32 +10002824: 3601 adds r6, #1 +10002826: 47d8 blx fp +10002828: 4546 cmp r6, r8 +1000282a: d1f7 bne.n 1000281c <_vsnprintf+0x3e8> +1000282c: 940a str r4, [sp, #40] @ 0x28 +1000282e: e61f b.n 10002470 <_vsnprintf+0x3c> +10002830: 286f cmp r0, #111 @ 0x6f +10002832: f000 8081 beq.w 10002938 <_vsnprintf+0x504> +10002836: f240 8248 bls.w 10002cca <_vsnprintf+0x896> +1000283a: 2878 cmp r0, #120 @ 0x78 +1000283c: f000 8190 beq.w 10002b60 <_vsnprintf+0x72c> +10002840: 270a movs r7, #10 +10002842: f023 0310 bic.w r3, r3, #16 +10002846: 46bc mov ip, r7 +10002848: e041 b.n 100028ce <_vsnprintf+0x49a> +1000284a: 2600 movs r6, #0 +1000284c: eb06 0686 add.w r6, r6, r6, lsl #2 +10002850: eb00 0046 add.w r0, r0, r6, lsl #1 +10002854: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002858: f811 0f01 ldrb.w r0, [r1, #1]! +1000285c: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002860: 2a09 cmp r2, #9 +10002862: d9f3 bls.n 1000284c <_vsnprintf+0x418> +10002864: 460a mov r2, r1 +10002866: 9109 str r1, [sp, #36] @ 0x24 +10002868: 3201 adds r2, #1 +1000286a: e62e b.n 100024ca <_vsnprintf+0x96> +1000286c: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002870: f851 6b04 ldr.w r6, [r1], #4 +10002874: 7890 ldrb r0, [r2, #2] +10002876: 3202 adds r2, #2 +10002878: 9209 str r2, [sp, #36] @ 0x24 +1000287a: 910a str r1, [sp, #40] @ 0x28 +1000287c: 3201 adds r2, #1 +1000287e: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002882: e622 b.n 100024ca <_vsnprintf+0x96> +10002884: f023 0010 bic.w r0, r3, #16 +10002888: f413 6280 ands.w r2, r3, #1024 @ 0x400 +1000288c: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002890: f43f aee7 beq.w 10002662 <_vsnprintf+0x22e> +10002894: ab12 add r3, sp, #72 @ 0x48 +10002896: 930b str r3, [sp, #44] @ 0x2c +10002898: 9b0b ldr r3, [sp, #44] @ 0x2c +1000289a: 9006 str r0, [sp, #24] +1000289c: 9300 str r3, [sp, #0] +1000289e: 2308 movs r3, #8 +100028a0: 2010 movs r0, #16 +100028a2: 9305 str r3, [sp, #20] +100028a4: 2300 movs r3, #0 +100028a6: 4642 mov r2, r8 +100028a8: e9cd 3002 strd r3, r0, [sp, #8] +100028ac: 9101 str r1, [sp, #4] +100028ae: 464b mov r3, r9 +100028b0: 4651 mov r1, sl +100028b2: 4658 mov r0, fp +100028b4: 9604 str r6, [sp, #16] +100028b6: f7fe ffaf bl 10001818 <_ntoa_format> +100028ba: 950a str r5, [sp, #40] @ 0x28 +100028bc: 4680 mov r8, r0 +100028be: e5d7 b.n 10002470 <_vsnprintf+0x3c> +100028c0: 2858 cmp r0, #88 @ 0x58 +100028c2: d062 beq.n 1000298a <_vsnprintf+0x556> +100028c4: 2862 cmp r0, #98 @ 0x62 +100028c6: f040 808f bne.w 100029e8 <_vsnprintf+0x5b4> +100028ca: 2702 movs r7, #2 +100028cc: 46bc mov ip, r7 +100028ce: f413 6080 ands.w r0, r3, #1024 @ 0x400 +100028d2: f000 80dd beq.w 10002a90 <_vsnprintf+0x65c> +100028d6: f023 030d bic.w r3, r3, #13 +100028da: f413 7200 ands.w r2, r3, #512 @ 0x200 +100028de: f040 8181 bne.w 10002be4 <_vsnprintf+0x7b0> +100028e2: 990a ldr r1, [sp, #40] @ 0x28 +100028e4: 1d0f adds r7, r1, #4 +100028e6: f413 7180 ands.w r1, r3, #256 @ 0x100 +100028ea: f040 8237 bne.w 10002d5c <_vsnprintf+0x928> +100028ee: 065c lsls r4, r3, #25 +100028f0: 9a0a ldr r2, [sp, #40] @ 0x28 +100028f2: f140 813b bpl.w 10002b6c <_vsnprintf+0x738> +100028f6: 7812 ldrb r2, [r2, #0] +100028f8: 2a00 cmp r2, #0 +100028fa: f040 814e bne.w 10002b9a <_vsnprintf+0x766> +100028fe: f023 0310 bic.w r3, r3, #16 +10002902: 2800 cmp r0, #0 +10002904: f000 8149 beq.w 10002b9a <_vsnprintf+0x766> +10002908: 4611 mov r1, r2 +1000290a: aa12 add r2, sp, #72 @ 0x48 +1000290c: 920b str r2, [sp, #44] @ 0x2c +1000290e: e9cd 5305 strd r5, r3, [sp, #20] +10002912: e9cd c603 strd ip, r6, [sp, #12] +10002916: 9101 str r1, [sp, #4] +10002918: 9b0b ldr r3, [sp, #44] @ 0x2c +1000291a: 4642 mov r2, r8 +1000291c: 9300 str r3, [sp, #0] +1000291e: 2300 movs r3, #0 +10002920: 4651 mov r1, sl +10002922: 9302 str r3, [sp, #8] +10002924: 4658 mov r0, fp +10002926: 464b mov r3, r9 +10002928: f7fe ff76 bl 10001818 <_ntoa_format> +1000292c: 970a str r7, [sp, #40] @ 0x28 +1000292e: 4680 mov r8, r0 +10002930: e59e b.n 10002470 <_vsnprintf+0x3c> +10002932: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002936: e729 b.n 1000278c <_vsnprintf+0x358> +10002938: 2708 movs r7, #8 +1000293a: 46bc mov ip, r7 +1000293c: e7c7 b.n 100028ce <_vsnprintf+0x49a> +1000293e: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002942: f043 0320 orr.w r3, r3, #32 +10002946: e721 b.n 1000278c <_vsnprintf+0x358> +10002948: f013 0302 ands.w r3, r3, #2 +1000294c: f000 818e beq.w 10002c6c <_vsnprintf+0x838> +10002950: 2302 movs r3, #2 +10002952: 950a str r5, [sp, #40] @ 0x28 +10002954: 461e mov r6, r3 +10002956: 460d mov r5, r1 +10002958: 4642 mov r2, r8 +1000295a: 464b mov r3, r9 +1000295c: 4651 mov r1, sl +1000295e: 47d8 blx fp +10002960: f817 0f01 ldrb.w r0, [r7, #1]! +10002964: f108 0801 add.w r8, r8, #1 +10002968: 2800 cmp r0, #0 +1000296a: d1f5 bne.n 10002958 <_vsnprintf+0x524> +1000296c: 4629 mov r1, r5 +1000296e: 4633 mov r3, r6 +10002970: 9d0a ldr r5, [sp, #40] @ 0x28 +10002972: e6e3 b.n 1000273c <_vsnprintf+0x308> +10002974: 1bd4 subs r4, r2, r7 +10002976: e6c2 b.n 100026fe <_vsnprintf+0x2ca> +10002978: 460a mov r2, r1 +1000297a: 7888 ldrb r0, [r1, #2] +1000297c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002980: 3203 adds r2, #3 +10002982: e5d4 b.n 1000252e <_vsnprintf+0xfa> +10002984: 4604 mov r4, r0 +10002986: 4680 mov r8, r0 +10002988: e646 b.n 10002618 <_vsnprintf+0x1e4> +1000298a: 2710 movs r7, #16 +1000298c: f043 0320 orr.w r3, r3, #32 +10002990: 46bc mov ip, r7 +10002992: e79c b.n 100028ce <_vsnprintf+0x49a> +10002994: 2d01 cmp r5, #1 +10002996: f240 80f8 bls.w 10002b8a <_vsnprintf+0x756> +1000299a: 4646 mov r6, r8 +1000299c: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +100029a0: 442f add r7, r5 +100029a2: 4632 mov r2, r6 +100029a4: 464b mov r3, r9 +100029a6: 4651 mov r1, sl +100029a8: 2020 movs r0, #32 +100029aa: 3601 adds r6, #1 +100029ac: 47d8 blx fp +100029ae: 42be cmp r6, r7 +100029b0: d1f7 bne.n 100029a2 <_vsnprintf+0x56e> +100029b2: 9b0a ldr r3, [sp, #40] @ 0x28 +100029b4: 4632 mov r2, r6 +100029b6: 7818 ldrb r0, [r3, #0] +100029b8: 4651 mov r1, sl +100029ba: 464b mov r3, r9 +100029bc: 47d8 blx fp +100029be: 44a8 add r8, r5 +100029c0: 940a str r4, [sp, #40] @ 0x28 +100029c2: e555 b.n 10002470 <_vsnprintf+0x3c> +100029c4: 4646 mov r6, r8 +100029c6: 42a5 cmp r5, r4 +100029c8: f67f aebb bls.w 10002742 <_vsnprintf+0x30e> +100029cc: 44a8 add r8, r5 +100029ce: eba8 0804 sub.w r8, r8, r4 +100029d2: 460c mov r4, r1 +100029d4: 4632 mov r2, r6 +100029d6: 464b mov r3, r9 +100029d8: 4651 mov r1, sl +100029da: 2020 movs r0, #32 +100029dc: 3601 adds r6, #1 +100029de: 47d8 blx fp +100029e0: 4546 cmp r6, r8 +100029e2: d1f7 bne.n 100029d4 <_vsnprintf+0x5a0> +100029e4: 4621 mov r1, r4 +100029e6: e6ac b.n 10002742 <_vsnprintf+0x30e> +100029e8: f413 6280 ands.w r2, r3, #1024 @ 0x400 +100029ec: f000 80bb beq.w 10002b66 <_vsnprintf+0x732> +100029f0: f44f 6280 mov.w r2, #1024 @ 0x400 +100029f4: f023 0c11 bic.w ip, r3, #17 +100029f8: f41c 7700 ands.w r7, ip, #512 @ 0x200 +100029fc: 9b0a ldr r3, [sp, #40] @ 0x28 +100029fe: d14a bne.n 10002a96 <_vsnprintf+0x662> +10002a00: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002a04: f103 0404 add.w r4, r3, #4 +10002a08: f040 8134 bne.w 10002c74 <_vsnprintf+0x840> +10002a0c: f01c 0f40 tst.w ip, #64 @ 0x40 +10002a10: f040 80a3 bne.w 10002b5a <_vsnprintf+0x726> +10002a14: f01c 0f80 tst.w ip, #128 @ 0x80 +10002a18: f000 81d3 beq.w 10002dc2 <_vsnprintf+0x98e> +10002a1c: f9b3 1000 ldrsh.w r1, [r3] +10002a20: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002a24: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002a28: b2bf uxth r7, r7 +10002a2a: 0fcb lsrs r3, r1, #31 +10002a2c: 2900 cmp r1, #0 +10002a2e: f000 8156 beq.w 10002cde <_vsnprintf+0x8aa> +10002a32: 463a mov r2, r7 +10002a34: a912 add r1, sp, #72 @ 0x48 +10002a36: 460f mov r7, r1 +10002a38: f8df e3d8 ldr.w lr, [pc, #984] @ 10002e14 <_vsnprintf+0x9e0> +10002a3c: 910b str r1, [sp, #44] @ 0x2c +10002a3e: 930a str r3, [sp, #40] @ 0x28 +10002a40: 950c str r5, [sp, #48] @ 0x30 +10002a42: e001 b.n 10002a48 <_vsnprintf+0x614> +10002a44: 2820 cmp r0, #32 +10002a46: d00f beq.n 10002a68 <_vsnprintf+0x634> +10002a48: 4615 mov r5, r2 +10002a4a: fbae 1302 umull r1, r3, lr, r2 +10002a4e: 08db lsrs r3, r3, #3 +10002a50: eb03 0183 add.w r1, r3, r3, lsl #2 +10002a54: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002a58: 3130 adds r1, #48 @ 0x30 +10002a5a: 2d09 cmp r5, #9 +10002a5c: 461a mov r2, r3 +10002a5e: f100 0001 add.w r0, r0, #1 +10002a62: f807 1b01 strb.w r1, [r7], #1 +10002a66: d8ed bhi.n 10002a44 <_vsnprintf+0x610> +10002a68: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a6a: 9d0c ldr r5, [sp, #48] @ 0x30 +10002a6c: e9cd 5c05 strd r5, ip, [sp, #20] +10002a70: e9cd 0301 strd r0, r3, [sp, #4] +10002a74: 9604 str r6, [sp, #16] +10002a76: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a78: 4642 mov r2, r8 +10002a7a: 9300 str r3, [sp, #0] +10002a7c: 230a movs r3, #10 +10002a7e: 4651 mov r1, sl +10002a80: 9303 str r3, [sp, #12] +10002a82: 4658 mov r0, fp +10002a84: 464b mov r3, r9 +10002a86: f7fe fec7 bl 10001818 <_ntoa_format> +10002a8a: 940a str r4, [sp, #40] @ 0x28 +10002a8c: 4680 mov r8, r0 +10002a8e: e4ef b.n 10002470 <_vsnprintf+0x3c> +10002a90: f023 030c bic.w r3, r3, #12 +10002a94: e721 b.n 100028da <_vsnprintf+0x4a6> +10002a96: 3307 adds r3, #7 +10002a98: f023 0307 bic.w r3, r3, #7 +10002a9c: 4619 mov r1, r3 +10002a9e: 4608 mov r0, r1 +10002aa0: 685b ldr r3, [r3, #4] +10002aa2: f850 1b08 ldr.w r1, [r0], #8 +10002aa6: 0fdf lsrs r7, r3, #31 +10002aa8: 900a str r0, [sp, #40] @ 0x28 +10002aaa: ea51 0003 orrs.w r0, r1, r3 +10002aae: d162 bne.n 10002b76 <_vsnprintf+0x742> +10002ab0: 2a00 cmp r2, #0 +10002ab2: f040 819f bne.w 10002df4 <_vsnprintf+0x9c0> +10002ab6: 4613 mov r3, r2 +10002ab8: 4611 mov r1, r2 +10002aba: aa12 add r2, sp, #72 @ 0x48 +10002abc: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002ac0: 2000 movs r0, #0 +10002ac2: 4615 mov r5, r2 +10002ac4: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002ac8: f8df e348 ldr.w lr, [pc, #840] @ 10002e14 <_vsnprintf+0x9e0> +10002acc: 920b str r2, [sp, #44] @ 0x2c +10002ace: e001 b.n 10002ad4 <_vsnprintf+0x6a0> +10002ad0: 2820 cmp r0, #32 +10002ad2: d02d beq.n 10002b30 <_vsnprintf+0x6fc> +10002ad4: 185a adds r2, r3, r1 +10002ad6: f142 0200 adc.w r2, r2, #0 +10002ada: fbae 7802 umull r7, r8, lr, r2 +10002ade: f028 0703 bic.w r7, r8, #3 +10002ae2: eb07 0798 add.w r7, r7, r8, lsr #2 +10002ae6: 1bd2 subs r2, r2, r7 +10002ae8: 461e mov r6, r3 +10002aea: 1a9b subs r3, r3, r2 +10002aec: f161 0700 sbc.w r7, r1, #0 +10002af0: 460c mov r4, r1 +10002af2: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002af6: fb01 f103 mul.w r1, r1, r3 +10002afa: fb0e 1107 mla r1, lr, r7, r1 +10002afe: fba3 730e umull r7, r3, r3, lr +10002b02: 4419 add r1, r3 +10002b04: 2305 movs r3, #5 +10002b06: f007 0801 and.w r8, r7, #1 +10002b0a: fba8 3803 umull r3, r8, r8, r3 +10002b0e: 189b adds r3, r3, r2 +10002b10: 2e0a cmp r6, #10 +10002b12: f103 0330 add.w r3, r3, #48 @ 0x30 +10002b16: ea4f 0757 mov.w r7, r7, lsr #1 +10002b1a: f174 0400 sbcs.w r4, r4, #0 +10002b1e: f805 3b01 strb.w r3, [r5], #1 +10002b22: f100 0001 add.w r0, r0, #1 +10002b26: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002b2a: ea4f 0151 mov.w r1, r1, lsr #1 +10002b2e: d2cf bcs.n 10002ad0 <_vsnprintf+0x69c> +10002b30: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002b34: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002b38: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b3a: 4642 mov r2, r8 +10002b3c: 9300 str r3, [sp, #0] +10002b3e: 230a movs r3, #10 +10002b40: e9cd 5c05 strd r5, ip, [sp, #20] +10002b44: e9cd 0701 strd r0, r7, [sp, #4] +10002b48: 9604 str r6, [sp, #16] +10002b4a: 9303 str r3, [sp, #12] +10002b4c: 464b mov r3, r9 +10002b4e: 4651 mov r1, sl +10002b50: 4658 mov r0, fp +10002b52: f7fe fe61 bl 10001818 <_ntoa_format> +10002b56: 4680 mov r8, r0 +10002b58: e48a b.n 10002470 <_vsnprintf+0x3c> +10002b5a: 7819 ldrb r1, [r3, #0] +10002b5c: 460f mov r7, r1 +10002b5e: e764 b.n 10002a2a <_vsnprintf+0x5f6> +10002b60: 2710 movs r7, #16 +10002b62: 46bc mov ip, r7 +10002b64: e6b3 b.n 100028ce <_vsnprintf+0x49a> +10002b66: f023 0c10 bic.w ip, r3, #16 +10002b6a: e745 b.n 100029f8 <_vsnprintf+0x5c4> +10002b6c: 061c lsls r4, r3, #24 +10002b6e: bf4c ite mi +10002b70: 8812 ldrhmi r2, [r2, #0] +10002b72: 6812 ldrpl r2, [r2, #0] +10002b74: e6c0 b.n 100028f8 <_vsnprintf+0x4c4> +10002b76: 460a mov r2, r1 +10002b78: 1e19 subs r1, r3, #0 +10002b7a: db01 blt.n 10002b80 <_vsnprintf+0x74c> +10002b7c: 4613 mov r3, r2 +10002b7e: e79c b.n 10002aba <_vsnprintf+0x686> +10002b80: 4252 negs r2, r2 +10002b82: 4613 mov r3, r2 +10002b84: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002b88: e797 b.n 10002aba <_vsnprintf+0x686> +10002b8a: 4613 mov r3, r2 +10002b8c: 4651 mov r1, sl +10002b8e: 7818 ldrb r0, [r3, #0] +10002b90: 4642 mov r2, r8 +10002b92: 464b mov r3, r9 +10002b94: 47d8 blx fp +10002b96: 46b0 mov r8, r6 +10002b98: e648 b.n 1000282c <_vsnprintf+0x3f8> +10002b9a: f013 0f20 tst.w r3, #32 +10002b9e: bf14 ite ne +10002ba0: 2041 movne r0, #65 @ 0x41 +10002ba2: 2061 moveq r0, #97 @ 0x61 +10002ba4: ac12 add r4, sp, #72 @ 0x48 +10002ba6: 46a6 mov lr, r4 +10002ba8: 940b str r4, [sp, #44] @ 0x2c +10002baa: 930a str r3, [sp, #40] @ 0x28 +10002bac: f1a0 040a sub.w r4, r0, #10 +10002bb0: 950c str r5, [sp, #48] @ 0x30 +10002bb2: e002 b.n 10002bba <_vsnprintf+0x786> +10002bb4: 2920 cmp r1, #32 +10002bb6: d012 beq.n 10002bde <_vsnprintf+0x7aa> +10002bb8: 462a mov r2, r5 +10002bba: fbb2 f5fc udiv r5, r2, ip +10002bbe: fb0c 2015 mls r0, ip, r5, r2 +10002bc2: b2c3 uxtb r3, r0 +10002bc4: 2809 cmp r0, #9 +10002bc6: f103 0030 add.w r0, r3, #48 @ 0x30 +10002bca: bf8a itet hi +10002bcc: 191b addhi r3, r3, r4 +10002bce: b2c3 uxtbls r3, r0 +10002bd0: b2db uxtbhi r3, r3 +10002bd2: 4562 cmp r2, ip +10002bd4: f80e 3b01 strb.w r3, [lr], #1 +10002bd8: f101 0101 add.w r1, r1, #1 +10002bdc: d2ea bcs.n 10002bb4 <_vsnprintf+0x780> +10002bde: 9b0a ldr r3, [sp, #40] @ 0x28 +10002be0: 9d0c ldr r5, [sp, #48] @ 0x30 +10002be2: e694 b.n 1000290e <_vsnprintf+0x4da> +10002be4: 9a0a ldr r2, [sp, #40] @ 0x28 +10002be6: 3207 adds r2, #7 +10002be8: f022 0207 bic.w r2, r2, #7 +10002bec: 6851 ldr r1, [r2, #4] +10002bee: f852 4b08 ldr.w r4, [r2], #8 +10002bf2: 468e mov lr, r1 +10002bf4: 920a str r2, [sp, #40] @ 0x28 +10002bf6: ea54 0201 orrs.w r2, r4, r1 +10002bfa: d176 bne.n 10002cea <_vsnprintf+0x8b6> +10002bfc: f023 0310 bic.w r3, r3, #16 +10002c00: 2800 cmp r0, #0 +10002c02: d072 beq.n 10002cea <_vsnprintf+0x8b6> +10002c04: 2200 movs r2, #0 +10002c06: 4611 mov r1, r2 +10002c08: aa12 add r2, sp, #72 @ 0x48 +10002c0a: 920b str r2, [sp, #44] @ 0x2c +10002c0c: e9cd 5305 strd r5, r3, [sp, #20] +10002c10: 9b0b ldr r3, [sp, #44] @ 0x2c +10002c12: 4642 mov r2, r8 +10002c14: 9300 str r3, [sp, #0] +10002c16: 2300 movs r3, #0 +10002c18: e9cd c603 strd ip, r6, [sp, #12] +10002c1c: 9101 str r1, [sp, #4] +10002c1e: 9302 str r3, [sp, #8] +10002c20: e794 b.n 10002b4c <_vsnprintf+0x718> +10002c22: 42a5 cmp r5, r4 +10002c24: bf98 it ls +10002c26: 3401 addls r4, #1 +10002c28: f67f ad74 bls.w 10002714 <_vsnprintf+0x2e0> +10002c2c: f44f 6380 mov.w r3, #1024 @ 0x400 +10002c30: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002c34: eb05 0208 add.w r2, r5, r8 +10002c38: 461f mov r7, r3 +10002c3a: 460d mov r5, r1 +10002c3c: 1b14 subs r4, r2, r4 +10002c3e: 4642 mov r2, r8 +10002c40: 464b mov r3, r9 +10002c42: 4651 mov r1, sl +10002c44: 2020 movs r0, #32 +10002c46: f108 0801 add.w r8, r8, #1 +10002c4a: 47d8 blx fp +10002c4c: 45a0 cmp r8, r4 +10002c4e: d1f6 bne.n 10002c3e <_vsnprintf+0x80a> +10002c50: 463b mov r3, r7 +10002c52: 9f0a ldr r7, [sp, #40] @ 0x28 +10002c54: 4629 mov r1, r5 +10002c56: 7838 ldrb r0, [r7, #0] +10002c58: 9d0b ldr r5, [sp, #44] @ 0x2c +10002c5a: 1c6c adds r4, r5, #1 +10002c5c: 2800 cmp r0, #0 +10002c5e: f43f ad70 beq.w 10002742 <_vsnprintf+0x30e> +10002c62: 2b00 cmp r3, #0 +10002c64: f43f ae75 beq.w 10002952 <_vsnprintf+0x51e> +10002c68: 2300 movs r3, #0 +10002c6a: e553 b.n 10002714 <_vsnprintf+0x2e0> +10002c6c: 42a5 cmp r5, r4 +10002c6e: d8df bhi.n 10002c30 <_vsnprintf+0x7fc> +10002c70: 3401 adds r4, #1 +10002c72: e66e b.n 10002952 <_vsnprintf+0x51e> +10002c74: 6819 ldr r1, [r3, #0] +10002c76: 0fcb lsrs r3, r1, #31 +10002c78: 2900 cmp r1, #0 +10002c7a: f000 80a8 beq.w 10002dce <_vsnprintf+0x99a> +10002c7e: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002c82: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002c86: a912 add r1, sp, #72 @ 0x48 +10002c88: 4608 mov r0, r1 +10002c8a: f8df e188 ldr.w lr, [pc, #392] @ 10002e14 <_vsnprintf+0x9e0> +10002c8e: 910b str r1, [sp, #44] @ 0x2c +10002c90: 930a str r3, [sp, #40] @ 0x28 +10002c92: 950c str r5, [sp, #48] @ 0x30 +10002c94: e001 b.n 10002c9a <_vsnprintf+0x866> +10002c96: 2f20 cmp r7, #32 +10002c98: d00f beq.n 10002cba <_vsnprintf+0x886> +10002c9a: 4615 mov r5, r2 +10002c9c: fbae 1302 umull r1, r3, lr, r2 +10002ca0: 08db lsrs r3, r3, #3 +10002ca2: eb03 0183 add.w r1, r3, r3, lsl #2 +10002ca6: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002caa: 3130 adds r1, #48 @ 0x30 +10002cac: 2d09 cmp r5, #9 +10002cae: 461a mov r2, r3 +10002cb0: f107 0701 add.w r7, r7, #1 +10002cb4: f800 1b01 strb.w r1, [r0], #1 +10002cb8: d8ed bhi.n 10002c96 <_vsnprintf+0x862> +10002cba: 9b0a ldr r3, [sp, #40] @ 0x28 +10002cbc: 9d0c ldr r5, [sp, #48] @ 0x30 +10002cbe: e9cd 5c05 strd r5, ip, [sp, #20] +10002cc2: e9cd 7301 strd r7, r3, [sp, #4] +10002cc6: 9604 str r6, [sp, #16] +10002cc8: e6d5 b.n 10002a76 <_vsnprintf+0x642> +10002cca: 2869 cmp r0, #105 @ 0x69 +10002ccc: f023 0c10 bic.w ip, r3, #16 +10002cd0: f040 808c bne.w 10002dec <_vsnprintf+0x9b8> +10002cd4: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002cd8: f43f ae8e beq.w 100029f8 <_vsnprintf+0x5c4> +10002cdc: e688 b.n 100029f0 <_vsnprintf+0x5bc> +10002cde: 2a00 cmp r2, #0 +10002ce0: f43f aea8 beq.w 10002a34 <_vsnprintf+0x600> +10002ce4: aa12 add r2, sp, #72 @ 0x48 +10002ce6: 920b str r2, [sp, #44] @ 0x2c +10002ce8: e6c0 b.n 10002a6c <_vsnprintf+0x638> +10002cea: f013 0f20 tst.w r3, #32 +10002cee: bf14 ite ne +10002cf0: 2241 movne r2, #65 @ 0x41 +10002cf2: 2261 moveq r2, #97 @ 0x61 +10002cf4: 2000 movs r0, #0 +10002cf6: a912 add r1, sp, #72 @ 0x48 +10002cf8: 3a0a subs r2, #10 +10002cfa: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002cfe: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002d02: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002d06: 4606 mov r6, r0 +10002d08: 4688 mov r8, r1 +10002d0a: 4675 mov r5, lr +10002d0c: 4693 mov fp, r2 +10002d0e: 910b str r1, [sp, #44] @ 0x2c +10002d10: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002d14: e003 b.n 10002d1e <_vsnprintf+0x8ea> +10002d16: 2e20 cmp r6, #32 +10002d18: d017 beq.n 10002d4a <_vsnprintf+0x916> +10002d1a: 4604 mov r4, r0 +10002d1c: 460d mov r5, r1 +10002d1e: 4629 mov r1, r5 +10002d20: 463a mov r2, r7 +10002d22: 2300 movs r3, #0 +10002d24: 4620 mov r0, r4 +10002d26: f000 fc47 bl 100035b8 <____aeabi_uldivmod_veneer> +10002d2a: b2d2 uxtb r2, r2 +10002d2c: 2a09 cmp r2, #9 +10002d2e: f102 0330 add.w r3, r2, #48 @ 0x30 +10002d32: bf88 it hi +10002d34: eb02 030b addhi.w r3, r2, fp +10002d38: 42bc cmp r4, r7 +10002d3a: b2db uxtb r3, r3 +10002d3c: f175 0500 sbcs.w r5, r5, #0 +10002d40: f808 3b01 strb.w r3, [r8], #1 +10002d44: f106 0601 add.w r6, r6, #1 +10002d48: d2e5 bcs.n 10002d16 <_vsnprintf+0x8e2> +10002d4a: 4631 mov r1, r6 +10002d4c: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002d50: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002d54: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002d58: 9e0e ldr r6, [sp, #56] @ 0x38 +10002d5a: e757 b.n 10002c0c <_vsnprintf+0x7d8> +10002d5c: 990a ldr r1, [sp, #40] @ 0x28 +10002d5e: 6809 ldr r1, [r1, #0] +10002d60: b951 cbnz r1, 10002d78 <_vsnprintf+0x944> +10002d62: f023 0310 bic.w r3, r3, #16 +10002d66: b138 cbz r0, 10002d78 <_vsnprintf+0x944> +10002d68: a912 add r1, sp, #72 @ 0x48 +10002d6a: 910b str r1, [sp, #44] @ 0x2c +10002d6c: e9cd 5305 strd r5, r3, [sp, #20] +10002d70: e9cd c603 strd ip, r6, [sp, #12] +10002d74: 9201 str r2, [sp, #4] +10002d76: e5cf b.n 10002918 <_vsnprintf+0x4e4> +10002d78: f013 0f20 tst.w r3, #32 +10002d7c: bf14 ite ne +10002d7e: 2041 movne r0, #65 @ 0x41 +10002d80: 2061 moveq r0, #97 @ 0x61 +10002d82: ac12 add r4, sp, #72 @ 0x48 +10002d84: 46a6 mov lr, r4 +10002d86: 940b str r4, [sp, #44] @ 0x2c +10002d88: 930a str r3, [sp, #40] @ 0x28 +10002d8a: f1a0 040a sub.w r4, r0, #10 +10002d8e: 950c str r5, [sp, #48] @ 0x30 +10002d90: e002 b.n 10002d98 <_vsnprintf+0x964> +10002d92: 2a20 cmp r2, #32 +10002d94: d012 beq.n 10002dbc <_vsnprintf+0x988> +10002d96: 4629 mov r1, r5 +10002d98: fbb1 f5fc udiv r5, r1, ip +10002d9c: fb0c 1015 mls r0, ip, r5, r1 +10002da0: b2c3 uxtb r3, r0 +10002da2: 2809 cmp r0, #9 +10002da4: f103 0030 add.w r0, r3, #48 @ 0x30 +10002da8: bf8a itet hi +10002daa: 191b addhi r3, r3, r4 +10002dac: b2c3 uxtbls r3, r0 +10002dae: b2db uxtbhi r3, r3 +10002db0: 4561 cmp r1, ip +10002db2: f80e 3b01 strb.w r3, [lr], #1 +10002db6: f102 0201 add.w r2, r2, #1 +10002dba: d2ea bcs.n 10002d92 <_vsnprintf+0x95e> +10002dbc: 9b0a ldr r3, [sp, #40] @ 0x28 +10002dbe: 9d0c ldr r5, [sp, #48] @ 0x30 +10002dc0: e7d4 b.n 10002d6c <_vsnprintf+0x938> +10002dc2: 6819 ldr r1, [r3, #0] +10002dc4: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002dc8: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002dcc: e62d b.n 10002a2a <_vsnprintf+0x5f6> +10002dce: 2a00 cmp r2, #0 +10002dd0: f43f af59 beq.w 10002c86 <_vsnprintf+0x852> +10002dd4: aa12 add r2, sp, #72 @ 0x48 +10002dd6: 920b str r2, [sp, #44] @ 0x2c +10002dd8: e771 b.n 10002cbe <_vsnprintf+0x88a> +10002dda: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002dde: d00d beq.n 10002dfc <_vsnprintf+0x9c8> +10002de0: f013 0402 ands.w r4, r3, #2 +10002de4: d012 beq.n 10002e0c <_vsnprintf+0x9d8> +10002de6: 4604 mov r4, r0 +10002de8: 4646 mov r6, r8 +10002dea: e5ec b.n 100029c6 <_vsnprintf+0x592> +10002dec: 270a movs r7, #10 +10002dee: 4663 mov r3, ip +10002df0: 46bc mov ip, r7 +10002df2: e56c b.n 100028ce <_vsnprintf+0x49a> +10002df4: ab12 add r3, sp, #72 @ 0x48 +10002df6: 2000 movs r0, #0 +10002df8: 930b str r3, [sp, #44] @ 0x2c +10002dfa: e69d b.n 10002b38 <_vsnprintf+0x704> +10002dfc: f013 0302 ands.w r3, r3, #2 +10002e00: f47f ade0 bne.w 100029c4 <_vsnprintf+0x590> +10002e04: 2d00 cmp r5, #0 +10002e06: f47f af13 bne.w 10002c30 <_vsnprintf+0x7fc> +10002e0a: e49a b.n 10002742 <_vsnprintf+0x30e> +10002e0c: 2d00 cmp r5, #0 +10002e0e: f47f af0d bne.w 10002c2c <_vsnprintf+0x7f8> +10002e12: e496 b.n 10002742 <_vsnprintf+0x30e> +10002e14: cccccccd .word 0xcccccccd + +10002e18 : +10002e18: b570 push {r4, r5, r6, lr} +10002e1a: 4694 mov ip, r2 +10002e1c: 461e mov r6, r3 +10002e1e: 4605 mov r5, r0 +10002e20: 460c mov r4, r1 +10002e22: b084 sub sp, #16 +10002e24: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e28: 4663 mov r3, ip +10002e2a: a902 add r1, sp, #8 +10002e2c: 9600 str r6, [sp, #0] +10002e2e: 4803 ldr r0, [pc, #12] @ (10002e3c ) +10002e30: e9cd 5402 strd r5, r4, [sp, #8] +10002e34: f7ff fafe bl 10002434 <_vsnprintf> +10002e38: b004 add sp, #16 +10002e3a: bd70 pop {r4, r5, r6, pc} +10002e3c: 100019f5 .word 0x100019f5 + +10002e40 : +10002e40: b510 push {r4, lr} +10002e42: 4b09 ldr r3, [pc, #36] @ (10002e68 ) +10002e44: b084 sub sp, #16 +10002e46: 681c ldr r4, [r3, #0] +10002e48: b14c cbz r4, 10002e5e +10002e4a: 4603 mov r3, r0 +10002e4c: 9100 str r1, [sp, #0] +10002e4e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e52: a903 add r1, sp, #12 +10002e54: 4805 ldr r0, [pc, #20] @ (10002e6c ) +10002e56: 47a0 blx r4 +10002e58: 2001 movs r0, #1 +10002e5a: b004 add sp, #16 +10002e5c: bd10 pop {r4, pc} +10002e5e: f000 f97d bl 1000315c <__wrap_puts> +10002e62: 4620 mov r0, r4 +10002e64: b004 add sp, #16 +10002e66: bd10 pop {r4, pc} +10002e68: 2000080c .word 0x2000080c +10002e6c: 100019ed .word 0x100019ed + +10002e70 <_exit>: +10002e70: be00 bkpt 0x0000 +10002e72: e7fd b.n 10002e70 <_exit> + +10002e74 : +10002e74: b508 push {r3, lr} +10002e76: f7ff fffb bl 10002e70 <_exit> +10002e7a: bf00 nop + +10002e7c : +10002e7c: b538 push {r3, r4, r5, lr} +10002e7e: 4c06 ldr r4, [pc, #24] @ (10002e98 ) +10002e80: 4d06 ldr r5, [pc, #24] @ (10002e9c ) +10002e82: f7fe fa07 bl 10001294 +10002e86: 42ac cmp r4, r5 +10002e88: d204 bcs.n 10002e94 +10002e8a: f854 3b04 ldr.w r3, [r4], #4 +10002e8e: 4798 blx r3 +10002e90: 42ac cmp r4, r5 +10002e92: d3fa bcc.n 10002e8a +10002e94: bd38 pop {r3, r4, r5, pc} +10002e96: bf00 nop +10002e98: 10003610 .word 0x10003610 +10002e9c: 10003614 .word 0x10003614 + +10002ea0 : +10002ea0: 6803 ldr r3, [r0, #0] +10002ea2: 4608 mov r0, r1 +10002ea4: 4611 mov r1, r2 +10002ea6: 4718 bx r3 + +10002ea8 : +10002ea8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002eac: 4615 mov r5, r2 +10002eae: 7d42 ldrb r2, [r0, #21] +10002eb0: 4607 mov r7, r0 +10002eb2: 4688 mov r8, r1 +10002eb4: 2a00 cmp r2, #0 +10002eb6: d046 beq.n 10002f46 +10002eb8: 2d00 cmp r5, #0 +10002eba: dd1d ble.n 10002ef8 +10002ebc: 780b ldrb r3, [r1, #0] +10002ebe: 2b0a cmp r3, #10 +10002ec0: d023 beq.n 10002f0a +10002ec2: 2d01 cmp r5, #1 +10002ec4: f04f 0c00 mov.w ip, #0 +10002ec8: d018 beq.n 10002efc +10002eca: 4646 mov r6, r8 +10002ecc: 2401 movs r4, #1 +10002ece: f816 2f01 ldrb.w r2, [r6, #1]! +10002ed2: 4621 mov r1, r4 +10002ed4: 2a0a cmp r2, #10 +10002ed6: f104 0401 add.w r4, r4, #1 +10002eda: d022 beq.n 10002f22 +10002edc: 42a5 cmp r5, r4 +10002ede: d1f6 bne.n 10002ece +10002ee0: 4565 cmp r5, ip +10002ee2: dc0b bgt.n 10002efc +10002ee4: eb08 0305 add.w r3, r8, r5 +10002ee8: f813 3c01 ldrb.w r3, [r3, #-1] +10002eec: f1a3 030d sub.w r3, r3, #13 +10002ef0: fab3 f383 clz r3, r3 +10002ef4: 095b lsrs r3, r3, #5 +10002ef6: 753b strb r3, [r7, #20] +10002ef8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002efc: 683b ldr r3, [r7, #0] +10002efe: eba5 010c sub.w r1, r5, ip +10002f02: eb08 000c add.w r0, r8, ip +10002f06: 4798 blx r3 +10002f08: e7ec b.n 10002ee4 +10002f0a: 7d03 ldrb r3, [r0, #20] +10002f0c: 2b00 cmp r3, #0 +10002f0e: d1d8 bne.n 10002ec2 +10002f10: 6803 ldr r3, [r0, #0] +10002f12: 2102 movs r1, #2 +10002f14: 480f ldr r0, [pc, #60] @ (10002f54 ) +10002f16: 4798 blx r3 +10002f18: 2d01 cmp r5, #1 +10002f1a: d0e3 beq.n 10002ee4 +10002f1c: f04f 0c01 mov.w ip, #1 +10002f20: e7d3 b.n 10002eca +10002f22: f816 3c01 ldrb.w r3, [r6, #-1] +10002f26: 2b0d cmp r3, #13 +10002f28: d0d8 beq.n 10002edc +10002f2a: 458c cmp ip, r1 +10002f2c: eb08 000c add.w r0, r8, ip +10002f30: eba1 010c sub.w r1, r1, ip +10002f34: da01 bge.n 10002f3a +10002f36: 683b ldr r3, [r7, #0] +10002f38: 4798 blx r3 +10002f3a: 2102 movs r1, #2 +10002f3c: 4805 ldr r0, [pc, #20] @ (10002f54 ) +10002f3e: 683b ldr r3, [r7, #0] +10002f40: 4798 blx r3 +10002f42: 46a4 mov ip, r4 +10002f44: e7ca b.n 10002edc +10002f46: 4629 mov r1, r5 +10002f48: 4640 mov r0, r8 +10002f4a: 683b ldr r3, [r7, #0] +10002f4c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002f50: 4718 bx r3 +10002f52: bf00 nop +10002f54: 100037b0 .word 0x100037b0 + +10002f58 : +10002f58: 680b ldr r3, [r1, #0] +10002f5a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002f5e: 2b80 cmp r3, #128 @ 0x80 +10002f60: 460d mov r5, r1 +10002f62: 4606 mov r6, r0 +10002f64: d005 beq.n 10002f72 +10002f66: 1c5a adds r2, r3, #1 +10002f68: 442b add r3, r5 +10002f6a: 602a str r2, [r5, #0] +10002f6c: 711e strb r6, [r3, #4] +10002f6e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002f72: 4b0f ldr r3, [pc, #60] @ (10002fb0 ) +10002f74: 681c ldr r4, [r3, #0] +10002f76: b1a4 cbz r4, 10002fa2 +10002f78: 4f0e ldr r7, [pc, #56] @ (10002fb4 ) +10002f7a: f101 0804 add.w r8, r1, #4 +10002f7e: e001 b.n 10002f84 +10002f80: 6924 ldr r4, [r4, #16] +10002f82: b174 cbz r4, 10002fa2 +10002f84: 6823 ldr r3, [r4, #0] +10002f86: 2b00 cmp r3, #0 +10002f88: d0fa beq.n 10002f80 +10002f8a: 683b ldr r3, [r7, #0] +10002f8c: b10b cbz r3, 10002f92 +10002f8e: 42a3 cmp r3, r4 +10002f90: d1f6 bne.n 10002f80 +10002f92: 4620 mov r0, r4 +10002f94: 4641 mov r1, r8 +10002f96: 682a ldr r2, [r5, #0] +10002f98: f7ff ff86 bl 10002ea8 +10002f9c: 6924 ldr r4, [r4, #16] +10002f9e: 2c00 cmp r4, #0 +10002fa0: d1f0 bne.n 10002f84 +10002fa2: 2300 movs r3, #0 +10002fa4: 2201 movs r2, #1 +10002fa6: 442b add r3, r5 +10002fa8: 602a str r2, [r5, #0] +10002faa: 711e strb r6, [r3, #4] +10002fac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002fb0: 20000804 .word 0x20000804 +10002fb4: 20000808 .word 0x20000808 + +10002fb8 : +10002fb8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002fbc: b082 sub sp, #8 +10002fbe: 460d mov r5, r1 +10002fc0: 4691 mov r9, r2 +10002fc2: 461c mov r4, r3 +10002fc4: 4606 mov r6, r0 +10002fc6: f7fd ff95 bl 10000ef4 +10002fca: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002fce: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002fd2: 4a2e ldr r2, [pc, #184] @ (1000308c ) +10002fd4: 1882 adds r2, r0, r2 +10002fd6: f141 0300 adc.w r3, r1, #0 +10002fda: 4594 cmp ip, r2 +10002fdc: eb77 0103 sbcs.w r1, r7, r3 +10002fe0: bf3c itt cc +10002fe2: 4662 movcc r2, ip +10002fe4: 463b movcc r3, r7 +10002fe6: 482a ldr r0, [pc, #168] @ (10003090 ) +10002fe8: f000 faee bl 100035c8 <__mutex_try_enter_block_until_veneer> +10002fec: 1c6b adds r3, r5, #1 +10002fee: 4680 mov r8, r0 +10002ff0: d040 beq.n 10003074 +10002ff2: b30c cbz r4, 10003038 +10002ff4: 4f27 ldr r7, [pc, #156] @ (10003094 ) +10002ff6: 4b28 ldr r3, [pc, #160] @ (10003098 ) +10002ff8: 681c ldr r4, [r3, #0] +10002ffa: b1b4 cbz r4, 1000302a +10002ffc: f1b9 0f00 cmp.w r9, #0 +10003000: d11c bne.n 1000303c +10003002: f8df 909c ldr.w r9, [pc, #156] @ 100030a0 +10003006: e001 b.n 1000300c +10003008: 6924 ldr r4, [r4, #16] +1000300a: b174 cbz r4, 1000302a +1000300c: 6823 ldr r3, [r4, #0] +1000300e: 2b00 cmp r3, #0 +10003010: d0fa beq.n 10003008 +10003012: f8d9 3000 ldr.w r3, [r9] +10003016: b10b cbz r3, 1000301c +10003018: 429c cmp r4, r3 +1000301a: d1f5 bne.n 10003008 +1000301c: 4620 mov r0, r4 +1000301e: 462a mov r2, r5 +10003020: 4631 mov r1, r6 +10003022: 47b8 blx r7 +10003024: 6924 ldr r4, [r4, #16] +10003026: 2c00 cmp r4, #0 +10003028: d1f0 bne.n 1000300c +1000302a: f1b8 0f00 cmp.w r8, #0 +1000302e: d126 bne.n 1000307e +10003030: 4628 mov r0, r5 +10003032: b002 add sp, #8 +10003034: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003038: 4f18 ldr r7, [pc, #96] @ (1000309c ) +1000303a: e7dc b.n 10002ff6 +1000303c: f04f 0a0a mov.w sl, #10 +10003040: f8df 905c ldr.w r9, [pc, #92] @ 100030a0 +10003044: e002 b.n 1000304c +10003046: 6924 ldr r4, [r4, #16] +10003048: 2c00 cmp r4, #0 +1000304a: d0ee beq.n 1000302a +1000304c: 6823 ldr r3, [r4, #0] +1000304e: 2b00 cmp r3, #0 +10003050: d0f9 beq.n 10003046 +10003052: f8d9 3000 ldr.w r3, [r9] +10003056: b10b cbz r3, 1000305c +10003058: 42a3 cmp r3, r4 +1000305a: d1f4 bne.n 10003046 +1000305c: 462a mov r2, r5 +1000305e: 4631 mov r1, r6 +10003060: 4620 mov r0, r4 +10003062: 47b8 blx r7 +10003064: 2201 movs r2, #1 +10003066: 4620 mov r0, r4 +10003068: f10d 0107 add.w r1, sp, #7 +1000306c: f88d a007 strb.w sl, [sp, #7] +10003070: 47b8 blx r7 +10003072: e7e8 b.n 10003046 +10003074: 4630 mov r0, r6 +10003076: f000 fa6f bl 10003558 +1000307a: 4605 mov r5, r0 +1000307c: e7b9 b.n 10002ff2 +1000307e: 4804 ldr r0, [pc, #16] @ (10003090 ) +10003080: f000 fa9e bl 100035c0 <__mutex_exit_veneer> +10003084: 4628 mov r0, r5 +10003086: b002 add sp, #8 +10003088: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000308c: 000f4240 .word 0x000f4240 +10003090: 20000624 .word 0x20000624 +10003094: 10002ea9 .word 0x10002ea9 +10003098: 20000804 .word 0x20000804 +1000309c: 10002ea1 .word 0x10002ea1 +100030a0: 20000808 .word 0x20000808 + +100030a4 : +100030a4: 4a08 ldr r2, [pc, #32] @ (100030c8 ) +100030a6: 6813 ldr r3, [r2, #0] +100030a8: b923 cbnz r3, 100030b4 +100030aa: e00a b.n 100030c2 +100030ac: f103 0210 add.w r2, r3, #16 +100030b0: 691b ldr r3, [r3, #16] +100030b2: b133 cbz r3, 100030c2 +100030b4: 4283 cmp r3, r0 +100030b6: d1f9 bne.n 100030ac +100030b8: b929 cbnz r1, 100030c6 +100030ba: 6918 ldr r0, [r3, #16] +100030bc: 6010 str r0, [r2, #0] +100030be: 6119 str r1, [r3, #16] +100030c0: 4770 bx lr +100030c2: b101 cbz r1, 100030c6 +100030c4: 6010 str r0, [r2, #0] +100030c6: 4770 bx lr +100030c8: 20000804 .word 0x20000804 + +100030cc : +100030cc: b508 push {r3, lr} +100030ce: f000 f9a3 bl 10003418 +100030d2: 2001 movs r0, #1 +100030d4: bd08 pop {r3, pc} +100030d6: bf00 nop + +100030d8 <__wrap_putchar>: +100030d8: b5f0 push {r4, r5, r6, r7, lr} +100030da: b083 sub sp, #12 +100030dc: 4606 mov r6, r0 +100030de: f88d 0007 strb.w r0, [sp, #7] +100030e2: f7fd ff07 bl 10000ef4 +100030e6: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100030ea: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100030ee: 4a17 ldr r2, [pc, #92] @ (1000314c <__wrap_putchar+0x74>) +100030f0: 1882 adds r2, r0, r2 +100030f2: f141 0300 adc.w r3, r1, #0 +100030f6: 4295 cmp r5, r2 +100030f8: eb74 0103 sbcs.w r1, r4, r3 +100030fc: bf3c itt cc +100030fe: 4623 movcc r3, r4 +10003100: 462a movcc r2, r5 +10003102: 4813 ldr r0, [pc, #76] @ (10003150 <__wrap_putchar+0x78>) +10003104: f000 fa60 bl 100035c8 <__mutex_try_enter_block_until_veneer> +10003108: 4b12 ldr r3, [pc, #72] @ (10003154 <__wrap_putchar+0x7c>) +1000310a: 4607 mov r7, r0 +1000310c: 681c ldr r4, [r3, #0] +1000310e: b19c cbz r4, 10003138 <__wrap_putchar+0x60> +10003110: 4d11 ldr r5, [pc, #68] @ (10003158 <__wrap_putchar+0x80>) +10003112: e001 b.n 10003118 <__wrap_putchar+0x40> +10003114: 6924 ldr r4, [r4, #16] +10003116: b17c cbz r4, 10003138 <__wrap_putchar+0x60> +10003118: 6823 ldr r3, [r4, #0] +1000311a: 2b00 cmp r3, #0 +1000311c: d0fa beq.n 10003114 <__wrap_putchar+0x3c> +1000311e: 682b ldr r3, [r5, #0] +10003120: b10b cbz r3, 10003126 <__wrap_putchar+0x4e> +10003122: 429c cmp r4, r3 +10003124: d1f6 bne.n 10003114 <__wrap_putchar+0x3c> +10003126: 4620 mov r0, r4 +10003128: 2201 movs r2, #1 +1000312a: f10d 0107 add.w r1, sp, #7 +1000312e: f7ff febb bl 10002ea8 +10003132: 6924 ldr r4, [r4, #16] +10003134: 2c00 cmp r4, #0 +10003136: d1ef bne.n 10003118 <__wrap_putchar+0x40> +10003138: b917 cbnz r7, 10003140 <__wrap_putchar+0x68> +1000313a: 4630 mov r0, r6 +1000313c: b003 add sp, #12 +1000313e: bdf0 pop {r4, r5, r6, r7, pc} +10003140: 4803 ldr r0, [pc, #12] @ (10003150 <__wrap_putchar+0x78>) +10003142: f000 fa3d bl 100035c0 <__mutex_exit_veneer> +10003146: 4630 mov r0, r6 +10003148: b003 add sp, #12 +1000314a: bdf0 pop {r4, r5, r6, r7, pc} +1000314c: 000f4240 .word 0x000f4240 +10003150: 20000624 .word 0x20000624 +10003154: 20000804 .word 0x20000804 +10003158: 20000808 .word 0x20000808 + +1000315c <__wrap_puts>: +1000315c: b538 push {r3, r4, r5, lr} +1000315e: 4604 mov r4, r0 +10003160: f000 f9fa bl 10003558 +10003164: 2301 movs r3, #1 +10003166: 4605 mov r5, r0 +10003168: 461a mov r2, r3 +1000316a: 4620 mov r0, r4 +1000316c: 4629 mov r1, r5 +1000316e: f7ff ff23 bl 10002fb8 +10003172: 4b08 ldr r3, [pc, #32] @ (10003194 <__wrap_puts+0x38>) +10003174: 681c ldr r4, [r3, #0] +10003176: b12c cbz r4, 10003184 <__wrap_puts+0x28> +10003178: 6863 ldr r3, [r4, #4] +1000317a: b12b cbz r3, 10003188 <__wrap_puts+0x2c> +1000317c: 4798 blx r3 +1000317e: 6924 ldr r4, [r4, #16] +10003180: 2c00 cmp r4, #0 +10003182: d1f9 bne.n 10003178 <__wrap_puts+0x1c> +10003184: 4628 mov r0, r5 +10003186: bd38 pop {r3, r4, r5, pc} +10003188: 6924 ldr r4, [r4, #16] +1000318a: 2c00 cmp r4, #0 +1000318c: d1f4 bne.n 10003178 <__wrap_puts+0x1c> +1000318e: 4628 mov r0, r5 +10003190: bd38 pop {r3, r4, r5, pc} +10003192: bf00 nop +10003194: 20000804 .word 0x20000804 + +10003198 <__wrap_vprintf>: +10003198: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000319c: b0a2 sub sp, #136 @ 0x88 +1000319e: 4604 mov r4, r0 +100031a0: 460d mov r5, r1 +100031a2: f7fd fea7 bl 10000ef4 +100031a6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +100031aa: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +100031ae: 4a26 ldr r2, [pc, #152] @ (10003248 <__wrap_vprintf+0xb0>) +100031b0: f8df 80a4 ldr.w r8, [pc, #164] @ 10003258 <__wrap_vprintf+0xc0> +100031b4: 1882 adds r2, r0, r2 +100031b6: f141 0300 adc.w r3, r1, #0 +100031ba: 4297 cmp r7, r2 +100031bc: eb76 0103 sbcs.w r1, r6, r3 +100031c0: bf3c itt cc +100031c2: 463a movcc r2, r7 +100031c4: 4633 movcc r3, r6 +100031c6: 4821 ldr r0, [pc, #132] @ (1000324c <__wrap_vprintf+0xb4>) +100031c8: f000 f9fe bl 100035c8 <__mutex_try_enter_block_until_veneer> +100031cc: 2700 movs r7, #0 +100031ce: 462b mov r3, r5 +100031d0: 4622 mov r2, r4 +100031d2: 4606 mov r6, r0 +100031d4: a901 add r1, sp, #4 +100031d6: 481e ldr r0, [pc, #120] @ (10003250 <__wrap_vprintf+0xb8>) +100031d8: 9701 str r7, [sp, #4] +100031da: f7ff fe1d bl 10002e18 +100031de: 9b01 ldr r3, [sp, #4] +100031e0: 4605 mov r5, r0 +100031e2: f8d8 4000 ldr.w r4, [r8] +100031e6: b1c3 cbz r3, 1000321a <__wrap_vprintf+0x82> +100031e8: 2c00 cmp r4, #0 +100031ea: d02b beq.n 10003244 <__wrap_vprintf+0xac> +100031ec: 4f19 ldr r7, [pc, #100] @ (10003254 <__wrap_vprintf+0xbc>) +100031ee: e001 b.n 100031f4 <__wrap_vprintf+0x5c> +100031f0: 6924 ldr r4, [r4, #16] +100031f2: b174 cbz r4, 10003212 <__wrap_vprintf+0x7a> +100031f4: 6823 ldr r3, [r4, #0] +100031f6: 2b00 cmp r3, #0 +100031f8: d0fa beq.n 100031f0 <__wrap_vprintf+0x58> +100031fa: 683b ldr r3, [r7, #0] +100031fc: b10b cbz r3, 10003202 <__wrap_vprintf+0x6a> +100031fe: 42a3 cmp r3, r4 +10003200: d1f6 bne.n 100031f0 <__wrap_vprintf+0x58> +10003202: 4620 mov r0, r4 +10003204: 9a01 ldr r2, [sp, #4] +10003206: a902 add r1, sp, #8 +10003208: f7ff fe4e bl 10002ea8 +1000320c: 6924 ldr r4, [r4, #16] +1000320e: 2c00 cmp r4, #0 +10003210: d1f0 bne.n 100031f4 <__wrap_vprintf+0x5c> +10003212: 2300 movs r3, #0 +10003214: f8d8 4000 ldr.w r4, [r8] +10003218: 9301 str r3, [sp, #4] +1000321a: b12c cbz r4, 10003228 <__wrap_vprintf+0x90> +1000321c: 6863 ldr r3, [r4, #4] +1000321e: b143 cbz r3, 10003232 <__wrap_vprintf+0x9a> +10003220: 4798 blx r3 +10003222: 6924 ldr r4, [r4, #16] +10003224: 2c00 cmp r4, #0 +10003226: d1f9 bne.n 1000321c <__wrap_vprintf+0x84> +10003228: b92e cbnz r6, 10003236 <__wrap_vprintf+0x9e> +1000322a: 4628 mov r0, r5 +1000322c: b022 add sp, #136 @ 0x88 +1000322e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003232: 6924 ldr r4, [r4, #16] +10003234: e7f1 b.n 1000321a <__wrap_vprintf+0x82> +10003236: 4805 ldr r0, [pc, #20] @ (1000324c <__wrap_vprintf+0xb4>) +10003238: f000 f9c2 bl 100035c0 <__mutex_exit_veneer> +1000323c: 4628 mov r0, r5 +1000323e: b022 add sp, #136 @ 0x88 +10003240: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003244: 9401 str r4, [sp, #4] +10003246: e7ef b.n 10003228 <__wrap_vprintf+0x90> +10003248: 000f4240 .word 0x000f4240 +1000324c: 20000624 .word 0x20000624 +10003250: 10002f59 .word 0x10002f59 +10003254: 20000808 .word 0x20000808 +10003258: 20000804 .word 0x20000804 + +1000325c <__wrap_printf>: +1000325c: b40f push {r0, r1, r2, r3} +1000325e: b500 push {lr} +10003260: b083 sub sp, #12 +10003262: a904 add r1, sp, #16 +10003264: f851 0b04 ldr.w r0, [r1], #4 +10003268: 9101 str r1, [sp, #4] +1000326a: f7ff ff95 bl 10003198 <__wrap_vprintf> +1000326e: b003 add sp, #12 +10003270: f85d eb04 ldr.w lr, [sp], #4 +10003274: b004 add sp, #16 +10003276: 4770 bx lr + +10003278 : +10003278: f1b1 0c00 subs.w ip, r1, #0 +1000327c: dd1d ble.n 100032ba +1000327e: 4a0f ldr r2, [pc, #60] @ (100032bc ) +10003280: 4b0f ldr r3, [pc, #60] @ (100032c0 ) +10003282: 6812 ldr r2, [r2, #0] +10003284: b530 push {r4, r5, lr} +10003286: 1ad3 subs r3, r2, r3 +10003288: fab3 f383 clz r3, r3 +1000328c: 240d movs r4, #13 +1000328e: 4d0d ldr r5, [pc, #52] @ (100032c4 ) +10003290: 095b lsrs r3, r3, #5 +10003292: 1e41 subs r1, r0, #1 +10003294: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003298: 448c add ip, r1 +1000329a: f811 0f01 ldrb.w r0, [r1, #1]! +1000329e: 4586 cmp lr, r0 +100032a0: d006 beq.n 100032b0 +100032a2: 6993 ldr r3, [r2, #24] +100032a4: 069b lsls r3, r3, #26 +100032a6: d4fc bmi.n 100032a2 +100032a8: 4561 cmp r1, ip +100032aa: 6010 str r0, [r2, #0] +100032ac: d1f5 bne.n 1000329a +100032ae: bd30 pop {r4, r5, pc} +100032b0: 6993 ldr r3, [r2, #24] +100032b2: 069d lsls r5, r3, #26 +100032b4: d4fc bmi.n 100032b0 +100032b6: 6014 str r4, [r2, #0] +100032b8: e7f3 b.n 100032a2 +100032ba: 4770 bx lr +100032bc: 20000850 .word 0x20000850 +100032c0: 40078000 .word 0x40078000 +100032c4: 2000084c .word 0x2000084c + +100032c8 : +100032c8: 4b22 ldr r3, [pc, #136] @ (10003354 ) +100032ca: f1b1 0c00 subs.w ip, r1, #0 +100032ce: b410 push {r4} +100032d0: 681c ldr r4, [r3, #0] +100032d2: dd2e ble.n 10003332 +100032d4: 4603 mov r3, r0 +100032d6: 2000 movs r0, #0 +100032d8: 4a1f ldr r2, [pc, #124] @ (10003358 ) +100032da: 1e59 subs r1, r3, #1 +100032dc: 6812 ldr r2, [r2, #0] +100032de: 6993 ldr r3, [r2, #24] +100032e0: 06db lsls r3, r3, #27 +100032e2: d417 bmi.n 10003314 +100032e4: 3001 adds r0, #1 +100032e6: 6993 ldr r3, [r2, #24] +100032e8: 06db lsls r3, r3, #27 +100032ea: d4fc bmi.n 100032e6 +100032ec: 6813 ldr r3, [r2, #0] +100032ee: 4584 cmp ip, r0 +100032f0: f801 3f01 strb.w r3, [r1, #1]! +100032f4: d1f3 bne.n 100032de +100032f6: b14c cbz r4, 1000330c +100032f8: 2150 movs r1, #80 @ 0x50 +100032fa: 4613 mov r3, r2 +100032fc: 6391 str r1, [r2, #56] @ 0x38 +100032fe: f853 2f34 ldr.w r2, [r3, #52]! +10003302: f002 0238 and.w r2, r2, #56 @ 0x38 +10003306: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000330a: 601a str r2, [r3, #0] +1000330c: 4660 mov r0, ip +1000330e: f85d 4b04 ldr.w r4, [sp], #4 +10003312: 4770 bx lr +10003314: b14c cbz r4, 1000332a +10003316: 2150 movs r1, #80 @ 0x50 +10003318: 4613 mov r3, r2 +1000331a: 6391 str r1, [r2, #56] @ 0x38 +1000331c: f853 2f34 ldr.w r2, [r3, #52]! +10003320: f002 0238 and.w r2, r2, #56 @ 0x38 +10003324: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003328: 601a str r2, [r3, #0] +1000332a: b178 cbz r0, 1000334c +1000332c: f85d 4b04 ldr.w r4, [sp], #4 +10003330: 4770 bx lr +10003332: b15c cbz r4, 1000334c +10003334: 4b08 ldr r3, [pc, #32] @ (10003358 ) +10003336: 2150 movs r1, #80 @ 0x50 +10003338: 681a ldr r2, [r3, #0] +1000333a: 4613 mov r3, r2 +1000333c: 6391 str r1, [r2, #56] @ 0x38 +1000333e: f853 2f34 ldr.w r2, [r3, #52]! +10003342: f002 0238 and.w r2, r2, #56 @ 0x38 +10003346: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000334a: 601a str r2, [r3, #0] +1000334c: f06f 0002 mvn.w r0, #2 +10003350: e7dd b.n 1000330e +10003352: bf00 nop +10003354: 200007d0 .word 0x200007d0 +10003358: 20000850 .word 0x20000850 + +1000335c : +1000335c: 4b05 ldr r3, [pc, #20] @ (10003374 ) +1000335e: 681b ldr r3, [r3, #0] +10003360: b133 cbz r3, 10003370 +10003362: 2100 movs r1, #0 +10003364: 4a04 ldr r2, [pc, #16] @ (10003378 ) +10003366: 4805 ldr r0, [pc, #20] @ (1000337c ) +10003368: 6812 ldr r2, [r2, #0] +1000336a: 6800 ldr r0, [r0, #0] +1000336c: 6391 str r1, [r2, #56] @ 0x38 +1000336e: 4718 bx r3 +10003370: 4770 bx lr +10003372: bf00 nop +10003374: 200007d0 .word 0x200007d0 +10003378: 20000850 .word 0x20000850 +1000337c: 200007d4 .word 0x200007d4 + +10003380 : +10003380: 4b02 ldr r3, [pc, #8] @ (1000338c ) +10003382: 681a ldr r2, [r3, #0] +10003384: 6993 ldr r3, [r2, #24] +10003386: 071b lsls r3, r3, #28 +10003388: d4fc bmi.n 10003384 +1000338a: 4770 bx lr +1000338c: 20000850 .word 0x20000850 + +10003390 : +10003390: b5f8 push {r3, r4, r5, r6, r7, lr} +10003392: 4f1c ldr r7, [pc, #112] @ (10003404 ) +10003394: 4d1c ldr r5, [pc, #112] @ (10003408 ) +10003396: 683a ldr r2, [r7, #0] +10003398: 4e1c ldr r6, [pc, #112] @ (1000340c ) +1000339a: 42aa cmp r2, r5 +1000339c: bf14 ite ne +1000339e: 2521 movne r5, #33 @ 0x21 +100033a0: 2522 moveq r5, #34 @ 0x22 +100033a2: 4604 mov r4, r0 +100033a4: f8d6 c000 ldr.w ip, [r6] +100033a8: b118 cbz r0, 100033b2 +100033aa: f1bc 0f00 cmp.w ip, #0 +100033ae: d010 beq.n 100033d2 +100033b0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100033b2: f1bc 0f00 cmp.w ip, #0 +100033b6: d0fb beq.n 100033b0 +100033b8: 4601 mov r1, r0 +100033ba: 6390 str r0, [r2, #56] @ 0x38 +100033bc: 4628 mov r0, r5 +100033be: f7fd f821 bl 10000404 +100033c2: 4628 mov r0, r5 +100033c4: 4912 ldr r1, [pc, #72] @ (10003410 ) +100033c6: f7fd f863 bl 10000490 +100033ca: 4b12 ldr r3, [pc, #72] @ (10003414 ) +100033cc: 6034 str r4, [r6, #0] +100033ce: 601c str r4, [r3, #0] +100033d0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100033d2: 460b mov r3, r1 +100033d4: 4a0f ldr r2, [pc, #60] @ (10003414 ) +100033d6: 490e ldr r1, [pc, #56] @ (10003410 ) +100033d8: 6030 str r0, [r6, #0] +100033da: 4628 mov r0, r5 +100033dc: 6013 str r3, [r2, #0] +100033de: f7fd f827 bl 10000430 +100033e2: 2101 movs r1, #1 +100033e4: 4628 mov r0, r5 +100033e6: f7fd f80d bl 10000404 +100033ea: 683a ldr r2, [r7, #0] +100033ec: 2150 movs r1, #80 @ 0x50 +100033ee: 4613 mov r3, r2 +100033f0: 6391 str r1, [r2, #56] @ 0x38 +100033f2: f853 2f34 ldr.w r2, [r3, #52]! +100033f6: f002 0238 and.w r2, r2, #56 @ 0x38 +100033fa: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100033fe: 601a str r2, [r3, #0] +10003400: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003402: bf00 nop +10003404: 20000850 .word 0x20000850 +10003408: 40078000 .word 0x40078000 +1000340c: 200007d0 .word 0x200007d0 +10003410: 1000335d .word 0x1000335d +10003414: 200007d4 .word 0x200007d4 + +10003418 : +10003418: b510 push {r4, lr} +1000341a: 490e ldr r1, [pc, #56] @ (10003454 ) +1000341c: 4c0e ldr r4, [pc, #56] @ (10003458 ) +1000341e: 480f ldr r0, [pc, #60] @ (1000345c ) +10003420: 4a0f ldr r2, [pc, #60] @ (10003460 ) +10003422: 4b10 ldr r3, [pc, #64] @ (10003464 ) +10003424: 7800 ldrb r0, [r0, #0] +10003426: 6021 str r1, [r4, #0] +10003428: 2000 movs r0, #0 +1000342a: 2102 movs r1, #2 +1000342c: 7812 ldrb r2, [r2, #0] +1000342e: 781b ldrb r3, [r3, #0] +10003430: f7fc ff22 bl 10000278 +10003434: 2102 movs r1, #2 +10003436: 2001 movs r0, #1 +10003438: f7fc ff1e bl 10000278 +1000343c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003440: 6820 ldr r0, [r4, #0] +10003442: f7fd fda1 bl 10000f88 +10003446: e8bd 4010 ldmia.w sp!, {r4, lr} +1000344a: 2101 movs r1, #1 +1000344c: 4806 ldr r0, [pc, #24] @ (10003468 ) +1000344e: f7ff be29 b.w 100030a4 +10003452: bf00 nop +10003454: 40070000 .word 0x40070000 +10003458: 20000850 .word 0x20000850 +1000345c: 10003800 .word 0x10003800 +10003460: 100037fc .word 0x100037fc +10003464: 100037f8 .word 0x100037f8 +10003468: 2000060c .word 0x2000060c + +1000346c : +1000346c: 4684 mov ip, r0 +1000346e: ea41 0300 orr.w r3, r1, r0 +10003472: f013 0303 ands.w r3, r3, #3 +10003476: d149 bne.n 1000350c +10003478: 3a40 subs r2, #64 @ 0x40 +1000347a: d323 bcc.n 100034c4 +1000347c: 680b ldr r3, [r1, #0] +1000347e: 6003 str r3, [r0, #0] +10003480: 684b ldr r3, [r1, #4] +10003482: 6043 str r3, [r0, #4] +10003484: 688b ldr r3, [r1, #8] +10003486: 6083 str r3, [r0, #8] +10003488: 68cb ldr r3, [r1, #12] +1000348a: 60c3 str r3, [r0, #12] +1000348c: 690b ldr r3, [r1, #16] +1000348e: 6103 str r3, [r0, #16] +10003490: 694b ldr r3, [r1, #20] +10003492: 6143 str r3, [r0, #20] +10003494: 698b ldr r3, [r1, #24] +10003496: 6183 str r3, [r0, #24] +10003498: 69cb ldr r3, [r1, #28] +1000349a: 61c3 str r3, [r0, #28] +1000349c: 6a0b ldr r3, [r1, #32] +1000349e: 6203 str r3, [r0, #32] +100034a0: 6a4b ldr r3, [r1, #36] @ 0x24 +100034a2: 6243 str r3, [r0, #36] @ 0x24 +100034a4: 6a8b ldr r3, [r1, #40] @ 0x28 +100034a6: 6283 str r3, [r0, #40] @ 0x28 +100034a8: 6acb ldr r3, [r1, #44] @ 0x2c +100034aa: 62c3 str r3, [r0, #44] @ 0x2c +100034ac: 6b0b ldr r3, [r1, #48] @ 0x30 +100034ae: 6303 str r3, [r0, #48] @ 0x30 +100034b0: 6b4b ldr r3, [r1, #52] @ 0x34 +100034b2: 6343 str r3, [r0, #52] @ 0x34 +100034b4: 6b8b ldr r3, [r1, #56] @ 0x38 +100034b6: 6383 str r3, [r0, #56] @ 0x38 +100034b8: 6bcb ldr r3, [r1, #60] @ 0x3c +100034ba: 63c3 str r3, [r0, #60] @ 0x3c +100034bc: 3040 adds r0, #64 @ 0x40 +100034be: 3140 adds r1, #64 @ 0x40 +100034c0: 3a40 subs r2, #64 @ 0x40 +100034c2: d2db bcs.n 1000347c +100034c4: 3230 adds r2, #48 @ 0x30 +100034c6: d30b bcc.n 100034e0 +100034c8: 680b ldr r3, [r1, #0] +100034ca: 6003 str r3, [r0, #0] +100034cc: 684b ldr r3, [r1, #4] +100034ce: 6043 str r3, [r0, #4] +100034d0: 688b ldr r3, [r1, #8] +100034d2: 6083 str r3, [r0, #8] +100034d4: 68cb ldr r3, [r1, #12] +100034d6: 60c3 str r3, [r0, #12] +100034d8: 3010 adds r0, #16 +100034da: 3110 adds r1, #16 +100034dc: 3a10 subs r2, #16 +100034de: d2f3 bcs.n 100034c8 +100034e0: 320c adds r2, #12 +100034e2: d305 bcc.n 100034f0 +100034e4: f851 3b04 ldr.w r3, [r1], #4 +100034e8: f840 3b04 str.w r3, [r0], #4 +100034ec: 3a04 subs r2, #4 +100034ee: d2f9 bcs.n 100034e4 +100034f0: 3204 adds r2, #4 +100034f2: d008 beq.n 10003506 +100034f4: 07d2 lsls r2, r2, #31 +100034f6: bf1c itt ne +100034f8: f811 3b01 ldrbne.w r3, [r1], #1 +100034fc: f800 3b01 strbne.w r3, [r0], #1 +10003500: d301 bcc.n 10003506 +10003502: 880b ldrh r3, [r1, #0] +10003504: 8003 strh r3, [r0, #0] +10003506: 4660 mov r0, ip +10003508: 4770 bx lr +1000350a: bf00 nop +1000350c: 2a08 cmp r2, #8 +1000350e: d313 bcc.n 10003538 +10003510: 078b lsls r3, r1, #30 +10003512: d0b1 beq.n 10003478 +10003514: f010 0303 ands.w r3, r0, #3 +10003518: d0ae beq.n 10003478 +1000351a: f1c3 0304 rsb r3, r3, #4 +1000351e: 1ad2 subs r2, r2, r3 +10003520: 07db lsls r3, r3, #31 +10003522: bf1c itt ne +10003524: f811 3b01 ldrbne.w r3, [r1], #1 +10003528: f800 3b01 strbne.w r3, [r0], #1 +1000352c: d3a4 bcc.n 10003478 +1000352e: f831 3b02 ldrh.w r3, [r1], #2 +10003532: f820 3b02 strh.w r3, [r0], #2 +10003536: e79f b.n 10003478 +10003538: 3a04 subs r2, #4 +1000353a: d3d9 bcc.n 100034f0 +1000353c: 3a01 subs r2, #1 +1000353e: f811 3b01 ldrb.w r3, [r1], #1 +10003542: f800 3b01 strb.w r3, [r0], #1 +10003546: d2f9 bcs.n 1000353c +10003548: 780b ldrb r3, [r1, #0] +1000354a: 7003 strb r3, [r0, #0] +1000354c: 784b ldrb r3, [r1, #1] +1000354e: 7043 strb r3, [r0, #1] +10003550: 788b ldrb r3, [r1, #2] +10003552: 7083 strb r3, [r0, #2] +10003554: 4660 mov r0, ip +10003556: 4770 bx lr + +10003558 : +10003558: f020 0103 bic.w r1, r0, #3 +1000355c: f010 0003 ands.w r0, r0, #3 +10003560: f1c0 0000 rsb r0, r0, #0 +10003564: f851 3b04 ldr.w r3, [r1], #4 +10003568: f100 0c04 add.w ip, r0, #4 +1000356c: ea4f 0ccc mov.w ip, ip, lsl #3 +10003570: f06f 0200 mvn.w r2, #0 +10003574: bf1c itt ne +10003576: fa22 f20c lsrne.w r2, r2, ip +1000357a: 4313 orrne r3, r2 +1000357c: f04f 0c01 mov.w ip, #1 +10003580: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003584: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003588: eba3 020c sub.w r2, r3, ip +1000358c: ea22 0203 bic.w r2, r2, r3 +10003590: ea12 12cc ands.w r2, r2, ip, lsl #7 +10003594: bf04 itt eq +10003596: f851 3b04 ldreq.w r3, [r1], #4 +1000359a: 3004 addeq r0, #4 +1000359c: d0f4 beq.n 10003588 +1000359e: f1c2 0100 rsb r1, r2, #0 +100035a2: ea02 0201 and.w r2, r2, r1 +100035a6: fab2 f282 clz r2, r2 +100035aa: f1c2 021f rsb r2, r2, #31 +100035ae: eb00 00d2 add.w r0, r0, r2, lsr #3 +100035b2: 4770 bx lr + +100035b4 <_fini>: +100035b4: b5f8 push {r3, r4, r5, r6, r7, lr} +100035b6: bf00 nop + +100035b8 <____aeabi_uldivmod_veneer>: +100035b8: f85f f000 ldr.w pc, [pc] @ 100035bc <____aeabi_uldivmod_veneer+0x4> +100035bc: 20000221 .word 0x20000221 + +100035c0 <__mutex_exit_veneer>: +100035c0: f85f f000 ldr.w pc, [pc] @ 100035c4 <__mutex_exit_veneer+0x4> +100035c4: 200001e5 .word 0x200001e5 + +100035c8 <__mutex_try_enter_block_until_veneer>: +100035c8: f85f f000 ldr.w pc, [pc] @ 100035cc <__mutex_try_enter_block_until_veneer+0x4> +100035cc: 2000017d .word 0x2000017d + +100035d0 <__pre_init_runtime_init_bootrom_reset>: +100035d0: 10001341 A... + +100035d4 <__pre_init_runtime_init_early_resets>: +100035d4: 100012b5 .... + +100035d8 <__pre_init_runtime_init_usb_power_down>: +100035d8: 100012e9 .... + +100035dc <__pre_init_runtime_init_clocks>: +100035dc: 100013d5 .... + +100035e0 <__pre_init_runtime_init_post_clock_resets>: +100035e0: 10001321 !... + +100035e4 <__pre_init_runtime_init_boot_locks_reset>: +100035e4: 10001239 9... + +100035e8 <__pre_init_runtime_init_spin_locks_reset>: +100035e8: 10001369 i... + +100035ec <__pre_init_runtime_init_bootrom_locking_enable>: +100035ec: 10001225 %... + +100035f0 <__pre_init_runtime_init_mutex>: +100035f0: 1000074d M... + +100035f4 <__pre_init_runtime_init_install_ram_vector_table>: +100035f4: 1000136d m... + +100035f8 <__pre_init_runtime_init_default_alarm_pool>: +100035f8: 10000ac9 .... + +100035fc <__pre_init_first_per_core_initializer>: +100035fc: 10001285 .... + +10003600 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003600: 10001355 U... + +10003604 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10003604: 10001305 .... + +10003608 <__pre_init_spinlock_set_extexclall>: +10003608: 1000039d .... + +1000360c <__pre_init_runtime_init_per_core_irq_priorities>: +1000360c: 100003c5 .... + +10003610 <__frame_dummy_init_array_entry>: +10003610: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000ded .word 0x10000ded + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 10000685 .word 0x10000685 + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003279 10003381 100032c9 10003391 y2...3...2...3.. +2000061c: 00000000 00000100 ........ + +20000624 : + ... diff --git a/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.elf b/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.elf new file mode 100755 index 0000000..2f73ff7 Binary files /dev/null and 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+:103CE4008506001000000000000000000000000035 +:103CF40000000000000000003006002079320010AF +:103D040081330010C932001091330010000000000C +:0C3D1400000100000000000000000000A2 +:103D2000D3DEFFFFFE010000FF01000018C4FFFF0B +:043D3000793512AB24 +:040000051000014D99 +:00000001FF diff --git a/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.uf2 b/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.uf2 new file mode 100644 index 0000000..5d77b4a Binary files /dev/null and b/WEEK04/0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.uf2 differ diff --git a/WEEK04/0x0008_uninitialized-variables/build/pico_flash_region.ld b/WEEK04/0x0008_uninitialized-variables/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK04/0x0008_uninitialized-variables/pico_sdk_import.cmake b/WEEK04/0x0008_uninitialized-variables/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK04/0x0008_uninitialized-variables/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK04/WEEK04-BN.md b/WEEK04/WEEK04-BN.md new file mode 100644 index 0000000..d9bb928 --- /dev/null +++ b/WEEK04/WEEK04-BN.md @@ -0,0 +1,1831 @@ +# Week 4-BN: Binary Ninja Personal — Resolve, Hack, and Patch the RP2350 (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into Binary Ninja at `0x10000000` +- **Break at `main`** on live silicon, even though `main` can move between programs +- **Hack a running target live** by editing a register in Binary Ninja's Registers widget +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map +- **Patch** the bytes that control the behavior, export the image, and flash it + +--- + +## How This Guide Works + +The build produces two files for each project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in Binary Ninja, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 4 lesson, and the Week 4 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it folds `age = 42` away in Project 1 and inlines `blink_and_print` into `main` in Project 2. If you build `Debug`, the SDK function addresses move and Project 2 keeps a separate `blink_and_print`, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**, twice — once per project: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the behavior change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Prints | Also does | The hack | +| ------- | ------ | --------- | -------- | +| `0x0005_intro-to-variables` | `age: 43` | loops on `printf` | change `43` to `70` | +| `0x0008_uninitialized-variables` | `age: 0` | blinks the red LED on GPIO 16 | change `0` to `66`, move the LED to GPIO 17 | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +file "$(which telnet)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**`telnet` is special — and optional.** The GDB MI workflow does not need it; it is only used by the command-port fallback. macOS no longer ships `telnet`, and the Homebrew build is often the Intel one, so `telnet 127.0.0.1 4444` fails with `bad CPU type in executable`. Your `brew` command itself may also be the Intel one: if `brew install telnet` fails with `.../portable-ruby/.../ruby: Bad CPU type in executable`, you are running the Intel Homebrew. Call the Apple Silicon Homebrew explicitly: + +```bash +/opt/homebrew/bin/brew install telnet +``` + +If you would rather not install anything, macOS ships an arm64 `nc`, which can connect to the same OpenOCD port: + +```bash +nc 127.0.0.1 4444 +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x0005_intro-to-variables/` and once inside `0x0008_uninitialized-variables/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x0005_intro-to-variables", "0x0008_uninitialized-variables"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0005_intro-to-variables", "0x0008_uninitialized-variables"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0005_intro-to-variables", "0x0008_uninitialized-variables"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x0005_intro-to-variables/build/0x0005_intro-to-variables.elf` and `.bin` — `.bin` is **15292** bytes +- `0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.elf` and `.bin` — `.bin` is **15668** bytes + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin` | +| Linux x64 | `/usr` | + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0005_intro-to-variables.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0008_uninitialized-variables.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0005_intro-to-variables.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. + +**Project 1 — `0x0005_intro-to-variables`:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function | +| `0x10000248` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO helper | +| `0x10002cfc` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002d04` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10002f54` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100030e4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | + +These signatures come from the ELF's DWARF debug info, so they are exact. You apply them in Binary Ninja in Step 16 (`G` -> address, then `Y` -> Change Type). + +**Project 2 — `0x0008_uninitialized-variables`:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (`blink_and_print` inlined) | +| `0x10000278` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO helper | +| `0x100002b4` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | +| `0x10000d10` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK delay | +| `0x10002e74` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002e7c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x100030cc` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x1000325c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | + +> **`main` is `0x10000234` in both projects.** In Project 2 the `static void blink_and_print` helper is inlined into `main` by the `Release` optimizer, so it does not appear as a separate symbol. That is why both projects put `main` at the same address. In a `Debug` build it stays separate and `main` moves — another reason to build `Release`. + +### Step 5: Flash Project 1 and confirm `age: 43` + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x0005_intro-to-variables\build\0x0005_intro-to-variables.bin +``` + +**Or flash from the Binary Ninja console** (with a database open, so the repo root is taken from it — otherwise use the terminal form above): + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0005_intro-to-variables", "build", "0x0005_intro-to-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0005_intro-to-variables", "build", "0x0005_intro-to-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 15292 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +age: 43 +age: 43 +age: 43 +... +``` + +### Step 6: Flash Project 2 and confirm `age: 0` + red LED + +```bash +# macOS / Linux +./flash.sh 0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.bin +``` +```powershell +# Windows +.\flash.ps1 -Bin 0x0008_uninitialized-variables\build\0x0008_uninitialized-variables.bin +``` + +**Or flash from the Binary Ninja console** (same form as Step 5, pointing at the Project 2 `.bin`): + +**macOS / Linux:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0008_uninitialized-variables", "build", "0x0008_uninitialized-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0008_uninitialized-variables", "build", "0x0008_uninitialized-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 15668 bytes ...`. The serial monitor shows: + +``` +age: 0 +age: 0 +age: 0 +... +``` + +and the **red LED on GPIO 16** blinks once per second. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> load("0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 8: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x0005_intro-to-variables.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +The two files have different roles: + +| File | Role | +| ---- | ---- | +| `0x0005_intro-to-variables.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x0005_intro-to-variables.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. If a database gets messy, delete the `.bndb` and re-import the `.bin` from Step 7 — the firmware is never at risk. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the OpenOCD command port, not from the GUI — see Step 13. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at `main` and Hack Live (Project 1) + +### Step 10: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 11. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. This is the whole reason the lab works cleanly — you never have to drive a reset from outside the GUI. +> +> Use the address you actually want to stop at: +> +> | What you want to stop at | Project 1 `0x0005` | Project 2 `0x0008` | Command | +> | --- | --- | --- | --- | +> | `main` (once per reset) | `0x10000234` | `0x10000234` | `BP_ADDR=0x10000234 ./debug-server.sh` | +> | The **loop** — the `printf` call, hit every iteration | `0x1000023e` | `0x1000024e` | `BP_ADDR=0x1000023e ./debug-server.sh` | +> +> ```bash +> BP_ADDR=0x10000234 ./debug-server.sh # park at main +> BP_ADDR=0x1000023e ./debug-server.sh # park in the loop instead +> ``` +> +> ```powershell +> $env:BP_ADDR="0x10000234"; .\debug-server.ps1 # park at main +> $env:BP_ADDR="0x1000023e"; .\debug-server.ps1 # park in the loop +> ``` +> +> **Note the loop address is not the same in both projects.** Project 2 does more setup before the loop, so its `bl __wrap_printf` sits at `0x1000024e`, not `0x1000023e`. Both were verified against the Release `.elf` with `arm-none-eabi-objdump` and confirmed live on hardware. +> +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 13) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 11: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 10 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length and handles step-over itself. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. Stops are reported as `Breakpoint` (not `SingleStep`). +> +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 10), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. +> +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build — which is what `/opt/homebrew/bin/arm-none-eabi-gdb` symlinks to — did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. +> +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. It is not the adapter for this lab. The dropdown is a combo box, so an accidental arrow-key press can land on it — always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +> **Watch for an off-screen error dialog.** When a connection fails, Binary Ninja pops a `Binary Ninja critical alert` window that can be positioned mostly outside the main window (seen at `2430,331` with the main window at `2560,30`), which makes it look like nothing happened. If the connect seems to do nothing, check your other display. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 12: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186 : +10000186: 4914 ldr r1, [pc, #80] ; @ 0x100001d8 +10000188: 4788 blx r1 ; runtime_init +1000018a: 4914 ldr r1, [pc, #80] ; @ 0x100001dc +1000018c: 4788 blx r1 ; main <-- the fixed anchor +1000018e: 4914 ldr r1, [pc, #80] ; @ 0x100001e0 +10000190: 4788 blx r1 ; exit +10000192: be00 bkpt 0x0000 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in both projects, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`, and clearing bit 0 gives `0x10000234`. + +### Step 13: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +> **Why older drafts used the command port.** Binary Ninja's **GDB RSP** adapter is its own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 FPB comparators need 2 bytes, so OpenOCD rejected it with `only breakpoints of two bytes length supported`. The old workaround was to arm breakpoints by hand over telnet. **The GDB MI adapter does not have this problem** — it drives real `arm-none-eabi-gdb`, which sends the right length. So everything below is done in the GUI. The command port still exists as a fallback (see the end of this step), but you do not need it. + +#### Where you can stop + +| You want to stop at | Address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 10), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **The loop** (`printf` call) | Project 1 `0x1000023e`, Project 2 `0x1000024e` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | + +#### Set the loop breakpoint in the GUI + +1. Press `G`, type the loop address (`0x1000023e` for Project 1, `0x1000024e` for Project 2), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the loop address and reports it as a **Breakpoint** — verified: `Stopped (Breakpoint) at 0x1000023e`. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 11). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +#### Stepping + +With the target halted at the breakpoint, **Step Into** (`F7`) and **Step Over** (`F8`) run through real GDB and move the PC. Verified: `0x1000023e -> 0x100030e4 -> 0x100030e6 -> ...`. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, so **Step Over** at the `printf` call behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 14 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +> **If you ever need the command port.** It is still there — `nc 127.0.0.1 4444`, and `bp 2 hw` still arms a breakpoint, `rbp ` / `rbp all` still remove them. It is the fallback if you switch back to the **GDB RSP** adapter, whose 1-byte breakpoints the GUI cannot set. With GDB MI you do not need it for this lab. + +### Step 14: HACK IT LIVE — change the printed value + +`main` loads the constant `0x2b` (43) into `r1` and calls `printf` on every iteration. We break on that call in the GUI and change it live. + +1. Press `G`, go to `0x1000023e` (the `bl __wrap_printf`). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the program counter at `0x1000023e` and `r1 = 0x2b`. +4. Open the **Registers** widget (bug icon -> **Registers**). +5. Find `r1`. Its value is `0x2b`. +6. **Set `r1` to `0x46`.** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r1", 0x46) + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r1` in the **Registers** widget, press `E` (edit), type `46`, and press Enter. The widget may not repaint the value, but the write reaches the target — you confirm it by the printed output in the next steps. +7. **Move the breakpoint past the call.** You want `printf` to run once and then stop, so move the breakpoint from `0x1000023e` to the instruction *after* the call, `0x10000242` (the `b.n` that closes the loop): remove the breakpoint at `0x1000023e` and set a hardware breakpoint at `0x10000242`. Two reasons not to just click **Step Over** here: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `__wrap_printf` on this raw `.bin` because the image carries no symbol for the call. Moving the breakpoint to the return site is deterministic. +8. Click **Resume** in Binary Ninja. The core executes `bl __wrap_printf` with `r1 = 0x46`, so this iteration prints `age: 70`, then stops at `0x10000242`. +9. Look at your serial monitor — the `screen` session on the Pico's USB serial port — and at the **Target** tab in Binary Ninja: + + ``` + age: 70 + ``` + +You changed a running program's output without touching the binary. + +### Step 14b: HACK THE STRING LIVE — change `age:` to `foo:` + +The text `"age: %d\r\n"` lives in flash (`.rodata`) at `0x100034a0`, and flash is **read-only at runtime** — a debugger write there does not stick (verified: writing `0x66` to `0x100034a0` read back unchanged). So you cannot overwrite the text in place. Instead you redirect the pointer: at the `printf` call, `r0` holds the string address, so you point `r0` at a replacement string you place in RAM. + +1. Arm the breakpoint at the `printf` call and hit it, exactly as in Step 14 steps 1-3. At the stop, `r0 = 0x100034a0` and `r1 = 0x2b`. +2. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console** (`Plugins -> Python Console`) — no command port needed: + ```python + dbg.write_memory(0x20080000, b"foo: %d\r\n\x00") + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. That writes the bytes `66 6f 6f 3a 20 25 64 0d 0a 00` = `"foo: %d\r\n\0"`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. Move the breakpoint past the call in the GUI (remove it at `0x1000023e`, set one at `0x10000242`) and click **Resume**. The core runs `printf` with `r0` pointing at your RAM string and `r1 = 0x2b`, so this iteration prints: + ``` + foo: 43 + ``` + then stops at `0x10000242`. + +Like the value hack, this is **one iteration only**: the loop reloads `r0` (and `r1`) from flash on every pass, so the next line is `age: 43` again. The permanent version is the static patch in Step 19b. + +### Step 15: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x1000023a`, which reloads `movs r1, #43`, so the next line is `age: 43`. The live edit changed one iteration only. There is no variable in memory to change; the value is baked into the instruction. To make `age: 70` permanent we must patch the instruction. That is the static pass. + +Press **Pause** to stop the output flood. + +### Step 15b: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch (Project 1) + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10002f54()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x10002f54`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `uart_init` + +1. `G` -> `0x10000e10`. +2. `Y` -> `uint uart_init(uart_inst_t *uart, uint baudrate)`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100030e4`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` only calls `stdio_init_all` and `printf`, so we follow that chain down: `stdio_init_all` pulls in the stdio/UART setup, and `printf` lands in the SDK's `__wrap_printf`. + +The call chain for this project: + +``` +main +├── stdio_init_all +│ ├── stdio_uart_init ── gpio_set_function, uart_init +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ ├── stdio_put_string ── strlen +│ └── time_us_64 +└── __wrap_printf ── __wrap_vprintf +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x10002cfc` | `exit` | `void exit(int)` | +| `0x10002d04` | `runtime_init` | `void runtime_init(void)` | +| `0x10002f54` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100032a0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10002f2c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10002d30` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002e40` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x100030e4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003020` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10000248` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e10` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10000da0` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100033e0` | `strlen` | `size_t strlen(const char*)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis (verified live). Setting the signature and the return type both failing while `return_value` succeeds looks like a bug or inconsistency in this build (BN 6.0.10601). If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`__wrap_printf` is the real symbol.** `printf` in our source compiles to the SDK's `__wrap_printf` (which forwards to `__wrap_vprintf`). Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. +> +> **`stdio_init_all` returns `bool`, not `void`** — `_Bool stdio_init_all(void)` in the ELF. The `main` source ignores the return value, so the decompiler still reads fine. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature); None means "leave the type alone" +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x10002cfc: ("exit", "void exit(int)"), +> 0x10002d04: ("runtime_init", "void runtime_init(void)"), +> 0x10002f54: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100032a0: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10002f2c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10002d30: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10002e40: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x100030e4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003020: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x10000248: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e10: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10000da0: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100033e0: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> if sig: +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `gpio_function_t`, `uart_inst_t`, plus `uint` and `va_list`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. It reads: + +```c +int32_t main(void) +{ + stdio_init_all(); + do + { + printf("age: %d\r\n", 0x2b); + } while (true); +} +``` + +The `0x2b` is the value we edited live. Now make it permanent. + +### Step 18: Patch `0x2b` to `0x46` in the GUI + +Go to `0x1000023a`: + +```asm +1000023a: 212b movs r1, #43 ; 0x2b +``` + +The halfword is `0x212b`, stored little-endian as `2b 21`. The immediate is the low byte, so the byte at the instruction's own address is `0x2b`. Change it to `0x46` (70). + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000023a` and change the byte `2B` to `46`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000023a, b"\x46") +print(hex(bv.read(0x1000023a, 1)[0])) # -> 0x46 +``` + +After reanalysis the instruction reads `movs r1, #70`. + +### Step 18b: Patch the string `age:` to `foo:` in the GUI + +The format string `"age: %d\r\n"` starts at `0x100034a0`. Its first three bytes are `61 67 65` (`age`). Change them to `66 6f 6f` (`foo`), leaving the `: %d\r\n` tail untouched, so the line prints `foo: 70`. + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x100034a0` and change the three bytes `61 67 65` to `66 6f 6f`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100034a0, b"foo") +print(bv.read(0x100034a0, 10)) # -> b'foo: %d\r\n\x00' +``` + +Keep the replacement exactly three bytes. If you use a shorter string you must pad it, or `%d` shifts and `printf` reads the wrong argument. A longer string would overwrite the `: %d` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0005_intro-to-variables", "build"), "0x0005_intro-to-variables-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15292 /.../build/0x0005_intro-to-variables-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3bbc` = 15292). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so `open("0x0005_intro-to-variables-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range (`0x10000000`..`0xe008000c`), which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0005_intro-to-variables-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0005_intro-to-variables-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0005_intro-to-variables", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0005_intro-to-variables-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +### Step 21: Flash and verify `age: 70` + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Open the serial monitor: + +``` +age: 70 +age: 70 +age: 70 +... +``` + +**43 became 70, permanently, with one byte changed and no source code.** + +> **Faster: flash over the Debug Probe (no BOOTSEL).** The repo's `flash.sh` writes the raw `.bin` straight into XIP flash over SWD (`program 0x10000000 verify reset exit`), so you never touch BOOTSEL or a UF2. Run it from a terminal (`./flash.sh `), or from the Binary Ninja console **without freezing it** — use `subprocess.Popen`, which returns immediately, and send OpenOCD's output to a log file. (`subprocess.run` blocks the console until the flash finishes; do not use it here.) +> +> ```python +> import os, subprocess +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +> bin_path = os.path.join(os.path.join(root, "0x0005_intro-to-variables", "build"), "0x0005_intro-to-variables-h.bin") +> log = os.path.join(os.path.join(root, "0x0005_intro-to-variables", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> The `pkill` frees the probe first; on Windows use `subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"])`. +> +> The console is free the moment this returns. Check it with `print(p.poll())` (`None` = still running, `0` = done) or read `flash.log` — success ends with `** Verified OK **`. (Verified: `Popen` returns in ~1 ms; the flash itself takes ~2 s.) +> +> The same non-blocking form without the script: +> +> ```python +> import os, subprocess +> ocd = os.path.expanduser("~/.pico-sdk/openocd/0.12.0+dev") +> bin_path = os.path.join(os.path.join(root, "0x0005_intro-to-variables", "build"), "0x0005_intro-to-variables-h.bin") +> log = os.path.join(os.path.join(root, "0x0005_intro-to-variables", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([f"{ocd}/openocd", "-s", f"{ocd}/scripts", +> "-f", "interface/cmsis-dap.cfg", "-f", "target/rp2350.cfg", +> "-c", "adapter speed 5000", +> "-c", f"program {bin_path} 0x10000000 verify reset exit"], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> **The Debug Probe is single-owner.** If Binary Ninja is still attached (the `debug-server.sh` OpenOCD is running), the flash cannot grab the probe. Detach in Binary Ninja and stop that OpenOCD first: +> +> ```bash +> # macOS / Linux +> pkill -TERM -f openocd +> ``` +> ```powershell +> # Windows +> Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +> ``` +> +> Success looks like `Programming Finished` -> `Verified OK` -> `Resetting Target`. On Windows use `flash.ps1` (`.\flash.ps1 -Bin `) the same way. + +--- + +## Part 5: Dynamic — Break at `main` and Hack Live (Project 2) + +### Step 22: Reflash Project 2 and reload Binary Ninja + +Part 4 left the Pico running the patched Project 1 image. Put the original Project 2 back and start a fresh session. + +1. Stop any running debug server so the flash script can use the probe: + + ```bash + # macOS / Linux + pkill -TERM -f openocd + ``` + ```powershell + # Windows + Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process + ``` + +2. Flash the original Project 2 image: + + ```bash + # macOS / Linux + ./flash.sh 0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.bin + ``` + ```powershell + # Windows + .\flash.ps1 -Bin 0x0008_uninitialized-variables\build\0x0008_uninitialized-variables.bin + ``` + + **Or do steps 1–2 from the Binary Ninja console** (the active view is still Project 1, so take the repo root from it and point at the Project 2 `.bin`): + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0008_uninitialized-variables", "build", "0x0008_uninitialized-variables.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first + subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("flashing Project 2 in the background; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0008_uninitialized-variables", "build", "0x0008_uninitialized-variables.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("flashing Project 2 in the background; log:", log) + ``` + +3. Start the debug server again (Step 10) and wait for `Listening on port 3333`. +4. Load Project 2 and save its database — see Step 22b. +5. Connect Binary Ninja again (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +Confirm the Pico prints `age: 0` and blinks the red LED. + +### Step 22b: Load Project 2 into Binary Ninja and save the database + +Exactly like Steps 7–8, but for Project 2. **Use `File -> Open with Options...`** (not plain `File -> Open`), select `0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.bin`, and set: + +- **Architecture:** `thumb2` +- **Platform:** `thumb2` +- **Base Address:** `0x10000000` + +Click **Open**. Then press `G`, type `0x10000000`, and confirm the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you see data at `0x00000000`, close the tab and redo it with `Open with Options`. + +Save it with `File -> Save As...` as `0x0008_uninitialized-variables.bndb` (next to the `.bin`). From now on open the `.bndb`, not the `.bin`; save with `Cmd+S` / `Ctrl+S` after every rename or patch. + +> **Console equivalent:** +> ```python +> load("0x0008_uninitialized-variables/build/0x0008_uninitialized-variables.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +Then resolve the functions for Project 2 the same way as Project 1 — Step 26. + +### Step 23: Break at `main` + +`main` is at `0x10000234` in this project too. The GUI sets breakpoints fine (Step 13); the only caution is not to drive `reset run` from the port while Binary Ninja is attached (it desyncs Binary Ninja's view). Use `BP_ADDR`, which arms `main` before Binary Ninja connects: + +1. Stop the server (Ctrl-C), then start it parked at `main`: + ```bash + # macOS / Linux + BP_ADDR=0x10000234 ./debug-server.sh + ``` + ```powershell + # Windows + $env:BP_ADDR="0x10000234"; .\debug-server.ps1 + ``` + + **Or restart it from the Binary Ninja console** — kill any running server, then start it parked at `main`: + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # kill any running server first + subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("OpenOCD restarted parked at main; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # kill any running server first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("OpenOCD restarted parked at main; log:", log) + ``` +2. Connect Binary Ninja (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +The target is already halted at `main` when Binary Ninja connects, and the sidebar reads `Stopped at 0x10000234`. + +> If you instead want to reach `main` on an already-connected session, you must Detach, send `reset run` from the port, then reconnect. Arming `main` and resetting while attached leaves the sidebar showing a stale address. + +`main` sets up GPIO 16 and then loops: print `age`, turn the LED on, sleep, turn it off, sleep. The whole loop is one function because `blink_and_print` was inlined: + +```asm +10000234
: +10000234: b538 push {r3, r4, r5, lr} +10000236: f002 ff49 bl 0x100030cc ; stdio_init_all +1000023a: 2010 movs r0, #16 ; LED_PIN +1000023c: f000 f83a bl 0x100002b4 ; gpio_init +10000240: f04f 0501 mov.w r5, #1 +10000244: 2310 movs r3, #16 ; LED_PIN +10000246: ec45 3044 mcrr 0, 4, r3, r5, cr4 ; gpio_set_dir(16, OUT) +1000024a: 2100 movs r1, #0 ; age +1000024c: 4809 ldr r0, [pc, #36] ; @ 0x10000274 -> "age: %d\r\n" +1000024e: f003 f805 bl 0x1000325c ; __wrap_printf +10000252: 2410 movs r4, #16 ; LED_PIN +10000254: ec45 4040 mcrr 0, 4, r4, r5, cr0 ; gpio_put(16, 1) +10000258: f44f 70fa mov.w r0, #500 +1000025c: f000 fd58 bl 0x10000d10 ; sleep_ms +10000260: f04f 0300 mov.w r3, #0 +10000264: ec43 4040 mcrr 0, 4, r4, r3, cr0 ; gpio_put(16, 0) +10000268: f44f 70fa mov.w r0, #500 +1000026c: f000 fd50 bl 0x10000d10 ; sleep_ms +10000270: e7eb b.n 0x1000024a +10000272: bf00 nop +10000274: 10003618 .word 0x10003618 +``` + +Look at the **Registers** widget at `0x1000024e`: `r1` is `0`, which is why the Pico prints `age: 0`. + +### Step 24: Inspect the GPIO registers live + +The GPIO hardware is memory-mapped. Go to each address and watch it change as you step: + +| Address | Block | Role | +| ------- | ----- | ---- | +| `0x40028000` | `IO_BANK0` | pin function select and status | +| `0x40038000` | `PADS_BANK0` | pad configuration | +| `0xd0000000` | `SIO` | single-cycle GPIO block driven by `mcrr` | + +Step Over through `0x10000254` (`mcrr 0, 4, r4, r5, cr0`) and watch the SIO output register change: this is `gpio_put(16, 1)` turning the red LED on at the hardware level. + +### Step 25: HACK IT LIVE — change the printed value + +1. Press `G`, go to `0x1000024e` (the `bl __wrap_printf`). +2. Set a **hardware execute** breakpoint at `0x1000024e` in the GUI (`Debugger -> Add Hardware Breakpoint...`; not `F2`). Note `0x1000024e` — Project 2's loop sits at a different address than Project 1's. +3. Click **Resume** in Binary Ninja. The target is already looping, so the breakpoint fires on the next pass. Binary Ninja stops with `r1 = 0`. +4. Set `r1` to `0x42` (66): + ```python + dbg.set_reg_value("r1", 0x42) + ``` + (Or right-click `r1` in the **Registers** widget, press `E`, type `42`, and press Enter.) +5. **Move the breakpoint past the call.** `0x10000252` is the instruction right after the `bl __wrap_printf`. Remove the breakpoint at `0x1000024e` and set a hardware breakpoint at `0x10000252`, then click **Resume**. The core runs `printf` with `r1 = 0x42` and stops at `0x10000252`. (Not **Step Over** — it steps into the call on this symbol-less `.bin`, and a breakpoint left on the current PC re-traps the step; Step 13 explains both.) +6. Look at your serial monitor and the **Target** tab: + + ``` + age: 66 + ``` + +Press **Resume** and the next iteration prints `age: 0` again, because the loop reloads `movs r1, #0` each pass. The live hack is temporary; the static patch makes it permanent. + +### Step 25b: HACK THE STRING LIVE — change `age:` to `foo:` + +Same idea as Project 1, different addresses. Here the format string is at `0x10003618` and the `printf` call is at `0x1000024e`. + +1. Hit the breakpoint at `0x1000024e` as in Step 25. At the stop, `r0 = 0x10003618` and `r1 = 0`. +2. Write the replacement string to free RAM at `0x20080000` from the **Python console** (`dbg.write_memory` — no command port needed): + ```python + dbg.write_memory(0x20080000, b"foo: %d\r\n\x00") + ``` + Bytes `66 6f 6f 3a 20 25 64 0d 0a 00` = `"foo: %d\r\n\0"`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. Move the breakpoint past the call in the GUI (remove it at `0x1000024e`, set one at `0x10000252`) and click **Resume**. This iteration prints: + ``` + foo: 0 + ``` + then stops at `0x10000252`. One iteration only — the loop reloads `r0` each pass. The permanent version is the static patch in Step 28b. + +### Step 25c: Kill the debugger and OpenOCD + +Same as Step 15b: click the **X** (**Kill**) in the **Debugger** sidebar (or **`Debugger -> Kill`**), then stop OpenOCD from the Binary Ninja console: + +**macOS / Linux:** + +```python +import subprocess +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe +``` + +**Windows:** + +```python +import subprocess +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe +``` + +--- + +## Part 6: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the Binary Ninja GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +The mechanics are identical to Step 16, so here are the worked examples for the functions that are specific to this project. + +#### `main` + +1. `G` -> `0x10000234`. +2. `Y` -> `int main(void)` (Binary Ninja shows `int32_t main(void)` — the same 32-bit `int`). + +#### `gpio_init` + +1. `G` -> `0x100002b4`. +2. `Y` -> `void gpio_init(uint gpio)`. + +#### `sleep_ms` + +1. `G` -> `0x10000d10`. +2. `Y` -> `void sleep_ms(uint32_t ms)`. + +#### `stdio_init_all` and `__wrap_printf` + +Same as Project 1, different addresses: `stdio_init_all` at `0x100030cc` (`bool stdio_init_all(void)`), and `__wrap_printf` at `0x1000325c` (`int __wrap_printf(const char *fmt, ...)`). + +Then work down the table the same way. + +Same idea as Project 1: **our code plus what it calls**, not the whole SDK. The call chain here is one function longer because `main` also drives the GPIO and sleeps: + +``` +main +├── stdio_init_all +│ ├── stdio_uart_init ── gpio_set_function, uart_init +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ ├── stdio_put_string ── strlen +│ └── time_us_64 +├── gpio_init +├── __wrap_printf ── __wrap_vprintf +└── sleep_ms +``` + +Two things in this project have **no symbol of their own**, because the compiler inlined them into `main`: + +- `blink_and_print` — the `static` helper in our own source is inlined, so there is no `blink_and_print` address to rename. You see its body directly inside `main`. +- `gpio_set_dir` and `gpio_put` — these are `static inline` in the SDK headers, so they compile to the `mcrr`/SIO writes you see in `main` rather than to calls. + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002b4` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000278` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000d10` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x10002e74` | `exit` | `void exit(int)` | +| `0x10002e7c` | `runtime_init` | `void runtime_init(void)` | +| `0x100030cc` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003418` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100030a4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10002ea8` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002fb8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000325c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003198` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10000f88` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10000ef4` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10003558` | `strlen` | `size_t strlen(const char*)` | + +Python console shortcut (resolves name **and** type): + +```python +from binaryninja import Symbol, SymbolType +# The raw .bin has no headers, so these SDK types don't exist. set_user_type() +# re-parses each signature as C, so an undefined name raises +# "SyntaxError: unknown type name '...'". Define them first. +sdk = bv.parse_types_from_string(""" +typedef unsigned int uint; +typedef char* va_list; +struct stdio_driver; +typedef struct stdio_driver stdio_driver_t; +struct uart_inst; +typedef struct uart_inst uart_inst_t; +enum gpio_function { + GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, + GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, + GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +}; +typedef enum gpio_function gpio_function_t; +""") +for name, ty in sdk.types.items(): + bv.define_user_type(name, ty) + +# address: (name, signature); None means "leave the type alone" +funcs = { + 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), + 0x10000186: ("platform_entry", "void platform_entry(void)"), + 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), + 0x100001e4: ("_init", "void _init(void)"), + 0x10000210: ("frame_dummy", "void frame_dummy(void)"), + 0x10000234: ("main", "int main(void)"), + 0x100002b4: ("gpio_init", "void gpio_init(uint)"), + 0x10000278: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), + 0x10000d10: ("sleep_ms", "void sleep_ms(uint32_t)"), + 0x10002e74: ("exit", "void exit(int)"), + 0x10002e7c: ("runtime_init", "void runtime_init(void)"), + 0x100030cc: ("stdio_init_all", "bool stdio_init_all(void)"), + 0x10003418: ("stdio_uart_init", "void stdio_uart_init(void)"), + 0x100030a4: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), + 0x10002ea8: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), + 0x10002fb8: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), + 0x1000325c: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), + 0x10003198: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), + 0x10000f88: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), + 0x10000ef4: ("time_us_64", "uint64_t time_us_64(void)"), + 0x10003558: ("strlen", "size_t strlen(const char*)"), +} +for addr, (name, sig) in funcs.items(): + bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) + if sig: + f = bv.get_function_at(addr) + if f is not None: + f.set_user_type(sig) +``` + +The decompiler now shows `main` initializing GPIO 16 and looping. We make two changes: + +- **Move the LED from GPIO 16 to GPIO 17** by patching three `0x10` immediates. +- **Change the printed value from 0 to 66** by patching one `0x00` immediate. + +### Step 27: Patch 1 — move the LED from GPIO 16 to GPIO 17 + +GPIO 16 is the red LED; GPIO 17 is the green LED. The pin number appears in three instructions. Change the low byte of each from `10` to `11`: + +| Address | Instruction | Bytes before | Bytes after | Role | +| ------- | ----------- | ------------ | ----------- | ---- | +| `0x1000023a` | `movs r0, #16` | `10 20` | `11 20` | pin passed to `gpio_init` | +| `0x10000244` | `movs r3, #16` | `10 23` | `11 23` | pin used by `gpio_set_dir` | +| `0x10000252` | `movs r4, #16` | `10 24` | `11 24` | pin used by `gpio_put` in the blink loop | + +In the **Hex** view (lock off), change each byte and reanalyze. Or in the Python console: + +```python +for addr in (0x1000023a, 0x10000244, 0x10000252): + bv.write(addr, b"\x11") +``` + +> **All three are required.** If you patch only the `gpio_set_dir` site, pin 17's output driver is enabled but `gpio_put` still drives pin 16, whose driver was never enabled. Nothing lights up. This is the most common mistake in this lesson. + +### Step 28: Patch 2 — change the printed value from 0 to 66 + +`main` loads `age = 0` with `movs r1, #0` at `0x1000024a`. Change the immediate byte from `00` to `42` (`0x42` = 66): + +```python +bv.write(0x1000024a, b"\x42") +``` + +Verify all four patches: + +```python +for addr in (0x1000023a, 0x10000244, 0x10000252, 0x1000024a): + print(hex(addr), hex(bv.read(addr, 1)[0])) +# -> 0x1000023a 0x11 +# -> 0x10000244 0x11 +# -> 0x10000252 0x11 +# -> 0x1000024a 0x42 +``` + +### Step 28b: Patch the string `age:` to `foo:` + +The format string starts at `0x10003618`; change its first three bytes `61 67 65` (`age`) to `66 6f 6f` (`foo`): + +```python +bv.write(0x10003618, b"foo") +print(bv.read(0x10003618, 10)) # -> b'foo: %d\r\n\x00' +``` + +Exactly three bytes, same rule as Project 1: a shorter string must be padded, a longer one overwrites the `: %d` tail. + +### Step 29: Export, convert, and flash + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0008_uninitialized-variables", "build"), "0x0008_uninitialized-variables-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15668 /.../build/0x0008_uninitialized-variables-h.bin +``` + +Same as Project 1: `seg.start` is the load base and `seg.data_length` is the image size (here `0x3d34` = 15668) — both read from the view, and no relative path (the console's CWD is read-only). + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0008_uninitialized-variables-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0008_uninitialized-variables-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the Binary Ninja console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21 (stop any running OpenOCD first, and use `Popen`, not `run`, so the console is not blocked): + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +bin_path = os.path.join(os.path.join(root, "0x0008_uninitialized-variables", "build"), "0x0008_uninitialized-variables-h.bin") +log = os.path.join(os.path.join(root, "0x0008_uninitialized-variables", "build"), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +### Step 30: Verify + +Open the serial monitor: + +``` +age: 66 +age: 66 +age: 66 +... +``` + +The **green LED on GPIO 17** now blinks instead of the red one. + +**We changed the printed value and moved the LED, with four bytes and no source code.** + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r1", 0x46)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 / 26 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 13). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Start the server parked in the loop | macOS/Linux: `BP_ADDR=0x1000023e ./debug-server.sh` — Windows: `$env:BP_ADDR="0x1000023e"; .\debug-server.ps1` (`0x1000024e` for Project 2) | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0005` | `0x1000023a` | `2b` | `46` | prints `age: 70` | +| `0x0008` | `0x1000023a` | `10` | `11` | `gpio_init` configures GPIO 17 | +| `0x0008` | `0x10000244` | `10` | `11` | `gpio_set_dir` enables GPIO 17 | +| `0x0008` | `0x10000252` | `10` | `11` | `gpio_put` drives GPIO 17 | +| `0x0008` | `0x1000024a` | `00` | `42` | prints `age: 66` | +| `0x0005` | `0x100034a0` | `61 67 65` | `66 6f 6f` | string prints `foo:` instead of `age:` | +| `0x0008` | `0x10003618` | `61 67 65` | `66 6f 6f` | string prints `foo:` instead of `age:` | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project 1 size | `15292` bytes | +| Project 2 size | `15668` bytes | +| Fixed `main` anchor (both projects) | `0x1000018c` (reset handler middle `blx`) | +| `main` (both projects) | `0x10000234` | +| `printf` call, Project 1 | `0x1000023e` | +| `printf` call, Project 2 | `0x1000024e` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints (see the next entry). +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 11). The 13.3.rel1 build (what `/opt/homebrew/bin/arm-none-eabi-gdb` symlinks to) did not connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +**Use GDB MI**, with the 14.2.rel1 path above. If it still fails, fall back to plain `arm-none-eabi-gdb` against the same server — the addresses and register values are identical to the GUI steps. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### The GUI refuses to set a breakpoint (GDB RSP adapter only) + +If you are on the **GDB RSP** adapter, the GUI cannot set breakpoints on this target. That adapter is Binary Ninja's own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 comparators need 2 bytes, so OpenOCD answers `only breakpoints of two bytes length supported`. It affects every address, both `Toggle Breakpoint` and `Add Hardware Breakpoint`, and the dialog's **Size** field is disabled. `gdb_breakpoint_override` makes no difference. + +**Fix: use the GDB MI adapter** (Step 11). It drives real GDB, which sends the correct length, so GUI breakpoints just work. If you must stay on GDB RSP, arm breakpoints from the command port after connecting (`bp 2 hw`) — but the lab uses GDB MI and does not need that. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. This is a Binary Ninja bug. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +Never have a breakpoint in the binary view before the GDB MI connection. If it hangs, quit Binary Ninja, restart the server with `BP_ADDR`, and connect again before adding any breakpoints. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping, because the RP2350 config's `-rtos hwthread` makes the current thread id 1 while Binary Ninja sends thread id 0. Fix: `rp2350.dap.core0 configure -rtos none` (the launcher scripts already pass this). **GDB MI does not hit this.** + +To tell them apart, turn on OpenOCD logging (`log_output /tmp/ocd.log`, then `debug_level 3` on the command port) and look for `fake step` versus `Duplicate Breakpoint`. + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps `blink_and_print` separate, so Project 2's `main` is not at `0x10000234`. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. With the **GDB MI** adapter, `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — that is a software breakpoint and cannot be written to read-only flash, so it never installs. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches (`breakpoint_remove_all_internal` -> `Delete all breakpoints`), so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line, and to `hbreak` followed by `detach` in GDB. +- **Verify it is armed:** `mdw 0xE0002000 8`. You should see your address with the low bit set (`0x10000234` -> `0x10000235`). All zeros means nothing is armed — re-read this first, because it distinguishes "not armed" from "armed but never reached". +- **Is the core running?** `poll` on the command port should not report a halt. If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup (Step 10) rather than `reset run` while attached. Loop addresses such as `0x1000023e` fire on the next pass with no reset — arm them and click **Resume** in Binary Ninja. +- **With GDB MI the stop is reported as `Breakpoint`** and appears in the **Breakpoints** widget, because GDB really did set it. (On the old **GDB RSP** workaround the stop showed as `SingleStep` with an empty widget, because the breakpoint was armed behind Binary Ninja's back.) + +### I edit `r1` (or another register) and it reverts + +`main` reloads the value at the top of every loop iteration — `movs r1, #43` at `0x1000023a` runs right before the `printf` at `0x1000023e`. So `r1` is only `0x46` for the instant between your edit and the next pass; then it is `0x2b` again. The edit sticks only if the core is **genuinely stopped** at the breakpoint and stays stopped. + +If it keeps reverting, the core is running, which almost always means the breakpoint is not installed — usually because it is a **software** breakpoint (`F2`) that cannot be written to read-only flash. Use `Debugger -> Add Hardware Breakpoint...` (hardware execute). Confirm with `mdw 0xE0002000 4` on the command port: a hardware breakpoint shows as `0x1000023f`; all zeros means nothing is armed. + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target, and there is no "refresh registers" command (only "Force Update Memory Cache", which is for memory). So a value changed outside Binary Ninja will not appear until the next stop. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first: clear canonical/echo flags, set `CLOCAL|CREAD`, and `B115200` on input and output. `screen /dev/cu.usbmodem* 115200` does all of this for you; a script must call `tcsetattr` itself. Once set, the capture reads clean `age: 43` lines. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +This is the most common failure, and it has one main cause: **driving the core from the OpenOCD command port while Binary Ninja is connected.** + +- If you send `reset run` from the port while attached, the core resets, runs, and halts at your breakpoint — but Binary Ninja never receives the stop event. Its sidebar keeps showing the *previous* location, so **Step** and **Resume** act on a stale PC and appear to do nothing. Verified: target at `0x1000023e` while the sidebar still read `Stopped at 0x10003020`. +- If the OpenOCD process dies (or you restart it) while attached, Binary Ninja keeps believing it is connected: the sidebar stays, but the menu shows **Pause** enabled and **Resume**/**Step** disabled because Binary Ninja last saw the target *running*. + +Recovery: **Detach, then reconnect.** If Detach does nothing (the connection is already dead), restart Binary Ninja — its menu still shows a session that no longer exists. + +Prevention: +- Stop at `main` with `BP_ADDR` on a fresh server start, not with `reset run` while attached. +- For loop addresses, set the breakpoint in the GUI and click **Resume**. Let Binary Ninja be the thing that starts the core. +- If you must reset, **Detach first**, `reset run`, then reconnect. +- Never leave a breakpoint on the PC you are about to step or resume from (see the stepping section above). + +> **If the stop is at `0x1000320c` rather than your breakpoint,** you stopped inside `stdio_uart_out_flush`, not at `main`. See the next section. + +### The target "blows past" `main` and stops at `0x1000320c` instead + +`0x1000320c` is inside `stdio_uart_out_flush`: + +```asm +1000320c: 6993 ldr r3, [r2, #24] +1000320e: 071b lsls r3, r3, #28 +10003210: d4fc bmi.n 0x1000320c +``` + +That is the UART transmit-FIFO drain loop inside `printf`, so the core is running `main`'s loop and simply spends nearly all its time there. The breakpoint at `main` did not fire because `main`'s entry (`0x10000234`) runs exactly **once per reset**. If you arm the breakpoint after the reset, or set it while the target is already running and just resume, the core is already past `0x10000234` and will never re-execute it. Either arm the breakpoint **before** resetting, or break inside the loop at `0x1000023e`, which fires every iteration. + +**`0x1000320c` is not a function.** It is one instruction inside `stdio_uart_out_flush`, which starts at `0x10003208`: + +```asm +10003208 : +10003208: 4b02 ldr r3, [pc, #8] ; @ 0x10003214 +1000320a: 681a ldr r2, [r3] +1000320c: 6993 ldr r3, [r2, #24] ; the core sits here while the UART drains +1000320e: 071b lsls r3, r3, #28 +10003210: d4fc bmi.n 0x1000320c +10003212: 4770 bx lr +10003214: 20000850 .word 0x20000850 +``` + +If Binary Ninja has created a function at `0x1000320c` (for example because the debugger stopped at that PC), the decompiler shows garbage: registers named `entry_r4`/`entry_r5`, and stores to invented constants like `0x3a` and `0xfffffff6`. Delete that bogus function (right-click it -> `Delete Function`, or put the cursor on it and press `U` to undefine) and reanalyze. The real function is `stdio_uart_out_flush` at `0x10003208`. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### `Connect to Remote Process` is greyed out and Pause does nothing + +Binary Ninja is in a stale session, usually because the debug server restarted while attached. Quit and reopen Binary Ninja (or the `.bndb`) and connect again. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +### Project 2's LED does not light at all after patching + +You patched only some of the three GPIO 16 sites. All three of `0x1000023a`, `0x10000244`, and `0x10000252` must change. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27 (see Troubleshooting), you can still do the live hack with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 10), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x1000023e +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x1000023e` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. If you reset first, the core runs `main` and you will not catch it. + +GDB stops at the `printf` call. Confirm the value, change it, and let it run: + +``` +info registers pc r1 # pc = 0x1000023e, r1 = 0x2b +set $r1 = 0x46 +stepi +continue +``` + +The serial monitor prints `age: 70` for the iteration you changed — the same temporary live hack as editing `r1` in the Binary Ninja Registers widget. When you are done, press `Ctrl-C`, then `detach` and `quit`. + +**If you specifically want to stop at `main` (`0x10000234`),** remember its entry runs only once per reset, so the breakpoint must be armed *before* the reset: + +``` +monitor reset halt +hbreak *0x10000234 +continue +``` + +If you instead set it while the target is running and just `continue`, you will "blow past" `main` and catch the core inside `printf` — in this build at `0x1000320c`, the `stdio_uart_out_flush` UART-drain loop. + +Project 2 is the same with the other call site and value: + +``` +hbreak *0x1000024e +continue +info registers pc r1 # pc = 0x1000024e, r1 = 0 +set $r1 = 0x42 +stepi +``` + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too; the old **GDB RSP** adapter was the one that sent a 1-byte length and could not set breakpoints here. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +| **Hardware breakpoint** | A breakpoint serviced by the CPU comparators, required for read-only flash | +| **Inlining** | The optimizer replacing a function call with the function body; why `blink_and_print` disappears in `Release` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, resolve the names from the ELF, then patch the bytes and flash. diff --git a/WEEK04/WEEK04-BN.pdf b/WEEK04/WEEK04-BN.pdf new file mode 100644 index 0000000..a77e1af Binary files /dev/null and b/WEEK04/WEEK04-BN.pdf differ diff --git a/WEEK04/WEEK04-IDA.md b/WEEK04/WEEK04-IDA.md new file mode 100644 index 0000000..8b3f2eb --- /dev/null +++ b/WEEK04/WEEK04-IDA.md @@ -0,0 +1,94 @@ +# Week 4-IDA: IDA Pro — Resolve, Hack, and Patch the RP2350 (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into IDA at `0x10000000` +- **Resolve the functions in the IDA GUI** using the ELF symbol map +- **Patch** the bytes that control the behavior, export the image, and export it + +--- + +## How This Guide Works + +The build produces two files for each project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in IDA, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 4 lesson, and the Week 4 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it folds `age = 42` away in Project 1 and inlines `blink_and_print` into `main` in Project 2. If you build `Debug`, the SDK function addresses move and Project 2 keeps a separate `blink_and_print`, so nothing lines up. Always build `Release` for this lesson. + +The workflow is static-only: import the raw image, recover the code, decompile it, and patch the artifact: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Prints | Also does | The hack | +| ------- | ------ | --------- | -------- | +| `0x0005_intro-to-variables` | `age: 43` | loops on `printf` | change `43` to `70` | +| `0x0008_uninitialized-variables` | `age: 0` | blinks the red LED on GPIO 16 | change `0` to `66`, move the LED to GPIO 17 | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +ly flash | +| **Inlining** | The optimizer replacing a function call with the function body; why `blink_and_print` disappears in `Release` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions. diff --git a/WEEK04/WEEK04-IDA.pdf b/WEEK04/WEEK04-IDA.pdf new file mode 100644 index 0000000..ad54289 Binary files /dev/null and b/WEEK04/WEEK04-IDA.pdf differ diff --git a/WEEK04/WEEK04-SLIDES.pdf b/WEEK04/WEEK04-SLIDES.pdf new file mode 100644 index 0000000..4716ca1 Binary files /dev/null and b/WEEK04/WEEK04-SLIDES.pdf differ diff --git a/WEEK04/WEEK04.md b/WEEK04/WEEK04.md new file mode 100644 index 0000000..bdc437e --- /dev/null +++ b/WEEK04/WEEK04.md @@ -0,0 +1,945 @@ +# Week 4: Variables in Embedded Systems: Debugging and Hacking Variables w/ GPIO Output Basics + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand what variables are and how they're stored in memory +- Know the difference between initialized, uninitialized, and constant variables +- Use Ghidra to analyze binaries without debug symbols +- Patch binary files to change program behavior permanently +- Control GPIO pins to blink LEDs on the Pico 2 +- Convert patched binaries to UF2 format for flashing +- Understand the `.data`, `.bss`, and `.rodata` memory sections + +--- + +## Part 1: Understanding Variables + +### What is a Variable? + +A **variable** is like a labeled box where you can store information. Imagine you have a row of boxes numbered 0 to 9. Each box can hold one item. In programming: + +- The **boxes** are memory locations (addresses in SRAM) +- The **items** are the values you store +- The **labels** are the variable names you choose + +``` ++-----------------------------------------------------------------+ +| Memory (SRAM) - Like a row of numbered boxes | +| | +| Box 0 Box 1 Box 2 Box 3 Box 4 ... | +| +----+ +----+ +----+ +----+ +----+ | +| | 42 | | 17 | | 0 | |255 | | 99 | | +| +----+ +----+ +----+ +----+ +----+ | +| age score count max temp | +| | ++-----------------------------------------------------------------+ +``` + +### Declaration vs Definition + +When working with variables, there are two important concepts: + +| Concept | What It Does | Example | +| ------------------ | ------------------------------------ | -------------------------- | +| **Declaration** | Tells the compiler the name and type | `uint8_t age;` | +| **Definition** | Allocates memory for the variable | (happens with declaration) | +| **Initialization** | Assigns an initial value | `uint8_t age = 42;` | + +**Important Rule:** You must declare a variable BEFORE you use it! + +### Understanding Data Types + +The **data type** tells the compiler how much memory to allocate: + +| Type | Size | Range | Description | +| ---------- | ------- | ------------------------------- | ----------------------- | +| `uint8_t` | 1 byte | 0 to 255 | Unsigned 8-bit integer | +| `int8_t` | 1 byte | -128 to 127 | Signed 8-bit integer | +| `uint16_t` | 2 bytes | 0 to 65,535 | Unsigned 16-bit integer | +| `int16_t` | 2 bytes | -32,768 to 32,767 | Signed 16-bit integer | +| `uint32_t` | 4 bytes | 0 to 4,294,967,295 | Unsigned 32-bit integer | +| `int32_t` | 4 bytes | -2,147,483,648 to 2,147,483,647 | Signed 32-bit integer | + +### Anatomy of a Variable Declaration + +Let's break down this line of code: + +```c +uint8_t age = 42; +``` + +| Part | Meaning | +| --------- | ----------------------------------------------------- | +| `uint8_t` | Data type - unsigned 8-bit integer (1 byte) | +| `age` | Variable name - how we refer to this storage location | +| `=` | Assignment operator - puts a value into the variable | +| `42` | The initial value | +| `;` | Semicolon - tells compiler the statement is complete | + +--- + +## Part 2: Memory Sections - Where Variables Live + +### The Three Main Sections + +When your program is compiled, variables go to different places depending on how they're declared: + +``` ++-----------------------------------------------------------------+ +| .data Section (Flash -> copied to RAM at startup) | +| Contains: Initialized global/static variables | +| Example: int counter = 42; | ++-----------------------------------------------------------------+ +| .bss Section (RAM - zeroed at startup) | +| Contains: Uninitialized global/static variables | +| Example: int counter; (will be 0) | ++-----------------------------------------------------------------+ +| .rodata Section (Flash - read only) | +| Contains: Constants, string literals | +| Example: const int MAX = 100; | +| Example: "hello, world" | ++-----------------------------------------------------------------+ +``` + +### What Happens to Uninitialized Variables? + +In older C compilers, uninitialized variables could contain "garbage" - random leftover data. But modern compilers (including the Pico SDK) are smarter: + +1. Uninitialized global variables go into the `.bss` section +2. The `.bss` section is **NOT stored in the binary** (saves space!) +3. At boot, the startup code uses `memset` to **zero out** all of `.bss` +4. So uninitialized variables are always `0`! + +This is why in our code: +```c +uint8_t age; // This will be 0, not garbage! +``` + +--- + +## Part 3: Understanding GPIO (General Purpose Input/Output) + +### What is GPIO? + +**GPIO** stands for **General Purpose Input/Output**. These are pins on the microcontroller that you can control with software. Think of them as tiny switches you can turn on and off. + +``` ++-----------------------------------------------------------------+ +| Raspberry Pi Pico 2 | +| | +| GPIO 16 -------► Red LED | +| GPIO 17 -------► Green LED | +| GPIO 18 -------► Blue LED | +| ... | +| GPIO 25 -------► Onboard LED | ++-----------------------------------------------------------------+ +``` + +### GPIO Functions in the Pico SDK + +The Pico SDK provides simple functions to control GPIO pins: + +| Function | Purpose | +| ------------------------------ | ------------------------------- | +| `gpio_init(pin)` | Initialize a GPIO pin for use | +| `gpio_set_dir(pin, direction)` | Set pin as INPUT or OUTPUT | +| `gpio_put(pin, value)` | Set pin HIGH (1) or LOW (0) | +| `sleep_ms(ms)` | Wait for specified milliseconds | + +### What Happens Behind the Scenes? + +Each high-level function calls lower-level code. Let's trace `gpio_init()`: + +``` +gpio_init(LED_PIN) + ↓ +gpio_set_dir(LED_PIN, GPIO_IN) // Initially set as input + ↓ +gpio_put(LED_PIN, 0) // Set output value to 0 + ↓ +gpio_set_function(LED_PIN, GPIO_FUNC_SIO) // Connect to SIO block +``` + +The SIO (Single-cycle I/O) block is a special hardware unit in the RP2350 that provides fast GPIO control! + +--- + +## Part 4: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. Ghidra installed (for static analysis) +3. Python installed (for UF2 conversion) +4. The sample projects: + - `0x0005_intro-to-variables` + - `0x0008_uninitialized-variables` +5. A serial monitor (PuTTY, minicom, or screen) + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x0005_intro-to-variables/ +| +-- build/ +| | +-- 0x0005_intro-to-variables.uf2 +| | +-- 0x0005_intro-to-variables.bin +| +-- 0x0005_intro-to-variables.c ++-- 0x0008_uninitialized-variables/ +| +-- build/ +| | +-- 0x0008_uninitialized-variables.uf2 +| | +-- 0x0008_uninitialized-variables.bin +| +-- 0x0008_uninitialized-variables.c ++-- uf2conv.py +``` + +--- + +## Part 5: Hands-On Tutorial - Analyzing Variables in Ghidra + +### Step 1: Review the Source Code + +First, let's look at the code we'll be analyzing: + +**File: `0x0005_intro-to-variables.c`** + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + uint8_t age = 42; + + age = 43; + + stdio_init_all(); + + while (true) + printf("age: %d\r\n", age); +} +``` + +**What this code does:** + +1. Declares a variable `age` and initializes it to `42` +2. Changes `age` to `43` +3. Initializes the serial output +4. Prints `age` forever in a loop + +### Step 2: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x0005_intro-to-variables.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 3: Verify It's Working + +Open your serial monitor (PuTTY, minicom, or screen) and you should see: + +``` +age: 43 +age: 43 +age: 43 +... +``` + +The program is printing `43` because that's what we assigned after the initial `42`. + +--- + +## Part 6: Setting Up Ghidra for Binary Analysis + +### Step 4: Start Ghidra + +**Open a terminal and type:** + +```cmd +ghidraRun +``` + +Ghidra will open. Now we need to create a new project. + +### Step 5: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x0005_intro-to-variables` +5. Click **Finish** + +### Step 6: Import the Binary + +1. Open your file explorer +2. Navigate to the `Embedded-Hacking` folder +3. Find `0x0005_intro-to-variables.bin` +4. Select Cortex M Little Endian 32 +5. Select Options and set up the .text and offset 10000000 +6. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 7: Configure the Binary Format + +A dialog appears. The file is identified as a "BIN" (raw binary without debug symbols). + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` (the XIP address!) +3. Click **OK** + +### Step 8: Open and Analyze + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete (watch the progress bar in the bottom right). + +--- + +## Part 7: Navigating and Resolving Functions + +### Step 9: Find the Functions + +Look at the **Symbol Tree** panel on the left. Expand **Functions**. + +You'll see function names like: + +- `FUN_1000019a` +- `FUN_10000210` +- `FUN_10000234` + +These are auto-generated names because we imported a raw binary without symbols! + +### Step 10: Resolve Known Functions + +From our previous chapters, we know what some of these functions are: + +| Ghidra Name | Actual Name | How We Know | +| -------------- | ------------- | -------------------------- | +| `FUN_1000019a` | `data_cpy` | From Week 3 boot analysis | +| `FUN_10000210` | `frame_dummy` | From Week 3 boot analysis | +| `FUN_10000234` | `main` | This is where our code is! | + +### Step 11: Update Main's Signature + +For `main`, let's also fix the return type: + +1. Right-click on `main` in the Decompile window +2. Select **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +--- + +## Part 8: Analyzing the Main Function + +### Step 12: Examine Main in Ghidra + +Click on `main` (or `FUN_10000234`). Look at the **Decompile** window: + +You'll see something like: + +```c +void FUN_10000234(void) + +{ + FUN_10002f54(); + do { + FUN_100030e4(DAT_10000244,0x2b); + } while( true ); +} +``` + +### Step 13: Resolve stdio_init_all + +1. Click on `FUN_10002f54` +2. Right-click -> **Edit Function Signature** +3. Change to: `bool stdio_init_all(void)` +4. Click **OK** + +### Step 14: Resolve printf + +1. Click on `FUN_100030e4` +2. Right-click -> **Edit Function Signature** +3. Change the name to `void printf (undefined4 param_1, ...)` +4. Check the **Varargs** checkbox (printf takes variable arguments!) +5. Click **OK** + +### Step 15: Understand the Optimization + +Look at the updated decompiled code. This will look different if you resolved your functions however do you notice something interesting? + +```c +int main(void) + +{ + stdio_init_all(); + do { + printf(DAT_10000244,0x2b); + } while( true ); +} +``` + +**Where's `uint8_t age = 42`?** It's gone! + +The compiler **optimized it out**! Here's what happened: + +1. Original code: `age = 42`, then `age = 43` +2. Compiler sees: "The `42` is never used, only `43` matters" +3. Compiler removes the unused `42` and just uses `43` directly + +**What is `0x2b`?** Let's check: + +- `0x2b` in hexadecimal = `43` in decimal + +The compiler replaced our variable with the constant value! + +--- + +## Part 9: Patching the Binary - Changing the Value + +### Step 16: Find the Value to Patch + +Look at the **Listing** window (assembly view). Find the instruction that loads `0x2b`: + +```assembly +1000023a 2b 21 movs r1,#0x2b +``` + +This instruction loads the value `0x2b` (43) into register `r1` before calling `printf`. + +### Step 17: Patch the Instruction + +We're going to change `0x2b` (43) to `0x46` (70)! + +To patch instructions cleanly in Ghidra without assembler context conflicts, use the **Bytes Window** workflow: + +1. Ensure the Bytes window is open (**Window** -> **Bytes: 0x0005_intro-to-variables.bin**). +2. In the Bytes window toolbar, click the **pencil icon** (**Toggle Edit Mode**) to enable editing. +3. In the **Listing** window, click on address `1000023a` (`movs r1,#0x2b`) and press **`C`** (**Clear Code Bytes**). +4. In the **Bytes** window at offset `1000023a`, click on byte `2B` and change it to **`46`**. +5. In the **Listing** window, click back on address `1000023a` and press **`D`** (**Disassemble**). + +*(Alternatively, you can right-click the instruction at `1000023a` in the Listing, select **Patch Instruction**, replace immediate `0x2b` with `0x46`, and press Enter)*. + +The instruction now reads: +```assembly +1000023a 46 21 movs r1,#0x46 +``` + +### Step 18: Export the Patched Binary + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. Navigate to your build directory +4. Name the file `0x0005_intro-to-variables-h.bin` +5. Click **OK** + +--- + +## Part 10: Converting and Flashing the Hacked Binary + +### Step 19: Convert to UF2 Format + +The Pico 2 expects UF2 files, not raw BIN files. We need to convert it! + +**Open a terminal and navigate to your project directory:** + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0005_intro-to-variables +``` + +**Run the conversion command:** + +```cmd +python ..\uf2conv.py build\0x0005_intro-to-variables-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +**What this command means:** + +- `uf2conv.py` = the conversion script +- `--base 0x10000000` = the XIP base address +- `--family 0xe48bff59` = the RP2350 family ID +- `--output build\hacked.uf2` = the output filename + +### Step 20: Flash the Hacked Binary + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Open your serial monitor + +**You should see:** + +``` +age: 70 +age: 70 +age: 70 +... +``` + + **BOOM! We hacked it!** The value changed from 43 to 70! + +--- + +## Part 11: Uninitialized Variables and GPIO + +Now let's work with a more complex example that includes GPIO control. + +### Step 21: Review the Uninitialized Variables Code + +**File: `0x0008_uninitialized-variables.c`** + +```c +#include +#include "pico/stdlib.h" + +#define LED_PIN 16 + +int main(void) { + uint8_t age; // Uninitialized! + + stdio_init_all(); + + gpio_init(LED_PIN); + gpio_set_dir(LED_PIN, GPIO_OUT); + + while (true) { + printf("age: %d\r\n", age); + + gpio_put(LED_PIN, 1); + sleep_ms(500); + + gpio_put(LED_PIN, 0); + sleep_ms(500); + } +} +``` + +**What this code does:** + +1. Declares `age` without initializing it (will be 0 due to BSS zeroing) +2. Initializes GPIO 16 as an output +3. In a loop: prints age, blinks the LED + +### Step 22: Flash and Verify + +1. Flash `0x0008_uninitialized-variables.uf2` to your Pico 2 +2. Open your serial monitor + +**You should see:** + +``` +age: 0 +age: 0 +age: 0 +... +``` + +And the **red LED on GPIO 16 should be blinking**! + +The value is `0` because uninitialized variables in the `.bss` section are zeroed at startup. + +--- + +## Part 12: Analyzing GPIO Code in Ghidra + +### Step 23: Set Up Ghidra for the New Binary + +1. Create a new project: `0x0008_uninitialized-variables` +2. Import `0x0008_uninitialized-variables.bin` +3. Set Language to **ARM Cortex 32 little endian** +4. Set Base Address to `.text` and `10000000` +5. Auto-analyze + +### Step 24: Resolve the Functions + +Find and rename these functions: + +| Ghidra Name | Actual Name | +| -------------- | ---------------- | +| `FUN_10000234` | `main` | +| `FUN_100030cc` | `stdio_init_all` | +| `FUN_100002b4` | `gpio_init` | +| `FUN_1000325c` | `printf` | + +For `gpio_init`, set the signature to: +```c +void gpio_init(uint gpio) +``` + +### Step 25: Examine the Main Function + +The decompiled main should look something like: + +```c +void FUN_10000234(void) + +{ + undefined4 extraout_r1; + undefined4 extraout_r2; + undefined4 in_cr0; + undefined4 in_cr4; + + FUN_100030cc(); + FUN_100002b4(0x10); + coprocessor_moveto2(0,4,0x10,1,in_cr4); + do { + FUN_1000325c(DAT_10000274,0); + coprocessor_moveto2(0,4,0x10,1,in_cr0); + FUN_10000d10(500); + coprocessor_moveto2(0,4,0x10,0,in_cr0); + FUN_10000d10(500,extraout_r1,extraout_r2,0); + } while( true ); +} +``` + +--- + +## Part 13: Hacking GPIO - Changing the LED Pin + +### Step 26: Find the GPIO Pin Value + +Look in the assembly for instructions that use `0x10` (which is 16 in decimal - our LED pin): + +```assembly +1000023a 10 20 movs r0,#0x10 +``` + +This is where `gpio_init(LED_PIN)` is called with GPIO 16. + +### Step 27: Patch GPIO 16 to GPIO 17 + +We'll change the red LED (GPIO 16) to the green LED (GPIO 17)! + +1. In the **Listing** window, click address `1000023a` (`movs r0,#0x10`) and press **`C`** (**Clear Code Bytes**). +2. In the **Bytes** window (with the pencil icon enabled), locate offset `1000023a`, click byte `10`, and change it to **`11`**. +3. In the **Listing** window, click back on address `1000023a` and press **`D`** (**Disassemble**). + +*(Alternatively, right-click `movs r0,#0x10` -> **Patch Instruction** -> change `0x10` to `0x11` and press Enter)*. + +### Step 28: Find All GPIO 16 References + +There are more places that use GPIO 16. Look for: + +```assembly +10000244 10 23 movs r3,#0x10 +``` + +This is used in `gpio_set_dir`. In Listing press **`C`** at `10000244`, change byte `10` to **`11`** in the Bytes window, and press **`D`** in Listing. + +```assembly +10000252 10 24 movs r4,#0x10 +``` + +This is inside the loop for `gpio_put`. In Listing press **`C`** at `10000252`, change byte `10` to **`11`** in the Bytes window, and press **`D`** in Listing. +Verify the patched bytes: + +- `10000244`: `10 23` -> `11 23` +- `10000252`: `10 24` -> `11 24` + +### Step 29: Bonus - Change the Printed Value + +Let's also change the printed value from `0` to `0x42` (66 in decimal): + +```assembly +1000024a 00 21 movs r1,#0x0 +``` + +1. In Listing, click `1000024a` and press **`C`** (**Clear Code Bytes**). +2. In the Bytes window, change byte `00` to **`42`**. +3. In Listing, click back on `1000024a` and press **`D`** (**Disassemble**). +4. Verify the instruction bytes change from `00 21` to `42 21`. + +--- + +## Part 14: Export and Test the Hacked GPIO + +### Step 30: Export the Patched Binary + +1. Click **File** -> **Export Program** +2. Format: **Raw Bytes** +3. Filename: `0x0008_uninitialized-variables-h.bin` +4. Click **OK** + +### Step 31: Convert to UF2 + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0008_uninitialized-variables +python ..\uf2conv.py build\0x0008_uninitialized-variables-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 32: Flash and Verify + +1. Flash `hacked.uf2` to your Pico 2 +2. Check your serial monitor + +**You should see:** + +``` +age: 66 +age: 66 +age: 66 +... +``` + +And now the **GREEN LED on GPIO 17** should be blinking instead of the red one! + + **We successfully:** + +1. Changed the printed value from 0 to 66 +2. Changed which LED blinks from red (GPIO 16) to green (GPIO 17) + +--- + +## Part 15: Deep Dive - GPIO at the Assembly Level + +### Understanding the GPIO Coprocessor + +The RP2350 has a special **GPIO coprocessor** that provides fast, single-cycle GPIO control. This is different from the RP2040! + +The coprocessor is accessed using special ARM instructions: + +```assembly +mcrr p0, #4, r4, r5, c0 ; GPIO output control +mcrr p0, #4, r4, r5, c4 ; GPIO direction control +``` + +**What this means:** + +- `mcrr` = Move to Coprocessor from two ARM Registers +- `p0` = Coprocessor 0 (the GPIO coprocessor) +- `r4` = Contains the GPIO pin number +- `r5` = Contains the value (0 or 1) +- `c0` = Output value register +- `c4` = Output enable register + +### The Full GPIO Initialization Sequence + +When you call `gpio_init(16)`, here's what actually happens: + +``` +Step 1: Configure pad (address 0x40038044) ++-----------------------------------------------------------------+ +| - Clear OD bit (output disable) | +| - Set IE bit (input enable) | +| - Clear ISO bit (isolation) | ++-----------------------------------------------------------------+ + +Step 2: Set function (address 0x40028084) ++-----------------------------------------------------------------+ +| - Set FUNCSEL to 5 (SIO - Software I/O) | ++-----------------------------------------------------------------+ + +Step 3: Enable output (via coprocessor) ++-----------------------------------------------------------------+ +| - mcrr p0, #4, r4, r5, c4 (where r4=16, r5=1) | ++-----------------------------------------------------------------+ +``` + +### Raw Assembly LED Blink + +Here's what a completely hand-written assembly LED blink looks like: + +```assembly +; Initialize GPIO 16 as output +movs r4, #0x10 ; GPIO 16 +movs r5, #0x01 ; Enable +mcrr p0, #4, r4, r5, c4 ; Set as output + +; Configure pad registers +ldr r3, =0x40038044 ; Pad control for GPIO 16 +ldr r2, [r3] ; Load current config +bic r2, r2, #0x80 ; Clear OD (output disable) +orr r2, r2, #0x40 ; Set IE (input enable) +str r2, [r3] ; Store config + +; Set GPIO function to SIO +ldr r3, =0x40028084 ; IO bank control for GPIO 16 +movs r2, #5 ; FUNCSEL = SIO +str r2, [r3] ; Set function + +; Main loop +loop: + ; LED ON + movs r4, #0x10 ; GPIO 16 + movs r5, #0x01 ; High + mcrr p0, #4, r4, r5, c0 + + ; Delay + ldr r2, =0x17D7840 ; ~25 million iterations +delay1: + subs r2, r2, #1 + bne delay1 + + ; LED OFF + movs r4, #0x10 ; GPIO 16 + movs r5, #0x00 ; Low + mcrr p0, #4, r4, r5, c0 + + ; Delay + ldr r2, =0x17D7840 +delay2: + subs r2, r2, #1 + bne delay2 + + b loop ; Repeat forever +``` + +--- + +## Part 16: Summary and Review + +### What We Accomplished + +1. **Learned about variables** - How they're declared, initialized, and stored +2. **Understood memory sections** - `.data`, `.bss`, and `.rodata` +3. **Analyzed binaries in Ghidra** - Without debug symbols! +4. **Patched binaries** - Changed values directly in the binary +5. **Controlled GPIO** - Made LEDs blink +6. **Changed program behavior** - Different LED, different value + +### The Binary Patching Workflow + +``` ++-----------------------------------------------------------------+ +| 1. Import .bin file into Ghidra | +| - Set language to ARM Cortex | +| - Set base address to 0x10000000 | ++-----------------------------------------------------------------+ +| 2. Analyze and resolve functions | +| - Rename functions to meaningful names | +| - Fix function signatures | ++-----------------------------------------------------------------+ +| 3. Find the values/instructions to patch | +| - Look in the assembly listing | +| - Bytes window (pencil, C, edit byte, D) or Patch Inst. | ++-----------------------------------------------------------------+ +| 4. Export the patched binary | +| - File -> Export Program | +| - Format: Raw Bytes | ++-----------------------------------------------------------------+ +| 5. Convert to UF2 | +| - python uf2conv.py file.bin --base 0x10000000 | +| --family 0xe48bff59 --output hacked.uf2 | ++-----------------------------------------------------------------+ +| 6. Flash and verify | +| - Hold BOOTSEL, plug in, drag UF2 | +| - Check serial output and LED behavior | ++-----------------------------------------------------------------+ +``` + +### Key Memory Sections + +| Section | Location | Contains | Writable? | +| --------- | -------- | ------------------------------ | --------- | +| `.text` | Flash | Code | No | +| `.rodata` | Flash | Constants, strings | No | +| `.data` | RAM | Initialized globals | Yes | +| `.bss` | RAM | Uninitialized globals (zeroed) | Yes | + +### Important Ghidra Commands + +| Action | How To Do It | +| ----------------- | ------------------------------------- | +| Rename function | Right-click -> Edit Function Signature | +| Patch instruction | Bytes window (pencil, C, edit, D) or Patch Instruction | +| Export binary | File -> Export Program -> Raw Bytes | +| Go to address | Press 'G' and enter address | + +--- + +--- + +## Key Takeaways + +1. **Variables are just memory locations** - The compiler assigns them addresses in SRAM. + +2. **Compilers optimize aggressively** - Unused code and values may be removed entirely. + +3. **Uninitialized doesn't mean random** - Modern compilers zero out the `.bss` section. + +4. **Ghidra works without symbols** - You can analyze any binary, even stripped ones. + +5. **Binary patching is powerful** - You can change behavior without source code. + +6. **UF2 conversion is required** - The Pico 2 needs UF2 format, not raw binaries. + +7. **GPIO is just memory-mapped I/O** - Writing to specific addresses controls hardware. + +--- + +## Glossary + +| Term | Definition | +| ------------------ | --------------------------------------------------------------------- | +| **BSS** | Block Started by Symbol - section for uninitialized global variables | +| **Declaration** | Telling the compiler a variable's name and type | +| **Definition** | Allocating memory for a variable | +| **GPIO** | General Purpose Input/Output - controllable pins on a microcontroller | +| **Initialization** | Assigning an initial value to a variable | +| **Linker** | Tool that combines compiled code and assigns memory addresses | +| **Optimization** | Compiler removing or simplifying code for efficiency | +| **Patching** | Modifying bytes directly in a binary file | +| **rodata** | Read-only data section for constants and string literals | +| **SIO** | Single-cycle I/O - fast GPIO control block in RP2350 | +| **UF2** | USB Flashing Format - file format for Pico 2 firmware | +| **Variable** | A named storage location in memory | + +--- + +## Additional Resources + +### GPIO Coprocessor Reference + +The RP2350 GPIO coprocessor instructions: + +| Instruction | Description | +| -------------------------- | ---------------------------- | +| `mcrr p0, #4, Rt, Rt2, c0` | Set/clear GPIO output | +| `mcrr p0, #4, Rt, Rt2, c4` | Set/clear GPIO output enable | + +### RP2350 Memory Map Quick Reference + +| Address | Description | +| ------------ | ------------------------ | +| `0x10000000` | XIP Flash (code) | +| `0x20000000` | SRAM (data) | +| `0x40028000` | IO_BANK0 (GPIO control) | +| `0x40038000` | PADS_BANK0 (pad control) | +| `0xd0000000` | SIO (single-cycle I/O) | + +--- + +**Remember:** Every binary you encounter in the real world can be analyzed and understood using these same techniques. Practice makes perfect! + +Happy hacking! + + diff --git a/WEEK04/WEEK04.pdf b/WEEK04/WEEK04.pdf new file mode 100644 index 0000000..5d887c2 Binary files /dev/null and b/WEEK04/WEEK04.pdf differ diff --git a/WEEK04/WEEK04a.md b/WEEK04/WEEK04a.md new file mode 100644 index 0000000..4c697fe --- /dev/null +++ b/WEEK04/WEEK04a.md @@ -0,0 +1,1063 @@ +# Week 4a: Hardware-Aware Reverse Engineering with CMSIS-SVD: Live GDB and Ghidra Analysis of Stripped Binaries + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand the fundamental differences between an ELF binary and a raw `.bin` firmware dump. +- Flash and debug `CTF-01.bin` using OpenOCD and a hardware Debug Probe with explicit base addressing ($0\text{x}10000000$). +- Operate GDB without an executable or symbol table, using hardware breakpoints (`hb`) and address-based disassembly (`x/i`). +- Navigate the ARM Cortex-M Vector Table at $0\text{x}10000000$ to find the initial Stack Pointer ($0\text{x}20082000$) and Reset Vector ($0\text{x}1000015B \rightarrow 0\text{x}1000015A$). +- Follow boot execution into `main()` at $0\text{x}100001E0$ without debug symbols. +- Identify the Memory-Mapped I/O (MMIO) peripheral blind spot in stripped binaries (UART0, IO_BANK0, PADS_BANK0, RESETS, SIO). +- Install and configure CMSIS-SVD (`rp2350.svd`) and `PyCortexMDebug` inside GDB for live dynamic peripheral inspection. +- Inspect UART0 baud rate and FIFO status registers, and verify GPIO 0/1 pin multiplexing live over SWD. +- Install and run `SVD-Loader-Ghidra` on `CTF-01.bin` to map peripheral memory blocks and auto-generate C struct definitions. +- Transform raw, obscure pointer decompilation into readable, vendor-grade peripheral struct accesses. +- Understand why arithmetic immediate instructions like `add.w r0, r0, #0x40000000` appear in the assembly listing while resolving cleanly in the decompiler. +- Execute a unified hardware-aware reverse engineering workflow combining static analysis in Ghidra and dynamic analysis in GDB to solve the CTF mission. + +--- + +## Part 1: The Raw Binary Dilemma (.elf vs .bin) + +### ELF Files: The Friendly Development Container + +In previous lessons, when debugging your firmware, you launched GDB pointing to an **Executable and Linkable Format (ELF)** file: + +```cmd +arm-none-eabi-gdb build\CTF-01.elf +``` + +An ELF file is not just machine code. It is a rich, structured container that contains: +1. **ELF Header**: Specifies the target architecture, endianness, and exact entry point address. +2. **Section Headers**: Defines memory segments such as `.text`, `.data`, `.rodata`, and `.bss`. +3. **Symbol Table**: Maps human-readable names (`main`, `grid_deviation`, `evaluate_grid`) to exact virtual memory addresses. +4. **DWARF Debug Information**: Links individual assembly instructions back to original C source file line numbers, variable types, and stack frame layouts. + +When GDB loads an ELF file, it knows the name of every function, the layout of every struct, and the location of `main`. + +### Raw .bin Files: The Harsh Reality of Firmware Extraction + +In real-world hardware reverse engineering, red teaming, and firmware extraction (such as reading an external SPI flash chip or intercepting an over-the-air firmware update), you will almost never have access to an ELF file. + +Instead, you are handed a **raw binary file (`.bin`)**: + +``` ++-----------------------------------------------------------------+ +| Comparison: ELF Container vs. Raw .bin Firmware | +| | +| CTF-01.elf (Development Build) | +| +-----------------------------------------------------------+ | +| | ELF Header (Entry Point: 0x1000015b) | | +| | Symbol Table (main -> 0x100001e0, evaluate_grid -> ...) | | +| | DWARF Debug Data (C Source Line Mapping) | | +| | Section Table (.text, .rodata, .data, .bss) | | +| | Machine Code Payload (15,920 bytes) | | +| +-----------------------------------------------------------+ | +| | +| CTF-01.bin (Field Recovery Image) | +| +-----------------------------------------------------------+ | +| | [Flat Machine Code Bytes Only - No Headers, No Symbols] | | +| | 00 20 08 20 5b 01 00 10 1b 01 00 10 1d 01 00 10 ... | | +| +-----------------------------------------------------------+ | ++-----------------------------------------------------------------+ +``` + +A `.bin` file is a byte-for-byte memory dump of flash memory. It contains: +- **No ELF header** +- **No section names** +- **No symbol names** +- **No debug information** +- **No base address metadata** (the file itself does not record where in memory it belongs) + +If you attempt to launch GDB with `0x0001b_ctf/CTF-01.bin` directly: + +```powershell +arm-none-eabi-gdb 0x0001b_ctf\CTF-01.bin +``` + +GDB immediately halts with an error: + +```text +"0x0001b_ctf/CTF-01.bin": not in executable format: file format not recognized +``` + +### The Hardware MMIO Blind Spot + +Stripped binaries introduce a second, even larger obstacle: **hardware peripherals**. + +Microcontrollers interact with the outside world using **Memory-Mapped Input/Output (MMIO)**. Peripherals like UART, GPIO, Clocks, and Resets do not have special CPU instructions. Instead, they are mapped to specific, fixed physical addresses in the microcontroller's memory map: + +| Subsystem | RP2350 Physical Address Base | Function | +| :--- | :--- | :--- | +| `RESETS` | `0x40020000` | Subsystem reset controller (releases UART and GPIO from reset) | +| `IO_BANK0` | `0x40028000` | GPIO pin function select (`FUNCSEL`) and overrides | +| `PADS_BANK0` | `0x40038000` | Electrical pad controls (drive strength, pulls, Schmitt) | +| `UART0` | `0x40070000` | Serial UART interface (115200 8N1 telemetry console) | +| `SIO` | `0xd0000000` | Single-cycle I/O (fast CPU core check, GPIO controls) | + +When analyzing a raw binary, neither GDB nor Ghidra understands what `0x40070018` or `0x40028004` mean. To standard tools, they are just arbitrary hexadecimal numbers. Reverse engineers are left manually cross-referencing thousands of pages of microcontroller datasheets. + +In this tutorial, you will master the two industry-standard tools that eliminate this blind spot: +1. **PyCortexMDebug** for live, dynamic hardware awareness in **GDB**. +2. **SVD-Loader-Ghidra** for automatic struct mapping and clear decompilation in **Ghidra**. + +--- + +## Part 2: The Target Application: `0x0001b_ctf` (Operation Black Start) + +### Mission Briefing + +Our primary target is the emergency firmware build from **`0x0001b_ctf`** (**CTF-01: Operation Black Start**). + +In this scenario, a critical cyberattack severed the primary SCADA network coordinating regional power grid interconnections. An emergency firmware build was deployed to the **GRID-7** fleet of relay controllers to manage an automated black-start restoration. However, the rushed build contains two critical defects: +1. **Miscalibrated Safety Threshold**: The frozen grid frequency deviation latched at $0.87\text{ Hz}$ is evaluated against a corrupt threshold of $95$ ($0.95\text{ Hz}$) instead of the hard engineering safety limit of $60$ ($0.60\text{ Hz}$), causing the relay to report a false-safe `STABLE` status. +2. **Hardcoded False Status Line**: The operator console line falsely asserts `SIGNAL: NORMAL` regardless of actual channel health. + +The source code was overwritten during the crisis build process. The only surviving artifact is the compiled raw binary: **`CTF-01.bin`**. + +### The Source Code Behind the Binary + +Let's review the firmware architecture from `0x0001b_ctf/src/` to understand what machine code the compiler generated: + +#### `main.c` + +```c +#include "console.h" +#include "grid.h" +#include "pico/stdlib.h" + +int main(void) +{ + stdio_init_all(); + retain_dispatch_frame(); + evaluate_grid(); + print_boot_banner(); + while (true) { + print_status(); + sleep_ms(1000); + } + return 0; +} +``` + +#### `grid.c` + +```c +#include "grid.h" +#include + +// Frozen grid frequency deviation reading latched when comms were severed. +volatile uint32_t grid_deviation = 87; + +// Operator-facing classification of the frozen reading (drives GRID STATUS). +volatile uint32_t operator_state = 0; + +// Automated dispatch authorization decision (drives DISPATCH PATH). +volatile uint32_t dispatch_state = 0; + +// Quarantined black-start authorization frame, retained in flash, never sent. +static volatile const char dispatch_frame[] = + "WORLDGRID:BLACKSTART:GRID-7:WATER-3"; + +void retain_dispatch_frame(void) +{ + volatile char frame_marker = dispatch_frame[0]; + (void)frame_marker; +} + +void evaluate_grid(void) +{ + operator_state = (grid_deviation < SAFE_THRESHOLD) ? 1 : 0; + dispatch_state = (grid_deviation < SAFE_THRESHOLD) ? 1 : 0; +} +``` + +#### `console.c` + +```c +#include "console.h" +#include "grid.h" +#include + +void print_boot_banner(void) +{ + printf("GLOBAL EMBEDDED RESPONSE NETWORK\r\n"); + printf("BLACK START WINDOW: 27 MINUTES\r\n"); + printf("UART0 115200 8N1 | AUTHORIZED LAB CONSOLE\r\n"); + printf("SIGNAL: NORMAL\r\n"); + printf("RESPONSE> "); +} + +void print_status(void) +{ + printf("GRID STATUS: %s\r\n", operator_state ? "STABLE" : "CRITICAL"); + printf("DISPATCH PATH: %s\r\n", dispatch_state ? "AUTHORIZED" : "HELD"); + printf("LAST FRAME: QUARANTINED\r\n"); + printf("RESPONSE> "); +} +``` + +### Hardware Actions Performed by This Code + +1. **`stdio_init_all()`**: + - Releases the UART0, IO_BANK0, and PADS_BANK0 peripherals from reset via `RESETS` (`0x40020000`). + - Configures `GPIO0` (TX) and `GPIO1` (RX) pin multiplexing to function select `2` (UART0) in `IO_BANK0` (`0x40028000`). + - Configures pad electrical properties in `PADS_BANK0` (`0x40038000`). + - Programs baud rate divisors (`UARTIBRD`, `UARTFBRD`) and line controls (`UARTLCR_H`) in `UART0` (`0x40070000`) for 115200 baud, 8 data bits, no parity, 1 stop bit (8N1). +2. **`retain_dispatch_frame()`**: + - Anchors the secret authorization token string `"WORLDGRID:BLACKSTART:GRID-7:WATER-3"` at physical flash address $0\text{x}100037A0$. +3. **`evaluate_grid()`**: + - Compares the global `grid_deviation` variable ($87$) against `SAFE_THRESHOLD` (compiled as `cmp r3, #94`). +4. **`print_boot_banner()` & `print_status()`**: + - Streams formatted strings through the UART0 Transmit FIFO buffer (`UART0_UARTDR`). + +In your workspace, this challenge is located in `0x0001b_ctf/`: +- `0x0001b_ctf/CTF-01.bin` (Raw 15,920-byte stripped firmware) +- `0x0001b_ctf/CTF-01.uf2` (Packaged UF2 image) + +For the remainder of this lesson, we assume you **only have `0x0001b_ctf/CTF-01.bin`**. + +--- + +## Part 3: Flashing and Connecting OpenOCD with Raw Binaries + +### Flashing a Raw Binary via OpenOCD + +When flashing an `.elf` file, OpenOCD reads target memory addresses directly from the ELF program headers. However, because a `.bin` file contains no header information, you **must explicitly specify the physical base address** ($0\text{x}10000000$ for RP2350 XIP flash). + +Open a PowerShell terminal in your repository root: + +```powershell +& "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\openocd.exe" ` + -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" ` + -f interface/cmsis-dap.cfg ` + -f target/rp2350.cfg ` + -c "adapter speed 5000; program 0x0001b_ctf/CTF-01.bin 0x10000000 verify reset exit" +``` + +Notice the crucial parameter: `0x10000000`. This instructs OpenOCD to write the binary bytes starting at the exact beginning of external flash memory. + +```text +** Programming Started ** +[rp2350.dap.core0] target halted due to debug-request +wrote 16384 bytes from file 0x0001b_ctf/CTF-01.bin in 0.412s +** Programming Finished ** +** Verify Started ** +verified 15920 bytes in 0.082s +** Verified OK ** +** Resetting Target ** +shutdown command invoked +``` + +### Starting OpenOCD as a Live Debug Server + +To debug the running firmware interactively, launch OpenOCD without the `exit` command. Keep this terminal open: + +```powershell +& "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\openocd.exe" ` + -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" ` + -f interface/cmsis-dap.cfg ` + -f target/rp2350.cfg ` + -c "adapter speed 5000; init" +``` + +OpenOCD initializes the SWD hardware connection and listens for GDB connections on TCP port `3333`. + +```text +Info : Hardware thread awareness created +Info : Listening on port 3333 for gdb connections +``` + +--- + +## Part 4: Dynamic Analysis in GDB Without an ELF + +Because we are analyzing a raw binary, we do not pass a file name to GDB on startup. + +Open a second terminal window: + +```powershell +arm-none-eabi-gdb +``` + +### Step 1: Set Target Architecture and Connect + +Inside the GDB prompt, tell GDB what processor architecture to expect, connect over TCP to OpenOCD, and immediately halt the processor: + +```gdb +set architecture armv8-m.main +target extended-remote :3333 +monitor reset halt +``` + +```text +The target architecture is assumed to be armv8-m.main +Remote debugging using :3333 +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x1000015a msp: 0x20082000 +``` + +### Step 2: Decode the Hardware Vector Table + +How did the CPU know to halt at `0x1000015a`? + +On ARM Cortex-M processors, the first entries of flash memory ($0\text{x}10000000$) define the **Vector Table**: +- **Word 0 ($0\text{x}10000000$)**: Initial Main Stack Pointer (`msp`). +- **Word 1 ($0\text{x}10000004$)**: Reset Vector (address of the first instruction to run upon reboot). + +Let's inspect the first four 32-bit words of flash using GDB's examine command (`x/4wx`): + +```gdb +x/4wx 0x10000000 +``` + +```text +0x10000000: 0x20082000 0x1000015b 0x1000011b 0x1000011d +``` + +Let's analyze what these words reveal: + +``` ++-----------------------------------------------------------------+ +| RP2350 Cortex-M33 Vector Table Decoding | +| | +| Address Value Meaning | +| 0x10000000: 0x20082000 Initial MSP (Top of 512KB SRAM) | +| 0x10000004: 0x1000015b Reset Vector (Thumb Execution Bit 0) | +| Execution begins at: 0x1000015a | ++-----------------------------------------------------------------+ +``` + +> [!NOTE] +> The Reset Vector value is `0x1000015b`. In ARM architecture, bit 0 indicates Thumb instruction mode ($0\text{x}1000015A + 1$). The processor automatically clears bit 0 and begins executing Thumb instructions at address `0x1000015a`. + +### Step 3: Why Symbolic Commands Fail + +If you try to use symbolic commands, GDB cannot help you: + +```gdb +break main +disassemble main +``` + +```text +No symbol table is loaded. Use the "file" command. +``` + +There are no symbols! To reverse engineer this firmware dynamically, we must navigate using **instruction addresses**. + +### Step 4: Disassemble by Address Range + +Disassemble 12 instructions starting at the Reset Handler address ($0\text{x}1000015A$): + +```gdb +x/12i 0x1000015a +``` + +```text +=> 0x1000015a: mov.w r0, #3489660928 ; 0xd0000000 (SIO base) + 0x1000015e: ldr r0, [r0, #0] ; SIO_CPUID (reads core id) + 0x10000160: cbz r0, 0x10000166 ; if Core 0, branch to init + 0x10000162: movs r0, #0 + 0x10000164: b.n 0x1000014e ; Core 1 sleeps + 0x10000166: add r4, pc, #52 ; loads init table pointer + 0x10000168: ldmia r4!, {r1, r2, r3} + 0x1000016a: cmp r1, #0 + 0x1000016c: beq.n 0x10000174 + 0x1000016e: bl 0x10000196 ; copy data section to SRAM + 0x10000172: b.n 0x10000168 + 0x10000174: ldr r1, [pc, #84] ; loads BSS bounds +``` + +Notice instruction `0x1000015a`: it immediately reads SIO register `0xd0000000` (`CPUID`) to check whether execution is occurring on Core 0 or Core 1! + +Now look further down the boot sequence at address `0x10000186`: + +```gdb +x/6i 0x10000184 +``` + +```text + 0x10000184: blx r1 + 0x10000186: ldr r1, [pc, #80] ; loads address from 0x100001d8 + 0x10000188: blx r1 ; calls main()! + 0x1000018a: ldr r1, [pc, #80] + 0x1000018c: blx r1 + 0x1000018e: bkpt 0x0000 +``` + +Inspect the pointer stored at `0x100001d8`: + +```gdb +x/wx 0x100001d8 +``` + +```text +0x100001d8: 0x100001e1 +``` + +Value `0x100001e1` is Thumb address $0\text{x}100001E0 + 1$. This reveals that **`main()` is located at address `0x100001e0`**! + +### Step 5: Setting Hardware Breakpoints on Flash Memory + +In RAM, GDB can set software breakpoints by temporarily replacing instructions with a breakpoint opcode (`bkpt`). However, external XIP flash ($0\text{x}10000000 - 0\text{x}1FFFFFFF$) is **read-only**. GDB cannot write to flash memory while the processor is running. + +Therefore, you must use **hardware breakpoints** (`hb`): + +```gdb +hb *0x100001e0 +continue +``` + +```text +Hardware assisted breakpoint 1 at 0x100001e0 +Continuing. + +Breakpoint 1, 0x100001e0 in ?? () +``` + +We are now stopped at the entry point of `main()` inside a completely stripped binary! + +Disassemble the instructions in `main()` from `0x100001e0` to `0x10000216`: + +```gdb +disassemble 0x100001e0, 0x10000216 +``` + +```text +Dump of assembler code from 0x100001e0 to 0x10000216: +=> 0x100001e0: push {r7, lr} + 0x100001e2: sub sp, #8 + 0x100001e4: bl 0x1000308c ; stdio_init_all() + 0x100001e8: ldr r3, [pc, #124] ; [0x10000268] -> 0x100037a0 (dispatch_frame) + 0x100001ea: ldr r2, [pc, #128] ; [0x1000026c] -> 0x200005d8 (grid_deviation) + 0x100001ec: ldrb r3, [r3, #0] ; retain_dispatch_frame(): reads dispatch_frame[0] ('W') + 0x100001ee: ldr r6, [pc, #128] ; [0x10000270] -> 0x20000844 (operator_state) + 0x100001f0: strb.w r3, [sp, #7] ; store frame_marker + 0x100001f4: ldrb.w r3, [sp, #7] ; reload frame_marker (volatile) + 0x100001f8: ldr r3, [r2, #0] ; evaluate_grid(): read grid_deviation (87) + 0x100001fa: ldr r5, [pc, #120] ; [0x10000274] -> 0x20000834 (dispatch_state) + 0x100001fc: cmp r3, #94 ; compare site A: if grid_deviation <= 94 + 0x100001fe: ite hi + 0x10000200: movhi r3, #0 + 0x10000202: movls r3, #1 + 0x10000204: str r3, [r6, #0] ; operator_state = 1 (STABLE) + 0x10000206: ldr r3, [r2, #0] ; read grid_deviation again + 0x10000208: ldr r0, [pc, #108] ; string pointer + 0x1000020a: cmp r3, #94 ; compare site B: if grid_deviation <= 94 + 0x1000020c: ite hi + 0x1000020e: movhi r3, #0 + 0x10000210: movls r3, #1 + 0x10000212: str r3, [r5, #0] ; dispatch_state = 1 (AUTHORIZED) + 0x10000214: bl 0x1000311c ; puts("GLOBAL EMBEDDED RESPONSE NETWORK") +End of assembler dump. +``` + +Notice what reverse engineering revealed right before our eyes: +- `0x100001e4`: `bl 0x1000308c` initializes UART0 serial communications. +- `0x100001e8`: Loads pointer `0x100037a0`. Inspecting `x/s 0x100037a0` reveals the secret token `"WORLDGRID:BLACKSTART:GRID-7:WATER-3"`! +- `0x100001fc` & `0x1000020a`: Both threshold checks compare `r3` against `#94` (`0x5e`). Because `grid_deviation` is $87$, $87 \le 94$, so both `operator_state` and `dispatch_state` are incorrectly set to $1$! + +### Step 6: The MMIO Blindness in Action + +Now step past `0x100001e4` (`stdio_init_all`) using `nexti` or `stepi`. + +In standard GDB, if you want to inspect what happened to UART0, you are forced to type raw hex addresses: + +```gdb +x/wx 0x40070018 +``` + +```text +0x40070018: 0x00000090 +``` + +What does `0x90` mean? +- Is the Transmit FIFO empty? +- Is the Receive FIFO full? +- Is the UART transmitter currently busy? +- What baud rate divisor was written to `0x40070024`? + +Standard GDB has no way to tell you. Let's fix that right now. + +--- + +## Part 5: Installing and Configuring CMSIS-SVD in GDB (PyCortexMDebug) + +### What is CMSIS-SVD? + +**CMSIS-SVD (Common Microcontroller Software Interface Standard - System View Description)** is an open XML specification developed by ARM. Silicon vendors publish an `.svd` file for every chip they manufacture. + +An SVD file contains a complete, machine-readable description of: +- Every peripheral on the chip +- Its physical base address +- Every register and offset +- Every bitfield, bitmask, access permission, and human-readable description + +``` ++-----------------------------------------------------------------+ +| CMSIS-SVD Hierarchy Tree | +| | +| Device: RP2350 | +| +-- Peripheral: UART0 (Base: 0x40070000) | +| | +-- Register: UARTDR (Offset: 0x000) | +| | +-- Register: UARTFR (Offset: 0x018) | +| | +-- Register: UARTIBRD (Offset: 0x024) | +| | +-- Register: UARTLCR_H (Offset: 0x02c) | +| +-- Peripheral: IO_BANK0 (Base: 0x40028000) | +| | +-- Register: GPIO0_CTRL (Offset: 0x004) -> UART0 TX | +| | +-- Register: GPIO1_CTRL (Offset: 0x00c) -> UART0 RX | +| +-- Peripheral: PADS_BANK0 (Base: 0x40038000) | +| | +-- Register: GPIO0 (Offset: 0x004) | +| +-- Peripheral: SIO (Base: 0xd0000000) | +| +-- Register: CPUID (Offset: 0x000) | ++-----------------------------------------------------------------+ +``` + +### Step 1: Obtain `rp2350.svd` + +A pre-downloaded copy of `rp2350.svd` is included directly in your course repository under `WEEK04/rp2350.svd`. You can also download the latest version directly from the official open-source `cmsis-svd-data` repository. + +Open a PowerShell terminal and create a dedicated `svd` directory in your user profile: + +```powershell +New-Item -ItemType Directory -Force -Path "$env:USERPROFILE\.svd" + +# Option A: Copy from local course folder +Copy-Item "WEEK04\rp2350.svd" "$env:USERPROFILE\.svd\rp2350.svd" + +# Option B: Download directly from GitHub +Invoke-WebRequest ` + -Uri "https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/RaspberryPi/rp2350.svd" ` + -OutFile "$env:USERPROFILE\.svd\rp2350.svd" +``` + +Verify that the file is in place: + +```powershell +Get-Item "$env:USERPROFILE\.svd\rp2350.svd" +``` + +### Step 2: Install `PyCortexMDebug` + +`PyCortexMDebug` is an open-source Python extension for GDB created by Bill Nahill. It parses SVD XML files and exposes high-level peripheral inspection commands inside your GDB session. + +Clone the repository into your user profile: + +```powershell +cd "$env:USERPROFILE" +git clone https://github.com/bnahill/PyCortexMDebug.git +``` + +### Step 3: Load PyCortexMDebug in GDB + +In your active GDB session, load the Python script and parse `rp2350.svd`: + +```gdb +source ~/PyCortexMDebug/scripts/gdb.py +svd_load ~/.svd/rp2350.svd +``` + +```text +Loading SVD file /Users/username/.svd/rp2350.svd... +Loaded 52 peripherals +``` + +Just like that, GDB now understands every single register, offset, and bitfield on the RP2350 microcontroller! + +> [!TIP] +> You can automate this process so SVD support is always active. Add the following lines to your `~/.gdbinit` file: +> ```gdb +> source ~/PyCortexMDebug/scripts/gdb.py +> svd_load ~/.svd/rp2350.svd +> ``` + +--- + +## Part 6: Live Dynamic Peripheral Inspection & Manipulation in GDB + +Now that GDB is hardware-aware, let's explore what we can do on our stripped `CTF-01.bin` firmware without touching source code. + +### Command 1: List All On-Chip Peripherals + +Type `svd` with no arguments to list all 52 peripherals on the RP2350: + +```gdb +svd +``` + +```text +Available Peripherals: + ACCESSCTRL ADC BUSCTRL CLOCKS + DMA GLITCH_DETECTOR I2C0 I2C1 + IO_BANK0 IO_QSPI OTP PADS_BANK0 + PADS_QSPI PIX_RP2040 PIO0 PIO1 + PIO2 PLL_SYS PLL_USB POWMAN + PWM QMI RESETS ROSC + SHA256 SIO SPI0 SPI1 + SYSINFO SYSCFG TBMAN TICKS + TIMER0 TIMER1 TRNG UART0 + UART1 USB VREG_AND_CHIP_RESET WATCHDOG + XIP_AUX XIP_CTRL XIP_QMI XOSC +``` + +### Command 2: Inspect a Peripheral Live (`svd UART0`) + +Inspect the **UART0** peripheral. GDB automatically reads the physical hardware registers across SWD and displays their live state: + +```gdb +svd UART0 +``` + +```text +UART0 @ 0x40070000: + UARTDR : 0x00000000 + UARTRSR : 0x00000000 + UARTFR : 0x00000090 + UARTILPR : 0x00000000 + UARTIBRD : 0x00000043 + UARTFBRD : 0x00000035 + UARTLCR_H : 0x00000070 + UARTCR : 0x00000301 + UARTIFLS : 0x00000012 + UARTIMSC : 0x00000000 + UARTRIS : 0x00000000 + UARTMIS : 0x00000000 + UARTICR : 0x00000000 + UARTDMACR : 0x00000003 +``` + +Look at what this dump proves: +- `UARTIBRD` ($0\text{x}43 = 67$) and `UARTFBRD` ($0\text{x}35 = 53$): These are the exact integer and fractional divisors for $115200\text{ baud}$ with a $125\text{ MHz}$ reference clock! +- `UARTLCR_H = 0x00000070`: Bits 6:5 are `11` ($8\text{ data bits}$) and bit 4 is `1` (FIFOs enabled). +- `UARTCR = 0x00000301`: Bit 0 is `UARTEN` ($1$), Bit 8 is `TXE` (Transmit Enable), Bit 9 is `RXE` (Receive Enable). + +### Command 3: Decode Bitfields (`svd /r UART0 UARTFR`) + +Remember the mysterious `0x00000090` we saw when reading `0x40070018`? Let's use the `/r` (raw/register decode) flag to decode it: + +```gdb +svd /r UART0 UARTFR +``` + +```text +UART0.UARTFR @ 0x40070018: 0x00000090 + [7] TXFE : 1 (Transmit FIFO empty) + [6] RXFF : 0 (Receive FIFO full) + [5] TXFF : 0 (Transmit FIFO full) + [4] RXFE : 1 (Receive FIFO empty) + [3] BUSY : 0 (UART busy transmitting) + [2] DCD : 0 (Data carrier detect) + [1] DSR : 0 (Data set ready) + [0] CTS : 0 (Clear to send) +``` + +In a single command, GDB completely decoded the raw hardware byte into human-readable FIFO and serial transmission states! + +Now inspect the pin multiplexer for `GPIO0`: + +```gdb +svd /r IO_BANK0 GPIO0_CTRL +``` + +```text +IO_BANK0.GPIO0_CTRL @ 0x40028004: 0x00000002 + [4:0] FUNCSEL : 2 (Function 2: UART0 TX) +``` + +This verifies that `GPIO0` has been successfully multiplexed to function as the hardware `UART0 TX` pin. + +### Command 4: Live Hardware Manipulation via SWD (`svd /w`) + +You can also **write** to registers by name using `svd /w`. + +While the processor is halted in GDB, look at your physical Pico 2 hardware board. Let's toggle the LED or write to a register directly: + +```gdb +svd /w SIO GPIO_OUT_SET 0x00010000 +``` + +You have full, symbolic, hardware-level control over a running target directly through GDB without having an ELF file or compiling a single line of code. + +--- + +## Part 7: Transitioning to Static Analysis in Ghidra + +Dynamic analysis in GDB lets us verify hardware state while stepping through execution. However, to understand the overall architecture, algorithms, and logic of a stripped firmware binary, we must perform **static analysis in Ghidra**. + +### Step 1: Import the Stripped Binary into Ghidra + +1. Launch Ghidra: `ghidraRun` +2. Create a new project named `CTF-01` +3. Drag and drop `0x0001b_ctf/CTF-01.bin` into the Active Project window. +4. In the Import dialog: + - **Language**: Click `...`, search for `Cortex`, and select **ARM:LE:32:Cortex (default)**. + - Click **Options...**: + - Change **Block Name** to `.text` + - Change **Base Address** to `10000000` (XIP Flash base) + - Click **OK**, then click **OK** to complete the import. +5. Double-click the file to open the CodeBrowser. +6. When prompted to analyze, click **Yes**, accept default analyzers, and click **Analyze**. + +### Step 2: The Decompiler Before SVD (The Pointer Maze) + +Navigate to `main` at address `0x100001E0` in the Ghidra decompiler. + +Before adding SVD support, the decompiler output looks like this: + +```c +void FUN_100001e0(void) +{ + byte extraout_DL; + + FUN_1000308c(); + FUN_1000311c(DAT_10000278); + FUN_1000311c(DAT_1000027c); + FUN_1000311c(DAT_10000280); + FUN_1000311c(DAT_10000284); + FUN_10003218(DAT_10000288); + do { + FUN_10003218(DAT_10000294,extraout_DL); + FUN_10003218(DAT_100002a0,extraout_DL); + FUN_1000311c(DAT_100002a4); + FUN_10003218(DAT_10000288); + FUN_10000cc4(1000); + } while( true ); +} +``` + +Now navigate to subroutine `FUN_100002a8` (`gpio_set_function`): + +```c +void FUN_100002a8(uint param_1, uint param_2) +{ + *(uint *)(0x40038000 + param_1 * 4 + 4) = + *(uint *)(0x40038000 + param_1 * 4 + 4) & 0xffffff7f | 0x40; + *(uint *)(0x40028000 + param_1 * 8 + 4) = param_2; + return; +} +``` + +Look at that decompilation: +- `*(uint *)(0x40038000 + param_1 * 4 + 4)` +- `*(uint *)(0x40028000 + param_1 * 8 + 4) = param_2` + +Ghidra doesn't know that `0x40038000` is `PADS_BANK0`, nor that `0x40028000` is `IO_BANK0`. In fact, if you double-click `0x40038000`, Ghidra warns that the address is **unmapped** because the `.bin` import only created a memory block for flash ($0\text{x}10000000$). + +--- + +## Part 8: Installing and Running SVD-Loader in Ghidra + +### Step 1: Install SVD-Loader-Ghidra + +`SVD-Loader-Ghidra` is an open-source Ghidra script created by Leveldown Security. It parses CMSIS-SVD files and automatically reconstructs microcontroller memory maps and data structures inside Ghidra. + +Open a PowerShell terminal and clone the repository: + +```powershell +cd "$env:USERPROFILE" +git clone https://github.com/leveldown-security/SVD-Loader-Ghidra.git +``` + +> [!IMPORTANT] +> **Ghidra 11/12+ Runtime Compatibility Fix (`#@runtime Jython`):** +> Modern Ghidra versions default to `PyGhidra` (CPython 3) for `.py` scripts. If Ghidra was not launched via `pyghidraRun`, running `SVD-Loader.py` will fail with: +> `Unable to load script: SVD-Loader.py - detail: Ghidra was not started with PyGhidra. Python is not available` +> +> `SVD-Loader` was developed for Ghidra's built-in **Jython** interpreter. To instruct Ghidra to use the built-in Jython engine, ensure `#@runtime Jython` is present at the top of `SVD-Loader.py`: +> ```python +> # Load specified SVD and generate peripheral memory maps & structures. +> #@runtime Jython +> #@author Thomas Roth , Ryan Pavlik +> ``` +> *(You can add this line using any text editor, or in Ghidra by right-clicking `SVD-Loader.py` in the Script Manager and selecting **Edit with basic editor**).* + +### Step 2: Add the Script to Ghidra Script Manager + +1. In Ghidra's CodeBrowser, open the **Script Manager**: + - Go to menu **Window** -> **Script Manager** (or click the **Script Manager** toolbar icon). + +> [!NOTE] +> **Script Manager Toolbar Icons Explained:** +> - **New Script (White Paper Icon):** To create a new script from scratch directly in Ghidra, you click the **piece of white paper** ("Create New Script") icon on the toolbar. Ghidra then prompts you to choose the script type: **`PyGhidra`** (Python 3 in Ghidra 11+), **`Java`**, or **`Jython`** (Python 2.7). +> - **Manage Script Directories (Folder with List Icon):** Because `SVD-Loader` is an existing multi-file package that relies on the bundled `cmsis_svd` parser library, we do not need to create a blank script. Instead, we register its cloned directory. + +2. In the top-right toolbar of the Script Manager window, click the **Manage Script Directories** icon (looks like a small folder with a list). +3. In the "Ghidra Script Directories / Bundle Manager" window that appears, click the **Display file chooser to add bundles to list** icon (the green `+` / folder icon on the top right). +4. Browse to and select your cloned directory: + `C:\Users\\SVD-Loader-Ghidra` +5. Click **OK** / **Select**, then close the Script Directories window. + +*(Alternatively, you can copy both `SVD-Loader.py` and the `cmsis_svd` folder directly into your default `~/ghidra_scripts` or `C:\Users\\ghidra_scripts` directory, which Ghidra discovers automatically).* + +### Step 3: Run SVD-Loader + +1. In the Script Manager search filter box, type: `SVD` +2. Locate **`SVD-Loader.py`** in the list. +3. Check the checkbox in the **In Tool** column next to `SVD-Loader.py`. This binds `SVD-Loader` directly to your CodeBrowser toolbar and menu for convenient access! +4. Select `SVD-Loader.py` and click the green **Run Script** button in the top right (or double-click the script entry). +5. A file picker dialog opens: + - Navigate to: `C:\Users\\.svd\rp2350.svd` + - Click **Open**. + +``` ++-----------------------------------------------------------------+ +| What SVD-Loader Does Automatically in Ghidra | +| | +| 1. Memory Blocks: Creates mapped, volatile memory blocks for | +| UART0, IO_BANK0, PADS_BANK0, SIO, CLOCKS, and RESETS. | +| 2. Symbol Labels: Creates global symbol labels at the exact | +| address of every register (e.g., UART0_UARTFR). | +| 3. C Structs: Generates full peripheral data structures in | +| the Data Type Manager (e.g., struct UART0_Type). | ++-----------------------------------------------------------------+ +``` + +Check the Ghidra Console window at the bottom of the screen. You will see: + +```text +Loaded SVD: rp2350.svd +Created peripheral block: SIO at 0xd0000000 (size: 0x1000) +Created peripheral block: PADS_BANK0 at 0x40038000 (size: 0x1000) +Created peripheral block: IO_BANK0 at 0x40028000 (size: 0x1000) +Created peripheral block: UART0 at 0x40070000 (size: 0x1000) +... +Successfully imported all peripherals! +``` + +### Step 4: Re-Run Auto-Analysis to Propagate References + +When you initially imported `CTF-01.bin`, Ghidra performed auto-analysis against only the initial Flash block ($0\text{x}10000000$). Now that `SVD-Loader.py` has created all 52 on-chip peripheral memory blocks, re-run analysis so Ghidra evaluates references against the newly created regions: + +1. Click menu **Analysis** -> **Auto Analyze 'CTF-01.bin'...** (or press keyboard shortcut **`A`**). +2. Ensure **Reference**, **Subroutine References**, and **Constant Reference Analyzer** are enabled. +3. Click **Analyze**. + +--- + +## Part 9: Decompiler Transformation: Before and After + +Now that the SVD structures are loaded, let's examine subroutine `FUN_100002a8` (`gpio_set_function`) again. + +### Side-by-Side Decompilation Comparison + +``` ++-----------------------------------------------------------------+ +| Decompilation of gpio_set_function() | +| | +| BEFORE SVD-Loader: | +| void FUN_100002a8(uint param_1, uint param_2) | +| { | +| *(uint *)(0x40038000 + param_1 * 4 + 4) = | +| *(uint *)(0x40038000 + param_1 * 4 + 4) & 0xffffff7f | +| | 0x40; | +| *(uint *)(0x40028000 + param_1 * 8 + 4) = param_2; | +| return; | +| } | +| | +| AFTER SVD-Loader: | +| void gpio_set_function(uint gpio, uint fn) | +| { | +| PADS_BANK0->GPIO[gpio] = | +| (PADS_BANK0->GPIO[gpio] & ~PADS_BANK0_OD) | +| | PADS_BANK0_IE; | +| IO_BANK0->GPIO[gpio].CTRL = fn; /* 2 = UART0 */ | +| return; | +| } | ++-----------------------------------------------------------------+ +``` + +Look at the difference: +1. **`*(uint *)(0x40038000 + param_1 * 4 + 4)`** is recognized as indexing into `PADS_BANK0` electrical pad controls. +2. **`& 0xffffff7f | 0x40`** is clearly revealed as clearing the `OD` (Output Disable) bit and setting the `IE` (Input Enable) bit. +3. **`*(uint *)(0x40028000 + param_1 * 8 + 4) = param_2`** immediately resolves in Ghidra's decompiler to: + ```c + (&Peripherals::IO_BANK0.GPIO0_CTRL)[param_1 * 2] = param_2; + ``` + **Why `[param_1 * 2]`?** In RP2350's `IO_BANK0`, each GPIO pin has two 32-bit registers (8 bytes total): `GPIOx_STATUS` (offset $+0$) and `GPIOx_CTRL` (offset $+4$). Because `GPIO0_CTRL` is a pointer to a 4-byte `uint32_t`, indexing by `[param_1 * 2]` steps forward by $2 \times 4\text{ bytes} = 8\text{ bytes}$ per pin, landing directly on each pin's `CTRL` register to assign `param_2` ($2$ for `UART0`)! + +> [!NOTE] +> **Understanding Assembly Listing vs. Decompiler Resolution:** +> You may notice that in the raw disassembly Listing view, line `100002be` still appears as: +> ```assembly +> 100002be 00 f1 80 40 add.w r0, r0, #0x40000000 +> ``` +> Why does `#0x40000000` not resolve to a peripheral label here? +> - **Arithmetic Immediates vs. Memory Operands:** `add.w` is an ALU integer addition, not a load or store instruction. In assembly listings, immediate scalar constants remain literal numbers. +> - **Intermediate Math vs. Target Address:** $0\text{x}40000000$ is the APB/AHB bridge base. The actual peripheral register address ($0\text{x}40028004$ for `IO_BANK0_GPIO0_CTRL`) is calculated dynamically at runtime by adding the pin index offset ($gpio \times 8$), bridge base ($0\text{x}40000000$), peripheral offset ($0\text{x}28000$), and register offset ($+4$). +> - **Where Resolution Appears:** Ghidra resolves this in the **Decompiler window** via data-flow analysis, and in the Listing window as **XREF** annotations on the subsequent `str`/`ldr` instructions that dereference the calculated pointer. If you want `#0x40000000` to show a name in the Listing, right-click the number and select **Set Equate...** (press **`E`**) to label it `PERIPHERALS_BASE`. + +### Exploring Structs in the Data Type Manager + +In Ghidra's **Data Type Manager** panel (bottom-left): +1. Expand the tree node for `CTF-01.bin`. +2. Expand the `rp2350.svd` category. +3. Locate **`UART0_Type`**: + - Double-click `UART0_Type` to open Ghidra's Structure Editor. + - You can see every field, its byte offset, and its data type: + - `0x000`: `UARTDR` (`uint32_t`) + - `0x018`: `UARTFR` (`uint32_t`) + - `0x024`: `UARTIBRD` (`uint32_t`) + - `0x028`: `UARTFBRD` (`uint32_t`) + - `0x02c`: `UARTLCR_H` (`uint32_t`) + - `0x030`: `UARTCR` (`uint32_t`) + +You can apply these struct types to any pointer in Ghidra by right-clicking a variable in the decompiler and selecting **Retype Variable** -> `UART0_Type *`. + +--- + +## Part 10: The Complete Hardware-Aware Reverse Engineering Workflow + +By combining SVD in both GDB and Ghidra, you achieve a seamless reverse engineering loop: + +``` ++-----------------------------------------------------------------+ +| The Hardware-Aware Reverse Engineering Loop | +| | +| +-----------------------------------------------------------+ | +| | 1. GHIDRA (Static Analysis + rp2350.svd) | | +| | - Identifies functions, call graph, and MMIO | | +| | - Pinpoints exact register addresses to watch | | +| +-----------------------------------------------------------+ | +| | | +| v | +| +-----------------------------------------------------------+ | +| | 2. GDB + OpenOCD (Dynamic Analysis + rp2350.svd) | | +| | - Sets hardware breakpoint (hb *0x100001e0) | | +| | - Steps through instructions with si / ni | | +| | - Inspects peripheral bitfields live (svd /r) | | +| +-----------------------------------------------------------+ | +| | | +| v | +| +-----------------------------------------------------------+ | +| | 3. LIVE HARDWARE INTERACTION | | +| | - Validates UART console telemetry (115200 8N1) | | +| | - Proves binary patches on physical silicon | | +| +-----------------------------------------------------------+ | ++-----------------------------------------------------------------+ +``` + +### Applying the Loop to Solve CTF-01 + +1. **Locate Defects via Ghidra Static Analysis**: + - In `main()` ($0\text{x}100001E0$), identify Compare Site A at $0\text{x}100001FC$ (`cmp r3, #94`) and Compare Site B at $0\text{x}1000020A$ (`cmp r3, #94`). + - Notice that while $0.87\text{ Hz}$ is dangerously high, it passes because $87 \le 94$. + - To enforce the $0.60\text{ Hz}$ safety limit, $x < 60$ is equivalent to $x \le 59$. The comparison immediate must be patched from `0x5E` ($94$) to `0x3B` ($59$). +2. **Locate the Quarantined Flag in Flash**: + - Trace the pointer loaded at address $0\text{x}100001E8$ to address $0\text{x}100037A0$. + - Inspecting that memory reveals the token: `"WORLDGRID:BLACKSTART:GRID-7:WATER-3"`. +3. **Patch and Export in Ghidra**: + - Use the **Bytes Window** workflow to prevent ARM Thumb IT-block context conflicts: + 1. Open the Bytes window (**Window** -> **Bytes: CTF-01.bin**). + 2. In the Bytes window toolbar, click the **pencil icon** (**Toggle Edit Mode**). + 3. In the Listing window, click `0x100001FC` and press **`C`** (**Clear Code Bytes**). + 4. In the Bytes window at offset `100001fc`, click on byte `5E` and change it to **`3B`**. + 5. In the Listing window, click back on `0x100001FC` and press **`D`** (**Disassemble**). + 6. Repeat at `0x1000020A`: click `0x1000020A` in the Listing, press **`C`**, change `5E` to **`3B`** in the Bytes window, click back in the Listing, and press **`D`**. + - Export the patched binary as `CTF-01_fixed.bin` via **File** -> **Export Program** -> **Format**: **Raw Bytes**. +4. **Verify on Live Hardware via OpenOCD & GDB**: + - Flash the patched binary to the Pico 2. + - Attach your USB-UART adapter to GPIO 0 (TX) and GPIO 1 (RX) at 115200 baud. + - Observe the corrected, truthful telemetry: + ```text + GRID STATUS: CRITICAL + DISPATCH PATH: HELD + LAST FRAME: QUARANTINED + RESPONSE> + ``` + +--- + +## Part 11: Summary, Cheatsheets & Review + +### GDB Raw Binary Debugging Cheatsheet + +| Task | Command | Description | +| :--- | :--- | :--- | +| Set Architecture | `set architecture armv8-m.main` | Configures GDB for ARM Cortex-M33 cores. | +| Connect to OpenOCD | `target extended-remote :3333` | Connects to OpenOCD debug server. | +| Reset & Halt | `monitor reset halt` | Sends reset signal and halts CPU at vector table. | +| Read Vector Table | `x/4wx 0x10000000` | Displays Initial Stack Pointer and Reset Vector. | +| Disassemble at PC | `x/10i $pc` | Disassembles 10 instructions at current Program Counter. | +| Disassemble Range | `disassemble 0x100001e0, 0x10000216` | Disassembles instructions between two hex addresses. | +| Hardware Breakpoint| `hb *0x100001e0` | Sets hardware breakpoint on read-only flash memory. | +| Read Memory Word | `x/wx 0x40070018` | Reads one 32-bit hexadecimal word from memory. | +| Write Memory Word | `set *0xd0000014 = 0x10000` | Writes 32-bit value directly to memory address. | + +### PyCortexMDebug SVD Cheatsheet + +| Task | Command | Description | +| :--- | :--- | :--- | +| Load Plugin | `source ~/PyCortexMDebug/scripts/gdb.py` | Imports PyCortexMDebug into GDB Python engine. | +| Load SVD File | `svd_load ~/.svd/rp2350.svd` | Parses chip peripheral XML definition. | +| List Peripherals | `svd` | Lists all on-chip hardware peripheral blocks. | +| Dump Peripheral | `svd UART0` | Reads and displays all registers in a peripheral. | +| Decode Bitfields | `svd /r UART0 UARTFR` | Decodes individual bitfields and named flags. | +| Write Register | `svd /w SIO GPIO_OUT_SET 0x10000` | Writes to peripheral register by symbolic name. | + +### RP2350 Peripheral Memory Map Quick Reference + +| Peripheral | Base Address | Size | Primary Purpose | +| :--- | :--- | :--- | :--- | +| `XIP_FLASH` | `0x10000000` | Up to 16MB | External QSPI Flash execution memory | +| `SRAM` | `0x20000000` | 512KB | On-chip data memory (stack, heap, `.data`, `.bss`) | +| `RESETS` | `0x40020000` | 4KB | Subsystem reset controller | +| `IO_BANK0` | `0x40028000` | 4KB | GPIO pin function multiplexing (`FUNCSEL`) | +| `PADS_BANK0`| `0x40038000` | 4KB | Electrical drive strength, pulls, and enables | +| `UART0` | `0x40070000` | 4KB | Serial communication interface 0 (115200 8N1) | +| `UART1` | `0x40078000` | 4KB | Serial communication interface 1 | +| `SIO` | `0xd0000000` | 4KB | Single-cycle I/O fast GPIO controls | + +--- + +## Key Takeaways + +1. **A raw `.bin` is not an ELF**: It has no headers, no symbols, and no entry point metadata. You must supply the base address ($0\text{x}10000000$) when flashing and debug using explicit addresses. +2. **Flash requires hardware breakpoints**: External flash is read-only during execution. Always use `hb *address` instead of software breakpoints (`b`). +3. **The Vector Table tells all**: Even without symbols, `x/4wx 0x10000000` gives you the initial stack pointer and the reset vector within seconds. +4. **SVD bridges the hardware gap**: CMSIS-SVD turns raw hexadecimal registers into named peripherals, registers, and bitfields across both GDB and Ghidra. +5. **GDB handles live dynamic manipulation**: `PyCortexMDebug` lets you inspect peripheral registers live, decode bitfields with `svd /r`, and toggle pins directly over SWD using `svd /w`. +6. **Ghidra handles static comprehension**: `SVD-Loader-Ghidra` creates mapped memory blocks and C structs, converting raw pointer arithmetic into readable code. +7. **Arithmetic instructions remain arithmetic**: Instructions like `add.w r0, r0, #0x40000000` calculate base addresses across multiple steps; resolution appears in the decompiler and at the load/store instructions that dereference the address. + +--- + +## Glossary + +| Term | Definition | +| :--- | :--- | +| **CMSIS-SVD** | Cortex Microcontroller Software Interface Standard - System View Description; an XML format describing microcontroller hardware peripherals. | +| **DWARF** | Standardized debugging data format embedded in ELF binaries that maps machine code to source code lines and symbols. | +| **Hardware Breakpoint (`hb`)** | A breakpoint implemented using dedicated CPU comparator registers, required for debugging code in read-only flash memory. | +| **MMIO** | Memory-Mapped Input/Output; a hardware architecture where peripheral registers are mapped into the CPU's regular memory address space. | +| **MSP** | Main Stack Pointer; the primary ARM Cortex-M stack pointer register. | +| **OpenOCD** | Open On-Chip Debugger; a software bridge that connects GDB to physical hardware via a Debug Probe. | +| **PyCortexMDebug** | A GDB Python extension that parses SVD files to provide live peripheral inspection and register manipulation. | +| **Reset Vector** | The address stored at offset $0\text{x}00000004$ in the vector table that points to the first instruction executed upon CPU reset. | +| **SIO** | Single-Cycle I/O; a dedicated RP2350 hardware block providing zero-wait-state GPIO manipulation. | +| **SVD-Loader** | A Ghidra script that imports SVD files to create memory blocks, symbol labels, and C structs for decompilation. | +| **SWD** | Serial Wire Debug; a two-wire physical debug protocol (SWCLK, SWDIO) used to debug ARM microcontrollers. | +| **UART** | Universal Asynchronous Receiver-Transmitter; a physical hardware communication protocol used for serial data transfer. | +| **XIP** | eXecute In Place; running code directly from external flash memory without copying it to RAM first. | + +*** + +Happy Hacking! diff --git a/WEEK04/WEEK04a.pdf b/WEEK04/WEEK04a.pdf new file mode 100644 index 0000000..68d606b Binary files /dev/null and b/WEEK04/WEEK04a.pdf differ diff --git a/WEEK04/rp2350.svd b/WEEK04/rp2350.svd new file mode 100644 index 0000000..aa2c362 --- /dev/null +++ b/WEEK04/rp2350.svd @@ -0,0 +1,105849 @@ + + + + Raspberry Pi + RP2350 + RP + 0.1 + + Dual Cortex-M33 or Hazard3 processors at 150MHz + 520kB on-chip SRAM, in 10 independent banks + Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD + 8kB of one-time-programmable storage (OTP) + Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus + Additional 16MB flash/PSRAM accessible via optional second chip-select + On-chip switched-mode power supply to generate core voltage + Low-quiescent-current LDO mode can be enabled for sleep states + 2x on-chip PLLs for internal or external clock generation + GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) + Security features: + Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP + Protected OTP storage for optional boot decryption key + Global bus filtering based on Arm or RISC-V security/privilege levels + Peripherals, GPIOs and DMA channels individually assignable to security domains + Hardware mitigations for fault injection attacks + Hardware SHA-256 accelerator + Peripherals: + 2x UARTs + 2x SPI controllers + 2x I2C controllers + 24x PWM channels + USB 1.1 controller and PHY, with host and device support + 12x PIO state machines + 1x HSTX peripheral + + 32 + 32 + 0xffffffff + 0x00000000 + read-write + + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r1p0 + little + true + true + 8 + 4 + 1 + 1 + false + 52 + + 8 + + + RESETS + 0x40020000 + + 0 + 12 + registers + + + + RESET + 0x00000000 + 0x1fffffff + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x00000004 + 0x00000000 + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x00000008 + 0x00000000 + + + USBCTRL + [28:28] + read-only + + + UART1 + [27:27] + read-only + + + UART0 + [26:26] + read-only + + + TRNG + [25:25] + read-only + + + TIMER1 + [24:24] + read-only + + + TIMER0 + [23:23] + read-only + + + TBMAN + [22:22] + read-only + + + SYSINFO + [21:21] + read-only + + + SYSCFG + [20:20] + read-only + + + SPI1 + [19:19] + read-only + + + SPI0 + [18:18] + read-only + + + SHA256 + [17:17] + read-only + + + PWM + [16:16] + read-only + + + PLL_USB + [15:15] + read-only + + + PLL_SYS + [14:14] + read-only + + + PIO2 + [13:13] + read-only + + + PIO1 + [12:12] + read-only + + + PIO0 + [11:11] + read-only + + + PADS_QSPI + [10:10] + read-only + + + PADS_BANK0 + [9:9] + read-only + + + JTAG + [8:8] + read-only + + + IO_QSPI + [7:7] + read-only + + + IO_BANK0 + [6:6] + read-only + + + I2C1 + [5:5] + read-only + + + I2C0 + [4:4] + read-only + + + HSTX + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40018000 + + 0 + 16 + registers + + + + FRCE_ON + 0x00000000 + Force block out of reset (i.e. power it on) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + FRCE_OFF + 0x00000004 + Force into reset (i.e. power it off) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + WDSEL + 0x00000008 + Set to 1 if the watchdog should reset this + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + DONE + 0x0000000c + Is the subsystem ready? + 0x00000000 + + + PROC1 + [24:24] + read-only + + + PROC0 + [23:23] + read-only + + + ACCESSCTRL + [22:22] + read-only + + + SIO + [21:21] + read-only + + + XIP + [20:20] + read-only + + + SRAM9 + [19:19] + read-only + + + SRAM8 + [18:18] + read-only + + + SRAM7 + [17:17] + read-only + + + SRAM6 + [16:16] + read-only + + + SRAM5 + [15:15] + read-only + + + SRAM4 + [14:14] + read-only + + + SRAM3 + [13:13] + read-only + + + SRAM2 + [12:12] + read-only + + + SRAM1 + [11:11] + read-only + + + SRAM0 + [10:10] + read-only + + + BOOTRAM + [9:9] + read-only + + + ROM + [8:8] + read-only + + + BUSFABRIC + [7:7] + read-only + + + PSM_READY + [6:6] + read-only + + + CLOCKS + [5:5] + read-only + + + RESETS + [4:4] + read-only + + + XOSC + [3:3] + read-only + + + ROSC + [2:2] + read-only + + + OTP + [1:1] + read-only + + + PROC_COLD + [0:0] + read-only + + + + + + + CLOCKS + 0x40010000 + + 0 + 212 + registers + + + CLOCKS_IRQ + 30 + + + + CLK_GPOUT0_CTRL + 0x00000000 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT0_DIV + 0x00000004 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT0_SELECTED + 0x00000008 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT1_CTRL + 0x0000000c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT1_DIV + 0x00000010 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT1_SELECTED + 0x00000014 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT2_CTRL + 0x00000018 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT2_DIV + 0x0000001c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT2_SELECTED + 0x00000020 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT3_CTRL + 0x00000024 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT3_DIV + 0x00000028 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT3_SELECTED + 0x0000002c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_REF_CTRL + 0x00000030 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb_primary_ref_opcg + 3 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + lposc_clksrc + 3 + + + + + + + CLK_REF_DIV + 0x00000034 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [23:16] + read-write + + + + + CLK_REF_SELECTED + 0x00000038 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [3:0] + read-only + + + + + CLK_SYS_CTRL + 0x0000003c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x00000040 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_SYS_SELECTED + 0x00000044 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [1:0] + read-only + + + + + CLK_PERI_CTRL + 0x00000048 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x0000004c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_PERI_SELECTED + 0x00000050 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_HSTX_CTRL + 0x00000054 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + clksrc_gpin0 + 3 + + + clksrc_gpin1 + 4 + + + + + + + CLK_HSTX_DIV + 0x00000058 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_HSTX_SELECTED + 0x0000005c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_HSTX_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_USB_CTRL + 0x00000060 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x00000064 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_USB_SELECTED + 0x00000068 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_ADC_CTRL + 0x0000006c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x00000070 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_ADC_SELECTED + 0x00000074 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + DFTCLK_XOSC_CTRL + 0x00000078 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary + 1 + + + clksrc_gpin0 + 2 + + + + + + + DFTCLK_ROSC_CTRL + 0x0000007c + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_sys_primary_rosc + 1 + + + clksrc_gpin1 + 2 + + + + + + + DFTCLK_LPOSC_CTRL + 0x00000080 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary_lposc + 1 + + + clksrc_gpin1 + 2 + + + + + + + CLK_SYS_RESUS_CTRL + 0x00000084 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x00000088 + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + 0x0000008c + Reference clock frequency in kHz + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + 0x00000090 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + 0x00000094 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + 0x00000098 + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + 0x0000009c + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + 0x000000a0 + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_hstx + 13 + + + lposc_clksrc + 14 + + + otp_clk2fc + 15 + + + pll_usb_clksrc_primary_dft + 16 + + + + + + + FC0_STATUS + 0x000000a4 + Frequency counter status + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + 0x000000a8 + Result of frequency measurement, only valid when status_done=1 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + 0x000000ac + enable clock in wake mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + 0x000000b0 + enable clock in wake mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + SLEEP_EN0 + 0x000000b4 + enable clock in sleep mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + 0x000000b8 + enable clock in sleep mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + ENABLED0 + 0x000000bc + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_SIO + [31:31] + read-only + + + CLK_SYS_SHA256 + [30:30] + read-only + + + CLK_SYS_PSM + [29:29] + read-only + + + CLK_SYS_ROSC + [28:28] + read-only + + + CLK_SYS_ROM + [27:27] + read-only + + + CLK_SYS_RESETS + [26:26] + read-only + + + CLK_SYS_PWM + [25:25] + read-only + + + CLK_SYS_POWMAN + [24:24] + read-only + + + CLK_REF_POWMAN + [23:23] + read-only + + + CLK_SYS_PLL_USB + [22:22] + read-only + + + CLK_SYS_PLL_SYS + [21:21] + read-only + + + CLK_SYS_PIO2 + [20:20] + read-only + + + CLK_SYS_PIO1 + [19:19] + read-only + + + CLK_SYS_PIO0 + [18:18] + read-only + + + CLK_SYS_PADS + [17:17] + read-only + + + CLK_SYS_OTP + [16:16] + read-only + + + CLK_REF_OTP + [15:15] + read-only + + + CLK_SYS_JTAG + [14:14] + read-only + + + CLK_SYS_IO + [13:13] + read-only + + + CLK_SYS_I2C1 + [12:12] + read-only + + + CLK_SYS_I2C0 + [11:11] + read-only + + + CLK_SYS_HSTX + [10:10] + read-only + + + CLK_HSTX + [9:9] + read-only + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-only + + + CLK_SYS_DMA + [7:7] + read-only + + + CLK_SYS_BUSFABRIC + [6:6] + read-only + + + CLK_SYS_BUSCTRL + [5:5] + read-only + + + CLK_SYS_BOOTRAM + [4:4] + read-only + + + CLK_SYS_ADC + [3:3] + read-only + + + CLK_ADC + [2:2] + read-only + + + CLK_SYS_ACCESSCTRL + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + 0x000000c0 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_XOSC + [30:30] + read-only + + + CLK_SYS_XIP + [29:29] + read-only + + + CLK_SYS_WATCHDOG + [28:28] + read-only + + + CLK_USB + [27:27] + read-only + + + CLK_SYS_USBCTRL + [26:26] + read-only + + + CLK_SYS_UART1 + [25:25] + read-only + + + CLK_PERI_UART1 + [24:24] + read-only + + + CLK_SYS_UART0 + [23:23] + read-only + + + CLK_PERI_UART0 + [22:22] + read-only + + + CLK_SYS_TRNG + [21:21] + read-only + + + CLK_SYS_TIMER1 + [20:20] + read-only + + + CLK_SYS_TIMER0 + [19:19] + read-only + + + CLK_SYS_TICKS + [18:18] + read-only + + + CLK_REF_TICKS + [17:17] + read-only + + + CLK_SYS_TBMAN + [16:16] + read-only + + + CLK_SYS_SYSINFO + [15:15] + read-only + + + CLK_SYS_SYSCFG + [14:14] + read-only + + + CLK_SYS_SRAM9 + [13:13] + read-only + + + CLK_SYS_SRAM8 + [12:12] + read-only + + + CLK_SYS_SRAM7 + [11:11] + read-only + + + CLK_SYS_SRAM6 + [10:10] + read-only + + + CLK_SYS_SRAM5 + [9:9] + read-only + + + CLK_SYS_SRAM4 + [8:8] + read-only + + + CLK_SYS_SRAM3 + [7:7] + read-only + + + CLK_SYS_SRAM2 + [6:6] + read-only + + + CLK_SYS_SRAM1 + [5:5] + read-only + + + CLK_SYS_SRAM0 + [4:4] + read-only + + + CLK_SYS_SPI1 + [3:3] + read-only + + + CLK_PERI_SPI1 + [2:2] + read-only + + + CLK_SYS_SPI0 + [1:1] + read-only + + + CLK_PERI_SPI0 + [0:0] + read-only + + + + + INTR + 0x000000c4 + Raw Interrupts + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + 0x000000c8 + Interrupt Enable + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + 0x000000cc + Interrupt Force + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + 0x000000d0 + Interrupt status after masking & forcing + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + TICKS + 0x40108000 + + 0 + 72 + registers + + + + PROC0_CTRL + 0x00000000 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC0_CYCLES + 0x00000004 + 0x00000000 + + + PROC0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC0_COUNT + 0x00000008 + 0x00000000 + + + PROC0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + PROC1_CTRL + 0x0000000c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC1_CYCLES + 0x00000010 + 0x00000000 + + + PROC1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC1_COUNT + 0x00000014 + 0x00000000 + + + PROC1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER0_CTRL + 0x00000018 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER0_CYCLES + 0x0000001c + 0x00000000 + + + TIMER0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER0_COUNT + 0x00000020 + 0x00000000 + + + TIMER0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER1_CTRL + 0x00000024 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER1_CYCLES + 0x00000028 + 0x00000000 + + + TIMER1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER1_COUNT + 0x0000002c + 0x00000000 + + + TIMER1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + WATCHDOG_CTRL + 0x00000030 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + WATCHDOG_CYCLES + 0x00000034 + 0x00000000 + + + WATCHDOG_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + WATCHDOG_COUNT + 0x00000038 + 0x00000000 + + + WATCHDOG_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + RISCV_CTRL + 0x0000003c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + RISCV_CYCLES + 0x00000040 + 0x00000000 + + + RISCV_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + RISCV_COUNT + 0x00000044 + 0x00000000 + + + RISCV_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + + + PADS_BANK0 + 0x40038000 + + 0 + 204 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO0 + 0x00000004 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + 0x00000008 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + 0x0000000c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + 0x00000010 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + 0x00000014 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + 0x00000018 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + 0x0000001c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + 0x00000020 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + 0x00000024 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + 0x00000028 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + 0x0000002c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + 0x00000030 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + 0x00000034 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + 0x00000038 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + 0x0000003c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + 0x00000040 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + 0x00000044 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + 0x00000048 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + 0x0000004c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + 0x00000050 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + 0x00000054 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + 0x00000058 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + 0x0000005c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + 0x00000060 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + 0x00000064 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + 0x00000068 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + 0x0000006c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + 0x00000070 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + 0x00000074 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + 0x00000078 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO30 + 0x0000007c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO31 + 0x00000080 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO32 + 0x00000084 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO33 + 0x00000088 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO34 + 0x0000008c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO35 + 0x00000090 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO36 + 0x00000094 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO37 + 0x00000098 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO38 + 0x0000009c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO39 + 0x000000a0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO40 + 0x000000a4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO41 + 0x000000a8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO42 + 0x000000ac + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO43 + 0x000000b0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO44 + 0x000000b4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO45 + 0x000000b8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO46 + 0x000000bc + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO47 + 0x000000c0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0x000000c4 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0x000000c8 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40040000 + + 0 + 28 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO_QSPI_SCLK + 0x00000004 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x00000008 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0x0000000c + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x00000010 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x00000014 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x00000018 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40030000 + + 0 + 576 + registers + + + IO_IRQ_QSPI + 23 + + + IO_IRQ_QSPI_NS + 24 + + + + USBPHY_DP_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DP_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_56 + 5 + + + null + 31 + + + + + + + USBPHY_DM_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DM_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_57 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SCLK_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_58 + 5 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SS_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_ss_n_0 + 0 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_59 + 5 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD0_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_60 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD1_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_61 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD2_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_62 + 5 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD3_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_63 + 5 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE + 0x00000200 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE + 0x00000204 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE + 0x00000208 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE + 0x0000020c + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE + 0x00000210 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE + 0x00000214 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + INTR + 0x00000218 + Raw Interrupts + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + oneToClear + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + oneToClear + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + oneToClear + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + oneToClear + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + 0x0000021c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + 0x00000220 + Interrupt Force for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + 0x00000224 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + 0x00000228 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + 0x0000022c + Interrupt Force for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + 0x00000230 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + 0x00000234 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + 0x00000238 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + 0x0000023c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40028000 + + 0 + 800 + registers + + + IO_IRQ_BANK0 + 21 + + + IO_IRQ_BANK0_NS + 22 + + + + GPIO0_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO0_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + pio2_0 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO1_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO1_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + pio2_1 + 8 + + + coresight_traceclk + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO2_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO2_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + pio2_2 + 8 + + + coresight_tracedata_0 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO3_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO3_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + pio2_3 + 8 + + + coresight_tracedata_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO4_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO4_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + pio2_4 + 8 + + + coresight_tracedata_2 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO5_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO5_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + pio2_5 + 8 + + + coresight_tracedata_3 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO6_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO6_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + pio2_6 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO7_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO7_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + pio2_7 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO8_STATUS + 0x00000040 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO8_CTRL + 0x00000044 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + pio2_8 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO9_STATUS + 0x00000048 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO9_CTRL + 0x0000004c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + pio2_9 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO10_STATUS + 0x00000050 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO10_CTRL + 0x00000054 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + pio2_10 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO11_STATUS + 0x00000058 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO11_CTRL + 0x0000005c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + pio2_11 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO12_STATUS + 0x00000060 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO12_CTRL + 0x00000064 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_0 + 0 + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + pio2_12 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO13_STATUS + 0x00000068 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO13_CTRL + 0x0000006c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_1 + 0 + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + pio2_13 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO14_STATUS + 0x00000070 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO14_CTRL + 0x00000074 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_2 + 0 + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + pio2_14 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO15_STATUS + 0x00000078 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO15_CTRL + 0x0000007c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_3 + 0 + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + pio2_15 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO16_STATUS + 0x00000080 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO16_CTRL + 0x00000084 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_4 + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + pio2_16 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO17_STATUS + 0x00000088 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO17_CTRL + 0x0000008c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_5 + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + pio2_17 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO18_STATUS + 0x00000090 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO18_CTRL + 0x00000094 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_6 + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + pio2_18 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO19_STATUS + 0x00000098 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO19_CTRL + 0x0000009c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_7 + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + pio2_19 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO20_STATUS + 0x000000a0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO20_CTRL + 0x000000a4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + pio2_20 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO21_STATUS + 0x000000a8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO21_CTRL + 0x000000ac + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + pio2_21 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO22_STATUS + 0x000000b0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO22_CTRL + 0x000000b4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + pio2_22 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO23_STATUS + 0x000000b8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO23_CTRL + 0x000000bc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + pio2_23 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO24_STATUS + 0x000000c0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO24_CTRL + 0x000000c4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + pio2_24 + 8 + + + clocks_gpout_2 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO25_STATUS + 0x000000c8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO25_CTRL + 0x000000cc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + pio2_25 + 8 + + + clocks_gpout_3 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO26_STATUS + 0x000000d0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO26_CTRL + 0x000000d4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + pio2_26 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO27_STATUS + 0x000000d8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO27_CTRL + 0x000000dc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + pio2_27 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO28_STATUS + 0x000000e0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO28_CTRL + 0x000000e4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + pio2_28 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO29_STATUS + 0x000000e8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO29_CTRL + 0x000000ec + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + pio2_29 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO30_STATUS + 0x000000f0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO30_CTRL + 0x000000f4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_30 + 5 + + + pio0_30 + 6 + + + pio1_30 + 7 + + + pio2_30 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO31_STATUS + 0x000000f8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO31_CTRL + 0x000000fc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_31 + 5 + + + pio0_31 + 6 + + + pio1_31 + 7 + + + pio2_31 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO32_STATUS + 0x00000100 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO32_CTRL + 0x00000104 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_32 + 5 + + + pio0_32 + 6 + + + pio1_32 + 7 + + + pio2_32 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO33_STATUS + 0x00000108 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO33_CTRL + 0x0000010c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_33 + 5 + + + pio0_33 + 6 + + + pio1_33 + 7 + + + pio2_33 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO34_STATUS + 0x00000110 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO34_CTRL + 0x00000114 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_34 + 5 + + + pio0_34 + 6 + + + pio1_34 + 7 + + + pio2_34 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO35_STATUS + 0x00000118 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO35_CTRL + 0x0000011c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_35 + 5 + + + pio0_35 + 6 + + + pio1_35 + 7 + + + pio2_35 + 8 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO36_STATUS + 0x00000120 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO36_CTRL + 0x00000124 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_36 + 5 + + + pio0_36 + 6 + + + pio1_36 + 7 + + + pio2_36 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO37_STATUS + 0x00000128 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO37_CTRL + 0x0000012c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_37 + 5 + + + pio0_37 + 6 + + + pio1_37 + 7 + + + pio2_37 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO38_STATUS + 0x00000130 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO38_CTRL + 0x00000134 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_38 + 5 + + + pio0_38 + 6 + + + pio1_38 + 7 + + + pio2_38 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO39_STATUS + 0x00000138 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO39_CTRL + 0x0000013c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_39 + 5 + + + pio0_39 + 6 + + + pio1_39 + 7 + + + pio2_39 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO40_STATUS + 0x00000140 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO40_CTRL + 0x00000144 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_40 + 5 + + + pio0_40 + 6 + + + pio1_40 + 7 + + + pio2_40 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO41_STATUS + 0x00000148 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO41_CTRL + 0x0000014c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_41 + 5 + + + pio0_41 + 6 + + + pio1_41 + 7 + + + pio2_41 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO42_STATUS + 0x00000150 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO42_CTRL + 0x00000154 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_42 + 5 + + + pio0_42 + 6 + + + pio1_42 + 7 + + + pio2_42 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO43_STATUS + 0x00000158 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO43_CTRL + 0x0000015c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_43 + 5 + + + pio0_43 + 6 + + + pio1_43 + 7 + + + pio2_43 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO44_STATUS + 0x00000160 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO44_CTRL + 0x00000164 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_44 + 5 + + + pio0_44 + 6 + + + pio1_44 + 7 + + + pio2_44 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO45_STATUS + 0x00000168 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO45_CTRL + 0x0000016c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_45 + 5 + + + pio0_45 + 6 + + + pio1_45 + 7 + + + pio2_45 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO46_STATUS + 0x00000170 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO46_CTRL + 0x00000174 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_46 + 5 + + + pio0_46 + 6 + + + pio1_46 + 7 + + + pio2_46 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO47_STATUS + 0x00000178 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO47_CTRL + 0x0000017c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_47 + 5 + + + pio0_47 + 6 + + + pio1_47 + 7 + + + pio2_47 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE0 + 0x00000200 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_SECURE1 + 0x00000204 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE0 + 0x00000208 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE1 + 0x0000020c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE0 + 0x00000210 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE1 + 0x00000214 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE0 + 0x00000218 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE1 + 0x0000021c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE0 + 0x00000220 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE1 + 0x00000224 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + 0x00000228 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 + 0x0000022c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + INTR0 + 0x00000230 + Raw Interrupts + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + 0x00000234 + Raw Interrupts + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + 0x00000238 + Raw Interrupts + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + 0x0000023c + Raw Interrupts + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO31_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO30_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + INTR4 + 0x00000240 + Raw Interrupts + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO39_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO38_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO37_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO36_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO35_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO34_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO33_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO32_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + INTR5 + 0x00000244 + Raw Interrupts + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO47_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO46_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO45_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO44_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO43_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO42_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO41_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO40_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + 0x00000248 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + 0x0000024c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + 0x00000250 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + 0x00000254 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE4 + 0x00000258 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE5 + 0x0000025c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + 0x00000260 + Interrupt Force for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + 0x00000264 + Interrupt Force for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + 0x00000268 + Interrupt Force for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + 0x0000026c + Interrupt Force for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF4 + 0x00000270 + Interrupt Force for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF5 + 0x00000274 + Interrupt Force for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + 0x00000278 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + 0x0000027c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + 0x00000280 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + 0x00000284 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS4 + 0x00000288 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS5 + 0x0000028c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + 0x00000290 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + 0x00000294 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + 0x00000298 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + 0x0000029c + Interrupt Enable for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE4 + 0x000002a0 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE5 + 0x000002a4 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + 0x000002a8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + 0x000002ac + Interrupt Force for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + 0x000002b0 + Interrupt Force for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + 0x000002b4 + Interrupt Force for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF4 + 0x000002b8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF5 + 0x000002bc + Interrupt Force for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + 0x000002c0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + 0x000002c4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + 0x000002c8 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + 0x000002cc + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS4 + 0x000002d0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS5 + 0x000002d4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + 0x000002d8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + 0x000002dc + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + 0x000002e0 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + 0x000002e4 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE4 + 0x000002e8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE5 + 0x000002ec + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + 0x000002f0 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + 0x000002f4 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + 0x000002f8 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + 0x000002fc + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF4 + 0x00000300 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF5 + 0x00000304 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + 0x00000308 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + 0x0000030c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + 0x00000310 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + 0x00000314 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS4 + 0x00000318 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS5 + 0x0000031c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0 + 24 + registers + + + + CHIP_ID + 0x00000000 + JEDEC JEP-106 compliant chip identifier. + 0x00000001 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:1] + read-only + + + STOP_BIT + [0:0] + read-only + + + + + PACKAGE_SEL + 0x00000004 + 0x00000000 + + + PACKAGE_SEL + [0:0] + read-only + + + + + PLATFORM + 0x00000008 + Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + 0x00000000 + + + GATESIM + [4:4] + read-only + + + BATCHSIM + [3:3] + read-only + + + HDLSIM + [2:2] + read-only + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2350 + 0x00000014 + Git hash of the chip source. Used to identify chip version. + 0x00000000 + + + GITREF_RP2350 + [31:0] + read-only + + + + + + + SHA256 + SHA-256 hash function implementation + 0x400f8000 + + 0 + 40 + registers + + + + CSR + 0x00000000 + Control and status register + 0x00001206 + + + BSWAP + Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. + + This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. + + However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. + + This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. + [12:12] + read-write + + + DMA_SIZE + Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. + + The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + [9:8] + read-write + + + 8bit + 0 + + + 16bit + 1 + + + 32bit + 2 + + + + + ERR_WDATA_NOT_RDY + Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. + [4:4] + read-write + oneToClear + + + SUM_VLD + If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. + + Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. + [2:2] + read-only + + + WDATA_RDY + If 1, the SHA-256 core is ready to accept more data through the WDATA register. + + After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. + [1:1] + read-only + + + START + Write 1 to prepare the SHA-256 core for a new checksum. + + The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. + + START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. + [0:0] + write-only + + + + + WDATA + 0x00000004 + Write data register + 0x00000000 + + + WDATA + After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. + + Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. + + After this, WDATA_RDY will return high, and more data can be written (if any). + + This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. + [31:0] + write-only + + + + + SUM0 + 0x00000008 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM0 + [31:0] + read-only + + + + + SUM1 + 0x0000000c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM1 + [31:0] + read-only + + + + + SUM2 + 0x00000010 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM2 + [31:0] + read-only + + + + + SUM3 + 0x00000014 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM3 + [31:0] + read-only + + + + + SUM4 + 0x00000018 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM4 + [31:0] + read-only + + + + + SUM5 + 0x0000001c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM5 + [31:0] + read-only + + + + + SUM6 + 0x00000020 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM6 + [31:0] + read-only + + + + + SUM7 + 0x00000024 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM7 + [31:0] + read-only + + + + + + + HSTX_FIFO + FIFO status and write access for HSTX + 0x50600000 + + 0 + 8 + registers + + + + STAT + 0x00000000 + FIFO status + 0x00000000 + + + WOF + FIFO was written when full. Write 1 to clear. + [10:10] + read-write + oneToClear + + + EMPTY + [9:9] + read-only + + + FULL + [8:8] + read-only + + + LEVEL + [7:0] + read-only + + + + + FIFO + 0x00000004 + Write access to FIFO + 0x00000000 + + + FIFO + [31:0] + write-only + + + + + + + HSTX_CTRL + Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. + 0x400c0000 + + 0 + 44 + registers + + + + CSR + 0x00000000 + 0x10050600 + + + CLKDIV + Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. + + For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). + + A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. + [31:28] + read-write + + + CLKPHASE + Set the initial phase of the generated clock. + + A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: + + * The clock will be initially low + + * The first rising edge will be 0.5 clk_hstx cycles after asserting first data + + * The first falling edge will be 1.5 clk_hstx cycles after asserting first data + + This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. + + When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. + + Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. + [27:24] + read-write + + + N_SHIFTS + Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) + + A register value of 0 means shift 32 times. + [20:16] + read-write + + + SHIFT + How many bits to right-rotate the shift register by each cycle. + + The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. + [12:8] + read-write + + + COUPLED_SEL + Select which PIO to use for coupled mode operation. + [6:5] + read-write + + + COUPLED_MODE + Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. + + When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. + + The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. + + For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. + [4:4] + read-write + + + EXPAND_EN + Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. + + Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. + [1:1] + read-write + + + EN + When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + + When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. + + Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. + [0:0] + read-write + + + + + BIT0 + 0x00000004 + Data control register for output bit 0 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT1 + 0x00000008 + Data control register for output bit 1 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT2 + 0x0000000c + Data control register for output bit 2 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT3 + 0x00000010 + Data control register for output bit 3 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT4 + 0x00000014 + Data control register for output bit 4 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT5 + 0x00000018 + Data control register for output bit 5 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT6 + 0x0000001c + Data control register for output bit 6 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT7 + 0x00000020 + Data control register for output bit 7 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + EXPAND_SHIFT + 0x00000024 + Configure the optional shifter inside the command expander + 0x01000100 + + + ENC_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. + [28:24] + read-write + + + ENC_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). + [20:16] + read-write + + + RAW_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. + [12:8] + read-write + + + RAW_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. + [4:0] + read-write + + + + + EXPAND_TMDS + 0x00000028 + Configure the optional TMDS encoder inside the command expander + 0x00000000 + + + L2_NBITS + Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [23:21] + read-write + + + L2_ROT + Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. + [20:16] + read-write + + + L1_NBITS + Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [15:13] + read-write + + + L1_ROT + Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. + [12:8] + read-write + + + L0_NBITS + Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [7:5] + read-write + + + L0_ROT + Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. + [4:0] + read-write + + + + + + + EPPB + Cortex-M33 EPPB vendor register block for RP2350 + 0xe0080000 + + 0 + 12 + registers + + + + NMI_MASK0 + 0x00000000 + NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK0 + [31:0] + read-write + + + + + NMI_MASK1 + 0x00000004 + NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK1 + [19:0] + read-write + + + + + SLEEPCTRL + 0x00000008 + Nonstandard sleep control register + 0x00000002 + + + WICENACK + Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. + [2:2] + read-only + + + WICENREQ + Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. + [1:1] + read-write + + + LIGHT_SLEEP + By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. + + Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. + [0:0] + read-write + + + + + + + PPB + TEAL registers accessible through the debug interface + 0xe0000000 + + 0 + 274432 + registers + + + + ITM_STIM0 + 0x00000000 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM1 + 0x00000004 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM2 + 0x00000008 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM3 + 0x0000000c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM4 + 0x00000010 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM5 + 0x00000014 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM6 + 0x00000018 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM7 + 0x0000001c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM8 + 0x00000020 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM9 + 0x00000024 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM10 + 0x00000028 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM11 + 0x0000002c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM12 + 0x00000030 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM13 + 0x00000034 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM14 + 0x00000038 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM15 + 0x0000003c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM16 + 0x00000040 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM17 + 0x00000044 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM18 + 0x00000048 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM19 + 0x0000004c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM20 + 0x00000050 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM21 + 0x00000054 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM22 + 0x00000058 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM23 + 0x0000005c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM24 + 0x00000060 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM25 + 0x00000064 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM26 + 0x00000068 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM27 + 0x0000006c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM28 + 0x00000070 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM29 + 0x00000074 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM30 + 0x00000078 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM31 + 0x0000007c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_TER0 + 0x00000e00 + Provide an individual enable bit for each ITM_STIM register + 0x00000000 + + + STIMENA + For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled + [31:0] + read-write + + + + + ITM_TPR + 0x00000e40 + Controls which stimulus ports can be accessed by unprivileged code + 0x00000000 + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports + [3:0] + read-write + + + + + ITM_TCR + 0x00000e80 + Configures and controls transfers through the ITM interface + 0x00000000 + + + BUSY + Indicates whether the ITM is currently processing events + [23:23] + read-only + + + TRACEBUSID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field + [22:16] + read-write + + + GTSFREQ + Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps + [11:10] + read-write + + + TSPRESCALE + Local timestamp prescaler, used with the trace packet reference clock + [9:8] + read-write + + + STALLENA + Stall the PE to guarantee delivery of Data Trace packets. + [5:5] + read-write + + + SWOENA + Enables asynchronous clocking of the timestamp counter + [4:4] + read-write + + + TXENA + Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU + [3:3] + read-write + + + SYNCENA + Enables Synchronization packet transmission for a synchronous TPIU + [2:2] + read-write + + + TSENA + Enables Local timestamp generation + [1:1] + read-write + + + ITMENA + Enables the ITM + [0:0] + read-write + + + + + INT_ATREADY + 0x00000ef0 + Integration Mode: Read ATB Ready + 0x00000000 + + + AFVALID + A read of this bit returns the value of AFVALID + [1:1] + read-only + + + ATREADY + A read of this bit returns the value of ATREADY + [0:0] + read-only + + + + + INT_ATVALID + 0x00000ef8 + Integration Mode: Write ATB Valid + 0x00000000 + + + AFREADY + A write to this bit gives the value of AFREADY + [1:1] + read-write + + + ATREADY + A write to this bit gives the value of ATVALID + [0:0] + read-write + + + + + ITM_ITCTRL + 0x00000f00 + Integration Mode Control Register + 0x00000000 + + + IME + Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. + [0:0] + read-write + + + + + ITM_DEVARCH + 0x00000fbc + Provides CoreSight discovery information for the ITM + 0x47701a01 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + ITM_DEVTYPE + 0x00000fcc + Provides CoreSight discovery information for the ITM + 0x00000043 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + ITM_PIDR4 + 0x00000fd0 + Provides CoreSight discovery information for the ITM + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR5 + 0x00000fd4 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR5 + [31:0] + read-write + + + + + ITM_PIDR6 + 0x00000fd8 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR6 + [31:0] + read-write + + + + + ITM_PIDR7 + 0x00000fdc + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR7 + [31:0] + read-write + + + + + ITM_PIDR0 + 0x00000fe0 + Provides CoreSight discovery information for the ITM + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_PIDR1 + 0x00000fe4 + Provides CoreSight discovery information for the ITM + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR2 + 0x00000fe8 + Provides CoreSight discovery information for the ITM + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + ITM_PIDR3 + 0x00000fec + Provides CoreSight discovery information for the ITM + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR0 + 0x00000ff0 + Provides CoreSight discovery information for the ITM + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR1 + 0x00000ff4 + Provides CoreSight discovery information for the ITM + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR2 + 0x00000ff8 + Provides CoreSight discovery information for the ITM + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR3 + 0x00000ffc + Provides CoreSight discovery information for the ITM + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CTRL + 0x00001000 + Provides configuration and status information for the DWT unit, and used to control features of the unit + 0x73741824 + + + NUMCOMP + Number of DWT comparators implemented + [31:28] + read-only + + + NOTRCPKT + Indicates whether the implementation does not support trace + [27:27] + read-only + + + NOEXTTRIG + Reserved, RAZ + [26:26] + read-only + + + NOCYCCNT + Indicates whether the implementation does not include a cycle counter + [25:25] + read-only + + + NOPRFCNT + Indicates whether the implementation does not include the profiling counters + [24:24] + read-only + + + CYCDISS + Controls whether the cycle counter is disabled in Secure state + [23:23] + read-write + + + CYCEVTENA + Enables Event Counter packet generation on POSTCNT underflow + [22:22] + read-write + + + FOLDEVTENA + Enables DWT_FOLDCNT counter + [21:21] + read-write + + + LSUEVTENA + Enables DWT_LSUCNT counter + [20:20] + read-write + + + SLEEPEVTENA + Enable DWT_SLEEPCNT counter + [19:19] + read-write + + + EXCEVTENA + Enables DWT_EXCCNT counter + [18:18] + read-write + + + CPIEVTENA + Enables DWT_CPICNT counter + [17:17] + read-write + + + EXTTRCENA + Enables generation of Exception Trace packets + [16:16] + read-write + + + PCSAMPLENA + Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation + [12:12] + read-write + + + SYNCTAP + Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate + [11:10] + read-write + + + CYCTAP + Selects the position of the POSTCNT tap on the CYCCNT counter + [9:9] + read-write + + + POSTINIT + Initial value for the POSTCNT counter + [8:5] + read-write + + + POSTPRESET + Reload value for the POSTCNT counter + [4:1] + read-write + + + CYCCNTENA + Enables CYCCNT + [0:0] + read-write + + + + + DWT_CYCCNT + 0x00001004 + Shows or sets the value of the processor cycle counter, CYCCNT + 0x00000000 + + + CYCCNT + Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero + [31:0] + read-write + + + + + DWT_EXCCNT + 0x0000100c + Counts the total cycles spent in exception processing + 0x00000000 + + + EXCCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_LSUCNT + 0x00001014 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + LSUCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_FOLDCNT + 0x00001018 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + FOLDCNT + Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one + [7:0] + read-write + + + + + DWT_COMP0 + 0x00001020 + Provides a reference value for use by watchpoint comparator 0 + 0x00000000 + + + DWT_COMP0 + [31:0] + read-write + + + + + DWT_FUNCTION0 + 0x00001028 + Controls the operation of watchpoint comparator 0 + 0x58000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP1 + 0x00001030 + Provides a reference value for use by watchpoint comparator 1 + 0x00000000 + + + DWT_COMP1 + [31:0] + read-write + + + + + DWT_FUNCTION1 + 0x00001038 + Controls the operation of watchpoint comparator 1 + 0x89000828 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP2 + 0x00001040 + Provides a reference value for use by watchpoint comparator 2 + 0x00000000 + + + DWT_COMP2 + [31:0] + read-write + + + + + DWT_FUNCTION2 + 0x00001048 + Controls the operation of watchpoint comparator 2 + 0x50000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP3 + 0x00001050 + Provides a reference value for use by watchpoint comparator 3 + 0x00000000 + + + DWT_COMP3 + [31:0] + read-write + + + + + DWT_FUNCTION3 + 0x00001058 + Controls the operation of watchpoint comparator 3 + 0x20000800 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_DEVARCH + 0x00001fbc + Provides CoreSight discovery information for the DWT + 0x47701a02 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DWT_DEVTYPE + 0x00001fcc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + DWT_PIDR4 + 0x00001fd0 + Provides CoreSight discovery information for the DWT + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR5 + 0x00001fd4 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR5 + [31:0] + read-write + + + + + DWT_PIDR6 + 0x00001fd8 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR6 + [31:0] + read-write + + + + + DWT_PIDR7 + 0x00001fdc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR7 + [31:0] + read-write + + + + + DWT_PIDR0 + 0x00001fe0 + Provides CoreSight discovery information for the DWT + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_PIDR1 + 0x00001fe4 + Provides CoreSight discovery information for the DWT + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR2 + 0x00001fe8 + Provides CoreSight discovery information for the DWT + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DWT_PIDR3 + 0x00001fec + Provides CoreSight discovery information for the DWT + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR0 + 0x00001ff0 + Provides CoreSight discovery information for the DWT + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR1 + 0x00001ff4 + Provides CoreSight discovery information for the DWT + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR2 + 0x00001ff8 + Provides CoreSight discovery information for the DWT + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR3 + 0x00001ffc + Provides CoreSight discovery information for the DWT + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CTRL + 0x00002000 + Provides FPB implementation information, and the global enable for the FPB unit + 0x60005580 + + + REV + Flash Patch and Breakpoint Unit architecture revision + [31:28] + read-only + + + NUM_CODE_14_12_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [14:12] + read-only + + + NUM_LIT + Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 + [11:8] + read-only + + + NUM_CODE_7_4_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [7:4] + read-only + + + KEY + Writes to the FP_CTRL are ignored unless KEY is concurrently written to one + [1:1] + read-write + + + ENABLE + Enables the FPB + [0:0] + read-write + + + + + FP_REMAP + 0x00002004 + Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + 0x00000000 + + + RMPSPT + Indicates whether the FPB unit supports the Flash Patch remap function + [29:29] + read-only + + + REMAP + Holds the bits[28:5] of the Flash Patch remap address + [28:5] + read-only + + + + + FP_COMP0 + 0x00002008 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP1 + 0x0000200c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP2 + 0x00002010 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP3 + 0x00002014 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP4 + 0x00002018 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP5 + 0x0000201c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP6 + 0x00002020 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP7 + 0x00002024 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_DEVARCH + 0x00002fbc + Provides CoreSight discovery information for the FPB + 0x47701a03 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + FP_DEVTYPE + 0x00002fcc + Provides CoreSight discovery information for the FPB + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + FP_PIDR4 + 0x00002fd0 + Provides CoreSight discovery information for the FP + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR5 + 0x00002fd4 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR5 + [31:0] + read-write + + + + + FP_PIDR6 + 0x00002fd8 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR6 + [31:0] + read-write + + + + + FP_PIDR7 + 0x00002fdc + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR7 + [31:0] + read-write + + + + + FP_PIDR0 + 0x00002fe0 + Provides CoreSight discovery information for the FP + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_PIDR1 + 0x00002fe4 + Provides CoreSight discovery information for the FP + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR2 + 0x00002fe8 + Provides CoreSight discovery information for the FP + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + FP_PIDR3 + 0x00002fec + Provides CoreSight discovery information for the FP + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR0 + 0x00002ff0 + Provides CoreSight discovery information for the FP + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR1 + 0x00002ff4 + Provides CoreSight discovery information for the FP + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR2 + 0x00002ff8 + Provides CoreSight discovery information for the FP + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR3 + 0x00002ffc + Provides CoreSight discovery information for the FP + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ICTR + 0x0000e004 + Provides information about the interrupt controller + 0x00000001 + + + INTLINESNUM + Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM + [3:0] + read-only + + + + + ACTLR + 0x0000e008 + Provides IMPLEMENTATION DEFINED configuration and control options + 0x00000000 + + + EXTEXCLALL + External Exclusives Allowed with no MPU + [29:29] + read-write + + + DISITMATBFLUSH + Disable ATB Flush + [12:12] + read-write + + + FPEXCODIS + Disable FPU exception outputs + [10:10] + read-write + + + DISOOFP + Disable out-of-order FP instruction completion + [9:9] + read-write + + + DISFOLD + Disable dual-issue. + [2:2] + read-write + + + DISMCYCINT + Disable dual-issue. + [0:0] + read-write + + + + + SYST_CSR + 0x0000e010 + Use the SysTick Control and Status Register to enable the SysTick features. + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + 0x0000e014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + 0x0000e018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + 0x0000e01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER0 + 0x0000e100 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISER1 + 0x0000e104 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER0 + 0x0000e180 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER1 + 0x0000e184 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISPR0 + 0x0000e200 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ISPR1 + 0x0000e204 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR0 + 0x0000e280 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR1 + 0x0000e284 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_IABR0 + 0x0000e300 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IABR1 + 0x0000e304 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS0 + 0x0000e380 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS1 + 0x0000e384 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IPR0 + 0x0000e400 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR1 + 0x0000e404 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR2 + 0x0000e408 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR3 + 0x0000e40c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR4 + 0x0000e410 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR5 + 0x0000e414 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR6 + 0x0000e418 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR7 + 0x0000e41c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR8 + 0x0000e420 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR9 + 0x0000e424 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR10 + 0x0000e428 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR11 + 0x0000e42c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR12 + 0x0000e430 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR13 + 0x0000e434 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR14 + 0x0000e438 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR15 + 0x0000e43c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + CPUID + 0x0000ed00 + Provides identification information for the PE, including an implementer code for the device and a device ID number + 0x411fd210 + + + IMPLEMENTER + This field must hold an implementer code that has been assigned by ARM + [31:24] + read-only + + + VARIANT + IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product + [23:20] + read-only + + + ARCHITECTURE + Defines the Architecture implemented by the PE + [19:16] + read-only + + + PARTNO + IMPLEMENTATION DEFINED primary part number for the device + [15:4] + read-only + + + REVISION + IMPLEMENTATION DEFINED revision number for the device + [3:0] + read-only + + + + + ICSR + 0x0000ed04 + Controls and provides status information for NMI, PendSV, SysTick and interrupts + 0x00000000 + + + PENDNMISET + Indicates whether the NMI exception is pending + [31:31] + read-only + + + PENDNMICLR + Allows the NMI exception pend state to be cleared + [30:30] + read-write + + + PENDSVSET + Indicates whether the PendSV `FTSSS exception is pending + [28:28] + read-only + + + PENDSVCLR + Allows the PendSV exception pend state to be cleared `FTSSS + [27:27] + read-write + + + PENDSTSET + Indicates whether the SysTick `FTSSS exception is pending + [26:26] + read-only + + + PENDSTCLR + Allows the SysTick exception pend state to be cleared `FTSSS + [25:25] + read-write + + + STTNS + Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure + [24:24] + read-write + + + ISRPREEMPT + Indicates whether a pending exception will be serviced on exit from debug halt state + [23:23] + read-only + + + ISRPENDING + Indicates whether an external interrupt, generated by the NVIC, is pending + [22:22] + read-only + + + VECTPENDING + The exception number of the highest priority pending and enabled interrupt + [20:12] + read-only + + + RETTOBASE + In Handler mode, indicates whether there is more than one active exception + [11:11] + read-only + + + VECTACTIVE + The exception number of the current executing exception + [8:0] + read-only + + + + + VTOR + 0x0000ed08 + The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + 0x00000000 + + + TBLOFF + Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. + [31:7] + read-write + + + + + AIRCR + 0x0000ed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are identical. + 1 Non-secure exceptions are de-prioritized. + [14:14] + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. + 0 BusFault, HardFault, and NMI are Secure. + 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + [13:13] + read-write + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + [10:8] + read-write + + + SYSRESETREQS + System reset request, Secure state only. + 0 SYSRESETREQ functionality is available to both Security states. + 1 SYSRESETREQ functionality is only available to Secure state. + [3:3] + read-write + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + 0x0000ed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEPS + 0 SLEEPDEEP is available to both security states + 1 SLEEPDEEP is only available to Secure state + [3:3] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + 0x0000ed14 + Sets or returns configuration and control data + 0x00000201 + + + BP + Enables program flow prediction `FTSSS + [18:18] + read-only + + + IC + This is a global enable bit for instruction caches in the selected Security state + [17:17] + read-only + + + DC + Enables data caching of all data accesses to Normal memory `FTSSS + [16:16] + read-only + + + STKOFHFNMIGN + Controls the effect of a stack limit violation while executing at a requested priority less than 0 + [10:10] + read-write + + + RES1 + Reserved, RES1 + [9:9] + read-only + + + BFHFNMIGN + Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 + [8:8] + read-write + + + DIV_0_TRP + Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero + [4:4] + read-write + + + UNALIGN_TRP + Controls the trapping of unaligned word or halfword accesses + [3:3] + read-write + + + USERSETMPEND + Determines whether unprivileged accesses are permitted to pend interrupts via the STIR + [1:1] + read-write + + + RES1_1 + Reserved, RES1 + [0:0] + read-only + + + + + SHPR1 + 0x0000ed18 + Sets or returns priority for system handlers 4 - 7 + 0x00000000 + + + PRI_7_3 + Priority of system handler 7, SecureFault + [31:29] + read-write + + + PRI_6_3 + Priority of system handler 6, SecureFault + [23:21] + read-write + + + PRI_5_3 + Priority of system handler 5, SecureFault + [15:13] + read-write + + + PRI_4_3 + Priority of system handler 4, SecureFault + [7:5] + read-write + + + + + SHPR2 + 0x0000ed1c + Sets or returns priority for system handlers 8 - 11 + 0x00000000 + + + PRI_11_3 + Priority of system handler 11, SecureFault + [31:29] + read-write + + + PRI_10 + Reserved, RES0 + [23:16] + read-only + + + PRI_9 + Reserved, RES0 + [15:8] + read-only + + + PRI_8 + Reserved, RES0 + [7:0] + read-only + + + + + SHPR3 + 0x0000ed20 + Sets or returns priority for system handlers 12 - 15 + 0x00000000 + + + PRI_15_3 + Priority of system handler 15, SecureFault + [31:29] + read-write + + + PRI_14_3 + Priority of system handler 14, SecureFault + [23:21] + read-write + + + PRI_13 + Reserved, RES0 + [15:8] + read-only + + + PRI_12_3 + Priority of system handler 12, SecureFault + [7:5] + read-write + + + + + SHCSR + 0x0000ed24 + Provides access to the active and pending status of system exceptions + 0x00000000 + + + HARDFAULTPENDED + `IAAMO the pending state of the HardFault exception `CTTSSS + [21:21] + read-write + + + SECUREFAULTPENDED + `IAAMO the pending state of the SecureFault exception + [20:20] + read-write + + + SECUREFAULTENA + `DW the SecureFault exception is enabled + [19:19] + read-write + + + USGFAULTENA + `DW the UsageFault exception is enabled `FTSSS + [18:18] + read-write + + + BUSFAULTENA + `DW the BusFault exception is enabled + [17:17] + read-write + + + MEMFAULTENA + `DW the MemManage exception is enabled `FTSSS + [16:16] + read-write + + + SVCALLPENDED + `IAAMO the pending state of the SVCall exception `FTSSS + [15:15] + read-write + + + BUSFAULTPENDED + `IAAMO the pending state of the BusFault exception + [14:14] + read-write + + + MEMFAULTPENDED + `IAAMO the pending state of the MemManage exception `FTSSS + [13:13] + read-write + + + USGFAULTPENDED + The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS + [12:12] + read-write + + + SYSTICKACT + `IAAMO the active state of the SysTick exception `FTSSS + [11:11] + read-write + + + PENDSVACT + `IAAMO the active state of the PendSV exception `FTSSS + [10:10] + read-write + + + MONITORACT + `IAAMO the active state of the DebugMonitor exception + [8:8] + read-write + + + SVCALLACT + `IAAMO the active state of the SVCall exception `FTSSS + [7:7] + read-write + + + NMIACT + `IAAMO the active state of the NMI exception + [5:5] + read-write + + + SECUREFAULTACT + `IAAMO the active state of the SecureFault exception + [4:4] + read-write + + + USGFAULTACT + `IAAMO the active state of the UsageFault exception `FTSSS + [3:3] + read-write + + + HARDFAULTACT + Indicates and allows limited modification of the active state of the HardFault exception `FTSSS + [2:2] + read-write + + + BUSFAULTACT + `IAAMO the active state of the BusFault exception + [1:1] + read-write + + + MEMFAULTACT + `IAAMO the active state of the MemManage exception `FTSSS + [0:0] + read-write + + + + + CFSR + 0x0000ed28 + Contains the three Configurable Fault Status Registers. + + 31:16 UFSR: Provides information on UsageFault exceptions + + 15:8 BFSR: Provides information on BusFault exceptions + + 7:0 MMFSR: Provides information on MemManage exceptions + 0x00000000 + + + UFSR_DIVBYZERO + Sticky flag indicating whether an integer division by zero error has occurred + [25:25] + read-write + + + UFSR_UNALIGNED + Sticky flag indicating whether an unaligned access error has occurred + [24:24] + read-write + + + UFSR_STKOF + Sticky flag indicating whether a stack overflow error has occurred + [20:20] + read-write + + + UFSR_NOCP + Sticky flag indicating whether a coprocessor disabled or not present error has occurred + [19:19] + read-write + + + UFSR_INVPC + Sticky flag indicating whether an integrity check error has occurred + [18:18] + read-write + + + UFSR_INVSTATE + Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred + [17:17] + read-write + + + UFSR_UNDEFINSTR + Sticky flag indicating whether an undefined instruction error has occurred + [16:16] + read-write + + + BFSR_BFARVALID + Indicates validity of the contents of the BFAR register + [15:15] + read-write + + + BFSR_LSPERR + Records whether a BusFault occurred during FP lazy state preservation + [13:13] + read-write + + + BFSR_STKERR + Records whether a derived BusFault occurred during exception entry stacking + [12:12] + read-write + + + BFSR_UNSTKERR + Records whether a derived BusFault occurred during exception return unstacking + [11:11] + read-write + + + BFSR_IMPRECISERR + Records whether an imprecise data access error has occurred + [10:10] + read-write + + + BFSR_PRECISERR + Records whether a precise data access error has occurred + [9:9] + read-write + + + BFSR_IBUSERR + Records whether a BusFault on an instruction prefetch has occurred + [8:8] + read-write + + + MMFSR + Provides information on MemManage exceptions + [7:0] + read-write + + + + + HFSR + 0x0000ed2c + Shows the cause of any HardFaults + 0x00000000 + + + DEBUGEVT + Indicates when a Debug event has occurred + [31:31] + read-write + + + FORCED + Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled + [30:30] + read-write + + + VECTTBL + Indicates when a fault has occurred because of a vector table read error on exception processing + [1:1] + read-write + + + + + DFSR + 0x0000ed30 + Shows which debug event occurred + 0x00000000 + + + EXTERNAL + Sticky flag indicating whether an External debug request debug event has occurred + [4:4] + read-write + + + VCATCH + Sticky flag indicating whether a Vector catch debug event has occurred + [3:3] + read-write + + + DWTTRAP + Sticky flag indicating whether a Watchpoint debug event has occurred + [2:2] + read-write + + + BKPT + Sticky flag indicating whether a Breakpoint debug event has occurred + [1:1] + read-write + + + HALTED + Sticky flag indicating that a Halt request debug event or Step debug event has occurred + [0:0] + read-write + + + + + MMFAR + 0x0000ed34 + Shows the address of the memory location that caused an MPU fault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + BFAR + 0x0000ed38 + Shows the address associated with a precise data access BusFault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + ID_PFR0 + 0x0000ed40 + Gives top-level information about the instruction set supported by the PE + 0x00000030 + + + STATE1 + T32 instruction set support + [7:4] + read-only + + + STATE0 + A32 instruction set support + [3:0] + read-only + + + + + ID_PFR1 + 0x0000ed44 + Gives information about the programmers' model and Extensions support + 0x00000520 + + + MPROGMOD + Identifies support for the M-Profile programmers' model support + [11:8] + read-only + + + SECURITY + Identifies whether the Security Extension is implemented + [7:4] + read-only + + + + + ID_DFR0 + 0x0000ed48 + Provides top level information about the debug system + 0x00200000 + + + MPROFDBG + Indicates the supported M-profile debug architecture + [23:20] + read-only + + + + + ID_AFR0 + 0x0000ed4c + Provides information about the IMPLEMENTATION DEFINED features of the PE + 0x00000000 + + + IMPDEF3 + IMPLEMENTATION DEFINED meaning + [15:12] + read-only + + + IMPDEF2 + IMPLEMENTATION DEFINED meaning + [11:8] + read-only + + + IMPDEF1 + IMPLEMENTATION DEFINED meaning + [7:4] + read-only + + + IMPDEF0 + IMPLEMENTATION DEFINED meaning + [3:0] + read-only + + + + + ID_MMFR0 + 0x0000ed50 + Provides information about the implemented memory model and memory management support + 0x00101f40 + + + AUXREG + Indicates support for Auxiliary Control Registers + [23:20] + read-only + + + TCM + Indicates support for tightly coupled memories (TCMs) + [19:16] + read-only + + + SHARELVL + Indicates the number of shareability levels implemented + [15:12] + read-only + + + OUTERSHR + Indicates the outermost shareability domain implemented + [11:8] + read-only + + + PMSA + Indicates support for the protected memory system architecture (PMSA) + [7:4] + read-only + + + + + ID_MMFR1 + 0x0000ed54 + Provides information about the implemented memory model and memory management support + 0x00000000 + + + ID_MMFR1 + [31:0] + read-write + + + + + ID_MMFR2 + 0x0000ed58 + Provides information about the implemented memory model and memory management support + 0x01000000 + + + WFISTALL + Indicates the support for Wait For Interrupt (WFI) stalling + [27:24] + read-only + + + + + ID_MMFR3 + 0x0000ed5c + Provides information about the implemented memory model and memory management support + 0x00000000 + + + BPMAINT + Indicates the supported branch predictor maintenance + [11:8] + read-only + + + CMAINTSW + Indicates the supported cache maintenance operations by set/way + [7:4] + read-only + + + CMAINTVA + Indicates the supported cache maintenance operations by address + [3:0] + read-only + + + + + ID_ISAR0 + 0x0000ed60 + Provides information about the instruction set implemented by the PE + 0x08092300 + + + DIVIDE + Indicates the supported Divide instructions + [27:24] + read-only + + + DEBUG + Indicates the implemented Debug instructions + [23:20] + read-only + + + COPROC + Indicates the supported Coprocessor instructions + [19:16] + read-only + + + CMPBRANCH + Indicates the supported combined Compare and Branch instructions + [15:12] + read-only + + + BITFIELD + Indicates the supported bit field instructions + [11:8] + read-only + + + BITCOUNT + Indicates the supported bit count instructions + [7:4] + read-only + + + + + ID_ISAR1 + 0x0000ed64 + Provides information about the instruction set implemented by the PE + 0x05725000 + + + INTERWORK + Indicates the implemented Interworking instructions + [27:24] + read-only + + + IMMEDIATE + Indicates the implemented for data-processing instructions with long immediates + [23:20] + read-only + + + IFTHEN + Indicates the implemented If-Then instructions + [19:16] + read-only + + + EXTEND + Indicates the implemented Extend instructions + [15:12] + read-only + + + + + ID_ISAR2 + 0x0000ed68 + Provides information about the instruction set implemented by the PE + 0x30173426 + + + REVERSAL + Indicates the implemented Reversal instructions + [31:28] + read-only + + + MULTU + Indicates the implemented advanced unsigned Multiply instructions + [23:20] + read-only + + + MULTS + Indicates the implemented advanced signed Multiply instructions + [19:16] + read-only + + + MULT + Indicates the implemented additional Multiply instructions + [15:12] + read-only + + + MULTIACCESSINT + Indicates the support for interruptible multi-access instructions + [11:8] + read-only + + + MEMHINT + Indicates the implemented Memory Hint instructions + [7:4] + read-only + + + LOADSTORE + Indicates the implemented additional load/store instructions + [3:0] + read-only + + + + + ID_ISAR3 + 0x0000ed6c + Provides information about the instruction set implemented by the PE + 0x07895729 + + + TRUENOP + Indicates the implemented true NOP instructions + [27:24] + read-only + + + T32COPY + Indicates the support for T32 non flag-setting MOV instructions + [23:20] + read-only + + + TABBRANCH + Indicates the implemented Table Branch instructions + [19:16] + read-only + + + SYNCHPRIM + Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions + [15:12] + read-only + + + SVC + Indicates the implemented SVC instructions + [11:8] + read-only + + + SIMD + Indicates the implemented SIMD instructions + [7:4] + read-only + + + SATURATE + Indicates the implemented saturating instructions + [3:0] + read-only + + + + + ID_ISAR4 + 0x0000ed70 + Provides information about the instruction set implemented by the PE + 0x01310132 + + + PSR_M + Indicates the implemented M profile instructions to modify the PSRs + [27:24] + read-only + + + SYNCPRIM_FRAC + Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions + [23:20] + read-only + + + BARRIER + Indicates the implemented Barrier instructions + [19:16] + read-only + + + WRITEBACK + Indicates the support for writeback addressing modes + [11:8] + read-only + + + WITHSHIFTS + Indicates the support for writeback addressing modes + [7:4] + read-only + + + UNPRIV + Indicates the implemented unprivileged instructions + [3:0] + read-only + + + + + ID_ISAR5 + 0x0000ed74 + Provides information about the instruction set implemented by the PE + 0x00000000 + + + ID_ISAR5 + [31:0] + read-write + + + + + CTR + 0x0000ed7c + Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + 0x8000c000 + + + RES1 + Reserved, RES1 + [31:31] + read-only + + + CWG + Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified + [27:24] + read-only + + + ERG + Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions + [23:20] + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE + [19:16] + read-only + + + RES1_1 + Reserved, RES1 + [15:14] + read-only + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE + [3:0] + read-only + + + + + CPACR + 0x0000ed88 + Specifies the access privileges for coprocessors and the FP Extension + 0x00000000 + + + CP11 + The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN + [23:22] + read-write + + + CP10 + Defines the access rights for the floating-point functionality + [21:20] + read-write + + + CP7 + Controls access privileges for coprocessor 7 + [15:14] + read-write + + + CP6 + Controls access privileges for coprocessor 6 + [13:12] + read-write + + + CP5 + Controls access privileges for coprocessor 5 + [11:10] + read-write + + + CP4 + Controls access privileges for coprocessor 4 + [9:8] + read-write + + + CP3 + Controls access privileges for coprocessor 3 + [7:6] + read-write + + + CP2 + Controls access privileges for coprocessor 2 + [5:4] + read-write + + + CP1 + Controls access privileges for coprocessor 1 + [3:2] + read-write + + + CP0 + Controls access privileges for coprocessor 0 + [1:0] + read-write + + + + + NSACR + 0x0000ed8c + Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + 0x00000000 + + + CP11 + Enables Non-secure access to the Floating-point Extension + [11:11] + read-write + + + CP10 + Enables Non-secure access to the Floating-point Extension + [10:10] + read-write + + + CP7 + Enables Non-secure access to coprocessor CP7 + [7:7] + read-write + + + CP6 + Enables Non-secure access to coprocessor CP6 + [6:6] + read-write + + + CP5 + Enables Non-secure access to coprocessor CP5 + [5:5] + read-write + + + CP4 + Enables Non-secure access to coprocessor CP4 + [4:4] + read-write + + + CP3 + Enables Non-secure access to coprocessor CP3 + [3:3] + read-write + + + CP2 + Enables Non-secure access to coprocessor CP2 + [2:2] + read-write + + + CP1 + Enables Non-secure access to coprocessor CP1 + [1:1] + read-write + + + CP0 + Enables Non-secure access to coprocessor CP0 + [0:0] + read-write + + + + + MPU_TYPE + 0x0000ed90 + The MPU Type Register indicates how many regions the MPU `FTSSS supports + 0x00000800 + + + DREGION + Number of regions supported by the MPU + [15:8] + read-only + + + SEPARATE + Indicates support for separate instructions and data address regions + [0:0] + read-only + + + + + MPU_CTRL + 0x0000ed94 + Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled for privileged software + [2:2] + read-write + + + HFNMIENA + Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + [1:1] + read-write + + + ENABLE + Enables the MPU + [0:0] + read-write + + + + + MPU_RNR + 0x0000ed98 + Selects the region currently accessed by MPU_RBAR and MPU_RLAR + 0x00000000 + + + REGION + Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + [2:0] + read-write + + + + + MPU_RBAR + 0x0000ed9c + Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR + 0x0000eda0 + Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A1 + 0x0000eda4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A1 + 0x0000eda8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A2 + 0x0000edac + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A2 + 0x0000edb0 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A3 + 0x0000edb4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A3 + 0x0000edb8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_MAIR0 + 0x0000edc0 + Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR3 + Memory attribute encoding for MPU regions with an AttrIndex of 3 + [31:24] + read-write + + + ATTR2 + Memory attribute encoding for MPU regions with an AttrIndex of 2 + [23:16] + read-write + + + ATTR1 + Memory attribute encoding for MPU regions with an AttrIndex of 1 + [15:8] + read-write + + + ATTR0 + Memory attribute encoding for MPU regions with an AttrIndex of 0 + [7:0] + read-write + + + + + MPU_MAIR1 + 0x0000edc4 + Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR7 + Memory attribute encoding for MPU regions with an AttrIndex of 7 + [31:24] + read-write + + + ATTR6 + Memory attribute encoding for MPU regions with an AttrIndex of 6 + [23:16] + read-write + + + ATTR5 + Memory attribute encoding for MPU regions with an AttrIndex of 5 + [15:8] + read-write + + + ATTR4 + Memory attribute encoding for MPU regions with an AttrIndex of 4 + [7:0] + read-write + + + + + SAU_CTRL + 0x0000edd0 + Allows enabling of the Security Attribution Unit + 0x00000000 + + + ALLNS + When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure + [1:1] + read-write + + + ENABLE + Enables the SAU + [0:0] + read-write + + + + + SAU_TYPE + 0x0000edd4 + Indicates the number of regions implemented by the Security Attribution Unit + 0x00000008 + + + SREGION + The number of implemented SAU regions + [7:0] + read-only + + + + + SAU_RNR + 0x0000edd8 + Selects the region currently accessed by SAU_RBAR and SAU_RLAR + 0x00000000 + + + REGION + Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + [7:0] + read-write + + + + + SAU_RBAR + 0x0000eddc + Provides indirect read and write access to the base address of the currently selected SAU region + 0x00000000 + + + BADDR + Holds bits [31:5] of the base address for the selected SAU region + [31:5] + read-write + + + + + SAU_RLAR + 0x0000ede0 + Provides indirect read and write access to the limit address of the currently selected SAU region + 0x00000000 + + + LADDR + Holds bits [31:5] of the limit address for the selected SAU region + [31:5] + read-write + + + NSC + Controls whether Non-secure state is permitted to execute an SG instruction from this region + [1:1] + read-write + + + ENABLE + SAU region enable + [0:0] + read-write + + + + + SFSR + 0x0000ede4 + Provides information about any security related faults + 0x00000000 + + + LSERR + Sticky flag indicating that an error occurred during lazy state activation or deactivation + [7:7] + read-write + + + SFARVALID + This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault + [6:6] + read-write + + + LSPERR + Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state + [5:5] + read-write + + + INVTRAN + Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory + [4:4] + read-write + + + AUVIOL + Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR + [3:3] + read-write + + + INVER + This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state + [2:2] + read-write + + + INVIS + This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation + [1:1] + read-write + + + INVEP + This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set + [0:0] + read-write + + + + + SFAR + 0x0000ede8 + Shows the address of the memory location that caused a Security violation + 0x00000000 + + + ADDRESS + The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state + [31:0] + read-write + + + + + DHCSR + 0x0000edf0 + Controls halting debug + 0x00000000 + + + S_RESTART_ST + Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request + [26:26] + read-only + + + S_RESET_ST + Indicates whether the PE has been reset since the last read of the DHCSR + [25:25] + read-only + + + S_RETIRE_ST + Set to 1 every time the PE retires one of more instructions + [24:24] + read-only + + + S_SDE + Indicates whether Secure invasive debug is allowed + [20:20] + read-only + + + S_LOCKUP + Indicates whether the PE is in Lockup state + [19:19] + read-only + + + S_SLEEP + Indicates whether the PE is sleeping + [18:18] + read-only + + + S_HALT + Indicates whether the PE is in Debug state + [17:17] + read-only + + + S_REGRDY + Handshake flag to transfers through the DCRDR + [16:16] + read-only + + + C_SNAPSTALL + Allow imprecise entry to Debug state + [5:5] + read-write + + + C_MASKINTS + When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts + [3:3] + read-write + + + C_STEP + Enable single instruction step + [2:2] + read-write + + + C_HALT + PE enter Debug state halt request + [1:1] + read-write + + + C_DEBUGEN + Enable Halting debug + [0:0] + read-write + + + + + DCRSR + 0x0000edf4 + With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + 0x00000000 + + + REGWNR + Specifies the access type for the transfer + [16:16] + read-write + + + REGSEL + Specifies the general-purpose register, special-purpose register, or FP register to transfer + [6:0] + read-write + + + + + DCRDR + 0x0000edf8 + With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + 0x00000000 + + + DBGTMP + Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers + [31:0] + read-write + + + + + DEMCR + 0x0000edfc + Manages vector catch behavior and DebugMonitor handling when debugging + 0x00000000 + + + TRCENA + Global enable for all DWT and ITM features + [24:24] + read-write + + + SDME + Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state + [20:20] + read-only + + + MON_REQ + DebugMonitor semaphore bit + [19:19] + read-write + + + MON_STEP + Enable DebugMonitor stepping + [18:18] + read-write + + + MON_PEND + Sets or clears the pending state of the DebugMonitor exception + [17:17] + read-write + + + MON_EN + Enable the DebugMonitor exception + [16:16] + read-write + + + VC_SFERR + SecureFault exception halting debug vector catch enable + [11:11] + read-write + + + VC_HARDERR + HardFault exception halting debug vector catch enable + [10:10] + read-write + + + VC_INTERR + Enable halting debug vector catch for faults during exception entry and return + [9:9] + read-write + + + VC_BUSERR + BusFault exception halting debug vector catch enable + [8:8] + read-write + + + VC_STATERR + Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception + [7:7] + read-write + + + VC_CHKERR + Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error + [6:6] + read-write + + + VC_NOCPERR + Enable halting debug trap on a UsageFault caused by an access to a coprocessor + [5:5] + read-write + + + VC_MMERR + Enable halting debug trap on a MemManage exception + [4:4] + read-write + + + VC_CORERESET + Enable Reset Vector Catch. This causes a warm reset to halt a running system + [0:0] + read-write + + + + + DSCSR + 0x0000ee08 + Provides control and status information for Secure debug + 0x00000000 + + + CDSKEY + Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero + [17:17] + read-write + + + CDS + This field indicates the current Security state of the processor + [16:16] + read-write + + + SBRSEL + If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger + [1:1] + read-write + + + SBRSELEN + Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger + [0:0] + read-write + + + + + STIR + 0x0000ef00 + Provides a mechanism for software to generate an interrupt + 0x00000000 + + + INTID + Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) + [8:0] + read-write + + + + + FPCCR + 0x0000ef34 + Holds control data for the Floating-point extension + 0x20000472 + + + ASPEN + When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 + [31:31] + read-write + + + LSPEN + Enables lazy context save of floating-point state + [30:30] + read-write + + + LSPENS + This bit controls whether the LSPEN bit is writeable from the Non-secure state + [29:29] + read-write + + + CLRONRET + Clear floating-point caller saved registers on exception return + [28:28] + read-write + + + CLRONRETS + This bit controls whether the CLRONRET bit is writeable from the Non-secure state + [27:27] + read-write + + + TS + Treat floating-point registers as Secure enable + [26:26] + read-write + + + UFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending + [10:10] + read-write + + + SPLIMVIOL + This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior + [9:9] + read-write + + + MONRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending + [8:8] + read-write + + + SFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state + [7:7] + read-write + + + BFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending + [6:6] + read-write + + + MMRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending + [5:5] + read-write + + + HFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending + [4:4] + read-write + + + THREAD + Indicates the PE mode when it allocated the floating-point stack frame + [3:3] + read-write + + + S + Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed + [2:2] + read-write + + + USER + Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame + [1:1] + read-write + + + LSPACT + Indicates whether lazy preservation of the floating-point state is active + [0:0] + read-write + + + + + FPCAR + 0x0000ef38 + Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + 0x00000000 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame + [31:3] + read-write + + + + + FPDSCR + 0x0000ef3c + Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + 0x00000000 + + + AHP + Default value for FPSCR.AHP + [26:26] + read-write + + + DN + Default value for FPSCR.DN + [25:25] + read-write + + + FZ + Default value for FPSCR.FZ + [24:24] + read-write + + + RMODE + Default value for FPSCR.RMode + [23:22] + read-write + + + + + MVFR0 + 0x0000ef40 + Describes the features provided by the Floating-point Extension + 0x60540601 + + + FPROUND + Indicates the rounding modes supported by the FP Extension + [31:28] + read-only + + + FPSQRT + Indicates the support for FP square root operations + [23:20] + read-only + + + FPDIVIDE + Indicates the support for FP divide operations + [19:16] + read-only + + + FPDP + Indicates support for FP double-precision operations + [11:8] + read-only + + + FPSP + Indicates support for FP single-precision operations + [7:4] + read-only + + + SIMDREG + Indicates size of FP register file + [3:0] + read-only + + + + + MVFR1 + 0x0000ef44 + Describes the features provided by the Floating-point Extension + 0x85000089 + + + FMAC + Indicates whether the FP Extension implements the fused multiply accumulate instructions + [31:28] + read-only + + + FPHP + Indicates whether the FP Extension implements half-precision FP conversion instructions + [27:24] + read-only + + + FPDNAN + Indicates whether the FP hardware implementation supports NaN propagation + [7:4] + read-only + + + FPFTZ + Indicates whether subnormals are always flushed-to-zero + [3:0] + read-only + + + + + MVFR2 + 0x0000ef48 + Describes the features provided by the Floating-point Extension + 0x00000060 + + + FPMISC + Indicates support for miscellaneous FP features + [7:4] + read-only + + + + + DDEVARCH + 0x0000efbc + Provides CoreSight discovery information for the SCS + 0x47702a04 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DDEVTYPE + 0x0000efcc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + CoreSight major type + [3:0] + read-only + + + + + DPIDR4 + 0x0000efd0 + Provides CoreSight discovery information for the SCS + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR5 + 0x0000efd4 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR5 + [31:0] + read-write + + + + + DPIDR6 + 0x0000efd8 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR6 + [31:0] + read-write + + + + + DPIDR7 + 0x0000efdc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR7 + [31:0] + read-write + + + + + DPIDR0 + 0x0000efe0 + Provides CoreSight discovery information for the SCS + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DPIDR1 + 0x0000efe4 + Provides CoreSight discovery information for the SCS + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR2 + 0x0000efe8 + Provides CoreSight discovery information for the SCS + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DPIDR3 + 0x0000efec + Provides CoreSight discovery information for the SCS + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR0 + 0x0000eff0 + Provides CoreSight discovery information for the SCS + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR1 + 0x0000eff4 + Provides CoreSight discovery information for the SCS + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR2 + 0x0000eff8 + Provides CoreSight discovery information for the SCS + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR3 + 0x0000effc + Provides CoreSight discovery information for the SCS + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + TRCPRGCTLR + 0x00041004 + Programming Control Register + 0x00000000 + + + EN + Trace Unit Enable + [0:0] + read-write + + + + + TRCSTATR + 0x0004100c + The TRCSTATR indicates the ETM-Teal status + 0x00000000 + + + PMSTABLE + Indicates whether the ETM-Teal registers are stable and can be read + [1:1] + read-only + + + IDLE + Indicates that the trace unit is inactive + [0:0] + read-only + + + + + TRCCONFIGR + 0x00041010 + The TRCCONFIGR sets the basic tracing options for the trace unit + 0x00000000 + + + RS + Return stack enable + [12:12] + read-write + + + TS + Global timestamp tracing + [11:11] + read-write + + + COND + Conditional instruction tracing + [10:5] + read-write + + + CCI + Cycle counting in instruction trace + [4:4] + read-write + + + BB + Branch broadcast mode + [3:3] + read-write + + + + + TRCEVENTCTL0R + 0x00041020 + The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + 0x00000000 + + + TYPE1 + Selects the resource type for event 1 + [15:15] + read-write + + + SEL1 + Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] + [10:8] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [2:0] + read-write + + + + + TRCEVENTCTL1R + 0x00041024 + The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + 0x00000000 + + + LPOVERRIDE + Low power state behavior override + [12:12] + read-write + + + ATB + ATB enabled + [11:11] + read-write + + + INSTEN1 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [1:1] + read-write + + + INSTEN0 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [0:0] + read-write + + + + + TRCSTALLCTLR + 0x0004102c + The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + 0x00000000 + + + INSTPRIORITY + Reserved, RES0 + [10:10] + read-only + + + ISTALL + Stall processor based on instruction trace buffer space + [8:8] + read-write + + + LEVEL + Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow + [3:2] + read-write + + + + + TRCTSCTLR + 0x00041030 + The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + 0x00000000 + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCSYNCPR + 0x00041034 + The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + 0x0000000a + + + PERIOD + Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes + [4:0] + read-only + + + + + TRCCCCTLR + 0x00041038 + The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + 0x00000000 + + + THRESHOLD + Instruction trace cycle count threshold + [11:0] + read-write + + + + + TRCVICTLR + 0x00041080 + The TRCVICTLR controls instruction trace filtering + 0x00000000 + + + EXLEVEL_S3 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [19:19] + read-write + + + EXLEVEL_S0 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [16:16] + read-write + + + TRCERR + Selects whether a system error exception must always be traced + [11:11] + read-write + + + TRCRESET + Selects whether a reset exception must always be traced + [10:10] + read-write + + + SSSTATUS + Indicates the current status of the start/stop logic + [9:9] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCCNTRLDVR0 + 0x00041140 + The TRCCNTRLDVR defines the reload value for the reduced function counter + 0x00000000 + + + VALUE + Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs + [15:0] + read-write + + + + + TRCIDR8 + 0x00041180 + TRCIDR8 + 0x00000000 + + + MAXSPEC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR9 + 0x00041184 + TRCIDR9 + 0x00000000 + + + NUMP0KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR10 + 0x00041188 + TRCIDR10 + 0x00000000 + + + NUMP1KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR11 + 0x0004118c + TRCIDR11 + 0x00000000 + + + NUMP1SPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR12 + 0x00041190 + TRCIDR12 + 0x00000001 + + + NUMCONDKEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR13 + 0x00041194 + TRCIDR13 + 0x00000000 + + + NUMCONDSPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIMSPEC + 0x000411c0 + The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + 0x00000000 + + + SUPPORT + Reserved, RES0 + [3:0] + read-only + + + + + TRCIDR0 + 0x000411e0 + TRCIDR0 + 0x280006e1 + + + COMMOPT + reads as `ImpDef + [29:29] + read-only + + + TSSIZE + reads as `ImpDef + [28:24] + read-only + + + TRCEXDATA + reads as `ImpDef + [17:17] + read-only + + + QSUPP + reads as `ImpDef + [16:15] + read-only + + + QFILT + reads as `ImpDef + [14:14] + read-only + + + CONDTYPE + reads as `ImpDef + [13:12] + read-only + + + NUMEVENT + reads as `ImpDef + [11:10] + read-only + + + RETSTACK + reads as `ImpDef + [9:9] + read-only + + + TRCCCI + reads as `ImpDef + [7:7] + read-only + + + TRCCOND + reads as `ImpDef + [6:6] + read-only + + + TRCBB + reads as `ImpDef + [5:5] + read-only + + + TRCDATA + reads as `ImpDef + [4:3] + read-only + + + INSTP0 + reads as `ImpDef + [2:1] + read-only + + + RES1 + Reserved, RES1 + [0:0] + read-only + + + + + TRCIDR1 + 0x000411e4 + TRCIDR1 + 0x4100f421 + + + DESIGNER + reads as `ImpDef + [31:24] + read-only + + + RES1 + Reserved, RES1 + [15:12] + read-only + + + TRCARCHMAJ + reads as 0b0100 + [11:8] + read-only + + + TRCARCHMIN + reads as 0b0000 + [7:4] + read-only + + + REVISION + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR2 + 0x000411e8 + TRCIDR2 + 0x00000004 + + + CCSIZE + reads as `ImpDef + [28:25] + read-only + + + DVSIZE + reads as `ImpDef + [24:20] + read-only + + + DASIZE + reads as `ImpDef + [19:15] + read-only + + + VMIDSIZE + reads as `ImpDef + [14:10] + read-only + + + CIDSIZE + reads as `ImpDef + [9:5] + read-only + + + IASIZE + reads as `ImpDef + [4:0] + read-only + + + + + TRCIDR3 + 0x000411ec + TRCIDR3 + 0x0f090004 + + + NOOVERFLOW + reads as `ImpDef + [31:31] + read-only + + + NUMPROC + reads as `ImpDef + [30:28] + read-only + + + SYSSTALL + reads as `ImpDef + [27:27] + read-only + + + STALLCTL + reads as `ImpDef + [26:26] + read-only + + + SYNCPR + reads as `ImpDef + [25:25] + read-only + + + TRCERR + reads as `ImpDef + [24:24] + read-only + + + EXLEVEL_NS + reads as `ImpDef + [23:20] + read-only + + + EXLEVEL_S + reads as `ImpDef + [19:16] + read-only + + + CCITMIN + reads as `ImpDef + [11:0] + read-only + + + + + TRCIDR4 + 0x000411f0 + TRCIDR4 + 0x00114000 + + + NUMVMIDC + reads as `ImpDef + [31:28] + read-only + + + NUMCIDC + reads as `ImpDef + [27:24] + read-only + + + NUMSSCC + reads as `ImpDef + [23:20] + read-only + + + NUMRSPAIR + reads as `ImpDef + [19:16] + read-only + + + NUMPC + reads as `ImpDef + [15:12] + read-only + + + SUPPDAC + reads as `ImpDef + [8:8] + read-only + + + NUMDVC + reads as `ImpDef + [7:4] + read-only + + + NUMACPAIRS + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR5 + 0x000411f4 + TRCIDR5 + 0x90c70004 + + + REDFUNCNTR + reads as `ImpDef + [31:31] + read-only + + + NUMCNTR + reads as `ImpDef + [30:28] + read-only + + + NUMSEQSTATE + reads as `ImpDef + [27:25] + read-only + + + LPOVERRIDE + reads as `ImpDef + [23:23] + read-only + + + ATBTRIG + reads as `ImpDef + [22:22] + read-only + + + TRACEIDSIZE + reads as 0x07 + [21:16] + read-only + + + NUMEXTINSEL + reads as `ImpDef + [11:9] + read-only + + + NUMEXTIN + reads as `ImpDef + [8:0] + read-only + + + + + TRCIDR6 + 0x000411f8 + TRCIDR6 + 0x00000000 + + + TRCIDR6 + [31:0] + read-write + + + + + TRCIDR7 + 0x000411fc + TRCIDR7 + 0x00000000 + + + TRCIDR7 + [31:0] + read-write + + + + + TRCRSCTLR2 + 0x00041208 + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCRSCTLR3 + 0x0004120c + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCSSCSR + 0x000412a0 + Controls the corresponding single-shot comparator resource + 0x00000000 + + + STATUS + Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + [31:31] + read-write + + + PC + Reserved, RES1 + [3:3] + read-only + + + DV + Reserved, RES0 + [2:2] + read-only + + + DA + Reserved, RES0 + [1:1] + read-only + + + INST + Reserved, RES0 + [0:0] + read-only + + + + + TRCSSPCICR + 0x000412c0 + Selects the PE comparator inputs for Single-shot control + 0x00000000 + + + PC + Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control + [3:0] + read-write + + + + + TRCPDCR + 0x00041310 + Requests the system to provide power to the trace unit + 0x00000000 + + + PU + Powerup request bit: + [3:3] + read-write + + + + + TRCPDSR + 0x00041314 + Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + 0x00000003 + + + OSLK + OS Lock status bit: + [5:5] + read-only + + + STICKYPD + Sticky powerdown status bit. Indicates whether the trace register state is valid: + [1:1] + read-only + + + POWER + Power status bit: + [0:0] + read-only + + + + + TRCITATBIDR + 0x00041ee4 + Trace Integration ATB Identification Register + 0x00000000 + + + ID + Trace ID + [6:0] + read-write + + + + + TRCITIATBINR + 0x00041ef4 + Trace Integration Instruction ATB In Register + 0x00000000 + + + AFVALIDM + Integration Mode instruction AFVALIDM in + [1:1] + read-write + + + ATREADYM + Integration Mode instruction ATREADYM in + [0:0] + read-write + + + + + TRCITIATBOUTR + 0x00041efc + Trace Integration Instruction ATB Out Register + 0x00000000 + + + AFREADY + Integration Mode instruction AFREADY out + [1:1] + read-write + + + ATVALID + Integration Mode instruction ATVALID out + [0:0] + read-write + + + + + TRCCLAIMSET + 0x00041fa0 + Claim Tag Set Register + 0x0000000f + + + SET3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + SET2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + SET1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + SET0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCCLAIMCLR + 0x00041fa4 + Claim Tag Clear Register + 0x00000000 + + + CLR3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + CLR2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + CLR1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + CLR0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCAUTHSTATUS + 0x00041fb8 + Returns the level of tracing that the trace unit can support + 0x00000000 + + + SNID + Indicates whether the system enables the trace unit to support Secure non-invasive debug: + [7:6] + read-only + + + SID + Indicates whether the trace unit supports Secure invasive debug: + [5:4] + read-only + + + NSNID + Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: + [3:2] + read-only + + + NSID + Indicates whether the trace unit supports Non-secure invasive debug: + [1:0] + read-only + + + + + TRCDEVARCH + 0x00041fbc + TRCDEVARCH + 0x47724a13 + + + ARCHITECT + reads as 0b01000111011 + [31:21] + read-only + + + PRESENT + reads as 0b1 + [20:20] + read-only + + + REVISION + reads as 0b0000 + [19:16] + read-only + + + ARCHID + reads as 0b0100101000010011 + [15:0] + read-only + + + + + TRCDEVID + 0x00041fc8 + TRCDEVID + 0x00000000 + + + TRCDEVID + [31:0] + read-write + + + + + TRCDEVTYPE + 0x00041fcc + TRCDEVTYPE + 0x00000013 + + + SUB + reads as 0b0001 + [7:4] + read-only + + + MAJOR + reads as 0b0011 + [3:0] + read-only + + + + + TRCPIDR4 + 0x00041fd0 + TRCPIDR4 + 0x00000004 + + + SIZE + reads as `ImpDef + [7:4] + read-only + + + DES_2 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR5 + 0x00041fd4 + TRCPIDR5 + 0x00000000 + + + TRCPIDR5 + [31:0] + read-write + + + + + TRCPIDR6 + 0x00041fd8 + TRCPIDR6 + 0x00000000 + + + TRCPIDR6 + [31:0] + read-write + + + + + TRCPIDR7 + 0x00041fdc + TRCPIDR7 + 0x00000000 + + + TRCPIDR7 + [31:0] + read-write + + + + + TRCPIDR0 + 0x00041fe0 + TRCPIDR0 + 0x00000021 + + + PART_0 + reads as `ImpDef + [7:0] + read-only + + + + + TRCPIDR1 + 0x00041fe4 + TRCPIDR1 + 0x000000bd + + + DES_0 + reads as `ImpDef + [7:4] + read-only + + + PART_0 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR2 + 0x00041fe8 + TRCPIDR2 + 0x0000002b + + + REVISION + reads as `ImpDef + [7:4] + read-only + + + JEDEC + reads as 0b1 + [3:3] + read-only + + + DES_0 + reads as `ImpDef + [2:0] + read-only + + + + + TRCPIDR3 + 0x00041fec + TRCPIDR3 + 0x00000000 + + + REVAND + reads as `ImpDef + [7:4] + read-only + + + CMOD + reads as `ImpDef + [3:0] + read-only + + + + + TRCCIDR0 + 0x00041ff0 + TRCCIDR0 + 0x0000000d + + + PRMBL_0 + reads as 0b00001101 + [7:0] + read-only + + + + + TRCCIDR1 + 0x00041ff4 + TRCCIDR1 + 0x00000090 + + + CLASS + reads as 0b1001 + [7:4] + read-only + + + PRMBL_1 + reads as 0b0000 + [3:0] + read-only + + + + + TRCCIDR2 + 0x00041ff8 + TRCCIDR2 + 0x00000005 + + + PRMBL_2 + reads as 0b00000101 + [7:0] + read-only + + + + + TRCCIDR3 + 0x00041ffc + TRCCIDR3 + 0x000000b1 + + + PRMBL_3 + reads as 0b10110001 + [7:0] + read-only + + + + + CTICONTROL + 0x00042000 + CTI Control Register + 0x00000000 + + + GLBEN + Enables or disables the CTI + [0:0] + read-write + + + + + CTIINTACK + 0x00042010 + CTI Interrupt Acknowledge Register + 0x00000000 + + + INTACK + Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. + [7:0] + read-write + + + + + CTIAPPSET + 0x00042014 + CTI Application Trigger Set Register + 0x00000000 + + + APPSET + Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel + [3:0] + read-write + + + + + CTIAPPCLEAR + 0x00042018 + CTI Application Trigger Clear Register + 0x00000000 + + + APPCLEAR + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIAPPPULSE + 0x0004201c + CTI Application Pulse Register + 0x00000000 + + + APPULSE + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIINEN0 + 0x00042020 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN1 + 0x00042024 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN2 + 0x00042028 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN3 + 0x0004202c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN4 + 0x00042030 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN5 + 0x00042034 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN6 + 0x00042038 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN7 + 0x0004203c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIOUTEN0 + 0x000420a0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN1 + 0x000420a4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN2 + 0x000420a8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN3 + 0x000420ac + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN4 + 0x000420b0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN5 + 0x000420b4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN6 + 0x000420b8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN7 + 0x000420bc + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTITRIGINSTATUS + 0x00042130 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINSTATUS + Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. + [7:0] + read-only + + + + + CTITRIGOUTSTATUS + 0x00042134 + CTI Trigger In Status Register + 0x00000000 + + + TRIGOUTSTATUS + Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. + [7:0] + read-only + + + + + CTICHINSTATUS + 0x00042138 + CTI Channel In Status Register + 0x00000000 + + + CTICHOUTSTATUS + Shows the status of the ctichout outputs. There is one bit of the field for each channel output + [3:0] + read-only + + + + + CTIGATE + 0x00042140 + Enable CTI Channel Gate register + 0x0000000f + + + CTIGATEEN3 + Enable ctichout3. Set to 0 to disable channel propagation. + [3:3] + read-write + + + CTIGATEEN2 + Enable ctichout2. Set to 0 to disable channel propagation. + [2:2] + read-write + + + CTIGATEEN1 + Enable ctichout1. Set to 0 to disable channel propagation. + [1:1] + read-write + + + CTIGATEEN0 + Enable ctichout0. Set to 0 to disable channel propagation. + [0:0] + read-write + + + + + ASICCTL + 0x00042144 + External Multiplexer Control register + 0x00000000 + + + ASICCTL + [31:0] + read-write + + + + + ITCHOUT + 0x00042ee4 + Integration Test Channel Output register + 0x00000000 + + + CTCHOUT + Sets the value of the ctichout outputs + [3:0] + read-write + + + + + ITTRIGOUT + 0x00042ee8 + Integration Test Trigger Output register + 0x00000000 + + + CTTRIGOUT + Sets the value of the ctitrigout outputs + [7:0] + read-write + + + + + ITCHIN + 0x00042ef4 + Integration Test Channel Input register + 0x00000000 + + + CTCHIN + Reads the value of the ctichin inputs. + [3:0] + read-only + + + + + ITCTRL + 0x00042f00 + Integration Mode Control register + 0x00000000 + + + IME + Integration Mode Enable + [0:0] + read-write + + + + + DEVARCH + 0x00042fbc + Device Architecture register + 0x47701a14 + + + ARCHITECT + Indicates the component architect + [31:21] + read-only + + + PRESENT + Indicates whether the DEVARCH register is present + [20:20] + read-only + + + REVISION + Indicates the architecture revision + [19:16] + read-only + + + ARCHID + Indicates the component + [15:0] + read-only + + + + + DEVID + 0x00042fc8 + Device Configuration register + 0x00040800 + + + NUMCH + Number of ECT channels available + [19:16] + read-only + + + NUMTRIG + Number of ECT triggers available. + [15:8] + read-only + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. + [4:0] + read-only + + + + + DEVTYPE + 0x00042fcc + Device Type Identifier register + 0x00000014 + + + SUB + Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. + [7:4] + read-only + + + MAJOR + Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. + [3:0] + read-only + + + + + PIDR4 + 0x00042fd0 + CoreSight Peripheral ID4 + 0x00000004 + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory + [7:4] + read-only + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [3:0] + read-only + + + + + PIDR5 + 0x00042fd4 + CoreSight Peripheral ID5 + 0x00000000 + + + PIDR5 + [31:0] + read-write + + + + + PIDR6 + 0x00042fd8 + CoreSight Peripheral ID6 + 0x00000000 + + + PIDR6 + [31:0] + read-write + + + + + PIDR7 + 0x00042fdc + CoreSight Peripheral ID7 + 0x00000000 + + + PIDR7 + [31:0] + read-write + + + + + PIDR0 + 0x00042fe0 + CoreSight Peripheral ID0 + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + [7:0] + read-only + + + + + PIDR1 + 0x00042fe4 + CoreSight Peripheral ID1 + 0x000000bd + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [7:4] + read-only + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + [3:0] + read-only + + + + + PIDR2 + 0x00042fe8 + CoreSight Peripheral ID2 + 0x0000000b + + + REVISION + This device is at r1p0 + [7:4] + read-only + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + [3:3] + read-only + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [2:0] + read-only + + + + + PIDR3 + 0x00042fec + CoreSight Peripheral ID3 + 0x00000000 + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + [7:4] + read-only + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. + [3:0] + read-only + + + + + CIDR0 + 0x00042ff0 + CoreSight Component ID0 + 0x0000000d + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code + [7:0] + read-only + + + + + CIDR1 + 0x00042ff4 + CoreSight Component ID1 + 0x00000090 + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. + [7:4] + read-only + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + [3:0] + read-only + + + + + CIDR2 + 0x00042ff8 + CoreSight Component ID2 + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + [7:0] + read-only + + + + + CIDR3 + 0x00042ffc + CoreSight Component ID3 + 0x000000b1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + [7:0] + read-only + + + + + + + PPB_NS + 0xe0020000 + + + QMI + QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. + 0x400d0000 + + 0 + 84 + registers + + + + DIRECT_CSR + 0x00000000 + Control and status for direct serial mode + + Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + 0x01800000 + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) + [31:30] + read-write + + + CLKDIV + Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. + [29:22] + read-write + + + RXLEVEL + Current level of DIRECT_RX FIFO + [20:18] + read-only + + + RXFULL + When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. + [17:17] + read-only + + + RXEMPTY + When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. + [16:16] + read-only + + + TXLEVEL + Current level of DIRECT_TX FIFO + [14:12] + read-only + + + TXEMPTY + When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. + [11:11] + read-only + + + TXFULL + When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. + [10:10] + read-only + + + AUTO_CS1N + When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. + [7:7] + read-write + + + AUTO_CS0N + When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. + [6:6] + read-write + + + ASSERT_CS1N + When 1, assert (i.e. drive low) the CS1n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [3:3] + read-write + + + ASSERT_CS0N + When 1, assert (i.e. drive low) the CS0n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [2:2] + read-write + + + BUSY + Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. + + The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. + + (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) + [1:1] + read-only + + + EN + Enable direct mode. + + In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. + + Memory-mapped accesses will generate bus errors when direct serial mode is enabled. + [0:0] + read-write + + + + + DIRECT_TX + 0x00000004 + Transmit FIFO for direct mode + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + DIRECT_RX + 0x00000008 + Receive FIFO for direct mode + 0x00000000 + + + DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + M0_TIMING + 0x0000000c + Timing configuration register for memory address window 0. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M0_RFMT + 0x00000010 + Read transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_RCMD + 0x00000014 + Command constants used for reads from memory address window 0. + + The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M0_WFMT + 0x00000018 + Write transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_WCMD + 0x0000001c + Command constants used for writes to memory address window 0. + + The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_TIMING + 0x00000020 + Timing configuration register for memory address window 1. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M1_RFMT + 0x00000024 + Read transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_RCMD + 0x00000028 + Command constants used for reads from memory address window 1. + + The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_WFMT + 0x0000002c + Write transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_WCMD + 0x00000030 + Command constants used for writes to memory address window 1. + + The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + ATRANS0 + 0x00000034 + Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS1 + 0x00000038 + Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS2 + 0x0000003c + Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS3 + 0x00000040 + Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS4 + 0x00000044 + Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS5 + 0x00000048 + Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS6 + 0x0000004c + Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS7 + 0x00000050 + Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x400c8000 + + 0 + 32 + registers + + + + CTRL + 0x00000000 + Cache control register. Read-only from a Non-secure context. + 0x00000083 + + + WRITABLE_M1 + If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [11:11] + read-write + + + WRITABLE_M0 + If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [10:10] + read-write + + + SPLIT_WAYS + When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. + + This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. + + A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. + [9:9] + read-write + + + MAINT_NONSEC + When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. + + Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. + + Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. + [8:8] + read-write + + + NO_UNTRANSLATED_NONSEC + When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [7:7] + read-write + + + NO_UNTRANSLATED_SEC + When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [6:6] + read-write + + + NO_UNCACHED_NONSEC + When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [5:5] + read-write + + + NO_UNCACHED_SEC + When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [4:4] + read-write + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. + [3:3] + read-write + + + EN_NONSECURE + When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + [1:1] + read-write + + + EN_SECURE + When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + + There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. + [0:0] + read-write + + + + + STAT + 0x00000008 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + + + CTR_HIT + 0x0000000c + Cache Hit counter + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + 0x00000010 + Cache Access counter + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + 0x00000014 + FIFO stream address + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + 0x00000018 + FIFO stream control + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + 0x0000001c + FIFO stream data + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + XIP_AUX + Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + 0x50500000 + + 0 + 12 + registers + + + + STREAM + 0x00000000 + Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + 0x00000000 + + + STREAM + [31:0] + read-only + modify + + + + + QMI_DIRECT_TX + 0x00000004 + Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + QMI_DIRECT_RX + 0x00000008 + Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + 0x00000000 + + + QMI_DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40008000 + + 0 + 24 + registers + + + + PROC_CONFIG + 0x00000000 + Configuration for processors + 0x00000000 + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + 0x00000004 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...31. + 0x00000000 + + + GPIO + [31:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + 0x00000008 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + DBGFORCE + 0x0000000c + Directly control the chip SWD debug port + 0x00000006 + + + ATTACH + Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + SWCLK + Directly drive SWCLK, if ATTACH is set + [2:2] + read-write + + + SWDI + Directly drive SWDIO input, if ATTACH is set + [1:1] + read-write + + + SWDO + Observe the value of SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + 0x00000010 + Control PD pins to memories. + Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible + Use with caution + 0x00000000 + + + BOOTRAM + [12:12] + read-write + + + ROM + [11:11] + read-write + + + USB + [10:10] + read-write + + + SRAM9 + [9:9] + read-write + + + SRAM8 + [8:8] + read-write + + + SRAM7 + [7:7] + read-write + + + SRAM6 + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + AUXCTRL + 0x00000014 + Auxiliary system control register + 0x00000000 + + + AUXCTRL + * Bits 7:2: Reserved + + * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. + + * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. + [7:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40048000 + + 0 + 20 + registers + + + + CTRL + 0x00000000 + Crystal Oscillator Control + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + [11:0] + read-write + + + 1_15MHZ + 2720 + + + 10_30MHZ + 2721 + + + 25_60MHZ + 2722 + + + 40_100MHZ + 2723 + + + + + + + STATUS + 0x00000004 + Crystal Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting + [1:0] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + + + DORMANT + 0x00000008 + Crystal Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + 0x0000000c + Controls the startup delay + 0x00000000 + + + X4 + Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + 0x00000010 + A down counter running at the xosc frequency which counts to zero and stops. + Can be used for short software pauses when setting up time sensitive hardware. + To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. + Minimum count value is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + PLL_SYS + 0x40050000 + + 0 + 32 + registers + + + PLL_SYS_IRQ + 42 + + + + CS + 0x00000000 + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + LOCK_N + PLL is not locked + Ideally this is cleared when PLL lock is seen and this should never normally be set + [30:30] + read-write + oneToClear + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + 0x00000004 + Controls the PLL power modes. + 0x0000002d + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + 0x00000008 + Feedback divisor + (note: this PLL does not support fractional division) + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + 0x0000000c + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + INTR + 0x00000010 + Raw Interrupts + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000014 + Interrupt Enable + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTF + 0x00000018 + Interrupt Force + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTS + 0x0000001c + Interrupt status after masking & forcing + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-only + + + + + + + PLL_USB + 0x40058000 + + PLL_USB_IRQ + 43 + + + + ACCESSCTRL + Hardware access control registers + 0x40060000 + + 0 + 236 + registers + + + + LOCK + 0x00000000 + Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. + + LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL + + Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + 0x00000004 + + + DEBUG + [3:3] + read-write + + + DMA + [2:2] + read-only + + + CORE1 + [1:1] + read-write + + + CORE0 + [0:0] + read-write + + + + + FORCE_CORE_NS + 0x00000004 + Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. + + Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + 0x00000000 + + + CORE1 + [1:1] + read-write + + + + + CFGRESET + 0x00000008 + Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. + + This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. + + Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + 0x00000000 + + + CFGRESET + [0:0] + write-only + + + + + GPIO_NSMASK0 + 0x0000000c + Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. + + 0 -> Secure access only + + 1 -> Secure + Non-secure access + 0x00000000 + + + GPIO_NSMASK0 + [31:0] + read-write + + + + + GPIO_NSMASK1 + 0x00000010 + Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + ROM + 0x00000014 + Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_MAIN + 0x00000018 + Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM0 + 0x0000001c + Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM1 + 0x00000020 + Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM2 + 0x00000024 + Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM3 + 0x00000028 + Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM3 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM3 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM4 + 0x0000002c + Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM4 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM4 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM5 + 0x00000030 + Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM5 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM5 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM6 + 0x00000034 + Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM6 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM6 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM7 + 0x00000038 + Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM7 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM7 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM8 + 0x0000003c + Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM8 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM8 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM9 + 0x00000040 + Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM9 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM9 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + DMA + 0x00000044 + Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, DMA can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, DMA can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + USBCTRL + 0x00000048 + Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, USBCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO0 + 0x0000004c + Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO1 + 0x00000050 + Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO2 + 0x00000054 + Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_TRACE + 0x00000058 + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_PERIPH + 0x0000005c + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSINFO + 0x00000060 + Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSINFO can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RESETS + 0x00000064 + Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RESETS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RESETS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK0 + 0x00000068 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK1 + 0x0000006c + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_BANK0 + 0x00000070 + Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_QSPI + 0x00000074 + Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + BUSCTRL + 0x00000078 + Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, BUSCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ADC0 + 0x0000007c + Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ADC0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ADC0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + HSTX + 0x00000080 + Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, HSTX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, HSTX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C0 + 0x00000084 + Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C1 + 0x00000088 + Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PWM + 0x0000008c + Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PWM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PWM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI0 + 0x00000090 + Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI1 + 0x00000094 + Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER0 + 0x00000098 + Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER1 + 0x0000009c + Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART0 + 0x000000a0 + Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART1 + 0x000000a4 + Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + OTP + 0x000000a8 + Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, OTP can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, OTP can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TBMAN + 0x000000ac + Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TBMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TBMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + POWMAN + 0x000000b0 + Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, POWMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, POWMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TRNG + 0x000000b4 + Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TRNG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TRNG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SHA256 + 0x000000b8 + Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SHA256 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SHA256 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSCFG + 0x000000bc + Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSCFG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CLOCKS + 0x000000c0 + Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CLOCKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XOSC + 0x000000c4 + Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XOSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XOSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ROSC + 0x000000c8 + Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_SYS + 0x000000cc + Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_SYS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_USB + 0x000000d0 + Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_USB can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TICKS + 0x000000d4 + Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TICKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TICKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + WATCHDOG + 0x000000d8 + Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, WATCHDOG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RSM + 0x000000dc + Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RSM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RSM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_CTRL + 0x000000e0 + Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_QMI + 0x000000e4 + Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_QMI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_AUX + 0x000000e8 + Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_AUX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + + + UART0 + 0x40070000 + + 0 + 4096 + registers + + + UART0_IRQ + 33 + + + + UARTDR + 0x00000000 + Data Register, UARTDR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + 0x00000004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + 0x00000018 + Flag Register, UARTFR + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + 0x00000020 + IrDA Low-Power Counter Register, UARTILPR + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + 0x00000024 + Integer Baud Rate Register, UARTIBRD + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + 0x00000028 + Fractional Baud Rate Register, UARTFBRD + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + 0x0000002c + Line Control Register, UARTLCR_H + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + 0x00000030 + Control Register, UARTCR + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + 0x00000034 + Interrupt FIFO Level Select Register, UARTIFLS + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + 0x00000038 + Interrupt Mask Set/Clear Register, UARTIMSC + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + 0x0000003c + Raw Interrupt Status Register, UARTRIS + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + 0x00000040 + Masked Interrupt Status Register, UARTMIS + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + 0x00000044 + Interrupt Clear Register, UARTICR + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + 0x00000048 + DMA Control Register, UARTDMACR + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + 0x00000fe0 + UARTPeriphID0 Register + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + 0x00000fe4 + UARTPeriphID1 Register + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + 0x00000fe8 + UARTPeriphID2 Register + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + 0x00000fec + UARTPeriphID3 Register + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + 0x00000ff0 + UARTPCellID0 Register + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + 0x00000ff4 + UARTPCellID1 Register + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + 0x00000ff8 + UARTPCellID2 Register + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + 0x00000ffc + UARTPCellID3 Register + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40078000 + + UART1_IRQ + 34 + + + + ROSC + 0x400e8000 + + 0 + 40 + registers + + + + CTRL + 0x00000000 + Ring Oscillator control + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + 0x00000004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1_RANDOM + Randomises the stage 1 drive strength + [7:7] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0_RANDOM + Randomises the stage 0 drive strength + [3:3] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + 0x00000008 + For a detailed description see freqa register + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + RANDOM + 0x0000000c + Loads a value to the LFSR randomiser + 0x3f04b16d + + + SEED + [31:0] + read-write + + + + + DORMANT + 0x00000010 + Ring Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + 0x00000014 + Controls the output divider + 0x00000000 + + + DIV + set to 0xaa00 + div where + div = 0 divides by 128 + div = 1-127 divides by div + any other value sets div=128 + this register resets to div=32 + [15:0] + read-write + + + PASS + 43520 + + + + + + + PHASE + 0x00000018 + Controls the phase shifted output + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + 0x0000001c + Ring Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + 0x00000020 + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + 0x00000024 + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + POWMAN + Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use + 0x40100000 + + 0 + 240 + registers + + + POWMAN_IRQ_POW + 44 + + + POWMAN_IRQ_TIMER + 45 + + + + BADPASSWD + 0x00000000 + Indicates a bad password has been used + 0x00000000 + + + BADPASSWD + [0:0] + read-write + oneToClear + + + + + VREG_CTRL + 0x00000004 + Voltage Regulator Control + 0x00008050 + + + RST_N + returns the regulator to its startup settings + 0 - reset + 1 - not reset (default) + [15:15] + read-write + + + UNLOCK + unlocks the VREG control interface after power up + 0 - Locked (default) + 1 - Unlocked + It cannot be relocked when it is unlocked. + [13:13] + read-write + + + ISOLATE + isolates the VREG control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + DISABLE_VOLTAGE_LIMIT + 0=not disabled, 1=enabled + [8:8] + read-write + + + HT_TH + high temperature protection threshold + regulator power transistors are disabled when junction temperature exceeds threshold + 000 - 100C + 001 - 105C + 010 - 110C + 011 - 115C + 100 - 120C + 101 - 125C + 110 - 135C + 111 - 150C + [6:4] + read-write + + + + + VREG_STS + 0x00000008 + Voltage Regulator Status + 0x00000000 + + + VOUT_OK + output regulation status + 0=not in regulation, 1=in regulation + [4:4] + read-only + + + STARTUP + startup status + 0=startup complete, 1=starting up + [0:0] + read-only + + + + + VREG + 0x0000000c + Voltage Regulator Settings + 0x000000b0 + + + UPDATE_IN_PROGRESS + regulator state is being updated + writes to the vreg register will be ignored when this field is set + [15:15] + read-only + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_ENTRY + 0x00000010 + Voltage Regulator Low Power Entry Settings + 0x000000b4 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_EXIT + 0x00000014 + Voltage Regulator Low Power Exit Settings + 0x000000b0 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + BOD_CTRL + 0x00000018 + Brown-out Detection Control + 0x00000000 + + + ISOLATE + isolates the brown-out detection control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + + + BOD + 0x0000001c + Brown-out Detection Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_ENTRY + 0x00000020 + Brown-out Detection Low Power Entry Settings + 0x000000b0 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_EXIT + 0x00000024 + Brown-out Detection Low Power Exit Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + LPOSC + 0x00000028 + Low power oscillator control register. + 0x00000203 + + + TRIM + Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% + [9:4] + read-write + + + MODE + This feature has been removed + [1:0] + read-write + + + + + CHIP_RESET + 0x0000002c + Chip reset control and status + 0x00000000 + + + HAD_WATCHDOG_RESET_RSM + Last reset was a watchdog timeout which was configured to reset the power-on state machine + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [28:28] + read-only + + + HAD_HZD_SYS_RESET_REQ + Last reset was a system reset from the hazard debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [27:27] + read-only + + + HAD_GLITCH_DETECT + Last reset was due to a power supply glitch + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [26:26] + read-only + + + HAD_SWCORE_PD + Last reset was a switched core powerdown + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [25:25] + read-only + + + HAD_WATCHDOG_RESET_SWCORE + Last reset was a watchdog timeout which was configured to reset the switched-core + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [24:24] + read-only + + + HAD_WATCHDOG_RESET_POWMAN + Last reset was a watchdog timeout which was configured to reset the power manager + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [23:23] + read-only + + + HAD_WATCHDOG_RESET_POWMAN_ASYNC + Last reset was a watchdog timeout which was configured to reset the power manager asynchronously + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [22:22] + read-only + + + HAD_RESCUE + Last reset was a rescue reset from the debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no, it sets this flag + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [21:21] + read-only + + + HAD_DP_RESET_REQ + Last reset was an reset request from the arm debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [19:19] + read-only + + + HAD_RUN_LOW + Last reset was from the RUN pin + This resets: + double_tap flag no + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [18:18] + read-only + + + HAD_BOR + Last reset was from the brown-out detection block + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [17:17] + read-only + + + HAD_POR + Last reset was from the power-on reset + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [16:16] + read-only + + + RESCUE_FLAG + This is set by a rescue reset from the RP-AP. + Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. + The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. + [4:4] + read-write + oneToClear + + + DOUBLE_TAP + This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. + [0:0] + read-write + + + + + WDSEL + 0x00000030 + Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). + Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + 0x00000000 + + + RESET_RSM + If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a reset from a glitch detector + [12:12] + read-write + + + RESET_SWCORE + If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain + [8:8] + read-write + + + RESET_POWMAN + If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain + and run the full power-on state machine (PSM) sequence + This relies on clk_ref running. Use reset_powman_async if that may not be true + [4:4] + read-write + + + RESET_POWMAN_ASYNC + If set to 1, a watchdog reset will restore powman defaults, reset the timer, + reset the switched core domain and run the full power-on state machine (PSM) sequence + This does not rely on clk_ref running + [0:0] + read-write + + + + + SEQ_CFG + 0x00000034 + For configuration of the power sequencer + Writes are ignored while POWMAN_STATE_CHANGING=1 + 0x001011f0 + + + USING_FAST_POWCK + 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) + 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) + [20:20] + read-only + + + USING_BOD_LP + Indicates the brown-out detector (BOD) mode + 0 = BOD high power mode which is the default + 1 = BOD low power mode + [17:17] + read-only + + + USING_VREG_LP + Indicates the voltage regulator (VREG) mode + 0 = VREG high power mode which is the default + 1 = VREG low power mode + [16:16] + read-only + + + USE_FAST_POWCK + selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. + 0 always run the POWMAN clock from the slow clock (lposc) + 1 run the POWMAN clock from the fast clock when available + This setting takes effect when a power up sequence is next run + [12:12] + read-write + + + RUN_LPOSC_IN_LP + Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer + This setting takes effect when the swcore is next powered down + [8:8] + read-write + + + USE_BOD_HP + Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [7:7] + read-write + + + USE_BOD_LP + Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [6:6] + read-write + + + USE_VREG_HP + Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [5:5] + read-write + + + USE_VREG_LP + Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [4:4] + read-write + + + HW_PWRUP_SRAM0 + Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [1:1] + read-write + + + HW_PWRUP_SRAM1 + Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [0:0] + read-write + + + + + STATE + 0x00000038 + This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. + To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + defined in the datasheet: + bit 3 = SWCORE + bit 2 = XIP cache + bit 1 = SRAM0 + bit 0 = SRAM1 + 0 = powered up + 1 = powered down + When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + 0x0000000f + + + CHANGING + [13:13] + read-only + + + WAITING + [12:12] + read-only + + + BAD_HW_REQ + Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) + [11:11] + read-only + + + BAD_SW_REQ + Bad software initiated state request. No action taken. + [10:10] + read-only + + + PWRUP_WHILE_WAITING + Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. + [9:9] + read-write + oneToClear + + + REQ_IGNORED + [8:8] + read-write + oneToClear + + + REQ + [7:4] + read-write + + + CURRENT + [3:0] + read-only + + + + + POW_FASTDIV + 0x0000003c + 0x00000040 + + + POW_FASTDIV + divides the POWMAN clock to provide a tick for the delay module and state machines + when clk_pow is running from the slow clock it is not divided + when clk_pow is running from the fast clock it is divided by tick_div + [10:0] + read-write + + + + + POW_DELAY + 0x00000040 + power state machine delays + 0x00002011 + + + SRAM_STEP + timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + [15:8] + read-write + + + XIP_STEP + timing between the xip power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [7:4] + read-write + + + SWCORE_STEP + timing between the swcore power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [3:0] + read-write + + + + + EXT_CTRL0 + 0x00000044 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_CTRL1 + 0x00000048 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_TIME_REF + 0x0000004c + Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + 0x00000000 + + + DRIVE_LPCK + Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + [4:4] + read-write + + + SOURCE_SEL + 0 -> gpio12 + 1 -> gpio20 + 2 -> gpio14 + 3 -> gpio22 + [1:0] + read-write + + + + + LPOSC_FREQ_KHZ_INT + 0x00000050 + Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + 0x00000020 + + + LPOSC_FREQ_KHZ_INT + Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [5:0] + read-write + + + + + LPOSC_FREQ_KHZ_FRAC + 0x00000054 + Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + 0x0000c49c + + + LPOSC_FREQ_KHZ_FRAC + Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_INT + 0x00000058 + Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + 0x00002ee0 + + + XOSC_FREQ_KHZ_INT + Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_FRAC + 0x0000005c + Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + 0x00000000 + + + XOSC_FREQ_KHZ_FRAC + Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + SET_TIME_63TO48 + 0x00000060 + 0x00000000 + + + SET_TIME_63TO48 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_47TO32 + 0x00000064 + 0x00000000 + + + SET_TIME_47TO32 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_31TO16 + 0x00000068 + 0x00000000 + + + SET_TIME_31TO16 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_15TO0 + 0x0000006c + 0x00000000 + + + SET_TIME_15TO0 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + READ_TIME_UPPER + 0x00000070 + 0x00000000 + + + READ_TIME_UPPER + For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. + [31:0] + read-only + + + + + READ_TIME_LOWER + 0x00000074 + 0x00000000 + + + READ_TIME_LOWER + For reading bits 31:0 of the timer. + [31:0] + read-only + + + + + ALARM_TIME_63TO48 + 0x00000078 + 0x00000000 + + + ALARM_TIME_63TO48 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_47TO32 + 0x0000007c + 0x00000000 + + + ALARM_TIME_47TO32 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_31TO16 + 0x00000080 + 0x00000000 + + + ALARM_TIME_31TO16 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_15TO0 + 0x00000084 + 0x00000000 + + + ALARM_TIME_15TO0 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + TIMER + 0x00000088 + 0x00000000 + + + USING_GPIO_1HZ + Timer is synchronised to a 1hz gpio source + [19:19] + read-only + + + USING_GPIO_1KHZ + Timer is running from a 1khz gpio source + [18:18] + read-only + + + USING_LPOSC + Timer is running from lposc + [17:17] + read-only + + + USING_XOSC + Timer is running from xosc + [16:16] + read-only + + + USE_GPIO_1HZ + Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. + [13:13] + read-write + + + USE_GPIO_1KHZ + switch to gpio as the source of the 1kHz timer tick + [10:10] + write-only + + + USE_XOSC + switch to xosc as the source of the 1kHz timer tick + [9:9] + write-only + + + USE_LPOSC + Switch to lposc as the source of the 1kHz timer tick + [8:8] + write-only + + + ALARM + Alarm has fired. Write to 1 to clear the alarm. + [6:6] + read-write + oneToClear + + + PWRUP_ON_ALARM + Alarm wakes the chip from low power mode + [5:5] + read-write + + + ALARM_ENAB + Enables the alarm. The alarm must be disabled while writing the alarm time. + [4:4] + read-write + + + CLEAR + Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. + [2:2] + write-only + + + RUN + Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. + + Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. + + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + [1:1] + read-write + + + NONSEC_WRITE + Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. + [0:0] + read-write + + + + + PWRUP0 + 0x0000008c + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP1 + 0x00000090 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP2 + 0x00000094 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP3 + 0x00000098 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + CURRENT_PWRUP_REQ + 0x0000009c + Indicates current powerup request state + pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + CURRENT_PWRUP_REQ + [6:0] + read-only + + + + + LAST_SWCORE_PWRUP + 0x000000a0 + Indicates which pwrup source triggered the last switched-core power up + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + LAST_SWCORE_PWRUP + [6:0] + read-only + + + + + DBG_PWRCFG + 0x000000a4 + 0x00000000 + + + IGNORE + Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req + [0:0] + read-write + + + + + BOOTDIS + 0x000000a8 + Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the OTP BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. + [1:1] + read-write + + + NOW + When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + DBGCONFIG + 0x000000ac + 0x00000000 + + + DP_INSTID + Configure DP instance ID for SWD multidrop selection. + Recommend that this is NOT changed until you require debug access in multi-chip environment + [3:0] + read-write + + + + + SCRATCH0 + 0x000000b0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x000000b4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x000000b8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x000000bc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x000000c0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x000000c4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x000000c8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x000000cc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + BOOT0 + 0x000000d0 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT0 + [31:0] + read-write + + + + + BOOT1 + 0x000000d4 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT1 + [31:0] + read-write + + + + + BOOT2 + 0x000000d8 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT2 + [31:0] + read-write + + + + + BOOT3 + 0x000000dc + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT3 + [31:0] + read-write + + + + + INTR + 0x000000e0 + Raw Interrupts + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-write + oneToClear + + + + + INTE + 0x000000e4 + Interrupt Enable + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTF + 0x000000e8 + Interrupt Force + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTS + 0x000000ec + Interrupt status after masking & forcing + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-only + + + + + + + WATCHDOG + 0x400d8000 + + 0 + 44 + registers + + + + CTRL + 0x00000000 + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the time in usec before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + 0x00000004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + 0x00000008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + 0x0000000c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x00000010 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x00000014 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x00000018 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x0000001c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x00000020 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x00000024 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x00000028 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0 + 3016 + registers + + + DMA_IRQ_0 + 10 + + + DMA_IRQ_1 + 11 + + + DMA_IRQ_2 + 12 + + + DMA_IRQ_3 + 13 + + + + CH0_READ_ADDR + 0x00000000 + DMA Channel 0 Read Address pointer + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH0_WRITE_ADDR + 0x00000004 + DMA Channel 0 Write Address pointer + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH0_TRANS_COUNT + 0x00000008 + DMA Channel 0 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH0_CTRL_TRIG + 0x0000000c + DMA Channel 0 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + 0x00000010 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL1_CTRL + [31:0] + read-write + + + + + CH0_AL1_READ_ADDR + 0x00000014 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH0_AL1_WRITE_ADDR + 0x00000018 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL1_TRANS_COUNT_TRIG + 0x0000001c + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH0_AL2_CTRL + 0x00000020 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL2_CTRL + [31:0] + read-write + + + + + CH0_AL2_TRANS_COUNT + 0x00000024 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL2_READ_ADDR + 0x00000028 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH0_AL2_WRITE_ADDR_TRIG + 0x0000002c + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH0_AL3_CTRL + 0x00000030 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL3_CTRL + [31:0] + read-write + + + + + CH0_AL3_WRITE_ADDR + 0x00000034 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL3_TRANS_COUNT + 0x00000038 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL3_READ_ADDR_TRIG + 0x0000003c + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH1_READ_ADDR + 0x00000040 + DMA Channel 1 Read Address pointer + 0x00000000 + + + CH1_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH1_WRITE_ADDR + 0x00000044 + DMA Channel 1 Write Address pointer + 0x00000000 + + + CH1_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH1_TRANS_COUNT + 0x00000048 + DMA Channel 1 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH1_CTRL_TRIG + 0x0000004c + DMA Channel 1 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + 0x00000050 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL1_CTRL + [31:0] + read-write + + + + + CH1_AL1_READ_ADDR + 0x00000054 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL1_READ_ADDR + [31:0] + read-write + + + + + CH1_AL1_WRITE_ADDR + 0x00000058 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL1_TRANS_COUNT_TRIG + 0x0000005c + Alias for channel 1 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH1_AL2_CTRL + 0x00000060 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL2_CTRL + [31:0] + read-write + + + + + CH1_AL2_TRANS_COUNT + 0x00000064 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL2_READ_ADDR + 0x00000068 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL2_READ_ADDR + [31:0] + read-write + + + + + CH1_AL2_WRITE_ADDR_TRIG + 0x0000006c + Alias for channel 1 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH1_AL3_CTRL + 0x00000070 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL3_CTRL + [31:0] + read-write + + + + + CH1_AL3_WRITE_ADDR + 0x00000074 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL3_TRANS_COUNT + 0x00000078 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL3_READ_ADDR_TRIG + 0x0000007c + Alias for channel 1 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH2_READ_ADDR + 0x00000080 + DMA Channel 2 Read Address pointer + 0x00000000 + + + CH2_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH2_WRITE_ADDR + 0x00000084 + DMA Channel 2 Write Address pointer + 0x00000000 + + + CH2_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH2_TRANS_COUNT + 0x00000088 + DMA Channel 2 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH2_CTRL_TRIG + 0x0000008c + DMA Channel 2 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + 0x00000090 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL1_CTRL + [31:0] + read-write + + + + + CH2_AL1_READ_ADDR + 0x00000094 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL1_READ_ADDR + [31:0] + read-write + + + + + CH2_AL1_WRITE_ADDR + 0x00000098 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL1_TRANS_COUNT_TRIG + 0x0000009c + Alias for channel 2 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH2_AL2_CTRL + 0x000000a0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL2_CTRL + [31:0] + read-write + + + + + CH2_AL2_TRANS_COUNT + 0x000000a4 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL2_READ_ADDR + 0x000000a8 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL2_READ_ADDR + [31:0] + read-write + + + + + CH2_AL2_WRITE_ADDR_TRIG + 0x000000ac + Alias for channel 2 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH2_AL3_CTRL + 0x000000b0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL3_CTRL + [31:0] + read-write + + + + + CH2_AL3_WRITE_ADDR + 0x000000b4 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL3_TRANS_COUNT + 0x000000b8 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL3_READ_ADDR_TRIG + 0x000000bc + Alias for channel 2 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH3_READ_ADDR + 0x000000c0 + DMA Channel 3 Read Address pointer + 0x00000000 + + + CH3_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH3_WRITE_ADDR + 0x000000c4 + DMA Channel 3 Write Address pointer + 0x00000000 + + + CH3_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH3_TRANS_COUNT + 0x000000c8 + DMA Channel 3 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH3_CTRL_TRIG + 0x000000cc + DMA Channel 3 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + 0x000000d0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL1_CTRL + [31:0] + read-write + + + + + CH3_AL1_READ_ADDR + 0x000000d4 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL1_READ_ADDR + [31:0] + read-write + + + + + CH3_AL1_WRITE_ADDR + 0x000000d8 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL1_TRANS_COUNT_TRIG + 0x000000dc + Alias for channel 3 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH3_AL2_CTRL + 0x000000e0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL2_CTRL + [31:0] + read-write + + + + + CH3_AL2_TRANS_COUNT + 0x000000e4 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL2_READ_ADDR + 0x000000e8 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL2_READ_ADDR + [31:0] + read-write + + + + + CH3_AL2_WRITE_ADDR_TRIG + 0x000000ec + Alias for channel 3 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH3_AL3_CTRL + 0x000000f0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL3_CTRL + [31:0] + read-write + + + + + CH3_AL3_WRITE_ADDR + 0x000000f4 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL3_TRANS_COUNT + 0x000000f8 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL3_READ_ADDR_TRIG + 0x000000fc + Alias for channel 3 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH4_READ_ADDR + 0x00000100 + DMA Channel 4 Read Address pointer + 0x00000000 + + + CH4_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH4_WRITE_ADDR + 0x00000104 + DMA Channel 4 Write Address pointer + 0x00000000 + + + CH4_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH4_TRANS_COUNT + 0x00000108 + DMA Channel 4 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH4_CTRL_TRIG + 0x0000010c + DMA Channel 4 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + 0x00000110 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL1_CTRL + [31:0] + read-write + + + + + CH4_AL1_READ_ADDR + 0x00000114 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL1_READ_ADDR + [31:0] + read-write + + + + + CH4_AL1_WRITE_ADDR + 0x00000118 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL1_TRANS_COUNT_TRIG + 0x0000011c + Alias for channel 4 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH4_AL2_CTRL + 0x00000120 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL2_CTRL + [31:0] + read-write + + + + + CH4_AL2_TRANS_COUNT + 0x00000124 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL2_READ_ADDR + 0x00000128 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL2_READ_ADDR + [31:0] + read-write + + + + + CH4_AL2_WRITE_ADDR_TRIG + 0x0000012c + Alias for channel 4 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH4_AL3_CTRL + 0x00000130 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL3_CTRL + [31:0] + read-write + + + + + CH4_AL3_WRITE_ADDR + 0x00000134 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL3_TRANS_COUNT + 0x00000138 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL3_READ_ADDR_TRIG + 0x0000013c + Alias for channel 4 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH5_READ_ADDR + 0x00000140 + DMA Channel 5 Read Address pointer + 0x00000000 + + + CH5_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH5_WRITE_ADDR + 0x00000144 + DMA Channel 5 Write Address pointer + 0x00000000 + + + CH5_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH5_TRANS_COUNT + 0x00000148 + DMA Channel 5 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH5_CTRL_TRIG + 0x0000014c + DMA Channel 5 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + 0x00000150 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL1_CTRL + [31:0] + read-write + + + + + CH5_AL1_READ_ADDR + 0x00000154 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL1_READ_ADDR + [31:0] + read-write + + + + + CH5_AL1_WRITE_ADDR + 0x00000158 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL1_TRANS_COUNT_TRIG + 0x0000015c + Alias for channel 5 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH5_AL2_CTRL + 0x00000160 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL2_CTRL + [31:0] + read-write + + + + + CH5_AL2_TRANS_COUNT + 0x00000164 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL2_READ_ADDR + 0x00000168 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL2_READ_ADDR + [31:0] + read-write + + + + + CH5_AL2_WRITE_ADDR_TRIG + 0x0000016c + Alias for channel 5 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH5_AL3_CTRL + 0x00000170 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL3_CTRL + [31:0] + read-write + + + + + CH5_AL3_WRITE_ADDR + 0x00000174 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL3_TRANS_COUNT + 0x00000178 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL3_READ_ADDR_TRIG + 0x0000017c + Alias for channel 5 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH6_READ_ADDR + 0x00000180 + DMA Channel 6 Read Address pointer + 0x00000000 + + + CH6_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH6_WRITE_ADDR + 0x00000184 + DMA Channel 6 Write Address pointer + 0x00000000 + + + CH6_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH6_TRANS_COUNT + 0x00000188 + DMA Channel 6 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH6_CTRL_TRIG + 0x0000018c + DMA Channel 6 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + 0x00000190 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL1_CTRL + [31:0] + read-write + + + + + CH6_AL1_READ_ADDR + 0x00000194 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL1_READ_ADDR + [31:0] + read-write + + + + + CH6_AL1_WRITE_ADDR + 0x00000198 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL1_TRANS_COUNT_TRIG + 0x0000019c + Alias for channel 6 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH6_AL2_CTRL + 0x000001a0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL2_CTRL + [31:0] + read-write + + + + + CH6_AL2_TRANS_COUNT + 0x000001a4 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL2_READ_ADDR + 0x000001a8 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL2_READ_ADDR + [31:0] + read-write + + + + + CH6_AL2_WRITE_ADDR_TRIG + 0x000001ac + Alias for channel 6 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH6_AL3_CTRL + 0x000001b0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL3_CTRL + [31:0] + read-write + + + + + CH6_AL3_WRITE_ADDR + 0x000001b4 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL3_TRANS_COUNT + 0x000001b8 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL3_READ_ADDR_TRIG + 0x000001bc + Alias for channel 6 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH7_READ_ADDR + 0x000001c0 + DMA Channel 7 Read Address pointer + 0x00000000 + + + CH7_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH7_WRITE_ADDR + 0x000001c4 + DMA Channel 7 Write Address pointer + 0x00000000 + + + CH7_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH7_TRANS_COUNT + 0x000001c8 + DMA Channel 7 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH7_CTRL_TRIG + 0x000001cc + DMA Channel 7 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + 0x000001d0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL1_CTRL + [31:0] + read-write + + + + + CH7_AL1_READ_ADDR + 0x000001d4 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL1_READ_ADDR + [31:0] + read-write + + + + + CH7_AL1_WRITE_ADDR + 0x000001d8 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL1_TRANS_COUNT_TRIG + 0x000001dc + Alias for channel 7 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH7_AL2_CTRL + 0x000001e0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL2_CTRL + [31:0] + read-write + + + + + CH7_AL2_TRANS_COUNT + 0x000001e4 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL2_READ_ADDR + 0x000001e8 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL2_READ_ADDR + [31:0] + read-write + + + + + CH7_AL2_WRITE_ADDR_TRIG + 0x000001ec + Alias for channel 7 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH7_AL3_CTRL + 0x000001f0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL3_CTRL + [31:0] + read-write + + + + + CH7_AL3_WRITE_ADDR + 0x000001f4 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL3_TRANS_COUNT + 0x000001f8 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL3_READ_ADDR_TRIG + 0x000001fc + Alias for channel 7 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH8_READ_ADDR + 0x00000200 + DMA Channel 8 Read Address pointer + 0x00000000 + + + CH8_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH8_WRITE_ADDR + 0x00000204 + DMA Channel 8 Write Address pointer + 0x00000000 + + + CH8_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH8_TRANS_COUNT + 0x00000208 + DMA Channel 8 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH8_CTRL_TRIG + 0x0000020c + DMA Channel 8 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + 0x00000210 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL1_CTRL + [31:0] + read-write + + + + + CH8_AL1_READ_ADDR + 0x00000214 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL1_READ_ADDR + [31:0] + read-write + + + + + CH8_AL1_WRITE_ADDR + 0x00000218 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL1_TRANS_COUNT_TRIG + 0x0000021c + Alias for channel 8 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH8_AL2_CTRL + 0x00000220 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL2_CTRL + [31:0] + read-write + + + + + CH8_AL2_TRANS_COUNT + 0x00000224 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL2_READ_ADDR + 0x00000228 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL2_READ_ADDR + [31:0] + read-write + + + + + CH8_AL2_WRITE_ADDR_TRIG + 0x0000022c + Alias for channel 8 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH8_AL3_CTRL + 0x00000230 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL3_CTRL + [31:0] + read-write + + + + + CH8_AL3_WRITE_ADDR + 0x00000234 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL3_TRANS_COUNT + 0x00000238 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL3_READ_ADDR_TRIG + 0x0000023c + Alias for channel 8 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH9_READ_ADDR + 0x00000240 + DMA Channel 9 Read Address pointer + 0x00000000 + + + CH9_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH9_WRITE_ADDR + 0x00000244 + DMA Channel 9 Write Address pointer + 0x00000000 + + + CH9_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH9_TRANS_COUNT + 0x00000248 + DMA Channel 9 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH9_CTRL_TRIG + 0x0000024c + DMA Channel 9 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + 0x00000250 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL1_CTRL + [31:0] + read-write + + + + + CH9_AL1_READ_ADDR + 0x00000254 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL1_READ_ADDR + [31:0] + read-write + + + + + CH9_AL1_WRITE_ADDR + 0x00000258 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL1_TRANS_COUNT_TRIG + 0x0000025c + Alias for channel 9 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH9_AL2_CTRL + 0x00000260 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL2_CTRL + [31:0] + read-write + + + + + CH9_AL2_TRANS_COUNT + 0x00000264 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL2_READ_ADDR + 0x00000268 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL2_READ_ADDR + [31:0] + read-write + + + + + CH9_AL2_WRITE_ADDR_TRIG + 0x0000026c + Alias for channel 9 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH9_AL3_CTRL + 0x00000270 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL3_CTRL + [31:0] + read-write + + + + + CH9_AL3_WRITE_ADDR + 0x00000274 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL3_TRANS_COUNT + 0x00000278 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL3_READ_ADDR_TRIG + 0x0000027c + Alias for channel 9 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH10_READ_ADDR + 0x00000280 + DMA Channel 10 Read Address pointer + 0x00000000 + + + CH10_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH10_WRITE_ADDR + 0x00000284 + DMA Channel 10 Write Address pointer + 0x00000000 + + + CH10_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH10_TRANS_COUNT + 0x00000288 + DMA Channel 10 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH10_CTRL_TRIG + 0x0000028c + DMA Channel 10 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + 0x00000290 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL1_CTRL + [31:0] + read-write + + + + + CH10_AL1_READ_ADDR + 0x00000294 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL1_READ_ADDR + [31:0] + read-write + + + + + CH10_AL1_WRITE_ADDR + 0x00000298 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL1_TRANS_COUNT_TRIG + 0x0000029c + Alias for channel 10 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH10_AL2_CTRL + 0x000002a0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL2_CTRL + [31:0] + read-write + + + + + CH10_AL2_TRANS_COUNT + 0x000002a4 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL2_READ_ADDR + 0x000002a8 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL2_READ_ADDR + [31:0] + read-write + + + + + CH10_AL2_WRITE_ADDR_TRIG + 0x000002ac + Alias for channel 10 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH10_AL3_CTRL + 0x000002b0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL3_CTRL + [31:0] + read-write + + + + + CH10_AL3_WRITE_ADDR + 0x000002b4 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL3_TRANS_COUNT + 0x000002b8 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL3_READ_ADDR_TRIG + 0x000002bc + Alias for channel 10 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH11_READ_ADDR + 0x000002c0 + DMA Channel 11 Read Address pointer + 0x00000000 + + + CH11_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH11_WRITE_ADDR + 0x000002c4 + DMA Channel 11 Write Address pointer + 0x00000000 + + + CH11_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH11_TRANS_COUNT + 0x000002c8 + DMA Channel 11 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH11_CTRL_TRIG + 0x000002cc + DMA Channel 11 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + 0x000002d0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL1_CTRL + [31:0] + read-write + + + + + CH11_AL1_READ_ADDR + 0x000002d4 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL1_READ_ADDR + [31:0] + read-write + + + + + CH11_AL1_WRITE_ADDR + 0x000002d8 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL1_TRANS_COUNT_TRIG + 0x000002dc + Alias for channel 11 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH11_AL2_CTRL + 0x000002e0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL2_CTRL + [31:0] + read-write + + + + + CH11_AL2_TRANS_COUNT + 0x000002e4 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL2_READ_ADDR + 0x000002e8 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL2_READ_ADDR + [31:0] + read-write + + + + + CH11_AL2_WRITE_ADDR_TRIG + 0x000002ec + Alias for channel 11 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH11_AL3_CTRL + 0x000002f0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL3_CTRL + [31:0] + read-write + + + + + CH11_AL3_WRITE_ADDR + 0x000002f4 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL3_TRANS_COUNT + 0x000002f8 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL3_READ_ADDR_TRIG + 0x000002fc + Alias for channel 11 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH12_READ_ADDR + 0x00000300 + DMA Channel 12 Read Address pointer + 0x00000000 + + + CH12_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH12_WRITE_ADDR + 0x00000304 + DMA Channel 12 Write Address pointer + 0x00000000 + + + CH12_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH12_TRANS_COUNT + 0x00000308 + DMA Channel 12 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH12_CTRL_TRIG + 0x0000030c + DMA Channel 12 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH12_AL1_CTRL + 0x00000310 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL1_CTRL + [31:0] + read-write + + + + + CH12_AL1_READ_ADDR + 0x00000314 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL1_READ_ADDR + [31:0] + read-write + + + + + CH12_AL1_WRITE_ADDR + 0x00000318 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL1_TRANS_COUNT_TRIG + 0x0000031c + Alias for channel 12 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH12_AL2_CTRL + 0x00000320 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL2_CTRL + [31:0] + read-write + + + + + CH12_AL2_TRANS_COUNT + 0x00000324 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL2_READ_ADDR + 0x00000328 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL2_READ_ADDR + [31:0] + read-write + + + + + CH12_AL2_WRITE_ADDR_TRIG + 0x0000032c + Alias for channel 12 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH12_AL3_CTRL + 0x00000330 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL3_CTRL + [31:0] + read-write + + + + + CH12_AL3_WRITE_ADDR + 0x00000334 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL3_TRANS_COUNT + 0x00000338 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL3_READ_ADDR_TRIG + 0x0000033c + Alias for channel 12 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH13_READ_ADDR + 0x00000340 + DMA Channel 13 Read Address pointer + 0x00000000 + + + CH13_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH13_WRITE_ADDR + 0x00000344 + DMA Channel 13 Write Address pointer + 0x00000000 + + + CH13_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH13_TRANS_COUNT + 0x00000348 + DMA Channel 13 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH13_CTRL_TRIG + 0x0000034c + DMA Channel 13 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH13_AL1_CTRL + 0x00000350 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL1_CTRL + [31:0] + read-write + + + + + CH13_AL1_READ_ADDR + 0x00000354 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL1_READ_ADDR + [31:0] + read-write + + + + + CH13_AL1_WRITE_ADDR + 0x00000358 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL1_TRANS_COUNT_TRIG + 0x0000035c + Alias for channel 13 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH13_AL2_CTRL + 0x00000360 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL2_CTRL + [31:0] + read-write + + + + + CH13_AL2_TRANS_COUNT + 0x00000364 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL2_READ_ADDR + 0x00000368 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL2_READ_ADDR + [31:0] + read-write + + + + + CH13_AL2_WRITE_ADDR_TRIG + 0x0000036c + Alias for channel 13 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH13_AL3_CTRL + 0x00000370 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL3_CTRL + [31:0] + read-write + + + + + CH13_AL3_WRITE_ADDR + 0x00000374 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL3_TRANS_COUNT + 0x00000378 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL3_READ_ADDR_TRIG + 0x0000037c + Alias for channel 13 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH14_READ_ADDR + 0x00000380 + DMA Channel 14 Read Address pointer + 0x00000000 + + + CH14_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH14_WRITE_ADDR + 0x00000384 + DMA Channel 14 Write Address pointer + 0x00000000 + + + CH14_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH14_TRANS_COUNT + 0x00000388 + DMA Channel 14 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH14_CTRL_TRIG + 0x0000038c + DMA Channel 14 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH14_AL1_CTRL + 0x00000390 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL1_CTRL + [31:0] + read-write + + + + + CH14_AL1_READ_ADDR + 0x00000394 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL1_READ_ADDR + [31:0] + read-write + + + + + CH14_AL1_WRITE_ADDR + 0x00000398 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL1_TRANS_COUNT_TRIG + 0x0000039c + Alias for channel 14 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH14_AL2_CTRL + 0x000003a0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL2_CTRL + [31:0] + read-write + + + + + CH14_AL2_TRANS_COUNT + 0x000003a4 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL2_READ_ADDR + 0x000003a8 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL2_READ_ADDR + [31:0] + read-write + + + + + CH14_AL2_WRITE_ADDR_TRIG + 0x000003ac + Alias for channel 14 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH14_AL3_CTRL + 0x000003b0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL3_CTRL + [31:0] + read-write + + + + + CH14_AL3_WRITE_ADDR + 0x000003b4 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL3_TRANS_COUNT + 0x000003b8 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL3_READ_ADDR_TRIG + 0x000003bc + Alias for channel 14 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH15_READ_ADDR + 0x000003c0 + DMA Channel 15 Read Address pointer + 0x00000000 + + + CH15_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH15_WRITE_ADDR + 0x000003c4 + DMA Channel 15 Write Address pointer + 0x00000000 + + + CH15_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH15_TRANS_COUNT + 0x000003c8 + DMA Channel 15 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH15_CTRL_TRIG + 0x000003cc + DMA Channel 15 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH15_AL1_CTRL + 0x000003d0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL1_CTRL + [31:0] + read-write + + + + + CH15_AL1_READ_ADDR + 0x000003d4 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL1_READ_ADDR + [31:0] + read-write + + + + + CH15_AL1_WRITE_ADDR + 0x000003d8 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL1_TRANS_COUNT_TRIG + 0x000003dc + Alias for channel 15 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH15_AL2_CTRL + 0x000003e0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL2_CTRL + [31:0] + read-write + + + + + CH15_AL2_TRANS_COUNT + 0x000003e4 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL2_READ_ADDR + 0x000003e8 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL2_READ_ADDR + [31:0] + read-write + + + + + CH15_AL2_WRITE_ADDR_TRIG + 0x000003ec + Alias for channel 15 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH15_AL3_CTRL + 0x000003f0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL3_CTRL + [31:0] + read-write + + + + + CH15_AL3_WRITE_ADDR + 0x000003f4 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL3_TRANS_COUNT + 0x000003f8 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL3_READ_ADDR_TRIG + 0x000003fc + Alias for channel 15 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + INTR + 0x00000400 + Interrupt Status (raw) + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE0 + 0x00000404 + Interrupt Enables for IRQ 0 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. + [15:0] + read-write + + + + + INTF0 + 0x00000408 + Force Interrupts + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + 0x0000040c + Interrupt Status for IRQ 0 + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR1 + 0x00000410 + Interrupt Status (raw) + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE1 + 0x00000414 + Interrupt Enables for IRQ 1 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. + [15:0] + read-write + + + + + INTF1 + 0x00000418 + Force Interrupts + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. + [15:0] + read-write + + + + + INTS1 + 0x0000041c + Interrupt Status for IRQ 1 + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR2 + 0x00000420 + Interrupt Status (raw) + 0x00000000 + + + INTR2 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE2 + 0x00000424 + Interrupt Enables for IRQ 2 + 0x00000000 + + + INTE2 + Set bit n to pass interrupts from channel n to DMA IRQ 2. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. + [15:0] + read-write + + + + + INTF2 + 0x00000428 + Force Interrupts + 0x00000000 + + + INTF2 + Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. + [15:0] + read-write + + + + + INTS2 + 0x0000042c + Interrupt Status for IRQ 2 + 0x00000000 + + + INTS2 + Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR3 + 0x00000430 + Interrupt Status (raw) + 0x00000000 + + + INTR3 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE3 + 0x00000434 + Interrupt Enables for IRQ 3 + 0x00000000 + + + INTE3 + Set bit n to pass interrupts from channel n to DMA IRQ 3. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. + [15:0] + read-write + + + + + INTF3 + 0x00000438 + Force Interrupts + 0x00000000 + + + INTF3 + Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. + [15:0] + read-write + + + + + INTS3 + 0x0000043c + Interrupt Status for IRQ 3 + 0x00000000 + + + INTS3 + Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + TIMER0 + 0x00000440 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + 0x00000444 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + 0x00000448 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + 0x0000044c + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + 0x00000450 + Trigger one or more channels simultaneously + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + 0x00000454 + Sniffer Control + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + 0 + Calculate a CRC-32 (IEEE802.3 polynomial) + + + CRC32R + 1 + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + + + CRC16 + 2 + Calculate a CRC-16-CCITT + + + CRC16R + 3 + Calculate a CRC-16-CCITT with bit reversed data + + + EVEN + 14 + XOR reduction over all data. == 1 if the total 1 population count is odd. + + + SUM + 15 + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + 0x00000458 + Data accumulator for sniff hardware + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + 0x00000460 + Debug RAF, WAF, TDF levels + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + 0x00000464 + Abort an in-progress transfer sequence on one or more channels + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + 0x00000468 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + SECCFG_CH0 + 0x00000480 + Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH1 + 0x00000484 + Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH2 + 0x00000488 + Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH3 + 0x0000048c + Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH4 + 0x00000490 + Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH5 + 0x00000494 + Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH6 + 0x00000498 + Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH7 + 0x0000049c + Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH8 + 0x000004a0 + Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH9 + 0x000004a4 + Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH10 + 0x000004a8 + Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH11 + 0x000004ac + Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH12 + 0x000004b0 + Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH13 + 0x000004b4 + Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH14 + 0x000004b8 + Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH15 + 0x000004bc + Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_IRQ0 + 0x000004c0 + Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ1 + 0x000004c4 + Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ2 + 0x000004c8 + Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ3 + 0x000004cc + Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_MISC + 0x000004d0 + Miscellaneous security configuration + 0x000003ff + + + TIMER3_S + If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. + [9:9] + read-write + + + TIMER3_P + If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. + [8:8] + read-write + + + TIMER2_S + If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. + [7:7] + read-write + + + TIMER2_P + If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. + [6:6] + read-write + + + TIMER1_S + If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. + [5:5] + read-write + + + TIMER1_P + If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. + [4:4] + read-write + + + TIMER0_S + If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. + [3:3] + read-write + + + TIMER0_P + If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. + [2:2] + read-write + + + SNIFF_S + If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. + + If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. + [1:1] + read-write + + + SNIFF_P + If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. + + If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. + [0:0] + read-write + + + + + MPU_CTRL + 0x00000500 + Control register for DMA MPU. Accessible only from a Privileged context. + 0x00000000 + + + NS_HIDE_ADDR + By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. + [3:3] + read-write + + + S + Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) + [2:2] + read-write + + + P + Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) + [1:1] + read-write + + + + + MPU_BAR0 + 0x00000504 + Base address register for MPU region 0. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR0 + 0x00000508 + Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR1 + 0x0000050c + Base address register for MPU region 1. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR1 + 0x00000510 + Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR2 + 0x00000514 + Base address register for MPU region 2. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR2 + 0x00000518 + Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR3 + 0x0000051c + Base address register for MPU region 3. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR3 + 0x00000520 + Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR4 + 0x00000524 + Base address register for MPU region 4. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR4 + 0x00000528 + Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR5 + 0x0000052c + Base address register for MPU region 5. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR5 + 0x00000530 + Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR6 + 0x00000534 + Base address register for MPU region 6. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR6 + 0x00000538 + Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR7 + 0x0000053c + Base address register for MPU region 7. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR7 + 0x00000540 + Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + CH0_DBG_CTDREQ + 0x00000800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + 0x00000804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + 0x00000840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + 0x00000844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + 0x00000880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + 0x00000884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + 0x000008c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + 0x000008c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + 0x00000900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + 0x00000904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + 0x00000940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + 0x00000944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + 0x00000980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + 0x00000984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + 0x000009c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + 0x000009c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + 0x00000a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + 0x00000a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + 0x00000a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + 0x00000a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + 0x00000a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + 0x00000a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + 0x00000ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + 0x00000ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + CH12_DBG_CTDREQ + 0x00000b00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH12_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH12_DBG_TCR + 0x00000b04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH12_DBG_TCR + [31:0] + read-only + + + + + CH13_DBG_CTDREQ + 0x00000b40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH13_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH13_DBG_TCR + 0x00000b44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH13_DBG_TCR + [31:0] + read-only + + + + + CH14_DBG_CTDREQ + 0x00000b80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH14_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH14_DBG_TCR + 0x00000b84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH14_DBG_TCR + [31:0] + read-only + + + + + CH15_DBG_CTDREQ + 0x00000bc0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH15_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH15_DBG_TCR + 0x00000bc4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH15_DBG_TCR + [31:0] + read-only + + + + + + + TIMER0 + Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing + 0x400b0000 + + 0 + 76 + registers + + + TIMER0_IRQ_0 + 0 + + + TIMER0_IRQ_1 + 1 + + + TIMER0_IRQ_2 + 2 + + + TIMER0_IRQ_3 + 3 + + + + TIMEHW + 0x00000000 + Write to bits 63:32 of time always write timelw before timehw + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + 0x00000004 + Write to bits 31:0 of time writes do not get copied to time until timehw is written + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + 0x00000008 + Read from bits 63:32 of time always read timelr before timehr + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + 0x0000000c + Read from bits 31:0 of time + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + 0x00000010 + Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + 0x00000014 + Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + 0x00000018 + Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + 0x0000001c + Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + 0x00000020 + Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + 0x00000024 + Raw read from bits 63:32 of time (no side effects) + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + 0x00000028 + Raw read from bits 31:0 of time (no side effects) + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + 0x0000002c + Set bits high to enable pause when the corresponding debug ports are active + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + 0x00000030 + Set high to pause the timer + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + LOCKED + 0x00000034 + Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + 0x00000000 + + + LOCKED + [0:0] + read-write + + + + + SOURCE + 0x00000038 + Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + 0x00000000 + + + CLK_SYS + [0:0] + read-write + + + TICK + 0 + + + CLK_SYS + 1 + + + + + + + INTR + 0x0000003c + Raw Interrupts + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000040 + Interrupt Enable + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + 0x00000044 + Interrupt Force + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + 0x00000048 + Interrupt status after masking & forcing + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + TIMER1 + 0x400b8000 + + TIMER1_IRQ_0 + 4 + + + TIMER1_IRQ_1 + 5 + + + TIMER1_IRQ_2 + 6 + + + TIMER1_IRQ_3 + 7 + + + + PWM + Simple PWM + 0x400a8000 + + 0 + 272 + registers + + + PWM_IRQ_WRAP_0 + 8 + + + PWM_IRQ_WRAP_1 + 9 + + + + CH0_CSR + 0x00000000 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + 0x00000004 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + 0x00000008 + Direct access to the PWM counter + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + 0x0000000c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + 0x00000010 + Counter wrap value + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + 0x00000014 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + 0x00000018 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + 0x0000001c + Direct access to the PWM counter + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + 0x00000020 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + 0x00000024 + Counter wrap value + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + 0x00000028 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + 0x0000002c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + 0x00000030 + Direct access to the PWM counter + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + 0x00000034 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + 0x00000038 + Counter wrap value + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + 0x0000003c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + 0x00000040 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + 0x00000044 + Direct access to the PWM counter + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + 0x00000048 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + 0x0000004c + Counter wrap value + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + 0x00000050 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + 0x00000054 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + 0x00000058 + Direct access to the PWM counter + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + 0x0000005c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + 0x00000060 + Counter wrap value + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + 0x00000064 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + 0x00000068 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + 0x0000006c + Direct access to the PWM counter + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + 0x00000070 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + 0x00000074 + Counter wrap value + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + 0x00000078 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + 0x0000007c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + 0x00000080 + Direct access to the PWM counter + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + 0x00000084 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + 0x00000088 + Counter wrap value + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + 0x0000008c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + 0x00000090 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + 0x00000094 + Direct access to the PWM counter + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + 0x00000098 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + 0x0000009c + Counter wrap value + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + CH8_CSR + 0x000000a0 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH8_DIV + 0x000000a4 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH8_CTR + 0x000000a8 + Direct access to the PWM counter + 0x00000000 + + + CH8_CTR + [15:0] + read-write + + + + + CH8_CC + 0x000000ac + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH8_TOP + 0x000000b0 + Counter wrap value + 0x0000ffff + + + CH8_TOP + [15:0] + read-write + + + + + CH9_CSR + 0x000000b4 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH9_DIV + 0x000000b8 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH9_CTR + 0x000000bc + Direct access to the PWM counter + 0x00000000 + + + CH9_CTR + [15:0] + read-write + + + + + CH9_CC + 0x000000c0 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH9_TOP + 0x000000c4 + Counter wrap value + 0x0000ffff + + + CH9_TOP + [15:0] + read-write + + + + + CH10_CSR + 0x000000c8 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH10_DIV + 0x000000cc + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH10_CTR + 0x000000d0 + Direct access to the PWM counter + 0x00000000 + + + CH10_CTR + [15:0] + read-write + + + + + CH10_CC + 0x000000d4 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH10_TOP + 0x000000d8 + Counter wrap value + 0x0000ffff + + + CH10_TOP + [15:0] + read-write + + + + + CH11_CSR + 0x000000dc + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH11_DIV + 0x000000e0 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH11_CTR + 0x000000e4 + Direct access to the PWM counter + 0x00000000 + + + CH11_CTR + [15:0] + read-write + + + + + CH11_CC + 0x000000e8 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH11_TOP + 0x000000ec + Counter wrap value + 0x0000ffff + + + CH11_TOP + [15:0] + read-write + + + + + EN + 0x000000f0 + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + 0x000000f4 + Raw Interrupts + 0x00000000 + + + CH11 + [11:11] + read-write + oneToClear + + + CH10 + [10:10] + read-write + oneToClear + + + CH9 + [9:9] + read-write + oneToClear + + + CH8 + [8:8] + read-write + oneToClear + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + IRQ0_INTE + 0x000000f8 + Interrupt Enable for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTF + 0x000000fc + Interrupt Force for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000100 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + IRQ1_INTE + 0x00000104 + Interrupt Enable for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000108 + Interrupt Force for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTS + 0x0000010c + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x400a0000 + + 0 + 36 + registers + + + ADC_IRQ_FIFO + 35 + + + + CS + 0x00000000 + ADC Control and Status + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [24:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order + [15:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + 0x00000004 + Result of most recent ADC conversion + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + 0x00000008 + FIFO control and status + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + 0x0000000c + Conversion result FIFO + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + 0x00000010 + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + 0x00000014 + Raw Interrupts + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + 0x00000018 + Interrupt Enable + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + 0x0000001c + Interrupt Force + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + 0x00000020 + Interrupt status after masking & forcing + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40090000 + + 0 + 256 + registers + + + I2C0_IRQ + 36 + + + + IC_CON + 0x00000000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + 0 + Overflow when RX_FIFO is full + + + ENABLED + 1 + Hold bus when RX_FIFO is full + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + 0 + Default behaviour of TX_EMPTY interrupt + + + ENABLED + 1 + Controlled generation of TX_EMPTY interrupt + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + 0 + slave issues STOP_DET intr always + + + ENABLED + 1 + slave issues STOP_DET intr only if addressed + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + 0 + Slave mode is enabled + + + SLAVE_DISABLED + 1 + Slave mode is disabled + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + 0 + Master restart disabled + + + ENABLED + 1 + Master restart enabled + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + 0 + Master 7Bit addressing mode + + + ADDR_10BITS + 1 + Master 10Bit addressing mode + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + 0 + Slave 7Bit addressing + + + ADDR_10BITS + 1 + Slave 10Bit addressing + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + 1 + Standard Speed mode of operation + + + FAST + 2 + Fast or Fast Plus mode of operation + + + HIGH + 3 + High Speed mode of operation + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + 0 + Master mode is disabled + + + ENABLED + 1 + Master mode is enabled + + + + + + + IC_TAR + 0x00000004 + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + 0 + Disables programming of GENERAL_CALL or START_BYTE transmission + + + ENABLED + 1 + Enables programming of GENERAL_CALL or START_BYTE transmission + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + 0 + GENERAL_CALL byte transmission + + + START_BYTE + 1 + START byte transmission + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + 0x00000008 + I2C Slave Address Register + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + 0x00000010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + 0 + Sequential data byte received + + + ACTIVE + 1 + Non sequential data byte received + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + 0 + Don't Issue RESTART before this command + + + ENABLE + 1 + Issue RESTART before this command + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + 0 + Don't Issue STOP after this command + + + ENABLE + 1 + Issue STOP after this command + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + 0 + Master Write Command + + + READ + 1 + Master Read Command + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + 0x00000014 + Standard Speed I2C Clock SCL High Count Register + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + 0x00000018 + Standard Speed I2C Clock SCL Low Count Register + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + 0x0000001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + 0x00000020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + 0x0000002c + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + R_RESTART_DET interrupt is inactive + + + ACTIVE + 1 + R_RESTART_DET interrupt is active + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + R_GEN_CALL interrupt is inactive + + + ACTIVE + 1 + R_GEN_CALL interrupt is active + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + R_START_DET interrupt is inactive + + + ACTIVE + 1 + R_START_DET interrupt is active + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + R_STOP_DET interrupt is inactive + + + ACTIVE + 1 + R_STOP_DET interrupt is active + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + R_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + R_ACTIVITY interrupt is active + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + R_RX_DONE interrupt is inactive + + + ACTIVE + 1 + R_RX_DONE interrupt is active + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + R_TX_ABRT interrupt is inactive + + + ACTIVE + 1 + R_TX_ABRT interrupt is active + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + R_RD_REQ interrupt is inactive + + + ACTIVE + 1 + R_RD_REQ interrupt is active + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + 0 + R_TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + R_TX_EMPTY interrupt is active + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + R_TX_OVER interrupt is inactive + + + ACTIVE + 1 + R_TX_OVER interrupt is active + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + R_RX_FULL interrupt is inactive + + + ACTIVE + 1 + R_RX_FULL interrupt is active + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + R_RX_OVER interrupt is inactive + + + ACTIVE + 1 + R_RX_OVER interrupt is active + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_INTR_MASK + 0x00000030 + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + 0 + RESTART_DET interrupt is masked + + + DISABLED + 1 + RESTART_DET interrupt is unmasked + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + 0 + GEN_CALL interrupt is masked + + + DISABLED + 1 + GEN_CALL interrupt is unmasked + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + 0 + START_DET interrupt is masked + + + DISABLED + 1 + START_DET interrupt is unmasked + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + 0 + STOP_DET interrupt is masked + + + DISABLED + 1 + STOP_DET interrupt is unmasked + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + 0 + ACTIVITY interrupt is masked + + + DISABLED + 1 + ACTIVITY interrupt is unmasked + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + 0 + RX_DONE interrupt is masked + + + DISABLED + 1 + RX_DONE interrupt is unmasked + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + 0 + TX_ABORT interrupt is masked + + + DISABLED + 1 + TX_ABORT interrupt is unmasked + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + 0 + RD_REQ interrupt is masked + + + DISABLED + 1 + RD_REQ interrupt is unmasked + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + 0 + TX_EMPTY interrupt is masked + + + DISABLED + 1 + TX_EMPTY interrupt is unmasked + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + 0 + TX_OVER interrupt is masked + + + DISABLED + 1 + TX_OVER interrupt is unmasked + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + 0 + RX_FULL interrupt is masked + + + DISABLED + 1 + RX_FULL interrupt is unmasked + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + 0 + RX_OVER interrupt is masked + + + DISABLED + 1 + RX_OVER interrupt is unmasked + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + 0 + RX_UNDER interrupt is masked + + + DISABLED + 1 + RX_UNDER interrupt is unmasked + + + + + + + IC_RAW_INTR_STAT + 0x00000034 + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + RESTART_DET interrupt is inactive + + + ACTIVE + 1 + RESTART_DET interrupt is active + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + GEN_CALL interrupt is inactive + + + ACTIVE + 1 + GEN_CALL interrupt is active + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + START_DET interrupt is inactive + + + ACTIVE + 1 + START_DET interrupt is active + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + STOP_DET interrupt is inactive + + + ACTIVE + 1 + STOP_DET interrupt is active + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + RAW_INTR_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + RAW_INTR_ACTIVITY interrupt is active + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + RX_DONE interrupt is inactive + + + ACTIVE + 1 + RX_DONE interrupt is active + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + TX_ABRT interrupt is inactive + + + ACTIVE + 1 + TX_ABRT interrupt is active + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + RD_REQ interrupt is inactive + + + ACTIVE + 1 + RD_REQ interrupt is active + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + 0 + TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + TX_EMPTY interrupt is active + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + TX_OVER interrupt is inactive + + + ACTIVE + 1 + TX_OVER interrupt is active + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + RX_FULL interrupt is inactive + + + ACTIVE + 1 + RX_FULL interrupt is active + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + RX_OVER interrupt is inactive + + + ACTIVE + 1 + RX_OVER interrupt is active + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_RX_TL + 0x00000038 + I2C Receive FIFO Threshold Register + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + 0x0000003c + I2C Transmit FIFO Threshold Register + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + 0x00000040 + Clear Combined and Individual Interrupt Register + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + 0x00000044 + Clear RX_UNDER Interrupt Register + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + 0x00000048 + Clear RX_OVER Interrupt Register + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + 0x0000004c + Clear TX_OVER Interrupt Register + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + 0x00000050 + Clear RD_REQ Interrupt Register + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + 0x00000054 + Clear TX_ABRT Interrupt Register + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + 0x00000058 + Clear RX_DONE Interrupt Register + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + 0x0000005c + Clear ACTIVITY Interrupt Register + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + 0x00000060 + Clear STOP_DET Interrupt Register + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + 0x00000064 + Clear START_DET Interrupt Register + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + 0x00000068 + Clear GEN_CALL Interrupt Register + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + 0x0000006c + I2C Enable Register + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + 0 + Tx Command execution not blocked + + + BLOCKED + 1 + Tx Command execution blocked + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + 0 + ABORT operation not in progress + + + ENABLED + 1 + ABORT operation in progress + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + I2C is disabled + + + ENABLED + 1 + I2C is enabled + + + + + + + IC_STATUS + 0x00000070 + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + 0 + Slave is idle + + + ACTIVE + 1 + Slave not idle + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + 0 + Master is idle + + + ACTIVE + 1 + Master not idle + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + 0 + Rx FIFO not full + + + FULL + 1 + Rx FIFO is full + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + 0 + Rx FIFO is empty + + + NOT_EMPTY + 1 + Rx FIFO not empty + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + 0 + Tx FIFO not empty + + + EMPTY + 1 + Tx FIFO is empty + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + 0 + Tx FIFO is full + + + NOT_FULL + 1 + Tx FIFO not full + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + I2C is idle + + + ACTIVE + 1 + I2C is active + + + + + + + IC_TXFLR + 0x00000074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + 0x00000078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + 0x0000007c + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + 0x00000080 + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + 0 + Transfer abort detected by master- scenario not present + + + ABRT_USER_ABRT_GENERATED + 1 + Transfer abort detected by master + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + 0 + Slave trying to transmit to remote master in read mode- scenario not present + + + ABRT_SLVRD_INTX_GENERATED + 1 + Slave trying to transmit to remote master in read mode + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + 0 + Slave lost arbitration to remote master- scenario not present + + + ABRT_SLV_ARBLOST_GENERATED + 1 + Slave lost arbitration to remote master + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + Slave flushes existing data in TX-FIFO upon getting read command + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + 0 + Master or Slave-Transmitter lost arbitration- scenario not present + + + ABRT_LOST_GENERATED + 1 + Master or Slave-Transmitter lost arbitration + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + 0 + User initiating master operation when MASTER disabled- scenario not present + + + ABRT_MASTER_DIS_GENERATED + 1 + User initiating master operation when MASTER disabled + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + 0 + Master not trying to read in 10Bit addressing mode when RESTART disabled + + + ABRT_10B_RD_GENERATED + 1 + Master trying to read in 10Bit addressing mode when RESTART disabled + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + 0 + User trying to send START byte when RESTART disabled- scenario not present + + + ABRT_SBYTE_NORSTRT_GENERATED + 1 + User trying to send START byte when RESTART disabled + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + 0 + User trying to switch Master to HS mode when RESTART disabled- scenario not present + + + ABRT_HS_NORSTRT_GENERATED + 1 + User trying to switch Master to HS mode when RESTART disabled + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + 0 + ACK detected for START byte- scenario not present + + + ABRT_SBYTE_ACKDET_GENERATED + 1 + ACK detected for START byte + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + 0 + HS Master code ACKed in HS Mode- scenario not present + + + ABRT_HS_ACK_GENERATED + 1 + HS Master code ACKed in HS Mode + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + 0 + GCALL is followed by read from bus-scenario not present + + + ABRT_GCALL_READ_GENERATED + 1 + GCALL is followed by read from bus + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + 0 + GCALL not ACKed by any slave-scenario not present + + + ABRT_GCALL_NOACK_GENERATED + 1 + GCALL not ACKed by any slave + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + 0 + Transmitted data non-ACKed by addressed slave-scenario not present + + + ABRT_TXDATA_NOACK_GENERATED + 1 + Transmitted data not ACKed by addressed slave + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 2 of 10Bit Address not ACKed by any slave + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 1 of 10Bit Address not ACKed by any slave + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + This abort is generated because of NOACK for 7-bit address + + + + + + + IC_SLV_DATA_NACK_ONLY + 0x00000084 + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Slave receiver generates NACK normally + + + ENABLED + 1 + Slave receiver generates NACK upon data reception only + + + + + + + IC_DMA_CR + 0x00000088 + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + 0 + transmit FIFO DMA channel disabled + + + ENABLED + 1 + Transmit FIFO DMA channel enabled + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Receive FIFO DMA channel disabled + + + ENABLED + 1 + Receive FIFO DMA channel enabled + + + + + + + IC_DMA_TDLR + 0x0000008c + DMA Transmit Data Level Register + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + 0x00000090 + I2C Receive Data Level Register + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + 0x00000094 + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + 0x00000098 + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + 0 + Generate NACK for a General Call + + + ENABLED + 1 + Generate ACK for a General Call + + + + + + + IC_ENABLE_STATUS + 0x0000009c + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + Slave RX Data is not lost + + + ACTIVE + 1 + Slave RX Data is lost + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + Slave is disabled when it is idle + + + ACTIVE + 1 + Slave is disabled when it is active + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + 0 + I2C disabled + + + ENABLED + 1 + I2C enabled + + + + + + + IC_FS_SPKLEN + 0x000000a0 + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + 0x000000a8 + Clear RESTART_DET Interrupt Register + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + 0x000000f4 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + 0x000000f8 + I2C Component Version Register + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + 0x000000fc + I2C Component Type Register + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40098000 + + I2C1_IRQ + 37 + + + + SPI0 + 0x40080000 + + 0 + 4096 + registers + + + SPI0_IRQ + 31 + + + + SSPCR0 + 0x00000000 + Control register 0, SSPCR0 on page 3-4 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + 0x00000004 + Control register 1, SSPCR1 on page 3-5 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + 0x00000008 + Data register, SSPDR on page 3-6 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + 0x0000000c + Status register, SSPSR on page 3-7 + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + 0x00000010 + Clock prescale register, SSPCPSR on page 3-8 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + 0x00000014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + 0x00000018 + Raw interrupt status register, SSPRIS on page 3-10 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + 0x0000001c + Masked interrupt status register, SSPMIS on page 3-11 + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + 0x00000020 + Interrupt clear register, SSPICR on page 3-11 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + 0x00000024 + DMA control register, SSPDMACR on page 3-12 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + 0x00000fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + 0x00000fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + 0x00000fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + 0x00000fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + 0x00000ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + 0x00000ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + 0x00000ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + 0x00000ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40088000 + + SPI1_IRQ + 32 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0 + 392 + registers + + + PIO0_IRQ_0 + 15 + + + PIO0_IRQ_1 + 16 + + + + CTRL + 0x00000000 + PIO control register + 0x00000000 + + + NEXTPREV_CLKDIV_RESTART + Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + [26:26] + write-only + + + NEXTPREV_SM_DISABLE + Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + [25:25] + write-only + + + NEXTPREV_SM_ENABLE + Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + + If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. + [24:24] + write-only + + + NEXT_PIO_MASK + A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [23:20] + write-only + + + PREV_PIO_MASK + A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [19:16] + write-only + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + 0x00000004 + FIFO status register + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + 0x00000008 + FIFO debug register + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + 0x0000000c + FIFO levels + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + 0x00000010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + TXF1 + 0x00000014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF1 + [31:0] + write-only + + + + + TXF2 + 0x00000018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF2 + [31:0] + write-only + + + + + TXF3 + 0x0000001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF3 + [31:0] + write-only + + + + + RXF0 + 0x00000020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + RXF1 + 0x00000024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF1 + [31:0] + read-only + modify + + + + + RXF2 + 0x00000028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF2 + [31:0] + read-only + modify + + + + + RXF3 + 0x0000002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF3 + [31:0] + read-only + modify + + + + + IRQ + 0x00000030 + State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + 0x00000034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + 0x00000038 + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + 0x0000003c + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + 0x00000040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + 0x00000044 + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x10000000 + + + VERSION + Version of the core PIO hardware. + [31:28] + read-only + + + v0 + 0 + Version 0 (RP2040) + + + v1 + 1 + Version 1 (RP2350) + + + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + 0x00000048 + Write-only access to instruction memory location 0 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + 0x0000004c + Write-only access to instruction memory location 1 + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + 0x00000050 + Write-only access to instruction memory location 2 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + 0x00000054 + Write-only access to instruction memory location 3 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + 0x00000058 + Write-only access to instruction memory location 4 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + 0x0000005c + Write-only access to instruction memory location 5 + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + 0x00000060 + Write-only access to instruction memory location 6 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + 0x00000064 + Write-only access to instruction memory location 7 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + 0x00000068 + Write-only access to instruction memory location 8 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + 0x0000006c + Write-only access to instruction memory location 9 + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + 0x00000070 + Write-only access to instruction memory location 10 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + 0x00000074 + Write-only access to instruction memory location 11 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + 0x00000078 + Write-only access to instruction memory location 12 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + 0x0000007c + Write-only access to instruction memory location 13 + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + 0x00000080 + Write-only access to instruction memory location 14 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + 0x00000084 + Write-only access to instruction memory location 15 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + 0x00000088 + Write-only access to instruction memory location 16 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + 0x0000008c + Write-only access to instruction memory location 17 + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + 0x00000090 + Write-only access to instruction memory location 18 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + 0x00000094 + Write-only access to instruction memory location 19 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + 0x00000098 + Write-only access to instruction memory location 20 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + 0x0000009c + Write-only access to instruction memory location 21 + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + 0x000000a0 + Write-only access to instruction memory location 22 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + 0x000000a4 + Write-only access to instruction memory location 23 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + 0x000000a8 + Write-only access to instruction memory location 24 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + 0x000000ac + Write-only access to instruction memory location 25 + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + 0x000000b0 + Write-only access to instruction memory location 26 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + 0x000000b4 + Write-only access to instruction memory location 27 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + 0x000000b8 + Write-only access to instruction memory location 28 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + 0x000000bc + Write-only access to instruction memory location 29 + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + 0x000000c0 + Write-only access to instruction memory location 30 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + 0x000000c4 + Write-only access to instruction memory location 31 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + 0x000000c8 + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + 0x000000cc + Execution/behavioural settings for state machine 0 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM0_SHIFTCTRL + 0x000000d0 + Control behaviour of the input/output shift registers for state machine 0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM0_ADDR + 0x000000d4 + Current instruction address of state machine 0 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + 0x000000d8 + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + 0x000000dc + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + 0x000000e0 + Clock divisor register for state machine 1 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + 0x000000e4 + Execution/behavioural settings for state machine 1 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM1_SHIFTCTRL + 0x000000e8 + Control behaviour of the input/output shift registers for state machine 1 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM1_ADDR + 0x000000ec + Current instruction address of state machine 1 + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + 0x000000f0 + Read to see the instruction currently addressed by state machine 1's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + 0x000000f4 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + 0x000000f8 + Clock divisor register for state machine 2 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + 0x000000fc + Execution/behavioural settings for state machine 2 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM2_SHIFTCTRL + 0x00000100 + Control behaviour of the input/output shift registers for state machine 2 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM2_ADDR + 0x00000104 + Current instruction address of state machine 2 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + 0x00000108 + Read to see the instruction currently addressed by state machine 2's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + 0x0000010c + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + 0x00000110 + Clock divisor register for state machine 3 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + 0x00000114 + Execution/behavioural settings for state machine 3 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM3_SHIFTCTRL + 0x00000118 + Control behaviour of the input/output shift registers for state machine 3 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM3_ADDR + 0x0000011c + Current instruction address of state machine 3 + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + 0x00000120 + Read to see the instruction currently addressed by state machine 3's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + 0x00000124 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + RXF0_PUTGET0 + 0x00000128 + Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET0 + [31:0] + read-write + + + + + RXF0_PUTGET1 + 0x0000012c + Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET1 + [31:0] + read-write + + + + + RXF0_PUTGET2 + 0x00000130 + Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET2 + [31:0] + read-write + + + + + RXF0_PUTGET3 + 0x00000134 + Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET3 + [31:0] + read-write + + + + + RXF1_PUTGET0 + 0x00000138 + Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET0 + [31:0] + read-write + + + + + RXF1_PUTGET1 + 0x0000013c + Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET1 + [31:0] + read-write + + + + + RXF1_PUTGET2 + 0x00000140 + Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET2 + [31:0] + read-write + + + + + RXF1_PUTGET3 + 0x00000144 + Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET3 + [31:0] + read-write + + + + + RXF2_PUTGET0 + 0x00000148 + Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET0 + [31:0] + read-write + + + + + RXF2_PUTGET1 + 0x0000014c + Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET1 + [31:0] + read-write + + + + + RXF2_PUTGET2 + 0x00000150 + Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET2 + [31:0] + read-write + + + + + RXF2_PUTGET3 + 0x00000154 + Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET3 + [31:0] + read-write + + + + + RXF3_PUTGET0 + 0x00000158 + Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET0 + [31:0] + read-write + + + + + RXF3_PUTGET1 + 0x0000015c + Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET1 + [31:0] + read-write + + + + + RXF3_PUTGET2 + 0x00000160 + Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET2 + [31:0] + read-write + + + + + RXF3_PUTGET3 + 0x00000164 + Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET3 + [31:0] + read-write + + + + + GPIOBASE + 0x00000168 + Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. + + Only the values 0 and 16 are supported (only bit 4 is writable). + 0x00000000 + + + GPIOBASE + [4:4] + read-write + + + + + INTR + 0x0000016c + Raw Interrupts + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + 0x00000170 + Interrupt Enable for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + 0x00000174 + Interrupt Force for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000178 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + 0x0000017c + Interrupt Enable for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000180 + Interrupt Force for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + 0x00000184 + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 17 + + + PIO1_IRQ_1 + 18 + + + + PIO2 + 0x50400000 + + PIO2_IRQ_0 + 19 + + + PIO2_IRQ_1 + 20 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40068000 + + 0 + 44 + registers + + + + BUS_PRIORITY + 0x00000000 + Set the priority of each master for bus arbitration. + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + 0x00000004 + Bus priority acknowledge + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR_EN + 0x00000008 + Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. + + The performance counters are initially disabled, to save energy. + 0x00000000 + + + PERFCTR_EN + [0:0] + read-write + + + + + PERFCTR0 + 0x0000000c + Bus fabric performance counter 0 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + 0x00000010 + Bus fabric performance event select for PERFCTR0 + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR1 + 0x00000014 + Bus fabric performance counter 1 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + 0x00000018 + Bus fabric performance event select for PERFCTR1 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR2 + 0x0000001c + Bus fabric performance counter 2 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + 0x00000020 + Bus fabric performance event select for PERFCTR2 + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR3 + 0x00000024 + Bus fabric performance counter 3 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + 0x00000028 + Bus fabric performance event select for PERFCTR3 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + + 0 + 488 + registers + + + SIO_IRQ_FIFO + 25 + + + SIO_IRQ_BELL + 26 + + + SIO_IRQ_FIFO_NS + 27 + + + SIO_IRQ_BELL_NS + 28 + + + SIO_IRQ_MTIMECMP + 29 + + + + CPUID + 0x00000000 + Processor core identifier + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + 0x00000004 + Input value for GPIO0...31. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + GPIO_IN + [31:0] + read-only + + + + + GPIO_HI_IN + 0x00000008 + Input value on GPIO32...47, QSPI IOs and USB pins + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + QSPI_SD + Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-only + + + QSPI_CSN + Input value on QSPI CSn pin + [27:27] + read-only + + + QSPI_SCK + Input value on QSPI SCK pin + [26:26] + read-only + + + USB_DM + Input value on USB D- pin + [25:25] + read-only + + + USB_DP + Input value on USB D+ pin + [24:24] + read-only + + + GPIO + Input value on GPIO32...47 + [15:0] + read-only + + + + + GPIO_OUT + 0x00000010 + GPIO0...31 output value + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. + + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OUT + 0x00000014 + Output value for GPIO32...47, QSPI IOs and USB pins. + + Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output value for USB D- pin + [25:25] + read-write + + + USB_DP + Output value for USB D+ pin + [24:24] + read-write + + + GPIO + Output value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OUT_SET + 0x00000018 + GPIO0...31 output value set + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_SET + 0x0000001c + Output value set for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_CLR + 0x00000020 + GPIO0...31 output value clear + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_CLR + 0x00000024 + Output value clear for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_XOR + 0x00000028 + GPIO0...31 output value XOR + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_XOR + 0x0000002c + Output value XOR for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE + 0x00000030 + GPIO0...31 output enable + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. + + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OE + 0x00000034 + Output enable value for GPIO32...47, QSPI IOs and USB pins. + + Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output enable value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output enable value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output enable value for USB D- pin + [25:25] + read-write + + + USB_DP + Output enable value for USB D+ pin + [24:24] + read-write + + + GPIO + Output enable value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OE_SET + 0x00000038 + GPIO0...31 output enable set + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_SET + 0x0000003c + Output enable set for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_CLR + 0x00000040 + GPIO0...31 output enable clear + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_CLR + 0x00000044 + Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_XOR + 0x00000048 + GPIO0...31 output enable XOR + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_XOR + 0x0000004c + Output enable XOR for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + FIFO_ST + 0x00000050 + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + 0x00000054 + Write access to this core's TX FIFO + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + 0x00000058 + Read access to this core's RX FIFO + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + 0x0000005c + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + INTERP0_ACCUM0 + 0x00000080 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + 0x00000084 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + 0x00000088 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + 0x0000008c + Read/write access to BASE1 register. + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + 0x00000090 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + 0x00000094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + 0x00000098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + 0x0000009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + 0x000000a0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + 0x000000a4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + 0x000000a8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + 0x000000ac + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + 0x000000b0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + 0x000000b4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + 0x000000b8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + 0x000000bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + 0x000000c0 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + 0x000000c4 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + 0x000000c8 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + 0x000000cc + Read/write access to BASE1 register. + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + 0x000000d0 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + 0x000000d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + 0x000000d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + 0x000000dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + 0x000000e0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + 0x000000e4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + 0x000000e8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + 0x000000ec + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + 0x000000f0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + 0x000000f4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + 0x000000f8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + 0x000000fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + SPINLOCK0 + 0x00000100 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + SPINLOCK1 + 0x00000104 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK1 + [31:0] + read-write + modify + + + + + SPINLOCK2 + 0x00000108 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK2 + [31:0] + read-write + modify + + + + + SPINLOCK3 + 0x0000010c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK3 + [31:0] + read-write + modify + + + + + SPINLOCK4 + 0x00000110 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK4 + [31:0] + read-write + modify + + + + + SPINLOCK5 + 0x00000114 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK5 + [31:0] + read-write + modify + + + + + SPINLOCK6 + 0x00000118 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK6 + [31:0] + read-write + modify + + + + + SPINLOCK7 + 0x0000011c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK7 + [31:0] + read-write + modify + + + + + SPINLOCK8 + 0x00000120 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK8 + [31:0] + read-write + modify + + + + + SPINLOCK9 + 0x00000124 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK9 + [31:0] + read-write + modify + + + + + SPINLOCK10 + 0x00000128 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK10 + [31:0] + read-write + modify + + + + + SPINLOCK11 + 0x0000012c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK11 + [31:0] + read-write + modify + + + + + SPINLOCK12 + 0x00000130 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK12 + [31:0] + read-write + modify + + + + + SPINLOCK13 + 0x00000134 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK13 + [31:0] + read-write + modify + + + + + SPINLOCK14 + 0x00000138 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK14 + [31:0] + read-write + modify + + + + + SPINLOCK15 + 0x0000013c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK15 + [31:0] + read-write + modify + + + + + SPINLOCK16 + 0x00000140 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK16 + [31:0] + read-write + modify + + + + + SPINLOCK17 + 0x00000144 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK17 + [31:0] + read-write + modify + + + + + SPINLOCK18 + 0x00000148 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK18 + [31:0] + read-write + modify + + + + + SPINLOCK19 + 0x0000014c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK19 + [31:0] + read-write + modify + + + + + SPINLOCK20 + 0x00000150 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK20 + [31:0] + read-write + modify + + + + + SPINLOCK21 + 0x00000154 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK21 + [31:0] + read-write + modify + + + + + SPINLOCK22 + 0x00000158 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK22 + [31:0] + read-write + modify + + + + + SPINLOCK23 + 0x0000015c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK23 + [31:0] + read-write + modify + + + + + SPINLOCK24 + 0x00000160 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK24 + [31:0] + read-write + modify + + + + + SPINLOCK25 + 0x00000164 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK25 + [31:0] + read-write + modify + + + + + SPINLOCK26 + 0x00000168 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK26 + [31:0] + read-write + modify + + + + + SPINLOCK27 + 0x0000016c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK27 + [31:0] + read-write + modify + + + + + SPINLOCK28 + 0x00000170 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK28 + [31:0] + read-write + modify + + + + + SPINLOCK29 + 0x00000174 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK29 + [31:0] + read-write + modify + + + + + SPINLOCK30 + 0x00000178 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK30 + [31:0] + read-write + modify + + + + + SPINLOCK31 + 0x0000017c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK31 + [31:0] + read-write + modify + + + + + DOORBELL_OUT_SET + 0x00000180 + Trigger a doorbell interrupt on the opposite core. + + Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. + + Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_SET + [7:0] + read-write + + + + + DOORBELL_OUT_CLR + 0x00000184 + Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. + + Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. + + Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_CLR + [7:0] + read-write + oneToClear + + + + + DOORBELL_IN_SET + 0x00000188 + Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_SET + [7:0] + read-write + + + + + DOORBELL_IN_CLR + 0x0000018c + Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. + + Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_CLR + [7:0] + read-write + oneToClear + + + + + PERI_NONSEC + 0x00000190 + Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. + + This register is per-core, and is only present on the Secure SIO. + + Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + 0x00000000 + + + TMDS + IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [5:5] + read-write + + + INTERP1 + If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [1:1] + read-write + + + INTERP0 + If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [0:0] + read-write + + + + + RISCV_SOFTIRQ + 0x000001a0 + Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. + + Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. + + It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + 0x00000000 + + + CORE1_CLR + Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. + [9:9] + read-write + + + CORE0_CLR + Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. + [8:8] + read-write + + + CORE1_SET + Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. + [1:1] + read-write + + + CORE0_SET + Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. + [0:0] + read-write + + + + + MTIME_CTRL + 0x000001a4 + Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. + + Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + 0x0000000d + + + DBGPAUSE_CORE1 + If 1, the timer pauses when core 1 is in the debug halt state. + [3:3] + read-write + + + DBGPAUSE_CORE0 + If 1, the timer pauses when core 0 is in the debug halt state. + [2:2] + read-write + + + FULLSPEED + If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. + [1:1] + read-write + + + EN + Timer enable bit. When 0, the timer will not increment automatically. + [0:0] + read-write + + + + + MTIME + 0x000001b0 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIME + [31:0] + read-write + + + + + MTIMEH + 0x000001b4 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIMEH + [31:0] + read-write + + + + + MTIMECMP + 0x000001b8 + Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMP + [31:0] + read-write + + + + + MTIMECMPH + 0x000001bc + High half of RISC-V Machine-mode timer comparator. This register is core-local. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMPH + [31:0] + read-write + + + + + TMDS_CTRL + 0x000001c0 + Control register for TMDS encoder. + 0x00000000 + + + CLEAR_BALANCE + Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. + [28:28] + write-only + + + PIX2_NOSHIFT + When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. + + This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. + [27:27] + read-write + + + PIX_SHIFT + Shift applied to the colour data register with each read of a POP alias register. + + Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. + + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + [26:24] + read-write + + + 0 + 0 + Do not shift the colour data register. + + + 1 + 1 + Shift the colour data register by 1 bit + + + 2 + 2 + Shift the colour data register by 2 bits + + + 4 + 3 + Shift the colour data register by 4 bits + + + 8 + 4 + Shift the colour data register by 8 bits + + + 16 + 5 + Shift the colour data register by 16 bits + + + + + INTERLEAVE + Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + + When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. + + When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. + [23:23] + read-write + + + L2_NBITS + Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [20:18] + read-write + + + L1_NBITS + Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [17:15] + read-write + + + L0_NBITS + Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [14:12] + read-write + + + L2_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. + [11:8] + read-write + + + L1_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. + [7:4] + read-write + + + L0_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. + [3:0] + read-write + + + + + TMDS_WDATA + 0x000001c4 + Write-only access to the TMDS colour data register. + 0x00000000 + + + TMDS_WDATA + [31:0] + write-only + + + + + TMDS_PEEK_SINGLE + 0x000001c8 + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). + + The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + 0x00000000 + + + TMDS_PEEK_SINGLE + [31:0] + read-only + modify + + + + + TMDS_POP_SINGLE + 0x000001cc + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. + + The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + 0x00000000 + + + TMDS_POP_SINGLE + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L0 + 0x000001d0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L0 + 0x000001d4 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L1 + 0x000001d8 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L1 + 0x000001dc + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L2 + 0x000001e0 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L2 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L2 + 0x000001e4 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L2 + [31:0] + read-only + modify + + + + + + + SIO_NS + 0xd0020000 + + + BOOTRAM + Additional registers mapped adjacent to the bootram, for use by the bootrom. + 0x400e0000 + + 0 + 2092 + registers + + + + WRITE_ONCE0 + 0x00000800 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE0 + [31:0] + read-write + + + + + WRITE_ONCE1 + 0x00000804 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE1 + [31:0] + read-write + + + + + BOOTLOCK_STAT + 0x00000808 + Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + 0x000000ff + + + BOOTLOCK_STAT + [7:0] + read-write + + + + + BOOTLOCK0 + 0x0000080c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK0 + [31:0] + read-write + + + + + BOOTLOCK1 + 0x00000810 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK1 + [31:0] + read-write + + + + + BOOTLOCK2 + 0x00000814 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK2 + [31:0] + read-write + + + + + BOOTLOCK3 + 0x00000818 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK3 + [31:0] + read-write + + + + + BOOTLOCK4 + 0x0000081c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK4 + [31:0] + read-write + + + + + BOOTLOCK5 + 0x00000820 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK5 + [31:0] + read-write + + + + + BOOTLOCK6 + 0x00000824 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK6 + [31:0] + read-write + + + + + BOOTLOCK7 + 0x00000828 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK7 + [31:0] + read-write + + + + + + + CORESIGHT_TRACE + Coresight block - RP specific registers + 0x50700000 + + 0 + 8 + registers + + + + CTRL_STATUS + 0x00000000 + Control and status register + 0x00000001 + + + TRACE_CAPTURE_FIFO_OVERFLOW + This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. + [1:1] + read-write + + + TRACE_CAPTURE_FIFO_FLUSH + Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. + + Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. + + Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. + [0:0] + read-write + + + + + TRACE_CAPTURE_FIFO + 0x00000004 + FIFO for trace data captured from the TPIU + 0x00000000 + + + RDATA + Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. + + Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: + + * TPIU TRACECTL output is low (normal trace data) + + * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) + + These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices + + The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + [31:0] + read-only + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0 + 280 + registers + + + USBCTRL_IRQ + 14 + + + + ADDR_ENDP + 0x00000000 + Device address and endpoint control + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + 0x00000004 + Interrupt endpoint 1. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + 0x00000008 + Interrupt endpoint 2. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + 0x0000000c + Interrupt endpoint 3. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + 0x00000010 + Interrupt endpoint 4. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + 0x00000014 + Interrupt endpoint 5. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + 0x00000018 + Interrupt endpoint 6. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + 0x0000001c + Interrupt endpoint 7. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + 0x00000020 + Interrupt endpoint 8. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + 0x00000024 + Interrupt endpoint 9. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + 0x00000028 + Interrupt endpoint 10. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + 0x0000002c + Interrupt endpoint 11. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + 0x00000030 + Interrupt endpoint 12. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + 0x00000034 + Interrupt endpoint 13. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + 0x00000038 + Interrupt endpoint 14. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + 0x0000003c + Interrupt endpoint 15. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + 0x00000040 + Main control register + 0x00000004 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + PHY_ISO + Isolates USB phy after controller power-up + Remove isolation once software has configured the controller + Not isolated = 0, Isolated = 1 + [2:2] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + 0x00000044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + 0x00000048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + 0x0000004c + SIE control register + 0x00008000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + EP0_STOP_ON_SHORT_PACKET + Device: Stop EP0 on a short packet. + [19:19] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + 0x00000050 + SIE status register + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + ENDPOINT_ERROR + An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. + [23:23] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RX_SHORT_PACKET + Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. + [12:12] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + 0x00000054 + interrupt endpoint control register + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + 0x00000058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + 0x0000005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + 0x00000060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + 0x00000064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + 0x00000068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + 0x0000006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x00100010 + + + RETRY_COUNT_HI + Bits 9:6 of nak_retry count + [31:28] + read-only + + + EPX_STOPPED_ON_NAK + EPX polling has stopped because a nak was received + [27:27] + read-write + oneToClear + + + STOP_EPX_ON_NAK + Stop polling epx when a nak is received + [26:26] + read-write + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + RETRY_COUNT_LO + Bits 5:0 of nak_retry_count + [15:10] + read-only + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + 0x00000070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + 0x00000074 + Where to connect the USB controller. Should be to_phy by default. + 0x00000001 + + + SWAP_DPDM + Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. + This is done at a low level so overrides all other controls. + [31:31] + read-write + + + USBPHY_AS_GPIO + Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. + [4:4] + read-write + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + 0x00000078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + 0x0000007c + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x00000000 + + + RX_DM_OVERRIDE + Override rx_dm value into controller + [25:25] + read-write + + + RX_DP_OVERRIDE + Override rx_dp value into controller + [24:24] + read-write + + + RX_DD_OVERRIDE + Override rx_dd value into controller + [23:23] + read-write + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + 0x00000080 + Override enable for each control in usbphy_direct + 0x00000000 + + + RX_DM_OVERRIDE_EN + [18:18] + read-write + + + RX_DP_OVERRIDE_EN + [17:17] + read-write + + + RX_DD_OVERRIDE_EN + [16:16] + read-write + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + 0x00000084 + Used to adjust trim values of USB phy pull down resistors. + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + LINESTATE_TUNING + 0x00000088 + Used for debug only. + 0x000000f8 + + + SPARE_FIX + [11:8] + read-write + + + DEV_LS_WAKE_FIX + Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer + [7:7] + read-write + + + DEV_RX_ERR_QUIESCE + Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. + [6:6] + read-write + + + SIE_RX_CHATTER_SE0_FIX + RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as + 8 consecutive idle bits. + [5:5] + read-write + + + SIE_RX_BITSTUFF_FIX + RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to + avoid a hang during certain packet phases. + [4:4] + read-write + + + DEV_BUFF_CONTROL_DOUBLE_READ_FIX + Device - the controller FSM performs two reads of the buffer status memory address to + avoid sampling metastable data. An enabled buffer is only used if both reads match. + [3:3] + read-write + + + MULTI_HUB_FIX + Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. + [2:2] + read-write + + + LINESTATE_DELAY + Device/Host - add an extra 1-bit debounce of linestate sampling. + [1:1] + read-write + + + RCV_DELAY + Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. + [0:0] + read-write + + + + + INTR + 0x0000008c + Raw Interrupts + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + 0x00000090 + Interrupt Enable + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + 0x00000094 + Interrupt Force + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + 0x00000098 + Interrupt status after masking & forcing + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + SOF_TIMESTAMP_RAW + 0x00000100 + Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + 0x00000000 + + + SOF_TIMESTAMP_RAW + [20:0] + read-only + + + + + SOF_TIMESTAMP_LAST + 0x00000104 + Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + 0x00000000 + + + SOF_TIMESTAMP_LAST + [20:0] + read-only + + + + + SM_STATE + 0x00000108 + 0x00000000 + + + RX_DASM + [11:8] + read-only + + + BC_STATE + [7:5] + read-only + + + STATE + [4:0] + read-only + + + + + EP_TX_ERROR + 0x0000010c + TX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15 + [31:30] + read-write + oneToClear + + + EP14 + [29:28] + read-write + oneToClear + + + EP13 + [27:26] + read-write + oneToClear + + + EP12 + [25:24] + read-write + oneToClear + + + EP11 + [23:22] + read-write + oneToClear + + + EP10 + [21:20] + read-write + oneToClear + + + EP9 + [19:18] + read-write + oneToClear + + + EP8 + [17:16] + read-write + oneToClear + + + EP7 + [15:14] + read-write + oneToClear + + + EP6 + [13:12] + read-write + oneToClear + + + EP5 + [11:10] + read-write + oneToClear + + + EP4 + [9:8] + read-write + oneToClear + + + EP3 + [7:6] + read-write + oneToClear + + + EP2 + [5:4] + read-write + oneToClear + + + EP1 + [3:2] + read-write + oneToClear + + + EP0 + [1:0] + read-write + oneToClear + + + + + EP_RX_ERROR + 0x00000110 + RX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15_SEQ + [31:31] + read-write + oneToClear + + + EP15_TRANSACTION + [30:30] + read-write + oneToClear + + + EP14_SEQ + [29:29] + read-write + oneToClear + + + EP14_TRANSACTION + [28:28] + read-write + oneToClear + + + EP13_SEQ + [27:27] + read-write + oneToClear + + + EP13_TRANSACTION + [26:26] + read-write + oneToClear + + + EP12_SEQ + [25:25] + read-write + oneToClear + + + EP12_TRANSACTION + [24:24] + read-write + oneToClear + + + EP11_SEQ + [23:23] + read-write + oneToClear + + + EP11_TRANSACTION + [22:22] + read-write + oneToClear + + + EP10_SEQ + [21:21] + read-write + oneToClear + + + EP10_TRANSACTION + [20:20] + read-write + oneToClear + + + EP9_SEQ + [19:19] + read-write + oneToClear + + + EP9_TRANSACTION + [18:18] + read-write + oneToClear + + + EP8_SEQ + [17:17] + read-write + oneToClear + + + EP8_TRANSACTION + [16:16] + read-write + oneToClear + + + EP7_SEQ + [15:15] + read-write + oneToClear + + + EP7_TRANSACTION + [14:14] + read-write + oneToClear + + + EP6_SEQ + [13:13] + read-write + oneToClear + + + EP6_TRANSACTION + [12:12] + read-write + oneToClear + + + EP5_SEQ + [11:11] + read-write + oneToClear + + + EP5_TRANSACTION + [10:10] + read-write + oneToClear + + + EP4_SEQ + [9:9] + read-write + oneToClear + + + EP4_TRANSACTION + [8:8] + read-write + oneToClear + + + EP3_SEQ + [7:7] + read-write + oneToClear + + + EP3_TRANSACTION + [6:6] + read-write + oneToClear + + + EP2_SEQ + [5:5] + read-write + oneToClear + + + EP2_TRANSACTION + [4:4] + read-write + oneToClear + + + EP1_SEQ + [3:3] + read-write + oneToClear + + + EP1_TRANSACTION + [2:2] + read-write + oneToClear + + + EP0_SEQ + [1:1] + read-write + oneToClear + + + EP0_TRANSACTION + [0:0] + read-write + oneToClear + + + + + DEV_SM_WATCHDOG + 0x00000114 + Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. + Set limit while enable is low and then set the enable. + 0x00000000 + + + FIRED + [20:20] + read-write + oneToClear + + + RESET + Set to 1 to forcibly reset the device state machine on watchdog expiry + [19:19] + read-write + + + ENABLE + [18:18] + read-write + + + LIMIT + [17:0] + read-write + + + + + + + TRNG + ARM TrustZone RNG register block + 0x400f0000 + + 0 + 492 + registers + + + TRNG_IRQ + 39 + + + + RNG_IMR + 0x00000100 + Interrupt masking. + 0x0000000f + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [3:3] + read-write + + + CRNGT_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [2:2] + read-write + + + AUTOCORR_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [1:1] + read-write + + + EHR_VALID_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [0:0] + read-write + + + + + RNG_ISR + 0x00000104 + RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. + [3:3] + read-only + + + CRNGT_ERR + 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. + [2:2] + read-only + + + AUTOCORR_ERR + 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. + [1:1] + read-only + + + EHR_VALID + 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. + [0:0] + read-only + + + + + RNG_ICR + 0x00000108 + Interrupt/status bit clear Register. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [3:3] + read-write + + + CRNGT_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [2:2] + read-write + + + AUTOCORR_ERR + Cannot be cleared by SW! Only RNG reset clears this bit. + [1:1] + read-write + + + EHR_VALID + Write 1'b1 - clear corresponding bit in RNG_ISR. + [0:0] + read-write + + + + + TRNG_CONFIG + 0x0000010c + Selecting the inverter-chain length. + 0x00000000 + + + RESERVED + RESERVED + [31:2] + read-only + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). + [1:0] + read-write + + + + + TRNG_VALID + 0x00000110 + 192 bit collection indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + EHR_VALID + 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. + [0:0] + read-only + + + + + EHR_DATA0 + 0x00000114 + RNG collected bits. + 0x00000000 + + + EHR_DATA0 + Bits [31:0] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA1 + 0x00000118 + RNG collected bits. + 0x00000000 + + + EHR_DATA1 + Bits [63:32] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA2 + 0x0000011c + RNG collected bits. + 0x00000000 + + + EHR_DATA2 + Bits [95:64] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA3 + 0x00000120 + RNG collected bits. + 0x00000000 + + + EHR_DATA3 + Bits [127:96] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA4 + 0x00000124 + RNG collected bits. + 0x00000000 + + + EHR_DATA4 + Bits [159:128] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA5 + 0x00000128 + RNG collected bits. + 0x00000000 + + + EHR_DATA5 + Bits [191:160] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + RND_SOURCE_ENABLE + 0x0000012c + Enable signal for the random source. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RND_SRC_EN + * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled + [0:0] + read-write + + + + + SAMPLE_CNT1 + 0x00000130 + Counts clocks between sampling of random bit. + 0x0000ffff + + + SAMPLE_CNTR1 + Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen + [31:0] + read-write + + + + + AUTOCORR_STATISTIC + 0x00000134 + Statistic about Autocorrelation test activations. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [21:14] + read-write + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [13:0] + read-write + + + + + TRNG_DEBUG_CONTROL + 0x00000138 + Debug register. + 0x00000000 + + + AUTO_CORRELATE_BYPASS + When set, the autocorrelation test in the TRNG module is bypassed. + [3:3] + read-write + + + TRNG_CRNGT_BYPASS + When set, the CRNGT test in the RNG is bypassed. + [2:2] + read-write + + + VNC_BYPASS + When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + [1:1] + read-write + + + RESERVED + N/A + [0:0] + read-only + + + + + TRNG_SW_RESET + 0x00000140 + Generate internal SW reset within the RNG block. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_SW_RESET + Writing 1'b1 to this register causes an internal RNG reset. + [0:0] + read-write + + + + + RNG_DEBUG_EN_INPUT + 0x000001b4 + Enable the RNG debug mode + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RNG_DEBUG_EN + * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + [0:0] + read-write + + + + + TRNG_BUSY + 0x000001b8 + RNG Busy indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_BUSY + Reflects rng_busy status. + [0:0] + read-only + + + + + RST_BITS_COUNTER + 0x000001bc + Reset the counter of collected bits in the RNG. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RST_BITS_COUNTER + Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. + [0:0] + read-write + + + + + RNG_VERSION + 0x000001c0 + Displays the version settings of the TRNG. + 0x00000000 + + + RESERVED + RESERVED + [31:8] + read-only + + + RNG_USE_5_SBOXES + * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + [7:7] + read-only + + + RESEEDING_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [6:6] + read-only + + + KAT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [5:5] + read-only + + + PRNG_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [4:4] + read-only + + + TRNG_TESTS_BYPASS_EN + * 1'b1 - Exists. *1'b0 - Does not exist + [3:3] + read-only + + + AUTOCORR_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [2:2] + read-only + + + CRNGT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [1:1] + read-only + + + EHR_WIDTH_192 + * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + [0:0] + read-only + + + + + RNG_BIST_CNTR_0 + 0x000001e0 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_1 + 0x000001e4 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_2 + 0x000001e8 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + + + GLITCH_DETECTOR + Glitch detector controls + 0x40158000 + + 0 + 24 + registers + + + + ARM + 0x00000000 + Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. + + Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + + This register is Secure read/write only. + 0x00005bad + + + ARM + [15:0] + read-write + + + no + 23469 + Do not force the glitch detectors to be armed + + + yes + 0 + Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) + + + + + + + DISARM + 0x00000004 + 0x00000000 + + + DISARM + Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. + + This register is Secure read/write only. + [15:0] + read-write + + + no + 0 + Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) + + + yes + 56495 + Disarm the glitch detectors + + + + + + + SENSITIVITY + 0x00000008 + Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. + + This register is Secure read/write only. + 0x00000000 + + + DEFAULT + [31:24] + read-write + + + yes + 0 + Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) + + + no + 222 + Do not use the default sensitivity configured in OTP. Instead use the value from this register. + + + + + DET3_INV + Must be the inverse of DET3, else the default value is used. + [15:14] + read-write + + + DET2_INV + Must be the inverse of DET2, else the default value is used. + [13:12] + read-write + + + DET1_INV + Must be the inverse of DET1, else the default value is used. + [11:10] + read-write + + + DET0_INV + Must be the inverse of DET0, else the default value is used. + [9:8] + read-write + + + DET3 + Set sensitivity for detector 3. Higher values are more sensitive. + [7:6] + read-write + + + DET2 + Set sensitivity for detector 2. Higher values are more sensitive. + [5:4] + read-write + + + DET1 + Set sensitivity for detector 1. Higher values are more sensitive. + [3:2] + read-write + + + DET0 + Set sensitivity for detector 0. Higher values are more sensitive. + [1:0] + read-write + + + + + LOCK + 0x0000000c + 0x00000000 + + + LOCK + Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. + [7:0] + read-write + + + + + TRIG_STATUS + 0x00000010 + Set when a detector output triggers. Write-1-clear. + + (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) + + This register is Secure read/write only. + 0x00000000 + + + DET3 + [3:3] + read-write + oneToClear + + + DET2 + [2:2] + read-write + oneToClear + + + DET1 + [1:1] + read-write + oneToClear + + + DET0 + [0:0] + read-write + oneToClear + + + + + TRIG_FORCE + 0x00000014 + Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. + + If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + + This register is Secure read/write only. + 0x00000000 + + + TRIG_FORCE + [3:0] + write-only + + + + + + + OTP + SNPS OTP control IF (SBPI and RPi wrapper control) + 0x40120000 + + 0 + 372 + registers + + + OTP_IRQ + 38 + + + + SW_LOCK0 + 0x00000000 + Software lock register for page 0. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK1 + 0x00000004 + Software lock register for page 1. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK2 + 0x00000008 + Software lock register for page 2. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK3 + 0x0000000c + Software lock register for page 3. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK4 + 0x00000010 + Software lock register for page 4. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK5 + 0x00000014 + Software lock register for page 5. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK6 + 0x00000018 + Software lock register for page 6. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK7 + 0x0000001c + Software lock register for page 7. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK8 + 0x00000020 + Software lock register for page 8. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK9 + 0x00000024 + Software lock register for page 9. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK10 + 0x00000028 + Software lock register for page 10. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK11 + 0x0000002c + Software lock register for page 11. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK12 + 0x00000030 + Software lock register for page 12. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK13 + 0x00000034 + Software lock register for page 13. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK14 + 0x00000038 + Software lock register for page 14. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK15 + 0x0000003c + Software lock register for page 15. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK16 + 0x00000040 + Software lock register for page 16. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK17 + 0x00000044 + Software lock register for page 17. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK18 + 0x00000048 + Software lock register for page 18. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK19 + 0x0000004c + Software lock register for page 19. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK20 + 0x00000050 + Software lock register for page 20. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK21 + 0x00000054 + Software lock register for page 21. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK22 + 0x00000058 + Software lock register for page 22. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK23 + 0x0000005c + Software lock register for page 23. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK24 + 0x00000060 + Software lock register for page 24. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK25 + 0x00000064 + Software lock register for page 25. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK26 + 0x00000068 + Software lock register for page 26. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK27 + 0x0000006c + Software lock register for page 27. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK28 + 0x00000070 + Software lock register for page 28. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK29 + 0x00000074 + Software lock register for page 29. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK30 + 0x00000078 + Software lock register for page 30. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK31 + 0x0000007c + Software lock register for page 31. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK32 + 0x00000080 + Software lock register for page 32. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK33 + 0x00000084 + Software lock register for page 33. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK34 + 0x00000088 + Software lock register for page 34. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK35 + 0x0000008c + Software lock register for page 35. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK36 + 0x00000090 + Software lock register for page 36. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK37 + 0x00000094 + Software lock register for page 37. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK38 + 0x00000098 + Software lock register for page 38. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK39 + 0x0000009c + Software lock register for page 39. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK40 + 0x000000a0 + Software lock register for page 40. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK41 + 0x000000a4 + Software lock register for page 41. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK42 + 0x000000a8 + Software lock register for page 42. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK43 + 0x000000ac + Software lock register for page 43. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK44 + 0x000000b0 + Software lock register for page 44. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK45 + 0x000000b4 + Software lock register for page 45. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK46 + 0x000000b8 + Software lock register for page 46. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK47 + 0x000000bc + Software lock register for page 47. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK48 + 0x000000c0 + Software lock register for page 48. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK49 + 0x000000c4 + Software lock register for page 49. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK50 + 0x000000c8 + Software lock register for page 50. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK51 + 0x000000cc + Software lock register for page 51. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK52 + 0x000000d0 + Software lock register for page 52. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK53 + 0x000000d4 + Software lock register for page 53. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK54 + 0x000000d8 + Software lock register for page 54. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK55 + 0x000000dc + Software lock register for page 55. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK56 + 0x000000e0 + Software lock register for page 56. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK57 + 0x000000e4 + Software lock register for page 57. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK58 + 0x000000e8 + Software lock register for page 58. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK59 + 0x000000ec + Software lock register for page 59. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK60 + 0x000000f0 + Software lock register for page 60. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK61 + 0x000000f4 + Software lock register for page 61. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK62 + 0x000000f8 + Software lock register for page 62. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK63 + 0x000000fc + Software lock register for page 63. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SBPI_INSTR + 0x00000100 + Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + 0x00000000 + + + EXEC + Execute instruction + [30:30] + write-only + + + IS_WR + Payload type is write + [29:29] + read-write + + + HAS_PAYLOAD + Instruction has payload (data to be written or to be read) + [28:28] + read-write + + + PAYLOAD_SIZE_M1 + Instruction payload size in bytes minus 1 + [27:24] + read-write + + + TARGET + Instruction target, it can be PMC (0x3a) or DAP (0x02) + [23:16] + read-write + + + CMD + [15:8] + read-write + + + SHORT_WDATA + wdata to be used only when payload_size_m1=0 + [7:0] + read-write + + + + + SBPI_WDATA_0 + 0x00000104 + SBPI write payload bytes 3..0 + 0x00000000 + + + SBPI_WDATA_0 + [31:0] + read-write + + + + + SBPI_WDATA_1 + 0x00000108 + SBPI write payload bytes 7..4 + 0x00000000 + + + SBPI_WDATA_1 + [31:0] + read-write + + + + + SBPI_WDATA_2 + 0x0000010c + SBPI write payload bytes 11..8 + 0x00000000 + + + SBPI_WDATA_2 + [31:0] + read-write + + + + + SBPI_WDATA_3 + 0x00000110 + SBPI write payload bytes 15..12 + 0x00000000 + + + SBPI_WDATA_3 + [31:0] + read-write + + + + + SBPI_RDATA_0 + 0x00000114 + Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_0 + [31:0] + read-only + modify + + + + + SBPI_RDATA_1 + 0x00000118 + Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_1 + [31:0] + read-only + modify + + + + + SBPI_RDATA_2 + 0x0000011c + Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_2 + [31:0] + read-only + modify + + + + + SBPI_RDATA_3 + 0x00000120 + Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_3 + [31:0] + read-only + modify + + + + + SBPI_STATUS + 0x00000124 + 0x00000000 + + + MISO + SBPI MISO (master in - slave out): response from SBPI + [23:16] + read-only + + + FLAG + SBPI flag + [12:12] + read-only + + + INSTR_MISS + Last instruction missed (dropped), as the previous has not finished running + [8:8] + read-write + oneToClear + + + INSTR_DONE + Last instruction done + [4:4] + read-write + oneToClear + + + RDATA_VLD + Read command has returned data + [0:0] + read-write + oneToClear + + + + + USR + 0x00000128 + Controls for APB data read interface (USER interface) + 0x00000001 + + + PD + Power-down; 1 disables current reference. Must be 0 to read data from the OTP. + [4:4] + read-write + + + DCTRL + 1 enables USER interface; 0 disables USER interface (enables SBPI). + + This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. + [0:0] + read-write + + + + + DBG + 0x0000012c + Debug for OTP power-on state machine + 0x00000000 + + + CUSTOMER_RMA_FLAG + The chip is in RMA mode + [12:12] + read-only + + + PSM_STATE + Monitor the PSM FSM's state + [7:4] + read-only + + + ROSC_UP + Ring oscillator is up and running + [3:3] + read-only + + + ROSC_UP_SEEN + Ring oscillator was seen up and running + [2:2] + read-write + oneToClear + + + BOOT_DONE + PSM boot done status flag + [1:1] + read-only + + + PSM_DONE + PSM done status flag + [0:0] + read-only + + + + + BIST + 0x00000134 + During BIST, count address locations that have at least one leaky bit + 0x0fff0000 + + + CNT_FAIL + Flag if the count of address locations with at least one leaky bit exceeds cnt_max + [30:30] + read-only + + + CNT_CLR + Clear counter before use + [29:29] + write-only + + + CNT_ENA + Enable the counter before the BIST function is initiated + [28:28] + read-write + + + CNT_MAX + The cnt_fail flag will be set if the number of leaky locations exceeds this number + [27:16] + read-write + + + CNT + Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. + [12:0] + read-only + + + + + CRT_KEY_W0 + 0x00000138 + Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W0 + [31:0] + write-only + + + + + CRT_KEY_W1 + 0x0000013c + Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W1 + [31:0] + write-only + + + + + CRT_KEY_W2 + 0x00000140 + Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W2 + [31:0] + write-only + + + + + CRT_KEY_W3 + 0x00000144 + Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W3 + [31:0] + write-only + + + + + CRITICAL + 0x00000148 + Quickly check values of critical flags read during boot up + 0x00000000 + + + RISCV_DISABLE + [17:17] + read-only + + + ARM_DISABLE + [16:16] + read-only + + + GLITCH_DETECTOR_SENS + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + [4:4] + read-only + + + DEFAULT_ARCHSEL + [3:3] + read-only + + + DEBUG_DISABLE + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + [1:1] + read-only + + + SECURE_BOOT_ENABLE + [0:0] + read-only + + + + + KEY_VALID + 0x0000014c + Which keys were valid (enrolled) at boot time + 0x00000000 + + + KEY_VALID + [7:0] + read-only + + + + + DEBUGEN + 0x00000150 + Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + + Specifically: + + - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. + + - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. + + - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + 0x00000000 + + + MISC + Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. + + These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [8:8] + read-write + + + PROC1_SECURE + Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). + + Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + [3:3] + read-write + + + PROC1 + Enable core 1's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [2:2] + read-write + + + PROC0_SECURE + Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). + + Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [1:1] + read-write + + + PROC0 + Enable core 0's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [0:0] + read-write + + + + + DEBUGEN_LOCK + 0x00000154 + Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + 0x00000000 + + + MISC + Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + [8:8] + read-write + + + PROC1_SECURE + Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. + [3:3] + read-write + + + PROC1 + Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + [2:2] + read-write + + + PROC0_SECURE + Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. + [1:1] + read-write + + + PROC0 + Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + [0:0] + read-write + + + + + ARCHSEL + 0x00000158 + Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. + + This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). + + Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. + + Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + 0x00000000 + + + CORE1 + Select architecture for core 1. + [1:1] + read-write + + + arm + 0 + Switch core 1 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 1 to RISC-V (Hazard3) + + + + + CORE0 + Select architecture for core 0. + [0:0] + read-write + + + arm + 0 + Switch core 0 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 0 to RISC-V (Hazard3) + + + + + + + ARCHSEL_STATUS + 0x0000015c + Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + 0x00000000 + + + CORE1 + Current architecture for core 0. Updated on processor warm reset. + [1:1] + read-only + + + arm + 0 + Core 1 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 1 is currently RISC-V (Hazard3) + + + + + CORE0 + Current architecture for core 0. Updated on processor warm reset. + [0:0] + read-only + + + arm + 0 + Core 0 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 0 is currently RISC-V (Hazard3) + + + + + + + BOOTDIS + 0x00000160 + Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the power manager BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. + [1:1] + read-write + + + NOW + When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + INTR + 0x00000164 + Raw Interrupts + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + oneToClear + + + APB_RD_SEC_FAIL + [3:3] + read-write + oneToClear + + + APB_DCTRL_FAIL + [2:2] + read-write + oneToClear + + + SBPI_WR_FAIL + [1:1] + read-write + oneToClear + + + SBPI_FLAG_N + [0:0] + read-only + + + + + INTE + 0x00000168 + Interrupt Enable + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTF + 0x0000016c + Interrupt Force + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTS + 0x00000170 + Interrupt status after masking & forcing + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-only + + + APB_RD_SEC_FAIL + [3:3] + read-only + + + APB_DCTRL_FAIL + [2:2] + read-only + + + SBPI_WR_FAIL + [1:1] + read-only + + + SBPI_FLAG_N + [0:0] + read-only + + + + + + + OTP_DATA + Predefined OTP data layout for RP2350 + 0x40130000 + + 0 + 7920 + registers + + + + CHIPID0 + 0x0000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 16 + 0x0000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x0002 + Bits 31:16 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x0004 + Bits 47:32 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0006 + Bits 63:48 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x0008 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 16 + 0x0000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x000a + Bits 31:16 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x000c + Bits 47:32 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x000e + Bits 63:48 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x0010 + Bits 79:64 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x0012 + Bits 95:80 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x0014 + Bits 111:96 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0016 + Bits 127:112 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x0020 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 16 + 0x0000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x0022 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 16 + 0x0000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x0030 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 16 + 0x0000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x006c + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 16 + 0x0000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x006e + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 16 + 0x0000 + + + INFO_CRC1 + [15:0] + read-only + + + + + FLASH_DEVINFO + 0x00a8 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 16 + 0x0000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00aa + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 16 + 0x0000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00ac + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 16 + 0x0000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x00ae + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 16 + 0x0000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00b0 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 16 + 0x0000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00b8 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 16 + 0x0000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00bc + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 16 + 0x0000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x00be + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 16 + 0x0000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00c0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00c2 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x0100 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x0102 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x0104 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0106 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x0108 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x010a + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x010c + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x010e + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x0110 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x0112 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x0114 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0116 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x0118 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x011a + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x011c + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x011e + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x0120 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x0122 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x0124 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0126 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x0128 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x012a + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x012c + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x012e + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x0130 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x0132 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x0134 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0136 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x0138 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x013a + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x013c + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x013e + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x0140 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x0142 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x0144 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0146 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x0148 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x014a + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x014c + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x014e + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x0150 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x0152 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x0154 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x0156 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x0158 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x015a + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x015c + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x015e + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x0160 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x0162 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x0164 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x0166 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x0168 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x016a + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x016c + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x016e + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x0170 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x0172 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x0174 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x0176 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x0178 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x017a + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x017c + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x017e + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x1e90 + Bits 15:0 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x1e92 + Bits 31:16 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x1e94 + Bits 47:32 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x1e96 + Bits 63:48 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x1e98 + Bits 79:64 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x1e9a + Bits 95:80 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x1e9c + Bits 111:96 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x1e9e + Bits 127:112 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x1ea0 + Bits 15:0 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x1ea2 + Bits 31:16 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x1ea4 + Bits 47:32 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x1ea6 + Bits 63:48 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x1ea8 + Bits 79:64 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x1eaa + Bits 95:80 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x1eac + Bits 111:96 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x1eae + Bits 127:112 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x1eb0 + Bits 15:0 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x1eb2 + Bits 31:16 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x1eb4 + Bits 47:32 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x1eb6 + Bits 63:48 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x1eb8 + Bits 79:64 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x1eba + Bits 95:80 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x1ebc + Bits 111:96 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x1ebe + Bits 127:112 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x1ec0 + Bits 15:0 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x1ec2 + Bits 31:16 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x1ec4 + Bits 47:32 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x1ec6 + Bits 63:48 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x1ec8 + Bits 79:64 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x1eca + Bits 95:80 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x1ecc + Bits 111:96 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x1ece + Bits 127:112 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x1ed0 + Bits 15:0 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x1ed2 + Bits 31:16 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x1ed4 + Bits 47:32 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x1ed6 + Bits 63:48 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x1ed8 + Bits 79:64 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x1eda + Bits 95:80 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x1edc + Bits 111:96 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x1ede + Bits 127:112 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x1ee0 + Bits 15:0 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x1ee2 + Bits 31:16 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x1ee4 + Bits 47:32 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x1ee6 + Bits 63:48 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x1ee8 + Bits 79:64 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x1eea + Bits 95:80 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x1eec + Bits 111:96 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x1eee + Bits 127:112 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_7 + [15:0] + read-only + + + + + + + OTP_DATA_RAW + Predefined OTP data layout for RP2350 + 0x40134000 + + 0 + 16384 + registers + + + + CHIPID0 + 0x00000000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 0x00000000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x00000004 + Bits 31:16 of public device ID (ECC) + 0x00000000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x00000008 + Bits 47:32 of public device ID (ECC) + 0x00000000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0000000c + Bits 63:48 of public device ID (ECC) + 0x00000000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x00000010 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 0x00000000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x00000014 + Bits 31:16 of private per-device random number (ECC) + 0x00000000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x00000018 + Bits 47:32 of private per-device random number (ECC) + 0x00000000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x0000001c + Bits 63:48 of private per-device random number (ECC) + 0x00000000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x00000020 + Bits 79:64 of private per-device random number (ECC) + 0x00000000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x00000024 + Bits 95:80 of private per-device random number (ECC) + 0x00000000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x00000028 + Bits 111:96 of private per-device random number (ECC) + 0x00000000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0000002c + Bits 127:112 of private per-device random number (ECC) + 0x00000000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x00000040 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 0x00000000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x00000044 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 0x00000000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x00000060 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 0x00000000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x000000d8 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 0x00000000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x000000dc + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 0x00000000 + + + INFO_CRC1 + [15:0] + read-only + + + + + CRIT0 + 0x000000e0 + Page 0 critical boot flags (RBIT-8) + 0x00000000 + + + RISCV_DISABLE + Permanently disable RISC-V processors (Hazard3) + [1:1] + read-only + + + ARM_DISABLE + Permanently disable ARM processors (Cortex-M33) + [0:0] + read-only + + + + + CRIT0_R1 + 0x000000e4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R1 + [23:0] + read-only + + + + + CRIT0_R2 + 0x000000e8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R2 + [23:0] + read-only + + + + + CRIT0_R3 + 0x000000ec + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R3 + [23:0] + read-only + + + + + CRIT0_R4 + 0x000000f0 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R4 + [23:0] + read-only + + + + + CRIT0_R5 + 0x000000f4 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R5 + [23:0] + read-only + + + + + CRIT0_R6 + 0x000000f8 + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R6 + [23:0] + read-only + + + + + CRIT0_R7 + 0x000000fc + Redundant copy of CRIT0 + 0x00000000 + + + CRIT0_R7 + [23:0] + read-only + + + + + CRIT1 + 0x00000100 + Page 1 critical boot flags (RBIT-8) + 0x00000000 + + + GLITCH_DETECTOR_SENS + Increase the sensitivity of the glitch detectors from their default. + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. + [4:4] + read-only + + + BOOT_ARCH + Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + [3:3] + read-only + + + DEBUG_DISABLE + Disable all debug access + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + Disable Secure debug access + [1:1] + read-only + + + SECURE_BOOT_ENABLE + Enable boot signature enforcement, and permanently disable the RISC-V cores. + [0:0] + read-only + + + + + CRIT1_R1 + 0x00000104 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R1 + [23:0] + read-only + + + + + CRIT1_R2 + 0x00000108 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R2 + [23:0] + read-only + + + + + CRIT1_R3 + 0x0000010c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R3 + [23:0] + read-only + + + + + CRIT1_R4 + 0x00000110 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R4 + [23:0] + read-only + + + + + CRIT1_R5 + 0x00000114 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R5 + [23:0] + read-only + + + + + CRIT1_R6 + 0x00000118 + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R6 + [23:0] + read-only + + + + + CRIT1_R7 + 0x0000011c + Redundant copy of CRIT1 + 0x00000000 + + + CRIT1_R7 + [23:0] + read-only + + + + + BOOT_FLAGS0 + 0x00000120 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DISABLE_SRAM_WINDOW_BOOT + [21:21] + read-only + + + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY + Disable all access to XIP after entering an SRAM binary. + + Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. + [20:20] + read-only + + + DISABLE_BOOTSEL_UART_BOOT + [19:19] + read-only + + + DISABLE_BOOTSEL_USB_PICOBOOT_IFC + [18:18] + read-only + + + DISABLE_BOOTSEL_USB_MSD_IFC + [17:17] + read-only + + + DISABLE_WATCHDOG_SCRATCH + [16:16] + read-only + + + DISABLE_POWER_SCRATCH + [15:15] + read-only + + + ENABLE_OTP_BOOT + Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. + + The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. + [14:14] + read-only + + + DISABLE_OTP_BOOT + Takes precedence over ENABLE_OTP_BOOT. + [13:13] + read-only + + + DISABLE_FLASH_BOOT + [12:12] + read-only + + + ROLLBACK_REQUIRED + Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. + [11:11] + read-only + + + HASHED_PARTITION_TABLE + Require a partition table to be hashed (if not signed) + [10:10] + read-only + + + SECURE_PARTITION_TABLE + Require a partition table to be signed + [9:9] + read-only + + + DISABLE_AUTO_SWITCH_ARCH + Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled + [8:8] + read-only + + + SINGLE_FLASH_BINARY + Restrict flash boot path to use of a single binary at the start of flash + [7:7] + read-only + + + OVERRIDE_FLASH_PARTITION_SLOT_SIZE + Override the limit for default flash metadata scanning. + + The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + [6:6] + read-only + + + FLASH_DEVINFO_ENABLE + Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. + [5:5] + read-only + + + FAST_SIGCHECK_ROSC_DIV + Enable quartering of ROSC divisor during signature check, to reduce secure boot time + [4:4] + read-only + + + FLASH_IO_VOLTAGE_1V8 + If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. + + If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) + [3:3] + read-only + + + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. + + Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. + + If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. + [2:2] + read-only + + + ENABLE_BOOTSEL_LED + Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid + [1:1] + read-only + + + DISABLE_BOOTSEL_EXEC2 + [0:0] + read-only + + + + + BOOT_FLAGS0_R1 + 0x00000124 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R1 + [23:0] + read-only + + + + + BOOT_FLAGS0_R2 + 0x00000128 + Redundant copy of BOOT_FLAGS0 + 0x00000000 + + + BOOT_FLAGS0_R2 + [23:0] + read-only + + + + + BOOT_FLAGS1 + 0x0000012c + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x00000000 + + + DOUBLE_TAP + Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. + + This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. + [19:19] + read-only + + + DOUBLE_TAP_DELAY + Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. + + For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. + + 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + [18:16] + read-only + + + KEY_INVALID + Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. + [11:8] + read-only + + + KEY_VALID + Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. + + Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. + + Do not enable secure boot without first installing a valid key. This will render your device unbootable. + [3:0] + read-only + + + + + BOOT_FLAGS1_R1 + 0x00000130 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R1 + [23:0] + read-only + + + + + BOOT_FLAGS1_R2 + 0x00000134 + Redundant copy of BOOT_FLAGS1 + 0x00000000 + + + BOOT_FLAGS1_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0 + 0x00000138 + Default boot version thermometer counter, bits 23:0 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION0 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R1 + 0x0000013c + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R2 + 0x00000140 + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1 + 0x00000144 + Default boot version thermometer counter, bits 47:24 (RBIT-3) + 0x00000000 + + + DEFAULT_BOOT_VERSION1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R1 + 0x00000148 + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R2 + 0x0000014c + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R2 + [23:0] + read-only + + + + + FLASH_DEVINFO + 0x00000150 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 0x00000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00000154 + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 0x00000000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00000158 + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 0x00000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x0000015c + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 0x00000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00000160 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 0x00000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_BOOT_FLAGS + 0x00000164 + USB boot specific feature flags (RBIT-3) + 0x00000000 + + + DP_DM_SWAP + Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). + [23:23] + read-only + + + WHITE_LABEL_ADDR_VALID + valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) + [22:22] + read-only + + + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID + valid flag for the USB_WHITE_LABEL_ADDR field + [15:15] + read-only + + + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID + valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) + [14:14] + read-only + + + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) + [13:13] + read-only + + + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) + [12:12] + read-only + + + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID + valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) + [11:11] + read-only + + + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID + valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) + [10:10] + read-only + + + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID + valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) + [9:9] + read-only + + + WL_VOLUME_LABEL_STRDEF_VALID + valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) + [8:8] + read-only + + + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID + valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) + [7:7] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID + valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) + [6:6] + read-only + + + WL_USB_DEVICE_PRODUCT_STRDEF_VALID + valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) + [5:5] + read-only + + + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID + valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) + [4:4] + read-only + + + WL_USB_DEVICE_LANG_ID_VALUE_VALID + valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) + [3:3] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID + valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) + [2:2] + read-only + + + WL_USB_DEVICE_PID_VALUE_VALID + valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) + [1:1] + read-only + + + WL_USB_DEVICE_VID_VALUE_VALID + valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) + [0:0] + read-only + + + + + USB_BOOT_FLAGS_R1 + 0x00000168 + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R1 + [23:0] + read-only + + + + + USB_BOOT_FLAGS_R2 + 0x0000016c + Redundant copy of USB_BOOT_FLAGS + 0x00000000 + + + USB_BOOT_FLAGS_R2 + [23:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00000170 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 0x00000000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00000178 + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 0x00000000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x0000017c + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 0x00000000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00000180 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00000184 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x00000000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x00000200 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x00000204 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x00000208 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0000020c + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x00000210 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x00000214 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x00000218 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x0000021c + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x00000220 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x00000224 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x00000228 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0000022c + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x00000230 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x00000234 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x00000238 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x0000023c + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 0x00000000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x00000240 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x00000244 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x00000248 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0000024c + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x00000250 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x00000254 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x00000258 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x0000025c + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x00000260 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x00000264 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x00000268 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0000026c + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x00000270 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x00000274 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x00000278 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x0000027c + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 0x00000000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x00000280 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x00000284 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x00000288 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0000028c + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x00000290 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x00000294 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x00000298 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x0000029c + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x000002a0 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x000002a4 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x000002a8 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x000002ac + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x000002b0 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x000002b4 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x000002b8 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x000002bc + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 0x00000000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x000002c0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x000002c4 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x000002c8 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x000002cc + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x000002d0 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x000002d4 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x000002d8 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x000002dc + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x000002e0 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x000002e4 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x000002e8 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x000002ec + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x000002f0 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x000002f4 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x000002f8 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x000002fc + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 0x00000000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x00003d20 + Bits 15:0 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x00003d24 + Bits 31:16 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x00003d28 + Bits 47:32 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x00003d2c + Bits 63:48 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x00003d30 + Bits 79:64 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x00003d34 + Bits 95:80 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x00003d38 + Bits 111:96 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x00003d3c + Bits 127:112 of OTP access key 1 (ECC) + 0x00000000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x00003d40 + Bits 15:0 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x00003d44 + Bits 31:16 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x00003d48 + Bits 47:32 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x00003d4c + Bits 63:48 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x00003d50 + Bits 79:64 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x00003d54 + Bits 95:80 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x00003d58 + Bits 111:96 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x00003d5c + Bits 127:112 of OTP access key 2 (ECC) + 0x00000000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x00003d60 + Bits 15:0 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x00003d64 + Bits 31:16 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x00003d68 + Bits 47:32 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x00003d6c + Bits 63:48 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x00003d70 + Bits 79:64 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x00003d74 + Bits 95:80 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x00003d78 + Bits 111:96 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x00003d7c + Bits 127:112 of OTP access key 3 (ECC) + 0x00000000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x00003d80 + Bits 15:0 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x00003d84 + Bits 31:16 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x00003d88 + Bits 47:32 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x00003d8c + Bits 63:48 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x00003d90 + Bits 79:64 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x00003d94 + Bits 95:80 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x00003d98 + Bits 111:96 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x00003d9c + Bits 127:112 of OTP access key 4 (ECC) + 0x00000000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x00003da0 + Bits 15:0 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x00003da4 + Bits 31:16 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x00003da8 + Bits 47:32 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x00003dac + Bits 63:48 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x00003db0 + Bits 79:64 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x00003db4 + Bits 95:80 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x00003db8 + Bits 111:96 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x00003dbc + Bits 127:112 of OTP access key 5 (ECC) + 0x00000000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x00003dc0 + Bits 15:0 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x00003dc4 + Bits 31:16 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x00003dc8 + Bits 47:32 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x00003dcc + Bits 63:48 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x00003dd0 + Bits 79:64 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x00003dd4 + Bits 95:80 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x00003dd8 + Bits 111:96 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x00003ddc + Bits 127:112 of OTP access key 6 (ECC) + 0x00000000 + + + KEY6_7 + [15:0] + read-only + + + + + KEY1_VALID + 0x00003de4 + Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY2_VALID + 0x00003de8 + Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY3_VALID + 0x00003dec + Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY4_VALID + 0x00003df0 + Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY5_VALID + 0x00003df4 + Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY6_VALID + 0x00003df8 + Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + PAGE0_LOCK0 + 0x00003e00 + Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE0_LOCK1 + 0x00003e04 + Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE1_LOCK0 + 0x00003e08 + Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE1_LOCK1 + 0x00003e0c + Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE2_LOCK0 + 0x00003e10 + Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE2_LOCK1 + 0x00003e14 + Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE3_LOCK0 + 0x00003e18 + Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE3_LOCK1 + 0x00003e1c + Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE4_LOCK0 + 0x00003e20 + Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE4_LOCK1 + 0x00003e24 + Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE5_LOCK0 + 0x00003e28 + Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE5_LOCK1 + 0x00003e2c + Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE6_LOCK0 + 0x00003e30 + Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE6_LOCK1 + 0x00003e34 + Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE7_LOCK0 + 0x00003e38 + Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE7_LOCK1 + 0x00003e3c + Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE8_LOCK0 + 0x00003e40 + Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE8_LOCK1 + 0x00003e44 + Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE9_LOCK0 + 0x00003e48 + Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE9_LOCK1 + 0x00003e4c + Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE10_LOCK0 + 0x00003e50 + Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE10_LOCK1 + 0x00003e54 + Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE11_LOCK0 + 0x00003e58 + Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE11_LOCK1 + 0x00003e5c + Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE12_LOCK0 + 0x00003e60 + Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE12_LOCK1 + 0x00003e64 + Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE13_LOCK0 + 0x00003e68 + Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE13_LOCK1 + 0x00003e6c + Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE14_LOCK0 + 0x00003e70 + Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE14_LOCK1 + 0x00003e74 + Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE15_LOCK0 + 0x00003e78 + Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE15_LOCK1 + 0x00003e7c + Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE16_LOCK0 + 0x00003e80 + Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE16_LOCK1 + 0x00003e84 + Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE17_LOCK0 + 0x00003e88 + Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE17_LOCK1 + 0x00003e8c + Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE18_LOCK0 + 0x00003e90 + Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE18_LOCK1 + 0x00003e94 + Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE19_LOCK0 + 0x00003e98 + Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE19_LOCK1 + 0x00003e9c + Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE20_LOCK0 + 0x00003ea0 + Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE20_LOCK1 + 0x00003ea4 + Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE21_LOCK0 + 0x00003ea8 + Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE21_LOCK1 + 0x00003eac + Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE22_LOCK0 + 0x00003eb0 + Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE22_LOCK1 + 0x00003eb4 + Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE23_LOCK0 + 0x00003eb8 + Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE23_LOCK1 + 0x00003ebc + Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE24_LOCK0 + 0x00003ec0 + Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE24_LOCK1 + 0x00003ec4 + Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE25_LOCK0 + 0x00003ec8 + Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE25_LOCK1 + 0x00003ecc + Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE26_LOCK0 + 0x00003ed0 + Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE26_LOCK1 + 0x00003ed4 + Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE27_LOCK0 + 0x00003ed8 + Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE27_LOCK1 + 0x00003edc + Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE28_LOCK0 + 0x00003ee0 + Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE28_LOCK1 + 0x00003ee4 + Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE29_LOCK0 + 0x00003ee8 + Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE29_LOCK1 + 0x00003eec + Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE30_LOCK0 + 0x00003ef0 + Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE30_LOCK1 + 0x00003ef4 + Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE31_LOCK0 + 0x00003ef8 + Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE31_LOCK1 + 0x00003efc + Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE32_LOCK0 + 0x00003f00 + Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE32_LOCK1 + 0x00003f04 + Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE33_LOCK0 + 0x00003f08 + Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE33_LOCK1 + 0x00003f0c + Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE34_LOCK0 + 0x00003f10 + Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE34_LOCK1 + 0x00003f14 + Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE35_LOCK0 + 0x00003f18 + Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE35_LOCK1 + 0x00003f1c + Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE36_LOCK0 + 0x00003f20 + Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE36_LOCK1 + 0x00003f24 + Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE37_LOCK0 + 0x00003f28 + Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE37_LOCK1 + 0x00003f2c + Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE38_LOCK0 + 0x00003f30 + Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE38_LOCK1 + 0x00003f34 + Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE39_LOCK0 + 0x00003f38 + Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE39_LOCK1 + 0x00003f3c + Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE40_LOCK0 + 0x00003f40 + Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE40_LOCK1 + 0x00003f44 + Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE41_LOCK0 + 0x00003f48 + Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE41_LOCK1 + 0x00003f4c + Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE42_LOCK0 + 0x00003f50 + Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE42_LOCK1 + 0x00003f54 + Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE43_LOCK0 + 0x00003f58 + Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE43_LOCK1 + 0x00003f5c + Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE44_LOCK0 + 0x00003f60 + Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE44_LOCK1 + 0x00003f64 + Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE45_LOCK0 + 0x00003f68 + Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE45_LOCK1 + 0x00003f6c + Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE46_LOCK0 + 0x00003f70 + Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE46_LOCK1 + 0x00003f74 + Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE47_LOCK0 + 0x00003f78 + Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE47_LOCK1 + 0x00003f7c + Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE48_LOCK0 + 0x00003f80 + Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE48_LOCK1 + 0x00003f84 + Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE49_LOCK0 + 0x00003f88 + Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE49_LOCK1 + 0x00003f8c + Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE50_LOCK0 + 0x00003f90 + Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE50_LOCK1 + 0x00003f94 + Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE51_LOCK0 + 0x00003f98 + Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE51_LOCK1 + 0x00003f9c + Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE52_LOCK0 + 0x00003fa0 + Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE52_LOCK1 + 0x00003fa4 + Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE53_LOCK0 + 0x00003fa8 + Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE53_LOCK1 + 0x00003fac + Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE54_LOCK0 + 0x00003fb0 + Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE54_LOCK1 + 0x00003fb4 + Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE55_LOCK0 + 0x00003fb8 + Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE55_LOCK1 + 0x00003fbc + Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE56_LOCK0 + 0x00003fc0 + Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE56_LOCK1 + 0x00003fc4 + Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE57_LOCK0 + 0x00003fc8 + Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE57_LOCK1 + 0x00003fcc + Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE58_LOCK0 + 0x00003fd0 + Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE58_LOCK1 + 0x00003fd4 + Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE59_LOCK0 + 0x00003fd8 + Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE59_LOCK1 + 0x00003fdc + Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE60_LOCK0 + 0x00003fe0 + Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE60_LOCK1 + 0x00003fe4 + Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE61_LOCK0 + 0x00003fe8 + Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE61_LOCK1 + 0x00003fec + Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE62_LOCK0 + 0x00003ff0 + Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE62_LOCK1 + 0x00003ff4 + Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE63_LOCK0 + 0x00003ff8 + Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + RMA + Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. + [7:7] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE63_LOCK1 + 0x00003ffc + Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + + + TBMAN + For managing simulation testbenches + 0x40160000 + + 0 + 4 + registers + + + + PLATFORM + 0x00000000 + Indicates the type of platform in use + 0x00000001 + + + HDLSIM + Indicates the platform is a simulation + [2:2] + read-only + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0 + 256 + registers + + + + SETUP_PACKET_LOW + 0x00000000 + Bytes 0-3 of the SETUP packet from the host. + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + 0x00000004 + Bytes 4-7 of the setup packet from the host. + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x00000008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x0000000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x00000010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x00000014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x00000018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x0000001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x00000020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x00000024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x00000028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x0000002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x00000030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x00000034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x00000038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x0000003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x00000040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x00000044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x00000048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x0000004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x00000050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x00000054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x00000058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x0000005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x00000060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x00000064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x00000068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x0000006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x00000070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x00000074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x00000078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x0000007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + 0x00000080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + 0x00000084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + 0x00000088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + 0x0000008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + 0x00000090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + 0x00000094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + 0x00000098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + 0x0000009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + 0x000000a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + 0x000000a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + 0x000000a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + 0x000000ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + 0x000000b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + 0x000000b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + 0x000000b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + 0x000000bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + 0x000000c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + 0x000000c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + 0x000000c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + 0x000000cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + 0x000000d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + 0x000000d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + 0x000000d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + 0x000000dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + 0x000000e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + 0x000000e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + 0x000000e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + 0x000000ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + 0x000000f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + 0x000000f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + 0x000000f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + 0x000000fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + + + diff --git a/WEEK04/slides/WEEK04-IMG00.svg b/WEEK04/slides/WEEK04-IMG00.svg new file mode 100644 index 0000000..2b2aae1 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 04 + + +Variables in Embedded Systems: +Debugging and Hacking Variables +w/ GPIO Output Basics + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK04/slides/WEEK04-IMG01.svg b/WEEK04/slides/WEEK04-IMG01.svg new file mode 100644 index 0000000..5331adf --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG01.svg @@ -0,0 +1,96 @@ + + + + + +What is a Variable? +Labeled Boxes in Memory (SRAM) + + + +Memory — A Row of Numbered Boxes + + + +42 +age +Box 0 + + + +17 +score +Box 1 + + + +0 +count +Box 2 + + + +255 +max +Box 3 + + + +99 +temp +Box 4 + + + +Anatomy of a Declaration + + +uint8_t age = 42; + +uint8_t +Data type (1 byte) + +age +Variable name (label) + += 42 +Initial value + +; +End of statement + + + +Key Concepts + + +Declaration +name + type + + +Definition +allocates memory + + +Initialization +assigns value + + + +Important Rule +You MUST declare a +variable BEFORE you +use it! +Compiler needs to know the type + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG02.svg b/WEEK04/slides/WEEK04-IMG02.svg new file mode 100644 index 0000000..8933406 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG02.svg @@ -0,0 +1,86 @@ + + + + + +Data Types & Sizes +How Much Memory Each Type Uses + + + + + + +Type +Size +Range +Description + + + +uint8_t +1 byte +0 — 255 +Unsigned 8-bit + + + +int8_t +1 byte +-128 — 127 +Signed 8-bit + + + +uint16_t +2 bytes +0 — 65,535 +Unsigned 16-bit + + + +int16_t +2 bytes +-32,768 — 32,767 +Signed 16-bit + + + +uint32_t +4 bytes +0 — 4,294,967,295 +Unsigned 32-bit + + + +int32_t +4 bytes +-2.1B — 2.1B +Signed 32-bit + + +Size Comparison + + +1B +uint8_t + + +2B +uint16_t + + +4 Bytes +uint32_t + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG03.svg b/WEEK04/slides/WEEK04-IMG03.svg new file mode 100644 index 0000000..0cbcf5a --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG03.svg @@ -0,0 +1,63 @@ + + + + + +Memory Sections +Where Variables Live After Compilation + + + + +.data +Flash -> copied to RAM at startup +Contains: Initialized global/static variables +int counter = 42; +Initial value stored in flash, copied to SRAM by data_cpy + + + + +.bss +RAM — zeroed at startup +Contains: Uninitialized global/static variables +int counter; +NOT stored in binary (saves space!) — memset to 0 at boot + + + + +.rodata +Flash — read only +Contains: Constants and string literals +const int MAX = 100; +Lives in flash permanently — cannot be modified at runtime + + + +.data +RAM +Writable +Initialized globals + +.bss +RAM +Writable +Uninitialized globals (zeroed) + +.rodata +Flash +Read-only +Constants & strings + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG04.svg b/WEEK04/slides/WEEK04-IMG04.svg new file mode 100644 index 0000000..82437d2 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG04.svg @@ -0,0 +1,79 @@ + + + + + +GPIO Basics +General Purpose Input/Output on RP2350 + + + +Pico 2 GPIO Pins + +GPIO 16 + +Red LED + +GPIO 17 + +Green LED + +GPIO 18 + +Blue LED + +GPIO 25 + +Onboard LED + +Software-controlled switches + + + +Pico SDK Functions + + +gpio_init(pin) +Init pin + + +gpio_set_dir(pin,d) +I/O dir + + +gpio_put(pin,val) +Set H/L + + +sleep_ms(ms) +Delay + + + +Basic LED Blink Code + + +#define LED_PIN 16 +int main(void) { +gpio_init(LED_PIN); +gpio_set_dir(LED_PIN, GPIO_OUT); +while (true) { +gpio_put(LED_PIN, 1); +// ON +sleep_ms(500); +gpio_put(LED_PIN, 0); +// OFF +sleep_ms(500); +}} + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG05.svg b/WEEK04/slides/WEEK04-IMG05.svg new file mode 100644 index 0000000..c6a0ef6 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG05.svg @@ -0,0 +1,79 @@ + + + + + +Ghidra Binary Analysis +Analyzing a Raw .bin Without Symbols + + + +1. Import + +File -> Import +Language: +ARM Cortex 32 LE +Block: +.text +Base: +10000000 +XIP address for RP2350 + + + +2. Analyze + +Auto-Analyze: Yes +Ghidra finds: +FUN_1000019a +FUN_10000210 +FUN_10000234 +Auto-generated names + + + +3. Resolve + +Edit Function Sig +Rename to: +data_cpy +frame_dummy +main +Fix signatures + + + +Decompiled main() in Ghidra + + +Before Resolving: +void FUN_10000234(void){ +FUN_10002f54(); +do { +FUN_100030e4( +DAT_10000244,0x2b); +} while(true); +} + + +After Resolving: +int main(void) { +stdio_init_all(); +do { +printf( +"age: %d\r\n" +, 0x2b); +} while(true); +} + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG06.svg b/WEEK04/slides/WEEK04-IMG06.svg new file mode 100644 index 0000000..156aeeb --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG06.svg @@ -0,0 +1,77 @@ + + + + + +Compiler Optimization +Why Your Variable Disappeared + + + +Source Code + + +int main(void) { +uint8_t age = 42; +age = 43; +stdio_init_all(); +while (true) +printf("age: %d", age); + + + +Compiler Thinks... + + +age = 42 is NEVER read + + +Dead store -> REMOVED + + +age = 43 -> constant fold + +Replaces variable with literal + + + +Resulting Assembly + + +1000023a +2b 21 +movs r1, #0x2b +; 0x2b = 43 +No age=42 instruction — compiler removed it + + + +Key Takeaway + + +Source Code +age = 42 +age = 43 + +-> + + +Binary +movs r1, #0x2b + + +Compiler +Optimizes dead +stores away! + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG07.svg b/WEEK04/slides/WEEK04-IMG07.svg new file mode 100644 index 0000000..2041444 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG07.svg @@ -0,0 +1,86 @@ + + + + + +Binary Patching +Changing Values in the Binary + + + +Before Patch + + +1000023a +2b 21 +movs r1,#0x2b + +0x2b = 43 decimal +Output: +age: 43 +Compiler-optimized constant + + + +After Patch + + +1000023a +46 21 +movs r1,#0x46 + +0x46 = 70 decimal +Output: +age: 70 +Changed program behavior! + + + +How to Patch in Ghidra + + +1. Find Instr + +-> + + +2. Rt-Click + +-> + + +3. Patch Val + +-> + + +Done! + +Patch Instruction: change operand + + + +Export Patched Binary + + +File: Export + + +Format: Raw Bytes + + +Save as *-h.bin + +Exported binary has your patches + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG08.svg b/WEEK04/slides/WEEK04-IMG08.svg new file mode 100644 index 0000000..eada6e7 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG08.svg @@ -0,0 +1,99 @@ + + + + + +GPIO Hacking +Patching GPIO 16 to GPIO 17 + + + +Original: GPIO 16 +Red LED on pin 16 + + +1000023a +10 20 +movs r0,#0x10 + + +10000244 +10 23 +movs r3,#0x10 + + +10000252 +10 24 +movs r4,#0x10 + +0x10 = 16, three locations + + + +Patched: GPIO 17 +Green LED on pin 17 + + +1000023a +11 20 +movs r0,#0x11 + + +10000244 +11 23 +movs r3,#0x11 + + +10000252 +11 24 +movs r4,#0x11 + +0x11 = 17, all patched! + + + +What Each Patch Controls + + +gpio_init +r0 + + +gpio_set_dir +r3 + + +gpio_put +r4 + +ALL pin refs must be patched + + + +Bonus: Change Print Value + + +00 21 +movs r1,#0x0 +age: 0 + +-> + + +42 21 +movs r1,#0x42 +age: 66 + +Changed value: 0 to 66 (0x42) + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG09.svg b/WEEK04/slides/WEEK04-IMG09.svg new file mode 100644 index 0000000..6743432 --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG09.svg @@ -0,0 +1,78 @@ + + + + + +GPIO Coprocessor +RP2350 Single-Cycle I/O via mcrr + + + +mcrr Instruction Breakdown + + +mcrr p0, #4, r4, r5, c0 + +mcrr +Move to Coprocessor (2 regs) +p0 +Coprocessor 0 (GPIO) +r4 +GPIO pin number +r5 +Value (0=LOW, 1=HIGH) + + + +Output Value (c0) + + +mcrr p0,#4,r4,r5,c0 + +r4 = pin number +r5 = 0 or 1 +Controls GPIO output state + + +Output Enable (c4) + + +mcrr p0,#4,r4,r5,c4 + +r4 = pin number +r5 = 1 (enable output) +Sets pin direction to OUTPUT + + + +gpio_init(16) Sequence + + +Step 1: Config Pad +addr 0x40038044 + + +Step 2: Set Func +FUNCSEL = 5 (SIO) + + +Step 3: Enable Out +mcrr p0,#4,r4,r5,c4 + + + + +Pad: clear OD, set IE, clear ISO +SIO = fast single-cycle GPIO access + \ No newline at end of file diff --git a/WEEK04/slides/WEEK04-IMG10.svg b/WEEK04/slides/WEEK04-IMG10.svg new file mode 100644 index 0000000..23741fe --- /dev/null +++ b/WEEK04/slides/WEEK04-IMG10.svg @@ -0,0 +1,119 @@ + + + + + +Full Patching Pipeline +End-to-End Binary Hacking Workflow + + + + +1 +Import .bin +Ghidra: Import +ARM Cortex 32 LE +Base: 0x10000000 + + + + + + + +2 +Analyze +Auto-analyze +Rename functions +Fix signatures + + + + + + + +3 +Find Target +Listing window +Find movs rN,#val +Identify bytes to change + + + + +4 +Patch +Right-click: +Patch Instruction +Change operand value + + + + + + + +5 +Export +File: Export +Format: Raw Bytes +Save as *-h.bin + + + + + + + +6 +Convert UF2 +uf2conv.py +--family 0xe48bff59 +RP2350 family ID + + + +UF2 Command + +python uf2conv.py file.bin --base 0x10000000 -o hacked.uf2 + + + +Flash to Pico 2 +1. Hold BOOTSEL + USB +2. Drop hacked.uf2 +3. Pico reboots hacked +RPI-RP2 drive in BOOTSEL + + + +Key Sections + +.text +Flash +Code + +.rodata +Flash +Constants + +.data +RAM +Init globals + +.bss +RAM +Zeroed globals + \ No newline at end of file diff --git a/WEEK05/0x000b_integer-data-type/.gitignore b/WEEK05/0x000b_integer-data-type/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK05/0x000b_integer-data-type/.vscode/c_cpp_properties.json b/WEEK05/0x000b_integer-data-type/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK05/0x000b_integer-data-type/.vscode/cmake-kits.json b/WEEK05/0x000b_integer-data-type/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK05/0x000b_integer-data-type/.vscode/extensions.json b/WEEK05/0x000b_integer-data-type/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK05/0x000b_integer-data-type/.vscode/launch.json b/WEEK05/0x000b_integer-data-type/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK05/0x000b_integer-data-type/.vscode/settings.json b/WEEK05/0x000b_integer-data-type/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK05/0x000b_integer-data-type/.vscode/tasks.json b/WEEK05/0x000b_integer-data-type/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK05/0x000b_integer-data-type/0x000b_integer-data-type.c b/WEEK05/0x000b_integer-data-type/0x000b_integer-data-type.c new file mode 100644 index 0000000..6a0d6ab --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/0x000b_integer-data-type.c @@ -0,0 +1,67 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + uint8_t age = 43; + int8_t range = -42; + + stdio_init_all(); + + __asm volatile ( + "ldr r3, =0x40038000\n" // address of PADS_BANK0_BASE + "ldr r2, =0x40028004\n" // address of IO_BANK0 GPIO0.ctrl + "movs r0, #16\n" // GPIO16 (start pin) + + "init_loop:\n" // loop start + "lsls r1, r0, #2\n" // pin * 4 (pad offset) + "adds r4, r3, r1\n" // PADS base + offset + "ldr r5, [r4]\n" // load current config + "bic r5, r5, #0x180\n" // clear OD+ISO + "orr r5, r5, #0x40\n" // set IE + "str r5, [r4]\n" // store updated config + + "lsls r1, r0, #3\n" // pin * 8 (ctrl offset) + "adds r4, r2, r1\n" // IO_BANK0 base + offset + "ldr r5, [r4]\n" // load current config + "bic r5, r5, #0x1f\n" // clear FUNCSEL bits [4:0] + "orr r5, r5, #5\n" // set FUNCSEL = 5 (SIO) + "str r5, [r4]\n" // store updated config + + "mov r4, r0\n" // pin + "movs r5, #1\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c4\n" // gpioc_bit_oe_put(pin,1) + "adds r0, r0, #1\n" // increment pin + "cmp r0, #20\n" // stop after pin 18 + "blt init_loop\n" // loop until r0 == 20 + ); + + uint8_t pin = 16; + + while (1) { + __asm volatile ( + "mov r4, %0\n" // pin + "movs r5, #0x01\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c0\n" // gpioc_bit_out_put(16, 1) + : + : "r"(pin) + : "r4","r5" + ); + sleep_ms(500); + + __asm volatile ( + "mov r4, %0\n" // pin + "movs r5, #0\n" // bit 0; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c0\n" // gpioc_bit_out_put(16, 0) + : + : "r"(pin) + : "r4","r5" + ); + sleep_ms(500); + + pin++; + if (pin > 18) pin = 16; + + printf("age: %d\r\n", age); + printf("range: %d\r\n", range); + } +} diff --git a/WEEK05/0x000b_integer-data-type/CMakeLists.txt b/WEEK05/0x000b_integer-data-type/CMakeLists.txt new file mode 100644 index 0000000..6178a2a --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x000b_integer-data-type C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x000b_integer-data-type 0x000b_integer-data-type.c ) + +pico_set_program_name(0x000b_integer-data-type "0x000b_integer-data-type") +pico_set_program_version(0x000b_integer-data-type "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x000b_integer-data-type 1) +pico_enable_stdio_usb(0x000b_integer-data-type 0) + +# Add the standard library to the build +target_link_libraries(0x000b_integer-data-type + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x000b_integer-data-type PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x000b_integer-data-type) + diff --git a/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.bin b/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.bin new file mode 100755 index 0000000..c1a873d Binary files /dev/null and b/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.bin differ diff --git a/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.dis b/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.dis new file mode 100644 index 0000000..5a52cee --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/build/0x000b_integer-data-type.dis @@ -0,0 +1,5882 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x000b_integer-data-type/build/0x000b_integer-data-type.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00003614 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001c0 10003618 10003618 00004618 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100037d8 100037d8 000047d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 100037e0 100037e0 000047e0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005d3c 2**0 + CONTENTS + 6 .data 0000051c 20000110 1000380c 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005d3c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003d28 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003d28 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005d3c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005d3c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003d28 10003d28 00005d28 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005d3c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005d70 2**0 + CONTENTS, READONLY + 17 .debug_info 0002086f 00000000 00000000 00005db5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 0000562f 00000000 00000000 00026624 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 00010037 00000000 00000000 0002bc53 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000be8 00000000 00000000 0003bc90 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 0000304a 00000000 00000000 0003c878 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00015a79 00000000 00000000 0003f8c2 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005748 00000000 00000000 0005533b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f3c 00000000 00000000 0005aa84 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002bf 00000000 00000000 0005c9c0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x000b_integer-data-type/build/0x000b_integer-data-type.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100037e0 .word 0x100037e0 +1000012c: 1000380c .word 0x1000380c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003bf0 .word 0x00003bf0 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 1000380c .word 0x1000380c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003d28 .word 0x10003d28 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003d28 .word 0x10003d28 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002e7d .word 0x10002e7d +100001dc: 10000235 .word 0x10000235 +100001e0: 10002e75 .word 0x10002e75 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 10003614 .word 0x10003614 + +10000234
: +10000234: b570 push {r4, r5, r6, lr} +10000236: f002 ff49 bl 100030cc +1000023a: 4b20 ldr r3, [pc, #128] @ (100002bc ) +1000023c: 4a20 ldr r2, [pc, #128] @ (100002c0 ) +1000023e: 2010 movs r0, #16 + +10000240 : +10000240: 0081 lsls r1, r0, #2 +10000242: 185c adds r4, r3, r1 +10000244: 6825 ldr r5, [r4, #0] +10000246: f425 75c0 bic.w r5, r5, #384 @ 0x180 +1000024a: f045 0540 orr.w r5, r5, #64 @ 0x40 +1000024e: 6025 str r5, [r4, #0] +10000250: 00c1 lsls r1, r0, #3 +10000252: 1854 adds r4, r2, r1 +10000254: 6825 ldr r5, [r4, #0] +10000256: f025 051f bic.w r5, r5, #31 +1000025a: f045 0505 orr.w r5, r5, #5 +1000025e: 6025 str r5, [r4, #0] +10000260: 4604 mov r4, r0 +10000262: 2501 movs r5, #1 +10000264: ec45 4044 gpioc_bit_oe_put r4, r5 +10000268: 3001 adds r0, #1 +1000026a: 2814 cmp r0, #20 +1000026c: dbe8 blt.n 10000240 +1000026e: 2610 movs r6, #16 +10000270: 4634 mov r4, r6 +10000272: 2501 movs r5, #1 +10000274: ec45 4040 gpioc_bit_out_put r4, r5 +10000278: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000027c: f000 fd48 bl 10000d10 +10000280: 4634 mov r4, r6 +10000282: 2500 movs r5, #0 +10000284: ec45 4040 gpioc_bit_out_put r4, r5 +10000288: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000028c: f000 fd40 bl 10000d10 +10000290: 2e13 cmp r6, #19 +10000292: f04f 012b mov.w r1, #43 @ 0x2b +10000296: f106 0601 add.w r6, r6, #1 +1000029a: 4806 ldr r0, [pc, #24] @ (100002b4 ) +1000029c: bf0c ite eq +1000029e: 2610 moveq r6, #16 +100002a0: b2f6 uxtbne r6, r6 +100002a2: f002 ffdb bl 1000325c <__wrap_printf> +100002a6: f06f 0129 mvn.w r1, #41 @ 0x29 +100002aa: 4803 ldr r0, [pc, #12] @ (100002b8 ) +100002ac: f002 ffd6 bl 1000325c <__wrap_printf> +100002b0: e7de b.n 10000270 +100002b2: bf00 nop +100002b4: 10003618 .word 0x10003618 +100002b8: 10003624 .word 0x10003624 +100002bc: 40038000 .word 0x40038000 +100002c0: 40028004 .word 0x40028004 + +100002c4 : +100002c4: b410 push {r4} +100002c6: f44f 7480 mov.w r4, #256 @ 0x100 +100002ca: 4b0c ldr r3, [pc, #48] @ (100002fc ) +100002cc: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100002d0: eb03 0380 add.w r3, r3, r0, lsl #2 +100002d4: 00c0 lsls r0, r0, #3 +100002d6: f082 0240 eor.w r2, r2, #64 @ 0x40 +100002da: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100002de: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +100002e2: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100002e6: f500 3020 add.w r0, r0, #163840 @ 0x28000 +100002ea: f503 5340 add.w r3, r3, #12288 @ 0x3000 +100002ee: f8cc 2000 str.w r2, [ip] +100002f2: 6041 str r1, [r0, #4] +100002f4: 601c str r4, [r3, #0] +100002f6: f85d 4b04 ldr.w r4, [sp], #4 +100002fa: 4770 bx lr +100002fc: 40038004 .word 0x40038004 + +10000300 : +10000300: b40f push {r0, r1, r2, r3} +10000302: b500 push {lr} +10000304: b083 sub sp, #12 +10000306: 9c04 ldr r4, [sp, #16] +10000308: 4807 ldr r0, [pc, #28] @ (10000328 ) +1000030a: f002 ff27 bl 1000315c <__wrap_puts> +1000030e: b13c cbz r4, 10000320 +10000310: a905 add r1, sp, #20 +10000312: 4620 mov r0, r4 +10000314: 9101 str r1, [sp, #4] +10000316: f002 fd93 bl 10002e40 +1000031a: 4804 ldr r0, [pc, #16] @ (1000032c ) +1000031c: f002 ff1e bl 1000315c <__wrap_puts> +10000320: 2001 movs r0, #1 +10000322: f002 fda5 bl 10002e70 <_exit> +10000326: bf00 nop +10000328: 10003630 .word 0x10003630 +1000032c: 10003620 .word 0x10003620 + +10000330 : +10000330: b570 push {r4, r5, r6, lr} +10000332: 4686 mov lr, r0 +10000334: f3ef 8510 mrs r5, PRIMASK +10000338: b672 cpsid i +1000033a: 4c12 ldr r4, [pc, #72] @ (10000384 ) +1000033c: e8d4 6fcf ldaexb r6, [r4] +10000340: 2001 movs r0, #1 +10000342: 2e00 cmp r6, #0 +10000344: d1fa bne.n 1000033c +10000346: e8c4 0f46 strexb r6, r0, [r4] +1000034a: 2e00 cmp r6, #0 +1000034c: d1f6 bne.n 1000033c +1000034e: f3bf 8f5f dmb sy +10000352: f04f 0c01 mov.w ip, #1 +10000356: 08c8 lsrs r0, r1, #3 +10000358: f001 0307 and.w r3, r1, #7 +1000035c: fa0c f303 lsl.w r3, ip, r3 +10000360: f81e c000 ldrb.w ip, [lr, r0] +10000364: ea1c 0603 ands.w r6, ip, r3 +10000368: d108 bne.n 1000037c +1000036a: ea4c 0c03 orr.w ip, ip, r3 +1000036e: f80e c000 strb.w ip, [lr, r0] +10000372: e8c4 6f8f stlb r6, [r4] +10000376: f385 8810 msr PRIMASK, r5 +1000037a: bd70 pop {r4, r5, r6, pc} +1000037c: 4610 mov r0, r2 +1000037e: f7ff ffbf bl 10000300 +10000382: bf00 nop +10000384: 200007bb .word 0x200007bb + +10000388 : +10000388: 4a04 ldr r2, [pc, #16] @ (1000039c ) +1000038a: 7810 ldrb r0, [r2, #0] +1000038c: 1c43 adds r3, r0, #1 +1000038e: b2db uxtb r3, r3 +10000390: 2b18 cmp r3, #24 +10000392: bf28 it cs +10000394: 2310 movcs r3, #16 +10000396: 7013 strb r3, [r2, #0] +10000398: 4770 bx lr +1000039a: bf00 nop +1000039c: 200005a8 .word 0x200005a8 + +100003a0 : +100003a0: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100003a4: 6893 ldr r3, [r2, #8] +100003a6: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100003aa: 6093 str r3, [r2, #8] +100003ac: 4770 bx lr +100003ae: bf00 nop + +100003b0 : +100003b0: 2100 movs r1, #0 +100003b2: 4b04 ldr r3, [pc, #16] @ (100003c4 ) +100003b4: f103 0220 add.w r2, r3, #32 +100003b8: e8c3 1f8f stlb r1, [r3] +100003bc: 3301 adds r3, #1 +100003be: 4293 cmp r3, r2 +100003c0: d1fa bne.n 100003b8 +100003c2: 4770 bx lr +100003c4: 200007b0 .word 0x200007b0 + +100003c8 : +100003c8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100003cc: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100003d0: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100003d4: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100003d8: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100003dc: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100003e0: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100003e4: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100003e8: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +100003ec: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100003f0: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100003f4: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100003f8: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100003fc: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000400: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000404: b662 cpsie i +10000406: 4770 bx lr + +10000408 : +10000408: 2301 movs r3, #1 +1000040a: f000 021f and.w r2, r0, #31 +1000040e: 4093 lsls r3, r2 +10000410: 0940 lsrs r0, r0, #5 +10000412: b141 cbz r1, 10000426 +10000414: 0080 lsls r0, r0, #2 +10000416: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000041a: f500 4061 add.w r0, r0, #57600 @ 0xe100 +1000041e: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000422: 6003 str r3, [r0, #0] +10000424: 4770 bx lr +10000426: 4a02 ldr r2, [pc, #8] @ (10000430 ) +10000428: 3020 adds r0, #32 +1000042a: f842 3020 str.w r3, [r2, r0, lsl #2] +1000042e: 4770 bx lr +10000430: e000e100 .word 0xe000e100 + +10000434 : +10000434: b5f8 push {r3, r4, r5, r6, r7, lr} +10000436: 460d mov r5, r1 +10000438: f3ef 8710 mrs r7, PRIMASK +1000043c: b672 cpsid i +1000043e: 4e12 ldr r6, [pc, #72] @ (10000488 ) +10000440: e8d6 2fcf ldaexb r2, [r6] +10000444: 2301 movs r3, #1 +10000446: 2a00 cmp r2, #0 +10000448: d1fa bne.n 10000440 +1000044a: e8c6 3f42 strexb r2, r3, [r6] +1000044e: 2a00 cmp r2, #0 +10000450: d1f6 bne.n 10000440 +10000452: f3bf 8f5f dmb sy +10000456: 4b0d ldr r3, [pc, #52] @ (1000048c ) +10000458: f100 0410 add.w r4, r0, #16 +1000045c: 689b ldr r3, [r3, #8] +1000045e: 4a0c ldr r2, [pc, #48] @ (10000490 ) +10000460: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000464: 4293 cmp r3, r2 +10000466: d003 beq.n 10000470 +10000468: 4299 cmp r1, r3 +1000046a: d001 beq.n 10000470 +1000046c: f000 ff0c bl 10001288 +10000470: 4b06 ldr r3, [pc, #24] @ (1000048c ) +10000472: 689b ldr r3, [r3, #8] +10000474: f843 5024 str.w r5, [r3, r4, lsl #2] +10000478: f3bf 8f5f dmb sy +1000047c: 2300 movs r3, #0 +1000047e: e8c6 3f8f stlb r3, [r6] +10000482: f387 8810 msr PRIMASK, r7 +10000486: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000488: 200007b9 .word 0x200007b9 +1000048c: e000ed00 .word 0xe000ed00 +10000490: 10000111 .word 0x10000111 + +10000494 : +10000494: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000498: b083 sub sp, #12 +1000049a: f3ef 8a10 mrs sl, PRIMASK +1000049e: b672 cpsid i +100004a0: 4e71 ldr r6, [pc, #452] @ (10000668 ) +100004a2: e8d6 2fcf ldaexb r2, [r6] +100004a6: 2301 movs r3, #1 +100004a8: 2a00 cmp r2, #0 +100004aa: d1fa bne.n 100004a2 +100004ac: e8c6 3f42 strexb r2, r3, [r6] +100004b0: 2a00 cmp r2, #0 +100004b2: d1f6 bne.n 100004a2 +100004b4: f3bf 8f5f dmb sy +100004b8: 4b6c ldr r3, [pc, #432] @ (1000066c ) +100004ba: f100 0810 add.w r8, r0, #16 +100004be: 689b ldr r3, [r3, #8] +100004c0: 4a6b ldr r2, [pc, #428] @ (10000670 ) +100004c2: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100004c6: 4295 cmp r5, r2 +100004c8: d045 beq.n 10000556 +100004ca: 428d cmp r5, r1 +100004cc: 460c mov r4, r1 +100004ce: d050 beq.n 10000572 +100004d0: 4f68 ldr r7, [pc, #416] @ (10000674 ) +100004d2: 1beb subs r3, r5, r7 +100004d4: 2b2f cmp r3, #47 @ 0x2f +100004d6: d83e bhi.n 10000556 +100004d8: 2101 movs r1, #1 +100004da: ea4f 1950 mov.w r9, r0, lsr #5 +100004de: ea4f 0989 mov.w r9, r9, lsl #2 +100004e2: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100004e6: f509 4961 add.w r9, r9, #57600 @ 0xe100 +100004ea: f000 031f and.w r3, r0, #31 +100004ee: fa01 f003 lsl.w r0, r1, r3 +100004f2: f8d9 3000 ldr.w r3, [r9] +100004f6: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100004fa: ea00 0b03 and.w fp, r0, r3 +100004fe: f3bf 8f5f dmb sy +10000502: f3ef 8105 mrs r1, IPSR +10000506: b2c9 uxtb r1, r1 +10000508: 2900 cmp r1, #0 +1000050a: d034 beq.n 10000576 +1000050c: 4588 cmp r8, r1 +1000050e: d005 beq.n 1000051c +10000510: e9cd 1000 strd r1, r0, [sp] +10000514: f000 feb8 bl 10001288 +10000518: e9dd 1000 ldrd r1, r0, [sp] +1000051c: f025 0e01 bic.w lr, r5, #1 +10000520: f8de c008 ldr.w ip, [lr, #8] +10000524: 4564 cmp r4, ip +10000526: d105 bne.n 10000534 +10000528: e089 b.n 1000063e +1000052a: f8d3 c008 ldr.w ip, [r3, #8] +1000052e: 4564 cmp r4, ip +10000530: d031 beq.n 10000596 +10000532: 469e mov lr, r3 +10000534: f99e 2006 ldrsb.w r2, [lr, #6] +10000538: eb02 0342 add.w r3, r2, r2, lsl #1 +1000053c: 2a00 cmp r2, #0 +1000053e: eb07 0383 add.w r3, r7, r3, lsl #2 +10000542: daf2 bge.n 1000052a +10000544: 4564 cmp r4, ip +10000546: d061 beq.n 1000060c +10000548: f1bb 0f00 cmp.w fp, #0 +1000054c: d020 beq.n 10000590 +1000054e: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +10000552: f8c9 0000 str.w r0, [r9] +10000556: 4b45 ldr r3, [pc, #276] @ (1000066c ) +10000558: 689b ldr r3, [r3, #8] +1000055a: f843 5028 str.w r5, [r3, r8, lsl #2] +1000055e: f3bf 8f5f dmb sy +10000562: 2300 movs r3, #0 +10000564: e8c6 3f8f stlb r3, [r6] +10000568: f38a 8810 msr PRIMASK, sl +1000056c: b003 add sp, #12 +1000056e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000572: 4615 mov r5, r2 +10000574: e7ef b.n 10000556 +10000576: f025 0e01 bic.w lr, r5, #1 +1000057a: f8de c008 ldr.w ip, [lr, #8] +1000057e: 4564 cmp r4, ip +10000580: d1d8 bne.n 10000534 +10000582: f99e 4006 ldrsb.w r4, [lr, #6] +10000586: 4673 mov r3, lr +10000588: 2c00 cmp r4, #0 +1000058a: da08 bge.n 1000059e +1000058c: 4615 mov r5, r2 +1000058e: e046 b.n 1000061e +10000590: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000594: e7df b.n 10000556 +10000596: f993 4006 ldrsb.w r4, [r3, #6] +1000059a: 2c00 cmp r4, #0 +1000059c: db37 blt.n 1000060e +1000059e: eb04 0c44 add.w ip, r4, r4, lsl #1 +100005a2: eb07 0c8c add.w ip, r7, ip, lsl #2 +100005a6: f89c 1007 ldrb.w r1, [ip, #7] +100005aa: f8dc 2008 ldr.w r2, [ip, #8] +100005ae: 71d9 strb r1, [r3, #7] +100005b0: 609a str r2, [r3, #8] +100005b2: f99c 2006 ldrsb.w r2, [ip, #6] +100005b6: 0061 lsls r1, r4, #1 +100005b8: 2a00 cmp r2, #0 +100005ba: 719a strb r2, [r3, #6] +100005bc: db3d blt.n 1000063a +100005be: f8bc e004 ldrh.w lr, [ip, #4] +100005c2: ea5f 5e4e movs.w lr, lr, lsl #21 +100005c6: d505 bpl.n 100005d4 +100005c8: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100005cc: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100005d0: f10e 0e1f add.w lr, lr, #31 +100005d4: f06f 0c07 mvn.w ip, #7 +100005d8: 190a adds r2, r1, r4 +100005da: ea4f 5e6e mov.w lr, lr, asr #21 +100005de: 0092 lsls r2, r2, #2 +100005e0: eb02 024e add.w r2, r2, lr, lsl #1 +100005e4: 3208 adds r2, #8 +100005e6: 443a add r2, r7 +100005e8: ebac 0c03 sub.w ip, ip, r3 +100005ec: 4462 add r2, ip +100005ee: f3c2 024a ubfx r2, r2, #1, #11 +100005f2: ea6f 42c2 mvn.w r2, r2, lsl #19 +100005f6: ea6f 42d2 mvn.w r2, r2, lsr #19 +100005fa: 809a strh r2, [r3, #4] +100005fc: 4b1e ldr r3, [pc, #120] @ (10000678 ) +100005fe: 4421 add r1, r4 +10000600: 781a ldrb r2, [r3, #0] +10000602: eb07 0181 add.w r1, r7, r1, lsl #2 +10000606: 701c strb r4, [r3, #0] +10000608: 718a strb r2, [r1, #6] +1000060a: e79d b.n 10000548 +1000060c: 4673 mov r3, lr +1000060e: b9d9 cbnz r1, 10000648 +10000610: 22ff movs r2, #255 @ 0xff +10000612: f88e 2006 strb.w r2, [lr, #6] +10000616: f64b 5201 movw r2, #48385 @ 0xbd01 +1000061a: f8ae 2004 strh.w r2, [lr, #4] +1000061e: 4c16 ldr r4, [pc, #88] @ (10000678 ) +10000620: f64a 22aa movw r2, #43690 @ 0xaaaa +10000624: f894 c000 ldrb.w ip, [r4] +10000628: 4619 mov r1, r3 +1000062a: 1bc9 subs r1, r1, r7 +1000062c: 4149 adcs r1, r1 +1000062e: 434a muls r2, r1 +10000630: 0d12 lsrs r2, r2, #20 +10000632: f883 c006 strb.w ip, [r3, #6] +10000636: 7022 strb r2, [r4, #0] +10000638: e786 b.n 10000548 +1000063a: 4a10 ldr r2, [pc, #64] @ (1000067c ) +1000063c: e7dd b.n 100005fa +1000063e: f99e 4006 ldrsb.w r4, [lr, #6] +10000642: 4673 mov r3, lr +10000644: 2c00 cmp r4, #0 +10000646: daaa bge.n 1000059e +10000648: 4a0d ldr r2, [pc, #52] @ (10000680 ) +1000064a: 4c0e ldr r4, [pc, #56] @ (10000684 ) +1000064c: 1ad2 subs r2, r2, r3 +1000064e: 3a08 subs r2, #8 +10000650: f3c2 310a ubfx r1, r2, #12, #11 +10000654: ea6f 5101 mvn.w r1, r1, lsl #20 +10000658: ea6f 5111 mvn.w r1, r1, lsr #20 +1000065c: ea44 0252 orr.w r2, r4, r2, lsr #1 +10000660: 80da strh r2, [r3, #6] +10000662: 8099 strh r1, [r3, #4] +10000664: e770 b.n 10000548 +10000666: bf00 nop +10000668: 200007b9 .word 0x200007b9 +1000066c: e000ed00 .word 0xe000ed00 +10000670: 10000111 .word 0x10000111 +10000674: 200005ac .word 0x200005ac +10000678: 20000854 .word 0x20000854 +1000067c: ffffbd01 .word 0xffffbd01 +10000680: 200005e6 .word 0x200005e6 +10000684: fffff800 .word 0xfffff800 + +10000688 : +10000688: b5f0 push {r4, r5, r6, r7, lr} +1000068a: f3ef 8505 mrs r5, IPSR +1000068e: b2ed uxtb r5, r5 +10000690: f3ef 8c10 mrs ip, PRIMASK +10000694: b672 cpsid i +10000696: 4926 ldr r1, [pc, #152] @ (10000730 ) +10000698: e8d1 2fcf ldaexb r2, [r1] +1000069c: 2301 movs r3, #1 +1000069e: 2a00 cmp r2, #0 +100006a0: d1fa bne.n 10000698 +100006a2: e8c1 3f42 strexb r2, r3, [r1] +100006a6: 2a00 cmp r2, #0 +100006a8: d1f6 bne.n 10000698 +100006aa: f3bf 8f5f dmb sy +100006ae: 4e21 ldr r6, [pc, #132] @ (10000734 ) +100006b0: f040 0e01 orr.w lr, r0, #1 +100006b4: 68b4 ldr r4, [r6, #8] +100006b6: f64a 23aa movw r3, #43690 @ 0xaaaa +100006ba: f854 7025 ldr.w r7, [r4, r5, lsl #2] +100006be: 4a1e ldr r2, [pc, #120] @ (10000738 ) +100006c0: 4604 mov r4, r0 +100006c2: 1aa4 subs r4, r4, r2 +100006c4: 4164 adcs r4, r4 +100006c6: 4363 muls r3, r4 +100006c8: 0d1b lsrs r3, r3, #20 +100006ca: 4577 cmp r7, lr +100006cc: b25b sxtb r3, r3 +100006ce: d01b beq.n 10000708 +100006d0: f992 4006 ldrsb.w r4, [r2, #6] +100006d4: 429c cmp r4, r3 +100006d6: d01c beq.n 10000712 +100006d8: f992 4012 ldrsb.w r4, [r2, #18] +100006dc: 429c cmp r4, r3 +100006de: d023 beq.n 10000728 +100006e0: f992 401e ldrsb.w r4, [r2, #30] +100006e4: 429c cmp r4, r3 +100006e6: d021 beq.n 1000072c +100006e8: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100006ec: 429c cmp r4, r3 +100006ee: bf08 it eq +100006f0: 2403 moveq r4, #3 +100006f2: d00f beq.n 10000714 +100006f4: 4a11 ldr r2, [pc, #68] @ (1000073c ) +100006f6: 2400 movs r4, #0 +100006f8: 7815 ldrb r5, [r2, #0] +100006fa: 7013 strb r3, [r2, #0] +100006fc: 7185 strb r5, [r0, #6] +100006fe: e8c1 4f8f stlb r4, [r1] +10000702: f38c 8810 msr PRIMASK, ip +10000706: bdf0 pop {r4, r5, r6, r7, pc} +10000708: 68b2 ldr r2, [r6, #8] +1000070a: 4c0d ldr r4, [pc, #52] @ (10000740 ) +1000070c: f842 4025 str.w r4, [r2, r5, lsl #2] +10000710: e7f0 b.n 100006f4 +10000712: 2400 movs r4, #0 +10000714: eb04 0444 add.w r4, r4, r4, lsl #1 +10000718: eb02 0284 add.w r2, r2, r4, lsl #2 +1000071c: 24ff movs r4, #255 @ 0xff +1000071e: 7194 strb r4, [r2, #6] +10000720: f64b 5401 movw r4, #48385 @ 0xbd01 +10000724: 8094 strh r4, [r2, #4] +10000726: e7e5 b.n 100006f4 +10000728: 2401 movs r4, #1 +1000072a: e7f3 b.n 10000714 +1000072c: 2402 movs r4, #2 +1000072e: e7f1 b.n 10000714 +10000730: 200007b9 .word 0x200007b9 +10000734: e000ed00 .word 0xe000ed00 +10000738: 200005ac .word 0x200005ac +1000073c: 20000854 .word 0x20000854 +10000740: 10000111 .word 0x10000111 + +10000744 : +10000744: 4b01 ldr r3, [pc, #4] @ (1000074c ) +10000746: 440b add r3, r1 +10000748: 6003 str r3, [r0, #0] +1000074a: 4770 bx lr +1000074c: 200007b0 .word 0x200007b0 + +10000750 : +10000750: b570 push {r4, r5, r6, lr} +10000752: 4c10 ldr r4, [pc, #64] @ (10000794 ) +10000754: 4d10 ldr r5, [pc, #64] @ (10000798 ) +10000756: 42ac cmp r4, r5 +10000758: d20e bcs.n 10000778 +1000075a: 26ff movs r6, #255 @ 0xff +1000075c: 6823 ldr r3, [r4, #0] +1000075e: b163 cbz r3, 1000077a +10000760: f7ff fe12 bl 10000388 +10000764: 4601 mov r1, r0 +10000766: 4620 mov r0, r4 +10000768: f7ff ffec bl 10000744 +1000076c: 80a6 strh r6, [r4, #4] +1000076e: f3bf 8f5f dmb sy +10000772: 3408 adds r4, #8 +10000774: 42ac cmp r4, r5 +10000776: d3f1 bcc.n 1000075c +10000778: bd70 pop {r4, r5, r6, pc} +1000077a: f7ff fe05 bl 10000388 +1000077e: 4601 mov r1, r0 +10000780: 4620 mov r0, r4 +10000782: f7ff ffdf bl 10000744 +10000786: 7126 strb r6, [r4, #4] +10000788: f3bf 8f5f dmb sy +1000078c: 3408 adds r4, #8 +1000078e: 42ac cmp r4, r5 +10000790: d3e4 bcc.n 1000075c +10000792: bd70 pop {r4, r5, r6, pc} +10000794: 20000624 .word 0x20000624 +10000798: 2000062c .word 0x2000062c + +1000079c : +1000079c: 4b0d ldr r3, [pc, #52] @ (100007d4 ) +1000079e: 681a ldr r2, [r3, #0] +100007a0: f3ef 8110 mrs r1, PRIMASK +100007a4: b672 cpsid i +100007a6: e8d2 cfcf ldaexb ip, [r2] +100007aa: 2001 movs r0, #1 +100007ac: f1bc 0f00 cmp.w ip, #0 +100007b0: d1f9 bne.n 100007a6 +100007b2: e8c2 0f4c strexb ip, r0, [r2] +100007b6: f1bc 0f00 cmp.w ip, #0 +100007ba: d1f4 bne.n 100007a6 +100007bc: f3bf 8f5f dmb sy +100007c0: 2200 movs r2, #0 +100007c2: 681b ldr r3, [r3, #0] +100007c4: e8c3 2f8f stlb r2, [r3] +100007c8: f381 8810 msr PRIMASK, r1 +100007cc: bf40 sev +100007ce: 2000 movs r0, #0 +100007d0: 2100 movs r1, #0 +100007d2: 4770 bx lr +100007d4: 20000848 .word 0x20000848 + +100007d8 : +100007d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007dc: ed2d 8b02 vpush {d8} +100007e0: b085 sub sp, #20 +100007e2: f3ef 8305 mrs r3, IPSR +100007e6: b2db uxtb r3, r3 +100007e8: 3b10 subs r3, #16 +100007ea: 089a lsrs r2, r3, #2 +100007ec: bf18 it ne +100007ee: 2201 movne r2, #1 +100007f0: f04f 0101 mov.w r1, #1 +100007f4: f003 0b03 and.w fp, r3, #3 +100007f8: bf18 it ne +100007fa: 4daf ldrne r5, [pc, #700] @ (10000ab8 ) +100007fc: 4baf ldr r3, [pc, #700] @ (10000abc ) +100007fe: bf08 it eq +10000800: 4daf ldreq r5, [pc, #700] @ (10000ac0 ) +10000802: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000806: f853 6022 ldr.w r6, [r3, r2, lsl #2] +1000080a: fa01 f20b lsl.w r2, r1, fp +1000080e: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000812: ed9f 8ba7 vldr d8, [pc, #668] @ 10000ab0 +10000816: 9201 str r2, [sp, #4] +10000818: 605a str r2, [r3, #4] +1000081a: e02f b.n 1000087c +1000081c: 88b3 ldrh r3, [r6, #4] +1000081e: 041c lsls r4, r3, #16 +10000820: f140 8093 bpl.w 1000094a +10000824: 79b3 ldrb r3, [r6, #6] +10000826: 2b00 cmp r3, #0 +10000828: f040 80dd bne.w 100009e6 +1000082c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000830: 2a00 cmp r2, #0 +10000832: f2c0 811e blt.w 10000a72 +10000836: 6973 ldr r3, [r6, #20] +10000838: eb02 0242 add.w r2, r2, r2, lsl #1 +1000083c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000840: e9d3 4702 ldrd r4, r7, [r3, #8] +10000844: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000848: bf08 it eq +1000084a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +1000084e: d00e beq.n 1000086e +10000850: eb05 018b add.w r1, r5, fp, lsl #2 +10000854: 6aab ldr r3, [r5, #40] @ 0x28 +10000856: 690a ldr r2, [r1, #16] +10000858: 1ad2 subs r2, r2, r3 +1000085a: 1ae3 subs r3, r4, r3 +1000085c: 4293 cmp r3, r2 +1000085e: d305 bcc.n 1000086c +10000860: 2301 movs r3, #1 +10000862: 6a2a ldr r2, [r5, #32] +10000864: fa03 f30b lsl.w r3, r3, fp +10000868: 4213 tst r3, r2 +1000086a: d100 bne.n 1000086e +1000086c: 610c str r4, [r1, #16] +1000086e: 4628 mov r0, r5 +10000870: f000 fb38 bl 10000ee4 +10000874: 42a0 cmp r0, r4 +10000876: 41b9 sbcs r1, r7 +10000878: f2c0 80fb blt.w 10000a72 +1000087c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000880: 9a01 ldr r2, [sp, #4] +10000882: 2b00 cmp r3, #0 +10000884: 9300 str r3, [sp, #0] +10000886: 63ea str r2, [r5, #60] @ 0x3c +10000888: dbc8 blt.n 1000081c +1000088a: f8d6 8014 ldr.w r8, [r6, #20] +1000088e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000892: 4628 mov r0, r5 +10000894: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000898: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000089c: f000 fb22 bl 10000ee4 +100008a0: 42a0 cmp r0, r4 +100008a2: eb71 010a sbcs.w r1, r1, sl +100008a6: dbb9 blt.n 1000081c +100008a8: f1ba 0f00 cmp.w sl, #0 +100008ac: f2c0 80c3 blt.w 10000a36 +100008b0: e9d7 3104 ldrd r3, r1, [r7, #16] +100008b4: 4a83 ldr r2, [pc, #524] @ (10000ac4 ) +100008b6: 4293 cmp r3, r2 +100008b8: f000 80ed beq.w 10000a96 +100008bc: 887a ldrh r2, [r7, #2] +100008be: f9b6 0008 ldrsh.w r0, [r6, #8] +100008c2: b292 uxth r2, r2 +100008c4: ea42 4000 orr.w r0, r2, r0, lsl #16 +100008c8: 4798 blx r3 +100008ca: 4602 mov r2, r0 +100008cc: 460b mov r3, r1 +100008ce: ea52 0103 orrs.w r1, r2, r3 +100008d2: f000 80b0 beq.w 10000a36 +100008d6: 2b00 cmp r3, #0 +100008d8: f280 80d1 bge.w 10000a7e +100008dc: ebb4 0e02 subs.w lr, r4, r2 +100008e0: eb6a 0a03 sbc.w sl, sl, r3 +100008e4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +100008e8: e9c7 ea02 strd lr, sl, [r7, #8] +100008ec: 2b00 cmp r3, #0 +100008ee: db95 blt.n 1000081c +100008f0: 6971 ldr r1, [r6, #20] +100008f2: eb03 0243 add.w r2, r3, r3, lsl #1 +100008f6: eb01 02c2 add.w r2, r1, r2, lsl #3 +100008fa: e9d2 7002 ldrd r7, r0, [r2, #8] +100008fe: 45be cmp lr, r7 +10000900: eb7a 0c00 sbcs.w ip, sl, r0 +10000904: ea4f 0243 mov.w r2, r3, lsl #1 +10000908: db88 blt.n 1000081c +1000090a: 46b4 mov ip, r6 +1000090c: f82c 3f08 strh.w r3, [ip, #8]! +10000910: e006 b.n 10000920 +10000912: eb03 0043 add.w r0, r3, r3, lsl #1 +10000916: eb01 00c0 add.w r0, r1, r0, lsl #3 +1000091a: 005a lsls r2, r3, #1 +1000091c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000920: 45be cmp lr, r7 +10000922: 441a add r2, r3 +10000924: eb7a 0000 sbcs.w r0, sl, r0 +10000928: eb01 04c2 add.w r4, r1, r2, lsl #3 +1000092c: db04 blt.n 10000938 +1000092e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000932: 46a4 mov ip, r4 +10000934: 2b00 cmp r3, #0 +10000936: daec bge.n 10000912 +10000938: f828 3039 strh.w r3, [r8, r9, lsl #3] +1000093c: 9b00 ldr r3, [sp, #0] +1000093e: f8ac 3000 strh.w r3, [ip] +10000942: 88b3 ldrh r3, [r6, #4] +10000944: 041c lsls r4, r3, #16 +10000946: f53f af6d bmi.w 10000824 +1000094a: 6933 ldr r3, [r6, #16] +1000094c: f3ef 8210 mrs r2, PRIMASK +10000950: b672 cpsid i +10000952: e8d3 0fcf ldaexb r0, [r3] +10000956: 2101 movs r1, #1 +10000958: 2800 cmp r0, #0 +1000095a: d1fa bne.n 10000952 +1000095c: e8c3 1f40 strexb r0, r1, [r3] +10000960: 2800 cmp r0, #0 +10000962: d1f6 bne.n 10000952 +10000964: f3bf 8f5f dmb sy +10000968: f64f 74ff movw r4, #65535 @ 0xffff +1000096c: 88b0 ldrh r0, [r6, #4] +1000096e: 2300 movs r3, #0 +10000970: 6931 ldr r1, [r6, #16] +10000972: b200 sxth r0, r0 +10000974: 80b4 strh r4, [r6, #4] +10000976: e8c1 3f8f stlb r3, [r1] +1000097a: f382 8810 msr PRIMASK, r2 +1000097e: 4298 cmp r0, r3 +10000980: f6ff af50 blt.w 10000824 +10000984: 4607 mov r7, r0 +10000986: 46a9 mov r9, r5 +10000988: 6974 ldr r4, [r6, #20] +1000098a: f106 0808 add.w r8, r6, #8 +1000098e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000992: eb04 03ce add.w r3, r4, lr, lsl #3 +10000996: e9d3 5002 ldrd r5, r0, [r3, #8] +1000099a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000099e: 46c4 mov ip, r8 +100009a0: 2b00 cmp r3, #0 +100009a2: db13 blt.n 100009cc +100009a4: 46b2 mov sl, r6 +100009a6: 9700 str r7, [sp, #0] +100009a8: e004 b.n 100009b4 +100009aa: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +100009ae: 4694 mov ip, r2 +100009b0: 2b00 cmp r3, #0 +100009b2: db09 blt.n 100009c8 +100009b4: eb03 0643 add.w r6, r3, r3, lsl #1 +100009b8: eb04 02c6 add.w r2, r4, r6, lsl #3 +100009bc: e9d2 7102 ldrd r7, r1, [r2, #8] +100009c0: 42bd cmp r5, r7 +100009c2: eb70 0101 sbcs.w r1, r0, r1 +100009c6: daf0 bge.n 100009aa +100009c8: 4656 mov r6, sl +100009ca: 9f00 ldr r7, [sp, #0] +100009cc: f8ac 7000 strh.w r7, [ip] +100009d0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +100009d4: f824 303e strh.w r3, [r4, lr, lsl #3] +100009d8: 2f00 cmp r7, #0 +100009da: dad8 bge.n 1000098e +100009dc: 79b3 ldrb r3, [r6, #6] +100009de: 464d mov r5, r9 +100009e0: 2b00 cmp r3, #0 +100009e2: f43f af23 beq.w 1000082c +100009e6: 2300 movs r3, #0 +100009e8: 71b3 strb r3, [r6, #6] +100009ea: f9b6 3008 ldrsh.w r3, [r6, #8] +100009ee: f106 0808 add.w r8, r6, #8 +100009f2: 1c58 adds r0, r3, #1 +100009f4: d03d beq.n 10000a72 +100009f6: 461a mov r2, r3 +100009f8: 6977 ldr r7, [r6, #20] +100009fa: e003 b.n 10000a04 +100009fc: 4680 mov r8, r0 +100009fe: 1c59 adds r1, r3, #1 +10000a00: f43f af16 beq.w 10000830 +10000a04: eb03 0143 add.w r1, r3, r3, lsl #1 +10000a08: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000a0c: f8b0 c002 ldrh.w ip, [r0, #2] +10000a10: 461c mov r4, r3 +10000a12: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000a16: 469e mov lr, r3 +10000a18: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000a1c: d0ee beq.n 100009fc +10000a1e: 4294 cmp r4, r2 +10000a20: ed80 8b02 vstr d8, [r0, #8] +10000a24: d005 beq.n 10000a32 +10000a26: f8a8 3000 strh.w r3, [r8] +10000a2a: 8932 ldrh r2, [r6, #8] +10000a2c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000a30: 8134 strh r4, [r6, #8] +10000a32: 4672 mov r2, lr +10000a34: e7e3 b.n 100009fe +10000a36: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000a3a: 8133 strh r3, [r6, #8] +10000a3c: 6933 ldr r3, [r6, #16] +10000a3e: f3ef 8210 mrs r2, PRIMASK +10000a42: b672 cpsid i +10000a44: e8d3 0fcf ldaexb r0, [r3] +10000a48: 2101 movs r1, #1 +10000a4a: 2800 cmp r0, #0 +10000a4c: d1fa bne.n 10000a44 +10000a4e: e8c3 1f40 strexb r0, r1, [r3] +10000a52: 2800 cmp r0, #0 +10000a54: d1f6 bne.n 10000a44 +10000a56: f3bf 8f5f dmb sy +10000a5a: 8873 ldrh r3, [r6, #2] +10000a5c: 6931 ldr r1, [r6, #16] +10000a5e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000a62: 9b00 ldr r3, [sp, #0] +10000a64: 8073 strh r3, [r6, #2] +10000a66: 2300 movs r3, #0 +10000a68: e8c1 3f8f stlb r3, [r1] +10000a6c: f382 8810 msr PRIMASK, r2 +10000a70: e6d4 b.n 1000081c +10000a72: bf40 sev +10000a74: b005 add sp, #20 +10000a76: ecbd 8b02 vpop {d8} +10000a7a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a7e: 4628 mov r0, r5 +10000a80: e9cd 2302 strd r2, r3, [sp, #8] +10000a84: f000 fa2e bl 10000ee4 +10000a88: 9a02 ldr r2, [sp, #8] +10000a8a: 9b03 ldr r3, [sp, #12] +10000a8c: eb10 0e02 adds.w lr, r0, r2 +10000a90: eb43 0a01 adc.w sl, r3, r1 +10000a94: e726 b.n 100008e4 +10000a96: 4608 mov r0, r1 +10000a98: 690b ldr r3, [r1, #16] +10000a9a: 9102 str r1, [sp, #8] +10000a9c: 4798 blx r3 +10000a9e: 2800 cmp r0, #0 +10000aa0: d0c9 beq.n 10000a36 +10000aa2: 9902 ldr r1, [sp, #8] +10000aa4: e9d1 2300 ldrd r2, r3, [r1] +10000aa8: e711 b.n 100008ce +10000aaa: bf00 nop +10000aac: f3af 8000 nop.w +10000ab0: ffffffff .word 0xffffffff +10000ab4: ffffffff .word 0xffffffff +10000ab8: 400b8000 .word 0x400b8000 +10000abc: 20000828 .word 0x20000828 +10000ac0: 400b0000 .word 0x400b0000 +10000ac4: 100007d9 .word 0x100007d9 + +10000ac8 : +10000ac8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000acc: 4c36 ldr r4, [pc, #216] @ (10000ba8 ) +10000ace: 6925 ldr r5, [r4, #16] +10000ad0: b12d cbz r5, 10000ade +10000ad2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000ad6: 210a movs r1, #10 +10000ad8: 4834 ldr r0, [pc, #208] @ (10000bac ) +10000ada: f7ff be33 b.w 10000744 +10000ade: f8df 80e4 ldr.w r8, [pc, #228] @ 10000bc4 +10000ae2: 2103 movs r1, #3 +10000ae4: 4640 mov r0, r8 +10000ae6: f000 f9eb bl 10000ec0 +10000aea: 2603 movs r6, #3 +10000aec: f8c4 800c str.w r8, [r4, #12] +10000af0: f7ff fc4a bl 10000388 +10000af4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000af8: 4b2d ldr r3, [pc, #180] @ (10000bb0 ) +10000afa: 7026 strb r6, [r4, #0] +10000afc: 4403 add r3, r0 +10000afe: 6123 str r3, [r4, #16] +10000b00: f8dc 3000 ldr.w r3, [ip] +10000b04: 210f movs r1, #15 +10000b06: 7063 strb r3, [r4, #1] +10000b08: 6963 ldr r3, [r4, #20] +10000b0a: 8061 strh r1, [r4, #2] +10000b0c: 831d strh r5, [r3, #24] +10000b0e: f04f 0504 mov.w r5, #4 +10000b12: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000b16: f04f 0505 mov.w r5, #5 +10000b1a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000b1e: f04f 0506 mov.w r5, #6 +10000b22: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000b26: f04f 0507 mov.w r5, #7 +10000b2a: 210e movs r1, #14 +10000b2c: f64f 72ff movw r2, #65535 @ 0xffff +10000b30: 2708 movs r7, #8 +10000b32: f04f 0e0a mov.w lr, #10 +10000b36: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000b3a: f04f 0901 mov.w r9, #1 +10000b3e: f04f 0c0c mov.w ip, #12 +10000b42: f04f 0b02 mov.w fp, #2 +10000b46: f04f 0a09 mov.w sl, #9 +10000b4a: 200d movs r0, #13 +10000b4c: f04f 050b mov.w r5, #11 +10000b50: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000b54: 4917 ldr r1, [pc, #92] @ (10000bb4 ) +10000b56: 80a2 strh r2, [r4, #4] +10000b58: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000b5c: 60a1 str r1, [r4, #8] +10000b5e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000b62: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000b66: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000b6a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000b6e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000b72: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000b76: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b7a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b7e: 801a strh r2, [r3, #0] +10000b80: 4b0d ldr r3, [pc, #52] @ (10000bb8 ) +10000b82: 4630 mov r0, r6 +10000b84: f8c8 7020 str.w r7, [r8, #32] +10000b88: 490c ldr r1, [pc, #48] @ (10000bbc ) +10000b8a: 60dc str r4, [r3, #12] +10000b8c: f7ff fc52 bl 10000434 +10000b90: 4649 mov r1, r9 +10000b92: 4630 mov r0, r6 +10000b94: f7ff fc38 bl 10000408 +10000b98: 4b09 ldr r3, [pc, #36] @ (10000bc0 ) +10000b9a: 210a movs r1, #10 +10000b9c: 641f str r7, [r3, #64] @ 0x40 +10000b9e: 4803 ldr r0, [pc, #12] @ (10000bac ) +10000ba0: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000ba4: f7ff bdce b.w 10000744 +10000ba8: 200005f4 .word 0x200005f4 +10000bac: 20000848 .word 0x20000848 +10000bb0: 200007b0 .word 0x200007b0 +10000bb4: 0010ffff .word 0x0010ffff +10000bb8: 20000828 .word 0x20000828 +10000bbc: 100007d9 .word 0x100007d9 +10000bc0: 400b2000 .word 0x400b2000 +10000bc4: 400b0000 .word 0x400b0000 + +10000bc8 : +10000bc8: 4601 mov r1, r0 +10000bca: b5f0 push {r4, r5, r6, r7, lr} +10000bcc: 6900 ldr r0, [r0, #16] +10000bce: f3ef 8710 mrs r7, PRIMASK +10000bd2: b672 cpsid i +10000bd4: e8d0 5fcf ldaexb r5, [r0] +10000bd8: 2401 movs r4, #1 +10000bda: 2d00 cmp r5, #0 +10000bdc: d1fa bne.n 10000bd4 +10000bde: e8c0 4f45 strexb r5, r4, [r0] +10000be2: 2d00 cmp r5, #0 +10000be4: d1f6 bne.n 10000bd4 +10000be6: f3bf 8f5f dmb sy +10000bea: f9b1 e002 ldrsh.w lr, [r1, #2] +10000bee: 694c ldr r4, [r1, #20] +10000bf0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000bf4: f1be 0f00 cmp.w lr, #0 +10000bf8: ea4f 05cc mov.w r5, ip, lsl #3 +10000bfc: 6908 ldr r0, [r1, #16] +10000bfe: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000c02: db3c blt.n 10000c7e +10000c04: 5b66 ldrh r6, [r4, r5] +10000c06: 804e strh r6, [r1, #2] +10000c08: 2600 movs r6, #0 +10000c0a: e8c0 6f8f stlb r6, [r0] +10000c0e: f387 8810 msr PRIMASK, r7 +10000c12: f8bc 0002 ldrh.w r0, [ip, #2] +10000c16: e9cc 2302 strd r2, r3, [ip, #8] +10000c1a: 3001 adds r0, #1 +10000c1c: f3c0 000e ubfx r0, r0, #0, #15 +10000c20: 2801 cmp r0, #1 +10000c22: bf38 it cc +10000c24: 2001 movcc r0, #1 +10000c26: 9b05 ldr r3, [sp, #20] +10000c28: f8ac 0002 strh.w r0, [ip, #2] +10000c2c: f8cc 3010 str.w r3, [ip, #16] +10000c30: 9b06 ldr r3, [sp, #24] +10000c32: ea40 400e orr.w r0, r0, lr, lsl #16 +10000c36: f8cc 3014 str.w r3, [ip, #20] +10000c3a: 690b ldr r3, [r1, #16] +10000c3c: f3ef 8210 mrs r2, PRIMASK +10000c40: b672 cpsid i +10000c42: e8d3 cfcf ldaexb ip, [r3] +10000c46: 2701 movs r7, #1 +10000c48: f1bc 0f00 cmp.w ip, #0 +10000c4c: d1f9 bne.n 10000c42 +10000c4e: e8c3 7f4c strexb ip, r7, [r3] +10000c52: f1bc 0f00 cmp.w ip, #0 +10000c56: d1f4 bne.n 10000c42 +10000c58: f3bf 8f5f dmb sy +10000c5c: 888b ldrh r3, [r1, #4] +10000c5e: 5363 strh r3, [r4, r5] +10000c60: f8a1 e004 strh.w lr, [r1, #4] +10000c64: 690b ldr r3, [r1, #16] +10000c66: e8c3 6f8f stlb r6, [r3] +10000c6a: f382 8810 msr PRIMASK, r2 +10000c6e: 2201 movs r2, #1 +10000c70: 68cb ldr r3, [r1, #12] +10000c72: 7809 ldrb r1, [r1, #0] +10000c74: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c78: 408a lsls r2, r1 +10000c7a: 605a str r2, [r3, #4] +10000c7c: bdf0 pop {r4, r5, r6, r7, pc} +10000c7e: 2300 movs r3, #0 +10000c80: e8c0 3f8f stlb r3, [r0] +10000c84: f387 8810 msr PRIMASK, r7 +10000c88: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c8c: bdf0 pop {r4, r5, r6, r7, pc} +10000c8e: bf00 nop + +10000c90 : +10000c90: 4603 mov r3, r0 +10000c92: 8940 ldrh r0, [r0, #10] +10000c94: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c98: dd37 ble.n 10000d0a +10000c9a: 6958 ldr r0, [r3, #20] +10000c9c: 140a asrs r2, r1, #16 +10000c9e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000ca2: b510 push {r4, lr} +10000ca4: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000ca8: 691c ldr r4, [r3, #16] +10000caa: f3ef 8c10 mrs ip, PRIMASK +10000cae: b672 cpsid i +10000cb0: e8d4 efcf ldaexb lr, [r4] +10000cb4: 2201 movs r2, #1 +10000cb6: f1be 0f00 cmp.w lr, #0 +10000cba: d1f9 bne.n 10000cb0 +10000cbc: e8c4 2f4e strexb lr, r2, [r4] +10000cc0: f1be 0f00 cmp.w lr, #0 +10000cc4: d1f4 bne.n 10000cb0 +10000cc6: f3bf 8f5f dmb sy +10000cca: 8842 ldrh r2, [r0, #2] +10000ccc: b289 uxth r1, r1 +10000cce: b292 uxth r2, r2 +10000cd0: 428a cmp r2, r1 +10000cd2: d007 beq.n 10000ce4 +10000cd4: 2200 movs r2, #0 +10000cd6: 691b ldr r3, [r3, #16] +10000cd8: e8c3 2f8f stlb r2, [r3] +10000cdc: f38c 8810 msr PRIMASK, ip +10000ce0: 2000 movs r0, #0 +10000ce2: bd10 pop {r4, pc} +10000ce4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000ce8: 8042 strh r2, [r0, #2] +10000cea: 2101 movs r1, #1 +10000cec: 2200 movs r2, #0 +10000cee: 6918 ldr r0, [r3, #16] +10000cf0: 7199 strb r1, [r3, #6] +10000cf2: e8c0 2f8f stlb r2, [r0] +10000cf6: f38c 8810 msr PRIMASK, ip +10000cfa: 781c ldrb r4, [r3, #0] +10000cfc: 68da ldr r2, [r3, #12] +10000cfe: 4608 mov r0, r1 +10000d00: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000d04: 40a1 lsls r1, r4 +10000d06: 6059 str r1, [r3, #4] +10000d08: bd10 pop {r4, pc} +10000d0a: 2000 movs r0, #0 +10000d0c: 4770 bx lr +10000d0e: bf00 nop + +10000d10 : +10000d10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000d14: b082 sub sp, #8 +10000d16: 4606 mov r6, r0 +10000d18: f000 f8ec bl 10000ef4 +10000d1c: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000d20: 4604 mov r4, r0 +10000d22: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000d26: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000d2a: fbe6 4103 umlal r4, r1, r6, r3 +10000d2e: 42a0 cmp r0, r4 +10000d30: eb72 0301 sbcs.w r3, r2, r1 +10000d34: bf3a itte cc +10000d36: 4604 movcc r4, r0 +10000d38: 4615 movcc r5, r2 +10000d3a: 460d movcs r5, r1 +10000d3c: 1fa6 subs r6, r4, #6 +10000d3e: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000d42: 42b4 cmp r4, r6 +10000d44: eb75 0307 sbcs.w r3, r5, r7 +10000d48: bf3c itt cc +10000d4a: 2600 movcc r6, #0 +10000d4c: 4637 movcc r7, r6 +10000d4e: f000 f8d1 bl 10000ef4 +10000d52: 1a30 subs r0, r6, r0 +10000d54: eb67 0101 sbc.w r1, r7, r1 +10000d58: 2801 cmp r0, #1 +10000d5a: f171 0100 sbcs.w r1, r1, #0 +10000d5e: da06 bge.n 10000d6e +10000d60: 4620 mov r0, r4 +10000d62: 4629 mov r1, r5 +10000d64: b002 add sp, #8 +10000d66: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000d6a: f000 b8fb b.w 10000f64 +10000d6e: f000 f8c1 bl 10000ef4 +10000d72: 4286 cmp r6, r0 +10000d74: eb67 0101 sbc.w r1, r7, r1 +10000d78: 2900 cmp r1, #0 +10000d7a: db0a blt.n 10000d92 +10000d7c: 2100 movs r1, #0 +10000d7e: 4b17 ldr r3, [pc, #92] @ (10000ddc ) +10000d80: 4632 mov r2, r6 +10000d82: 9300 str r3, [sp, #0] +10000d84: 4816 ldr r0, [pc, #88] @ (10000de0 ) +10000d86: 463b mov r3, r7 +10000d88: 9101 str r1, [sp, #4] +10000d8a: f7ff ff1d bl 10000bc8 +10000d8e: 3001 adds r0, #1 +10000d90: d0e6 beq.n 10000d60 +10000d92: f04f 0c00 mov.w ip, #0 +10000d96: 4a13 ldr r2, [pc, #76] @ (10000de4 ) +10000d98: 4913 ldr r1, [pc, #76] @ (10000de8 ) +10000d9a: 6a53 ldr r3, [r2, #36] @ 0x24 +10000d9c: 429f cmp r7, r3 +10000d9e: d804 bhi.n 10000daa +10000da0: 6a90 ldr r0, [r2, #40] @ 0x28 +10000da2: 42b0 cmp r0, r6 +10000da4: d2dc bcs.n 10000d60 +10000da6: 429f cmp r7, r3 +10000da8: d1da bne.n 10000d60 +10000daa: 680b ldr r3, [r1, #0] +10000dac: f3ef 8010 mrs r0, PRIMASK +10000db0: b672 cpsid i +10000db2: e8d3 8fcf ldaexb r8, [r3] +10000db6: f05f 0e01 movs.w lr, #1 +10000dba: f1b8 0f00 cmp.w r8, #0 +10000dbe: d1f8 bne.n 10000db2 +10000dc0: e8c3 ef48 strexb r8, lr, [r3] +10000dc4: f1b8 0f00 cmp.w r8, #0 +10000dc8: d1f3 bne.n 10000db2 +10000dca: f3bf 8f5f dmb sy +10000dce: 680b ldr r3, [r1, #0] +10000dd0: e8c3 cf8f stlb ip, [r3] +10000dd4: f380 8810 msr PRIMASK, r0 +10000dd8: bf20 wfe +10000dda: e7de b.n 10000d9a +10000ddc: 1000079d .word 0x1000079d +10000de0: 200005f4 .word 0x200005f4 +10000de4: 400b0000 .word 0x400b0000 +10000de8: 20000848 .word 0x20000848 + +10000dec : +10000dec: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000df0: 4606 mov r6, r0 +10000df2: 460d mov r5, r1 +10000df4: b083 sub sp, #12 +10000df6: f3ef 8405 mrs r4, IPSR +10000dfa: b2e4 uxtb r4, r4 +10000dfc: b13c cbz r4, 10000e0e +10000dfe: 4b2d ldr r3, [pc, #180] @ (10000eb4 ) +10000e00: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e02: 42aa cmp r2, r5 +10000e04: d21c bcs.n 10000e40 +10000e06: 2000 movs r0, #0 +10000e08: b003 add sp, #12 +10000e0a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000e0e: 4f2a ldr r7, [pc, #168] @ (10000eb8 ) +10000e10: f8d7 900c ldr.w r9, [r7, #12] +10000e14: f897 8000 ldrb.w r8, [r7] +10000e18: 4648 mov r0, r9 +10000e1a: f000 f863 bl 10000ee4 +10000e1e: f108 0804 add.w r8, r8, #4 +10000e22: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000e26: 1a1b subs r3, r3, r0 +10000e28: 1a30 subs r0, r6, r0 +10000e2a: eb65 0101 sbc.w r1, r5, r1 +10000e2e: 4298 cmp r0, r3 +10000e30: f171 0100 sbcs.w r1, r1, #0 +10000e34: db10 blt.n 10000e58 +10000e36: bf20 wfe +10000e38: 4b1e ldr r3, [pc, #120] @ (10000eb4 ) +10000e3a: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e3c: 42aa cmp r2, r5 +10000e3e: d3e2 bcc.n 10000e06 +10000e40: bf14 ite ne +10000e42: 2401 movne r4, #1 +10000e44: 2400 moveq r4, #0 +10000e46: 6a9b ldr r3, [r3, #40] @ 0x28 +10000e48: 42b3 cmp r3, r6 +10000e4a: bf34 ite cc +10000e4c: 4620 movcc r0, r4 +10000e4e: f044 0001 orrcs.w r0, r4, #1 +10000e52: b003 add sp, #12 +10000e54: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000e58: f000 f84c bl 10000ef4 +10000e5c: 4286 cmp r6, r0 +10000e5e: eb65 0101 sbc.w r1, r5, r1 +10000e62: 2900 cmp r1, #0 +10000e64: db14 blt.n 10000e90 +10000e66: 4b15 ldr r3, [pc, #84] @ (10000ebc ) +10000e68: 4638 mov r0, r7 +10000e6a: e9cd 3400 strd r3, r4, [sp] +10000e6e: 4632 mov r2, r6 +10000e70: 462b mov r3, r5 +10000e72: f7ff fea9 bl 10000bc8 +10000e76: 1e01 subs r1, r0, #0 +10000e78: dd0a ble.n 10000e90 +10000e7a: 4b0e ldr r3, [pc, #56] @ (10000eb4 ) +10000e7c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000e7e: 42aa cmp r2, r5 +10000e80: d316 bcc.n 10000eb0 +10000e82: 6a9b ldr r3, [r3, #40] @ 0x28 +10000e84: 42b3 cmp r3, r6 +10000e86: d311 bcc.n 10000eac +10000e88: 480b ldr r0, [pc, #44] @ (10000eb8 ) +10000e8a: f7ff ff01 bl 10000c90 +10000e8e: e7b6 b.n 10000dfe +10000e90: 4b08 ldr r3, [pc, #32] @ (10000eb4 ) +10000e92: 6a5c ldr r4, [r3, #36] @ 0x24 +10000e94: 42ac cmp r4, r5 +10000e96: d3b6 bcc.n 10000e06 +10000e98: 1b64 subs r4, r4, r5 +10000e9a: bf18 it ne +10000e9c: 2401 movne r4, #1 +10000e9e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000ea0: 42b3 cmp r3, r6 +10000ea2: bf34 ite cc +10000ea4: 4620 movcc r0, r4 +10000ea6: f044 0001 orrcs.w r0, r4, #1 +10000eaa: e7ad b.n 10000e08 +10000eac: 42aa cmp r2, r5 +10000eae: d1eb bne.n 10000e88 +10000eb0: bf20 wfe +10000eb2: e7e9 b.n 10000e88 +10000eb4: 400b0000 .word 0x400b0000 +10000eb8: 200005f4 .word 0x200005f4 +10000ebc: 1000079d .word 0x1000079d + +10000ec0 : +10000ec0: b410 push {r4} +10000ec2: 4b05 ldr r3, [pc, #20] @ (10000ed8 ) +10000ec4: 4c05 ldr r4, [pc, #20] @ (10000edc ) +10000ec6: 4a06 ldr r2, [pc, #24] @ (10000ee0 ) +10000ec8: 42a0 cmp r0, r4 +10000eca: bf14 ite ne +10000ecc: 4618 movne r0, r3 +10000ece: 1c58 addeq r0, r3, #1 +10000ed0: f85d 4b04 ldr.w r4, [sp], #4 +10000ed4: f7ff ba2c b.w 10000330 +10000ed8: 200007d8 .word 0x200007d8 +10000edc: 400b8000 .word 0x400b8000 +10000ee0: 10003640 .word 0x10003640 + +10000ee4 : +10000ee4: 4603 mov r3, r0 +10000ee6: 6a41 ldr r1, [r0, #36] @ 0x24 +10000ee8: 460a mov r2, r1 +10000eea: 6a98 ldr r0, [r3, #40] @ 0x28 +10000eec: 6a59 ldr r1, [r3, #36] @ 0x24 +10000eee: 428a cmp r2, r1 +10000ef0: d1fa bne.n 10000ee8 +10000ef2: 4770 bx lr + +10000ef4 : +10000ef4: 4b03 ldr r3, [pc, #12] @ (10000f04 ) +10000ef6: 6a59 ldr r1, [r3, #36] @ 0x24 +10000ef8: 460a mov r2, r1 +10000efa: 6a98 ldr r0, [r3, #40] @ 0x28 +10000efc: 6a59 ldr r1, [r3, #36] @ 0x24 +10000efe: 4291 cmp r1, r2 +10000f00: d1fa bne.n 10000ef8 +10000f02: 4770 bx lr +10000f04: 400b0000 .word 0x400b0000 + +10000f08 : +10000f08: b430 push {r4, r5} +10000f0a: 4a15 ldr r2, [pc, #84] @ (10000f60 ) +10000f0c: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f0e: 469c mov ip, r3 +10000f10: 6a94 ldr r4, [r2, #40] @ 0x28 +10000f12: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f14: 4563 cmp r3, ip +10000f16: d1fa bne.n 10000f0e +10000f18: 1902 adds r2, r0, r4 +10000f1a: 4159 adcs r1, r3 +10000f1c: f04f 0500 mov.w r5, #0 +10000f20: bf28 it cs +10000f22: 2501 movcs r5, #1 +10000f24: 4b0e ldr r3, [pc, #56] @ (10000f60 ) +10000f26: 6a5b ldr r3, [r3, #36] @ 0x24 +10000f28: b1b5 cbz r5, 10000f58 +10000f2a: 1c5a adds r2, r3, #1 +10000f2c: bf08 it eq +10000f2e: 461a moveq r2, r3 +10000f30: d008 beq.n 10000f44 +10000f32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000f36: 460a mov r2, r1 +10000f38: 4809 ldr r0, [pc, #36] @ (10000f60 ) +10000f3a: 6a43 ldr r3, [r0, #36] @ 0x24 +10000f3c: 428b cmp r3, r1 +10000f3e: d3fc bcc.n 10000f3a +10000f40: 428b cmp r3, r1 +10000f42: d107 bne.n 10000f54 +10000f44: 4906 ldr r1, [pc, #24] @ (10000f60 ) +10000f46: e002 b.n 10000f4e +10000f48: 6a48 ldr r0, [r1, #36] @ 0x24 +10000f4a: 4298 cmp r0, r3 +10000f4c: d102 bne.n 10000f54 +10000f4e: 6a88 ldr r0, [r1, #40] @ 0x28 +10000f50: 4290 cmp r0, r2 +10000f52: d3f9 bcc.n 10000f48 +10000f54: bc30 pop {r4, r5} +10000f56: 4770 bx lr +10000f58: 4299 cmp r1, r3 +10000f5a: d8ed bhi.n 10000f38 +10000f5c: e7f0 b.n 10000f40 +10000f5e: bf00 nop +10000f60: 400b0000 .word 0x400b0000 + +10000f64 : +10000f64: 4a07 ldr r2, [pc, #28] @ (10000f84 ) +10000f66: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f68: 4299 cmp r1, r3 +10000f6a: d8fc bhi.n 10000f66 +10000f6c: 4299 cmp r1, r3 +10000f6e: d107 bne.n 10000f80 +10000f70: 4b04 ldr r3, [pc, #16] @ (10000f84 ) +10000f72: e002 b.n 10000f7a +10000f74: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f76: 4291 cmp r1, r2 +10000f78: d102 bne.n 10000f80 +10000f7a: 6a9a ldr r2, [r3, #40] @ 0x28 +10000f7c: 4290 cmp r0, r2 +10000f7e: d8f9 bhi.n 10000f74 +10000f80: 4770 bx lr +10000f82: bf00 nop +10000f84: 400b0000 .word 0x400b0000 + +10000f88 : +10000f88: b5f8 push {r3, r4, r5, r6, r7, lr} +10000f8a: 4605 mov r5, r0 +10000f8c: 2006 movs r0, #6 +10000f8e: 460e mov r6, r1 +10000f90: f000 f8e4 bl 1000115c +10000f94: 2800 cmp r0, #0 +10000f96: d042 beq.n 1000101e +10000f98: 4a35 ldr r2, [pc, #212] @ (10001070 ) +10000f9a: 4836 ldr r0, [pc, #216] @ (10001074 ) +10000f9c: 4295 cmp r5, r2 +10000f9e: bf14 ite ne +10000fa0: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000fa4: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000fa8: 4b33 ldr r3, [pc, #204] @ (10001078 ) +10000faa: 4934 ldr r1, [pc, #208] @ (1000107c ) +10000fac: 6002 str r2, [r0, #0] +10000fae: 601a str r2, [r3, #0] +10000fb0: 688c ldr r4, [r1, #8] +10000fb2: ea32 0404 bics.w r4, r2, r4 +10000fb6: d1fb bne.n 10000fb0 +10000fb8: 4b2d ldr r3, [pc, #180] @ (10001070 ) +10000fba: f44f 7180 mov.w r1, #256 @ 0x100 +10000fbe: 1aeb subs r3, r5, r3 +10000fc0: fab3 f383 clz r3, r3 +10000fc4: 4a2e ldr r2, [pc, #184] @ (10001080 ) +10000fc6: 095b lsrs r3, r3, #5 +10000fc8: 2006 movs r0, #6 +10000fca: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000fce: f000 f8c5 bl 1000115c +10000fd2: 00c3 lsls r3, r0, #3 +10000fd4: fbb3 f3f6 udiv r3, r3, r6 +10000fd8: 3301 adds r3, #1 +10000fda: 09da lsrs r2, r3, #7 +10000fdc: d120 bne.n 10001020 +10000fde: 2640 movs r6, #64 @ 0x40 +10000fe0: 2101 movs r1, #1 +10000fe2: 6269 str r1, [r5, #36] @ 0x24 +10000fe4: 62aa str r2, [r5, #40] @ 0x28 +10000fe6: 6b2f ldr r7, [r5, #48] @ 0x30 +10000fe8: 07fb lsls r3, r7, #31 +10000fea: d422 bmi.n 10001032 +10000fec: 462b mov r3, r5 +10000fee: 2200 movs r2, #0 +10000ff0: f853 1f2c ldr.w r1, [r3, #44]! +10000ff4: 2006 movs r0, #6 +10000ff6: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000ffa: 6022 str r2, [r4, #0] +10000ffc: 632f str r7, [r5, #48] @ 0x30 +10000ffe: f000 f8ad bl 1000115c +10001002: f240 3101 movw r1, #769 @ 0x301 +10001006: 2203 movs r2, #3 +10001008: 0080 lsls r0, r0, #2 +1000100a: fbb0 f0f6 udiv r0, r0, r6 +1000100e: 6aeb ldr r3, [r5, #44] @ 0x2c +10001010: f083 0370 eor.w r3, r3, #112 @ 0x70 +10001014: f003 037e and.w r3, r3, #126 @ 0x7e +10001018: 6023 str r3, [r4, #0] +1000101a: 6329 str r1, [r5, #48] @ 0x30 +1000101c: 64aa str r2, [r5, #72] @ 0x48 +1000101e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001020: f64f 71fe movw r1, #65534 @ 0xfffe +10001024: 428a cmp r2, r1 +10001026: d91b bls.n 10001060 +10001028: 4622 mov r2, r4 +1000102a: f64f 71ff movw r1, #65535 @ 0xffff +1000102e: 4e15 ldr r6, [pc, #84] @ (10001084 ) +10001030: e7d7 b.n 10000fe2 +10001032: f240 3201 movw r2, #769 @ 0x301 +10001036: f505 5340 add.w r3, r5, #12288 @ 0x3000 +1000103a: 631a str r2, [r3, #48] @ 0x30 +1000103c: 6a6b ldr r3, [r5, #36] @ 0x24 +1000103e: 6aac ldr r4, [r5, #40] @ 0x28 +10001040: 2006 movs r0, #6 +10001042: eb04 1483 add.w r4, r4, r3, lsl #6 +10001046: f000 f889 bl 1000115c +1000104a: 4b0f ldr r3, [pc, #60] @ (10001088 ) +1000104c: 02a4 lsls r4, r4, #10 +1000104e: fba3 2300 umull r2, r3, r3, r0 +10001052: 0adb lsrs r3, r3, #11 +10001054: 2100 movs r1, #0 +10001056: fbb4 f0f3 udiv r0, r4, r3 +1000105a: f7ff ff55 bl 10000f08 +1000105e: e7c5 b.n 10000fec +10001060: f3c3 0345 ubfx r3, r3, #1, #6 +10001064: 4611 mov r1, r2 +10001066: eb03 1682 add.w r6, r3, r2, lsl #6 +1000106a: 461a mov r2, r3 +1000106c: e7b9 b.n 10000fe2 +1000106e: bf00 nop +10001070: 40078000 .word 0x40078000 +10001074: 40022000 .word 0x40022000 +10001078: 40023000 .word 0x40023000 +1000107c: 40020000 .word 0x40020000 +10001080: 2000084c .word 0x2000084c +10001084: 003fffc0 .word 0x003fffc0 +10001088: 8f2b7b75 .word 0x8f2b7b75 + +1000108c : +1000108c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001090: ea4f 0c8c mov.w ip, ip, lsl #2 +10001094: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001098: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +1000109c: b5f0 push {r4, r5, r6, r7, lr} +1000109e: 4616 mov r6, r2 +100010a0: f8dc 2004 ldr.w r2, [ip, #4] +100010a4: 1f05 subs r5, r0, #4 +100010a6: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +100010aa: bf38 it cc +100010ac: f44f 3280 movcc.w r2, #65536 @ 0x10000 +100010b0: b2ed uxtb r5, r5 +100010b2: bf38 it cc +100010b4: f8cc 2004 strcc.w r2, [ip, #4] +100010b8: 2d01 cmp r5, #1 +100010ba: d92a bls.n 10001112 +100010bc: f44f 6700 mov.w r7, #2048 @ 0x800 +100010c0: 4c25 ldr r4, [pc, #148] @ (10001158 ) +100010c2: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100010c6: 6017 str r7, [r2, #0] +100010c8: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100010cc: b9b2 cbnz r2, 100010fc +100010ce: f8dc 2000 ldr.w r2, [ip] +100010d2: 2d01 cmp r5, #1 +100010d4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100010d8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100010dc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100010e0: 6032 str r2, [r6, #0] +100010e2: d92a bls.n 1000113a +100010e4: f44f 6100 mov.w r1, #2048 @ 0x800 +100010e8: f844 3020 str.w r3, [r4, r0, lsl #2] +100010ec: f44f 3380 mov.w r3, #65536 @ 0x10000 +100010f0: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100010f4: 6011 str r1, [r2, #0] +100010f6: f8cc 3004 str.w r3, [ip, #4] +100010fa: bdf0 pop {r4, r5, r6, r7, pc} +100010fc: 6967 ldr r7, [r4, #20] +100010fe: fbb7 fef2 udiv lr, r7, r2 +10001102: f10e 0e01 add.w lr, lr, #1 +10001106: eb0e 0e4e add.w lr, lr, lr, lsl #1 +1000110a: f1be 0e03 subs.w lr, lr, #3 +1000110e: d2fc bcs.n 1000110a +10001110: e7dd b.n 100010ce +10001112: 2901 cmp r1, #1 +10001114: d1d2 bne.n 100010bc +10001116: 2403 movs r4, #3 +10001118: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000111c: 6014 str r4, [r2, #0] +1000111e: f8dc 2008 ldr.w r2, [ip, #8] +10001122: 07d2 lsls r2, r2, #31 +10001124: d5fb bpl.n 1000111e +10001126: f8dc 2000 ldr.w r2, [ip] +1000112a: 4c0b ldr r4, [pc, #44] @ (10001158 ) +1000112c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001130: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001134: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001138: 6032 str r2, [r6, #0] +1000113a: 2201 movs r2, #1 +1000113c: f8dc 5000 ldr.w r5, [ip] +10001140: 404d eors r5, r1 +10001142: f005 0503 and.w r5, r5, #3 +10001146: 6035 str r5, [r6, #0] +10001148: fa02 f101 lsl.w r1, r2, r1 +1000114c: f8dc 2008 ldr.w r2, [ip, #8] +10001150: 420a tst r2, r1 +10001152: d0fb beq.n 1000114c +10001154: e7c6 b.n 100010e4 +10001156: bf00 nop +10001158: 200007dc .word 0x200007dc + +1000115c : +1000115c: 4b01 ldr r3, [pc, #4] @ (10001164 ) +1000115e: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001162: 4770 bx lr +10001164: 200007dc .word 0x200007dc + +10001168 : +10001168: b470 push {r4, r5, r6} +1000116a: 9d03 ldr r5, [sp, #12] +1000116c: 6804 ldr r4, [r0, #0] +1000116e: 032d lsls r5, r5, #12 +10001170: ea45 4503 orr.w r5, r5, r3, lsl #16 +10001174: 4b1b ldr r3, [pc, #108] @ (100011e4 ) +10001176: 2c00 cmp r4, #0 +10001178: fbb3 f3f1 udiv r3, r3, r1 +1000117c: fbb2 f6f3 udiv r6, r2, r3 +10001180: db1f blt.n 100011c2 +10001182: 4a19 ldr r2, [pc, #100] @ (100011e8 ) +10001184: 4b19 ldr r3, [pc, #100] @ (100011ec ) +10001186: 4290 cmp r0, r2 +10001188: bf14 ite ne +1000118a: f44f 4280 movne.w r2, #16384 @ 0x4000 +1000118e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10001192: 4c17 ldr r4, [pc, #92] @ (100011f0 ) +10001194: 601a str r2, [r3, #0] +10001196: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000119a: 601a str r2, [r3, #0] +1000119c: 68a3 ldr r3, [r4, #8] +1000119e: ea32 0303 bics.w r3, r2, r3 +100011a2: d1fb bne.n 1000119c +100011a4: 2221 movs r2, #33 @ 0x21 +100011a6: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100011aa: 3304 adds r3, #4 +100011ac: 6001 str r1, [r0, #0] +100011ae: 6086 str r6, [r0, #8] +100011b0: 601a str r2, [r3, #0] +100011b2: 6802 ldr r2, [r0, #0] +100011b4: 2a00 cmp r2, #0 +100011b6: dafc bge.n 100011b2 +100011b8: 2208 movs r2, #8 +100011ba: 60c5 str r5, [r0, #12] +100011bc: 601a str r2, [r3, #0] +100011be: bc70 pop {r4, r5, r6} +100011c0: 4770 bx lr +100011c2: 6803 ldr r3, [r0, #0] +100011c4: f003 033f and.w r3, r3, #63 @ 0x3f +100011c8: 428b cmp r3, r1 +100011ca: d1da bne.n 10001182 +100011cc: 6883 ldr r3, [r0, #8] +100011ce: f3c3 030b ubfx r3, r3, #0, #12 +100011d2: 42b3 cmp r3, r6 +100011d4: d1d5 bne.n 10001182 +100011d6: 68c3 ldr r3, [r0, #12] +100011d8: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100011dc: 42ab cmp r3, r5 +100011de: d1d0 bne.n 10001182 +100011e0: e7ed b.n 100011be +100011e2: bf00 nop +100011e4: 00b71b00 .word 0x00b71b00 +100011e8: 40058000 .word 0x40058000 +100011ec: 40022000 .word 0x40022000 +100011f0: 40020000 .word 0x40020000 + +100011f4 : +100011f4: 2301 movs r3, #1 +100011f6: eb00 0040 add.w r0, r0, r0, lsl #1 +100011fa: 0080 lsls r0, r0, #2 +100011fc: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001200: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001204: 6041 str r1, [r0, #4] +10001206: 6003 str r3, [r0, #0] +10001208: 4770 bx lr +1000120a: bf00 nop + +1000120c : +1000120c: 2300 movs r3, #0 +1000120e: 8adb ldrh r3, [r3, #22] +10001210: 2200 movs r2, #0 +10001212: e842 f200 tt r2, r2 +10001216: 0252 lsls r2, r2, #9 +10001218: d401 bmi.n 1000121e +1000121a: 2110 movs r1, #16 +1000121c: 4718 bx r3 +1000121e: 2104 movs r1, #4 +10001220: 4718 bx r3 +10001222: bf00 nop + +10001224 : +10001224: 4a03 ldr r2, [pc, #12] @ (10001234 ) +10001226: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +1000122a: 2b00 cmp r3, #0 +1000122c: d0fb beq.n 10001226 +1000122e: f3bf 8f5f dmb sy +10001232: 4770 bx lr +10001234: 400e0000 .word 0x400e0000 + +10001238 : +10001238: 2100 movs r1, #0 +1000123a: 4b04 ldr r3, [pc, #16] @ (1000124c ) +1000123c: 4a04 ldr r2, [pc, #16] @ (10001250 ) +1000123e: f3bf 8f5f dmb sy +10001242: f843 1b04 str.w r1, [r3], #4 +10001246: 4293 cmp r3, r2 +10001248: d1f9 bne.n 1000123e +1000124a: 4770 bx lr +1000124c: 400e080c .word 0x400e080c +10001250: 400e082c .word 0x400e082c + +10001254 : +10001254: b410 push {r4} +10001256: f44f 708d mov.w r0, #282 @ 0x11a +1000125a: f44f 642a mov.w r4, #2720 @ 0xaa0 +1000125e: 4a06 ldr r2, [pc, #24] @ (10001278 ) +10001260: 4b06 ldr r3, [pc, #24] @ (1000127c ) +10001262: 4907 ldr r1, [pc, #28] @ (10001280 ) +10001264: 6014 str r4, [r2, #0] +10001266: 60d0 str r0, [r2, #12] +10001268: 6019 str r1, [r3, #0] +1000126a: 6853 ldr r3, [r2, #4] +1000126c: 2b00 cmp r3, #0 +1000126e: dafc bge.n 1000126a +10001270: f85d 4b04 ldr.w r4, [sp], #4 +10001274: 4770 bx lr +10001276: bf00 nop +10001278: 40048000 .word 0x40048000 +1000127c: 4004a000 .word 0x4004a000 +10001280: 00fab000 .word 0x00fab000 + +10001284 : +10001284: 4770 bx lr +10001286: bf00 nop + +10001288 : +10001288: b508 push {r3, lr} +1000128a: 4801 ldr r0, [pc, #4] @ (10001290 ) +1000128c: f7ff f838 bl 10000300 +10001290: 10003664 .word 0x10003664 + +10001294 : +10001294: b538 push {r3, r4, r5, lr} +10001296: 4c05 ldr r4, [pc, #20] @ (100012ac ) +10001298: 4d05 ldr r5, [pc, #20] @ (100012b0 ) +1000129a: 42ac cmp r4, r5 +1000129c: d204 bcs.n 100012a8 +1000129e: f854 3b04 ldr.w r3, [r4], #4 +100012a2: 4798 blx r3 +100012a4: 42ac cmp r4, r5 +100012a6: d3fa bcc.n 1000129e +100012a8: bd38 pop {r3, r4, r5, pc} +100012aa: bf00 nop +100012ac: 100035d0 .word 0x100035d0 +100012b0: 10003610 .word 0x10003610 + +100012b4 : +100012b4: b410 push {r4} +100012b6: 4807 ldr r0, [pc, #28] @ (100012d4 ) +100012b8: 4c07 ldr r4, [pc, #28] @ (100012d8 ) +100012ba: 4b08 ldr r3, [pc, #32] @ (100012dc ) +100012bc: 4a08 ldr r2, [pc, #32] @ (100012e0 ) +100012be: 4909 ldr r1, [pc, #36] @ (100012e4 ) +100012c0: 6004 str r4, [r0, #0] +100012c2: 601a str r2, [r3, #0] +100012c4: 688b ldr r3, [r1, #8] +100012c6: ea32 0303 bics.w r3, r2, r3 +100012ca: d1fb bne.n 100012c4 +100012cc: f85d 4b04 ldr.w r4, [sp], #4 +100012d0: 4770 bx lr +100012d2: bf00 nop +100012d4: 40022000 .word 0x40022000 +100012d8: efef3b7f .word 0xefef3b7f +100012dc: 40023000 .word 0x40023000 +100012e0: 03f3fff6 .word 0x03f3fff6 +100012e4: 40020000 .word 0x40020000 + +100012e8 : +100012e8: 4b04 ldr r3, [pc, #16] @ (100012fc ) +100012ea: 6cdb ldr r3, [r3, #76] @ 0x4c +100012ec: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100012f0: d103 bne.n 100012fa +100012f2: f44f 2280 mov.w r2, #262144 @ 0x40000 +100012f6: 4b02 ldr r3, [pc, #8] @ (10001300 ) +100012f8: 64da str r2, [r3, #76] @ 0x4c +100012fa: 4770 bx lr +100012fc: 50110000 .word 0x50110000 +10001300: 50112000 .word 0x50112000 + +10001304 : +10001304: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001308: 4b04 ldr r3, [pc, #16] @ (1000131c ) +1000130a: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +1000130e: 430b orrs r3, r1 +10001310: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10001314: ee10 0430 dcp_rcmp r0 +10001318: 4770 bx lr +1000131a: bf00 nop +1000131c: 00300303 .word 0x00300303 + +10001320 : +10001320: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10001324: 4b04 ldr r3, [pc, #16] @ (10001338 ) +10001326: 4a05 ldr r2, [pc, #20] @ (1000133c ) +10001328: 6019 str r1, [r3, #0] +1000132a: 6893 ldr r3, [r2, #8] +1000132c: 43db mvns r3, r3 +1000132e: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10001332: d1fa bne.n 1000132a +10001334: 4770 bx lr +10001336: bf00 nop +10001338: 40023000 .word 0x40023000 +1000133c: 40020000 .word 0x40020000 + +10001340 : +10001340: b510 push {r4, lr} +10001342: f245 2053 movw r0, #21075 @ 0x5253 +10001346: f7ff ff61 bl 1000120c +1000134a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000134e: 4603 mov r3, r0 +10001350: 2004 movs r0, #4 +10001352: 4718 bx r3 + +10001354 : +10001354: b510 push {r4, lr} +10001356: f245 2053 movw r0, #21075 @ 0x5253 +1000135a: f7ff ff57 bl 1000120c +1000135e: e8bd 4010 ldmia.w sp!, {r4, lr} +10001362: 4603 mov r3, r0 +10001364: 2001 movs r0, #1 +10001366: 4718 bx r3 + +10001368 : +10001368: f7ff b822 b.w 100003b0 + +1000136c : +1000136c: 4914 ldr r1, [pc, #80] @ (100013c0 ) +1000136e: 4b15 ldr r3, [pc, #84] @ (100013c4 ) +10001370: b570 push {r4, r5, r6, lr} +10001372: 1a5c subs r4, r3, r1 +10001374: 10a6 asrs r6, r4, #2 +10001376: 2e44 cmp r6, #68 @ 0x44 +10001378: 4632 mov r2, r6 +1000137a: bf28 it cs +1000137c: 2244 movcs r2, #68 @ 0x44 +1000137e: 4d12 ldr r5, [pc, #72] @ (100013c8 ) +10001380: 0092 lsls r2, r2, #2 +10001382: 4628 mov r0, r5 +10001384: f002 f872 bl 1000346c +10001388: f5b4 7f86 cmp.w r4, #268 @ 0x10c +1000138c: d813 bhi.n 100013b6 +1000138e: 4a0f ldr r2, [pc, #60] @ (100013cc ) +10001390: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10001394: d012 beq.n 100013bc +10001396: 192b adds r3, r5, r4 +10001398: 0841 lsrs r1, r0, #1 +1000139a: eb03 01c1 add.w r1, r3, r1, lsl #3 +1000139e: e9c3 2200 strd r2, r2, [r3] +100013a2: 3308 adds r3, #8 +100013a4: 428b cmp r3, r1 +100013a6: d1fa bne.n 1000139e +100013a8: 07c3 lsls r3, r0, #31 +100013aa: d504 bpl.n 100013b6 +100013ac: f020 0001 bic.w r0, r0, #1 +100013b0: 4430 add r0, r6 +100013b2: f845 2020 str.w r2, [r5, r0, lsl #2] +100013b6: 4b06 ldr r3, [pc, #24] @ (100013d0 ) +100013b8: 609d str r5, [r3, #8] +100013ba: bd70 pop {r4, r5, r6, pc} +100013bc: 2043 movs r0, #67 @ 0x43 +100013be: e7f8 b.n 100013b2 +100013c0: 10000000 .word 0x10000000 +100013c4: 10000110 .word 0x10000110 +100013c8: 20000000 .word 0x20000000 +100013cc: 10000111 .word 0x10000111 +100013d0: e000ed00 .word 0xe000ed00 + +100013d4 : +100013d4: 2300 movs r3, #0 +100013d6: b570 push {r4, r5, r6, lr} +100013d8: 4c2b ldr r4, [pc, #172] @ (10001488 ) +100013da: b082 sub sp, #8 +100013dc: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100013e0: f7ff ff38 bl 10001254 +100013e4: 2201 movs r2, #1 +100013e6: 4b29 ldr r3, [pc, #164] @ (1000148c ) +100013e8: 63da str r2, [r3, #60] @ 0x3c +100013ea: 6c63 ldr r3, [r4, #68] @ 0x44 +100013ec: 2b01 cmp r3, #1 +100013ee: d1fc bne.n 100013ea +100013f0: 2103 movs r1, #3 +100013f2: 4a26 ldr r2, [pc, #152] @ (1000148c ) +100013f4: 4b24 ldr r3, [pc, #144] @ (10001488 ) +100013f6: 6311 str r1, [r2, #48] @ 0x30 +100013f8: 6b9c ldr r4, [r3, #56] @ 0x38 +100013fa: 2c01 cmp r4, #1 +100013fc: d1fc bne.n 100013f8 +100013fe: 2602 movs r6, #2 +10001400: 2505 movs r5, #5 +10001402: 4621 mov r1, r4 +10001404: 2305 movs r3, #5 +10001406: 4a22 ldr r2, [pc, #136] @ (10001490 ) +10001408: 4822 ldr r0, [pc, #136] @ (10001494 ) +1000140a: 9600 str r6, [sp, #0] +1000140c: f7ff feac bl 10001168 +10001410: 4621 mov r1, r4 +10001412: 462b mov r3, r5 +10001414: 4a20 ldr r2, [pc, #128] @ (10001498 ) +10001416: 4821 ldr r0, [pc, #132] @ (1000149c ) +10001418: 9500 str r5, [sp, #0] +1000141a: f7ff fea5 bl 10001168 +1000141e: 2200 movs r2, #0 +10001420: 2004 movs r0, #4 +10001422: 4631 mov r1, r6 +10001424: 4b1e ldr r3, [pc, #120] @ (100014a0 ) +10001426: f7ff fe31 bl 1000108c +1000142a: 4621 mov r1, r4 +1000142c: 4628 mov r0, r5 +1000142e: 2200 movs r2, #0 +10001430: 4b1c ldr r3, [pc, #112] @ (100014a4 ) +10001432: f7ff fe2b bl 1000108c +10001436: 2200 movs r2, #0 +10001438: 2008 movs r0, #8 +1000143a: 4611 mov r1, r2 +1000143c: 4b1a ldr r3, [pc, #104] @ (100014a8 ) +1000143e: f7ff fe25 bl 1000108c +10001442: 2200 movs r2, #0 +10001444: 2009 movs r0, #9 +10001446: 4611 mov r1, r2 +10001448: 4b17 ldr r3, [pc, #92] @ (100014a8 ) +1000144a: f7ff fe1f bl 1000108c +1000144e: 2200 movs r2, #0 +10001450: 2006 movs r0, #6 +10001452: 4611 mov r1, r2 +10001454: 4b13 ldr r3, [pc, #76] @ (100014a4 ) +10001456: f7ff fe19 bl 1000108c +1000145a: 2200 movs r2, #0 +1000145c: 4b11 ldr r3, [pc, #68] @ (100014a4 ) +1000145e: 2007 movs r0, #7 +10001460: 4611 mov r1, r2 +10001462: f7ff fe13 bl 1000108c +10001466: 2004 movs r0, #4 +10001468: f7ff fe78 bl 1000115c +1000146c: 2400 movs r4, #0 +1000146e: 4b0f ldr r3, [pc, #60] @ (100014ac ) +10001470: fba3 3500 umull r3, r5, r3, r0 +10001474: 0cad lsrs r5, r5, #18 +10001476: b2e0 uxtb r0, r4 +10001478: 4629 mov r1, r5 +1000147a: 3401 adds r4, #1 +1000147c: f7ff feba bl 100011f4 +10001480: 2c06 cmp r4, #6 +10001482: d1f8 bne.n 10001476 +10001484: b002 add sp, #8 +10001486: bd70 pop {r4, r5, r6, pc} +10001488: 40010000 .word 0x40010000 +1000148c: 40013000 .word 0x40013000 +10001490: 59682f00 .word 0x59682f00 +10001494: 40050000 .word 0x40050000 +10001498: 47868c00 .word 0x47868c00 +1000149c: 40058000 .word 0x40058000 +100014a0: 00b71b00 .word 0x00b71b00 +100014a4: 08f0d180 .word 0x08f0d180 +100014a8: 02dc6c00 .word 0x02dc6c00 +100014ac: 431bde83 .word 0x431bde83 + +100014b0 : +100014b0: b086 sub sp, #24 +100014b2: b403 push {r0, r1} +100014b4: fc51 0408 dcp_pxmd r0, r1 +100014b8: e9cd 0102 strd r0, r1, [sp, #8] +100014bc: fc51 0409 dcp_pymd r0, r1 +100014c0: e9cd 0104 strd r0, r1, [sp, #16] +100014c4: ec51 040a dcp_refd r0, r1 +100014c8: e9cd 0106 strd r0, r1, [sp, #24] +100014cc: bc03 pop {r0, r1} +100014ce: 47f0 blx lr + +100014d0 : +100014d0: e8bd 5000 ldmia.w sp!, {ip, lr} +100014d4: ec4e c400 dcp_wxmd ip, lr +100014d8: e8bd 5000 ldmia.w sp!, {ip, lr} +100014dc: ec4e c401 dcp_wymd ip, lr +100014e0: e8bd 5000 ldmia.w sp!, {ip, lr} +100014e4: ec4e c402 dcp_wefd ip, lr +100014e8: bd00 pop {pc} +100014ea: 0000 movs r0, r0 +100014ec: b500 push {lr} +100014ee: f7ff ffdf bl 100014b0 +100014f2: e002 b.n 100014fa <__wrap___aeabi_dadd+0x6> + +100014f4 <__wrap___aeabi_dadd>: +100014f4: fe10 f430 dcp_pcmp APSR_nzcv +100014f8: d4f8 bmi.n 100014ec +100014fa: ec41 0410 dcp_wxup r0, r1 +100014fe: ec43 2411 dcp_wyup r2, r3 +10001502: ee00 0401 dcp_add0 +10001506: ee10 0401 dcp_add1 +1000150a: ee80 0420 dcp_nrdd +1000150e: ec51 0410 dcp_rdda r0, r1 +10001512: 4770 bx lr +10001514: b500 push {lr} +10001516: f7ff ffcb bl 100014b0 +1000151a: e002 b.n 10001522 <__wrap___aeabi_dsub+0x6> + +1000151c <__wrap___aeabi_dsub>: +1000151c: fe10 f430 dcp_pcmp APSR_nzcv +10001520: d4f8 bmi.n 10001514 <__wrap___aeabi_dadd+0x20> +10001522: ec41 0410 dcp_wxup r0, r1 +10001526: ec43 2411 dcp_wyup r2, r3 +1000152a: ee00 0401 dcp_add0 +1000152e: ee10 0421 dcp_sub1 +10001532: ee80 0420 dcp_nrdd +10001536: ec51 0430 dcp_rdds r0, r1 +1000153a: 4770 bx lr +1000153c: b500 push {lr} +1000153e: f7ff ffb7 bl 100014b0 +10001542: e002 b.n 1000154a <__wrap___aeabi_dmul+0x6> + +10001544 <__wrap___aeabi_dmul>: +10001544: fe10 f430 dcp_pcmp APSR_nzcv +10001548: d4f8 bmi.n 1000153c <__wrap___aeabi_dsub+0x20> +1000154a: b510 push {r4, lr} +1000154c: ec41 0410 dcp_wxup r0, r1 +10001550: ec43 2411 dcp_wyup r2, r3 +10001554: ec51 0404 dcp_rxms r0, r1, #0x0 +10001558: ec53 2405 dcp_ryms r2, r3, #0x0 +1000155c: fba0 4c02 umull r4, ip, r0, r2 +10001560: f05f 0e00 movs.w lr, #0 +10001564: fbe0 ce03 umlal ip, lr, r0, r3 +10001568: fbe1 ce02 umlal ip, lr, r1, r2 +1000156c: ec4c 4420 dcp_wxms r4, ip +10001570: 2400 movs r4, #0 +10001572: fbe1 e403 umlal lr, r4, r1, r3 +10001576: ec44 e430 dcp_wxmo lr, r4 +1000157a: ee80 0420 dcp_nrdd +1000157e: ec51 0450 dcp_rddm r0, r1 +10001582: e8bd 4010 ldmia.w sp!, {r4, lr} +10001586: 4770 bx lr +10001588: b500 push {lr} +1000158a: f7ff ff91 bl 100014b0 +1000158e: e002 b.n 10001596 <__wrap___aeabi_ddiv+0x6> + +10001590 <__wrap___aeabi_ddiv>: +10001590: fe10 f430 dcp_pcmp APSR_nzcv +10001594: d4f8 bmi.n 10001588 <__wrap___aeabi_dmul+0x44> +10001596: ec41 0410 dcp_wxup r0, r1 +1000159a: ec43 2411 dcp_wyup r2, r3 +1000159e: ec51 0421 dcp_rymr r0, r1 +100015a2: fba0 1201 umull r1, r2, r0, r1 +100015a6: ea6f 0282 mvn.w r2, r2, lsl #2 +100015aa: fb52 0010 smmlar r0, r2, r0, r0 +100015ae: fb52 f212 smmulr r2, r2, r2 +100015b2: fb52 0010 smmlar r0, r2, r0, r0 +100015b6: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +100015ba: ec53 2404 dcp_rxms r2, r3, #0x0 +100015be: fb5c f113 smmulr r1, ip, r3 +100015c2: ec53 2415 dcp_ryms r2, r3, #0x1 +100015c6: fba1 2002 umull r2, r0, r1, r2 +100015ca: fb01 0003 mla r0, r1, r3, r0 +100015ce: ec53 2444 dcp_rxms r2, r3, #0x4 +100015d2: eba2 0000 sub.w r0, r2, r0 +100015d6: fb50 f21c smmulr r2, r0, ip +100015da: ea4f 1311 mov.w r3, r1, lsr #4 +100015de: eb12 7001 adds.w r0, r2, r1, lsl #28 +100015e2: eb43 71e2 adc.w r1, r3, r2, asr #31 +100015e6: ea40 5051 orr.w r0, r0, r1, lsr #21 +100015ea: ea20 5091 bic.w r0, r0, r1, lsr #22 +100015ee: f020 0007 bic.w r0, r0, #7 +100015f2: ec53 2475 dcp_ryms r2, r3, #0x7 +100015f6: fba0 3c02 umull r3, ip, r0, r2 +100015fa: ec53 2475 dcp_ryms r2, r3, #0x7 +100015fe: fb00 cc03 mla ip, r0, r3, ip +10001602: fb01 cc02 mla ip, r1, r2, ip +10001606: ec53 2404 dcp_rxms r2, r3, #0x0 +1000160a: ebac 4c82 sub.w ip, ip, r2, lsl #18 +1000160e: ea40 705c orr.w r0, r0, ip, lsr #29 +10001612: f1a0 0001 sub.w r0, r0, #1 +10001616: ec41 0440 dcp_wxdd r0, r1 +1000161a: ee80 0420 dcp_nrdd +1000161e: ec51 0470 dcp_rddd r0, r1 +10001622: 4770 bx lr +10001624: b500 push {lr} +10001626: f7ff ff43 bl 100014b0 +1000162a: e002 b.n 10001632 <__wrap___aeabi_i2d+0x6> + +1000162c <__wrap___aeabi_i2d>: +1000162c: fe10 f430 dcp_pcmp APSR_nzcv +10001630: d4f8 bmi.n 10001624 <__wrap___aeabi_ddiv+0x94> +10001632: ec40 0470 dcp_wxic r0, r0 +10001636: ee00 0401 dcp_add0 +1000163a: ee10 0421 dcp_sub1 +1000163e: ee80 0420 dcp_nrdd +10001642: ec51 0430 dcp_rdds r0, r1 +10001646: 4770 bx lr +10001648: b500 push {lr} +1000164a: f7ff ff31 bl 100014b0 +1000164e: e002 b.n 10001656 <__wrap___aeabi_ui2d+0x6> + +10001650 <__wrap___aeabi_ui2d>: +10001650: fe10 f430 dcp_pcmp APSR_nzcv +10001654: d4f8 bmi.n 10001648 <__wrap___aeabi_i2d+0x1c> +10001656: ec40 0460 dcp_wxuc r0, r0 +1000165a: ee00 0401 dcp_add0 +1000165e: ee10 0421 dcp_sub1 +10001662: ee80 0420 dcp_nrdd +10001666: ec51 0430 dcp_rdds r0, r1 +1000166a: 4770 bx lr +1000166c: b500 push {lr} +1000166e: f7ff ff1f bl 100014b0 +10001672: e002 b.n 1000167a + +10001674 <__wrap___aeabi_d2iz>: +10001674: fe10 f430 dcp_pcmp APSR_nzcv +10001678: d4f8 bmi.n 1000166c <__wrap___aeabi_ui2d+0x1c> + +1000167a : +1000167a: ec41 0480 dcp_wxdc r0, r1 +1000167e: ee00 0401 dcp_add0 +10001682: ee10 0401 dcp_add1 +10001686: ee80 0440 dcp_ntdc +1000168a: ee10 0413 dcp_rdic r0 +1000168e: 4770 bx lr +10001690: b500 push {lr} +10001692: f7ff ff0d bl 100014b0 +10001696: e002 b.n 1000169e + +10001698 <__wrap___aeabi_d2uiz>: +10001698: fe10 f430 dcp_pcmp APSR_nzcv +1000169c: d4f8 bmi.n 10001690 + +1000169e : +1000169e: ec41 0480 dcp_wxdc r0, r1 +100016a2: ee00 0401 dcp_add0 +100016a6: ee10 0401 dcp_add1 +100016aa: ee80 0440 dcp_ntdc +100016ae: ee10 0433 dcp_rduc r0 +100016b2: 4770 bx lr +100016b4: b500 push {lr} +100016b6: f7ff fefb bl 100014b0 +100016ba: e002 b.n 100016c2 <__wrap___aeabi_dcmpun+0x6> + +100016bc <__wrap___aeabi_dcmpun>: +100016bc: fe10 f430 dcp_pcmp APSR_nzcv +100016c0: d4f8 bmi.n 100016b4 +100016c2: ec41 0410 dcp_wxup r0, r1 +100016c6: ec43 2411 dcp_wyup r2, r3 +100016ca: ee00 0401 dcp_add0 +100016ce: ee10 0430 dcp_rcmp r0 +100016d2: f3c0 7000 ubfx r0, r0, #28, #1 +100016d6: 4770 bx lr +100016d8: b500 push {lr} +100016da: f7ff fee9 bl 100014b0 +100016de: e002 b.n 100016e6 <__wrap___aeabi_dcmplt+0x6> + +100016e0 <__wrap___aeabi_dcmplt>: +100016e0: fe10 f430 dcp_pcmp APSR_nzcv +100016e4: d4f8 bmi.n 100016d8 <__wrap___aeabi_dcmpun+0x1c> +100016e6: ec43 2410 dcp_wxup r2, r3 +100016ea: ec41 0411 dcp_wyup r0, r1 +100016ee: ee00 0401 dcp_add0 +100016f2: ee10 f430 dcp_rcmp APSR_nzcv +100016f6: bf8c ite hi +100016f8: 2001 movhi r0, #1 +100016fa: 2000 movls r0, #0 +100016fc: 4770 bx lr +100016fe: bf00 nop +10001700: b500 push {lr} +10001702: f7ff fed5 bl 100014b0 +10001706: e002 b.n 1000170e <__wrap___aeabi_dcmple+0x6> + +10001708 <__wrap___aeabi_dcmple>: +10001708: fe10 f430 dcp_pcmp APSR_nzcv +1000170c: d4f8 bmi.n 10001700 <__wrap___aeabi_dcmplt+0x20> +1000170e: ec43 2410 dcp_wxup r2, r3 +10001712: ec41 0411 dcp_wyup r0, r1 +10001716: ee00 0401 dcp_add0 +1000171a: ee10 f430 dcp_rcmp APSR_nzcv +1000171e: bf2c ite cs +10001720: 2001 movcs r0, #1 +10001722: 2000 movcc r0, #0 +10001724: 4770 bx lr +10001726: bf00 nop +10001728: b500 push {lr} +1000172a: f7ff fec1 bl 100014b0 +1000172e: e002 b.n 10001736 <__wrap___aeabi_dcmpge+0x6> + +10001730 <__wrap___aeabi_dcmpge>: +10001730: fe10 f430 dcp_pcmp APSR_nzcv +10001734: d4f8 bmi.n 10001728 <__wrap___aeabi_dcmple+0x20> +10001736: ec41 0410 dcp_wxup r0, r1 +1000173a: ec43 2411 dcp_wyup r2, r3 +1000173e: ee00 0401 dcp_add0 +10001742: ee10 f430 dcp_rcmp APSR_nzcv +10001746: bf2c ite cs +10001748: 2001 movcs r0, #1 +1000174a: 2000 movcc r0, #0 +1000174c: 4770 bx lr +1000174e: bf00 nop +10001750: b500 push {lr} +10001752: f7ff fead bl 100014b0 +10001756: e002 b.n 1000175e <__wrap___aeabi_dcmpgt+0x6> + +10001758 <__wrap___aeabi_dcmpgt>: +10001758: fe10 f430 dcp_pcmp APSR_nzcv +1000175c: d4f8 bmi.n 10001750 <__wrap___aeabi_dcmpge+0x20> +1000175e: ec41 0410 dcp_wxup r0, r1 +10001762: ec43 2411 dcp_wyup r2, r3 +10001766: ee00 0401 dcp_add0 +1000176a: ee10 f430 dcp_rcmp APSR_nzcv +1000176e: bf8c ite hi +10001770: 2001 movhi r0, #1 +10001772: 2000 movls r0, #0 +10001774: 4770 bx lr +10001776: bf00 nop + +10001778 <_out_null>: +10001778: 4770 bx lr +1000177a: bf00 nop + +1000177c <_out_rev>: +1000177c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001780: b083 sub sp, #12 +10001782: 4699 mov r9, r3 +10001784: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001788: 9b0f ldr r3, [sp, #60] @ 0x3c +1000178a: 4688 mov r8, r1 +1000178c: 4611 mov r1, r2 +1000178e: 079a lsls r2, r3, #30 +10001790: 4607 mov r7, r0 +10001792: d116 bne.n 100017c2 <_out_rev+0x46> +10001794: 45da cmp sl, fp +10001796: d23a bcs.n 1000180e <_out_rev+0x92> +10001798: 460c mov r4, r1 +1000179a: 460d mov r5, r1 +1000179c: ebab 060a sub.w r6, fp, sl +100017a0: 440e add r6, r1 +100017a2: 4622 mov r2, r4 +100017a4: 464b mov r3, r9 +100017a6: 4641 mov r1, r8 +100017a8: 2020 movs r0, #32 +100017aa: 3401 adds r4, #1 +100017ac: 47b8 blx r7 +100017ae: 42b4 cmp r4, r6 +100017b0: d1f7 bne.n 100017a2 <_out_rev+0x26> +100017b2: 4629 mov r1, r5 +100017b4: f1ba 0f00 cmp.w sl, #0 +100017b8: d108 bne.n 100017cc <_out_rev+0x50> +100017ba: 4620 mov r0, r4 +100017bc: b003 add sp, #12 +100017be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100017c2: 460c mov r4, r1 +100017c4: f1ba 0f00 cmp.w sl, #0 +100017c8: d010 beq.n 100017ec <_out_rev+0x70> +100017ca: 460e mov r6, r1 +100017cc: 4655 mov r5, sl +100017ce: 9b0c ldr r3, [sp, #48] @ 0x30 +100017d0: 442e add r6, r5 +100017d2: 449a add sl, r3 +100017d4: 9101 str r1, [sp, #4] +100017d6: 1b72 subs r2, r6, r5 +100017d8: 464b mov r3, r9 +100017da: 3d01 subs r5, #1 +100017dc: 4641 mov r1, r8 +100017de: f81a 0d01 ldrb.w r0, [sl, #-1]! +100017e2: 4634 mov r4, r6 +100017e4: 47b8 blx r7 +100017e6: 2d00 cmp r5, #0 +100017e8: d1f5 bne.n 100017d6 <_out_rev+0x5a> +100017ea: 9901 ldr r1, [sp, #4] +100017ec: 9b0f ldr r3, [sp, #60] @ 0x3c +100017ee: 079b lsls r3, r3, #30 +100017f0: d5e3 bpl.n 100017ba <_out_rev+0x3e> +100017f2: 1a65 subs r5, r4, r1 +100017f4: 45ab cmp fp, r5 +100017f6: d9e0 bls.n 100017ba <_out_rev+0x3e> +100017f8: 4622 mov r2, r4 +100017fa: 464b mov r3, r9 +100017fc: 4641 mov r1, r8 +100017fe: 2020 movs r0, #32 +10001800: 3501 adds r5, #1 +10001802: 47b8 blx r7 +10001804: 455d cmp r5, fp +10001806: f104 0401 add.w r4, r4, #1 +1000180a: d3f5 bcc.n 100017f8 <_out_rev+0x7c> +1000180c: e7d5 b.n 100017ba <_out_rev+0x3e> +1000180e: 460c mov r4, r1 +10001810: f1ba 0f00 cmp.w sl, #0 +10001814: d1d9 bne.n 100017ca <_out_rev+0x4e> +10001816: e7d0 b.n 100017ba <_out_rev+0x3e> + +10001818 <_ntoa_format>: +10001818: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000181c: 9f0f ldr r7, [sp, #60] @ 0x3c +1000181e: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001822: f017 0f02 tst.w r7, #2 +10001826: 9c0a ldr r4, [sp, #40] @ 0x28 +10001828: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +1000182c: 9d0e ldr r5, [sp, #56] @ 0x38 +1000182e: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001832: d144 bne.n 100018be <_ntoa_format+0xa6> +10001834: bbf5 cbnz r5, 100018b4 <_ntoa_format+0x9c> +10001836: 42b4 cmp r4, r6 +10001838: d241 bcs.n 100018be <_ntoa_format+0xa6> +1000183a: f007 0b01 and.w fp, r7, #1 +1000183e: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001842: f04f 0e30 mov.w lr, #48 @ 0x30 +10001846: 44c4 add ip, r8 +10001848: e004 b.n 10001854 <_ntoa_format+0x3c> +1000184a: 3401 adds r4, #1 +1000184c: 42a6 cmp r6, r4 +1000184e: f80c ef01 strb.w lr, [ip, #1]! +10001852: d901 bls.n 10001858 <_ntoa_format+0x40> +10001854: 2c20 cmp r4, #32 +10001856: d1f8 bne.n 1000184a <_ntoa_format+0x32> +10001858: f1bb 0f00 cmp.w fp, #0 +1000185c: f000 8088 beq.w 10001970 <_ntoa_format+0x158> +10001860: 42a5 cmp r5, r4 +10001862: d92c bls.n 100018be <_ntoa_format+0xa6> +10001864: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001868: f04f 0e30 mov.w lr, #48 @ 0x30 +1000186c: 44c4 add ip, r8 +1000186e: e004 b.n 1000187a <_ntoa_format+0x62> +10001870: 3401 adds r4, #1 +10001872: 42ac cmp r4, r5 +10001874: f80c ef01 strb.w lr, [ip, #1]! +10001878: d021 beq.n 100018be <_ntoa_format+0xa6> +1000187a: 2c20 cmp r4, #32 +1000187c: d1f8 bne.n 10001870 <_ntoa_format+0x58> +1000187e: f017 0f10 tst.w r7, #16 +10001882: d00e beq.n 100018a2 <_ntoa_format+0x8a> +10001884: f417 6f80 tst.w r7, #1024 @ 0x400 +10001888: d154 bne.n 10001934 <_ntoa_format+0x11c> +1000188a: 42a6 cmp r6, r4 +1000188c: d063 beq.n 10001956 <_ntoa_format+0x13e> +1000188e: 42a5 cmp r5, r4 +10001890: d061 beq.n 10001956 <_ntoa_format+0x13e> +10001892: f1b9 0f10 cmp.w r9, #16 +10001896: d050 beq.n 1000193a <_ntoa_format+0x122> +10001898: f1b9 0f02 cmp.w r9, #2 +1000189c: d056 beq.n 1000194c <_ntoa_format+0x134> +1000189e: 2c20 cmp r4, #32 +100018a0: d129 bne.n 100018f6 <_ntoa_format+0xde> +100018a2: 2420 movs r4, #32 +100018a4: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100018a8: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100018ac: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100018b0: f7ff bf64 b.w 1000177c <_out_rev> +100018b4: f017 0b01 ands.w fp, r7, #1 +100018b8: d134 bne.n 10001924 <_ntoa_format+0x10c> +100018ba: 42b4 cmp r4, r6 +100018bc: d3bf bcc.n 1000183e <_ntoa_format+0x26> +100018be: f017 0f10 tst.w r7, #16 +100018c2: d01e beq.n 10001902 <_ntoa_format+0xea> +100018c4: f417 6f80 tst.w r7, #1024 @ 0x400 +100018c8: d1e3 bne.n 10001892 <_ntoa_format+0x7a> +100018ca: 2c00 cmp r4, #0 +100018cc: d1dd bne.n 1000188a <_ntoa_format+0x72> +100018ce: f1b9 0f10 cmp.w r9, #16 +100018d2: d063 beq.n 1000199c <_ntoa_format+0x184> +100018d4: f1b9 0f02 cmp.w r9, #2 +100018d8: d077 beq.n 100019ca <_ntoa_format+0x1b2> +100018da: 2430 movs r4, #48 @ 0x30 +100018dc: f888 4000 strb.w r4, [r8] +100018e0: 2401 movs r4, #1 +100018e2: f1ba 0f00 cmp.w sl, #0 +100018e6: d111 bne.n 1000190c <_ntoa_format+0xf4> +100018e8: 077e lsls r6, r7, #29 +100018ea: d548 bpl.n 1000197e <_ntoa_format+0x166> +100018ec: 262b movs r6, #43 @ 0x2b +100018ee: f808 6004 strb.w r6, [r8, r4] +100018f2: 3401 adds r4, #1 +100018f4: e7d6 b.n 100018a4 <_ntoa_format+0x8c> +100018f6: 4626 mov r6, r4 +100018f8: 3401 adds r4, #1 +100018fa: f04f 0c30 mov.w ip, #48 @ 0x30 +100018fe: f808 c006 strb.w ip, [r8, r6] +10001902: 2c20 cmp r4, #32 +10001904: d0cd beq.n 100018a2 <_ntoa_format+0x8a> +10001906: f1ba 0f00 cmp.w sl, #0 +1000190a: d0ed beq.n 100018e8 <_ntoa_format+0xd0> +1000190c: 262d movs r6, #45 @ 0x2d +1000190e: f808 6004 strb.w r6, [r8, r4] +10001912: 3401 adds r4, #1 +10001914: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001918: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +1000191c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001920: f7ff bf2c b.w 1000177c <_out_rev> +10001924: f1ba 0f00 cmp.w sl, #0 +10001928: d030 beq.n 1000198c <_ntoa_format+0x174> +1000192a: 42b4 cmp r4, r6 +1000192c: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001930: d385 bcc.n 1000183e <_ntoa_format+0x26> +10001932: e795 b.n 10001860 <_ntoa_format+0x48> +10001934: f1b9 0f10 cmp.w r9, #16 +10001938: d1b3 bne.n 100018a2 <_ntoa_format+0x8a> +1000193a: 06be lsls r6, r7, #26 +1000193c: d53b bpl.n 100019b6 <_ntoa_format+0x19e> +1000193e: 2c20 cmp r4, #32 +10001940: d0af beq.n 100018a2 <_ntoa_format+0x8a> +10001942: 2658 movs r6, #88 @ 0x58 +10001944: f808 6004 strb.w r6, [r8, r4] +10001948: 3401 adds r4, #1 +1000194a: e7a8 b.n 1000189e <_ntoa_format+0x86> +1000194c: 2c20 cmp r4, #32 +1000194e: d0a8 beq.n 100018a2 <_ntoa_format+0x8a> +10001950: 4626 mov r6, r4 +10001952: 3401 adds r4, #1 +10001954: e007 b.n 10001966 <_ntoa_format+0x14e> +10001956: 1e66 subs r6, r4, #1 +10001958: d0b9 beq.n 100018ce <_ntoa_format+0xb6> +1000195a: f1b9 0f10 cmp.w r9, #16 +1000195e: d036 beq.n 100019ce <_ntoa_format+0x1b6> +10001960: f1b9 0f02 cmp.w r9, #2 +10001964: d1c9 bne.n 100018fa <_ntoa_format+0xe2> +10001966: f04f 0c62 mov.w ip, #98 @ 0x62 +1000196a: f808 c006 strb.w ip, [r8, r6] +1000196e: e796 b.n 1000189e <_ntoa_format+0x86> +10001970: f017 0f10 tst.w r7, #16 +10001974: d0c5 beq.n 10001902 <_ntoa_format+0xea> +10001976: f417 6f80 tst.w r7, #1024 @ 0x400 +1000197a: d086 beq.n 1000188a <_ntoa_format+0x72> +1000197c: e789 b.n 10001892 <_ntoa_format+0x7a> +1000197e: 073e lsls r6, r7, #28 +10001980: d590 bpl.n 100018a4 <_ntoa_format+0x8c> +10001982: 2620 movs r6, #32 +10001984: f808 6004 strb.w r6, [r8, r4] +10001988: 3401 adds r4, #1 +1000198a: e78b b.n 100018a4 <_ntoa_format+0x8c> +1000198c: f017 0f0c tst.w r7, #12 +10001990: d000 beq.n 10001994 <_ntoa_format+0x17c> +10001992: 3d01 subs r5, #1 +10001994: 42b4 cmp r4, r6 +10001996: f4ff af52 bcc.w 1000183e <_ntoa_format+0x26> +1000199a: e761 b.n 10001860 <_ntoa_format+0x48> +1000199c: 06bc lsls r4, r7, #26 +1000199e: d412 bmi.n 100019c6 <_ntoa_format+0x1ae> +100019a0: 2478 movs r4, #120 @ 0x78 +100019a2: f888 4000 strb.w r4, [r8] +100019a6: 2430 movs r4, #48 @ 0x30 +100019a8: f888 4001 strb.w r4, [r8, #1] +100019ac: 2402 movs r4, #2 +100019ae: f1ba 0f00 cmp.w sl, #0 +100019b2: d099 beq.n 100018e8 <_ntoa_format+0xd0> +100019b4: e7aa b.n 1000190c <_ntoa_format+0xf4> +100019b6: 2c20 cmp r4, #32 +100019b8: f43f af73 beq.w 100018a2 <_ntoa_format+0x8a> +100019bc: 2678 movs r6, #120 @ 0x78 +100019be: f808 6004 strb.w r6, [r8, r4] +100019c2: 3401 adds r4, #1 +100019c4: e76b b.n 1000189e <_ntoa_format+0x86> +100019c6: 2458 movs r4, #88 @ 0x58 +100019c8: e7eb b.n 100019a2 <_ntoa_format+0x18a> +100019ca: 2462 movs r4, #98 @ 0x62 +100019cc: e7e9 b.n 100019a2 <_ntoa_format+0x18a> +100019ce: f017 0f20 tst.w r7, #32 +100019d2: f1a4 0c02 sub.w ip, r4, #2 +100019d6: d004 beq.n 100019e2 <_ntoa_format+0x1ca> +100019d8: f04f 0e58 mov.w lr, #88 @ 0x58 +100019dc: f808 e00c strb.w lr, [r8, ip] +100019e0: e78b b.n 100018fa <_ntoa_format+0xe2> +100019e2: f04f 0e78 mov.w lr, #120 @ 0x78 +100019e6: f808 e00c strb.w lr, [r8, ip] +100019ea: e786 b.n 100018fa <_ntoa_format+0xe2> + +100019ec <_out_char>: +100019ec: b900 cbnz r0, 100019f0 <_out_char+0x4> +100019ee: 4770 bx lr +100019f0: f001 bb72 b.w 100030d8 <__wrap_putchar> + +100019f4 <_out_fct>: +100019f4: b110 cbz r0, 100019fc <_out_fct+0x8> +100019f6: e9d1 3100 ldrd r3, r1, [r1] +100019fa: 4718 bx r3 +100019fc: 4770 bx lr +100019fe: bf00 nop + +10001a00 <_ftoa>: +10001a00: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a04: b097 sub sp, #92 @ 0x5c +10001a06: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001a0a: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001a0e: 4607 mov r7, r0 +10001a10: 4688 mov r8, r1 +10001a12: ec51 0b17 vmov r0, r1, d7 +10001a16: 9c24 ldr r4, [sp, #144] @ 0x90 +10001a18: 4699 mov r9, r3 +10001a1a: 920c str r2, [sp, #48] @ 0x30 +10001a1c: 460b mov r3, r1 +10001a1e: 4602 mov r2, r0 +10001a20: ed8d 7b04 vstr d7, [sp, #16] +10001a24: 9407 str r4, [sp, #28] +10001a26: f7ff fe49 bl 100016bc <__wrap___aeabi_dcmpun> +10001a2a: 2800 cmp r0, #0 +10001a2c: f040 81f4 bne.w 10001e18 <_ftoa+0x418> +10001a30: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a34: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a38: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001a3c: f7ff fe50 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a40: 2800 cmp r0, #0 +10001a42: f040 811b bne.w 10001c7c <_ftoa+0x27c> +10001a46: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a4a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001a4e: 4bac ldr r3, [pc, #688] @ (10001d00 <_ftoa+0x300>) +10001a50: f7ff fe82 bl 10001758 <__wrap___aeabi_dcmpgt> +10001a54: 2800 cmp r0, #0 +10001a56: f040 80ee bne.w 10001c36 <_ftoa+0x236> +10001a5a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a5e: a3a4 add r3, pc, #656 @ (adr r3, 10001cf0 <_ftoa+0x2f0>) +10001a60: e9d3 2300 ldrd r2, r3, [r3] +10001a64: f7ff fe78 bl 10001758 <__wrap___aeabi_dcmpgt> +10001a68: 2800 cmp r0, #0 +10001a6a: f040 80d3 bne.w 10001c14 <_ftoa+0x214> +10001a6e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a72: a3a1 add r3, pc, #644 @ (adr r3, 10001cf8 <_ftoa+0x2f8>) +10001a74: e9d3 2300 ldrd r2, r3, [r3] +10001a78: f7ff fe32 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a7c: 2800 cmp r0, #0 +10001a7e: f040 80c9 bne.w 10001c14 <_ftoa+0x214> +10001a82: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a86: 2200 movs r2, #0 +10001a88: 2300 movs r3, #0 +10001a8a: f7ff fe29 bl 100016e0 <__wrap___aeabi_dcmplt> +10001a8e: 2800 cmp r0, #0 +10001a90: f040 80e8 bne.w 10001c64 <_ftoa+0x264> +10001a94: 4623 mov r3, r4 +10001a96: 900d str r0, [sp, #52] @ 0x34 +10001a98: f413 6f80 tst.w r3, #1024 @ 0x400 +10001a9c: bf08 it eq +10001a9e: 2506 moveq r5, #6 +10001aa0: 2130 movs r1, #48 @ 0x30 +10001aa2: 462b mov r3, r5 +10001aa4: aa0e add r2, sp, #56 @ 0x38 +10001aa6: f1a5 0620 sub.w r6, r5, #32 +10001aaa: e005 b.n 10001ab8 <_ftoa+0xb8> +10001aac: 3b01 subs r3, #1 +10001aae: 42b3 cmp r3, r6 +10001ab0: f802 1b01 strb.w r1, [r2], #1 +10001ab4: f000 8193 beq.w 10001dde <_ftoa+0x3de> +10001ab8: 2b09 cmp r3, #9 +10001aba: d8f7 bhi.n 10001aac <_ftoa+0xac> +10001abc: 461e mov r6, r3 +10001abe: 1aed subs r5, r5, r3 +10001ac0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ac4: f7ff fdd6 bl 10001674 <__wrap___aeabi_d2iz> +10001ac8: 4b8e ldr r3, [pc, #568] @ (10001d04 <_ftoa+0x304>) +10001aca: 4604 mov r4, r0 +10001acc: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001ad0: ed93 7b00 vldr d7, [r3] +10001ad4: ed8d 7b08 vstr d7, [sp, #32] +10001ad8: f7ff fda8 bl 1000162c <__wrap___aeabi_i2d> +10001adc: 4602 mov r2, r0 +10001ade: 460b mov r3, r1 +10001ae0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ae4: f7ff fd1a bl 1000151c <__wrap___aeabi_dsub> +10001ae8: e9dd 2308 ldrd r2, r3, [sp, #32] +10001aec: f7ff fd2a bl 10001544 <__wrap___aeabi_dmul> +10001af0: 4602 mov r2, r0 +10001af2: 460b mov r3, r1 +10001af4: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001af8: f7ff fdce bl 10001698 <__wrap___aeabi_d2uiz> +10001afc: 4682 mov sl, r0 +10001afe: f7ff fda7 bl 10001650 <__wrap___aeabi_ui2d> +10001b02: 4602 mov r2, r0 +10001b04: 460b mov r3, r1 +10001b06: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001b0a: f7ff fd07 bl 1000151c <__wrap___aeabi_dsub> +10001b0e: 4602 mov r2, r0 +10001b10: 460b mov r3, r1 +10001b12: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001b16: 2200 movs r2, #0 +10001b18: 4b7b ldr r3, [pc, #492] @ (10001d08 <_ftoa+0x308>) +10001b1a: f7ff fe1d bl 10001758 <__wrap___aeabi_dcmpgt> +10001b1e: 2800 cmp r0, #0 +10001b20: f000 80fe beq.w 10001d20 <_ftoa+0x320> +10001b24: f10a 0a01 add.w sl, sl, #1 +10001b28: 4650 mov r0, sl +10001b2a: f7ff fd91 bl 10001650 <__wrap___aeabi_ui2d> +10001b2e: 4602 mov r2, r0 +10001b30: 460b mov r3, r1 +10001b32: e9dd 0108 ldrd r0, r1, [sp, #32] +10001b36: f7ff fde7 bl 10001708 <__wrap___aeabi_dcmple> +10001b3a: b110 cbz r0, 10001b42 <_ftoa+0x142> +10001b3c: f04f 0a00 mov.w sl, #0 +10001b40: 3401 adds r4, #1 +10001b42: 2e00 cmp r6, #0 +10001b44: f000 80fd beq.w 10001d42 <_ftoa+0x342> +10001b48: 1e68 subs r0, r5, #1 +10001b4a: ab0e add r3, sp, #56 @ 0x38 +10001b4c: f8df c1cc ldr.w ip, [pc, #460] @ 10001d1c <_ftoa+0x31c> +10001b50: 4418 add r0, r3 +10001b52: e00f b.n 10001b74 <_ftoa+0x174> +10001b54: fbac 210a umull r2, r1, ip, sl +10001b58: 08c9 lsrs r1, r1, #3 +10001b5a: eb01 0281 add.w r2, r1, r1, lsl #2 +10001b5e: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001b62: 3230 adds r2, #48 @ 0x30 +10001b64: f1ba 0f09 cmp.w sl, #9 +10001b68: f800 2f01 strb.w r2, [r0, #1]! +10001b6c: f240 811c bls.w 10001da8 <_ftoa+0x3a8> +10001b70: 468a mov sl, r1 +10001b72: 461d mov r5, r3 +10001b74: 2d20 cmp r5, #32 +10001b76: f105 0301 add.w r3, r5, #1 +10001b7a: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001b7e: d1e9 bne.n 10001b54 <_ftoa+0x154> +10001b80: 2520 movs r5, #32 +10001b82: 1e69 subs r1, r5, #1 +10001b84: ab0e add r3, sp, #56 @ 0x38 +10001b86: 4861 ldr r0, [pc, #388] @ (10001d0c <_ftoa+0x30c>) +10001b88: 4419 add r1, r3 +10001b8a: e010 b.n 10001bae <_ftoa+0x1ae> +10001b8c: fb80 6204 smull r6, r2, r0, r4 +10001b90: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001b94: eb03 0283 add.w r2, r3, r3, lsl #2 +10001b98: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001b9c: f104 0230 add.w r2, r4, #48 @ 0x30 +10001ba0: 3501 adds r5, #1 +10001ba2: 461c mov r4, r3 +10001ba4: f801 2f01 strb.w r2, [r1, #1]! +10001ba8: 2b00 cmp r3, #0 +10001baa: f000 80eb beq.w 10001d84 <_ftoa+0x384> +10001bae: 2d20 cmp r5, #32 +10001bb0: ea4f 73e4 mov.w r3, r4, asr #31 +10001bb4: d1ea bne.n 10001b8c <_ftoa+0x18c> +10001bb6: 9b07 ldr r3, [sp, #28] +10001bb8: f003 0303 and.w r3, r3, #3 +10001bbc: 2b01 cmp r3, #1 +10001bbe: d118 bne.n 10001bf2 <_ftoa+0x1f2> +10001bc0: f1bb 0f00 cmp.w fp, #0 +10001bc4: d015 beq.n 10001bf2 <_ftoa+0x1f2> +10001bc6: 9b0d ldr r3, [sp, #52] @ 0x34 +10001bc8: 2b00 cmp r3, #0 +10001bca: f000 810a beq.w 10001de2 <_ftoa+0x3e2> +10001bce: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001bd2: f1bb 0f20 cmp.w fp, #32 +10001bd6: d90c bls.n 10001bf2 <_ftoa+0x1f2> +10001bd8: 1e6b subs r3, r5, #1 +10001bda: a90e add r1, sp, #56 @ 0x38 +10001bdc: 2230 movs r2, #48 @ 0x30 +10001bde: 440b add r3, r1 +10001be0: e005 b.n 10001bee <_ftoa+0x1ee> +10001be2: 3501 adds r5, #1 +10001be4: 455d cmp r5, fp +10001be6: f803 2f01 strb.w r2, [r3, #1]! +10001bea: f080 80d1 bcs.w 10001d90 <_ftoa+0x390> +10001bee: 2d20 cmp r5, #32 +10001bf0: d1f7 bne.n 10001be2 <_ftoa+0x1e2> +10001bf2: 9b07 ldr r3, [sp, #28] +10001bf4: ac0e add r4, sp, #56 @ 0x38 +10001bf6: e9cd b302 strd fp, r3, [sp, #8] +10001bfa: 4641 mov r1, r8 +10001bfc: 464b mov r3, r9 +10001bfe: 4638 mov r0, r7 +10001c00: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c02: 9501 str r5, [sp, #4] +10001c04: 9400 str r4, [sp, #0] +10001c06: f7ff fdb9 bl 1000177c <_out_rev> +10001c0a: 4682 mov sl, r0 +10001c0c: 4650 mov r0, sl +10001c0e: b017 add sp, #92 @ 0x5c +10001c10: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001c14: 9b07 ldr r3, [sp, #28] +10001c16: ed9d 7b04 vldr d7, [sp, #16] +10001c1a: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001c1e: 4641 mov r1, r8 +10001c20: 464b mov r3, r9 +10001c22: 4638 mov r0, r7 +10001c24: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c26: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001c2a: 9522 str r5, [sp, #136] @ 0x88 +10001c2c: b017 add sp, #92 @ 0x5c +10001c2e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c32: f000 b945 b.w 10001ec0 <_etoa> +10001c36: 0761 lsls r1, r4, #29 +10001c38: 4623 mov r3, r4 +10001c3a: bf4c ite mi +10001c3c: 2304 movmi r3, #4 +10001c3e: 2303 movpl r3, #3 +10001c40: 4641 mov r1, r8 +10001c42: 9321 str r3, [sp, #132] @ 0x84 +10001c44: 4638 mov r0, r7 +10001c46: 464b mov r3, r9 +10001c48: 9a07 ldr r2, [sp, #28] +10001c4a: bf48 it mi +10001c4c: 4c30 ldrmi r4, [pc, #192] @ (10001d10 <_ftoa+0x310>) +10001c4e: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001c52: bf58 it pl +10001c54: 4c2f ldrpl r4, [pc, #188] @ (10001d14 <_ftoa+0x314>) +10001c56: 9a0c ldr r2, [sp, #48] @ 0x30 +10001c58: 9420 str r4, [sp, #128] @ 0x80 +10001c5a: b017 add sp, #92 @ 0x5c +10001c5c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c60: f7ff bd8c b.w 1000177c <_out_rev> +10001c64: e9dd 2304 ldrd r2, r3, [sp, #16] +10001c68: 2000 movs r0, #0 +10001c6a: 2100 movs r1, #0 +10001c6c: f7ff fc56 bl 1000151c <__wrap___aeabi_dsub> +10001c70: 2301 movs r3, #1 +10001c72: e9cd 0104 strd r0, r1, [sp, #16] +10001c76: 930d str r3, [sp, #52] @ 0x34 +10001c78: 4623 mov r3, r4 +10001c7a: e70d b.n 10001a98 <_ftoa+0x98> +10001c7c: 4623 mov r3, r4 +10001c7e: 079c lsls r4, r3, #30 +10001c80: f040 80aa bne.w 10001dd8 <_ftoa+0x3d8> +10001c84: f1bb 0f04 cmp.w fp, #4 +10001c88: f240 80a6 bls.w 10001dd8 <_ftoa+0x3d8> +10001c8c: 9b0c ldr r3, [sp, #48] @ 0x30 +10001c8e: 461d mov r5, r3 +10001c90: 1f1c subs r4, r3, #4 +10001c92: eb04 0a0b add.w sl, r4, fp +10001c96: 462a mov r2, r5 +10001c98: 464b mov r3, r9 +10001c9a: 4641 mov r1, r8 +10001c9c: 2020 movs r0, #32 +10001c9e: 3501 adds r5, #1 +10001ca0: 47b8 blx r7 +10001ca2: 45aa cmp sl, r5 +10001ca4: d1f7 bne.n 10001c96 <_ftoa+0x296> +10001ca6: 4655 mov r5, sl +10001ca8: 4c1b ldr r4, [pc, #108] @ (10001d18 <_ftoa+0x318>) +10001caa: 1f26 subs r6, r4, #4 +10001cac: f814 0d01 ldrb.w r0, [r4, #-1]! +10001cb0: 462a mov r2, r5 +10001cb2: 464b mov r3, r9 +10001cb4: 4641 mov r1, r8 +10001cb6: 47b8 blx r7 +10001cb8: 42b4 cmp r4, r6 +10001cba: f105 0501 add.w r5, r5, #1 +10001cbe: d1f5 bne.n 10001cac <_ftoa+0x2ac> +10001cc0: 9b07 ldr r3, [sp, #28] +10001cc2: f10a 0a04 add.w sl, sl, #4 +10001cc6: 0798 lsls r0, r3, #30 +10001cc8: d5a0 bpl.n 10001c0c <_ftoa+0x20c> +10001cca: 9c0c ldr r4, [sp, #48] @ 0x30 +10001ccc: ebaa 0304 sub.w r3, sl, r4 +10001cd0: 459b cmp fp, r3 +10001cd2: d99b bls.n 10001c0c <_ftoa+0x20c> +10001cd4: 4652 mov r2, sl +10001cd6: 464b mov r3, r9 +10001cd8: 4641 mov r1, r8 +10001cda: 2020 movs r0, #32 +10001cdc: f10a 0a01 add.w sl, sl, #1 +10001ce0: 47b8 blx r7 +10001ce2: ebaa 0304 sub.w r3, sl, r4 +10001ce6: 455b cmp r3, fp +10001ce8: d3f4 bcc.n 10001cd4 <_ftoa+0x2d4> +10001cea: e78f b.n 10001c0c <_ftoa+0x20c> +10001cec: f3af 8000 nop.w +10001cf0: 00000000 .word 0x00000000 +10001cf4: 41cdcd65 .word 0x41cdcd65 +10001cf8: 00000000 .word 0x00000000 +10001cfc: c1cdcd65 .word 0xc1cdcd65 +10001d00: 7fefffff .word 0x7fefffff +10001d04: 10003768 .word 0x10003768 +10001d08: 3fe00000 .word 0x3fe00000 +10001d0c: 66666667 .word 0x66666667 +10001d10: 100036c4 .word 0x100036c4 +10001d14: 100036cc .word 0x100036cc +10001d18: 100036d8 .word 0x100036d8 +10001d1c: cccccccd .word 0xcccccccd +10001d20: 2200 movs r2, #0 +10001d22: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001d26: 4b63 ldr r3, [pc, #396] @ (10001eb4 <_ftoa+0x4b4>) +10001d28: f7ff fcda bl 100016e0 <__wrap___aeabi_dcmplt> +10001d2c: 2800 cmp r0, #0 +10001d2e: f47f af08 bne.w 10001b42 <_ftoa+0x142> +10001d32: f1ba 0f00 cmp.w sl, #0 +10001d36: d16a bne.n 10001e0e <_ftoa+0x40e> +10001d38: f10a 0a01 add.w sl, sl, #1 +10001d3c: 2e00 cmp r6, #0 +10001d3e: f47f af03 bne.w 10001b48 <_ftoa+0x148> +10001d42: 4620 mov r0, r4 +10001d44: f7ff fc72 bl 1000162c <__wrap___aeabi_i2d> +10001d48: 4602 mov r2, r0 +10001d4a: 460b mov r3, r1 +10001d4c: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d50: f7ff fbe4 bl 1000151c <__wrap___aeabi_dsub> +10001d54: 4602 mov r2, r0 +10001d56: 460b mov r3, r1 +10001d58: e9cd 2304 strd r2, r3, [sp, #16] +10001d5c: 2200 movs r2, #0 +10001d5e: 4b55 ldr r3, [pc, #340] @ (10001eb4 <_ftoa+0x4b4>) +10001d60: f7ff fcbe bl 100016e0 <__wrap___aeabi_dcmplt> +10001d64: 2800 cmp r0, #0 +10001d66: f47f af0c bne.w 10001b82 <_ftoa+0x182> +10001d6a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d6e: 2200 movs r2, #0 +10001d70: 4b50 ldr r3, [pc, #320] @ (10001eb4 <_ftoa+0x4b4>) +10001d72: f7ff fcf1 bl 10001758 <__wrap___aeabi_dcmpgt> +10001d76: 2800 cmp r0, #0 +10001d78: f47f af03 bne.w 10001b82 <_ftoa+0x182> +10001d7c: 3401 adds r4, #1 +10001d7e: f024 0401 bic.w r4, r4, #1 +10001d82: e6fe b.n 10001b82 <_ftoa+0x182> +10001d84: 9b07 ldr r3, [sp, #28] +10001d86: f003 0303 and.w r3, r3, #3 +10001d8a: 2b01 cmp r3, #1 +10001d8c: f000 8082 beq.w 10001e94 <_ftoa+0x494> +10001d90: 2d20 cmp r5, #32 +10001d92: f43f af2e beq.w 10001bf2 <_ftoa+0x1f2> +10001d96: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d98: b37b cbz r3, 10001dfa <_ftoa+0x3fa> +10001d9a: 222d movs r2, #45 @ 0x2d +10001d9c: eb0d 0305 add.w r3, sp, r5 +10001da0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001da4: 3501 adds r5, #1 +10001da6: e724 b.n 10001bf2 <_ftoa+0x1f2> +10001da8: 2b20 cmp r3, #32 +10001daa: f43f aee9 beq.w 10001b80 <_ftoa+0x180> +10001dae: aa0e add r2, sp, #56 @ 0x38 +10001db0: 4415 add r5, r2 +10001db2: 441e add r6, r3 +10001db4: 2230 movs r2, #48 @ 0x30 +10001db6: e004 b.n 10001dc2 <_ftoa+0x3c2> +10001db8: 2b20 cmp r3, #32 +10001dba: f805 2f01 strb.w r2, [r5, #1]! +10001dbe: f43f aedf beq.w 10001b80 <_ftoa+0x180> +10001dc2: 429e cmp r6, r3 +10001dc4: f103 0301 add.w r3, r3, #1 +10001dc8: d1f6 bne.n 10001db8 <_ftoa+0x3b8> +10001dca: 222e movs r2, #46 @ 0x2e +10001dcc: eb0d 0306 add.w r3, sp, r6 +10001dd0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001dd4: 1c75 adds r5, r6, #1 +10001dd6: e6d4 b.n 10001b82 <_ftoa+0x182> +10001dd8: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001ddc: e763 b.n 10001ca6 <_ftoa+0x2a6> +10001dde: 2520 movs r5, #32 +10001de0: e66e b.n 10001ac0 <_ftoa+0xc0> +10001de2: 9b07 ldr r3, [sp, #28] +10001de4: f013 0f0c tst.w r3, #12 +10001de8: d050 beq.n 10001e8c <_ftoa+0x48c> +10001dea: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001dee: 45ab cmp fp, r5 +10001df0: f63f aef2 bhi.w 10001bd8 <_ftoa+0x1d8> +10001df4: 2d20 cmp r5, #32 +10001df6: f43f aefc beq.w 10001bf2 <_ftoa+0x1f2> +10001dfa: 9b07 ldr r3, [sp, #28] +10001dfc: 075a lsls r2, r3, #29 +10001dfe: d501 bpl.n 10001e04 <_ftoa+0x404> +10001e00: 222b movs r2, #43 @ 0x2b +10001e02: e7cb b.n 10001d9c <_ftoa+0x39c> +10001e04: 071b lsls r3, r3, #28 +10001e06: f57f aef4 bpl.w 10001bf2 <_ftoa+0x1f2> +10001e0a: 2220 movs r2, #32 +10001e0c: e7c6 b.n 10001d9c <_ftoa+0x39c> +10001e0e: f01a 0f01 tst.w sl, #1 +10001e12: f43f ae96 beq.w 10001b42 <_ftoa+0x142> +10001e16: e78f b.n 10001d38 <_ftoa+0x338> +10001e18: 07a6 lsls r6, r4, #30 +10001e1a: d134 bne.n 10001e86 <_ftoa+0x486> +10001e1c: f1bb 0f03 cmp.w fp, #3 +10001e20: d931 bls.n 10001e86 <_ftoa+0x486> +10001e22: 9b0c ldr r3, [sp, #48] @ 0x30 +10001e24: 461d mov r5, r3 +10001e26: 1edc subs r4, r3, #3 +10001e28: eb04 0a0b add.w sl, r4, fp +10001e2c: 462a mov r2, r5 +10001e2e: 464b mov r3, r9 +10001e30: 4641 mov r1, r8 +10001e32: 2020 movs r0, #32 +10001e34: 3501 adds r5, #1 +10001e36: 47b8 blx r7 +10001e38: 4555 cmp r5, sl +10001e3a: d1f7 bne.n 10001e2c <_ftoa+0x42c> +10001e3c: 4655 mov r5, sl +10001e3e: 4c1e ldr r4, [pc, #120] @ (10001eb8 <_ftoa+0x4b8>) +10001e40: 1ee6 subs r6, r4, #3 +10001e42: f814 0d01 ldrb.w r0, [r4, #-1]! +10001e46: 462a mov r2, r5 +10001e48: 464b mov r3, r9 +10001e4a: 4641 mov r1, r8 +10001e4c: 47b8 blx r7 +10001e4e: 42a6 cmp r6, r4 +10001e50: f105 0501 add.w r5, r5, #1 +10001e54: d1f5 bne.n 10001e42 <_ftoa+0x442> +10001e56: 9b07 ldr r3, [sp, #28] +10001e58: f10a 0a03 add.w sl, sl, #3 +10001e5c: 079d lsls r5, r3, #30 +10001e5e: f57f aed5 bpl.w 10001c0c <_ftoa+0x20c> +10001e62: 9c0c ldr r4, [sp, #48] @ 0x30 +10001e64: ebaa 0304 sub.w r3, sl, r4 +10001e68: 459b cmp fp, r3 +10001e6a: f67f aecf bls.w 10001c0c <_ftoa+0x20c> +10001e6e: 4652 mov r2, sl +10001e70: 464b mov r3, r9 +10001e72: 4641 mov r1, r8 +10001e74: 2020 movs r0, #32 +10001e76: f10a 0a01 add.w sl, sl, #1 +10001e7a: 47b8 blx r7 +10001e7c: ebaa 0304 sub.w r3, sl, r4 +10001e80: 459b cmp fp, r3 +10001e82: d8f4 bhi.n 10001e6e <_ftoa+0x46e> +10001e84: e6c2 b.n 10001c0c <_ftoa+0x20c> +10001e86: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001e8a: e7d7 b.n 10001e3c <_ftoa+0x43c> +10001e8c: 45ab cmp fp, r5 +10001e8e: f63f aea3 bhi.w 10001bd8 <_ftoa+0x1d8> +10001e92: e6ae b.n 10001bf2 <_ftoa+0x1f2> +10001e94: f1bb 0f00 cmp.w fp, #0 +10001e98: f43f af7a beq.w 10001d90 <_ftoa+0x390> +10001e9c: 9b0d ldr r3, [sp, #52] @ 0x34 +10001e9e: 2b00 cmp r3, #0 +10001ea0: d09f beq.n 10001de2 <_ftoa+0x3e2> +10001ea2: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001ea6: 455d cmp r5, fp +10001ea8: f4ff ae96 bcc.w 10001bd8 <_ftoa+0x1d8> +10001eac: 2d20 cmp r5, #32 +10001eae: f47f af74 bne.w 10001d9a <_ftoa+0x39a> +10001eb2: e69e b.n 10001bf2 <_ftoa+0x1f2> +10001eb4: 3fe00000 .word 0x3fe00000 +10001eb8: 100036d3 .word 0x100036d3 +10001ebc: 00000000 .word 0x00000000 + +10001ec0 <_etoa>: +10001ec0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ec4: b09f sub sp, #124 @ 0x7c +10001ec6: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001ec8: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001ecc: 4607 mov r7, r0 +10001ece: 4693 mov fp, r2 +10001ed0: 9108 str r1, [sp, #32] +10001ed2: 9309 str r3, [sp, #36] @ 0x24 +10001ed4: 4622 mov r2, r4 +10001ed6: 462b mov r3, r5 +10001ed8: 4620 mov r0, r4 +10001eda: 4629 mov r1, r5 +10001edc: 960e str r6, [sp, #56] @ 0x38 +10001ede: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001ee2: f7ff fbeb bl 100016bc <__wrap___aeabi_dcmpun> +10001ee6: 2800 cmp r0, #0 +10001ee8: f040 80be bne.w 10002068 <_etoa+0x1a8> +10001eec: 4620 mov r0, r4 +10001eee: 4629 mov r1, r5 +10001ef0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001ef4: 4b78 ldr r3, [pc, #480] @ (100020d8 <_etoa+0x218>) +10001ef6: f7ff fc2f bl 10001758 <__wrap___aeabi_dcmpgt> +10001efa: 2800 cmp r0, #0 +10001efc: f040 80b4 bne.w 10002068 <_etoa+0x1a8> +10001f00: 4620 mov r0, r4 +10001f02: 4629 mov r1, r5 +10001f04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001f08: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001f0c: f7ff fbe8 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f10: 2800 cmp r0, #0 +10001f12: f040 80a9 bne.w 10002068 <_etoa+0x1a8> +10001f16: 4620 mov r0, r4 +10001f18: 4629 mov r1, r5 +10001f1a: 2200 movs r2, #0 +10001f1c: 2300 movs r3, #0 +10001f1e: f7ff fbdf bl 100016e0 <__wrap___aeabi_dcmplt> +10001f22: 2800 cmp r0, #0 +10001f24: f040 81d5 bne.w 100022d2 <_etoa+0x412> +10001f28: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001f2c: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001f30: 4690 mov r8, r2 +10001f32: 4699 mov r9, r3 +10001f34: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001f38: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001f3c: 920f str r2, [sp, #60] @ 0x3c +10001f3e: 9313 str r3, [sp, #76] @ 0x4c +10001f40: f040 80a1 bne.w 10002086 <_etoa+0x1c6> +10001f44: ea58 0309 orrs.w r3, r8, r9 +10001f48: f040 80ca bne.w 100020e0 <_etoa+0x220> +10001f4c: 2a00 cmp r2, #0 +10001f4e: f040 81e3 bne.w 10002318 <_etoa+0x458> +10001f52: 2306 movs r3, #6 +10001f54: 930e str r3, [sp, #56] @ 0x38 +10001f56: f016 0202 ands.w r2, r6, #2 +10001f5a: 9210 str r2, [sp, #64] @ 0x40 +10001f5c: f040 81d4 bne.w 10002308 <_etoa+0x448> +10001f60: 4653 mov r3, sl +10001f62: 2b04 cmp r3, #4 +10001f64: bf38 it cc +10001f66: 2304 movcc r3, #4 +10001f68: 920c str r2, [sp, #48] @ 0x30 +10001f6a: 2204 movs r2, #4 +10001f6c: 3b04 subs r3, #4 +10001f6e: 9212 str r2, [sp, #72] @ 0x48 +10001f70: 930f str r3, [sp, #60] @ 0x3c +10001f72: 4620 mov r0, r4 +10001f74: 4629 mov r1, r5 +10001f76: 2200 movs r2, #0 +10001f78: 2300 movs r3, #0 +10001f7a: f7ff fbb1 bl 100016e0 <__wrap___aeabi_dcmplt> +10001f7e: 2800 cmp r0, #0 +10001f80: f040 81f3 bne.w 1000236a <_etoa+0x4aa> +10001f84: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001f88: 9b0f ldr r3, [sp, #60] @ 0x3c +10001f8a: 465a mov r2, fp +10001f8c: 9303 str r3, [sp, #12] +10001f8e: 9b0e ldr r3, [sp, #56] @ 0x38 +10001f90: ed8d 7b00 vstr d7, [sp] +10001f94: 9302 str r3, [sp, #8] +10001f96: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001f9a: 9304 str r3, [sp, #16] +10001f9c: 4638 mov r0, r7 +10001f9e: 9b09 ldr r3, [sp, #36] @ 0x24 +10001fa0: 9908 ldr r1, [sp, #32] +10001fa2: f7ff fd2d bl 10001a00 <_ftoa> +10001fa6: 4602 mov r2, r0 +10001fa8: f016 0f20 tst.w r6, #32 +10001fac: 9b09 ldr r3, [sp, #36] @ 0x24 +10001fae: 9908 ldr r1, [sp, #32] +10001fb0: bf0c ite eq +10001fb2: 2065 moveq r0, #101 @ 0x65 +10001fb4: 2045 movne r0, #69 @ 0x45 +10001fb6: f102 0801 add.w r8, r2, #1 +10001fba: 47b8 blx r7 +10001fbc: 9a0c ldr r2, [sp, #48] @ 0x30 +10001fbe: 9b12 ldr r3, [sp, #72] @ 0x48 +10001fc0: ac16 add r4, sp, #88 @ 0x58 +10001fc2: 1e5d subs r5, r3, #1 +10001fc4: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001fc8: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001fcc: 0fd1 lsrs r1, r2, #31 +10001fce: 2600 movs r6, #0 +10001fd0: 4622 mov r2, r4 +10001fd2: 4699 mov r9, r3 +10001fd4: f8df c104 ldr.w ip, [pc, #260] @ 100020dc <_etoa+0x21c> +10001fd8: e001 b.n 10001fde <_etoa+0x11e> +10001fda: 2e20 cmp r6, #32 +10001fdc: d010 beq.n 10002000 <_etoa+0x140> +10001fde: 46ce mov lr, r9 +10001fe0: fbac 3009 umull r3, r0, ip, r9 +10001fe4: 08c0 lsrs r0, r0, #3 +10001fe6: eb00 0380 add.w r3, r0, r0, lsl #2 +10001fea: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001fee: 3330 adds r3, #48 @ 0x30 +10001ff0: f1be 0f09 cmp.w lr, #9 +10001ff4: 4681 mov r9, r0 +10001ff6: f106 0601 add.w r6, r6, #1 +10001ffa: f802 3b01 strb.w r3, [r2], #1 +10001ffe: d8ec bhi.n 10001fda <_etoa+0x11a> +10002000: 2305 movs r3, #5 +10002002: 2000 movs r0, #0 +10002004: 9306 str r3, [sp, #24] +10002006: 230a movs r3, #10 +10002008: 9505 str r5, [sp, #20] +1000200a: 9400 str r4, [sp, #0] +1000200c: 9d09 ldr r5, [sp, #36] @ 0x24 +1000200e: 9c08 ldr r4, [sp, #32] +10002010: 4642 mov r2, r8 +10002012: e9cd 3003 strd r3, r0, [sp, #12] +10002016: e9cd 6101 strd r6, r1, [sp, #4] +1000201a: 462b mov r3, r5 +1000201c: 4621 mov r1, r4 +1000201e: 4638 mov r0, r7 +10002020: f7ff fbfa bl 10001818 <_ntoa_format> +10002024: 9a10 ldr r2, [sp, #64] @ 0x40 +10002026: 4680 mov r8, r0 +10002028: b1d2 cbz r2, 10002060 <_etoa+0x1a0> +1000202a: eba0 060b sub.w r6, r0, fp +1000202e: 45b2 cmp sl, r6 +10002030: d916 bls.n 10002060 <_etoa+0x1a0> +10002032: eb0b 0206 add.w r2, fp, r6 +10002036: 462b mov r3, r5 +10002038: 4621 mov r1, r4 +1000203a: 2020 movs r0, #32 +1000203c: 3601 adds r6, #1 +1000203e: 47b8 blx r7 +10002040: 45b2 cmp sl, r6 +10002042: d8f6 bhi.n 10002032 <_etoa+0x172> +10002044: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002048: 4453 add r3, sl +1000204a: f1cb 0201 rsb r2, fp, #1 +1000204e: eba3 0308 sub.w r3, r3, r8 +10002052: 4442 add r2, r8 +10002054: 4592 cmp sl, r2 +10002056: bf38 it cc +10002058: 2300 movcc r3, #0 +1000205a: f108 0801 add.w r8, r8, #1 +1000205e: 4498 add r8, r3 +10002060: 4640 mov r0, r8 +10002062: b01f add sp, #124 @ 0x7c +10002064: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002068: 465a mov r2, fp +1000206a: 4638 mov r0, r7 +1000206c: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002070: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10002074: 9c0e ldr r4, [sp, #56] @ 0x38 +10002076: 9b09 ldr r3, [sp, #36] @ 0x24 +10002078: 9908 ldr r1, [sp, #32] +1000207a: 942a str r4, [sp, #168] @ 0xa8 +1000207c: b01f add sp, #124 @ 0x7c +1000207e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002082: f7ff bcbd b.w 10001a00 <_ftoa> +10002086: ea58 0309 orrs.w r3, r8, r9 +1000208a: d12b bne.n 100020e4 <_etoa+0x224> +1000208c: 2a00 cmp r2, #0 +1000208e: f43f af62 beq.w 10001f56 <_etoa+0x96> +10002092: 2300 movs r3, #0 +10002094: 930c str r3, [sp, #48] @ 0x30 +10002096: 9b0e ldr r3, [sp, #56] @ 0x38 +10002098: 9a0c ldr r2, [sp, #48] @ 0x30 +1000209a: 4293 cmp r3, r2 +1000209c: f300 81b9 bgt.w 10002412 <_etoa+0x552> +100020a0: f04f 0800 mov.w r8, #0 +100020a4: 4620 mov r0, r4 +100020a6: 4629 mov r1, r5 +100020a8: 2200 movs r2, #0 +100020aa: 2300 movs r3, #0 +100020ac: f7ff fb18 bl 100016e0 <__wrap___aeabi_dcmplt> +100020b0: 2800 cmp r0, #0 +100020b2: f040 8113 bne.w 100022dc <_etoa+0x41c> +100020b6: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +100020ba: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100020be: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100020c2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100020c6: 465a mov r2, fp +100020c8: 4638 mov r0, r7 +100020ca: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100020ce: 9b09 ldr r3, [sp, #36] @ 0x24 +100020d0: 9908 ldr r1, [sp, #32] +100020d2: 962c str r6, [sp, #176] @ 0xb0 +100020d4: e7d2 b.n 1000207c <_etoa+0x1bc> +100020d6: bf00 nop +100020d8: 7fefffff .word 0x7fefffff +100020dc: cccccccd .word 0xcccccccd +100020e0: 2306 movs r3, #6 +100020e2: 930e str r3, [sp, #56] @ 0x38 +100020e4: f3c9 500a ubfx r0, r9, #20, #11 +100020e8: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100020ec: f7ff fa9e bl 1000162c <__wrap___aeabi_i2d> +100020f0: a3c1 add r3, pc, #772 @ (adr r3, 100023f8 <_etoa+0x538>) +100020f2: e9d3 2300 ldrd r2, r3, [r3] +100020f6: f7ff fa25 bl 10001544 <__wrap___aeabi_dmul> +100020fa: a3c1 add r3, pc, #772 @ (adr r3, 10002400 <_etoa+0x540>) +100020fc: e9d3 2300 ldrd r2, r3, [r3] +10002100: f7ff f9f8 bl 100014f4 <__wrap___aeabi_dadd> +10002104: f3c9 0913 ubfx r9, r9, #0, #20 +10002108: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +1000210c: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002110: 4640 mov r0, r8 +10002112: 2200 movs r2, #0 +10002114: 4bb2 ldr r3, [pc, #712] @ (100023e0 <_etoa+0x520>) +10002116: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +1000211a: f7ff f9ff bl 1000151c <__wrap___aeabi_dsub> +1000211e: a3a4 add r3, pc, #656 @ (adr r3, 100023b0 <_etoa+0x4f0>) +10002120: e9d3 2300 ldrd r2, r3, [r3] +10002124: f7ff fa0e bl 10001544 <__wrap___aeabi_dmul> +10002128: 4602 mov r2, r0 +1000212a: 460b mov r3, r1 +1000212c: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002130: f7ff f9e0 bl 100014f4 <__wrap___aeabi_dadd> +10002134: f7ff fa9e bl 10001674 <__wrap___aeabi_d2iz> +10002138: 900c str r0, [sp, #48] @ 0x30 +1000213a: f7ff fa77 bl 1000162c <__wrap___aeabi_i2d> +1000213e: a39e add r3, pc, #632 @ (adr r3, 100023b8 <_etoa+0x4f8>) +10002140: e9d3 2300 ldrd r2, r3, [r3] +10002144: 4680 mov r8, r0 +10002146: 4689 mov r9, r1 +10002148: f7ff f9fc bl 10001544 <__wrap___aeabi_dmul> +1000214c: 2200 movs r2, #0 +1000214e: 4ba5 ldr r3, [pc, #660] @ (100023e4 <_etoa+0x524>) +10002150: f7ff f9d0 bl 100014f4 <__wrap___aeabi_dadd> +10002154: f7ff fa8e bl 10001674 <__wrap___aeabi_d2iz> +10002158: 4603 mov r3, r0 +1000215a: 4649 mov r1, r9 +1000215c: 4640 mov r0, r8 +1000215e: 9312 str r3, [sp, #72] @ 0x48 +10002160: a397 add r3, pc, #604 @ (adr r3, 100023c0 <_etoa+0x500>) +10002162: e9d3 2300 ldrd r2, r3, [r3] +10002166: f7ff f9ed bl 10001544 <__wrap___aeabi_dmul> +1000216a: 4680 mov r8, r0 +1000216c: 9812 ldr r0, [sp, #72] @ 0x48 +1000216e: 4689 mov r9, r1 +10002170: f7ff fa5c bl 1000162c <__wrap___aeabi_i2d> +10002174: a394 add r3, pc, #592 @ (adr r3, 100023c8 <_etoa+0x508>) +10002176: e9d3 2300 ldrd r2, r3, [r3] +1000217a: f7ff f9e3 bl 10001544 <__wrap___aeabi_dmul> +1000217e: 4602 mov r2, r0 +10002180: 460b mov r3, r1 +10002182: 4640 mov r0, r8 +10002184: 4649 mov r1, r9 +10002186: f7ff f9c9 bl 1000151c <__wrap___aeabi_dsub> +1000218a: 4602 mov r2, r0 +1000218c: 460b mov r3, r1 +1000218e: 4680 mov r8, r0 +10002190: 4689 mov r9, r1 +10002192: f7ff f9d7 bl 10001544 <__wrap___aeabi_dmul> +10002196: 4642 mov r2, r8 +10002198: 464b mov r3, r9 +1000219a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +1000219e: 4640 mov r0, r8 +100021a0: 4649 mov r1, r9 +100021a2: f7ff f9a7 bl 100014f4 <__wrap___aeabi_dadd> +100021a6: 2200 movs r2, #0 +100021a8: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +100021ac: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021b0: 4b8d ldr r3, [pc, #564] @ (100023e8 <_etoa+0x528>) +100021b2: f7ff f9ed bl 10001590 <__wrap___aeabi_ddiv> +100021b6: 2200 movs r2, #0 +100021b8: 4b8c ldr r3, [pc, #560] @ (100023ec <_etoa+0x52c>) +100021ba: f7ff f99b bl 100014f4 <__wrap___aeabi_dadd> +100021be: 4602 mov r2, r0 +100021c0: 460b mov r3, r1 +100021c2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021c6: f7ff f9e3 bl 10001590 <__wrap___aeabi_ddiv> +100021ca: 2200 movs r2, #0 +100021cc: 4b88 ldr r3, [pc, #544] @ (100023f0 <_etoa+0x530>) +100021ce: f7ff f991 bl 100014f4 <__wrap___aeabi_dadd> +100021d2: 4602 mov r2, r0 +100021d4: 460b mov r3, r1 +100021d6: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100021da: f7ff f9d9 bl 10001590 <__wrap___aeabi_ddiv> +100021de: 4642 mov r2, r8 +100021e0: 464b mov r3, r9 +100021e2: 4680 mov r8, r0 +100021e4: 4689 mov r9, r1 +100021e6: 2000 movs r0, #0 +100021e8: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100021ec: f7ff f996 bl 1000151c <__wrap___aeabi_dsub> +100021f0: 4602 mov r2, r0 +100021f2: 460b mov r3, r1 +100021f4: 4640 mov r0, r8 +100021f6: 4649 mov r1, r9 +100021f8: f7ff f97c bl 100014f4 <__wrap___aeabi_dadd> +100021fc: 4602 mov r2, r0 +100021fe: 460b mov r3, r1 +10002200: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +10002204: f7ff f9c4 bl 10001590 <__wrap___aeabi_ddiv> +10002208: 2200 movs r2, #0 +1000220a: 4b7a ldr r3, [pc, #488] @ (100023f4 <_etoa+0x534>) +1000220c: f7ff f972 bl 100014f4 <__wrap___aeabi_dadd> +10002210: 9b12 ldr r3, [sp, #72] @ 0x48 +10002212: 2200 movs r2, #0 +10002214: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002218: ea4f 530c mov.w r3, ip, lsl #20 +1000221c: f7ff f992 bl 10001544 <__wrap___aeabi_dmul> +10002220: 4680 mov r8, r0 +10002222: 4689 mov r9, r1 +10002224: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002228: 4642 mov r2, r8 +1000222a: 464b mov r3, r9 +1000222c: f7ff fa58 bl 100016e0 <__wrap___aeabi_dcmplt> +10002230: b150 cbz r0, 10002248 <_etoa+0x388> +10002232: 9b0c ldr r3, [sp, #48] @ 0x30 +10002234: 4640 mov r0, r8 +10002236: 3b01 subs r3, #1 +10002238: 4649 mov r1, r9 +1000223a: 930c str r3, [sp, #48] @ 0x30 +1000223c: 2200 movs r2, #0 +1000223e: 4b6b ldr r3, [pc, #428] @ (100023ec <_etoa+0x52c>) +10002240: f7ff f9a6 bl 10001590 <__wrap___aeabi_ddiv> +10002244: 4680 mov r8, r0 +10002246: 4689 mov r9, r1 +10002248: 9a0c ldr r2, [sp, #48] @ 0x30 +1000224a: 4643 mov r3, r8 +1000224c: 3263 adds r2, #99 @ 0x63 +1000224e: 2ac6 cmp r2, #198 @ 0xc6 +10002250: f006 0202 and.w r2, r6, #2 +10002254: 9210 str r2, [sp, #64] @ 0x40 +10002256: 4649 mov r1, r9 +10002258: 9a0f ldr r2, [sp, #60] @ 0x3c +1000225a: d82c bhi.n 100022b6 <_etoa+0x3f6> +1000225c: 2a00 cmp r2, #0 +1000225e: d05e beq.n 1000231e <_etoa+0x45e> +10002260: 2204 movs r2, #4 +10002262: 9212 str r2, [sp, #72] @ 0x48 +10002264: 430b orrs r3, r1 +10002266: f43f af16 beq.w 10002096 <_etoa+0x1d6> +1000226a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000226e: a358 add r3, pc, #352 @ (adr r3, 100023d0 <_etoa+0x510>) +10002270: e9d3 2300 ldrd r2, r3, [r3] +10002274: f7ff fa5c bl 10001730 <__wrap___aeabi_dcmpge> +10002278: b148 cbz r0, 1000228e <_etoa+0x3ce> +1000227a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000227e: a356 add r3, pc, #344 @ (adr r3, 100023d8 <_etoa+0x518>) +10002280: e9d3 2300 ldrd r2, r3, [r3] +10002284: f7ff fa2c bl 100016e0 <__wrap___aeabi_dcmplt> +10002288: 2800 cmp r0, #0 +1000228a: f47f af04 bne.w 10002096 <_etoa+0x1d6> +1000228e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002290: 2b00 cmp r3, #0 +10002292: d050 beq.n 10002336 <_etoa+0x476> +10002294: 9a13 ldr r2, [sp, #76] @ 0x4c +10002296: 2a00 cmp r2, #0 +10002298: d07d beq.n 10002396 <_etoa+0x4d6> +1000229a: 3b01 subs r3, #1 +1000229c: 930e str r3, [sp, #56] @ 0x38 +1000229e: 9b12 ldr r3, [sp, #72] @ 0x48 +100022a0: 459a cmp sl, r3 +100022a2: d905 bls.n 100022b0 <_etoa+0x3f0> +100022a4: 9b10 ldr r3, [sp, #64] @ 0x40 +100022a6: 2b00 cmp r3, #0 +100022a8: f000 80ae beq.w 10002408 <_etoa+0x548> +100022ac: 2302 movs r3, #2 +100022ae: 9310 str r3, [sp, #64] @ 0x40 +100022b0: 2300 movs r3, #0 +100022b2: 930f str r3, [sp, #60] @ 0x3c +100022b4: e044 b.n 10002340 <_etoa+0x480> +100022b6: bb22 cbnz r2, 10002302 <_etoa+0x442> +100022b8: f1ba 0f05 cmp.w sl, #5 +100022bc: d94f bls.n 1000235e <_etoa+0x49e> +100022be: f006 0302 and.w r3, r6, #2 +100022c2: 2b00 cmp r3, #0 +100022c4: d149 bne.n 1000235a <_etoa+0x49a> +100022c6: 2305 movs r3, #5 +100022c8: 9312 str r3, [sp, #72] @ 0x48 +100022ca: f1aa 0305 sub.w r3, sl, #5 +100022ce: 930f str r3, [sp, #60] @ 0x3c +100022d0: e03a b.n 10002348 <_etoa+0x488> +100022d2: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +100022d6: 940a str r4, [sp, #40] @ 0x28 +100022d8: 930b str r3, [sp, #44] @ 0x2c +100022da: e627 b.n 10001f2c <_etoa+0x6c> +100022dc: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100022e0: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100022e4: 4638 mov r0, r7 +100022e6: 962c str r6, [sp, #176] @ 0xb0 +100022e8: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +100022ec: 4634 mov r4, r6 +100022ee: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100022f2: 465a mov r2, fp +100022f4: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100022f8: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100022fc: 9b09 ldr r3, [sp, #36] @ 0x24 +100022fe: 9908 ldr r1, [sp, #32] +10002300: e6bc b.n 1000207c <_etoa+0x1bc> +10002302: 2205 movs r2, #5 +10002304: 9212 str r2, [sp, #72] @ 0x48 +10002306: e7ad b.n 10002264 <_etoa+0x3a4> +10002308: 2300 movs r3, #0 +1000230a: 2202 movs r2, #2 +1000230c: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002310: 2204 movs r2, #4 +10002312: 930c str r3, [sp, #48] @ 0x30 +10002314: 9212 str r2, [sp, #72] @ 0x48 +10002316: e62c b.n 10001f72 <_etoa+0xb2> +10002318: f04f 0805 mov.w r8, #5 +1000231c: e6c2 b.n 100020a4 <_etoa+0x1e4> +1000231e: f1ba 0f04 cmp.w sl, #4 +10002322: d91f bls.n 10002364 <_etoa+0x4a4> +10002324: 9b10 ldr r3, [sp, #64] @ 0x40 +10002326: 2b00 cmp r3, #0 +10002328: d178 bne.n 1000241c <_etoa+0x55c> +1000232a: 2304 movs r3, #4 +1000232c: 9312 str r3, [sp, #72] @ 0x48 +1000232e: f1aa 0304 sub.w r3, sl, #4 +10002332: 930f str r3, [sp, #60] @ 0x3c +10002334: e004 b.n 10002340 <_etoa+0x480> +10002336: 9b12 ldr r3, [sp, #72] @ 0x48 +10002338: 459a cmp sl, r3 +1000233a: d831 bhi.n 100023a0 <_etoa+0x4e0> +1000233c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000233e: 930f str r3, [sp, #60] @ 0x3c +10002340: 9b0c ldr r3, [sp, #48] @ 0x30 +10002342: 2b00 cmp r3, #0 +10002344: f43f ae15 beq.w 10001f72 <_etoa+0xb2> +10002348: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000234c: 4642 mov r2, r8 +1000234e: 464b mov r3, r9 +10002350: f7ff f91e bl 10001590 <__wrap___aeabi_ddiv> +10002354: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10002358: e60b b.n 10001f72 <_etoa+0xb2> +1000235a: 2302 movs r3, #2 +1000235c: 9310 str r3, [sp, #64] @ 0x40 +1000235e: 2305 movs r3, #5 +10002360: 9312 str r3, [sp, #72] @ 0x48 +10002362: e7f1 b.n 10002348 <_etoa+0x488> +10002364: 2304 movs r3, #4 +10002366: 9312 str r3, [sp, #72] @ 0x48 +10002368: e7ea b.n 10002340 <_etoa+0x480> +1000236a: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +1000236e: 46a0 mov r8, r4 +10002370: 9b0f ldr r3, [sp, #60] @ 0x3c +10002372: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +10002376: 9303 str r3, [sp, #12] +10002378: 9b0e ldr r3, [sp, #56] @ 0x38 +1000237a: 465a mov r2, fp +1000237c: 9302 str r3, [sp, #8] +1000237e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002382: 9304 str r3, [sp, #16] +10002384: 4638 mov r0, r7 +10002386: e9cd 8900 strd r8, r9, [sp] +1000238a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000238c: 9908 ldr r1, [sp, #32] +1000238e: f7ff fb37 bl 10001a00 <_ftoa> +10002392: 4602 mov r2, r0 +10002394: e608 b.n 10001fa8 <_etoa+0xe8> +10002396: 9b12 ldr r3, [sp, #72] @ 0x48 +10002398: 459a cmp sl, r3 +1000239a: d844 bhi.n 10002426 <_etoa+0x566> +1000239c: 920f str r2, [sp, #60] @ 0x3c +1000239e: e7cf b.n 10002340 <_etoa+0x480> +100023a0: 9b10 ldr r3, [sp, #64] @ 0x40 +100023a2: b38b cbz r3, 10002408 <_etoa+0x548> +100023a4: 9b0e ldr r3, [sp, #56] @ 0x38 +100023a6: 930f str r3, [sp, #60] @ 0x3c +100023a8: 2302 movs r3, #2 +100023aa: 9310 str r3, [sp, #64] @ 0x40 +100023ac: e7c8 b.n 10002340 <_etoa+0x480> +100023ae: bf00 nop +100023b0: 636f4361 .word 0x636f4361 +100023b4: 3fd287a7 .word 0x3fd287a7 +100023b8: 0979a371 .word 0x0979a371 +100023bc: 400a934f .word 0x400a934f +100023c0: bbb55516 .word 0xbbb55516 +100023c4: 40026bb1 .word 0x40026bb1 +100023c8: fefa39ef .word 0xfefa39ef +100023cc: 3fe62e42 .word 0x3fe62e42 +100023d0: eb1c432d .word 0xeb1c432d +100023d4: 3f1a36e2 .word 0x3f1a36e2 +100023d8: 00000000 .word 0x00000000 +100023dc: 412e8480 .word 0x412e8480 +100023e0: 3ff80000 .word 0x3ff80000 +100023e4: 3fe00000 .word 0x3fe00000 +100023e8: 402c0000 .word 0x402c0000 +100023ec: 40240000 .word 0x40240000 +100023f0: 40180000 .word 0x40180000 +100023f4: 3ff00000 .word 0x3ff00000 +100023f8: 509f79fb .word 0x509f79fb +100023fc: 3fd34413 .word 0x3fd34413 +10002400: 8b60c8b3 .word 0x8b60c8b3 +10002404: 3fc68a28 .word 0x3fc68a28 +10002408: 9b12 ldr r3, [sp, #72] @ 0x48 +1000240a: ebaa 0303 sub.w r3, sl, r3 +1000240e: 930f str r3, [sp, #60] @ 0x3c +10002410: e796 b.n 10002340 <_etoa+0x480> +10002412: eba3 0802 sub.w r8, r3, r2 +10002416: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +1000241a: e643 b.n 100020a4 <_etoa+0x1e4> +1000241c: 2304 movs r3, #4 +1000241e: 9312 str r3, [sp, #72] @ 0x48 +10002420: 2302 movs r3, #2 +10002422: 9310 str r3, [sp, #64] @ 0x40 +10002424: e78c b.n 10002340 <_etoa+0x480> +10002426: 9b10 ldr r3, [sp, #64] @ 0x40 +10002428: 2b00 cmp r3, #0 +1000242a: d0ed beq.n 10002408 <_etoa+0x548> +1000242c: 2302 movs r3, #2 +1000242e: 920f str r2, [sp, #60] @ 0x3c +10002430: 9310 str r3, [sp, #64] @ 0x40 +10002432: e785 b.n 10002340 <_etoa+0x480> + +10002434 <_vsnprintf>: +10002434: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002438: b09b sub sp, #108 @ 0x6c +1000243a: 9c24 ldr r4, [sp, #144] @ 0x90 +1000243c: 4d95 ldr r5, [pc, #596] @ (10002694 <_vsnprintf+0x260>) +1000243e: 940a str r4, [sp, #40] @ 0x28 +10002440: 4c95 ldr r4, [pc, #596] @ (10002698 <_vsnprintf+0x264>) +10002442: f1b1 0a00 subs.w sl, r1, #0 +10002446: bf18 it ne +10002448: 4683 movne fp, r0 +1000244a: 6025 str r5, [r4, #0] +1000244c: 7818 ldrb r0, [r3, #0] +1000244e: 4c93 ldr r4, [pc, #588] @ (1000269c <_vsnprintf+0x268>) +10002450: 4691 mov r9, r2 +10002452: bf08 it eq +10002454: 46a3 moveq fp, r4 +10002456: 9309 str r3, [sp, #36] @ 0x24 +10002458: 2800 cmp r0, #0 +1000245a: f000 8293 beq.w 10002984 <_vsnprintf+0x550> +1000245e: f04f 0800 mov.w r8, #0 +10002462: e00a b.n 1000247a <_vsnprintf+0x46> +10002464: 4642 mov r2, r8 +10002466: 464b mov r3, r9 +10002468: 4651 mov r1, sl +1000246a: f108 0801 add.w r8, r8, #1 +1000246e: 47d8 blx fp +10002470: 9b09 ldr r3, [sp, #36] @ 0x24 +10002472: 7818 ldrb r0, [r3, #0] +10002474: 2800 cmp r0, #0 +10002476: f000 80ce beq.w 10002616 <_vsnprintf+0x1e2> +1000247a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000247c: 2825 cmp r0, #37 @ 0x25 +1000247e: f103 0301 add.w r3, r3, #1 +10002482: 9309 str r3, [sp, #36] @ 0x24 +10002484: d1ee bne.n 10002464 <_vsnprintf+0x30> +10002486: 461c mov r4, r3 +10002488: 2300 movs r3, #0 +1000248a: 4622 mov r2, r4 +1000248c: f812 0b01 ldrb.w r0, [r2], #1 +10002490: f1a0 0120 sub.w r1, r0, #32 +10002494: 2910 cmp r1, #16 +10002496: d80a bhi.n 100024ae <_vsnprintf+0x7a> +10002498: e8df f001 tbb [pc, r1] +1000249c: 3c090940 .word 0x3c090940 +100024a0: 09090909 .word 0x09090909 +100024a4: 38090909 .word 0x38090909 +100024a8: 09093409 .word 0x09093409 +100024ac: 30 .byte 0x30 +100024ad: 00 .byte 0x00 +100024ae: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100024b2: 2909 cmp r1, #9 +100024b4: 9409 str r4, [sp, #36] @ 0x24 +100024b6: f240 808a bls.w 100025ce <_vsnprintf+0x19a> +100024ba: 282a cmp r0, #42 @ 0x2a +100024bc: f000 80f0 beq.w 100026a0 <_vsnprintf+0x26c> +100024c0: 2500 movs r5, #0 +100024c2: 282e cmp r0, #46 @ 0x2e +100024c4: f000 8096 beq.w 100025f4 <_vsnprintf+0x1c0> +100024c8: 2600 movs r6, #0 +100024ca: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +100024ce: 2912 cmp r1, #18 +100024d0: d82d bhi.n 1000252e <_vsnprintf+0xfa> +100024d2: e8df f011 tbh [pc, r1, lsl #1] +100024d6: 0149 .short 0x0149 +100024d8: 0143002c .word 0x0143002c +100024dc: 0138002c .word 0x0138002c +100024e0: 002c002c .word 0x002c002c +100024e4: 002c002c .word 0x002c002c +100024e8: 002c002c .word 0x002c002c +100024ec: 0027002c .word 0x0027002c +100024f0: 002c002c .word 0x002c002c +100024f4: 002c002c .word 0x002c002c +100024f8: 0027002c .word 0x0027002c +100024fc: 4614 mov r4, r2 +100024fe: f043 0301 orr.w r3, r3, #1 +10002502: e7c2 b.n 1000248a <_vsnprintf+0x56> +10002504: 4614 mov r4, r2 +10002506: f043 0302 orr.w r3, r3, #2 +1000250a: e7be b.n 1000248a <_vsnprintf+0x56> +1000250c: 4614 mov r4, r2 +1000250e: f043 0304 orr.w r3, r3, #4 +10002512: e7ba b.n 1000248a <_vsnprintf+0x56> +10002514: 4614 mov r4, r2 +10002516: f043 0310 orr.w r3, r3, #16 +1000251a: e7b6 b.n 1000248a <_vsnprintf+0x56> +1000251c: 4614 mov r4, r2 +1000251e: f043 0308 orr.w r3, r3, #8 +10002522: e7b2 b.n 1000248a <_vsnprintf+0x56> +10002524: 9909 ldr r1, [sp, #36] @ 0x24 +10002526: 7848 ldrb r0, [r1, #1] +10002528: f443 7380 orr.w r3, r3, #256 @ 0x100 +1000252c: 3201 adds r2, #1 +1000252e: 2867 cmp r0, #103 @ 0x67 +10002530: 9209 str r2, [sp, #36] @ 0x24 +10002532: d87e bhi.n 10002632 <_vsnprintf+0x1fe> +10002534: 2824 cmp r0, #36 @ 0x24 +10002536: f240 80c1 bls.w 100026bc <_vsnprintf+0x288> +1000253a: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +1000253e: 2a42 cmp r2, #66 @ 0x42 +10002540: f200 80bc bhi.w 100026bc <_vsnprintf+0x288> +10002544: e8df f012 tbh [pc, r2, lsl #1] +10002548: 00ba0150 .word 0x00ba0150 +1000254c: 00ba00ba .word 0x00ba00ba +10002550: 00ba00ba .word 0x00ba00ba +10002554: 00ba00ba .word 0x00ba00ba +10002558: 00ba00ba .word 0x00ba00ba +1000255c: 00ba00ba .word 0x00ba00ba +10002560: 00ba00ba .word 0x00ba00ba +10002564: 00ba00ba .word 0x00ba00ba +10002568: 00ba00ba .word 0x00ba00ba +1000256c: 00ba00ba .word 0x00ba00ba +10002570: 00ba00ba .word 0x00ba00ba +10002574: 00ba00ba .word 0x00ba00ba +10002578: 00ba00ba .word 0x00ba00ba +1000257c: 00ba00ba .word 0x00ba00ba +10002580: 00ba00ba .word 0x00ba00ba +10002584: 00ba00ba .word 0x00ba00ba +10002588: 01370119 .word 0x01370119 +1000258c: 00ba0119 .word 0x00ba0119 +10002590: 00ba00ba .word 0x00ba00ba +10002594: 00ba00ba .word 0x00ba00ba +10002598: 00ba00ba .word 0x00ba00ba +1000259c: 00ba00ba .word 0x00ba00ba +100025a0: 00ba00ba .word 0x00ba00ba +100025a4: 00ba00ba .word 0x00ba00ba +100025a8: 00ba00ba .word 0x00ba00ba +100025ac: 01bc00ba .word 0x01bc00ba +100025b0: 00ba00ba .word 0x00ba00ba +100025b4: 00ba00ba .word 0x00ba00ba +100025b8: 00ba00ba .word 0x00ba00ba +100025bc: 00ba00ba .word 0x00ba00ba +100025c0: 01bc00ba .word 0x01bc00ba +100025c4: 01bc0158 .word 0x01bc0158 +100025c8: 01370119 .word 0x01370119 +100025cc: 0119 .short 0x0119 +100025ce: 2500 movs r5, #0 +100025d0: e000 b.n 100025d4 <_vsnprintf+0x1a0> +100025d2: 3201 adds r2, #1 +100025d4: eb05 0585 add.w r5, r5, r5, lsl #2 +100025d8: eb00 0545 add.w r5, r0, r5, lsl #1 +100025dc: 7810 ldrb r0, [r2, #0] +100025de: 3d30 subs r5, #48 @ 0x30 +100025e0: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100025e4: 2909 cmp r1, #9 +100025e6: d9f4 bls.n 100025d2 <_vsnprintf+0x19e> +100025e8: 282e cmp r0, #46 @ 0x2e +100025ea: 9209 str r2, [sp, #36] @ 0x24 +100025ec: f102 0201 add.w r2, r2, #1 +100025f0: f47f af6a bne.w 100024c8 <_vsnprintf+0x94> +100025f4: 9909 ldr r1, [sp, #36] @ 0x24 +100025f6: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100025fa: 7848 ldrb r0, [r1, #1] +100025fc: 4611 mov r1, r2 +100025fe: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002602: 2e09 cmp r6, #9 +10002604: f240 8121 bls.w 1000284a <_vsnprintf+0x416> +10002608: 282a cmp r0, #42 @ 0x2a +1000260a: f000 812f beq.w 1000286c <_vsnprintf+0x438> +1000260e: 9209 str r2, [sp, #36] @ 0x24 +10002610: 2600 movs r6, #0 +10002612: 3201 adds r2, #1 +10002614: e759 b.n 100024ca <_vsnprintf+0x96> +10002616: 4644 mov r4, r8 +10002618: 45c1 cmp r9, r8 +1000261a: d801 bhi.n 10002620 <_vsnprintf+0x1ec> +1000261c: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002620: 464b mov r3, r9 +10002622: 4642 mov r2, r8 +10002624: 4651 mov r1, sl +10002626: 2000 movs r0, #0 +10002628: 47d8 blx fp +1000262a: 4620 mov r0, r4 +1000262c: b01b add sp, #108 @ 0x6c +1000262e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002632: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +10002636: b2d2 uxtb r2, r2 +10002638: 2a0f cmp r2, #15 +1000263a: d83f bhi.n 100026bc <_vsnprintf+0x288> +1000263c: 2101 movs r1, #1 +1000263e: f249 0741 movw r7, #36929 @ 0x9041 +10002642: 4091 lsls r1, r2 +10002644: 4039 ands r1, r7 +10002646: f040 80f3 bne.w 10002830 <_vsnprintf+0x3fc> +1000264a: 2a0a cmp r2, #10 +1000264c: d03d beq.n 100026ca <_vsnprintf+0x296> +1000264e: 2a07 cmp r2, #7 +10002650: d134 bne.n 100026bc <_vsnprintf+0x288> +10002652: 9d0a ldr r5, [sp, #40] @ 0x28 +10002654: f855 2b04 ldr.w r2, [r5], #4 +10002658: 2a00 cmp r2, #0 +1000265a: f000 8113 beq.w 10002884 <_vsnprintf+0x450> +1000265e: f043 0021 orr.w r0, r3, #33 @ 0x21 +10002662: ab12 add r3, sp, #72 @ 0x48 +10002664: 461f mov r7, r3 +10002666: 930b str r3, [sp, #44] @ 0x2c +10002668: e003 b.n 10002672 <_vsnprintf+0x23e> +1000266a: 2920 cmp r1, #32 +1000266c: f000 8114 beq.w 10002898 <_vsnprintf+0x464> +10002670: 461a mov r2, r3 +10002672: f002 040f and.w r4, r2, #15 +10002676: 4623 mov r3, r4 +10002678: 2c09 cmp r4, #9 +1000267a: bf94 ite ls +1000267c: 3330 addls r3, #48 @ 0x30 +1000267e: 3337 addhi r3, #55 @ 0x37 +10002680: 2a0f cmp r2, #15 +10002682: f807 3b01 strb.w r3, [r7], #1 +10002686: f101 0101 add.w r1, r1, #1 +1000268a: ea4f 1312 mov.w r3, r2, lsr #4 +1000268e: d8ec bhi.n 1000266a <_vsnprintf+0x236> +10002690: e102 b.n 10002898 <_vsnprintf+0x464> +10002692: bf00 nop +10002694: 10002435 .word 0x10002435 +10002698: 2000080c .word 0x2000080c +1000269c: 10001779 .word 0x10001779 +100026a0: 990a ldr r1, [sp, #40] @ 0x28 +100026a2: 9809 ldr r0, [sp, #36] @ 0x24 +100026a4: f851 5b04 ldr.w r5, [r1], #4 +100026a8: 7840 ldrb r0, [r0, #1] +100026aa: 2d00 cmp r5, #0 +100026ac: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +100026b0: bfbc itt lt +100026b2: f043 0302 orrlt.w r3, r3, #2 +100026b6: 426d neglt r5, r5 +100026b8: 3201 adds r2, #1 +100026ba: e702 b.n 100024c2 <_vsnprintf+0x8e> +100026bc: 4642 mov r2, r8 +100026be: 464b mov r3, r9 +100026c0: 4651 mov r1, sl +100026c2: f108 0801 add.w r8, r8, #1 +100026c6: 47d8 blx fp +100026c8: e6d2 b.n 10002470 <_vsnprintf+0x3c> +100026ca: 990a ldr r1, [sp, #40] @ 0x28 +100026cc: 2e00 cmp r6, #0 +100026ce: f851 7b04 ldr.w r7, [r1], #4 +100026d2: bf18 it ne +100026d4: 4632 movne r2, r6 +100026d6: 7838 ldrb r0, [r7, #0] +100026d8: bf08 it eq +100026da: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +100026de: 2800 cmp r0, #0 +100026e0: f000 837b beq.w 10002dda <_vsnprintf+0x9a6> +100026e4: 18bc adds r4, r7, r2 +100026e6: 46a4 mov ip, r4 +100026e8: 463a mov r2, r7 +100026ea: e004 b.n 100026f6 <_vsnprintf+0x2c2> +100026ec: f812 4f01 ldrb.w r4, [r2, #1]! +100026f0: 2c00 cmp r4, #0 +100026f2: f000 813f beq.w 10002974 <_vsnprintf+0x540> +100026f6: 4594 cmp ip, r2 +100026f8: d1f8 bne.n 100026ec <_vsnprintf+0x2b8> +100026fa: 4664 mov r4, ip +100026fc: 1be4 subs r4, r4, r7 +100026fe: 055a lsls r2, r3, #21 +10002700: f140 8122 bpl.w 10002948 <_vsnprintf+0x514> +10002704: 42b4 cmp r4, r6 +10002706: bf28 it cs +10002708: 4634 movcs r4, r6 +1000270a: f013 0302 ands.w r3, r3, #2 +1000270e: f000 8288 beq.w 10002c22 <_vsnprintf+0x7ee> +10002712: 2302 movs r3, #2 +10002714: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002718: 4642 mov r2, r8 +1000271a: 461d mov r5, r3 +1000271c: 4446 add r6, r8 +1000271e: e008 b.n 10002732 <_vsnprintf+0x2fe> +10002720: 464b mov r3, r9 +10002722: 4651 mov r1, sl +10002724: 47d8 blx fp +10002726: f817 0f01 ldrb.w r0, [r7, #1]! +1000272a: f108 0801 add.w r8, r8, #1 +1000272e: b110 cbz r0, 10002736 <_vsnprintf+0x302> +10002730: 4642 mov r2, r8 +10002732: 4546 cmp r6, r8 +10002734: d1f4 bne.n 10002720 <_vsnprintf+0x2ec> +10002736: 462b mov r3, r5 +10002738: 990b ldr r1, [sp, #44] @ 0x2c +1000273a: 9d0a ldr r5, [sp, #40] @ 0x28 +1000273c: 2b00 cmp r3, #0 +1000273e: f040 8141 bne.w 100029c4 <_vsnprintf+0x590> +10002742: 910a str r1, [sp, #40] @ 0x28 +10002744: e694 b.n 10002470 <_vsnprintf+0x3c> +10002746: 9909 ldr r1, [sp, #36] @ 0x24 +10002748: 7848 ldrb r0, [r1, #1] +1000274a: 286c cmp r0, #108 @ 0x6c +1000274c: f47f aeec bne.w 10002528 <_vsnprintf+0xf4> +10002750: 460a mov r2, r1 +10002752: 7888 ldrb r0, [r1, #2] +10002754: f443 7340 orr.w r3, r3, #768 @ 0x300 +10002758: 3203 adds r2, #3 +1000275a: e6e8 b.n 1000252e <_vsnprintf+0xfa> +1000275c: 9909 ldr r1, [sp, #36] @ 0x24 +1000275e: f443 7300 orr.w r3, r3, #512 @ 0x200 +10002762: 7848 ldrb r0, [r1, #1] +10002764: 3201 adds r2, #1 +10002766: e6e2 b.n 1000252e <_vsnprintf+0xfa> +10002768: 9909 ldr r1, [sp, #36] @ 0x24 +1000276a: 7848 ldrb r0, [r1, #1] +1000276c: 2868 cmp r0, #104 @ 0x68 +1000276e: f000 8103 beq.w 10002978 <_vsnprintf+0x544> +10002772: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002776: 3201 adds r2, #1 +10002778: e6d9 b.n 1000252e <_vsnprintf+0xfa> +1000277a: 2867 cmp r0, #103 @ 0x67 +1000277c: f000 80d9 beq.w 10002932 <_vsnprintf+0x4fe> +10002780: 2847 cmp r0, #71 @ 0x47 +10002782: f000 80dc beq.w 1000293e <_vsnprintf+0x50a> +10002786: 2845 cmp r0, #69 @ 0x45 +10002788: f000 80db beq.w 10002942 <_vsnprintf+0x50e> +1000278c: e9cd 5303 strd r5, r3, [sp, #12] +10002790: 9b0a ldr r3, [sp, #40] @ 0x28 +10002792: 9602 str r6, [sp, #8] +10002794: 3307 adds r3, #7 +10002796: f023 0307 bic.w r3, r3, #7 +1000279a: 461c mov r4, r3 +1000279c: 4642 mov r2, r8 +1000279e: e8f4 6702 ldrd r6, r7, [r4], #8 +100027a2: 464b mov r3, r9 +100027a4: 4651 mov r1, sl +100027a6: 4658 mov r0, fp +100027a8: e9cd 6700 strd r6, r7, [sp] +100027ac: 940a str r4, [sp, #40] @ 0x28 +100027ae: f7ff fb87 bl 10001ec0 <_etoa> +100027b2: 4680 mov r8, r0 +100027b4: e65c b.n 10002470 <_vsnprintf+0x3c> +100027b6: 2846 cmp r0, #70 @ 0x46 +100027b8: bf08 it eq +100027ba: f043 0320 orreq.w r3, r3, #32 +100027be: e9cd 5303 strd r5, r3, [sp, #12] +100027c2: 9b0a ldr r3, [sp, #40] @ 0x28 +100027c4: 9602 str r6, [sp, #8] +100027c6: 3307 adds r3, #7 +100027c8: f023 0307 bic.w r3, r3, #7 +100027cc: 461c mov r4, r3 +100027ce: 4642 mov r2, r8 +100027d0: e8f4 6702 ldrd r6, r7, [r4], #8 +100027d4: 464b mov r3, r9 +100027d6: 4651 mov r1, sl +100027d8: 4658 mov r0, fp +100027da: e9cd 6700 strd r6, r7, [sp] +100027de: 940a str r4, [sp, #40] @ 0x28 +100027e0: f7ff f90e bl 10001a00 <_ftoa> +100027e4: 4680 mov r8, r0 +100027e6: e643 b.n 10002470 <_vsnprintf+0x3c> +100027e8: 4642 mov r2, r8 +100027ea: 464b mov r3, r9 +100027ec: 4651 mov r1, sl +100027ee: 2025 movs r0, #37 @ 0x25 +100027f0: f108 0801 add.w r8, r8, #1 +100027f4: 47d8 blx fp +100027f6: e63b b.n 10002470 <_vsnprintf+0x3c> +100027f8: 9a0a ldr r2, [sp, #40] @ 0x28 +100027fa: 0799 lsls r1, r3, #30 +100027fc: f102 0404 add.w r4, r2, #4 +10002800: f108 0601 add.w r6, r8, #1 +10002804: f140 80c6 bpl.w 10002994 <_vsnprintf+0x560> +10002808: 7810 ldrb r0, [r2, #0] +1000280a: 464b mov r3, r9 +1000280c: 4642 mov r2, r8 +1000280e: 4651 mov r1, sl +10002810: 47d8 blx fp +10002812: 2d01 cmp r5, #1 +10002814: bf88 it hi +10002816: 44a8 addhi r8, r5 +10002818: f240 81bd bls.w 10002b96 <_vsnprintf+0x762> +1000281c: 4632 mov r2, r6 +1000281e: 464b mov r3, r9 +10002820: 4651 mov r1, sl +10002822: 2020 movs r0, #32 +10002824: 3601 adds r6, #1 +10002826: 47d8 blx fp +10002828: 4546 cmp r6, r8 +1000282a: d1f7 bne.n 1000281c <_vsnprintf+0x3e8> +1000282c: 940a str r4, [sp, #40] @ 0x28 +1000282e: e61f b.n 10002470 <_vsnprintf+0x3c> +10002830: 286f cmp r0, #111 @ 0x6f +10002832: f000 8081 beq.w 10002938 <_vsnprintf+0x504> +10002836: f240 8248 bls.w 10002cca <_vsnprintf+0x896> +1000283a: 2878 cmp r0, #120 @ 0x78 +1000283c: f000 8190 beq.w 10002b60 <_vsnprintf+0x72c> +10002840: 270a movs r7, #10 +10002842: f023 0310 bic.w r3, r3, #16 +10002846: 46bc mov ip, r7 +10002848: e041 b.n 100028ce <_vsnprintf+0x49a> +1000284a: 2600 movs r6, #0 +1000284c: eb06 0686 add.w r6, r6, r6, lsl #2 +10002850: eb00 0046 add.w r0, r0, r6, lsl #1 +10002854: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002858: f811 0f01 ldrb.w r0, [r1, #1]! +1000285c: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002860: 2a09 cmp r2, #9 +10002862: d9f3 bls.n 1000284c <_vsnprintf+0x418> +10002864: 460a mov r2, r1 +10002866: 9109 str r1, [sp, #36] @ 0x24 +10002868: 3201 adds r2, #1 +1000286a: e62e b.n 100024ca <_vsnprintf+0x96> +1000286c: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002870: f851 6b04 ldr.w r6, [r1], #4 +10002874: 7890 ldrb r0, [r2, #2] +10002876: 3202 adds r2, #2 +10002878: 9209 str r2, [sp, #36] @ 0x24 +1000287a: 910a str r1, [sp, #40] @ 0x28 +1000287c: 3201 adds r2, #1 +1000287e: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002882: e622 b.n 100024ca <_vsnprintf+0x96> +10002884: f023 0010 bic.w r0, r3, #16 +10002888: f413 6280 ands.w r2, r3, #1024 @ 0x400 +1000288c: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002890: f43f aee7 beq.w 10002662 <_vsnprintf+0x22e> +10002894: ab12 add r3, sp, #72 @ 0x48 +10002896: 930b str r3, [sp, #44] @ 0x2c +10002898: 9b0b ldr r3, [sp, #44] @ 0x2c +1000289a: 9006 str r0, [sp, #24] +1000289c: 9300 str r3, [sp, #0] +1000289e: 2308 movs r3, #8 +100028a0: 2010 movs r0, #16 +100028a2: 9305 str r3, [sp, #20] +100028a4: 2300 movs r3, #0 +100028a6: 4642 mov r2, r8 +100028a8: e9cd 3002 strd r3, r0, [sp, #8] +100028ac: 9101 str r1, [sp, #4] +100028ae: 464b mov r3, r9 +100028b0: 4651 mov r1, sl +100028b2: 4658 mov r0, fp +100028b4: 9604 str r6, [sp, #16] +100028b6: f7fe ffaf bl 10001818 <_ntoa_format> +100028ba: 950a str r5, [sp, #40] @ 0x28 +100028bc: 4680 mov r8, r0 +100028be: e5d7 b.n 10002470 <_vsnprintf+0x3c> +100028c0: 2858 cmp r0, #88 @ 0x58 +100028c2: d062 beq.n 1000298a <_vsnprintf+0x556> +100028c4: 2862 cmp r0, #98 @ 0x62 +100028c6: f040 808f bne.w 100029e8 <_vsnprintf+0x5b4> +100028ca: 2702 movs r7, #2 +100028cc: 46bc mov ip, r7 +100028ce: f413 6080 ands.w r0, r3, #1024 @ 0x400 +100028d2: f000 80dd beq.w 10002a90 <_vsnprintf+0x65c> +100028d6: f023 030d bic.w r3, r3, #13 +100028da: f413 7200 ands.w r2, r3, #512 @ 0x200 +100028de: f040 8181 bne.w 10002be4 <_vsnprintf+0x7b0> +100028e2: 990a ldr r1, [sp, #40] @ 0x28 +100028e4: 1d0f adds r7, r1, #4 +100028e6: f413 7180 ands.w r1, r3, #256 @ 0x100 +100028ea: f040 8237 bne.w 10002d5c <_vsnprintf+0x928> +100028ee: 065c lsls r4, r3, #25 +100028f0: 9a0a ldr r2, [sp, #40] @ 0x28 +100028f2: f140 813b bpl.w 10002b6c <_vsnprintf+0x738> +100028f6: 7812 ldrb r2, [r2, #0] +100028f8: 2a00 cmp r2, #0 +100028fa: f040 814e bne.w 10002b9a <_vsnprintf+0x766> +100028fe: f023 0310 bic.w r3, r3, #16 +10002902: 2800 cmp r0, #0 +10002904: f000 8149 beq.w 10002b9a <_vsnprintf+0x766> +10002908: 4611 mov r1, r2 +1000290a: aa12 add r2, sp, #72 @ 0x48 +1000290c: 920b str r2, [sp, #44] @ 0x2c +1000290e: e9cd 5305 strd r5, r3, [sp, #20] +10002912: e9cd c603 strd ip, r6, [sp, #12] +10002916: 9101 str r1, [sp, #4] +10002918: 9b0b ldr r3, [sp, #44] @ 0x2c +1000291a: 4642 mov r2, r8 +1000291c: 9300 str r3, [sp, #0] +1000291e: 2300 movs r3, #0 +10002920: 4651 mov r1, sl +10002922: 9302 str r3, [sp, #8] +10002924: 4658 mov r0, fp +10002926: 464b mov r3, r9 +10002928: f7fe ff76 bl 10001818 <_ntoa_format> +1000292c: 970a str r7, [sp, #40] @ 0x28 +1000292e: 4680 mov r8, r0 +10002930: e59e b.n 10002470 <_vsnprintf+0x3c> +10002932: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002936: e729 b.n 1000278c <_vsnprintf+0x358> +10002938: 2708 movs r7, #8 +1000293a: 46bc mov ip, r7 +1000293c: e7c7 b.n 100028ce <_vsnprintf+0x49a> +1000293e: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002942: f043 0320 orr.w r3, r3, #32 +10002946: e721 b.n 1000278c <_vsnprintf+0x358> +10002948: f013 0302 ands.w r3, r3, #2 +1000294c: f000 818e beq.w 10002c6c <_vsnprintf+0x838> +10002950: 2302 movs r3, #2 +10002952: 950a str r5, [sp, #40] @ 0x28 +10002954: 461e mov r6, r3 +10002956: 460d mov r5, r1 +10002958: 4642 mov r2, r8 +1000295a: 464b mov r3, r9 +1000295c: 4651 mov r1, sl +1000295e: 47d8 blx fp +10002960: f817 0f01 ldrb.w r0, [r7, #1]! +10002964: f108 0801 add.w r8, r8, #1 +10002968: 2800 cmp r0, #0 +1000296a: d1f5 bne.n 10002958 <_vsnprintf+0x524> +1000296c: 4629 mov r1, r5 +1000296e: 4633 mov r3, r6 +10002970: 9d0a ldr r5, [sp, #40] @ 0x28 +10002972: e6e3 b.n 1000273c <_vsnprintf+0x308> +10002974: 1bd4 subs r4, r2, r7 +10002976: e6c2 b.n 100026fe <_vsnprintf+0x2ca> +10002978: 460a mov r2, r1 +1000297a: 7888 ldrb r0, [r1, #2] +1000297c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002980: 3203 adds r2, #3 +10002982: e5d4 b.n 1000252e <_vsnprintf+0xfa> +10002984: 4604 mov r4, r0 +10002986: 4680 mov r8, r0 +10002988: e646 b.n 10002618 <_vsnprintf+0x1e4> +1000298a: 2710 movs r7, #16 +1000298c: f043 0320 orr.w r3, r3, #32 +10002990: 46bc mov ip, r7 +10002992: e79c b.n 100028ce <_vsnprintf+0x49a> +10002994: 2d01 cmp r5, #1 +10002996: f240 80f8 bls.w 10002b8a <_vsnprintf+0x756> +1000299a: 4646 mov r6, r8 +1000299c: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +100029a0: 442f add r7, r5 +100029a2: 4632 mov r2, r6 +100029a4: 464b mov r3, r9 +100029a6: 4651 mov r1, sl +100029a8: 2020 movs r0, #32 +100029aa: 3601 adds r6, #1 +100029ac: 47d8 blx fp +100029ae: 42be cmp r6, r7 +100029b0: d1f7 bne.n 100029a2 <_vsnprintf+0x56e> +100029b2: 9b0a ldr r3, [sp, #40] @ 0x28 +100029b4: 4632 mov r2, r6 +100029b6: 7818 ldrb r0, [r3, #0] +100029b8: 4651 mov r1, sl +100029ba: 464b mov r3, r9 +100029bc: 47d8 blx fp +100029be: 44a8 add r8, r5 +100029c0: 940a str r4, [sp, #40] @ 0x28 +100029c2: e555 b.n 10002470 <_vsnprintf+0x3c> +100029c4: 4646 mov r6, r8 +100029c6: 42a5 cmp r5, r4 +100029c8: f67f aebb bls.w 10002742 <_vsnprintf+0x30e> +100029cc: 44a8 add r8, r5 +100029ce: eba8 0804 sub.w r8, r8, r4 +100029d2: 460c mov r4, r1 +100029d4: 4632 mov r2, r6 +100029d6: 464b mov r3, r9 +100029d8: 4651 mov r1, sl +100029da: 2020 movs r0, #32 +100029dc: 3601 adds r6, #1 +100029de: 47d8 blx fp +100029e0: 4546 cmp r6, r8 +100029e2: d1f7 bne.n 100029d4 <_vsnprintf+0x5a0> +100029e4: 4621 mov r1, r4 +100029e6: e6ac b.n 10002742 <_vsnprintf+0x30e> +100029e8: f413 6280 ands.w r2, r3, #1024 @ 0x400 +100029ec: f000 80bb beq.w 10002b66 <_vsnprintf+0x732> +100029f0: f44f 6280 mov.w r2, #1024 @ 0x400 +100029f4: f023 0c11 bic.w ip, r3, #17 +100029f8: f41c 7700 ands.w r7, ip, #512 @ 0x200 +100029fc: 9b0a ldr r3, [sp, #40] @ 0x28 +100029fe: d14a bne.n 10002a96 <_vsnprintf+0x662> +10002a00: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002a04: f103 0404 add.w r4, r3, #4 +10002a08: f040 8134 bne.w 10002c74 <_vsnprintf+0x840> +10002a0c: f01c 0f40 tst.w ip, #64 @ 0x40 +10002a10: f040 80a3 bne.w 10002b5a <_vsnprintf+0x726> +10002a14: f01c 0f80 tst.w ip, #128 @ 0x80 +10002a18: f000 81d3 beq.w 10002dc2 <_vsnprintf+0x98e> +10002a1c: f9b3 1000 ldrsh.w r1, [r3] +10002a20: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002a24: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002a28: b2bf uxth r7, r7 +10002a2a: 0fcb lsrs r3, r1, #31 +10002a2c: 2900 cmp r1, #0 +10002a2e: f000 8156 beq.w 10002cde <_vsnprintf+0x8aa> +10002a32: 463a mov r2, r7 +10002a34: a912 add r1, sp, #72 @ 0x48 +10002a36: 460f mov r7, r1 +10002a38: f8df e3d8 ldr.w lr, [pc, #984] @ 10002e14 <_vsnprintf+0x9e0> +10002a3c: 910b str r1, [sp, #44] @ 0x2c +10002a3e: 930a str r3, [sp, #40] @ 0x28 +10002a40: 950c str r5, [sp, #48] @ 0x30 +10002a42: e001 b.n 10002a48 <_vsnprintf+0x614> +10002a44: 2820 cmp r0, #32 +10002a46: d00f beq.n 10002a68 <_vsnprintf+0x634> +10002a48: 4615 mov r5, r2 +10002a4a: fbae 1302 umull r1, r3, lr, r2 +10002a4e: 08db lsrs r3, r3, #3 +10002a50: eb03 0183 add.w r1, r3, r3, lsl #2 +10002a54: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002a58: 3130 adds r1, #48 @ 0x30 +10002a5a: 2d09 cmp r5, #9 +10002a5c: 461a mov r2, r3 +10002a5e: f100 0001 add.w r0, r0, #1 +10002a62: f807 1b01 strb.w r1, [r7], #1 +10002a66: d8ed bhi.n 10002a44 <_vsnprintf+0x610> +10002a68: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a6a: 9d0c ldr r5, [sp, #48] @ 0x30 +10002a6c: e9cd 5c05 strd r5, ip, [sp, #20] +10002a70: e9cd 0301 strd r0, r3, [sp, #4] +10002a74: 9604 str r6, [sp, #16] +10002a76: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a78: 4642 mov r2, r8 +10002a7a: 9300 str r3, [sp, #0] +10002a7c: 230a movs r3, #10 +10002a7e: 4651 mov r1, sl +10002a80: 9303 str r3, [sp, #12] +10002a82: 4658 mov r0, fp +10002a84: 464b mov r3, r9 +10002a86: f7fe fec7 bl 10001818 <_ntoa_format> +10002a8a: 940a str r4, [sp, #40] @ 0x28 +10002a8c: 4680 mov r8, r0 +10002a8e: e4ef b.n 10002470 <_vsnprintf+0x3c> +10002a90: f023 030c bic.w r3, r3, #12 +10002a94: e721 b.n 100028da <_vsnprintf+0x4a6> +10002a96: 3307 adds r3, #7 +10002a98: f023 0307 bic.w r3, r3, #7 +10002a9c: 4619 mov r1, r3 +10002a9e: 4608 mov r0, r1 +10002aa0: 685b ldr r3, [r3, #4] +10002aa2: f850 1b08 ldr.w r1, [r0], #8 +10002aa6: 0fdf lsrs r7, r3, #31 +10002aa8: 900a str r0, [sp, #40] @ 0x28 +10002aaa: ea51 0003 orrs.w r0, r1, r3 +10002aae: d162 bne.n 10002b76 <_vsnprintf+0x742> +10002ab0: 2a00 cmp r2, #0 +10002ab2: f040 819f bne.w 10002df4 <_vsnprintf+0x9c0> +10002ab6: 4613 mov r3, r2 +10002ab8: 4611 mov r1, r2 +10002aba: aa12 add r2, sp, #72 @ 0x48 +10002abc: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002ac0: 2000 movs r0, #0 +10002ac2: 4615 mov r5, r2 +10002ac4: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002ac8: f8df e348 ldr.w lr, [pc, #840] @ 10002e14 <_vsnprintf+0x9e0> +10002acc: 920b str r2, [sp, #44] @ 0x2c +10002ace: e001 b.n 10002ad4 <_vsnprintf+0x6a0> +10002ad0: 2820 cmp r0, #32 +10002ad2: d02d beq.n 10002b30 <_vsnprintf+0x6fc> +10002ad4: 185a adds r2, r3, r1 +10002ad6: f142 0200 adc.w r2, r2, #0 +10002ada: fbae 7802 umull r7, r8, lr, r2 +10002ade: f028 0703 bic.w r7, r8, #3 +10002ae2: eb07 0798 add.w r7, r7, r8, lsr #2 +10002ae6: 1bd2 subs r2, r2, r7 +10002ae8: 461e mov r6, r3 +10002aea: 1a9b subs r3, r3, r2 +10002aec: f161 0700 sbc.w r7, r1, #0 +10002af0: 460c mov r4, r1 +10002af2: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002af6: fb01 f103 mul.w r1, r1, r3 +10002afa: fb0e 1107 mla r1, lr, r7, r1 +10002afe: fba3 730e umull r7, r3, r3, lr +10002b02: 4419 add r1, r3 +10002b04: 2305 movs r3, #5 +10002b06: f007 0801 and.w r8, r7, #1 +10002b0a: fba8 3803 umull r3, r8, r8, r3 +10002b0e: 189b adds r3, r3, r2 +10002b10: 2e0a cmp r6, #10 +10002b12: f103 0330 add.w r3, r3, #48 @ 0x30 +10002b16: ea4f 0757 mov.w r7, r7, lsr #1 +10002b1a: f174 0400 sbcs.w r4, r4, #0 +10002b1e: f805 3b01 strb.w r3, [r5], #1 +10002b22: f100 0001 add.w r0, r0, #1 +10002b26: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002b2a: ea4f 0151 mov.w r1, r1, lsr #1 +10002b2e: d2cf bcs.n 10002ad0 <_vsnprintf+0x69c> +10002b30: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002b34: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002b38: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b3a: 4642 mov r2, r8 +10002b3c: 9300 str r3, [sp, #0] +10002b3e: 230a movs r3, #10 +10002b40: e9cd 5c05 strd r5, ip, [sp, #20] +10002b44: e9cd 0701 strd r0, r7, [sp, #4] +10002b48: 9604 str r6, [sp, #16] +10002b4a: 9303 str r3, [sp, #12] +10002b4c: 464b mov r3, r9 +10002b4e: 4651 mov r1, sl +10002b50: 4658 mov r0, fp +10002b52: f7fe fe61 bl 10001818 <_ntoa_format> +10002b56: 4680 mov r8, r0 +10002b58: e48a b.n 10002470 <_vsnprintf+0x3c> +10002b5a: 7819 ldrb r1, [r3, #0] +10002b5c: 460f mov r7, r1 +10002b5e: e764 b.n 10002a2a <_vsnprintf+0x5f6> +10002b60: 2710 movs r7, #16 +10002b62: 46bc mov ip, r7 +10002b64: e6b3 b.n 100028ce <_vsnprintf+0x49a> +10002b66: f023 0c10 bic.w ip, r3, #16 +10002b6a: e745 b.n 100029f8 <_vsnprintf+0x5c4> +10002b6c: 061c lsls r4, r3, #24 +10002b6e: bf4c ite mi +10002b70: 8812 ldrhmi r2, [r2, #0] +10002b72: 6812 ldrpl r2, [r2, #0] +10002b74: e6c0 b.n 100028f8 <_vsnprintf+0x4c4> +10002b76: 460a mov r2, r1 +10002b78: 1e19 subs r1, r3, #0 +10002b7a: db01 blt.n 10002b80 <_vsnprintf+0x74c> +10002b7c: 4613 mov r3, r2 +10002b7e: e79c b.n 10002aba <_vsnprintf+0x686> +10002b80: 4252 negs r2, r2 +10002b82: 4613 mov r3, r2 +10002b84: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002b88: e797 b.n 10002aba <_vsnprintf+0x686> +10002b8a: 4613 mov r3, r2 +10002b8c: 4651 mov r1, sl +10002b8e: 7818 ldrb r0, [r3, #0] +10002b90: 4642 mov r2, r8 +10002b92: 464b mov r3, r9 +10002b94: 47d8 blx fp +10002b96: 46b0 mov r8, r6 +10002b98: e648 b.n 1000282c <_vsnprintf+0x3f8> +10002b9a: f013 0f20 tst.w r3, #32 +10002b9e: bf14 ite ne +10002ba0: 2041 movne r0, #65 @ 0x41 +10002ba2: 2061 moveq r0, #97 @ 0x61 +10002ba4: ac12 add r4, sp, #72 @ 0x48 +10002ba6: 46a6 mov lr, r4 +10002ba8: 940b str r4, [sp, #44] @ 0x2c +10002baa: 930a str r3, [sp, #40] @ 0x28 +10002bac: f1a0 040a sub.w r4, r0, #10 +10002bb0: 950c str r5, [sp, #48] @ 0x30 +10002bb2: e002 b.n 10002bba <_vsnprintf+0x786> +10002bb4: 2920 cmp r1, #32 +10002bb6: d012 beq.n 10002bde <_vsnprintf+0x7aa> +10002bb8: 462a mov r2, r5 +10002bba: fbb2 f5fc udiv r5, r2, ip +10002bbe: fb0c 2015 mls r0, ip, r5, r2 +10002bc2: b2c3 uxtb r3, r0 +10002bc4: 2809 cmp r0, #9 +10002bc6: f103 0030 add.w r0, r3, #48 @ 0x30 +10002bca: bf8a itet hi +10002bcc: 191b addhi r3, r3, r4 +10002bce: b2c3 uxtbls r3, r0 +10002bd0: b2db uxtbhi r3, r3 +10002bd2: 4562 cmp r2, ip +10002bd4: f80e 3b01 strb.w r3, [lr], #1 +10002bd8: f101 0101 add.w r1, r1, #1 +10002bdc: d2ea bcs.n 10002bb4 <_vsnprintf+0x780> +10002bde: 9b0a ldr r3, [sp, #40] @ 0x28 +10002be0: 9d0c ldr r5, [sp, #48] @ 0x30 +10002be2: e694 b.n 1000290e <_vsnprintf+0x4da> +10002be4: 9a0a ldr r2, [sp, #40] @ 0x28 +10002be6: 3207 adds r2, #7 +10002be8: f022 0207 bic.w r2, r2, #7 +10002bec: 6851 ldr r1, [r2, #4] +10002bee: f852 4b08 ldr.w r4, [r2], #8 +10002bf2: 468e mov lr, r1 +10002bf4: 920a str r2, [sp, #40] @ 0x28 +10002bf6: ea54 0201 orrs.w r2, r4, r1 +10002bfa: d176 bne.n 10002cea <_vsnprintf+0x8b6> +10002bfc: f023 0310 bic.w r3, r3, #16 +10002c00: 2800 cmp r0, #0 +10002c02: d072 beq.n 10002cea <_vsnprintf+0x8b6> +10002c04: 2200 movs r2, #0 +10002c06: 4611 mov r1, r2 +10002c08: aa12 add r2, sp, #72 @ 0x48 +10002c0a: 920b str r2, [sp, #44] @ 0x2c +10002c0c: e9cd 5305 strd r5, r3, [sp, #20] +10002c10: 9b0b ldr r3, [sp, #44] @ 0x2c +10002c12: 4642 mov r2, r8 +10002c14: 9300 str r3, [sp, #0] +10002c16: 2300 movs r3, #0 +10002c18: e9cd c603 strd ip, r6, [sp, #12] +10002c1c: 9101 str r1, [sp, #4] +10002c1e: 9302 str r3, [sp, #8] +10002c20: e794 b.n 10002b4c <_vsnprintf+0x718> +10002c22: 42a5 cmp r5, r4 +10002c24: bf98 it ls +10002c26: 3401 addls r4, #1 +10002c28: f67f ad74 bls.w 10002714 <_vsnprintf+0x2e0> +10002c2c: f44f 6380 mov.w r3, #1024 @ 0x400 +10002c30: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002c34: eb05 0208 add.w r2, r5, r8 +10002c38: 461f mov r7, r3 +10002c3a: 460d mov r5, r1 +10002c3c: 1b14 subs r4, r2, r4 +10002c3e: 4642 mov r2, r8 +10002c40: 464b mov r3, r9 +10002c42: 4651 mov r1, sl +10002c44: 2020 movs r0, #32 +10002c46: f108 0801 add.w r8, r8, #1 +10002c4a: 47d8 blx fp +10002c4c: 45a0 cmp r8, r4 +10002c4e: d1f6 bne.n 10002c3e <_vsnprintf+0x80a> +10002c50: 463b mov r3, r7 +10002c52: 9f0a ldr r7, [sp, #40] @ 0x28 +10002c54: 4629 mov r1, r5 +10002c56: 7838 ldrb r0, [r7, #0] +10002c58: 9d0b ldr r5, [sp, #44] @ 0x2c +10002c5a: 1c6c adds r4, r5, #1 +10002c5c: 2800 cmp r0, #0 +10002c5e: f43f ad70 beq.w 10002742 <_vsnprintf+0x30e> +10002c62: 2b00 cmp r3, #0 +10002c64: f43f ae75 beq.w 10002952 <_vsnprintf+0x51e> +10002c68: 2300 movs r3, #0 +10002c6a: e553 b.n 10002714 <_vsnprintf+0x2e0> +10002c6c: 42a5 cmp r5, r4 +10002c6e: d8df bhi.n 10002c30 <_vsnprintf+0x7fc> +10002c70: 3401 adds r4, #1 +10002c72: e66e b.n 10002952 <_vsnprintf+0x51e> +10002c74: 6819 ldr r1, [r3, #0] +10002c76: 0fcb lsrs r3, r1, #31 +10002c78: 2900 cmp r1, #0 +10002c7a: f000 80a8 beq.w 10002dce <_vsnprintf+0x99a> +10002c7e: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002c82: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002c86: a912 add r1, sp, #72 @ 0x48 +10002c88: 4608 mov r0, r1 +10002c8a: f8df e188 ldr.w lr, [pc, #392] @ 10002e14 <_vsnprintf+0x9e0> +10002c8e: 910b str r1, [sp, #44] @ 0x2c +10002c90: 930a str r3, [sp, #40] @ 0x28 +10002c92: 950c str r5, [sp, #48] @ 0x30 +10002c94: e001 b.n 10002c9a <_vsnprintf+0x866> +10002c96: 2f20 cmp r7, #32 +10002c98: d00f beq.n 10002cba <_vsnprintf+0x886> +10002c9a: 4615 mov r5, r2 +10002c9c: fbae 1302 umull r1, r3, lr, r2 +10002ca0: 08db lsrs r3, r3, #3 +10002ca2: eb03 0183 add.w r1, r3, r3, lsl #2 +10002ca6: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002caa: 3130 adds r1, #48 @ 0x30 +10002cac: 2d09 cmp r5, #9 +10002cae: 461a mov r2, r3 +10002cb0: f107 0701 add.w r7, r7, #1 +10002cb4: f800 1b01 strb.w r1, [r0], #1 +10002cb8: d8ed bhi.n 10002c96 <_vsnprintf+0x862> +10002cba: 9b0a ldr r3, [sp, #40] @ 0x28 +10002cbc: 9d0c ldr r5, [sp, #48] @ 0x30 +10002cbe: e9cd 5c05 strd r5, ip, [sp, #20] +10002cc2: e9cd 7301 strd r7, r3, [sp, #4] +10002cc6: 9604 str r6, [sp, #16] +10002cc8: e6d5 b.n 10002a76 <_vsnprintf+0x642> +10002cca: 2869 cmp r0, #105 @ 0x69 +10002ccc: f023 0c10 bic.w ip, r3, #16 +10002cd0: f040 808c bne.w 10002dec <_vsnprintf+0x9b8> +10002cd4: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002cd8: f43f ae8e beq.w 100029f8 <_vsnprintf+0x5c4> +10002cdc: e688 b.n 100029f0 <_vsnprintf+0x5bc> +10002cde: 2a00 cmp r2, #0 +10002ce0: f43f aea8 beq.w 10002a34 <_vsnprintf+0x600> +10002ce4: aa12 add r2, sp, #72 @ 0x48 +10002ce6: 920b str r2, [sp, #44] @ 0x2c +10002ce8: e6c0 b.n 10002a6c <_vsnprintf+0x638> +10002cea: f013 0f20 tst.w r3, #32 +10002cee: bf14 ite ne +10002cf0: 2241 movne r2, #65 @ 0x41 +10002cf2: 2261 moveq r2, #97 @ 0x61 +10002cf4: 2000 movs r0, #0 +10002cf6: a912 add r1, sp, #72 @ 0x48 +10002cf8: 3a0a subs r2, #10 +10002cfa: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002cfe: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002d02: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002d06: 4606 mov r6, r0 +10002d08: 4688 mov r8, r1 +10002d0a: 4675 mov r5, lr +10002d0c: 4693 mov fp, r2 +10002d0e: 910b str r1, [sp, #44] @ 0x2c +10002d10: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002d14: e003 b.n 10002d1e <_vsnprintf+0x8ea> +10002d16: 2e20 cmp r6, #32 +10002d18: d017 beq.n 10002d4a <_vsnprintf+0x916> +10002d1a: 4604 mov r4, r0 +10002d1c: 460d mov r5, r1 +10002d1e: 4629 mov r1, r5 +10002d20: 463a mov r2, r7 +10002d22: 2300 movs r3, #0 +10002d24: 4620 mov r0, r4 +10002d26: f000 fc47 bl 100035b8 <____aeabi_uldivmod_veneer> +10002d2a: b2d2 uxtb r2, r2 +10002d2c: 2a09 cmp r2, #9 +10002d2e: f102 0330 add.w r3, r2, #48 @ 0x30 +10002d32: bf88 it hi +10002d34: eb02 030b addhi.w r3, r2, fp +10002d38: 42bc cmp r4, r7 +10002d3a: b2db uxtb r3, r3 +10002d3c: f175 0500 sbcs.w r5, r5, #0 +10002d40: f808 3b01 strb.w r3, [r8], #1 +10002d44: f106 0601 add.w r6, r6, #1 +10002d48: d2e5 bcs.n 10002d16 <_vsnprintf+0x8e2> +10002d4a: 4631 mov r1, r6 +10002d4c: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002d50: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002d54: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002d58: 9e0e ldr r6, [sp, #56] @ 0x38 +10002d5a: e757 b.n 10002c0c <_vsnprintf+0x7d8> +10002d5c: 990a ldr r1, [sp, #40] @ 0x28 +10002d5e: 6809 ldr r1, [r1, #0] +10002d60: b951 cbnz r1, 10002d78 <_vsnprintf+0x944> +10002d62: f023 0310 bic.w r3, r3, #16 +10002d66: b138 cbz r0, 10002d78 <_vsnprintf+0x944> +10002d68: a912 add r1, sp, #72 @ 0x48 +10002d6a: 910b str r1, [sp, #44] @ 0x2c +10002d6c: e9cd 5305 strd r5, r3, [sp, #20] +10002d70: e9cd c603 strd ip, r6, [sp, #12] +10002d74: 9201 str r2, [sp, #4] +10002d76: e5cf b.n 10002918 <_vsnprintf+0x4e4> +10002d78: f013 0f20 tst.w r3, #32 +10002d7c: bf14 ite ne +10002d7e: 2041 movne r0, #65 @ 0x41 +10002d80: 2061 moveq r0, #97 @ 0x61 +10002d82: ac12 add r4, sp, #72 @ 0x48 +10002d84: 46a6 mov lr, r4 +10002d86: 940b str r4, [sp, #44] @ 0x2c +10002d88: 930a str r3, [sp, #40] @ 0x28 +10002d8a: f1a0 040a sub.w r4, r0, #10 +10002d8e: 950c str r5, [sp, #48] @ 0x30 +10002d90: e002 b.n 10002d98 <_vsnprintf+0x964> +10002d92: 2a20 cmp r2, #32 +10002d94: d012 beq.n 10002dbc <_vsnprintf+0x988> +10002d96: 4629 mov r1, r5 +10002d98: fbb1 f5fc udiv r5, r1, ip +10002d9c: fb0c 1015 mls r0, ip, r5, r1 +10002da0: b2c3 uxtb r3, r0 +10002da2: 2809 cmp r0, #9 +10002da4: f103 0030 add.w r0, r3, #48 @ 0x30 +10002da8: bf8a itet hi +10002daa: 191b addhi r3, r3, r4 +10002dac: b2c3 uxtbls r3, r0 +10002dae: b2db uxtbhi r3, r3 +10002db0: 4561 cmp r1, ip +10002db2: f80e 3b01 strb.w r3, [lr], #1 +10002db6: f102 0201 add.w r2, r2, #1 +10002dba: d2ea bcs.n 10002d92 <_vsnprintf+0x95e> +10002dbc: 9b0a ldr r3, [sp, #40] @ 0x28 +10002dbe: 9d0c ldr r5, [sp, #48] @ 0x30 +10002dc0: e7d4 b.n 10002d6c <_vsnprintf+0x938> +10002dc2: 6819 ldr r1, [r3, #0] +10002dc4: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002dc8: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002dcc: e62d b.n 10002a2a <_vsnprintf+0x5f6> +10002dce: 2a00 cmp r2, #0 +10002dd0: f43f af59 beq.w 10002c86 <_vsnprintf+0x852> +10002dd4: aa12 add r2, sp, #72 @ 0x48 +10002dd6: 920b str r2, [sp, #44] @ 0x2c +10002dd8: e771 b.n 10002cbe <_vsnprintf+0x88a> +10002dda: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002dde: d00d beq.n 10002dfc <_vsnprintf+0x9c8> +10002de0: f013 0402 ands.w r4, r3, #2 +10002de4: d012 beq.n 10002e0c <_vsnprintf+0x9d8> +10002de6: 4604 mov r4, r0 +10002de8: 4646 mov r6, r8 +10002dea: e5ec b.n 100029c6 <_vsnprintf+0x592> +10002dec: 270a movs r7, #10 +10002dee: 4663 mov r3, ip +10002df0: 46bc mov ip, r7 +10002df2: e56c b.n 100028ce <_vsnprintf+0x49a> +10002df4: ab12 add r3, sp, #72 @ 0x48 +10002df6: 2000 movs r0, #0 +10002df8: 930b str r3, [sp, #44] @ 0x2c +10002dfa: e69d b.n 10002b38 <_vsnprintf+0x704> +10002dfc: f013 0302 ands.w r3, r3, #2 +10002e00: f47f ade0 bne.w 100029c4 <_vsnprintf+0x590> +10002e04: 2d00 cmp r5, #0 +10002e06: f47f af13 bne.w 10002c30 <_vsnprintf+0x7fc> +10002e0a: e49a b.n 10002742 <_vsnprintf+0x30e> +10002e0c: 2d00 cmp r5, #0 +10002e0e: f47f af0d bne.w 10002c2c <_vsnprintf+0x7f8> +10002e12: e496 b.n 10002742 <_vsnprintf+0x30e> +10002e14: cccccccd .word 0xcccccccd + +10002e18 : +10002e18: b570 push {r4, r5, r6, lr} +10002e1a: 4694 mov ip, r2 +10002e1c: 461e mov r6, r3 +10002e1e: 4605 mov r5, r0 +10002e20: 460c mov r4, r1 +10002e22: b084 sub sp, #16 +10002e24: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e28: 4663 mov r3, ip +10002e2a: a902 add r1, sp, #8 +10002e2c: 9600 str r6, [sp, #0] +10002e2e: 4803 ldr r0, [pc, #12] @ (10002e3c ) +10002e30: e9cd 5402 strd r5, r4, [sp, #8] +10002e34: f7ff fafe bl 10002434 <_vsnprintf> +10002e38: b004 add sp, #16 +10002e3a: bd70 pop {r4, r5, r6, pc} +10002e3c: 100019f5 .word 0x100019f5 + +10002e40 : +10002e40: b510 push {r4, lr} +10002e42: 4b09 ldr r3, [pc, #36] @ (10002e68 ) +10002e44: b084 sub sp, #16 +10002e46: 681c ldr r4, [r3, #0] +10002e48: b14c cbz r4, 10002e5e +10002e4a: 4603 mov r3, r0 +10002e4c: 9100 str r1, [sp, #0] +10002e4e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002e52: a903 add r1, sp, #12 +10002e54: 4805 ldr r0, [pc, #20] @ (10002e6c ) +10002e56: 47a0 blx r4 +10002e58: 2001 movs r0, #1 +10002e5a: b004 add sp, #16 +10002e5c: bd10 pop {r4, pc} +10002e5e: f000 f97d bl 1000315c <__wrap_puts> +10002e62: 4620 mov r0, r4 +10002e64: b004 add sp, #16 +10002e66: bd10 pop {r4, pc} +10002e68: 2000080c .word 0x2000080c +10002e6c: 100019ed .word 0x100019ed + +10002e70 <_exit>: +10002e70: be00 bkpt 0x0000 +10002e72: e7fd b.n 10002e70 <_exit> + +10002e74 : +10002e74: b508 push {r3, lr} +10002e76: f7ff fffb bl 10002e70 <_exit> +10002e7a: bf00 nop + +10002e7c : +10002e7c: b538 push {r3, r4, r5, lr} +10002e7e: 4c06 ldr r4, [pc, #24] @ (10002e98 ) +10002e80: 4d06 ldr r5, [pc, #24] @ (10002e9c ) +10002e82: f7fe fa07 bl 10001294 +10002e86: 42ac cmp r4, r5 +10002e88: d204 bcs.n 10002e94 +10002e8a: f854 3b04 ldr.w r3, [r4], #4 +10002e8e: 4798 blx r3 +10002e90: 42ac cmp r4, r5 +10002e92: d3fa bcc.n 10002e8a +10002e94: bd38 pop {r3, r4, r5, pc} +10002e96: bf00 nop +10002e98: 10003610 .word 0x10003610 +10002e9c: 10003614 .word 0x10003614 + +10002ea0 : +10002ea0: 6803 ldr r3, [r0, #0] +10002ea2: 4608 mov r0, r1 +10002ea4: 4611 mov r1, r2 +10002ea6: 4718 bx r3 + +10002ea8 : +10002ea8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002eac: 4615 mov r5, r2 +10002eae: 7d42 ldrb r2, [r0, #21] +10002eb0: 4607 mov r7, r0 +10002eb2: 4688 mov r8, r1 +10002eb4: 2a00 cmp r2, #0 +10002eb6: d046 beq.n 10002f46 +10002eb8: 2d00 cmp r5, #0 +10002eba: dd1d ble.n 10002ef8 +10002ebc: 780b ldrb r3, [r1, #0] +10002ebe: 2b0a cmp r3, #10 +10002ec0: d023 beq.n 10002f0a +10002ec2: 2d01 cmp r5, #1 +10002ec4: f04f 0c00 mov.w ip, #0 +10002ec8: d018 beq.n 10002efc +10002eca: 4646 mov r6, r8 +10002ecc: 2401 movs r4, #1 +10002ece: f816 2f01 ldrb.w r2, [r6, #1]! +10002ed2: 4621 mov r1, r4 +10002ed4: 2a0a cmp r2, #10 +10002ed6: f104 0401 add.w r4, r4, #1 +10002eda: d022 beq.n 10002f22 +10002edc: 42a5 cmp r5, r4 +10002ede: d1f6 bne.n 10002ece +10002ee0: 4565 cmp r5, ip +10002ee2: dc0b bgt.n 10002efc +10002ee4: eb08 0305 add.w r3, r8, r5 +10002ee8: f813 3c01 ldrb.w r3, [r3, #-1] +10002eec: f1a3 030d sub.w r3, r3, #13 +10002ef0: fab3 f383 clz r3, r3 +10002ef4: 095b lsrs r3, r3, #5 +10002ef6: 753b strb r3, [r7, #20] +10002ef8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002efc: 683b ldr r3, [r7, #0] +10002efe: eba5 010c sub.w r1, r5, ip +10002f02: eb08 000c add.w r0, r8, ip +10002f06: 4798 blx r3 +10002f08: e7ec b.n 10002ee4 +10002f0a: 7d03 ldrb r3, [r0, #20] +10002f0c: 2b00 cmp r3, #0 +10002f0e: d1d8 bne.n 10002ec2 +10002f10: 6803 ldr r3, [r0, #0] +10002f12: 2102 movs r1, #2 +10002f14: 480f ldr r0, [pc, #60] @ (10002f54 ) +10002f16: 4798 blx r3 +10002f18: 2d01 cmp r5, #1 +10002f1a: d0e3 beq.n 10002ee4 +10002f1c: f04f 0c01 mov.w ip, #1 +10002f20: e7d3 b.n 10002eca +10002f22: f816 3c01 ldrb.w r3, [r6, #-1] +10002f26: 2b0d cmp r3, #13 +10002f28: d0d8 beq.n 10002edc +10002f2a: 458c cmp ip, r1 +10002f2c: eb08 000c add.w r0, r8, ip +10002f30: eba1 010c sub.w r1, r1, ip +10002f34: da01 bge.n 10002f3a +10002f36: 683b ldr r3, [r7, #0] +10002f38: 4798 blx r3 +10002f3a: 2102 movs r1, #2 +10002f3c: 4805 ldr r0, [pc, #20] @ (10002f54 ) +10002f3e: 683b ldr r3, [r7, #0] +10002f40: 4798 blx r3 +10002f42: 46a4 mov ip, r4 +10002f44: e7ca b.n 10002edc +10002f46: 4629 mov r1, r5 +10002f48: 4640 mov r0, r8 +10002f4a: 683b ldr r3, [r7, #0] +10002f4c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002f50: 4718 bx r3 +10002f52: bf00 nop +10002f54: 100037b8 .word 0x100037b8 + +10002f58 : +10002f58: 680b ldr r3, [r1, #0] +10002f5a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002f5e: 2b80 cmp r3, #128 @ 0x80 +10002f60: 460d mov r5, r1 +10002f62: 4606 mov r6, r0 +10002f64: d005 beq.n 10002f72 +10002f66: 1c5a adds r2, r3, #1 +10002f68: 442b add r3, r5 +10002f6a: 602a str r2, [r5, #0] +10002f6c: 711e strb r6, [r3, #4] +10002f6e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002f72: 4b0f ldr r3, [pc, #60] @ (10002fb0 ) +10002f74: 681c ldr r4, [r3, #0] +10002f76: b1a4 cbz r4, 10002fa2 +10002f78: 4f0e ldr r7, [pc, #56] @ (10002fb4 ) +10002f7a: f101 0804 add.w r8, r1, #4 +10002f7e: e001 b.n 10002f84 +10002f80: 6924 ldr r4, [r4, #16] +10002f82: b174 cbz r4, 10002fa2 +10002f84: 6823 ldr r3, [r4, #0] +10002f86: 2b00 cmp r3, #0 +10002f88: d0fa beq.n 10002f80 +10002f8a: 683b ldr r3, [r7, #0] +10002f8c: b10b cbz r3, 10002f92 +10002f8e: 42a3 cmp r3, r4 +10002f90: d1f6 bne.n 10002f80 +10002f92: 4620 mov r0, r4 +10002f94: 4641 mov r1, r8 +10002f96: 682a ldr r2, [r5, #0] +10002f98: f7ff ff86 bl 10002ea8 +10002f9c: 6924 ldr r4, [r4, #16] +10002f9e: 2c00 cmp r4, #0 +10002fa0: d1f0 bne.n 10002f84 +10002fa2: 2300 movs r3, #0 +10002fa4: 2201 movs r2, #1 +10002fa6: 442b add r3, r5 +10002fa8: 602a str r2, [r5, #0] +10002faa: 711e strb r6, [r3, #4] +10002fac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002fb0: 20000804 .word 0x20000804 +10002fb4: 20000808 .word 0x20000808 + +10002fb8 : +10002fb8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002fbc: b082 sub sp, #8 +10002fbe: 460d mov r5, r1 +10002fc0: 4691 mov r9, r2 +10002fc2: 461c mov r4, r3 +10002fc4: 4606 mov r6, r0 +10002fc6: f7fd ff95 bl 10000ef4 +10002fca: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002fce: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002fd2: 4a2e ldr r2, [pc, #184] @ (1000308c ) +10002fd4: 1882 adds r2, r0, r2 +10002fd6: f141 0300 adc.w r3, r1, #0 +10002fda: 4594 cmp ip, r2 +10002fdc: eb77 0103 sbcs.w r1, r7, r3 +10002fe0: bf3c itt cc +10002fe2: 4662 movcc r2, ip +10002fe4: 463b movcc r3, r7 +10002fe6: 482a ldr r0, [pc, #168] @ (10003090 ) +10002fe8: f000 faee bl 100035c8 <__mutex_try_enter_block_until_veneer> +10002fec: 1c6b adds r3, r5, #1 +10002fee: 4680 mov r8, r0 +10002ff0: d040 beq.n 10003074 +10002ff2: b30c cbz r4, 10003038 +10002ff4: 4f27 ldr r7, [pc, #156] @ (10003094 ) +10002ff6: 4b28 ldr r3, [pc, #160] @ (10003098 ) +10002ff8: 681c ldr r4, [r3, #0] +10002ffa: b1b4 cbz r4, 1000302a +10002ffc: f1b9 0f00 cmp.w r9, #0 +10003000: d11c bne.n 1000303c +10003002: f8df 909c ldr.w r9, [pc, #156] @ 100030a0 +10003006: e001 b.n 1000300c +10003008: 6924 ldr r4, [r4, #16] +1000300a: b174 cbz r4, 1000302a +1000300c: 6823 ldr r3, [r4, #0] +1000300e: 2b00 cmp r3, #0 +10003010: d0fa beq.n 10003008 +10003012: f8d9 3000 ldr.w r3, [r9] +10003016: b10b cbz r3, 1000301c +10003018: 429c cmp r4, r3 +1000301a: d1f5 bne.n 10003008 +1000301c: 4620 mov r0, r4 +1000301e: 462a mov r2, r5 +10003020: 4631 mov r1, r6 +10003022: 47b8 blx r7 +10003024: 6924 ldr r4, [r4, #16] +10003026: 2c00 cmp r4, #0 +10003028: d1f0 bne.n 1000300c +1000302a: f1b8 0f00 cmp.w r8, #0 +1000302e: d126 bne.n 1000307e +10003030: 4628 mov r0, r5 +10003032: b002 add sp, #8 +10003034: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003038: 4f18 ldr r7, [pc, #96] @ (1000309c ) +1000303a: e7dc b.n 10002ff6 +1000303c: f04f 0a0a mov.w sl, #10 +10003040: f8df 905c ldr.w r9, [pc, #92] @ 100030a0 +10003044: e002 b.n 1000304c +10003046: 6924 ldr r4, [r4, #16] +10003048: 2c00 cmp r4, #0 +1000304a: d0ee beq.n 1000302a +1000304c: 6823 ldr r3, [r4, #0] +1000304e: 2b00 cmp r3, #0 +10003050: d0f9 beq.n 10003046 +10003052: f8d9 3000 ldr.w r3, [r9] +10003056: b10b cbz r3, 1000305c +10003058: 42a3 cmp r3, r4 +1000305a: d1f4 bne.n 10003046 +1000305c: 462a mov r2, r5 +1000305e: 4631 mov r1, r6 +10003060: 4620 mov r0, r4 +10003062: 47b8 blx r7 +10003064: 2201 movs r2, #1 +10003066: 4620 mov r0, r4 +10003068: f10d 0107 add.w r1, sp, #7 +1000306c: f88d a007 strb.w sl, [sp, #7] +10003070: 47b8 blx r7 +10003072: e7e8 b.n 10003046 +10003074: 4630 mov r0, r6 +10003076: f000 fa6f bl 10003558 +1000307a: 4605 mov r5, r0 +1000307c: e7b9 b.n 10002ff2 +1000307e: 4804 ldr r0, [pc, #16] @ (10003090 ) +10003080: f000 fa9e bl 100035c0 <__mutex_exit_veneer> +10003084: 4628 mov r0, r5 +10003086: b002 add sp, #8 +10003088: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000308c: 000f4240 .word 0x000f4240 +10003090: 20000624 .word 0x20000624 +10003094: 10002ea9 .word 0x10002ea9 +10003098: 20000804 .word 0x20000804 +1000309c: 10002ea1 .word 0x10002ea1 +100030a0: 20000808 .word 0x20000808 + +100030a4 : +100030a4: 4a08 ldr r2, [pc, #32] @ (100030c8 ) +100030a6: 6813 ldr r3, [r2, #0] +100030a8: b923 cbnz r3, 100030b4 +100030aa: e00a b.n 100030c2 +100030ac: f103 0210 add.w r2, r3, #16 +100030b0: 691b ldr r3, [r3, #16] +100030b2: b133 cbz r3, 100030c2 +100030b4: 4283 cmp r3, r0 +100030b6: d1f9 bne.n 100030ac +100030b8: b929 cbnz r1, 100030c6 +100030ba: 6918 ldr r0, [r3, #16] +100030bc: 6010 str r0, [r2, #0] +100030be: 6119 str r1, [r3, #16] +100030c0: 4770 bx lr +100030c2: b101 cbz r1, 100030c6 +100030c4: 6010 str r0, [r2, #0] +100030c6: 4770 bx lr +100030c8: 20000804 .word 0x20000804 + +100030cc : +100030cc: b508 push {r3, lr} +100030ce: f000 f9a3 bl 10003418 +100030d2: 2001 movs r0, #1 +100030d4: bd08 pop {r3, pc} +100030d6: bf00 nop + +100030d8 <__wrap_putchar>: +100030d8: b5f0 push {r4, r5, r6, r7, lr} +100030da: b083 sub sp, #12 +100030dc: 4606 mov r6, r0 +100030de: f88d 0007 strb.w r0, [sp, #7] +100030e2: f7fd ff07 bl 10000ef4 +100030e6: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100030ea: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100030ee: 4a17 ldr r2, [pc, #92] @ (1000314c <__wrap_putchar+0x74>) +100030f0: 1882 adds r2, r0, r2 +100030f2: f141 0300 adc.w r3, r1, #0 +100030f6: 4295 cmp r5, r2 +100030f8: eb74 0103 sbcs.w r1, r4, r3 +100030fc: bf3c itt cc +100030fe: 4623 movcc r3, r4 +10003100: 462a movcc r2, r5 +10003102: 4813 ldr r0, [pc, #76] @ (10003150 <__wrap_putchar+0x78>) +10003104: f000 fa60 bl 100035c8 <__mutex_try_enter_block_until_veneer> +10003108: 4b12 ldr r3, [pc, #72] @ (10003154 <__wrap_putchar+0x7c>) +1000310a: 4607 mov r7, r0 +1000310c: 681c ldr r4, [r3, #0] +1000310e: b19c cbz r4, 10003138 <__wrap_putchar+0x60> +10003110: 4d11 ldr r5, [pc, #68] @ (10003158 <__wrap_putchar+0x80>) +10003112: e001 b.n 10003118 <__wrap_putchar+0x40> +10003114: 6924 ldr r4, [r4, #16] +10003116: b17c cbz r4, 10003138 <__wrap_putchar+0x60> +10003118: 6823 ldr r3, [r4, #0] +1000311a: 2b00 cmp r3, #0 +1000311c: d0fa beq.n 10003114 <__wrap_putchar+0x3c> +1000311e: 682b ldr r3, [r5, #0] +10003120: b10b cbz r3, 10003126 <__wrap_putchar+0x4e> +10003122: 429c cmp r4, r3 +10003124: d1f6 bne.n 10003114 <__wrap_putchar+0x3c> +10003126: 4620 mov r0, r4 +10003128: 2201 movs r2, #1 +1000312a: f10d 0107 add.w r1, sp, #7 +1000312e: f7ff febb bl 10002ea8 +10003132: 6924 ldr r4, [r4, #16] +10003134: 2c00 cmp r4, #0 +10003136: d1ef bne.n 10003118 <__wrap_putchar+0x40> +10003138: b917 cbnz r7, 10003140 <__wrap_putchar+0x68> +1000313a: 4630 mov r0, r6 +1000313c: b003 add sp, #12 +1000313e: bdf0 pop {r4, r5, r6, r7, pc} +10003140: 4803 ldr r0, [pc, #12] @ (10003150 <__wrap_putchar+0x78>) +10003142: f000 fa3d bl 100035c0 <__mutex_exit_veneer> +10003146: 4630 mov r0, r6 +10003148: b003 add sp, #12 +1000314a: bdf0 pop {r4, r5, r6, r7, pc} +1000314c: 000f4240 .word 0x000f4240 +10003150: 20000624 .word 0x20000624 +10003154: 20000804 .word 0x20000804 +10003158: 20000808 .word 0x20000808 + +1000315c <__wrap_puts>: +1000315c: b538 push {r3, r4, r5, lr} +1000315e: 4604 mov r4, r0 +10003160: f000 f9fa bl 10003558 +10003164: 2301 movs r3, #1 +10003166: 4605 mov r5, r0 +10003168: 461a mov r2, r3 +1000316a: 4620 mov r0, r4 +1000316c: 4629 mov r1, r5 +1000316e: f7ff ff23 bl 10002fb8 +10003172: 4b08 ldr r3, [pc, #32] @ (10003194 <__wrap_puts+0x38>) +10003174: 681c ldr r4, [r3, #0] +10003176: b12c cbz r4, 10003184 <__wrap_puts+0x28> +10003178: 6863 ldr r3, [r4, #4] +1000317a: b12b cbz r3, 10003188 <__wrap_puts+0x2c> +1000317c: 4798 blx r3 +1000317e: 6924 ldr r4, [r4, #16] +10003180: 2c00 cmp r4, #0 +10003182: d1f9 bne.n 10003178 <__wrap_puts+0x1c> +10003184: 4628 mov r0, r5 +10003186: bd38 pop {r3, r4, r5, pc} +10003188: 6924 ldr r4, [r4, #16] +1000318a: 2c00 cmp r4, #0 +1000318c: d1f4 bne.n 10003178 <__wrap_puts+0x1c> +1000318e: 4628 mov r0, r5 +10003190: bd38 pop {r3, r4, r5, pc} +10003192: bf00 nop +10003194: 20000804 .word 0x20000804 + +10003198 <__wrap_vprintf>: +10003198: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000319c: b0a2 sub sp, #136 @ 0x88 +1000319e: 4604 mov r4, r0 +100031a0: 460d mov r5, r1 +100031a2: f7fd fea7 bl 10000ef4 +100031a6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +100031aa: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +100031ae: 4a26 ldr r2, [pc, #152] @ (10003248 <__wrap_vprintf+0xb0>) +100031b0: f8df 80a4 ldr.w r8, [pc, #164] @ 10003258 <__wrap_vprintf+0xc0> +100031b4: 1882 adds r2, r0, r2 +100031b6: f141 0300 adc.w r3, r1, #0 +100031ba: 4297 cmp r7, r2 +100031bc: eb76 0103 sbcs.w r1, r6, r3 +100031c0: bf3c itt cc +100031c2: 463a movcc r2, r7 +100031c4: 4633 movcc r3, r6 +100031c6: 4821 ldr r0, [pc, #132] @ (1000324c <__wrap_vprintf+0xb4>) +100031c8: f000 f9fe bl 100035c8 <__mutex_try_enter_block_until_veneer> +100031cc: 2700 movs r7, #0 +100031ce: 462b mov r3, r5 +100031d0: 4622 mov r2, r4 +100031d2: 4606 mov r6, r0 +100031d4: a901 add r1, sp, #4 +100031d6: 481e ldr r0, [pc, #120] @ (10003250 <__wrap_vprintf+0xb8>) +100031d8: 9701 str r7, [sp, #4] +100031da: f7ff fe1d bl 10002e18 +100031de: 9b01 ldr r3, [sp, #4] +100031e0: 4605 mov r5, r0 +100031e2: f8d8 4000 ldr.w r4, [r8] +100031e6: b1c3 cbz r3, 1000321a <__wrap_vprintf+0x82> +100031e8: 2c00 cmp r4, #0 +100031ea: d02b beq.n 10003244 <__wrap_vprintf+0xac> +100031ec: 4f19 ldr r7, [pc, #100] @ (10003254 <__wrap_vprintf+0xbc>) +100031ee: e001 b.n 100031f4 <__wrap_vprintf+0x5c> +100031f0: 6924 ldr r4, [r4, #16] +100031f2: b174 cbz r4, 10003212 <__wrap_vprintf+0x7a> +100031f4: 6823 ldr r3, [r4, #0] +100031f6: 2b00 cmp r3, #0 +100031f8: d0fa beq.n 100031f0 <__wrap_vprintf+0x58> +100031fa: 683b ldr r3, [r7, #0] +100031fc: b10b cbz r3, 10003202 <__wrap_vprintf+0x6a> +100031fe: 42a3 cmp r3, r4 +10003200: d1f6 bne.n 100031f0 <__wrap_vprintf+0x58> +10003202: 4620 mov r0, r4 +10003204: 9a01 ldr r2, [sp, #4] +10003206: a902 add r1, sp, #8 +10003208: f7ff fe4e bl 10002ea8 +1000320c: 6924 ldr r4, [r4, #16] +1000320e: 2c00 cmp r4, #0 +10003210: d1f0 bne.n 100031f4 <__wrap_vprintf+0x5c> +10003212: 2300 movs r3, #0 +10003214: f8d8 4000 ldr.w r4, [r8] +10003218: 9301 str r3, [sp, #4] +1000321a: b12c cbz r4, 10003228 <__wrap_vprintf+0x90> +1000321c: 6863 ldr r3, [r4, #4] +1000321e: b143 cbz r3, 10003232 <__wrap_vprintf+0x9a> +10003220: 4798 blx r3 +10003222: 6924 ldr r4, [r4, #16] +10003224: 2c00 cmp r4, #0 +10003226: d1f9 bne.n 1000321c <__wrap_vprintf+0x84> +10003228: b92e cbnz r6, 10003236 <__wrap_vprintf+0x9e> +1000322a: 4628 mov r0, r5 +1000322c: b022 add sp, #136 @ 0x88 +1000322e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003232: 6924 ldr r4, [r4, #16] +10003234: e7f1 b.n 1000321a <__wrap_vprintf+0x82> +10003236: 4805 ldr r0, [pc, #20] @ (1000324c <__wrap_vprintf+0xb4>) +10003238: f000 f9c2 bl 100035c0 <__mutex_exit_veneer> +1000323c: 4628 mov r0, r5 +1000323e: b022 add sp, #136 @ 0x88 +10003240: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003244: 9401 str r4, [sp, #4] +10003246: e7ef b.n 10003228 <__wrap_vprintf+0x90> +10003248: 000f4240 .word 0x000f4240 +1000324c: 20000624 .word 0x20000624 +10003250: 10002f59 .word 0x10002f59 +10003254: 20000808 .word 0x20000808 +10003258: 20000804 .word 0x20000804 + +1000325c <__wrap_printf>: +1000325c: b40f push {r0, r1, r2, r3} +1000325e: b500 push {lr} +10003260: b083 sub sp, #12 +10003262: a904 add r1, sp, #16 +10003264: f851 0b04 ldr.w r0, [r1], #4 +10003268: 9101 str r1, [sp, #4] +1000326a: f7ff ff95 bl 10003198 <__wrap_vprintf> +1000326e: b003 add sp, #12 +10003270: f85d eb04 ldr.w lr, [sp], #4 +10003274: b004 add sp, #16 +10003276: 4770 bx lr + +10003278 : +10003278: f1b1 0c00 subs.w ip, r1, #0 +1000327c: dd1d ble.n 100032ba +1000327e: 4a0f ldr r2, [pc, #60] @ (100032bc ) +10003280: 4b0f ldr r3, [pc, #60] @ (100032c0 ) +10003282: 6812 ldr r2, [r2, #0] +10003284: b530 push {r4, r5, lr} +10003286: 1ad3 subs r3, r2, r3 +10003288: fab3 f383 clz r3, r3 +1000328c: 240d movs r4, #13 +1000328e: 4d0d ldr r5, [pc, #52] @ (100032c4 ) +10003290: 095b lsrs r3, r3, #5 +10003292: 1e41 subs r1, r0, #1 +10003294: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003298: 448c add ip, r1 +1000329a: f811 0f01 ldrb.w r0, [r1, #1]! +1000329e: 4586 cmp lr, r0 +100032a0: d006 beq.n 100032b0 +100032a2: 6993 ldr r3, [r2, #24] +100032a4: 069b lsls r3, r3, #26 +100032a6: d4fc bmi.n 100032a2 +100032a8: 4561 cmp r1, ip +100032aa: 6010 str r0, [r2, #0] +100032ac: d1f5 bne.n 1000329a +100032ae: bd30 pop {r4, r5, pc} +100032b0: 6993 ldr r3, [r2, #24] +100032b2: 069d lsls r5, r3, #26 +100032b4: d4fc bmi.n 100032b0 +100032b6: 6014 str r4, [r2, #0] +100032b8: e7f3 b.n 100032a2 +100032ba: 4770 bx lr +100032bc: 20000850 .word 0x20000850 +100032c0: 40078000 .word 0x40078000 +100032c4: 2000084c .word 0x2000084c + +100032c8 : +100032c8: 4b22 ldr r3, [pc, #136] @ (10003354 ) +100032ca: f1b1 0c00 subs.w ip, r1, #0 +100032ce: b410 push {r4} +100032d0: 681c ldr r4, [r3, #0] +100032d2: dd2e ble.n 10003332 +100032d4: 4603 mov r3, r0 +100032d6: 2000 movs r0, #0 +100032d8: 4a1f ldr r2, [pc, #124] @ (10003358 ) +100032da: 1e59 subs r1, r3, #1 +100032dc: 6812 ldr r2, [r2, #0] +100032de: 6993 ldr r3, [r2, #24] +100032e0: 06db lsls r3, r3, #27 +100032e2: d417 bmi.n 10003314 +100032e4: 3001 adds r0, #1 +100032e6: 6993 ldr r3, [r2, #24] +100032e8: 06db lsls r3, r3, #27 +100032ea: d4fc bmi.n 100032e6 +100032ec: 6813 ldr r3, [r2, #0] +100032ee: 4584 cmp ip, r0 +100032f0: f801 3f01 strb.w r3, [r1, #1]! +100032f4: d1f3 bne.n 100032de +100032f6: b14c cbz r4, 1000330c +100032f8: 2150 movs r1, #80 @ 0x50 +100032fa: 4613 mov r3, r2 +100032fc: 6391 str r1, [r2, #56] @ 0x38 +100032fe: f853 2f34 ldr.w r2, [r3, #52]! +10003302: f002 0238 and.w r2, r2, #56 @ 0x38 +10003306: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000330a: 601a str r2, [r3, #0] +1000330c: 4660 mov r0, ip +1000330e: f85d 4b04 ldr.w r4, [sp], #4 +10003312: 4770 bx lr +10003314: b14c cbz r4, 1000332a +10003316: 2150 movs r1, #80 @ 0x50 +10003318: 4613 mov r3, r2 +1000331a: 6391 str r1, [r2, #56] @ 0x38 +1000331c: f853 2f34 ldr.w r2, [r3, #52]! +10003320: f002 0238 and.w r2, r2, #56 @ 0x38 +10003324: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003328: 601a str r2, [r3, #0] +1000332a: b178 cbz r0, 1000334c +1000332c: f85d 4b04 ldr.w r4, [sp], #4 +10003330: 4770 bx lr +10003332: b15c cbz r4, 1000334c +10003334: 4b08 ldr r3, [pc, #32] @ (10003358 ) +10003336: 2150 movs r1, #80 @ 0x50 +10003338: 681a ldr r2, [r3, #0] +1000333a: 4613 mov r3, r2 +1000333c: 6391 str r1, [r2, #56] @ 0x38 +1000333e: f853 2f34 ldr.w r2, [r3, #52]! +10003342: f002 0238 and.w r2, r2, #56 @ 0x38 +10003346: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000334a: 601a str r2, [r3, #0] +1000334c: f06f 0002 mvn.w r0, #2 +10003350: e7dd b.n 1000330e +10003352: bf00 nop +10003354: 200007d0 .word 0x200007d0 +10003358: 20000850 .word 0x20000850 + +1000335c : +1000335c: 4b05 ldr r3, [pc, #20] @ (10003374 ) +1000335e: 681b ldr r3, [r3, #0] +10003360: b133 cbz r3, 10003370 +10003362: 2100 movs r1, #0 +10003364: 4a04 ldr r2, [pc, #16] @ (10003378 ) +10003366: 4805 ldr r0, [pc, #20] @ (1000337c ) +10003368: 6812 ldr r2, [r2, #0] +1000336a: 6800 ldr r0, [r0, #0] +1000336c: 6391 str r1, [r2, #56] @ 0x38 +1000336e: 4718 bx r3 +10003370: 4770 bx lr +10003372: bf00 nop +10003374: 200007d0 .word 0x200007d0 +10003378: 20000850 .word 0x20000850 +1000337c: 200007d4 .word 0x200007d4 + +10003380 : +10003380: 4b02 ldr r3, [pc, #8] @ (1000338c ) +10003382: 681a ldr r2, [r3, #0] +10003384: 6993 ldr r3, [r2, #24] +10003386: 071b lsls r3, r3, #28 +10003388: d4fc bmi.n 10003384 +1000338a: 4770 bx lr +1000338c: 20000850 .word 0x20000850 + +10003390 : +10003390: b5f8 push {r3, r4, r5, r6, r7, lr} +10003392: 4f1c ldr r7, [pc, #112] @ (10003404 ) +10003394: 4d1c ldr r5, [pc, #112] @ (10003408 ) +10003396: 683a ldr r2, [r7, #0] +10003398: 4e1c ldr r6, [pc, #112] @ (1000340c ) +1000339a: 42aa cmp r2, r5 +1000339c: bf14 ite ne +1000339e: 2521 movne r5, #33 @ 0x21 +100033a0: 2522 moveq r5, #34 @ 0x22 +100033a2: 4604 mov r4, r0 +100033a4: f8d6 c000 ldr.w ip, [r6] +100033a8: b118 cbz r0, 100033b2 +100033aa: f1bc 0f00 cmp.w ip, #0 +100033ae: d010 beq.n 100033d2 +100033b0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100033b2: f1bc 0f00 cmp.w ip, #0 +100033b6: d0fb beq.n 100033b0 +100033b8: 4601 mov r1, r0 +100033ba: 6390 str r0, [r2, #56] @ 0x38 +100033bc: 4628 mov r0, r5 +100033be: f7fd f823 bl 10000408 +100033c2: 4628 mov r0, r5 +100033c4: 4912 ldr r1, [pc, #72] @ (10003410 ) +100033c6: f7fd f865 bl 10000494 +100033ca: 4b12 ldr r3, [pc, #72] @ (10003414 ) +100033cc: 6034 str r4, [r6, #0] +100033ce: 601c str r4, [r3, #0] +100033d0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100033d2: 460b mov r3, r1 +100033d4: 4a0f ldr r2, [pc, #60] @ (10003414 ) +100033d6: 490e ldr r1, [pc, #56] @ (10003410 ) +100033d8: 6030 str r0, [r6, #0] +100033da: 4628 mov r0, r5 +100033dc: 6013 str r3, [r2, #0] +100033de: f7fd f829 bl 10000434 +100033e2: 2101 movs r1, #1 +100033e4: 4628 mov r0, r5 +100033e6: f7fd f80f bl 10000408 +100033ea: 683a ldr r2, [r7, #0] +100033ec: 2150 movs r1, #80 @ 0x50 +100033ee: 4613 mov r3, r2 +100033f0: 6391 str r1, [r2, #56] @ 0x38 +100033f2: f853 2f34 ldr.w r2, [r3, #52]! +100033f6: f002 0238 and.w r2, r2, #56 @ 0x38 +100033fa: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100033fe: 601a str r2, [r3, #0] +10003400: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003402: bf00 nop +10003404: 20000850 .word 0x20000850 +10003408: 40078000 .word 0x40078000 +1000340c: 200007d0 .word 0x200007d0 +10003410: 1000335d .word 0x1000335d +10003414: 200007d4 .word 0x200007d4 + +10003418 : +10003418: b510 push {r4, lr} +1000341a: 490e ldr r1, [pc, #56] @ (10003454 ) +1000341c: 4c0e ldr r4, [pc, #56] @ (10003458 ) +1000341e: 480f ldr r0, [pc, #60] @ (1000345c ) +10003420: 4a0f ldr r2, [pc, #60] @ (10003460 ) +10003422: 4b10 ldr r3, [pc, #64] @ (10003464 ) +10003424: 7800 ldrb r0, [r0, #0] +10003426: 6021 str r1, [r4, #0] +10003428: 2000 movs r0, #0 +1000342a: 2102 movs r1, #2 +1000342c: 7812 ldrb r2, [r2, #0] +1000342e: 781b ldrb r3, [r3, #0] +10003430: f7fc ff48 bl 100002c4 +10003434: 2102 movs r1, #2 +10003436: 2001 movs r0, #1 +10003438: f7fc ff44 bl 100002c4 +1000343c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003440: 6820 ldr r0, [r4, #0] +10003442: f7fd fda1 bl 10000f88 +10003446: e8bd 4010 ldmia.w sp!, {r4, lr} +1000344a: 2101 movs r1, #1 +1000344c: 4806 ldr r0, [pc, #24] @ (10003468 ) +1000344e: f7ff be29 b.w 100030a4 +10003452: bf00 nop +10003454: 40070000 .word 0x40070000 +10003458: 20000850 .word 0x20000850 +1000345c: 10003808 .word 0x10003808 +10003460: 10003804 .word 0x10003804 +10003464: 10003800 .word 0x10003800 +10003468: 2000060c .word 0x2000060c + +1000346c : +1000346c: 4684 mov ip, r0 +1000346e: ea41 0300 orr.w r3, r1, r0 +10003472: f013 0303 ands.w r3, r3, #3 +10003476: d149 bne.n 1000350c +10003478: 3a40 subs r2, #64 @ 0x40 +1000347a: d323 bcc.n 100034c4 +1000347c: 680b ldr r3, [r1, #0] +1000347e: 6003 str r3, [r0, #0] +10003480: 684b ldr r3, [r1, #4] +10003482: 6043 str r3, [r0, #4] +10003484: 688b ldr r3, [r1, #8] +10003486: 6083 str r3, [r0, #8] +10003488: 68cb ldr r3, [r1, #12] +1000348a: 60c3 str r3, [r0, #12] +1000348c: 690b ldr r3, [r1, #16] +1000348e: 6103 str r3, [r0, #16] +10003490: 694b ldr r3, [r1, #20] +10003492: 6143 str r3, [r0, #20] +10003494: 698b ldr r3, [r1, #24] +10003496: 6183 str r3, [r0, #24] +10003498: 69cb ldr r3, [r1, #28] +1000349a: 61c3 str r3, [r0, #28] +1000349c: 6a0b ldr r3, [r1, #32] +1000349e: 6203 str r3, [r0, #32] +100034a0: 6a4b ldr r3, [r1, #36] @ 0x24 +100034a2: 6243 str r3, [r0, #36] @ 0x24 +100034a4: 6a8b ldr r3, [r1, #40] @ 0x28 +100034a6: 6283 str r3, [r0, #40] @ 0x28 +100034a8: 6acb ldr r3, [r1, #44] @ 0x2c +100034aa: 62c3 str r3, [r0, #44] @ 0x2c +100034ac: 6b0b ldr r3, [r1, #48] @ 0x30 +100034ae: 6303 str r3, [r0, #48] @ 0x30 +100034b0: 6b4b ldr r3, [r1, #52] @ 0x34 +100034b2: 6343 str r3, [r0, #52] @ 0x34 +100034b4: 6b8b ldr r3, [r1, #56] @ 0x38 +100034b6: 6383 str r3, [r0, #56] @ 0x38 +100034b8: 6bcb ldr r3, [r1, #60] @ 0x3c +100034ba: 63c3 str r3, [r0, #60] @ 0x3c +100034bc: 3040 adds r0, #64 @ 0x40 +100034be: 3140 adds r1, #64 @ 0x40 +100034c0: 3a40 subs r2, #64 @ 0x40 +100034c2: d2db bcs.n 1000347c +100034c4: 3230 adds r2, #48 @ 0x30 +100034c6: d30b bcc.n 100034e0 +100034c8: 680b ldr r3, [r1, #0] +100034ca: 6003 str r3, [r0, #0] +100034cc: 684b ldr r3, [r1, #4] +100034ce: 6043 str r3, [r0, #4] +100034d0: 688b ldr r3, [r1, #8] +100034d2: 6083 str r3, [r0, #8] +100034d4: 68cb ldr r3, [r1, #12] +100034d6: 60c3 str r3, [r0, #12] +100034d8: 3010 adds r0, #16 +100034da: 3110 adds r1, #16 +100034dc: 3a10 subs r2, #16 +100034de: d2f3 bcs.n 100034c8 +100034e0: 320c adds r2, #12 +100034e2: d305 bcc.n 100034f0 +100034e4: f851 3b04 ldr.w r3, [r1], #4 +100034e8: f840 3b04 str.w r3, [r0], #4 +100034ec: 3a04 subs r2, #4 +100034ee: d2f9 bcs.n 100034e4 +100034f0: 3204 adds r2, #4 +100034f2: d008 beq.n 10003506 +100034f4: 07d2 lsls r2, r2, #31 +100034f6: bf1c itt ne +100034f8: f811 3b01 ldrbne.w r3, [r1], #1 +100034fc: f800 3b01 strbne.w r3, [r0], #1 +10003500: d301 bcc.n 10003506 +10003502: 880b ldrh r3, [r1, #0] +10003504: 8003 strh r3, [r0, #0] +10003506: 4660 mov r0, ip +10003508: 4770 bx lr +1000350a: bf00 nop +1000350c: 2a08 cmp r2, #8 +1000350e: d313 bcc.n 10003538 +10003510: 078b lsls r3, r1, #30 +10003512: d0b1 beq.n 10003478 +10003514: f010 0303 ands.w r3, r0, #3 +10003518: d0ae beq.n 10003478 +1000351a: f1c3 0304 rsb r3, r3, #4 +1000351e: 1ad2 subs r2, r2, r3 +10003520: 07db lsls r3, r3, #31 +10003522: bf1c itt ne +10003524: f811 3b01 ldrbne.w r3, [r1], #1 +10003528: f800 3b01 strbne.w r3, [r0], #1 +1000352c: d3a4 bcc.n 10003478 +1000352e: f831 3b02 ldrh.w r3, [r1], #2 +10003532: f820 3b02 strh.w r3, [r0], #2 +10003536: e79f b.n 10003478 +10003538: 3a04 subs r2, #4 +1000353a: d3d9 bcc.n 100034f0 +1000353c: 3a01 subs r2, #1 +1000353e: f811 3b01 ldrb.w r3, [r1], #1 +10003542: f800 3b01 strb.w r3, [r0], #1 +10003546: d2f9 bcs.n 1000353c +10003548: 780b ldrb r3, [r1, #0] +1000354a: 7003 strb r3, [r0, #0] +1000354c: 784b ldrb r3, [r1, #1] +1000354e: 7043 strb r3, [r0, #1] +10003550: 788b ldrb r3, [r1, #2] +10003552: 7083 strb r3, [r0, #2] +10003554: 4660 mov r0, ip +10003556: 4770 bx lr + +10003558 : +10003558: f020 0103 bic.w r1, r0, #3 +1000355c: f010 0003 ands.w r0, r0, #3 +10003560: f1c0 0000 rsb r0, r0, #0 +10003564: f851 3b04 ldr.w r3, [r1], #4 +10003568: f100 0c04 add.w ip, r0, #4 +1000356c: ea4f 0ccc mov.w ip, ip, lsl #3 +10003570: f06f 0200 mvn.w r2, #0 +10003574: bf1c itt ne +10003576: fa22 f20c lsrne.w r2, r2, ip +1000357a: 4313 orrne r3, r2 +1000357c: f04f 0c01 mov.w ip, #1 +10003580: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003584: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003588: eba3 020c sub.w r2, r3, ip +1000358c: ea22 0203 bic.w r2, r2, r3 +10003590: ea12 12cc ands.w r2, r2, ip, lsl #7 +10003594: bf04 itt eq +10003596: f851 3b04 ldreq.w r3, [r1], #4 +1000359a: 3004 addeq r0, #4 +1000359c: d0f4 beq.n 10003588 +1000359e: f1c2 0100 rsb r1, r2, #0 +100035a2: ea02 0201 and.w r2, r2, r1 +100035a6: fab2 f282 clz r2, r2 +100035aa: f1c2 021f rsb r2, r2, #31 +100035ae: eb00 00d2 add.w r0, r0, r2, lsr #3 +100035b2: 4770 bx lr + +100035b4 <_fini>: +100035b4: b5f8 push {r3, r4, r5, r6, r7, lr} +100035b6: bf00 nop + +100035b8 <____aeabi_uldivmod_veneer>: +100035b8: f85f f000 ldr.w pc, [pc] @ 100035bc <____aeabi_uldivmod_veneer+0x4> +100035bc: 20000221 .word 0x20000221 + +100035c0 <__mutex_exit_veneer>: +100035c0: f85f f000 ldr.w pc, [pc] @ 100035c4 <__mutex_exit_veneer+0x4> +100035c4: 200001e5 .word 0x200001e5 + +100035c8 <__mutex_try_enter_block_until_veneer>: +100035c8: f85f f000 ldr.w pc, [pc] @ 100035cc <__mutex_try_enter_block_until_veneer+0x4> +100035cc: 2000017d .word 0x2000017d + +100035d0 <__pre_init_runtime_init_bootrom_reset>: +100035d0: 10001341 A... + +100035d4 <__pre_init_runtime_init_early_resets>: +100035d4: 100012b5 .... + +100035d8 <__pre_init_runtime_init_usb_power_down>: +100035d8: 100012e9 .... + +100035dc <__pre_init_runtime_init_clocks>: +100035dc: 100013d5 .... + +100035e0 <__pre_init_runtime_init_post_clock_resets>: +100035e0: 10001321 !... + +100035e4 <__pre_init_runtime_init_boot_locks_reset>: +100035e4: 10001239 9... + +100035e8 <__pre_init_runtime_init_spin_locks_reset>: +100035e8: 10001369 i... + +100035ec <__pre_init_runtime_init_bootrom_locking_enable>: +100035ec: 10001225 %... + +100035f0 <__pre_init_runtime_init_mutex>: +100035f0: 10000751 Q... + +100035f4 <__pre_init_runtime_init_install_ram_vector_table>: +100035f4: 1000136d m... + +100035f8 <__pre_init_runtime_init_default_alarm_pool>: +100035f8: 10000ac9 .... + +100035fc <__pre_init_first_per_core_initializer>: +100035fc: 10001285 .... + +10003600 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003600: 10001355 U... + +10003604 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10003604: 10001305 .... + +10003608 <__pre_init_spinlock_set_extexclall>: +10003608: 100003a1 .... + +1000360c <__pre_init_runtime_init_per_core_irq_priorities>: +1000360c: 100003c9 .... + +10003610 <__frame_dummy_init_array_entry>: +10003610: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs 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f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000ded .word 0x10000ded + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 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b/WEEK05/0x000b_integer-data-type/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK05/0x000b_integer-data-type/pico_sdk_import.cmake b/WEEK05/0x000b_integer-data-type/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK05/0x000b_integer-data-type/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK05/0x000e_floating-point-data-type/.gitignore b/WEEK05/0x000e_floating-point-data-type/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/c_cpp_properties.json b/WEEK05/0x000e_floating-point-data-type/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..e80461d --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h", + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/cmake-kits.json b/WEEK05/0x000e_floating-point-data-type/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/extensions.json b/WEEK05/0x000e_floating-point-data-type/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/launch.json b/WEEK05/0x000e_floating-point-data-type/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/settings.json b/WEEK05/0x000e_floating-point-data-type/.vscode/settings.json new file mode 100644 index 0000000..cdb8e61 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK05/0x000e_floating-point-data-type/.vscode/tasks.json b/WEEK05/0x000e_floating-point-data-type/.vscode/tasks.json new file mode 100644 index 0000000..f427bf0 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK05/0x000e_floating-point-data-type/0x000e_floating-point-data-type.c b/WEEK05/0x000e_floating-point-data-type/0x000e_floating-point-data-type.c new file mode 100644 index 0000000..fb3d382 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/0x000e_floating-point-data-type.c @@ -0,0 +1,11 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + float fav_num = 42.5; + + stdio_init_all(); + + while (true) + printf("fav_num: %f\r\n", fav_num); +} diff --git a/WEEK05/0x000e_floating-point-data-type/CMakeLists.txt b/WEEK05/0x000e_floating-point-data-type/CMakeLists.txt new file mode 100644 index 0000000..72041a0 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x000e_floating-point-data-type C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x000e_floating-point-data-type 0x000e_floating-point-data-type.c ) + +pico_set_program_name(0x000e_floating-point-data-type "0x000e_floating-point-data-type") +pico_set_program_version(0x000e_floating-point-data-type "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x000e_floating-point-data-type 1) +pico_enable_stdio_usb(0x000e_floating-point-data-type 0) + +# Add the standard library to the build +target_link_libraries(0x000e_floating-point-data-type + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x000e_floating-point-data-type PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x000e_floating-point-data-type) + diff --git a/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin new file mode 100755 index 0000000..a44e4e2 Binary files /dev/null and b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin differ diff --git a/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.dis b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.dis new file mode 100644 index 0000000..09fc38e --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.dis @@ -0,0 +1,5741 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000034a4 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001c0 100034a8 100034a8 000044a8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003668 10003668 00004668 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003670 10003670 00004670 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005bcc 2**0 + CONTENTS + 6 .data 0000051c 20000110 1000369c 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005bcc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003bb8 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003bb8 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005bcc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005bcc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003bb8 10003bb8 00005bb8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005bcc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005c00 2**0 + CONTENTS, READONLY + 17 .debug_info 000206ec 00000000 00000000 00005c45 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005544 00000000 00000000 00026331 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000be8 00000000 00000000 0002b878 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 0000303d 00000000 00000000 0002c460 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 00015924 00000000 00000000 0002f49d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 00005739 00000000 00000000 00044dc1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00001f3c 00000000 00000000 0004a4fc 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000ffd1 00000000 00000000 0004c438 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c6 00000000 00000000 0005c409 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003670 .word 0x10003670 +1000012c: 1000369c .word 0x1000369c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003a80 .word 0x00003a80 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 1000369c .word 0x1000369c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003bb8 .word 0x10003bb8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003bb8 .word 0x10003bb8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002d0d .word 0x10002d0d +100001dc: 10000235 .word 0x10000235 +100001e0: 10002d05 .word 0x10002d05 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 100034a4 .word 0x100034a4 + +10000234
: +10000234: b538 push {r3, r4, r5, lr} +10000236: f002 fe91 bl 10002f5c +1000023a: 2400 movs r4, #0 +1000023c: 4d03 ldr r5, [pc, #12] @ (1000024c ) +1000023e: 4622 mov r2, r4 +10000240: 462b mov r3, r5 +10000242: 4803 ldr r0, [pc, #12] @ (10000250 ) +10000244: f002 ff52 bl 100030ec <__wrap_printf> +10000248: e7f9 b.n 1000023e +1000024a: bf00 nop +1000024c: 40454000 .word 0x40454000 +10000250: 100034a8 .word 0x100034a8 + +10000254 : +10000254: b410 push {r4} +10000256: f44f 7480 mov.w r4, #256 @ 0x100 +1000025a: 4b0c ldr r3, [pc, #48] @ (1000028c ) +1000025c: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000260: eb03 0380 add.w r3, r3, r0, lsl #2 +10000264: 00c0 lsls r0, r0, #3 +10000266: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000026a: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +1000026e: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000272: f002 02c0 and.w r2, r2, #192 @ 0xc0 +10000276: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000027a: f503 5340 add.w r3, r3, #12288 @ 0x3000 +1000027e: f8cc 2000 str.w r2, [ip] +10000282: 6041 str r1, [r0, #4] +10000284: 601c str r4, [r3, #0] +10000286: f85d 4b04 ldr.w r4, [sp], #4 +1000028a: 4770 bx lr +1000028c: 40038004 .word 0x40038004 + +10000290 : +10000290: b40f push {r0, r1, r2, r3} +10000292: b500 push {lr} +10000294: b083 sub sp, #12 +10000296: 9c04 ldr r4, [sp, #16] +10000298: 4807 ldr r0, [pc, #28] @ (100002b8 ) +1000029a: f002 fea7 bl 10002fec <__wrap_puts> +1000029e: b13c cbz r4, 100002b0 +100002a0: a905 add r1, sp, #20 +100002a2: 4620 mov r0, r4 +100002a4: 9101 str r1, [sp, #4] +100002a6: f002 fd13 bl 10002cd0 +100002aa: 4804 ldr r0, [pc, #16] @ (100002bc ) +100002ac: f002 fe9e bl 10002fec <__wrap_puts> +100002b0: 2001 movs r0, #1 +100002b2: f002 fd25 bl 10002d00 <_exit> +100002b6: bf00 nop +100002b8: 100034b8 .word 0x100034b8 +100002bc: 100034b4 .word 0x100034b4 + +100002c0 : +100002c0: b570 push {r4, r5, r6, lr} +100002c2: 4686 mov lr, r0 +100002c4: f3ef 8510 mrs r5, PRIMASK +100002c8: b672 cpsid i +100002ca: 4c12 ldr r4, [pc, #72] @ (10000314 ) +100002cc: e8d4 6fcf ldaexb r6, [r4] +100002d0: 2001 movs r0, #1 +100002d2: 2e00 cmp r6, #0 +100002d4: d1fa bne.n 100002cc +100002d6: e8c4 0f46 strexb r6, r0, [r4] +100002da: 2e00 cmp r6, #0 +100002dc: d1f6 bne.n 100002cc +100002de: f3bf 8f5f dmb sy +100002e2: f04f 0c01 mov.w ip, #1 +100002e6: 08c8 lsrs r0, r1, #3 +100002e8: f001 0307 and.w r3, r1, #7 +100002ec: fa0c f303 lsl.w r3, ip, r3 +100002f0: f81e c000 ldrb.w ip, [lr, r0] +100002f4: ea1c 0603 ands.w r6, ip, r3 +100002f8: d108 bne.n 1000030c +100002fa: ea4c 0c03 orr.w ip, ip, r3 +100002fe: f80e c000 strb.w ip, [lr, r0] +10000302: e8c4 6f8f stlb r6, [r4] +10000306: f385 8810 msr PRIMASK, r5 +1000030a: bd70 pop {r4, r5, r6, pc} +1000030c: 4610 mov r0, r2 +1000030e: f7ff ffbf bl 10000290 +10000312: bf00 nop +10000314: 200007bb .word 0x200007bb + +10000318 : +10000318: 4a04 ldr r2, [pc, #16] @ (1000032c ) +1000031a: 7810 ldrb r0, [r2, #0] +1000031c: 1c43 adds r3, r0, #1 +1000031e: b2db uxtb r3, r3 +10000320: 2b18 cmp r3, #24 +10000322: bf28 it cs +10000324: 2310 movcs r3, #16 +10000326: 7013 strb r3, [r2, #0] +10000328: 4770 bx lr +1000032a: bf00 nop +1000032c: 200005a8 .word 0x200005a8 + +10000330 : +10000330: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000334: 6893 ldr r3, [r2, #8] +10000336: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000033a: 6093 str r3, [r2, #8] +1000033c: 4770 bx lr +1000033e: bf00 nop + +10000340 : +10000340: 2100 movs r1, #0 +10000342: 4b04 ldr r3, [pc, #16] @ (10000354 ) +10000344: f103 0220 add.w r2, r3, #32 +10000348: e8c3 1f8f stlb r1, [r3] +1000034c: 3301 adds r3, #1 +1000034e: 4293 cmp r3, r2 +10000350: d1fa bne.n 10000348 +10000352: 4770 bx lr +10000354: 200007b0 .word 0x200007b0 + +10000358 : +10000358: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000035c: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000360: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000364: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000368: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +1000036c: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000370: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000374: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000378: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +1000037c: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000380: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000384: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000388: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +1000038c: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000390: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000394: b662 cpsie i +10000396: 4770 bx lr + +10000398 : +10000398: 2301 movs r3, #1 +1000039a: f000 021f and.w r2, r0, #31 +1000039e: 4093 lsls r3, r2 +100003a0: 0940 lsrs r0, r0, #5 +100003a2: b141 cbz r1, 100003b6 +100003a4: 0080 lsls r0, r0, #2 +100003a6: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003aa: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003ae: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003b2: 6003 str r3, [r0, #0] +100003b4: 4770 bx lr +100003b6: 4a02 ldr r2, [pc, #8] @ (100003c0 ) +100003b8: 3020 adds r0, #32 +100003ba: f842 3020 str.w r3, [r2, r0, lsl #2] +100003be: 4770 bx lr +100003c0: e000e100 .word 0xe000e100 + +100003c4 : +100003c4: b5f8 push {r3, r4, r5, r6, r7, lr} +100003c6: 460d mov r5, r1 +100003c8: f3ef 8710 mrs r7, PRIMASK +100003cc: b672 cpsid i +100003ce: 4e12 ldr r6, [pc, #72] @ (10000418 ) +100003d0: e8d6 2fcf ldaexb r2, [r6] +100003d4: 2301 movs r3, #1 +100003d6: 2a00 cmp r2, #0 +100003d8: d1fa bne.n 100003d0 +100003da: e8c6 3f42 strexb r2, r3, [r6] +100003de: 2a00 cmp r2, #0 +100003e0: d1f6 bne.n 100003d0 +100003e2: f3bf 8f5f dmb sy +100003e6: 4b0d ldr r3, [pc, #52] @ (1000041c ) +100003e8: f100 0410 add.w r4, r0, #16 +100003ec: 689b ldr r3, [r3, #8] +100003ee: 4a0c ldr r2, [pc, #48] @ (10000420 ) +100003f0: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003f4: 4293 cmp r3, r2 +100003f6: d003 beq.n 10000400 +100003f8: 4299 cmp r1, r3 +100003fa: d001 beq.n 10000400 +100003fc: f000 fe8c bl 10001118 +10000400: 4b06 ldr r3, [pc, #24] @ (1000041c ) +10000402: 689b ldr r3, [r3, #8] +10000404: f843 5024 str.w r5, [r3, r4, lsl #2] +10000408: f3bf 8f5f dmb sy +1000040c: 2300 movs r3, #0 +1000040e: e8c6 3f8f stlb r3, [r6] +10000412: f387 8810 msr PRIMASK, r7 +10000416: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000418: 200007b9 .word 0x200007b9 +1000041c: e000ed00 .word 0xe000ed00 +10000420: 10000111 .word 0x10000111 + +10000424 : +10000424: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000428: b083 sub sp, #12 +1000042a: f3ef 8a10 mrs sl, PRIMASK +1000042e: b672 cpsid i +10000430: 4e71 ldr r6, [pc, #452] @ (100005f8 ) +10000432: e8d6 2fcf ldaexb r2, [r6] +10000436: 2301 movs r3, #1 +10000438: 2a00 cmp r2, #0 +1000043a: d1fa bne.n 10000432 +1000043c: e8c6 3f42 strexb r2, r3, [r6] +10000440: 2a00 cmp r2, #0 +10000442: d1f6 bne.n 10000432 +10000444: f3bf 8f5f dmb sy +10000448: 4b6c ldr r3, [pc, #432] @ (100005fc ) +1000044a: f100 0810 add.w r8, r0, #16 +1000044e: 689b ldr r3, [r3, #8] +10000450: 4a6b ldr r2, [pc, #428] @ (10000600 ) +10000452: f853 5028 ldr.w r5, [r3, r8, lsl #2] +10000456: 4295 cmp r5, r2 +10000458: d045 beq.n 100004e6 +1000045a: 428d cmp r5, r1 +1000045c: 460c mov r4, r1 +1000045e: d050 beq.n 10000502 +10000460: 4f68 ldr r7, [pc, #416] @ (10000604 ) +10000462: 1beb subs r3, r5, r7 +10000464: 2b2f cmp r3, #47 @ 0x2f +10000466: d83e bhi.n 100004e6 +10000468: 2101 movs r1, #1 +1000046a: ea4f 1950 mov.w r9, r0, lsr #5 +1000046e: ea4f 0989 mov.w r9, r9, lsl #2 +10000472: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +10000476: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000047a: f000 031f and.w r3, r0, #31 +1000047e: fa01 f003 lsl.w r0, r1, r3 +10000482: f8d9 3000 ldr.w r3, [r9] +10000486: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000048a: ea00 0b03 and.w fp, r0, r3 +1000048e: f3bf 8f5f dmb sy +10000492: f3ef 8105 mrs r1, IPSR +10000496: b2c9 uxtb r1, r1 +10000498: 2900 cmp r1, #0 +1000049a: d034 beq.n 10000506 +1000049c: 4588 cmp r8, r1 +1000049e: d005 beq.n 100004ac +100004a0: e9cd 1000 strd r1, r0, [sp] +100004a4: f000 fe38 bl 10001118 +100004a8: e9dd 1000 ldrd r1, r0, [sp] +100004ac: f025 0e01 bic.w lr, r5, #1 +100004b0: f8de c008 ldr.w ip, [lr, #8] +100004b4: 4564 cmp r4, ip +100004b6: d105 bne.n 100004c4 +100004b8: e089 b.n 100005ce +100004ba: f8d3 c008 ldr.w ip, [r3, #8] +100004be: 4564 cmp r4, ip +100004c0: d031 beq.n 10000526 +100004c2: 469e mov lr, r3 +100004c4: f99e 2006 ldrsb.w r2, [lr, #6] +100004c8: eb02 0342 add.w r3, r2, r2, lsl #1 +100004cc: 2a00 cmp r2, #0 +100004ce: eb07 0383 add.w r3, r7, r3, lsl #2 +100004d2: daf2 bge.n 100004ba +100004d4: 4564 cmp r4, ip +100004d6: d061 beq.n 1000059c +100004d8: f1bb 0f00 cmp.w fp, #0 +100004dc: d020 beq.n 10000520 +100004de: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004e2: f8c9 0000 str.w r0, [r9] +100004e6: 4b45 ldr r3, [pc, #276] @ (100005fc ) +100004e8: 689b ldr r3, [r3, #8] +100004ea: f843 5028 str.w r5, [r3, r8, lsl #2] +100004ee: f3bf 8f5f dmb sy +100004f2: 2300 movs r3, #0 +100004f4: e8c6 3f8f stlb r3, [r6] +100004f8: f38a 8810 msr PRIMASK, sl +100004fc: b003 add sp, #12 +100004fe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000502: 4615 mov r5, r2 +10000504: e7ef b.n 100004e6 +10000506: f025 0e01 bic.w lr, r5, #1 +1000050a: f8de c008 ldr.w ip, [lr, #8] +1000050e: 4564 cmp r4, ip +10000510: d1d8 bne.n 100004c4 +10000512: f99e 4006 ldrsb.w r4, [lr, #6] +10000516: 4673 mov r3, lr +10000518: 2c00 cmp r4, #0 +1000051a: da08 bge.n 1000052e +1000051c: 4615 mov r5, r2 +1000051e: e046 b.n 100005ae +10000520: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000524: e7df b.n 100004e6 +10000526: f993 4006 ldrsb.w r4, [r3, #6] +1000052a: 2c00 cmp r4, #0 +1000052c: db37 blt.n 1000059e +1000052e: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000532: eb07 0c8c add.w ip, r7, ip, lsl #2 +10000536: f89c 1007 ldrb.w r1, [ip, #7] +1000053a: f8dc 2008 ldr.w r2, [ip, #8] +1000053e: 71d9 strb r1, [r3, #7] +10000540: 609a str r2, [r3, #8] +10000542: f99c 2006 ldrsb.w r2, [ip, #6] +10000546: 0061 lsls r1, r4, #1 +10000548: 2a00 cmp r2, #0 +1000054a: 719a strb r2, [r3, #6] +1000054c: db3d blt.n 100005ca +1000054e: f8bc e004 ldrh.w lr, [ip, #4] +10000552: ea5f 5e4e movs.w lr, lr, lsl #21 +10000556: d505 bpl.n 10000564 +10000558: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +1000055c: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000560: f10e 0e1f add.w lr, lr, #31 +10000564: f06f 0c07 mvn.w ip, #7 +10000568: 190a adds r2, r1, r4 +1000056a: ea4f 5e6e mov.w lr, lr, asr #21 +1000056e: 0092 lsls r2, r2, #2 +10000570: eb02 024e add.w r2, r2, lr, lsl #1 +10000574: 3208 adds r2, #8 +10000576: 443a add r2, r7 +10000578: ebac 0c03 sub.w ip, ip, r3 +1000057c: 4462 add r2, ip +1000057e: f3c2 024a ubfx r2, r2, #1, #11 +10000582: ea6f 42c2 mvn.w r2, r2, lsl #19 +10000586: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000058a: 809a strh r2, [r3, #4] +1000058c: 4b1e ldr r3, [pc, #120] @ (10000608 ) +1000058e: 4421 add r1, r4 +10000590: 781a ldrb r2, [r3, #0] +10000592: eb07 0181 add.w r1, r7, r1, lsl #2 +10000596: 701c strb r4, [r3, #0] +10000598: 718a strb r2, [r1, #6] +1000059a: e79d b.n 100004d8 +1000059c: 4673 mov r3, lr +1000059e: b9d9 cbnz r1, 100005d8 +100005a0: 22ff movs r2, #255 @ 0xff +100005a2: f88e 2006 strb.w r2, [lr, #6] +100005a6: f64b 5201 movw r2, #48385 @ 0xbd01 +100005aa: f8ae 2004 strh.w r2, [lr, #4] +100005ae: 4c16 ldr r4, [pc, #88] @ (10000608 ) +100005b0: f64a 22aa movw r2, #43690 @ 0xaaaa +100005b4: f894 c000 ldrb.w ip, [r4] +100005b8: 4619 mov r1, r3 +100005ba: 1bc9 subs r1, r1, r7 +100005bc: 4149 adcs r1, r1 +100005be: 434a muls r2, r1 +100005c0: 0d12 lsrs r2, r2, #20 +100005c2: f883 c006 strb.w ip, [r3, #6] +100005c6: 7022 strb r2, [r4, #0] +100005c8: e786 b.n 100004d8 +100005ca: 4a10 ldr r2, [pc, #64] @ (1000060c ) +100005cc: e7dd b.n 1000058a +100005ce: f99e 4006 ldrsb.w r4, [lr, #6] +100005d2: 4673 mov r3, lr +100005d4: 2c00 cmp r4, #0 +100005d6: daaa bge.n 1000052e +100005d8: 4a0d ldr r2, [pc, #52] @ (10000610 ) +100005da: 4c0e ldr r4, [pc, #56] @ (10000614 ) +100005dc: 1ad2 subs r2, r2, r3 +100005de: 3a08 subs r2, #8 +100005e0: f3c2 310a ubfx r1, r2, #12, #11 +100005e4: ea6f 5101 mvn.w r1, r1, lsl #20 +100005e8: ea6f 5111 mvn.w r1, r1, lsr #20 +100005ec: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005f0: 80da strh r2, [r3, #6] +100005f2: 8099 strh r1, [r3, #4] +100005f4: e770 b.n 100004d8 +100005f6: bf00 nop +100005f8: 200007b9 .word 0x200007b9 +100005fc: e000ed00 .word 0xe000ed00 +10000600: 10000111 .word 0x10000111 +10000604: 200005ac .word 0x200005ac +10000608: 20000854 .word 0x20000854 +1000060c: ffffbd01 .word 0xffffbd01 +10000610: 200005e6 .word 0x200005e6 +10000614: fffff800 .word 0xfffff800 + +10000618 : +10000618: b5f0 push {r4, r5, r6, r7, lr} +1000061a: f3ef 8505 mrs r5, IPSR +1000061e: b2ed uxtb r5, r5 +10000620: f3ef 8c10 mrs ip, PRIMASK +10000624: b672 cpsid i +10000626: 4926 ldr r1, [pc, #152] @ (100006c0 ) +10000628: e8d1 2fcf ldaexb r2, [r1] +1000062c: 2301 movs r3, #1 +1000062e: 2a00 cmp r2, #0 +10000630: d1fa bne.n 10000628 +10000632: e8c1 3f42 strexb r2, r3, [r1] +10000636: 2a00 cmp r2, #0 +10000638: d1f6 bne.n 10000628 +1000063a: f3bf 8f5f dmb sy +1000063e: 4e21 ldr r6, [pc, #132] @ (100006c4 ) +10000640: f040 0e01 orr.w lr, r0, #1 +10000644: 68b4 ldr r4, [r6, #8] +10000646: f64a 23aa movw r3, #43690 @ 0xaaaa +1000064a: f854 7025 ldr.w r7, [r4, r5, lsl #2] +1000064e: 4a1e ldr r2, [pc, #120] @ (100006c8 ) +10000650: 4604 mov r4, r0 +10000652: 1aa4 subs r4, r4, r2 +10000654: 4164 adcs r4, r4 +10000656: 4363 muls r3, r4 +10000658: 0d1b lsrs r3, r3, #20 +1000065a: 4577 cmp r7, lr +1000065c: b25b sxtb r3, r3 +1000065e: d01b beq.n 10000698 +10000660: f992 4006 ldrsb.w r4, [r2, #6] +10000664: 429c cmp r4, r3 +10000666: d01c beq.n 100006a2 +10000668: f992 4012 ldrsb.w r4, [r2, #18] +1000066c: 429c cmp r4, r3 +1000066e: d023 beq.n 100006b8 +10000670: f992 401e ldrsb.w r4, [r2, #30] +10000674: 429c cmp r4, r3 +10000676: d021 beq.n 100006bc +10000678: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +1000067c: 429c cmp r4, r3 +1000067e: bf08 it eq +10000680: 2403 moveq r4, #3 +10000682: d00f beq.n 100006a4 +10000684: 4a11 ldr r2, [pc, #68] @ (100006cc ) +10000686: 2400 movs r4, #0 +10000688: 7815 ldrb r5, [r2, #0] +1000068a: 7013 strb r3, [r2, #0] +1000068c: 7185 strb r5, [r0, #6] +1000068e: e8c1 4f8f stlb r4, [r1] +10000692: f38c 8810 msr PRIMASK, ip +10000696: bdf0 pop {r4, r5, r6, r7, pc} +10000698: 68b2 ldr r2, [r6, #8] +1000069a: 4c0d ldr r4, [pc, #52] @ (100006d0 ) +1000069c: f842 4025 str.w r4, [r2, r5, lsl #2] +100006a0: e7f0 b.n 10000684 +100006a2: 2400 movs r4, #0 +100006a4: eb04 0444 add.w r4, r4, r4, lsl #1 +100006a8: eb02 0284 add.w r2, r2, r4, lsl #2 +100006ac: 24ff movs r4, #255 @ 0xff +100006ae: 7194 strb r4, [r2, #6] +100006b0: f64b 5401 movw r4, #48385 @ 0xbd01 +100006b4: 8094 strh r4, [r2, #4] +100006b6: e7e5 b.n 10000684 +100006b8: 2401 movs r4, #1 +100006ba: e7f3 b.n 100006a4 +100006bc: 2402 movs r4, #2 +100006be: e7f1 b.n 100006a4 +100006c0: 200007b9 .word 0x200007b9 +100006c4: e000ed00 .word 0xe000ed00 +100006c8: 200005ac .word 0x200005ac +100006cc: 20000854 .word 0x20000854 +100006d0: 10000111 .word 0x10000111 + +100006d4 : +100006d4: 4b01 ldr r3, [pc, #4] @ (100006dc ) +100006d6: 440b add r3, r1 +100006d8: 6003 str r3, [r0, #0] +100006da: 4770 bx lr +100006dc: 200007b0 .word 0x200007b0 + +100006e0 : +100006e0: b570 push {r4, r5, r6, lr} +100006e2: 4c10 ldr r4, [pc, #64] @ (10000724 ) +100006e4: 4d10 ldr r5, [pc, #64] @ (10000728 ) +100006e6: 42ac cmp r4, r5 +100006e8: d20e bcs.n 10000708 +100006ea: 26ff movs r6, #255 @ 0xff +100006ec: 6823 ldr r3, [r4, #0] +100006ee: b163 cbz r3, 1000070a +100006f0: f7ff fe12 bl 10000318 +100006f4: 4601 mov r1, r0 +100006f6: 4620 mov r0, r4 +100006f8: f7ff ffec bl 100006d4 +100006fc: 80a6 strh r6, [r4, #4] +100006fe: f3bf 8f5f dmb sy +10000702: 3408 adds r4, #8 +10000704: 42ac cmp r4, r5 +10000706: d3f1 bcc.n 100006ec +10000708: bd70 pop {r4, r5, r6, pc} +1000070a: f7ff fe05 bl 10000318 +1000070e: 4601 mov r1, r0 +10000710: 4620 mov r0, r4 +10000712: f7ff ffdf bl 100006d4 +10000716: 7126 strb r6, [r4, #4] +10000718: f3bf 8f5f dmb sy +1000071c: 3408 adds r4, #8 +1000071e: 42ac cmp r4, r5 +10000720: d3e4 bcc.n 100006ec +10000722: bd70 pop {r4, r5, r6, pc} +10000724: 20000624 .word 0x20000624 +10000728: 2000062c .word 0x2000062c + +1000072c : +1000072c: 4b0d ldr r3, [pc, #52] @ (10000764 ) +1000072e: 681a ldr r2, [r3, #0] +10000730: f3ef 8110 mrs r1, PRIMASK +10000734: b672 cpsid i +10000736: e8d2 cfcf ldaexb ip, [r2] +1000073a: 2001 movs r0, #1 +1000073c: f1bc 0f00 cmp.w ip, #0 +10000740: d1f9 bne.n 10000736 +10000742: e8c2 0f4c strexb ip, r0, [r2] +10000746: f1bc 0f00 cmp.w ip, #0 +1000074a: d1f4 bne.n 10000736 +1000074c: f3bf 8f5f dmb sy +10000750: 2200 movs r2, #0 +10000752: 681b ldr r3, [r3, #0] +10000754: e8c3 2f8f stlb r2, [r3] +10000758: f381 8810 msr PRIMASK, r1 +1000075c: bf40 sev +1000075e: 2000 movs r0, #0 +10000760: 2100 movs r1, #0 +10000762: 4770 bx lr +10000764: 20000848 .word 0x20000848 + +10000768 : +10000768: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000076c: ed2d 8b02 vpush {d8} +10000770: b085 sub sp, #20 +10000772: f3ef 8305 mrs r3, IPSR +10000776: b2db uxtb r3, r3 +10000778: 3b10 subs r3, #16 +1000077a: 089a lsrs r2, r3, #2 +1000077c: bf18 it ne +1000077e: 2201 movne r2, #1 +10000780: f04f 0101 mov.w r1, #1 +10000784: f003 0b03 and.w fp, r3, #3 +10000788: bf18 it ne +1000078a: 4daf ldrne r5, [pc, #700] @ (10000a48 ) +1000078c: 4baf ldr r3, [pc, #700] @ (10000a4c ) +1000078e: bf08 it eq +10000790: 4daf ldreq r5, [pc, #700] @ (10000a50 ) +10000792: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000796: f853 6022 ldr.w r6, [r3, r2, lsl #2] +1000079a: fa01 f20b lsl.w r2, r1, fp +1000079e: f505 5341 add.w r3, r5, #12352 @ 0x3040 +100007a2: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a40 +100007a6: 9201 str r2, [sp, #4] +100007a8: 605a str r2, [r3, #4] +100007aa: e02f b.n 1000080c +100007ac: 88b3 ldrh r3, [r6, #4] +100007ae: 041c lsls r4, r3, #16 +100007b0: f140 8093 bpl.w 100008da +100007b4: 79b3 ldrb r3, [r6, #6] +100007b6: 2b00 cmp r3, #0 +100007b8: f040 80dd bne.w 10000976 +100007bc: f9b6 2008 ldrsh.w r2, [r6, #8] +100007c0: 2a00 cmp r2, #0 +100007c2: f2c0 811e blt.w 10000a02 +100007c6: 6973 ldr r3, [r6, #20] +100007c8: eb02 0242 add.w r2, r2, r2, lsl #1 +100007cc: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007d0: e9d3 4702 ldrd r4, r7, [r3, #8] +100007d4: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007d8: bf08 it eq +100007da: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007de: d00e beq.n 100007fe +100007e0: eb05 018b add.w r1, r5, fp, lsl #2 +100007e4: 6aab ldr r3, [r5, #40] @ 0x28 +100007e6: 690a ldr r2, [r1, #16] +100007e8: 1ad2 subs r2, r2, r3 +100007ea: 1ae3 subs r3, r4, r3 +100007ec: 4293 cmp r3, r2 +100007ee: d305 bcc.n 100007fc +100007f0: 2301 movs r3, #1 +100007f2: 6a2a ldr r2, [r5, #32] +100007f4: fa03 f30b lsl.w r3, r3, fp +100007f8: 4213 tst r3, r2 +100007fa: d100 bne.n 100007fe +100007fc: 610c str r4, [r1, #16] +100007fe: 4628 mov r0, r5 +10000800: f000 faca bl 10000d98 +10000804: 42a0 cmp r0, r4 +10000806: 41b9 sbcs r1, r7 +10000808: f2c0 80fb blt.w 10000a02 +1000080c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000810: 9a01 ldr r2, [sp, #4] +10000812: 2b00 cmp r3, #0 +10000814: 9300 str r3, [sp, #0] +10000816: 63ea str r2, [r5, #60] @ 0x3c +10000818: dbc8 blt.n 100007ac +1000081a: f8d6 8014 ldr.w r8, [r6, #20] +1000081e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000822: 4628 mov r0, r5 +10000824: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000828: e9d7 4a02 ldrd r4, sl, [r7, #8] +1000082c: f000 fab4 bl 10000d98 +10000830: 42a0 cmp r0, r4 +10000832: eb71 010a sbcs.w r1, r1, sl +10000836: dbb9 blt.n 100007ac +10000838: f1ba 0f00 cmp.w sl, #0 +1000083c: f2c0 80c3 blt.w 100009c6 +10000840: e9d7 3104 ldrd r3, r1, [r7, #16] +10000844: 4a83 ldr r2, [pc, #524] @ (10000a54 ) +10000846: 4293 cmp r3, r2 +10000848: f000 80ed beq.w 10000a26 +1000084c: 887a ldrh r2, [r7, #2] +1000084e: f9b6 0008 ldrsh.w r0, [r6, #8] +10000852: b292 uxth r2, r2 +10000854: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000858: 4798 blx r3 +1000085a: 4602 mov r2, r0 +1000085c: 460b mov r3, r1 +1000085e: ea52 0103 orrs.w r1, r2, r3 +10000862: f000 80b0 beq.w 100009c6 +10000866: 2b00 cmp r3, #0 +10000868: f280 80d1 bge.w 10000a0e +1000086c: ebb4 0e02 subs.w lr, r4, r2 +10000870: eb6a 0a03 sbc.w sl, sl, r3 +10000874: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000878: e9c7 ea02 strd lr, sl, [r7, #8] +1000087c: 2b00 cmp r3, #0 +1000087e: db95 blt.n 100007ac +10000880: 6971 ldr r1, [r6, #20] +10000882: eb03 0243 add.w r2, r3, r3, lsl #1 +10000886: eb01 02c2 add.w r2, r1, r2, lsl #3 +1000088a: e9d2 7002 ldrd r7, r0, [r2, #8] +1000088e: 45be cmp lr, r7 +10000890: eb7a 0c00 sbcs.w ip, sl, r0 +10000894: ea4f 0243 mov.w r2, r3, lsl #1 +10000898: db88 blt.n 100007ac +1000089a: 46b4 mov ip, r6 +1000089c: f82c 3f08 strh.w r3, [ip, #8]! +100008a0: e006 b.n 100008b0 +100008a2: eb03 0043 add.w r0, r3, r3, lsl #1 +100008a6: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008aa: 005a lsls r2, r3, #1 +100008ac: e9d0 7002 ldrd r7, r0, [r0, #8] +100008b0: 45be cmp lr, r7 +100008b2: 441a add r2, r3 +100008b4: eb7a 0000 sbcs.w r0, sl, r0 +100008b8: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008bc: db04 blt.n 100008c8 +100008be: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008c2: 46a4 mov ip, r4 +100008c4: 2b00 cmp r3, #0 +100008c6: daec bge.n 100008a2 +100008c8: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008cc: 9b00 ldr r3, [sp, #0] +100008ce: f8ac 3000 strh.w r3, [ip] +100008d2: 88b3 ldrh r3, [r6, #4] +100008d4: 041c lsls r4, r3, #16 +100008d6: f53f af6d bmi.w 100007b4 +100008da: 6933 ldr r3, [r6, #16] +100008dc: f3ef 8210 mrs r2, PRIMASK +100008e0: b672 cpsid i +100008e2: e8d3 0fcf ldaexb r0, [r3] +100008e6: 2101 movs r1, #1 +100008e8: 2800 cmp r0, #0 +100008ea: d1fa bne.n 100008e2 +100008ec: e8c3 1f40 strexb r0, r1, [r3] +100008f0: 2800 cmp r0, #0 +100008f2: d1f6 bne.n 100008e2 +100008f4: f3bf 8f5f dmb sy +100008f8: f64f 74ff movw r4, #65535 @ 0xffff +100008fc: 88b0 ldrh r0, [r6, #4] +100008fe: 2300 movs r3, #0 +10000900: 6931 ldr r1, [r6, #16] +10000902: b200 sxth r0, r0 +10000904: 80b4 strh r4, [r6, #4] +10000906: e8c1 3f8f stlb r3, [r1] +1000090a: f382 8810 msr PRIMASK, r2 +1000090e: 4298 cmp r0, r3 +10000910: f6ff af50 blt.w 100007b4 +10000914: 4607 mov r7, r0 +10000916: 46a9 mov r9, r5 +10000918: 6974 ldr r4, [r6, #20] +1000091a: f106 0808 add.w r8, r6, #8 +1000091e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000922: eb04 03ce add.w r3, r4, lr, lsl #3 +10000926: e9d3 5002 ldrd r5, r0, [r3, #8] +1000092a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000092e: 46c4 mov ip, r8 +10000930: 2b00 cmp r3, #0 +10000932: db13 blt.n 1000095c +10000934: 46b2 mov sl, r6 +10000936: 9700 str r7, [sp, #0] +10000938: e004 b.n 10000944 +1000093a: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +1000093e: 4694 mov ip, r2 +10000940: 2b00 cmp r3, #0 +10000942: db09 blt.n 10000958 +10000944: eb03 0643 add.w r6, r3, r3, lsl #1 +10000948: eb04 02c6 add.w r2, r4, r6, lsl #3 +1000094c: e9d2 7102 ldrd r7, r1, [r2, #8] +10000950: 42bd cmp r5, r7 +10000952: eb70 0101 sbcs.w r1, r0, r1 +10000956: daf0 bge.n 1000093a +10000958: 4656 mov r6, sl +1000095a: 9f00 ldr r7, [sp, #0] +1000095c: f8ac 7000 strh.w r7, [ip] +10000960: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000964: f824 303e strh.w r3, [r4, lr, lsl #3] +10000968: 2f00 cmp r7, #0 +1000096a: dad8 bge.n 1000091e +1000096c: 79b3 ldrb r3, [r6, #6] +1000096e: 464d mov r5, r9 +10000970: 2b00 cmp r3, #0 +10000972: f43f af23 beq.w 100007bc +10000976: 2300 movs r3, #0 +10000978: 71b3 strb r3, [r6, #6] +1000097a: f9b6 3008 ldrsh.w r3, [r6, #8] +1000097e: f106 0808 add.w r8, r6, #8 +10000982: 1c58 adds r0, r3, #1 +10000984: d03d beq.n 10000a02 +10000986: 461a mov r2, r3 +10000988: 6977 ldr r7, [r6, #20] +1000098a: e003 b.n 10000994 +1000098c: 4680 mov r8, r0 +1000098e: 1c59 adds r1, r3, #1 +10000990: f43f af16 beq.w 100007c0 +10000994: eb03 0143 add.w r1, r3, r3, lsl #1 +10000998: eb07 00c1 add.w r0, r7, r1, lsl #3 +1000099c: f8b0 c002 ldrh.w ip, [r0, #2] +100009a0: 461c mov r4, r3 +100009a2: f41c 4f00 tst.w ip, #32768 @ 0x8000 +100009a6: 469e mov lr, r3 +100009a8: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009ac: d0ee beq.n 1000098c +100009ae: 4294 cmp r4, r2 +100009b0: ed80 8b02 vstr d8, [r0, #8] +100009b4: d005 beq.n 100009c2 +100009b6: f8a8 3000 strh.w r3, [r8] +100009ba: 8932 ldrh r2, [r6, #8] +100009bc: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009c0: 8134 strh r4, [r6, #8] +100009c2: 4672 mov r2, lr +100009c4: e7e3 b.n 1000098e +100009c6: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009ca: 8133 strh r3, [r6, #8] +100009cc: 6933 ldr r3, [r6, #16] +100009ce: f3ef 8210 mrs r2, PRIMASK +100009d2: b672 cpsid i +100009d4: e8d3 0fcf ldaexb r0, [r3] +100009d8: 2101 movs r1, #1 +100009da: 2800 cmp r0, #0 +100009dc: d1fa bne.n 100009d4 +100009de: e8c3 1f40 strexb r0, r1, [r3] +100009e2: 2800 cmp r0, #0 +100009e4: d1f6 bne.n 100009d4 +100009e6: f3bf 8f5f dmb sy +100009ea: 8873 ldrh r3, [r6, #2] +100009ec: 6931 ldr r1, [r6, #16] +100009ee: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009f2: 9b00 ldr r3, [sp, #0] +100009f4: 8073 strh r3, [r6, #2] +100009f6: 2300 movs r3, #0 +100009f8: e8c1 3f8f stlb r3, [r1] +100009fc: f382 8810 msr PRIMASK, r2 +10000a00: e6d4 b.n 100007ac +10000a02: bf40 sev +10000a04: b005 add sp, #20 +10000a06: ecbd 8b02 vpop {d8} +10000a0a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a0e: 4628 mov r0, r5 +10000a10: e9cd 2302 strd r2, r3, [sp, #8] +10000a14: f000 f9c0 bl 10000d98 +10000a18: 9a02 ldr r2, [sp, #8] +10000a1a: 9b03 ldr r3, [sp, #12] +10000a1c: eb10 0e02 adds.w lr, r0, r2 +10000a20: eb43 0a01 adc.w sl, r3, r1 +10000a24: e726 b.n 10000874 +10000a26: 4608 mov r0, r1 +10000a28: 690b ldr r3, [r1, #16] +10000a2a: 9102 str r1, [sp, #8] +10000a2c: 4798 blx r3 +10000a2e: 2800 cmp r0, #0 +10000a30: d0c9 beq.n 100009c6 +10000a32: 9902 ldr r1, [sp, #8] +10000a34: e9d1 2300 ldrd r2, r3, [r1] +10000a38: e711 b.n 1000085e +10000a3a: bf00 nop +10000a3c: f3af 8000 nop.w +10000a40: ffffffff .word 0xffffffff +10000a44: ffffffff .word 0xffffffff +10000a48: 400b8000 .word 0x400b8000 +10000a4c: 20000828 .word 0x20000828 +10000a50: 400b0000 .word 0x400b0000 +10000a54: 10000769 .word 0x10000769 + +10000a58 : +10000a58: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a5c: 4c36 ldr r4, [pc, #216] @ (10000b38 ) +10000a5e: 6925 ldr r5, [r4, #16] +10000a60: b12d cbz r5, 10000a6e +10000a62: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a66: 210a movs r1, #10 +10000a68: 4834 ldr r0, [pc, #208] @ (10000b3c ) +10000a6a: f7ff be33 b.w 100006d4 +10000a6e: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b54 +10000a72: 2103 movs r1, #3 +10000a74: 4640 mov r0, r8 +10000a76: f000 f97d bl 10000d74 +10000a7a: 2603 movs r6, #3 +10000a7c: f8c4 800c str.w r8, [r4, #12] +10000a80: f7ff fc4a bl 10000318 +10000a84: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a88: 4b2d ldr r3, [pc, #180] @ (10000b40 ) +10000a8a: 7026 strb r6, [r4, #0] +10000a8c: 4403 add r3, r0 +10000a8e: 6123 str r3, [r4, #16] +10000a90: f8dc 3000 ldr.w r3, [ip] +10000a94: 210f movs r1, #15 +10000a96: 7063 strb r3, [r4, #1] +10000a98: 6963 ldr r3, [r4, #20] +10000a9a: 8061 strh r1, [r4, #2] +10000a9c: 831d strh r5, [r3, #24] +10000a9e: f04f 0504 mov.w r5, #4 +10000aa2: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000aa6: f04f 0505 mov.w r5, #5 +10000aaa: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000aae: f04f 0506 mov.w r5, #6 +10000ab2: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000ab6: f04f 0507 mov.w r5, #7 +10000aba: 210e movs r1, #14 +10000abc: f64f 72ff movw r2, #65535 @ 0xffff +10000ac0: 2708 movs r7, #8 +10000ac2: f04f 0e0a mov.w lr, #10 +10000ac6: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000aca: f04f 0901 mov.w r9, #1 +10000ace: f04f 0c0c mov.w ip, #12 +10000ad2: f04f 0b02 mov.w fp, #2 +10000ad6: f04f 0a09 mov.w sl, #9 +10000ada: 200d movs r0, #13 +10000adc: f04f 050b mov.w r5, #11 +10000ae0: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000ae4: 4917 ldr r1, [pc, #92] @ (10000b44 ) +10000ae6: 80a2 strh r2, [r4, #4] +10000ae8: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000aec: 60a1 str r1, [r4, #8] +10000aee: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000af2: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000af6: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000afa: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000afe: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000b02: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000b06: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b0a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b0e: 801a strh r2, [r3, #0] +10000b10: 4b0d ldr r3, [pc, #52] @ (10000b48 ) +10000b12: 4630 mov r0, r6 +10000b14: f8c8 7020 str.w r7, [r8, #32] +10000b18: 490c ldr r1, [pc, #48] @ (10000b4c ) +10000b1a: 60dc str r4, [r3, #12] +10000b1c: f7ff fc52 bl 100003c4 +10000b20: 4649 mov r1, r9 +10000b22: 4630 mov r0, r6 +10000b24: f7ff fc38 bl 10000398 +10000b28: 4b09 ldr r3, [pc, #36] @ (10000b50 ) +10000b2a: 210a movs r1, #10 +10000b2c: 641f str r7, [r3, #64] @ 0x40 +10000b2e: 4803 ldr r0, [pc, #12] @ (10000b3c ) +10000b30: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b34: f7ff bdce b.w 100006d4 +10000b38: 200005f4 .word 0x200005f4 +10000b3c: 20000848 .word 0x20000848 +10000b40: 200007b0 .word 0x200007b0 +10000b44: 0010ffff .word 0x0010ffff +10000b48: 20000828 .word 0x20000828 +10000b4c: 10000769 .word 0x10000769 +10000b50: 400b2000 .word 0x400b2000 +10000b54: 400b0000 .word 0x400b0000 + +10000b58 : +10000b58: 4601 mov r1, r0 +10000b5a: b5f0 push {r4, r5, r6, r7, lr} +10000b5c: 6900 ldr r0, [r0, #16] +10000b5e: f3ef 8710 mrs r7, PRIMASK +10000b62: b672 cpsid i +10000b64: e8d0 5fcf ldaexb r5, [r0] +10000b68: 2401 movs r4, #1 +10000b6a: 2d00 cmp r5, #0 +10000b6c: d1fa bne.n 10000b64 +10000b6e: e8c0 4f45 strexb r5, r4, [r0] +10000b72: 2d00 cmp r5, #0 +10000b74: d1f6 bne.n 10000b64 +10000b76: f3bf 8f5f dmb sy +10000b7a: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b7e: 694c ldr r4, [r1, #20] +10000b80: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b84: f1be 0f00 cmp.w lr, #0 +10000b88: ea4f 05cc mov.w r5, ip, lsl #3 +10000b8c: 6908 ldr r0, [r1, #16] +10000b8e: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b92: db3c blt.n 10000c0e +10000b94: 5b66 ldrh r6, [r4, r5] +10000b96: 804e strh r6, [r1, #2] +10000b98: 2600 movs r6, #0 +10000b9a: e8c0 6f8f stlb r6, [r0] +10000b9e: f387 8810 msr PRIMASK, r7 +10000ba2: f8bc 0002 ldrh.w r0, [ip, #2] +10000ba6: e9cc 2302 strd r2, r3, [ip, #8] +10000baa: 3001 adds r0, #1 +10000bac: f3c0 000e ubfx r0, r0, #0, #15 +10000bb0: 2801 cmp r0, #1 +10000bb2: bf38 it cc +10000bb4: 2001 movcc r0, #1 +10000bb6: 9b05 ldr r3, [sp, #20] +10000bb8: f8ac 0002 strh.w r0, [ip, #2] +10000bbc: f8cc 3010 str.w r3, [ip, #16] +10000bc0: 9b06 ldr r3, [sp, #24] +10000bc2: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bc6: f8cc 3014 str.w r3, [ip, #20] +10000bca: 690b ldr r3, [r1, #16] +10000bcc: f3ef 8210 mrs r2, PRIMASK +10000bd0: b672 cpsid i +10000bd2: e8d3 cfcf ldaexb ip, [r3] +10000bd6: 2701 movs r7, #1 +10000bd8: f1bc 0f00 cmp.w ip, #0 +10000bdc: d1f9 bne.n 10000bd2 +10000bde: e8c3 7f4c strexb ip, r7, [r3] +10000be2: f1bc 0f00 cmp.w ip, #0 +10000be6: d1f4 bne.n 10000bd2 +10000be8: f3bf 8f5f dmb sy +10000bec: 888b ldrh r3, [r1, #4] +10000bee: 5363 strh r3, [r4, r5] +10000bf0: f8a1 e004 strh.w lr, [r1, #4] +10000bf4: 690b ldr r3, [r1, #16] +10000bf6: e8c3 6f8f stlb r6, [r3] +10000bfa: f382 8810 msr PRIMASK, r2 +10000bfe: 2201 movs r2, #1 +10000c00: 68cb ldr r3, [r1, #12] +10000c02: 7809 ldrb r1, [r1, #0] +10000c04: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c08: 408a lsls r2, r1 +10000c0a: 605a str r2, [r3, #4] +10000c0c: bdf0 pop {r4, r5, r6, r7, pc} +10000c0e: 2300 movs r3, #0 +10000c10: e8c0 3f8f stlb r3, [r0] +10000c14: f387 8810 msr PRIMASK, r7 +10000c18: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c1c: bdf0 pop {r4, r5, r6, r7, pc} +10000c1e: bf00 nop + +10000c20 : +10000c20: 4603 mov r3, r0 +10000c22: 8940 ldrh r0, [r0, #10] +10000c24: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c28: dd37 ble.n 10000c9a +10000c2a: 6958 ldr r0, [r3, #20] +10000c2c: 140a asrs r2, r1, #16 +10000c2e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c32: b510 push {r4, lr} +10000c34: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c38: 691c ldr r4, [r3, #16] +10000c3a: f3ef 8c10 mrs ip, PRIMASK +10000c3e: b672 cpsid i +10000c40: e8d4 efcf ldaexb lr, [r4] +10000c44: 2201 movs r2, #1 +10000c46: f1be 0f00 cmp.w lr, #0 +10000c4a: d1f9 bne.n 10000c40 +10000c4c: e8c4 2f4e strexb lr, r2, [r4] +10000c50: f1be 0f00 cmp.w lr, #0 +10000c54: d1f4 bne.n 10000c40 +10000c56: f3bf 8f5f dmb sy +10000c5a: 8842 ldrh r2, [r0, #2] +10000c5c: b289 uxth r1, r1 +10000c5e: b292 uxth r2, r2 +10000c60: 428a cmp r2, r1 +10000c62: d007 beq.n 10000c74 +10000c64: 2200 movs r2, #0 +10000c66: 691b ldr r3, [r3, #16] +10000c68: e8c3 2f8f stlb r2, [r3] +10000c6c: f38c 8810 msr PRIMASK, ip +10000c70: 2000 movs r0, #0 +10000c72: bd10 pop {r4, pc} +10000c74: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c78: 8042 strh r2, [r0, #2] +10000c7a: 2101 movs r1, #1 +10000c7c: 2200 movs r2, #0 +10000c7e: 6918 ldr r0, [r3, #16] +10000c80: 7199 strb r1, [r3, #6] +10000c82: e8c0 2f8f stlb r2, [r0] +10000c86: f38c 8810 msr PRIMASK, ip +10000c8a: 781c ldrb r4, [r3, #0] +10000c8c: 68da ldr r2, [r3, #12] +10000c8e: 4608 mov r0, r1 +10000c90: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c94: 40a1 lsls r1, r4 +10000c96: 6059 str r1, [r3, #4] +10000c98: bd10 pop {r4, pc} +10000c9a: 2000 movs r0, #0 +10000c9c: 4770 bx lr +10000c9e: bf00 nop + +10000ca0 : +10000ca0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000ca4: 4606 mov r6, r0 +10000ca6: 460d mov r5, r1 +10000ca8: b083 sub sp, #12 +10000caa: f3ef 8405 mrs r4, IPSR +10000cae: b2e4 uxtb r4, r4 +10000cb0: b13c cbz r4, 10000cc2 +10000cb2: 4b2d ldr r3, [pc, #180] @ (10000d68 ) +10000cb4: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cb6: 42aa cmp r2, r5 +10000cb8: d21c bcs.n 10000cf4 +10000cba: 2000 movs r0, #0 +10000cbc: b003 add sp, #12 +10000cbe: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cc2: 4f2a ldr r7, [pc, #168] @ (10000d6c ) +10000cc4: f8d7 900c ldr.w r9, [r7, #12] +10000cc8: f897 8000 ldrb.w r8, [r7] +10000ccc: 4648 mov r0, r9 +10000cce: f000 f863 bl 10000d98 +10000cd2: f108 0804 add.w r8, r8, #4 +10000cd6: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000cda: 1a1b subs r3, r3, r0 +10000cdc: 1a30 subs r0, r6, r0 +10000cde: eb65 0101 sbc.w r1, r5, r1 +10000ce2: 4298 cmp r0, r3 +10000ce4: f171 0100 sbcs.w r1, r1, #0 +10000ce8: db10 blt.n 10000d0c +10000cea: bf20 wfe +10000cec: 4b1e ldr r3, [pc, #120] @ (10000d68 ) +10000cee: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cf0: 42aa cmp r2, r5 +10000cf2: d3e2 bcc.n 10000cba +10000cf4: bf14 ite ne +10000cf6: 2401 movne r4, #1 +10000cf8: 2400 moveq r4, #0 +10000cfa: 6a9b ldr r3, [r3, #40] @ 0x28 +10000cfc: 42b3 cmp r3, r6 +10000cfe: bf34 ite cc +10000d00: 4620 movcc r0, r4 +10000d02: f044 0001 orrcs.w r0, r4, #1 +10000d06: b003 add sp, #12 +10000d08: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d0c: f000 f84c bl 10000da8 +10000d10: 4286 cmp r6, r0 +10000d12: eb65 0101 sbc.w r1, r5, r1 +10000d16: 2900 cmp r1, #0 +10000d18: db14 blt.n 10000d44 +10000d1a: 4b15 ldr r3, [pc, #84] @ (10000d70 ) +10000d1c: 4638 mov r0, r7 +10000d1e: e9cd 3400 strd r3, r4, [sp] +10000d22: 4632 mov r2, r6 +10000d24: 462b mov r3, r5 +10000d26: f7ff ff17 bl 10000b58 +10000d2a: 1e01 subs r1, r0, #0 +10000d2c: dd0a ble.n 10000d44 +10000d2e: 4b0e ldr r3, [pc, #56] @ (10000d68 ) +10000d30: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d32: 42aa cmp r2, r5 +10000d34: d316 bcc.n 10000d64 +10000d36: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d38: 42b3 cmp r3, r6 +10000d3a: d311 bcc.n 10000d60 +10000d3c: 480b ldr r0, [pc, #44] @ (10000d6c ) +10000d3e: f7ff ff6f bl 10000c20 +10000d42: e7b6 b.n 10000cb2 +10000d44: 4b08 ldr r3, [pc, #32] @ (10000d68 ) +10000d46: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d48: 42ac cmp r4, r5 +10000d4a: d3b6 bcc.n 10000cba +10000d4c: 1b64 subs r4, r4, r5 +10000d4e: bf18 it ne +10000d50: 2401 movne r4, #1 +10000d52: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d54: 42b3 cmp r3, r6 +10000d56: bf34 ite cc +10000d58: 4620 movcc r0, r4 +10000d5a: f044 0001 orrcs.w r0, r4, #1 +10000d5e: e7ad b.n 10000cbc +10000d60: 42aa cmp r2, r5 +10000d62: d1eb bne.n 10000d3c +10000d64: bf20 wfe +10000d66: e7e9 b.n 10000d3c +10000d68: 400b0000 .word 0x400b0000 +10000d6c: 200005f4 .word 0x200005f4 +10000d70: 1000072d .word 0x1000072d + +10000d74 : +10000d74: b410 push {r4} +10000d76: 4b05 ldr r3, [pc, #20] @ (10000d8c ) +10000d78: 4c05 ldr r4, [pc, #20] @ (10000d90 ) +10000d7a: 4a06 ldr r2, [pc, #24] @ (10000d94 ) +10000d7c: 42a0 cmp r0, r4 +10000d7e: bf14 ite ne +10000d80: 4618 movne r0, r3 +10000d82: 1c58 addeq r0, r3, #1 +10000d84: f85d 4b04 ldr.w r4, [sp], #4 +10000d88: f7ff ba9a b.w 100002c0 +10000d8c: 200007d8 .word 0x200007d8 +10000d90: 400b8000 .word 0x400b8000 +10000d94: 100034c8 .word 0x100034c8 + +10000d98 : +10000d98: 4603 mov r3, r0 +10000d9a: 6a41 ldr r1, [r0, #36] @ 0x24 +10000d9c: 460a mov r2, r1 +10000d9e: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da0: 6a59 ldr r1, [r3, #36] @ 0x24 +10000da2: 428a cmp r2, r1 +10000da4: d1fa bne.n 10000d9c +10000da6: 4770 bx lr + +10000da8 : +10000da8: 4b03 ldr r3, [pc, #12] @ (10000db8 ) +10000daa: 6a59 ldr r1, [r3, #36] @ 0x24 +10000dac: 460a mov r2, r1 +10000dae: 6a98 ldr r0, [r3, #40] @ 0x28 +10000db0: 6a59 ldr r1, [r3, #36] @ 0x24 +10000db2: 4291 cmp r1, r2 +10000db4: d1fa bne.n 10000dac +10000db6: 4770 bx lr +10000db8: 400b0000 .word 0x400b0000 + +10000dbc : +10000dbc: b430 push {r4, r5} +10000dbe: 4a15 ldr r2, [pc, #84] @ (10000e14 ) +10000dc0: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc2: 469c mov ip, r3 +10000dc4: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dc6: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dc8: 4563 cmp r3, ip +10000dca: d1fa bne.n 10000dc2 +10000dcc: 1902 adds r2, r0, r4 +10000dce: 4159 adcs r1, r3 +10000dd0: f04f 0500 mov.w r5, #0 +10000dd4: bf28 it cs +10000dd6: 2501 movcs r5, #1 +10000dd8: 4b0e ldr r3, [pc, #56] @ (10000e14 ) +10000dda: 6a5b ldr r3, [r3, #36] @ 0x24 +10000ddc: b1b5 cbz r5, 10000e0c +10000dde: 1c5a adds r2, r3, #1 +10000de0: bf08 it eq +10000de2: 461a moveq r2, r3 +10000de4: d008 beq.n 10000df8 +10000de6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000dea: 460a mov r2, r1 +10000dec: 4809 ldr r0, [pc, #36] @ (10000e14 ) +10000dee: 6a43 ldr r3, [r0, #36] @ 0x24 +10000df0: 428b cmp r3, r1 +10000df2: d3fc bcc.n 10000dee +10000df4: 428b cmp r3, r1 +10000df6: d107 bne.n 10000e08 +10000df8: 4906 ldr r1, [pc, #24] @ (10000e14 ) +10000dfa: e002 b.n 10000e02 +10000dfc: 6a48 ldr r0, [r1, #36] @ 0x24 +10000dfe: 4298 cmp r0, r3 +10000e00: d102 bne.n 10000e08 +10000e02: 6a88 ldr r0, [r1, #40] @ 0x28 +10000e04: 4290 cmp r0, r2 +10000e06: d3f9 bcc.n 10000dfc +10000e08: bc30 pop {r4, r5} +10000e0a: 4770 bx lr +10000e0c: 4299 cmp r1, r3 +10000e0e: d8ed bhi.n 10000dec +10000e10: e7f0 b.n 10000df4 +10000e12: bf00 nop +10000e14: 400b0000 .word 0x400b0000 + +10000e18 : +10000e18: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e1a: 4605 mov r5, r0 +10000e1c: 2006 movs r0, #6 +10000e1e: 460e mov r6, r1 +10000e20: f000 f8e4 bl 10000fec +10000e24: 2800 cmp r0, #0 +10000e26: d042 beq.n 10000eae +10000e28: 4a35 ldr r2, [pc, #212] @ (10000f00 ) +10000e2a: 4836 ldr r0, [pc, #216] @ (10000f04 ) +10000e2c: 4295 cmp r5, r2 +10000e2e: bf14 ite ne +10000e30: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e34: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e38: 4b33 ldr r3, [pc, #204] @ (10000f08 ) +10000e3a: 4934 ldr r1, [pc, #208] @ (10000f0c ) +10000e3c: 6002 str r2, [r0, #0] +10000e3e: 601a str r2, [r3, #0] +10000e40: 688c ldr r4, [r1, #8] +10000e42: ea32 0404 bics.w r4, r2, r4 +10000e46: d1fb bne.n 10000e40 +10000e48: 4b2d ldr r3, [pc, #180] @ (10000f00 ) +10000e4a: f44f 7180 mov.w r1, #256 @ 0x100 +10000e4e: 1aeb subs r3, r5, r3 +10000e50: fab3 f383 clz r3, r3 +10000e54: 4a2e ldr r2, [pc, #184] @ (10000f10 ) +10000e56: 095b lsrs r3, r3, #5 +10000e58: 2006 movs r0, #6 +10000e5a: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e5e: f000 f8c5 bl 10000fec +10000e62: 00c3 lsls r3, r0, #3 +10000e64: fbb3 f3f6 udiv r3, r3, r6 +10000e68: 3301 adds r3, #1 +10000e6a: 09da lsrs r2, r3, #7 +10000e6c: d120 bne.n 10000eb0 +10000e6e: 2640 movs r6, #64 @ 0x40 +10000e70: 2101 movs r1, #1 +10000e72: 6269 str r1, [r5, #36] @ 0x24 +10000e74: 62aa str r2, [r5, #40] @ 0x28 +10000e76: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e78: 07fb lsls r3, r7, #31 +10000e7a: d422 bmi.n 10000ec2 +10000e7c: 462b mov r3, r5 +10000e7e: 2200 movs r2, #0 +10000e80: f853 1f2c ldr.w r1, [r3, #44]! +10000e84: 2006 movs r0, #6 +10000e86: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e8a: 6022 str r2, [r4, #0] +10000e8c: 632f str r7, [r5, #48] @ 0x30 +10000e8e: f000 f8ad bl 10000fec +10000e92: f240 3101 movw r1, #769 @ 0x301 +10000e96: 2203 movs r2, #3 +10000e98: 0080 lsls r0, r0, #2 +10000e9a: fbb0 f0f6 udiv r0, r0, r6 +10000e9e: 6aeb ldr r3, [r5, #44] @ 0x2c +10000ea0: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000ea4: f003 037e and.w r3, r3, #126 @ 0x7e +10000ea8: 6023 str r3, [r4, #0] +10000eaa: 6329 str r1, [r5, #48] @ 0x30 +10000eac: 64aa str r2, [r5, #72] @ 0x48 +10000eae: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000eb0: f64f 71fe movw r1, #65534 @ 0xfffe +10000eb4: 428a cmp r2, r1 +10000eb6: d91b bls.n 10000ef0 +10000eb8: 4622 mov r2, r4 +10000eba: f64f 71ff movw r1, #65535 @ 0xffff +10000ebe: 4e15 ldr r6, [pc, #84] @ (10000f14 ) +10000ec0: e7d7 b.n 10000e72 +10000ec2: f240 3201 movw r2, #769 @ 0x301 +10000ec6: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000eca: 631a str r2, [r3, #48] @ 0x30 +10000ecc: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ece: 6aac ldr r4, [r5, #40] @ 0x28 +10000ed0: 2006 movs r0, #6 +10000ed2: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ed6: f000 f889 bl 10000fec +10000eda: 4b0f ldr r3, [pc, #60] @ (10000f18 ) +10000edc: 02a4 lsls r4, r4, #10 +10000ede: fba3 2300 umull r2, r3, r3, r0 +10000ee2: 0adb lsrs r3, r3, #11 +10000ee4: 2100 movs r1, #0 +10000ee6: fbb4 f0f3 udiv r0, r4, r3 +10000eea: f7ff ff67 bl 10000dbc +10000eee: e7c5 b.n 10000e7c +10000ef0: f3c3 0345 ubfx r3, r3, #1, #6 +10000ef4: 4611 mov r1, r2 +10000ef6: eb03 1682 add.w r6, r3, r2, lsl #6 +10000efa: 461a mov r2, r3 +10000efc: e7b9 b.n 10000e72 +10000efe: bf00 nop +10000f00: 40078000 .word 0x40078000 +10000f04: 40022000 .word 0x40022000 +10000f08: 40023000 .word 0x40023000 +10000f0c: 40020000 .word 0x40020000 +10000f10: 2000084c .word 0x2000084c +10000f14: 003fffc0 .word 0x003fffc0 +10000f18: 8f2b7b75 .word 0x8f2b7b75 + +10000f1c : +10000f1c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f20: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f24: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f28: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f2c: b5f0 push {r4, r5, r6, r7, lr} +10000f2e: 4616 mov r6, r2 +10000f30: f8dc 2004 ldr.w r2, [ip, #4] +10000f34: 1f05 subs r5, r0, #4 +10000f36: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f3a: bf38 it cc +10000f3c: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f40: b2ed uxtb r5, r5 +10000f42: bf38 it cc +10000f44: f8cc 2004 strcc.w r2, [ip, #4] +10000f48: 2d01 cmp r5, #1 +10000f4a: d92a bls.n 10000fa2 +10000f4c: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f50: 4c25 ldr r4, [pc, #148] @ (10000fe8 ) +10000f52: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f56: 6017 str r7, [r2, #0] +10000f58: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f5c: b9b2 cbnz r2, 10000f8c +10000f5e: f8dc 2000 ldr.w r2, [ip] +10000f62: 2d01 cmp r5, #1 +10000f64: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f68: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f6c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f70: 6032 str r2, [r6, #0] +10000f72: d92a bls.n 10000fca +10000f74: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f78: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f7c: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f80: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f84: 6011 str r1, [r2, #0] +10000f86: f8cc 3004 str.w r3, [ip, #4] +10000f8a: bdf0 pop {r4, r5, r6, r7, pc} +10000f8c: 6967 ldr r7, [r4, #20] +10000f8e: fbb7 fef2 udiv lr, r7, r2 +10000f92: f10e 0e01 add.w lr, lr, #1 +10000f96: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000f9a: f1be 0e03 subs.w lr, lr, #3 +10000f9e: d2fc bcs.n 10000f9a +10000fa0: e7dd b.n 10000f5e +10000fa2: 2901 cmp r1, #1 +10000fa4: d1d2 bne.n 10000f4c +10000fa6: 2403 movs r4, #3 +10000fa8: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fac: 6014 str r4, [r2, #0] +10000fae: f8dc 2008 ldr.w r2, [ip, #8] +10000fb2: 07d2 lsls r2, r2, #31 +10000fb4: d5fb bpl.n 10000fae +10000fb6: f8dc 2000 ldr.w r2, [ip] +10000fba: 4c0b ldr r4, [pc, #44] @ (10000fe8 ) +10000fbc: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fc0: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fc4: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fc8: 6032 str r2, [r6, #0] +10000fca: 2201 movs r2, #1 +10000fcc: f8dc 5000 ldr.w r5, [ip] +10000fd0: 404d eors r5, r1 +10000fd2: f005 0503 and.w r5, r5, #3 +10000fd6: 6035 str r5, [r6, #0] +10000fd8: fa02 f101 lsl.w r1, r2, r1 +10000fdc: f8dc 2008 ldr.w r2, [ip, #8] +10000fe0: 420a tst r2, r1 +10000fe2: d0fb beq.n 10000fdc +10000fe4: e7c6 b.n 10000f74 +10000fe6: bf00 nop +10000fe8: 200007dc .word 0x200007dc + +10000fec : +10000fec: 4b01 ldr r3, [pc, #4] @ (10000ff4 ) +10000fee: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000ff2: 4770 bx lr +10000ff4: 200007dc .word 0x200007dc + +10000ff8 : +10000ff8: b470 push {r4, r5, r6} +10000ffa: 9d03 ldr r5, [sp, #12] +10000ffc: 6804 ldr r4, [r0, #0] +10000ffe: 032d lsls r5, r5, #12 +10001000: ea45 4503 orr.w r5, r5, r3, lsl #16 +10001004: 4b1b ldr r3, [pc, #108] @ (10001074 ) +10001006: 2c00 cmp r4, #0 +10001008: fbb3 f3f1 udiv r3, r3, r1 +1000100c: fbb2 f6f3 udiv r6, r2, r3 +10001010: db1f blt.n 10001052 +10001012: 4a19 ldr r2, [pc, #100] @ (10001078 ) +10001014: 4b19 ldr r3, [pc, #100] @ (1000107c ) +10001016: 4290 cmp r0, r2 +10001018: bf14 ite ne +1000101a: f44f 4280 movne.w r2, #16384 @ 0x4000 +1000101e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10001022: 4c17 ldr r4, [pc, #92] @ (10001080 ) +10001024: 601a str r2, [r3, #0] +10001026: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000102a: 601a str r2, [r3, #0] +1000102c: 68a3 ldr r3, [r4, #8] +1000102e: ea32 0303 bics.w r3, r2, r3 +10001032: d1fb bne.n 1000102c +10001034: 2221 movs r2, #33 @ 0x21 +10001036: f500 5340 add.w r3, r0, #12288 @ 0x3000 +1000103a: 3304 adds r3, #4 +1000103c: 6001 str r1, [r0, #0] +1000103e: 6086 str r6, [r0, #8] +10001040: 601a str r2, [r3, #0] +10001042: 6802 ldr r2, [r0, #0] +10001044: 2a00 cmp r2, #0 +10001046: dafc bge.n 10001042 +10001048: 2208 movs r2, #8 +1000104a: 60c5 str r5, [r0, #12] +1000104c: 601a str r2, [r3, #0] +1000104e: bc70 pop {r4, r5, r6} +10001050: 4770 bx lr +10001052: 6803 ldr r3, [r0, #0] +10001054: f003 033f and.w r3, r3, #63 @ 0x3f +10001058: 428b cmp r3, r1 +1000105a: d1da bne.n 10001012 +1000105c: 6883 ldr r3, [r0, #8] +1000105e: f3c3 030b ubfx r3, r3, #0, #12 +10001062: 42b3 cmp r3, r6 +10001064: d1d5 bne.n 10001012 +10001066: 68c3 ldr r3, [r0, #12] +10001068: f403 23ee and.w r3, r3, #487424 @ 0x77000 +1000106c: 42ab cmp r3, r5 +1000106e: d1d0 bne.n 10001012 +10001070: e7ed b.n 1000104e +10001072: bf00 nop +10001074: 00b71b00 .word 0x00b71b00 +10001078: 40058000 .word 0x40058000 +1000107c: 40022000 .word 0x40022000 +10001080: 40020000 .word 0x40020000 + +10001084 : +10001084: 2301 movs r3, #1 +10001086: eb00 0040 add.w r0, r0, r0, lsl #1 +1000108a: 0080 lsls r0, r0, #2 +1000108c: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001090: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001094: 6041 str r1, [r0, #4] +10001096: 6003 str r3, [r0, #0] +10001098: 4770 bx lr +1000109a: bf00 nop + +1000109c : +1000109c: 2300 movs r3, #0 +1000109e: 8adb ldrh r3, [r3, #22] +100010a0: 2200 movs r2, #0 +100010a2: e842 f200 tt r2, r2 +100010a6: 0252 lsls r2, r2, #9 +100010a8: d401 bmi.n 100010ae +100010aa: 2110 movs r1, #16 +100010ac: 4718 bx r3 +100010ae: 2104 movs r1, #4 +100010b0: 4718 bx r3 +100010b2: bf00 nop + +100010b4 : +100010b4: 4a03 ldr r2, [pc, #12] @ (100010c4 ) +100010b6: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010ba: 2b00 cmp r3, #0 +100010bc: d0fb beq.n 100010b6 +100010be: f3bf 8f5f dmb sy +100010c2: 4770 bx lr +100010c4: 400e0000 .word 0x400e0000 + +100010c8 : +100010c8: 2100 movs r1, #0 +100010ca: 4b04 ldr r3, [pc, #16] @ (100010dc ) +100010cc: 4a04 ldr r2, [pc, #16] @ (100010e0 ) +100010ce: f3bf 8f5f dmb sy +100010d2: f843 1b04 str.w r1, [r3], #4 +100010d6: 4293 cmp r3, r2 +100010d8: d1f9 bne.n 100010ce +100010da: 4770 bx lr +100010dc: 400e080c .word 0x400e080c +100010e0: 400e082c .word 0x400e082c + +100010e4 : +100010e4: b410 push {r4} +100010e6: f44f 708d mov.w r0, #282 @ 0x11a +100010ea: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010ee: 4a06 ldr r2, [pc, #24] @ (10001108 ) +100010f0: 4b06 ldr r3, [pc, #24] @ (1000110c ) +100010f2: 4907 ldr r1, [pc, #28] @ (10001110 ) +100010f4: 6014 str r4, [r2, #0] +100010f6: 60d0 str r0, [r2, #12] +100010f8: 6019 str r1, [r3, #0] +100010fa: 6853 ldr r3, [r2, #4] +100010fc: 2b00 cmp r3, #0 +100010fe: dafc bge.n 100010fa +10001100: f85d 4b04 ldr.w r4, [sp], #4 +10001104: 4770 bx lr +10001106: bf00 nop +10001108: 40048000 .word 0x40048000 +1000110c: 4004a000 .word 0x4004a000 +10001110: 00fab000 .word 0x00fab000 + +10001114 : +10001114: 4770 bx lr +10001116: bf00 nop + +10001118 : +10001118: b508 push {r3, lr} +1000111a: 4801 ldr r0, [pc, #4] @ (10001120 ) +1000111c: f7ff f8b8 bl 10000290 +10001120: 100034ec .word 0x100034ec + +10001124 : +10001124: b538 push {r3, r4, r5, lr} +10001126: 4c05 ldr r4, [pc, #20] @ (1000113c ) +10001128: 4d05 ldr r5, [pc, #20] @ (10001140 ) +1000112a: 42ac cmp r4, r5 +1000112c: d204 bcs.n 10001138 +1000112e: f854 3b04 ldr.w r3, [r4], #4 +10001132: 4798 blx r3 +10001134: 42ac cmp r4, r5 +10001136: d3fa bcc.n 1000112e +10001138: bd38 pop {r3, r4, r5, pc} +1000113a: bf00 nop +1000113c: 10003460 .word 0x10003460 +10001140: 100034a0 .word 0x100034a0 + +10001144 : +10001144: b410 push {r4} +10001146: 4807 ldr r0, [pc, #28] @ (10001164 ) +10001148: 4c07 ldr r4, [pc, #28] @ (10001168 ) +1000114a: 4b08 ldr r3, [pc, #32] @ (1000116c ) +1000114c: 4a08 ldr r2, [pc, #32] @ (10001170 ) +1000114e: 4909 ldr r1, [pc, #36] @ (10001174 ) +10001150: 6004 str r4, [r0, #0] +10001152: 601a str r2, [r3, #0] +10001154: 688b ldr r3, [r1, #8] +10001156: ea32 0303 bics.w r3, r2, r3 +1000115a: d1fb bne.n 10001154 +1000115c: f85d 4b04 ldr.w r4, [sp], #4 +10001160: 4770 bx lr +10001162: bf00 nop +10001164: 40022000 .word 0x40022000 +10001168: efef3b7f .word 0xefef3b7f +1000116c: 40023000 .word 0x40023000 +10001170: 03f3fff6 .word 0x03f3fff6 +10001174: 40020000 .word 0x40020000 + +10001178 : +10001178: 4b04 ldr r3, [pc, #16] @ (1000118c ) +1000117a: 6cdb ldr r3, [r3, #76] @ 0x4c +1000117c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001180: d103 bne.n 1000118a +10001182: f44f 2280 mov.w r2, #262144 @ 0x40000 +10001186: 4b02 ldr r3, [pc, #8] @ (10001190 ) +10001188: 64da str r2, [r3, #76] @ 0x4c +1000118a: 4770 bx lr +1000118c: 50110000 .word 0x50110000 +10001190: 50112000 .word 0x50112000 + +10001194 : +10001194: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001198: 4b04 ldr r3, [pc, #16] @ (100011ac ) +1000119a: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +1000119e: 430b orrs r3, r1 +100011a0: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100011a4: ee10 0430 dcp_rcmp r0 +100011a8: 4770 bx lr +100011aa: bf00 nop +100011ac: 00300303 .word 0x00300303 + +100011b0 : +100011b0: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011b4: 4b04 ldr r3, [pc, #16] @ (100011c8 ) +100011b6: 4a05 ldr r2, [pc, #20] @ (100011cc ) +100011b8: 6019 str r1, [r3, #0] +100011ba: 6893 ldr r3, [r2, #8] +100011bc: 43db mvns r3, r3 +100011be: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011c2: d1fa bne.n 100011ba +100011c4: 4770 bx lr +100011c6: bf00 nop +100011c8: 40023000 .word 0x40023000 +100011cc: 40020000 .word 0x40020000 + +100011d0 : +100011d0: b510 push {r4, lr} +100011d2: f245 2053 movw r0, #21075 @ 0x5253 +100011d6: f7ff ff61 bl 1000109c +100011da: e8bd 4010 ldmia.w sp!, {r4, lr} +100011de: 4603 mov r3, r0 +100011e0: 2004 movs r0, #4 +100011e2: 4718 bx r3 + +100011e4 : +100011e4: b510 push {r4, lr} +100011e6: f245 2053 movw r0, #21075 @ 0x5253 +100011ea: f7ff ff57 bl 1000109c +100011ee: e8bd 4010 ldmia.w sp!, {r4, lr} +100011f2: 4603 mov r3, r0 +100011f4: 2001 movs r0, #1 +100011f6: 4718 bx r3 + +100011f8 : +100011f8: f7ff b8a2 b.w 10000340 + +100011fc : +100011fc: 4914 ldr r1, [pc, #80] @ (10001250 ) +100011fe: 4b15 ldr r3, [pc, #84] @ (10001254 ) +10001200: b570 push {r4, r5, r6, lr} +10001202: 1a5c subs r4, r3, r1 +10001204: 10a6 asrs r6, r4, #2 +10001206: 2e44 cmp r6, #68 @ 0x44 +10001208: 4632 mov r2, r6 +1000120a: bf28 it cs +1000120c: 2244 movcs r2, #68 @ 0x44 +1000120e: 4d12 ldr r5, [pc, #72] @ (10001258 ) +10001210: 0092 lsls r2, r2, #2 +10001212: 4628 mov r0, r5 +10001214: f002 f872 bl 100032fc +10001218: f5b4 7f86 cmp.w r4, #268 @ 0x10c +1000121c: d813 bhi.n 10001246 +1000121e: 4a0f ldr r2, [pc, #60] @ (1000125c ) +10001220: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10001224: d012 beq.n 1000124c +10001226: 192b adds r3, r5, r4 +10001228: 0841 lsrs r1, r0, #1 +1000122a: eb03 01c1 add.w r1, r3, r1, lsl #3 +1000122e: e9c3 2200 strd r2, r2, [r3] +10001232: 3308 adds r3, #8 +10001234: 428b cmp r3, r1 +10001236: d1fa bne.n 1000122e +10001238: 07c3 lsls r3, r0, #31 +1000123a: d504 bpl.n 10001246 +1000123c: f020 0001 bic.w r0, r0, #1 +10001240: 4430 add r0, r6 +10001242: f845 2020 str.w r2, [r5, r0, lsl #2] +10001246: 4b06 ldr r3, [pc, #24] @ (10001260 ) +10001248: 609d str r5, [r3, #8] +1000124a: bd70 pop {r4, r5, r6, pc} +1000124c: 2043 movs r0, #67 @ 0x43 +1000124e: e7f8 b.n 10001242 +10001250: 10000000 .word 0x10000000 +10001254: 10000110 .word 0x10000110 +10001258: 20000000 .word 0x20000000 +1000125c: 10000111 .word 0x10000111 +10001260: e000ed00 .word 0xe000ed00 + +10001264 : +10001264: 2300 movs r3, #0 +10001266: b570 push {r4, r5, r6, lr} +10001268: 4c2b ldr r4, [pc, #172] @ (10001318 ) +1000126a: b082 sub sp, #8 +1000126c: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001270: f7ff ff38 bl 100010e4 +10001274: 2201 movs r2, #1 +10001276: 4b29 ldr r3, [pc, #164] @ (1000131c ) +10001278: 63da str r2, [r3, #60] @ 0x3c +1000127a: 6c63 ldr r3, [r4, #68] @ 0x44 +1000127c: 2b01 cmp r3, #1 +1000127e: d1fc bne.n 1000127a +10001280: 2103 movs r1, #3 +10001282: 4a26 ldr r2, [pc, #152] @ (1000131c ) +10001284: 4b24 ldr r3, [pc, #144] @ (10001318 ) +10001286: 6311 str r1, [r2, #48] @ 0x30 +10001288: 6b9c ldr r4, [r3, #56] @ 0x38 +1000128a: 2c01 cmp r4, #1 +1000128c: d1fc bne.n 10001288 +1000128e: 2602 movs r6, #2 +10001290: 2505 movs r5, #5 +10001292: 4621 mov r1, r4 +10001294: 2305 movs r3, #5 +10001296: 4a22 ldr r2, [pc, #136] @ (10001320 ) +10001298: 4822 ldr r0, [pc, #136] @ (10001324 ) +1000129a: 9600 str r6, [sp, #0] +1000129c: f7ff feac bl 10000ff8 +100012a0: 4621 mov r1, r4 +100012a2: 462b mov r3, r5 +100012a4: 4a20 ldr r2, [pc, #128] @ (10001328 ) +100012a6: 4821 ldr r0, [pc, #132] @ (1000132c ) +100012a8: 9500 str r5, [sp, #0] +100012aa: f7ff fea5 bl 10000ff8 +100012ae: 2200 movs r2, #0 +100012b0: 2004 movs r0, #4 +100012b2: 4631 mov r1, r6 +100012b4: 4b1e ldr r3, [pc, #120] @ (10001330 ) +100012b6: f7ff fe31 bl 10000f1c +100012ba: 4621 mov r1, r4 +100012bc: 4628 mov r0, r5 +100012be: 2200 movs r2, #0 +100012c0: 4b1c ldr r3, [pc, #112] @ (10001334 ) +100012c2: f7ff fe2b bl 10000f1c +100012c6: 2200 movs r2, #0 +100012c8: 2008 movs r0, #8 +100012ca: 4611 mov r1, r2 +100012cc: 4b1a ldr r3, [pc, #104] @ (10001338 ) +100012ce: f7ff fe25 bl 10000f1c +100012d2: 2200 movs r2, #0 +100012d4: 2009 movs r0, #9 +100012d6: 4611 mov r1, r2 +100012d8: 4b17 ldr r3, [pc, #92] @ (10001338 ) +100012da: f7ff fe1f bl 10000f1c +100012de: 2200 movs r2, #0 +100012e0: 2006 movs r0, #6 +100012e2: 4611 mov r1, r2 +100012e4: 4b13 ldr r3, [pc, #76] @ (10001334 ) +100012e6: f7ff fe19 bl 10000f1c +100012ea: 2200 movs r2, #0 +100012ec: 4b11 ldr r3, [pc, #68] @ (10001334 ) +100012ee: 2007 movs r0, #7 +100012f0: 4611 mov r1, r2 +100012f2: f7ff fe13 bl 10000f1c +100012f6: 2004 movs r0, #4 +100012f8: f7ff fe78 bl 10000fec +100012fc: 2400 movs r4, #0 +100012fe: 4b0f ldr r3, [pc, #60] @ (1000133c ) +10001300: fba3 3500 umull r3, r5, r3, r0 +10001304: 0cad lsrs r5, r5, #18 +10001306: b2e0 uxtb r0, r4 +10001308: 4629 mov r1, r5 +1000130a: 3401 adds r4, #1 +1000130c: f7ff feba bl 10001084 +10001310: 2c06 cmp r4, #6 +10001312: d1f8 bne.n 10001306 +10001314: b002 add sp, #8 +10001316: bd70 pop {r4, r5, r6, pc} +10001318: 40010000 .word 0x40010000 +1000131c: 40013000 .word 0x40013000 +10001320: 59682f00 .word 0x59682f00 +10001324: 40050000 .word 0x40050000 +10001328: 47868c00 .word 0x47868c00 +1000132c: 40058000 .word 0x40058000 +10001330: 00b71b00 .word 0x00b71b00 +10001334: 08f0d180 .word 0x08f0d180 +10001338: 02dc6c00 .word 0x02dc6c00 +1000133c: 431bde83 .word 0x431bde83 + +10001340 : +10001340: b086 sub sp, #24 +10001342: b403 push {r0, r1} +10001344: fc51 0408 dcp_pxmd r0, r1 +10001348: e9cd 0102 strd r0, r1, [sp, #8] +1000134c: fc51 0409 dcp_pymd r0, r1 +10001350: e9cd 0104 strd r0, r1, [sp, #16] +10001354: ec51 040a dcp_refd r0, r1 +10001358: e9cd 0106 strd r0, r1, [sp, #24] +1000135c: bc03 pop {r0, r1} +1000135e: 47f0 blx lr + +10001360 : +10001360: e8bd 5000 ldmia.w sp!, {ip, lr} +10001364: ec4e c400 dcp_wxmd ip, lr +10001368: e8bd 5000 ldmia.w sp!, {ip, lr} +1000136c: ec4e c401 dcp_wymd ip, lr +10001370: e8bd 5000 ldmia.w sp!, {ip, lr} +10001374: ec4e c402 dcp_wefd ip, lr +10001378: bd00 pop {pc} +1000137a: 0000 movs r0, r0 +1000137c: b500 push {lr} +1000137e: f7ff ffdf bl 10001340 +10001382: e002 b.n 1000138a <__wrap___aeabi_dadd+0x6> + +10001384 <__wrap___aeabi_dadd>: +10001384: fe10 f430 dcp_pcmp APSR_nzcv +10001388: d4f8 bmi.n 1000137c +1000138a: ec41 0410 dcp_wxup r0, r1 +1000138e: ec43 2411 dcp_wyup r2, r3 +10001392: ee00 0401 dcp_add0 +10001396: ee10 0401 dcp_add1 +1000139a: ee80 0420 dcp_nrdd +1000139e: ec51 0410 dcp_rdda r0, r1 +100013a2: 4770 bx lr +100013a4: b500 push {lr} +100013a6: f7ff ffcb bl 10001340 +100013aa: e002 b.n 100013b2 <__wrap___aeabi_dsub+0x6> + +100013ac <__wrap___aeabi_dsub>: +100013ac: fe10 f430 dcp_pcmp APSR_nzcv +100013b0: d4f8 bmi.n 100013a4 <__wrap___aeabi_dadd+0x20> +100013b2: ec41 0410 dcp_wxup r0, r1 +100013b6: ec43 2411 dcp_wyup r2, r3 +100013ba: ee00 0401 dcp_add0 +100013be: ee10 0421 dcp_sub1 +100013c2: ee80 0420 dcp_nrdd +100013c6: ec51 0430 dcp_rdds r0, r1 +100013ca: 4770 bx lr +100013cc: b500 push {lr} +100013ce: f7ff ffb7 bl 10001340 +100013d2: e002 b.n 100013da <__wrap___aeabi_dmul+0x6> + +100013d4 <__wrap___aeabi_dmul>: +100013d4: fe10 f430 dcp_pcmp APSR_nzcv +100013d8: d4f8 bmi.n 100013cc <__wrap___aeabi_dsub+0x20> +100013da: b510 push {r4, lr} +100013dc: ec41 0410 dcp_wxup r0, r1 +100013e0: ec43 2411 dcp_wyup r2, r3 +100013e4: ec51 0404 dcp_rxms r0, r1, #0x0 +100013e8: ec53 2405 dcp_ryms r2, r3, #0x0 +100013ec: fba0 4c02 umull r4, ip, r0, r2 +100013f0: f05f 0e00 movs.w lr, #0 +100013f4: fbe0 ce03 umlal ip, lr, r0, r3 +100013f8: fbe1 ce02 umlal ip, lr, r1, r2 +100013fc: ec4c 4420 dcp_wxms r4, ip +10001400: 2400 movs r4, #0 +10001402: fbe1 e403 umlal lr, r4, r1, r3 +10001406: ec44 e430 dcp_wxmo lr, r4 +1000140a: ee80 0420 dcp_nrdd +1000140e: ec51 0450 dcp_rddm r0, r1 +10001412: e8bd 4010 ldmia.w sp!, {r4, lr} +10001416: 4770 bx lr +10001418: b500 push {lr} +1000141a: f7ff ff91 bl 10001340 +1000141e: e002 b.n 10001426 <__wrap___aeabi_ddiv+0x6> + +10001420 <__wrap___aeabi_ddiv>: +10001420: fe10 f430 dcp_pcmp APSR_nzcv +10001424: d4f8 bmi.n 10001418 <__wrap___aeabi_dmul+0x44> +10001426: ec41 0410 dcp_wxup r0, r1 +1000142a: ec43 2411 dcp_wyup r2, r3 +1000142e: ec51 0421 dcp_rymr r0, r1 +10001432: fba0 1201 umull r1, r2, r0, r1 +10001436: ea6f 0282 mvn.w r2, r2, lsl #2 +1000143a: fb52 0010 smmlar r0, r2, r0, r0 +1000143e: fb52 f212 smmulr r2, r2, r2 +10001442: fb52 0010 smmlar r0, r2, r0, r0 +10001446: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +1000144a: ec53 2404 dcp_rxms r2, r3, #0x0 +1000144e: fb5c f113 smmulr r1, ip, r3 +10001452: ec53 2415 dcp_ryms r2, r3, #0x1 +10001456: fba1 2002 umull r2, r0, r1, r2 +1000145a: fb01 0003 mla r0, r1, r3, r0 +1000145e: ec53 2444 dcp_rxms r2, r3, #0x4 +10001462: eba2 0000 sub.w r0, r2, r0 +10001466: fb50 f21c smmulr r2, r0, ip +1000146a: ea4f 1311 mov.w r3, r1, lsr #4 +1000146e: eb12 7001 adds.w r0, r2, r1, lsl #28 +10001472: eb43 71e2 adc.w r1, r3, r2, asr #31 +10001476: ea40 5051 orr.w r0, r0, r1, lsr #21 +1000147a: ea20 5091 bic.w r0, r0, r1, lsr #22 +1000147e: f020 0007 bic.w r0, r0, #7 +10001482: ec53 2475 dcp_ryms r2, r3, #0x7 +10001486: fba0 3c02 umull r3, ip, r0, r2 +1000148a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000148e: fb00 cc03 mla ip, r0, r3, ip +10001492: fb01 cc02 mla ip, r1, r2, ip +10001496: ec53 2404 dcp_rxms r2, r3, #0x0 +1000149a: ebac 4c82 sub.w ip, ip, r2, lsl #18 +1000149e: ea40 705c orr.w r0, r0, ip, lsr #29 +100014a2: f1a0 0001 sub.w r0, r0, #1 +100014a6: ec41 0440 dcp_wxdd r0, r1 +100014aa: ee80 0420 dcp_nrdd +100014ae: ec51 0470 dcp_rddd r0, r1 +100014b2: 4770 bx lr +100014b4: b500 push {lr} +100014b6: f7ff ff43 bl 10001340 +100014ba: e002 b.n 100014c2 <__wrap___aeabi_i2d+0x6> + +100014bc <__wrap___aeabi_i2d>: +100014bc: fe10 f430 dcp_pcmp APSR_nzcv +100014c0: d4f8 bmi.n 100014b4 <__wrap___aeabi_ddiv+0x94> +100014c2: ec40 0470 dcp_wxic r0, r0 +100014c6: ee00 0401 dcp_add0 +100014ca: ee10 0421 dcp_sub1 +100014ce: ee80 0420 dcp_nrdd +100014d2: ec51 0430 dcp_rdds r0, r1 +100014d6: 4770 bx lr +100014d8: b500 push {lr} +100014da: f7ff ff31 bl 10001340 +100014de: e002 b.n 100014e6 <__wrap___aeabi_ui2d+0x6> + +100014e0 <__wrap___aeabi_ui2d>: +100014e0: fe10 f430 dcp_pcmp APSR_nzcv +100014e4: d4f8 bmi.n 100014d8 <__wrap___aeabi_i2d+0x1c> +100014e6: ec40 0460 dcp_wxuc r0, r0 +100014ea: ee00 0401 dcp_add0 +100014ee: ee10 0421 dcp_sub1 +100014f2: ee80 0420 dcp_nrdd +100014f6: ec51 0430 dcp_rdds r0, r1 +100014fa: 4770 bx lr +100014fc: b500 push {lr} +100014fe: f7ff ff1f bl 10001340 +10001502: e002 b.n 1000150a + +10001504 <__wrap___aeabi_d2iz>: +10001504: fe10 f430 dcp_pcmp APSR_nzcv +10001508: d4f8 bmi.n 100014fc <__wrap___aeabi_ui2d+0x1c> + +1000150a : +1000150a: ec41 0480 dcp_wxdc r0, r1 +1000150e: ee00 0401 dcp_add0 +10001512: ee10 0401 dcp_add1 +10001516: ee80 0440 dcp_ntdc +1000151a: ee10 0413 dcp_rdic r0 +1000151e: 4770 bx lr +10001520: b500 push {lr} +10001522: f7ff ff0d bl 10001340 +10001526: e002 b.n 1000152e + +10001528 <__wrap___aeabi_d2uiz>: +10001528: fe10 f430 dcp_pcmp APSR_nzcv +1000152c: d4f8 bmi.n 10001520 + +1000152e : +1000152e: ec41 0480 dcp_wxdc r0, r1 +10001532: ee00 0401 dcp_add0 +10001536: ee10 0401 dcp_add1 +1000153a: ee80 0440 dcp_ntdc +1000153e: ee10 0433 dcp_rduc r0 +10001542: 4770 bx lr +10001544: b500 push {lr} +10001546: f7ff fefb bl 10001340 +1000154a: e002 b.n 10001552 <__wrap___aeabi_dcmpun+0x6> + +1000154c <__wrap___aeabi_dcmpun>: +1000154c: fe10 f430 dcp_pcmp APSR_nzcv +10001550: d4f8 bmi.n 10001544 +10001552: ec41 0410 dcp_wxup r0, r1 +10001556: ec43 2411 dcp_wyup r2, r3 +1000155a: ee00 0401 dcp_add0 +1000155e: ee10 0430 dcp_rcmp r0 +10001562: f3c0 7000 ubfx r0, r0, #28, #1 +10001566: 4770 bx lr +10001568: b500 push {lr} +1000156a: f7ff fee9 bl 10001340 +1000156e: e002 b.n 10001576 <__wrap___aeabi_dcmplt+0x6> + +10001570 <__wrap___aeabi_dcmplt>: +10001570: fe10 f430 dcp_pcmp APSR_nzcv +10001574: d4f8 bmi.n 10001568 <__wrap___aeabi_dcmpun+0x1c> +10001576: ec43 2410 dcp_wxup r2, r3 +1000157a: ec41 0411 dcp_wyup r0, r1 +1000157e: ee00 0401 dcp_add0 +10001582: ee10 f430 dcp_rcmp APSR_nzcv +10001586: bf8c ite hi +10001588: 2001 movhi r0, #1 +1000158a: 2000 movls r0, #0 +1000158c: 4770 bx lr +1000158e: bf00 nop +10001590: b500 push {lr} +10001592: f7ff fed5 bl 10001340 +10001596: e002 b.n 1000159e <__wrap___aeabi_dcmple+0x6> + +10001598 <__wrap___aeabi_dcmple>: +10001598: fe10 f430 dcp_pcmp APSR_nzcv +1000159c: d4f8 bmi.n 10001590 <__wrap___aeabi_dcmplt+0x20> +1000159e: ec43 2410 dcp_wxup r2, r3 +100015a2: ec41 0411 dcp_wyup r0, r1 +100015a6: ee00 0401 dcp_add0 +100015aa: ee10 f430 dcp_rcmp APSR_nzcv +100015ae: bf2c ite cs +100015b0: 2001 movcs r0, #1 +100015b2: 2000 movcc r0, #0 +100015b4: 4770 bx lr +100015b6: bf00 nop +100015b8: b500 push {lr} +100015ba: f7ff fec1 bl 10001340 +100015be: e002 b.n 100015c6 <__wrap___aeabi_dcmpge+0x6> + +100015c0 <__wrap___aeabi_dcmpge>: +100015c0: fe10 f430 dcp_pcmp APSR_nzcv +100015c4: d4f8 bmi.n 100015b8 <__wrap___aeabi_dcmple+0x20> +100015c6: ec41 0410 dcp_wxup r0, r1 +100015ca: ec43 2411 dcp_wyup r2, r3 +100015ce: ee00 0401 dcp_add0 +100015d2: ee10 f430 dcp_rcmp APSR_nzcv +100015d6: bf2c ite cs +100015d8: 2001 movcs r0, #1 +100015da: 2000 movcc r0, #0 +100015dc: 4770 bx lr +100015de: bf00 nop +100015e0: b500 push {lr} +100015e2: f7ff fead bl 10001340 +100015e6: e002 b.n 100015ee <__wrap___aeabi_dcmpgt+0x6> + +100015e8 <__wrap___aeabi_dcmpgt>: +100015e8: fe10 f430 dcp_pcmp APSR_nzcv +100015ec: d4f8 bmi.n 100015e0 <__wrap___aeabi_dcmpge+0x20> +100015ee: ec41 0410 dcp_wxup r0, r1 +100015f2: ec43 2411 dcp_wyup r2, r3 +100015f6: ee00 0401 dcp_add0 +100015fa: ee10 f430 dcp_rcmp APSR_nzcv +100015fe: bf8c ite hi +10001600: 2001 movhi r0, #1 +10001602: 2000 movls r0, #0 +10001604: 4770 bx lr +10001606: bf00 nop + +10001608 <_out_null>: +10001608: 4770 bx lr +1000160a: bf00 nop + +1000160c <_out_rev>: +1000160c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001610: b083 sub sp, #12 +10001612: 4699 mov r9, r3 +10001614: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001618: 9b0f ldr r3, [sp, #60] @ 0x3c +1000161a: 4688 mov r8, r1 +1000161c: 4611 mov r1, r2 +1000161e: 079a lsls r2, r3, #30 +10001620: 4607 mov r7, r0 +10001622: d116 bne.n 10001652 <_out_rev+0x46> +10001624: 45da cmp sl, fp +10001626: d23a bcs.n 1000169e <_out_rev+0x92> +10001628: 460c mov r4, r1 +1000162a: 460d mov r5, r1 +1000162c: ebab 060a sub.w r6, fp, sl +10001630: 440e add r6, r1 +10001632: 4622 mov r2, r4 +10001634: 464b mov r3, r9 +10001636: 4641 mov r1, r8 +10001638: 2020 movs r0, #32 +1000163a: 3401 adds r4, #1 +1000163c: 47b8 blx r7 +1000163e: 42b4 cmp r4, r6 +10001640: d1f7 bne.n 10001632 <_out_rev+0x26> +10001642: 4629 mov r1, r5 +10001644: f1ba 0f00 cmp.w sl, #0 +10001648: d108 bne.n 1000165c <_out_rev+0x50> +1000164a: 4620 mov r0, r4 +1000164c: b003 add sp, #12 +1000164e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001652: 460c mov r4, r1 +10001654: f1ba 0f00 cmp.w sl, #0 +10001658: d010 beq.n 1000167c <_out_rev+0x70> +1000165a: 460e mov r6, r1 +1000165c: 4655 mov r5, sl +1000165e: 9b0c ldr r3, [sp, #48] @ 0x30 +10001660: 442e add r6, r5 +10001662: 449a add sl, r3 +10001664: 9101 str r1, [sp, #4] +10001666: 1b72 subs r2, r6, r5 +10001668: 464b mov r3, r9 +1000166a: 3d01 subs r5, #1 +1000166c: 4641 mov r1, r8 +1000166e: f81a 0d01 ldrb.w r0, [sl, #-1]! +10001672: 4634 mov r4, r6 +10001674: 47b8 blx r7 +10001676: 2d00 cmp r5, #0 +10001678: d1f5 bne.n 10001666 <_out_rev+0x5a> +1000167a: 9901 ldr r1, [sp, #4] +1000167c: 9b0f ldr r3, [sp, #60] @ 0x3c +1000167e: 079b lsls r3, r3, #30 +10001680: d5e3 bpl.n 1000164a <_out_rev+0x3e> +10001682: 1a65 subs r5, r4, r1 +10001684: 45ab cmp fp, r5 +10001686: d9e0 bls.n 1000164a <_out_rev+0x3e> +10001688: 4622 mov r2, r4 +1000168a: 464b mov r3, r9 +1000168c: 4641 mov r1, r8 +1000168e: 2020 movs r0, #32 +10001690: 3501 adds r5, #1 +10001692: 47b8 blx r7 +10001694: 455d cmp r5, fp +10001696: f104 0401 add.w r4, r4, #1 +1000169a: d3f5 bcc.n 10001688 <_out_rev+0x7c> +1000169c: e7d5 b.n 1000164a <_out_rev+0x3e> +1000169e: 460c mov r4, r1 +100016a0: f1ba 0f00 cmp.w sl, #0 +100016a4: d1d9 bne.n 1000165a <_out_rev+0x4e> +100016a6: e7d0 b.n 1000164a <_out_rev+0x3e> + +100016a8 <_ntoa_format>: +100016a8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100016ac: 9f0f ldr r7, [sp, #60] @ 0x3c +100016ae: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +100016b2: f017 0f02 tst.w r7, #2 +100016b6: 9c0a ldr r4, [sp, #40] @ 0x28 +100016b8: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +100016bc: 9d0e ldr r5, [sp, #56] @ 0x38 +100016be: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +100016c2: d144 bne.n 1000174e <_ntoa_format+0xa6> +100016c4: bbf5 cbnz r5, 10001744 <_ntoa_format+0x9c> +100016c6: 42b4 cmp r4, r6 +100016c8: d241 bcs.n 1000174e <_ntoa_format+0xa6> +100016ca: f007 0b01 and.w fp, r7, #1 +100016ce: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100016d2: f04f 0e30 mov.w lr, #48 @ 0x30 +100016d6: 44c4 add ip, r8 +100016d8: e004 b.n 100016e4 <_ntoa_format+0x3c> +100016da: 3401 adds r4, #1 +100016dc: 42a6 cmp r6, r4 +100016de: f80c ef01 strb.w lr, [ip, #1]! +100016e2: d901 bls.n 100016e8 <_ntoa_format+0x40> +100016e4: 2c20 cmp r4, #32 +100016e6: d1f8 bne.n 100016da <_ntoa_format+0x32> +100016e8: f1bb 0f00 cmp.w fp, #0 +100016ec: f000 8088 beq.w 10001800 <_ntoa_format+0x158> +100016f0: 42a5 cmp r5, r4 +100016f2: d92c bls.n 1000174e <_ntoa_format+0xa6> +100016f4: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100016f8: f04f 0e30 mov.w lr, #48 @ 0x30 +100016fc: 44c4 add ip, r8 +100016fe: e004 b.n 1000170a <_ntoa_format+0x62> +10001700: 3401 adds r4, #1 +10001702: 42ac cmp r4, r5 +10001704: f80c ef01 strb.w lr, [ip, #1]! +10001708: d021 beq.n 1000174e <_ntoa_format+0xa6> +1000170a: 2c20 cmp r4, #32 +1000170c: d1f8 bne.n 10001700 <_ntoa_format+0x58> +1000170e: f017 0f10 tst.w r7, #16 +10001712: d00e beq.n 10001732 <_ntoa_format+0x8a> +10001714: f417 6f80 tst.w r7, #1024 @ 0x400 +10001718: d154 bne.n 100017c4 <_ntoa_format+0x11c> +1000171a: 42a6 cmp r6, r4 +1000171c: d063 beq.n 100017e6 <_ntoa_format+0x13e> +1000171e: 42a5 cmp r5, r4 +10001720: d061 beq.n 100017e6 <_ntoa_format+0x13e> +10001722: f1b9 0f10 cmp.w r9, #16 +10001726: d050 beq.n 100017ca <_ntoa_format+0x122> +10001728: f1b9 0f02 cmp.w r9, #2 +1000172c: d056 beq.n 100017dc <_ntoa_format+0x134> +1000172e: 2c20 cmp r4, #32 +10001730: d129 bne.n 10001786 <_ntoa_format+0xde> +10001732: 2420 movs r4, #32 +10001734: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001738: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +1000173c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001740: f7ff bf64 b.w 1000160c <_out_rev> +10001744: f017 0b01 ands.w fp, r7, #1 +10001748: d134 bne.n 100017b4 <_ntoa_format+0x10c> +1000174a: 42b4 cmp r4, r6 +1000174c: d3bf bcc.n 100016ce <_ntoa_format+0x26> +1000174e: f017 0f10 tst.w r7, #16 +10001752: d01e beq.n 10001792 <_ntoa_format+0xea> +10001754: f417 6f80 tst.w r7, #1024 @ 0x400 +10001758: d1e3 bne.n 10001722 <_ntoa_format+0x7a> +1000175a: 2c00 cmp r4, #0 +1000175c: d1dd bne.n 1000171a <_ntoa_format+0x72> +1000175e: f1b9 0f10 cmp.w r9, #16 +10001762: d063 beq.n 1000182c <_ntoa_format+0x184> +10001764: f1b9 0f02 cmp.w r9, #2 +10001768: d077 beq.n 1000185a <_ntoa_format+0x1b2> +1000176a: 2430 movs r4, #48 @ 0x30 +1000176c: f888 4000 strb.w r4, [r8] +10001770: 2401 movs r4, #1 +10001772: f1ba 0f00 cmp.w sl, #0 +10001776: d111 bne.n 1000179c <_ntoa_format+0xf4> +10001778: 077e lsls r6, r7, #29 +1000177a: d548 bpl.n 1000180e <_ntoa_format+0x166> +1000177c: 262b movs r6, #43 @ 0x2b +1000177e: f808 6004 strb.w r6, [r8, r4] +10001782: 3401 adds r4, #1 +10001784: e7d6 b.n 10001734 <_ntoa_format+0x8c> +10001786: 4626 mov r6, r4 +10001788: 3401 adds r4, #1 +1000178a: f04f 0c30 mov.w ip, #48 @ 0x30 +1000178e: f808 c006 strb.w ip, [r8, r6] +10001792: 2c20 cmp r4, #32 +10001794: d0cd beq.n 10001732 <_ntoa_format+0x8a> +10001796: f1ba 0f00 cmp.w sl, #0 +1000179a: d0ed beq.n 10001778 <_ntoa_format+0xd0> +1000179c: 262d movs r6, #45 @ 0x2d +1000179e: f808 6004 strb.w r6, [r8, r4] +100017a2: 3401 adds r4, #1 +100017a4: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100017a8: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100017ac: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100017b0: f7ff bf2c b.w 1000160c <_out_rev> +100017b4: f1ba 0f00 cmp.w sl, #0 +100017b8: d030 beq.n 1000181c <_ntoa_format+0x174> +100017ba: 42b4 cmp r4, r6 +100017bc: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +100017c0: d385 bcc.n 100016ce <_ntoa_format+0x26> +100017c2: e795 b.n 100016f0 <_ntoa_format+0x48> +100017c4: f1b9 0f10 cmp.w r9, #16 +100017c8: d1b3 bne.n 10001732 <_ntoa_format+0x8a> +100017ca: 06be lsls r6, r7, #26 +100017cc: d53b bpl.n 10001846 <_ntoa_format+0x19e> +100017ce: 2c20 cmp r4, #32 +100017d0: d0af beq.n 10001732 <_ntoa_format+0x8a> +100017d2: 2658 movs r6, #88 @ 0x58 +100017d4: f808 6004 strb.w r6, [r8, r4] +100017d8: 3401 adds r4, #1 +100017da: e7a8 b.n 1000172e <_ntoa_format+0x86> +100017dc: 2c20 cmp r4, #32 +100017de: d0a8 beq.n 10001732 <_ntoa_format+0x8a> +100017e0: 4626 mov r6, r4 +100017e2: 3401 adds r4, #1 +100017e4: e007 b.n 100017f6 <_ntoa_format+0x14e> +100017e6: 1e66 subs r6, r4, #1 +100017e8: d0b9 beq.n 1000175e <_ntoa_format+0xb6> +100017ea: f1b9 0f10 cmp.w r9, #16 +100017ee: d036 beq.n 1000185e <_ntoa_format+0x1b6> +100017f0: f1b9 0f02 cmp.w r9, #2 +100017f4: d1c9 bne.n 1000178a <_ntoa_format+0xe2> +100017f6: f04f 0c62 mov.w ip, #98 @ 0x62 +100017fa: f808 c006 strb.w ip, [r8, r6] +100017fe: e796 b.n 1000172e <_ntoa_format+0x86> +10001800: f017 0f10 tst.w r7, #16 +10001804: d0c5 beq.n 10001792 <_ntoa_format+0xea> +10001806: f417 6f80 tst.w r7, #1024 @ 0x400 +1000180a: d086 beq.n 1000171a <_ntoa_format+0x72> +1000180c: e789 b.n 10001722 <_ntoa_format+0x7a> +1000180e: 073e lsls r6, r7, #28 +10001810: d590 bpl.n 10001734 <_ntoa_format+0x8c> +10001812: 2620 movs r6, #32 +10001814: f808 6004 strb.w r6, [r8, r4] +10001818: 3401 adds r4, #1 +1000181a: e78b b.n 10001734 <_ntoa_format+0x8c> +1000181c: f017 0f0c tst.w r7, #12 +10001820: d000 beq.n 10001824 <_ntoa_format+0x17c> +10001822: 3d01 subs r5, #1 +10001824: 42b4 cmp r4, r6 +10001826: f4ff af52 bcc.w 100016ce <_ntoa_format+0x26> +1000182a: e761 b.n 100016f0 <_ntoa_format+0x48> +1000182c: 06bc lsls r4, r7, #26 +1000182e: d412 bmi.n 10001856 <_ntoa_format+0x1ae> +10001830: 2478 movs r4, #120 @ 0x78 +10001832: f888 4000 strb.w r4, [r8] +10001836: 2430 movs r4, #48 @ 0x30 +10001838: f888 4001 strb.w r4, [r8, #1] +1000183c: 2402 movs r4, #2 +1000183e: f1ba 0f00 cmp.w sl, #0 +10001842: d099 beq.n 10001778 <_ntoa_format+0xd0> +10001844: e7aa b.n 1000179c <_ntoa_format+0xf4> +10001846: 2c20 cmp r4, #32 +10001848: f43f af73 beq.w 10001732 <_ntoa_format+0x8a> +1000184c: 2678 movs r6, #120 @ 0x78 +1000184e: f808 6004 strb.w r6, [r8, r4] +10001852: 3401 adds r4, #1 +10001854: e76b b.n 1000172e <_ntoa_format+0x86> +10001856: 2458 movs r4, #88 @ 0x58 +10001858: e7eb b.n 10001832 <_ntoa_format+0x18a> +1000185a: 2462 movs r4, #98 @ 0x62 +1000185c: e7e9 b.n 10001832 <_ntoa_format+0x18a> +1000185e: f017 0f20 tst.w r7, #32 +10001862: f1a4 0c02 sub.w ip, r4, #2 +10001866: d004 beq.n 10001872 <_ntoa_format+0x1ca> +10001868: f04f 0e58 mov.w lr, #88 @ 0x58 +1000186c: f808 e00c strb.w lr, [r8, ip] +10001870: e78b b.n 1000178a <_ntoa_format+0xe2> +10001872: f04f 0e78 mov.w lr, #120 @ 0x78 +10001876: f808 e00c strb.w lr, [r8, ip] +1000187a: e786 b.n 1000178a <_ntoa_format+0xe2> + +1000187c <_out_char>: +1000187c: b900 cbnz r0, 10001880 <_out_char+0x4> +1000187e: 4770 bx lr +10001880: f001 bb72 b.w 10002f68 <__wrap_putchar> + +10001884 <_out_fct>: +10001884: b110 cbz r0, 1000188c <_out_fct+0x8> +10001886: e9d1 3100 ldrd r3, r1, [r1] +1000188a: 4718 bx r3 +1000188c: 4770 bx lr +1000188e: bf00 nop + +10001890 <_ftoa>: +10001890: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001894: b097 sub sp, #92 @ 0x5c +10001896: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +1000189a: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +1000189e: 4607 mov r7, r0 +100018a0: 4688 mov r8, r1 +100018a2: ec51 0b17 vmov r0, r1, d7 +100018a6: 9c24 ldr r4, [sp, #144] @ 0x90 +100018a8: 4699 mov r9, r3 +100018aa: 920c str r2, [sp, #48] @ 0x30 +100018ac: 460b mov r3, r1 +100018ae: 4602 mov r2, r0 +100018b0: ed8d 7b04 vstr d7, [sp, #16] +100018b4: 9407 str r4, [sp, #28] +100018b6: f7ff fe49 bl 1000154c <__wrap___aeabi_dcmpun> +100018ba: 2800 cmp r0, #0 +100018bc: f040 81f4 bne.w 10001ca8 <_ftoa+0x418> +100018c0: e9dd 0104 ldrd r0, r1, [sp, #16] +100018c4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018c8: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100018cc: f7ff fe50 bl 10001570 <__wrap___aeabi_dcmplt> +100018d0: 2800 cmp r0, #0 +100018d2: f040 811b bne.w 10001b0c <_ftoa+0x27c> +100018d6: e9dd 0104 ldrd r0, r1, [sp, #16] +100018da: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018de: 4bac ldr r3, [pc, #688] @ (10001b90 <_ftoa+0x300>) +100018e0: f7ff fe82 bl 100015e8 <__wrap___aeabi_dcmpgt> +100018e4: 2800 cmp r0, #0 +100018e6: f040 80ee bne.w 10001ac6 <_ftoa+0x236> +100018ea: e9dd 0104 ldrd r0, r1, [sp, #16] +100018ee: a3a4 add r3, pc, #656 @ (adr r3, 10001b80 <_ftoa+0x2f0>) +100018f0: e9d3 2300 ldrd r2, r3, [r3] +100018f4: f7ff fe78 bl 100015e8 <__wrap___aeabi_dcmpgt> +100018f8: 2800 cmp r0, #0 +100018fa: f040 80d3 bne.w 10001aa4 <_ftoa+0x214> +100018fe: e9dd 0104 ldrd r0, r1, [sp, #16] +10001902: a3a1 add r3, pc, #644 @ (adr r3, 10001b88 <_ftoa+0x2f8>) +10001904: e9d3 2300 ldrd r2, r3, [r3] +10001908: f7ff fe32 bl 10001570 <__wrap___aeabi_dcmplt> +1000190c: 2800 cmp r0, #0 +1000190e: f040 80c9 bne.w 10001aa4 <_ftoa+0x214> +10001912: e9dd 0104 ldrd r0, r1, [sp, #16] +10001916: 2200 movs r2, #0 +10001918: 2300 movs r3, #0 +1000191a: f7ff fe29 bl 10001570 <__wrap___aeabi_dcmplt> +1000191e: 2800 cmp r0, #0 +10001920: f040 80e8 bne.w 10001af4 <_ftoa+0x264> +10001924: 4623 mov r3, r4 +10001926: 900d str r0, [sp, #52] @ 0x34 +10001928: f413 6f80 tst.w r3, #1024 @ 0x400 +1000192c: bf08 it eq +1000192e: 2506 moveq r5, #6 +10001930: 2130 movs r1, #48 @ 0x30 +10001932: 462b mov r3, r5 +10001934: aa0e add r2, sp, #56 @ 0x38 +10001936: f1a5 0620 sub.w r6, r5, #32 +1000193a: e005 b.n 10001948 <_ftoa+0xb8> +1000193c: 3b01 subs r3, #1 +1000193e: 42b3 cmp r3, r6 +10001940: f802 1b01 strb.w r1, [r2], #1 +10001944: f000 8193 beq.w 10001c6e <_ftoa+0x3de> +10001948: 2b09 cmp r3, #9 +1000194a: d8f7 bhi.n 1000193c <_ftoa+0xac> +1000194c: 461e mov r6, r3 +1000194e: 1aed subs r5, r5, r3 +10001950: e9dd 0104 ldrd r0, r1, [sp, #16] +10001954: f7ff fdd6 bl 10001504 <__wrap___aeabi_d2iz> +10001958: 4b8e ldr r3, [pc, #568] @ (10001b94 <_ftoa+0x304>) +1000195a: 4604 mov r4, r0 +1000195c: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001960: ed93 7b00 vldr d7, [r3] +10001964: ed8d 7b08 vstr d7, [sp, #32] +10001968: f7ff fda8 bl 100014bc <__wrap___aeabi_i2d> +1000196c: 4602 mov r2, r0 +1000196e: 460b mov r3, r1 +10001970: e9dd 0104 ldrd r0, r1, [sp, #16] +10001974: f7ff fd1a bl 100013ac <__wrap___aeabi_dsub> +10001978: e9dd 2308 ldrd r2, r3, [sp, #32] +1000197c: f7ff fd2a bl 100013d4 <__wrap___aeabi_dmul> +10001980: 4602 mov r2, r0 +10001982: 460b mov r3, r1 +10001984: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001988: f7ff fdce bl 10001528 <__wrap___aeabi_d2uiz> +1000198c: 4682 mov sl, r0 +1000198e: f7ff fda7 bl 100014e0 <__wrap___aeabi_ui2d> +10001992: 4602 mov r2, r0 +10001994: 460b mov r3, r1 +10001996: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000199a: f7ff fd07 bl 100013ac <__wrap___aeabi_dsub> +1000199e: 4602 mov r2, r0 +100019a0: 460b mov r3, r1 +100019a2: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +100019a6: 2200 movs r2, #0 +100019a8: 4b7b ldr r3, [pc, #492] @ (10001b98 <_ftoa+0x308>) +100019aa: f7ff fe1d bl 100015e8 <__wrap___aeabi_dcmpgt> +100019ae: 2800 cmp r0, #0 +100019b0: f000 80fe beq.w 10001bb0 <_ftoa+0x320> +100019b4: f10a 0a01 add.w sl, sl, #1 +100019b8: 4650 mov r0, sl +100019ba: f7ff fd91 bl 100014e0 <__wrap___aeabi_ui2d> +100019be: 4602 mov r2, r0 +100019c0: 460b mov r3, r1 +100019c2: e9dd 0108 ldrd r0, r1, [sp, #32] +100019c6: f7ff fde7 bl 10001598 <__wrap___aeabi_dcmple> +100019ca: b110 cbz r0, 100019d2 <_ftoa+0x142> +100019cc: f04f 0a00 mov.w sl, #0 +100019d0: 3401 adds r4, #1 +100019d2: 2e00 cmp r6, #0 +100019d4: f000 80fd beq.w 10001bd2 <_ftoa+0x342> +100019d8: 1e68 subs r0, r5, #1 +100019da: ab0e add r3, sp, #56 @ 0x38 +100019dc: f8df c1cc ldr.w ip, [pc, #460] @ 10001bac <_ftoa+0x31c> +100019e0: 4418 add r0, r3 +100019e2: e00f b.n 10001a04 <_ftoa+0x174> +100019e4: fbac 210a umull r2, r1, ip, sl +100019e8: 08c9 lsrs r1, r1, #3 +100019ea: eb01 0281 add.w r2, r1, r1, lsl #2 +100019ee: ebaa 0242 sub.w r2, sl, r2, lsl #1 +100019f2: 3230 adds r2, #48 @ 0x30 +100019f4: f1ba 0f09 cmp.w sl, #9 +100019f8: f800 2f01 strb.w r2, [r0, #1]! +100019fc: f240 811c bls.w 10001c38 <_ftoa+0x3a8> +10001a00: 468a mov sl, r1 +10001a02: 461d mov r5, r3 +10001a04: 2d20 cmp r5, #32 +10001a06: f105 0301 add.w r3, r5, #1 +10001a0a: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001a0e: d1e9 bne.n 100019e4 <_ftoa+0x154> +10001a10: 2520 movs r5, #32 +10001a12: 1e69 subs r1, r5, #1 +10001a14: ab0e add r3, sp, #56 @ 0x38 +10001a16: 4861 ldr r0, [pc, #388] @ (10001b9c <_ftoa+0x30c>) +10001a18: 4419 add r1, r3 +10001a1a: e010 b.n 10001a3e <_ftoa+0x1ae> +10001a1c: fb80 6204 smull r6, r2, r0, r4 +10001a20: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001a24: eb03 0283 add.w r2, r3, r3, lsl #2 +10001a28: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001a2c: f104 0230 add.w r2, r4, #48 @ 0x30 +10001a30: 3501 adds r5, #1 +10001a32: 461c mov r4, r3 +10001a34: f801 2f01 strb.w r2, [r1, #1]! +10001a38: 2b00 cmp r3, #0 +10001a3a: f000 80eb beq.w 10001c14 <_ftoa+0x384> +10001a3e: 2d20 cmp r5, #32 +10001a40: ea4f 73e4 mov.w r3, r4, asr #31 +10001a44: d1ea bne.n 10001a1c <_ftoa+0x18c> +10001a46: 9b07 ldr r3, [sp, #28] +10001a48: f003 0303 and.w r3, r3, #3 +10001a4c: 2b01 cmp r3, #1 +10001a4e: d118 bne.n 10001a82 <_ftoa+0x1f2> +10001a50: f1bb 0f00 cmp.w fp, #0 +10001a54: d015 beq.n 10001a82 <_ftoa+0x1f2> +10001a56: 9b0d ldr r3, [sp, #52] @ 0x34 +10001a58: 2b00 cmp r3, #0 +10001a5a: f000 810a beq.w 10001c72 <_ftoa+0x3e2> +10001a5e: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001a62: f1bb 0f20 cmp.w fp, #32 +10001a66: d90c bls.n 10001a82 <_ftoa+0x1f2> +10001a68: 1e6b subs r3, r5, #1 +10001a6a: a90e add r1, sp, #56 @ 0x38 +10001a6c: 2230 movs r2, #48 @ 0x30 +10001a6e: 440b add r3, r1 +10001a70: e005 b.n 10001a7e <_ftoa+0x1ee> +10001a72: 3501 adds r5, #1 +10001a74: 455d cmp r5, fp +10001a76: f803 2f01 strb.w r2, [r3, #1]! +10001a7a: f080 80d1 bcs.w 10001c20 <_ftoa+0x390> +10001a7e: 2d20 cmp r5, #32 +10001a80: d1f7 bne.n 10001a72 <_ftoa+0x1e2> +10001a82: 9b07 ldr r3, [sp, #28] +10001a84: ac0e add r4, sp, #56 @ 0x38 +10001a86: e9cd b302 strd fp, r3, [sp, #8] +10001a8a: 4641 mov r1, r8 +10001a8c: 464b mov r3, r9 +10001a8e: 4638 mov r0, r7 +10001a90: 9a0c ldr r2, [sp, #48] @ 0x30 +10001a92: 9501 str r5, [sp, #4] +10001a94: 9400 str r4, [sp, #0] +10001a96: f7ff fdb9 bl 1000160c <_out_rev> +10001a9a: 4682 mov sl, r0 +10001a9c: 4650 mov r0, sl +10001a9e: b017 add sp, #92 @ 0x5c +10001aa0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001aa4: 9b07 ldr r3, [sp, #28] +10001aa6: ed9d 7b04 vldr d7, [sp, #16] +10001aaa: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001aae: 4641 mov r1, r8 +10001ab0: 464b mov r3, r9 +10001ab2: 4638 mov r0, r7 +10001ab4: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ab6: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001aba: 9522 str r5, [sp, #136] @ 0x88 +10001abc: b017 add sp, #92 @ 0x5c +10001abe: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ac2: f000 b945 b.w 10001d50 <_etoa> +10001ac6: 0761 lsls r1, r4, #29 +10001ac8: 4623 mov r3, r4 +10001aca: bf4c ite mi +10001acc: 2304 movmi r3, #4 +10001ace: 2303 movpl r3, #3 +10001ad0: 4641 mov r1, r8 +10001ad2: 9321 str r3, [sp, #132] @ 0x84 +10001ad4: 4638 mov r0, r7 +10001ad6: 464b mov r3, r9 +10001ad8: 9a07 ldr r2, [sp, #28] +10001ada: bf48 it mi +10001adc: 4c30 ldrmi r4, [pc, #192] @ (10001ba0 <_ftoa+0x310>) +10001ade: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001ae2: bf58 it pl +10001ae4: 4c2f ldrpl r4, [pc, #188] @ (10001ba4 <_ftoa+0x314>) +10001ae6: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ae8: 9420 str r4, [sp, #128] @ 0x80 +10001aea: b017 add sp, #92 @ 0x5c +10001aec: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001af0: f7ff bd8c b.w 1000160c <_out_rev> +10001af4: e9dd 2304 ldrd r2, r3, [sp, #16] +10001af8: 2000 movs r0, #0 +10001afa: 2100 movs r1, #0 +10001afc: f7ff fc56 bl 100013ac <__wrap___aeabi_dsub> +10001b00: 2301 movs r3, #1 +10001b02: e9cd 0104 strd r0, r1, [sp, #16] +10001b06: 930d str r3, [sp, #52] @ 0x34 +10001b08: 4623 mov r3, r4 +10001b0a: e70d b.n 10001928 <_ftoa+0x98> +10001b0c: 4623 mov r3, r4 +10001b0e: 079c lsls r4, r3, #30 +10001b10: f040 80aa bne.w 10001c68 <_ftoa+0x3d8> +10001b14: f1bb 0f04 cmp.w fp, #4 +10001b18: f240 80a6 bls.w 10001c68 <_ftoa+0x3d8> +10001b1c: 9b0c ldr r3, [sp, #48] @ 0x30 +10001b1e: 461d mov r5, r3 +10001b20: 1f1c subs r4, r3, #4 +10001b22: eb04 0a0b add.w sl, r4, fp +10001b26: 462a mov r2, r5 +10001b28: 464b mov r3, r9 +10001b2a: 4641 mov r1, r8 +10001b2c: 2020 movs r0, #32 +10001b2e: 3501 adds r5, #1 +10001b30: 47b8 blx r7 +10001b32: 45aa cmp sl, r5 +10001b34: d1f7 bne.n 10001b26 <_ftoa+0x296> +10001b36: 4655 mov r5, sl +10001b38: 4c1b ldr r4, [pc, #108] @ (10001ba8 <_ftoa+0x318>) +10001b3a: 1f26 subs r6, r4, #4 +10001b3c: f814 0d01 ldrb.w r0, [r4, #-1]! +10001b40: 462a mov r2, r5 +10001b42: 464b mov r3, r9 +10001b44: 4641 mov r1, r8 +10001b46: 47b8 blx r7 +10001b48: 42b4 cmp r4, r6 +10001b4a: f105 0501 add.w r5, r5, #1 +10001b4e: d1f5 bne.n 10001b3c <_ftoa+0x2ac> +10001b50: 9b07 ldr r3, [sp, #28] +10001b52: f10a 0a04 add.w sl, sl, #4 +10001b56: 0798 lsls r0, r3, #30 +10001b58: d5a0 bpl.n 10001a9c <_ftoa+0x20c> +10001b5a: 9c0c ldr r4, [sp, #48] @ 0x30 +10001b5c: ebaa 0304 sub.w r3, sl, r4 +10001b60: 459b cmp fp, r3 +10001b62: d99b bls.n 10001a9c <_ftoa+0x20c> +10001b64: 4652 mov r2, sl +10001b66: 464b mov r3, r9 +10001b68: 4641 mov r1, r8 +10001b6a: 2020 movs r0, #32 +10001b6c: f10a 0a01 add.w sl, sl, #1 +10001b70: 47b8 blx r7 +10001b72: ebaa 0304 sub.w r3, sl, r4 +10001b76: 455b cmp r3, fp +10001b78: d3f4 bcc.n 10001b64 <_ftoa+0x2d4> +10001b7a: e78f b.n 10001a9c <_ftoa+0x20c> +10001b7c: f3af 8000 nop.w +10001b80: 00000000 .word 0x00000000 +10001b84: 41cdcd65 .word 0x41cdcd65 +10001b88: 00000000 .word 0x00000000 +10001b8c: c1cdcd65 .word 0xc1cdcd65 +10001b90: 7fefffff .word 0x7fefffff +10001b94: 100035f8 .word 0x100035f8 +10001b98: 3fe00000 .word 0x3fe00000 +10001b9c: 66666667 .word 0x66666667 +10001ba0: 10003550 .word 0x10003550 +10001ba4: 10003558 .word 0x10003558 +10001ba8: 10003564 .word 0x10003564 +10001bac: cccccccd .word 0xcccccccd +10001bb0: 2200 movs r2, #0 +10001bb2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001bb6: 4b63 ldr r3, [pc, #396] @ (10001d44 <_ftoa+0x4b4>) +10001bb8: f7ff fcda bl 10001570 <__wrap___aeabi_dcmplt> +10001bbc: 2800 cmp r0, #0 +10001bbe: f47f af08 bne.w 100019d2 <_ftoa+0x142> +10001bc2: f1ba 0f00 cmp.w sl, #0 +10001bc6: d16a bne.n 10001c9e <_ftoa+0x40e> +10001bc8: f10a 0a01 add.w sl, sl, #1 +10001bcc: 2e00 cmp r6, #0 +10001bce: f47f af03 bne.w 100019d8 <_ftoa+0x148> +10001bd2: 4620 mov r0, r4 +10001bd4: f7ff fc72 bl 100014bc <__wrap___aeabi_i2d> +10001bd8: 4602 mov r2, r0 +10001bda: 460b mov r3, r1 +10001bdc: e9dd 0104 ldrd r0, r1, [sp, #16] +10001be0: f7ff fbe4 bl 100013ac <__wrap___aeabi_dsub> +10001be4: 4602 mov r2, r0 +10001be6: 460b mov r3, r1 +10001be8: e9cd 2304 strd r2, r3, [sp, #16] +10001bec: 2200 movs r2, #0 +10001bee: 4b55 ldr r3, [pc, #340] @ (10001d44 <_ftoa+0x4b4>) +10001bf0: f7ff fcbe bl 10001570 <__wrap___aeabi_dcmplt> +10001bf4: 2800 cmp r0, #0 +10001bf6: f47f af0c bne.w 10001a12 <_ftoa+0x182> +10001bfa: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bfe: 2200 movs r2, #0 +10001c00: 4b50 ldr r3, [pc, #320] @ (10001d44 <_ftoa+0x4b4>) +10001c02: f7ff fcf1 bl 100015e8 <__wrap___aeabi_dcmpgt> +10001c06: 2800 cmp r0, #0 +10001c08: f47f af03 bne.w 10001a12 <_ftoa+0x182> +10001c0c: 3401 adds r4, #1 +10001c0e: f024 0401 bic.w r4, r4, #1 +10001c12: e6fe b.n 10001a12 <_ftoa+0x182> +10001c14: 9b07 ldr r3, [sp, #28] +10001c16: f003 0303 and.w r3, r3, #3 +10001c1a: 2b01 cmp r3, #1 +10001c1c: f000 8082 beq.w 10001d24 <_ftoa+0x494> +10001c20: 2d20 cmp r5, #32 +10001c22: f43f af2e beq.w 10001a82 <_ftoa+0x1f2> +10001c26: 9b0d ldr r3, [sp, #52] @ 0x34 +10001c28: b37b cbz r3, 10001c8a <_ftoa+0x3fa> +10001c2a: 222d movs r2, #45 @ 0x2d +10001c2c: eb0d 0305 add.w r3, sp, r5 +10001c30: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c34: 3501 adds r5, #1 +10001c36: e724 b.n 10001a82 <_ftoa+0x1f2> +10001c38: 2b20 cmp r3, #32 +10001c3a: f43f aee9 beq.w 10001a10 <_ftoa+0x180> +10001c3e: aa0e add r2, sp, #56 @ 0x38 +10001c40: 4415 add r5, r2 +10001c42: 441e add r6, r3 +10001c44: 2230 movs r2, #48 @ 0x30 +10001c46: e004 b.n 10001c52 <_ftoa+0x3c2> +10001c48: 2b20 cmp r3, #32 +10001c4a: f805 2f01 strb.w r2, [r5, #1]! +10001c4e: f43f aedf beq.w 10001a10 <_ftoa+0x180> +10001c52: 429e cmp r6, r3 +10001c54: f103 0301 add.w r3, r3, #1 +10001c58: d1f6 bne.n 10001c48 <_ftoa+0x3b8> +10001c5a: 222e movs r2, #46 @ 0x2e +10001c5c: eb0d 0306 add.w r3, sp, r6 +10001c60: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c64: 1c75 adds r5, r6, #1 +10001c66: e6d4 b.n 10001a12 <_ftoa+0x182> +10001c68: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001c6c: e763 b.n 10001b36 <_ftoa+0x2a6> +10001c6e: 2520 movs r5, #32 +10001c70: e66e b.n 10001950 <_ftoa+0xc0> +10001c72: 9b07 ldr r3, [sp, #28] +10001c74: f013 0f0c tst.w r3, #12 +10001c78: d050 beq.n 10001d1c <_ftoa+0x48c> +10001c7a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001c7e: 45ab cmp fp, r5 +10001c80: f63f aef2 bhi.w 10001a68 <_ftoa+0x1d8> +10001c84: 2d20 cmp r5, #32 +10001c86: f43f aefc beq.w 10001a82 <_ftoa+0x1f2> +10001c8a: 9b07 ldr r3, [sp, #28] +10001c8c: 075a lsls r2, r3, #29 +10001c8e: d501 bpl.n 10001c94 <_ftoa+0x404> +10001c90: 222b movs r2, #43 @ 0x2b +10001c92: e7cb b.n 10001c2c <_ftoa+0x39c> +10001c94: 071b lsls r3, r3, #28 +10001c96: f57f aef4 bpl.w 10001a82 <_ftoa+0x1f2> +10001c9a: 2220 movs r2, #32 +10001c9c: e7c6 b.n 10001c2c <_ftoa+0x39c> +10001c9e: f01a 0f01 tst.w sl, #1 +10001ca2: f43f ae96 beq.w 100019d2 <_ftoa+0x142> +10001ca6: e78f b.n 10001bc8 <_ftoa+0x338> +10001ca8: 07a6 lsls r6, r4, #30 +10001caa: d134 bne.n 10001d16 <_ftoa+0x486> +10001cac: f1bb 0f03 cmp.w fp, #3 +10001cb0: d931 bls.n 10001d16 <_ftoa+0x486> +10001cb2: 9b0c ldr r3, [sp, #48] @ 0x30 +10001cb4: 461d mov r5, r3 +10001cb6: 1edc subs r4, r3, #3 +10001cb8: eb04 0a0b add.w sl, r4, fp +10001cbc: 462a mov r2, r5 +10001cbe: 464b mov r3, r9 +10001cc0: 4641 mov r1, r8 +10001cc2: 2020 movs r0, #32 +10001cc4: 3501 adds r5, #1 +10001cc6: 47b8 blx r7 +10001cc8: 4555 cmp r5, sl +10001cca: d1f7 bne.n 10001cbc <_ftoa+0x42c> +10001ccc: 4655 mov r5, sl +10001cce: 4c1e ldr r4, [pc, #120] @ (10001d48 <_ftoa+0x4b8>) +10001cd0: 1ee6 subs r6, r4, #3 +10001cd2: f814 0d01 ldrb.w r0, [r4, #-1]! +10001cd6: 462a mov r2, r5 +10001cd8: 464b mov r3, r9 +10001cda: 4641 mov r1, r8 +10001cdc: 47b8 blx r7 +10001cde: 42a6 cmp r6, r4 +10001ce0: f105 0501 add.w r5, r5, #1 +10001ce4: d1f5 bne.n 10001cd2 <_ftoa+0x442> +10001ce6: 9b07 ldr r3, [sp, #28] +10001ce8: f10a 0a03 add.w sl, sl, #3 +10001cec: 079d lsls r5, r3, #30 +10001cee: f57f aed5 bpl.w 10001a9c <_ftoa+0x20c> +10001cf2: 9c0c ldr r4, [sp, #48] @ 0x30 +10001cf4: ebaa 0304 sub.w r3, sl, r4 +10001cf8: 459b cmp fp, r3 +10001cfa: f67f aecf bls.w 10001a9c <_ftoa+0x20c> +10001cfe: 4652 mov r2, sl +10001d00: 464b mov r3, r9 +10001d02: 4641 mov r1, r8 +10001d04: 2020 movs r0, #32 +10001d06: f10a 0a01 add.w sl, sl, #1 +10001d0a: 47b8 blx r7 +10001d0c: ebaa 0304 sub.w r3, sl, r4 +10001d10: 459b cmp fp, r3 +10001d12: d8f4 bhi.n 10001cfe <_ftoa+0x46e> +10001d14: e6c2 b.n 10001a9c <_ftoa+0x20c> +10001d16: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001d1a: e7d7 b.n 10001ccc <_ftoa+0x43c> +10001d1c: 45ab cmp fp, r5 +10001d1e: f63f aea3 bhi.w 10001a68 <_ftoa+0x1d8> +10001d22: e6ae b.n 10001a82 <_ftoa+0x1f2> +10001d24: f1bb 0f00 cmp.w fp, #0 +10001d28: f43f af7a beq.w 10001c20 <_ftoa+0x390> +10001d2c: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d2e: 2b00 cmp r3, #0 +10001d30: d09f beq.n 10001c72 <_ftoa+0x3e2> +10001d32: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d36: 455d cmp r5, fp +10001d38: f4ff ae96 bcc.w 10001a68 <_ftoa+0x1d8> +10001d3c: 2d20 cmp r5, #32 +10001d3e: f47f af74 bne.w 10001c2a <_ftoa+0x39a> +10001d42: e69e b.n 10001a82 <_ftoa+0x1f2> +10001d44: 3fe00000 .word 0x3fe00000 +10001d48: 1000355f .word 0x1000355f +10001d4c: 00000000 .word 0x00000000 + +10001d50 <_etoa>: +10001d50: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001d54: b09f sub sp, #124 @ 0x7c +10001d56: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001d58: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001d5c: 4607 mov r7, r0 +10001d5e: 4693 mov fp, r2 +10001d60: 9108 str r1, [sp, #32] +10001d62: 9309 str r3, [sp, #36] @ 0x24 +10001d64: 4622 mov r2, r4 +10001d66: 462b mov r3, r5 +10001d68: 4620 mov r0, r4 +10001d6a: 4629 mov r1, r5 +10001d6c: 960e str r6, [sp, #56] @ 0x38 +10001d6e: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001d72: f7ff fbeb bl 1000154c <__wrap___aeabi_dcmpun> +10001d76: 2800 cmp r0, #0 +10001d78: f040 80be bne.w 10001ef8 <_etoa+0x1a8> +10001d7c: 4620 mov r0, r4 +10001d7e: 4629 mov r1, r5 +10001d80: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d84: 4b78 ldr r3, [pc, #480] @ (10001f68 <_etoa+0x218>) +10001d86: f7ff fc2f bl 100015e8 <__wrap___aeabi_dcmpgt> +10001d8a: 2800 cmp r0, #0 +10001d8c: f040 80b4 bne.w 10001ef8 <_etoa+0x1a8> +10001d90: 4620 mov r0, r4 +10001d92: 4629 mov r1, r5 +10001d94: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d98: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001d9c: f7ff fbe8 bl 10001570 <__wrap___aeabi_dcmplt> +10001da0: 2800 cmp r0, #0 +10001da2: f040 80a9 bne.w 10001ef8 <_etoa+0x1a8> +10001da6: 4620 mov r0, r4 +10001da8: 4629 mov r1, r5 +10001daa: 2200 movs r2, #0 +10001dac: 2300 movs r3, #0 +10001dae: f7ff fbdf bl 10001570 <__wrap___aeabi_dcmplt> +10001db2: 2800 cmp r0, #0 +10001db4: f040 81d5 bne.w 10002162 <_etoa+0x412> +10001db8: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001dbc: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001dc0: 4690 mov r8, r2 +10001dc2: 4699 mov r9, r3 +10001dc4: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001dc8: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001dcc: 920f str r2, [sp, #60] @ 0x3c +10001dce: 9313 str r3, [sp, #76] @ 0x4c +10001dd0: f040 80a1 bne.w 10001f16 <_etoa+0x1c6> +10001dd4: ea58 0309 orrs.w r3, r8, r9 +10001dd8: f040 80ca bne.w 10001f70 <_etoa+0x220> +10001ddc: 2a00 cmp r2, #0 +10001dde: f040 81e3 bne.w 100021a8 <_etoa+0x458> +10001de2: 2306 movs r3, #6 +10001de4: 930e str r3, [sp, #56] @ 0x38 +10001de6: f016 0202 ands.w r2, r6, #2 +10001dea: 9210 str r2, [sp, #64] @ 0x40 +10001dec: f040 81d4 bne.w 10002198 <_etoa+0x448> +10001df0: 4653 mov r3, sl +10001df2: 2b04 cmp r3, #4 +10001df4: bf38 it cc +10001df6: 2304 movcc r3, #4 +10001df8: 920c str r2, [sp, #48] @ 0x30 +10001dfa: 2204 movs r2, #4 +10001dfc: 3b04 subs r3, #4 +10001dfe: 9212 str r2, [sp, #72] @ 0x48 +10001e00: 930f str r3, [sp, #60] @ 0x3c +10001e02: 4620 mov r0, r4 +10001e04: 4629 mov r1, r5 +10001e06: 2200 movs r2, #0 +10001e08: 2300 movs r3, #0 +10001e0a: f7ff fbb1 bl 10001570 <__wrap___aeabi_dcmplt> +10001e0e: 2800 cmp r0, #0 +10001e10: f040 81f3 bne.w 100021fa <_etoa+0x4aa> +10001e14: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001e18: 9b0f ldr r3, [sp, #60] @ 0x3c +10001e1a: 465a mov r2, fp +10001e1c: 9303 str r3, [sp, #12] +10001e1e: 9b0e ldr r3, [sp, #56] @ 0x38 +10001e20: ed8d 7b00 vstr d7, [sp] +10001e24: 9302 str r3, [sp, #8] +10001e26: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001e2a: 9304 str r3, [sp, #16] +10001e2c: 4638 mov r0, r7 +10001e2e: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e30: 9908 ldr r1, [sp, #32] +10001e32: f7ff fd2d bl 10001890 <_ftoa> +10001e36: 4602 mov r2, r0 +10001e38: f016 0f20 tst.w r6, #32 +10001e3c: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e3e: 9908 ldr r1, [sp, #32] +10001e40: bf0c ite eq +10001e42: 2065 moveq r0, #101 @ 0x65 +10001e44: 2045 movne r0, #69 @ 0x45 +10001e46: f102 0801 add.w r8, r2, #1 +10001e4a: 47b8 blx r7 +10001e4c: 9a0c ldr r2, [sp, #48] @ 0x30 +10001e4e: 9b12 ldr r3, [sp, #72] @ 0x48 +10001e50: ac16 add r4, sp, #88 @ 0x58 +10001e52: 1e5d subs r5, r3, #1 +10001e54: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001e58: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001e5c: 0fd1 lsrs r1, r2, #31 +10001e5e: 2600 movs r6, #0 +10001e60: 4622 mov r2, r4 +10001e62: 4699 mov r9, r3 +10001e64: f8df c104 ldr.w ip, [pc, #260] @ 10001f6c <_etoa+0x21c> +10001e68: e001 b.n 10001e6e <_etoa+0x11e> +10001e6a: 2e20 cmp r6, #32 +10001e6c: d010 beq.n 10001e90 <_etoa+0x140> +10001e6e: 46ce mov lr, r9 +10001e70: fbac 3009 umull r3, r0, ip, r9 +10001e74: 08c0 lsrs r0, r0, #3 +10001e76: eb00 0380 add.w r3, r0, r0, lsl #2 +10001e7a: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001e7e: 3330 adds r3, #48 @ 0x30 +10001e80: f1be 0f09 cmp.w lr, #9 +10001e84: 4681 mov r9, r0 +10001e86: f106 0601 add.w r6, r6, #1 +10001e8a: f802 3b01 strb.w r3, [r2], #1 +10001e8e: d8ec bhi.n 10001e6a <_etoa+0x11a> +10001e90: 2305 movs r3, #5 +10001e92: 2000 movs r0, #0 +10001e94: 9306 str r3, [sp, #24] +10001e96: 230a movs r3, #10 +10001e98: 9505 str r5, [sp, #20] +10001e9a: 9400 str r4, [sp, #0] +10001e9c: 9d09 ldr r5, [sp, #36] @ 0x24 +10001e9e: 9c08 ldr r4, [sp, #32] +10001ea0: 4642 mov r2, r8 +10001ea2: e9cd 3003 strd r3, r0, [sp, #12] +10001ea6: e9cd 6101 strd r6, r1, [sp, #4] +10001eaa: 462b mov r3, r5 +10001eac: 4621 mov r1, r4 +10001eae: 4638 mov r0, r7 +10001eb0: f7ff fbfa bl 100016a8 <_ntoa_format> +10001eb4: 9a10 ldr r2, [sp, #64] @ 0x40 +10001eb6: 4680 mov r8, r0 +10001eb8: b1d2 cbz r2, 10001ef0 <_etoa+0x1a0> +10001eba: eba0 060b sub.w r6, r0, fp +10001ebe: 45b2 cmp sl, r6 +10001ec0: d916 bls.n 10001ef0 <_etoa+0x1a0> +10001ec2: eb0b 0206 add.w r2, fp, r6 +10001ec6: 462b mov r3, r5 +10001ec8: 4621 mov r1, r4 +10001eca: 2020 movs r0, #32 +10001ecc: 3601 adds r6, #1 +10001ece: 47b8 blx r7 +10001ed0: 45b2 cmp sl, r6 +10001ed2: d8f6 bhi.n 10001ec2 <_etoa+0x172> +10001ed4: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10001ed8: 4453 add r3, sl +10001eda: f1cb 0201 rsb r2, fp, #1 +10001ede: eba3 0308 sub.w r3, r3, r8 +10001ee2: 4442 add r2, r8 +10001ee4: 4592 cmp sl, r2 +10001ee6: bf38 it cc +10001ee8: 2300 movcc r3, #0 +10001eea: f108 0801 add.w r8, r8, #1 +10001eee: 4498 add r8, r3 +10001ef0: 4640 mov r0, r8 +10001ef2: b01f add sp, #124 @ 0x7c +10001ef4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001ef8: 465a mov r2, fp +10001efa: 4638 mov r0, r7 +10001efc: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10001f00: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10001f04: 9c0e ldr r4, [sp, #56] @ 0x38 +10001f06: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f08: 9908 ldr r1, [sp, #32] +10001f0a: 942a str r4, [sp, #168] @ 0xa8 +10001f0c: b01f add sp, #124 @ 0x7c +10001f0e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f12: f7ff bcbd b.w 10001890 <_ftoa> +10001f16: ea58 0309 orrs.w r3, r8, r9 +10001f1a: d12b bne.n 10001f74 <_etoa+0x224> +10001f1c: 2a00 cmp r2, #0 +10001f1e: f43f af62 beq.w 10001de6 <_etoa+0x96> +10001f22: 2300 movs r3, #0 +10001f24: 930c str r3, [sp, #48] @ 0x30 +10001f26: 9b0e ldr r3, [sp, #56] @ 0x38 +10001f28: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f2a: 4293 cmp r3, r2 +10001f2c: f300 81b9 bgt.w 100022a2 <_etoa+0x552> +10001f30: f04f 0800 mov.w r8, #0 +10001f34: 4620 mov r0, r4 +10001f36: 4629 mov r1, r5 +10001f38: 2200 movs r2, #0 +10001f3a: 2300 movs r3, #0 +10001f3c: f7ff fb18 bl 10001570 <__wrap___aeabi_dcmplt> +10001f40: 2800 cmp r0, #0 +10001f42: f040 8113 bne.w 1000216c <_etoa+0x41c> +10001f46: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001f4a: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10001f4e: f446 6680 orr.w r6, r6, #1024 @ 0x400 +10001f52: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +10001f56: 465a mov r2, fp +10001f58: 4638 mov r0, r7 +10001f5a: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10001f5e: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f60: 9908 ldr r1, [sp, #32] +10001f62: 962c str r6, [sp, #176] @ 0xb0 +10001f64: e7d2 b.n 10001f0c <_etoa+0x1bc> +10001f66: bf00 nop +10001f68: 7fefffff .word 0x7fefffff +10001f6c: cccccccd .word 0xcccccccd +10001f70: 2306 movs r3, #6 +10001f72: 930e str r3, [sp, #56] @ 0x38 +10001f74: f3c9 500a ubfx r0, r9, #20, #11 +10001f78: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10001f7c: f7ff fa9e bl 100014bc <__wrap___aeabi_i2d> +10001f80: a3c1 add r3, pc, #772 @ (adr r3, 10002288 <_etoa+0x538>) +10001f82: e9d3 2300 ldrd r2, r3, [r3] +10001f86: f7ff fa25 bl 100013d4 <__wrap___aeabi_dmul> +10001f8a: a3c1 add r3, pc, #772 @ (adr r3, 10002290 <_etoa+0x540>) +10001f8c: e9d3 2300 ldrd r2, r3, [r3] +10001f90: f7ff f9f8 bl 10001384 <__wrap___aeabi_dadd> +10001f94: f3c9 0913 ubfx r9, r9, #0, #20 +10001f98: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10001f9c: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10001fa0: 4640 mov r0, r8 +10001fa2: 2200 movs r2, #0 +10001fa4: 4bb2 ldr r3, [pc, #712] @ (10002270 <_etoa+0x520>) +10001fa6: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10001faa: f7ff f9ff bl 100013ac <__wrap___aeabi_dsub> +10001fae: a3a4 add r3, pc, #656 @ (adr r3, 10002240 <_etoa+0x4f0>) +10001fb0: e9d3 2300 ldrd r2, r3, [r3] +10001fb4: f7ff fa0e bl 100013d4 <__wrap___aeabi_dmul> +10001fb8: 4602 mov r2, r0 +10001fba: 460b mov r3, r1 +10001fbc: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10001fc0: f7ff f9e0 bl 10001384 <__wrap___aeabi_dadd> +10001fc4: f7ff fa9e bl 10001504 <__wrap___aeabi_d2iz> +10001fc8: 900c str r0, [sp, #48] @ 0x30 +10001fca: f7ff fa77 bl 100014bc <__wrap___aeabi_i2d> +10001fce: a39e add r3, pc, #632 @ (adr r3, 10002248 <_etoa+0x4f8>) +10001fd0: e9d3 2300 ldrd r2, r3, [r3] +10001fd4: 4680 mov r8, r0 +10001fd6: 4689 mov r9, r1 +10001fd8: f7ff f9fc bl 100013d4 <__wrap___aeabi_dmul> +10001fdc: 2200 movs r2, #0 +10001fde: 4ba5 ldr r3, [pc, #660] @ (10002274 <_etoa+0x524>) +10001fe0: f7ff f9d0 bl 10001384 <__wrap___aeabi_dadd> +10001fe4: f7ff fa8e bl 10001504 <__wrap___aeabi_d2iz> +10001fe8: 4603 mov r3, r0 +10001fea: 4649 mov r1, r9 +10001fec: 4640 mov r0, r8 +10001fee: 9312 str r3, [sp, #72] @ 0x48 +10001ff0: a397 add r3, pc, #604 @ (adr r3, 10002250 <_etoa+0x500>) +10001ff2: e9d3 2300 ldrd r2, r3, [r3] +10001ff6: f7ff f9ed bl 100013d4 <__wrap___aeabi_dmul> +10001ffa: 4680 mov r8, r0 +10001ffc: 9812 ldr r0, [sp, #72] @ 0x48 +10001ffe: 4689 mov r9, r1 +10002000: f7ff fa5c bl 100014bc <__wrap___aeabi_i2d> +10002004: a394 add r3, pc, #592 @ (adr r3, 10002258 <_etoa+0x508>) +10002006: e9d3 2300 ldrd r2, r3, [r3] +1000200a: f7ff f9e3 bl 100013d4 <__wrap___aeabi_dmul> +1000200e: 4602 mov r2, r0 +10002010: 460b mov r3, r1 +10002012: 4640 mov r0, r8 +10002014: 4649 mov r1, r9 +10002016: f7ff f9c9 bl 100013ac <__wrap___aeabi_dsub> +1000201a: 4602 mov r2, r0 +1000201c: 460b mov r3, r1 +1000201e: 4680 mov r8, r0 +10002020: 4689 mov r9, r1 +10002022: f7ff f9d7 bl 100013d4 <__wrap___aeabi_dmul> +10002026: 4642 mov r2, r8 +10002028: 464b mov r3, r9 +1000202a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +1000202e: 4640 mov r0, r8 +10002030: 4649 mov r1, r9 +10002032: f7ff f9a7 bl 10001384 <__wrap___aeabi_dadd> +10002036: 2200 movs r2, #0 +10002038: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +1000203c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002040: 4b8d ldr r3, [pc, #564] @ (10002278 <_etoa+0x528>) +10002042: f7ff f9ed bl 10001420 <__wrap___aeabi_ddiv> +10002046: 2200 movs r2, #0 +10002048: 4b8c ldr r3, [pc, #560] @ (1000227c <_etoa+0x52c>) +1000204a: f7ff f99b bl 10001384 <__wrap___aeabi_dadd> +1000204e: 4602 mov r2, r0 +10002050: 460b mov r3, r1 +10002052: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002056: f7ff f9e3 bl 10001420 <__wrap___aeabi_ddiv> +1000205a: 2200 movs r2, #0 +1000205c: 4b88 ldr r3, [pc, #544] @ (10002280 <_etoa+0x530>) +1000205e: f7ff f991 bl 10001384 <__wrap___aeabi_dadd> +10002062: 4602 mov r2, r0 +10002064: 460b mov r3, r1 +10002066: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000206a: f7ff f9d9 bl 10001420 <__wrap___aeabi_ddiv> +1000206e: 4642 mov r2, r8 +10002070: 464b mov r3, r9 +10002072: 4680 mov r8, r0 +10002074: 4689 mov r9, r1 +10002076: 2000 movs r0, #0 +10002078: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +1000207c: f7ff f996 bl 100013ac <__wrap___aeabi_dsub> +10002080: 4602 mov r2, r0 +10002082: 460b mov r3, r1 +10002084: 4640 mov r0, r8 +10002086: 4649 mov r1, r9 +10002088: f7ff f97c bl 10001384 <__wrap___aeabi_dadd> +1000208c: 4602 mov r2, r0 +1000208e: 460b mov r3, r1 +10002090: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +10002094: f7ff f9c4 bl 10001420 <__wrap___aeabi_ddiv> +10002098: 2200 movs r2, #0 +1000209a: 4b7a ldr r3, [pc, #488] @ (10002284 <_etoa+0x534>) +1000209c: f7ff f972 bl 10001384 <__wrap___aeabi_dadd> +100020a0: 9b12 ldr r3, [sp, #72] @ 0x48 +100020a2: 2200 movs r2, #0 +100020a4: f203 3cff addw ip, r3, #1023 @ 0x3ff +100020a8: ea4f 530c mov.w r3, ip, lsl #20 +100020ac: f7ff f992 bl 100013d4 <__wrap___aeabi_dmul> +100020b0: 4680 mov r8, r0 +100020b2: 4689 mov r9, r1 +100020b4: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100020b8: 4642 mov r2, r8 +100020ba: 464b mov r3, r9 +100020bc: f7ff fa58 bl 10001570 <__wrap___aeabi_dcmplt> +100020c0: b150 cbz r0, 100020d8 <_etoa+0x388> +100020c2: 9b0c ldr r3, [sp, #48] @ 0x30 +100020c4: 4640 mov r0, r8 +100020c6: 3b01 subs r3, #1 +100020c8: 4649 mov r1, r9 +100020ca: 930c str r3, [sp, #48] @ 0x30 +100020cc: 2200 movs r2, #0 +100020ce: 4b6b ldr r3, [pc, #428] @ (1000227c <_etoa+0x52c>) +100020d0: f7ff f9a6 bl 10001420 <__wrap___aeabi_ddiv> +100020d4: 4680 mov r8, r0 +100020d6: 4689 mov r9, r1 +100020d8: 9a0c ldr r2, [sp, #48] @ 0x30 +100020da: 4643 mov r3, r8 +100020dc: 3263 adds r2, #99 @ 0x63 +100020de: 2ac6 cmp r2, #198 @ 0xc6 +100020e0: f006 0202 and.w r2, r6, #2 +100020e4: 9210 str r2, [sp, #64] @ 0x40 +100020e6: 4649 mov r1, r9 +100020e8: 9a0f ldr r2, [sp, #60] @ 0x3c +100020ea: d82c bhi.n 10002146 <_etoa+0x3f6> +100020ec: 2a00 cmp r2, #0 +100020ee: d05e beq.n 100021ae <_etoa+0x45e> +100020f0: 2204 movs r2, #4 +100020f2: 9212 str r2, [sp, #72] @ 0x48 +100020f4: 430b orrs r3, r1 +100020f6: f43f af16 beq.w 10001f26 <_etoa+0x1d6> +100020fa: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100020fe: a358 add r3, pc, #352 @ (adr r3, 10002260 <_etoa+0x510>) +10002100: e9d3 2300 ldrd r2, r3, [r3] +10002104: f7ff fa5c bl 100015c0 <__wrap___aeabi_dcmpge> +10002108: b148 cbz r0, 1000211e <_etoa+0x3ce> +1000210a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000210e: a356 add r3, pc, #344 @ (adr r3, 10002268 <_etoa+0x518>) +10002110: e9d3 2300 ldrd r2, r3, [r3] +10002114: f7ff fa2c bl 10001570 <__wrap___aeabi_dcmplt> +10002118: 2800 cmp r0, #0 +1000211a: f47f af04 bne.w 10001f26 <_etoa+0x1d6> +1000211e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002120: 2b00 cmp r3, #0 +10002122: d050 beq.n 100021c6 <_etoa+0x476> +10002124: 9a13 ldr r2, [sp, #76] @ 0x4c +10002126: 2a00 cmp r2, #0 +10002128: d07d beq.n 10002226 <_etoa+0x4d6> +1000212a: 3b01 subs r3, #1 +1000212c: 930e str r3, [sp, #56] @ 0x38 +1000212e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002130: 459a cmp sl, r3 +10002132: d905 bls.n 10002140 <_etoa+0x3f0> +10002134: 9b10 ldr r3, [sp, #64] @ 0x40 +10002136: 2b00 cmp r3, #0 +10002138: f000 80ae beq.w 10002298 <_etoa+0x548> +1000213c: 2302 movs r3, #2 +1000213e: 9310 str r3, [sp, #64] @ 0x40 +10002140: 2300 movs r3, #0 +10002142: 930f str r3, [sp, #60] @ 0x3c +10002144: e044 b.n 100021d0 <_etoa+0x480> +10002146: bb22 cbnz r2, 10002192 <_etoa+0x442> +10002148: f1ba 0f05 cmp.w sl, #5 +1000214c: d94f bls.n 100021ee <_etoa+0x49e> +1000214e: f006 0302 and.w r3, r6, #2 +10002152: 2b00 cmp r3, #0 +10002154: d149 bne.n 100021ea <_etoa+0x49a> +10002156: 2305 movs r3, #5 +10002158: 9312 str r3, [sp, #72] @ 0x48 +1000215a: f1aa 0305 sub.w r3, sl, #5 +1000215e: 930f str r3, [sp, #60] @ 0x3c +10002160: e03a b.n 100021d8 <_etoa+0x488> +10002162: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +10002166: 940a str r4, [sp, #40] @ 0x28 +10002168: 930b str r3, [sp, #44] @ 0x2c +1000216a: e627 b.n 10001dbc <_etoa+0x6c> +1000216c: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002170: f446 6680 orr.w r6, r6, #1024 @ 0x400 +10002174: 4638 mov r0, r7 +10002176: 962c str r6, [sp, #176] @ 0xb0 +10002178: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +1000217c: 4634 mov r4, r6 +1000217e: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +10002182: 465a mov r2, fp +10002184: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002188: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +1000218c: 9b09 ldr r3, [sp, #36] @ 0x24 +1000218e: 9908 ldr r1, [sp, #32] +10002190: e6bc b.n 10001f0c <_etoa+0x1bc> +10002192: 2205 movs r2, #5 +10002194: 9212 str r2, [sp, #72] @ 0x48 +10002196: e7ad b.n 100020f4 <_etoa+0x3a4> +10002198: 2300 movs r3, #0 +1000219a: 2202 movs r2, #2 +1000219c: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +100021a0: 2204 movs r2, #4 +100021a2: 930c str r3, [sp, #48] @ 0x30 +100021a4: 9212 str r2, [sp, #72] @ 0x48 +100021a6: e62c b.n 10001e02 <_etoa+0xb2> +100021a8: f04f 0805 mov.w r8, #5 +100021ac: e6c2 b.n 10001f34 <_etoa+0x1e4> +100021ae: f1ba 0f04 cmp.w sl, #4 +100021b2: d91f bls.n 100021f4 <_etoa+0x4a4> +100021b4: 9b10 ldr r3, [sp, #64] @ 0x40 +100021b6: 2b00 cmp r3, #0 +100021b8: d178 bne.n 100022ac <_etoa+0x55c> +100021ba: 2304 movs r3, #4 +100021bc: 9312 str r3, [sp, #72] @ 0x48 +100021be: f1aa 0304 sub.w r3, sl, #4 +100021c2: 930f str r3, [sp, #60] @ 0x3c +100021c4: e004 b.n 100021d0 <_etoa+0x480> +100021c6: 9b12 ldr r3, [sp, #72] @ 0x48 +100021c8: 459a cmp sl, r3 +100021ca: d831 bhi.n 10002230 <_etoa+0x4e0> +100021cc: 9b0e ldr r3, [sp, #56] @ 0x38 +100021ce: 930f str r3, [sp, #60] @ 0x3c +100021d0: 9b0c ldr r3, [sp, #48] @ 0x30 +100021d2: 2b00 cmp r3, #0 +100021d4: f43f ae15 beq.w 10001e02 <_etoa+0xb2> +100021d8: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100021dc: 4642 mov r2, r8 +100021de: 464b mov r3, r9 +100021e0: f7ff f91e bl 10001420 <__wrap___aeabi_ddiv> +100021e4: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100021e8: e60b b.n 10001e02 <_etoa+0xb2> +100021ea: 2302 movs r3, #2 +100021ec: 9310 str r3, [sp, #64] @ 0x40 +100021ee: 2305 movs r3, #5 +100021f0: 9312 str r3, [sp, #72] @ 0x48 +100021f2: e7f1 b.n 100021d8 <_etoa+0x488> +100021f4: 2304 movs r3, #4 +100021f6: 9312 str r3, [sp, #72] @ 0x48 +100021f8: e7ea b.n 100021d0 <_etoa+0x480> +100021fa: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100021fe: 46a0 mov r8, r4 +10002200: 9b0f ldr r3, [sp, #60] @ 0x3c +10002202: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +10002206: 9303 str r3, [sp, #12] +10002208: 9b0e ldr r3, [sp, #56] @ 0x38 +1000220a: 465a mov r2, fp +1000220c: 9302 str r3, [sp, #8] +1000220e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002212: 9304 str r3, [sp, #16] +10002214: 4638 mov r0, r7 +10002216: e9cd 8900 strd r8, r9, [sp] +1000221a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000221c: 9908 ldr r1, [sp, #32] +1000221e: f7ff fb37 bl 10001890 <_ftoa> +10002222: 4602 mov r2, r0 +10002224: e608 b.n 10001e38 <_etoa+0xe8> +10002226: 9b12 ldr r3, [sp, #72] @ 0x48 +10002228: 459a cmp sl, r3 +1000222a: d844 bhi.n 100022b6 <_etoa+0x566> +1000222c: 920f str r2, [sp, #60] @ 0x3c +1000222e: e7cf b.n 100021d0 <_etoa+0x480> +10002230: 9b10 ldr r3, [sp, #64] @ 0x40 +10002232: b38b cbz r3, 10002298 <_etoa+0x548> +10002234: 9b0e ldr r3, [sp, #56] @ 0x38 +10002236: 930f str r3, [sp, #60] @ 0x3c +10002238: 2302 movs r3, #2 +1000223a: 9310 str r3, [sp, #64] @ 0x40 +1000223c: e7c8 b.n 100021d0 <_etoa+0x480> +1000223e: bf00 nop +10002240: 636f4361 .word 0x636f4361 +10002244: 3fd287a7 .word 0x3fd287a7 +10002248: 0979a371 .word 0x0979a371 +1000224c: 400a934f .word 0x400a934f +10002250: bbb55516 .word 0xbbb55516 +10002254: 40026bb1 .word 0x40026bb1 +10002258: fefa39ef .word 0xfefa39ef +1000225c: 3fe62e42 .word 0x3fe62e42 +10002260: eb1c432d .word 0xeb1c432d +10002264: 3f1a36e2 .word 0x3f1a36e2 +10002268: 00000000 .word 0x00000000 +1000226c: 412e8480 .word 0x412e8480 +10002270: 3ff80000 .word 0x3ff80000 +10002274: 3fe00000 .word 0x3fe00000 +10002278: 402c0000 .word 0x402c0000 +1000227c: 40240000 .word 0x40240000 +10002280: 40180000 .word 0x40180000 +10002284: 3ff00000 .word 0x3ff00000 +10002288: 509f79fb .word 0x509f79fb +1000228c: 3fd34413 .word 0x3fd34413 +10002290: 8b60c8b3 .word 0x8b60c8b3 +10002294: 3fc68a28 .word 0x3fc68a28 +10002298: 9b12 ldr r3, [sp, #72] @ 0x48 +1000229a: ebaa 0303 sub.w r3, sl, r3 +1000229e: 930f str r3, [sp, #60] @ 0x3c +100022a0: e796 b.n 100021d0 <_etoa+0x480> +100022a2: eba3 0802 sub.w r8, r3, r2 +100022a6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100022aa: e643 b.n 10001f34 <_etoa+0x1e4> +100022ac: 2304 movs r3, #4 +100022ae: 9312 str r3, [sp, #72] @ 0x48 +100022b0: 2302 movs r3, #2 +100022b2: 9310 str r3, [sp, #64] @ 0x40 +100022b4: e78c b.n 100021d0 <_etoa+0x480> +100022b6: 9b10 ldr r3, [sp, #64] @ 0x40 +100022b8: 2b00 cmp r3, #0 +100022ba: d0ed beq.n 10002298 <_etoa+0x548> +100022bc: 2302 movs r3, #2 +100022be: 920f str r2, [sp, #60] @ 0x3c +100022c0: 9310 str r3, [sp, #64] @ 0x40 +100022c2: e785 b.n 100021d0 <_etoa+0x480> + +100022c4 <_vsnprintf>: +100022c4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100022c8: b09b sub sp, #108 @ 0x6c +100022ca: 9c24 ldr r4, [sp, #144] @ 0x90 +100022cc: 4d95 ldr r5, [pc, #596] @ (10002524 <_vsnprintf+0x260>) +100022ce: 940a str r4, [sp, #40] @ 0x28 +100022d0: 4c95 ldr r4, [pc, #596] @ (10002528 <_vsnprintf+0x264>) +100022d2: f1b1 0a00 subs.w sl, r1, #0 +100022d6: bf18 it ne +100022d8: 4683 movne fp, r0 +100022da: 6025 str r5, [r4, #0] +100022dc: 7818 ldrb r0, [r3, #0] +100022de: 4c93 ldr r4, [pc, #588] @ (1000252c <_vsnprintf+0x268>) +100022e0: 4691 mov r9, r2 +100022e2: bf08 it eq +100022e4: 46a3 moveq fp, r4 +100022e6: 9309 str r3, [sp, #36] @ 0x24 +100022e8: 2800 cmp r0, #0 +100022ea: f000 8293 beq.w 10002814 <_vsnprintf+0x550> +100022ee: f04f 0800 mov.w r8, #0 +100022f2: e00a b.n 1000230a <_vsnprintf+0x46> +100022f4: 4642 mov r2, r8 +100022f6: 464b mov r3, r9 +100022f8: 4651 mov r1, sl +100022fa: f108 0801 add.w r8, r8, #1 +100022fe: 47d8 blx fp +10002300: 9b09 ldr r3, [sp, #36] @ 0x24 +10002302: 7818 ldrb r0, [r3, #0] +10002304: 2800 cmp r0, #0 +10002306: f000 80ce beq.w 100024a6 <_vsnprintf+0x1e2> +1000230a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000230c: 2825 cmp r0, #37 @ 0x25 +1000230e: f103 0301 add.w r3, r3, #1 +10002312: 9309 str r3, [sp, #36] @ 0x24 +10002314: d1ee bne.n 100022f4 <_vsnprintf+0x30> +10002316: 461c mov r4, r3 +10002318: 2300 movs r3, #0 +1000231a: 4622 mov r2, r4 +1000231c: f812 0b01 ldrb.w r0, [r2], #1 +10002320: f1a0 0120 sub.w r1, r0, #32 +10002324: 2910 cmp r1, #16 +10002326: d80a bhi.n 1000233e <_vsnprintf+0x7a> +10002328: e8df f001 tbb [pc, r1] +1000232c: 3c090940 .word 0x3c090940 +10002330: 09090909 .word 0x09090909 +10002334: 38090909 .word 0x38090909 +10002338: 09093409 .word 0x09093409 +1000233c: 30 .byte 0x30 +1000233d: 00 .byte 0x00 +1000233e: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +10002342: 2909 cmp r1, #9 +10002344: 9409 str r4, [sp, #36] @ 0x24 +10002346: f240 808a bls.w 1000245e <_vsnprintf+0x19a> +1000234a: 282a cmp r0, #42 @ 0x2a +1000234c: f000 80f0 beq.w 10002530 <_vsnprintf+0x26c> +10002350: 2500 movs r5, #0 +10002352: 282e cmp r0, #46 @ 0x2e +10002354: f000 8096 beq.w 10002484 <_vsnprintf+0x1c0> +10002358: 2600 movs r6, #0 +1000235a: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +1000235e: 2912 cmp r1, #18 +10002360: d82d bhi.n 100023be <_vsnprintf+0xfa> +10002362: e8df f011 tbh [pc, r1, lsl #1] +10002366: 0149 .short 0x0149 +10002368: 0143002c .word 0x0143002c +1000236c: 0138002c .word 0x0138002c +10002370: 002c002c .word 0x002c002c +10002374: 002c002c .word 0x002c002c +10002378: 002c002c .word 0x002c002c +1000237c: 0027002c .word 0x0027002c +10002380: 002c002c .word 0x002c002c +10002384: 002c002c .word 0x002c002c +10002388: 0027002c .word 0x0027002c +1000238c: 4614 mov r4, r2 +1000238e: f043 0301 orr.w r3, r3, #1 +10002392: e7c2 b.n 1000231a <_vsnprintf+0x56> +10002394: 4614 mov r4, r2 +10002396: f043 0302 orr.w r3, r3, #2 +1000239a: e7be b.n 1000231a <_vsnprintf+0x56> +1000239c: 4614 mov r4, r2 +1000239e: f043 0304 orr.w r3, r3, #4 +100023a2: e7ba b.n 1000231a <_vsnprintf+0x56> +100023a4: 4614 mov r4, r2 +100023a6: f043 0310 orr.w r3, r3, #16 +100023aa: e7b6 b.n 1000231a <_vsnprintf+0x56> +100023ac: 4614 mov r4, r2 +100023ae: f043 0308 orr.w r3, r3, #8 +100023b2: e7b2 b.n 1000231a <_vsnprintf+0x56> +100023b4: 9909 ldr r1, [sp, #36] @ 0x24 +100023b6: 7848 ldrb r0, [r1, #1] +100023b8: f443 7380 orr.w r3, r3, #256 @ 0x100 +100023bc: 3201 adds r2, #1 +100023be: 2867 cmp r0, #103 @ 0x67 +100023c0: 9209 str r2, [sp, #36] @ 0x24 +100023c2: d87e bhi.n 100024c2 <_vsnprintf+0x1fe> +100023c4: 2824 cmp r0, #36 @ 0x24 +100023c6: f240 80c1 bls.w 1000254c <_vsnprintf+0x288> +100023ca: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100023ce: 2a42 cmp r2, #66 @ 0x42 +100023d0: f200 80bc bhi.w 1000254c <_vsnprintf+0x288> +100023d4: e8df f012 tbh [pc, r2, lsl #1] +100023d8: 00ba0150 .word 0x00ba0150 +100023dc: 00ba00ba .word 0x00ba00ba +100023e0: 00ba00ba .word 0x00ba00ba +100023e4: 00ba00ba .word 0x00ba00ba +100023e8: 00ba00ba .word 0x00ba00ba +100023ec: 00ba00ba .word 0x00ba00ba +100023f0: 00ba00ba .word 0x00ba00ba +100023f4: 00ba00ba .word 0x00ba00ba +100023f8: 00ba00ba .word 0x00ba00ba +100023fc: 00ba00ba .word 0x00ba00ba +10002400: 00ba00ba .word 0x00ba00ba +10002404: 00ba00ba .word 0x00ba00ba +10002408: 00ba00ba .word 0x00ba00ba +1000240c: 00ba00ba .word 0x00ba00ba +10002410: 00ba00ba .word 0x00ba00ba +10002414: 00ba00ba .word 0x00ba00ba +10002418: 01370119 .word 0x01370119 +1000241c: 00ba0119 .word 0x00ba0119 +10002420: 00ba00ba .word 0x00ba00ba +10002424: 00ba00ba .word 0x00ba00ba +10002428: 00ba00ba .word 0x00ba00ba +1000242c: 00ba00ba .word 0x00ba00ba +10002430: 00ba00ba .word 0x00ba00ba +10002434: 00ba00ba .word 0x00ba00ba +10002438: 00ba00ba .word 0x00ba00ba +1000243c: 01bc00ba .word 0x01bc00ba +10002440: 00ba00ba .word 0x00ba00ba +10002444: 00ba00ba .word 0x00ba00ba +10002448: 00ba00ba .word 0x00ba00ba +1000244c: 00ba00ba .word 0x00ba00ba +10002450: 01bc00ba .word 0x01bc00ba +10002454: 01bc0158 .word 0x01bc0158 +10002458: 01370119 .word 0x01370119 +1000245c: 0119 .short 0x0119 +1000245e: 2500 movs r5, #0 +10002460: e000 b.n 10002464 <_vsnprintf+0x1a0> +10002462: 3201 adds r2, #1 +10002464: eb05 0585 add.w r5, r5, r5, lsl #2 +10002468: eb00 0545 add.w r5, r0, r5, lsl #1 +1000246c: 7810 ldrb r0, [r2, #0] +1000246e: 3d30 subs r5, #48 @ 0x30 +10002470: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +10002474: 2909 cmp r1, #9 +10002476: d9f4 bls.n 10002462 <_vsnprintf+0x19e> +10002478: 282e cmp r0, #46 @ 0x2e +1000247a: 9209 str r2, [sp, #36] @ 0x24 +1000247c: f102 0201 add.w r2, r2, #1 +10002480: f47f af6a bne.w 10002358 <_vsnprintf+0x94> +10002484: 9909 ldr r1, [sp, #36] @ 0x24 +10002486: f443 6380 orr.w r3, r3, #1024 @ 0x400 +1000248a: 7848 ldrb r0, [r1, #1] +1000248c: 4611 mov r1, r2 +1000248e: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002492: 2e09 cmp r6, #9 +10002494: f240 8121 bls.w 100026da <_vsnprintf+0x416> +10002498: 282a cmp r0, #42 @ 0x2a +1000249a: f000 812f beq.w 100026fc <_vsnprintf+0x438> +1000249e: 9209 str r2, [sp, #36] @ 0x24 +100024a0: 2600 movs r6, #0 +100024a2: 3201 adds r2, #1 +100024a4: e759 b.n 1000235a <_vsnprintf+0x96> +100024a6: 4644 mov r4, r8 +100024a8: 45c1 cmp r9, r8 +100024aa: d801 bhi.n 100024b0 <_vsnprintf+0x1ec> +100024ac: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100024b0: 464b mov r3, r9 +100024b2: 4642 mov r2, r8 +100024b4: 4651 mov r1, sl +100024b6: 2000 movs r0, #0 +100024b8: 47d8 blx fp +100024ba: 4620 mov r0, r4 +100024bc: b01b add sp, #108 @ 0x6c +100024be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100024c2: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100024c6: b2d2 uxtb r2, r2 +100024c8: 2a0f cmp r2, #15 +100024ca: d83f bhi.n 1000254c <_vsnprintf+0x288> +100024cc: 2101 movs r1, #1 +100024ce: f249 0741 movw r7, #36929 @ 0x9041 +100024d2: 4091 lsls r1, r2 +100024d4: 4039 ands r1, r7 +100024d6: f040 80f3 bne.w 100026c0 <_vsnprintf+0x3fc> +100024da: 2a0a cmp r2, #10 +100024dc: d03d beq.n 1000255a <_vsnprintf+0x296> +100024de: 2a07 cmp r2, #7 +100024e0: d134 bne.n 1000254c <_vsnprintf+0x288> +100024e2: 9d0a ldr r5, [sp, #40] @ 0x28 +100024e4: f855 2b04 ldr.w r2, [r5], #4 +100024e8: 2a00 cmp r2, #0 +100024ea: f000 8113 beq.w 10002714 <_vsnprintf+0x450> +100024ee: f043 0021 orr.w r0, r3, #33 @ 0x21 +100024f2: ab12 add r3, sp, #72 @ 0x48 +100024f4: 461f mov r7, r3 +100024f6: 930b str r3, [sp, #44] @ 0x2c +100024f8: e003 b.n 10002502 <_vsnprintf+0x23e> +100024fa: 2920 cmp r1, #32 +100024fc: f000 8114 beq.w 10002728 <_vsnprintf+0x464> +10002500: 461a mov r2, r3 +10002502: f002 040f and.w r4, r2, #15 +10002506: 4623 mov r3, r4 +10002508: 2c09 cmp r4, #9 +1000250a: bf94 ite ls +1000250c: 3330 addls r3, #48 @ 0x30 +1000250e: 3337 addhi r3, #55 @ 0x37 +10002510: 2a0f cmp r2, #15 +10002512: f807 3b01 strb.w r3, [r7], #1 +10002516: f101 0101 add.w r1, r1, #1 +1000251a: ea4f 1312 mov.w r3, r2, lsr #4 +1000251e: d8ec bhi.n 100024fa <_vsnprintf+0x236> +10002520: e102 b.n 10002728 <_vsnprintf+0x464> +10002522: bf00 nop +10002524: 100022c5 .word 0x100022c5 +10002528: 2000080c .word 0x2000080c +1000252c: 10001609 .word 0x10001609 +10002530: 990a ldr r1, [sp, #40] @ 0x28 +10002532: 9809 ldr r0, [sp, #36] @ 0x24 +10002534: f851 5b04 ldr.w r5, [r1], #4 +10002538: 7840 ldrb r0, [r0, #1] +1000253a: 2d00 cmp r5, #0 +1000253c: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002540: bfbc itt lt +10002542: f043 0302 orrlt.w r3, r3, #2 +10002546: 426d neglt r5, r5 +10002548: 3201 adds r2, #1 +1000254a: e702 b.n 10002352 <_vsnprintf+0x8e> +1000254c: 4642 mov r2, r8 +1000254e: 464b mov r3, r9 +10002550: 4651 mov r1, sl +10002552: f108 0801 add.w r8, r8, #1 +10002556: 47d8 blx fp +10002558: e6d2 b.n 10002300 <_vsnprintf+0x3c> +1000255a: 990a ldr r1, [sp, #40] @ 0x28 +1000255c: 2e00 cmp r6, #0 +1000255e: f851 7b04 ldr.w r7, [r1], #4 +10002562: bf18 it ne +10002564: 4632 movne r2, r6 +10002566: 7838 ldrb r0, [r7, #0] +10002568: bf08 it eq +1000256a: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +1000256e: 2800 cmp r0, #0 +10002570: f000 837b beq.w 10002c6a <_vsnprintf+0x9a6> +10002574: 18bc adds r4, r7, r2 +10002576: 46a4 mov ip, r4 +10002578: 463a mov r2, r7 +1000257a: e004 b.n 10002586 <_vsnprintf+0x2c2> +1000257c: f812 4f01 ldrb.w r4, [r2, #1]! +10002580: 2c00 cmp r4, #0 +10002582: f000 813f beq.w 10002804 <_vsnprintf+0x540> +10002586: 4594 cmp ip, r2 +10002588: d1f8 bne.n 1000257c <_vsnprintf+0x2b8> +1000258a: 4664 mov r4, ip +1000258c: 1be4 subs r4, r4, r7 +1000258e: 055a lsls r2, r3, #21 +10002590: f140 8122 bpl.w 100027d8 <_vsnprintf+0x514> +10002594: 42b4 cmp r4, r6 +10002596: bf28 it cs +10002598: 4634 movcs r4, r6 +1000259a: f013 0302 ands.w r3, r3, #2 +1000259e: f000 8288 beq.w 10002ab2 <_vsnprintf+0x7ee> +100025a2: 2302 movs r3, #2 +100025a4: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100025a8: 4642 mov r2, r8 +100025aa: 461d mov r5, r3 +100025ac: 4446 add r6, r8 +100025ae: e008 b.n 100025c2 <_vsnprintf+0x2fe> +100025b0: 464b mov r3, r9 +100025b2: 4651 mov r1, sl +100025b4: 47d8 blx fp +100025b6: f817 0f01 ldrb.w r0, [r7, #1]! +100025ba: f108 0801 add.w r8, r8, #1 +100025be: b110 cbz r0, 100025c6 <_vsnprintf+0x302> +100025c0: 4642 mov r2, r8 +100025c2: 4546 cmp r6, r8 +100025c4: d1f4 bne.n 100025b0 <_vsnprintf+0x2ec> +100025c6: 462b mov r3, r5 +100025c8: 990b ldr r1, [sp, #44] @ 0x2c +100025ca: 9d0a ldr r5, [sp, #40] @ 0x28 +100025cc: 2b00 cmp r3, #0 +100025ce: f040 8141 bne.w 10002854 <_vsnprintf+0x590> +100025d2: 910a str r1, [sp, #40] @ 0x28 +100025d4: e694 b.n 10002300 <_vsnprintf+0x3c> +100025d6: 9909 ldr r1, [sp, #36] @ 0x24 +100025d8: 7848 ldrb r0, [r1, #1] +100025da: 286c cmp r0, #108 @ 0x6c +100025dc: f47f aeec bne.w 100023b8 <_vsnprintf+0xf4> +100025e0: 460a mov r2, r1 +100025e2: 7888 ldrb r0, [r1, #2] +100025e4: f443 7340 orr.w r3, r3, #768 @ 0x300 +100025e8: 3203 adds r2, #3 +100025ea: e6e8 b.n 100023be <_vsnprintf+0xfa> +100025ec: 9909 ldr r1, [sp, #36] @ 0x24 +100025ee: f443 7300 orr.w r3, r3, #512 @ 0x200 +100025f2: 7848 ldrb r0, [r1, #1] +100025f4: 3201 adds r2, #1 +100025f6: e6e2 b.n 100023be <_vsnprintf+0xfa> +100025f8: 9909 ldr r1, [sp, #36] @ 0x24 +100025fa: 7848 ldrb r0, [r1, #1] +100025fc: 2868 cmp r0, #104 @ 0x68 +100025fe: f000 8103 beq.w 10002808 <_vsnprintf+0x544> +10002602: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002606: 3201 adds r2, #1 +10002608: e6d9 b.n 100023be <_vsnprintf+0xfa> +1000260a: 2867 cmp r0, #103 @ 0x67 +1000260c: f000 80d9 beq.w 100027c2 <_vsnprintf+0x4fe> +10002610: 2847 cmp r0, #71 @ 0x47 +10002612: f000 80dc beq.w 100027ce <_vsnprintf+0x50a> +10002616: 2845 cmp r0, #69 @ 0x45 +10002618: f000 80db beq.w 100027d2 <_vsnprintf+0x50e> +1000261c: e9cd 5303 strd r5, r3, [sp, #12] +10002620: 9b0a ldr r3, [sp, #40] @ 0x28 +10002622: 9602 str r6, [sp, #8] +10002624: 3307 adds r3, #7 +10002626: f023 0307 bic.w r3, r3, #7 +1000262a: 461c mov r4, r3 +1000262c: 4642 mov r2, r8 +1000262e: e8f4 6702 ldrd r6, r7, [r4], #8 +10002632: 464b mov r3, r9 +10002634: 4651 mov r1, sl +10002636: 4658 mov r0, fp +10002638: e9cd 6700 strd r6, r7, [sp] +1000263c: 940a str r4, [sp, #40] @ 0x28 +1000263e: f7ff fb87 bl 10001d50 <_etoa> +10002642: 4680 mov r8, r0 +10002644: e65c b.n 10002300 <_vsnprintf+0x3c> +10002646: 2846 cmp r0, #70 @ 0x46 +10002648: bf08 it eq +1000264a: f043 0320 orreq.w r3, r3, #32 +1000264e: e9cd 5303 strd r5, r3, [sp, #12] +10002652: 9b0a ldr r3, [sp, #40] @ 0x28 +10002654: 9602 str r6, [sp, #8] +10002656: 3307 adds r3, #7 +10002658: f023 0307 bic.w r3, r3, #7 +1000265c: 461c mov r4, r3 +1000265e: 4642 mov r2, r8 +10002660: e8f4 6702 ldrd r6, r7, [r4], #8 +10002664: 464b mov r3, r9 +10002666: 4651 mov r1, sl +10002668: 4658 mov r0, fp +1000266a: e9cd 6700 strd r6, r7, [sp] +1000266e: 940a str r4, [sp, #40] @ 0x28 +10002670: f7ff f90e bl 10001890 <_ftoa> +10002674: 4680 mov r8, r0 +10002676: e643 b.n 10002300 <_vsnprintf+0x3c> +10002678: 4642 mov r2, r8 +1000267a: 464b mov r3, r9 +1000267c: 4651 mov r1, sl +1000267e: 2025 movs r0, #37 @ 0x25 +10002680: f108 0801 add.w r8, r8, #1 +10002684: 47d8 blx fp +10002686: e63b b.n 10002300 <_vsnprintf+0x3c> +10002688: 9a0a ldr r2, [sp, #40] @ 0x28 +1000268a: 0799 lsls r1, r3, #30 +1000268c: f102 0404 add.w r4, r2, #4 +10002690: f108 0601 add.w r6, r8, #1 +10002694: f140 80c6 bpl.w 10002824 <_vsnprintf+0x560> +10002698: 7810 ldrb r0, [r2, #0] +1000269a: 464b mov r3, r9 +1000269c: 4642 mov r2, r8 +1000269e: 4651 mov r1, sl +100026a0: 47d8 blx fp +100026a2: 2d01 cmp r5, #1 +100026a4: bf88 it hi +100026a6: 44a8 addhi r8, r5 +100026a8: f240 81bd bls.w 10002a26 <_vsnprintf+0x762> +100026ac: 4632 mov r2, r6 +100026ae: 464b mov r3, r9 +100026b0: 4651 mov r1, sl +100026b2: 2020 movs r0, #32 +100026b4: 3601 adds r6, #1 +100026b6: 47d8 blx fp +100026b8: 4546 cmp r6, r8 +100026ba: d1f7 bne.n 100026ac <_vsnprintf+0x3e8> +100026bc: 940a str r4, [sp, #40] @ 0x28 +100026be: e61f b.n 10002300 <_vsnprintf+0x3c> +100026c0: 286f cmp r0, #111 @ 0x6f +100026c2: f000 8081 beq.w 100027c8 <_vsnprintf+0x504> +100026c6: f240 8248 bls.w 10002b5a <_vsnprintf+0x896> +100026ca: 2878 cmp r0, #120 @ 0x78 +100026cc: f000 8190 beq.w 100029f0 <_vsnprintf+0x72c> +100026d0: 270a movs r7, #10 +100026d2: f023 0310 bic.w r3, r3, #16 +100026d6: 46bc mov ip, r7 +100026d8: e041 b.n 1000275e <_vsnprintf+0x49a> +100026da: 2600 movs r6, #0 +100026dc: eb06 0686 add.w r6, r6, r6, lsl #2 +100026e0: eb00 0046 add.w r0, r0, r6, lsl #1 +100026e4: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100026e8: f811 0f01 ldrb.w r0, [r1, #1]! +100026ec: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100026f0: 2a09 cmp r2, #9 +100026f2: d9f3 bls.n 100026dc <_vsnprintf+0x418> +100026f4: 460a mov r2, r1 +100026f6: 9109 str r1, [sp, #36] @ 0x24 +100026f8: 3201 adds r2, #1 +100026fa: e62e b.n 1000235a <_vsnprintf+0x96> +100026fc: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002700: f851 6b04 ldr.w r6, [r1], #4 +10002704: 7890 ldrb r0, [r2, #2] +10002706: 3202 adds r2, #2 +10002708: 9209 str r2, [sp, #36] @ 0x24 +1000270a: 910a str r1, [sp, #40] @ 0x28 +1000270c: 3201 adds r2, #1 +1000270e: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002712: e622 b.n 1000235a <_vsnprintf+0x96> +10002714: f023 0010 bic.w r0, r3, #16 +10002718: f413 6280 ands.w r2, r3, #1024 @ 0x400 +1000271c: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002720: f43f aee7 beq.w 100024f2 <_vsnprintf+0x22e> +10002724: ab12 add r3, sp, #72 @ 0x48 +10002726: 930b str r3, [sp, #44] @ 0x2c +10002728: 9b0b ldr r3, [sp, #44] @ 0x2c +1000272a: 9006 str r0, [sp, #24] +1000272c: 9300 str r3, [sp, #0] +1000272e: 2308 movs r3, #8 +10002730: 2010 movs r0, #16 +10002732: 9305 str r3, [sp, #20] +10002734: 2300 movs r3, #0 +10002736: 4642 mov r2, r8 +10002738: e9cd 3002 strd r3, r0, [sp, #8] +1000273c: 9101 str r1, [sp, #4] +1000273e: 464b mov r3, r9 +10002740: 4651 mov r1, sl +10002742: 4658 mov r0, fp +10002744: 9604 str r6, [sp, #16] +10002746: f7fe ffaf bl 100016a8 <_ntoa_format> +1000274a: 950a str r5, [sp, #40] @ 0x28 +1000274c: 4680 mov r8, r0 +1000274e: e5d7 b.n 10002300 <_vsnprintf+0x3c> +10002750: 2858 cmp r0, #88 @ 0x58 +10002752: d062 beq.n 1000281a <_vsnprintf+0x556> +10002754: 2862 cmp r0, #98 @ 0x62 +10002756: f040 808f bne.w 10002878 <_vsnprintf+0x5b4> +1000275a: 2702 movs r7, #2 +1000275c: 46bc mov ip, r7 +1000275e: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002762: f000 80dd beq.w 10002920 <_vsnprintf+0x65c> +10002766: f023 030d bic.w r3, r3, #13 +1000276a: f413 7200 ands.w r2, r3, #512 @ 0x200 +1000276e: f040 8181 bne.w 10002a74 <_vsnprintf+0x7b0> +10002772: 990a ldr r1, [sp, #40] @ 0x28 +10002774: 1d0f adds r7, r1, #4 +10002776: f413 7180 ands.w r1, r3, #256 @ 0x100 +1000277a: f040 8237 bne.w 10002bec <_vsnprintf+0x928> +1000277e: 065c lsls r4, r3, #25 +10002780: 9a0a ldr r2, [sp, #40] @ 0x28 +10002782: f140 813b bpl.w 100029fc <_vsnprintf+0x738> +10002786: 7812 ldrb r2, [r2, #0] +10002788: 2a00 cmp r2, #0 +1000278a: f040 814e bne.w 10002a2a <_vsnprintf+0x766> +1000278e: f023 0310 bic.w r3, r3, #16 +10002792: 2800 cmp r0, #0 +10002794: f000 8149 beq.w 10002a2a <_vsnprintf+0x766> +10002798: 4611 mov r1, r2 +1000279a: aa12 add r2, sp, #72 @ 0x48 +1000279c: 920b str r2, [sp, #44] @ 0x2c +1000279e: e9cd 5305 strd r5, r3, [sp, #20] +100027a2: e9cd c603 strd ip, r6, [sp, #12] +100027a6: 9101 str r1, [sp, #4] +100027a8: 9b0b ldr r3, [sp, #44] @ 0x2c +100027aa: 4642 mov r2, r8 +100027ac: 9300 str r3, [sp, #0] +100027ae: 2300 movs r3, #0 +100027b0: 4651 mov r1, sl +100027b2: 9302 str r3, [sp, #8] +100027b4: 4658 mov r0, fp +100027b6: 464b mov r3, r9 +100027b8: f7fe ff76 bl 100016a8 <_ntoa_format> +100027bc: 970a str r7, [sp, #40] @ 0x28 +100027be: 4680 mov r8, r0 +100027c0: e59e b.n 10002300 <_vsnprintf+0x3c> +100027c2: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027c6: e729 b.n 1000261c <_vsnprintf+0x358> +100027c8: 2708 movs r7, #8 +100027ca: 46bc mov ip, r7 +100027cc: e7c7 b.n 1000275e <_vsnprintf+0x49a> +100027ce: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027d2: f043 0320 orr.w r3, r3, #32 +100027d6: e721 b.n 1000261c <_vsnprintf+0x358> +100027d8: f013 0302 ands.w r3, r3, #2 +100027dc: f000 818e beq.w 10002afc <_vsnprintf+0x838> +100027e0: 2302 movs r3, #2 +100027e2: 950a str r5, [sp, #40] @ 0x28 +100027e4: 461e mov r6, r3 +100027e6: 460d mov r5, r1 +100027e8: 4642 mov r2, r8 +100027ea: 464b mov r3, r9 +100027ec: 4651 mov r1, sl +100027ee: 47d8 blx fp +100027f0: f817 0f01 ldrb.w r0, [r7, #1]! +100027f4: f108 0801 add.w r8, r8, #1 +100027f8: 2800 cmp r0, #0 +100027fa: d1f5 bne.n 100027e8 <_vsnprintf+0x524> +100027fc: 4629 mov r1, r5 +100027fe: 4633 mov r3, r6 +10002800: 9d0a ldr r5, [sp, #40] @ 0x28 +10002802: e6e3 b.n 100025cc <_vsnprintf+0x308> +10002804: 1bd4 subs r4, r2, r7 +10002806: e6c2 b.n 1000258e <_vsnprintf+0x2ca> +10002808: 460a mov r2, r1 +1000280a: 7888 ldrb r0, [r1, #2] +1000280c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002810: 3203 adds r2, #3 +10002812: e5d4 b.n 100023be <_vsnprintf+0xfa> +10002814: 4604 mov r4, r0 +10002816: 4680 mov r8, r0 +10002818: e646 b.n 100024a8 <_vsnprintf+0x1e4> +1000281a: 2710 movs r7, #16 +1000281c: f043 0320 orr.w r3, r3, #32 +10002820: 46bc mov ip, r7 +10002822: e79c b.n 1000275e <_vsnprintf+0x49a> +10002824: 2d01 cmp r5, #1 +10002826: f240 80f8 bls.w 10002a1a <_vsnprintf+0x756> +1000282a: 4646 mov r6, r8 +1000282c: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002830: 442f add r7, r5 +10002832: 4632 mov r2, r6 +10002834: 464b mov r3, r9 +10002836: 4651 mov r1, sl +10002838: 2020 movs r0, #32 +1000283a: 3601 adds r6, #1 +1000283c: 47d8 blx fp +1000283e: 42be cmp r6, r7 +10002840: d1f7 bne.n 10002832 <_vsnprintf+0x56e> +10002842: 9b0a ldr r3, [sp, #40] @ 0x28 +10002844: 4632 mov r2, r6 +10002846: 7818 ldrb r0, [r3, #0] +10002848: 4651 mov r1, sl +1000284a: 464b mov r3, r9 +1000284c: 47d8 blx fp +1000284e: 44a8 add r8, r5 +10002850: 940a str r4, [sp, #40] @ 0x28 +10002852: e555 b.n 10002300 <_vsnprintf+0x3c> +10002854: 4646 mov r6, r8 +10002856: 42a5 cmp r5, r4 +10002858: f67f aebb bls.w 100025d2 <_vsnprintf+0x30e> +1000285c: 44a8 add r8, r5 +1000285e: eba8 0804 sub.w r8, r8, r4 +10002862: 460c mov r4, r1 +10002864: 4632 mov r2, r6 +10002866: 464b mov r3, r9 +10002868: 4651 mov r1, sl +1000286a: 2020 movs r0, #32 +1000286c: 3601 adds r6, #1 +1000286e: 47d8 blx fp +10002870: 4546 cmp r6, r8 +10002872: d1f7 bne.n 10002864 <_vsnprintf+0x5a0> +10002874: 4621 mov r1, r4 +10002876: e6ac b.n 100025d2 <_vsnprintf+0x30e> +10002878: f413 6280 ands.w r2, r3, #1024 @ 0x400 +1000287c: f000 80bb beq.w 100029f6 <_vsnprintf+0x732> +10002880: f44f 6280 mov.w r2, #1024 @ 0x400 +10002884: f023 0c11 bic.w ip, r3, #17 +10002888: f41c 7700 ands.w r7, ip, #512 @ 0x200 +1000288c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000288e: d14a bne.n 10002926 <_vsnprintf+0x662> +10002890: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002894: f103 0404 add.w r4, r3, #4 +10002898: f040 8134 bne.w 10002b04 <_vsnprintf+0x840> +1000289c: f01c 0f40 tst.w ip, #64 @ 0x40 +100028a0: f040 80a3 bne.w 100029ea <_vsnprintf+0x726> +100028a4: f01c 0f80 tst.w ip, #128 @ 0x80 +100028a8: f000 81d3 beq.w 10002c52 <_vsnprintf+0x98e> +100028ac: f9b3 1000 ldrsh.w r1, [r3] +100028b0: ea81 77e1 eor.w r7, r1, r1, asr #31 +100028b4: eba7 77e1 sub.w r7, r7, r1, asr #31 +100028b8: b2bf uxth r7, r7 +100028ba: 0fcb lsrs r3, r1, #31 +100028bc: 2900 cmp r1, #0 +100028be: f000 8156 beq.w 10002b6e <_vsnprintf+0x8aa> +100028c2: 463a mov r2, r7 +100028c4: a912 add r1, sp, #72 @ 0x48 +100028c6: 460f mov r7, r1 +100028c8: f8df e3d8 ldr.w lr, [pc, #984] @ 10002ca4 <_vsnprintf+0x9e0> +100028cc: 910b str r1, [sp, #44] @ 0x2c +100028ce: 930a str r3, [sp, #40] @ 0x28 +100028d0: 950c str r5, [sp, #48] @ 0x30 +100028d2: e001 b.n 100028d8 <_vsnprintf+0x614> +100028d4: 2820 cmp r0, #32 +100028d6: d00f beq.n 100028f8 <_vsnprintf+0x634> +100028d8: 4615 mov r5, r2 +100028da: fbae 1302 umull r1, r3, lr, r2 +100028de: 08db lsrs r3, r3, #3 +100028e0: eb03 0183 add.w r1, r3, r3, lsl #2 +100028e4: eba2 0141 sub.w r1, r2, r1, lsl #1 +100028e8: 3130 adds r1, #48 @ 0x30 +100028ea: 2d09 cmp r5, #9 +100028ec: 461a mov r2, r3 +100028ee: f100 0001 add.w r0, r0, #1 +100028f2: f807 1b01 strb.w r1, [r7], #1 +100028f6: d8ed bhi.n 100028d4 <_vsnprintf+0x610> +100028f8: 9b0a ldr r3, [sp, #40] @ 0x28 +100028fa: 9d0c ldr r5, [sp, #48] @ 0x30 +100028fc: e9cd 5c05 strd r5, ip, [sp, #20] +10002900: e9cd 0301 strd r0, r3, [sp, #4] +10002904: 9604 str r6, [sp, #16] +10002906: 9b0b ldr r3, [sp, #44] @ 0x2c +10002908: 4642 mov r2, r8 +1000290a: 9300 str r3, [sp, #0] +1000290c: 230a movs r3, #10 +1000290e: 4651 mov r1, sl +10002910: 9303 str r3, [sp, #12] +10002912: 4658 mov r0, fp +10002914: 464b mov r3, r9 +10002916: f7fe fec7 bl 100016a8 <_ntoa_format> +1000291a: 940a str r4, [sp, #40] @ 0x28 +1000291c: 4680 mov r8, r0 +1000291e: e4ef b.n 10002300 <_vsnprintf+0x3c> +10002920: f023 030c bic.w r3, r3, #12 +10002924: e721 b.n 1000276a <_vsnprintf+0x4a6> +10002926: 3307 adds r3, #7 +10002928: f023 0307 bic.w r3, r3, #7 +1000292c: 4619 mov r1, r3 +1000292e: 4608 mov r0, r1 +10002930: 685b ldr r3, [r3, #4] +10002932: f850 1b08 ldr.w r1, [r0], #8 +10002936: 0fdf lsrs r7, r3, #31 +10002938: 900a str r0, [sp, #40] @ 0x28 +1000293a: ea51 0003 orrs.w r0, r1, r3 +1000293e: d162 bne.n 10002a06 <_vsnprintf+0x742> +10002940: 2a00 cmp r2, #0 +10002942: f040 819f bne.w 10002c84 <_vsnprintf+0x9c0> +10002946: 4613 mov r3, r2 +10002948: 4611 mov r1, r2 +1000294a: aa12 add r2, sp, #72 @ 0x48 +1000294c: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002950: 2000 movs r0, #0 +10002952: 4615 mov r5, r2 +10002954: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002958: f8df e348 ldr.w lr, [pc, #840] @ 10002ca4 <_vsnprintf+0x9e0> +1000295c: 920b str r2, [sp, #44] @ 0x2c +1000295e: e001 b.n 10002964 <_vsnprintf+0x6a0> +10002960: 2820 cmp r0, #32 +10002962: d02d beq.n 100029c0 <_vsnprintf+0x6fc> +10002964: 185a adds r2, r3, r1 +10002966: f142 0200 adc.w r2, r2, #0 +1000296a: fbae 7802 umull r7, r8, lr, r2 +1000296e: f028 0703 bic.w r7, r8, #3 +10002972: eb07 0798 add.w r7, r7, r8, lsr #2 +10002976: 1bd2 subs r2, r2, r7 +10002978: 461e mov r6, r3 +1000297a: 1a9b subs r3, r3, r2 +1000297c: f161 0700 sbc.w r7, r1, #0 +10002980: 460c mov r4, r1 +10002982: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002986: fb01 f103 mul.w r1, r1, r3 +1000298a: fb0e 1107 mla r1, lr, r7, r1 +1000298e: fba3 730e umull r7, r3, r3, lr +10002992: 4419 add r1, r3 +10002994: 2305 movs r3, #5 +10002996: f007 0801 and.w r8, r7, #1 +1000299a: fba8 3803 umull r3, r8, r8, r3 +1000299e: 189b adds r3, r3, r2 +100029a0: 2e0a cmp r6, #10 +100029a2: f103 0330 add.w r3, r3, #48 @ 0x30 +100029a6: ea4f 0757 mov.w r7, r7, lsr #1 +100029aa: f174 0400 sbcs.w r4, r4, #0 +100029ae: f805 3b01 strb.w r3, [r5], #1 +100029b2: f100 0001 add.w r0, r0, #1 +100029b6: ea47 73c1 orr.w r3, r7, r1, lsl #31 +100029ba: ea4f 0151 mov.w r1, r1, lsr #1 +100029be: d2cf bcs.n 10002960 <_vsnprintf+0x69c> +100029c0: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +100029c4: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +100029c8: 9b0b ldr r3, [sp, #44] @ 0x2c +100029ca: 4642 mov r2, r8 +100029cc: 9300 str r3, [sp, #0] +100029ce: 230a movs r3, #10 +100029d0: e9cd 5c05 strd r5, ip, [sp, #20] +100029d4: e9cd 0701 strd r0, r7, [sp, #4] +100029d8: 9604 str r6, [sp, #16] +100029da: 9303 str r3, [sp, #12] +100029dc: 464b mov r3, r9 +100029de: 4651 mov r1, sl +100029e0: 4658 mov r0, fp +100029e2: f7fe fe61 bl 100016a8 <_ntoa_format> +100029e6: 4680 mov r8, r0 +100029e8: e48a b.n 10002300 <_vsnprintf+0x3c> +100029ea: 7819 ldrb r1, [r3, #0] +100029ec: 460f mov r7, r1 +100029ee: e764 b.n 100028ba <_vsnprintf+0x5f6> +100029f0: 2710 movs r7, #16 +100029f2: 46bc mov ip, r7 +100029f4: e6b3 b.n 1000275e <_vsnprintf+0x49a> +100029f6: f023 0c10 bic.w ip, r3, #16 +100029fa: e745 b.n 10002888 <_vsnprintf+0x5c4> +100029fc: 061c lsls r4, r3, #24 +100029fe: bf4c ite mi +10002a00: 8812 ldrhmi r2, [r2, #0] +10002a02: 6812 ldrpl r2, [r2, #0] +10002a04: e6c0 b.n 10002788 <_vsnprintf+0x4c4> +10002a06: 460a mov r2, r1 +10002a08: 1e19 subs r1, r3, #0 +10002a0a: db01 blt.n 10002a10 <_vsnprintf+0x74c> +10002a0c: 4613 mov r3, r2 +10002a0e: e79c b.n 1000294a <_vsnprintf+0x686> +10002a10: 4252 negs r2, r2 +10002a12: 4613 mov r3, r2 +10002a14: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002a18: e797 b.n 1000294a <_vsnprintf+0x686> +10002a1a: 4613 mov r3, r2 +10002a1c: 4651 mov r1, sl +10002a1e: 7818 ldrb r0, [r3, #0] +10002a20: 4642 mov r2, r8 +10002a22: 464b mov r3, r9 +10002a24: 47d8 blx fp +10002a26: 46b0 mov r8, r6 +10002a28: e648 b.n 100026bc <_vsnprintf+0x3f8> +10002a2a: f013 0f20 tst.w r3, #32 +10002a2e: bf14 ite ne +10002a30: 2041 movne r0, #65 @ 0x41 +10002a32: 2061 moveq r0, #97 @ 0x61 +10002a34: ac12 add r4, sp, #72 @ 0x48 +10002a36: 46a6 mov lr, r4 +10002a38: 940b str r4, [sp, #44] @ 0x2c +10002a3a: 930a str r3, [sp, #40] @ 0x28 +10002a3c: f1a0 040a sub.w r4, r0, #10 +10002a40: 950c str r5, [sp, #48] @ 0x30 +10002a42: e002 b.n 10002a4a <_vsnprintf+0x786> +10002a44: 2920 cmp r1, #32 +10002a46: d012 beq.n 10002a6e <_vsnprintf+0x7aa> +10002a48: 462a mov r2, r5 +10002a4a: fbb2 f5fc udiv r5, r2, ip +10002a4e: fb0c 2015 mls r0, ip, r5, r2 +10002a52: b2c3 uxtb r3, r0 +10002a54: 2809 cmp r0, #9 +10002a56: f103 0030 add.w r0, r3, #48 @ 0x30 +10002a5a: bf8a itet hi +10002a5c: 191b addhi r3, r3, r4 +10002a5e: b2c3 uxtbls r3, r0 +10002a60: b2db uxtbhi r3, r3 +10002a62: 4562 cmp r2, ip +10002a64: f80e 3b01 strb.w r3, [lr], #1 +10002a68: f101 0101 add.w r1, r1, #1 +10002a6c: d2ea bcs.n 10002a44 <_vsnprintf+0x780> +10002a6e: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a70: 9d0c ldr r5, [sp, #48] @ 0x30 +10002a72: e694 b.n 1000279e <_vsnprintf+0x4da> +10002a74: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a76: 3207 adds r2, #7 +10002a78: f022 0207 bic.w r2, r2, #7 +10002a7c: 6851 ldr r1, [r2, #4] +10002a7e: f852 4b08 ldr.w r4, [r2], #8 +10002a82: 468e mov lr, r1 +10002a84: 920a str r2, [sp, #40] @ 0x28 +10002a86: ea54 0201 orrs.w r2, r4, r1 +10002a8a: d176 bne.n 10002b7a <_vsnprintf+0x8b6> +10002a8c: f023 0310 bic.w r3, r3, #16 +10002a90: 2800 cmp r0, #0 +10002a92: d072 beq.n 10002b7a <_vsnprintf+0x8b6> +10002a94: 2200 movs r2, #0 +10002a96: 4611 mov r1, r2 +10002a98: aa12 add r2, sp, #72 @ 0x48 +10002a9a: 920b str r2, [sp, #44] @ 0x2c +10002a9c: e9cd 5305 strd r5, r3, [sp, #20] +10002aa0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002aa2: 4642 mov r2, r8 +10002aa4: 9300 str r3, [sp, #0] +10002aa6: 2300 movs r3, #0 +10002aa8: e9cd c603 strd ip, r6, [sp, #12] +10002aac: 9101 str r1, [sp, #4] +10002aae: 9302 str r3, [sp, #8] +10002ab0: e794 b.n 100029dc <_vsnprintf+0x718> +10002ab2: 42a5 cmp r5, r4 +10002ab4: bf98 it ls +10002ab6: 3401 addls r4, #1 +10002ab8: f67f ad74 bls.w 100025a4 <_vsnprintf+0x2e0> +10002abc: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ac0: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002ac4: eb05 0208 add.w r2, r5, r8 +10002ac8: 461f mov r7, r3 +10002aca: 460d mov r5, r1 +10002acc: 1b14 subs r4, r2, r4 +10002ace: 4642 mov r2, r8 +10002ad0: 464b mov r3, r9 +10002ad2: 4651 mov r1, sl +10002ad4: 2020 movs r0, #32 +10002ad6: f108 0801 add.w r8, r8, #1 +10002ada: 47d8 blx fp +10002adc: 45a0 cmp r8, r4 +10002ade: d1f6 bne.n 10002ace <_vsnprintf+0x80a> +10002ae0: 463b mov r3, r7 +10002ae2: 9f0a ldr r7, [sp, #40] @ 0x28 +10002ae4: 4629 mov r1, r5 +10002ae6: 7838 ldrb r0, [r7, #0] +10002ae8: 9d0b ldr r5, [sp, #44] @ 0x2c +10002aea: 1c6c adds r4, r5, #1 +10002aec: 2800 cmp r0, #0 +10002aee: f43f ad70 beq.w 100025d2 <_vsnprintf+0x30e> +10002af2: 2b00 cmp r3, #0 +10002af4: f43f ae75 beq.w 100027e2 <_vsnprintf+0x51e> +10002af8: 2300 movs r3, #0 +10002afa: e553 b.n 100025a4 <_vsnprintf+0x2e0> +10002afc: 42a5 cmp r5, r4 +10002afe: d8df bhi.n 10002ac0 <_vsnprintf+0x7fc> +10002b00: 3401 adds r4, #1 +10002b02: e66e b.n 100027e2 <_vsnprintf+0x51e> +10002b04: 6819 ldr r1, [r3, #0] +10002b06: 0fcb lsrs r3, r1, #31 +10002b08: 2900 cmp r1, #0 +10002b0a: f000 80a8 beq.w 10002c5e <_vsnprintf+0x99a> +10002b0e: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002b12: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002b16: a912 add r1, sp, #72 @ 0x48 +10002b18: 4608 mov r0, r1 +10002b1a: f8df e188 ldr.w lr, [pc, #392] @ 10002ca4 <_vsnprintf+0x9e0> +10002b1e: 910b str r1, [sp, #44] @ 0x2c +10002b20: 930a str r3, [sp, #40] @ 0x28 +10002b22: 950c str r5, [sp, #48] @ 0x30 +10002b24: e001 b.n 10002b2a <_vsnprintf+0x866> +10002b26: 2f20 cmp r7, #32 +10002b28: d00f beq.n 10002b4a <_vsnprintf+0x886> +10002b2a: 4615 mov r5, r2 +10002b2c: fbae 1302 umull r1, r3, lr, r2 +10002b30: 08db lsrs r3, r3, #3 +10002b32: eb03 0183 add.w r1, r3, r3, lsl #2 +10002b36: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002b3a: 3130 adds r1, #48 @ 0x30 +10002b3c: 2d09 cmp r5, #9 +10002b3e: 461a mov r2, r3 +10002b40: f107 0701 add.w r7, r7, #1 +10002b44: f800 1b01 strb.w r1, [r0], #1 +10002b48: d8ed bhi.n 10002b26 <_vsnprintf+0x862> +10002b4a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b4c: 9d0c ldr r5, [sp, #48] @ 0x30 +10002b4e: e9cd 5c05 strd r5, ip, [sp, #20] +10002b52: e9cd 7301 strd r7, r3, [sp, #4] +10002b56: 9604 str r6, [sp, #16] +10002b58: e6d5 b.n 10002906 <_vsnprintf+0x642> +10002b5a: 2869 cmp r0, #105 @ 0x69 +10002b5c: f023 0c10 bic.w ip, r3, #16 +10002b60: f040 808c bne.w 10002c7c <_vsnprintf+0x9b8> +10002b64: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b68: f43f ae8e beq.w 10002888 <_vsnprintf+0x5c4> +10002b6c: e688 b.n 10002880 <_vsnprintf+0x5bc> +10002b6e: 2a00 cmp r2, #0 +10002b70: f43f aea8 beq.w 100028c4 <_vsnprintf+0x600> +10002b74: aa12 add r2, sp, #72 @ 0x48 +10002b76: 920b str r2, [sp, #44] @ 0x2c +10002b78: e6c0 b.n 100028fc <_vsnprintf+0x638> +10002b7a: f013 0f20 tst.w r3, #32 +10002b7e: bf14 ite ne +10002b80: 2241 movne r2, #65 @ 0x41 +10002b82: 2261 moveq r2, #97 @ 0x61 +10002b84: 2000 movs r0, #0 +10002b86: a912 add r1, sp, #72 @ 0x48 +10002b88: 3a0a subs r2, #10 +10002b8a: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002b8e: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002b92: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002b96: 4606 mov r6, r0 +10002b98: 4688 mov r8, r1 +10002b9a: 4675 mov r5, lr +10002b9c: 4693 mov fp, r2 +10002b9e: 910b str r1, [sp, #44] @ 0x2c +10002ba0: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002ba4: e003 b.n 10002bae <_vsnprintf+0x8ea> +10002ba6: 2e20 cmp r6, #32 +10002ba8: d017 beq.n 10002bda <_vsnprintf+0x916> +10002baa: 4604 mov r4, r0 +10002bac: 460d mov r5, r1 +10002bae: 4629 mov r1, r5 +10002bb0: 463a mov r2, r7 +10002bb2: 2300 movs r3, #0 +10002bb4: 4620 mov r0, r4 +10002bb6: f000 fc47 bl 10003448 <____aeabi_uldivmod_veneer> +10002bba: b2d2 uxtb r2, r2 +10002bbc: 2a09 cmp r2, #9 +10002bbe: f102 0330 add.w r3, r2, #48 @ 0x30 +10002bc2: bf88 it hi +10002bc4: eb02 030b addhi.w r3, r2, fp +10002bc8: 42bc cmp r4, r7 +10002bca: b2db uxtb r3, r3 +10002bcc: f175 0500 sbcs.w r5, r5, #0 +10002bd0: f808 3b01 strb.w r3, [r8], #1 +10002bd4: f106 0601 add.w r6, r6, #1 +10002bd8: d2e5 bcs.n 10002ba6 <_vsnprintf+0x8e2> +10002bda: 4631 mov r1, r6 +10002bdc: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002be0: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002be4: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002be8: 9e0e ldr r6, [sp, #56] @ 0x38 +10002bea: e757 b.n 10002a9c <_vsnprintf+0x7d8> +10002bec: 990a ldr r1, [sp, #40] @ 0x28 +10002bee: 6809 ldr r1, [r1, #0] +10002bf0: b951 cbnz r1, 10002c08 <_vsnprintf+0x944> +10002bf2: f023 0310 bic.w r3, r3, #16 +10002bf6: b138 cbz r0, 10002c08 <_vsnprintf+0x944> +10002bf8: a912 add r1, sp, #72 @ 0x48 +10002bfa: 910b str r1, [sp, #44] @ 0x2c +10002bfc: e9cd 5305 strd r5, r3, [sp, #20] +10002c00: e9cd c603 strd ip, r6, [sp, #12] +10002c04: 9201 str r2, [sp, #4] +10002c06: e5cf b.n 100027a8 <_vsnprintf+0x4e4> +10002c08: f013 0f20 tst.w r3, #32 +10002c0c: bf14 ite ne +10002c0e: 2041 movne r0, #65 @ 0x41 +10002c10: 2061 moveq r0, #97 @ 0x61 +10002c12: ac12 add r4, sp, #72 @ 0x48 +10002c14: 46a6 mov lr, r4 +10002c16: 940b str r4, [sp, #44] @ 0x2c +10002c18: 930a str r3, [sp, #40] @ 0x28 +10002c1a: f1a0 040a sub.w r4, r0, #10 +10002c1e: 950c str r5, [sp, #48] @ 0x30 +10002c20: e002 b.n 10002c28 <_vsnprintf+0x964> +10002c22: 2a20 cmp r2, #32 +10002c24: d012 beq.n 10002c4c <_vsnprintf+0x988> +10002c26: 4629 mov r1, r5 +10002c28: fbb1 f5fc udiv r5, r1, ip +10002c2c: fb0c 1015 mls r0, ip, r5, r1 +10002c30: b2c3 uxtb r3, r0 +10002c32: 2809 cmp r0, #9 +10002c34: f103 0030 add.w r0, r3, #48 @ 0x30 +10002c38: bf8a itet hi +10002c3a: 191b addhi r3, r3, r4 +10002c3c: b2c3 uxtbls r3, r0 +10002c3e: b2db uxtbhi r3, r3 +10002c40: 4561 cmp r1, ip +10002c42: f80e 3b01 strb.w r3, [lr], #1 +10002c46: f102 0201 add.w r2, r2, #1 +10002c4a: d2ea bcs.n 10002c22 <_vsnprintf+0x95e> +10002c4c: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c4e: 9d0c ldr r5, [sp, #48] @ 0x30 +10002c50: e7d4 b.n 10002bfc <_vsnprintf+0x938> +10002c52: 6819 ldr r1, [r3, #0] +10002c54: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002c58: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002c5c: e62d b.n 100028ba <_vsnprintf+0x5f6> +10002c5e: 2a00 cmp r2, #0 +10002c60: f43f af59 beq.w 10002b16 <_vsnprintf+0x852> +10002c64: aa12 add r2, sp, #72 @ 0x48 +10002c66: 920b str r2, [sp, #44] @ 0x2c +10002c68: e771 b.n 10002b4e <_vsnprintf+0x88a> +10002c6a: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002c6e: d00d beq.n 10002c8c <_vsnprintf+0x9c8> +10002c70: f013 0402 ands.w r4, r3, #2 +10002c74: d012 beq.n 10002c9c <_vsnprintf+0x9d8> +10002c76: 4604 mov r4, r0 +10002c78: 4646 mov r6, r8 +10002c7a: e5ec b.n 10002856 <_vsnprintf+0x592> +10002c7c: 270a movs r7, #10 +10002c7e: 4663 mov r3, ip +10002c80: 46bc mov ip, r7 +10002c82: e56c b.n 1000275e <_vsnprintf+0x49a> +10002c84: ab12 add r3, sp, #72 @ 0x48 +10002c86: 2000 movs r0, #0 +10002c88: 930b str r3, [sp, #44] @ 0x2c +10002c8a: e69d b.n 100029c8 <_vsnprintf+0x704> +10002c8c: f013 0302 ands.w r3, r3, #2 +10002c90: f47f ade0 bne.w 10002854 <_vsnprintf+0x590> +10002c94: 2d00 cmp r5, #0 +10002c96: f47f af13 bne.w 10002ac0 <_vsnprintf+0x7fc> +10002c9a: e49a b.n 100025d2 <_vsnprintf+0x30e> +10002c9c: 2d00 cmp r5, #0 +10002c9e: f47f af0d bne.w 10002abc <_vsnprintf+0x7f8> +10002ca2: e496 b.n 100025d2 <_vsnprintf+0x30e> +10002ca4: cccccccd .word 0xcccccccd + +10002ca8 : +10002ca8: b570 push {r4, r5, r6, lr} +10002caa: 4694 mov ip, r2 +10002cac: 461e mov r6, r3 +10002cae: 4605 mov r5, r0 +10002cb0: 460c mov r4, r1 +10002cb2: b084 sub sp, #16 +10002cb4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002cb8: 4663 mov r3, ip +10002cba: a902 add r1, sp, #8 +10002cbc: 9600 str r6, [sp, #0] +10002cbe: 4803 ldr r0, [pc, #12] @ (10002ccc ) +10002cc0: e9cd 5402 strd r5, r4, [sp, #8] +10002cc4: f7ff fafe bl 100022c4 <_vsnprintf> +10002cc8: b004 add sp, #16 +10002cca: bd70 pop {r4, r5, r6, pc} +10002ccc: 10001885 .word 0x10001885 + +10002cd0 : +10002cd0: b510 push {r4, lr} +10002cd2: 4b09 ldr r3, [pc, #36] @ (10002cf8 ) +10002cd4: b084 sub sp, #16 +10002cd6: 681c ldr r4, [r3, #0] +10002cd8: b14c cbz r4, 10002cee +10002cda: 4603 mov r3, r0 +10002cdc: 9100 str r1, [sp, #0] +10002cde: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002ce2: a903 add r1, sp, #12 +10002ce4: 4805 ldr r0, [pc, #20] @ (10002cfc ) +10002ce6: 47a0 blx r4 +10002ce8: 2001 movs r0, #1 +10002cea: b004 add sp, #16 +10002cec: bd10 pop {r4, pc} +10002cee: f000 f97d bl 10002fec <__wrap_puts> +10002cf2: 4620 mov r0, r4 +10002cf4: b004 add sp, #16 +10002cf6: bd10 pop {r4, pc} +10002cf8: 2000080c .word 0x2000080c +10002cfc: 1000187d .word 0x1000187d + +10002d00 <_exit>: +10002d00: be00 bkpt 0x0000 +10002d02: e7fd b.n 10002d00 <_exit> + +10002d04 : +10002d04: b508 push {r3, lr} +10002d06: f7ff fffb bl 10002d00 <_exit> +10002d0a: bf00 nop + +10002d0c : +10002d0c: b538 push {r3, r4, r5, lr} +10002d0e: 4c06 ldr r4, [pc, #24] @ (10002d28 ) +10002d10: 4d06 ldr r5, [pc, #24] @ (10002d2c ) +10002d12: f7fe fa07 bl 10001124 +10002d16: 42ac cmp r4, r5 +10002d18: d204 bcs.n 10002d24 +10002d1a: f854 3b04 ldr.w r3, [r4], #4 +10002d1e: 4798 blx r3 +10002d20: 42ac cmp r4, r5 +10002d22: d3fa bcc.n 10002d1a +10002d24: bd38 pop {r3, r4, r5, pc} +10002d26: bf00 nop +10002d28: 100034a0 .word 0x100034a0 +10002d2c: 100034a4 .word 0x100034a4 + +10002d30 : +10002d30: 6803 ldr r3, [r0, #0] +10002d32: 4608 mov r0, r1 +10002d34: 4611 mov r1, r2 +10002d36: 4718 bx r3 + +10002d38 : +10002d38: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002d3c: 4615 mov r5, r2 +10002d3e: 7d42 ldrb r2, [r0, #21] +10002d40: 4607 mov r7, r0 +10002d42: 4688 mov r8, r1 +10002d44: 2a00 cmp r2, #0 +10002d46: d046 beq.n 10002dd6 +10002d48: 2d00 cmp r5, #0 +10002d4a: dd1d ble.n 10002d88 +10002d4c: 780b ldrb r3, [r1, #0] +10002d4e: 2b0a cmp r3, #10 +10002d50: d023 beq.n 10002d9a +10002d52: 2d01 cmp r5, #1 +10002d54: f04f 0c00 mov.w ip, #0 +10002d58: d018 beq.n 10002d8c +10002d5a: 4646 mov r6, r8 +10002d5c: 2401 movs r4, #1 +10002d5e: f816 2f01 ldrb.w r2, [r6, #1]! +10002d62: 4621 mov r1, r4 +10002d64: 2a0a cmp r2, #10 +10002d66: f104 0401 add.w r4, r4, #1 +10002d6a: d022 beq.n 10002db2 +10002d6c: 42a5 cmp r5, r4 +10002d6e: d1f6 bne.n 10002d5e +10002d70: 4565 cmp r5, ip +10002d72: dc0b bgt.n 10002d8c +10002d74: eb08 0305 add.w r3, r8, r5 +10002d78: f813 3c01 ldrb.w r3, [r3, #-1] +10002d7c: f1a3 030d sub.w r3, r3, #13 +10002d80: fab3 f383 clz r3, r3 +10002d84: 095b lsrs r3, r3, #5 +10002d86: 753b strb r3, [r7, #20] +10002d88: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002d8c: 683b ldr r3, [r7, #0] +10002d8e: eba5 010c sub.w r1, r5, ip +10002d92: eb08 000c add.w r0, r8, ip +10002d96: 4798 blx r3 +10002d98: e7ec b.n 10002d74 +10002d9a: 7d03 ldrb r3, [r0, #20] +10002d9c: 2b00 cmp r3, #0 +10002d9e: d1d8 bne.n 10002d52 +10002da0: 6803 ldr r3, [r0, #0] +10002da2: 2102 movs r1, #2 +10002da4: 480f ldr r0, [pc, #60] @ (10002de4 ) +10002da6: 4798 blx r3 +10002da8: 2d01 cmp r5, #1 +10002daa: d0e3 beq.n 10002d74 +10002dac: f04f 0c01 mov.w ip, #1 +10002db0: e7d3 b.n 10002d5a +10002db2: f816 3c01 ldrb.w r3, [r6, #-1] +10002db6: 2b0d cmp r3, #13 +10002db8: d0d8 beq.n 10002d6c +10002dba: 458c cmp ip, r1 +10002dbc: eb08 000c add.w r0, r8, ip +10002dc0: eba1 010c sub.w r1, r1, ip +10002dc4: da01 bge.n 10002dca +10002dc6: 683b ldr r3, [r7, #0] +10002dc8: 4798 blx r3 +10002dca: 2102 movs r1, #2 +10002dcc: 4805 ldr r0, [pc, #20] @ (10002de4 ) +10002dce: 683b ldr r3, [r7, #0] +10002dd0: 4798 blx r3 +10002dd2: 46a4 mov ip, r4 +10002dd4: e7ca b.n 10002d6c +10002dd6: 4629 mov r1, r5 +10002dd8: 4640 mov r0, r8 +10002dda: 683b ldr r3, [r7, #0] +10002ddc: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002de0: 4718 bx r3 +10002de2: bf00 nop +10002de4: 10003648 .word 0x10003648 + +10002de8 : +10002de8: 680b ldr r3, [r1, #0] +10002dea: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002dee: 2b80 cmp r3, #128 @ 0x80 +10002df0: 460d mov r5, r1 +10002df2: 4606 mov r6, r0 +10002df4: d005 beq.n 10002e02 +10002df6: 1c5a adds r2, r3, #1 +10002df8: 442b add r3, r5 +10002dfa: 602a str r2, [r5, #0] +10002dfc: 711e strb r6, [r3, #4] +10002dfe: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e02: 4b0f ldr r3, [pc, #60] @ (10002e40 ) +10002e04: 681c ldr r4, [r3, #0] +10002e06: b1a4 cbz r4, 10002e32 +10002e08: 4f0e ldr r7, [pc, #56] @ (10002e44 ) +10002e0a: f101 0804 add.w r8, r1, #4 +10002e0e: e001 b.n 10002e14 +10002e10: 6924 ldr r4, [r4, #16] +10002e12: b174 cbz r4, 10002e32 +10002e14: 6823 ldr r3, [r4, #0] +10002e16: 2b00 cmp r3, #0 +10002e18: d0fa beq.n 10002e10 +10002e1a: 683b ldr r3, [r7, #0] +10002e1c: b10b cbz r3, 10002e22 +10002e1e: 42a3 cmp r3, r4 +10002e20: d1f6 bne.n 10002e10 +10002e22: 4620 mov r0, r4 +10002e24: 4641 mov r1, r8 +10002e26: 682a ldr r2, [r5, #0] +10002e28: f7ff ff86 bl 10002d38 +10002e2c: 6924 ldr r4, [r4, #16] +10002e2e: 2c00 cmp r4, #0 +10002e30: d1f0 bne.n 10002e14 +10002e32: 2300 movs r3, #0 +10002e34: 2201 movs r2, #1 +10002e36: 442b add r3, r5 +10002e38: 602a str r2, [r5, #0] +10002e3a: 711e strb r6, [r3, #4] +10002e3c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e40: 20000804 .word 0x20000804 +10002e44: 20000808 .word 0x20000808 + +10002e48 : +10002e48: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002e4c: b082 sub sp, #8 +10002e4e: 460d mov r5, r1 +10002e50: 4691 mov r9, r2 +10002e52: 461c mov r4, r3 +10002e54: 4606 mov r6, r0 +10002e56: f7fd ffa7 bl 10000da8 +10002e5a: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002e5e: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002e62: 4a2e ldr r2, [pc, #184] @ (10002f1c ) +10002e64: 1882 adds r2, r0, r2 +10002e66: f141 0300 adc.w r3, r1, #0 +10002e6a: 4594 cmp ip, r2 +10002e6c: eb77 0103 sbcs.w r1, r7, r3 +10002e70: bf3c itt cc +10002e72: 4662 movcc r2, ip +10002e74: 463b movcc r3, r7 +10002e76: 482a ldr r0, [pc, #168] @ (10002f20 ) +10002e78: f000 faee bl 10003458 <__mutex_try_enter_block_until_veneer> +10002e7c: 1c6b adds r3, r5, #1 +10002e7e: 4680 mov r8, r0 +10002e80: d040 beq.n 10002f04 +10002e82: b30c cbz r4, 10002ec8 +10002e84: 4f27 ldr r7, [pc, #156] @ (10002f24 ) +10002e86: 4b28 ldr r3, [pc, #160] @ (10002f28 ) +10002e88: 681c ldr r4, [r3, #0] +10002e8a: b1b4 cbz r4, 10002eba +10002e8c: f1b9 0f00 cmp.w r9, #0 +10002e90: d11c bne.n 10002ecc +10002e92: f8df 909c ldr.w r9, [pc, #156] @ 10002f30 +10002e96: e001 b.n 10002e9c +10002e98: 6924 ldr r4, [r4, #16] +10002e9a: b174 cbz r4, 10002eba +10002e9c: 6823 ldr r3, [r4, #0] +10002e9e: 2b00 cmp r3, #0 +10002ea0: d0fa beq.n 10002e98 +10002ea2: f8d9 3000 ldr.w r3, [r9] +10002ea6: b10b cbz r3, 10002eac +10002ea8: 429c cmp r4, r3 +10002eaa: d1f5 bne.n 10002e98 +10002eac: 4620 mov r0, r4 +10002eae: 462a mov r2, r5 +10002eb0: 4631 mov r1, r6 +10002eb2: 47b8 blx r7 +10002eb4: 6924 ldr r4, [r4, #16] +10002eb6: 2c00 cmp r4, #0 +10002eb8: d1f0 bne.n 10002e9c +10002eba: f1b8 0f00 cmp.w r8, #0 +10002ebe: d126 bne.n 10002f0e +10002ec0: 4628 mov r0, r5 +10002ec2: b002 add sp, #8 +10002ec4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002ec8: 4f18 ldr r7, [pc, #96] @ (10002f2c ) +10002eca: e7dc b.n 10002e86 +10002ecc: f04f 0a0a mov.w sl, #10 +10002ed0: f8df 905c ldr.w r9, [pc, #92] @ 10002f30 +10002ed4: e002 b.n 10002edc +10002ed6: 6924 ldr r4, [r4, #16] +10002ed8: 2c00 cmp r4, #0 +10002eda: d0ee beq.n 10002eba +10002edc: 6823 ldr r3, [r4, #0] +10002ede: 2b00 cmp r3, #0 +10002ee0: d0f9 beq.n 10002ed6 +10002ee2: f8d9 3000 ldr.w r3, [r9] +10002ee6: b10b cbz r3, 10002eec +10002ee8: 42a3 cmp r3, r4 +10002eea: d1f4 bne.n 10002ed6 +10002eec: 462a mov r2, r5 +10002eee: 4631 mov r1, r6 +10002ef0: 4620 mov r0, r4 +10002ef2: 47b8 blx r7 +10002ef4: 2201 movs r2, #1 +10002ef6: 4620 mov r0, r4 +10002ef8: f10d 0107 add.w r1, sp, #7 +10002efc: f88d a007 strb.w sl, [sp, #7] +10002f00: 47b8 blx r7 +10002f02: e7e8 b.n 10002ed6 +10002f04: 4630 mov r0, r6 +10002f06: f000 fa6f bl 100033e8 +10002f0a: 4605 mov r5, r0 +10002f0c: e7b9 b.n 10002e82 +10002f0e: 4804 ldr r0, [pc, #16] @ (10002f20 ) +10002f10: f000 fa9e bl 10003450 <__mutex_exit_veneer> +10002f14: 4628 mov r0, r5 +10002f16: b002 add sp, #8 +10002f18: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002f1c: 000f4240 .word 0x000f4240 +10002f20: 20000624 .word 0x20000624 +10002f24: 10002d39 .word 0x10002d39 +10002f28: 20000804 .word 0x20000804 +10002f2c: 10002d31 .word 0x10002d31 +10002f30: 20000808 .word 0x20000808 + +10002f34 : +10002f34: 4a08 ldr r2, [pc, #32] @ (10002f58 ) +10002f36: 6813 ldr r3, [r2, #0] +10002f38: b923 cbnz r3, 10002f44 +10002f3a: e00a b.n 10002f52 +10002f3c: f103 0210 add.w r2, r3, #16 +10002f40: 691b ldr r3, [r3, #16] +10002f42: b133 cbz r3, 10002f52 +10002f44: 4283 cmp r3, r0 +10002f46: d1f9 bne.n 10002f3c +10002f48: b929 cbnz r1, 10002f56 +10002f4a: 6918 ldr r0, [r3, #16] +10002f4c: 6010 str r0, [r2, #0] +10002f4e: 6119 str r1, [r3, #16] +10002f50: 4770 bx lr +10002f52: b101 cbz r1, 10002f56 +10002f54: 6010 str r0, [r2, #0] +10002f56: 4770 bx lr +10002f58: 20000804 .word 0x20000804 + +10002f5c : +10002f5c: b508 push {r3, lr} +10002f5e: f000 f9a3 bl 100032a8 +10002f62: 2001 movs r0, #1 +10002f64: bd08 pop {r3, pc} +10002f66: bf00 nop + +10002f68 <__wrap_putchar>: +10002f68: b5f0 push {r4, r5, r6, r7, lr} +10002f6a: b083 sub sp, #12 +10002f6c: 4606 mov r6, r0 +10002f6e: f88d 0007 strb.w r0, [sp, #7] +10002f72: f7fd ff19 bl 10000da8 +10002f76: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10002f7a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10002f7e: 4a17 ldr r2, [pc, #92] @ (10002fdc <__wrap_putchar+0x74>) +10002f80: 1882 adds r2, r0, r2 +10002f82: f141 0300 adc.w r3, r1, #0 +10002f86: 4295 cmp r5, r2 +10002f88: eb74 0103 sbcs.w r1, r4, r3 +10002f8c: bf3c itt cc +10002f8e: 4623 movcc r3, r4 +10002f90: 462a movcc r2, r5 +10002f92: 4813 ldr r0, [pc, #76] @ (10002fe0 <__wrap_putchar+0x78>) +10002f94: f000 fa60 bl 10003458 <__mutex_try_enter_block_until_veneer> +10002f98: 4b12 ldr r3, [pc, #72] @ (10002fe4 <__wrap_putchar+0x7c>) +10002f9a: 4607 mov r7, r0 +10002f9c: 681c ldr r4, [r3, #0] +10002f9e: b19c cbz r4, 10002fc8 <__wrap_putchar+0x60> +10002fa0: 4d11 ldr r5, [pc, #68] @ (10002fe8 <__wrap_putchar+0x80>) +10002fa2: e001 b.n 10002fa8 <__wrap_putchar+0x40> +10002fa4: 6924 ldr r4, [r4, #16] +10002fa6: b17c cbz r4, 10002fc8 <__wrap_putchar+0x60> +10002fa8: 6823 ldr r3, [r4, #0] +10002faa: 2b00 cmp r3, #0 +10002fac: d0fa beq.n 10002fa4 <__wrap_putchar+0x3c> +10002fae: 682b ldr r3, [r5, #0] +10002fb0: b10b cbz r3, 10002fb6 <__wrap_putchar+0x4e> +10002fb2: 429c cmp r4, r3 +10002fb4: d1f6 bne.n 10002fa4 <__wrap_putchar+0x3c> +10002fb6: 4620 mov r0, r4 +10002fb8: 2201 movs r2, #1 +10002fba: f10d 0107 add.w r1, sp, #7 +10002fbe: f7ff febb bl 10002d38 +10002fc2: 6924 ldr r4, [r4, #16] +10002fc4: 2c00 cmp r4, #0 +10002fc6: d1ef bne.n 10002fa8 <__wrap_putchar+0x40> +10002fc8: b917 cbnz r7, 10002fd0 <__wrap_putchar+0x68> +10002fca: 4630 mov r0, r6 +10002fcc: b003 add sp, #12 +10002fce: bdf0 pop {r4, r5, r6, r7, pc} +10002fd0: 4803 ldr r0, [pc, #12] @ (10002fe0 <__wrap_putchar+0x78>) +10002fd2: f000 fa3d bl 10003450 <__mutex_exit_veneer> +10002fd6: 4630 mov r0, r6 +10002fd8: b003 add sp, #12 +10002fda: bdf0 pop {r4, r5, r6, r7, pc} +10002fdc: 000f4240 .word 0x000f4240 +10002fe0: 20000624 .word 0x20000624 +10002fe4: 20000804 .word 0x20000804 +10002fe8: 20000808 .word 0x20000808 + +10002fec <__wrap_puts>: +10002fec: b538 push {r3, r4, r5, lr} +10002fee: 4604 mov r4, r0 +10002ff0: f000 f9fa bl 100033e8 +10002ff4: 2301 movs r3, #1 +10002ff6: 4605 mov r5, r0 +10002ff8: 461a mov r2, r3 +10002ffa: 4620 mov r0, r4 +10002ffc: 4629 mov r1, r5 +10002ffe: f7ff ff23 bl 10002e48 +10003002: 4b08 ldr r3, [pc, #32] @ (10003024 <__wrap_puts+0x38>) +10003004: 681c ldr r4, [r3, #0] +10003006: b12c cbz r4, 10003014 <__wrap_puts+0x28> +10003008: 6863 ldr r3, [r4, #4] +1000300a: b12b cbz r3, 10003018 <__wrap_puts+0x2c> +1000300c: 4798 blx r3 +1000300e: 6924 ldr r4, [r4, #16] +10003010: 2c00 cmp r4, #0 +10003012: d1f9 bne.n 10003008 <__wrap_puts+0x1c> +10003014: 4628 mov r0, r5 +10003016: bd38 pop {r3, r4, r5, pc} +10003018: 6924 ldr r4, [r4, #16] +1000301a: 2c00 cmp r4, #0 +1000301c: d1f4 bne.n 10003008 <__wrap_puts+0x1c> +1000301e: 4628 mov r0, r5 +10003020: bd38 pop {r3, r4, r5, pc} +10003022: bf00 nop +10003024: 20000804 .word 0x20000804 + +10003028 <__wrap_vprintf>: +10003028: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000302c: b0a2 sub sp, #136 @ 0x88 +1000302e: 4604 mov r4, r0 +10003030: 460d mov r5, r1 +10003032: f7fd feb9 bl 10000da8 +10003036: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +1000303a: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +1000303e: 4a26 ldr r2, [pc, #152] @ (100030d8 <__wrap_vprintf+0xb0>) +10003040: f8df 80a4 ldr.w r8, [pc, #164] @ 100030e8 <__wrap_vprintf+0xc0> +10003044: 1882 adds r2, r0, r2 +10003046: f141 0300 adc.w r3, r1, #0 +1000304a: 4297 cmp r7, r2 +1000304c: eb76 0103 sbcs.w r1, r6, r3 +10003050: bf3c itt cc +10003052: 463a movcc r2, r7 +10003054: 4633 movcc r3, r6 +10003056: 4821 ldr r0, [pc, #132] @ (100030dc <__wrap_vprintf+0xb4>) +10003058: f000 f9fe bl 10003458 <__mutex_try_enter_block_until_veneer> +1000305c: 2700 movs r7, #0 +1000305e: 462b mov r3, r5 +10003060: 4622 mov r2, r4 +10003062: 4606 mov r6, r0 +10003064: a901 add r1, sp, #4 +10003066: 481e ldr r0, [pc, #120] @ (100030e0 <__wrap_vprintf+0xb8>) +10003068: 9701 str r7, [sp, #4] +1000306a: f7ff fe1d bl 10002ca8 +1000306e: 9b01 ldr r3, [sp, #4] +10003070: 4605 mov r5, r0 +10003072: f8d8 4000 ldr.w r4, [r8] +10003076: b1c3 cbz r3, 100030aa <__wrap_vprintf+0x82> +10003078: 2c00 cmp r4, #0 +1000307a: d02b beq.n 100030d4 <__wrap_vprintf+0xac> +1000307c: 4f19 ldr r7, [pc, #100] @ (100030e4 <__wrap_vprintf+0xbc>) +1000307e: e001 b.n 10003084 <__wrap_vprintf+0x5c> +10003080: 6924 ldr r4, [r4, #16] +10003082: b174 cbz r4, 100030a2 <__wrap_vprintf+0x7a> +10003084: 6823 ldr r3, [r4, #0] +10003086: 2b00 cmp r3, #0 +10003088: d0fa beq.n 10003080 <__wrap_vprintf+0x58> +1000308a: 683b ldr r3, [r7, #0] +1000308c: b10b cbz r3, 10003092 <__wrap_vprintf+0x6a> +1000308e: 42a3 cmp r3, r4 +10003090: d1f6 bne.n 10003080 <__wrap_vprintf+0x58> +10003092: 4620 mov r0, r4 +10003094: 9a01 ldr r2, [sp, #4] +10003096: a902 add r1, sp, #8 +10003098: f7ff fe4e bl 10002d38 +1000309c: 6924 ldr r4, [r4, #16] +1000309e: 2c00 cmp r4, #0 +100030a0: d1f0 bne.n 10003084 <__wrap_vprintf+0x5c> +100030a2: 2300 movs r3, #0 +100030a4: f8d8 4000 ldr.w r4, [r8] +100030a8: 9301 str r3, [sp, #4] +100030aa: b12c cbz r4, 100030b8 <__wrap_vprintf+0x90> +100030ac: 6863 ldr r3, [r4, #4] +100030ae: b143 cbz r3, 100030c2 <__wrap_vprintf+0x9a> +100030b0: 4798 blx r3 +100030b2: 6924 ldr r4, [r4, #16] +100030b4: 2c00 cmp r4, #0 +100030b6: d1f9 bne.n 100030ac <__wrap_vprintf+0x84> +100030b8: b92e cbnz r6, 100030c6 <__wrap_vprintf+0x9e> +100030ba: 4628 mov r0, r5 +100030bc: b022 add sp, #136 @ 0x88 +100030be: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030c2: 6924 ldr r4, [r4, #16] +100030c4: e7f1 b.n 100030aa <__wrap_vprintf+0x82> +100030c6: 4805 ldr r0, [pc, #20] @ (100030dc <__wrap_vprintf+0xb4>) +100030c8: f000 f9c2 bl 10003450 <__mutex_exit_veneer> +100030cc: 4628 mov r0, r5 +100030ce: b022 add sp, #136 @ 0x88 +100030d0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030d4: 9401 str r4, [sp, #4] +100030d6: e7ef b.n 100030b8 <__wrap_vprintf+0x90> +100030d8: 000f4240 .word 0x000f4240 +100030dc: 20000624 .word 0x20000624 +100030e0: 10002de9 .word 0x10002de9 +100030e4: 20000808 .word 0x20000808 +100030e8: 20000804 .word 0x20000804 + +100030ec <__wrap_printf>: +100030ec: b40f push {r0, r1, r2, r3} +100030ee: b500 push {lr} +100030f0: b083 sub sp, #12 +100030f2: a904 add r1, sp, #16 +100030f4: f851 0b04 ldr.w r0, [r1], #4 +100030f8: 9101 str r1, [sp, #4] +100030fa: f7ff ff95 bl 10003028 <__wrap_vprintf> +100030fe: b003 add sp, #12 +10003100: f85d eb04 ldr.w lr, [sp], #4 +10003104: b004 add sp, #16 +10003106: 4770 bx lr + +10003108 : +10003108: f1b1 0c00 subs.w ip, r1, #0 +1000310c: dd1d ble.n 1000314a +1000310e: 4a0f ldr r2, [pc, #60] @ (1000314c ) +10003110: 4b0f ldr r3, [pc, #60] @ (10003150 ) +10003112: 6812 ldr r2, [r2, #0] +10003114: b530 push {r4, r5, lr} +10003116: 1ad3 subs r3, r2, r3 +10003118: fab3 f383 clz r3, r3 +1000311c: 240d movs r4, #13 +1000311e: 4d0d ldr r5, [pc, #52] @ (10003154 ) +10003120: 095b lsrs r3, r3, #5 +10003122: 1e41 subs r1, r0, #1 +10003124: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003128: 448c add ip, r1 +1000312a: f811 0f01 ldrb.w r0, [r1, #1]! +1000312e: 4586 cmp lr, r0 +10003130: d006 beq.n 10003140 +10003132: 6993 ldr r3, [r2, #24] +10003134: 069b lsls r3, r3, #26 +10003136: d4fc bmi.n 10003132 +10003138: 4561 cmp r1, ip +1000313a: 6010 str r0, [r2, #0] +1000313c: d1f5 bne.n 1000312a +1000313e: bd30 pop {r4, r5, pc} +10003140: 6993 ldr r3, [r2, #24] +10003142: 069d lsls r5, r3, #26 +10003144: d4fc bmi.n 10003140 +10003146: 6014 str r4, [r2, #0] +10003148: e7f3 b.n 10003132 +1000314a: 4770 bx lr +1000314c: 20000850 .word 0x20000850 +10003150: 40078000 .word 0x40078000 +10003154: 2000084c .word 0x2000084c + +10003158 : +10003158: 4b22 ldr r3, [pc, #136] @ (100031e4 ) +1000315a: f1b1 0c00 subs.w ip, r1, #0 +1000315e: b410 push {r4} +10003160: 681c ldr r4, [r3, #0] +10003162: dd2e ble.n 100031c2 +10003164: 4603 mov r3, r0 +10003166: 2000 movs r0, #0 +10003168: 4a1f ldr r2, [pc, #124] @ (100031e8 ) +1000316a: 1e59 subs r1, r3, #1 +1000316c: 6812 ldr r2, [r2, #0] +1000316e: 6993 ldr r3, [r2, #24] +10003170: 06db lsls r3, r3, #27 +10003172: d417 bmi.n 100031a4 +10003174: 3001 adds r0, #1 +10003176: 6993 ldr r3, [r2, #24] +10003178: 06db lsls r3, r3, #27 +1000317a: d4fc bmi.n 10003176 +1000317c: 6813 ldr r3, [r2, #0] +1000317e: 4584 cmp ip, r0 +10003180: f801 3f01 strb.w r3, [r1, #1]! +10003184: d1f3 bne.n 1000316e +10003186: b14c cbz r4, 1000319c +10003188: 2150 movs r1, #80 @ 0x50 +1000318a: 4613 mov r3, r2 +1000318c: 6391 str r1, [r2, #56] @ 0x38 +1000318e: f853 2f34 ldr.w r2, [r3, #52]! +10003192: f002 0238 and.w r2, r2, #56 @ 0x38 +10003196: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000319a: 601a str r2, [r3, #0] +1000319c: 4660 mov r0, ip +1000319e: f85d 4b04 ldr.w r4, [sp], #4 +100031a2: 4770 bx lr +100031a4: b14c cbz r4, 100031ba +100031a6: 2150 movs r1, #80 @ 0x50 +100031a8: 4613 mov r3, r2 +100031aa: 6391 str r1, [r2, #56] @ 0x38 +100031ac: f853 2f34 ldr.w r2, [r3, #52]! +100031b0: f002 0238 and.w r2, r2, #56 @ 0x38 +100031b4: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031b8: 601a str r2, [r3, #0] +100031ba: b178 cbz r0, 100031dc +100031bc: f85d 4b04 ldr.w r4, [sp], #4 +100031c0: 4770 bx lr +100031c2: b15c cbz r4, 100031dc +100031c4: 4b08 ldr r3, [pc, #32] @ (100031e8 ) +100031c6: 2150 movs r1, #80 @ 0x50 +100031c8: 681a ldr r2, [r3, #0] +100031ca: 4613 mov r3, r2 +100031cc: 6391 str r1, [r2, #56] @ 0x38 +100031ce: f853 2f34 ldr.w r2, [r3, #52]! +100031d2: f002 0238 and.w r2, r2, #56 @ 0x38 +100031d6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031da: 601a str r2, [r3, #0] +100031dc: f06f 0002 mvn.w r0, #2 +100031e0: e7dd b.n 1000319e +100031e2: bf00 nop +100031e4: 200007d0 .word 0x200007d0 +100031e8: 20000850 .word 0x20000850 + +100031ec : +100031ec: 4b05 ldr r3, [pc, #20] @ (10003204 ) +100031ee: 681b ldr r3, [r3, #0] +100031f0: b133 cbz r3, 10003200 +100031f2: 2100 movs r1, #0 +100031f4: 4a04 ldr r2, [pc, #16] @ (10003208 ) +100031f6: 4805 ldr r0, [pc, #20] @ (1000320c ) +100031f8: 6812 ldr r2, [r2, #0] +100031fa: 6800 ldr r0, [r0, #0] +100031fc: 6391 str r1, [r2, #56] @ 0x38 +100031fe: 4718 bx r3 +10003200: 4770 bx lr +10003202: bf00 nop +10003204: 200007d0 .word 0x200007d0 +10003208: 20000850 .word 0x20000850 +1000320c: 200007d4 .word 0x200007d4 + +10003210 : +10003210: 4b02 ldr r3, [pc, #8] @ (1000321c ) +10003212: 681a ldr r2, [r3, #0] +10003214: 6993 ldr r3, [r2, #24] +10003216: 071b lsls r3, r3, #28 +10003218: d4fc bmi.n 10003214 +1000321a: 4770 bx lr +1000321c: 20000850 .word 0x20000850 + +10003220 : +10003220: b5f8 push {r3, r4, r5, r6, r7, lr} +10003222: 4f1c ldr r7, [pc, #112] @ (10003294 ) +10003224: 4d1c ldr r5, [pc, #112] @ (10003298 ) +10003226: 683a ldr r2, [r7, #0] +10003228: 4e1c ldr r6, [pc, #112] @ (1000329c ) +1000322a: 42aa cmp r2, r5 +1000322c: bf14 ite ne +1000322e: 2521 movne r5, #33 @ 0x21 +10003230: 2522 moveq r5, #34 @ 0x22 +10003232: 4604 mov r4, r0 +10003234: f8d6 c000 ldr.w ip, [r6] +10003238: b118 cbz r0, 10003242 +1000323a: f1bc 0f00 cmp.w ip, #0 +1000323e: d010 beq.n 10003262 +10003240: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003242: f1bc 0f00 cmp.w ip, #0 +10003246: d0fb beq.n 10003240 +10003248: 4601 mov r1, r0 +1000324a: 6390 str r0, [r2, #56] @ 0x38 +1000324c: 4628 mov r0, r5 +1000324e: f7fd f8a3 bl 10000398 +10003252: 4628 mov r0, r5 +10003254: 4912 ldr r1, [pc, #72] @ (100032a0 ) +10003256: f7fd f8e5 bl 10000424 +1000325a: 4b12 ldr r3, [pc, #72] @ (100032a4 ) +1000325c: 6034 str r4, [r6, #0] +1000325e: 601c str r4, [r3, #0] +10003260: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003262: 460b mov r3, r1 +10003264: 4a0f ldr r2, [pc, #60] @ (100032a4 ) +10003266: 490e ldr r1, [pc, #56] @ (100032a0 ) +10003268: 6030 str r0, [r6, #0] +1000326a: 4628 mov r0, r5 +1000326c: 6013 str r3, [r2, #0] +1000326e: f7fd f8a9 bl 100003c4 +10003272: 2101 movs r1, #1 +10003274: 4628 mov r0, r5 +10003276: f7fd f88f bl 10000398 +1000327a: 683a ldr r2, [r7, #0] +1000327c: 2150 movs r1, #80 @ 0x50 +1000327e: 4613 mov r3, r2 +10003280: 6391 str r1, [r2, #56] @ 0x38 +10003282: f853 2f34 ldr.w r2, [r3, #52]! +10003286: f002 0238 and.w r2, r2, #56 @ 0x38 +1000328a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000328e: 601a str r2, [r3, #0] +10003290: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003292: bf00 nop +10003294: 20000850 .word 0x20000850 +10003298: 40078000 .word 0x40078000 +1000329c: 200007d0 .word 0x200007d0 +100032a0: 100031ed .word 0x100031ed +100032a4: 200007d4 .word 0x200007d4 + +100032a8 : +100032a8: b510 push {r4, lr} +100032aa: 490e ldr r1, [pc, #56] @ (100032e4 ) +100032ac: 4c0e ldr r4, [pc, #56] @ (100032e8 ) +100032ae: 480f ldr r0, [pc, #60] @ (100032ec ) +100032b0: 4a0f ldr r2, [pc, #60] @ (100032f0 ) +100032b2: 4b10 ldr r3, [pc, #64] @ (100032f4 ) +100032b4: 7800 ldrb r0, [r0, #0] +100032b6: 6021 str r1, [r4, #0] +100032b8: 2000 movs r0, #0 +100032ba: 2102 movs r1, #2 +100032bc: 7812 ldrb r2, [r2, #0] +100032be: 781b ldrb r3, [r3, #0] +100032c0: f7fc ffc8 bl 10000254 +100032c4: 2102 movs r1, #2 +100032c6: 2001 movs r0, #1 +100032c8: f7fc ffc4 bl 10000254 +100032cc: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100032d0: 6820 ldr r0, [r4, #0] +100032d2: f7fd fda1 bl 10000e18 +100032d6: e8bd 4010 ldmia.w sp!, {r4, lr} +100032da: 2101 movs r1, #1 +100032dc: 4806 ldr r0, [pc, #24] @ (100032f8 ) +100032de: f7ff be29 b.w 10002f34 +100032e2: bf00 nop +100032e4: 40070000 .word 0x40070000 +100032e8: 20000850 .word 0x20000850 +100032ec: 10003698 .word 0x10003698 +100032f0: 10003694 .word 0x10003694 +100032f4: 10003690 .word 0x10003690 +100032f8: 2000060c .word 0x2000060c + +100032fc : +100032fc: 4684 mov ip, r0 +100032fe: ea41 0300 orr.w r3, r1, r0 +10003302: f013 0303 ands.w r3, r3, #3 +10003306: d149 bne.n 1000339c +10003308: 3a40 subs r2, #64 @ 0x40 +1000330a: d323 bcc.n 10003354 +1000330c: 680b ldr r3, [r1, #0] +1000330e: 6003 str r3, [r0, #0] +10003310: 684b ldr r3, [r1, #4] +10003312: 6043 str r3, [r0, #4] +10003314: 688b ldr r3, [r1, #8] +10003316: 6083 str r3, [r0, #8] +10003318: 68cb ldr r3, [r1, #12] +1000331a: 60c3 str r3, [r0, #12] +1000331c: 690b ldr r3, [r1, #16] +1000331e: 6103 str r3, [r0, #16] +10003320: 694b ldr r3, [r1, #20] +10003322: 6143 str r3, [r0, #20] +10003324: 698b ldr r3, [r1, #24] +10003326: 6183 str r3, [r0, #24] +10003328: 69cb ldr r3, [r1, #28] +1000332a: 61c3 str r3, [r0, #28] +1000332c: 6a0b ldr r3, [r1, #32] +1000332e: 6203 str r3, [r0, #32] +10003330: 6a4b ldr r3, [r1, #36] @ 0x24 +10003332: 6243 str r3, [r0, #36] @ 0x24 +10003334: 6a8b ldr r3, [r1, #40] @ 0x28 +10003336: 6283 str r3, [r0, #40] @ 0x28 +10003338: 6acb ldr r3, [r1, #44] @ 0x2c +1000333a: 62c3 str r3, [r0, #44] @ 0x2c +1000333c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000333e: 6303 str r3, [r0, #48] @ 0x30 +10003340: 6b4b ldr r3, [r1, #52] @ 0x34 +10003342: 6343 str r3, [r0, #52] @ 0x34 +10003344: 6b8b ldr r3, [r1, #56] @ 0x38 +10003346: 6383 str r3, [r0, #56] @ 0x38 +10003348: 6bcb ldr r3, [r1, #60] @ 0x3c +1000334a: 63c3 str r3, [r0, #60] @ 0x3c +1000334c: 3040 adds r0, #64 @ 0x40 +1000334e: 3140 adds r1, #64 @ 0x40 +10003350: 3a40 subs r2, #64 @ 0x40 +10003352: d2db bcs.n 1000330c +10003354: 3230 adds r2, #48 @ 0x30 +10003356: d30b bcc.n 10003370 +10003358: 680b ldr r3, [r1, #0] +1000335a: 6003 str r3, [r0, #0] +1000335c: 684b ldr r3, [r1, #4] +1000335e: 6043 str r3, [r0, #4] +10003360: 688b ldr r3, [r1, #8] +10003362: 6083 str r3, [r0, #8] +10003364: 68cb ldr r3, [r1, #12] +10003366: 60c3 str r3, [r0, #12] +10003368: 3010 adds r0, #16 +1000336a: 3110 adds r1, #16 +1000336c: 3a10 subs r2, #16 +1000336e: d2f3 bcs.n 10003358 +10003370: 320c adds r2, #12 +10003372: d305 bcc.n 10003380 +10003374: f851 3b04 ldr.w r3, [r1], #4 +10003378: f840 3b04 str.w r3, [r0], #4 +1000337c: 3a04 subs r2, #4 +1000337e: d2f9 bcs.n 10003374 +10003380: 3204 adds r2, #4 +10003382: d008 beq.n 10003396 +10003384: 07d2 lsls r2, r2, #31 +10003386: bf1c itt ne +10003388: f811 3b01 ldrbne.w r3, [r1], #1 +1000338c: f800 3b01 strbne.w r3, [r0], #1 +10003390: d301 bcc.n 10003396 +10003392: 880b ldrh r3, [r1, #0] +10003394: 8003 strh r3, [r0, #0] +10003396: 4660 mov r0, ip +10003398: 4770 bx lr +1000339a: bf00 nop +1000339c: 2a08 cmp r2, #8 +1000339e: d313 bcc.n 100033c8 +100033a0: 078b lsls r3, r1, #30 +100033a2: d0b1 beq.n 10003308 +100033a4: f010 0303 ands.w r3, r0, #3 +100033a8: d0ae beq.n 10003308 +100033aa: f1c3 0304 rsb r3, r3, #4 +100033ae: 1ad2 subs r2, r2, r3 +100033b0: 07db lsls r3, r3, #31 +100033b2: bf1c itt ne +100033b4: f811 3b01 ldrbne.w r3, [r1], #1 +100033b8: f800 3b01 strbne.w r3, [r0], #1 +100033bc: d3a4 bcc.n 10003308 +100033be: f831 3b02 ldrh.w r3, [r1], #2 +100033c2: f820 3b02 strh.w r3, [r0], #2 +100033c6: e79f b.n 10003308 +100033c8: 3a04 subs r2, #4 +100033ca: d3d9 bcc.n 10003380 +100033cc: 3a01 subs r2, #1 +100033ce: f811 3b01 ldrb.w r3, [r1], #1 +100033d2: f800 3b01 strb.w r3, [r0], #1 +100033d6: d2f9 bcs.n 100033cc +100033d8: 780b ldrb r3, [r1, #0] +100033da: 7003 strb r3, [r0, #0] +100033dc: 784b ldrb r3, [r1, #1] +100033de: 7043 strb r3, [r0, #1] +100033e0: 788b ldrb r3, [r1, #2] +100033e2: 7083 strb r3, [r0, #2] +100033e4: 4660 mov r0, ip +100033e6: 4770 bx lr + +100033e8 : +100033e8: f020 0103 bic.w r1, r0, #3 +100033ec: f010 0003 ands.w r0, r0, #3 +100033f0: f1c0 0000 rsb r0, r0, #0 +100033f4: f851 3b04 ldr.w r3, [r1], #4 +100033f8: f100 0c04 add.w ip, r0, #4 +100033fc: ea4f 0ccc mov.w ip, ip, lsl #3 +10003400: f06f 0200 mvn.w r2, #0 +10003404: bf1c itt ne +10003406: fa22 f20c lsrne.w r2, r2, ip +1000340a: 4313 orrne r3, r2 +1000340c: f04f 0c01 mov.w ip, #1 +10003410: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003414: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003418: eba3 020c sub.w r2, r3, ip +1000341c: ea22 0203 bic.w r2, r2, r3 +10003420: ea12 12cc ands.w r2, r2, ip, lsl #7 +10003424: bf04 itt eq +10003426: f851 3b04 ldreq.w r3, [r1], #4 +1000342a: 3004 addeq r0, #4 +1000342c: d0f4 beq.n 10003418 +1000342e: f1c2 0100 rsb r1, r2, #0 +10003432: ea02 0201 and.w r2, r2, r1 +10003436: fab2 f282 clz r2, r2 +1000343a: f1c2 021f rsb r2, r2, #31 +1000343e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10003442: 4770 bx lr + +10003444 <_fini>: +10003444: b5f8 push {r3, r4, r5, r6, r7, lr} +10003446: bf00 nop + +10003448 <____aeabi_uldivmod_veneer>: +10003448: f85f f000 ldr.w pc, [pc] @ 1000344c <____aeabi_uldivmod_veneer+0x4> +1000344c: 20000221 .word 0x20000221 + +10003450 <__mutex_exit_veneer>: +10003450: f85f f000 ldr.w pc, [pc] @ 10003454 <__mutex_exit_veneer+0x4> +10003454: 200001e5 .word 0x200001e5 + +10003458 <__mutex_try_enter_block_until_veneer>: +10003458: f85f f000 ldr.w pc, [pc] @ 1000345c <__mutex_try_enter_block_until_veneer+0x4> +1000345c: 2000017d .word 0x2000017d + +10003460 <__pre_init_runtime_init_bootrom_reset>: +10003460: 100011d1 .... + +10003464 <__pre_init_runtime_init_early_resets>: +10003464: 10001145 E... + +10003468 <__pre_init_runtime_init_usb_power_down>: +10003468: 10001179 y... + +1000346c <__pre_init_runtime_init_clocks>: +1000346c: 10001265 e... + +10003470 <__pre_init_runtime_init_post_clock_resets>: +10003470: 100011b1 .... + +10003474 <__pre_init_runtime_init_boot_locks_reset>: +10003474: 100010c9 .... + +10003478 <__pre_init_runtime_init_spin_locks_reset>: +10003478: 100011f9 .... + +1000347c <__pre_init_runtime_init_bootrom_locking_enable>: +1000347c: 100010b5 .... + +10003480 <__pre_init_runtime_init_mutex>: +10003480: 100006e1 .... + +10003484 <__pre_init_runtime_init_install_ram_vector_table>: +10003484: 100011fd .... + +10003488 <__pre_init_runtime_init_default_alarm_pool>: +10003488: 10000a59 Y... + +1000348c <__pre_init_first_per_core_initializer>: +1000348c: 10001115 .... + +10003490 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003490: 100011e5 .... + +10003494 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10003494: 10001195 .... + +10003498 <__pre_init_spinlock_set_extexclall>: +10003498: 10000331 1... + +1000349c <__pre_init_runtime_init_per_core_irq_priorities>: +1000349c: 10000359 Y... + +100034a0 <__frame_dummy_init_array_entry>: +100034a0: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000ca1 .word 0x10000ca1 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 10000619 .word 0x10000619 + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003109 10003211 10003159 10003221 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b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.uf2 new file mode 100644 index 0000000..f3e8c64 Binary files /dev/null and b/WEEK05/0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.uf2 differ diff --git a/WEEK05/0x000e_floating-point-data-type/build/pico_flash_region.ld b/WEEK05/0x000e_floating-point-data-type/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK05/0x000e_floating-point-data-type/pico_sdk_import.cmake b/WEEK05/0x000e_floating-point-data-type/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK05/0x000e_floating-point-data-type/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK05/0x0011_double-floating-point-data-type/.gitignore b/WEEK05/0x0011_double-floating-point-data-type/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/c_cpp_properties.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/cmake-kits.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/extensions.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/launch.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/settings.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK05/0x0011_double-floating-point-data-type/.vscode/tasks.json b/WEEK05/0x0011_double-floating-point-data-type/.vscode/tasks.json new file mode 100644 index 0000000..2359f7f --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Risc-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK05/0x0011_double-floating-point-data-type/0x0011_double-floating-point-data-type.c b/WEEK05/0x0011_double-floating-point-data-type/0x0011_double-floating-point-data-type.c new file mode 100644 index 0000000..d4f3d11 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/0x0011_double-floating-point-data-type.c @@ -0,0 +1,11 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + double fav_num = 42.52525; + + stdio_init_all(); + + while (true) + printf("fav_num: %lf\r\n", fav_num); +} diff --git a/WEEK05/0x0011_double-floating-point-data-type/CMakeLists.txt b/WEEK05/0x0011_double-floating-point-data-type/CMakeLists.txt new file mode 100644 index 0000000..035b92e --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0011_double-floating-point-data-type C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0011_double-floating-point-data-type 0x0011_double-floating-point-data-type.c ) + +pico_set_program_name(0x0011_double-floating-point-data-type "0x0011_double-floating-point-data-type") +pico_set_program_version(0x0011_double-floating-point-data-type "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0011_double-floating-point-data-type 1) +pico_enable_stdio_usb(0x0011_double-floating-point-data-type 0) + +# Add the standard library to the build +target_link_libraries(0x0011_double-floating-point-data-type + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0011_double-floating-point-data-type PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0011_double-floating-point-data-type) + diff --git a/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin new file mode 100755 index 0000000..4e8170d Binary files /dev/null and b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin differ diff --git a/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.dis b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.dis new file mode 100644 index 0000000..f34ae90 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.dis @@ -0,0 +1,5742 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000034ac 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001c8 100034b0 100034b0 000044b0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003678 10003678 00004678 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003680 10003680 00004680 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005bdc 2**0 + CONTENTS + 6 .data 0000051c 20000110 100036ac 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005bdc 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003bc8 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003bc8 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005bdc 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005bdc 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003bc8 10003bc8 00005bc8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005bdc 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005c10 2**0 + CONTENTS, READONLY + 17 .debug_info 000206f0 00000000 00000000 00005c55 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005544 00000000 00000000 00026345 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000be8 00000000 00000000 0002b890 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 0000303d 00000000 00000000 0002c478 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 00015930 00000000 00000000 0002f4b5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 00005748 00000000 00000000 00044de5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00001f3c 00000000 00000000 0004a530 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 0000ffd1 00000000 00000000 0004c46c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002cd 00000000 00000000 0005c43d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003680 .word 0x10003680 +1000012c: 100036ac .word 0x100036ac +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003a90 .word 0x00003a90 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100036ac .word 0x100036ac +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003bc8 .word 0x10003bc8 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003bc8 .word 0x10003bc8 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002d15 .word 0x10002d15 +100001dc: 10000239 .word 0x10000239 +100001e0: 10002d0d .word 0x10002d0d + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 100034ac .word 0x100034ac +10000234: 00000000 .word 0x00000000 + +10000238
: +10000238: b538 push {r3, r4, r5, lr} +1000023a: a506 add r5, pc, #24 @ (adr r5, 10000254 ) +1000023c: e9d5 4500 ldrd r4, r5, [r5] +10000240: f002 fe90 bl 10002f64 +10000244: 4622 mov r2, r4 +10000246: 462b mov r3, r5 +10000248: 4801 ldr r0, [pc, #4] @ (10000250 ) +1000024a: f002 ff53 bl 100030f4 <__wrap_printf> +1000024e: e7f9 b.n 10000244 +10000250: 100034b0 .word 0x100034b0 +10000254: 645a1cac .word 0x645a1cac +10000258: 4045433b .word 0x4045433b + +1000025c : +1000025c: b410 push {r4} +1000025e: f44f 7480 mov.w r4, #256 @ 0x100 +10000262: 4b0c ldr r3, [pc, #48] @ (10000294 ) +10000264: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000268: eb03 0380 add.w r3, r3, r0, lsl #2 +1000026c: 00c0 lsls r0, r0, #3 +1000026e: f082 0240 eor.w r2, r2, #64 @ 0x40 +10000272: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000276: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +1000027a: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000027e: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000282: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000286: f8cc 2000 str.w r2, [ip] +1000028a: 6041 str r1, [r0, #4] +1000028c: 601c str r4, [r3, #0] +1000028e: f85d 4b04 ldr.w r4, [sp], #4 +10000292: 4770 bx lr +10000294: 40038004 .word 0x40038004 + +10000298 : +10000298: b40f push {r0, r1, r2, r3} +1000029a: b500 push {lr} +1000029c: b083 sub sp, #12 +1000029e: 9c04 ldr r4, [sp, #16] +100002a0: 4807 ldr r0, [pc, #28] @ (100002c0 ) +100002a2: f002 fea7 bl 10002ff4 <__wrap_puts> +100002a6: b13c cbz r4, 100002b8 +100002a8: a905 add r1, sp, #20 +100002aa: 4620 mov r0, r4 +100002ac: 9101 str r1, [sp, #4] +100002ae: f002 fd13 bl 10002cd8 +100002b2: 4804 ldr r0, [pc, #16] @ (100002c4 ) +100002b4: f002 fe9e bl 10002ff4 <__wrap_puts> +100002b8: 2001 movs r0, #1 +100002ba: f002 fd25 bl 10002d08 <_exit> +100002be: bf00 nop +100002c0: 100034c0 .word 0x100034c0 +100002c4: 100034d0 .word 0x100034d0 + +100002c8 : +100002c8: b570 push {r4, r5, r6, lr} +100002ca: 4686 mov lr, r0 +100002cc: f3ef 8510 mrs r5, PRIMASK +100002d0: b672 cpsid i +100002d2: 4c12 ldr r4, [pc, #72] @ (1000031c ) +100002d4: e8d4 6fcf ldaexb r6, [r4] +100002d8: 2001 movs r0, #1 +100002da: 2e00 cmp r6, #0 +100002dc: d1fa bne.n 100002d4 +100002de: e8c4 0f46 strexb r6, r0, [r4] +100002e2: 2e00 cmp r6, #0 +100002e4: d1f6 bne.n 100002d4 +100002e6: f3bf 8f5f dmb sy +100002ea: f04f 0c01 mov.w ip, #1 +100002ee: 08c8 lsrs r0, r1, #3 +100002f0: f001 0307 and.w r3, r1, #7 +100002f4: fa0c f303 lsl.w r3, ip, r3 +100002f8: f81e c000 ldrb.w ip, [lr, r0] +100002fc: ea1c 0603 ands.w r6, ip, r3 +10000300: d108 bne.n 10000314 +10000302: ea4c 0c03 orr.w ip, ip, r3 +10000306: f80e c000 strb.w ip, [lr, r0] +1000030a: e8c4 6f8f stlb r6, [r4] +1000030e: f385 8810 msr PRIMASK, r5 +10000312: bd70 pop {r4, r5, r6, pc} +10000314: 4610 mov r0, r2 +10000316: f7ff ffbf bl 10000298 +1000031a: bf00 nop +1000031c: 200007bb .word 0x200007bb + +10000320 : +10000320: 4a04 ldr r2, [pc, #16] @ (10000334 ) +10000322: 7810 ldrb r0, [r2, #0] +10000324: 1c43 adds r3, r0, #1 +10000326: b2db uxtb r3, r3 +10000328: 2b18 cmp r3, #24 +1000032a: bf28 it cs +1000032c: 2310 movcs r3, #16 +1000032e: 7013 strb r3, [r2, #0] +10000330: 4770 bx lr +10000332: bf00 nop +10000334: 200005a8 .word 0x200005a8 + +10000338 : +10000338: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +1000033c: 6893 ldr r3, [r2, #8] +1000033e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +10000342: 6093 str r3, [r2, #8] +10000344: 4770 bx lr +10000346: bf00 nop + +10000348 : +10000348: 2100 movs r1, #0 +1000034a: 4b04 ldr r3, [pc, #16] @ (1000035c ) +1000034c: f103 0220 add.w r2, r3, #32 +10000350: e8c3 1f8f stlb r1, [r3] +10000354: 3301 adds r3, #1 +10000356: 4293 cmp r3, r2 +10000358: d1fa bne.n 10000350 +1000035a: 4770 bx lr +1000035c: 200007b0 .word 0x200007b0 + +10000360 : +10000360: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000364: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000368: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +1000036c: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000370: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000374: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000378: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +1000037c: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000380: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000384: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000388: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000038c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000390: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000394: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000398: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000039c: b662 cpsie i +1000039e: 4770 bx lr + +100003a0 : +100003a0: 2301 movs r3, #1 +100003a2: f000 021f and.w r2, r0, #31 +100003a6: 4093 lsls r3, r2 +100003a8: 0940 lsrs r0, r0, #5 +100003aa: b141 cbz r1, 100003be +100003ac: 0080 lsls r0, r0, #2 +100003ae: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100003b2: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100003b6: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100003ba: 6003 str r3, [r0, #0] +100003bc: 4770 bx lr +100003be: 4a02 ldr r2, [pc, #8] @ (100003c8 ) +100003c0: 3020 adds r0, #32 +100003c2: f842 3020 str.w r3, [r2, r0, lsl #2] +100003c6: 4770 bx lr +100003c8: e000e100 .word 0xe000e100 + +100003cc : +100003cc: b5f8 push {r3, r4, r5, r6, r7, lr} +100003ce: 460d mov r5, r1 +100003d0: f3ef 8710 mrs r7, PRIMASK +100003d4: b672 cpsid i +100003d6: 4e12 ldr r6, [pc, #72] @ (10000420 ) +100003d8: e8d6 2fcf ldaexb r2, [r6] +100003dc: 2301 movs r3, #1 +100003de: 2a00 cmp r2, #0 +100003e0: d1fa bne.n 100003d8 +100003e2: e8c6 3f42 strexb r2, r3, [r6] +100003e6: 2a00 cmp r2, #0 +100003e8: d1f6 bne.n 100003d8 +100003ea: f3bf 8f5f dmb sy +100003ee: 4b0d ldr r3, [pc, #52] @ (10000424 ) +100003f0: f100 0410 add.w r4, r0, #16 +100003f4: 689b ldr r3, [r3, #8] +100003f6: 4a0c ldr r2, [pc, #48] @ (10000428 ) +100003f8: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100003fc: 4293 cmp r3, r2 +100003fe: d003 beq.n 10000408 +10000400: 4299 cmp r1, r3 +10000402: d001 beq.n 10000408 +10000404: f000 fe8c bl 10001120 +10000408: 4b06 ldr r3, [pc, #24] @ (10000424 ) +1000040a: 689b ldr r3, [r3, #8] +1000040c: f843 5024 str.w r5, [r3, r4, lsl #2] +10000410: f3bf 8f5f dmb sy +10000414: 2300 movs r3, #0 +10000416: e8c6 3f8f stlb r3, [r6] +1000041a: f387 8810 msr PRIMASK, r7 +1000041e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000420: 200007b9 .word 0x200007b9 +10000424: e000ed00 .word 0xe000ed00 +10000428: 10000111 .word 0x10000111 + +1000042c : +1000042c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000430: b083 sub sp, #12 +10000432: f3ef 8a10 mrs sl, PRIMASK +10000436: b672 cpsid i +10000438: 4e71 ldr r6, [pc, #452] @ (10000600 ) +1000043a: e8d6 2fcf ldaexb r2, [r6] +1000043e: 2301 movs r3, #1 +10000440: 2a00 cmp r2, #0 +10000442: d1fa bne.n 1000043a +10000444: e8c6 3f42 strexb r2, r3, [r6] +10000448: 2a00 cmp r2, #0 +1000044a: d1f6 bne.n 1000043a +1000044c: f3bf 8f5f dmb sy +10000450: 4b6c ldr r3, [pc, #432] @ (10000604 ) +10000452: f100 0810 add.w r8, r0, #16 +10000456: 689b ldr r3, [r3, #8] +10000458: 4a6b ldr r2, [pc, #428] @ (10000608 ) +1000045a: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000045e: 4295 cmp r5, r2 +10000460: d045 beq.n 100004ee +10000462: 428d cmp r5, r1 +10000464: 460c mov r4, r1 +10000466: d050 beq.n 1000050a +10000468: 4f68 ldr r7, [pc, #416] @ (1000060c ) +1000046a: 1beb subs r3, r5, r7 +1000046c: 2b2f cmp r3, #47 @ 0x2f +1000046e: d83e bhi.n 100004ee +10000470: 2101 movs r1, #1 +10000472: ea4f 1950 mov.w r9, r0, lsr #5 +10000476: ea4f 0989 mov.w r9, r9, lsl #2 +1000047a: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000047e: f509 4961 add.w r9, r9, #57600 @ 0xe100 +10000482: f000 031f and.w r3, r0, #31 +10000486: fa01 f003 lsl.w r0, r1, r3 +1000048a: f8d9 3000 ldr.w r3, [r9] +1000048e: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000492: ea00 0b03 and.w fp, r0, r3 +10000496: f3bf 8f5f dmb sy +1000049a: f3ef 8105 mrs r1, IPSR +1000049e: b2c9 uxtb r1, r1 +100004a0: 2900 cmp r1, #0 +100004a2: d034 beq.n 1000050e +100004a4: 4588 cmp r8, r1 +100004a6: d005 beq.n 100004b4 +100004a8: e9cd 1000 strd r1, r0, [sp] +100004ac: f000 fe38 bl 10001120 +100004b0: e9dd 1000 ldrd r1, r0, [sp] +100004b4: f025 0e01 bic.w lr, r5, #1 +100004b8: f8de c008 ldr.w ip, [lr, #8] +100004bc: 4564 cmp r4, ip +100004be: d105 bne.n 100004cc +100004c0: e089 b.n 100005d6 +100004c2: f8d3 c008 ldr.w ip, [r3, #8] +100004c6: 4564 cmp r4, ip +100004c8: d031 beq.n 1000052e +100004ca: 469e mov lr, r3 +100004cc: f99e 2006 ldrsb.w r2, [lr, #6] +100004d0: eb02 0342 add.w r3, r2, r2, lsl #1 +100004d4: 2a00 cmp r2, #0 +100004d6: eb07 0383 add.w r3, r7, r3, lsl #2 +100004da: daf2 bge.n 100004c2 +100004dc: 4564 cmp r4, ip +100004de: d061 beq.n 100005a4 +100004e0: f1bb 0f00 cmp.w fp, #0 +100004e4: d020 beq.n 10000528 +100004e6: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100004ea: f8c9 0000 str.w r0, [r9] +100004ee: 4b45 ldr r3, [pc, #276] @ (10000604 ) +100004f0: 689b ldr r3, [r3, #8] +100004f2: f843 5028 str.w r5, [r3, r8, lsl #2] +100004f6: f3bf 8f5f dmb sy +100004fa: 2300 movs r3, #0 +100004fc: e8c6 3f8f stlb r3, [r6] +10000500: f38a 8810 msr PRIMASK, sl +10000504: b003 add sp, #12 +10000506: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000050a: 4615 mov r5, r2 +1000050c: e7ef b.n 100004ee +1000050e: f025 0e01 bic.w lr, r5, #1 +10000512: f8de c008 ldr.w ip, [lr, #8] +10000516: 4564 cmp r4, ip +10000518: d1d8 bne.n 100004cc +1000051a: f99e 4006 ldrsb.w r4, [lr, #6] +1000051e: 4673 mov r3, lr +10000520: 2c00 cmp r4, #0 +10000522: da08 bge.n 10000536 +10000524: 4615 mov r5, r2 +10000526: e046 b.n 100005b6 +10000528: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000052c: e7df b.n 100004ee +1000052e: f993 4006 ldrsb.w r4, [r3, #6] +10000532: 2c00 cmp r4, #0 +10000534: db37 blt.n 100005a6 +10000536: eb04 0c44 add.w ip, r4, r4, lsl #1 +1000053a: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000053e: f89c 1007 ldrb.w r1, [ip, #7] +10000542: f8dc 2008 ldr.w r2, [ip, #8] +10000546: 71d9 strb r1, [r3, #7] +10000548: 609a str r2, [r3, #8] +1000054a: f99c 2006 ldrsb.w r2, [ip, #6] +1000054e: 0061 lsls r1, r4, #1 +10000550: 2a00 cmp r2, #0 +10000552: 719a strb r2, [r3, #6] +10000554: db3d blt.n 100005d2 +10000556: f8bc e004 ldrh.w lr, [ip, #4] +1000055a: ea5f 5e4e movs.w lr, lr, lsl #21 +1000055e: d505 bpl.n 1000056c +10000560: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000564: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000568: f10e 0e1f add.w lr, lr, #31 +1000056c: f06f 0c07 mvn.w ip, #7 +10000570: 190a adds r2, r1, r4 +10000572: ea4f 5e6e mov.w lr, lr, asr #21 +10000576: 0092 lsls r2, r2, #2 +10000578: eb02 024e add.w r2, r2, lr, lsl #1 +1000057c: 3208 adds r2, #8 +1000057e: 443a add r2, r7 +10000580: ebac 0c03 sub.w ip, ip, r3 +10000584: 4462 add r2, ip +10000586: f3c2 024a ubfx r2, r2, #1, #11 +1000058a: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000058e: ea6f 42d2 mvn.w r2, r2, lsr #19 +10000592: 809a strh r2, [r3, #4] +10000594: 4b1e ldr r3, [pc, #120] @ (10000610 ) +10000596: 4421 add r1, r4 +10000598: 781a ldrb r2, [r3, #0] +1000059a: eb07 0181 add.w r1, r7, r1, lsl #2 +1000059e: 701c strb r4, [r3, #0] +100005a0: 718a strb r2, [r1, #6] +100005a2: e79d b.n 100004e0 +100005a4: 4673 mov r3, lr +100005a6: b9d9 cbnz r1, 100005e0 +100005a8: 22ff movs r2, #255 @ 0xff +100005aa: f88e 2006 strb.w r2, [lr, #6] +100005ae: f64b 5201 movw r2, #48385 @ 0xbd01 +100005b2: f8ae 2004 strh.w r2, [lr, #4] +100005b6: 4c16 ldr r4, [pc, #88] @ (10000610 ) +100005b8: f64a 22aa movw r2, #43690 @ 0xaaaa +100005bc: f894 c000 ldrb.w ip, [r4] +100005c0: 4619 mov r1, r3 +100005c2: 1bc9 subs r1, r1, r7 +100005c4: 4149 adcs r1, r1 +100005c6: 434a muls r2, r1 +100005c8: 0d12 lsrs r2, r2, #20 +100005ca: f883 c006 strb.w ip, [r3, #6] +100005ce: 7022 strb r2, [r4, #0] +100005d0: e786 b.n 100004e0 +100005d2: 4a10 ldr r2, [pc, #64] @ (10000614 ) +100005d4: e7dd b.n 10000592 +100005d6: f99e 4006 ldrsb.w r4, [lr, #6] +100005da: 4673 mov r3, lr +100005dc: 2c00 cmp r4, #0 +100005de: daaa bge.n 10000536 +100005e0: 4a0d ldr r2, [pc, #52] @ (10000618 ) +100005e2: 4c0e ldr r4, [pc, #56] @ (1000061c ) +100005e4: 1ad2 subs r2, r2, r3 +100005e6: 3a08 subs r2, #8 +100005e8: f3c2 310a ubfx r1, r2, #12, #11 +100005ec: ea6f 5101 mvn.w r1, r1, lsl #20 +100005f0: ea6f 5111 mvn.w r1, r1, lsr #20 +100005f4: ea44 0252 orr.w r2, r4, r2, lsr #1 +100005f8: 80da strh r2, [r3, #6] +100005fa: 8099 strh r1, [r3, #4] +100005fc: e770 b.n 100004e0 +100005fe: bf00 nop +10000600: 200007b9 .word 0x200007b9 +10000604: e000ed00 .word 0xe000ed00 +10000608: 10000111 .word 0x10000111 +1000060c: 200005ac .word 0x200005ac +10000610: 20000854 .word 0x20000854 +10000614: ffffbd01 .word 0xffffbd01 +10000618: 200005e6 .word 0x200005e6 +1000061c: fffff800 .word 0xfffff800 + +10000620 : +10000620: b5f0 push {r4, r5, r6, r7, lr} +10000622: f3ef 8505 mrs r5, IPSR +10000626: b2ed uxtb r5, r5 +10000628: f3ef 8c10 mrs ip, PRIMASK +1000062c: b672 cpsid i +1000062e: 4926 ldr r1, [pc, #152] @ (100006c8 ) +10000630: e8d1 2fcf ldaexb r2, [r1] +10000634: 2301 movs r3, #1 +10000636: 2a00 cmp r2, #0 +10000638: d1fa bne.n 10000630 +1000063a: e8c1 3f42 strexb r2, r3, [r1] +1000063e: 2a00 cmp r2, #0 +10000640: d1f6 bne.n 10000630 +10000642: f3bf 8f5f dmb sy +10000646: 4e21 ldr r6, [pc, #132] @ (100006cc ) +10000648: f040 0e01 orr.w lr, r0, #1 +1000064c: 68b4 ldr r4, [r6, #8] +1000064e: f64a 23aa movw r3, #43690 @ 0xaaaa +10000652: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000656: 4a1e ldr r2, [pc, #120] @ (100006d0 ) +10000658: 4604 mov r4, r0 +1000065a: 1aa4 subs r4, r4, r2 +1000065c: 4164 adcs r4, r4 +1000065e: 4363 muls r3, r4 +10000660: 0d1b lsrs r3, r3, #20 +10000662: 4577 cmp r7, lr +10000664: b25b sxtb r3, r3 +10000666: d01b beq.n 100006a0 +10000668: f992 4006 ldrsb.w r4, [r2, #6] +1000066c: 429c cmp r4, r3 +1000066e: d01c beq.n 100006aa +10000670: f992 4012 ldrsb.w r4, [r2, #18] +10000674: 429c cmp r4, r3 +10000676: d023 beq.n 100006c0 +10000678: f992 401e ldrsb.w r4, [r2, #30] +1000067c: 429c cmp r4, r3 +1000067e: d021 beq.n 100006c4 +10000680: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000684: 429c cmp r4, r3 +10000686: bf08 it eq +10000688: 2403 moveq r4, #3 +1000068a: d00f beq.n 100006ac +1000068c: 4a11 ldr r2, [pc, #68] @ (100006d4 ) +1000068e: 2400 movs r4, #0 +10000690: 7815 ldrb r5, [r2, #0] +10000692: 7013 strb r3, [r2, #0] +10000694: 7185 strb r5, [r0, #6] +10000696: e8c1 4f8f stlb r4, [r1] +1000069a: f38c 8810 msr PRIMASK, ip +1000069e: bdf0 pop {r4, r5, r6, r7, pc} +100006a0: 68b2 ldr r2, [r6, #8] +100006a2: 4c0d ldr r4, [pc, #52] @ (100006d8 ) +100006a4: f842 4025 str.w r4, [r2, r5, lsl #2] +100006a8: e7f0 b.n 1000068c +100006aa: 2400 movs r4, #0 +100006ac: eb04 0444 add.w r4, r4, r4, lsl #1 +100006b0: eb02 0284 add.w r2, r2, r4, lsl #2 +100006b4: 24ff movs r4, #255 @ 0xff +100006b6: 7194 strb r4, [r2, #6] +100006b8: f64b 5401 movw r4, #48385 @ 0xbd01 +100006bc: 8094 strh r4, [r2, #4] +100006be: e7e5 b.n 1000068c +100006c0: 2401 movs r4, #1 +100006c2: e7f3 b.n 100006ac +100006c4: 2402 movs r4, #2 +100006c6: e7f1 b.n 100006ac +100006c8: 200007b9 .word 0x200007b9 +100006cc: e000ed00 .word 0xe000ed00 +100006d0: 200005ac .word 0x200005ac +100006d4: 20000854 .word 0x20000854 +100006d8: 10000111 .word 0x10000111 + +100006dc : +100006dc: 4b01 ldr r3, [pc, #4] @ (100006e4 ) +100006de: 440b add r3, r1 +100006e0: 6003 str r3, [r0, #0] +100006e2: 4770 bx lr +100006e4: 200007b0 .word 0x200007b0 + +100006e8 : +100006e8: b570 push {r4, r5, r6, lr} +100006ea: 4c10 ldr r4, [pc, #64] @ (1000072c ) +100006ec: 4d10 ldr r5, [pc, #64] @ (10000730 ) +100006ee: 42ac cmp r4, r5 +100006f0: d20e bcs.n 10000710 +100006f2: 26ff movs r6, #255 @ 0xff +100006f4: 6823 ldr r3, [r4, #0] +100006f6: b163 cbz r3, 10000712 +100006f8: f7ff fe12 bl 10000320 +100006fc: 4601 mov r1, r0 +100006fe: 4620 mov r0, r4 +10000700: f7ff ffec bl 100006dc +10000704: 80a6 strh r6, [r4, #4] +10000706: f3bf 8f5f dmb sy +1000070a: 3408 adds r4, #8 +1000070c: 42ac cmp r4, r5 +1000070e: d3f1 bcc.n 100006f4 +10000710: bd70 pop {r4, r5, r6, pc} +10000712: f7ff fe05 bl 10000320 +10000716: 4601 mov r1, r0 +10000718: 4620 mov r0, r4 +1000071a: f7ff ffdf bl 100006dc +1000071e: 7126 strb r6, [r4, #4] +10000720: f3bf 8f5f dmb sy +10000724: 3408 adds r4, #8 +10000726: 42ac cmp r4, r5 +10000728: d3e4 bcc.n 100006f4 +1000072a: bd70 pop {r4, r5, r6, pc} +1000072c: 20000624 .word 0x20000624 +10000730: 2000062c .word 0x2000062c + +10000734 : +10000734: 4b0d ldr r3, [pc, #52] @ (1000076c ) +10000736: 681a ldr r2, [r3, #0] +10000738: f3ef 8110 mrs r1, PRIMASK +1000073c: b672 cpsid i +1000073e: e8d2 cfcf ldaexb ip, [r2] +10000742: 2001 movs r0, #1 +10000744: f1bc 0f00 cmp.w ip, #0 +10000748: d1f9 bne.n 1000073e +1000074a: e8c2 0f4c strexb ip, r0, [r2] +1000074e: f1bc 0f00 cmp.w ip, #0 +10000752: d1f4 bne.n 1000073e +10000754: f3bf 8f5f dmb sy +10000758: 2200 movs r2, #0 +1000075a: 681b ldr r3, [r3, #0] +1000075c: e8c3 2f8f stlb r2, [r3] +10000760: f381 8810 msr PRIMASK, r1 +10000764: bf40 sev +10000766: 2000 movs r0, #0 +10000768: 2100 movs r1, #0 +1000076a: 4770 bx lr +1000076c: 20000848 .word 0x20000848 + +10000770 : +10000770: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000774: ed2d 8b02 vpush {d8} +10000778: b085 sub sp, #20 +1000077a: f3ef 8305 mrs r3, IPSR +1000077e: b2db uxtb r3, r3 +10000780: 3b10 subs r3, #16 +10000782: 089a lsrs r2, r3, #2 +10000784: bf18 it ne +10000786: 2201 movne r2, #1 +10000788: f04f 0101 mov.w r1, #1 +1000078c: f003 0b03 and.w fp, r3, #3 +10000790: bf18 it ne +10000792: 4daf ldrne r5, [pc, #700] @ (10000a50 ) +10000794: 4baf ldr r3, [pc, #700] @ (10000a54 ) +10000796: bf08 it eq +10000798: 4daf ldreq r5, [pc, #700] @ (10000a58 ) +1000079a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000079e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +100007a2: fa01 f20b lsl.w r2, r1, fp +100007a6: f505 5341 add.w r3, r5, #12352 @ 0x3040 +100007aa: ed9f 8ba7 vldr d8, [pc, #668] @ 10000a48 +100007ae: 9201 str r2, [sp, #4] +100007b0: 605a str r2, [r3, #4] +100007b2: e02f b.n 10000814 +100007b4: 88b3 ldrh r3, [r6, #4] +100007b6: 041c lsls r4, r3, #16 +100007b8: f140 8093 bpl.w 100008e2 +100007bc: 79b3 ldrb r3, [r6, #6] +100007be: 2b00 cmp r3, #0 +100007c0: f040 80dd bne.w 1000097e +100007c4: f9b6 2008 ldrsh.w r2, [r6, #8] +100007c8: 2a00 cmp r2, #0 +100007ca: f2c0 811e blt.w 10000a0a +100007ce: 6973 ldr r3, [r6, #20] +100007d0: eb02 0242 add.w r2, r2, r2, lsl #1 +100007d4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100007d8: e9d3 4702 ldrd r4, r7, [r3, #8] +100007dc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100007e0: bf08 it eq +100007e2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100007e6: d00e beq.n 10000806 +100007e8: eb05 018b add.w r1, r5, fp, lsl #2 +100007ec: 6aab ldr r3, [r5, #40] @ 0x28 +100007ee: 690a ldr r2, [r1, #16] +100007f0: 1ad2 subs r2, r2, r3 +100007f2: 1ae3 subs r3, r4, r3 +100007f4: 4293 cmp r3, r2 +100007f6: d305 bcc.n 10000804 +100007f8: 2301 movs r3, #1 +100007fa: 6a2a ldr r2, [r5, #32] +100007fc: fa03 f30b lsl.w r3, r3, fp +10000800: 4213 tst r3, r2 +10000802: d100 bne.n 10000806 +10000804: 610c str r4, [r1, #16] +10000806: 4628 mov r0, r5 +10000808: f000 faca bl 10000da0 +1000080c: 42a0 cmp r0, r4 +1000080e: 41b9 sbcs r1, r7 +10000810: f2c0 80fb blt.w 10000a0a +10000814: f9b6 3008 ldrsh.w r3, [r6, #8] +10000818: 9a01 ldr r2, [sp, #4] +1000081a: 2b00 cmp r3, #0 +1000081c: 9300 str r3, [sp, #0] +1000081e: 63ea str r2, [r5, #60] @ 0x3c +10000820: dbc8 blt.n 100007b4 +10000822: f8d6 8014 ldr.w r8, [r6, #20] +10000826: eb03 0943 add.w r9, r3, r3, lsl #1 +1000082a: 4628 mov r0, r5 +1000082c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000830: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000834: f000 fab4 bl 10000da0 +10000838: 42a0 cmp r0, r4 +1000083a: eb71 010a sbcs.w r1, r1, sl +1000083e: dbb9 blt.n 100007b4 +10000840: f1ba 0f00 cmp.w sl, #0 +10000844: f2c0 80c3 blt.w 100009ce +10000848: e9d7 3104 ldrd r3, r1, [r7, #16] +1000084c: 4a83 ldr r2, [pc, #524] @ (10000a5c ) +1000084e: 4293 cmp r3, r2 +10000850: f000 80ed beq.w 10000a2e +10000854: 887a ldrh r2, [r7, #2] +10000856: f9b6 0008 ldrsh.w r0, [r6, #8] +1000085a: b292 uxth r2, r2 +1000085c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000860: 4798 blx r3 +10000862: 4602 mov r2, r0 +10000864: 460b mov r3, r1 +10000866: ea52 0103 orrs.w r1, r2, r3 +1000086a: f000 80b0 beq.w 100009ce +1000086e: 2b00 cmp r3, #0 +10000870: f280 80d1 bge.w 10000a16 +10000874: ebb4 0e02 subs.w lr, r4, r2 +10000878: eb6a 0a03 sbc.w sl, sl, r3 +1000087c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000880: e9c7 ea02 strd lr, sl, [r7, #8] +10000884: 2b00 cmp r3, #0 +10000886: db95 blt.n 100007b4 +10000888: 6971 ldr r1, [r6, #20] +1000088a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000088e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000892: e9d2 7002 ldrd r7, r0, [r2, #8] +10000896: 45be cmp lr, r7 +10000898: eb7a 0c00 sbcs.w ip, sl, r0 +1000089c: ea4f 0243 mov.w r2, r3, lsl #1 +100008a0: db88 blt.n 100007b4 +100008a2: 46b4 mov ip, r6 +100008a4: f82c 3f08 strh.w r3, [ip, #8]! +100008a8: e006 b.n 100008b8 +100008aa: eb03 0043 add.w r0, r3, r3, lsl #1 +100008ae: eb01 00c0 add.w r0, r1, r0, lsl #3 +100008b2: 005a lsls r2, r3, #1 +100008b4: e9d0 7002 ldrd r7, r0, [r0, #8] +100008b8: 45be cmp lr, r7 +100008ba: 441a add r2, r3 +100008bc: eb7a 0000 sbcs.w r0, sl, r0 +100008c0: eb01 04c2 add.w r4, r1, r2, lsl #3 +100008c4: db04 blt.n 100008d0 +100008c6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +100008ca: 46a4 mov ip, r4 +100008cc: 2b00 cmp r3, #0 +100008ce: daec bge.n 100008aa +100008d0: f828 3039 strh.w r3, [r8, r9, lsl #3] +100008d4: 9b00 ldr r3, [sp, #0] +100008d6: f8ac 3000 strh.w r3, [ip] +100008da: 88b3 ldrh r3, [r6, #4] +100008dc: 041c lsls r4, r3, #16 +100008de: f53f af6d bmi.w 100007bc +100008e2: 6933 ldr r3, [r6, #16] +100008e4: f3ef 8210 mrs r2, PRIMASK +100008e8: b672 cpsid i +100008ea: e8d3 0fcf ldaexb r0, [r3] +100008ee: 2101 movs r1, #1 +100008f0: 2800 cmp r0, #0 +100008f2: d1fa bne.n 100008ea +100008f4: e8c3 1f40 strexb r0, r1, [r3] +100008f8: 2800 cmp r0, #0 +100008fa: d1f6 bne.n 100008ea +100008fc: f3bf 8f5f dmb sy +10000900: f64f 74ff movw r4, #65535 @ 0xffff +10000904: 88b0 ldrh r0, [r6, #4] +10000906: 2300 movs r3, #0 +10000908: 6931 ldr r1, [r6, #16] +1000090a: b200 sxth r0, r0 +1000090c: 80b4 strh r4, [r6, #4] +1000090e: e8c1 3f8f stlb r3, [r1] +10000912: f382 8810 msr PRIMASK, r2 +10000916: 4298 cmp r0, r3 +10000918: f6ff af50 blt.w 100007bc +1000091c: 4607 mov r7, r0 +1000091e: 46a9 mov r9, r5 +10000920: 6974 ldr r4, [r6, #20] +10000922: f106 0808 add.w r8, r6, #8 +10000926: eb07 0e47 add.w lr, r7, r7, lsl #1 +1000092a: eb04 03ce add.w r3, r4, lr, lsl #3 +1000092e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000932: f9b6 3008 ldrsh.w r3, [r6, #8] +10000936: 46c4 mov ip, r8 +10000938: 2b00 cmp r3, #0 +1000093a: db13 blt.n 10000964 +1000093c: 46b2 mov sl, r6 +1000093e: 9700 str r7, [sp, #0] +10000940: e004 b.n 1000094c +10000942: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000946: 4694 mov ip, r2 +10000948: 2b00 cmp r3, #0 +1000094a: db09 blt.n 10000960 +1000094c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000950: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000954: e9d2 7102 ldrd r7, r1, [r2, #8] +10000958: 42bd cmp r5, r7 +1000095a: eb70 0101 sbcs.w r1, r0, r1 +1000095e: daf0 bge.n 10000942 +10000960: 4656 mov r6, sl +10000962: 9f00 ldr r7, [sp, #0] +10000964: f8ac 7000 strh.w r7, [ip] +10000968: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000096c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000970: 2f00 cmp r7, #0 +10000972: dad8 bge.n 10000926 +10000974: 79b3 ldrb r3, [r6, #6] +10000976: 464d mov r5, r9 +10000978: 2b00 cmp r3, #0 +1000097a: f43f af23 beq.w 100007c4 +1000097e: 2300 movs r3, #0 +10000980: 71b3 strb r3, [r6, #6] +10000982: f9b6 3008 ldrsh.w r3, [r6, #8] +10000986: f106 0808 add.w r8, r6, #8 +1000098a: 1c58 adds r0, r3, #1 +1000098c: d03d beq.n 10000a0a +1000098e: 461a mov r2, r3 +10000990: 6977 ldr r7, [r6, #20] +10000992: e003 b.n 1000099c +10000994: 4680 mov r8, r0 +10000996: 1c59 adds r1, r3, #1 +10000998: f43f af16 beq.w 100007c8 +1000099c: eb03 0143 add.w r1, r3, r3, lsl #1 +100009a0: eb07 00c1 add.w r0, r7, r1, lsl #3 +100009a4: f8b0 c002 ldrh.w ip, [r0, #2] +100009a8: 461c mov r4, r3 +100009aa: f41c 4f00 tst.w ip, #32768 @ 0x8000 +100009ae: 469e mov lr, r3 +100009b0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +100009b4: d0ee beq.n 10000994 +100009b6: 4294 cmp r4, r2 +100009b8: ed80 8b02 vstr d8, [r0, #8] +100009bc: d005 beq.n 100009ca +100009be: f8a8 3000 strh.w r3, [r8] +100009c2: 8932 ldrh r2, [r6, #8] +100009c4: f827 2031 strh.w r2, [r7, r1, lsl #3] +100009c8: 8134 strh r4, [r6, #8] +100009ca: 4672 mov r2, lr +100009cc: e7e3 b.n 10000996 +100009ce: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +100009d2: 8133 strh r3, [r6, #8] +100009d4: 6933 ldr r3, [r6, #16] +100009d6: f3ef 8210 mrs r2, PRIMASK +100009da: b672 cpsid i +100009dc: e8d3 0fcf ldaexb r0, [r3] +100009e0: 2101 movs r1, #1 +100009e2: 2800 cmp r0, #0 +100009e4: d1fa bne.n 100009dc +100009e6: e8c3 1f40 strexb r0, r1, [r3] +100009ea: 2800 cmp r0, #0 +100009ec: d1f6 bne.n 100009dc +100009ee: f3bf 8f5f dmb sy +100009f2: 8873 ldrh r3, [r6, #2] +100009f4: 6931 ldr r1, [r6, #16] +100009f6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100009fa: 9b00 ldr r3, [sp, #0] +100009fc: 8073 strh r3, [r6, #2] +100009fe: 2300 movs r3, #0 +10000a00: e8c1 3f8f stlb r3, [r1] +10000a04: f382 8810 msr PRIMASK, r2 +10000a08: e6d4 b.n 100007b4 +10000a0a: bf40 sev +10000a0c: b005 add sp, #20 +10000a0e: ecbd 8b02 vpop {d8} +10000a12: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000a16: 4628 mov r0, r5 +10000a18: e9cd 2302 strd r2, r3, [sp, #8] +10000a1c: f000 f9c0 bl 10000da0 +10000a20: 9a02 ldr r2, [sp, #8] +10000a22: 9b03 ldr r3, [sp, #12] +10000a24: eb10 0e02 adds.w lr, r0, r2 +10000a28: eb43 0a01 adc.w sl, r3, r1 +10000a2c: e726 b.n 1000087c +10000a2e: 4608 mov r0, r1 +10000a30: 690b ldr r3, [r1, #16] +10000a32: 9102 str r1, [sp, #8] +10000a34: 4798 blx r3 +10000a36: 2800 cmp r0, #0 +10000a38: d0c9 beq.n 100009ce +10000a3a: 9902 ldr r1, [sp, #8] +10000a3c: e9d1 2300 ldrd r2, r3, [r1] +10000a40: e711 b.n 10000866 +10000a42: bf00 nop +10000a44: f3af 8000 nop.w +10000a48: ffffffff .word 0xffffffff +10000a4c: ffffffff .word 0xffffffff +10000a50: 400b8000 .word 0x400b8000 +10000a54: 20000828 .word 0x20000828 +10000a58: 400b0000 .word 0x400b0000 +10000a5c: 10000771 .word 0x10000771 + +10000a60 : +10000a60: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a64: 4c36 ldr r4, [pc, #216] @ (10000b40 ) +10000a66: 6925 ldr r5, [r4, #16] +10000a68: b12d cbz r5, 10000a76 +10000a6a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a6e: 210a movs r1, #10 +10000a70: 4834 ldr r0, [pc, #208] @ (10000b44 ) +10000a72: f7ff be33 b.w 100006dc +10000a76: f8df 80e4 ldr.w r8, [pc, #228] @ 10000b5c +10000a7a: 2103 movs r1, #3 +10000a7c: 4640 mov r0, r8 +10000a7e: f000 f97d bl 10000d7c +10000a82: 2603 movs r6, #3 +10000a84: f8c4 800c str.w r8, [r4, #12] +10000a88: f7ff fc4a bl 10000320 +10000a8c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000a90: 4b2d ldr r3, [pc, #180] @ (10000b48 ) +10000a92: 7026 strb r6, [r4, #0] +10000a94: 4403 add r3, r0 +10000a96: 6123 str r3, [r4, #16] +10000a98: f8dc 3000 ldr.w r3, [ip] +10000a9c: 210f movs r1, #15 +10000a9e: 7063 strb r3, [r4, #1] +10000aa0: 6963 ldr r3, [r4, #20] +10000aa2: 8061 strh r1, [r4, #2] +10000aa4: 831d strh r5, [r3, #24] +10000aa6: f04f 0504 mov.w r5, #4 +10000aaa: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000aae: f04f 0505 mov.w r5, #5 +10000ab2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000ab6: f04f 0506 mov.w r5, #6 +10000aba: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000abe: f04f 0507 mov.w r5, #7 +10000ac2: 210e movs r1, #14 +10000ac4: f64f 72ff movw r2, #65535 @ 0xffff +10000ac8: 2708 movs r7, #8 +10000aca: f04f 0e0a mov.w lr, #10 +10000ace: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000ad2: f04f 0901 mov.w r9, #1 +10000ad6: f04f 0c0c mov.w ip, #12 +10000ada: f04f 0b02 mov.w fp, #2 +10000ade: f04f 0a09 mov.w sl, #9 +10000ae2: 200d movs r0, #13 +10000ae4: f04f 050b mov.w r5, #11 +10000ae8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000aec: 4917 ldr r1, [pc, #92] @ (10000b4c ) +10000aee: 80a2 strh r2, [r4, #4] +10000af0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000af4: 60a1 str r1, [r4, #8] +10000af6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000afa: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000afe: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000b02: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000b06: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000b0a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000b0e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000b12: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000b16: 801a strh r2, [r3, #0] +10000b18: 4b0d ldr r3, [pc, #52] @ (10000b50 ) +10000b1a: 4630 mov r0, r6 +10000b1c: f8c8 7020 str.w r7, [r8, #32] +10000b20: 490c ldr r1, [pc, #48] @ (10000b54 ) +10000b22: 60dc str r4, [r3, #12] +10000b24: f7ff fc52 bl 100003cc +10000b28: 4649 mov r1, r9 +10000b2a: 4630 mov r0, r6 +10000b2c: f7ff fc38 bl 100003a0 +10000b30: 4b09 ldr r3, [pc, #36] @ (10000b58 ) +10000b32: 210a movs r1, #10 +10000b34: 641f str r7, [r3, #64] @ 0x40 +10000b36: 4803 ldr r0, [pc, #12] @ (10000b44 ) +10000b38: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b3c: f7ff bdce b.w 100006dc +10000b40: 200005f4 .word 0x200005f4 +10000b44: 20000848 .word 0x20000848 +10000b48: 200007b0 .word 0x200007b0 +10000b4c: 0010ffff .word 0x0010ffff +10000b50: 20000828 .word 0x20000828 +10000b54: 10000771 .word 0x10000771 +10000b58: 400b2000 .word 0x400b2000 +10000b5c: 400b0000 .word 0x400b0000 + +10000b60 : +10000b60: 4601 mov r1, r0 +10000b62: b5f0 push {r4, r5, r6, r7, lr} +10000b64: 6900 ldr r0, [r0, #16] +10000b66: f3ef 8710 mrs r7, PRIMASK +10000b6a: b672 cpsid i +10000b6c: e8d0 5fcf ldaexb r5, [r0] +10000b70: 2401 movs r4, #1 +10000b72: 2d00 cmp r5, #0 +10000b74: d1fa bne.n 10000b6c +10000b76: e8c0 4f45 strexb r5, r4, [r0] +10000b7a: 2d00 cmp r5, #0 +10000b7c: d1f6 bne.n 10000b6c +10000b7e: f3bf 8f5f dmb sy +10000b82: f9b1 e002 ldrsh.w lr, [r1, #2] +10000b86: 694c ldr r4, [r1, #20] +10000b88: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000b8c: f1be 0f00 cmp.w lr, #0 +10000b90: ea4f 05cc mov.w r5, ip, lsl #3 +10000b94: 6908 ldr r0, [r1, #16] +10000b96: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000b9a: db3c blt.n 10000c16 +10000b9c: 5b66 ldrh r6, [r4, r5] +10000b9e: 804e strh r6, [r1, #2] +10000ba0: 2600 movs r6, #0 +10000ba2: e8c0 6f8f stlb r6, [r0] +10000ba6: f387 8810 msr PRIMASK, r7 +10000baa: f8bc 0002 ldrh.w r0, [ip, #2] +10000bae: e9cc 2302 strd r2, r3, [ip, #8] +10000bb2: 3001 adds r0, #1 +10000bb4: f3c0 000e ubfx r0, r0, #0, #15 +10000bb8: 2801 cmp r0, #1 +10000bba: bf38 it cc +10000bbc: 2001 movcc r0, #1 +10000bbe: 9b05 ldr r3, [sp, #20] +10000bc0: f8ac 0002 strh.w r0, [ip, #2] +10000bc4: f8cc 3010 str.w r3, [ip, #16] +10000bc8: 9b06 ldr r3, [sp, #24] +10000bca: ea40 400e orr.w r0, r0, lr, lsl #16 +10000bce: f8cc 3014 str.w r3, [ip, #20] +10000bd2: 690b ldr r3, [r1, #16] +10000bd4: f3ef 8210 mrs r2, PRIMASK +10000bd8: b672 cpsid i +10000bda: e8d3 cfcf ldaexb ip, [r3] +10000bde: 2701 movs r7, #1 +10000be0: f1bc 0f00 cmp.w ip, #0 +10000be4: d1f9 bne.n 10000bda +10000be6: e8c3 7f4c strexb ip, r7, [r3] +10000bea: f1bc 0f00 cmp.w ip, #0 +10000bee: d1f4 bne.n 10000bda +10000bf0: f3bf 8f5f dmb sy +10000bf4: 888b ldrh r3, [r1, #4] +10000bf6: 5363 strh r3, [r4, r5] +10000bf8: f8a1 e004 strh.w lr, [r1, #4] +10000bfc: 690b ldr r3, [r1, #16] +10000bfe: e8c3 6f8f stlb r6, [r3] +10000c02: f382 8810 msr PRIMASK, r2 +10000c06: 2201 movs r2, #1 +10000c08: 68cb ldr r3, [r1, #12] +10000c0a: 7809 ldrb r1, [r1, #0] +10000c0c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000c10: 408a lsls r2, r1 +10000c12: 605a str r2, [r3, #4] +10000c14: bdf0 pop {r4, r5, r6, r7, pc} +10000c16: 2300 movs r3, #0 +10000c18: e8c0 3f8f stlb r3, [r0] +10000c1c: f387 8810 msr PRIMASK, r7 +10000c20: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000c24: bdf0 pop {r4, r5, r6, r7, pc} +10000c26: bf00 nop + +10000c28 : +10000c28: 4603 mov r3, r0 +10000c2a: 8940 ldrh r0, [r0, #10] +10000c2c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000c30: dd37 ble.n 10000ca2 +10000c32: 6958 ldr r0, [r3, #20] +10000c34: 140a asrs r2, r1, #16 +10000c36: eb02 0242 add.w r2, r2, r2, lsl #1 +10000c3a: b510 push {r4, lr} +10000c3c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000c40: 691c ldr r4, [r3, #16] +10000c42: f3ef 8c10 mrs ip, PRIMASK +10000c46: b672 cpsid i +10000c48: e8d4 efcf ldaexb lr, [r4] +10000c4c: 2201 movs r2, #1 +10000c4e: f1be 0f00 cmp.w lr, #0 +10000c52: d1f9 bne.n 10000c48 +10000c54: e8c4 2f4e strexb lr, r2, [r4] +10000c58: f1be 0f00 cmp.w lr, #0 +10000c5c: d1f4 bne.n 10000c48 +10000c5e: f3bf 8f5f dmb sy +10000c62: 8842 ldrh r2, [r0, #2] +10000c64: b289 uxth r1, r1 +10000c66: b292 uxth r2, r2 +10000c68: 428a cmp r2, r1 +10000c6a: d007 beq.n 10000c7c +10000c6c: 2200 movs r2, #0 +10000c6e: 691b ldr r3, [r3, #16] +10000c70: e8c3 2f8f stlb r2, [r3] +10000c74: f38c 8810 msr PRIMASK, ip +10000c78: 2000 movs r0, #0 +10000c7a: bd10 pop {r4, pc} +10000c7c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000c80: 8042 strh r2, [r0, #2] +10000c82: 2101 movs r1, #1 +10000c84: 2200 movs r2, #0 +10000c86: 6918 ldr r0, [r3, #16] +10000c88: 7199 strb r1, [r3, #6] +10000c8a: e8c0 2f8f stlb r2, [r0] +10000c8e: f38c 8810 msr PRIMASK, ip +10000c92: 781c ldrb r4, [r3, #0] +10000c94: 68da ldr r2, [r3, #12] +10000c96: 4608 mov r0, r1 +10000c98: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000c9c: 40a1 lsls r1, r4 +10000c9e: 6059 str r1, [r3, #4] +10000ca0: bd10 pop {r4, pc} +10000ca2: 2000 movs r0, #0 +10000ca4: 4770 bx lr +10000ca6: bf00 nop + +10000ca8 : +10000ca8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000cac: 4606 mov r6, r0 +10000cae: 460d mov r5, r1 +10000cb0: b083 sub sp, #12 +10000cb2: f3ef 8405 mrs r4, IPSR +10000cb6: b2e4 uxtb r4, r4 +10000cb8: b13c cbz r4, 10000cca +10000cba: 4b2d ldr r3, [pc, #180] @ (10000d70 ) +10000cbc: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cbe: 42aa cmp r2, r5 +10000cc0: d21c bcs.n 10000cfc +10000cc2: 2000 movs r0, #0 +10000cc4: b003 add sp, #12 +10000cc6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000cca: 4f2a ldr r7, [pc, #168] @ (10000d74 ) +10000ccc: f8d7 900c ldr.w r9, [r7, #12] +10000cd0: f897 8000 ldrb.w r8, [r7] +10000cd4: 4648 mov r0, r9 +10000cd6: f000 f863 bl 10000da0 +10000cda: f108 0804 add.w r8, r8, #4 +10000cde: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000ce2: 1a1b subs r3, r3, r0 +10000ce4: 1a30 subs r0, r6, r0 +10000ce6: eb65 0101 sbc.w r1, r5, r1 +10000cea: 4298 cmp r0, r3 +10000cec: f171 0100 sbcs.w r1, r1, #0 +10000cf0: db10 blt.n 10000d14 +10000cf2: bf20 wfe +10000cf4: 4b1e ldr r3, [pc, #120] @ (10000d70 ) +10000cf6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000cf8: 42aa cmp r2, r5 +10000cfa: d3e2 bcc.n 10000cc2 +10000cfc: bf14 ite ne +10000cfe: 2401 movne r4, #1 +10000d00: 2400 moveq r4, #0 +10000d02: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d04: 42b3 cmp r3, r6 +10000d06: bf34 ite cc +10000d08: 4620 movcc r0, r4 +10000d0a: f044 0001 orrcs.w r0, r4, #1 +10000d0e: b003 add sp, #12 +10000d10: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d14: f000 f84c bl 10000db0 +10000d18: 4286 cmp r6, r0 +10000d1a: eb65 0101 sbc.w r1, r5, r1 +10000d1e: 2900 cmp r1, #0 +10000d20: db14 blt.n 10000d4c +10000d22: 4b15 ldr r3, [pc, #84] @ (10000d78 ) +10000d24: 4638 mov r0, r7 +10000d26: e9cd 3400 strd r3, r4, [sp] +10000d2a: 4632 mov r2, r6 +10000d2c: 462b mov r3, r5 +10000d2e: f7ff ff17 bl 10000b60 +10000d32: 1e01 subs r1, r0, #0 +10000d34: dd0a ble.n 10000d4c +10000d36: 4b0e ldr r3, [pc, #56] @ (10000d70 ) +10000d38: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d3a: 42aa cmp r2, r5 +10000d3c: d316 bcc.n 10000d6c +10000d3e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d40: 42b3 cmp r3, r6 +10000d42: d311 bcc.n 10000d68 +10000d44: 480b ldr r0, [pc, #44] @ (10000d74 ) +10000d46: f7ff ff6f bl 10000c28 +10000d4a: e7b6 b.n 10000cba +10000d4c: 4b08 ldr r3, [pc, #32] @ (10000d70 ) +10000d4e: 6a5c ldr r4, [r3, #36] @ 0x24 +10000d50: 42ac cmp r4, r5 +10000d52: d3b6 bcc.n 10000cc2 +10000d54: 1b64 subs r4, r4, r5 +10000d56: bf18 it ne +10000d58: 2401 movne r4, #1 +10000d5a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000d5c: 42b3 cmp r3, r6 +10000d5e: bf34 ite cc +10000d60: 4620 movcc r0, r4 +10000d62: f044 0001 orrcs.w r0, r4, #1 +10000d66: e7ad b.n 10000cc4 +10000d68: 42aa cmp r2, r5 +10000d6a: d1eb bne.n 10000d44 +10000d6c: bf20 wfe +10000d6e: e7e9 b.n 10000d44 +10000d70: 400b0000 .word 0x400b0000 +10000d74: 200005f4 .word 0x200005f4 +10000d78: 10000735 .word 0x10000735 + +10000d7c : +10000d7c: b410 push {r4} +10000d7e: 4b05 ldr r3, [pc, #20] @ (10000d94 ) +10000d80: 4c05 ldr r4, [pc, #20] @ (10000d98 ) +10000d82: 4a06 ldr r2, [pc, #24] @ (10000d9c ) +10000d84: 42a0 cmp r0, r4 +10000d86: bf14 ite ne +10000d88: 4618 movne r0, r3 +10000d8a: 1c58 addeq r0, r3, #1 +10000d8c: f85d 4b04 ldr.w r4, [sp], #4 +10000d90: f7ff ba9a b.w 100002c8 +10000d94: 200007d8 .word 0x200007d8 +10000d98: 400b8000 .word 0x400b8000 +10000d9c: 100034d4 .word 0x100034d4 + +10000da0 : +10000da0: 4603 mov r3, r0 +10000da2: 6a41 ldr r1, [r0, #36] @ 0x24 +10000da4: 460a mov r2, r1 +10000da6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000da8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000daa: 428a cmp r2, r1 +10000dac: d1fa bne.n 10000da4 +10000dae: 4770 bx lr + +10000db0 : +10000db0: 4b03 ldr r3, [pc, #12] @ (10000dc0 ) +10000db2: 6a59 ldr r1, [r3, #36] @ 0x24 +10000db4: 460a mov r2, r1 +10000db6: 6a98 ldr r0, [r3, #40] @ 0x28 +10000db8: 6a59 ldr r1, [r3, #36] @ 0x24 +10000dba: 4291 cmp r1, r2 +10000dbc: d1fa bne.n 10000db4 +10000dbe: 4770 bx lr +10000dc0: 400b0000 .word 0x400b0000 + +10000dc4 : +10000dc4: b430 push {r4, r5} +10000dc6: 4a15 ldr r2, [pc, #84] @ (10000e1c ) +10000dc8: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dca: 469c mov ip, r3 +10000dcc: 6a94 ldr r4, [r2, #40] @ 0x28 +10000dce: 6a53 ldr r3, [r2, #36] @ 0x24 +10000dd0: 4563 cmp r3, ip +10000dd2: d1fa bne.n 10000dca +10000dd4: 1902 adds r2, r0, r4 +10000dd6: 4159 adcs r1, r3 +10000dd8: f04f 0500 mov.w r5, #0 +10000ddc: bf28 it cs +10000dde: 2501 movcs r5, #1 +10000de0: 4b0e ldr r3, [pc, #56] @ (10000e1c ) +10000de2: 6a5b ldr r3, [r3, #36] @ 0x24 +10000de4: b1b5 cbz r5, 10000e14 +10000de6: 1c5a adds r2, r3, #1 +10000de8: bf08 it eq +10000dea: 461a moveq r2, r3 +10000dec: d008 beq.n 10000e00 +10000dee: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000df2: 460a mov r2, r1 +10000df4: 4809 ldr r0, [pc, #36] @ (10000e1c ) +10000df6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000df8: 428b cmp r3, r1 +10000dfa: d3fc bcc.n 10000df6 +10000dfc: 428b cmp r3, r1 +10000dfe: d107 bne.n 10000e10 +10000e00: 4906 ldr r1, [pc, #24] @ (10000e1c ) +10000e02: e002 b.n 10000e0a +10000e04: 6a48 ldr r0, [r1, #36] @ 0x24 +10000e06: 4298 cmp r0, r3 +10000e08: d102 bne.n 10000e10 +10000e0a: 6a88 ldr r0, [r1, #40] @ 0x28 +10000e0c: 4290 cmp r0, r2 +10000e0e: d3f9 bcc.n 10000e04 +10000e10: bc30 pop {r4, r5} +10000e12: 4770 bx lr +10000e14: 4299 cmp r1, r3 +10000e16: d8ed bhi.n 10000df4 +10000e18: e7f0 b.n 10000dfc +10000e1a: bf00 nop +10000e1c: 400b0000 .word 0x400b0000 + +10000e20 : +10000e20: b5f8 push {r3, r4, r5, r6, r7, lr} +10000e22: 4605 mov r5, r0 +10000e24: 2006 movs r0, #6 +10000e26: 460e mov r6, r1 +10000e28: f000 f8e4 bl 10000ff4 +10000e2c: 2800 cmp r0, #0 +10000e2e: d042 beq.n 10000eb6 +10000e30: 4a35 ldr r2, [pc, #212] @ (10000f08 ) +10000e32: 4836 ldr r0, [pc, #216] @ (10000f0c ) +10000e34: 4295 cmp r5, r2 +10000e36: bf14 ite ne +10000e38: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000e3c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000e40: 4b33 ldr r3, [pc, #204] @ (10000f10 ) +10000e42: 4934 ldr r1, [pc, #208] @ (10000f14 ) +10000e44: 6002 str r2, [r0, #0] +10000e46: 601a str r2, [r3, #0] +10000e48: 688c ldr r4, [r1, #8] +10000e4a: ea32 0404 bics.w r4, r2, r4 +10000e4e: d1fb bne.n 10000e48 +10000e50: 4b2d ldr r3, [pc, #180] @ (10000f08 ) +10000e52: f44f 7180 mov.w r1, #256 @ 0x100 +10000e56: 1aeb subs r3, r5, r3 +10000e58: fab3 f383 clz r3, r3 +10000e5c: 4a2e ldr r2, [pc, #184] @ (10000f18 ) +10000e5e: 095b lsrs r3, r3, #5 +10000e60: 2006 movs r0, #6 +10000e62: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000e66: f000 f8c5 bl 10000ff4 +10000e6a: 00c3 lsls r3, r0, #3 +10000e6c: fbb3 f3f6 udiv r3, r3, r6 +10000e70: 3301 adds r3, #1 +10000e72: 09da lsrs r2, r3, #7 +10000e74: d120 bne.n 10000eb8 +10000e76: 2640 movs r6, #64 @ 0x40 +10000e78: 2101 movs r1, #1 +10000e7a: 6269 str r1, [r5, #36] @ 0x24 +10000e7c: 62aa str r2, [r5, #40] @ 0x28 +10000e7e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000e80: 07fb lsls r3, r7, #31 +10000e82: d422 bmi.n 10000eca +10000e84: 462b mov r3, r5 +10000e86: 2200 movs r2, #0 +10000e88: f853 1f2c ldr.w r1, [r3, #44]! +10000e8c: 2006 movs r0, #6 +10000e8e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000e92: 6022 str r2, [r4, #0] +10000e94: 632f str r7, [r5, #48] @ 0x30 +10000e96: f000 f8ad bl 10000ff4 +10000e9a: f240 3101 movw r1, #769 @ 0x301 +10000e9e: 2203 movs r2, #3 +10000ea0: 0080 lsls r0, r0, #2 +10000ea2: fbb0 f0f6 udiv r0, r0, r6 +10000ea6: 6aeb ldr r3, [r5, #44] @ 0x2c +10000ea8: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000eac: f003 037e and.w r3, r3, #126 @ 0x7e +10000eb0: 6023 str r3, [r4, #0] +10000eb2: 6329 str r1, [r5, #48] @ 0x30 +10000eb4: 64aa str r2, [r5, #72] @ 0x48 +10000eb6: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000eb8: f64f 71fe movw r1, #65534 @ 0xfffe +10000ebc: 428a cmp r2, r1 +10000ebe: d91b bls.n 10000ef8 +10000ec0: 4622 mov r2, r4 +10000ec2: f64f 71ff movw r1, #65535 @ 0xffff +10000ec6: 4e15 ldr r6, [pc, #84] @ (10000f1c ) +10000ec8: e7d7 b.n 10000e7a +10000eca: f240 3201 movw r2, #769 @ 0x301 +10000ece: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000ed2: 631a str r2, [r3, #48] @ 0x30 +10000ed4: 6a6b ldr r3, [r5, #36] @ 0x24 +10000ed6: 6aac ldr r4, [r5, #40] @ 0x28 +10000ed8: 2006 movs r0, #6 +10000eda: eb04 1483 add.w r4, r4, r3, lsl #6 +10000ede: f000 f889 bl 10000ff4 +10000ee2: 4b0f ldr r3, [pc, #60] @ (10000f20 ) +10000ee4: 02a4 lsls r4, r4, #10 +10000ee6: fba3 2300 umull r2, r3, r3, r0 +10000eea: 0adb lsrs r3, r3, #11 +10000eec: 2100 movs r1, #0 +10000eee: fbb4 f0f3 udiv r0, r4, r3 +10000ef2: f7ff ff67 bl 10000dc4 +10000ef6: e7c5 b.n 10000e84 +10000ef8: f3c3 0345 ubfx r3, r3, #1, #6 +10000efc: 4611 mov r1, r2 +10000efe: eb03 1682 add.w r6, r3, r2, lsl #6 +10000f02: 461a mov r2, r3 +10000f04: e7b9 b.n 10000e7a +10000f06: bf00 nop +10000f08: 40078000 .word 0x40078000 +10000f0c: 40022000 .word 0x40022000 +10000f10: 40023000 .word 0x40023000 +10000f14: 40020000 .word 0x40020000 +10000f18: 2000084c .word 0x2000084c +10000f1c: 003fffc0 .word 0x003fffc0 +10000f20: 8f2b7b75 .word 0x8f2b7b75 + +10000f24 : +10000f24: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000f28: ea4f 0c8c mov.w ip, ip, lsl #2 +10000f2c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000f30: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000f34: b5f0 push {r4, r5, r6, r7, lr} +10000f36: 4616 mov r6, r2 +10000f38: f8dc 2004 ldr.w r2, [ip, #4] +10000f3c: 1f05 subs r5, r0, #4 +10000f3e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000f42: bf38 it cc +10000f44: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000f48: b2ed uxtb r5, r5 +10000f4a: bf38 it cc +10000f4c: f8cc 2004 strcc.w r2, [ip, #4] +10000f50: 2d01 cmp r5, #1 +10000f52: d92a bls.n 10000faa +10000f54: f44f 6700 mov.w r7, #2048 @ 0x800 +10000f58: 4c25 ldr r4, [pc, #148] @ (10000ff0 ) +10000f5a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000f5e: 6017 str r7, [r2, #0] +10000f60: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000f64: b9b2 cbnz r2, 10000f94 +10000f66: f8dc 2000 ldr.w r2, [ip] +10000f6a: 2d01 cmp r5, #1 +10000f6c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000f70: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000f74: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000f78: 6032 str r2, [r6, #0] +10000f7a: d92a bls.n 10000fd2 +10000f7c: f44f 6100 mov.w r1, #2048 @ 0x800 +10000f80: f844 3020 str.w r3, [r4, r0, lsl #2] +10000f84: f44f 3380 mov.w r3, #65536 @ 0x10000 +10000f88: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10000f8c: 6011 str r1, [r2, #0] +10000f8e: f8cc 3004 str.w r3, [ip, #4] +10000f92: bdf0 pop {r4, r5, r6, r7, pc} +10000f94: 6967 ldr r7, [r4, #20] +10000f96: fbb7 fef2 udiv lr, r7, r2 +10000f9a: f10e 0e01 add.w lr, lr, #1 +10000f9e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10000fa2: f1be 0e03 subs.w lr, lr, #3 +10000fa6: d2fc bcs.n 10000fa2 +10000fa8: e7dd b.n 10000f66 +10000faa: 2901 cmp r1, #1 +10000fac: d1d2 bne.n 10000f54 +10000fae: 2403 movs r4, #3 +10000fb0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10000fb4: 6014 str r4, [r2, #0] +10000fb6: f8dc 2008 ldr.w r2, [ip, #8] +10000fba: 07d2 lsls r2, r2, #31 +10000fbc: d5fb bpl.n 10000fb6 +10000fbe: f8dc 2000 ldr.w r2, [ip] +10000fc2: 4c0b ldr r4, [pc, #44] @ (10000ff0 ) +10000fc4: ea82 1246 eor.w r2, r2, r6, lsl #5 +10000fc8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10000fcc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10000fd0: 6032 str r2, [r6, #0] +10000fd2: 2201 movs r2, #1 +10000fd4: f8dc 5000 ldr.w r5, [ip] +10000fd8: 404d eors r5, r1 +10000fda: f005 0503 and.w r5, r5, #3 +10000fde: 6035 str r5, [r6, #0] +10000fe0: fa02 f101 lsl.w r1, r2, r1 +10000fe4: f8dc 2008 ldr.w r2, [ip, #8] +10000fe8: 420a tst r2, r1 +10000fea: d0fb beq.n 10000fe4 +10000fec: e7c6 b.n 10000f7c +10000fee: bf00 nop +10000ff0: 200007dc .word 0x200007dc + +10000ff4 : +10000ff4: 4b01 ldr r3, [pc, #4] @ (10000ffc ) +10000ff6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10000ffa: 4770 bx lr +10000ffc: 200007dc .word 0x200007dc + +10001000 : +10001000: b470 push {r4, r5, r6} +10001002: 9d03 ldr r5, [sp, #12] +10001004: 6804 ldr r4, [r0, #0] +10001006: 032d lsls r5, r5, #12 +10001008: ea45 4503 orr.w r5, r5, r3, lsl #16 +1000100c: 4b1b ldr r3, [pc, #108] @ (1000107c ) +1000100e: 2c00 cmp r4, #0 +10001010: fbb3 f3f1 udiv r3, r3, r1 +10001014: fbb2 f6f3 udiv r6, r2, r3 +10001018: db1f blt.n 1000105a +1000101a: 4a19 ldr r2, [pc, #100] @ (10001080 ) +1000101c: 4b19 ldr r3, [pc, #100] @ (10001084 ) +1000101e: 4290 cmp r0, r2 +10001020: bf14 ite ne +10001022: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001026: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000102a: 4c17 ldr r4, [pc, #92] @ (10001088 ) +1000102c: 601a str r2, [r3, #0] +1000102e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001032: 601a str r2, [r3, #0] +10001034: 68a3 ldr r3, [r4, #8] +10001036: ea32 0303 bics.w r3, r2, r3 +1000103a: d1fb bne.n 10001034 +1000103c: 2221 movs r2, #33 @ 0x21 +1000103e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001042: 3304 adds r3, #4 +10001044: 6001 str r1, [r0, #0] +10001046: 6086 str r6, [r0, #8] +10001048: 601a str r2, [r3, #0] +1000104a: 6802 ldr r2, [r0, #0] +1000104c: 2a00 cmp r2, #0 +1000104e: dafc bge.n 1000104a +10001050: 2208 movs r2, #8 +10001052: 60c5 str r5, [r0, #12] +10001054: 601a str r2, [r3, #0] +10001056: bc70 pop {r4, r5, r6} +10001058: 4770 bx lr +1000105a: 6803 ldr r3, [r0, #0] +1000105c: f003 033f and.w r3, r3, #63 @ 0x3f +10001060: 428b cmp r3, r1 +10001062: d1da bne.n 1000101a +10001064: 6883 ldr r3, [r0, #8] +10001066: f3c3 030b ubfx r3, r3, #0, #12 +1000106a: 42b3 cmp r3, r6 +1000106c: d1d5 bne.n 1000101a +1000106e: 68c3 ldr r3, [r0, #12] +10001070: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001074: 42ab cmp r3, r5 +10001076: d1d0 bne.n 1000101a +10001078: e7ed b.n 10001056 +1000107a: bf00 nop +1000107c: 00b71b00 .word 0x00b71b00 +10001080: 40058000 .word 0x40058000 +10001084: 40022000 .word 0x40022000 +10001088: 40020000 .word 0x40020000 + +1000108c : +1000108c: 2301 movs r3, #1 +1000108e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001092: 0080 lsls r0, r0, #2 +10001094: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001098: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000109c: 6041 str r1, [r0, #4] +1000109e: 6003 str r3, [r0, #0] +100010a0: 4770 bx lr +100010a2: bf00 nop + +100010a4 : +100010a4: 2300 movs r3, #0 +100010a6: 8adb ldrh r3, [r3, #22] +100010a8: 2200 movs r2, #0 +100010aa: e842 f200 tt r2, r2 +100010ae: 0252 lsls r2, r2, #9 +100010b0: d401 bmi.n 100010b6 +100010b2: 2110 movs r1, #16 +100010b4: 4718 bx r3 +100010b6: 2104 movs r1, #4 +100010b8: 4718 bx r3 +100010ba: bf00 nop + +100010bc : +100010bc: 4a03 ldr r2, [pc, #12] @ (100010cc ) +100010be: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100010c2: 2b00 cmp r3, #0 +100010c4: d0fb beq.n 100010be +100010c6: f3bf 8f5f dmb sy +100010ca: 4770 bx lr +100010cc: 400e0000 .word 0x400e0000 + +100010d0 : +100010d0: 2100 movs r1, #0 +100010d2: 4b04 ldr r3, [pc, #16] @ (100010e4 ) +100010d4: 4a04 ldr r2, [pc, #16] @ (100010e8 ) +100010d6: f3bf 8f5f dmb sy +100010da: f843 1b04 str.w r1, [r3], #4 +100010de: 4293 cmp r3, r2 +100010e0: d1f9 bne.n 100010d6 +100010e2: 4770 bx lr +100010e4: 400e080c .word 0x400e080c +100010e8: 400e082c .word 0x400e082c + +100010ec : +100010ec: b410 push {r4} +100010ee: f44f 708d mov.w r0, #282 @ 0x11a +100010f2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100010f6: 4a06 ldr r2, [pc, #24] @ (10001110 ) +100010f8: 4b06 ldr r3, [pc, #24] @ (10001114 ) +100010fa: 4907 ldr r1, [pc, #28] @ (10001118 ) +100010fc: 6014 str r4, [r2, #0] +100010fe: 60d0 str r0, [r2, #12] +10001100: 6019 str r1, [r3, #0] +10001102: 6853 ldr r3, [r2, #4] +10001104: 2b00 cmp r3, #0 +10001106: dafc bge.n 10001102 +10001108: f85d 4b04 ldr.w r4, [sp], #4 +1000110c: 4770 bx lr +1000110e: bf00 nop +10001110: 40048000 .word 0x40048000 +10001114: 4004a000 .word 0x4004a000 +10001118: 00fab000 .word 0x00fab000 + +1000111c : +1000111c: 4770 bx lr +1000111e: bf00 nop + +10001120 : +10001120: b508 push {r3, lr} +10001122: 4801 ldr r0, [pc, #4] @ (10001128 ) +10001124: f7ff f8b8 bl 10000298 +10001128: 100034f8 .word 0x100034f8 + +1000112c : +1000112c: b538 push {r3, r4, r5, lr} +1000112e: 4c05 ldr r4, [pc, #20] @ (10001144 ) +10001130: 4d05 ldr r5, [pc, #20] @ (10001148 ) +10001132: 42ac cmp r4, r5 +10001134: d204 bcs.n 10001140 +10001136: f854 3b04 ldr.w r3, [r4], #4 +1000113a: 4798 blx r3 +1000113c: 42ac cmp r4, r5 +1000113e: d3fa bcc.n 10001136 +10001140: bd38 pop {r3, r4, r5, pc} +10001142: bf00 nop +10001144: 10003468 .word 0x10003468 +10001148: 100034a8 .word 0x100034a8 + +1000114c : +1000114c: b410 push {r4} +1000114e: 4807 ldr r0, [pc, #28] @ (1000116c ) +10001150: 4c07 ldr r4, [pc, #28] @ (10001170 ) +10001152: 4b08 ldr r3, [pc, #32] @ (10001174 ) +10001154: 4a08 ldr r2, [pc, #32] @ (10001178 ) +10001156: 4909 ldr r1, [pc, #36] @ (1000117c ) +10001158: 6004 str r4, [r0, #0] +1000115a: 601a str r2, [r3, #0] +1000115c: 688b ldr r3, [r1, #8] +1000115e: ea32 0303 bics.w r3, r2, r3 +10001162: d1fb bne.n 1000115c +10001164: f85d 4b04 ldr.w r4, [sp], #4 +10001168: 4770 bx lr +1000116a: bf00 nop +1000116c: 40022000 .word 0x40022000 +10001170: efef3b7f .word 0xefef3b7f +10001174: 40023000 .word 0x40023000 +10001178: 03f3fff6 .word 0x03f3fff6 +1000117c: 40020000 .word 0x40020000 + +10001180 : +10001180: 4b04 ldr r3, [pc, #16] @ (10001194 ) +10001182: 6cdb ldr r3, [r3, #76] @ 0x4c +10001184: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001188: d103 bne.n 10001192 +1000118a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000118e: 4b02 ldr r3, [pc, #8] @ (10001198 ) +10001190: 64da str r2, [r3, #76] @ 0x4c +10001192: 4770 bx lr +10001194: 50110000 .word 0x50110000 +10001198: 50112000 .word 0x50112000 + +1000119c : +1000119c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100011a0: 4b04 ldr r3, [pc, #16] @ (100011b4 ) +100011a2: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100011a6: 430b orrs r3, r1 +100011a8: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100011ac: ee10 0430 dcp_rcmp r0 +100011b0: 4770 bx lr +100011b2: bf00 nop +100011b4: 00300303 .word 0x00300303 + +100011b8 : +100011b8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100011bc: 4b04 ldr r3, [pc, #16] @ (100011d0 ) +100011be: 4a05 ldr r2, [pc, #20] @ (100011d4 ) +100011c0: 6019 str r1, [r3, #0] +100011c2: 6893 ldr r3, [r2, #8] +100011c4: 43db mvns r3, r3 +100011c6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100011ca: d1fa bne.n 100011c2 +100011cc: 4770 bx lr +100011ce: bf00 nop +100011d0: 40023000 .word 0x40023000 +100011d4: 40020000 .word 0x40020000 + +100011d8 : +100011d8: b510 push {r4, lr} +100011da: f245 2053 movw r0, #21075 @ 0x5253 +100011de: f7ff ff61 bl 100010a4 +100011e2: e8bd 4010 ldmia.w sp!, {r4, lr} +100011e6: 4603 mov r3, r0 +100011e8: 2004 movs r0, #4 +100011ea: 4718 bx r3 + +100011ec : +100011ec: b510 push {r4, lr} +100011ee: f245 2053 movw r0, #21075 @ 0x5253 +100011f2: f7ff ff57 bl 100010a4 +100011f6: e8bd 4010 ldmia.w sp!, {r4, lr} +100011fa: 4603 mov r3, r0 +100011fc: 2001 movs r0, #1 +100011fe: 4718 bx r3 + +10001200 : +10001200: f7ff b8a2 b.w 10000348 + +10001204 : +10001204: 4914 ldr r1, [pc, #80] @ (10001258 ) +10001206: 4b15 ldr r3, [pc, #84] @ (1000125c ) +10001208: b570 push {r4, r5, r6, lr} +1000120a: 1a5c subs r4, r3, r1 +1000120c: 10a6 asrs r6, r4, #2 +1000120e: 2e44 cmp r6, #68 @ 0x44 +10001210: 4632 mov r2, r6 +10001212: bf28 it cs +10001214: 2244 movcs r2, #68 @ 0x44 +10001216: 4d12 ldr r5, [pc, #72] @ (10001260 ) +10001218: 0092 lsls r2, r2, #2 +1000121a: 4628 mov r0, r5 +1000121c: f002 f872 bl 10003304 +10001220: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001224: d813 bhi.n 1000124e +10001226: 4a0f ldr r2, [pc, #60] @ (10001264 ) +10001228: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000122c: d012 beq.n 10001254 +1000122e: 192b adds r3, r5, r4 +10001230: 0841 lsrs r1, r0, #1 +10001232: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001236: e9c3 2200 strd r2, r2, [r3] +1000123a: 3308 adds r3, #8 +1000123c: 428b cmp r3, r1 +1000123e: d1fa bne.n 10001236 +10001240: 07c3 lsls r3, r0, #31 +10001242: d504 bpl.n 1000124e +10001244: f020 0001 bic.w r0, r0, #1 +10001248: 4430 add r0, r6 +1000124a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000124e: 4b06 ldr r3, [pc, #24] @ (10001268 ) +10001250: 609d str r5, [r3, #8] +10001252: bd70 pop {r4, r5, r6, pc} +10001254: 2043 movs r0, #67 @ 0x43 +10001256: e7f8 b.n 1000124a +10001258: 10000000 .word 0x10000000 +1000125c: 10000110 .word 0x10000110 +10001260: 20000000 .word 0x20000000 +10001264: 10000111 .word 0x10000111 +10001268: e000ed00 .word 0xe000ed00 + +1000126c : +1000126c: 2300 movs r3, #0 +1000126e: b570 push {r4, r5, r6, lr} +10001270: 4c2b ldr r4, [pc, #172] @ (10001320 ) +10001272: b082 sub sp, #8 +10001274: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001278: f7ff ff38 bl 100010ec +1000127c: 2201 movs r2, #1 +1000127e: 4b29 ldr r3, [pc, #164] @ (10001324 ) +10001280: 63da str r2, [r3, #60] @ 0x3c +10001282: 6c63 ldr r3, [r4, #68] @ 0x44 +10001284: 2b01 cmp r3, #1 +10001286: d1fc bne.n 10001282 +10001288: 2103 movs r1, #3 +1000128a: 4a26 ldr r2, [pc, #152] @ (10001324 ) +1000128c: 4b24 ldr r3, [pc, #144] @ (10001320 ) +1000128e: 6311 str r1, [r2, #48] @ 0x30 +10001290: 6b9c ldr r4, [r3, #56] @ 0x38 +10001292: 2c01 cmp r4, #1 +10001294: d1fc bne.n 10001290 +10001296: 2602 movs r6, #2 +10001298: 2505 movs r5, #5 +1000129a: 4621 mov r1, r4 +1000129c: 2305 movs r3, #5 +1000129e: 4a22 ldr r2, [pc, #136] @ (10001328 ) +100012a0: 4822 ldr r0, [pc, #136] @ (1000132c ) +100012a2: 9600 str r6, [sp, #0] +100012a4: f7ff feac bl 10001000 +100012a8: 4621 mov r1, r4 +100012aa: 462b mov r3, r5 +100012ac: 4a20 ldr r2, [pc, #128] @ (10001330 ) +100012ae: 4821 ldr r0, [pc, #132] @ (10001334 ) +100012b0: 9500 str r5, [sp, #0] +100012b2: f7ff fea5 bl 10001000 +100012b6: 2200 movs r2, #0 +100012b8: 2004 movs r0, #4 +100012ba: 4631 mov r1, r6 +100012bc: 4b1e ldr r3, [pc, #120] @ (10001338 ) +100012be: f7ff fe31 bl 10000f24 +100012c2: 4621 mov r1, r4 +100012c4: 4628 mov r0, r5 +100012c6: 2200 movs r2, #0 +100012c8: 4b1c ldr r3, [pc, #112] @ (1000133c ) +100012ca: f7ff fe2b bl 10000f24 +100012ce: 2200 movs r2, #0 +100012d0: 2008 movs r0, #8 +100012d2: 4611 mov r1, r2 +100012d4: 4b1a ldr r3, [pc, #104] @ (10001340 ) +100012d6: f7ff fe25 bl 10000f24 +100012da: 2200 movs r2, #0 +100012dc: 2009 movs r0, #9 +100012de: 4611 mov r1, r2 +100012e0: 4b17 ldr r3, [pc, #92] @ (10001340 ) +100012e2: f7ff fe1f bl 10000f24 +100012e6: 2200 movs r2, #0 +100012e8: 2006 movs r0, #6 +100012ea: 4611 mov r1, r2 +100012ec: 4b13 ldr r3, [pc, #76] @ (1000133c ) +100012ee: f7ff fe19 bl 10000f24 +100012f2: 2200 movs r2, #0 +100012f4: 4b11 ldr r3, [pc, #68] @ (1000133c ) +100012f6: 2007 movs r0, #7 +100012f8: 4611 mov r1, r2 +100012fa: f7ff fe13 bl 10000f24 +100012fe: 2004 movs r0, #4 +10001300: f7ff fe78 bl 10000ff4 +10001304: 2400 movs r4, #0 +10001306: 4b0f ldr r3, [pc, #60] @ (10001344 ) +10001308: fba3 3500 umull r3, r5, r3, r0 +1000130c: 0cad lsrs r5, r5, #18 +1000130e: b2e0 uxtb r0, r4 +10001310: 4629 mov r1, r5 +10001312: 3401 adds r4, #1 +10001314: f7ff feba bl 1000108c +10001318: 2c06 cmp r4, #6 +1000131a: d1f8 bne.n 1000130e +1000131c: b002 add sp, #8 +1000131e: bd70 pop {r4, r5, r6, pc} +10001320: 40010000 .word 0x40010000 +10001324: 40013000 .word 0x40013000 +10001328: 59682f00 .word 0x59682f00 +1000132c: 40050000 .word 0x40050000 +10001330: 47868c00 .word 0x47868c00 +10001334: 40058000 .word 0x40058000 +10001338: 00b71b00 .word 0x00b71b00 +1000133c: 08f0d180 .word 0x08f0d180 +10001340: 02dc6c00 .word 0x02dc6c00 +10001344: 431bde83 .word 0x431bde83 + +10001348 : +10001348: b086 sub sp, #24 +1000134a: b403 push {r0, r1} +1000134c: fc51 0408 dcp_pxmd r0, r1 +10001350: e9cd 0102 strd r0, r1, [sp, #8] +10001354: fc51 0409 dcp_pymd r0, r1 +10001358: e9cd 0104 strd r0, r1, [sp, #16] +1000135c: ec51 040a dcp_refd r0, r1 +10001360: e9cd 0106 strd r0, r1, [sp, #24] +10001364: bc03 pop {r0, r1} +10001366: 47f0 blx lr + +10001368 : +10001368: e8bd 5000 ldmia.w sp!, {ip, lr} +1000136c: ec4e c400 dcp_wxmd ip, lr +10001370: e8bd 5000 ldmia.w sp!, {ip, lr} +10001374: ec4e c401 dcp_wymd ip, lr +10001378: e8bd 5000 ldmia.w sp!, {ip, lr} +1000137c: ec4e c402 dcp_wefd ip, lr +10001380: bd00 pop {pc} +10001382: 0000 movs r0, r0 +10001384: b500 push {lr} +10001386: f7ff ffdf bl 10001348 +1000138a: e002 b.n 10001392 <__wrap___aeabi_dadd+0x6> + +1000138c <__wrap___aeabi_dadd>: +1000138c: fe10 f430 dcp_pcmp APSR_nzcv +10001390: d4f8 bmi.n 10001384 +10001392: ec41 0410 dcp_wxup r0, r1 +10001396: ec43 2411 dcp_wyup r2, r3 +1000139a: ee00 0401 dcp_add0 +1000139e: ee10 0401 dcp_add1 +100013a2: ee80 0420 dcp_nrdd +100013a6: ec51 0410 dcp_rdda r0, r1 +100013aa: 4770 bx lr +100013ac: b500 push {lr} +100013ae: f7ff ffcb bl 10001348 +100013b2: e002 b.n 100013ba <__wrap___aeabi_dsub+0x6> + +100013b4 <__wrap___aeabi_dsub>: +100013b4: fe10 f430 dcp_pcmp APSR_nzcv +100013b8: d4f8 bmi.n 100013ac <__wrap___aeabi_dadd+0x20> +100013ba: ec41 0410 dcp_wxup r0, r1 +100013be: ec43 2411 dcp_wyup r2, r3 +100013c2: ee00 0401 dcp_add0 +100013c6: ee10 0421 dcp_sub1 +100013ca: ee80 0420 dcp_nrdd +100013ce: ec51 0430 dcp_rdds r0, r1 +100013d2: 4770 bx lr +100013d4: b500 push {lr} +100013d6: f7ff ffb7 bl 10001348 +100013da: e002 b.n 100013e2 <__wrap___aeabi_dmul+0x6> + +100013dc <__wrap___aeabi_dmul>: +100013dc: fe10 f430 dcp_pcmp APSR_nzcv +100013e0: d4f8 bmi.n 100013d4 <__wrap___aeabi_dsub+0x20> +100013e2: b510 push {r4, lr} +100013e4: ec41 0410 dcp_wxup r0, r1 +100013e8: ec43 2411 dcp_wyup r2, r3 +100013ec: ec51 0404 dcp_rxms r0, r1, #0x0 +100013f0: ec53 2405 dcp_ryms r2, r3, #0x0 +100013f4: fba0 4c02 umull r4, ip, r0, r2 +100013f8: f05f 0e00 movs.w lr, #0 +100013fc: fbe0 ce03 umlal ip, lr, r0, r3 +10001400: fbe1 ce02 umlal ip, lr, r1, r2 +10001404: ec4c 4420 dcp_wxms r4, ip +10001408: 2400 movs r4, #0 +1000140a: fbe1 e403 umlal lr, r4, r1, r3 +1000140e: ec44 e430 dcp_wxmo lr, r4 +10001412: ee80 0420 dcp_nrdd +10001416: ec51 0450 dcp_rddm r0, r1 +1000141a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000141e: 4770 bx lr +10001420: b500 push {lr} +10001422: f7ff ff91 bl 10001348 +10001426: e002 b.n 1000142e <__wrap___aeabi_ddiv+0x6> + +10001428 <__wrap___aeabi_ddiv>: +10001428: fe10 f430 dcp_pcmp APSR_nzcv +1000142c: d4f8 bmi.n 10001420 <__wrap___aeabi_dmul+0x44> +1000142e: ec41 0410 dcp_wxup r0, r1 +10001432: ec43 2411 dcp_wyup r2, r3 +10001436: ec51 0421 dcp_rymr r0, r1 +1000143a: fba0 1201 umull r1, r2, r0, r1 +1000143e: ea6f 0282 mvn.w r2, r2, lsl #2 +10001442: fb52 0010 smmlar r0, r2, r0, r0 +10001446: fb52 f212 smmulr r2, r2, r2 +1000144a: fb52 0010 smmlar r0, r2, r0, r0 +1000144e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001452: ec53 2404 dcp_rxms r2, r3, #0x0 +10001456: fb5c f113 smmulr r1, ip, r3 +1000145a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000145e: fba1 2002 umull r2, r0, r1, r2 +10001462: fb01 0003 mla r0, r1, r3, r0 +10001466: ec53 2444 dcp_rxms r2, r3, #0x4 +1000146a: eba2 0000 sub.w r0, r2, r0 +1000146e: fb50 f21c smmulr r2, r0, ip +10001472: ea4f 1311 mov.w r3, r1, lsr #4 +10001476: eb12 7001 adds.w r0, r2, r1, lsl #28 +1000147a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1000147e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001482: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001486: f020 0007 bic.w r0, r0, #7 +1000148a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000148e: fba0 3c02 umull r3, ip, r0, r2 +10001492: ec53 2475 dcp_ryms r2, r3, #0x7 +10001496: fb00 cc03 mla ip, r0, r3, ip +1000149a: fb01 cc02 mla ip, r1, r2, ip +1000149e: ec53 2404 dcp_rxms r2, r3, #0x0 +100014a2: ebac 4c82 sub.w ip, ip, r2, lsl #18 +100014a6: ea40 705c orr.w r0, r0, ip, lsr #29 +100014aa: f1a0 0001 sub.w r0, r0, #1 +100014ae: ec41 0440 dcp_wxdd r0, r1 +100014b2: ee80 0420 dcp_nrdd +100014b6: ec51 0470 dcp_rddd r0, r1 +100014ba: 4770 bx lr +100014bc: b500 push {lr} +100014be: f7ff ff43 bl 10001348 +100014c2: e002 b.n 100014ca <__wrap___aeabi_i2d+0x6> + +100014c4 <__wrap___aeabi_i2d>: +100014c4: fe10 f430 dcp_pcmp APSR_nzcv +100014c8: d4f8 bmi.n 100014bc <__wrap___aeabi_ddiv+0x94> +100014ca: ec40 0470 dcp_wxic r0, r0 +100014ce: ee00 0401 dcp_add0 +100014d2: ee10 0421 dcp_sub1 +100014d6: ee80 0420 dcp_nrdd +100014da: ec51 0430 dcp_rdds r0, r1 +100014de: 4770 bx lr +100014e0: b500 push {lr} +100014e2: f7ff ff31 bl 10001348 +100014e6: e002 b.n 100014ee <__wrap___aeabi_ui2d+0x6> + +100014e8 <__wrap___aeabi_ui2d>: +100014e8: fe10 f430 dcp_pcmp APSR_nzcv +100014ec: d4f8 bmi.n 100014e0 <__wrap___aeabi_i2d+0x1c> +100014ee: ec40 0460 dcp_wxuc r0, r0 +100014f2: ee00 0401 dcp_add0 +100014f6: ee10 0421 dcp_sub1 +100014fa: ee80 0420 dcp_nrdd +100014fe: ec51 0430 dcp_rdds r0, r1 +10001502: 4770 bx lr +10001504: b500 push {lr} +10001506: f7ff ff1f bl 10001348 +1000150a: e002 b.n 10001512 + +1000150c <__wrap___aeabi_d2iz>: +1000150c: fe10 f430 dcp_pcmp APSR_nzcv +10001510: d4f8 bmi.n 10001504 <__wrap___aeabi_ui2d+0x1c> + +10001512 : +10001512: ec41 0480 dcp_wxdc r0, r1 +10001516: ee00 0401 dcp_add0 +1000151a: ee10 0401 dcp_add1 +1000151e: ee80 0440 dcp_ntdc +10001522: ee10 0413 dcp_rdic r0 +10001526: 4770 bx lr +10001528: b500 push {lr} +1000152a: f7ff ff0d bl 10001348 +1000152e: e002 b.n 10001536 + +10001530 <__wrap___aeabi_d2uiz>: +10001530: fe10 f430 dcp_pcmp APSR_nzcv +10001534: d4f8 bmi.n 10001528 + +10001536 : +10001536: ec41 0480 dcp_wxdc r0, r1 +1000153a: ee00 0401 dcp_add0 +1000153e: ee10 0401 dcp_add1 +10001542: ee80 0440 dcp_ntdc +10001546: ee10 0433 dcp_rduc r0 +1000154a: 4770 bx lr +1000154c: b500 push {lr} +1000154e: f7ff fefb bl 10001348 +10001552: e002 b.n 1000155a <__wrap___aeabi_dcmpun+0x6> + +10001554 <__wrap___aeabi_dcmpun>: +10001554: fe10 f430 dcp_pcmp APSR_nzcv +10001558: d4f8 bmi.n 1000154c +1000155a: ec41 0410 dcp_wxup r0, r1 +1000155e: ec43 2411 dcp_wyup r2, r3 +10001562: ee00 0401 dcp_add0 +10001566: ee10 0430 dcp_rcmp r0 +1000156a: f3c0 7000 ubfx r0, r0, #28, #1 +1000156e: 4770 bx lr +10001570: b500 push {lr} +10001572: f7ff fee9 bl 10001348 +10001576: e002 b.n 1000157e <__wrap___aeabi_dcmplt+0x6> + +10001578 <__wrap___aeabi_dcmplt>: +10001578: fe10 f430 dcp_pcmp APSR_nzcv +1000157c: d4f8 bmi.n 10001570 <__wrap___aeabi_dcmpun+0x1c> +1000157e: ec43 2410 dcp_wxup r2, r3 +10001582: ec41 0411 dcp_wyup r0, r1 +10001586: ee00 0401 dcp_add0 +1000158a: ee10 f430 dcp_rcmp APSR_nzcv +1000158e: bf8c ite hi +10001590: 2001 movhi r0, #1 +10001592: 2000 movls r0, #0 +10001594: 4770 bx lr +10001596: bf00 nop +10001598: b500 push {lr} +1000159a: f7ff fed5 bl 10001348 +1000159e: e002 b.n 100015a6 <__wrap___aeabi_dcmple+0x6> + +100015a0 <__wrap___aeabi_dcmple>: +100015a0: fe10 f430 dcp_pcmp APSR_nzcv +100015a4: d4f8 bmi.n 10001598 <__wrap___aeabi_dcmplt+0x20> +100015a6: ec43 2410 dcp_wxup r2, r3 +100015aa: ec41 0411 dcp_wyup r0, r1 +100015ae: ee00 0401 dcp_add0 +100015b2: ee10 f430 dcp_rcmp APSR_nzcv +100015b6: bf2c ite cs +100015b8: 2001 movcs r0, #1 +100015ba: 2000 movcc r0, #0 +100015bc: 4770 bx lr +100015be: bf00 nop +100015c0: b500 push {lr} +100015c2: f7ff fec1 bl 10001348 +100015c6: e002 b.n 100015ce <__wrap___aeabi_dcmpge+0x6> + +100015c8 <__wrap___aeabi_dcmpge>: +100015c8: fe10 f430 dcp_pcmp APSR_nzcv +100015cc: d4f8 bmi.n 100015c0 <__wrap___aeabi_dcmple+0x20> +100015ce: ec41 0410 dcp_wxup r0, r1 +100015d2: ec43 2411 dcp_wyup r2, r3 +100015d6: ee00 0401 dcp_add0 +100015da: ee10 f430 dcp_rcmp APSR_nzcv +100015de: bf2c ite cs +100015e0: 2001 movcs r0, #1 +100015e2: 2000 movcc r0, #0 +100015e4: 4770 bx lr +100015e6: bf00 nop +100015e8: b500 push {lr} +100015ea: f7ff fead bl 10001348 +100015ee: e002 b.n 100015f6 <__wrap___aeabi_dcmpgt+0x6> + +100015f0 <__wrap___aeabi_dcmpgt>: +100015f0: fe10 f430 dcp_pcmp APSR_nzcv +100015f4: d4f8 bmi.n 100015e8 <__wrap___aeabi_dcmpge+0x20> +100015f6: ec41 0410 dcp_wxup r0, r1 +100015fa: ec43 2411 dcp_wyup r2, r3 +100015fe: ee00 0401 dcp_add0 +10001602: ee10 f430 dcp_rcmp APSR_nzcv +10001606: bf8c ite hi +10001608: 2001 movhi r0, #1 +1000160a: 2000 movls r0, #0 +1000160c: 4770 bx lr +1000160e: bf00 nop + +10001610 <_out_null>: +10001610: 4770 bx lr +10001612: bf00 nop + +10001614 <_out_rev>: +10001614: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001618: b083 sub sp, #12 +1000161a: 4699 mov r9, r3 +1000161c: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001620: 9b0f ldr r3, [sp, #60] @ 0x3c +10001622: 4688 mov r8, r1 +10001624: 4611 mov r1, r2 +10001626: 079a lsls r2, r3, #30 +10001628: 4607 mov r7, r0 +1000162a: d116 bne.n 1000165a <_out_rev+0x46> +1000162c: 45da cmp sl, fp +1000162e: d23a bcs.n 100016a6 <_out_rev+0x92> +10001630: 460c mov r4, r1 +10001632: 460d mov r5, r1 +10001634: ebab 060a sub.w r6, fp, sl +10001638: 440e add r6, r1 +1000163a: 4622 mov r2, r4 +1000163c: 464b mov r3, r9 +1000163e: 4641 mov r1, r8 +10001640: 2020 movs r0, #32 +10001642: 3401 adds r4, #1 +10001644: 47b8 blx r7 +10001646: 42b4 cmp r4, r6 +10001648: d1f7 bne.n 1000163a <_out_rev+0x26> +1000164a: 4629 mov r1, r5 +1000164c: f1ba 0f00 cmp.w sl, #0 +10001650: d108 bne.n 10001664 <_out_rev+0x50> +10001652: 4620 mov r0, r4 +10001654: b003 add sp, #12 +10001656: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000165a: 460c mov r4, r1 +1000165c: f1ba 0f00 cmp.w sl, #0 +10001660: d010 beq.n 10001684 <_out_rev+0x70> +10001662: 460e mov r6, r1 +10001664: 4655 mov r5, sl +10001666: 9b0c ldr r3, [sp, #48] @ 0x30 +10001668: 442e add r6, r5 +1000166a: 449a add sl, r3 +1000166c: 9101 str r1, [sp, #4] +1000166e: 1b72 subs r2, r6, r5 +10001670: 464b mov r3, r9 +10001672: 3d01 subs r5, #1 +10001674: 4641 mov r1, r8 +10001676: f81a 0d01 ldrb.w r0, [sl, #-1]! +1000167a: 4634 mov r4, r6 +1000167c: 47b8 blx r7 +1000167e: 2d00 cmp r5, #0 +10001680: d1f5 bne.n 1000166e <_out_rev+0x5a> +10001682: 9901 ldr r1, [sp, #4] +10001684: 9b0f ldr r3, [sp, #60] @ 0x3c +10001686: 079b lsls r3, r3, #30 +10001688: d5e3 bpl.n 10001652 <_out_rev+0x3e> +1000168a: 1a65 subs r5, r4, r1 +1000168c: 45ab cmp fp, r5 +1000168e: d9e0 bls.n 10001652 <_out_rev+0x3e> +10001690: 4622 mov r2, r4 +10001692: 464b mov r3, r9 +10001694: 4641 mov r1, r8 +10001696: 2020 movs r0, #32 +10001698: 3501 adds r5, #1 +1000169a: 47b8 blx r7 +1000169c: 455d cmp r5, fp +1000169e: f104 0401 add.w r4, r4, #1 +100016a2: d3f5 bcc.n 10001690 <_out_rev+0x7c> +100016a4: e7d5 b.n 10001652 <_out_rev+0x3e> +100016a6: 460c mov r4, r1 +100016a8: f1ba 0f00 cmp.w sl, #0 +100016ac: d1d9 bne.n 10001662 <_out_rev+0x4e> +100016ae: e7d0 b.n 10001652 <_out_rev+0x3e> + +100016b0 <_ntoa_format>: +100016b0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100016b4: 9f0f ldr r7, [sp, #60] @ 0x3c +100016b6: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +100016ba: f017 0f02 tst.w r7, #2 +100016be: 9c0a ldr r4, [sp, #40] @ 0x28 +100016c0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +100016c4: 9d0e ldr r5, [sp, #56] @ 0x38 +100016c6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +100016ca: d144 bne.n 10001756 <_ntoa_format+0xa6> +100016cc: bbf5 cbnz r5, 1000174c <_ntoa_format+0x9c> +100016ce: 42b4 cmp r4, r6 +100016d0: d241 bcs.n 10001756 <_ntoa_format+0xa6> +100016d2: f007 0b01 and.w fp, r7, #1 +100016d6: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100016da: f04f 0e30 mov.w lr, #48 @ 0x30 +100016de: 44c4 add ip, r8 +100016e0: e004 b.n 100016ec <_ntoa_format+0x3c> +100016e2: 3401 adds r4, #1 +100016e4: 42a6 cmp r6, r4 +100016e6: f80c ef01 strb.w lr, [ip, #1]! +100016ea: d901 bls.n 100016f0 <_ntoa_format+0x40> +100016ec: 2c20 cmp r4, #32 +100016ee: d1f8 bne.n 100016e2 <_ntoa_format+0x32> +100016f0: f1bb 0f00 cmp.w fp, #0 +100016f4: f000 8088 beq.w 10001808 <_ntoa_format+0x158> +100016f8: 42a5 cmp r5, r4 +100016fa: d92c bls.n 10001756 <_ntoa_format+0xa6> +100016fc: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001700: f04f 0e30 mov.w lr, #48 @ 0x30 +10001704: 44c4 add ip, r8 +10001706: e004 b.n 10001712 <_ntoa_format+0x62> +10001708: 3401 adds r4, #1 +1000170a: 42ac cmp r4, r5 +1000170c: f80c ef01 strb.w lr, [ip, #1]! +10001710: d021 beq.n 10001756 <_ntoa_format+0xa6> +10001712: 2c20 cmp r4, #32 +10001714: d1f8 bne.n 10001708 <_ntoa_format+0x58> +10001716: f017 0f10 tst.w r7, #16 +1000171a: d00e beq.n 1000173a <_ntoa_format+0x8a> +1000171c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001720: d154 bne.n 100017cc <_ntoa_format+0x11c> +10001722: 42a6 cmp r6, r4 +10001724: d063 beq.n 100017ee <_ntoa_format+0x13e> +10001726: 42a5 cmp r5, r4 +10001728: d061 beq.n 100017ee <_ntoa_format+0x13e> +1000172a: f1b9 0f10 cmp.w r9, #16 +1000172e: d050 beq.n 100017d2 <_ntoa_format+0x122> +10001730: f1b9 0f02 cmp.w r9, #2 +10001734: d056 beq.n 100017e4 <_ntoa_format+0x134> +10001736: 2c20 cmp r4, #32 +10001738: d129 bne.n 1000178e <_ntoa_format+0xde> +1000173a: 2420 movs r4, #32 +1000173c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001740: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001744: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001748: f7ff bf64 b.w 10001614 <_out_rev> +1000174c: f017 0b01 ands.w fp, r7, #1 +10001750: d134 bne.n 100017bc <_ntoa_format+0x10c> +10001752: 42b4 cmp r4, r6 +10001754: d3bf bcc.n 100016d6 <_ntoa_format+0x26> +10001756: f017 0f10 tst.w r7, #16 +1000175a: d01e beq.n 1000179a <_ntoa_format+0xea> +1000175c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001760: d1e3 bne.n 1000172a <_ntoa_format+0x7a> +10001762: 2c00 cmp r4, #0 +10001764: d1dd bne.n 10001722 <_ntoa_format+0x72> +10001766: f1b9 0f10 cmp.w r9, #16 +1000176a: d063 beq.n 10001834 <_ntoa_format+0x184> +1000176c: f1b9 0f02 cmp.w r9, #2 +10001770: d077 beq.n 10001862 <_ntoa_format+0x1b2> +10001772: 2430 movs r4, #48 @ 0x30 +10001774: f888 4000 strb.w r4, [r8] +10001778: 2401 movs r4, #1 +1000177a: f1ba 0f00 cmp.w sl, #0 +1000177e: d111 bne.n 100017a4 <_ntoa_format+0xf4> +10001780: 077e lsls r6, r7, #29 +10001782: d548 bpl.n 10001816 <_ntoa_format+0x166> +10001784: 262b movs r6, #43 @ 0x2b +10001786: f808 6004 strb.w r6, [r8, r4] +1000178a: 3401 adds r4, #1 +1000178c: e7d6 b.n 1000173c <_ntoa_format+0x8c> +1000178e: 4626 mov r6, r4 +10001790: 3401 adds r4, #1 +10001792: f04f 0c30 mov.w ip, #48 @ 0x30 +10001796: f808 c006 strb.w ip, [r8, r6] +1000179a: 2c20 cmp r4, #32 +1000179c: d0cd beq.n 1000173a <_ntoa_format+0x8a> +1000179e: f1ba 0f00 cmp.w sl, #0 +100017a2: d0ed beq.n 10001780 <_ntoa_format+0xd0> +100017a4: 262d movs r6, #45 @ 0x2d +100017a6: f808 6004 strb.w r6, [r8, r4] +100017aa: 3401 adds r4, #1 +100017ac: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100017b0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100017b4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100017b8: f7ff bf2c b.w 10001614 <_out_rev> +100017bc: f1ba 0f00 cmp.w sl, #0 +100017c0: d030 beq.n 10001824 <_ntoa_format+0x174> +100017c2: 42b4 cmp r4, r6 +100017c4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +100017c8: d385 bcc.n 100016d6 <_ntoa_format+0x26> +100017ca: e795 b.n 100016f8 <_ntoa_format+0x48> +100017cc: f1b9 0f10 cmp.w r9, #16 +100017d0: d1b3 bne.n 1000173a <_ntoa_format+0x8a> +100017d2: 06be lsls r6, r7, #26 +100017d4: d53b bpl.n 1000184e <_ntoa_format+0x19e> +100017d6: 2c20 cmp r4, #32 +100017d8: d0af beq.n 1000173a <_ntoa_format+0x8a> +100017da: 2658 movs r6, #88 @ 0x58 +100017dc: f808 6004 strb.w r6, [r8, r4] +100017e0: 3401 adds r4, #1 +100017e2: e7a8 b.n 10001736 <_ntoa_format+0x86> +100017e4: 2c20 cmp r4, #32 +100017e6: d0a8 beq.n 1000173a <_ntoa_format+0x8a> +100017e8: 4626 mov r6, r4 +100017ea: 3401 adds r4, #1 +100017ec: e007 b.n 100017fe <_ntoa_format+0x14e> +100017ee: 1e66 subs r6, r4, #1 +100017f0: d0b9 beq.n 10001766 <_ntoa_format+0xb6> +100017f2: f1b9 0f10 cmp.w r9, #16 +100017f6: d036 beq.n 10001866 <_ntoa_format+0x1b6> +100017f8: f1b9 0f02 cmp.w r9, #2 +100017fc: d1c9 bne.n 10001792 <_ntoa_format+0xe2> +100017fe: f04f 0c62 mov.w ip, #98 @ 0x62 +10001802: f808 c006 strb.w ip, [r8, r6] +10001806: e796 b.n 10001736 <_ntoa_format+0x86> +10001808: f017 0f10 tst.w r7, #16 +1000180c: d0c5 beq.n 1000179a <_ntoa_format+0xea> +1000180e: f417 6f80 tst.w r7, #1024 @ 0x400 +10001812: d086 beq.n 10001722 <_ntoa_format+0x72> +10001814: e789 b.n 1000172a <_ntoa_format+0x7a> +10001816: 073e lsls r6, r7, #28 +10001818: d590 bpl.n 1000173c <_ntoa_format+0x8c> +1000181a: 2620 movs r6, #32 +1000181c: f808 6004 strb.w r6, [r8, r4] +10001820: 3401 adds r4, #1 +10001822: e78b b.n 1000173c <_ntoa_format+0x8c> +10001824: f017 0f0c tst.w r7, #12 +10001828: d000 beq.n 1000182c <_ntoa_format+0x17c> +1000182a: 3d01 subs r5, #1 +1000182c: 42b4 cmp r4, r6 +1000182e: f4ff af52 bcc.w 100016d6 <_ntoa_format+0x26> +10001832: e761 b.n 100016f8 <_ntoa_format+0x48> +10001834: 06bc lsls r4, r7, #26 +10001836: d412 bmi.n 1000185e <_ntoa_format+0x1ae> +10001838: 2478 movs r4, #120 @ 0x78 +1000183a: f888 4000 strb.w r4, [r8] +1000183e: 2430 movs r4, #48 @ 0x30 +10001840: f888 4001 strb.w r4, [r8, #1] +10001844: 2402 movs r4, #2 +10001846: f1ba 0f00 cmp.w sl, #0 +1000184a: d099 beq.n 10001780 <_ntoa_format+0xd0> +1000184c: e7aa b.n 100017a4 <_ntoa_format+0xf4> +1000184e: 2c20 cmp r4, #32 +10001850: f43f af73 beq.w 1000173a <_ntoa_format+0x8a> +10001854: 2678 movs r6, #120 @ 0x78 +10001856: f808 6004 strb.w r6, [r8, r4] +1000185a: 3401 adds r4, #1 +1000185c: e76b b.n 10001736 <_ntoa_format+0x86> +1000185e: 2458 movs r4, #88 @ 0x58 +10001860: e7eb b.n 1000183a <_ntoa_format+0x18a> +10001862: 2462 movs r4, #98 @ 0x62 +10001864: e7e9 b.n 1000183a <_ntoa_format+0x18a> +10001866: f017 0f20 tst.w r7, #32 +1000186a: f1a4 0c02 sub.w ip, r4, #2 +1000186e: d004 beq.n 1000187a <_ntoa_format+0x1ca> +10001870: f04f 0e58 mov.w lr, #88 @ 0x58 +10001874: f808 e00c strb.w lr, [r8, ip] +10001878: e78b b.n 10001792 <_ntoa_format+0xe2> +1000187a: f04f 0e78 mov.w lr, #120 @ 0x78 +1000187e: f808 e00c strb.w lr, [r8, ip] +10001882: e786 b.n 10001792 <_ntoa_format+0xe2> + +10001884 <_out_char>: +10001884: b900 cbnz r0, 10001888 <_out_char+0x4> +10001886: 4770 bx lr +10001888: f001 bb72 b.w 10002f70 <__wrap_putchar> + +1000188c <_out_fct>: +1000188c: b110 cbz r0, 10001894 <_out_fct+0x8> +1000188e: e9d1 3100 ldrd r3, r1, [r1] +10001892: 4718 bx r3 +10001894: 4770 bx lr +10001896: bf00 nop + +10001898 <_ftoa>: +10001898: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000189c: b097 sub sp, #92 @ 0x5c +1000189e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +100018a2: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +100018a6: 4607 mov r7, r0 +100018a8: 4688 mov r8, r1 +100018aa: ec51 0b17 vmov r0, r1, d7 +100018ae: 9c24 ldr r4, [sp, #144] @ 0x90 +100018b0: 4699 mov r9, r3 +100018b2: 920c str r2, [sp, #48] @ 0x30 +100018b4: 460b mov r3, r1 +100018b6: 4602 mov r2, r0 +100018b8: ed8d 7b04 vstr d7, [sp, #16] +100018bc: 9407 str r4, [sp, #28] +100018be: f7ff fe49 bl 10001554 <__wrap___aeabi_dcmpun> +100018c2: 2800 cmp r0, #0 +100018c4: f040 81f4 bne.w 10001cb0 <_ftoa+0x418> +100018c8: e9dd 0104 ldrd r0, r1, [sp, #16] +100018cc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018d0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100018d4: f7ff fe50 bl 10001578 <__wrap___aeabi_dcmplt> +100018d8: 2800 cmp r0, #0 +100018da: f040 811b bne.w 10001b14 <_ftoa+0x27c> +100018de: e9dd 0104 ldrd r0, r1, [sp, #16] +100018e2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100018e6: 4bac ldr r3, [pc, #688] @ (10001b98 <_ftoa+0x300>) +100018e8: f7ff fe82 bl 100015f0 <__wrap___aeabi_dcmpgt> +100018ec: 2800 cmp r0, #0 +100018ee: f040 80ee bne.w 10001ace <_ftoa+0x236> +100018f2: e9dd 0104 ldrd r0, r1, [sp, #16] +100018f6: a3a4 add r3, pc, #656 @ (adr r3, 10001b88 <_ftoa+0x2f0>) +100018f8: e9d3 2300 ldrd r2, r3, [r3] +100018fc: f7ff fe78 bl 100015f0 <__wrap___aeabi_dcmpgt> +10001900: 2800 cmp r0, #0 +10001902: f040 80d3 bne.w 10001aac <_ftoa+0x214> +10001906: e9dd 0104 ldrd r0, r1, [sp, #16] +1000190a: a3a1 add r3, pc, #644 @ (adr r3, 10001b90 <_ftoa+0x2f8>) +1000190c: e9d3 2300 ldrd r2, r3, [r3] +10001910: f7ff fe32 bl 10001578 <__wrap___aeabi_dcmplt> +10001914: 2800 cmp r0, #0 +10001916: f040 80c9 bne.w 10001aac <_ftoa+0x214> +1000191a: e9dd 0104 ldrd r0, r1, [sp, #16] +1000191e: 2200 movs r2, #0 +10001920: 2300 movs r3, #0 +10001922: f7ff fe29 bl 10001578 <__wrap___aeabi_dcmplt> +10001926: 2800 cmp r0, #0 +10001928: f040 80e8 bne.w 10001afc <_ftoa+0x264> +1000192c: 4623 mov r3, r4 +1000192e: 900d str r0, [sp, #52] @ 0x34 +10001930: f413 6f80 tst.w r3, #1024 @ 0x400 +10001934: bf08 it eq +10001936: 2506 moveq r5, #6 +10001938: 2130 movs r1, #48 @ 0x30 +1000193a: 462b mov r3, r5 +1000193c: aa0e add r2, sp, #56 @ 0x38 +1000193e: f1a5 0620 sub.w r6, r5, #32 +10001942: e005 b.n 10001950 <_ftoa+0xb8> +10001944: 3b01 subs r3, #1 +10001946: 42b3 cmp r3, r6 +10001948: f802 1b01 strb.w r1, [r2], #1 +1000194c: f000 8193 beq.w 10001c76 <_ftoa+0x3de> +10001950: 2b09 cmp r3, #9 +10001952: d8f7 bhi.n 10001944 <_ftoa+0xac> +10001954: 461e mov r6, r3 +10001956: 1aed subs r5, r5, r3 +10001958: e9dd 0104 ldrd r0, r1, [sp, #16] +1000195c: f7ff fdd6 bl 1000150c <__wrap___aeabi_d2iz> +10001960: 4b8e ldr r3, [pc, #568] @ (10001b9c <_ftoa+0x304>) +10001962: 4604 mov r4, r0 +10001964: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001968: ed93 7b00 vldr d7, [r3] +1000196c: ed8d 7b08 vstr d7, [sp, #32] +10001970: f7ff fda8 bl 100014c4 <__wrap___aeabi_i2d> +10001974: 4602 mov r2, r0 +10001976: 460b mov r3, r1 +10001978: e9dd 0104 ldrd r0, r1, [sp, #16] +1000197c: f7ff fd1a bl 100013b4 <__wrap___aeabi_dsub> +10001980: e9dd 2308 ldrd r2, r3, [sp, #32] +10001984: f7ff fd2a bl 100013dc <__wrap___aeabi_dmul> +10001988: 4602 mov r2, r0 +1000198a: 460b mov r3, r1 +1000198c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001990: f7ff fdce bl 10001530 <__wrap___aeabi_d2uiz> +10001994: 4682 mov sl, r0 +10001996: f7ff fda7 bl 100014e8 <__wrap___aeabi_ui2d> +1000199a: 4602 mov r2, r0 +1000199c: 460b mov r3, r1 +1000199e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100019a2: f7ff fd07 bl 100013b4 <__wrap___aeabi_dsub> +100019a6: 4602 mov r2, r0 +100019a8: 460b mov r3, r1 +100019aa: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +100019ae: 2200 movs r2, #0 +100019b0: 4b7b ldr r3, [pc, #492] @ (10001ba0 <_ftoa+0x308>) +100019b2: f7ff fe1d bl 100015f0 <__wrap___aeabi_dcmpgt> +100019b6: 2800 cmp r0, #0 +100019b8: f000 80fe beq.w 10001bb8 <_ftoa+0x320> +100019bc: f10a 0a01 add.w sl, sl, #1 +100019c0: 4650 mov r0, sl +100019c2: f7ff fd91 bl 100014e8 <__wrap___aeabi_ui2d> +100019c6: 4602 mov r2, r0 +100019c8: 460b mov r3, r1 +100019ca: e9dd 0108 ldrd r0, r1, [sp, #32] +100019ce: f7ff fde7 bl 100015a0 <__wrap___aeabi_dcmple> +100019d2: b110 cbz r0, 100019da <_ftoa+0x142> +100019d4: f04f 0a00 mov.w sl, #0 +100019d8: 3401 adds r4, #1 +100019da: 2e00 cmp r6, #0 +100019dc: f000 80fd beq.w 10001bda <_ftoa+0x342> +100019e0: 1e68 subs r0, r5, #1 +100019e2: ab0e add r3, sp, #56 @ 0x38 +100019e4: f8df c1cc ldr.w ip, [pc, #460] @ 10001bb4 <_ftoa+0x31c> +100019e8: 4418 add r0, r3 +100019ea: e00f b.n 10001a0c <_ftoa+0x174> +100019ec: fbac 210a umull r2, r1, ip, sl +100019f0: 08c9 lsrs r1, r1, #3 +100019f2: eb01 0281 add.w r2, r1, r1, lsl #2 +100019f6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +100019fa: 3230 adds r2, #48 @ 0x30 +100019fc: f1ba 0f09 cmp.w sl, #9 +10001a00: f800 2f01 strb.w r2, [r0, #1]! +10001a04: f240 811c bls.w 10001c40 <_ftoa+0x3a8> +10001a08: 468a mov sl, r1 +10001a0a: 461d mov r5, r3 +10001a0c: 2d20 cmp r5, #32 +10001a0e: f105 0301 add.w r3, r5, #1 +10001a12: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001a16: d1e9 bne.n 100019ec <_ftoa+0x154> +10001a18: 2520 movs r5, #32 +10001a1a: 1e69 subs r1, r5, #1 +10001a1c: ab0e add r3, sp, #56 @ 0x38 +10001a1e: 4861 ldr r0, [pc, #388] @ (10001ba4 <_ftoa+0x30c>) +10001a20: 4419 add r1, r3 +10001a22: e010 b.n 10001a46 <_ftoa+0x1ae> +10001a24: fb80 6204 smull r6, r2, r0, r4 +10001a28: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001a2c: eb03 0283 add.w r2, r3, r3, lsl #2 +10001a30: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001a34: f104 0230 add.w r2, r4, #48 @ 0x30 +10001a38: 3501 adds r5, #1 +10001a3a: 461c mov r4, r3 +10001a3c: f801 2f01 strb.w r2, [r1, #1]! +10001a40: 2b00 cmp r3, #0 +10001a42: f000 80eb beq.w 10001c1c <_ftoa+0x384> +10001a46: 2d20 cmp r5, #32 +10001a48: ea4f 73e4 mov.w r3, r4, asr #31 +10001a4c: d1ea bne.n 10001a24 <_ftoa+0x18c> +10001a4e: 9b07 ldr r3, [sp, #28] +10001a50: f003 0303 and.w r3, r3, #3 +10001a54: 2b01 cmp r3, #1 +10001a56: d118 bne.n 10001a8a <_ftoa+0x1f2> +10001a58: f1bb 0f00 cmp.w fp, #0 +10001a5c: d015 beq.n 10001a8a <_ftoa+0x1f2> +10001a5e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001a60: 2b00 cmp r3, #0 +10001a62: f000 810a beq.w 10001c7a <_ftoa+0x3e2> +10001a66: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001a6a: f1bb 0f20 cmp.w fp, #32 +10001a6e: d90c bls.n 10001a8a <_ftoa+0x1f2> +10001a70: 1e6b subs r3, r5, #1 +10001a72: a90e add r1, sp, #56 @ 0x38 +10001a74: 2230 movs r2, #48 @ 0x30 +10001a76: 440b add r3, r1 +10001a78: e005 b.n 10001a86 <_ftoa+0x1ee> +10001a7a: 3501 adds r5, #1 +10001a7c: 455d cmp r5, fp +10001a7e: f803 2f01 strb.w r2, [r3, #1]! +10001a82: f080 80d1 bcs.w 10001c28 <_ftoa+0x390> +10001a86: 2d20 cmp r5, #32 +10001a88: d1f7 bne.n 10001a7a <_ftoa+0x1e2> +10001a8a: 9b07 ldr r3, [sp, #28] +10001a8c: ac0e add r4, sp, #56 @ 0x38 +10001a8e: e9cd b302 strd fp, r3, [sp, #8] +10001a92: 4641 mov r1, r8 +10001a94: 464b mov r3, r9 +10001a96: 4638 mov r0, r7 +10001a98: 9a0c ldr r2, [sp, #48] @ 0x30 +10001a9a: 9501 str r5, [sp, #4] +10001a9c: 9400 str r4, [sp, #0] +10001a9e: f7ff fdb9 bl 10001614 <_out_rev> +10001aa2: 4682 mov sl, r0 +10001aa4: 4650 mov r0, sl +10001aa6: b017 add sp, #92 @ 0x5c +10001aa8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001aac: 9b07 ldr r3, [sp, #28] +10001aae: ed9d 7b04 vldr d7, [sp, #16] +10001ab2: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001ab6: 4641 mov r1, r8 +10001ab8: 464b mov r3, r9 +10001aba: 4638 mov r0, r7 +10001abc: 9a0c ldr r2, [sp, #48] @ 0x30 +10001abe: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001ac2: 9522 str r5, [sp, #136] @ 0x88 +10001ac4: b017 add sp, #92 @ 0x5c +10001ac6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001aca: f000 b945 b.w 10001d58 <_etoa> +10001ace: 0761 lsls r1, r4, #29 +10001ad0: 4623 mov r3, r4 +10001ad2: bf4c ite mi +10001ad4: 2304 movmi r3, #4 +10001ad6: 2303 movpl r3, #3 +10001ad8: 4641 mov r1, r8 +10001ada: 9321 str r3, [sp, #132] @ 0x84 +10001adc: 4638 mov r0, r7 +10001ade: 464b mov r3, r9 +10001ae0: 9a07 ldr r2, [sp, #28] +10001ae2: bf48 it mi +10001ae4: 4c30 ldrmi r4, [pc, #192] @ (10001ba8 <_ftoa+0x310>) +10001ae6: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001aea: bf58 it pl +10001aec: 4c2f ldrpl r4, [pc, #188] @ (10001bac <_ftoa+0x314>) +10001aee: 9a0c ldr r2, [sp, #48] @ 0x30 +10001af0: 9420 str r4, [sp, #128] @ 0x80 +10001af2: b017 add sp, #92 @ 0x5c +10001af4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001af8: f7ff bd8c b.w 10001614 <_out_rev> +10001afc: e9dd 2304 ldrd r2, r3, [sp, #16] +10001b00: 2000 movs r0, #0 +10001b02: 2100 movs r1, #0 +10001b04: f7ff fc56 bl 100013b4 <__wrap___aeabi_dsub> +10001b08: 2301 movs r3, #1 +10001b0a: e9cd 0104 strd r0, r1, [sp, #16] +10001b0e: 930d str r3, [sp, #52] @ 0x34 +10001b10: 4623 mov r3, r4 +10001b12: e70d b.n 10001930 <_ftoa+0x98> +10001b14: 4623 mov r3, r4 +10001b16: 079c lsls r4, r3, #30 +10001b18: f040 80aa bne.w 10001c70 <_ftoa+0x3d8> +10001b1c: f1bb 0f04 cmp.w fp, #4 +10001b20: f240 80a6 bls.w 10001c70 <_ftoa+0x3d8> +10001b24: 9b0c ldr r3, [sp, #48] @ 0x30 +10001b26: 461d mov r5, r3 +10001b28: 1f1c subs r4, r3, #4 +10001b2a: eb04 0a0b add.w sl, r4, fp +10001b2e: 462a mov r2, r5 +10001b30: 464b mov r3, r9 +10001b32: 4641 mov r1, r8 +10001b34: 2020 movs r0, #32 +10001b36: 3501 adds r5, #1 +10001b38: 47b8 blx r7 +10001b3a: 45aa cmp sl, r5 +10001b3c: d1f7 bne.n 10001b2e <_ftoa+0x296> +10001b3e: 4655 mov r5, sl +10001b40: 4c1b ldr r4, [pc, #108] @ (10001bb0 <_ftoa+0x318>) +10001b42: 1f26 subs r6, r4, #4 +10001b44: f814 0d01 ldrb.w r0, [r4, #-1]! +10001b48: 462a mov r2, r5 +10001b4a: 464b mov r3, r9 +10001b4c: 4641 mov r1, r8 +10001b4e: 47b8 blx r7 +10001b50: 42b4 cmp r4, r6 +10001b52: f105 0501 add.w r5, r5, #1 +10001b56: d1f5 bne.n 10001b44 <_ftoa+0x2ac> +10001b58: 9b07 ldr r3, [sp, #28] +10001b5a: f10a 0a04 add.w sl, sl, #4 +10001b5e: 0798 lsls r0, r3, #30 +10001b60: d5a0 bpl.n 10001aa4 <_ftoa+0x20c> +10001b62: 9c0c ldr r4, [sp, #48] @ 0x30 +10001b64: ebaa 0304 sub.w r3, sl, r4 +10001b68: 459b cmp fp, r3 +10001b6a: d99b bls.n 10001aa4 <_ftoa+0x20c> +10001b6c: 4652 mov r2, sl +10001b6e: 464b mov r3, r9 +10001b70: 4641 mov r1, r8 +10001b72: 2020 movs r0, #32 +10001b74: f10a 0a01 add.w sl, sl, #1 +10001b78: 47b8 blx r7 +10001b7a: ebaa 0304 sub.w r3, sl, r4 +10001b7e: 455b cmp r3, fp +10001b80: d3f4 bcc.n 10001b6c <_ftoa+0x2d4> +10001b82: e78f b.n 10001aa4 <_ftoa+0x20c> +10001b84: f3af 8000 nop.w +10001b88: 00000000 .word 0x00000000 +10001b8c: 41cdcd65 .word 0x41cdcd65 +10001b90: 00000000 .word 0x00000000 +10001b94: c1cdcd65 .word 0xc1cdcd65 +10001b98: 7fefffff .word 0x7fefffff +10001b9c: 10003608 .word 0x10003608 +10001ba0: 3fe00000 .word 0x3fe00000 +10001ba4: 66666667 .word 0x66666667 +10001ba8: 10003564 .word 0x10003564 +10001bac: 1000356c .word 0x1000356c +10001bb0: 10003578 .word 0x10003578 +10001bb4: cccccccd .word 0xcccccccd +10001bb8: 2200 movs r2, #0 +10001bba: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001bbe: 4b63 ldr r3, [pc, #396] @ (10001d4c <_ftoa+0x4b4>) +10001bc0: f7ff fcda bl 10001578 <__wrap___aeabi_dcmplt> +10001bc4: 2800 cmp r0, #0 +10001bc6: f47f af08 bne.w 100019da <_ftoa+0x142> +10001bca: f1ba 0f00 cmp.w sl, #0 +10001bce: d16a bne.n 10001ca6 <_ftoa+0x40e> +10001bd0: f10a 0a01 add.w sl, sl, #1 +10001bd4: 2e00 cmp r6, #0 +10001bd6: f47f af03 bne.w 100019e0 <_ftoa+0x148> +10001bda: 4620 mov r0, r4 +10001bdc: f7ff fc72 bl 100014c4 <__wrap___aeabi_i2d> +10001be0: 4602 mov r2, r0 +10001be2: 460b mov r3, r1 +10001be4: e9dd 0104 ldrd r0, r1, [sp, #16] +10001be8: f7ff fbe4 bl 100013b4 <__wrap___aeabi_dsub> +10001bec: 4602 mov r2, r0 +10001bee: 460b mov r3, r1 +10001bf0: e9cd 2304 strd r2, r3, [sp, #16] +10001bf4: 2200 movs r2, #0 +10001bf6: 4b55 ldr r3, [pc, #340] @ (10001d4c <_ftoa+0x4b4>) +10001bf8: f7ff fcbe bl 10001578 <__wrap___aeabi_dcmplt> +10001bfc: 2800 cmp r0, #0 +10001bfe: f47f af0c bne.w 10001a1a <_ftoa+0x182> +10001c02: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c06: 2200 movs r2, #0 +10001c08: 4b50 ldr r3, [pc, #320] @ (10001d4c <_ftoa+0x4b4>) +10001c0a: f7ff fcf1 bl 100015f0 <__wrap___aeabi_dcmpgt> +10001c0e: 2800 cmp r0, #0 +10001c10: f47f af03 bne.w 10001a1a <_ftoa+0x182> +10001c14: 3401 adds r4, #1 +10001c16: f024 0401 bic.w r4, r4, #1 +10001c1a: e6fe b.n 10001a1a <_ftoa+0x182> +10001c1c: 9b07 ldr r3, [sp, #28] +10001c1e: f003 0303 and.w r3, r3, #3 +10001c22: 2b01 cmp r3, #1 +10001c24: f000 8082 beq.w 10001d2c <_ftoa+0x494> +10001c28: 2d20 cmp r5, #32 +10001c2a: f43f af2e beq.w 10001a8a <_ftoa+0x1f2> +10001c2e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001c30: b37b cbz r3, 10001c92 <_ftoa+0x3fa> +10001c32: 222d movs r2, #45 @ 0x2d +10001c34: eb0d 0305 add.w r3, sp, r5 +10001c38: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c3c: 3501 adds r5, #1 +10001c3e: e724 b.n 10001a8a <_ftoa+0x1f2> +10001c40: 2b20 cmp r3, #32 +10001c42: f43f aee9 beq.w 10001a18 <_ftoa+0x180> +10001c46: aa0e add r2, sp, #56 @ 0x38 +10001c48: 4415 add r5, r2 +10001c4a: 441e add r6, r3 +10001c4c: 2230 movs r2, #48 @ 0x30 +10001c4e: e004 b.n 10001c5a <_ftoa+0x3c2> +10001c50: 2b20 cmp r3, #32 +10001c52: f805 2f01 strb.w r2, [r5, #1]! +10001c56: f43f aedf beq.w 10001a18 <_ftoa+0x180> +10001c5a: 429e cmp r6, r3 +10001c5c: f103 0301 add.w r3, r3, #1 +10001c60: d1f6 bne.n 10001c50 <_ftoa+0x3b8> +10001c62: 222e movs r2, #46 @ 0x2e +10001c64: eb0d 0306 add.w r3, sp, r6 +10001c68: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001c6c: 1c75 adds r5, r6, #1 +10001c6e: e6d4 b.n 10001a1a <_ftoa+0x182> +10001c70: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001c74: e763 b.n 10001b3e <_ftoa+0x2a6> +10001c76: 2520 movs r5, #32 +10001c78: e66e b.n 10001958 <_ftoa+0xc0> +10001c7a: 9b07 ldr r3, [sp, #28] +10001c7c: f013 0f0c tst.w r3, #12 +10001c80: d050 beq.n 10001d24 <_ftoa+0x48c> +10001c82: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001c86: 45ab cmp fp, r5 +10001c88: f63f aef2 bhi.w 10001a70 <_ftoa+0x1d8> +10001c8c: 2d20 cmp r5, #32 +10001c8e: f43f aefc beq.w 10001a8a <_ftoa+0x1f2> +10001c92: 9b07 ldr r3, [sp, #28] +10001c94: 075a lsls r2, r3, #29 +10001c96: d501 bpl.n 10001c9c <_ftoa+0x404> +10001c98: 222b movs r2, #43 @ 0x2b +10001c9a: e7cb b.n 10001c34 <_ftoa+0x39c> +10001c9c: 071b lsls r3, r3, #28 +10001c9e: f57f aef4 bpl.w 10001a8a <_ftoa+0x1f2> +10001ca2: 2220 movs r2, #32 +10001ca4: e7c6 b.n 10001c34 <_ftoa+0x39c> +10001ca6: f01a 0f01 tst.w sl, #1 +10001caa: f43f ae96 beq.w 100019da <_ftoa+0x142> +10001cae: e78f b.n 10001bd0 <_ftoa+0x338> +10001cb0: 07a6 lsls r6, r4, #30 +10001cb2: d134 bne.n 10001d1e <_ftoa+0x486> +10001cb4: f1bb 0f03 cmp.w fp, #3 +10001cb8: d931 bls.n 10001d1e <_ftoa+0x486> +10001cba: 9b0c ldr r3, [sp, #48] @ 0x30 +10001cbc: 461d mov r5, r3 +10001cbe: 1edc subs r4, r3, #3 +10001cc0: eb04 0a0b add.w sl, r4, fp +10001cc4: 462a mov r2, r5 +10001cc6: 464b mov r3, r9 +10001cc8: 4641 mov r1, r8 +10001cca: 2020 movs r0, #32 +10001ccc: 3501 adds r5, #1 +10001cce: 47b8 blx r7 +10001cd0: 4555 cmp r5, sl +10001cd2: d1f7 bne.n 10001cc4 <_ftoa+0x42c> +10001cd4: 4655 mov r5, sl +10001cd6: 4c1e ldr r4, [pc, #120] @ (10001d50 <_ftoa+0x4b8>) +10001cd8: 1ee6 subs r6, r4, #3 +10001cda: f814 0d01 ldrb.w r0, [r4, #-1]! +10001cde: 462a mov r2, r5 +10001ce0: 464b mov r3, r9 +10001ce2: 4641 mov r1, r8 +10001ce4: 47b8 blx r7 +10001ce6: 42a6 cmp r6, r4 +10001ce8: f105 0501 add.w r5, r5, #1 +10001cec: d1f5 bne.n 10001cda <_ftoa+0x442> +10001cee: 9b07 ldr r3, [sp, #28] +10001cf0: f10a 0a03 add.w sl, sl, #3 +10001cf4: 079d lsls r5, r3, #30 +10001cf6: f57f aed5 bpl.w 10001aa4 <_ftoa+0x20c> +10001cfa: 9c0c ldr r4, [sp, #48] @ 0x30 +10001cfc: ebaa 0304 sub.w r3, sl, r4 +10001d00: 459b cmp fp, r3 +10001d02: f67f aecf bls.w 10001aa4 <_ftoa+0x20c> +10001d06: 4652 mov r2, sl +10001d08: 464b mov r3, r9 +10001d0a: 4641 mov r1, r8 +10001d0c: 2020 movs r0, #32 +10001d0e: f10a 0a01 add.w sl, sl, #1 +10001d12: 47b8 blx r7 +10001d14: ebaa 0304 sub.w r3, sl, r4 +10001d18: 459b cmp fp, r3 +10001d1a: d8f4 bhi.n 10001d06 <_ftoa+0x46e> +10001d1c: e6c2 b.n 10001aa4 <_ftoa+0x20c> +10001d1e: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001d22: e7d7 b.n 10001cd4 <_ftoa+0x43c> +10001d24: 45ab cmp fp, r5 +10001d26: f63f aea3 bhi.w 10001a70 <_ftoa+0x1d8> +10001d2a: e6ae b.n 10001a8a <_ftoa+0x1f2> +10001d2c: f1bb 0f00 cmp.w fp, #0 +10001d30: f43f af7a beq.w 10001c28 <_ftoa+0x390> +10001d34: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d36: 2b00 cmp r3, #0 +10001d38: d09f beq.n 10001c7a <_ftoa+0x3e2> +10001d3a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d3e: 455d cmp r5, fp +10001d40: f4ff ae96 bcc.w 10001a70 <_ftoa+0x1d8> +10001d44: 2d20 cmp r5, #32 +10001d46: f47f af74 bne.w 10001c32 <_ftoa+0x39a> +10001d4a: e69e b.n 10001a8a <_ftoa+0x1f2> +10001d4c: 3fe00000 .word 0x3fe00000 +10001d50: 10003573 .word 0x10003573 +10001d54: 00000000 .word 0x00000000 + +10001d58 <_etoa>: +10001d58: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001d5c: b09f sub sp, #124 @ 0x7c +10001d5e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001d60: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001d64: 4607 mov r7, r0 +10001d66: 4693 mov fp, r2 +10001d68: 9108 str r1, [sp, #32] +10001d6a: 9309 str r3, [sp, #36] @ 0x24 +10001d6c: 4622 mov r2, r4 +10001d6e: 462b mov r3, r5 +10001d70: 4620 mov r0, r4 +10001d72: 4629 mov r1, r5 +10001d74: 960e str r6, [sp, #56] @ 0x38 +10001d76: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001d7a: f7ff fbeb bl 10001554 <__wrap___aeabi_dcmpun> +10001d7e: 2800 cmp r0, #0 +10001d80: f040 80be bne.w 10001f00 <_etoa+0x1a8> +10001d84: 4620 mov r0, r4 +10001d86: 4629 mov r1, r5 +10001d88: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d8c: 4b78 ldr r3, [pc, #480] @ (10001f70 <_etoa+0x218>) +10001d8e: f7ff fc2f bl 100015f0 <__wrap___aeabi_dcmpgt> +10001d92: 2800 cmp r0, #0 +10001d94: f040 80b4 bne.w 10001f00 <_etoa+0x1a8> +10001d98: 4620 mov r0, r4 +10001d9a: 4629 mov r1, r5 +10001d9c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001da0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001da4: f7ff fbe8 bl 10001578 <__wrap___aeabi_dcmplt> +10001da8: 2800 cmp r0, #0 +10001daa: f040 80a9 bne.w 10001f00 <_etoa+0x1a8> +10001dae: 4620 mov r0, r4 +10001db0: 4629 mov r1, r5 +10001db2: 2200 movs r2, #0 +10001db4: 2300 movs r3, #0 +10001db6: f7ff fbdf bl 10001578 <__wrap___aeabi_dcmplt> +10001dba: 2800 cmp r0, #0 +10001dbc: f040 81d5 bne.w 1000216a <_etoa+0x412> +10001dc0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001dc4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001dc8: 4690 mov r8, r2 +10001dca: 4699 mov r9, r3 +10001dcc: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001dd0: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001dd4: 920f str r2, [sp, #60] @ 0x3c +10001dd6: 9313 str r3, [sp, #76] @ 0x4c +10001dd8: f040 80a1 bne.w 10001f1e <_etoa+0x1c6> +10001ddc: ea58 0309 orrs.w r3, r8, r9 +10001de0: f040 80ca bne.w 10001f78 <_etoa+0x220> +10001de4: 2a00 cmp r2, #0 +10001de6: f040 81e3 bne.w 100021b0 <_etoa+0x458> +10001dea: 2306 movs r3, #6 +10001dec: 930e str r3, [sp, #56] @ 0x38 +10001dee: f016 0202 ands.w r2, r6, #2 +10001df2: 9210 str r2, [sp, #64] @ 0x40 +10001df4: f040 81d4 bne.w 100021a0 <_etoa+0x448> +10001df8: 4653 mov r3, sl +10001dfa: 2b04 cmp r3, #4 +10001dfc: bf38 it cc +10001dfe: 2304 movcc r3, #4 +10001e00: 920c str r2, [sp, #48] @ 0x30 +10001e02: 2204 movs r2, #4 +10001e04: 3b04 subs r3, #4 +10001e06: 9212 str r2, [sp, #72] @ 0x48 +10001e08: 930f str r3, [sp, #60] @ 0x3c +10001e0a: 4620 mov r0, r4 +10001e0c: 4629 mov r1, r5 +10001e0e: 2200 movs r2, #0 +10001e10: 2300 movs r3, #0 +10001e12: f7ff fbb1 bl 10001578 <__wrap___aeabi_dcmplt> +10001e16: 2800 cmp r0, #0 +10001e18: f040 81f3 bne.w 10002202 <_etoa+0x4aa> +10001e1c: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001e20: 9b0f ldr r3, [sp, #60] @ 0x3c +10001e22: 465a mov r2, fp +10001e24: 9303 str r3, [sp, #12] +10001e26: 9b0e ldr r3, [sp, #56] @ 0x38 +10001e28: ed8d 7b00 vstr d7, [sp] +10001e2c: 9302 str r3, [sp, #8] +10001e2e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001e32: 9304 str r3, [sp, #16] +10001e34: 4638 mov r0, r7 +10001e36: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e38: 9908 ldr r1, [sp, #32] +10001e3a: f7ff fd2d bl 10001898 <_ftoa> +10001e3e: 4602 mov r2, r0 +10001e40: f016 0f20 tst.w r6, #32 +10001e44: 9b09 ldr r3, [sp, #36] @ 0x24 +10001e46: 9908 ldr r1, [sp, #32] +10001e48: bf0c ite eq +10001e4a: 2065 moveq r0, #101 @ 0x65 +10001e4c: 2045 movne r0, #69 @ 0x45 +10001e4e: f102 0801 add.w r8, r2, #1 +10001e52: 47b8 blx r7 +10001e54: 9a0c ldr r2, [sp, #48] @ 0x30 +10001e56: 9b12 ldr r3, [sp, #72] @ 0x48 +10001e58: ac16 add r4, sp, #88 @ 0x58 +10001e5a: 1e5d subs r5, r3, #1 +10001e5c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001e60: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001e64: 0fd1 lsrs r1, r2, #31 +10001e66: 2600 movs r6, #0 +10001e68: 4622 mov r2, r4 +10001e6a: 4699 mov r9, r3 +10001e6c: f8df c104 ldr.w ip, [pc, #260] @ 10001f74 <_etoa+0x21c> +10001e70: e001 b.n 10001e76 <_etoa+0x11e> +10001e72: 2e20 cmp r6, #32 +10001e74: d010 beq.n 10001e98 <_etoa+0x140> +10001e76: 46ce mov lr, r9 +10001e78: fbac 3009 umull r3, r0, ip, r9 +10001e7c: 08c0 lsrs r0, r0, #3 +10001e7e: eb00 0380 add.w r3, r0, r0, lsl #2 +10001e82: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001e86: 3330 adds r3, #48 @ 0x30 +10001e88: f1be 0f09 cmp.w lr, #9 +10001e8c: 4681 mov r9, r0 +10001e8e: f106 0601 add.w r6, r6, #1 +10001e92: f802 3b01 strb.w r3, [r2], #1 +10001e96: d8ec bhi.n 10001e72 <_etoa+0x11a> +10001e98: 2305 movs r3, #5 +10001e9a: 2000 movs r0, #0 +10001e9c: 9306 str r3, [sp, #24] +10001e9e: 230a movs r3, #10 +10001ea0: 9505 str r5, [sp, #20] +10001ea2: 9400 str r4, [sp, #0] +10001ea4: 9d09 ldr r5, [sp, #36] @ 0x24 +10001ea6: 9c08 ldr r4, [sp, #32] +10001ea8: 4642 mov r2, r8 +10001eaa: e9cd 3003 strd r3, r0, [sp, #12] +10001eae: e9cd 6101 strd r6, r1, [sp, #4] +10001eb2: 462b mov r3, r5 +10001eb4: 4621 mov r1, r4 +10001eb6: 4638 mov r0, r7 +10001eb8: f7ff fbfa bl 100016b0 <_ntoa_format> +10001ebc: 9a10 ldr r2, [sp, #64] @ 0x40 +10001ebe: 4680 mov r8, r0 +10001ec0: b1d2 cbz r2, 10001ef8 <_etoa+0x1a0> +10001ec2: eba0 060b sub.w r6, r0, fp +10001ec6: 45b2 cmp sl, r6 +10001ec8: d916 bls.n 10001ef8 <_etoa+0x1a0> +10001eca: eb0b 0206 add.w r2, fp, r6 +10001ece: 462b mov r3, r5 +10001ed0: 4621 mov r1, r4 +10001ed2: 2020 movs r0, #32 +10001ed4: 3601 adds r6, #1 +10001ed6: 47b8 blx r7 +10001ed8: 45b2 cmp sl, r6 +10001eda: d8f6 bhi.n 10001eca <_etoa+0x172> +10001edc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10001ee0: 4453 add r3, sl +10001ee2: f1cb 0201 rsb r2, fp, #1 +10001ee6: eba3 0308 sub.w r3, r3, r8 +10001eea: 4442 add r2, r8 +10001eec: 4592 cmp sl, r2 +10001eee: bf38 it cc +10001ef0: 2300 movcc r3, #0 +10001ef2: f108 0801 add.w r8, r8, #1 +10001ef6: 4498 add r8, r3 +10001ef8: 4640 mov r0, r8 +10001efa: b01f add sp, #124 @ 0x7c +10001efc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001f00: 465a mov r2, fp +10001f02: 4638 mov r0, r7 +10001f04: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10001f08: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10001f0c: 9c0e ldr r4, [sp, #56] @ 0x38 +10001f0e: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f10: 9908 ldr r1, [sp, #32] +10001f12: 942a str r4, [sp, #168] @ 0xa8 +10001f14: b01f add sp, #124 @ 0x7c +10001f16: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f1a: f7ff bcbd b.w 10001898 <_ftoa> +10001f1e: ea58 0309 orrs.w r3, r8, r9 +10001f22: d12b bne.n 10001f7c <_etoa+0x224> +10001f24: 2a00 cmp r2, #0 +10001f26: f43f af62 beq.w 10001dee <_etoa+0x96> +10001f2a: 2300 movs r3, #0 +10001f2c: 930c str r3, [sp, #48] @ 0x30 +10001f2e: 9b0e ldr r3, [sp, #56] @ 0x38 +10001f30: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f32: 4293 cmp r3, r2 +10001f34: f300 81b9 bgt.w 100022aa <_etoa+0x552> +10001f38: f04f 0800 mov.w r8, #0 +10001f3c: 4620 mov r0, r4 +10001f3e: 4629 mov r1, r5 +10001f40: 2200 movs r2, #0 +10001f42: 2300 movs r3, #0 +10001f44: f7ff fb18 bl 10001578 <__wrap___aeabi_dcmplt> +10001f48: 2800 cmp r0, #0 +10001f4a: f040 8113 bne.w 10002174 <_etoa+0x41c> +10001f4e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001f52: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10001f56: f446 6680 orr.w r6, r6, #1024 @ 0x400 +10001f5a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +10001f5e: 465a mov r2, fp +10001f60: 4638 mov r0, r7 +10001f62: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10001f66: 9b09 ldr r3, [sp, #36] @ 0x24 +10001f68: 9908 ldr r1, [sp, #32] +10001f6a: 962c str r6, [sp, #176] @ 0xb0 +10001f6c: e7d2 b.n 10001f14 <_etoa+0x1bc> +10001f6e: bf00 nop +10001f70: 7fefffff .word 0x7fefffff +10001f74: cccccccd .word 0xcccccccd +10001f78: 2306 movs r3, #6 +10001f7a: 930e str r3, [sp, #56] @ 0x38 +10001f7c: f3c9 500a ubfx r0, r9, #20, #11 +10001f80: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10001f84: f7ff fa9e bl 100014c4 <__wrap___aeabi_i2d> +10001f88: a3c1 add r3, pc, #772 @ (adr r3, 10002290 <_etoa+0x538>) +10001f8a: e9d3 2300 ldrd r2, r3, [r3] +10001f8e: f7ff fa25 bl 100013dc <__wrap___aeabi_dmul> +10001f92: a3c1 add r3, pc, #772 @ (adr r3, 10002298 <_etoa+0x540>) +10001f94: e9d3 2300 ldrd r2, r3, [r3] +10001f98: f7ff f9f8 bl 1000138c <__wrap___aeabi_dadd> +10001f9c: f3c9 0913 ubfx r9, r9, #0, #20 +10001fa0: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10001fa4: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10001fa8: 4640 mov r0, r8 +10001faa: 2200 movs r2, #0 +10001fac: 4bb2 ldr r3, [pc, #712] @ (10002278 <_etoa+0x520>) +10001fae: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10001fb2: f7ff f9ff bl 100013b4 <__wrap___aeabi_dsub> +10001fb6: a3a4 add r3, pc, #656 @ (adr r3, 10002248 <_etoa+0x4f0>) +10001fb8: e9d3 2300 ldrd r2, r3, [r3] +10001fbc: f7ff fa0e bl 100013dc <__wrap___aeabi_dmul> +10001fc0: 4602 mov r2, r0 +10001fc2: 460b mov r3, r1 +10001fc4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10001fc8: f7ff f9e0 bl 1000138c <__wrap___aeabi_dadd> +10001fcc: f7ff fa9e bl 1000150c <__wrap___aeabi_d2iz> +10001fd0: 900c str r0, [sp, #48] @ 0x30 +10001fd2: f7ff fa77 bl 100014c4 <__wrap___aeabi_i2d> +10001fd6: a39e add r3, pc, #632 @ (adr r3, 10002250 <_etoa+0x4f8>) +10001fd8: e9d3 2300 ldrd r2, r3, [r3] +10001fdc: 4680 mov r8, r0 +10001fde: 4689 mov r9, r1 +10001fe0: f7ff f9fc bl 100013dc <__wrap___aeabi_dmul> +10001fe4: 2200 movs r2, #0 +10001fe6: 4ba5 ldr r3, [pc, #660] @ (1000227c <_etoa+0x524>) +10001fe8: f7ff f9d0 bl 1000138c <__wrap___aeabi_dadd> +10001fec: f7ff fa8e bl 1000150c <__wrap___aeabi_d2iz> +10001ff0: 4603 mov r3, r0 +10001ff2: 4649 mov r1, r9 +10001ff4: 4640 mov r0, r8 +10001ff6: 9312 str r3, [sp, #72] @ 0x48 +10001ff8: a397 add r3, pc, #604 @ (adr r3, 10002258 <_etoa+0x500>) +10001ffa: e9d3 2300 ldrd r2, r3, [r3] +10001ffe: f7ff f9ed bl 100013dc <__wrap___aeabi_dmul> +10002002: 4680 mov r8, r0 +10002004: 9812 ldr r0, [sp, #72] @ 0x48 +10002006: 4689 mov r9, r1 +10002008: f7ff fa5c bl 100014c4 <__wrap___aeabi_i2d> +1000200c: a394 add r3, pc, #592 @ (adr r3, 10002260 <_etoa+0x508>) +1000200e: e9d3 2300 ldrd r2, r3, [r3] +10002012: f7ff f9e3 bl 100013dc <__wrap___aeabi_dmul> +10002016: 4602 mov r2, r0 +10002018: 460b mov r3, r1 +1000201a: 4640 mov r0, r8 +1000201c: 4649 mov r1, r9 +1000201e: f7ff f9c9 bl 100013b4 <__wrap___aeabi_dsub> +10002022: 4602 mov r2, r0 +10002024: 460b mov r3, r1 +10002026: 4680 mov r8, r0 +10002028: 4689 mov r9, r1 +1000202a: f7ff f9d7 bl 100013dc <__wrap___aeabi_dmul> +1000202e: 4642 mov r2, r8 +10002030: 464b mov r3, r9 +10002032: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002036: 4640 mov r0, r8 +10002038: 4649 mov r1, r9 +1000203a: f7ff f9a7 bl 1000138c <__wrap___aeabi_dadd> +1000203e: 2200 movs r2, #0 +10002040: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10002044: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002048: 4b8d ldr r3, [pc, #564] @ (10002280 <_etoa+0x528>) +1000204a: f7ff f9ed bl 10001428 <__wrap___aeabi_ddiv> +1000204e: 2200 movs r2, #0 +10002050: 4b8c ldr r3, [pc, #560] @ (10002284 <_etoa+0x52c>) +10002052: f7ff f99b bl 1000138c <__wrap___aeabi_dadd> +10002056: 4602 mov r2, r0 +10002058: 460b mov r3, r1 +1000205a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000205e: f7ff f9e3 bl 10001428 <__wrap___aeabi_ddiv> +10002062: 2200 movs r2, #0 +10002064: 4b88 ldr r3, [pc, #544] @ (10002288 <_etoa+0x530>) +10002066: f7ff f991 bl 1000138c <__wrap___aeabi_dadd> +1000206a: 4602 mov r2, r0 +1000206c: 460b mov r3, r1 +1000206e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002072: f7ff f9d9 bl 10001428 <__wrap___aeabi_ddiv> +10002076: 4642 mov r2, r8 +10002078: 464b mov r3, r9 +1000207a: 4680 mov r8, r0 +1000207c: 4689 mov r9, r1 +1000207e: 2000 movs r0, #0 +10002080: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002084: f7ff f996 bl 100013b4 <__wrap___aeabi_dsub> +10002088: 4602 mov r2, r0 +1000208a: 460b mov r3, r1 +1000208c: 4640 mov r0, r8 +1000208e: 4649 mov r1, r9 +10002090: f7ff f97c bl 1000138c <__wrap___aeabi_dadd> +10002094: 4602 mov r2, r0 +10002096: 460b mov r3, r1 +10002098: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000209c: f7ff f9c4 bl 10001428 <__wrap___aeabi_ddiv> +100020a0: 2200 movs r2, #0 +100020a2: 4b7a ldr r3, [pc, #488] @ (1000228c <_etoa+0x534>) +100020a4: f7ff f972 bl 1000138c <__wrap___aeabi_dadd> +100020a8: 9b12 ldr r3, [sp, #72] @ 0x48 +100020aa: 2200 movs r2, #0 +100020ac: f203 3cff addw ip, r3, #1023 @ 0x3ff +100020b0: ea4f 530c mov.w r3, ip, lsl #20 +100020b4: f7ff f992 bl 100013dc <__wrap___aeabi_dmul> +100020b8: 4680 mov r8, r0 +100020ba: 4689 mov r9, r1 +100020bc: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100020c0: 4642 mov r2, r8 +100020c2: 464b mov r3, r9 +100020c4: f7ff fa58 bl 10001578 <__wrap___aeabi_dcmplt> +100020c8: b150 cbz r0, 100020e0 <_etoa+0x388> +100020ca: 9b0c ldr r3, [sp, #48] @ 0x30 +100020cc: 4640 mov r0, r8 +100020ce: 3b01 subs r3, #1 +100020d0: 4649 mov r1, r9 +100020d2: 930c str r3, [sp, #48] @ 0x30 +100020d4: 2200 movs r2, #0 +100020d6: 4b6b ldr r3, [pc, #428] @ (10002284 <_etoa+0x52c>) +100020d8: f7ff f9a6 bl 10001428 <__wrap___aeabi_ddiv> +100020dc: 4680 mov r8, r0 +100020de: 4689 mov r9, r1 +100020e0: 9a0c ldr r2, [sp, #48] @ 0x30 +100020e2: 4643 mov r3, r8 +100020e4: 3263 adds r2, #99 @ 0x63 +100020e6: 2ac6 cmp r2, #198 @ 0xc6 +100020e8: f006 0202 and.w r2, r6, #2 +100020ec: 9210 str r2, [sp, #64] @ 0x40 +100020ee: 4649 mov r1, r9 +100020f0: 9a0f ldr r2, [sp, #60] @ 0x3c +100020f2: d82c bhi.n 1000214e <_etoa+0x3f6> +100020f4: 2a00 cmp r2, #0 +100020f6: d05e beq.n 100021b6 <_etoa+0x45e> +100020f8: 2204 movs r2, #4 +100020fa: 9212 str r2, [sp, #72] @ 0x48 +100020fc: 430b orrs r3, r1 +100020fe: f43f af16 beq.w 10001f2e <_etoa+0x1d6> +10002102: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002106: a358 add r3, pc, #352 @ (adr r3, 10002268 <_etoa+0x510>) +10002108: e9d3 2300 ldrd r2, r3, [r3] +1000210c: f7ff fa5c bl 100015c8 <__wrap___aeabi_dcmpge> +10002110: b148 cbz r0, 10002126 <_etoa+0x3ce> +10002112: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002116: a356 add r3, pc, #344 @ (adr r3, 10002270 <_etoa+0x518>) +10002118: e9d3 2300 ldrd r2, r3, [r3] +1000211c: f7ff fa2c bl 10001578 <__wrap___aeabi_dcmplt> +10002120: 2800 cmp r0, #0 +10002122: f47f af04 bne.w 10001f2e <_etoa+0x1d6> +10002126: 9b0e ldr r3, [sp, #56] @ 0x38 +10002128: 2b00 cmp r3, #0 +1000212a: d050 beq.n 100021ce <_etoa+0x476> +1000212c: 9a13 ldr r2, [sp, #76] @ 0x4c +1000212e: 2a00 cmp r2, #0 +10002130: d07d beq.n 1000222e <_etoa+0x4d6> +10002132: 3b01 subs r3, #1 +10002134: 930e str r3, [sp, #56] @ 0x38 +10002136: 9b12 ldr r3, [sp, #72] @ 0x48 +10002138: 459a cmp sl, r3 +1000213a: d905 bls.n 10002148 <_etoa+0x3f0> +1000213c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000213e: 2b00 cmp r3, #0 +10002140: f000 80ae beq.w 100022a0 <_etoa+0x548> +10002144: 2302 movs r3, #2 +10002146: 9310 str r3, [sp, #64] @ 0x40 +10002148: 2300 movs r3, #0 +1000214a: 930f str r3, [sp, #60] @ 0x3c +1000214c: e044 b.n 100021d8 <_etoa+0x480> +1000214e: bb22 cbnz r2, 1000219a <_etoa+0x442> +10002150: f1ba 0f05 cmp.w sl, #5 +10002154: d94f bls.n 100021f6 <_etoa+0x49e> +10002156: f006 0302 and.w r3, r6, #2 +1000215a: 2b00 cmp r3, #0 +1000215c: d149 bne.n 100021f2 <_etoa+0x49a> +1000215e: 2305 movs r3, #5 +10002160: 9312 str r3, [sp, #72] @ 0x48 +10002162: f1aa 0305 sub.w r3, sl, #5 +10002166: 930f str r3, [sp, #60] @ 0x3c +10002168: e03a b.n 100021e0 <_etoa+0x488> +1000216a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000216e: 940a str r4, [sp, #40] @ 0x28 +10002170: 930b str r3, [sp, #44] @ 0x2c +10002172: e627 b.n 10001dc4 <_etoa+0x6c> +10002174: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002178: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000217c: 4638 mov r0, r7 +1000217e: 962c str r6, [sp, #176] @ 0xb0 +10002180: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002184: 4634 mov r4, r6 +10002186: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000218a: 465a mov r2, fp +1000218c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002190: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002194: 9b09 ldr r3, [sp, #36] @ 0x24 +10002196: 9908 ldr r1, [sp, #32] +10002198: e6bc b.n 10001f14 <_etoa+0x1bc> +1000219a: 2205 movs r2, #5 +1000219c: 9212 str r2, [sp, #72] @ 0x48 +1000219e: e7ad b.n 100020fc <_etoa+0x3a4> +100021a0: 2300 movs r3, #0 +100021a2: 2202 movs r2, #2 +100021a4: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +100021a8: 2204 movs r2, #4 +100021aa: 930c str r3, [sp, #48] @ 0x30 +100021ac: 9212 str r2, [sp, #72] @ 0x48 +100021ae: e62c b.n 10001e0a <_etoa+0xb2> +100021b0: f04f 0805 mov.w r8, #5 +100021b4: e6c2 b.n 10001f3c <_etoa+0x1e4> +100021b6: f1ba 0f04 cmp.w sl, #4 +100021ba: d91f bls.n 100021fc <_etoa+0x4a4> +100021bc: 9b10 ldr r3, [sp, #64] @ 0x40 +100021be: 2b00 cmp r3, #0 +100021c0: d178 bne.n 100022b4 <_etoa+0x55c> +100021c2: 2304 movs r3, #4 +100021c4: 9312 str r3, [sp, #72] @ 0x48 +100021c6: f1aa 0304 sub.w r3, sl, #4 +100021ca: 930f str r3, [sp, #60] @ 0x3c +100021cc: e004 b.n 100021d8 <_etoa+0x480> +100021ce: 9b12 ldr r3, [sp, #72] @ 0x48 +100021d0: 459a cmp sl, r3 +100021d2: d831 bhi.n 10002238 <_etoa+0x4e0> +100021d4: 9b0e ldr r3, [sp, #56] @ 0x38 +100021d6: 930f str r3, [sp, #60] @ 0x3c +100021d8: 9b0c ldr r3, [sp, #48] @ 0x30 +100021da: 2b00 cmp r3, #0 +100021dc: f43f ae15 beq.w 10001e0a <_etoa+0xb2> +100021e0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100021e4: 4642 mov r2, r8 +100021e6: 464b mov r3, r9 +100021e8: f7ff f91e bl 10001428 <__wrap___aeabi_ddiv> +100021ec: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100021f0: e60b b.n 10001e0a <_etoa+0xb2> +100021f2: 2302 movs r3, #2 +100021f4: 9310 str r3, [sp, #64] @ 0x40 +100021f6: 2305 movs r3, #5 +100021f8: 9312 str r3, [sp, #72] @ 0x48 +100021fa: e7f1 b.n 100021e0 <_etoa+0x488> +100021fc: 2304 movs r3, #4 +100021fe: 9312 str r3, [sp, #72] @ 0x48 +10002200: e7ea b.n 100021d8 <_etoa+0x480> +10002202: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +10002206: 46a0 mov r8, r4 +10002208: 9b0f ldr r3, [sp, #60] @ 0x3c +1000220a: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +1000220e: 9303 str r3, [sp, #12] +10002210: 9b0e ldr r3, [sp, #56] @ 0x38 +10002212: 465a mov r2, fp +10002214: 9302 str r3, [sp, #8] +10002216: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1000221a: 9304 str r3, [sp, #16] +1000221c: 4638 mov r0, r7 +1000221e: e9cd 8900 strd r8, r9, [sp] +10002222: 9b09 ldr r3, [sp, #36] @ 0x24 +10002224: 9908 ldr r1, [sp, #32] +10002226: f7ff fb37 bl 10001898 <_ftoa> +1000222a: 4602 mov r2, r0 +1000222c: e608 b.n 10001e40 <_etoa+0xe8> +1000222e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002230: 459a cmp sl, r3 +10002232: d844 bhi.n 100022be <_etoa+0x566> +10002234: 920f str r2, [sp, #60] @ 0x3c +10002236: e7cf b.n 100021d8 <_etoa+0x480> +10002238: 9b10 ldr r3, [sp, #64] @ 0x40 +1000223a: b38b cbz r3, 100022a0 <_etoa+0x548> +1000223c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000223e: 930f str r3, [sp, #60] @ 0x3c +10002240: 2302 movs r3, #2 +10002242: 9310 str r3, [sp, #64] @ 0x40 +10002244: e7c8 b.n 100021d8 <_etoa+0x480> +10002246: bf00 nop +10002248: 636f4361 .word 0x636f4361 +1000224c: 3fd287a7 .word 0x3fd287a7 +10002250: 0979a371 .word 0x0979a371 +10002254: 400a934f .word 0x400a934f +10002258: bbb55516 .word 0xbbb55516 +1000225c: 40026bb1 .word 0x40026bb1 +10002260: fefa39ef .word 0xfefa39ef +10002264: 3fe62e42 .word 0x3fe62e42 +10002268: eb1c432d .word 0xeb1c432d +1000226c: 3f1a36e2 .word 0x3f1a36e2 +10002270: 00000000 .word 0x00000000 +10002274: 412e8480 .word 0x412e8480 +10002278: 3ff80000 .word 0x3ff80000 +1000227c: 3fe00000 .word 0x3fe00000 +10002280: 402c0000 .word 0x402c0000 +10002284: 40240000 .word 0x40240000 +10002288: 40180000 .word 0x40180000 +1000228c: 3ff00000 .word 0x3ff00000 +10002290: 509f79fb .word 0x509f79fb +10002294: 3fd34413 .word 0x3fd34413 +10002298: 8b60c8b3 .word 0x8b60c8b3 +1000229c: 3fc68a28 .word 0x3fc68a28 +100022a0: 9b12 ldr r3, [sp, #72] @ 0x48 +100022a2: ebaa 0303 sub.w r3, sl, r3 +100022a6: 930f str r3, [sp, #60] @ 0x3c +100022a8: e796 b.n 100021d8 <_etoa+0x480> +100022aa: eba3 0802 sub.w r8, r3, r2 +100022ae: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100022b2: e643 b.n 10001f3c <_etoa+0x1e4> +100022b4: 2304 movs r3, #4 +100022b6: 9312 str r3, [sp, #72] @ 0x48 +100022b8: 2302 movs r3, #2 +100022ba: 9310 str r3, [sp, #64] @ 0x40 +100022bc: e78c b.n 100021d8 <_etoa+0x480> +100022be: 9b10 ldr r3, [sp, #64] @ 0x40 +100022c0: 2b00 cmp r3, #0 +100022c2: d0ed beq.n 100022a0 <_etoa+0x548> +100022c4: 2302 movs r3, #2 +100022c6: 920f str r2, [sp, #60] @ 0x3c +100022c8: 9310 str r3, [sp, #64] @ 0x40 +100022ca: e785 b.n 100021d8 <_etoa+0x480> + +100022cc <_vsnprintf>: +100022cc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100022d0: b09b sub sp, #108 @ 0x6c +100022d2: 9c24 ldr r4, [sp, #144] @ 0x90 +100022d4: 4d95 ldr r5, [pc, #596] @ (1000252c <_vsnprintf+0x260>) +100022d6: 940a str r4, [sp, #40] @ 0x28 +100022d8: 4c95 ldr r4, [pc, #596] @ (10002530 <_vsnprintf+0x264>) +100022da: f1b1 0a00 subs.w sl, r1, #0 +100022de: bf18 it ne +100022e0: 4683 movne fp, r0 +100022e2: 6025 str r5, [r4, #0] +100022e4: 7818 ldrb r0, [r3, #0] +100022e6: 4c93 ldr r4, [pc, #588] @ (10002534 <_vsnprintf+0x268>) +100022e8: 4691 mov r9, r2 +100022ea: bf08 it eq +100022ec: 46a3 moveq fp, r4 +100022ee: 9309 str r3, [sp, #36] @ 0x24 +100022f0: 2800 cmp r0, #0 +100022f2: f000 8293 beq.w 1000281c <_vsnprintf+0x550> +100022f6: f04f 0800 mov.w r8, #0 +100022fa: e00a b.n 10002312 <_vsnprintf+0x46> +100022fc: 4642 mov r2, r8 +100022fe: 464b mov r3, r9 +10002300: 4651 mov r1, sl +10002302: f108 0801 add.w r8, r8, #1 +10002306: 47d8 blx fp +10002308: 9b09 ldr r3, [sp, #36] @ 0x24 +1000230a: 7818 ldrb r0, [r3, #0] +1000230c: 2800 cmp r0, #0 +1000230e: f000 80ce beq.w 100024ae <_vsnprintf+0x1e2> +10002312: 9b09 ldr r3, [sp, #36] @ 0x24 +10002314: 2825 cmp r0, #37 @ 0x25 +10002316: f103 0301 add.w r3, r3, #1 +1000231a: 9309 str r3, [sp, #36] @ 0x24 +1000231c: d1ee bne.n 100022fc <_vsnprintf+0x30> +1000231e: 461c mov r4, r3 +10002320: 2300 movs r3, #0 +10002322: 4622 mov r2, r4 +10002324: f812 0b01 ldrb.w r0, [r2], #1 +10002328: f1a0 0120 sub.w r1, r0, #32 +1000232c: 2910 cmp r1, #16 +1000232e: d80a bhi.n 10002346 <_vsnprintf+0x7a> +10002330: e8df f001 tbb [pc, r1] +10002334: 3c090940 .word 0x3c090940 +10002338: 09090909 .word 0x09090909 +1000233c: 38090909 .word 0x38090909 +10002340: 09093409 .word 0x09093409 +10002344: 30 .byte 0x30 +10002345: 00 .byte 0x00 +10002346: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000234a: 2909 cmp r1, #9 +1000234c: 9409 str r4, [sp, #36] @ 0x24 +1000234e: f240 808a bls.w 10002466 <_vsnprintf+0x19a> +10002352: 282a cmp r0, #42 @ 0x2a +10002354: f000 80f0 beq.w 10002538 <_vsnprintf+0x26c> +10002358: 2500 movs r5, #0 +1000235a: 282e cmp r0, #46 @ 0x2e +1000235c: f000 8096 beq.w 1000248c <_vsnprintf+0x1c0> +10002360: 2600 movs r6, #0 +10002362: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002366: 2912 cmp r1, #18 +10002368: d82d bhi.n 100023c6 <_vsnprintf+0xfa> +1000236a: e8df f011 tbh [pc, r1, lsl #1] +1000236e: 0149 .short 0x0149 +10002370: 0143002c .word 0x0143002c +10002374: 0138002c .word 0x0138002c +10002378: 002c002c .word 0x002c002c +1000237c: 002c002c .word 0x002c002c +10002380: 002c002c .word 0x002c002c +10002384: 0027002c .word 0x0027002c +10002388: 002c002c .word 0x002c002c +1000238c: 002c002c .word 0x002c002c +10002390: 0027002c .word 0x0027002c +10002394: 4614 mov r4, r2 +10002396: f043 0301 orr.w r3, r3, #1 +1000239a: e7c2 b.n 10002322 <_vsnprintf+0x56> +1000239c: 4614 mov r4, r2 +1000239e: f043 0302 orr.w r3, r3, #2 +100023a2: e7be b.n 10002322 <_vsnprintf+0x56> +100023a4: 4614 mov r4, r2 +100023a6: f043 0304 orr.w r3, r3, #4 +100023aa: e7ba b.n 10002322 <_vsnprintf+0x56> +100023ac: 4614 mov r4, r2 +100023ae: f043 0310 orr.w r3, r3, #16 +100023b2: e7b6 b.n 10002322 <_vsnprintf+0x56> +100023b4: 4614 mov r4, r2 +100023b6: f043 0308 orr.w r3, r3, #8 +100023ba: e7b2 b.n 10002322 <_vsnprintf+0x56> +100023bc: 9909 ldr r1, [sp, #36] @ 0x24 +100023be: 7848 ldrb r0, [r1, #1] +100023c0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100023c4: 3201 adds r2, #1 +100023c6: 2867 cmp r0, #103 @ 0x67 +100023c8: 9209 str r2, [sp, #36] @ 0x24 +100023ca: d87e bhi.n 100024ca <_vsnprintf+0x1fe> +100023cc: 2824 cmp r0, #36 @ 0x24 +100023ce: f240 80c1 bls.w 10002554 <_vsnprintf+0x288> +100023d2: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100023d6: 2a42 cmp r2, #66 @ 0x42 +100023d8: f200 80bc bhi.w 10002554 <_vsnprintf+0x288> +100023dc: e8df f012 tbh [pc, r2, lsl #1] +100023e0: 00ba0150 .word 0x00ba0150 +100023e4: 00ba00ba .word 0x00ba00ba +100023e8: 00ba00ba .word 0x00ba00ba +100023ec: 00ba00ba .word 0x00ba00ba +100023f0: 00ba00ba .word 0x00ba00ba +100023f4: 00ba00ba .word 0x00ba00ba +100023f8: 00ba00ba .word 0x00ba00ba +100023fc: 00ba00ba .word 0x00ba00ba +10002400: 00ba00ba .word 0x00ba00ba +10002404: 00ba00ba .word 0x00ba00ba +10002408: 00ba00ba .word 0x00ba00ba +1000240c: 00ba00ba .word 0x00ba00ba +10002410: 00ba00ba .word 0x00ba00ba +10002414: 00ba00ba .word 0x00ba00ba +10002418: 00ba00ba .word 0x00ba00ba +1000241c: 00ba00ba .word 0x00ba00ba +10002420: 01370119 .word 0x01370119 +10002424: 00ba0119 .word 0x00ba0119 +10002428: 00ba00ba .word 0x00ba00ba +1000242c: 00ba00ba .word 0x00ba00ba +10002430: 00ba00ba .word 0x00ba00ba +10002434: 00ba00ba .word 0x00ba00ba +10002438: 00ba00ba .word 0x00ba00ba +1000243c: 00ba00ba .word 0x00ba00ba +10002440: 00ba00ba .word 0x00ba00ba +10002444: 01bc00ba .word 0x01bc00ba +10002448: 00ba00ba .word 0x00ba00ba +1000244c: 00ba00ba .word 0x00ba00ba +10002450: 00ba00ba .word 0x00ba00ba +10002454: 00ba00ba .word 0x00ba00ba +10002458: 01bc00ba .word 0x01bc00ba +1000245c: 01bc0158 .word 0x01bc0158 +10002460: 01370119 .word 0x01370119 +10002464: 0119 .short 0x0119 +10002466: 2500 movs r5, #0 +10002468: e000 b.n 1000246c <_vsnprintf+0x1a0> +1000246a: 3201 adds r2, #1 +1000246c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002470: eb00 0545 add.w r5, r0, r5, lsl #1 +10002474: 7810 ldrb r0, [r2, #0] +10002476: 3d30 subs r5, #48 @ 0x30 +10002478: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000247c: 2909 cmp r1, #9 +1000247e: d9f4 bls.n 1000246a <_vsnprintf+0x19e> +10002480: 282e cmp r0, #46 @ 0x2e +10002482: 9209 str r2, [sp, #36] @ 0x24 +10002484: f102 0201 add.w r2, r2, #1 +10002488: f47f af6a bne.w 10002360 <_vsnprintf+0x94> +1000248c: 9909 ldr r1, [sp, #36] @ 0x24 +1000248e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002492: 7848 ldrb r0, [r1, #1] +10002494: 4611 mov r1, r2 +10002496: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000249a: 2e09 cmp r6, #9 +1000249c: f240 8121 bls.w 100026e2 <_vsnprintf+0x416> +100024a0: 282a cmp r0, #42 @ 0x2a +100024a2: f000 812f beq.w 10002704 <_vsnprintf+0x438> +100024a6: 9209 str r2, [sp, #36] @ 0x24 +100024a8: 2600 movs r6, #0 +100024aa: 3201 adds r2, #1 +100024ac: e759 b.n 10002362 <_vsnprintf+0x96> +100024ae: 4644 mov r4, r8 +100024b0: 45c1 cmp r9, r8 +100024b2: d801 bhi.n 100024b8 <_vsnprintf+0x1ec> +100024b4: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100024b8: 464b mov r3, r9 +100024ba: 4642 mov r2, r8 +100024bc: 4651 mov r1, sl +100024be: 2000 movs r0, #0 +100024c0: 47d8 blx fp +100024c2: 4620 mov r0, r4 +100024c4: b01b add sp, #108 @ 0x6c +100024c6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100024ca: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100024ce: b2d2 uxtb r2, r2 +100024d0: 2a0f cmp r2, #15 +100024d2: d83f bhi.n 10002554 <_vsnprintf+0x288> +100024d4: 2101 movs r1, #1 +100024d6: f249 0741 movw r7, #36929 @ 0x9041 +100024da: 4091 lsls r1, r2 +100024dc: 4039 ands r1, r7 +100024de: f040 80f3 bne.w 100026c8 <_vsnprintf+0x3fc> +100024e2: 2a0a cmp r2, #10 +100024e4: d03d beq.n 10002562 <_vsnprintf+0x296> +100024e6: 2a07 cmp r2, #7 +100024e8: d134 bne.n 10002554 <_vsnprintf+0x288> +100024ea: 9d0a ldr r5, [sp, #40] @ 0x28 +100024ec: f855 2b04 ldr.w r2, [r5], #4 +100024f0: 2a00 cmp r2, #0 +100024f2: f000 8113 beq.w 1000271c <_vsnprintf+0x450> +100024f6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100024fa: ab12 add r3, sp, #72 @ 0x48 +100024fc: 461f mov r7, r3 +100024fe: 930b str r3, [sp, #44] @ 0x2c +10002500: e003 b.n 1000250a <_vsnprintf+0x23e> +10002502: 2920 cmp r1, #32 +10002504: f000 8114 beq.w 10002730 <_vsnprintf+0x464> +10002508: 461a mov r2, r3 +1000250a: f002 040f and.w r4, r2, #15 +1000250e: 4623 mov r3, r4 +10002510: 2c09 cmp r4, #9 +10002512: bf94 ite ls +10002514: 3330 addls r3, #48 @ 0x30 +10002516: 3337 addhi r3, #55 @ 0x37 +10002518: 2a0f cmp r2, #15 +1000251a: f807 3b01 strb.w r3, [r7], #1 +1000251e: f101 0101 add.w r1, r1, #1 +10002522: ea4f 1312 mov.w r3, r2, lsr #4 +10002526: d8ec bhi.n 10002502 <_vsnprintf+0x236> +10002528: e102 b.n 10002730 <_vsnprintf+0x464> +1000252a: bf00 nop +1000252c: 100022cd .word 0x100022cd +10002530: 2000080c .word 0x2000080c +10002534: 10001611 .word 0x10001611 +10002538: 990a ldr r1, [sp, #40] @ 0x28 +1000253a: 9809 ldr r0, [sp, #36] @ 0x24 +1000253c: f851 5b04 ldr.w r5, [r1], #4 +10002540: 7840 ldrb r0, [r0, #1] +10002542: 2d00 cmp r5, #0 +10002544: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002548: bfbc itt lt +1000254a: f043 0302 orrlt.w r3, r3, #2 +1000254e: 426d neglt r5, r5 +10002550: 3201 adds r2, #1 +10002552: e702 b.n 1000235a <_vsnprintf+0x8e> +10002554: 4642 mov r2, r8 +10002556: 464b mov r3, r9 +10002558: 4651 mov r1, sl +1000255a: f108 0801 add.w r8, r8, #1 +1000255e: 47d8 blx fp +10002560: e6d2 b.n 10002308 <_vsnprintf+0x3c> +10002562: 990a ldr r1, [sp, #40] @ 0x28 +10002564: 2e00 cmp r6, #0 +10002566: f851 7b04 ldr.w r7, [r1], #4 +1000256a: bf18 it ne +1000256c: 4632 movne r2, r6 +1000256e: 7838 ldrb r0, [r7, #0] +10002570: bf08 it eq +10002572: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002576: 2800 cmp r0, #0 +10002578: f000 837b beq.w 10002c72 <_vsnprintf+0x9a6> +1000257c: 18bc adds r4, r7, r2 +1000257e: 46a4 mov ip, r4 +10002580: 463a mov r2, r7 +10002582: e004 b.n 1000258e <_vsnprintf+0x2c2> +10002584: f812 4f01 ldrb.w r4, [r2, #1]! +10002588: 2c00 cmp r4, #0 +1000258a: f000 813f beq.w 1000280c <_vsnprintf+0x540> +1000258e: 4594 cmp ip, r2 +10002590: d1f8 bne.n 10002584 <_vsnprintf+0x2b8> +10002592: 4664 mov r4, ip +10002594: 1be4 subs r4, r4, r7 +10002596: 055a lsls r2, r3, #21 +10002598: f140 8122 bpl.w 100027e0 <_vsnprintf+0x514> +1000259c: 42b4 cmp r4, r6 +1000259e: bf28 it cs +100025a0: 4634 movcs r4, r6 +100025a2: f013 0302 ands.w r3, r3, #2 +100025a6: f000 8288 beq.w 10002aba <_vsnprintf+0x7ee> +100025aa: 2302 movs r3, #2 +100025ac: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100025b0: 4642 mov r2, r8 +100025b2: 461d mov r5, r3 +100025b4: 4446 add r6, r8 +100025b6: e008 b.n 100025ca <_vsnprintf+0x2fe> +100025b8: 464b mov r3, r9 +100025ba: 4651 mov r1, sl +100025bc: 47d8 blx fp +100025be: f817 0f01 ldrb.w r0, [r7, #1]! +100025c2: f108 0801 add.w r8, r8, #1 +100025c6: b110 cbz r0, 100025ce <_vsnprintf+0x302> +100025c8: 4642 mov r2, r8 +100025ca: 4546 cmp r6, r8 +100025cc: d1f4 bne.n 100025b8 <_vsnprintf+0x2ec> +100025ce: 462b mov r3, r5 +100025d0: 990b ldr r1, [sp, #44] @ 0x2c +100025d2: 9d0a ldr r5, [sp, #40] @ 0x28 +100025d4: 2b00 cmp r3, #0 +100025d6: f040 8141 bne.w 1000285c <_vsnprintf+0x590> +100025da: 910a str r1, [sp, #40] @ 0x28 +100025dc: e694 b.n 10002308 <_vsnprintf+0x3c> +100025de: 9909 ldr r1, [sp, #36] @ 0x24 +100025e0: 7848 ldrb r0, [r1, #1] +100025e2: 286c cmp r0, #108 @ 0x6c +100025e4: f47f aeec bne.w 100023c0 <_vsnprintf+0xf4> +100025e8: 460a mov r2, r1 +100025ea: 7888 ldrb r0, [r1, #2] +100025ec: f443 7340 orr.w r3, r3, #768 @ 0x300 +100025f0: 3203 adds r2, #3 +100025f2: e6e8 b.n 100023c6 <_vsnprintf+0xfa> +100025f4: 9909 ldr r1, [sp, #36] @ 0x24 +100025f6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100025fa: 7848 ldrb r0, [r1, #1] +100025fc: 3201 adds r2, #1 +100025fe: e6e2 b.n 100023c6 <_vsnprintf+0xfa> +10002600: 9909 ldr r1, [sp, #36] @ 0x24 +10002602: 7848 ldrb r0, [r1, #1] +10002604: 2868 cmp r0, #104 @ 0x68 +10002606: f000 8103 beq.w 10002810 <_vsnprintf+0x544> +1000260a: f043 0380 orr.w r3, r3, #128 @ 0x80 +1000260e: 3201 adds r2, #1 +10002610: e6d9 b.n 100023c6 <_vsnprintf+0xfa> +10002612: 2867 cmp r0, #103 @ 0x67 +10002614: f000 80d9 beq.w 100027ca <_vsnprintf+0x4fe> +10002618: 2847 cmp r0, #71 @ 0x47 +1000261a: f000 80dc beq.w 100027d6 <_vsnprintf+0x50a> +1000261e: 2845 cmp r0, #69 @ 0x45 +10002620: f000 80db beq.w 100027da <_vsnprintf+0x50e> +10002624: e9cd 5303 strd r5, r3, [sp, #12] +10002628: 9b0a ldr r3, [sp, #40] @ 0x28 +1000262a: 9602 str r6, [sp, #8] +1000262c: 3307 adds r3, #7 +1000262e: f023 0307 bic.w r3, r3, #7 +10002632: 461c mov r4, r3 +10002634: 4642 mov r2, r8 +10002636: e8f4 6702 ldrd r6, r7, [r4], #8 +1000263a: 464b mov r3, r9 +1000263c: 4651 mov r1, sl +1000263e: 4658 mov r0, fp +10002640: e9cd 6700 strd r6, r7, [sp] +10002644: 940a str r4, [sp, #40] @ 0x28 +10002646: f7ff fb87 bl 10001d58 <_etoa> +1000264a: 4680 mov r8, r0 +1000264c: e65c b.n 10002308 <_vsnprintf+0x3c> +1000264e: 2846 cmp r0, #70 @ 0x46 +10002650: bf08 it eq +10002652: f043 0320 orreq.w r3, r3, #32 +10002656: e9cd 5303 strd r5, r3, [sp, #12] +1000265a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000265c: 9602 str r6, [sp, #8] +1000265e: 3307 adds r3, #7 +10002660: f023 0307 bic.w r3, r3, #7 +10002664: 461c mov r4, r3 +10002666: 4642 mov r2, r8 +10002668: e8f4 6702 ldrd r6, r7, [r4], #8 +1000266c: 464b mov r3, r9 +1000266e: 4651 mov r1, sl +10002670: 4658 mov r0, fp +10002672: e9cd 6700 strd r6, r7, [sp] +10002676: 940a str r4, [sp, #40] @ 0x28 +10002678: f7ff f90e bl 10001898 <_ftoa> +1000267c: 4680 mov r8, r0 +1000267e: e643 b.n 10002308 <_vsnprintf+0x3c> +10002680: 4642 mov r2, r8 +10002682: 464b mov r3, r9 +10002684: 4651 mov r1, sl +10002686: 2025 movs r0, #37 @ 0x25 +10002688: f108 0801 add.w r8, r8, #1 +1000268c: 47d8 blx fp +1000268e: e63b b.n 10002308 <_vsnprintf+0x3c> +10002690: 9a0a ldr r2, [sp, #40] @ 0x28 +10002692: 0799 lsls r1, r3, #30 +10002694: f102 0404 add.w r4, r2, #4 +10002698: f108 0601 add.w r6, r8, #1 +1000269c: f140 80c6 bpl.w 1000282c <_vsnprintf+0x560> +100026a0: 7810 ldrb r0, [r2, #0] +100026a2: 464b mov r3, r9 +100026a4: 4642 mov r2, r8 +100026a6: 4651 mov r1, sl +100026a8: 47d8 blx fp +100026aa: 2d01 cmp r5, #1 +100026ac: bf88 it hi +100026ae: 44a8 addhi r8, r5 +100026b0: f240 81bd bls.w 10002a2e <_vsnprintf+0x762> +100026b4: 4632 mov r2, r6 +100026b6: 464b mov r3, r9 +100026b8: 4651 mov r1, sl +100026ba: 2020 movs r0, #32 +100026bc: 3601 adds r6, #1 +100026be: 47d8 blx fp +100026c0: 4546 cmp r6, r8 +100026c2: d1f7 bne.n 100026b4 <_vsnprintf+0x3e8> +100026c4: 940a str r4, [sp, #40] @ 0x28 +100026c6: e61f b.n 10002308 <_vsnprintf+0x3c> +100026c8: 286f cmp r0, #111 @ 0x6f +100026ca: f000 8081 beq.w 100027d0 <_vsnprintf+0x504> +100026ce: f240 8248 bls.w 10002b62 <_vsnprintf+0x896> +100026d2: 2878 cmp r0, #120 @ 0x78 +100026d4: f000 8190 beq.w 100029f8 <_vsnprintf+0x72c> +100026d8: 270a movs r7, #10 +100026da: f023 0310 bic.w r3, r3, #16 +100026de: 46bc mov ip, r7 +100026e0: e041 b.n 10002766 <_vsnprintf+0x49a> +100026e2: 2600 movs r6, #0 +100026e4: eb06 0686 add.w r6, r6, r6, lsl #2 +100026e8: eb00 0046 add.w r0, r0, r6, lsl #1 +100026ec: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100026f0: f811 0f01 ldrb.w r0, [r1, #1]! +100026f4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100026f8: 2a09 cmp r2, #9 +100026fa: d9f3 bls.n 100026e4 <_vsnprintf+0x418> +100026fc: 460a mov r2, r1 +100026fe: 9109 str r1, [sp, #36] @ 0x24 +10002700: 3201 adds r2, #1 +10002702: e62e b.n 10002362 <_vsnprintf+0x96> +10002704: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002708: f851 6b04 ldr.w r6, [r1], #4 +1000270c: 7890 ldrb r0, [r2, #2] +1000270e: 3202 adds r2, #2 +10002710: 9209 str r2, [sp, #36] @ 0x24 +10002712: 910a str r1, [sp, #40] @ 0x28 +10002714: 3201 adds r2, #1 +10002716: ea26 76e6 bic.w r6, r6, r6, asr #31 +1000271a: e622 b.n 10002362 <_vsnprintf+0x96> +1000271c: f023 0010 bic.w r0, r3, #16 +10002720: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002724: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002728: f43f aee7 beq.w 100024fa <_vsnprintf+0x22e> +1000272c: ab12 add r3, sp, #72 @ 0x48 +1000272e: 930b str r3, [sp, #44] @ 0x2c +10002730: 9b0b ldr r3, [sp, #44] @ 0x2c +10002732: 9006 str r0, [sp, #24] +10002734: 9300 str r3, [sp, #0] +10002736: 2308 movs r3, #8 +10002738: 2010 movs r0, #16 +1000273a: 9305 str r3, [sp, #20] +1000273c: 2300 movs r3, #0 +1000273e: 4642 mov r2, r8 +10002740: e9cd 3002 strd r3, r0, [sp, #8] +10002744: 9101 str r1, [sp, #4] +10002746: 464b mov r3, r9 +10002748: 4651 mov r1, sl +1000274a: 4658 mov r0, fp +1000274c: 9604 str r6, [sp, #16] +1000274e: f7fe ffaf bl 100016b0 <_ntoa_format> +10002752: 950a str r5, [sp, #40] @ 0x28 +10002754: 4680 mov r8, r0 +10002756: e5d7 b.n 10002308 <_vsnprintf+0x3c> +10002758: 2858 cmp r0, #88 @ 0x58 +1000275a: d062 beq.n 10002822 <_vsnprintf+0x556> +1000275c: 2862 cmp r0, #98 @ 0x62 +1000275e: f040 808f bne.w 10002880 <_vsnprintf+0x5b4> +10002762: 2702 movs r7, #2 +10002764: 46bc mov ip, r7 +10002766: f413 6080 ands.w r0, r3, #1024 @ 0x400 +1000276a: f000 80dd beq.w 10002928 <_vsnprintf+0x65c> +1000276e: f023 030d bic.w r3, r3, #13 +10002772: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002776: f040 8181 bne.w 10002a7c <_vsnprintf+0x7b0> +1000277a: 990a ldr r1, [sp, #40] @ 0x28 +1000277c: 1d0f adds r7, r1, #4 +1000277e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002782: f040 8237 bne.w 10002bf4 <_vsnprintf+0x928> +10002786: 065c lsls r4, r3, #25 +10002788: 9a0a ldr r2, [sp, #40] @ 0x28 +1000278a: f140 813b bpl.w 10002a04 <_vsnprintf+0x738> +1000278e: 7812 ldrb r2, [r2, #0] +10002790: 2a00 cmp r2, #0 +10002792: f040 814e bne.w 10002a32 <_vsnprintf+0x766> +10002796: f023 0310 bic.w r3, r3, #16 +1000279a: 2800 cmp r0, #0 +1000279c: f000 8149 beq.w 10002a32 <_vsnprintf+0x766> +100027a0: 4611 mov r1, r2 +100027a2: aa12 add r2, sp, #72 @ 0x48 +100027a4: 920b str r2, [sp, #44] @ 0x2c +100027a6: e9cd 5305 strd r5, r3, [sp, #20] +100027aa: e9cd c603 strd ip, r6, [sp, #12] +100027ae: 9101 str r1, [sp, #4] +100027b0: 9b0b ldr r3, [sp, #44] @ 0x2c +100027b2: 4642 mov r2, r8 +100027b4: 9300 str r3, [sp, #0] +100027b6: 2300 movs r3, #0 +100027b8: 4651 mov r1, sl +100027ba: 9302 str r3, [sp, #8] +100027bc: 4658 mov r0, fp +100027be: 464b mov r3, r9 +100027c0: f7fe ff76 bl 100016b0 <_ntoa_format> +100027c4: 970a str r7, [sp, #40] @ 0x28 +100027c6: 4680 mov r8, r0 +100027c8: e59e b.n 10002308 <_vsnprintf+0x3c> +100027ca: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027ce: e729 b.n 10002624 <_vsnprintf+0x358> +100027d0: 2708 movs r7, #8 +100027d2: 46bc mov ip, r7 +100027d4: e7c7 b.n 10002766 <_vsnprintf+0x49a> +100027d6: f443 6300 orr.w r3, r3, #2048 @ 0x800 +100027da: f043 0320 orr.w r3, r3, #32 +100027de: e721 b.n 10002624 <_vsnprintf+0x358> +100027e0: f013 0302 ands.w r3, r3, #2 +100027e4: f000 818e beq.w 10002b04 <_vsnprintf+0x838> +100027e8: 2302 movs r3, #2 +100027ea: 950a str r5, [sp, #40] @ 0x28 +100027ec: 461e mov r6, r3 +100027ee: 460d mov r5, r1 +100027f0: 4642 mov r2, r8 +100027f2: 464b mov r3, r9 +100027f4: 4651 mov r1, sl +100027f6: 47d8 blx fp +100027f8: f817 0f01 ldrb.w r0, [r7, #1]! +100027fc: f108 0801 add.w r8, r8, #1 +10002800: 2800 cmp r0, #0 +10002802: d1f5 bne.n 100027f0 <_vsnprintf+0x524> +10002804: 4629 mov r1, r5 +10002806: 4633 mov r3, r6 +10002808: 9d0a ldr r5, [sp, #40] @ 0x28 +1000280a: e6e3 b.n 100025d4 <_vsnprintf+0x308> +1000280c: 1bd4 subs r4, r2, r7 +1000280e: e6c2 b.n 10002596 <_vsnprintf+0x2ca> +10002810: 460a mov r2, r1 +10002812: 7888 ldrb r0, [r1, #2] +10002814: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002818: 3203 adds r2, #3 +1000281a: e5d4 b.n 100023c6 <_vsnprintf+0xfa> +1000281c: 4604 mov r4, r0 +1000281e: 4680 mov r8, r0 +10002820: e646 b.n 100024b0 <_vsnprintf+0x1e4> +10002822: 2710 movs r7, #16 +10002824: f043 0320 orr.w r3, r3, #32 +10002828: 46bc mov ip, r7 +1000282a: e79c b.n 10002766 <_vsnprintf+0x49a> +1000282c: 2d01 cmp r5, #1 +1000282e: f240 80f8 bls.w 10002a22 <_vsnprintf+0x756> +10002832: 4646 mov r6, r8 +10002834: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002838: 442f add r7, r5 +1000283a: 4632 mov r2, r6 +1000283c: 464b mov r3, r9 +1000283e: 4651 mov r1, sl +10002840: 2020 movs r0, #32 +10002842: 3601 adds r6, #1 +10002844: 47d8 blx fp +10002846: 42be cmp r6, r7 +10002848: d1f7 bne.n 1000283a <_vsnprintf+0x56e> +1000284a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000284c: 4632 mov r2, r6 +1000284e: 7818 ldrb r0, [r3, #0] +10002850: 4651 mov r1, sl +10002852: 464b mov r3, r9 +10002854: 47d8 blx fp +10002856: 44a8 add r8, r5 +10002858: 940a str r4, [sp, #40] @ 0x28 +1000285a: e555 b.n 10002308 <_vsnprintf+0x3c> +1000285c: 4646 mov r6, r8 +1000285e: 42a5 cmp r5, r4 +10002860: f67f aebb bls.w 100025da <_vsnprintf+0x30e> +10002864: 44a8 add r8, r5 +10002866: eba8 0804 sub.w r8, r8, r4 +1000286a: 460c mov r4, r1 +1000286c: 4632 mov r2, r6 +1000286e: 464b mov r3, r9 +10002870: 4651 mov r1, sl +10002872: 2020 movs r0, #32 +10002874: 3601 adds r6, #1 +10002876: 47d8 blx fp +10002878: 4546 cmp r6, r8 +1000287a: d1f7 bne.n 1000286c <_vsnprintf+0x5a0> +1000287c: 4621 mov r1, r4 +1000287e: e6ac b.n 100025da <_vsnprintf+0x30e> +10002880: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002884: f000 80bb beq.w 100029fe <_vsnprintf+0x732> +10002888: f44f 6280 mov.w r2, #1024 @ 0x400 +1000288c: f023 0c11 bic.w ip, r3, #17 +10002890: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002894: 9b0a ldr r3, [sp, #40] @ 0x28 +10002896: d14a bne.n 1000292e <_vsnprintf+0x662> +10002898: f41c 7080 ands.w r0, ip, #256 @ 0x100 +1000289c: f103 0404 add.w r4, r3, #4 +100028a0: f040 8134 bne.w 10002b0c <_vsnprintf+0x840> +100028a4: f01c 0f40 tst.w ip, #64 @ 0x40 +100028a8: f040 80a3 bne.w 100029f2 <_vsnprintf+0x726> +100028ac: f01c 0f80 tst.w ip, #128 @ 0x80 +100028b0: f000 81d3 beq.w 10002c5a <_vsnprintf+0x98e> +100028b4: f9b3 1000 ldrsh.w r1, [r3] +100028b8: ea81 77e1 eor.w r7, r1, r1, asr #31 +100028bc: eba7 77e1 sub.w r7, r7, r1, asr #31 +100028c0: b2bf uxth r7, r7 +100028c2: 0fcb lsrs r3, r1, #31 +100028c4: 2900 cmp r1, #0 +100028c6: f000 8156 beq.w 10002b76 <_vsnprintf+0x8aa> +100028ca: 463a mov r2, r7 +100028cc: a912 add r1, sp, #72 @ 0x48 +100028ce: 460f mov r7, r1 +100028d0: f8df e3d8 ldr.w lr, [pc, #984] @ 10002cac <_vsnprintf+0x9e0> +100028d4: 910b str r1, [sp, #44] @ 0x2c +100028d6: 930a str r3, [sp, #40] @ 0x28 +100028d8: 950c str r5, [sp, #48] @ 0x30 +100028da: e001 b.n 100028e0 <_vsnprintf+0x614> +100028dc: 2820 cmp r0, #32 +100028de: d00f beq.n 10002900 <_vsnprintf+0x634> +100028e0: 4615 mov r5, r2 +100028e2: fbae 1302 umull r1, r3, lr, r2 +100028e6: 08db lsrs r3, r3, #3 +100028e8: eb03 0183 add.w r1, r3, r3, lsl #2 +100028ec: eba2 0141 sub.w r1, r2, r1, lsl #1 +100028f0: 3130 adds r1, #48 @ 0x30 +100028f2: 2d09 cmp r5, #9 +100028f4: 461a mov r2, r3 +100028f6: f100 0001 add.w r0, r0, #1 +100028fa: f807 1b01 strb.w r1, [r7], #1 +100028fe: d8ed bhi.n 100028dc <_vsnprintf+0x610> +10002900: 9b0a ldr r3, [sp, #40] @ 0x28 +10002902: 9d0c ldr r5, [sp, #48] @ 0x30 +10002904: e9cd 5c05 strd r5, ip, [sp, #20] +10002908: e9cd 0301 strd r0, r3, [sp, #4] +1000290c: 9604 str r6, [sp, #16] +1000290e: 9b0b ldr r3, [sp, #44] @ 0x2c +10002910: 4642 mov r2, r8 +10002912: 9300 str r3, [sp, #0] +10002914: 230a movs r3, #10 +10002916: 4651 mov r1, sl +10002918: 9303 str r3, [sp, #12] +1000291a: 4658 mov r0, fp +1000291c: 464b mov r3, r9 +1000291e: f7fe fec7 bl 100016b0 <_ntoa_format> +10002922: 940a str r4, [sp, #40] @ 0x28 +10002924: 4680 mov r8, r0 +10002926: e4ef b.n 10002308 <_vsnprintf+0x3c> +10002928: f023 030c bic.w r3, r3, #12 +1000292c: e721 b.n 10002772 <_vsnprintf+0x4a6> +1000292e: 3307 adds r3, #7 +10002930: f023 0307 bic.w r3, r3, #7 +10002934: 4619 mov r1, r3 +10002936: 4608 mov r0, r1 +10002938: 685b ldr r3, [r3, #4] +1000293a: f850 1b08 ldr.w r1, [r0], #8 +1000293e: 0fdf lsrs r7, r3, #31 +10002940: 900a str r0, [sp, #40] @ 0x28 +10002942: ea51 0003 orrs.w r0, r1, r3 +10002946: d162 bne.n 10002a0e <_vsnprintf+0x742> +10002948: 2a00 cmp r2, #0 +1000294a: f040 819f bne.w 10002c8c <_vsnprintf+0x9c0> +1000294e: 4613 mov r3, r2 +10002950: 4611 mov r1, r2 +10002952: aa12 add r2, sp, #72 @ 0x48 +10002954: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002958: 2000 movs r0, #0 +1000295a: 4615 mov r5, r2 +1000295c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002960: f8df e348 ldr.w lr, [pc, #840] @ 10002cac <_vsnprintf+0x9e0> +10002964: 920b str r2, [sp, #44] @ 0x2c +10002966: e001 b.n 1000296c <_vsnprintf+0x6a0> +10002968: 2820 cmp r0, #32 +1000296a: d02d beq.n 100029c8 <_vsnprintf+0x6fc> +1000296c: 185a adds r2, r3, r1 +1000296e: f142 0200 adc.w r2, r2, #0 +10002972: fbae 7802 umull r7, r8, lr, r2 +10002976: f028 0703 bic.w r7, r8, #3 +1000297a: eb07 0798 add.w r7, r7, r8, lsr #2 +1000297e: 1bd2 subs r2, r2, r7 +10002980: 461e mov r6, r3 +10002982: 1a9b subs r3, r3, r2 +10002984: f161 0700 sbc.w r7, r1, #0 +10002988: 460c mov r4, r1 +1000298a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +1000298e: fb01 f103 mul.w r1, r1, r3 +10002992: fb0e 1107 mla r1, lr, r7, r1 +10002996: fba3 730e umull r7, r3, r3, lr +1000299a: 4419 add r1, r3 +1000299c: 2305 movs r3, #5 +1000299e: f007 0801 and.w r8, r7, #1 +100029a2: fba8 3803 umull r3, r8, r8, r3 +100029a6: 189b adds r3, r3, r2 +100029a8: 2e0a cmp r6, #10 +100029aa: f103 0330 add.w r3, r3, #48 @ 0x30 +100029ae: ea4f 0757 mov.w r7, r7, lsr #1 +100029b2: f174 0400 sbcs.w r4, r4, #0 +100029b6: f805 3b01 strb.w r3, [r5], #1 +100029ba: f100 0001 add.w r0, r0, #1 +100029be: ea47 73c1 orr.w r3, r7, r1, lsl #31 +100029c2: ea4f 0151 mov.w r1, r1, lsr #1 +100029c6: d2cf bcs.n 10002968 <_vsnprintf+0x69c> +100029c8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +100029cc: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +100029d0: 9b0b ldr r3, [sp, #44] @ 0x2c +100029d2: 4642 mov r2, r8 +100029d4: 9300 str r3, [sp, #0] +100029d6: 230a movs r3, #10 +100029d8: e9cd 5c05 strd r5, ip, [sp, #20] +100029dc: e9cd 0701 strd r0, r7, [sp, #4] +100029e0: 9604 str r6, [sp, #16] +100029e2: 9303 str r3, [sp, #12] +100029e4: 464b mov r3, r9 +100029e6: 4651 mov r1, sl +100029e8: 4658 mov r0, fp +100029ea: f7fe fe61 bl 100016b0 <_ntoa_format> +100029ee: 4680 mov r8, r0 +100029f0: e48a b.n 10002308 <_vsnprintf+0x3c> +100029f2: 7819 ldrb r1, [r3, #0] +100029f4: 460f mov r7, r1 +100029f6: e764 b.n 100028c2 <_vsnprintf+0x5f6> +100029f8: 2710 movs r7, #16 +100029fa: 46bc mov ip, r7 +100029fc: e6b3 b.n 10002766 <_vsnprintf+0x49a> +100029fe: f023 0c10 bic.w ip, r3, #16 +10002a02: e745 b.n 10002890 <_vsnprintf+0x5c4> +10002a04: 061c lsls r4, r3, #24 +10002a06: bf4c ite mi +10002a08: 8812 ldrhmi r2, [r2, #0] +10002a0a: 6812 ldrpl r2, [r2, #0] +10002a0c: e6c0 b.n 10002790 <_vsnprintf+0x4c4> +10002a0e: 460a mov r2, r1 +10002a10: 1e19 subs r1, r3, #0 +10002a12: db01 blt.n 10002a18 <_vsnprintf+0x74c> +10002a14: 4613 mov r3, r2 +10002a16: e79c b.n 10002952 <_vsnprintf+0x686> +10002a18: 4252 negs r2, r2 +10002a1a: 4613 mov r3, r2 +10002a1c: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002a20: e797 b.n 10002952 <_vsnprintf+0x686> +10002a22: 4613 mov r3, r2 +10002a24: 4651 mov r1, sl +10002a26: 7818 ldrb r0, [r3, #0] +10002a28: 4642 mov r2, r8 +10002a2a: 464b mov r3, r9 +10002a2c: 47d8 blx fp +10002a2e: 46b0 mov r8, r6 +10002a30: e648 b.n 100026c4 <_vsnprintf+0x3f8> +10002a32: f013 0f20 tst.w r3, #32 +10002a36: bf14 ite ne +10002a38: 2041 movne r0, #65 @ 0x41 +10002a3a: 2061 moveq r0, #97 @ 0x61 +10002a3c: ac12 add r4, sp, #72 @ 0x48 +10002a3e: 46a6 mov lr, r4 +10002a40: 940b str r4, [sp, #44] @ 0x2c +10002a42: 930a str r3, [sp, #40] @ 0x28 +10002a44: f1a0 040a sub.w r4, r0, #10 +10002a48: 950c str r5, [sp, #48] @ 0x30 +10002a4a: e002 b.n 10002a52 <_vsnprintf+0x786> +10002a4c: 2920 cmp r1, #32 +10002a4e: d012 beq.n 10002a76 <_vsnprintf+0x7aa> +10002a50: 462a mov r2, r5 +10002a52: fbb2 f5fc udiv r5, r2, ip +10002a56: fb0c 2015 mls r0, ip, r5, r2 +10002a5a: b2c3 uxtb r3, r0 +10002a5c: 2809 cmp r0, #9 +10002a5e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002a62: bf8a itet hi +10002a64: 191b addhi r3, r3, r4 +10002a66: b2c3 uxtbls r3, r0 +10002a68: b2db uxtbhi r3, r3 +10002a6a: 4562 cmp r2, ip +10002a6c: f80e 3b01 strb.w r3, [lr], #1 +10002a70: f101 0101 add.w r1, r1, #1 +10002a74: d2ea bcs.n 10002a4c <_vsnprintf+0x780> +10002a76: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a78: 9d0c ldr r5, [sp, #48] @ 0x30 +10002a7a: e694 b.n 100027a6 <_vsnprintf+0x4da> +10002a7c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a7e: 3207 adds r2, #7 +10002a80: f022 0207 bic.w r2, r2, #7 +10002a84: 6851 ldr r1, [r2, #4] +10002a86: f852 4b08 ldr.w r4, [r2], #8 +10002a8a: 468e mov lr, r1 +10002a8c: 920a str r2, [sp, #40] @ 0x28 +10002a8e: ea54 0201 orrs.w r2, r4, r1 +10002a92: d176 bne.n 10002b82 <_vsnprintf+0x8b6> +10002a94: f023 0310 bic.w r3, r3, #16 +10002a98: 2800 cmp r0, #0 +10002a9a: d072 beq.n 10002b82 <_vsnprintf+0x8b6> +10002a9c: 2200 movs r2, #0 +10002a9e: 4611 mov r1, r2 +10002aa0: aa12 add r2, sp, #72 @ 0x48 +10002aa2: 920b str r2, [sp, #44] @ 0x2c +10002aa4: e9cd 5305 strd r5, r3, [sp, #20] +10002aa8: 9b0b ldr r3, [sp, #44] @ 0x2c +10002aaa: 4642 mov r2, r8 +10002aac: 9300 str r3, [sp, #0] +10002aae: 2300 movs r3, #0 +10002ab0: e9cd c603 strd ip, r6, [sp, #12] +10002ab4: 9101 str r1, [sp, #4] +10002ab6: 9302 str r3, [sp, #8] +10002ab8: e794 b.n 100029e4 <_vsnprintf+0x718> +10002aba: 42a5 cmp r5, r4 +10002abc: bf98 it ls +10002abe: 3401 addls r4, #1 +10002ac0: f67f ad74 bls.w 100025ac <_vsnprintf+0x2e0> +10002ac4: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ac8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002acc: eb05 0208 add.w r2, r5, r8 +10002ad0: 461f mov r7, r3 +10002ad2: 460d mov r5, r1 +10002ad4: 1b14 subs r4, r2, r4 +10002ad6: 4642 mov r2, r8 +10002ad8: 464b mov r3, r9 +10002ada: 4651 mov r1, sl +10002adc: 2020 movs r0, #32 +10002ade: f108 0801 add.w r8, r8, #1 +10002ae2: 47d8 blx fp +10002ae4: 45a0 cmp r8, r4 +10002ae6: d1f6 bne.n 10002ad6 <_vsnprintf+0x80a> +10002ae8: 463b mov r3, r7 +10002aea: 9f0a ldr r7, [sp, #40] @ 0x28 +10002aec: 4629 mov r1, r5 +10002aee: 7838 ldrb r0, [r7, #0] +10002af0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002af2: 1c6c adds r4, r5, #1 +10002af4: 2800 cmp r0, #0 +10002af6: f43f ad70 beq.w 100025da <_vsnprintf+0x30e> +10002afa: 2b00 cmp r3, #0 +10002afc: f43f ae75 beq.w 100027ea <_vsnprintf+0x51e> +10002b00: 2300 movs r3, #0 +10002b02: e553 b.n 100025ac <_vsnprintf+0x2e0> +10002b04: 42a5 cmp r5, r4 +10002b06: d8df bhi.n 10002ac8 <_vsnprintf+0x7fc> +10002b08: 3401 adds r4, #1 +10002b0a: e66e b.n 100027ea <_vsnprintf+0x51e> +10002b0c: 6819 ldr r1, [r3, #0] +10002b0e: 0fcb lsrs r3, r1, #31 +10002b10: 2900 cmp r1, #0 +10002b12: f000 80a8 beq.w 10002c66 <_vsnprintf+0x99a> +10002b16: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002b1a: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002b1e: a912 add r1, sp, #72 @ 0x48 +10002b20: 4608 mov r0, r1 +10002b22: f8df e188 ldr.w lr, [pc, #392] @ 10002cac <_vsnprintf+0x9e0> +10002b26: 910b str r1, [sp, #44] @ 0x2c +10002b28: 930a str r3, [sp, #40] @ 0x28 +10002b2a: 950c str r5, [sp, #48] @ 0x30 +10002b2c: e001 b.n 10002b32 <_vsnprintf+0x866> +10002b2e: 2f20 cmp r7, #32 +10002b30: d00f beq.n 10002b52 <_vsnprintf+0x886> +10002b32: 4615 mov r5, r2 +10002b34: fbae 1302 umull r1, r3, lr, r2 +10002b38: 08db lsrs r3, r3, #3 +10002b3a: eb03 0183 add.w r1, r3, r3, lsl #2 +10002b3e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002b42: 3130 adds r1, #48 @ 0x30 +10002b44: 2d09 cmp r5, #9 +10002b46: 461a mov r2, r3 +10002b48: f107 0701 add.w r7, r7, #1 +10002b4c: f800 1b01 strb.w r1, [r0], #1 +10002b50: d8ed bhi.n 10002b2e <_vsnprintf+0x862> +10002b52: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b54: 9d0c ldr r5, [sp, #48] @ 0x30 +10002b56: e9cd 5c05 strd r5, ip, [sp, #20] +10002b5a: e9cd 7301 strd r7, r3, [sp, #4] +10002b5e: 9604 str r6, [sp, #16] +10002b60: e6d5 b.n 1000290e <_vsnprintf+0x642> +10002b62: 2869 cmp r0, #105 @ 0x69 +10002b64: f023 0c10 bic.w ip, r3, #16 +10002b68: f040 808c bne.w 10002c84 <_vsnprintf+0x9b8> +10002b6c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b70: f43f ae8e beq.w 10002890 <_vsnprintf+0x5c4> +10002b74: e688 b.n 10002888 <_vsnprintf+0x5bc> +10002b76: 2a00 cmp r2, #0 +10002b78: f43f aea8 beq.w 100028cc <_vsnprintf+0x600> +10002b7c: aa12 add r2, sp, #72 @ 0x48 +10002b7e: 920b str r2, [sp, #44] @ 0x2c +10002b80: e6c0 b.n 10002904 <_vsnprintf+0x638> +10002b82: f013 0f20 tst.w r3, #32 +10002b86: bf14 ite ne +10002b88: 2241 movne r2, #65 @ 0x41 +10002b8a: 2261 moveq r2, #97 @ 0x61 +10002b8c: 2000 movs r0, #0 +10002b8e: a912 add r1, sp, #72 @ 0x48 +10002b90: 3a0a subs r2, #10 +10002b92: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002b96: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002b9a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002b9e: 4606 mov r6, r0 +10002ba0: 4688 mov r8, r1 +10002ba2: 4675 mov r5, lr +10002ba4: 4693 mov fp, r2 +10002ba6: 910b str r1, [sp, #44] @ 0x2c +10002ba8: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002bac: e003 b.n 10002bb6 <_vsnprintf+0x8ea> +10002bae: 2e20 cmp r6, #32 +10002bb0: d017 beq.n 10002be2 <_vsnprintf+0x916> +10002bb2: 4604 mov r4, r0 +10002bb4: 460d mov r5, r1 +10002bb6: 4629 mov r1, r5 +10002bb8: 463a mov r2, r7 +10002bba: 2300 movs r3, #0 +10002bbc: 4620 mov r0, r4 +10002bbe: f000 fc47 bl 10003450 <____aeabi_uldivmod_veneer> +10002bc2: b2d2 uxtb r2, r2 +10002bc4: 2a09 cmp r2, #9 +10002bc6: f102 0330 add.w r3, r2, #48 @ 0x30 +10002bca: bf88 it hi +10002bcc: eb02 030b addhi.w r3, r2, fp +10002bd0: 42bc cmp r4, r7 +10002bd2: b2db uxtb r3, r3 +10002bd4: f175 0500 sbcs.w r5, r5, #0 +10002bd8: f808 3b01 strb.w r3, [r8], #1 +10002bdc: f106 0601 add.w r6, r6, #1 +10002be0: d2e5 bcs.n 10002bae <_vsnprintf+0x8e2> +10002be2: 4631 mov r1, r6 +10002be4: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002be8: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002bec: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002bf0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002bf2: e757 b.n 10002aa4 <_vsnprintf+0x7d8> +10002bf4: 990a ldr r1, [sp, #40] @ 0x28 +10002bf6: 6809 ldr r1, [r1, #0] +10002bf8: b951 cbnz r1, 10002c10 <_vsnprintf+0x944> +10002bfa: f023 0310 bic.w r3, r3, #16 +10002bfe: b138 cbz r0, 10002c10 <_vsnprintf+0x944> +10002c00: a912 add r1, sp, #72 @ 0x48 +10002c02: 910b str r1, [sp, #44] @ 0x2c +10002c04: e9cd 5305 strd r5, r3, [sp, #20] +10002c08: e9cd c603 strd ip, r6, [sp, #12] +10002c0c: 9201 str r2, [sp, #4] +10002c0e: e5cf b.n 100027b0 <_vsnprintf+0x4e4> +10002c10: f013 0f20 tst.w r3, #32 +10002c14: bf14 ite ne +10002c16: 2041 movne r0, #65 @ 0x41 +10002c18: 2061 moveq r0, #97 @ 0x61 +10002c1a: ac12 add r4, sp, #72 @ 0x48 +10002c1c: 46a6 mov lr, r4 +10002c1e: 940b str r4, [sp, #44] @ 0x2c +10002c20: 930a str r3, [sp, #40] @ 0x28 +10002c22: f1a0 040a sub.w r4, r0, #10 +10002c26: 950c str r5, [sp, #48] @ 0x30 +10002c28: e002 b.n 10002c30 <_vsnprintf+0x964> +10002c2a: 2a20 cmp r2, #32 +10002c2c: d012 beq.n 10002c54 <_vsnprintf+0x988> +10002c2e: 4629 mov r1, r5 +10002c30: fbb1 f5fc udiv r5, r1, ip +10002c34: fb0c 1015 mls r0, ip, r5, r1 +10002c38: b2c3 uxtb r3, r0 +10002c3a: 2809 cmp r0, #9 +10002c3c: f103 0030 add.w r0, r3, #48 @ 0x30 +10002c40: bf8a itet hi +10002c42: 191b addhi r3, r3, r4 +10002c44: b2c3 uxtbls r3, r0 +10002c46: b2db uxtbhi r3, r3 +10002c48: 4561 cmp r1, ip +10002c4a: f80e 3b01 strb.w r3, [lr], #1 +10002c4e: f102 0201 add.w r2, r2, #1 +10002c52: d2ea bcs.n 10002c2a <_vsnprintf+0x95e> +10002c54: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c56: 9d0c ldr r5, [sp, #48] @ 0x30 +10002c58: e7d4 b.n 10002c04 <_vsnprintf+0x938> +10002c5a: 6819 ldr r1, [r3, #0] +10002c5c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002c60: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002c64: e62d b.n 100028c2 <_vsnprintf+0x5f6> +10002c66: 2a00 cmp r2, #0 +10002c68: f43f af59 beq.w 10002b1e <_vsnprintf+0x852> +10002c6c: aa12 add r2, sp, #72 @ 0x48 +10002c6e: 920b str r2, [sp, #44] @ 0x2c +10002c70: e771 b.n 10002b56 <_vsnprintf+0x88a> +10002c72: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002c76: d00d beq.n 10002c94 <_vsnprintf+0x9c8> +10002c78: f013 0402 ands.w r4, r3, #2 +10002c7c: d012 beq.n 10002ca4 <_vsnprintf+0x9d8> +10002c7e: 4604 mov r4, r0 +10002c80: 4646 mov r6, r8 +10002c82: e5ec b.n 1000285e <_vsnprintf+0x592> +10002c84: 270a movs r7, #10 +10002c86: 4663 mov r3, ip +10002c88: 46bc mov ip, r7 +10002c8a: e56c b.n 10002766 <_vsnprintf+0x49a> +10002c8c: ab12 add r3, sp, #72 @ 0x48 +10002c8e: 2000 movs r0, #0 +10002c90: 930b str r3, [sp, #44] @ 0x2c +10002c92: e69d b.n 100029d0 <_vsnprintf+0x704> +10002c94: f013 0302 ands.w r3, r3, #2 +10002c98: f47f ade0 bne.w 1000285c <_vsnprintf+0x590> +10002c9c: 2d00 cmp r5, #0 +10002c9e: f47f af13 bne.w 10002ac8 <_vsnprintf+0x7fc> +10002ca2: e49a b.n 100025da <_vsnprintf+0x30e> +10002ca4: 2d00 cmp r5, #0 +10002ca6: f47f af0d bne.w 10002ac4 <_vsnprintf+0x7f8> +10002caa: e496 b.n 100025da <_vsnprintf+0x30e> +10002cac: cccccccd .word 0xcccccccd + +10002cb0 : +10002cb0: b570 push {r4, r5, r6, lr} +10002cb2: 4694 mov ip, r2 +10002cb4: 461e mov r6, r3 +10002cb6: 4605 mov r5, r0 +10002cb8: 460c mov r4, r1 +10002cba: b084 sub sp, #16 +10002cbc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002cc0: 4663 mov r3, ip +10002cc2: a902 add r1, sp, #8 +10002cc4: 9600 str r6, [sp, #0] +10002cc6: 4803 ldr r0, [pc, #12] @ (10002cd4 ) +10002cc8: e9cd 5402 strd r5, r4, [sp, #8] +10002ccc: f7ff fafe bl 100022cc <_vsnprintf> +10002cd0: b004 add sp, #16 +10002cd2: bd70 pop {r4, r5, r6, pc} +10002cd4: 1000188d .word 0x1000188d + +10002cd8 : +10002cd8: b510 push {r4, lr} +10002cda: 4b09 ldr r3, [pc, #36] @ (10002d00 ) +10002cdc: b084 sub sp, #16 +10002cde: 681c ldr r4, [r3, #0] +10002ce0: b14c cbz r4, 10002cf6 +10002ce2: 4603 mov r3, r0 +10002ce4: 9100 str r1, [sp, #0] +10002ce6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002cea: a903 add r1, sp, #12 +10002cec: 4805 ldr r0, [pc, #20] @ (10002d04 ) +10002cee: 47a0 blx r4 +10002cf0: 2001 movs r0, #1 +10002cf2: b004 add sp, #16 +10002cf4: bd10 pop {r4, pc} +10002cf6: f000 f97d bl 10002ff4 <__wrap_puts> +10002cfa: 4620 mov r0, r4 +10002cfc: b004 add sp, #16 +10002cfe: bd10 pop {r4, pc} +10002d00: 2000080c .word 0x2000080c +10002d04: 10001885 .word 0x10001885 + +10002d08 <_exit>: +10002d08: be00 bkpt 0x0000 +10002d0a: e7fd b.n 10002d08 <_exit> + +10002d0c : +10002d0c: b508 push {r3, lr} +10002d0e: f7ff fffb bl 10002d08 <_exit> +10002d12: bf00 nop + +10002d14 : +10002d14: b538 push {r3, r4, r5, lr} +10002d16: 4c06 ldr r4, [pc, #24] @ (10002d30 ) +10002d18: 4d06 ldr r5, [pc, #24] @ (10002d34 ) +10002d1a: f7fe fa07 bl 1000112c +10002d1e: 42ac cmp r4, r5 +10002d20: d204 bcs.n 10002d2c +10002d22: f854 3b04 ldr.w r3, [r4], #4 +10002d26: 4798 blx r3 +10002d28: 42ac cmp r4, r5 +10002d2a: d3fa bcc.n 10002d22 +10002d2c: bd38 pop {r3, r4, r5, pc} +10002d2e: bf00 nop +10002d30: 100034a8 .word 0x100034a8 +10002d34: 100034ac .word 0x100034ac + +10002d38 : +10002d38: 6803 ldr r3, [r0, #0] +10002d3a: 4608 mov r0, r1 +10002d3c: 4611 mov r1, r2 +10002d3e: 4718 bx r3 + +10002d40 : +10002d40: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002d44: 4615 mov r5, r2 +10002d46: 7d42 ldrb r2, [r0, #21] +10002d48: 4607 mov r7, r0 +10002d4a: 4688 mov r8, r1 +10002d4c: 2a00 cmp r2, #0 +10002d4e: d046 beq.n 10002dde +10002d50: 2d00 cmp r5, #0 +10002d52: dd1d ble.n 10002d90 +10002d54: 780b ldrb r3, [r1, #0] +10002d56: 2b0a cmp r3, #10 +10002d58: d023 beq.n 10002da2 +10002d5a: 2d01 cmp r5, #1 +10002d5c: f04f 0c00 mov.w ip, #0 +10002d60: d018 beq.n 10002d94 +10002d62: 4646 mov r6, r8 +10002d64: 2401 movs r4, #1 +10002d66: f816 2f01 ldrb.w r2, [r6, #1]! +10002d6a: 4621 mov r1, r4 +10002d6c: 2a0a cmp r2, #10 +10002d6e: f104 0401 add.w r4, r4, #1 +10002d72: d022 beq.n 10002dba +10002d74: 42a5 cmp r5, r4 +10002d76: d1f6 bne.n 10002d66 +10002d78: 4565 cmp r5, ip +10002d7a: dc0b bgt.n 10002d94 +10002d7c: eb08 0305 add.w r3, r8, r5 +10002d80: f813 3c01 ldrb.w r3, [r3, #-1] +10002d84: f1a3 030d sub.w r3, r3, #13 +10002d88: fab3 f383 clz r3, r3 +10002d8c: 095b lsrs r3, r3, #5 +10002d8e: 753b strb r3, [r7, #20] +10002d90: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002d94: 683b ldr r3, [r7, #0] +10002d96: eba5 010c sub.w r1, r5, ip +10002d9a: eb08 000c add.w r0, r8, ip +10002d9e: 4798 blx r3 +10002da0: e7ec b.n 10002d7c +10002da2: 7d03 ldrb r3, [r0, #20] +10002da4: 2b00 cmp r3, #0 +10002da6: d1d8 bne.n 10002d5a +10002da8: 6803 ldr r3, [r0, #0] +10002daa: 2102 movs r1, #2 +10002dac: 480f ldr r0, [pc, #60] @ (10002dec ) +10002dae: 4798 blx r3 +10002db0: 2d01 cmp r5, #1 +10002db2: d0e3 beq.n 10002d7c +10002db4: f04f 0c01 mov.w ip, #1 +10002db8: e7d3 b.n 10002d62 +10002dba: f816 3c01 ldrb.w r3, [r6, #-1] +10002dbe: 2b0d cmp r3, #13 +10002dc0: d0d8 beq.n 10002d74 +10002dc2: 458c cmp ip, r1 +10002dc4: eb08 000c add.w r0, r8, ip +10002dc8: eba1 010c sub.w r1, r1, ip +10002dcc: da01 bge.n 10002dd2 +10002dce: 683b ldr r3, [r7, #0] +10002dd0: 4798 blx r3 +10002dd2: 2102 movs r1, #2 +10002dd4: 4805 ldr r0, [pc, #20] @ (10002dec ) +10002dd6: 683b ldr r3, [r7, #0] +10002dd8: 4798 blx r3 +10002dda: 46a4 mov ip, r4 +10002ddc: e7ca b.n 10002d74 +10002dde: 4629 mov r1, r5 +10002de0: 4640 mov r0, r8 +10002de2: 683b ldr r3, [r7, #0] +10002de4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002de8: 4718 bx r3 +10002dea: bf00 nop +10002dec: 10003658 .word 0x10003658 + +10002df0 : +10002df0: 680b ldr r3, [r1, #0] +10002df2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002df6: 2b80 cmp r3, #128 @ 0x80 +10002df8: 460d mov r5, r1 +10002dfa: 4606 mov r6, r0 +10002dfc: d005 beq.n 10002e0a +10002dfe: 1c5a adds r2, r3, #1 +10002e00: 442b add r3, r5 +10002e02: 602a str r2, [r5, #0] +10002e04: 711e strb r6, [r3, #4] +10002e06: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e0a: 4b0f ldr r3, [pc, #60] @ (10002e48 ) +10002e0c: 681c ldr r4, [r3, #0] +10002e0e: b1a4 cbz r4, 10002e3a +10002e10: 4f0e ldr r7, [pc, #56] @ (10002e4c ) +10002e12: f101 0804 add.w r8, r1, #4 +10002e16: e001 b.n 10002e1c +10002e18: 6924 ldr r4, [r4, #16] +10002e1a: b174 cbz r4, 10002e3a +10002e1c: 6823 ldr r3, [r4, #0] +10002e1e: 2b00 cmp r3, #0 +10002e20: d0fa beq.n 10002e18 +10002e22: 683b ldr r3, [r7, #0] +10002e24: b10b cbz r3, 10002e2a +10002e26: 42a3 cmp r3, r4 +10002e28: d1f6 bne.n 10002e18 +10002e2a: 4620 mov r0, r4 +10002e2c: 4641 mov r1, r8 +10002e2e: 682a ldr r2, [r5, #0] +10002e30: f7ff ff86 bl 10002d40 +10002e34: 6924 ldr r4, [r4, #16] +10002e36: 2c00 cmp r4, #0 +10002e38: d1f0 bne.n 10002e1c +10002e3a: 2300 movs r3, #0 +10002e3c: 2201 movs r2, #1 +10002e3e: 442b add r3, r5 +10002e40: 602a str r2, [r5, #0] +10002e42: 711e strb r6, [r3, #4] +10002e44: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e48: 20000804 .word 0x20000804 +10002e4c: 20000808 .word 0x20000808 + +10002e50 : +10002e50: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002e54: b082 sub sp, #8 +10002e56: 460d mov r5, r1 +10002e58: 4691 mov r9, r2 +10002e5a: 461c mov r4, r3 +10002e5c: 4606 mov r6, r0 +10002e5e: f7fd ffa7 bl 10000db0 +10002e62: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002e66: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002e6a: 4a2e ldr r2, [pc, #184] @ (10002f24 ) +10002e6c: 1882 adds r2, r0, r2 +10002e6e: f141 0300 adc.w r3, r1, #0 +10002e72: 4594 cmp ip, r2 +10002e74: eb77 0103 sbcs.w r1, r7, r3 +10002e78: bf3c itt cc +10002e7a: 4662 movcc r2, ip +10002e7c: 463b movcc r3, r7 +10002e7e: 482a ldr r0, [pc, #168] @ (10002f28 ) +10002e80: f000 faee bl 10003460 <__mutex_try_enter_block_until_veneer> +10002e84: 1c6b adds r3, r5, #1 +10002e86: 4680 mov r8, r0 +10002e88: d040 beq.n 10002f0c +10002e8a: b30c cbz r4, 10002ed0 +10002e8c: 4f27 ldr r7, [pc, #156] @ (10002f2c ) +10002e8e: 4b28 ldr r3, [pc, #160] @ (10002f30 ) +10002e90: 681c ldr r4, [r3, #0] +10002e92: b1b4 cbz r4, 10002ec2 +10002e94: f1b9 0f00 cmp.w r9, #0 +10002e98: d11c bne.n 10002ed4 +10002e9a: f8df 909c ldr.w r9, [pc, #156] @ 10002f38 +10002e9e: e001 b.n 10002ea4 +10002ea0: 6924 ldr r4, [r4, #16] +10002ea2: b174 cbz r4, 10002ec2 +10002ea4: 6823 ldr r3, [r4, #0] +10002ea6: 2b00 cmp r3, #0 +10002ea8: d0fa beq.n 10002ea0 +10002eaa: f8d9 3000 ldr.w r3, [r9] +10002eae: b10b cbz r3, 10002eb4 +10002eb0: 429c cmp r4, r3 +10002eb2: d1f5 bne.n 10002ea0 +10002eb4: 4620 mov r0, r4 +10002eb6: 462a mov r2, r5 +10002eb8: 4631 mov r1, r6 +10002eba: 47b8 blx r7 +10002ebc: 6924 ldr r4, [r4, #16] +10002ebe: 2c00 cmp r4, #0 +10002ec0: d1f0 bne.n 10002ea4 +10002ec2: f1b8 0f00 cmp.w r8, #0 +10002ec6: d126 bne.n 10002f16 +10002ec8: 4628 mov r0, r5 +10002eca: b002 add sp, #8 +10002ecc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002ed0: 4f18 ldr r7, [pc, #96] @ (10002f34 ) +10002ed2: e7dc b.n 10002e8e +10002ed4: f04f 0a0a mov.w sl, #10 +10002ed8: f8df 905c ldr.w r9, [pc, #92] @ 10002f38 +10002edc: e002 b.n 10002ee4 +10002ede: 6924 ldr r4, [r4, #16] +10002ee0: 2c00 cmp r4, #0 +10002ee2: d0ee beq.n 10002ec2 +10002ee4: 6823 ldr r3, [r4, #0] +10002ee6: 2b00 cmp r3, #0 +10002ee8: d0f9 beq.n 10002ede +10002eea: f8d9 3000 ldr.w r3, [r9] +10002eee: b10b cbz r3, 10002ef4 +10002ef0: 42a3 cmp r3, r4 +10002ef2: d1f4 bne.n 10002ede +10002ef4: 462a mov r2, r5 +10002ef6: 4631 mov r1, r6 +10002ef8: 4620 mov r0, r4 +10002efa: 47b8 blx r7 +10002efc: 2201 movs r2, #1 +10002efe: 4620 mov r0, r4 +10002f00: f10d 0107 add.w r1, sp, #7 +10002f04: f88d a007 strb.w sl, [sp, #7] +10002f08: 47b8 blx r7 +10002f0a: e7e8 b.n 10002ede +10002f0c: 4630 mov r0, r6 +10002f0e: f000 fa6f bl 100033f0 +10002f12: 4605 mov r5, r0 +10002f14: e7b9 b.n 10002e8a +10002f16: 4804 ldr r0, [pc, #16] @ (10002f28 ) +10002f18: f000 fa9e bl 10003458 <__mutex_exit_veneer> +10002f1c: 4628 mov r0, r5 +10002f1e: b002 add sp, #8 +10002f20: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002f24: 000f4240 .word 0x000f4240 +10002f28: 20000624 .word 0x20000624 +10002f2c: 10002d41 .word 0x10002d41 +10002f30: 20000804 .word 0x20000804 +10002f34: 10002d39 .word 0x10002d39 +10002f38: 20000808 .word 0x20000808 + +10002f3c : +10002f3c: 4a08 ldr r2, [pc, #32] @ (10002f60 ) +10002f3e: 6813 ldr r3, [r2, #0] +10002f40: b923 cbnz r3, 10002f4c +10002f42: e00a b.n 10002f5a +10002f44: f103 0210 add.w r2, r3, #16 +10002f48: 691b ldr r3, [r3, #16] +10002f4a: b133 cbz r3, 10002f5a +10002f4c: 4283 cmp r3, r0 +10002f4e: d1f9 bne.n 10002f44 +10002f50: b929 cbnz r1, 10002f5e +10002f52: 6918 ldr r0, [r3, #16] +10002f54: 6010 str r0, [r2, #0] +10002f56: 6119 str r1, [r3, #16] +10002f58: 4770 bx lr +10002f5a: b101 cbz r1, 10002f5e +10002f5c: 6010 str r0, [r2, #0] +10002f5e: 4770 bx lr +10002f60: 20000804 .word 0x20000804 + +10002f64 : +10002f64: b508 push {r3, lr} +10002f66: f000 f9a3 bl 100032b0 +10002f6a: 2001 movs r0, #1 +10002f6c: bd08 pop {r3, pc} +10002f6e: bf00 nop + +10002f70 <__wrap_putchar>: +10002f70: b5f0 push {r4, r5, r6, r7, lr} +10002f72: b083 sub sp, #12 +10002f74: 4606 mov r6, r0 +10002f76: f88d 0007 strb.w r0, [sp, #7] +10002f7a: f7fd ff19 bl 10000db0 +10002f7e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10002f82: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10002f86: 4a17 ldr r2, [pc, #92] @ (10002fe4 <__wrap_putchar+0x74>) +10002f88: 1882 adds r2, r0, r2 +10002f8a: f141 0300 adc.w r3, r1, #0 +10002f8e: 4295 cmp r5, r2 +10002f90: eb74 0103 sbcs.w r1, r4, r3 +10002f94: bf3c itt cc +10002f96: 4623 movcc r3, r4 +10002f98: 462a movcc r2, r5 +10002f9a: 4813 ldr r0, [pc, #76] @ (10002fe8 <__wrap_putchar+0x78>) +10002f9c: f000 fa60 bl 10003460 <__mutex_try_enter_block_until_veneer> +10002fa0: 4b12 ldr r3, [pc, #72] @ (10002fec <__wrap_putchar+0x7c>) +10002fa2: 4607 mov r7, r0 +10002fa4: 681c ldr r4, [r3, #0] +10002fa6: b19c cbz r4, 10002fd0 <__wrap_putchar+0x60> +10002fa8: 4d11 ldr r5, [pc, #68] @ (10002ff0 <__wrap_putchar+0x80>) +10002faa: e001 b.n 10002fb0 <__wrap_putchar+0x40> +10002fac: 6924 ldr r4, [r4, #16] +10002fae: b17c cbz r4, 10002fd0 <__wrap_putchar+0x60> +10002fb0: 6823 ldr r3, [r4, #0] +10002fb2: 2b00 cmp r3, #0 +10002fb4: d0fa beq.n 10002fac <__wrap_putchar+0x3c> +10002fb6: 682b ldr r3, [r5, #0] +10002fb8: b10b cbz r3, 10002fbe <__wrap_putchar+0x4e> +10002fba: 429c cmp r4, r3 +10002fbc: d1f6 bne.n 10002fac <__wrap_putchar+0x3c> +10002fbe: 4620 mov r0, r4 +10002fc0: 2201 movs r2, #1 +10002fc2: f10d 0107 add.w r1, sp, #7 +10002fc6: f7ff febb bl 10002d40 +10002fca: 6924 ldr r4, [r4, #16] +10002fcc: 2c00 cmp r4, #0 +10002fce: d1ef bne.n 10002fb0 <__wrap_putchar+0x40> +10002fd0: b917 cbnz r7, 10002fd8 <__wrap_putchar+0x68> +10002fd2: 4630 mov r0, r6 +10002fd4: b003 add sp, #12 +10002fd6: bdf0 pop {r4, r5, r6, r7, pc} +10002fd8: 4803 ldr r0, [pc, #12] @ (10002fe8 <__wrap_putchar+0x78>) +10002fda: f000 fa3d bl 10003458 <__mutex_exit_veneer> +10002fde: 4630 mov r0, r6 +10002fe0: b003 add sp, #12 +10002fe2: bdf0 pop {r4, r5, r6, r7, pc} +10002fe4: 000f4240 .word 0x000f4240 +10002fe8: 20000624 .word 0x20000624 +10002fec: 20000804 .word 0x20000804 +10002ff0: 20000808 .word 0x20000808 + +10002ff4 <__wrap_puts>: +10002ff4: b538 push {r3, r4, r5, lr} +10002ff6: 4604 mov r4, r0 +10002ff8: f000 f9fa bl 100033f0 +10002ffc: 2301 movs r3, #1 +10002ffe: 4605 mov r5, r0 +10003000: 461a mov r2, r3 +10003002: 4620 mov r0, r4 +10003004: 4629 mov r1, r5 +10003006: f7ff ff23 bl 10002e50 +1000300a: 4b08 ldr r3, [pc, #32] @ (1000302c <__wrap_puts+0x38>) +1000300c: 681c ldr r4, [r3, #0] +1000300e: b12c cbz r4, 1000301c <__wrap_puts+0x28> +10003010: 6863 ldr r3, [r4, #4] +10003012: b12b cbz r3, 10003020 <__wrap_puts+0x2c> +10003014: 4798 blx r3 +10003016: 6924 ldr r4, [r4, #16] +10003018: 2c00 cmp r4, #0 +1000301a: d1f9 bne.n 10003010 <__wrap_puts+0x1c> +1000301c: 4628 mov r0, r5 +1000301e: bd38 pop {r3, r4, r5, pc} +10003020: 6924 ldr r4, [r4, #16] +10003022: 2c00 cmp r4, #0 +10003024: d1f4 bne.n 10003010 <__wrap_puts+0x1c> +10003026: 4628 mov r0, r5 +10003028: bd38 pop {r3, r4, r5, pc} +1000302a: bf00 nop +1000302c: 20000804 .word 0x20000804 + +10003030 <__wrap_vprintf>: +10003030: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003034: b0a2 sub sp, #136 @ 0x88 +10003036: 4604 mov r4, r0 +10003038: 460d mov r5, r1 +1000303a: f7fd feb9 bl 10000db0 +1000303e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10003042: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003046: 4a26 ldr r2, [pc, #152] @ (100030e0 <__wrap_vprintf+0xb0>) +10003048: f8df 80a4 ldr.w r8, [pc, #164] @ 100030f0 <__wrap_vprintf+0xc0> +1000304c: 1882 adds r2, r0, r2 +1000304e: f141 0300 adc.w r3, r1, #0 +10003052: 4297 cmp r7, r2 +10003054: eb76 0103 sbcs.w r1, r6, r3 +10003058: bf3c itt cc +1000305a: 463a movcc r2, r7 +1000305c: 4633 movcc r3, r6 +1000305e: 4821 ldr r0, [pc, #132] @ (100030e4 <__wrap_vprintf+0xb4>) +10003060: f000 f9fe bl 10003460 <__mutex_try_enter_block_until_veneer> +10003064: 2700 movs r7, #0 +10003066: 462b mov r3, r5 +10003068: 4622 mov r2, r4 +1000306a: 4606 mov r6, r0 +1000306c: a901 add r1, sp, #4 +1000306e: 481e ldr r0, [pc, #120] @ (100030e8 <__wrap_vprintf+0xb8>) +10003070: 9701 str r7, [sp, #4] +10003072: f7ff fe1d bl 10002cb0 +10003076: 9b01 ldr r3, [sp, #4] +10003078: 4605 mov r5, r0 +1000307a: f8d8 4000 ldr.w r4, [r8] +1000307e: b1c3 cbz r3, 100030b2 <__wrap_vprintf+0x82> +10003080: 2c00 cmp r4, #0 +10003082: d02b beq.n 100030dc <__wrap_vprintf+0xac> +10003084: 4f19 ldr r7, [pc, #100] @ (100030ec <__wrap_vprintf+0xbc>) +10003086: e001 b.n 1000308c <__wrap_vprintf+0x5c> +10003088: 6924 ldr r4, [r4, #16] +1000308a: b174 cbz r4, 100030aa <__wrap_vprintf+0x7a> +1000308c: 6823 ldr r3, [r4, #0] +1000308e: 2b00 cmp r3, #0 +10003090: d0fa beq.n 10003088 <__wrap_vprintf+0x58> +10003092: 683b ldr r3, [r7, #0] +10003094: b10b cbz r3, 1000309a <__wrap_vprintf+0x6a> +10003096: 42a3 cmp r3, r4 +10003098: d1f6 bne.n 10003088 <__wrap_vprintf+0x58> +1000309a: 4620 mov r0, r4 +1000309c: 9a01 ldr r2, [sp, #4] +1000309e: a902 add r1, sp, #8 +100030a0: f7ff fe4e bl 10002d40 +100030a4: 6924 ldr r4, [r4, #16] +100030a6: 2c00 cmp r4, #0 +100030a8: d1f0 bne.n 1000308c <__wrap_vprintf+0x5c> +100030aa: 2300 movs r3, #0 +100030ac: f8d8 4000 ldr.w r4, [r8] +100030b0: 9301 str r3, [sp, #4] +100030b2: b12c cbz r4, 100030c0 <__wrap_vprintf+0x90> +100030b4: 6863 ldr r3, [r4, #4] +100030b6: b143 cbz r3, 100030ca <__wrap_vprintf+0x9a> +100030b8: 4798 blx r3 +100030ba: 6924 ldr r4, [r4, #16] +100030bc: 2c00 cmp r4, #0 +100030be: d1f9 bne.n 100030b4 <__wrap_vprintf+0x84> +100030c0: b92e cbnz r6, 100030ce <__wrap_vprintf+0x9e> +100030c2: 4628 mov r0, r5 +100030c4: b022 add sp, #136 @ 0x88 +100030c6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030ca: 6924 ldr r4, [r4, #16] +100030cc: e7f1 b.n 100030b2 <__wrap_vprintf+0x82> +100030ce: 4805 ldr r0, [pc, #20] @ (100030e4 <__wrap_vprintf+0xb4>) +100030d0: f000 f9c2 bl 10003458 <__mutex_exit_veneer> +100030d4: 4628 mov r0, r5 +100030d6: b022 add sp, #136 @ 0x88 +100030d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030dc: 9401 str r4, [sp, #4] +100030de: e7ef b.n 100030c0 <__wrap_vprintf+0x90> +100030e0: 000f4240 .word 0x000f4240 +100030e4: 20000624 .word 0x20000624 +100030e8: 10002df1 .word 0x10002df1 +100030ec: 20000808 .word 0x20000808 +100030f0: 20000804 .word 0x20000804 + +100030f4 <__wrap_printf>: +100030f4: b40f push {r0, r1, r2, r3} +100030f6: b500 push {lr} +100030f8: b083 sub sp, #12 +100030fa: a904 add r1, sp, #16 +100030fc: f851 0b04 ldr.w r0, [r1], #4 +10003100: 9101 str r1, [sp, #4] +10003102: f7ff ff95 bl 10003030 <__wrap_vprintf> +10003106: b003 add sp, #12 +10003108: f85d eb04 ldr.w lr, [sp], #4 +1000310c: b004 add sp, #16 +1000310e: 4770 bx lr + +10003110 : +10003110: f1b1 0c00 subs.w ip, r1, #0 +10003114: dd1d ble.n 10003152 +10003116: 4a0f ldr r2, [pc, #60] @ (10003154 ) +10003118: 4b0f ldr r3, [pc, #60] @ (10003158 ) +1000311a: 6812 ldr r2, [r2, #0] +1000311c: b530 push {r4, r5, lr} +1000311e: 1ad3 subs r3, r2, r3 +10003120: fab3 f383 clz r3, r3 +10003124: 240d movs r4, #13 +10003126: 4d0d ldr r5, [pc, #52] @ (1000315c ) +10003128: 095b lsrs r3, r3, #5 +1000312a: 1e41 subs r1, r0, #1 +1000312c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003130: 448c add ip, r1 +10003132: f811 0f01 ldrb.w r0, [r1, #1]! +10003136: 4586 cmp lr, r0 +10003138: d006 beq.n 10003148 +1000313a: 6993 ldr r3, [r2, #24] +1000313c: 069b lsls r3, r3, #26 +1000313e: d4fc bmi.n 1000313a +10003140: 4561 cmp r1, ip +10003142: 6010 str r0, [r2, #0] +10003144: d1f5 bne.n 10003132 +10003146: bd30 pop {r4, r5, pc} +10003148: 6993 ldr r3, [r2, #24] +1000314a: 069d lsls r5, r3, #26 +1000314c: d4fc bmi.n 10003148 +1000314e: 6014 str r4, [r2, #0] +10003150: e7f3 b.n 1000313a +10003152: 4770 bx lr +10003154: 20000850 .word 0x20000850 +10003158: 40078000 .word 0x40078000 +1000315c: 2000084c .word 0x2000084c + +10003160 : +10003160: 4b22 ldr r3, [pc, #136] @ (100031ec ) +10003162: f1b1 0c00 subs.w ip, r1, #0 +10003166: b410 push {r4} +10003168: 681c ldr r4, [r3, #0] +1000316a: dd2e ble.n 100031ca +1000316c: 4603 mov r3, r0 +1000316e: 2000 movs r0, #0 +10003170: 4a1f ldr r2, [pc, #124] @ (100031f0 ) +10003172: 1e59 subs r1, r3, #1 +10003174: 6812 ldr r2, [r2, #0] +10003176: 6993 ldr r3, [r2, #24] +10003178: 06db lsls r3, r3, #27 +1000317a: d417 bmi.n 100031ac +1000317c: 3001 adds r0, #1 +1000317e: 6993 ldr r3, [r2, #24] +10003180: 06db lsls r3, r3, #27 +10003182: d4fc bmi.n 1000317e +10003184: 6813 ldr r3, [r2, #0] +10003186: 4584 cmp ip, r0 +10003188: f801 3f01 strb.w r3, [r1, #1]! +1000318c: d1f3 bne.n 10003176 +1000318e: b14c cbz r4, 100031a4 +10003190: 2150 movs r1, #80 @ 0x50 +10003192: 4613 mov r3, r2 +10003194: 6391 str r1, [r2, #56] @ 0x38 +10003196: f853 2f34 ldr.w r2, [r3, #52]! +1000319a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000319e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031a2: 601a str r2, [r3, #0] +100031a4: 4660 mov r0, ip +100031a6: f85d 4b04 ldr.w r4, [sp], #4 +100031aa: 4770 bx lr +100031ac: b14c cbz r4, 100031c2 +100031ae: 2150 movs r1, #80 @ 0x50 +100031b0: 4613 mov r3, r2 +100031b2: 6391 str r1, [r2, #56] @ 0x38 +100031b4: f853 2f34 ldr.w r2, [r3, #52]! +100031b8: f002 0238 and.w r2, r2, #56 @ 0x38 +100031bc: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031c0: 601a str r2, [r3, #0] +100031c2: b178 cbz r0, 100031e4 +100031c4: f85d 4b04 ldr.w r4, [sp], #4 +100031c8: 4770 bx lr +100031ca: b15c cbz r4, 100031e4 +100031cc: 4b08 ldr r3, [pc, #32] @ (100031f0 ) +100031ce: 2150 movs r1, #80 @ 0x50 +100031d0: 681a ldr r2, [r3, #0] +100031d2: 4613 mov r3, r2 +100031d4: 6391 str r1, [r2, #56] @ 0x38 +100031d6: f853 2f34 ldr.w r2, [r3, #52]! +100031da: f002 0238 and.w r2, r2, #56 @ 0x38 +100031de: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100031e2: 601a str r2, [r3, #0] +100031e4: f06f 0002 mvn.w r0, #2 +100031e8: e7dd b.n 100031a6 +100031ea: bf00 nop +100031ec: 200007d0 .word 0x200007d0 +100031f0: 20000850 .word 0x20000850 + +100031f4 : +100031f4: 4b05 ldr r3, [pc, #20] @ (1000320c ) +100031f6: 681b ldr r3, [r3, #0] +100031f8: b133 cbz r3, 10003208 +100031fa: 2100 movs r1, #0 +100031fc: 4a04 ldr r2, [pc, #16] @ (10003210 ) +100031fe: 4805 ldr r0, [pc, #20] @ (10003214 ) +10003200: 6812 ldr r2, [r2, #0] +10003202: 6800 ldr r0, [r0, #0] +10003204: 6391 str r1, [r2, #56] @ 0x38 +10003206: 4718 bx r3 +10003208: 4770 bx lr +1000320a: bf00 nop +1000320c: 200007d0 .word 0x200007d0 +10003210: 20000850 .word 0x20000850 +10003214: 200007d4 .word 0x200007d4 + +10003218 : +10003218: 4b02 ldr r3, [pc, #8] @ (10003224 ) +1000321a: 681a ldr r2, [r3, #0] +1000321c: 6993 ldr r3, [r2, #24] +1000321e: 071b lsls r3, r3, #28 +10003220: d4fc bmi.n 1000321c +10003222: 4770 bx lr +10003224: 20000850 .word 0x20000850 + +10003228 : +10003228: b5f8 push {r3, r4, r5, r6, r7, lr} +1000322a: 4f1c ldr r7, [pc, #112] @ (1000329c ) +1000322c: 4d1c ldr r5, [pc, #112] @ (100032a0 ) +1000322e: 683a ldr r2, [r7, #0] +10003230: 4e1c ldr r6, [pc, #112] @ (100032a4 ) +10003232: 42aa cmp r2, r5 +10003234: bf14 ite ne +10003236: 2521 movne r5, #33 @ 0x21 +10003238: 2522 moveq r5, #34 @ 0x22 +1000323a: 4604 mov r4, r0 +1000323c: f8d6 c000 ldr.w ip, [r6] +10003240: b118 cbz r0, 1000324a +10003242: f1bc 0f00 cmp.w ip, #0 +10003246: d010 beq.n 1000326a +10003248: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000324a: f1bc 0f00 cmp.w ip, #0 +1000324e: d0fb beq.n 10003248 +10003250: 4601 mov r1, r0 +10003252: 6390 str r0, [r2, #56] @ 0x38 +10003254: 4628 mov r0, r5 +10003256: f7fd f8a3 bl 100003a0 +1000325a: 4628 mov r0, r5 +1000325c: 4912 ldr r1, [pc, #72] @ (100032a8 ) +1000325e: f7fd f8e5 bl 1000042c +10003262: 4b12 ldr r3, [pc, #72] @ (100032ac ) +10003264: 6034 str r4, [r6, #0] +10003266: 601c str r4, [r3, #0] +10003268: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000326a: 460b mov r3, r1 +1000326c: 4a0f ldr r2, [pc, #60] @ (100032ac ) +1000326e: 490e ldr r1, [pc, #56] @ (100032a8 ) +10003270: 6030 str r0, [r6, #0] +10003272: 4628 mov r0, r5 +10003274: 6013 str r3, [r2, #0] +10003276: f7fd f8a9 bl 100003cc +1000327a: 2101 movs r1, #1 +1000327c: 4628 mov r0, r5 +1000327e: f7fd f88f bl 100003a0 +10003282: 683a ldr r2, [r7, #0] +10003284: 2150 movs r1, #80 @ 0x50 +10003286: 4613 mov r3, r2 +10003288: 6391 str r1, [r2, #56] @ 0x38 +1000328a: f853 2f34 ldr.w r2, [r3, #52]! +1000328e: f002 0238 and.w r2, r2, #56 @ 0x38 +10003292: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003296: 601a str r2, [r3, #0] +10003298: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000329a: bf00 nop +1000329c: 20000850 .word 0x20000850 +100032a0: 40078000 .word 0x40078000 +100032a4: 200007d0 .word 0x200007d0 +100032a8: 100031f5 .word 0x100031f5 +100032ac: 200007d4 .word 0x200007d4 + +100032b0 : +100032b0: b510 push {r4, lr} +100032b2: 490e ldr r1, [pc, #56] @ (100032ec ) +100032b4: 4c0e ldr r4, [pc, #56] @ (100032f0 ) +100032b6: 480f ldr r0, [pc, #60] @ (100032f4 ) +100032b8: 4a0f ldr r2, [pc, #60] @ (100032f8 ) +100032ba: 4b10 ldr r3, [pc, #64] @ (100032fc ) +100032bc: 7800 ldrb r0, [r0, #0] +100032be: 6021 str r1, [r4, #0] +100032c0: 2000 movs r0, #0 +100032c2: 2102 movs r1, #2 +100032c4: 7812 ldrb r2, [r2, #0] +100032c6: 781b ldrb r3, [r3, #0] +100032c8: f7fc ffc8 bl 1000025c +100032cc: 2102 movs r1, #2 +100032ce: 2001 movs r0, #1 +100032d0: f7fc ffc4 bl 1000025c +100032d4: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100032d8: 6820 ldr r0, [r4, #0] +100032da: f7fd fda1 bl 10000e20 +100032de: e8bd 4010 ldmia.w sp!, {r4, lr} +100032e2: 2101 movs r1, #1 +100032e4: 4806 ldr r0, [pc, #24] @ (10003300 ) +100032e6: f7ff be29 b.w 10002f3c +100032ea: bf00 nop +100032ec: 40070000 .word 0x40070000 +100032f0: 20000850 .word 0x20000850 +100032f4: 100036a8 .word 0x100036a8 +100032f8: 100036a4 .word 0x100036a4 +100032fc: 100036a0 .word 0x100036a0 +10003300: 2000060c .word 0x2000060c + +10003304 : +10003304: 4684 mov ip, r0 +10003306: ea41 0300 orr.w r3, r1, r0 +1000330a: f013 0303 ands.w r3, r3, #3 +1000330e: d149 bne.n 100033a4 +10003310: 3a40 subs r2, #64 @ 0x40 +10003312: d323 bcc.n 1000335c +10003314: 680b ldr r3, [r1, #0] +10003316: 6003 str r3, [r0, #0] +10003318: 684b ldr r3, [r1, #4] +1000331a: 6043 str r3, [r0, #4] +1000331c: 688b ldr r3, [r1, #8] +1000331e: 6083 str r3, [r0, #8] +10003320: 68cb ldr r3, [r1, #12] +10003322: 60c3 str r3, [r0, #12] +10003324: 690b ldr r3, [r1, #16] +10003326: 6103 str r3, [r0, #16] +10003328: 694b ldr r3, [r1, #20] +1000332a: 6143 str r3, [r0, #20] +1000332c: 698b ldr r3, [r1, #24] +1000332e: 6183 str r3, [r0, #24] +10003330: 69cb ldr r3, [r1, #28] +10003332: 61c3 str r3, [r0, #28] +10003334: 6a0b ldr r3, [r1, #32] +10003336: 6203 str r3, [r0, #32] +10003338: 6a4b ldr r3, [r1, #36] @ 0x24 +1000333a: 6243 str r3, [r0, #36] @ 0x24 +1000333c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000333e: 6283 str r3, [r0, #40] @ 0x28 +10003340: 6acb ldr r3, [r1, #44] @ 0x2c +10003342: 62c3 str r3, [r0, #44] @ 0x2c +10003344: 6b0b ldr r3, [r1, #48] @ 0x30 +10003346: 6303 str r3, [r0, #48] @ 0x30 +10003348: 6b4b ldr r3, [r1, #52] @ 0x34 +1000334a: 6343 str r3, [r0, #52] @ 0x34 +1000334c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000334e: 6383 str r3, [r0, #56] @ 0x38 +10003350: 6bcb ldr r3, [r1, #60] @ 0x3c +10003352: 63c3 str r3, [r0, #60] @ 0x3c +10003354: 3040 adds r0, #64 @ 0x40 +10003356: 3140 adds r1, #64 @ 0x40 +10003358: 3a40 subs r2, #64 @ 0x40 +1000335a: d2db bcs.n 10003314 +1000335c: 3230 adds r2, #48 @ 0x30 +1000335e: d30b bcc.n 10003378 +10003360: 680b ldr r3, [r1, #0] +10003362: 6003 str r3, [r0, #0] +10003364: 684b ldr r3, [r1, #4] +10003366: 6043 str r3, [r0, #4] +10003368: 688b ldr r3, [r1, #8] +1000336a: 6083 str r3, [r0, #8] +1000336c: 68cb ldr r3, [r1, #12] +1000336e: 60c3 str r3, [r0, #12] +10003370: 3010 adds r0, #16 +10003372: 3110 adds r1, #16 +10003374: 3a10 subs r2, #16 +10003376: d2f3 bcs.n 10003360 +10003378: 320c adds r2, #12 +1000337a: d305 bcc.n 10003388 +1000337c: f851 3b04 ldr.w r3, [r1], #4 +10003380: f840 3b04 str.w r3, [r0], #4 +10003384: 3a04 subs r2, #4 +10003386: d2f9 bcs.n 1000337c +10003388: 3204 adds r2, #4 +1000338a: d008 beq.n 1000339e +1000338c: 07d2 lsls r2, r2, #31 +1000338e: bf1c itt ne +10003390: f811 3b01 ldrbne.w r3, [r1], #1 +10003394: f800 3b01 strbne.w r3, [r0], #1 +10003398: d301 bcc.n 1000339e +1000339a: 880b ldrh r3, [r1, #0] +1000339c: 8003 strh r3, [r0, #0] +1000339e: 4660 mov r0, ip +100033a0: 4770 bx lr +100033a2: bf00 nop +100033a4: 2a08 cmp r2, #8 +100033a6: d313 bcc.n 100033d0 +100033a8: 078b lsls r3, r1, #30 +100033aa: d0b1 beq.n 10003310 +100033ac: f010 0303 ands.w r3, r0, #3 +100033b0: d0ae beq.n 10003310 +100033b2: f1c3 0304 rsb r3, r3, #4 +100033b6: 1ad2 subs r2, r2, r3 +100033b8: 07db lsls r3, r3, #31 +100033ba: bf1c itt ne +100033bc: f811 3b01 ldrbne.w r3, [r1], #1 +100033c0: f800 3b01 strbne.w r3, [r0], #1 +100033c4: d3a4 bcc.n 10003310 +100033c6: f831 3b02 ldrh.w r3, [r1], #2 +100033ca: f820 3b02 strh.w r3, [r0], #2 +100033ce: e79f b.n 10003310 +100033d0: 3a04 subs r2, #4 +100033d2: d3d9 bcc.n 10003388 +100033d4: 3a01 subs r2, #1 +100033d6: f811 3b01 ldrb.w r3, [r1], #1 +100033da: f800 3b01 strb.w r3, [r0], #1 +100033de: d2f9 bcs.n 100033d4 +100033e0: 780b ldrb r3, [r1, #0] +100033e2: 7003 strb r3, [r0, #0] +100033e4: 784b ldrb r3, [r1, #1] +100033e6: 7043 strb r3, [r0, #1] +100033e8: 788b ldrb r3, [r1, #2] +100033ea: 7083 strb r3, [r0, #2] +100033ec: 4660 mov r0, ip +100033ee: 4770 bx lr + +100033f0 : +100033f0: f020 0103 bic.w r1, r0, #3 +100033f4: f010 0003 ands.w r0, r0, #3 +100033f8: f1c0 0000 rsb r0, r0, #0 +100033fc: f851 3b04 ldr.w r3, [r1], #4 +10003400: f100 0c04 add.w ip, r0, #4 +10003404: ea4f 0ccc mov.w ip, ip, lsl #3 +10003408: f06f 0200 mvn.w r2, #0 +1000340c: bf1c itt ne +1000340e: fa22 f20c lsrne.w r2, r2, ip +10003412: 4313 orrne r3, r2 +10003414: f04f 0c01 mov.w ip, #1 +10003418: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000341c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003420: eba3 020c sub.w r2, r3, ip +10003424: ea22 0203 bic.w r2, r2, r3 +10003428: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000342c: bf04 itt eq +1000342e: f851 3b04 ldreq.w r3, [r1], #4 +10003432: 3004 addeq r0, #4 +10003434: d0f4 beq.n 10003420 +10003436: f1c2 0100 rsb r1, r2, #0 +1000343a: ea02 0201 and.w r2, r2, r1 +1000343e: fab2 f282 clz r2, r2 +10003442: f1c2 021f rsb r2, r2, #31 +10003446: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000344a: 4770 bx lr + +1000344c <_fini>: +1000344c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000344e: bf00 nop + +10003450 <____aeabi_uldivmod_veneer>: +10003450: f85f f000 ldr.w pc, [pc] @ 10003454 <____aeabi_uldivmod_veneer+0x4> +10003454: 20000221 .word 0x20000221 + +10003458 <__mutex_exit_veneer>: +10003458: f85f f000 ldr.w pc, [pc] @ 1000345c <__mutex_exit_veneer+0x4> +1000345c: 200001e5 .word 0x200001e5 + +10003460 <__mutex_try_enter_block_until_veneer>: +10003460: f85f f000 ldr.w pc, [pc] @ 10003464 <__mutex_try_enter_block_until_veneer+0x4> +10003464: 2000017d .word 0x2000017d + +10003468 <__pre_init_runtime_init_bootrom_reset>: +10003468: 100011d9 .... + +1000346c <__pre_init_runtime_init_early_resets>: +1000346c: 1000114d M... + +10003470 <__pre_init_runtime_init_usb_power_down>: +10003470: 10001181 .... + +10003474 <__pre_init_runtime_init_clocks>: +10003474: 1000126d m... + +10003478 <__pre_init_runtime_init_post_clock_resets>: +10003478: 100011b9 .... + +1000347c <__pre_init_runtime_init_boot_locks_reset>: +1000347c: 100010d1 .... + +10003480 <__pre_init_runtime_init_spin_locks_reset>: +10003480: 10001201 .... + +10003484 <__pre_init_runtime_init_bootrom_locking_enable>: +10003484: 100010bd .... + +10003488 <__pre_init_runtime_init_mutex>: +10003488: 100006e9 .... + +1000348c <__pre_init_runtime_init_install_ram_vector_table>: +1000348c: 10001205 .... + +10003490 <__pre_init_runtime_init_default_alarm_pool>: +10003490: 10000a61 a... + +10003494 <__pre_init_first_per_core_initializer>: +10003494: 1000111d .... + +10003498 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003498: 100011ed .... + +1000349c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000349c: 1000119d .... + +100034a0 <__pre_init_spinlock_set_extexclall>: +100034a0: 10000339 9... + +100034a4 <__pre_init_runtime_init_per_core_irq_priorities>: +100034a4: 10000361 a... + +100034a8 <__frame_dummy_init_array_entry>: +100034a8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000ca9 .word 0x10000ca9 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 10000621 .word 0x10000621 + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003111 10003219 10003161 10003229 .1...2..a1..)2.. +2000061c: 00000000 00000100 ........ + +20000624 : + ... diff --git a/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf new file mode 100755 index 0000000..bf21692 Binary files /dev/null and b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf differ diff --git a/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf.map b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf.map new file mode 100644 index 0000000..21544f7 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf.map @@ -0,0 +1,3654 @@ +Archive member included to satisfy reference by file (symbol) + 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b/WEEK05/0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.uf2 differ diff --git a/WEEK05/0x0011_double-floating-point-data-type/build/pico_flash_region.ld b/WEEK05/0x0011_double-floating-point-data-type/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK05/0x0011_double-floating-point-data-type/pico_sdk_import.cmake b/WEEK05/0x0011_double-floating-point-data-type/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK05/0x0011_double-floating-point-data-type/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK05/WEEK05-BN.md b/WEEK05/WEEK05-BN.md new file mode 100644 index 0000000..5e9fe5c --- /dev/null +++ b/WEEK05/WEEK05-BN.md @@ -0,0 +1,2014 @@ +# Week 5-BN: Binary Ninja Personal — Decode, Hack, and Patch IEEE 754 Floats and Doubles (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into Binary Ninja at `0x10000000` +- Read how a `float`/`double` constant is materialized from the compiler's literal pool +- **Break at `main`** on live silicon, even though `main` moves between these two programs +- Reconstruct a 64-bit `double` from the ABI register pair `r2:r3` and hack it live +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map, including the `pico_double` formatting helpers `printf` pulls in +- **Patch** the constant bytes, export the image, convert to UF2, and flash it +- Prove why `42.5 -> 99.0` is a one-word patch but `42.52525 -> 99.99` needs two + +--- + +## How This Guide Works + +The build produces two files for each project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in Binary Ninja, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 5 lesson, and the Week 5 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it folds the `float`/`double` initializer into the literal pool and links the `pico_double` formatting helpers straight into the `printf` path. If you build `Debug`, the SDK function addresses move and the float/double helpers are laid out differently, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**, twice — once per project: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the output change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Prints | The hack | +| ------- | ------ | -------- | +| `0x000e_floating-point-data-type` | `fav_num: 42.500000` | change the printed double `42.5` to `99.0` (one word) | +| `0x0011_double-floating-point-data-type` | `fav_num: 42.525250` | change the printed double `42.52525` to `99.99` (two words) | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **`main` is not at the same address in both projects this week.** It is `0x10000234` in Project 1 and `0x10000238` in Project 2, because each program materializes its constant slightly differently. We still anchor to `main` through the one byte-identical place that always names it: the middle `blx` in `platform_entry` (Step 12). + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +file "$(which telnet)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**`telnet` is special — and optional.** The GDB MI workflow does not need it; it is only used by the command-port fallback. macOS no longer ships `telnet`, and the Homebrew build is often the Intel one, so `telnet 127.0.0.1 4444` fails with `bad CPU type in executable`. Your `brew` command itself may also be the Intel one: if `brew install telnet` fails with `.../portable-ruby/.../ruby: Bad CPU type in executable`, you are running the Intel Homebrew. Call the Apple Silicon Homebrew explicitly: + +```bash +/opt/homebrew/bin/brew install telnet +``` + +If you would rather not install anything, macOS ships an arm64 `nc`, which can connect to the same OpenOCD port: + +```bash +nc 127.0.0.1 4444 +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x000e_floating-point-data-type/` and once inside `0x0011_double-floating-point-data-type/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x000e_floating-point-data-type", "0x0011_double-floating-point-data-type"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x000e_floating-point-data-type", "0x0011_double-floating-point-data-type"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x000e_floating-point-data-type", "0x0011_double-floating-point-data-type"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.elf` and `.bin` — `.bin` is **15308** bytes (`0x3bcc`) +- `0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.elf` and `.bin` — `.bin` is **15324** bytes (`0x3bdc`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x000e_floating-point-data-type.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0011_double-floating-point-data-type.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x000e_floating-point-data-type.elf | Select-String ' [Tt] ' +arm-none-eabi-nm -n --defined-only build\0x0011_double-floating-point-data-type.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Project 1 — `0x000e_floating-point-data-type`:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function | +| `0x10000254` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO helper | +| `0x10000da8` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10000e18` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10002ca8` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002d04` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002d0c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10002d38` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10002e48` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10002f34` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10002f5c` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003028` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100030ec` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x100032a8` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100033e8` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +Project 1 also links in the `pico_double` formatting helpers that `printf`'s `%f` path calls. These are reachable from `main` through `__wrap_printf`: + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10001384` | `__wrap___aeabi_dadd` | `double __wrap___aeabi_dadd(double, double)` | double add | +| `0x100013ac` | `__wrap___aeabi_dsub` | `double __wrap___aeabi_dsub(double, double)` | double subtract | +| `0x100013d4` | `__wrap___aeabi_dmul` | `double __wrap___aeabi_dmul(double, double)` | double multiply | +| `0x10001420` | `__wrap___aeabi_ddiv` | `double __wrap___aeabi_ddiv(double, double)` | double divide | +| `0x100014bc` | `__wrap___aeabi_i2d` | `double __wrap___aeabi_i2d(int)` | int -> double | +| `0x100014e0` | `__wrap___aeabi_ui2d` | `double __wrap___aeabi_ui2d(unsigned)` | unsigned -> double | +| `0x10001504` | `__wrap___aeabi_d2iz` | `int __wrap___aeabi_d2iz(double)` | double -> int | +| `0x10001528` | `__wrap___aeabi_d2uiz` | `unsigned __wrap___aeabi_d2uiz(double)` | double -> unsigned | +| `0x1000154c` | `__wrap___aeabi_dcmpun` | `int __wrap___aeabi_dcmpun(double, double)` | unordered compare | +| `0x10001570` | `__wrap___aeabi_dcmplt` | `int __wrap___aeabi_dcmplt(double, double)` | less-than compare | +| `0x10001598` | `__wrap___aeabi_dcmple` | `int __wrap___aeabi_dcmple(double, double)` | less-or-equal compare | +| `0x100015c0` | `__wrap___aeabi_dcmpge` | `int __wrap___aeabi_dcmpge(double, double)` | greater-or-equal compare | +| `0x100015e8` | `__wrap___aeabi_dcmpgt` | `int __wrap___aeabi_dcmpgt(double, double)` | greater-than compare | +| `0x1000160c` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x100016a8` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x1000187c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x10001890` | `_ftoa` | `unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | fixed-point float formatter | +| `0x10001d50` | `_etoa` | `unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | exponential float formatter | +| `0x100022c4` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10000dbc` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10000fec` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +**Project 2 — `0x0011_double-floating-point-data-type`:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000238` | `main` | `int main(void)` | the lesson function | +| `0x1000025c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO helper | +| `0x10000db0` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10000e20` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10002cb0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002d0c` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002d14` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10002d40` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10002e50` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10002f3c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10002f64` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003030` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100030f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x100032b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100033f0` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +Project 2 uses the same `pico_double` formatting helpers as Project 1, shifted by eight bytes because `main` moved: + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000138c` | `__wrap___aeabi_dadd` | `double __wrap___aeabi_dadd(double, double)` | double add | +| `0x100013b4` | `__wrap___aeabi_dsub` | `double __wrap___aeabi_dsub(double, double)` | double subtract | +| `0x100013dc` | `__wrap___aeabi_dmul` | `double __wrap___aeabi_dmul(double, double)` | double multiply | +| `0x10001428` | `__wrap___aeabi_ddiv` | `double __wrap___aeabi_ddiv(double, double)` | double divide | +| `0x100014c4` | `__wrap___aeabi_i2d` | `double __wrap___aeabi_i2d(int)` | int -> double | +| `0x100014e8` | `__wrap___aeabi_ui2d` | `double __wrap___aeabi_ui2d(unsigned)` | unsigned -> double | +| `0x1000150c` | `__wrap___aeabi_d2iz` | `int __wrap___aeabi_d2iz(double)` | double -> int | +| `0x10001530` | `__wrap___aeabi_d2uiz` | `unsigned __wrap___aeabi_d2uiz(double)` | double -> unsigned | +| `0x10001554` | `__wrap___aeabi_dcmpun` | `int __wrap___aeabi_dcmpun(double, double)` | unordered compare | +| `0x10001578` | `__wrap___aeabi_dcmplt` | `int __wrap___aeabi_dcmplt(double, double)` | less-than compare | +| `0x100015a0` | `__wrap___aeabi_dcmple` | `int __wrap___aeabi_dcmple(double, double)` | less-or-equal compare | +| `0x100015c8` | `__wrap___aeabi_dcmpge` | `int __wrap___aeabi_dcmpge(double, double)` | greater-or-equal compare | +| `0x100015f0` | `__wrap___aeabi_dcmpgt` | `int __wrap___aeabi_dcmpgt(double, double)` | greater-than compare | +| `0x10001614` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x100016b0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x10001884` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x10001898` | `_ftoa` | `unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | fixed-point float formatter | +| `0x10001d58` | `_etoa` | `unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | exponential float formatter | +| `0x100022cc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10000dc4` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10000ff4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +> **A literal pool is still a pool.** The `float`/`double` initializer does not survive as a C variable, but the compiler still has to place the IEEE-754 bit pattern somewhere. It parks the 32-bit word (or word pair) right after `main`'s code and reaches it with a PC-relative `ldr`/`ldrd`. That is why the value you patch is a `.word` in the image, not a stack store. + +### Step 5: Flash Project 1 and confirm `fav_num: 42.500000` + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x000e_floating-point-data-type\build\0x000e_floating-point-data-type.bin +``` + +**Or flash from the Binary Ninja console** (the console reads the repo root from the marker file, so it works with no database open): + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x000e_floating-point-data-type", "build", "0x000e_floating-point-data-type.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x000e_floating-point-data-type", "build", "0x000e_floating-point-data-type.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 15308 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +fav_num: 42.500000 +fav_num: 42.500000 +fav_num: 42.500000 +... +``` + +The program prints `42.500000` because `printf` with `%f` defaults to six decimal places. + +### Step 6: Flash Project 2 and confirm `fav_num: 42.525250` + +```bash +# macOS / Linux +./flash.sh 0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin +``` +```powershell +# Windows +.\flash.ps1 -Bin 0x0011_double-floating-point-data-type\build\0x0011_double-floating-point-data-type.bin +``` + +**Or flash from the Binary Ninja console** (same form as Step 5, pointing at the Project 2 `.bin`): + +**macOS / Linux:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0011_double-floating-point-data-type", "build", "0x0011_double-floating-point-data-type.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0011_double-floating-point-data-type", "build", "0x0011_double-floating-point-data-type.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 15324 bytes ...`. The serial monitor shows: + +``` +fav_num: 42.525250 +fav_num: 42.525250 +fav_num: 42.525250 +... +``` + +`42.52525` has a repeating binary fraction, so its 52 mantissa bits are not all zero. Remember that: it is why this value needs two words patched, and `42.5` needs only one. +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> load("0x000e_floating-point-data-type/build/0x000e_floating-point-data-type.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 8: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x000e_floating-point-data-type.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +The two files have different roles: + +| File | Role | +| ---- | ---- | +| `0x000e_floating-point-data-type.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x000e_floating-point-data-type.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. If a database gets messy, delete the `.bndb` and re-import the `.bin` from Step 7 — the firmware is never at risk. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 13. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at `main` and Hack Live (Project 1) + +### Step 10: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 11. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. This is the whole reason the lab works cleanly — you never have to drive a reset from outside the GUI. +> +> Use the address you actually want to stop at: +> +> | What you want to stop at | Project 1 `0x000e` | Project 2 `0x0011` | Command | +> | --- | --- | --- | --- | +> | `main` (once per reset) | `0x10000234` | `0x10000238` | `BP_ADDR=0x10000234 ./debug-server.sh` | +> | The **loop** — the `printf` call, hit every iteration | `0x10000244` | `0x1000024a` | `BP_ADDR=0x10000244 ./debug-server.sh` | +> +> ```bash +> BP_ADDR=0x10000234 ./debug-server.sh # park at main +> BP_ADDR=0x10000244 ./debug-server.sh # park in the loop instead +> ``` +> +> ```powershell +> $env:BP_ADDR="0x10000234"; .\debug-server.ps1 # park at main +> $env:BP_ADDR="0x10000244"; .\debug-server.ps1 # park in the loop +> ``` +> +> **Note the loop address differs from Week 4 and between the two projects.** In Project 1 the `bl __wrap_printf` sits at `0x10000244`; in Project 2 it sits at `0x1000024a`, because Project 2 loads the pair with `ldrd` first. Both were verified against the Release `.elf` with `arm-none-eabi-objdump` and confirmed live on hardware. +> +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 13) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 11: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 10 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length and handles step-over itself. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. Stops are reported as `Breakpoint` (not `SingleStep`). +> +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 10), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. +> +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. +> +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. It is not the adapter for this lab. The dropdown is a combo box, so an accidental arrow-key press can land on it — always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +> **Watch for an off-screen error dialog.** When a connection fails, Binary Ninja pops a `Binary Ninja critical alert` window that can be positioned mostly outside the main window, which makes it look like nothing happened. If the connect seems to do nothing, check your other display. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 12: Find `main` without relying on its address + +`main` moves between these programs (`0x10000234` vs `0x10000238`), so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186: 4914 ldr r1, [pc, #80] ; @ 0x100001d8 +10000188: 4788 blx r1 ; runtime_init +1000018a: 4914 ldr r1, [pc, #80] ; @ 0x100001dc +1000018c: 4788 blx r1 ; main <-- the fixed anchor +1000018e: 4914 ldr r1, [pc, #80] ; @ 0x100001e0 +10000190: 4788 blx r1 ; exit +10000192: be00 bkpt 0x0000 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in both projects, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234` for Project 1 and `0x10000238` for Project 2. + +### Step 13: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +> **Why older drafts used the command port.** Binary Ninja's **GDB RSP** adapter is its own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 FPB comparators need 2 bytes, so OpenOCD rejected it with `only breakpoints of two bytes length supported`. The old workaround was to arm breakpoints by hand over telnet. **The GDB MI adapter does not have this problem** — it drives real `arm-none-eabi-gdb`, which sends the right length. So everything below is done in the GUI. The command port still exists as a fallback (see the end of this step), but you do not need it. + +#### Where you can stop + +| You want to stop at | Address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | Project 1 `0x10000234`, Project 2 `0x10000238` | The server starts parked there with `BP_ADDR` (Step 10), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **The loop** (`printf` call) | Project 1 `0x10000244`, Project 2 `0x1000024a` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | + +#### Set the loop breakpoint in the GUI + +1. Press `G`, type the loop address (`0x10000244` for Project 1, `0x1000024a` for Project 2), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the loop address and reports it as a **Breakpoint** — verified: `Stopped (Breakpoint) at 0x10000244`. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 11). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +#### Stepping + +With the target halted at the breakpoint, **Step Into** (`F7`) and **Step Over** (`F8`) run through real GDB and move the PC. Verified: `0x10000244 -> 0x100030ec -> 0x100030ee -> ...`. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, so **Step Over** at the `printf` call behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 14 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +> **If you ever need the command port.** It is still there — `nc 127.0.0.1 4444`, and `bp 2 hw` still arms a breakpoint, `rbp ` / `rbp all` still remove them. It is the fallback if you switch back to the **GDB RSP** adapter, whose 1-byte breakpoints the GUI cannot set. With GDB MI you do not need it for this lab. + +### Step 14: HACK IT LIVE — change the printed double + +Project 1's `main` sets `r4 = 0`, loads the high word of the double into `r5`, and on every iteration copies them into the `r2:r3` argument pair before calling `printf`. We break on that call and change the value live: + +1. Press `G`, go to `0x10000244` (the `bl __wrap_printf`). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the program counter at `0x10000244`, `r2 = 0x00000000`, and `r3 = 0x40454000`. +4. Open the **Registers** widget (bug icon -> **Registers**). +5. The ABI passes the promoted `double` in `r2:r3` — `r2` is the low 32 bits, `r3` the high 32 bits. Together they are `0x40454000_00000000`, the IEEE-754 encoding of `42.5`. +6. **Set `r3` to `0x4058C000`** — the high word of `99.0` — from Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r2", 0x00000000) # low word of the 99.0 double (unchanged) + dbg.set_reg_value("r3", 0x4058C000) # high word of the 99.0 double + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click a register in the **Registers** widget, press `E` (edit), type the hex value, and press Enter. The widget may not repaint, but the write reaches the target — you confirm it by the printed output in the next steps. +7. **Move the breakpoint past the call.** You want `printf` to run once and then stop, so move the breakpoint from `0x10000244` to the instruction *after* the call, `0x10000248` (the `b.n` that closes the loop): remove the breakpoint at `0x10000244` and set a hardware breakpoint at `0x10000248`. Two reasons not to just click **Step Over** here: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `__wrap_printf` on this raw `.bin` because the image carries no symbol for the call. Moving the breakpoint to the return site is deterministic. +8. Click **Resume** in Binary Ninja. The core executes `bl __wrap_printf` with `r2:r3 = 0x4058C000_00000000`, so this iteration prints `fav_num: 99.000000`, then stops at `0x10000248`. +9. Look at your serial monitor — the `screen` session on the Pico's USB serial port — and at the **Target** tab in Binary Ninja: + + ``` + fav_num: 99.000000 + ``` + +You changed a running program's output without touching the binary. + +### Step 14b: HACK THE STRING LIVE — change `fav_num:` to `myvalue:` + +The text `"fav_num: %f\r\n"` lives in flash (`.rodata`) at `0x100034a8`, and flash is **read-only at runtime** — a debugger write there does not stick. So instead of overwriting the text in place, redirect the pointer: at the `printf` call, `r0` holds the string address, so point `r0` at a replacement string you place in RAM. + +1. Arm the breakpoint at the `printf` call and hit it, exactly as in Step 14 steps 1-3. At the stop, `r0 = 0x100034a8`, `r2 = 0x00000000`, and `r3 = 0x40454000`. +2. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console** (`Plugins -> Python Console`) — no command port needed: + ```python + dbg.write_memory(0x20080000, b"myvalue: %f\r\n\x00") + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. That writes the bytes `6d 79 76 61 6c 75 65 3a 20 25 66 0d 0a 00` = `"myvalue: %f\r\n\0"`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. If you want the value hack too, set `r3` to `0x4058C000` as in Step 14. Then move the breakpoint past the call in the GUI (remove it at `0x10000244`, set one at `0x10000248`) and click **Resume**. The core runs `printf` with `r0` pointing at your RAM string and `r2:r3` holding `99.0`, so this iteration prints: + ``` + myvalue: 99.000000 + ``` + then stops at `0x10000248`. + +Like the value hack, this is **one iteration only**: the loop reloads `r0` (and `r2`/`r3`) from flash/literals on every pass, so the next line is `fav_num: 42.500000` again. The permanent version is the static patch in Step 18b. + +### Step 15: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x1000023e`, which copies `r4` and `r5` into `r2` and `r3` again. `r4` and `r5` were set once before the loop (`movs r4, #0`, `ldr r5, [pc, #12]`), so your `r3` edit is overwritten and the next line is `fav_num: 42.500000`. The live edit changed one iteration only. There is no variable in memory to change; the value is baked into the instruction/literal pool. To make `99.0` permanent we must patch the constant. That is the static pass. + +Press **Pause** to stop the output flood. + +### Step 15b: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch (Project 1) + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10002f5c()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x10002f5c`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `uart_init` + +1. `G` -> `0x10000e18`. +2. `Y` -> `uint uart_init(uart_inst_t *uart, uint baudrate)`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100030ec`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +#### Worked example: `_ftoa` (the double formatter) + +1. `G` -> `0x10001890`. +2. `Y` -> `unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)`. + +This is the function that actually turns the double into the `42.500000` text. It is why the `pico_double` `__aeabi_*` helpers are in the image at all. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` only calls `stdio_init_all` and `printf`, so we follow that chain down: `stdio_init_all` pulls in the stdio/UART setup, and `printf` lands in the SDK's `__wrap_printf`, which reaches the `pico_double` formatter. + +The call chain for this project: + +``` +main +├── stdio_init_all +│ └── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +└── __wrap_printf ── __wrap_vprintf + ├── vfctprintf ── _vsnprintf + │ ├── _ftoa / _etoa ── __wrap___aeabi_* (the pico_double helpers) + │ └── _ntoa_format / _out_rev + ├── stdio_out_chars_crlf + └── time_us_64 +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x10002ca8` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002d04` | `exit` | `void exit(int)` | +| `0x10002d0c` | `runtime_init` | `void runtime_init(void)` | +| `0x10002d38` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002e48` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10002f34` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10002f5c` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003028` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100030ec` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100032a8` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100033e8` | `strlen` | `size_t strlen(const char*)` | +| `0x10000254` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e18` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10000da8` | `time_us_64` | `uint64_t time_us_64(void)` | + +**Project 1 — resolve the `pico_double` formatting helpers `printf` reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10001384` | `__wrap___aeabi_dadd` | `double __wrap___aeabi_dadd(double, double)` | +| `0x100013ac` | `__wrap___aeabi_dsub` | `double __wrap___aeabi_dsub(double, double)` | +| `0x100013d4` | `__wrap___aeabi_dmul` | `double __wrap___aeabi_dmul(double, double)` | +| `0x10001420` | `__wrap___aeabi_ddiv` | `double __wrap___aeabi_ddiv(double, double)` | +| `0x100014bc` | `__wrap___aeabi_i2d` | `double __wrap___aeabi_i2d(int)` | +| `0x100014e0` | `__wrap___aeabi_ui2d` | `double __wrap___aeabi_ui2d(unsigned)` | +| `0x10001504` | `__wrap___aeabi_d2iz` | `int __wrap___aeabi_d2iz(double)` | +| `0x10001528` | `__wrap___aeabi_d2uiz` | `unsigned __wrap___aeabi_d2uiz(double)` | +| `0x1000154c` | `__wrap___aeabi_dcmpun` | `int __wrap___aeabi_dcmpun(double, double)` | +| `0x10001570` | `__wrap___aeabi_dcmplt` | `int __wrap___aeabi_dcmplt(double, double)` | +| `0x10001598` | `__wrap___aeabi_dcmple` | `int __wrap___aeabi_dcmple(double, double)` | +| `0x100015c0` | `__wrap___aeabi_dcmpge` | `int __wrap___aeabi_dcmpge(double, double)` | +| `0x100015e8` | `__wrap___aeabi_dcmpgt` | `int __wrap___aeabi_dcmpgt(double, double)` | +| `0x1000160c` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x100016a8` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x1000187c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x10001890` | `_ftoa` | `unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | +| `0x10001d50` | `_etoa` | `unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | +| `0x100022c4` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10000dbc` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10000fec` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`__wrap_printf` is the real symbol.** `printf` in our source compiles to the SDK's `__wrap_printf` (which forwards to `__wrap_vprintf`). Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. +> +> **`stdio_init_all` returns `bool`, not `void`** — `_Bool stdio_init_all(void)` in the ELF. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x10002ca8: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x10002d04: ("exit", "void exit(int)"), +> 0x10002d0c: ("runtime_init", "void runtime_init(void)"), +> 0x10002d38: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10002e48: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x10002f34: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10002f5c: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x10003028: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x100030ec: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100032a8: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x100033e8: ("strlen", "size_t strlen(const char*)"), +> 0x10000254: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e18: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10000da8: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001384: ("__wrap___aeabi_dadd", "double __wrap___aeabi_dadd(double, double)"), +> 0x100013ac: ("__wrap___aeabi_dsub", "double __wrap___aeabi_dsub(double, double)"), +> 0x100013d4: ("__wrap___aeabi_dmul", "double __wrap___aeabi_dmul(double, double)"), +> 0x10001420: ("__wrap___aeabi_ddiv", "double __wrap___aeabi_ddiv(double, double)"), +> 0x100014bc: ("__wrap___aeabi_i2d", "double __wrap___aeabi_i2d(int)"), +> 0x100014e0: ("__wrap___aeabi_ui2d", "double __wrap___aeabi_ui2d(unsigned)"), +> 0x10001504: ("__wrap___aeabi_d2iz", "int __wrap___aeabi_d2iz(double)"), +> 0x10001528: ("__wrap___aeabi_d2uiz", "unsigned __wrap___aeabi_d2uiz(double)"), +> 0x1000154c: ("__wrap___aeabi_dcmpun", "int __wrap___aeabi_dcmpun(double, double)"), +> 0x10001570: ("__wrap___aeabi_dcmplt", "int __wrap___aeabi_dcmplt(double, double)"), +> 0x10001598: ("__wrap___aeabi_dcmple", "int __wrap___aeabi_dcmple(double, double)"), +> 0x100015c0: ("__wrap___aeabi_dcmpge", "int __wrap___aeabi_dcmpge(double, double)"), +> 0x100015e8: ("__wrap___aeabi_dcmpgt", "int __wrap___aeabi_dcmpgt(double, double)"), +> 0x1000160c: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x100016a8: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x1000187c: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> 0x10001890: ("_ftoa", "unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)"), +> 0x10001d50: ("_etoa", "unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)"), +> 0x100022c4: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x10000dbc: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10000fec: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `gpio_function_t`, `uart_inst_t`, plus `uint`, `va_list`, `out_fct_type`, and `clock_handle_t`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. It reads: + +```c +int32_t main(void) +{ + stdio_init_all(); + do + { + __wrap_printf("fav_num: %f\r\n", 0, 0x40454000); + } while (true); +} +``` + +The trailing pair is the promoted `double`: `r2 = 0`, `r3 = 0x40454000`. Binary Ninja already knows the calling convention, so once `__wrap_printf` is typed `int __wrap_printf(const char*, ...)`, the pair is shown as data. Now make the hack permanent. + +### Step 18: Patch `0x40454000` to `0x4058C000` in the GUI + +Go to `0x1000024c`: + +```asm +1000024c: 40454000 .word 0x40454000 +``` + +That word is the high half of the `double` `42.5`. Its bytes, little-endian, are `00 40 45 40`. Change them to `00 c0 58 40`, the high half of `99.0`: + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x000e` | `0x1000024c` | `00 40 45 40` | `00 c0 58 40` | high word of `42.5` -> `99.0` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000024c` and change `00 40 45 40` to `00 c0 58 40`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000024c, bytes.fromhex("00c05840")) +print(bv.read(0x1000024c, 4)) # -> b'\x00\xc0X@' +``` + +After reanalysis the literal reads `0x4058C000`, and the decompiler shows `__wrap_printf("fav_num: %f\r\n", 0, 0x4058c000)`. + +### Step 18b: Patch the string `fav_num:` to `myvalue:` in the GUI + +The format string `"fav_num: %f\r\n"` starts at `0x100034a8`. Its first eight bytes are `66 61 76 5f 6e 75 6d 3a` (`fav_num:`). Change them to `6d 79 76 61 6c 75 65 3a` (`myvalue:`), leaving the ` %f\r\n` tail untouched, so the line prints `myvalue: 99.000000`. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x000e` | `0x100034a8` | `66 61 76 5f 6e 75 6d 3a` | `6d 79 76 61 6c 75 65 3a` | `fav_num:` -> `myvalue:` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x100034a8` and change the eight bytes `66 61 76 5f 6e 75 6d 3a` to `6d 79 76 61 6c 75 65 3a`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100034a8, b"myvalue:") +print(bv.read(0x100034a8, 15)) # -> b'myvalue: %f\r\n\x00' +``` + +Keep the replacement exactly eight bytes. If you use a shorter string you must pad it, or `%f` shifts and `printf` reads the wrong argument. A longer string would overwrite the ` %f` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x000e_floating-point-data-type", "build"), "0x000e_floating-point-data-type-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15308 /.../build/0x000e_floating-point-data-type-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3bcc` = 15308). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so `open("0x000e_floating-point-data-type-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x000e_floating-point-data-type-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x000e_floating-point-data-type-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x000e_floating-point-data-type", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x000e_floating-point-data-type-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +### Step 21: Flash and verify `fav_num: 99.000000` + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Open the serial monitor: + +``` +myvalue: 99.000000 +myvalue: 99.000000 +myvalue: 99.000000 +... +``` + +**42.5 became 99.0, permanently, with one 32-bit word changed and no source code.** + +> **Faster: flash over the Debug Probe (no BOOTSEL).** The repo's `flash.sh` writes the raw `.bin` straight into XIP flash over SWD (`program 0x10000000 verify reset exit`), so you never touch BOOTSEL or a UF2. Run it from a terminal (`./flash.sh `), or from the Binary Ninja console **without freezing it** — use `subprocess.Popen`, which returns immediately, and send OpenOCD's output to a log file. (`subprocess.run` blocks the console until the flash finishes; do not use it here.) +> +> ```python +> import os, subprocess +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +> bin_path = os.path.join(os.path.join(root, "0x000e_floating-point-data-type", "build"), "0x000e_floating-point-data-type-h.bin") +> log = os.path.join(os.path.join(root, "0x000e_floating-point-data-type", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> The `pkill` frees the probe first; on Windows use `subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"])`. +> +> The console is free the moment this returns. Check it with `print(p.poll())` (`None` = still running, `0` = done) or read `flash.log` — success ends with `** Verified OK **`. +> +> The same non-blocking form without the script: +> +> ```python +> import os, subprocess +> ocd = os.path.expanduser("~/.pico-sdk/openocd/0.12.0+dev") +> bin_path = os.path.join(os.path.join(root, "0x000e_floating-point-data-type", "build"), "0x000e_floating-point-data-type-h.bin") +> log = os.path.join(os.path.join(root, "0x000e_floating-point-data-type", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([f"{ocd}/openocd", "-s", f"{ocd}/scripts", +> "-f", "interface/cmsis-dap.cfg", "-f", "target/rp2350.cfg", +> "-c", "adapter speed 5000", +> "-c", f"program {bin_path} 0x10000000 verify reset exit"], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> **The Debug Probe is single-owner.** If Binary Ninja is still attached (the `debug-server.sh` OpenOCD is running), the flash cannot grab the probe. Detach in Binary Ninja and stop that OpenOCD first: +> +> ```bash +> # macOS / Linux +> pkill -TERM -f openocd +> ``` +> ```powershell +> # Windows +> Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +> ``` +> +> Success looks like `Programming Finished` -> `Verified OK` -> `Resetting Target`. On Windows use `flash.ps1` (`.\flash.ps1 -Bin `) the same way. +--- + +## Part 5: Dynamic — Break at `main` and Hack Live (Project 2) + +### Step 22: Reflash Project 2 and reload Binary Ninja + +Part 4 left the Pico running the patched Project 1 image. Put the original Project 2 back and start a fresh session. + +1. Stop any running debug server so the flash script can use the probe: + + ```bash + # macOS / Linux + pkill -TERM -f openocd + ``` + ```powershell + # Windows + Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process + ``` + +2. Flash the original Project 2 image: + + ```bash + # macOS / Linux + ./flash.sh 0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin + ``` + ```powershell + # Windows + .\flash.ps1 -Bin 0x0011_double-floating-point-data-type\build\0x0011_double-floating-point-data-type.bin + ``` + + **Or do steps 1-2 from the Binary Ninja console** (the active view is still Project 1, so take the repo root from the marker file and point at the Project 2 `.bin`): + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0011_double-floating-point-data-type", "build", "0x0011_double-floating-point-data-type.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first + subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("flashing Project 2 in the background; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0011_double-floating-point-data-type", "build", "0x0011_double-floating-point-data-type.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("flashing Project 2 in the background; log:", log) + ``` + +3. Start the debug server again (Step 10) and wait for `Listening on port 3333`. +4. Load Project 2 and save its database — see Step 22b. +5. Connect Binary Ninja again (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +Confirm the Pico prints `fav_num: 42.525250`. + +### Step 22b: Load Project 2 into Binary Ninja and save the database + +Exactly like Steps 7-8, but for Project 2. **Use `File -> Open with Options...`** (not plain `File -> Open`), select `0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin`, and set: + +- **Architecture:** `thumb2` +- **Platform:** `thumb2` +- **Base Address:** `0x10000000` + +Click **Open**. Then press `G`, type `0x10000000`, and confirm the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you see data at `0x00000000`, close the tab and redo it with `Open with Options`. + +Save it with `File -> Save As...` as `0x0011_double-floating-point-data-type.bndb` (next to the `.bin`). From now on open the `.bndb`, not the `.bin`; save with `Cmd+S` / `Ctrl+S` after every rename or patch. + +> **Console equivalent:** +> ```python +> load("0x0011_double-floating-point-data-type/build/0x0011_double-floating-point-data-type.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +Then resolve the functions for Project 2 the same way as Project 1 — Step 26. + +### Step 23: Break at `main` + +`main` is at `0x10000238` in this project. The GUI sets breakpoints fine (Step 13); the only caution is not to drive `reset run` from the port while Binary Ninja is attached (it desyncs Binary Ninja's view). Use `BP_ADDR`, which arms `main` before Binary Ninja connects: + +1. Stop the server (Ctrl-C), then start it parked at `main`: + ```bash + # macOS / Linux + BP_ADDR=0x10000238 ./debug-server.sh + ``` + ```powershell + # Windows + $env:BP_ADDR="0x10000238"; .\debug-server.ps1 + ``` + + **Or restart it from the Binary Ninja console** — kill any running server, then start it parked at `main`: + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # kill any running server first + subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000238"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("OpenOCD restarted parked at main; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # kill any running server first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000238"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("OpenOCD restarted parked at main; log:", log) + ``` +2. Connect Binary Ninja (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +The target is already halted at `main` when Binary Ninja connects, and the sidebar reads `Stopped at 0x10000238`. + +> If you instead want to reach `main` on an already-connected session, you must Detach, send `reset run` from the port, then reconnect. Arming `main` and resetting while attached leaves the sidebar showing a stale address. + +`main` loads the whole 64-bit `double` from a single literal-pool address, then loops: copy the pair into `r2:r3` and call `printf`. The whole thing is one function: + +```asm +10000238: b538 push {r3, r4, r5, lr} +1000023a: a506 add r5, pc, #24 ; adr r5, 0x10000254 +1000023c: e9d5 4500 ldrd r4, r5, [r5] ; r4 = low word, r5 = high word +10000240: f002 fe90 bl 0x10002f64 ; stdio_init_all +10000244: 4622 mov r2, r4 +10000246: 462b mov r3, r5 +10000248: 4801 ldr r0, [pc, #4] ; -> 0x10000250 = 0x100034b0 (format string) +1000024a: f002 ff53 bl 0x100030f4 ; __wrap_printf +1000024e: e7f9 b.n 0x10000244 +10000250: 100034b0 .word 0x100034b0 +10000254: 645a1cac .word 0x645a1cac +10000258: 4045433b .word 0x4045433b +``` + +Notice the `ldrd r4, r5, [r5]` — a single 64-bit load from the literal pool at `0x10000254`, which fills **both** halves of the double at once. That is the structural difference from Project 1, where the low half was a register zero (`movs r4, #0`) and only the high half lived in the pool. + +Look at the **Registers** widget at `0x1000024a`: `r2 = 0x645A1CAC` (low) and `r3 = 0x4045433B` (high). Together that is `0x4045433B_645A1CAC`, the IEEE-754 encoding of `42.52525`. + +### Step 24: Inspect the double argument live + +The `double` crosses the ABI in two registers. At the `printf` call the pair is exactly the literal-pool word pair: + +| Register | Value | Role | +| -------- | ----- | ---- | +| `r2` | `0x645A1CAC` | low 32 bits of `42.52525` | +| `r3` | `0x4045433B` | high 32 bits of `42.52525` | + +Step Over through `0x10000244` (`mov r2, r4`) and `0x10000246` (`mov r3, r5`) and watch `r2`/`r3` populate from `r4`/`r5`. This is C's variadic rule in action: `printf`'s `%lf` receives a 64-bit `double`, and on this target a `double` argument travels in `r2:r3`. + +> **Why `r2:r3`, not `r0:r1`?** The first variadic argument goes after the named format pointer, so `printf(fmt, value)` puts `fmt` in `r0` and the promoted `double` in `r2:r3`. That leaves `r1` unused here, which is why the format string pointer is `r0` and the number is `r2:r3`. + +### Step 25: HACK IT LIVE — change the printed double + +1. Press `G`, go to `0x1000024a` (the `bl __wrap_printf`). +2. Set a **hardware execute** breakpoint at `0x1000024a` in the GUI (`Debugger -> Add Hardware Breakpoint...`; not `F2`). Note `0x1000024a` — Project 2's loop sits at a different address than Project 1's. +3. Click **Resume** in Binary Ninja. The target is already looping, so the breakpoint fires on the next pass. Binary Ninja stops with `r2 = 0x645A1CAC`, `r3 = 0x4045433B`. +4. Overwrite both halves with the encoding of `99.99` (`0x4058FF5C_28F5C28F`): + ```python + dbg.set_reg_value("r2", 0x28F5C28F) # low word of the 99.99 double + dbg.set_reg_value("r3", 0x4058FF5C) # high word of the 99.99 double + ``` + (Or right-click each register in the **Registers** widget, press `E`, type the hex value, and press Enter.) +5. **Move the breakpoint past the call.** `0x1000024e` is the instruction right after the `bl __wrap_printf`. Remove the breakpoint at `0x1000024a` and set a hardware breakpoint at `0x1000024e`, then click **Resume**. The core runs `printf` with `r2:r3 = 0x4058FF5C_28F5C28F` and stops at `0x1000024e`. (Not **Step Over** — it steps into the call on this symbol-less `.bin`, and a breakpoint left on the current PC re-traps the step; Step 13 explains both.) +6. Look at your serial monitor and the **Target** tab: + + ``` + fav_num: 99.990000 + ``` + +Press **Resume** and the next iteration prints `fav_num: 42.525250` again, because the loop reloads `r2`/`r3` from `r4`/`r5` each pass. The live hack is temporary; the static patch makes it permanent. + +### Step 25b: HACK THE STRING LIVE — change `fav_num:` to `myvalue:` + +Same idea as Project 1, different addresses. Here the format string is at `0x100034b0` and the `printf` call is at `0x1000024a`. + +1. Hit the breakpoint at `0x1000024a` as in Step 25. At the stop, `r0 = 0x100034b0`, `r2 = 0x645A1CAC`, `r3 = 0x4045433B`. +2. Write the replacement string to free RAM at `0x20080000` from the **Python console** (`dbg.write_memory` — no command port needed): + ```python + dbg.write_memory(0x20080000, b"myvalue: %lf\r\n\x00") + ``` + Bytes `6d 79 76 61 6c 75 65 3a 20 25 6c 66 0d 0a 00` = `"myvalue: %lf\r\n\0"`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. If you want the value hack too, set `r2 = 0x28F5C28F` and `r3 = 0x4058FF5C` as in Step 25. Then move the breakpoint past the call in the GUI (remove it at `0x1000024a`, set one at `0x1000024e`) and click **Resume**. This iteration prints: + ``` + myvalue: 99.990000 + ``` + then stops at `0x1000024e`. One iteration only — the loop reloads `r0` (and `r2`/`r3`) each pass. The permanent version is the static patch in Step 28b. + +### Step 25c: Kill the debugger and OpenOCD + +Same as Step 15b: click the **X** (**Kill**) in the **Debugger** sidebar (or **`Debugger -> Kill`**), then stop OpenOCD from the Binary Ninja console: + +**macOS / Linux:** + +```python +import subprocess +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe +``` + +**Windows:** + +```python +import subprocess +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe +``` +--- + +## Part 6: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the Binary Ninja GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +The mechanics are identical to Step 16, so here are the worked examples for the functions that are specific to this project. + +#### `main` + +1. `G` -> `0x10000238`. +2. `Y` -> `int main(void)` (Binary Ninja shows `int32_t main(void)` — the same 32-bit `int`). + +#### `stdio_uart_init` + +1. `G` -> `0x100032b0`. +2. `Y` -> `void stdio_uart_init(void)`. + +#### `_ftoa` and `_etoa` + +Same formatters as Project 1, eight bytes higher: `_ftoa` at `0x10001898` (`unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)`) and `_etoa` at `0x10001d58` (same prototype). + +#### `stdio_init_all` and `__wrap_printf` + +Same as Project 1, different addresses: `stdio_init_all` at `0x10002f64` (`bool stdio_init_all(void)`), and `__wrap_printf` at `0x100030f4` (`int __wrap_printf(const char *fmt, ...)`). + +Then work down the table the same way. + +Same idea as Project 1: **our code plus what it calls**, not the whole SDK. The call chain here is identical to Project 1 — because `%lf` and `%f` both route into the same `pico_double` formatter: + +``` +main +├── stdio_init_all +│ └── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +└── __wrap_printf ── __wrap_vprintf + ├── vfctprintf ── _vsnprintf + │ ├── _ftoa / _etoa ── __wrap___aeabi_* (the pico_double helpers) + │ └── _ntoa_format / _out_rev + ├── stdio_out_chars_crlf + └── time_us_64 +``` + +One thing in this project has **no separate call**, because the compiler emitted it as a single instruction: the 64-bit literal load is the `ldrd r4, r5, [r5]` you see inside `main`. There is no helper function to rename for it — it is two `.word`s in the pool at `0x10000254`. + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000238`** | **`main`** | **`int main(void)`** | +| `0x10002cb0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002d0c` | `exit` | `void exit(int)` | +| `0x10002d14` | `runtime_init` | `void runtime_init(void)` | +| `0x10002d40` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002e50` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10002f3c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10002f64` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003030` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100030f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100032b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100033f0` | `strlen` | `size_t strlen(const char*)` | +| `0x1000025c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e20` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10000db0` | `time_us_64` | `uint64_t time_us_64(void)` | + +**Project 2 — resolve the `pico_double` formatting helpers `printf` reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000138c` | `__wrap___aeabi_dadd` | `double __wrap___aeabi_dadd(double, double)` | +| `0x100013b4` | `__wrap___aeabi_dsub` | `double __wrap___aeabi_dsub(double, double)` | +| `0x100013dc` | `__wrap___aeabi_dmul` | `double __wrap___aeabi_dmul(double, double)` | +| `0x10001428` | `__wrap___aeabi_ddiv` | `double __wrap___aeabi_ddiv(double, double)` | +| `0x100014c4` | `__wrap___aeabi_i2d` | `double __wrap___aeabi_i2d(int)` | +| `0x100014e8` | `__wrap___aeabi_ui2d` | `double __wrap___aeabi_ui2d(unsigned)` | +| `0x1000150c` | `__wrap___aeabi_d2iz` | `int __wrap___aeabi_d2iz(double)` | +| `0x10001530` | `__wrap___aeabi_d2uiz` | `unsigned __wrap___aeabi_d2uiz(double)` | +| `0x10001554` | `__wrap___aeabi_dcmpun` | `int __wrap___aeabi_dcmpun(double, double)` | +| `0x10001578` | `__wrap___aeabi_dcmplt` | `int __wrap___aeabi_dcmplt(double, double)` | +| `0x100015a0` | `__wrap___aeabi_dcmple` | `int __wrap___aeabi_dcmple(double, double)` | +| `0x100015c8` | `__wrap___aeabi_dcmpge` | `int __wrap___aeabi_dcmpge(double, double)` | +| `0x100015f0` | `__wrap___aeabi_dcmpgt` | `int __wrap___aeabi_dcmpgt(double, double)` | +| `0x10001614` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x100016b0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x10001884` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x10001898` | `_ftoa` | `unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | +| `0x10001d58` | `_etoa` | `unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)` | +| `0x100022cc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10000dc4` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10000ff4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | + +Python console shortcut (resolves name **and** type): + +```python +from binaryninja import Symbol, SymbolType +# The raw .bin has no headers, so these SDK types don't exist. set_user_type() +# re-parses each signature as C, so an undefined name raises +# "SyntaxError: unknown type name '...'". Define them first. +sdk = bv.parse_types_from_string(""" +typedef unsigned int uint; +typedef char* va_list; +typedef unsigned long clock_handle_t; +typedef void (*out_fct_type)(char, void*, size_t, size_t); +struct stdio_driver; +typedef struct stdio_driver stdio_driver_t; +struct uart_inst; +typedef struct uart_inst uart_inst_t; +enum gpio_function { + GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, + GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, + GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +}; +typedef enum gpio_function gpio_function_t; +""") +for name, ty in sdk.types.items(): + bv.define_user_type(name, ty) + +# address: (name, signature) +funcs = { + 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), + 0x10000186: ("platform_entry", "void platform_entry(void)"), + 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), + 0x100001e4: ("_init", "void _init(void)"), + 0x10000210: ("frame_dummy", "void frame_dummy(void)"), + 0x10000238: ("main", "int main(void)"), + 0x10002cb0: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), + 0x10002d0c: ("exit", "void exit(int)"), + 0x10002d14: ("runtime_init", "void runtime_init(void)"), + 0x10002d40: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), + 0x10002e50: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), + 0x10002f3c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), + 0x10002f64: ("stdio_init_all", "bool stdio_init_all(void)"), + 0x10003030: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), + 0x100030f4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), + 0x100032b0: ("stdio_uart_init", "void stdio_uart_init(void)"), + 0x100033f0: ("strlen", "size_t strlen(const char*)"), + 0x1000025c: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), + 0x10000e20: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), + 0x10000db0: ("time_us_64", "uint64_t time_us_64(void)"), + 0x1000138c: ("__wrap___aeabi_dadd", "double __wrap___aeabi_dadd(double, double)"), + 0x100013b4: ("__wrap___aeabi_dsub", "double __wrap___aeabi_dsub(double, double)"), + 0x100013dc: ("__wrap___aeabi_dmul", "double __wrap___aeabi_dmul(double, double)"), + 0x10001428: ("__wrap___aeabi_ddiv", "double __wrap___aeabi_ddiv(double, double)"), + 0x100014c4: ("__wrap___aeabi_i2d", "double __wrap___aeabi_i2d(int)"), + 0x100014e8: ("__wrap___aeabi_ui2d", "double __wrap___aeabi_ui2d(unsigned)"), + 0x1000150c: ("__wrap___aeabi_d2iz", "int __wrap___aeabi_d2iz(double)"), + 0x10001530: ("__wrap___aeabi_d2uiz", "unsigned __wrap___aeabi_d2uiz(double)"), + 0x10001554: ("__wrap___aeabi_dcmpun", "int __wrap___aeabi_dcmpun(double, double)"), + 0x10001578: ("__wrap___aeabi_dcmplt", "int __wrap___aeabi_dcmplt(double, double)"), + 0x100015a0: ("__wrap___aeabi_dcmple", "int __wrap___aeabi_dcmple(double, double)"), + 0x100015c8: ("__wrap___aeabi_dcmpge", "int __wrap___aeabi_dcmpge(double, double)"), + 0x100015f0: ("__wrap___aeabi_dcmpgt", "int __wrap___aeabi_dcmpgt(double, double)"), + 0x10001614: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), + 0x100016b0: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), + 0x10001884: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), + 0x10001898: ("_ftoa", "unsigned int _ftoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)"), + 0x10001d58: ("_etoa", "unsigned int _etoa(out_fct_type, char*, size_t, size_t, double, unsigned int, unsigned int, unsigned int)"), + 0x100022cc: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), + 0x10000dc4: ("busy_wait_us", "void busy_wait_us(uint64_t)"), + 0x10000ff4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +} +for addr, (name, sig) in funcs.items(): + bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) + f = bv.get_function_at(addr) + if f is not None: + f.set_user_type(sig) +``` + +The decompiler now shows `main` loading the `double` pair and looping. We make two changes: + +- **Change the printed value from `42.52525` to `99.99`** by patching **both** literal words. +- **Rename the label** `fav_num:` to `myvalue:` by patching the format string. + +### Step 27: Patch 1 — the low word `0x645A1CAC` to `0x28F5C28F` + +`99.99` is `0x4058FF5C_28F5C28F`, so the low word changes from `0x645A1CAC` to `0x28F5C28F`. At `0x10000254` the stored bytes are `ac 1c 5a 64`; change them to `8f c2 f5 28`: + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0011` | `0x10000254` | `ac 1c 5a 64` | `8f c2 f5 28` | low word of `42.52525` -> `99.99` | + +**Hex view:** lock off, go to `0x10000254`, change `ac 1c 5a 64` to `8f c2 f5 28`, reanalyze. **Or the Python console:** + +```python +bv.write(0x10000254, bytes.fromhex("8fc2f528")) +print(bv.read(0x10000254, 4)) # -> b'\x8f\xc2\xf5(' +``` + +### Step 28: Patch 2 — the high word `0x4045433B` to `0x4058FF5C` + +At `0x10000258` the stored bytes are `3b 43 45 40`; change them to `5c ff 58 40`: + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0011` | `0x10000258` | `3b 43 45 40` | `5c ff 58 40` | high word of `42.52525` -> `99.99` | + +**Hex view:** go to `0x10000258`, change `3b 43 45 40` to `5c ff 58 40`, reanalyze. **Or the Python console:** + +```python +bv.write(0x10000258, bytes.fromhex("5cff5840")) +for addr in (0x10000254, 0x10000258): + print(hex(addr), bv.read(addr, 4).hex()) +# -> 0x10000254 8fc2f528 +# -> 0x10000258 5cff5840 +``` + +> **Both words are required.** `42.52525` has a repeating binary fraction, so its low word is non-zero (`0x645A1CAC`). Patching only the high word leaves the low 20 mantissa bits from `0.52525`, and `printf` prints a wrong hybrid. Compare Project 1, where `42.5` is exact and the low word was already `0x00000000`, so one word sufficed. + +### Step 28b: Patch the string `fav_num:` to `myvalue:` + +The format string starts at `0x100034b0`; change its first eight bytes `66 61 76 5f 6e 75 6d 3a` (`fav_num:`) to `6d 79 76 61 6c 75 65 3a` (`myvalue:`): + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0011` | `0x100034b0` | `66 61 76 5f 6e 75 6d 3a` | `6d 79 76 61 6c 75 65 3a` | `fav_num:` -> `myvalue:` | + +```python +bv.write(0x100034b0, b"myvalue:") +print(bv.read(0x100034b0, 15)) # -> b'myvalue: %lf\r\n\x00' +``` + +Exactly eight bytes, same rule as Project 1: a shorter string must be padded, a longer one overwrites the ` %lf` tail. + +### Step 29: Export, convert, and flash + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0011_double-floating-point-data-type", "build"), "0x0011_double-floating-point-data-type-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15324 /.../build/0x0011_double-floating-point-data-type-h.bin +``` + +Same as Project 1: `seg.start` is the load base and `seg.data_length` is the image size (here `0x3bdc` = 15324) — both read from the view, and no relative path (the console's CWD is read-only). + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0011_double-floating-point-data-type-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0011_double-floating-point-data-type-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the Binary Ninja console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21 (stop any running OpenOCD first, and use `Popen`, not `run`, so the console is not blocked): + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +bin_path = os.path.join(os.path.join(root, "0x0011_double-floating-point-data-type", "build"), "0x0011_double-floating-point-data-type-h.bin") +log = os.path.join(os.path.join(root, "0x0011_double-floating-point-data-type", "build"), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +### Step 30: Verify + +Open the serial monitor: + +``` +myvalue: 99.990000 +myvalue: 99.990000 +myvalue: 99.990000 +... +``` + +**We changed the printed value and relabeled the line, with ten bytes and no source code.** `42.52525` became `99.99` because both halves of the double moved together. +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r3", 0x4058C000)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write a RAM string live | `dbg.write_memory(0x20080000, b"myvalue: %f\r\n\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 / 26 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 13). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` (Project 2: `0x10000238`) — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Start the server parked in the loop | macOS/Linux: `BP_ADDR=0x10000244 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000244"; .\debug-server.ps1` (`0x1000024a` for Project 2) | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x000e` | `0x1000024c` | `00 40 45 40` | `00 c0 58 40` | high word of the double: `42.5` -> `99.0` | +| `0x0011` | `0x10000254` | `ac 1c 5a 64` | `8f c2 f5 28` | low word of the double: `42.52525` -> `99.99` | +| `0x0011` | `0x10000258` | `3b 43 45 40` | `5c ff 58 40` | high word of the double: `42.52525` -> `99.99` | +| `0x000e` | `0x100034a8` | `66 61 76 5f 6e 75 6d 3a` | `6d 79 76 61 6c 75 65 3a` | string prints `myvalue:` instead of `fav_num:` | +| `0x0011` | `0x100034b0` | `66 61 76 5f 6e 75 6d 3a` | `6d 79 76 61 6c 75 65 3a` | string prints `myvalue:` instead of `fav_num:` | + +### IEEE 754 Quick Reference for the Values in This Lesson + +| Value | Double Hex | High Word (`r3`) | Low Word (`r2`) | +| ----- | ---------- | ---------------- | --------------- | +| `42.5` | `0x4045400000000000` | `0x40454000` | `0x00000000` | +| `42.52525` | `0x4045433B645A1CAC` | `0x4045433B` | `0x645A1CAC` | +| `99.0` | `0x4058C00000000000` | `0x4058C000` | `0x00000000` | +| `99.99` | `0x4058FF5C28F5C28F` | `0x4058FF5C` | `0x28F5C28F` | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project 1 size | `15308` bytes (`0x3bcc`) | +| Project 2 size | `15324` bytes (`0x3bdc`) | +| Fixed `main` anchor (both projects) | `0x1000018c` (reset handler middle `blx`) | +| `main`, Project 1 | `0x10000234` | +| `main`, Project 2 | `0x10000238` | +| `printf` call / return, Project 1 | `0x10000244` / `0x10000248` | +| `printf` call / return, Project 2 | `0x1000024a` / `0x1000024e` | +| `double` argument registers | `r2` (low) : `r3` (high) | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints (see the next entry). +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 11). The 13.3.rel1 build did **not** connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +**Use GDB MI**, with the 14.2.rel1 path above. If it still fails, fall back to plain `arm-none-eabi-gdb` against the same server — the addresses and register values are identical to the GUI steps. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### The GUI refuses to set a breakpoint (GDB RSP adapter only) + +If you are on the **GDB RSP** adapter, the GUI cannot set breakpoints on this target. That adapter is Binary Ninja's own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 comparators need 2 bytes, so OpenOCD answers `only breakpoints of two bytes length supported`. It affects every address, both `Toggle Breakpoint` and `Add Hardware Breakpoint`, and the dialog's **Size** field is disabled. `gdb_breakpoint_override` makes no difference. + +**Fix: use the GDB MI adapter** (Step 11). It drives real GDB, which sends the correct length, so GUI breakpoints just work. If you must stay on GDB RSP, arm breakpoints from the command port after connecting (`bp 2 hw`) — but the lab uses GDB MI and does not need that. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. This is a Binary Ninja bug. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +Never have a breakpoint in the binary view before the GDB MI connection. If it hangs, quit Binary Ninja, restart the server with `BP_ADDR`, and connect again before adding any breakpoints. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping, because the RP2350 config's `-rtos hwthread` makes the current thread id 1 while Binary Ninja sends thread id 0. Fix: `rp2350.dap.core0 configure -rtos none` (the launcher scripts already pass this). **GDB MI does not hit this.** + +To tell them apart, turn on OpenOCD logging (`log_output /tmp/ocd.log`, then `debug_level 3` on the command port) and look for `fake step` versus `Duplicate Breakpoint`. + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and lays the `pico_double` helpers out differently, so Project 2's `main` is not at `0x10000238`. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. With the **GDB MI** adapter, `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — that is a software breakpoint and cannot be written to read-only flash, so it never installs. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Verify it is armed:** `mdw 0xE0002000 8`. You should see your address with the low bit set (`0x10000234` -> `0x10000235`). All zeros means nothing is armed — re-read this first, because it distinguishes "not armed" from "armed but never reached". +- **Is the core running?** `poll` on the command port should not report a halt. If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup (Step 10) rather than `reset run` while attached. Loop addresses such as `0x10000244` fire on the next pass with no reset — arm them and click **Resume** in Binary Ninja. +- **With GDB MI the stop is reported as `Breakpoint`** and appears in the **Breakpoints** widget, because GDB really did set it. + +### I edit `r2`/`r3` (or another register) and it reverts + +Both `main`s reload the argument pair at the top of every loop iteration — `mov r2, r4` / `mov r3, r5` run right before the `printf` call. So your edit is only live for the instant between the write and the next pass; then the pair is reloaded from `r4`/`r5` (Project 1) or from the literal pool via `ldrd` (Project 2). The edit sticks only if the core is **genuinely stopped** at the breakpoint and stays stopped. + +If it keeps reverting, the core is running, which almost always means the breakpoint is not installed — usually because it is a **software** breakpoint (`F2`) that cannot be written to read-only flash. Use `Debugger -> Add Hardware Breakpoint...` (hardware execute). + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target, and there is no "refresh registers" command. So a value changed outside Binary Ninja will not appear until the next stop. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first: clear canonical/echo flags, set `CLOCAL|CREAD`, and `B115200` on input and output. `screen /dev/cu.usbmodem* 115200` does all of this for you; a script must call `tcsetattr` itself. Once set, the capture reads clean `fav_num: 42.500000` lines. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +This is the most common failure, and it has one main cause: **driving the core from the OpenOCD command port while Binary Ninja is connected.** + +- If you send `reset run` from the port while attached, the core resets, runs, and halts at your breakpoint — but Binary Ninja never receives the stop event. Its sidebar keeps showing the *previous* location, so **Step** and **Resume** act on a stale PC and appear to do nothing. +- If the OpenOCD process dies (or you restart it) while attached, Binary Ninja keeps believing it is connected: the sidebar stays, but the menu shows **Pause** enabled and **Resume**/**Step** disabled because Binary Ninja last saw the target *running*. + +Recovery: **Detach, then reconnect.** If Detach does nothing (the connection is already dead), restart Binary Ninja — its menu still shows a session that no longer exists. + +Prevention: +- Stop at `main` with `BP_ADDR` on a fresh server start, not with `reset run` while attached. +- For loop addresses, set the breakpoint in the GUI and click **Resume**. Let Binary Ninja be the thing that starts the core. +- If you must reset, **Detach first**, `reset run`, then reconnect. +- Never leave a breakpoint on the PC you are about to step or resume from. + +### The target "blows past" `main` and stops at `0x10003214` instead + +`0x10003214` is inside `stdio_uart_out_flush`: + +```asm +10003210: 4b02 ldr r3, [pc, #8] ; @ 0x1000321c +10003212: 681a ldr r2, [r3] +10003214: 6993 ldr r3, [r2, #24] ; the core sits here while the UART drains +10003216: 071b lsls r3, r3, #28 +10003218: d4fc bmi.n 0x10003214 +1000321a: 4770 bx lr +1000321c: 20000850 .word 0x20000850 +``` + +That is the UART transmit-FIFO drain loop inside `printf`, so the core is running `main`'s loop and simply spends nearly all its time there. The breakpoint at `main` did not fire because `main`'s entry runs exactly **once per reset**. If you arm the breakpoint after the reset, or set it while the target is already running and just resume, the core is already past `main` and will never re-execute it. Either arm the breakpoint **before** resetting, or break inside the loop at the `printf` call, which fires every iteration. + +**`0x10003214` is not a function.** It is one instruction inside `stdio_uart_out_flush`, which starts at `0x10003210`. If Binary Ninja has created a function at `0x10003214` (for example because the debugger stopped at that PC), the decompiler shows garbage. Delete that bogus function (right-click it -> `Delete Function`, or put the cursor on it and press `U` to undefine) and reanalyze. The real function is `stdio_uart_out_flush` at `0x10003210`. (In Project 2 the same drain loop is at `0x1000321c`.) + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### `Connect to Remote Process` is greyed out and Pause does nothing + +Binary Ninja is in a stale session, usually because the debug server restarted while attached. Quit and reopen Binary Ninja (or the `.bndb`) and connect again. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +### Project 2 prints a wrong, hybrid number after patching + +You patched only one of the two literal words. `42.52525` has a non-zero low word, so `0x10000254` **and** `0x10000258` must both change. Project 1's `42.5` is the opposite case: its low word is `0x00000000`, so only `0x1000024c` changes. + +### The double does not print as `99.99` after patching + +Confirm you wrote the bytes little-endian. `0x28F5C28F` is stored `8f c2 f5 28`, and `0x4058FF5C` is stored `5c ff 58 40`. If you typed the words in big-endian order the value is nonsense. The Python form `bytes.fromhex("8fc2f528")` is already in file order. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27 (see Troubleshooting), you can still do the live hack with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 10), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x10000244 +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x10000244` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. If you reset first, the core runs `main` and you will not catch it. + +GDB stops at the `printf` call. Confirm the pair, change it, and let it run: + +``` +info registers pc r2 r3 # pc = 0x10000244, r2 = 0x00000000, r3 = 0x40454000 +set $r3 = 0x4058C000 +stepi +continue +``` + +The serial monitor prints `fav_num: 99.000000` for the iteration you changed — the same temporary live hack as editing `r3` in the Binary Ninja Registers widget. When you are done, press `Ctrl-C`, then `detach` and `quit`. + +**If you specifically want to stop at `main` (`0x10000234`),** remember its entry runs only once per reset, so the breakpoint must be armed *before* the reset: + +``` +monitor reset halt +hbreak *0x10000234 +continue +``` + +If you instead set it while the target is running and just `continue`, you will "blow past" `main` and catch the core inside `printf` — in this build at `0x10003214`, the `stdio_uart_out_flush` UART-drain loop. + +Project 2 is the same with the other call site and pair: + +``` +hbreak *0x1000024a +continue +info registers pc r2 r3 # pc = 0x1000024a, r2 = 0x645A1CAC, r3 = 0x4045433B +set $r2 = 0x28F5C28F +set $r3 = 0x4058FF5C +stepi +``` + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too; the old **GDB RSP** adapter was the one that sent a 1-byte length and could not set breakpoints here. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **Bias** | Constant added to an IEEE 754 exponent (`127` for float, `1023` for double) | +| **Double** | 64-bit IEEE 754 floating-point type (1 sign, 11 exponent, 52 mantissa) | +| **Float** | 32-bit IEEE 754 floating-point type (1 sign, 8 exponent, 23 mantissa) | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +| **Hardware breakpoint** | A breakpoint serviced by the CPU comparators, required for read-only flash | +| **IEEE 754** | The standard that defines binary floating-point encoding | +| **Inlining** | The optimizer replacing a function call with the function body | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr`/`ldrd` | +| **Mantissa** | The fractional significand bits (23 for float, 52 for double) | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **Promotion** | C's automatic `float` -> `double` conversion for variadic arguments | +| **Register pair** | Two 32-bit registers (`r2:r3`) that together hold a 64-bit value | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically by reading `r2:r3`, resolve the names from the ELF, then patch the constant bytes — one word for a clean fraction like `42.5`, two words for a repeating one like `42.52525` — and flash. diff --git a/WEEK05/WEEK05-BN.pdf b/WEEK05/WEEK05-BN.pdf new file mode 100644 index 0000000..0d542c8 Binary files /dev/null and b/WEEK05/WEEK05-BN.pdf differ diff --git a/WEEK05/WEEK05-IDA.md b/WEEK05/WEEK05-IDA.md new file mode 100644 index 0000000..b090047 --- /dev/null +++ b/WEEK05/WEEK05-IDA.md @@ -0,0 +1,109 @@ +# Week 5-IDA: IDA Pro — Decode, Hack, and Patch IEEE 754 Floats and Doubles (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into IDA at `0x10000000` +- Read how a `float`/`double` constant is materialized from the compiler's literal pool + these two programs +- Reconstruct a 64-bit `double` from the ABI register pair `r2:r3` and hack it live +- **Resolve the functions in the IDA GUI** using the ELF symbol map, including the `pico_double` formatting helpers `printf` pulls in +- **Patch** the constant bytes, export the image, convert to UF2, and export it +- Prove why `42.5 -> 99.0` is a one-word patch but `42.52525 -> 99.99` needs two + +--- + +## How This Guide Works + +The build produces two files for each project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in IDA, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 5 lesson, and the Week 5 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it folds the `float`/`double` initializer into the literal pool and links the `pico_double` formatting helpers straight into the `printf` path. If you build `Debug`, the SDK function addresses move and the float/double helpers are laid out differently, so nothing lines up. Always build `Release` for this lesson. + +The workflow is static-only: import the raw image, recover the code, decompile it, and patch the artifact: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Prints | The hack | +| ------- | ------ | -------- | +| `0x000e_floating-point-data-type` | `fav_num: 42.500000` | change the printed double `42.5` to `99.0` (one word) | +| `0x0011_double-floating-point-data-type` | `fav_num: 42.525250` | change the printed double `42.52525` to `99.99` (two words) | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **`main` is not at the same address in both projects this week.** It is `0x10000234` in Project 1 and `0x10000238` in Project 2, because each program materializes its constant slightly differently. We still anchor to `main` through the one byte-identical place that always names it: the middle `blx` in `platform_entry` (Step 12). + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +bash + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **Bias** | Constant added to an IEEE 754 exponent (`127` for float, `1023` for double) | +| **Double** | 64-bit IEEE 754 floating-point type (1 sign, 11 exponent, 52 mantissa) | +| **Float** | 32-bit IEEE 754 floating-point type (1 sign, 8 exponent, 23 mantissa) | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +ly flash | +| **IEEE 754** | The standard that defines binary floating-point encoding | +| **Inlining** | The optimizer replacing a function call with the function body | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr`/`ldrd` | +| **Mantissa** | The fractional significand bits (23 for float, 52 for double) | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **Promotion** | C's automatic `float` -> `double` conversion for variadic arguments | +| **Register pair** | Two 32-bit registers (`r2:r3`) that together hold a 64-bit value | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions.5`, two words for a repeating one like `42.52525` — and export the patched artifact. diff --git a/WEEK05/WEEK05-IDA.pdf b/WEEK05/WEEK05-IDA.pdf new file mode 100644 index 0000000..3baf0b8 Binary files /dev/null and b/WEEK05/WEEK05-IDA.pdf differ diff --git a/WEEK05/WEEK05-SLIDES.pdf b/WEEK05/WEEK05-SLIDES.pdf new file mode 100644 index 0000000..d6078b0 Binary files /dev/null and b/WEEK05/WEEK05-SLIDES.pdf differ diff --git a/WEEK05/WEEK05.md b/WEEK05/WEEK05.md new file mode 100644 index 0000000..c66ab20 --- /dev/null +++ b/WEEK05/WEEK05.md @@ -0,0 +1,1529 @@ +# Week 5: Integers and Floats in Embedded Systems: Debugging and Hacking Integers and Floats w/ Intermediate GPIO Output Assembler Analysis + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand how integers and floating-point numbers are stored in memory +- Know the difference between signed and unsigned integers (`uint8_t` vs `int8_t`) +- Understand how floats and doubles are represented using IEEE 754 encoding +- Use inline assembly to control GPIO pins directly at the hardware level +- Debug numeric data types using GDB and the OpenOCD debugger +- Hack integer values by modifying registers at runtime +- Hack floating-point values by understanding and manipulating their binary representation +- Reconstruct 64-bit doubles from two 32-bit registers +--- + +## Part 1: Understanding Integer Data Types + +### What is an Integer? + +An **integer** is a whole number without any decimal point. Think of it like counting apples: you can have 0 apples, 1 apple, 42 apples, but you can't have 3.5 apples (that would be a fraction!). + +In C programming for embedded systems, we have special integer types that tell the compiler exactly how much memory to use: + +``` ++-----------------------------------------------------------------+ +| Integer Types - Different Sizes for Different Needs | +| | +| uint8_t: 1 byte (0 to 255) - like a small box | +| int8_t: 1 byte (-128 to 127) - can hold negatives! | +| uint16_t: 2 bytes (0 to 65,535) - medium box | +| uint32_t: 4 bytes (0 to 4 billion) - big box | +| | ++-----------------------------------------------------------------+ +``` + +### Signed vs Unsigned Integers + +The difference between `uint8_t` and `int8_t` is whether the number can be **negative**: + +| Type | Prefix | Range | Use Case | +| --------- | ------ | ----------- | ----------------------------- | +| `uint8_t` | `u` | 0 to 255 | Ages, counts, always positive | +| `int8_t` | none | -128 to 127 | Temperature, can be negative | + +#### The Integer Variables + +Let's say a program declares two integer variables that demonstrate the difference between **signed** and **unsigned** types: + +```c +uint8_t age = 43; +int8_t range = -42; +``` + +The variable `age` is a `uint8_t` - an **unsigned** 8-bit integer that can only hold values from `0` to `255`. Since age is always a positive number, unsigned is the right choice. The variable `range` is an `int8_t` - a **signed** 8-bit integer that can hold values from `-128` to `127`. The signed type allows it to represent negative numbers like `-42`. Under the hood, negative values are stored using **two's complement** encoding: the CPU flips all the bits of `42` (`0x2A`) and adds `1`, producing `0xD6`, which is how `-42` lives in a single byte of memory. + +--- + +## Part 2: Understanding Floating-Point Data Types + +### What is a Float? + +A **float** is a number that can have a decimal point. Unlike integers which can only hold whole numbers like `42`, a float can hold values like `42.5`, `3.14`, or `-0.001`. In C, the `float` type uses **32 bits (4 bytes)** to store a number using the **IEEE 754** standard. + +``` ++-----------------------------------------------------------------+ +| IEEE 754 Single-Precision (32-bit float) | +| | +| +------+----------+---------------------------+ | +| | Sign | Exponent | Mantissa (Fraction) | | +| | 1bit | 8 bits | 23 bits | | +| +------+----------+---------------------------+ | +| | +| Value = (-1)^sign * 2^(exponent-127) * 1.mantissa | +| | +| Example: 42.5 | +| Sign: 0 (positive) | +| Exponent: 10000100 (132 - 127 = 5) | +| Mantissa: 01010100000000000000000 | +| Full: 0 10000100 01010100000000000000000 | +| Hex: 0x422A0000 | +| | ++-----------------------------------------------------------------+ +``` + +### How to Compute This by Hand (42.5 -> IEEE 754) + +Use this exact process any time you need to encode a decimal float manually. + +1. Determine the sign bit. + - `42.5` is positive, so `sign = 0`. + +2. Convert the number to binary. + - Integer part: `42 = 101010 (base 2)` + - $42 = 32 + 8 + 2 = 2^5 + 2^3 + 2^1$ + - In 6-bit binary: `101010` + - Fractional part: use repeated multiply-by-2 on the fraction. + - Start with `0.5` + - $0.5 \times 2 = 1.0 \implies$ integer part is `1` (this is the first binary fractional bit) + - Remaining fractional part is now `0.0`, so we stop. + - Therefore `0.5 = 0.1 (base 2)`. + - Combined fixed-point binary: `42.5 = 101010.1 (base 2)` + +3. Normalize to scientific form ($1.\text{mantissa} \times 2^n$) - Where the 5 comes from! + - **Why is the exponent 5?** Look at the powers of 2 for the integer part (42): + - $2^4 = 16$ + - $2^5 = 32$ + - $2^6 = 64$ + - Because $32 \le 42 < 64$ (that is, $2^5 \le 42 < 2^6$), the largest power of 2 contained within 42 is $2^{\mathbf{5}}$. This mathematical bound guarantees that when normalized, the exponent **must be 5**. + - Now count the binary point shifts to bring the number into $1.xxxx$ form: + +``` +Original position: 1 0 1 0 1 0 . 1 x 2^0 (value: 42.5) +Shift 1 place left: 1 0 1 0 1 . 0 1 x 2^1 +Shift 2 places left: 1 0 1 0 . 1 0 1 x 2^2 +Shift 3 places left: 1 0 1 . 0 1 0 1 x 2^3 +Shift 4 places left: 1 0 . 1 0 1 0 1 x 2^4 +Shift 5 places left: 1 . 0 1 0 1 0 1 x 2^5 + ^ + Binary point is now right after the first '1'! +``` + + - We shifted the binary point **exactly 5 places to the left**, so the true exponent is $n = \mathbf{5}$: + $$101010.1_2 = 1.010101_2 \times 2^{\mathbf{5}}$$ + +4. Compute the stored exponent (bias 127 for float, 1023 for double). + - For a 32-bit `float`: + $$\text{stored exponent} = n + 127 = 5 + 127 = 132 = 10000100_2$$ + - For a 64-bit `double`: + $$\text{stored exponent} = n + 1023 = 5 + 1023 = 1028 = 10000000100_2$$ + + > Tip: **Why 127?** The exponent field is 8 bits wide, giving $2^8 = 256$ total values. Half of that range should represent negative exponents and half positive. The midpoint is $(2^8 / 2) - 1 = 127$. So a stored exponent of `127` means a real exponent of **0**, values below `127` are negative exponents, and values above `127` are positive exponents. Doubles use an 11-bit exponent field so their midpoint (bias) is $( 2^{11} / 2) - 1 = 1023$ instead. + +5. Build the mantissa (fraction bits). + - Take bits after the leading `1.` from `1.010101` -> `010101` + - Pad with zeros to 23 bits (for 32-bit float): + - `01010100000000000000000` + +6. Assemble all fields. + - `sign | exponent | mantissa` + - `0 | 10000100 | 01010100000000000000000` + - Full 32-bit pattern: + - `01000010001010100000000000000000` + +7. Convert the 32-bit binary to hex (group by 4 bits). + - `0100 0010 0010 1010 0000 0000 0000 0000` + - `4 2 2 A 0 0 0 0` + - Final result: `0x422A0000` + +Quick decode check (reverse direction, fully expanded): + +Given the 32-bit pattern: + +- `0 | 10000100 | 01010100000000000000000` + +Decode it field by field back to decimal: + +1. Sign bit + - Sign bit is `0` -> number is positive: `(+1)`. + +2. Exponent field + - Exponent bits are `10000100`. + - Convert to decimal: $10000100_2 = 128 + 4 = 132$. + - Float bias is `127`, so subtract the bias to recover the true exponent: + $$132 - 127 = \mathbf{5}$$ + - Recovering **5** tells us the significand was scaled by $2^5$. + +3. Mantissa field + - Stored mantissa bits are `01010100000000000000000`. + - IEEE 754 normal numbers restore the implicit leading `1.`, so significand becomes: + $$1.010101_2$$ + +4. Rebuild the value (undo the normalization) + - Formula: $\text{value} = (+1) \times 1.010101_2 \times 2^5$. + - Multiplying by $2^5$ shifts the binary point **5 places to the right**: + +``` +Start: 1 . 0 1 0 1 0 1 x 2^5 +Shift 1 place right: 1 0 . 1 0 1 0 1 x 2^4 +Shift 2 places right: 1 0 1 . 0 1 0 1 x 2^3 +Shift 3 places right: 1 0 1 0 . 1 0 1 x 2^2 +Shift 4 places right: 1 0 1 0 1 . 0 1 x 2^1 +Shift 5 places right: 1 0 1 0 1 0 . 1 x 2^0 = 101010.1 +``` + + - Resulting fixed-point binary: $101010.1_2$. + +5. Convert $101010.1_2$ to decimal + - Integer part: $101010_2 = 32 + 8 + 2 = 42$ + - Fraction part: $.1_2 = 1/2 = 0.5$ + - Total: $42 + 0.5 = \mathbf{42.5} \checkmark$ + +So the decoded value is exactly `42.5`. + +### Float vs Integer - Key Differences + +| Property | Integer (`uint8_t`) | Float (`float`) | +| -------------- | ---------------------- | --------------------------- | +| **Size** | 1 byte | 4 bytes | +| **Precision** | Exact | ~7 decimal digits | +| **Range** | 0 to 255 | 3.4 10^38 | +| **Encoding** | Direct binary | IEEE 754 (sign/exp/mantissa)| +| **printf** | `%d` | `%f` | + +### Our Floating-Point Program + +Let's look at a simple program that uses a `float` variable: + +**File: `0x000e_floating-point-data-type.c`** + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + float fav_num = 42.5; + + stdio_init_all(); + + while (true) + printf("fav_num: %f\r\n", fav_num); +} +``` + +> Note: `fav_num` is declared inside `main`, so by C rules it is an automatic (stack) variable. In optimized embedded builds, the compiler may avoid creating a real stack slot and instead materialize the value from read-only constant storage (typically `.rodata` and/or an ARM literal pool). +> +> An ARM **literal pool** is a small table of constants that the assembler places near code in memory. Instead of encoding a large immediate value directly in an instruction, the CPU executes a load instruction (such as `ldr`) that reads the constant from that nearby table. That is why Ghidra can show constant loads rather than a classic stack local. + +**What this code does:** + +1. Declares a `float` variable `fav_num` and initializes it to `42.5` +2. Initializes the serial output +3. Prints `fav_num` forever in a loop using the `%f` format specifier + +> Tip: **Why `%f` instead of `%d`?** The `%d` format specifier tells `printf` to expect an integer. The `%f` specifier tells it to expect a floating-point number. Using the wrong one would print garbage! + +### Step 1: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x000e_floating-point-data-type.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 2: Verify It's Working + +Open your serial monitor (PuTTY) and you should see: + +**You should see:** + +``` +fav_num: 42.500000 +fav_num: 42.500000 +fav_num: 42.500000 +... +``` + +The program is printing `42.500000` because `printf` with `%f` defaults to 6 decimal places. + +--- + +## Part 2.5: Setting Up Ghidra for Float Analysis + +### Step 3: Start Ghidra + +**Open a terminal and type:** + +```cmd +ghidraRun +``` + +Ghidra will open. Now we need to create a new project. + +### Step 4: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x000e_floating-point-data-type` +5. Click **Finish** + +### Step 5: Import the Binary + +1. Open your file explorer +2. Navigate to the `Embedded-Hacking` folder +3. Find `0x000e_floating-point-data-type.bin` +4. Select Cortex M Little Endian 32 +5. Select Options and set up the .text and offset 10000000 +6. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 6: Configure the Binary Format + +A dialog appears. The file is identified as a "BIN" (raw binary without debug symbols). + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` (the XIP address!) +3. Click **OK** + +### Step 7: Open and Analyze + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete (watch the progress bar in the bottom right). + +--- + +## Part 2.6: Navigating and Resolving Functions + +### Step 8: Find the Functions + +Look at the **Symbol Tree** panel on the left. Expand **Functions**. + +You'll see function names like: + +- `FUN_1000019a` +- `FUN_10000210` +- `FUN_10000234` + +These are auto-generated names because we imported a raw binary without symbols! + +### Step 9: Resolve Known Functions + +From our previous chapters, we know what some of these functions are: + +| Ghidra Name | Actual Name | How We Know | +| -------------- | ------------- | -------------------------- | +| `FUN_1000019a` | `data_cpy` | From Week 3 boot analysis | +| `FUN_10000210` | `frame_dummy` | From Week 3 boot analysis | +| `FUN_10000234` | `main` | This is where our code is! | + +### Step 10: Update Main's Signature + +For `main`, let's also fix the return type: + +1. Right-click on `main` in the Decompile window +2. Select **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +--- + +## Part 2.7: Analyzing the Main Function + +### Step 11: Examine Main in Ghidra + +Click on `main` (or `FUN_10000234`). Look at the **Decompile** window: + +You'll see something like: + +```c +int main(void) + +{ + undefined4 uVar1; + undefined4 extraout_r1; + undefined4 uVar2; + undefined4 extraout_r1_00; + + FUN_10002f5c(); + uVar1 = DAT_1000024c; + uVar2 = extraout_r1; + do { + FUN_100030ec(DAT_10000250,uVar2,0,uVar1); + uVar2 = extraout_r1_00; + } while( true ); +} +``` + +### Step 12: Resolve stdio_init_all + +1. Click on `FUN_10002f5c` +2. Right-click -> **Edit Function Signature** +3. Change to: `bool stdio_init_all(void)` +4. Click **OK** + +### Step 13: Resolve printf + +1. Click on `FUN_100030ec` +2. Right-click -> **Edit Function Signature** +3. Change to: `int printf(char *format,...)` +4. Check the **Varargs** checkbox (printf takes variable arguments!) +5. Click **OK** + +### Step 14: Understand the Float Encoding + +Look at the decompiled code after resolving functions: + +```c +int main(void) + +{ + undefined4 uVar1; + undefined4 extraout_r1; + undefined4 uVar2; + undefined4 extraout_r1_00; + + stdio_init_all(); + uVar1 = DAT_1000024c; + uVar2 = extraout_r1; + do { + printf(DAT_10000250,uVar2,0,uVar1); + uVar2 = extraout_r1_00; + } while( true ); +} +``` + +**Where's `float fav_num = 42.5`?** It's been optimized into an immediate value! + +The compiler replaced our float variable with constants passed directly to `printf`. But wait - we see **two** values: `0x0`, in `r2` and `DAT_1000024c` or `0x40454000`, in `r3`. That's because `printf` with `%f` always receives a **double** (64-bit), not a `float` (32-bit). The C standard requires that `float` arguments to variadic functions like `printf` are **promoted to `double`**. + +A 64-bit double is passed in two 32-bit registers: + +| Register | Value | Role | +| -------- | ------------ | ------------ | +| `r2` | `0x00000000` | Low 32 bits | +| `r3` | `0x40454000` | High 32 bits | + +Together they form `0x40454000_00000000` - the IEEE 754 **double-precision** encoding of `42.5`. + +### Step 15: Verify the Double Encoding + +We need to decode `0x4045400000000000` field by field. The two registers give us the full 64-bit value: + +``` +r3 (high 32 bits): 0x40454000 = 0100 0000 0100 0101 0100 0000 0000 0000 +r2 (low 32 bits): 0x00000000 = 0000 0000 0000 0000 0000 0000 0000 0000 +``` + +Laid out as a single 64-bit value with every bit numbered: + +``` +Bit: 63 62-52 (11b) 51-32 (20b from r3) 31-0 (32b from r2) ++---+-------------+---------------------+-------------------------+ +| 0 | 10000000100 | 01010100000000000000| 00000000...00000000 | ++---+-------------+---------------------+-------------------------+ +Sign Exponent Mantissa (High 20) Mantissa (Low 32) + (from r3 bits 19-0) (from r2, all zero) +``` + +**Step-by-step field extraction:** + +**1. Sign bit** + +In IEEE 754, the **sign bit** is the very first (leftmost) bit of the 64-bit double. In the full 64-bit layout we call it **bit 63**: + +``` +64-bit double: [bit 63] [bit 62 ... bit 0] + ^ + sign bit +``` + +But we don't have a single 64-bit register - we have **two** 32-bit registers. The high register `r3` holds bits 63-32 of the double. So bit 63 of the double is the same physical bit as **bit 31 of r3** (the topmost bit of r3): + +``` +r3 holds bits 63-32 of the double +r2 holds bits 31-0 of the double +``` + +Now let's check it. IEEE 754 uses a simple rule for the sign bit: + +| Sign bit | Meaning | +|----------|----------| +| `0` | Positive | +| `1` | Negative | + +``` +r3 = 0x40454000 = 0100 0000 0100 0101 0100 0000 0000 0000 + ^ + r3 bit 31 = 0 -> sign = 0 -> Positive number +``` + +The topmost bit of r3 is `0`, so the number is **positive**. If that bit were `1` instead (e.g. `0xC0454000`), the number would be negative (`-42.5`). + +**2. Exponent - bits 62-52 of the 64-bit value = bits 30-20 of r3** + +Extract bits 30-20 from `0x40454000`: + +``` +0x40454000 in binary: 0 10000000100 01010100000000000000 + sign exponent mantissa (top 20 bits) +``` + +Exponent bits: `10000000100` + +Convert to decimal: $2^{10} + 2^{2} = 1024 + 4 = 1028$ + +But `1028` is **not** the actual power of 2 yet. IEEE 754 stores exponents with a **bias** - a fixed number that gets added during encoding so that the stored value is always positive (no sign bit needed for the exponent). For doubles, the bias is **1023**. + +> Tip: **Why 1023?** The exponent field is 11 bits wide, giving $2^{11} = 2048$ total values. Half of that range should represent negative exponents and half positive. The midpoint is $(2^{11} / 2) - 1 = 1023$. So a stored exponent of `1023` means a real exponent of **0**, values below `1023` are negative exponents, and values above `1023` are positive exponents. + +To recover the real exponent, we subtract the bias: + +$$\text{real exponent} = \text{stored exponent} - \text{bias}$$ + +$$\text{real exponent} = 1028 - 1023 = \mathbf{5}$$ + +This confirms the number is scaled by $2^5 = 32$. When reconstructing the value, multiplying the significand $1.010101_2$ by $2^5$ shifts the binary point 5 places to the right, recovering $101010.1_2 = 42.5$. + +**3. Mantissa - bits 51-0 of the 64-bit value** + +- **High 20 bits of mantissa** (bits 51-32) = bits 19-0 of r3: + +``` +r3 bits 19-0: 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +``` + +- **Low 32 bits of mantissa** (bits 31-0) = all of r2: + +``` +r2 = 0x00000000 -> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +``` + +Full 52-bit mantissa: + +``` +0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + <- top 20 bits from r3 -> <- bottom 32 bits from r2 (all zero) -> +``` + +IEEE 754 always prepends an **implied leading `1`**, so the actual value represented is: + +``` +1.010101 00000... (the 1. is implicit, not stored) +``` + +**4. Reconstruct the value** + +$$1.010101\text{ (base 2)} \times 2^5$$ + +Shift the binary point 5 places right: + +$$101010.1\text{ (base 2)}$$ + +Now convert each bit position to decimal: + +| Bit position | Power of 2 | Value | +|---|---|---| +| `1` (bit 5) | $2^5$ | 32 | +| `0` (bit 4) | $2^4$ | 0 | +| `1` (bit 3) | $2^3$ | 8 | +| `0` (bit 2) | $2^2$ | 0 | +| `1` (bit 1) | $2^1$ | 2 | +| `0` (bit 0) | $2^0$ | 0 | +| `1` (bit -1) | $2^{-1}$ | 0.5 | + +$$32 + 8 + 2 + 0.5 = \mathbf{42.5}$$ + +### Step 16: Examine the Assembly + +Look at the **Listing** window (assembly view). Find the main function: + +``` + ************************************************************* + * FUNCTION + ************************************************************* + int __stdcall main (void ) + int r0:4 + main+1 XREF[1,1]: 1000018c (c) , 1000018a (*) + main + 10000234 38 b5 push {r3,r4,r5,lr} + 10000236 02 f0 91 fe bl stdio_init_all bool stdio_init_all(void) + 1000023a 00 24 movs r4,#0x0 + 1000023c 03 4d ldr r5,[DAT_1000024c ] = 40454000h + LAB_1000023e XREF[1]: 10000248 (j) + 1000023e 22 46 mov r2,r4 + 10000240 2b 46 mov r3,r5 + 10000242 03 48 ldr r0=>s_fav_num:_%f_100034a8 ,[DAT_10000250 ] = "fav_num: %f\r\n" + = 100034A8h + 10000244 02 f0 52 ff bl printf int printf(char * format, ...) + 10000248 f9 e7 b LAB_1000023e + 1000024a 00 ?? 00h + 1000024b bf ?? BFh + DAT_1000024c XREF[1]: main:1000023c (R) + 1000024c 00 40 45 40 undefine 40454000h + DAT_10000250 XREF[1]: main:10000242 (R) + 10000250 a8 34 00 10 undefine 100034A8h * -> 100034a8 +``` + +> **Key Insight:** The `mov.w r2, #0x0` loads the low 32 bits (all zeros) and `ldr r3, [DAT_...]` loads the high 32 bits (`0x40454000`) of the double. Together, `r2:r3` = `0x40454000_00000000` = `42.5` as a double. + +### Step 17: Find the Format String + +In the Listing view, click on the data reference to find the format string: + +``` + s_fav_num:_%f_100034a8 XREF[1]: main:10000242 (*) + 100034a8 66 61 76 ds "fav_num: %f\r\n" + 5f 6e 75 + 6d 3a 20 +``` + +This confirms `printf` is called with the format string `"fav_num: %f\r\n"` and the double-precision value of `42.5`. + +--- + +## Part 2.8: Patching the Float - Changing 42.5 to 99.0 + +### Step 18: Calculate the New IEEE 754 Encoding + +We want to change `42.5` to `99.0`. First, we need to figure out the double-precision encoding of `99.0`: + +**Step A - Convert the integer part (99) to binary:** + +| Division | Quotient | Remainder | +|---------------|----------|-----------| +| 99 2 | 49 | **1** | +| 49 2 | 24 | **1** | +| 24 2 | 12 | **0** | +| 12 2 | 6 | **0** | +| 6 2 | 3 | **0** | +| 3 2 | 1 | **1** | +| 1 2 | 0 | **1** | + +Read remainders bottom-to-top: 99 (base 10) = 1100011 (base 2) + +**Step B - Convert the fractional part (.0) to binary:** + +There is no fractional part - `.0` is exactly zero, so the fractional binary is just `0`. + +**Step C - Combine:** + +$$99.0\text{ (base 10)} = 1100011.0\text{ (base 2)}$$ + +**Step D - Normalize to IEEE 754 form** (move the binary point so there's exactly one `1` before it): + +$$1100011.0\text{ (base 2)} = 1.100011\text{ (base 2)} \times 2^6$$ + +We shifted the binary point 6 places left, so the exponent is **6**. + +**Step E - Extract the IEEE 754 fields:** + +1. **Sign:** `0` (positive) +2. **Exponent:** $6 + 1023 = 1029 = 10000000101\text{ (base 2)}$ +3. **Mantissa:** `1000110000000000...` (everything after the `1.`, padded with zeros to 52 bits) +4. **Full double:** `0x4058C00000000000` + +| Register | Old Value | New Value | +| -------- | ------------ | ------------ | +| `r2` | `0x00000000` | `0x00000000` | +| `r3` | `0x40454000` | `0x4058C000` | + +Since `r2` stays `0x00000000`, we only need to patch the high word loaded into `r3`. + +### Step 19: Find the Value to Patch + +Look in the Listing view for the data that loads the high word of the double: + +``` + 1000024c 00 40 45 40 undefined4 40454000h +``` + +This is the 32-bit constant that gets loaded into `r3` - the high word of our double `42.5`. + +### Step 20: Patch the Constant + +1. Click on Window -> Bytes +2. Click on the Pencil icon to enable byte editing +3. At address `1000024c`, overwrite `00 40 45 40` with `00 C0 58 40` (little-endian for `0x40454000 -> 0x4058C000`) +4. Press Enter + +This changes the high word from `0x40454000` (42.5 as double) to `0x4058C000` (99.0 as double). + +--- + +## Part 2.9: Export and Test the Hacked Binary + +### Step 21: Export the Patched Binary + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. Navigate to your build directory +4. Name the file `0x000e_floating-point-data-type-h.bin` +5. Click **OK** + +### Step 22: Convert to UF2 Format + +**Open a terminal and navigate to your project directory:** + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x000e_floating-point-data-type +``` + +**Run the conversion command:** + +```cmd +python ..\uf2conv.py build\0x000e_floating-point-data-type-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 23: Flash the Hacked Binary + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Open your serial monitor + +**You should see:** + +``` +fav_num: 99.000000 +fav_num: 99.000000 +fav_num: 99.000000 +... +``` + + **BOOM! We hacked the float!** The value changed from `42.5` to `99.0`! + +--- + +## Part 3: Understanding Double-Precision Floating-Point Data Types + +### What is a Double? + +A **double** (short for "double-precision floating-point") is like a `float` but with **twice the precision**. While a `float` uses 32 bits, a `double` uses **64 bits (8 bytes)**, giving it roughly **15-16 significant decimal digits** of precision compared to a float's ~7. + +``` ++-----------------------------------------------------------------+ +| IEEE 754 Double-Precision (64-bit double) | +| | +| +------+-----------+--------------------------------------+ | +| | Sign | Exponent | Mantissa (Fraction) | | +| | 1bit | 11 bits | 52 bits | | +| +------+-----------+--------------------------------------+ | +| | +| Value = (-1)^sign * 2^(exponent-1023) * 1.mantissa | +| | +| Example: 42.52525 | +| Sign: 0 (positive) | +| Exponent: 10000000100 (1028 - 1023 = 5) | +| Mantissa: 0101010000110011101101100100010110100001110010101100 | +| Hex: 0x4045433B645A1CAC | +| | ++-----------------------------------------------------------------+ +``` + +### Float vs Double - Key Differences + +| Property | Float (`float`) | Double (`double`) | +| --------------- | ---------------------- | --------------------------- | +| **Size** | 4 bytes (32 bits) | 8 bytes (64 bits) | +| **Precision** | ~7 decimal digits | ~15 decimal digits | +| **Exponent** | 8 bits (bias 127) | 11 bits (bias 1023) | +| **Mantissa** | 23 bits | 52 bits | +| **Range** | 3.4 10^38 | 1.8 10^308 | +| **printf** | `%f` | `%lf` | +| **ARM passing** | Promoted to double | Native in `r2:r3` | + +> Tip: **Why does precision matter?** With a `float`, the value `42.52525` might be stored as `42.525249` due to rounding. A `double` can represent it as `42.525250` with much higher fidelity. For scientific or financial applications, that extra precision is critical! + +### Our Double-Precision Program + +Let's look at a program that uses a `double` variable: + +**File: `0x0011_double-floating-point-data-type.c`** + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + double fav_num = 42.52525; + + stdio_init_all(); + + while (true) + printf("fav_num: %lf\r\n", fav_num); +} +``` + +**What this code does:** + +1. Declares a `double` variable `fav_num` and initializes it to `42.52525` +2. Initializes the serial output +3. Prints `fav_num` forever in a loop using the `%lf` format specifier + +> Tip: **`%lf` vs `%f`:** While `printf` actually treats `%f` and `%lf` identically (both expect a `double`), using `%lf` makes your intent clear - you're explicitly working with a `double`, not a `float`. It's good practice to match the format specifier to your variable type. + +### Step 1: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x0011_double-floating-point-data-type.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 2: Verify It's Working + +Open your serial monitor (PuTTY) and you should see: + +**You should see:** + +``` +fav_num: 42.525250 +fav_num: 42.525250 +fav_num: 42.525250 +... +``` + +The program is printing `42.525250` because `printf` with `%lf` defaults to 6 decimal places. + +--- + +## Part 3.5: Setting Up Ghidra for Double Analysis + +### Step 3: Start Ghidra + +**Open a terminal and type:** + +```cmd +ghidraRun +``` + +Ghidra will open. Now we need to create a new project. + +### Step 4: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x0011_double-floating-point-data-type` +5. Click **Finish** + +### Step 5: Import the Binary + +1. Open your file explorer +2. Navigate to the `Embedded-Hacking` folder +3. Find `0x0011_double-floating-point-data-type.bin` +4. Select Cortex M Little Endian 32 +5. Select Options and set up the .text and offset 10000000 +6. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 6: Configure the Binary Format + +A dialog appears. The file is identified as a "BIN" (raw binary without debug symbols). + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` (the XIP address!) +3. Click **OK** + +### Step 7: Open and Analyze + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete (watch the progress bar in the bottom right). + +--- + +## Part 3.6: Navigating and Resolving Functions + +### Step 8: Find the Functions + +Look at the **Symbol Tree** panel on the left. Expand **Functions**. + +You'll see function names like: + +- `FUN_1000019a` +- `FUN_10000210` +- `FUN_10000238` + +These are auto-generated names because we imported a raw binary without symbols! + +### Step 9: Resolve Known Functions + +From our previous chapters, we know what some of these functions are: + +| Ghidra Name | Actual Name | How We Know | +| -------------- | ------------- | -------------------------- | +| `FUN_1000019a` | `data_cpy` | From Week 3 boot analysis | +| `FUN_10000210` | `frame_dummy` | From Week 3 boot analysis | +| `FUN_10000238` | `main` | This is where our code is! | + +### Step 10: Update Main's Signature + +For `main`, let's also fix the return type: + +1. Right-click on `main` in the Decompile window +2. Select **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +--- + +## Part 3.7: Analyzing the Main Function + +### Step 11: Examine Main in Ghidra + +Click on `main` (or `FUN_10000234`). Look at the **Decompile** window: + +You'll see something like: + +```c +int main(void) + +{ + undefined4 uVar1; + undefined4 uVar2; + undefined4 extraout_r1; + undefined4 uVar3; + undefined4 extraout_r1_00; + + uVar2 = DAT_10000258; + uVar1 = DAT_10000254; + FUN_10002f64(); + uVar3 = extraout_r1; + do { + FUN_100030f4(DAT_10000250,uVar3,uVar1,uVar2); + uVar3 = extraout_r1_00; + } while( true ); +} +``` + +### Step 12: Resolve stdio_init_all + +1. Click on `FUN_10002f64` +2. Right-click -> **Edit Function Signature** +3. Change to: `bool stdio_init_all(void)` +4. Click **OK** + +### Step 13: Resolve printf + +1. Click on `FUN_100030f4` +2. Right-click -> **Edit Function Signature** +3. Change to: `int printf(char *format,...)` +4. Check the **Varargs** checkbox (printf takes variable arguments!) +5. Click **OK** + +### Step 14: Understand the Double Encoding + +Look at the decompiled code after resolving functions: + +```c +int main(void) + +{ + undefined4 uVar1; + undefined4 uVar2; + undefined4 extraout_r1; + undefined4 uVar3; + undefined4 extraout_r1_00; + + uVar2 = DAT_10000258; + uVar1 = DAT_10000254; + stdio_init_all(); + uVar3 = extraout_r1; + do { + printf(DAT_10000250,uVar3,uVar1,uVar2); + uVar3 = extraout_r1_00; + } while( true ); +} +``` + +**Where's `double fav_num = 42.52525`?** It's been optimized into immediate values! + +This time we see **two** non-zero values: `0x645a1cac` and `0x4045433b`. Unlike the float example where the low word was `0x0`, a double with a fractional part like `42.52525` needs **all 52 mantissa bits** - so both halves carry data. + +A 64-bit double is passed in two 32-bit registers: + +| Register | Value | Role | +| -------- | ------------ | ------------ | +| `r2` | `0x645A1CAC` | Low 32 bits | +| `r3` | `0x4045433B` | High 32 bits | + +Together they form `0x4045433B645A1CAC` - the IEEE 754 **double-precision** encoding of `42.52525`. + +> **Key Difference from Float:** In the float example, `r2` was `0x00000000` because `42.5` has a clean fractional part. But `42.52525` has a repeating binary fraction, so the low 32 bits are non-zero (`0x645A1CAC`). This means **both** registers matter when patching doubles with complex fractional values! + +### Step 15: Verify the Double Encoding + +We need to decode `0x4045433B645A1CAC` field by field. The two registers give us the full 64-bit value: + +``` +r3 (high 32 bits): 0x4045433B = 0100 0000 0100 0101 0100 0011 0011 1011 +r2 (low 32 bits): 0x645A1CAC = 0110 0100 0101 1010 0001 1100 1010 1100 +``` + +Laid out as a single 64-bit value with every bit numbered: + +``` +Bit: 63 62-52 (11b) 51-32 (20b from r3) 31-0 (32b from r2) ++---+-------------+---------------------+-------------------------+ +| 0 | 10000000100 | 01010100001100111011| 01100100...10101100 | ++---+-------------+---------------------+-------------------------+ +Sign Exponent Mantissa (High 20) Mantissa (Low 32) + (from r3 bits 19-0) (from r2) +``` + +**Step-by-step field extraction:** + +**1. Sign bit** + +The sign bit is bit 63 of the 64-bit double, which is bit 31 of r3 (the high register holds bits 63-32): + +``` +r3 = 0x4045433B = 0100 0000 0100 0101 0100 0011 0011 1011 + ^ + r3 bit 31 = 0 -> sign = 0 -> Positive number ✓ +``` + +**2. Exponent - bits 62-52 = bits 30-20 of r3** + +Extract bits 30-20 from `0x4045433B`: + +``` +0x4045433B in binary: 0 10000000100 01010100001100111011 + sign exponent mantissa (top 20 bits) +``` + +Exponent bits: `10000000100` + +Convert to decimal: $2^{10} + 2^{2} = 1024 + 4 = 1028$ + +Subtract the bias (the bias is 1023 for all 64-bit doubles): + +$$\text{real exponent} = 1028 - 1023 = \mathbf{5}$$ + +#### Deep Dive: Where Did the Exponent 5 Come From? + +If you are wondering why the real exponent is **5**, let's walk through the foundational math step-by-step using `42.5`. This shows both how decimal `42.5` converts into IEEE 754 format, and how that converted value breaks down step-by-step back to `42.5`. + +##### 1. Forward Conversion: Decimal 42.5 to IEEE 754 + +**Step A: The Power-of-2 Bounding Rule (Why 5?)** +Why is the exponent 5 and not 4 or 6? Look at the powers of 2 around the integer part (42): +- $2^4 = 16$ +- $2^5 = 32$ +- $2^6 = 64$ + +Because $32 \le 42 < 64$ (that is, $2^{\mathbf{5}} \le 42 < 2^6$), the largest power of 2 contained within 42 is $2^{\mathbf{5}}$. This mathematical bound guarantees that when normalized, the exponent **must be 5**. + +**Step B: Convert 42.5 to Fixed-Point Binary** +- Integer part (42): + - $42 - 32 = 10 \implies 2^5$ bit is `1` + - $10 < 16 \implies 2^4$ bit is `0` + - $10 - 8 = 2 \implies 2^3$ bit is `1` + - $2 < 4 \implies 2^2$ bit is `0` + - $2 - 2 = 0 \implies 2^1$ bit is `1` + - $0 \implies 2^0$ bit is `0` + - Result: $42_{10} = 101010_2$ +- Fractional part (0.5): + - $0.5 \times 2 = 1.0 \implies$ integer part `1`, remainder `0.0` + - Result: $0.5_{10} = 0.1_2$ +- Combined fixed-point binary: + $$42.5_{10} = 101010.1_2$$ + +**Step C: Normalize to Scientific Notation (Counting the 5 Shifts Left)** +IEEE 754 requires every normal non-zero number to be represented in scientific form: +$$1.\text{mantissa} \times 2^n$$ +We start with $101010.1$ and shift the binary point to the left until exactly one non-zero bit (`1`) remains before the point: + +``` +Original position: 1 0 1 0 1 0 . 1 x 2^0 (value: 42.5) +Shift 1 place left: 1 0 1 0 1 . 0 1 x 2^1 +Shift 2 places left: 1 0 1 0 . 1 0 1 x 2^2 +Shift 3 places left: 1 0 1 . 0 1 0 1 x 2^3 +Shift 4 places left: 1 0 . 1 0 1 0 1 x 2^4 +Shift 5 places left: 1 . 0 1 0 1 0 1 x 2^5 + ^ + Point is now immediately after the first 1! +``` + +Notice we shifted the binary point **exactly 5 places to the left**. That shift count is our true exponent: +$$101010.1_2 = 1.010101_2 \times 2^{\mathbf{5}}$$ +**That is exactly where the 5 comes from!** + +**Step D: Add the Exponent Bias** +IEEE 754 adds a fixed bias so exponents are stored as unsigned positive integers: +- For `float` (bias 127): $\text{stored exponent} = 5 + 127 = 132 = 10000100_2$ +- For `double` (bias 1023): $\text{stored exponent} = 5 + 1023 = 1028 = 10000000100_2$ + +**Step E: Assemble the 64-Bit Double Pattern for 42.5** +- Sign (1 bit): `0` (positive) +- Exponent (11 bits): `10000000100` (1028) +- Mantissa (52 bits): `010101` followed by 46 zeros (the leading `1.` is implied) +- Register distribution: + - `r3` (high 32 bits): `0x40454000` + - `r2` (low 32 bits): `0x00000000` + +##### 2. Reverse Breakdown: IEEE 754 Double Back to Decimal 42.5 + +Now take `r3 = 0x40454000` and `r2 = 0x00000000` and break it down step-by-step back to `42.5`: + +**Step A: Recover the Real Exponent 5** +- Extract the 11 exponent bits from `r3` (bits 30-20): + $$\text{Stored exponent} = 10000000100_2 = 1024 + 4 = 1028$$ +- Subtract the 1023 bias: + $$\text{Real Exponent} = 1028 - 1023 = \mathbf{5}$$ +Subtracting 1023 recovers our shift count of **5**, telling us the significand was scaled by $2^{\mathbf{5}}$. + +**Step B: Restore the Significand (Reattach Implicit 1)** +- Stored mantissa bits from `r3`: `01010100000...` +- Reattach the implicit leading `1.`: + $$\text{Significand} = 1.010101_2$$ + +**Step C: Multiply by $2^5$ (Shift Binary Point 5 Places Right)** +$$\text{Value} = 1.010101_2 \times 2^{\mathbf{5}}$$ +Multiplying by $2^5$ shifts the binary point **5 places to the right**: + +``` +Start: 1 . 0 1 0 1 0 1 x 2^5 +Shift 1 place right: 1 0 . 1 0 1 0 1 x 2^4 +Shift 2 places right: 1 0 1 . 0 1 0 1 x 2^3 +Shift 3 places right: 1 0 1 0 . 1 0 1 x 2^2 +Shift 4 places right: 1 0 1 0 1 . 0 1 x 2^1 +Shift 5 places right: 1 0 1 0 1 0 . 1 x 2^0 = 101010.1 +``` + +The un-normalized fixed-point binary representation is: +$$101010.1_2$$ + +**Step D: Convert Fixed-Point Binary to Decimal** +- Integer part (`101010`): + - $1 \times 2^5 = 32$ + - $0 \times 2^4 = 0$ + - $1 \times 2^3 = 8$ + - $0 \times 2^2 = 0$ + - $1 \times 2^1 = 2$ + - $0 \times 2^0 = 0$ + - Sum: $32 + 8 + 2 = 42$ +- Fractional part (`.1`): + - $1 \times 2^{-1} = 0.5$ +- Final Total: + $$42 + 0.5 = \mathbf{42.5} \checkmark$$ + +##### 3. Why 42.52525 Shares the Exact Same Exponent 5 + +Now return to `42.52525` in our binary (`r3 = 0x4045433B`): +- The integer part of `42.52525` is still **42**. +- Since $32 \le 42.52525 < 64$ ($2^{\mathbf{5}} \le 42.52525 < 2^6$), the largest power of 2 fitting in the number is still $2^{\mathbf{5}}$. +- Normalizing $101010.10000110011101..._2$ to $1.xxxx...$ still requires shifting the binary point **5 places to the left**: + $$1.0101010000110011101..._2 \times 2^{\mathbf{5}}$$ +- Therefore, the stored exponent in `r3` is identically $5 + 1023 = 1028$ (`10000000100`), producing the exact same `0x404...` in the upper 12 bits of `r3`! +- The only difference between `42.5` (`0x40454000_00000000`) and `42.52525` (`0x4045433B_645A1CAC`) is in the remaining mantissa bits that capture the fractional difference between `0.5` and `0.52525`. + +**3. Mantissa - bits 51-0** + +Unlike the `42.5` example where r2 was all zeros, **both registers contribute non-zero bits** here: + +- **High 20 bits of mantissa** (bits 51-32) = bits 19-0 of r3: + +``` +r3 bits 19-0: 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 1 1 +``` + +- **Low 32 bits of mantissa** (bits 31-0) = all of r2: + +``` +r2 = 0x645A1CAC -> 0 1 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 +``` + +Full 52-bit mantissa: + +``` +0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 1 1 | 0 1 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 + <- top 20 bits from r3 -> <- bottom 32 bits from r2 -> +``` + +IEEE 754 always prepends an **implied leading `1`**, so the actual value represented is: + +``` +1.0101010000110011101101100100010110100001110010101100 (the 1. is implicit, not stored) +``` + +**4. Reconstruct the value** + +$$1.0101010000110011101101100100...\text{ (base 2)} \times 2^5$$ + +Shift the binary point 5 places right: + +$$101010.10000110011101101100100010110100001110010101100\text{ (base 2)}$$ + +**Integer part** (`101010`): + +| Bit position | Power of 2 | Value | +|---|---|---| +| `1` (bit 5) | $2^5$ | 32 | +| `0` (bit 4) | $2^4$ | 0 | +| `1` (bit 3) | $2^3$ | 8 | +| `0` (bit 2) | $2^2$ | 0 | +| `1` (bit 1) | $2^1$ | 2 | +| `0` (bit 0) | $2^0$ | 0 | + +$$32 + 8 + 2 = \mathbf{42}$$ + +**Fractional part** (`.10000110011101101...`): + +| Bit position | Power of 2 | Decimal value | +|---|---|---| +| `1` (bit -1) | $2^{-1}$ | 0.5 | +| `0` (bit -2) | $2^{-2}$ | 0 | +| `0` (bit -3) | $2^{-3}$ | 0 | +| `0` (bit -4) | $2^{-4}$ | 0 | +| `0` (bit -5) | $2^{-5}$ | 0 | +| `1` (bit -6) | $2^{-6}$ | 0.015625 | +| `1` (bit -7) | $2^{-7}$ | 0.0078125 | +| `0` (bit -8) | $2^{-8}$ | 0 | +| `0` (bit -9) | $2^{-9}$ | 0 | +| `1` (bit -10) | $2^{-10}$ | 0.0009765625 | +| `1` (bit -11) | $2^{-11}$ | 0.00048828125 | +| `1` (bit -12) | $2^{-12}$ | 0.000244140625 | +| ... | ... | *(remaining 35 bits add smaller and smaller fractions)* | + +First 12 fractional bits sum: $0.5 + 0.015625 + 0.0078125 + 0.0009765625 + 0.00048828125 + 0.000244140625 \approx 0.5251$ + +The remaining 35 fractional bits refine this to $\approx 0.52525$. This is because `0.52525` is a **repeating fraction** in binary - it can never be represented with a finite number of bits, so double precision stores the closest possible 52-bit approximation. + +$$42 + 0.52525 = \mathbf{42.52525} \checkmark$$ + +### Step 16: Examine the Assembly + +Look at the **Listing** window (assembly view). Find the main function: + +``` + ************************************************************* + * FUNCTION + ************************************************************* + int __stdcall main (void ) + int r0:4 + main+1 XREF[1,1]: 1000018c (c) , 1000018a (*) + main + 10000238 38 b5 push {r3,r4,r5,lr} + 1000023a 06 a5 adr r5,[0x10000254 ] + 1000023c d5 e9 00 45 ldrd r4,r5,[r5,#0x0 ]=>DAT_10000254 = 645A1CACh + = 4045433Bh + 10000240 02 f0 90 fe bl stdio_init_all bool stdio_init_all(void) + LAB_10000244 XREF[1]: 1000024e (j) + 10000244 22 46 mov r2,r4 + 10000246 2b 46 mov r3,r5 + 10000248 01 48 ldr r0=>s_fav_num:_%lf_100034b0 ,[DAT_10000250 ] = "fav_num: %lf\r\n" + = 100034B0h + 1000024a 02 f0 53 ff bl printf int printf(char * format, ...) + 1000024e f9 e7 b LAB_10000244 + DAT_10000250 XREF[1]: main:10000248 (R) + 10000250 b0 34 00 10 undefine 100034B0h ? -> 100034b0 + DAT_10000254 XREF[1]: main:1000023c (R) + 10000254 ac 1c 5a 64 undefine 645A1CACh + DAT_10000258 XREF[1]: main:1000023c (R) + 10000258 3b 43 45 40 undefine 4045433Bh +``` + +> **Key Insight:** Notice that **both** `r2` and `r3` are loaded from data constants using `ldr`. Compare this to the float example where `r2` was loaded with `mov.w r2, #0x0`. Because `42.52525` requires all 52 mantissa bits, neither word can be zero - the compiler must store both halves as separate data constants. + +### Step 17: Find the Format String + +In the Listing view, click on the data reference to find the format string: + +``` + s_fav_num:_%lf_100034b0 XREF[1]: main:10000248 (*) + 100034b0 66 61 76 ds "fav_num: %lf\r\n" + 5f 6e 75 + 6d 3a 20 +``` + +This confirms `printf` is called with the format string `"fav_num: %lf\r\n"` and the double-precision value of `42.52525`. + +--- + +## Part 3.8: Patching the Double - Changing 42.52525 to 99.99 + +### Step 18: Calculate the New IEEE 754 Encoding + +We want to change `42.52525` to `99.99`. First, we need to figure out the double-precision encoding of `99.99`: + +1. $99.99 = 1.5623... \times 2^6 = 1.100011111111...\text{ (base 2)} \times 2^6$ +2. **Sign:** `0` (positive) +3. **Exponent:** $6 + 1023 = 1029 = 10000000101\text{ (base 2)}$ +4. **Mantissa:** `1000111111010111000010100011110101110000101000111... (base 2)` +5. **Full double:** `0x4058FF5C28F5C28F` + +| Register | Old Value | New Value | +| -------- | ------------ | ------------ | +| `r2` | `0x645A1CAC` | `0x28F5C28F` | +| `r3` | `0x4045433B` | `0x4058FF5C` | + +Unlike the float example, **both** registers change! The value `99.99` has a repeating binary fraction, so both the high and low words are different. + +### Step 19: Find the Values to Patch + +Look in the Listing view for the two data constants: + +**Low word (loaded into `r2`):** +``` + 10000254 ac 1c 5a 64 undefined4 645A1CACh +``` + +**High word (loaded into `r3`):** +``` + 10000258 3b 43 45 40 undefined4 4045433Bh +``` + +### Step 20: Patch Both Constants + +**Patch the low word:** + +1. Click on the data at address `10000254` containing `645A1CAC` +2. Open the Bytes window and enable byte editing (Pencil icon) +3. Overwrite bytes `ac 1c 5a 64` with `8f c2 f5 28` (little-endian for `0x645A1CAC -> 0x28F5C28F`) +4. Press Enter + +**Patch the high word:** + +1. Click on the data at address `10000258` containing `4045433B` +2. Keep byte editing enabled in the Bytes window +3. Overwrite bytes `3b 43 45 40` with `5c ff 58 40` (little-endian for `0x4045433B -> 0x4058FF5C`) +4. Press Enter + +This changes the full 64-bit double from `0x4045433B645A1CAC` (42.52525) to `0x4058FF5C28F5C28F` (99.99). + +> **Key Difference from Float Patching:** When we patched the float `42.5`, we only needed to change one word (the high word in `r3`) because the low word was all zeros. With `42.52525 -> 99.99`, **both** words change. Always check whether the low word is non-zero before patching! + +--- + +## Part 3.9: Export and Test the Hacked Binary + +### Step 21: Export the Patched Binary + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. Navigate to your build directory +4. Name the file `0x0011_double-floating-point-data-type-h.bin` +5. Click **OK** + +### Step 22: Convert to UF2 Format + +**Open a terminal and navigate to your project directory:** + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0011_double-floating-point-data-type +``` + +**Run the conversion command:** + +```cmd +python ..\uf2conv.py build\0x0011_double-floating-point-data-type-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 23: Flash the Hacked Binary + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Open your serial monitor + +**You should see:** + +``` +fav_num: 99.990000 +fav_num: 99.990000 +fav_num: 99.990000 +... +``` + + **BOOM! We hacked the double!** The value changed from `42.52525` to `99.99`! + +--- + +## Part 3.95: Summary - Float and Double Analysis + +### What We Accomplished + +1. **Learned about IEEE 754** - How floating-point numbers are encoded in 32-bit (float) and 64-bit (double) formats +2. **Discovered float-to-double promotion** - `printf` with `%f` always receives a `double`, even when you pass a `float` +3. **Decoded register pairs** - 64-bit doubles are split across `r2` (low) and `r3` (high) +4. **Patched a float value** - Changed `42.5` to `99.0` by modifying only the high word +5. **Patched a double value** - Changed `42.52525` to `99.99` by modifying **both** words +6. **Understood the key difference** - Clean fractions (like `42.5`) have a zero low word; complex fractions (like `42.52525`) require patching both words + +### IEEE 754 Quick Reference for Common Values + +| Value | Double Hex | High Word (r3) | Low Word (r2) | +| -------- | ------------------------ | --------------- | -------------- | +| 42.0 | `0x4045000000000000` | `0x40450000` | `0x00000000` | +| 42.5 | `0x4045400000000000` | `0x40454000` | `0x00000000` | +| 42.52525 | `0x4045433B645A1CAC` | `0x4045433B` | `0x645A1CAC` | +| 43.0 | `0x4045800000000000` | `0x40458000` | `0x00000000` | +| 99.0 | `0x4058C00000000000` | `0x4058C000` | `0x00000000` | +| 99.99 | `0x4058FF5C28F5C28F` | `0x4058FF5C` | `0x28F5C28F` | +| 100.0 | `0x4059000000000000` | `0x40590000` | `0x00000000` | +| 3.14 | `0x40091EB851EB851F` | `0x40091EB8` | `0x51EB851F` | + +### The Float/Double Patching Workflow + +``` ++-----------------------------------------------------------------+ +| 1. Identify the float/double value in the decompiled view | +| - Look for hex constants like 0x40454000 or 0x4045433B | ++-----------------------------------------------------------------+ +| 2. Determine if it's float (32-bit) or double (64-bit) | +| - printf promotes floats to doubles! | +| - Check if value spans r2:r3 (double) or just r0 (float) | ++-----------------------------------------------------------------+ +| 3. Check if the low word (r2) is zero or non-zero | +| - Zero low word = only patch the high word | +| - Non-zero low word = patch BOTH words | ++-----------------------------------------------------------------+ +| 4. Calculate the new IEEE 754 encoding | +| - Convert your desired value to IEEE 754 | +| - Split into high/low words | ++-----------------------------------------------------------------+ +| 5. Patch the constant(s) in Ghidra | +| - Edit bytes in the Bytes window (Pencil mode) | +| - Replace the old encoding with the new one | ++-----------------------------------------------------------------+ +| 6. Export -> Convert to UF2 -> Flash -> Verify | +| - Same workflow as integer patching | ++-----------------------------------------------------------------+ +``` + +> Tip: **Key takeaway:** Hacking doubles is the same process as hacking floats - find the IEEE 754 constant, calculate the new encoding, patch it. The only extra step is checking whether the **low word** (`r2`) is also non-zero. Clean values like `42.5` only need one patch; messy fractions like `42.52525` need two! + +--- + +--- + +## Key Takeaways + +1. **Integers have fixed sizes** - `uint8_t` is 1 byte (0-255), `int8_t` is 1 byte (-128 to 127). The `u` prefix means unsigned. + +2. **IEEE 754 encodes floats in binary** - Sign bit, exponent (with bias), and mantissa form the encoding for both 32-bit floats and 64-bit doubles. + +3. **printf promotes floats to doubles** - Even when you pass a `float`, `printf` receives a 64-bit `double` due to C's variadic function rules. + +4. **64-bit values span two registers** - On ARM Cortex-M33, doubles use `r2` (low 32 bits) and `r3` (high 32 bits). + +5. **Clean fractions have zero low words** - Values like `42.5` have `0x00000000` in the low word; complex fractions like `42.52525` have non-zero low words. + +6. **Inline assembly controls hardware directly** - The `mcrr` coprocessor instruction talks to the GPIO block without any SDK overhead. + +7. **Binary patching works on any data type** - Integers, floats, and doubles can all be patched in Ghidra using the same workflow. + +--- + +## Glossary + +| Term | Definition | +| ----------------------- | ------------------------------------------------------------------------------ | +| **Bias** | Constant added to the exponent in IEEE 754 (127 for float, 1023 for double) | +| **Double** | 64-bit floating-point type following IEEE 754 double-precision format | +| **Exponent** | Part of IEEE 754 encoding that determines the magnitude of the number | +| **Float** | 32-bit floating-point type following IEEE 754 single-precision format | +| **FUNCSEL** | Function Select - register field that assigns a GPIO pin's function (e.g., SIO)| +| **GPIO** | General Purpose Input/Output - controllable pins on a microcontroller | +| **IEEE 754** | International standard for floating-point arithmetic and binary encoding | +| **Inline Assembly** | Assembly code embedded directly within C source using `__asm volatile` | +| **int8_t** | Signed 8-bit integer type (-128 to 127) | +| **IO_BANK0** | Register block at `0x40028000` that controls GPIO pin function selection | +| **Mantissa** | Fractional part of IEEE 754 encoding (23 bits for float, 52 bits for double) | +| **mcrr** | ARM coprocessor register transfer instruction used for GPIO control | +| **PADS_BANK0** | Register block at `0x40038000` that controls GPIO pad electrical properties | +| **Promotion** | Automatic conversion of a smaller type to a larger type (float -> double) | +| **Register Pair** | Two 32-bit registers (r2:r3) used together to hold a 64-bit value | +| **UF2** | USB Flashing Format - file format for Pico 2 firmware | +| **uint8_t** | Unsigned 8-bit integer type (0 to 255) | + +--- + +## Additional Resources + +### GPIO Coprocessor Reference + +The RP2350 GPIO coprocessor instructions: + +| Instruction | Description | +| --------------------------- | ---------------------------- | +| `mcrr p0, #4, Rt, Rt2, c0` | Set/clear GPIO output | +| `mcrr p0, #4, Rt, Rt2, c4` | Set/clear GPIO output enable | + +### RP2350 Memory Map Quick Reference + +| Address | Description | +| ------------ | ------------------------ | +| `0x10000000` | XIP Flash (code) | +| `0x20000000` | SRAM (data) | +| `0x40028000` | IO_BANK0 (GPIO control) | +| `0x40038000` | PADS_BANK0 (pad control) | +| `0xd0000000` | SIO (single-cycle I/O) | + +### IEEE 754 Encoding Formula + +``` ++-----------------------------------------------------------------+ +| Float (32-bit): [1 sign] [8 exponent] [23 mantissa] | +| Double (64-bit): [1 sign] [11 exponent] [52 mantissa] | +| | +| Value = (-1)^sign * 2^(exponent - bias) * (1 + mantissa) | +| | +| Float bias: 127 | +| Double bias: 1023 | ++-----------------------------------------------------------------+ +``` + +--- + +**Remember:** Every binary you encounter in the real world can be analyzed and understood using these same techniques. Whether it's an integer, a float, or a double - it's all just bits waiting to be decoded. Practice makes perfect! + +Happy hacking! + diff --git a/WEEK05/WEEK05.pdf b/WEEK05/WEEK05.pdf new file mode 100644 index 0000000..6a7cd6a Binary files /dev/null and b/WEEK05/WEEK05.pdf differ diff --git a/WEEK05/WEEK05a.md b/WEEK05/WEEK05a.md new file mode 100644 index 0000000..e0fc4d4 --- /dev/null +++ b/WEEK05/WEEK05a.md @@ -0,0 +1,615 @@ +# Week 5a: Deep-Dive Hardware Architecture: RP2350 PADS_BANK0, IO_BANK0, SIO, and the GPIO Coprocessor (GPIOC) + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Master the physical silicon reality of General Purpose Input/Output (GPIO) on the RP2350 microcontroller from Chapter 9 of the datasheet. +- Understand why microcontroller pins are never simple wires, dissecting the split between the internal 1.1V digital core domain (Vcore / DVDD) and the external 3.3V analog pad ring domain (Vio / IOVDD). +- Decouple the two independent hardware layers: electrical pad configuration (`PADS_BANK0` at `0x40038000`) versus digital crossbar multiplexing (`IO_BANK0` at `0x40028000`). +- Dissect every bitfield of `PADS_BANK0`: Output Disable (`OD`), Input Enable (`IE`), Pad Isolation (`ISO`), Drive Strength (2/4/8/12 mA), Pull-Up (`PUE`), Pull-Down (`PDE`), Schmitt Trigger (`SCHMITT`), and Slew Rate (`SLEWFAST`). +- Discover why unconfigured RP2350 pins are physically isolated by default (`ISO = 1`) and why digital input buffers are disconnected (`IE = 0`) to prevent catastrophic CMOS shoot-through leakage current. +- Master RP2350 **Bus Keeper Mode**, activated by setting both `PUE = 1` and `PDE = 1` to weakly latch floating line states without power dissipation. +- Navigate the digital crossbar switchboard in `IO_BANK0`: function selection (`FUNCSEL 0..31`), peripheral routing (UART, SPI, I2C, PWM, SIO, PIO), and signal overrides (`OUTOVER`, `OEOVER`, `INOVER`, `IRQOVER`). +- Analyze edge-sensitive and level-sensitive hardware interrupt generation across `proc0`, `proc1`, and `dormant_wake`. +- Understand the hardware Single-Cycle I/O (`SIO` at `0xd0000000`) block and contrast standard MMIO load/store operations against the RP2350 **GPIO Coprocessor (GPIOC)** on ARM Cortex-M33 Coprocessor Port `p0` (Section 3.6.1 and Section 9.9). +- Trace Thumb-2 coprocessor instructions (`mcrr p0`, `mcr p0`, `mrrc p0`) that set, clear, toggle, and configure GPIO output-enables in a single clock cycle with zero memory bus arbitration. +- Deconstruct the assembly implementation in `0x000b_integer-data-type.c`, performing a cycle-accurate trace of `asm_init_gpio_range()` and `asm_blink_pin()`. +- Eliminate the disassembler "hardware MMIO blind spot" using PyCortexMDebug in GDB for live dynamic peripheral struct inspection. +- Import CMSIS-SVD hardware definitions into Ghidra using SVD-Loader-Ghidra to reconstruct clear, readable decompilation from raw binary firmware. + +--- + +## Part 1: Why Microcontroller Pins Are Not Simple Wires + +### The Silicon Reality: Core Logic vs. The Pad Ring + +In software, a developer writes `gpio_put(16, 1)` and visualizes a direct wire connecting a CPU register bit to an external copper pin. In silicon engineering, this concept is completely false. + +A modern microcontroller die like the RP2350 is divided into two radically distinct physical and electrical domains: + +1. **The Internal Digital Core Domain (1.1V nominal DVDD):** + The central silicon die contains the dual ARM Cortex-M33 processors, the bus fabric, static RAM, cache controllers, and digital peripheral state machines (UART, SPI, PIO). These circuits are fabricated using ultra-thin, low-voltage nanoscale transistors designed exclusively for high switching speeds (150 MHz) and ultra-low power consumption. These microscopic gates cannot tolerate voltages above 1.21V. Connecting an external 3.3V signal directly to a core gate would instantly cause dielectric oxide breakdown, permanently melting the transistor. + +2. **The External Pad Ring Domain (1.8V - 3.3V nominal IOVDD):** + Surrounding the perimeter of the die is the **Pad Ring**. The pad ring consists of specialized, high-voltage analog and electrical interface cells ("pad cells") fabricated with thick-oxide transistors. These cells translate internal 1.1V digital logic signals up to external 3.3V board voltages, provide electrostatic discharge (ESD) protection diodes, supply high output drive currents (up to 12 mA) to charge external capacitive PCB traces, and filter noisy incoming analog edges. +``` ++-----------------------------------------------------------------+ +| RP2350 GPIO HARDWARE SUBSYSTEM ARCHITECTURE | +| | +| ARM Cortex-M33 Core / DMA / Interconnect | +| +---------------------------------------------------------+ | +| | Coprocessor Port p0 (GPIOC) / SIO (0xd0000000) | | +| | - 1-cycle atomic bit set/clear/toggle/oe (mcrr/mcr) | | +| | - 32-bit MMIO registers: GPIO_OUT, GPIO_OE, GPIO_IN | | +| +----------------------------+----------------------------+ | +| | | +| On-Chip Peripherals | | +| +----------------------------+----------------------------+ | +| | UART0/1, SPI0/1, I2C0/1, PWM, PIO0/1/2, CLK_GP, HSTX | | +| +----------------------------+----------------------------+ | +| | | +| v | +| Digital Routing Domain (clk_sys / 150 MHz) | +| +---------------------------------------------------------+ | +| | IO_BANK0 (0x40028000) - Digital Crossbar Switchboard | | +| | - FUNCSEL (bits 4:0): Selects function (0..31) | | +| | - Signal Overrides: OUTOVER, OEOVER, INOVER, IRQOVER | | +| | - Edge/Level Interrupt Detection (PROC0/1/DORMANT) | | +| +----------------------------+----------------------------+ | +| | | +| v | +| Physical / Electrical Domain (IOVDD 1.8V - 3.3V) | +| +---------------------------------------------------------+ | +| | PADS_BANK0 (0x40038000) - Die Perimeter Pad Ring | | +| | - ISO (bit 8): Pad Isolation Latch (frozen on reset!) | | +| | - OD / IE (bits 7,6): Output Disable / Input Enable | | +| | - DRIVE (bits 5:4): 2mA / 4mA / 8mA / 12mA Strength | | +| | - PUE / PDE (bits 3,2): Pull-Up / Pull-Down / Keeper | | +| | - SCHMITT / SLEWFAST (bits 1,0): Hysteresis & Slew | | +| +----------------------------+----------------------------+ | +| | | +| v | +| Physical Bond Pad & Pin | ++-----------------------------------------------------------------+ +``` +### The Physical Hazards of Uncontrolled I/O + +Why can't a microcontroller provide a single "GPIO register" where bit n directly drives pin n? Because every physical pin faces severe physical and electrical constraints: + +- **CMOS Shoot-Through Current:** When a CMOS digital input buffer encounters a voltage near mid-rail (e.g., 1.65V on a 3.3V rail), both the upper P-channel and lower N-channel MOSFETs turn partially ON simultaneously. This creates a low-resistance path directly from `IOVDD` to ground, dissipating substantial leakage current and generating heat. To prevent this on unused or analog pins (such as ADC inputs), the chip must provide a hardware switch to completely disconnect the input buffer (`IE = 0`). +- **Electrostatic Discharge (ESD):** External human touch or inductive spikes can inject thousands of volts into a pin. Pad cells integrate dual clamping diodes to shunt overvoltage spikes safely into power and ground rails. +- **Power Domain Collapse during Deep Sleep:** When the RP2350 enters low-power dormant sleep, the 1.1V core voltage can be completely powered down by the Power Manager (`POWMAN`). If the pad ring were directly connected to the core, the unpowered core outputs would float, causing external actuators, transceivers, or power supplies to turn on uncontrollably. The pad ring must therefore integrate **Pad Isolation Latches (`ISO`)** that freeze the external electrical state even when the CPU and digital core no longer exist! + +To solve these orthogonal challenges, the RP2350 divides GPIO into a clean three-tier hardware hierarchy: +- **`PADS_BANK0` (`0x40038000`):** Governs the electrical pad cells along the silicon die perimeter. +- **`IO_BANK0` (`0x40028000`):** Governs digital routing, multiplexing, and signal overrides. +- **`SIO` (`0xd0000000`) & Coprocessor Port `p0`:** Governs single-cycle processor execution. + +--- + +## Part 2: PADS_BANK0 Deep Dive: The Electrical Pad Ring + +### Physical Placement and Register Map + +The User Bank Pad Control registers reside at base address **`0x40038000`** (`PADS_BANK0_BASE`). + +According to **Chapter 9.11.3 (Table 851)** of the RP2350 Datasheet: +- Offset `0x00`: **`VOLTAGE_SELECT`** (Bank-wide voltage threshold: `0 = 3.3V`, `1 = 1.8V`). +- Offset `0x04`: **`GPIO0`** pad control register. +- Offset `0x08`: **`GPIO1`** pad control register. +- ... +- Offset `0x04 + (4 * x)`: **`GPIOx`** pad control register. + +Each 32-bit register controls the analog and physical circuitry of exactly one pin. +``` ++-----------------------------------------------------------------+ +| ANATOMY OF A SINGLE RP2350 PAD CELL | +| | +| IO_BANK0 Digital Signal PADS_BANK0 Controls | +| +-----------------------+ +-------------------+ | +| | OUTTOPAD (Data) | | DRIVE (2/4/8/12mA)| | +| | OETOPAD (Enable) | | SLEWFAST (0/1) | | +| +-----------+-----------+ | ISO (Isolation) | | +| | | OD (Out Disable) | | +| v +---------+---------+ | +| [ISO Latch (bit 8)] | | +| | | | +| v v | +| +---------------+ +-------------------+ | +| | Output Buffer |<----------------| High-Voltage CMOS | | +| | Driver Stage | | Push-Pull MOSFETs | | +| +-------+-------+ +---------+---------+ | +| | | | +| +-----------------+-----------------+ | +| | | +| +-----------------------------+---------------------------+ | +| | PHYSICAL PAD (External Pin) | | +| | - ESD Protection Diodes to IOVDD and GND | | +| | - Switchable 50k Pull-Up (PUE) to IOVDD | | +| | - Switchable 50k Pull-Down (PDE) to GND | | +| | - Bus Keeper: PUE=1 + PDE=1 (Weak State Retention) | | +| +-----------------------------+---------------------------+ | +| | | +| v | +| [Schmitt Trigger Filter] | +| | | +| v | +| [Input Enable Gate (IE)] | +| | | +| v | +| INFROMPAD to IO_BANK0 | ++-----------------------------------------------------------------+ +``` +### The PADS_BANK0 Bitfield Breakdown + +Every 32-bit `GPIOx` register in `PADS_BANK0` has the exact bitfield structure defined in **Table 853**: +``` ++-----------------------------------------------------------------+ +| PADS_BANK0: GPIOx REGISTER BITFIELDS (Offset: 0x04 + 4*x) | +| | +| 31 9 8 7 6 5 4 3 2 1 0 | +| +---------------+---+---+---+-------+---+---+---+---+ | +| | Reserved |ISO|OD |IE | DRIVE |PUE|PDE|SCH|SLW| | +| +---------------+---+---+---+-------+---+---+---+---+ | +| | +| Bit 8: ISO - Pad isolation latch (1 = isolated/frozen) | +| Bit 7: OD - Output disable (1 = output driver off) | +| Bit 6: IE - Input enable (1 = digital input buffer on)| +| Bits 5:4 DRIVE - Drive strength (00=2mA, 01=4mA, 10=8mA, | +| 11=12mA) | +| Bit 3: PUE - Pull-up resistor enable (~50 kOhm) | +| Bit 2: PDE - Pull-down resistor enable (~50 kOhm) | +| PUE & PDE == 1 - Bus Keeper Mode (weakly holds last state) | +| Bit 1: SCHMITT - Schmitt trigger hysteresis filter | +| Bit 0: SLEWFAST - Slew rate control (0 = Slow, 1 = Fast) | ++-----------------------------------------------------------------+ +``` +Let us examine each bitfield with silicon-level precision: + +#### 1. ISO (Bit 8) - Pad Isolation Control +- **Reset Value:** `0x1` (Isolated!). +- **Function:** When `ISO = 1`, an analog transmission gate isolates the pad from the switched core domain. The output driver state, output enable, and pull resistors remain frozen at their last latched values. +- **The Startup Gotcha:** Upon microcontroller power-up or reset, `ISO` resets to `1` across all pads! Before any pin can be driven or read by software, **the application software must explicitly clear the `ISO` bit**. If you attempt to configure `IO_BANK0` or `SIO` while `ISO = 1`, the external pin will remain totally unresponsive! + +#### 2. OD (Bit 7) - Output Disable +- **Reset Value:** `0x0`. +- **Function:** Master hardware output disable. When `OD = 1`, the pad's output driver transistors are completely turned OFF, forcing the pin into high-impedance (High-Z) mode. +- **Priority:** `OD` has absolute silicon priority over any output-enable signal emitted by internal peripherals (UART, SPI, PWM, SIO). Even if the UART hardware attempts to transmit, setting `OD = 1` silences the pin. + +#### 3. IE (Bit 6) - Input Enable +- **Reset Value:** `0x0` (Disabled!). +- **Function:** Master hardware gate for the digital input buffer. +- **The Analog Protection Rule:** When a pin is used as an analog input (e.g., ADC pins GPIO 26..29), or when a pin is left disconnected/floating, `IE` must remain `0`. Disabling the input buffer prevents floating voltages from causing CMOS shoot-through currents across internal transistor pairs. +- **The Input Gotcha:** If you want to read digital input from a button or serial line using SIO (`sio_hw->gpio_in`), you **must explicitly set `IE = 1`** in `PADS_BANK0`. If `IE = 0`, reading `GPIO_IN` will always return `0`, regardless of the voltage applied to the physical pin! + +#### 4. DRIVE (Bits 5:4) - Output Drive Strength +- **Reset Value:** `0x1` (4 mA). +- **Options:** `00 = 2mA`, `01 = 4mA`, `10 = 8mA`, `11 = 12mA`. +- **Silicon Implementation:** Inside the pad cell, the output push-pull stage consists of parallel arrays of PMOS (pull-up) and NMOS (pull-down) transistors. Selecting 2 mA enables a single transistor pair; selecting 12 mA switches on all parallel pairs, dramatically lowering the driver's output resistance (Ron). +- **Engineering Trade-off:** High drive strength (12 mA) charges external trace capacitance rapidly, enabling high-speed 50 MHz+ SPI clocks. However, it generates sharp current transients (dI/dt), leading to ground bounce, ringing, and electromagnetic interference (EMI). Low drive strength (2 mA) softens transitions, producing clean, low-noise waveforms on sensitive sensor buses. + +#### 5. PUE (Bit 3) & PDE (Bit 2) - Pull-Up and Pull-Down Resistors +- **Reset Value:** `PUE = 0`, `PDE = 1` (Pads reset with weak pull-downs active!). +- **Electrical Specification:** Nominal internal resistance of approximately 50 kOhm to `IOVDD` (PUE) or ground (PDE). +- **Bus Keeper Mode (Section 9.6.1):** What happens if software sets both `PUE = 1` and `PDE = 1` simultaneously? On older microcontrollers, this would create an illegal cross-conduction voltage divider dissipating power. On the RP2350, setting both bits activates **Bus Keeper Mode**! In this mode: + - If the pad's voltage is High, the pad pulls weakly Up. + - If the pad's voltage is Low, the pad pulls weakly Down. + When an external device stops driving a shared bus (e.g., a bidirectional data line in tri-state), the Bus Keeper holds the last valid logic level indefinitely, preventing the line from floating into mid-rail states without drawing active power! + +#### 6. SCHMITT (Bit 1) - Schmitt Trigger Enable +- **Reset Value:** `0x1` (Enabled). +- **Function:** Adds voltage hysteresis to the input comparator (VIH ~ 2.0V, VIL ~ 0.8V). If an incoming digital signal has a slow rise time or is corrupted by high-frequency noise, the Schmitt trigger prevents false multi-triggering and oscillation at the digital threshold. + +#### 7. SLEWFAST (Bit 0) - Slew Rate Control +- **Reset Value:** `0x0` (Slow). +- **Function:** `0 = Slow`, `1 = Fast`. Slow slew rate actively limits the edge rate (dV/dt) of the output buffer, minimizing radiated emissions and transmission-line reflections on unterminated PCB traces. Fast slew rate is required for high-frequency interfaces like QSPI, HSTX, or high-speed UART. + +--- + +## Part 3: IO_BANK0 Deep Dive: The Digital Crossbar Switchboard + +### The Multiplexer Matrix (`0x40028000`) + +Once a signal passes through the electrical pad ring, it enters the digital core domain. Here sits **`IO_BANK0`**, located at base address **`0x40028000`** (`IO_BANK0_BASE`). + +`IO_BANK0` functions as an enormous digital crossbar switchboard. The RP2350 contains dozens of peripheral controllers: +- Two SPI controllers (`SPI0`, `SPI1`) +- Two UART controllers (`UART0`, `UART1`) +- Two I2C controllers (`I2C0`, `I2C1`) +- Up to 12 dual-channel PWM slices (`PWM0` through `PWM11`) +- Three Programmable I/O blocks (`PIO0`, `PIO1`, `PIO2`) +- Single-Cycle I/O (`SIO`) +- General Purpose Clock outputs (`CLK_GP`) +- High-Speed Serial Transmitter (`HSTX`) + +None of these peripherals own any dedicated physical pins! Instead, every peripheral signal is routed through `IO_BANK0`, which selects which peripheral connects to which pad. + +### Register Structure per Pin + +In `IO_BANK0`, every GPIO pin occupies an **8-byte stride** containing two 32-bit registers (Section 9.11.1, Table 649): + +```text +GPIOx_STATUS Offset = 0x000 + (8 * x) +GPIOx_CTRL Offset = 0x004 + (8 * x) +``` + +For example, for GPIO 16: +```text +GPIO16_CTRL Offset = 0x004 + (8 * 16) = 0x004 + 0x080 = 0x084 +Physical Address = 0x40028000 + 0x084 = 0x40028084 +``` + +### The GPIOx_CTRL Register: Function Selection & Overrides +``` ++-----------------------------------------------------------------+ +| IO_BANK0: GPIOx_CTRL REGISTER BITFIELDS (Offset: 0x04+8*x)| +| | +| 31 30 29 28 27 18 17 16 15 14 13 12 11 5 4 0 | +| +-----+-----+---------+-----+-----+-----+---------+---------+ | +| |Rsvd |IRQO |Reserved |INOV |OEOV |OUTOV|Reserved | FUNCSEL | | +| +-----+-----+---------+-----+-----+-----+---------+---------+ | +| | +| Bits 4:0 FUNCSEL - Function Select (0..31, 5=SIO, 31=NULL) | +| Bits 13:12 OUTOVER - Output signal override (0=norm, 1=invert, | +| 2=force low, 3=force high) | +| Bits 15:14 OEOVER - Output enable override (0=norm, 1=invert, | +| 2=force disable, 3=force enable) | +| Bits 17:16 INOVER - Input signal override (0=norm, 1=invert, | +| 2=force low, 3=force high) | +| Bits 29:28 IRQOVER - Interrupt override (0=norm, 1=invert, | +| 2=force low, 3=force high) | ++-----------------------------------------------------------------+ +``` +According to **Table 651**, the bitfields of `GPIOx_CTRL` provide ultimate routing and logic control: + +#### 1. FUNCSEL (Bits 4:0) - Function Select +A 5-bit multiplexer index determining which peripheral controls the pin: +- `0x00`: JTAG +- `0x01`: SPI +- `0x02`: UART +- `0x03`: I2C +- `0x04`: PWM +- **`0x05`: SIO (Single-Cycle I/O - CPU / Coprocessor Software Control)** +- `0x06`: PIO0 +- `0x07`: PIO1 +- `0x08`: PIO2 +- `0x09`: Clock / Auxiliary +- `0x1f` (`31`): **NULL / Disconnected** (Reset Value!) + +Upon reset, `FUNCSEL` is set to `0x1f` (NULL). The pin is completely disconnected from all internal peripherals. To control a pin via CPU software or inline assembly, you must write `5` to `FUNCSEL`. + +#### 2. Signal Overrides (OUTOVER, OEOVER, INOVER, IRQOVER) +The RP2350 allows hardware hackers and defensive engineers to intercept, invert, or force signals between peripherals and pads without reconfiguring peripheral registers: + +| Override Field | Bits | Values & Behavior | +|:---|:---|:---| +| **`OUTOVER`** | `13:12` | `0 = Normal` (Peripheral drives data)
`1 = Invert` (Invert peripheral data)
`2 = Force Low` (Drive 0 to pad)
`3 = Force High` (Drive 1 to pad) | +| **`OEOVER`** | `15:14` | `0 = Normal` (Peripheral drives OE)
`1 = Invert` (Invert OE)
`2 = Force Disable` (Disable output driver)
`3 = Force Enable` (Enable output driver) | +| **`INOVER`** | `17:16` | `0 = Normal` (Pad drives peripheral)
`1 = Invert` (Invert pad data to peripheral)
`2 = Force Low` (Peripheral sees 0)
`3 = Force High` (Peripheral sees 1) | +| **`IRQOVER`** | `29:28` | `0 = Normal` (Pad drives interrupt)
`1 = Invert` (Invert interrupt logic)
`2 = Force Low` (Deassert IRQ)
`3 = Force High` (Assert IRQ) | + +*Security/Hacking Implication:* If a target firmware runs a proprietary UART protocol on GPIO 0/1, an analyst can invert the transmitted serial stream in hardware by writing `0x1` to `OUTOVER`, without the target firmware ever detecting that its serial framing has been altered! + +### The GPIOx_STATUS Register: Real-Time Silicon Probing + +The read-only `GPIOx_STATUS` register (+`0x000`) provides a live digital probe inside the chip (Table 650): +- **`INFROMPAD` (Bit 17):** The raw digital logic level coming from the pad cell (after Schmitt trigger, before any `INOVER` inversion). +- **`OETOPAD` (Bit 13):** The effective Output Enable signal being transmitted to the pad cell after all overrides. +- **`OUTTOPAD` (Bit 9):** The effective Output Data signal being transmitted to the pad cell after all overrides. +- **`IRQTOPROC` (Bit 26):** The interrupt status signal sent to the CPU NVIC. + +--- + +## Part 4: SIO vs. The RP2350 GPIO Coprocessor (GPIOC) + +### The Single-Cycle I/O (SIO) Architecture + +When a pin's `FUNCSEL` is set to `5` in `IO_BANK0`, it connects to the **SIO (Single-Cycle I/O)** block, located at base address **`0xd0000000`** (`SIO_BASE`). + +SIO provides fast, non-blocking registers that allow the ARM CPU to manipulate GPIOs in 1 clock cycle: +- `GPIO_OUT` (`0xd0000010`): Direct 32-bit output value. +- `GPIO_OUT_SET` (`0xd0000014`): Atomic bit set (writing a `1` sets the corresponding pin High). +- `GPIO_OUT_CLR` (`0xd0000018`): Atomic bit clear (writing a `1` clears the corresponding pin Low). +- `GPIO_OUT_XOR` (`0xd000001c`): Atomic bit toggle (writing a `1` inverts the corresponding pin). +- `GPIO_OE` (`0xd0000020`), `GPIO_OE_SET`, `GPIO_OE_CLR`, `GPIO_OE_XOR`: Output Enable registers. +- `GPIO_IN` (`0xd0000004`): Direct 32-bit digital input read. + +### The Memory Bus Overhead Bottleneck + +While SIO registers respond in a single clock cycle, interacting with them via standard ARM memory-mapped instructions (`ldr`, `str`) suffers from severe software overhead: + +1. **Address Materialization:** Cortex-M33 instructions cannot embed a 32-bit address like `0xd0000014` directly in a single 16-bit Thumb opcode. The compiler must generate an `ldr r0, =0xd0000014` instruction, pulling the 32-bit address from a Flash literal pool (taking 2 cycles plus cache/wait-states). +2. **Register Pressure:** The CPU must allocate a general-purpose register (`r0`) to hold the address and a second register (`r1`) to hold the bitmask (`1 << pin`). +3. **Bus Arbitration:** Even though SIO is single-cycle, the `str` instruction still arbitrates across the internal AHB-Lite bus matrix. +``` ++-----------------------------------------------------------------+ +| SIO MMIO ACCESS VS. GPIOC COPROCESSOR PORT P0 | +| | +| Standard SIO Access (3 to 5 Instructions / Bus Bottleneck) | +| +---------------------------------------------------------+ | +| | ldr r0, =0xd0000000 ; Load 32-bit SIO base | | +| | movs r1, #1 ; Load bitmask | | +| | lsls r1, r1, #16 ; Shift to pin 16 | | +| | str r1, [r0, #0x14] ; Write to GPIO_OUT_SET | | +| | => Requires register allocation, memory bus arbitration| | +| +---------------------------------------------------------+ | +| | +| RP2350 GPIOC Coprocessor Access (1 Instruction / Zero Bus) | +| +---------------------------------------------------------+ | +| | mcrr p0, #4, r4, r5, c0 ; gpioc_bit_out_put(pin,val) | | +| | - r4 = pin number (16) | | +| | - r5 = value (1 = High, 0 = Low) | | +| | => 1 CPU clock cycle! Zero bus traffic! Zero address! | | +| +---------------------------------------------------------+ | ++-----------------------------------------------------------------+ +``` +### The Silicon Breakthrough: GPIOC on Coprocessor Port p0 + +To eliminate this overhead entirely, Raspberry Pi engineered a custom hardware **GPIO Coprocessor (GPIOC)** directly into each ARM Cortex-M33 core on **Coprocessor Port `p0`** (Datasheet Section 3.6.1 and Section 9.9). + +Instead of issuing memory load and store instructions across the system bus, the ARM core uses native ARMv8-M coprocessor instructions (`mcr`, `mcrr`, `mrc`, `mrrc`): +``` ++-----------------------------------------------------------------+ +| COMPLETE RP2350 GPIO SIGNAL FLOW PATH | +| | +| [ Cortex-M33 CPU ] | +| | | +| (Coprocessor p0 / SIO) | +| v | +| [ SIO Block (0xd0000000) ] | +| | (Raw Out Data & Out Enable) | +| v | +| [ IO_BANK0 Crossbar (0x40028000) ] | +| | - Mux: FUNCSEL = 5 (Select SIO) | +| | - Apply OUTOVER / OEOVER overrides | +| v | +| [ Voltage Level Shifter ] (1.1V DVDD Core -> 3.3V IOVDD Pad) | +| v | +| [ PADS_BANK0 (0x40038000) ] | +| | - Check ISO latch (Must be cleared = 0) | +| | - Check OD bit (Must be cleared = 0) | +| | - Apply DRIVE strength (2/4/8/12mA) and SLEWFAST | +| v | +| [ Physical Bond Pad & Package Pin ] | +| | | +| |------> External Circuit (e.g. LED, Scope, Target) | +| | | +| [ Schmitt Trigger Input Buffer ] | +| | | +| [ PADS_BANK0 IE Gate ] (Must be set = 1 to pass) | +| v | +| [ Voltage Level Shifter ] (3.3V IOVDD Pad -> 1.1V DVDD Core) | +| v | +| [ IO_BANK0 INFROMPAD ] | +| | - Apply INOVER override | +| | - Route to Edge/Level Interrupt Detector | +| v | +| [ SIO GPIO_IN Register / Peripheral RX ] | ++-----------------------------------------------------------------+ +``` +According to **Section 3.6.1**, the GPIOC instruction set provides instantaneous, zero-latency GPIO control: + +#### 1. Single-Bit Output Enable (gpioc_bit_oe_put) +- **Opcode:** `mcrr p0, #4, Rt, Rt2, c4` +- `Rt`: General-purpose register holding the pin number (0..47). +- `Rt2`: General-purpose register holding the 1-bit value (1 = Output, 0 = Input). +- **Operation:** Atomically sets or clears the output enable for pin `Rt` in **1 single clock cycle**! No 32-bit addresses, no bit-shifts (`1 << pin`), and zero bus traffic! + +#### 2. Single-Bit Output Data (gpioc_bit_out_put) +- **Opcode:** `mcrr p0, #4, Rt, Rt2, c0` +- `Rt`: Pin number (0..47). +- `Rt2`: Value (1 = High, 0 = Low). +- **Operation:** Atomically drives pin `Rt` High or Low in 1 clock cycle. + +#### 3. Single-Pin Direct Toggling / Setting / Clearing +- Toggle pin `Rt`: `mcr p0, #5, Rt, c0, c0` (`gpioc_bit_out_xor`) +- Set pin `Rt` High: `mcr p0, #6, Rt, c0, c0` (`gpioc_bit_out_set`) +- Clear pin `Rt` Low: `mcr p0, #7, Rt, c0, c0` (`gpioc_bit_out_clr`) + +#### 4. 64-Bit Simultaneous Sampling +- **Opcode:** `mrrc p0, #0, Rt, Rt2, c0` +- Reads back all 48 GPIO pins simultaneously into register pair `Rt:Rt2` in a single clock cycle! + +--- + +## Part 5: Deconstructing 0x000b_integer-data-type.c + +Now let us examine the production firmware in `0x000b_integer-data-type/0x000b_integer-data-type.c`. This program configures pins 16, 17, and 18 entirely through raw assembly, manipulating `PADS_BANK0`, `IO_BANK0`, and the `GPIOC` coprocessor. + +### Dissecting asm_init_gpio_range() + +```c +static void asm_init_gpio_range(void) { + __asm volatile ( + "ldr r3, =0x40038000\n" // address of PADS_BANK0_BASE + "ldr r2, =0x40028004\n" // address of IO_BANK0 GPIO0.ctrl + "movs r0, #16\n" // GPIO16 (start pin) + "init_loop:\n" // loop start + "lsls r1, r0, #2\n" // pin * 4 (pad offset) + "adds r4, r3, r1\n" // PADS base + offset + "ldr r5, [r4]\n" // load current config + "bic r5, r5, #0x180\n" // clear OD+ISO + "orr r5, r5, #0x40\n" // set IE + "str r5, [r4]\n" // store updated config + "lsls r1, r0, #3\n" // pin * 8 (ctrl offset) + "adds r4, r2, r1\n" // IO_BANK0 base + offset + "ldr r5, [r4]\n" // load current config + "bic r5, r5, #0x1f\n" // clear FUNCSEL bits [4:0] + "orr r5, r5, #5\n" // set FUNCSEL = 5 (SIO) + "str r5, [r4]\n" // store updated config + "mov r4, r0\n" // pin + "movs r5, #1\n" // bit 1; used for OUT/OE writes + "mcrr p0, #4, r4, r5, c4\n" // gpioc_bit_oe_put(pin,1) + "adds r0, r0, #1\n" // increment pin + "cmp r0, #20\n" // stop after pin 18 + "blt init_loop\n" // loop until r0 == 20 + ); +} +``` + +### Line-by-Line Machine Code and Silicon Execution Trace + +1. **`ldr r3, =0x40038000`:** Loads `PADS_BANK0_BASE` into `r3`. +2. **`ldr r2, =0x40028004`:** Loads the address of `IO_BANK0: GPIO0_CTRL` into `r2`. +3. **`movs r0, #16`:** Sets loop counter starting at GPIO 16. +4. **`lsls r1, r0, #2`:** Multiplies pin number by 4 (16 * 4 = 64 = 0x40). +5. **`adds r4, r3, r1`:** Calculates the pad register address (0x40038000 + 0x40 = 0x40038040). +6. **`ldr r5, [r4]`:** Reads current pad configuration. +7. **`bic r5, r5, #0x180`:** Clears bits 7 and 8 (0x180 = 0001 1000 0000b): + - **Bit 7 (`OD`):** Cleared to `0` -> Output driver enabled! + - **Bit 8 (`ISO`):** Cleared to `0` -> Pad isolation latch de-asserted! The pad is connected to internal core logic! +8. **`orr r5, r5, #0x40`:** Sets bit 6 (0x40 = 0100 0000b): + - **Bit 6 (`IE`):** Set to `1` -> Input buffer enabled! +9. **`str r5, [r4]`:** Writes new configuration back to `PADS_BANK0`. The physical pad cell is now electrically active! +10. **`lsls r1, r0, #3`:** Multiplies pin number by 8 (16 * 8 = 128 = 0x80). +11. **`adds r4, r2, r1`:** Calculates `GPIO16_CTRL` address (0x40028004 + 0x80 = 0x40028084). +12. **`ldr r5, [r4]`:** Reads current control register. +13. **`bic r5, r5, #0x1f`:** Clears bits 4:0 (`FUNCSEL`), wiping out the reset value of `31` (NULL). +14. **`orr r5, r5, #5`:** Sets `FUNCSEL = 5` -> Connects pin 16 to the SIO block! +15. **`str r5, [r4]`:** Writes back to `IO_BANK0`. The digital routing switchboard is now connected! +16. **`mcrr p0, #4, r4, r5, c4`:** Calls `gpioc_bit_oe_put(16, 1)`. The GPIO coprocessor on port `p0` sets the Output Enable bit in SIO in 1 single clock cycle! + +### Dissecting asm_blink_pin() + +```c +static void asm_blink_pin(uint8_t pin) { + __asm volatile ( + "mov r4, %0\n" + "movs r5, #0x01\n" + "mcrr p0, #4, r4, r5, c0\n" // Drive High + : : "r"(pin) : "r4", "r5" + ); + sleep_ms(500); + __asm volatile ( + "mov r4, %0\n" + "movs r5, #0\n" + "mcrr p0, #4, r4, r5, c0\n" // Drive Low + : : "r"(pin) : "r4", "r5" + ); + sleep_ms(500); +} +``` + +- When `mcrr p0, #4, r4, r5, c0` executes with `r5 = 1`, the coprocessor drives the output bit High in 1 cycle. +- The high signal flows from SIO -> `IO_BANK0` multiplexer -> Voltage Level Shifter (1.1V -> 3.3V) -> `PADS_BANK0` push-pull MOSFET driver -> Physical Pin 16 -> LED illuminates! +- When `mcrr p0, #4, r4, r5, c0` executes with `r5 = 0`, the coprocessor drives the output bit Low in 1 cycle, turning off the LED. + +--- + +## Part 6: Live GDB and Ghidra Dynamic & Static Reverse Engineering + +### The Hardware MMIO Blind Spot + +When a reverse engineer opens a stripped binary or analyzes a firmware dump, disassemblers do not possess semantic knowledge of microcontroller memory maps. + +In standard GDB disassembly, you encounter instructions like: +```text +0x10000320 <+16>: ldr r3, [pc, #48] ; =0x40038000 +0x10000322 <+18>: ldr r2, [pc, #48] ; =0x40028004 +0x1000032c <+28>: bic r5, r5, #384 ; 0x180 +0x10000336 <+38>: orr r5, r5, #5 +0x1000033c <+44>: mcrr p0, #4, r4, r5, c4 +``` + +To an unassisted analyst, `0x40038000` is an anonymous memory address, `0x180` is an arbitrary bitmask, and `mcrr p0` looks like an invalid or proprietary instruction. This is the **Hardware MMIO Blind Spot**. + +### Dynamic Hardware Awareness with PyCortexMDebug in GDB + +To eliminate this blind spot in live debugging, we use **PyCortexMDebug**. PyCortexMDebug ingests the official ARM CMSIS System View Description (`.svd`) file for the RP2350 (`rp2350.svd`). + +Once loaded into GDB over OpenOCD and SWD: + +```text +(gdb) svd-load /path/to/rp2350.svd +(gdb) svd PADS_BANK0 +PADS_BANK0 @ 0x40038000: + VOLTAGE_SELECT = 0x00000000 + GPIO0 = 0x00000104 [ISO=1, DRIVE=4mA, PDE=1, SCHMITT=1] + GPIO16 = 0x00000054 [ISO=0, OD=0, IE=1, DRIVE=4mA, PDE=1, SCHMITT=1] +``` + +Notice the difference! In an instant: +- We verify that `GPIO0` has `ISO=1` (pad is isolated). +- We verify that after `asm_init_gpio_range()` runs, `GPIO16` has `ISO=0`, `OD=0`, and `IE=1`! + +You can also read the live hardware status of the digital crossbar switchboard: +```text +(gdb) svd IO_BANK0 GPIO16_CTRL +IO_BANK0 -> GPIO16_CTRL @ 0x40028084: + FUNCSEL = 0x05 (SIO) + OUTOVER = 0x00 (NORMAL) + OEOVER = 0x00 (NORMAL) + INOVER = 0x00 (NORMAL) +``` + +GDB confirms that GPIO 16 is actively routed to the SIO block! + +### Static Reversing with SVD-Loader-Ghidra + +In static analysis with Ghidra, decompiled code for raw MMIO looks like: +```c +*(uint32_t *)(uVar3 + 0x40) = *(uint32_t *)(uVar3 + 0x40) & 0xfffffe7f | 0x40; +*(uint32_t *)(uVar2 + 0x80) = *(uint32_t *)(uVar2 + 0x80) & 0xffffffe0 | 5; +``` + +This decompilation is obscure. By running **SVD-Loader-Ghidra**: +1. Ghidra creates memory-mapped peripheral blocks labeled `PADS_BANK0` and `IO_BANK0`. +2. Ghidra generates C structure definitions matching the RP2350 hardware layout. +3. The decompilation transforms into clean, readable peripheral code: + +```c +pads_bank0->GPIO[16] = (pads_bank0->GPIO[16] & ~0x180) | 0x40; +io_bank0->GPIO[16].CTRL = (io_bank0->GPIO[16].CTRL & ~0x1f) | FUNCSEL_SIO; +``` + +--- + +## Part 7: Summary & Hardware Register Master Cheat Sheet + +### Architectural Summary + +1. **Hardware Split:** RP2350 enforces a strict division between electrical physics (`PADS_BANK0`) and digital logic (`IO_BANK0`). +2. **PADS_BANK0 (`0x40038000`):** Manages analog pad cells. Controls `ISO` (isolation latch), `OD` (output disable), `IE` (input enable), `DRIVE` (2/4/8/12 mA), `PUE`/`PDE` (pulls and Bus Keeper), `SCHMITT`, and `SLEWFAST`. +3. **IO_BANK0 (`0x40028000`):** Manages digital crossbar routing. Controls `FUNCSEL` (functions 0..31; 5 = SIO), logic overrides (`OUTOVER`, `OEOVER`, `INOVER`, `IRQOVER`), and edge/level interrupt generation. +4. **SIO (`0xd0000000`):** Single-Cycle I/O memory-mapped registers for 32-bit atomic bit set, clear, toggle, and read. +5. **GPIOC (Coprocessor Port `p0`):** Native ARMv8-M coprocessor hardware enabling 1-cycle single-bit output and output-enable manipulation (`mcrr p0, #4`), single-pin toggling (`mcr p0, #5`), and 64-bit sampling (`mrrc p0, #0`) with zero memory bus overhead. + +### Hardware Register Reference Table + +| Subsystem | Base Address | Register / Offset | Key Bitfields & Silicon Function | +|:---|:---|:---|:---| +| **PADS_BANK0** | `0x40038000` | `VOLTAGE_SELECT` (`+0x00`) | Bit 0: Bank voltage select (`0 = 3.3V`, `1 = 1.8V`) | +| **PADS_BANK0** | `0x40038000` | `GPIOx` (`+0x04 + 4*x`) | Bit 8: `ISO` (Isolation Latch, reset=1)
Bit 7: `OD` (Output Disable)
Bit 6: `IE` (Input Enable, reset=0)
Bits 5:4: `DRIVE` (`00=2mA`, `01=4mA`, `10=8mA`, `11=12mA`)
Bit 3: `PUE` (Pull-Up Enable)
Bit 2: `PDE` (Pull-Down Enable)
Bit 1: `SCHMITT` (Hysteresis Enable)
Bit 0: `SLEWFAST` (Slew Rate Control) | +| **IO_BANK0** | `0x40028000` | `GPIOx_STATUS` (`+0x000 + 8*x`) | Bit 17: `INFROMPAD` (Raw input level)
Bit 13: `OETOPAD` (Effective Output Enable)
Bit 9: `OUTTOPAD` (Effective Output Data)
Bit 26: `IRQTOPROC` (Interrupt status) | +| **IO_BANK0** | `0x40028000` | `GPIOx_CTRL` (`+0x004 + 8*x`) | Bits 4:0: `FUNCSEL` (`0=JTAG`, `1=SPI`, `2=UART`, `3=I2C`, `4=PWM`, `5=SIO`, `6=PIO0`, `31=NULL`)
Bits 13:12: `OUTOVER`
Bits 15:14: `OEOVER`
Bits 17:16: `INOVER`
Bits 29:28: `IRQOVER` | +| **SIO** | `0xd0000000` | `GPIO_OUT` (`+0x10`) | Bits 31:0: Output data values | +| **SIO** | `0xd0000000` | `GPIO_OUT_SET` (`+0x14`) | Bits 31:0: Atomic bit set High | +| **SIO** | `0xd0000000` | `GPIO_OUT_CLR` (`+0x18`) | Bits 31:0: Atomic bit clear Low | +| **SIO** | `0xd0000000` | `GPIO_OUT_XOR` (`+0x1c`) | Bits 31:0: Atomic bit toggle | +| **SIO** | `0xd0000000` | `GPIO_OE` (`+0x20`) | Bits 31:0: Output enable (`1 = Out, 0 = In`) | +| **SIO** | `0xd0000000` | `GPIO_IN` (`+0x04`) | Bits 31:0: Direct input sample (Requires `IE=1`) | +| **GPIOC** | Port `p0` | `mcrr p0, #4, Rt, Rt2, c4` | Single-pin atomic output enable write (`gpioc_bit_oe_put`) | +| **GPIOC** | Port `p0` | `mcrr p0, #4, Rt, Rt2, c0` | Single-pin atomic output data write (`gpioc_bit_out_put`) | +| **GPIOC** | Port `p0` | `mcr p0, #5, Rt, c0, c0` | Single-pin atomic output toggle (`gpioc_bit_out_xor`) | +| **GPIOC** | Port `p0` | `mcr p0, #6, Rt, c0, c0` | Single-pin atomic output set (`gpioc_bit_out_set`) | +| **GPIOC** | Port `p0` | `mcr p0, #7, Rt, c0, c0` | Single-pin atomic output clear (`gpioc_bit_out_clr`) | +| **GPIOC** | Port `p0` | `mrrc p0, #0, Rt, Rt2, c0` | 64-bit dual-word simultaneous GPIO sample | + +*** diff --git a/WEEK05/WEEK05a.pdf b/WEEK05/WEEK05a.pdf new file mode 100644 index 0000000..05776d7 Binary files /dev/null and b/WEEK05/WEEK05a.pdf differ diff --git a/WEEK05/float_hex_converter.py b/WEEK05/float_hex_converter.py new file mode 100644 index 0000000..e2241e9 --- /dev/null +++ b/WEEK05/float_hex_converter.py @@ -0,0 +1,202 @@ +#!/usr/bin/env python3 +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: float_hex_converter.py +# Desc: Convert and explain IEEE 754 float/hex operations step-by-step. +# Created: 2026 + +"""Convert and explain IEEE 754 float/hex operations step-by-step.""" + +import argparse +import struct +import sys + + +def _exp_str(e_val: int, bias: int, is_64: bool) -> str: + """ + Get accurate true exponent string accounting for IEEE 754 edge cases. + + Parameters + ---------- + e_val : int + The stored exponent value. + bias : int + The exponent bias (127 or 1023). + is_64 : bool + True if 64-bit precision. + + Returns + ------- + str + The formatted true exponent explanation string. + """ + if e_val == 0: + return f"0 (Zero/Subnormal, True Exp: {1 - bias})" + if e_val == (2047 if is_64 else 255): + return f"{e_val} (Inf/NaN flag)" + return f"{e_val} - {bias} = {e_val - bias}" + + +def _print_encode_steps(val: float, b: int) -> None: + """ + Print the math steps for encoding a float to hex. + + Parameters + ---------- + val : float + The float value to encode. + b : int + The bit size (32 or 64). + + Returns + ------- + None + """ + f1, f2, bias = (" None: + """ + Print the math steps for decoding a hex string to float. + + Parameters + ---------- + hex_str : str + The hex string to decode. + + Returns + ------- + None + """ + c = hex_str.lower() + if c.startswith("0x"): + c = c[2:] + b, f1, f2, bias = (64, " 8 else (32, " bool: + """ + Check if a string is a hexadecimal representation. + + Parameters + ---------- + s : str + Candidate string, with or without a 0x prefix. + + Returns + ------- + bool + True if every character is a hexadecimal digit. + """ + cleaned = s.lower() + if cleaned.startswith("0x"): + cleaned = cleaned[2:] + if not cleaned: + return False + return all(c in "0123456789abcdef" for c in cleaned) + + +def _process_conversion(val_str: str) -> None: + """ + Execute the conversion and print the output. + + Parameters + ---------- + val_str : str + The raw input string to process. + + Returns + ------- + None + """ + cleaned = val_str.strip() + if cleaned.lower().startswith("0x") or (len(cleaned) >= 8 and _is_hex(cleaned)): + _print_decode_steps(cleaned) + else: + val = float(cleaned) + _print_encode_steps(val, 32) + _print_encode_steps(val, 64) + + +def main() -> int: + """ + Execute the conversion pipeline based on CLI arguments. + + Parameters + ---------- + None + + Returns + ------- + int + Zero on successful conversion, otherwise non-zero. + """ + parser = argparse.ArgumentParser(description="Float/Hex step converter.") + parser.add_argument("val", help="Hex (0x...) or Float value to convert.") + args = parser.parse_args() + try: + _process_conversion(args.val) + return 0 + except Exception as e: + print(f"Error: {e}", file=sys.stderr) + return 1 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/WEEK05/slides/WEEK05-IMG00.svg b/WEEK05/slides/WEEK05-IMG00.svg new file mode 100644 index 0000000..77db88a --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 05 + + +Integers and Floats in Embedded Systems: +Debugging and Hacking Integers and Floats +w/ Intermediate GPIO Output Analysis + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK05/slides/WEEK05-IMG01.svg b/WEEK05/slides/WEEK05-IMG01.svg new file mode 100644 index 0000000..1659bfa --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG01.svg @@ -0,0 +1,77 @@ + + + + + +Integer Data Types +Fixed-Size Types for Embedded Systems + + + +uint8_t +Unsigned 8-bit +1 byte +Range: +0 to 255 +Ages, counts, always positive + + + +int8_t +Signed 8-bit +1 byte +Range: +-128 to 127 +Temperature, can be negative + + + +uint16_t +Unsigned 16-bit +2 bytes +Range: +0 to 65,535 +Sensor readings, medium values + + + +uint32_t +Unsigned 32-bit +4 bytes +Range: +0 to ~4 billion +Addresses, timestamps + + + +Code Example + +uint8_t age = 43; +// unsigned, 0-255 +int8_t range = -42; +// signed, -128 to 127 + + + +Key Insight +The +u +prefix means +unsigned +(no negatives) +Without +u += signed (allows negatives) +Choose the smallest type that fits your data + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG02.svg b/WEEK05/slides/WEEK05-IMG02.svg new file mode 100644 index 0000000..229f5e9 --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG02.svg @@ -0,0 +1,79 @@ + + + + + +Two's Complement +How Negative Numbers are Stored + + + +Encoding -42 as int8_t + + +Step 1: Start +42 = 0x2A + + +Step 2: Flip +~0x2A = 0xD5 + + +Step 3: Add 1 +0xD5+1 = 0xD6 + +Binary: +00101010 +-> +11010101 +-> +11010110 + +Result: -42 stored as 0xD6 in memory +Top bit = 1 means negative + + + +Signed vs Unsigned: Same Bits! + +Hex +Binary +uint8_t +int8_t + + + +0x2A +00101010 +42 +42 + +0xD6 +11010110 +214 +-42 + +Same byte 0xD6 = 214 unsigned, -42 signed + + + +GDB Verification + + +(gdb) +x/1xb &range +0x200003e7: +0xd6 +// -42 in memory + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG03.svg b/WEEK05/slides/WEEK05-IMG03.svg new file mode 100644 index 0000000..497a13d --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG03.svg @@ -0,0 +1,75 @@ + + + + + +Inline Assembly GPIO +Direct Hardware Control via ASM + + + +GPIO Init Loop (pins 16-19) + + +1. Config Pad +PADS_BANK0 +Clear OD+ISO, set IE +0x40038000 + + +2. Set Function +IO_BANK0 +FUNCSEL = 5 (SIO) +0x40028004 + + +3. Enable Out +GPIO Coprocessor +mcrr p0,#4,r4,r5,c4 +Output Enable + +Loop: r0 = 16 to 19 +Red, Green, Blue, Yellow LEDs +Each pin: pad config + function select + OE + + + +Blink Loop + + +mcrr p0,#4,r4,r5,c0 + +r4 = pin, r5 = value +c0 = output value register +r5=1 ON, r5=0 OFF + + + +Pin Cycling + + +pin++; +if (pin > 18) pin=16; + +Cycles: 16 -> 17 -> 18 -> 16 +Red -> Green -> Blue -> repeat + + + +Why Inline Assembly? +gpio_put(16,1) calls +mcrr +underneath +Inline ASM shows what the SDK does at hardware level + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG04.svg b/WEEK05/slides/WEEK05-IMG04.svg new file mode 100644 index 0000000..ecfa467 --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG04.svg @@ -0,0 +1,83 @@ + + + + + +IEEE 754 Float +32-bit Single Precision Encoding + + + +Float Bit Layout (32 bits) + + +S + + +Exponent (8) + + +Mantissa (23) + +1 bit +sign + +8 bits +bias=127 + +23 bits ++implicit 1 + + + +Decode Formula +Value = (-1)^sign × 2^(exp-127) × (1 + mantissa) +Sign determines +/- Exponent scales with bias 127 Mantissa adds precision +Special cases: exp=0 or 255 (denorm, inf, NaN) + + + +Decode Example: 42.5 + +Sign Bit: 0 +Positive number + +Exponent: 10000100 += 132 decimal + +Bias subtraction: 132 - 127 = 5 + +Mantissa: 01010100...0 += 1.010101 + +Combine: 1.010101 × 2^5 = 42.5 + +Hex: 0x422A0000 + +Binary: 01000010001010100000000000000000 + + + +32-bit Storage Comparison + +Integer: +Exact values +Range: -2.1B to +2.1B +No decimals + +Float: +Approximate values +Range: ±10^38 +~7 sig digits + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG05.svg b/WEEK05/slides/WEEK05-IMG05.svg new file mode 100644 index 0000000..90e591f --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG05.svg @@ -0,0 +1,76 @@ + + + + + +Float in Ghidra +Analyzing 42.5 in the Binary + + + +Decompiled main() + + +int main(void) { +stdio_init_all(); +uVar1 = DAT_1000024c; +do { +printf(fmt,0,uVar1); +} while(true); + + + +Key Discovery + +printf with %f always +receives a +double +(64-bit) + +C promotes float to double +for variadic functions! + + +42.5 sent as double + + + +Register Pair r2:r3 + + +r2 (low): +0x00000000 + + +r3 (high): +0x40454000 + +Combined: 0x4045400000000000 += 42.5 + + + +Assembly View + + +1000023a +00 24 +movs r4, #0x0 +// r2 = 0 + +1000023c +03 4d +ldr r5,[DAT...] +// r3 = 0x40454000 + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG06.svg b/WEEK05/slides/WEEK05-IMG06.svg new file mode 100644 index 0000000..3c82e9e --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG06.svg @@ -0,0 +1,87 @@ + + + + + +Patching Float +Changing 42.5 to 99.0 in Ghidra + + + +Calculate 99.0 as Double + +99 decimal = +1100011 +binary + +Normalize: +1.100011 x 2^6 + +Sign: +0 +Exp: +6+1023 = 1029 + +Mantissa: +100011000...0 + +Full double: 0x4058C00000000000 + + + +Before (42.5) + + +r2: +0x00000000 + + +r3: +0x40454000 + +Output: fav_num: 42.500000 + + +After (99.0) + + +r2: +0x00000000 +same! + + +r3: +0x4058C000 +changed + +Output: fav_num: 99.000000 + + + +Patch in Ghidra + + +1. Window: Bytes +Open byte editor + + +2. Find 00404540 +High word of 42.5 + + +3. Patch 00C05840 +High word of 99.0 + +Only one word to patch (low word is 0) + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG07.svg b/WEEK05/slides/WEEK05-IMG07.svg new file mode 100644 index 0000000..d67d52e --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG07.svg @@ -0,0 +1,75 @@ + + + + + +Double Precision +IEEE 754 64-bit Floating Point + + + +64-Bit Layout + + +Sign +1 bit + + +Exponent +11 bits (bias 1023) + + +Mantissa (Fraction) +52 bits + +Formula: (-1)^S x 1.Mantissa x 2^(Exp-1023) + + + +Encoding 42.52525 + +Sign: +0 (positive) + +Exponent: +5 + 1023 = 1028 += 0x404 (hex) + +Mantissa: +0101010000110011... + +Full 64-bit hex: +0x4045433B645A1CAC + + + +Float (32-bit) + +Size: 4 bytes +Exp: 8 bits +Mantissa: 23 bits +Precision: ~7 digits +Bias: 127 +1 register (ARM) + + +Double (64-bit) + +Size: 8 bytes +Exp: 11 bits +Mantissa: 52 bits +Precision: ~15 digits +Bias: 1023 +2 registers (r2:r3) + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG08.svg b/WEEK05/slides/WEEK05-IMG08.svg new file mode 100644 index 0000000..ad7749c --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG08.svg @@ -0,0 +1,71 @@ + + + + + +Double in Ghidra +Analyzing 42.52525 in memory + + + +Decompiled main() + + +int main(void) { +double fav_num + = 42.52525; +stdio_init_all(); +} + + + +Key Difference + +Float (42.5): +r2 = 0x00000000 (zero!) +r3 = 0x40454000 + +Double (42.52525): +r2 = 0x645A1CAC (non-zero!) + + + +Register Pair r2:r3 + + +r3 (HIGH): +0x4045433B + + +r2 (LOW): +0x645A1CAC + +Combined: 0x4045433B645A1CAC = 42.52525 + + + +Assembly (ldrd) + + +ldrd r2,r3,[PC,#0x10] +; Loads BOTH words at once +; r2 gets low word +; r3 gets high word + + +ldrd = Load +Register +Doubleword +ARM Cortex-M33 + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG09.svg b/WEEK05/slides/WEEK05-IMG09.svg new file mode 100644 index 0000000..fcf359f --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG09.svg @@ -0,0 +1,88 @@ + + + + + +Patching Double +Changing 42.52525 to 99.99 + + + +99.99 as IEEE 754 Double + +Sign: +0 +Exp: +6 + 1023 = 1029 + +Result: +0x4058FF5C28F5C28F + +r3 (HIGH) = 0x4058FF5C +r2 (LOW) = 0x28F5C28F + + + +Before (42.52525) + + +r3: +0x4045433B + + +r2: +0x645A1CAC + +printf: 42.525250 +Both words non-zero + + +After (99.99) + + +r3: +0x4058FF5C +changed + + +r2: +0x28F5C28F +changed + +printf: 99.990000 +BOTH words changed! + + + +Float Patch + +Words changed: +1 +r2 (low): +stays 0x0 +r3 (high): +patched +Easier to patch + + +Double Patch + +Words changed: +2 +r2 (low): +patched +r3 (high): +patched +Both words must change + \ No newline at end of file diff --git a/WEEK05/slides/WEEK05-IMG10.svg b/WEEK05/slides/WEEK05-IMG10.svg new file mode 100644 index 0000000..ce71556 --- /dev/null +++ b/WEEK05/slides/WEEK05-IMG10.svg @@ -0,0 +1,101 @@ + + + + + +IEEE 754 & Data Types +Data Types and IEEE 754 Reference + + + +IEEE 754 Hex Values + + +Value +Float (32b) +Double (64b) + + + + +42.0 +0x42280000 +0x4045000000000000 + + +42.5 +0x422A0000 +0x4045400000000000 + + +99.0 +0x42C60000 +0x4058C00000000000 + + +99.99 +0x42C7F5C3 +0x4058FF5C28F5C28F + + +3.14 +0x4048F5C3 +0x40091EB851EB851F + + +100.0 +0x42C80000 +0x4059000000000000 + +Tip: float low word often 0x0; double low word usually non-zero + + + +Patching Workflow + + +1. Identify +float / double + + +2. Check r2 +zero = float + + +3. Calculate +new hex value + + +4. Patch +in byte editor + + +5. Export +UF2 + test + + + +Integer Types + +uint8_t: 0-255 +int8_t: -128 to 127 +Two's complement for signed + + +Key Insight + +Float: patch 1 word +Double: patch 2 words +Check r2 to detect type + \ No newline at end of file diff --git a/WEEK06/0x0011a_cb/0x0011a_cb.bin b/WEEK06/0x0011a_cb/0x0011a_cb.bin new file mode 100755 index 0000000..65ecf0b Binary files /dev/null and b/WEEK06/0x0011a_cb/0x0011a_cb.bin differ diff --git a/WEEK06/0x0011a_cb/0x0011a_cb.uf2 b/WEEK06/0x0011a_cb/0x0011a_cb.uf2 new file mode 100644 index 0000000..e356615 Binary files /dev/null and b/WEEK06/0x0011a_cb/0x0011a_cb.uf2 differ diff --git a/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.md b/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.md new file mode 100644 index 0000000..43e3610 --- /dev/null +++ b/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.md @@ -0,0 +1,159 @@ +# Operation Dark Vector: Classified Intelligence Briefing + +``` ++-----------------------------------------------------------------+ +| TOP SECRET // NOFORN | ++-----------------------------------------------------------------+ +| | +|OPERATION DARK VECTOR | +| | +|CLASSIFIED BRIEFING: LIVE CHALLENGE 0x01 | +| | +|NATIONAL SECURITY AGENCY / GMU RHET | ++-----------------------------------------------------------------+ +``` + +## 1. The Advice + +INT. NSA EXPLOITATION CELL. 05:03. + +A carbon-fiber forward fuselage section of a downed state-sponsored autonomous +micro-UAV sits clamped in an anti-static fixture on the bench. + +On the front of the avionics bay, a status diode glows a steady red: `GP16` high. +Beside it, an I2C 1602 LCD backpack is wired to `GP2` and `GP3`, outputting +telemetry coordinates. A mock propeller servo is wired to `GP6`, a u-blox NEO-6M +GPS receiver is wired to PIO UART RX on `GP7`, and a REYAX RYLR998 LoRa transceiver +is wired to `UART1` on `GP8` and `GP9`. A thin jumper loops from `GP15` up to the +`3V3` rail. + +The Director sets down a field report and looks at the red diode. + +**DIRECTOR:** Where was it heading? + +**ANALYST:** Buddy says it knows. + +**DIRECTOR:** Buddy. + +**ANALYST:** The model. The one we built for automated firmware triage. Give it +the image, ask it the question. + +**DIRECTOR:** And? + +**ANALYST:** Nine seconds with the stripped flash image. + +She turns her monitor toward him. + +``` ++-----------------------------------------------------------------+ +| BUDDY // CLASSIFIED EXPLOITATION ASSIST // CONF: 0.98 | ++-----------------------------------------------------------------+ +| ACTION : Recover target waypoint coordinates. | +| MECHANISM : Literal pool constants in .rodata parsed. | +| PREDICTION : Destination is +38.840280, -77.428890. | +| CONFIDENCE : 0.98 | ++-----------------------------------------------------------------+ +``` + +**DIRECTOR:** 0.98. Centreville, Virginia. That is the whole answer. + +**ANALYST:** Buddy found the pre-programmed decoy coordinate in `.rodata`. Buddy +never looked at SRAM. Buddy never audited the cryptographic routine decrypting +the true mission target at boot. + +**DIRECTOR:** Buddy says 0.98. + +**ANALYST:** Buddy saw a float pair in Flash and stopped looking. If that drone +were flying to Centreville, it would not be broadcasting those exact coordinates +in plaintext telemetry for every SIGINT sensor in the sector to hear. + +## 2. What Buddy Is + +Buddy is not a person. It is a model. It has parsed more disassembled machine +code than any engineer on earth, and it speaks with total, unhesitating certainty. + +That certainty is lethal when tracking an adversary strike platform. + +Buddy scanned the flash image, spotted two IEEE-754 double-precision floating-point +constants matching geographic coordinates, and concluded that finding the floats +is the whole game. It extracted the numbers, declared the target solved, and moved +on. + +What Buddy failed to consider is that adversary weapons engineers anticipate +capture and forensic recovery. They do not hardcode high-value strategic targets +in plaintext Flash memory. A real drone stores decoy launch coordinates in Flash, +while encrypting its true destination under 128-bit AES. At power-on, firmware +decrypts the authentic waypoint directly into SRAM before engaging guidance. + +The plaintext coordinates in Flash are bait. Buddy took the bait. + +Buddy saw the floating-point constants. Buddy did not verify the ground truth. + +## 3. The Operation + +At 04:17, radar pickets tracked an adversary one-way micro-UAV descending into +the woods outside Centreville, Virginia after battery exhaustion. Technical +Intelligence operators recovered the airframe before adversary recovery forces +could zeroize the avionics. + +The flight computer is built around a bare-metal RP2350 (ARM Cortex-M33). There +are no debug symbols. There is no operating system. There is no SVD file to label +the registers. All you have is `0x0011a_cb.bin` mapped into Flash at `0x10000000`, +and the physical breadboard hardware in front of you. + +* **Pin 4 (`GP2`)**: I2C1 SDA (to 1602 LCD backpack). +* **Pin 5 (`GP3`)**: I2C1 SCL (to 1602 LCD backpack). +* **Pin 9 (`GP6`)**: SG90 servo PWM mock propeller blade. +* **Pin 10 (`GP7`)**: PIO UART RX (from u-blox NEO-6M GPS TXD). +* **Pin 11 (`GP8`)**: LoRa UART1 TX (to RYLR998 RXD). +* **Pin 12 (`GP9`)**: LoRa UART1 RX (from RYLR998 TXD). +* **Pin 20 (`GP15`)**: Mission telemetry sync trigger (pull-up to `3V3`). +* **Pin 21 (`GP16`)**: Red LED (`NO GNSS FIX // UNGUIDED SEARCH`). +* **Pin 22 (`GP17`)**: Green LED (`TARGET REACHED // PAYLOAD RELEASED`). +* **Pin 24 (`GP18`)**: Yellow LED (`SATELLITES ACQUIRED // 3D FIX LOCK`). +* **Pin 36 (`3V3`)**: 3.3V power rail (RYLR998 VDD and GPS VCC). +* **Pin 38 (`GND`)**: Ground reference. +* **Pin 40 (`VBUS`)**: 5V power rail (SG90 servo VCC and LCD power). + +Inside this image there is an AES-128 ECB decryption routine, an encrypted 16-byte +target coordinate block in `.rodata`, double-precision floating-point navigation +math, and dynamic GNSS state evaluation. Whatever coordinates actually steer the +aircraft are buried in the stripped ARM Thumb-2 machine code. + +## 4. The Mandate + +The Director crosses his arms. + +**DIRECTOR:** Prove Buddy right, or prove it wrong. + +**ANALYST:** I need thirty minutes with GDB and Ghidra. + +**DIRECTOR:** You have twenty. Reverse the boot sequence. Audit the memory +structures. Do not sign off on that flight path until you have extracted the true +target from silicon and verified it bit-for-bit. + +The orders are clear: + +1. **Disprove the Decoy Coordinates**: Locate the pre-programmed coordinates in + Flash and prove why they represent a decoy origin rather than the real target. +2. **Recover the AES-128 Key and Ciphertext**: Identify the 16-byte ciphertext + block and the 16-byte AES key embedded within `.rodata`. +3. **Decrypt the True Destination**: Reverse the boot decryption sequence and + compute the true target latitude and longitude in double-precision IEEE-754. +4. **Neutralize the Flight Plan**: Execute a verified exploit—either by mutating + the destination coordinates in SRAM via GDB or patching the binary in Flash. +5. **Verify the Hardware**: Transition the live breadboard from the Red LED on + `GP16` to the solid Green LED on `GP17` on physical silicon. + +A machine's 0.98 guess does not authorize an airstrike. + +## 5. The Challenge + +You have the image. You have the board. You have the tools and the time Buddy did +not need. + +Buddy has given you its answer, and it is confident. + +Is it that simple? + +Go find out. diff --git a/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.pdf b/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.pdf new file mode 100644 index 0000000..d5bd238 Binary files /dev/null and b/WEEK06/0x0011a_cb/CLASSIFIED-BRIEF-0x01.pdf differ diff --git a/WEEK06/0x0011a_cb/scripts/lora_console.py b/WEEK06/0x0011a_cb/scripts/lora_console.py new file mode 100755 index 0000000..24310f9 --- /dev/null +++ b/WEEK06/0x0011a_cb/scripts/lora_console.py @@ -0,0 +1,195 @@ +#!/usr/bin/env python3 +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: lora_console.py +# Desc: Interactive REYAX RYLR998 terminal for the FT232RL ground station. +# Created: 2026 + +""" +Interactive LoRa terminal for the REYAX RYLR998 ground station. + +Sends AT commands as complete bursts terminated with a carriage return and line +feed to avoid the RYLR998 inter-character timeout error, and prints incoming +packets from the airborne node as they arrive. +""" + +import argparse +import sys +import threading +import time + +try: + import serial +except ImportError: + serial = None + + +def _reader_thread(ser: "serial.Serial") -> None: + """ + Continuously read and display incoming packets from the radio. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + while True: + try: + line = ser.readline().decode("utf-8", errors="ignore").strip() + if line: + print(f"\n[LORA RX] {line}\n> ", end="", flush=True) + except Exception: + break + + +def _parse_args() -> argparse.Namespace: + """ + Parse command line arguments for the LoRa console. + + Parameters + ---------- + None + + Returns + ------- + argparse.Namespace + Parsed arguments with the serial port and baud rate. + """ + parser = argparse.ArgumentParser(description="REYAX RYLR998 console") + parser.add_argument("--port", default="/dev/cu.usbserial-A50285BI") + parser.add_argument("--baud", type=int, default=115200) + return parser.parse_args() + + +def _open_radio(port: str, baud: int) -> "serial.Serial": + """ + Open serial connection to the REYAX transceiver. + + Parameters + ---------- + port : str + Serial device path or COM port identifier. + baud : int + Baud rate for serial communication. + + Returns + ------- + serial.Serial + Open serial interface to the radio. + """ + print(f"[*] Opening REYAX RYLR998 on {port} @ {baud}...") + try: + return serial.Serial(port, baud, timeout=0.5) + except Exception as e: + sys.exit(f"[-] Failed to open {port}: {e}") + + +def _start_radio(ser: "serial.Serial") -> None: + """ + Start listener thread and send initial AT ping. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + thread = threading.Thread(target=_reader_thread, args=(ser,), daemon=True) + thread.start() + time.sleep(0.1) + ser.write(b"AT\r\n") + + +def _print_banner() -> None: + """ + Print console connection info and operator command instructions. + + Parameters + ---------- + None + + Returns + ------- + None + """ + print("[+] Connected. Type AT commands (e.g. AT, AT+BAND?, AT+NETWORKID?).") + print("[+] Incoming airborne packets print as [LORA RX] +RCV=...") + print("[+] Press Ctrl-C or Ctrl-D to exit.\n") + + +def _console_loop(ser: "serial.Serial") -> None: + """ + Forward operator input lines to the serial transceiver. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + try: + while True: + cmd = input("> ").strip() + if cmd: + ser.write(cmd.encode("utf-8") + b"\r\n") + except (KeyboardInterrupt, EOFError): + print("\n[*] Exiting LoRa console.") + ser.close() + + +def main() -> None: + """ + Open the ground station radio and forward operator input. + + Parameters + ---------- + None + + Returns + ------- + None + """ + if serial is None: + sys.exit("pyserial required: pip install pyserial") + args = _parse_args() + ser = _open_radio(args.port, args.baud) + _start_radio(ser) + _print_banner() + _console_loop(ser) + + +if __name__ == "__main__": + main() diff --git a/WEEK06/0x0011a_cb/scripts/telemetry_monitor.py b/WEEK06/0x0011a_cb/scripts/telemetry_monitor.py new file mode 100644 index 0000000..c10a5d0 --- /dev/null +++ b/WEEK06/0x0011a_cb/scripts/telemetry_monitor.py @@ -0,0 +1,301 @@ +#!/usr/bin/env python3 +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: telemetry_monitor.py +# Desc: Real-time telemetry monitor for Operation Dark Vector. +# Created: 2026 + +""" +Real-time telemetry monitor for Operation Dark Vector. + +Reads live avionics and GPS telemetry from the FT232RL USB-to-UART ground +station bridge, parses coordinates and distance, and prints a mission status +dashboard to the terminal. +""" + +import argparse +import re +import sys +import time + +try: + import serial +except ImportError: + serial = None + + +def _format_coord(val: float, pos_c: str, neg_c: str) -> str: + """ + Format a decimal coordinate with cardinal direction. + + Parameters + ---------- + val : float + Coordinate value in degrees. + pos_c : str + Cardinal letter for positive values. + neg_c : str + Cardinal letter for negative values. + + Returns + ------- + str + Formatted coordinate string. + """ + card = pos_c if val >= 0.0 else neg_c + return f"{abs(val):.6f} deg {card}" + + +def _format_pos(lat: float, lon: float) -> str: + """ + Format combined latitude and longitude string. + + Parameters + ---------- + lat : float + Latitude coordinate. + lon : float + Longitude coordinate. + + Returns + ------- + str + Formatted dual coordinate string. + """ + lat_s = _format_coord(lat, 'N', 'S') + lon_s = _format_coord(lon, 'E', 'W') + return f"{lat_s} {lon_s}" + + +def _format_hud_rows( + cur_lat: float, + cur_lon: float, + is_rel: bool, + has_lock: bool = False +) -> list[str]: + """ + Format HUD data rows. + + Parameters + ---------- + cur_lat : float + Current UAV latitude. + cur_lon : float + Current UAV longitude. + is_rel : bool + Whether payload has released. + has_lock : bool + Whether active GNSS 3D lock has been acquired. + + Returns + ------- + list[str] + List of formatted box rows. + """ + if cur_lat == 0.0 and cur_lon == 0.0: + c_s = "0.000000 deg N 0.000000 deg E" + g_s = "SEARCHING SATELLITES" + m_s = "MOTOR STOPPED [WAITING FOR 3D LOCK]" + else: + c_s = _format_pos(cur_lat, cur_lon) + g_s = "ACTIVE 3D LOCK" if has_lock else "SEARCHING SATELLITES" + m_s = "ACTIVE PROPULSION [SERVO SPINNING]" if has_lock else "MOTOR STOPPED [WAITING FOR 3D LOCK]" + return [ + f"| CURRENT POSITION : {c_s:<44} |", + f"| GNSS SUBSYSTEM : {g_s:<44} |", + f"| PROPULSION MOTOR : {m_s:<44} |" + ] + + +def _print_box(title: str, link: str, rows: list[str]) -> None: + """ + Print framed ASCII box. + + Parameters + ---------- + title : str + Box title line. + link : str + Sub-header line. + rows : list[str] + Body content rows. + + Returns + ------- + None + """ + hdr = f"+{'-' * 65}+" + print(hdr) + print(title) + print(link) + print(hdr) + for r in rows: + print(r) + print(hdr + "\n", flush=True) + + +def _print_hud( + cur_lat: float, + cur_lon: float, + is_released: bool, + has_lock: bool = False +) -> None: + """ + Display the 67-character telemetry mission HUD. + + Parameters + ---------- + cur_lat : float + Current UAV latitude. + cur_lon : float + Current UAV longitude. + is_released : bool + Whether payload solenoid has been energized. + has_lock : bool + Whether active GNSS 3D lock has been acquired. + + Returns + ------- + None + """ + rows = _format_hud_rows(cur_lat, cur_lon, is_released, has_lock) + title = f"|{'DARK VECTOR TELEMETRY CONSOLE':^65}|" + status = f"{'STATUS: ONLINE':>20}" + link = f"| LINK: FT232RL / RYLR998 LORA GROUND STATION{status} |" + _print_box(title, link, rows) + + +def _run_demo() -> None: + """ + Execute simulation of drone telemetry stream. + + Parameters + ---------- + None + + Returns + ------- + None + """ + print("[*] Running simulated ground station telemetry stream...\n") + _print_hud(0.0, 0.0, False, False) + time.sleep(1.0) + _print_hud(38.840280, -77.428890, False, True) + time.sleep(1.0) + _print_hud(38.861110, -77.439585, False, True) + time.sleep(1.0) + _print_hud(38.881940, -77.450280, True, True) + + +def _process_line( + line: str, + coords: dict[str, any] +) -> bool: + """ + Parse a single line of serial telemetry using regex. + + Parameters + ---------- + line : str + Raw serial string. + coords : dict[str, any] + State dictionary of coordinates. + + Returns + ------- + bool + True if telemetry data was updated, False otherwise. + """ + updated = False + m_cur = re.search(r"CURRENT LAT:\s*([-+]?\d*\.?\d+).*?LON:\s*([-+]?\d*\.?\d+)", line) + if m_cur: + coords["cur_lat"] = float(m_cur.group(1)) + coords["cur_lon"] = float(m_cur.group(2)) + coords["has_lock"] = True + updated = True + if "PAYLOAD RELEASED" in line: + coords["released"] = 1.0 + updated = True + return updated + + +def _monitor_serial(port: str, baud: int) -> None: + """ + Monitor serial stream from FT232RL ground station. + + Parameters + ---------- + port : str + Serial device path. + baud : int + Baud rate. + + Returns + ------- + None + """ + if serial is None: + sys.exit("pyserial required: pip install pyserial") + coords = { + "cur_lat": 0.0, + "cur_lon": 0.0, + "released": 0.0, + "has_lock": False + } + with serial.Serial(port, baud, timeout=1.0) as ser: + while True: + raw = ser.readline().decode("utf-8", errors="ignore").strip() + if raw: + _process_line(raw, coords) + rel = coords["released"] > 0.5 + _print_hud(coords["cur_lat"], coords["cur_lon"], rel, coords["has_lock"]) + + +def main() -> None: + """ + Parse arguments and start telemetry monitor. + + Parameters + ---------- + None + + Returns + ------- + None + """ + parser = argparse.ArgumentParser(description="Dark Vector Telemetry") + parser.add_argument("--port", default="/dev/tty.usbserial-0001") + parser.add_argument("--baud", type=int, default=115200) + parser.add_argument("--demo", action="store_true") + args = parser.parse_args() + if args.demo: + _run_demo() + return + _monitor_serial(args.port, args.baud) + + +if __name__ == "__main__": + main() diff --git a/WEEK06/0x0014_static-variables/.gitignore b/WEEK06/0x0014_static-variables/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK06/0x0014_static-variables/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK06/0x0014_static-variables/.vscode/c_cpp_properties.json b/WEEK06/0x0014_static-variables/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK06/0x0014_static-variables/.vscode/cmake-kits.json b/WEEK06/0x0014_static-variables/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK06/0x0014_static-variables/.vscode/extensions.json b/WEEK06/0x0014_static-variables/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK06/0x0014_static-variables/.vscode/launch.json b/WEEK06/0x0014_static-variables/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK06/0x0014_static-variables/.vscode/settings.json b/WEEK06/0x0014_static-variables/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK06/0x0014_static-variables/.vscode/tasks.json b/WEEK06/0x0014_static-variables/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK06/0x0014_static-variables/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK06/0x0014_static-variables/0x0014_static-variables.c b/WEEK06/0x0014_static-variables/0x0014_static-variables.c new file mode 100644 index 0000000..bb34259 --- /dev/null +++ b/WEEK06/0x0014_static-variables/0x0014_static-variables.c @@ -0,0 +1,31 @@ +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + const uint BUTTON_GPIO = 15; + const uint LED_GPIO = 16; + bool pressed = 0; + + gpio_init(BUTTON_GPIO); + gpio_set_dir(BUTTON_GPIO, GPIO_IN); + gpio_pull_up(BUTTON_GPIO); + + gpio_init(LED_GPIO); + gpio_set_dir(LED_GPIO, GPIO_OUT); + + while (true) { + uint8_t regular_fav_num = 42; + static uint8_t static_fav_num = 42; + + printf("regular_fav_num: %d\r\n", regular_fav_num); + printf("static_fav_num: %d\r\n", static_fav_num); + + regular_fav_num++; + static_fav_num++; + + pressed = gpio_get(BUTTON_GPIO); + gpio_put(LED_GPIO, pressed ? 0 : 1); + } +} diff --git a/WEEK06/0x0014_static-variables/CMakeLists.txt b/WEEK06/0x0014_static-variables/CMakeLists.txt new file mode 100644 index 0000000..63d1f6b --- /dev/null +++ b/WEEK06/0x0014_static-variables/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0014_static-variables C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0014_static-variables 0x0014_static-variables.c ) + +pico_set_program_name(0x0014_static-variables "0x0014_static-variables") +pico_set_program_version(0x0014_static-variables "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0014_static-variables 1) +pico_enable_stdio_usb(0x0014_static-variables 0) + +# Add the standard library to the build +target_link_libraries(0x0014_static-variables + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0014_static-variables PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0014_static-variables) + diff --git a/WEEK06/0x0014_static-variables/build/0x0014_static-variables.bin b/WEEK06/0x0014_static-variables/build/0x0014_static-variables.bin new file mode 100755 index 0000000..e060bf2 Binary files /dev/null and b/WEEK06/0x0014_static-variables/build/0x0014_static-variables.bin differ diff --git a/WEEK06/0x0014_static-variables/build/0x0014_static-variables.dis b/WEEK06/0x0014_static-variables/build/0x0014_static-variables.dis new file mode 100644 index 0000000..db1fb05 --- /dev/null +++ b/WEEK06/0x0014_static-variables/build/0x0014_static-variables.dis @@ -0,0 +1,5807 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0014_static-variables/build/0x0014_static-variables.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000355c 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001d8 10003560 10003560 00004560 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003738 10003738 00004738 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003740 10003740 00004740 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005c9c 2**0 + CONTENTS + 6 .data 0000051c 20000110 1000376c 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005c9c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000228 20000630 10003c88 00006630 2**3 + ALLOC + 10 .heap 00000800 20000858 10003c88 00006858 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005c9c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005c9c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003c88 10003c88 00005c88 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005c9c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00005cd0 2**0 + CONTENTS, READONLY + 17 .debug_info 00020e3a 00000000 00000000 00005d15 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005736 00000000 00000000 00026b4f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 000100be 00000000 00000000 0002c285 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000be8 00000000 00000000 0003c348 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00003058 00000000 00000000 0003cf30 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00015c3e 00000000 00000000 0003ff88 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 000059ce 00000000 00000000 00055bc6 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f38 00000000 00000000 0005b594 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002be 00000000 00000000 0005d4cc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0014_static-variables/build/0x0014_static-variables.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003740 .word 0x10003740 +1000012c: 1000376c .word 0x1000376c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003b50 .word 0x00003b50 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 1000376c .word 0x1000376c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003c88 .word 0x10003c88 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003c88 .word 0x10003c88 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000858 .word 0x20000858 +100001d8: 10002dc5 .word 0x10002dc5 +100001dc: 10000235 .word 0x10000235 +100001e0: 10002dbd .word 0x10002dbd + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 1000355c .word 0x1000355c + +10000234
: +10000234: b508 push {r3, lr} +10000236: f002 feed bl 10003014 +1000023a: 200f movs r0, #15 +1000023c: f000 f860 bl 10000300 +10000240: 200f movs r0, #15 +10000242: f04f 0300 mov.w r3, #0 +10000246: ec43 0044 gpioc_bit_oe_put r0, r3 +1000024a: 2200 movs r2, #0 +1000024c: 2101 movs r1, #1 +1000024e: f000 f843 bl 100002d8 +10000252: 2010 movs r0, #16 +10000254: f000 f854 bl 10000300 +10000258: 2310 movs r3, #16 +1000025a: f04f 0201 mov.w r2, #1 +1000025e: ec42 3044 gpioc_bit_oe_put r3, r2 +10000262: 4c0b ldr r4, [pc, #44] @ (10000290 ) +10000264: 212a movs r1, #42 @ 0x2a +10000266: 480b ldr r0, [pc, #44] @ (10000294 ) +10000268: f002 ff9c bl 100031a4 <__wrap_printf> +1000026c: 7821 ldrb r1, [r4, #0] +1000026e: 480a ldr r0, [pc, #40] @ (10000298 ) +10000270: f002 ff98 bl 100031a4 <__wrap_printf> +10000274: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +10000278: 7823 ldrb r3, [r4, #0] +1000027a: 2210 movs r2, #16 +1000027c: 3301 adds r3, #1 +1000027e: 7023 strb r3, [r4, #0] +10000280: 684b ldr r3, [r1, #4] +10000282: f3c3 33c0 ubfx r3, r3, #15, #1 +10000286: f083 0301 eor.w r3, r3, #1 +1000028a: ec43 2040 gpioc_bit_out_put r2, r3 +1000028e: e7e9 b.n 10000264 +10000290: 200005a8 .word 0x200005a8 +10000294: 10003560 .word 0x10003560 +10000298: 10003578 .word 0x10003578 + +1000029c : +1000029c: b410 push {r4} +1000029e: f44f 7480 mov.w r4, #256 @ 0x100 +100002a2: 4b0c ldr r3, [pc, #48] @ (100002d4 ) +100002a4: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100002a8: eb03 0380 add.w r3, r3, r0, lsl #2 +100002ac: 00c0 lsls r0, r0, #3 +100002ae: f082 0240 eor.w r2, r2, #64 @ 0x40 +100002b2: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100002b6: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +100002ba: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100002be: f500 3020 add.w r0, r0, #163840 @ 0x28000 +100002c2: f503 5340 add.w r3, r3, #12288 @ 0x3000 +100002c6: f8cc 2000 str.w r2, [ip] +100002ca: 6041 str r1, [r0, #4] +100002cc: 601c str r4, [r3, #0] +100002ce: f85d 4b04 ldr.w r4, [sp], #4 +100002d2: 4770 bx lr +100002d4: 40038004 .word 0x40038004 + +100002d8 : +100002d8: b410 push {r4} +100002da: 4c08 ldr r4, [pc, #32] @ (100002fc ) +100002dc: 00c9 lsls r1, r1, #3 +100002de: ea41 0182 orr.w r1, r1, r2, lsl #2 +100002e2: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100002e6: eb04 0380 add.w r3, r4, r0, lsl #2 +100002ea: 4051 eors r1, r2 +100002ec: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100002f0: f001 010c and.w r1, r1, #12 +100002f4: f85d 4b04 ldr.w r4, [sp], #4 +100002f8: 6019 str r1, [r3, #0] +100002fa: 4770 bx lr +100002fc: 40038004 .word 0x40038004 + +10000300 : +10000300: b430 push {r4, r5} +10000302: f04f 0300 mov.w r3, #0 +10000306: ec43 0044 gpioc_bit_oe_put r0, r3 +1000030a: ec43 0040 gpioc_bit_out_put r0, r3 +1000030e: 2505 movs r5, #5 +10000310: f44f 7480 mov.w r4, #256 @ 0x100 +10000314: 4b0b ldr r3, [pc, #44] @ (10000344 ) +10000316: 00c2 lsls r2, r0, #3 +10000318: f853 1020 ldr.w r1, [r3, r0, lsl #2] +1000031c: eb03 0080 add.w r0, r3, r0, lsl #2 +10000320: f081 0140 eor.w r1, r1, #64 @ 0x40 +10000324: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +10000328: f503 3320 add.w r3, r3, #163840 @ 0x28000 +1000032c: f001 02c0 and.w r2, r1, #192 @ 0xc0 +10000330: f500 5180 add.w r1, r0, #4096 @ 0x1000 +10000334: f500 5040 add.w r0, r0, #12288 @ 0x3000 +10000338: 600a str r2, [r1, #0] +1000033a: 605d str r5, [r3, #4] +1000033c: 6004 str r4, [r0, #0] +1000033e: bc30 pop {r4, r5} +10000340: 4770 bx lr +10000342: bf00 nop +10000344: 40038004 .word 0x40038004 + +10000348 : +10000348: b40f push {r0, r1, r2, r3} +1000034a: b500 push {lr} +1000034c: b083 sub sp, #12 +1000034e: 9c04 ldr r4, [sp, #16] +10000350: 4807 ldr r0, [pc, #28] @ (10000370 ) +10000352: f002 fea7 bl 100030a4 <__wrap_puts> +10000356: b13c cbz r4, 10000368 +10000358: a905 add r1, sp, #20 +1000035a: 4620 mov r0, r4 +1000035c: 9101 str r1, [sp, #4] +1000035e: f002 fd13 bl 10002d88 +10000362: 4804 ldr r0, [pc, #16] @ (10000374 ) +10000364: f002 fe9e bl 100030a4 <__wrap_puts> +10000368: 2001 movs r0, #1 +1000036a: f002 fd25 bl 10002db8 <_exit> +1000036e: bf00 nop +10000370: 10003590 .word 0x10003590 +10000374: 100035a0 .word 0x100035a0 + +10000378 : +10000378: b570 push {r4, r5, r6, lr} +1000037a: 4686 mov lr, r0 +1000037c: f3ef 8510 mrs r5, PRIMASK +10000380: b672 cpsid i +10000382: 4c12 ldr r4, [pc, #72] @ (100003cc ) +10000384: e8d4 6fcf ldaexb r6, [r4] +10000388: 2001 movs r0, #1 +1000038a: 2e00 cmp r6, #0 +1000038c: d1fa bne.n 10000384 +1000038e: e8c4 0f46 strexb r6, r0, [r4] +10000392: 2e00 cmp r6, #0 +10000394: d1f6 bne.n 10000384 +10000396: f3bf 8f5f dmb sy +1000039a: f04f 0c01 mov.w ip, #1 +1000039e: 08c8 lsrs r0, r1, #3 +100003a0: f001 0307 and.w r3, r1, #7 +100003a4: fa0c f303 lsl.w r3, ip, r3 +100003a8: f81e c000 ldrb.w ip, [lr, r0] +100003ac: ea1c 0603 ands.w r6, ip, r3 +100003b0: d108 bne.n 100003c4 +100003b2: ea4c 0c03 orr.w ip, ip, r3 +100003b6: f80e c000 strb.w ip, [lr, r0] +100003ba: e8c4 6f8f stlb r6, [r4] +100003be: f385 8810 msr PRIMASK, r5 +100003c2: bd70 pop {r4, r5, r6, pc} +100003c4: 4610 mov r0, r2 +100003c6: f7ff ffbf bl 10000348 +100003ca: bf00 nop +100003cc: 200007bb .word 0x200007bb + +100003d0 : +100003d0: 4a04 ldr r2, [pc, #16] @ (100003e4 ) +100003d2: 7810 ldrb r0, [r2, #0] +100003d4: 1c43 adds r3, r0, #1 +100003d6: b2db uxtb r3, r3 +100003d8: 2b18 cmp r3, #24 +100003da: bf28 it cs +100003dc: 2310 movcs r3, #16 +100003de: 7013 strb r3, [r2, #0] +100003e0: 4770 bx lr +100003e2: bf00 nop +100003e4: 200005a9 .word 0x200005a9 + +100003e8 : +100003e8: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100003ec: 6893 ldr r3, [r2, #8] +100003ee: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100003f2: 6093 str r3, [r2, #8] +100003f4: 4770 bx lr +100003f6: bf00 nop + +100003f8 : +100003f8: 2100 movs r1, #0 +100003fa: 4b04 ldr r3, [pc, #16] @ (1000040c ) +100003fc: f103 0220 add.w r2, r3, #32 +10000400: e8c3 1f8f stlb r1, [r3] +10000404: 3301 adds r3, #1 +10000406: 4293 cmp r3, r2 +10000408: d1fa bne.n 10000400 +1000040a: 4770 bx lr +1000040c: 200007b0 .word 0x200007b0 + +10000410 : +10000410: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000414: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000418: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +1000041c: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000420: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000424: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000428: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +1000042c: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000430: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000434: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000438: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000043c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000440: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000444: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000448: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000044c: b662 cpsie i +1000044e: 4770 bx lr + +10000450 : +10000450: 2301 movs r3, #1 +10000452: f000 021f and.w r2, r0, #31 +10000456: 4093 lsls r3, r2 +10000458: 0940 lsrs r0, r0, #5 +1000045a: b141 cbz r1, 1000046e +1000045c: 0080 lsls r0, r0, #2 +1000045e: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000462: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000466: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000046a: 6003 str r3, [r0, #0] +1000046c: 4770 bx lr +1000046e: 4a02 ldr r2, [pc, #8] @ (10000478 ) +10000470: 3020 adds r0, #32 +10000472: f842 3020 str.w r3, [r2, r0, lsl #2] +10000476: 4770 bx lr +10000478: e000e100 .word 0xe000e100 + +1000047c : +1000047c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000047e: 460d mov r5, r1 +10000480: f3ef 8710 mrs r7, PRIMASK +10000484: b672 cpsid i +10000486: 4e12 ldr r6, [pc, #72] @ (100004d0 ) +10000488: e8d6 2fcf ldaexb r2, [r6] +1000048c: 2301 movs r3, #1 +1000048e: 2a00 cmp r2, #0 +10000490: d1fa bne.n 10000488 +10000492: e8c6 3f42 strexb r2, r3, [r6] +10000496: 2a00 cmp r2, #0 +10000498: d1f6 bne.n 10000488 +1000049a: f3bf 8f5f dmb sy +1000049e: 4b0d ldr r3, [pc, #52] @ (100004d4 ) +100004a0: f100 0410 add.w r4, r0, #16 +100004a4: 689b ldr r3, [r3, #8] +100004a6: 4a0c ldr r2, [pc, #48] @ (100004d8 ) +100004a8: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100004ac: 4293 cmp r3, r2 +100004ae: d003 beq.n 100004b8 +100004b0: 4299 cmp r1, r3 +100004b2: d001 beq.n 100004b8 +100004b4: f000 fe8c bl 100011d0 +100004b8: 4b06 ldr r3, [pc, #24] @ (100004d4 ) +100004ba: 689b ldr r3, [r3, #8] +100004bc: f843 5024 str.w r5, [r3, r4, lsl #2] +100004c0: f3bf 8f5f dmb sy +100004c4: 2300 movs r3, #0 +100004c6: e8c6 3f8f stlb r3, [r6] +100004ca: f387 8810 msr PRIMASK, r7 +100004ce: bdf8 pop {r3, r4, r5, r6, r7, pc} +100004d0: 200007b9 .word 0x200007b9 +100004d4: e000ed00 .word 0xe000ed00 +100004d8: 10000111 .word 0x10000111 + +100004dc : +100004dc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100004e0: b083 sub sp, #12 +100004e2: f3ef 8a10 mrs sl, PRIMASK +100004e6: b672 cpsid i +100004e8: 4e71 ldr r6, [pc, #452] @ (100006b0 ) +100004ea: e8d6 2fcf ldaexb r2, [r6] +100004ee: 2301 movs r3, #1 +100004f0: 2a00 cmp r2, #0 +100004f2: d1fa bne.n 100004ea +100004f4: e8c6 3f42 strexb r2, r3, [r6] +100004f8: 2a00 cmp r2, #0 +100004fa: d1f6 bne.n 100004ea +100004fc: f3bf 8f5f dmb sy +10000500: 4b6c ldr r3, [pc, #432] @ (100006b4 ) +10000502: f100 0810 add.w r8, r0, #16 +10000506: 689b ldr r3, [r3, #8] +10000508: 4a6b ldr r2, [pc, #428] @ (100006b8 ) +1000050a: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000050e: 4295 cmp r5, r2 +10000510: d045 beq.n 1000059e +10000512: 428d cmp r5, r1 +10000514: 460c mov r4, r1 +10000516: d050 beq.n 100005ba +10000518: 4f68 ldr r7, [pc, #416] @ (100006bc ) +1000051a: 1beb subs r3, r5, r7 +1000051c: 2b2f cmp r3, #47 @ 0x2f +1000051e: d83e bhi.n 1000059e +10000520: 2101 movs r1, #1 +10000522: ea4f 1950 mov.w r9, r0, lsr #5 +10000526: ea4f 0989 mov.w r9, r9, lsl #2 +1000052a: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000052e: f509 4961 add.w r9, r9, #57600 @ 0xe100 +10000532: f000 031f and.w r3, r0, #31 +10000536: fa01 f003 lsl.w r0, r1, r3 +1000053a: f8d9 3000 ldr.w r3, [r9] +1000053e: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000542: ea00 0b03 and.w fp, r0, r3 +10000546: f3bf 8f5f dmb sy +1000054a: f3ef 8105 mrs r1, IPSR +1000054e: b2c9 uxtb r1, r1 +10000550: 2900 cmp r1, #0 +10000552: d034 beq.n 100005be +10000554: 4588 cmp r8, r1 +10000556: d005 beq.n 10000564 +10000558: e9cd 1000 strd r1, r0, [sp] +1000055c: f000 fe38 bl 100011d0 +10000560: e9dd 1000 ldrd r1, r0, [sp] +10000564: f025 0e01 bic.w lr, r5, #1 +10000568: f8de c008 ldr.w ip, [lr, #8] +1000056c: 4564 cmp r4, ip +1000056e: d105 bne.n 1000057c +10000570: e089 b.n 10000686 +10000572: f8d3 c008 ldr.w ip, [r3, #8] +10000576: 4564 cmp r4, ip +10000578: d031 beq.n 100005de +1000057a: 469e mov lr, r3 +1000057c: f99e 2006 ldrsb.w r2, [lr, #6] +10000580: eb02 0342 add.w r3, r2, r2, lsl #1 +10000584: 2a00 cmp r2, #0 +10000586: eb07 0383 add.w r3, r7, r3, lsl #2 +1000058a: daf2 bge.n 10000572 +1000058c: 4564 cmp r4, ip +1000058e: d061 beq.n 10000654 +10000590: f1bb 0f00 cmp.w fp, #0 +10000594: d020 beq.n 100005d8 +10000596: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +1000059a: f8c9 0000 str.w r0, [r9] +1000059e: 4b45 ldr r3, [pc, #276] @ (100006b4 ) +100005a0: 689b ldr r3, [r3, #8] +100005a2: f843 5028 str.w r5, [r3, r8, lsl #2] +100005a6: f3bf 8f5f dmb sy +100005aa: 2300 movs r3, #0 +100005ac: e8c6 3f8f stlb r3, [r6] +100005b0: f38a 8810 msr PRIMASK, sl +100005b4: b003 add sp, #12 +100005b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100005ba: 4615 mov r5, r2 +100005bc: e7ef b.n 1000059e +100005be: f025 0e01 bic.w lr, r5, #1 +100005c2: f8de c008 ldr.w ip, [lr, #8] +100005c6: 4564 cmp r4, ip +100005c8: d1d8 bne.n 1000057c +100005ca: f99e 4006 ldrsb.w r4, [lr, #6] +100005ce: 4673 mov r3, lr +100005d0: 2c00 cmp r4, #0 +100005d2: da08 bge.n 100005e6 +100005d4: 4615 mov r5, r2 +100005d6: e046 b.n 10000666 +100005d8: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100005dc: e7df b.n 1000059e +100005de: f993 4006 ldrsb.w r4, [r3, #6] +100005e2: 2c00 cmp r4, #0 +100005e4: db37 blt.n 10000656 +100005e6: eb04 0c44 add.w ip, r4, r4, lsl #1 +100005ea: eb07 0c8c add.w ip, r7, ip, lsl #2 +100005ee: f89c 1007 ldrb.w r1, [ip, #7] +100005f2: f8dc 2008 ldr.w r2, [ip, #8] +100005f6: 71d9 strb r1, [r3, #7] +100005f8: 609a str r2, [r3, #8] +100005fa: f99c 2006 ldrsb.w r2, [ip, #6] +100005fe: 0061 lsls r1, r4, #1 +10000600: 2a00 cmp r2, #0 +10000602: 719a strb r2, [r3, #6] +10000604: db3d blt.n 10000682 +10000606: f8bc e004 ldrh.w lr, [ip, #4] +1000060a: ea5f 5e4e movs.w lr, lr, lsl #21 +1000060e: d505 bpl.n 1000061c +10000610: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000614: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000618: f10e 0e1f add.w lr, lr, #31 +1000061c: f06f 0c07 mvn.w ip, #7 +10000620: 190a adds r2, r1, r4 +10000622: ea4f 5e6e mov.w lr, lr, asr #21 +10000626: 0092 lsls r2, r2, #2 +10000628: eb02 024e add.w r2, r2, lr, lsl #1 +1000062c: 3208 adds r2, #8 +1000062e: 443a add r2, r7 +10000630: ebac 0c03 sub.w ip, ip, r3 +10000634: 4462 add r2, ip +10000636: f3c2 024a ubfx r2, r2, #1, #11 +1000063a: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000063e: ea6f 42d2 mvn.w r2, r2, lsr #19 +10000642: 809a strh r2, [r3, #4] +10000644: 4b1e ldr r3, [pc, #120] @ (100006c0 ) +10000646: 4421 add r1, r4 +10000648: 781a ldrb r2, [r3, #0] +1000064a: eb07 0181 add.w r1, r7, r1, lsl #2 +1000064e: 701c strb r4, [r3, #0] +10000650: 718a strb r2, [r1, #6] +10000652: e79d b.n 10000590 +10000654: 4673 mov r3, lr +10000656: b9d9 cbnz r1, 10000690 +10000658: 22ff movs r2, #255 @ 0xff +1000065a: f88e 2006 strb.w r2, [lr, #6] +1000065e: f64b 5201 movw r2, #48385 @ 0xbd01 +10000662: f8ae 2004 strh.w r2, [lr, #4] +10000666: 4c16 ldr r4, [pc, #88] @ (100006c0 ) +10000668: f64a 22aa movw r2, #43690 @ 0xaaaa +1000066c: f894 c000 ldrb.w ip, [r4] +10000670: 4619 mov r1, r3 +10000672: 1bc9 subs r1, r1, r7 +10000674: 4149 adcs r1, r1 +10000676: 434a muls r2, r1 +10000678: 0d12 lsrs r2, r2, #20 +1000067a: f883 c006 strb.w ip, [r3, #6] +1000067e: 7022 strb r2, [r4, #0] +10000680: e786 b.n 10000590 +10000682: 4a10 ldr r2, [pc, #64] @ (100006c4 ) +10000684: e7dd b.n 10000642 +10000686: f99e 4006 ldrsb.w r4, [lr, #6] +1000068a: 4673 mov r3, lr +1000068c: 2c00 cmp r4, #0 +1000068e: daaa bge.n 100005e6 +10000690: 4a0d ldr r2, [pc, #52] @ (100006c8 ) +10000692: 4c0e ldr r4, [pc, #56] @ (100006cc ) +10000694: 1ad2 subs r2, r2, r3 +10000696: 3a08 subs r2, #8 +10000698: f3c2 310a ubfx r1, r2, #12, #11 +1000069c: ea6f 5101 mvn.w r1, r1, lsl #20 +100006a0: ea6f 5111 mvn.w r1, r1, lsr #20 +100006a4: ea44 0252 orr.w r2, r4, r2, lsr #1 +100006a8: 80da strh r2, [r3, #6] +100006aa: 8099 strh r1, [r3, #4] +100006ac: e770 b.n 10000590 +100006ae: bf00 nop +100006b0: 200007b9 .word 0x200007b9 +100006b4: e000ed00 .word 0xe000ed00 +100006b8: 10000111 .word 0x10000111 +100006bc: 200005ac .word 0x200005ac +100006c0: 20000854 .word 0x20000854 +100006c4: ffffbd01 .word 0xffffbd01 +100006c8: 200005e6 .word 0x200005e6 +100006cc: fffff800 .word 0xfffff800 + +100006d0 : +100006d0: b5f0 push {r4, r5, r6, r7, lr} +100006d2: f3ef 8505 mrs r5, IPSR +100006d6: b2ed uxtb r5, r5 +100006d8: f3ef 8c10 mrs ip, PRIMASK +100006dc: b672 cpsid i +100006de: 4926 ldr r1, [pc, #152] @ (10000778 ) +100006e0: e8d1 2fcf ldaexb r2, [r1] +100006e4: 2301 movs r3, #1 +100006e6: 2a00 cmp r2, #0 +100006e8: d1fa bne.n 100006e0 +100006ea: e8c1 3f42 strexb r2, r3, [r1] +100006ee: 2a00 cmp r2, #0 +100006f0: d1f6 bne.n 100006e0 +100006f2: f3bf 8f5f dmb sy +100006f6: 4e21 ldr r6, [pc, #132] @ (1000077c ) +100006f8: f040 0e01 orr.w lr, r0, #1 +100006fc: 68b4 ldr r4, [r6, #8] +100006fe: f64a 23aa movw r3, #43690 @ 0xaaaa +10000702: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000706: 4a1e ldr r2, [pc, #120] @ (10000780 ) +10000708: 4604 mov r4, r0 +1000070a: 1aa4 subs r4, r4, r2 +1000070c: 4164 adcs r4, r4 +1000070e: 4363 muls r3, r4 +10000710: 0d1b lsrs r3, r3, #20 +10000712: 4577 cmp r7, lr +10000714: b25b sxtb r3, r3 +10000716: d01b beq.n 10000750 +10000718: f992 4006 ldrsb.w r4, [r2, #6] +1000071c: 429c cmp r4, r3 +1000071e: d01c beq.n 1000075a +10000720: f992 4012 ldrsb.w r4, [r2, #18] +10000724: 429c cmp r4, r3 +10000726: d023 beq.n 10000770 +10000728: f992 401e ldrsb.w r4, [r2, #30] +1000072c: 429c cmp r4, r3 +1000072e: d021 beq.n 10000774 +10000730: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000734: 429c cmp r4, r3 +10000736: bf08 it eq +10000738: 2403 moveq r4, #3 +1000073a: d00f beq.n 1000075c +1000073c: 4a11 ldr r2, [pc, #68] @ (10000784 ) +1000073e: 2400 movs r4, #0 +10000740: 7815 ldrb r5, [r2, #0] +10000742: 7013 strb r3, [r2, #0] +10000744: 7185 strb r5, [r0, #6] +10000746: e8c1 4f8f stlb r4, [r1] +1000074a: f38c 8810 msr PRIMASK, ip +1000074e: bdf0 pop {r4, r5, r6, r7, pc} +10000750: 68b2 ldr r2, [r6, #8] +10000752: 4c0d ldr r4, [pc, #52] @ (10000788 ) +10000754: f842 4025 str.w r4, [r2, r5, lsl #2] +10000758: e7f0 b.n 1000073c +1000075a: 2400 movs r4, #0 +1000075c: eb04 0444 add.w r4, r4, r4, lsl #1 +10000760: eb02 0284 add.w r2, r2, r4, lsl #2 +10000764: 24ff movs r4, #255 @ 0xff +10000766: 7194 strb r4, [r2, #6] +10000768: f64b 5401 movw r4, #48385 @ 0xbd01 +1000076c: 8094 strh r4, [r2, #4] +1000076e: e7e5 b.n 1000073c +10000770: 2401 movs r4, #1 +10000772: e7f3 b.n 1000075c +10000774: 2402 movs r4, #2 +10000776: e7f1 b.n 1000075c +10000778: 200007b9 .word 0x200007b9 +1000077c: e000ed00 .word 0xe000ed00 +10000780: 200005ac .word 0x200005ac +10000784: 20000854 .word 0x20000854 +10000788: 10000111 .word 0x10000111 + +1000078c : +1000078c: 4b01 ldr r3, [pc, #4] @ (10000794 ) +1000078e: 440b add r3, r1 +10000790: 6003 str r3, [r0, #0] +10000792: 4770 bx lr +10000794: 200007b0 .word 0x200007b0 + +10000798 : +10000798: b570 push {r4, r5, r6, lr} +1000079a: 4c10 ldr r4, [pc, #64] @ (100007dc ) +1000079c: 4d10 ldr r5, [pc, #64] @ (100007e0 ) +1000079e: 42ac cmp r4, r5 +100007a0: d20e bcs.n 100007c0 +100007a2: 26ff movs r6, #255 @ 0xff +100007a4: 6823 ldr r3, [r4, #0] +100007a6: b163 cbz r3, 100007c2 +100007a8: f7ff fe12 bl 100003d0 +100007ac: 4601 mov r1, r0 +100007ae: 4620 mov r0, r4 +100007b0: f7ff ffec bl 1000078c +100007b4: 80a6 strh r6, [r4, #4] +100007b6: f3bf 8f5f dmb sy +100007ba: 3408 adds r4, #8 +100007bc: 42ac cmp r4, r5 +100007be: d3f1 bcc.n 100007a4 +100007c0: bd70 pop {r4, r5, r6, pc} +100007c2: f7ff fe05 bl 100003d0 +100007c6: 4601 mov r1, r0 +100007c8: 4620 mov r0, r4 +100007ca: f7ff ffdf bl 1000078c +100007ce: 7126 strb r6, [r4, #4] +100007d0: f3bf 8f5f dmb sy +100007d4: 3408 adds r4, #8 +100007d6: 42ac cmp r4, r5 +100007d8: d3e4 bcc.n 100007a4 +100007da: bd70 pop {r4, r5, r6, pc} +100007dc: 20000624 .word 0x20000624 +100007e0: 2000062c .word 0x2000062c + +100007e4 : +100007e4: 4b0d ldr r3, [pc, #52] @ (1000081c ) +100007e6: 681a ldr r2, [r3, #0] +100007e8: f3ef 8110 mrs r1, PRIMASK +100007ec: b672 cpsid i +100007ee: e8d2 cfcf ldaexb ip, [r2] +100007f2: 2001 movs r0, #1 +100007f4: f1bc 0f00 cmp.w ip, #0 +100007f8: d1f9 bne.n 100007ee +100007fa: e8c2 0f4c strexb ip, r0, [r2] +100007fe: f1bc 0f00 cmp.w ip, #0 +10000802: d1f4 bne.n 100007ee +10000804: f3bf 8f5f dmb sy +10000808: 2200 movs r2, #0 +1000080a: 681b ldr r3, [r3, #0] +1000080c: e8c3 2f8f stlb r2, [r3] +10000810: f381 8810 msr PRIMASK, r1 +10000814: bf40 sev +10000816: 2000 movs r0, #0 +10000818: 2100 movs r1, #0 +1000081a: 4770 bx lr +1000081c: 20000848 .word 0x20000848 + +10000820 : +10000820: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000824: ed2d 8b02 vpush {d8} +10000828: b085 sub sp, #20 +1000082a: f3ef 8305 mrs r3, IPSR +1000082e: b2db uxtb r3, r3 +10000830: 3b10 subs r3, #16 +10000832: 089a lsrs r2, r3, #2 +10000834: bf18 it ne +10000836: 2201 movne r2, #1 +10000838: f04f 0101 mov.w r1, #1 +1000083c: f003 0b03 and.w fp, r3, #3 +10000840: bf18 it ne +10000842: 4daf ldrne r5, [pc, #700] @ (10000b00 ) +10000844: 4baf ldr r3, [pc, #700] @ (10000b04 ) +10000846: bf08 it eq +10000848: 4daf ldreq r5, [pc, #700] @ (10000b08 ) +1000084a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000084e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000852: fa01 f20b lsl.w r2, r1, fp +10000856: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000085a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000af8 +1000085e: 9201 str r2, [sp, #4] +10000860: 605a str r2, [r3, #4] +10000862: e02f b.n 100008c4 +10000864: 88b3 ldrh r3, [r6, #4] +10000866: 041c lsls r4, r3, #16 +10000868: f140 8093 bpl.w 10000992 +1000086c: 79b3 ldrb r3, [r6, #6] +1000086e: 2b00 cmp r3, #0 +10000870: f040 80dd bne.w 10000a2e +10000874: f9b6 2008 ldrsh.w r2, [r6, #8] +10000878: 2a00 cmp r2, #0 +1000087a: f2c0 811e blt.w 10000aba +1000087e: 6973 ldr r3, [r6, #20] +10000880: eb02 0242 add.w r2, r2, r2, lsl #1 +10000884: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000888: e9d3 4702 ldrd r4, r7, [r3, #8] +1000088c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000890: bf08 it eq +10000892: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000896: d00e beq.n 100008b6 +10000898: eb05 018b add.w r1, r5, fp, lsl #2 +1000089c: 6aab ldr r3, [r5, #40] @ 0x28 +1000089e: 690a ldr r2, [r1, #16] +100008a0: 1ad2 subs r2, r2, r3 +100008a2: 1ae3 subs r3, r4, r3 +100008a4: 4293 cmp r3, r2 +100008a6: d305 bcc.n 100008b4 +100008a8: 2301 movs r3, #1 +100008aa: 6a2a ldr r2, [r5, #32] +100008ac: fa03 f30b lsl.w r3, r3, fp +100008b0: 4213 tst r3, r2 +100008b2: d100 bne.n 100008b6 +100008b4: 610c str r4, [r1, #16] +100008b6: 4628 mov r0, r5 +100008b8: f000 faca bl 10000e50 +100008bc: 42a0 cmp r0, r4 +100008be: 41b9 sbcs r1, r7 +100008c0: f2c0 80fb blt.w 10000aba +100008c4: f9b6 3008 ldrsh.w r3, [r6, #8] +100008c8: 9a01 ldr r2, [sp, #4] +100008ca: 2b00 cmp r3, #0 +100008cc: 9300 str r3, [sp, #0] +100008ce: 63ea str r2, [r5, #60] @ 0x3c +100008d0: dbc8 blt.n 10000864 +100008d2: f8d6 8014 ldr.w r8, [r6, #20] +100008d6: eb03 0943 add.w r9, r3, r3, lsl #1 +100008da: 4628 mov r0, r5 +100008dc: eb08 07c9 add.w r7, r8, r9, lsl #3 +100008e0: e9d7 4a02 ldrd r4, sl, [r7, #8] +100008e4: f000 fab4 bl 10000e50 +100008e8: 42a0 cmp r0, r4 +100008ea: eb71 010a sbcs.w r1, r1, sl +100008ee: dbb9 blt.n 10000864 +100008f0: f1ba 0f00 cmp.w sl, #0 +100008f4: f2c0 80c3 blt.w 10000a7e +100008f8: e9d7 3104 ldrd r3, r1, [r7, #16] +100008fc: 4a83 ldr r2, [pc, #524] @ (10000b0c ) +100008fe: 4293 cmp r3, r2 +10000900: f000 80ed beq.w 10000ade +10000904: 887a ldrh r2, [r7, #2] +10000906: f9b6 0008 ldrsh.w r0, [r6, #8] +1000090a: b292 uxth r2, r2 +1000090c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000910: 4798 blx r3 +10000912: 4602 mov r2, r0 +10000914: 460b mov r3, r1 +10000916: ea52 0103 orrs.w r1, r2, r3 +1000091a: f000 80b0 beq.w 10000a7e +1000091e: 2b00 cmp r3, #0 +10000920: f280 80d1 bge.w 10000ac6 +10000924: ebb4 0e02 subs.w lr, r4, r2 +10000928: eb6a 0a03 sbc.w sl, sl, r3 +1000092c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000930: e9c7 ea02 strd lr, sl, [r7, #8] +10000934: 2b00 cmp r3, #0 +10000936: db95 blt.n 10000864 +10000938: 6971 ldr r1, [r6, #20] +1000093a: eb03 0243 add.w r2, r3, r3, lsl #1 +1000093e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000942: e9d2 7002 ldrd r7, r0, [r2, #8] +10000946: 45be cmp lr, r7 +10000948: eb7a 0c00 sbcs.w ip, sl, r0 +1000094c: ea4f 0243 mov.w r2, r3, lsl #1 +10000950: db88 blt.n 10000864 +10000952: 46b4 mov ip, r6 +10000954: f82c 3f08 strh.w r3, [ip, #8]! +10000958: e006 b.n 10000968 +1000095a: eb03 0043 add.w r0, r3, r3, lsl #1 +1000095e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000962: 005a lsls r2, r3, #1 +10000964: e9d0 7002 ldrd r7, r0, [r0, #8] +10000968: 45be cmp lr, r7 +1000096a: 441a add r2, r3 +1000096c: eb7a 0000 sbcs.w r0, sl, r0 +10000970: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000974: db04 blt.n 10000980 +10000976: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +1000097a: 46a4 mov ip, r4 +1000097c: 2b00 cmp r3, #0 +1000097e: daec bge.n 1000095a +10000980: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000984: 9b00 ldr r3, [sp, #0] +10000986: f8ac 3000 strh.w r3, [ip] +1000098a: 88b3 ldrh r3, [r6, #4] +1000098c: 041c lsls r4, r3, #16 +1000098e: f53f af6d bmi.w 1000086c +10000992: 6933 ldr r3, [r6, #16] +10000994: f3ef 8210 mrs r2, PRIMASK +10000998: b672 cpsid i +1000099a: e8d3 0fcf ldaexb r0, [r3] +1000099e: 2101 movs r1, #1 +100009a0: 2800 cmp r0, #0 +100009a2: d1fa bne.n 1000099a +100009a4: e8c3 1f40 strexb r0, r1, [r3] +100009a8: 2800 cmp r0, #0 +100009aa: d1f6 bne.n 1000099a +100009ac: f3bf 8f5f dmb sy +100009b0: f64f 74ff movw r4, #65535 @ 0xffff +100009b4: 88b0 ldrh r0, [r6, #4] +100009b6: 2300 movs r3, #0 +100009b8: 6931 ldr r1, [r6, #16] +100009ba: b200 sxth r0, r0 +100009bc: 80b4 strh r4, [r6, #4] +100009be: e8c1 3f8f stlb r3, [r1] +100009c2: f382 8810 msr PRIMASK, r2 +100009c6: 4298 cmp r0, r3 +100009c8: f6ff af50 blt.w 1000086c +100009cc: 4607 mov r7, r0 +100009ce: 46a9 mov r9, r5 +100009d0: 6974 ldr r4, [r6, #20] +100009d2: f106 0808 add.w r8, r6, #8 +100009d6: eb07 0e47 add.w lr, r7, r7, lsl #1 +100009da: eb04 03ce add.w r3, r4, lr, lsl #3 +100009de: e9d3 5002 ldrd r5, r0, [r3, #8] +100009e2: f9b6 3008 ldrsh.w r3, [r6, #8] +100009e6: 46c4 mov ip, r8 +100009e8: 2b00 cmp r3, #0 +100009ea: db13 blt.n 10000a14 +100009ec: 46b2 mov sl, r6 +100009ee: 9700 str r7, [sp, #0] +100009f0: e004 b.n 100009fc +100009f2: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +100009f6: 4694 mov ip, r2 +100009f8: 2b00 cmp r3, #0 +100009fa: db09 blt.n 10000a10 +100009fc: eb03 0643 add.w r6, r3, r3, lsl #1 +10000a00: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000a04: e9d2 7102 ldrd r7, r1, [r2, #8] +10000a08: 42bd cmp r5, r7 +10000a0a: eb70 0101 sbcs.w r1, r0, r1 +10000a0e: daf0 bge.n 100009f2 +10000a10: 4656 mov r6, sl +10000a12: 9f00 ldr r7, [sp, #0] +10000a14: f8ac 7000 strh.w r7, [ip] +10000a18: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000a1c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000a20: 2f00 cmp r7, #0 +10000a22: dad8 bge.n 100009d6 +10000a24: 79b3 ldrb r3, [r6, #6] +10000a26: 464d mov r5, r9 +10000a28: 2b00 cmp r3, #0 +10000a2a: f43f af23 beq.w 10000874 +10000a2e: 2300 movs r3, #0 +10000a30: 71b3 strb r3, [r6, #6] +10000a32: f9b6 3008 ldrsh.w r3, [r6, #8] +10000a36: f106 0808 add.w r8, r6, #8 +10000a3a: 1c58 adds r0, r3, #1 +10000a3c: d03d beq.n 10000aba +10000a3e: 461a mov r2, r3 +10000a40: 6977 ldr r7, [r6, #20] +10000a42: e003 b.n 10000a4c +10000a44: 4680 mov r8, r0 +10000a46: 1c59 adds r1, r3, #1 +10000a48: f43f af16 beq.w 10000878 +10000a4c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000a50: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000a54: f8b0 c002 ldrh.w ip, [r0, #2] +10000a58: 461c mov r4, r3 +10000a5a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000a5e: 469e mov lr, r3 +10000a60: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000a64: d0ee beq.n 10000a44 +10000a66: 4294 cmp r4, r2 +10000a68: ed80 8b02 vstr d8, [r0, #8] +10000a6c: d005 beq.n 10000a7a +10000a6e: f8a8 3000 strh.w r3, [r8] +10000a72: 8932 ldrh r2, [r6, #8] +10000a74: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000a78: 8134 strh r4, [r6, #8] +10000a7a: 4672 mov r2, lr +10000a7c: e7e3 b.n 10000a46 +10000a7e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000a82: 8133 strh r3, [r6, #8] +10000a84: 6933 ldr r3, [r6, #16] +10000a86: f3ef 8210 mrs r2, PRIMASK +10000a8a: b672 cpsid i +10000a8c: e8d3 0fcf ldaexb r0, [r3] +10000a90: 2101 movs r1, #1 +10000a92: 2800 cmp r0, #0 +10000a94: d1fa bne.n 10000a8c +10000a96: e8c3 1f40 strexb r0, r1, [r3] +10000a9a: 2800 cmp r0, #0 +10000a9c: d1f6 bne.n 10000a8c +10000a9e: f3bf 8f5f dmb sy +10000aa2: 8873 ldrh r3, [r6, #2] +10000aa4: 6931 ldr r1, [r6, #16] +10000aa6: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000aaa: 9b00 ldr r3, [sp, #0] +10000aac: 8073 strh r3, [r6, #2] +10000aae: 2300 movs r3, #0 +10000ab0: e8c1 3f8f stlb r3, [r1] +10000ab4: f382 8810 msr PRIMASK, r2 +10000ab8: e6d4 b.n 10000864 +10000aba: bf40 sev +10000abc: b005 add sp, #20 +10000abe: ecbd 8b02 vpop {d8} +10000ac2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000ac6: 4628 mov r0, r5 +10000ac8: e9cd 2302 strd r2, r3, [sp, #8] +10000acc: f000 f9c0 bl 10000e50 +10000ad0: 9a02 ldr r2, [sp, #8] +10000ad2: 9b03 ldr r3, [sp, #12] +10000ad4: eb10 0e02 adds.w lr, r0, r2 +10000ad8: eb43 0a01 adc.w sl, r3, r1 +10000adc: e726 b.n 1000092c +10000ade: 4608 mov r0, r1 +10000ae0: 690b ldr r3, [r1, #16] +10000ae2: 9102 str r1, [sp, #8] +10000ae4: 4798 blx r3 +10000ae6: 2800 cmp r0, #0 +10000ae8: d0c9 beq.n 10000a7e +10000aea: 9902 ldr r1, [sp, #8] +10000aec: e9d1 2300 ldrd r2, r3, [r1] +10000af0: e711 b.n 10000916 +10000af2: bf00 nop +10000af4: f3af 8000 nop.w +10000af8: ffffffff .word 0xffffffff +10000afc: ffffffff .word 0xffffffff +10000b00: 400b8000 .word 0x400b8000 +10000b04: 20000828 .word 0x20000828 +10000b08: 400b0000 .word 0x400b0000 +10000b0c: 10000821 .word 0x10000821 + +10000b10 : +10000b10: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b14: 4c36 ldr r4, [pc, #216] @ (10000bf0 ) +10000b16: 6925 ldr r5, [r4, #16] +10000b18: b12d cbz r5, 10000b26 +10000b1a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b1e: 210a movs r1, #10 +10000b20: 4834 ldr r0, [pc, #208] @ (10000bf4 ) +10000b22: f7ff be33 b.w 1000078c +10000b26: f8df 80e4 ldr.w r8, [pc, #228] @ 10000c0c +10000b2a: 2103 movs r1, #3 +10000b2c: 4640 mov r0, r8 +10000b2e: f000 f97d bl 10000e2c +10000b32: 2603 movs r6, #3 +10000b34: f8c4 800c str.w r8, [r4, #12] +10000b38: f7ff fc4a bl 100003d0 +10000b3c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000b40: 4b2d ldr r3, [pc, #180] @ (10000bf8 ) +10000b42: 7026 strb r6, [r4, #0] +10000b44: 4403 add r3, r0 +10000b46: 6123 str r3, [r4, #16] +10000b48: f8dc 3000 ldr.w r3, [ip] +10000b4c: 210f movs r1, #15 +10000b4e: 7063 strb r3, [r4, #1] +10000b50: 6963 ldr r3, [r4, #20] +10000b52: 8061 strh r1, [r4, #2] +10000b54: 831d strh r5, [r3, #24] +10000b56: f04f 0504 mov.w r5, #4 +10000b5a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000b5e: f04f 0505 mov.w r5, #5 +10000b62: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000b66: f04f 0506 mov.w r5, #6 +10000b6a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000b6e: f04f 0507 mov.w r5, #7 +10000b72: 210e movs r1, #14 +10000b74: f64f 72ff movw r2, #65535 @ 0xffff +10000b78: 2708 movs r7, #8 +10000b7a: f04f 0e0a mov.w lr, #10 +10000b7e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000b82: f04f 0901 mov.w r9, #1 +10000b86: f04f 0c0c mov.w ip, #12 +10000b8a: f04f 0b02 mov.w fp, #2 +10000b8e: f04f 0a09 mov.w sl, #9 +10000b92: 200d movs r0, #13 +10000b94: f04f 050b mov.w r5, #11 +10000b98: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000b9c: 4917 ldr r1, [pc, #92] @ (10000bfc ) +10000b9e: 80a2 strh r2, [r4, #4] +10000ba0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000ba4: 60a1 str r1, [r4, #8] +10000ba6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000baa: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000bae: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000bb2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000bb6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000bba: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000bbe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000bc2: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000bc6: 801a strh r2, [r3, #0] +10000bc8: 4b0d ldr r3, [pc, #52] @ (10000c00 ) +10000bca: 4630 mov r0, r6 +10000bcc: f8c8 7020 str.w r7, [r8, #32] +10000bd0: 490c ldr r1, [pc, #48] @ (10000c04 ) +10000bd2: 60dc str r4, [r3, #12] +10000bd4: f7ff fc52 bl 1000047c +10000bd8: 4649 mov r1, r9 +10000bda: 4630 mov r0, r6 +10000bdc: f7ff fc38 bl 10000450 +10000be0: 4b09 ldr r3, [pc, #36] @ (10000c08 ) +10000be2: 210a movs r1, #10 +10000be4: 641f str r7, [r3, #64] @ 0x40 +10000be6: 4803 ldr r0, [pc, #12] @ (10000bf4 ) +10000be8: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000bec: f7ff bdce b.w 1000078c +10000bf0: 200005f4 .word 0x200005f4 +10000bf4: 20000848 .word 0x20000848 +10000bf8: 200007b0 .word 0x200007b0 +10000bfc: 0010ffff .word 0x0010ffff +10000c00: 20000828 .word 0x20000828 +10000c04: 10000821 .word 0x10000821 +10000c08: 400b2000 .word 0x400b2000 +10000c0c: 400b0000 .word 0x400b0000 + +10000c10 : +10000c10: 4601 mov r1, r0 +10000c12: b5f0 push {r4, r5, r6, r7, lr} +10000c14: 6900 ldr r0, [r0, #16] +10000c16: f3ef 8710 mrs r7, PRIMASK +10000c1a: b672 cpsid i +10000c1c: e8d0 5fcf ldaexb r5, [r0] +10000c20: 2401 movs r4, #1 +10000c22: 2d00 cmp r5, #0 +10000c24: d1fa bne.n 10000c1c +10000c26: e8c0 4f45 strexb r5, r4, [r0] +10000c2a: 2d00 cmp r5, #0 +10000c2c: d1f6 bne.n 10000c1c +10000c2e: f3bf 8f5f dmb sy +10000c32: f9b1 e002 ldrsh.w lr, [r1, #2] +10000c36: 694c ldr r4, [r1, #20] +10000c38: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000c3c: f1be 0f00 cmp.w lr, #0 +10000c40: ea4f 05cc mov.w r5, ip, lsl #3 +10000c44: 6908 ldr r0, [r1, #16] +10000c46: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000c4a: db3c blt.n 10000cc6 +10000c4c: 5b66 ldrh r6, [r4, r5] +10000c4e: 804e strh r6, [r1, #2] +10000c50: 2600 movs r6, #0 +10000c52: e8c0 6f8f stlb r6, [r0] +10000c56: f387 8810 msr PRIMASK, r7 +10000c5a: f8bc 0002 ldrh.w r0, [ip, #2] +10000c5e: e9cc 2302 strd r2, r3, [ip, #8] +10000c62: 3001 adds r0, #1 +10000c64: f3c0 000e ubfx r0, r0, #0, #15 +10000c68: 2801 cmp r0, #1 +10000c6a: bf38 it cc +10000c6c: 2001 movcc r0, #1 +10000c6e: 9b05 ldr r3, [sp, #20] +10000c70: f8ac 0002 strh.w r0, [ip, #2] +10000c74: f8cc 3010 str.w r3, [ip, #16] +10000c78: 9b06 ldr r3, [sp, #24] +10000c7a: ea40 400e orr.w r0, r0, lr, lsl #16 +10000c7e: f8cc 3014 str.w r3, [ip, #20] +10000c82: 690b ldr r3, [r1, #16] +10000c84: f3ef 8210 mrs r2, PRIMASK +10000c88: b672 cpsid i +10000c8a: e8d3 cfcf ldaexb ip, [r3] +10000c8e: 2701 movs r7, #1 +10000c90: f1bc 0f00 cmp.w ip, #0 +10000c94: d1f9 bne.n 10000c8a +10000c96: e8c3 7f4c strexb ip, r7, [r3] +10000c9a: f1bc 0f00 cmp.w ip, #0 +10000c9e: d1f4 bne.n 10000c8a +10000ca0: f3bf 8f5f dmb sy +10000ca4: 888b ldrh r3, [r1, #4] +10000ca6: 5363 strh r3, [r4, r5] +10000ca8: f8a1 e004 strh.w lr, [r1, #4] +10000cac: 690b ldr r3, [r1, #16] +10000cae: e8c3 6f8f stlb r6, [r3] +10000cb2: f382 8810 msr PRIMASK, r2 +10000cb6: 2201 movs r2, #1 +10000cb8: 68cb ldr r3, [r1, #12] +10000cba: 7809 ldrb r1, [r1, #0] +10000cbc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000cc0: 408a lsls r2, r1 +10000cc2: 605a str r2, [r3, #4] +10000cc4: bdf0 pop {r4, r5, r6, r7, pc} +10000cc6: 2300 movs r3, #0 +10000cc8: e8c0 3f8f stlb r3, [r0] +10000ccc: f387 8810 msr PRIMASK, r7 +10000cd0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000cd4: bdf0 pop {r4, r5, r6, r7, pc} +10000cd6: bf00 nop + +10000cd8 : +10000cd8: 4603 mov r3, r0 +10000cda: 8940 ldrh r0, [r0, #10] +10000cdc: ebb0 4f21 cmp.w r0, r1, asr #16 +10000ce0: dd37 ble.n 10000d52 +10000ce2: 6958 ldr r0, [r3, #20] +10000ce4: 140a asrs r2, r1, #16 +10000ce6: eb02 0242 add.w r2, r2, r2, lsl #1 +10000cea: b510 push {r4, lr} +10000cec: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000cf0: 691c ldr r4, [r3, #16] +10000cf2: f3ef 8c10 mrs ip, PRIMASK +10000cf6: b672 cpsid i +10000cf8: e8d4 efcf ldaexb lr, [r4] +10000cfc: 2201 movs r2, #1 +10000cfe: f1be 0f00 cmp.w lr, #0 +10000d02: d1f9 bne.n 10000cf8 +10000d04: e8c4 2f4e strexb lr, r2, [r4] +10000d08: f1be 0f00 cmp.w lr, #0 +10000d0c: d1f4 bne.n 10000cf8 +10000d0e: f3bf 8f5f dmb sy +10000d12: 8842 ldrh r2, [r0, #2] +10000d14: b289 uxth r1, r1 +10000d16: b292 uxth r2, r2 +10000d18: 428a cmp r2, r1 +10000d1a: d007 beq.n 10000d2c +10000d1c: 2200 movs r2, #0 +10000d1e: 691b ldr r3, [r3, #16] +10000d20: e8c3 2f8f stlb r2, [r3] +10000d24: f38c 8810 msr PRIMASK, ip +10000d28: 2000 movs r0, #0 +10000d2a: bd10 pop {r4, pc} +10000d2c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000d30: 8042 strh r2, [r0, #2] +10000d32: 2101 movs r1, #1 +10000d34: 2200 movs r2, #0 +10000d36: 6918 ldr r0, [r3, #16] +10000d38: 7199 strb r1, [r3, #6] +10000d3a: e8c0 2f8f stlb r2, [r0] +10000d3e: f38c 8810 msr PRIMASK, ip +10000d42: 781c ldrb r4, [r3, #0] +10000d44: 68da ldr r2, [r3, #12] +10000d46: 4608 mov r0, r1 +10000d48: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000d4c: 40a1 lsls r1, r4 +10000d4e: 6059 str r1, [r3, #4] +10000d50: bd10 pop {r4, pc} +10000d52: 2000 movs r0, #0 +10000d54: 4770 bx lr +10000d56: bf00 nop + +10000d58 : +10000d58: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000d5c: 4606 mov r6, r0 +10000d5e: 460d mov r5, r1 +10000d60: b083 sub sp, #12 +10000d62: f3ef 8405 mrs r4, IPSR +10000d66: b2e4 uxtb r4, r4 +10000d68: b13c cbz r4, 10000d7a +10000d6a: 4b2d ldr r3, [pc, #180] @ (10000e20 ) +10000d6c: 6a5a ldr r2, [r3, #36] @ 0x24 +10000d6e: 42aa cmp r2, r5 +10000d70: d21c bcs.n 10000dac +10000d72: 2000 movs r0, #0 +10000d74: b003 add sp, #12 +10000d76: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000d7a: 4f2a ldr r7, [pc, #168] @ (10000e24 ) +10000d7c: f8d7 900c ldr.w r9, [r7, #12] +10000d80: f897 8000 ldrb.w r8, [r7] +10000d84: 4648 mov r0, r9 +10000d86: f000 f863 bl 10000e50 +10000d8a: f108 0804 add.w r8, r8, #4 +10000d8e: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000d92: 1a1b subs r3, r3, r0 +10000d94: 1a30 subs r0, r6, r0 +10000d96: eb65 0101 sbc.w r1, r5, r1 +10000d9a: 4298 cmp r0, r3 +10000d9c: f171 0100 sbcs.w r1, r1, #0 +10000da0: db10 blt.n 10000dc4 +10000da2: bf20 wfe +10000da4: 4b1e ldr r3, [pc, #120] @ (10000e20 ) +10000da6: 6a5a ldr r2, [r3, #36] @ 0x24 +10000da8: 42aa cmp r2, r5 +10000daa: d3e2 bcc.n 10000d72 +10000dac: bf14 ite ne +10000dae: 2401 movne r4, #1 +10000db0: 2400 moveq r4, #0 +10000db2: 6a9b ldr r3, [r3, #40] @ 0x28 +10000db4: 42b3 cmp r3, r6 +10000db6: bf34 ite cc +10000db8: 4620 movcc r0, r4 +10000dba: f044 0001 orrcs.w r0, r4, #1 +10000dbe: b003 add sp, #12 +10000dc0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000dc4: f000 f84c bl 10000e60 +10000dc8: 4286 cmp r6, r0 +10000dca: eb65 0101 sbc.w r1, r5, r1 +10000dce: 2900 cmp r1, #0 +10000dd0: db14 blt.n 10000dfc +10000dd2: 4b15 ldr r3, [pc, #84] @ (10000e28 ) +10000dd4: 4638 mov r0, r7 +10000dd6: e9cd 3400 strd r3, r4, [sp] +10000dda: 4632 mov r2, r6 +10000ddc: 462b mov r3, r5 +10000dde: f7ff ff17 bl 10000c10 +10000de2: 1e01 subs r1, r0, #0 +10000de4: dd0a ble.n 10000dfc +10000de6: 4b0e ldr r3, [pc, #56] @ (10000e20 ) +10000de8: 6a5a ldr r2, [r3, #36] @ 0x24 +10000dea: 42aa cmp r2, r5 +10000dec: d316 bcc.n 10000e1c +10000dee: 6a9b ldr r3, [r3, #40] @ 0x28 +10000df0: 42b3 cmp r3, r6 +10000df2: d311 bcc.n 10000e18 +10000df4: 480b ldr r0, [pc, #44] @ (10000e24 ) +10000df6: f7ff ff6f bl 10000cd8 +10000dfa: e7b6 b.n 10000d6a +10000dfc: 4b08 ldr r3, [pc, #32] @ (10000e20 ) +10000dfe: 6a5c ldr r4, [r3, #36] @ 0x24 +10000e00: 42ac cmp r4, r5 +10000e02: d3b6 bcc.n 10000d72 +10000e04: 1b64 subs r4, r4, r5 +10000e06: bf18 it ne +10000e08: 2401 movne r4, #1 +10000e0a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000e0c: 42b3 cmp r3, r6 +10000e0e: bf34 ite cc +10000e10: 4620 movcc r0, r4 +10000e12: f044 0001 orrcs.w r0, r4, #1 +10000e16: e7ad b.n 10000d74 +10000e18: 42aa cmp r2, r5 +10000e1a: d1eb bne.n 10000df4 +10000e1c: bf20 wfe +10000e1e: e7e9 b.n 10000df4 +10000e20: 400b0000 .word 0x400b0000 +10000e24: 200005f4 .word 0x200005f4 +10000e28: 100007e5 .word 0x100007e5 + +10000e2c : +10000e2c: b410 push {r4} +10000e2e: 4b05 ldr r3, [pc, #20] @ (10000e44 ) +10000e30: 4c05 ldr r4, [pc, #20] @ (10000e48 ) +10000e32: 4a06 ldr r2, [pc, #24] @ (10000e4c ) +10000e34: 42a0 cmp r0, r4 +10000e36: bf14 ite ne +10000e38: 4618 movne r0, r3 +10000e3a: 1c58 addeq r0, r3, #1 +10000e3c: f85d 4b04 ldr.w r4, [sp], #4 +10000e40: f7ff ba9a b.w 10000378 +10000e44: 200007d8 .word 0x200007d8 +10000e48: 400b8000 .word 0x400b8000 +10000e4c: 100035a4 .word 0x100035a4 + +10000e50 : +10000e50: 4603 mov r3, r0 +10000e52: 6a41 ldr r1, [r0, #36] @ 0x24 +10000e54: 460a mov r2, r1 +10000e56: 6a98 ldr r0, [r3, #40] @ 0x28 +10000e58: 6a59 ldr r1, [r3, #36] @ 0x24 +10000e5a: 428a cmp r2, r1 +10000e5c: d1fa bne.n 10000e54 +10000e5e: 4770 bx lr + +10000e60 : +10000e60: 4b03 ldr r3, [pc, #12] @ (10000e70 ) +10000e62: 6a59 ldr r1, [r3, #36] @ 0x24 +10000e64: 460a mov r2, r1 +10000e66: 6a98 ldr r0, [r3, #40] @ 0x28 +10000e68: 6a59 ldr r1, [r3, #36] @ 0x24 +10000e6a: 4291 cmp r1, r2 +10000e6c: d1fa bne.n 10000e64 +10000e6e: 4770 bx lr +10000e70: 400b0000 .word 0x400b0000 + +10000e74 : +10000e74: b430 push {r4, r5} +10000e76: 4a15 ldr r2, [pc, #84] @ (10000ecc ) +10000e78: 6a53 ldr r3, [r2, #36] @ 0x24 +10000e7a: 469c mov ip, r3 +10000e7c: 6a94 ldr r4, [r2, #40] @ 0x28 +10000e7e: 6a53 ldr r3, [r2, #36] @ 0x24 +10000e80: 4563 cmp r3, ip +10000e82: d1fa bne.n 10000e7a +10000e84: 1902 adds r2, r0, r4 +10000e86: 4159 adcs r1, r3 +10000e88: f04f 0500 mov.w r5, #0 +10000e8c: bf28 it cs +10000e8e: 2501 movcs r5, #1 +10000e90: 4b0e ldr r3, [pc, #56] @ (10000ecc ) +10000e92: 6a5b ldr r3, [r3, #36] @ 0x24 +10000e94: b1b5 cbz r5, 10000ec4 +10000e96: 1c5a adds r2, r3, #1 +10000e98: bf08 it eq +10000e9a: 461a moveq r2, r3 +10000e9c: d008 beq.n 10000eb0 +10000e9e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10000ea2: 460a mov r2, r1 +10000ea4: 4809 ldr r0, [pc, #36] @ (10000ecc ) +10000ea6: 6a43 ldr r3, [r0, #36] @ 0x24 +10000ea8: 428b cmp r3, r1 +10000eaa: d3fc bcc.n 10000ea6 +10000eac: 428b cmp r3, r1 +10000eae: d107 bne.n 10000ec0 +10000eb0: 4906 ldr r1, [pc, #24] @ (10000ecc ) +10000eb2: e002 b.n 10000eba +10000eb4: 6a48 ldr r0, [r1, #36] @ 0x24 +10000eb6: 4298 cmp r0, r3 +10000eb8: d102 bne.n 10000ec0 +10000eba: 6a88 ldr r0, [r1, #40] @ 0x28 +10000ebc: 4290 cmp r0, r2 +10000ebe: d3f9 bcc.n 10000eb4 +10000ec0: bc30 pop {r4, r5} +10000ec2: 4770 bx lr +10000ec4: 4299 cmp r1, r3 +10000ec6: d8ed bhi.n 10000ea4 +10000ec8: e7f0 b.n 10000eac +10000eca: bf00 nop +10000ecc: 400b0000 .word 0x400b0000 + +10000ed0 : +10000ed0: b5f8 push {r3, r4, r5, r6, r7, lr} +10000ed2: 4605 mov r5, r0 +10000ed4: 2006 movs r0, #6 +10000ed6: 460e mov r6, r1 +10000ed8: f000 f8e4 bl 100010a4 +10000edc: 2800 cmp r0, #0 +10000ede: d042 beq.n 10000f66 +10000ee0: 4a35 ldr r2, [pc, #212] @ (10000fb8 ) +10000ee2: 4836 ldr r0, [pc, #216] @ (10000fbc ) +10000ee4: 4295 cmp r5, r2 +10000ee6: bf14 ite ne +10000ee8: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10000eec: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10000ef0: 4b33 ldr r3, [pc, #204] @ (10000fc0 ) +10000ef2: 4934 ldr r1, [pc, #208] @ (10000fc4 ) +10000ef4: 6002 str r2, [r0, #0] +10000ef6: 601a str r2, [r3, #0] +10000ef8: 688c ldr r4, [r1, #8] +10000efa: ea32 0404 bics.w r4, r2, r4 +10000efe: d1fb bne.n 10000ef8 +10000f00: 4b2d ldr r3, [pc, #180] @ (10000fb8 ) +10000f02: f44f 7180 mov.w r1, #256 @ 0x100 +10000f06: 1aeb subs r3, r5, r3 +10000f08: fab3 f383 clz r3, r3 +10000f0c: 4a2e ldr r2, [pc, #184] @ (10000fc8 ) +10000f0e: 095b lsrs r3, r3, #5 +10000f10: 2006 movs r0, #6 +10000f12: f822 1013 strh.w r1, [r2, r3, lsl #1] +10000f16: f000 f8c5 bl 100010a4 +10000f1a: 00c3 lsls r3, r0, #3 +10000f1c: fbb3 f3f6 udiv r3, r3, r6 +10000f20: 3301 adds r3, #1 +10000f22: 09da lsrs r2, r3, #7 +10000f24: d120 bne.n 10000f68 +10000f26: 2640 movs r6, #64 @ 0x40 +10000f28: 2101 movs r1, #1 +10000f2a: 6269 str r1, [r5, #36] @ 0x24 +10000f2c: 62aa str r2, [r5, #40] @ 0x28 +10000f2e: 6b2f ldr r7, [r5, #48] @ 0x30 +10000f30: 07fb lsls r3, r7, #31 +10000f32: d422 bmi.n 10000f7a +10000f34: 462b mov r3, r5 +10000f36: 2200 movs r2, #0 +10000f38: f853 1f2c ldr.w r1, [r3, #44]! +10000f3c: 2006 movs r0, #6 +10000f3e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10000f42: 6022 str r2, [r4, #0] +10000f44: 632f str r7, [r5, #48] @ 0x30 +10000f46: f000 f8ad bl 100010a4 +10000f4a: f240 3101 movw r1, #769 @ 0x301 +10000f4e: 2203 movs r2, #3 +10000f50: 0080 lsls r0, r0, #2 +10000f52: fbb0 f0f6 udiv r0, r0, r6 +10000f56: 6aeb ldr r3, [r5, #44] @ 0x2c +10000f58: f083 0370 eor.w r3, r3, #112 @ 0x70 +10000f5c: f003 037e and.w r3, r3, #126 @ 0x7e +10000f60: 6023 str r3, [r4, #0] +10000f62: 6329 str r1, [r5, #48] @ 0x30 +10000f64: 64aa str r2, [r5, #72] @ 0x48 +10000f66: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000f68: f64f 71fe movw r1, #65534 @ 0xfffe +10000f6c: 428a cmp r2, r1 +10000f6e: d91b bls.n 10000fa8 +10000f70: 4622 mov r2, r4 +10000f72: f64f 71ff movw r1, #65535 @ 0xffff +10000f76: 4e15 ldr r6, [pc, #84] @ (10000fcc ) +10000f78: e7d7 b.n 10000f2a +10000f7a: f240 3201 movw r2, #769 @ 0x301 +10000f7e: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10000f82: 631a str r2, [r3, #48] @ 0x30 +10000f84: 6a6b ldr r3, [r5, #36] @ 0x24 +10000f86: 6aac ldr r4, [r5, #40] @ 0x28 +10000f88: 2006 movs r0, #6 +10000f8a: eb04 1483 add.w r4, r4, r3, lsl #6 +10000f8e: f000 f889 bl 100010a4 +10000f92: 4b0f ldr r3, [pc, #60] @ (10000fd0 ) +10000f94: 02a4 lsls r4, r4, #10 +10000f96: fba3 2300 umull r2, r3, r3, r0 +10000f9a: 0adb lsrs r3, r3, #11 +10000f9c: 2100 movs r1, #0 +10000f9e: fbb4 f0f3 udiv r0, r4, r3 +10000fa2: f7ff ff67 bl 10000e74 +10000fa6: e7c5 b.n 10000f34 +10000fa8: f3c3 0345 ubfx r3, r3, #1, #6 +10000fac: 4611 mov r1, r2 +10000fae: eb03 1682 add.w r6, r3, r2, lsl #6 +10000fb2: 461a mov r2, r3 +10000fb4: e7b9 b.n 10000f2a +10000fb6: bf00 nop +10000fb8: 40078000 .word 0x40078000 +10000fbc: 40022000 .word 0x40022000 +10000fc0: 40023000 .word 0x40023000 +10000fc4: 40020000 .word 0x40020000 +10000fc8: 2000084c .word 0x2000084c +10000fcc: 003fffc0 .word 0x003fffc0 +10000fd0: 8f2b7b75 .word 0x8f2b7b75 + +10000fd4 : +10000fd4: eb00 0c40 add.w ip, r0, r0, lsl #1 +10000fd8: ea4f 0c8c mov.w ip, ip, lsl #2 +10000fdc: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10000fe0: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10000fe4: b5f0 push {r4, r5, r6, r7, lr} +10000fe6: 4616 mov r6, r2 +10000fe8: f8dc 2004 ldr.w r2, [ip, #4] +10000fec: 1f05 subs r5, r0, #4 +10000fee: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10000ff2: bf38 it cc +10000ff4: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10000ff8: b2ed uxtb r5, r5 +10000ffa: bf38 it cc +10000ffc: f8cc 2004 strcc.w r2, [ip, #4] +10001000: 2d01 cmp r5, #1 +10001002: d92a bls.n 1000105a +10001004: f44f 6700 mov.w r7, #2048 @ 0x800 +10001008: 4c25 ldr r4, [pc, #148] @ (100010a0 ) +1000100a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000100e: 6017 str r7, [r2, #0] +10001010: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10001014: b9b2 cbnz r2, 10001044 +10001016: f8dc 2000 ldr.w r2, [ip] +1000101a: 2d01 cmp r5, #1 +1000101c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001020: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001024: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001028: 6032 str r2, [r6, #0] +1000102a: d92a bls.n 10001082 +1000102c: f44f 6100 mov.w r1, #2048 @ 0x800 +10001030: f844 3020 str.w r3, [r4, r0, lsl #2] +10001034: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001038: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1000103c: 6011 str r1, [r2, #0] +1000103e: f8cc 3004 str.w r3, [ip, #4] +10001042: bdf0 pop {r4, r5, r6, r7, pc} +10001044: 6967 ldr r7, [r4, #20] +10001046: fbb7 fef2 udiv lr, r7, r2 +1000104a: f10e 0e01 add.w lr, lr, #1 +1000104e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10001052: f1be 0e03 subs.w lr, lr, #3 +10001056: d2fc bcs.n 10001052 +10001058: e7dd b.n 10001016 +1000105a: 2901 cmp r1, #1 +1000105c: d1d2 bne.n 10001004 +1000105e: 2403 movs r4, #3 +10001060: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10001064: 6014 str r4, [r2, #0] +10001066: f8dc 2008 ldr.w r2, [ip, #8] +1000106a: 07d2 lsls r2, r2, #31 +1000106c: d5fb bpl.n 10001066 +1000106e: f8dc 2000 ldr.w r2, [ip] +10001072: 4c0b ldr r4, [pc, #44] @ (100010a0 ) +10001074: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001078: f002 02e0 and.w r2, r2, #224 @ 0xe0 +1000107c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001080: 6032 str r2, [r6, #0] +10001082: 2201 movs r2, #1 +10001084: f8dc 5000 ldr.w r5, [ip] +10001088: 404d eors r5, r1 +1000108a: f005 0503 and.w r5, r5, #3 +1000108e: 6035 str r5, [r6, #0] +10001090: fa02 f101 lsl.w r1, r2, r1 +10001094: f8dc 2008 ldr.w r2, [ip, #8] +10001098: 420a tst r2, r1 +1000109a: d0fb beq.n 10001094 +1000109c: e7c6 b.n 1000102c +1000109e: bf00 nop +100010a0: 200007dc .word 0x200007dc + +100010a4 : +100010a4: 4b01 ldr r3, [pc, #4] @ (100010ac ) +100010a6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +100010aa: 4770 bx lr +100010ac: 200007dc .word 0x200007dc + +100010b0 : +100010b0: b470 push {r4, r5, r6} +100010b2: 9d03 ldr r5, [sp, #12] +100010b4: 6804 ldr r4, [r0, #0] +100010b6: 032d lsls r5, r5, #12 +100010b8: ea45 4503 orr.w r5, r5, r3, lsl #16 +100010bc: 4b1b ldr r3, [pc, #108] @ (1000112c ) +100010be: 2c00 cmp r4, #0 +100010c0: fbb3 f3f1 udiv r3, r3, r1 +100010c4: fbb2 f6f3 udiv r6, r2, r3 +100010c8: db1f blt.n 1000110a +100010ca: 4a19 ldr r2, [pc, #100] @ (10001130 ) +100010cc: 4b19 ldr r3, [pc, #100] @ (10001134 ) +100010ce: 4290 cmp r0, r2 +100010d0: bf14 ite ne +100010d2: f44f 4280 movne.w r2, #16384 @ 0x4000 +100010d6: f44f 4200 moveq.w r2, #32768 @ 0x8000 +100010da: 4c17 ldr r4, [pc, #92] @ (10001138 ) +100010dc: 601a str r2, [r3, #0] +100010de: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100010e2: 601a str r2, [r3, #0] +100010e4: 68a3 ldr r3, [r4, #8] +100010e6: ea32 0303 bics.w r3, r2, r3 +100010ea: d1fb bne.n 100010e4 +100010ec: 2221 movs r2, #33 @ 0x21 +100010ee: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100010f2: 3304 adds r3, #4 +100010f4: 6001 str r1, [r0, #0] +100010f6: 6086 str r6, [r0, #8] +100010f8: 601a str r2, [r3, #0] +100010fa: 6802 ldr r2, [r0, #0] +100010fc: 2a00 cmp r2, #0 +100010fe: dafc bge.n 100010fa +10001100: 2208 movs r2, #8 +10001102: 60c5 str r5, [r0, #12] +10001104: 601a str r2, [r3, #0] +10001106: bc70 pop {r4, r5, r6} +10001108: 4770 bx lr +1000110a: 6803 ldr r3, [r0, #0] +1000110c: f003 033f and.w r3, r3, #63 @ 0x3f +10001110: 428b cmp r3, r1 +10001112: d1da bne.n 100010ca +10001114: 6883 ldr r3, [r0, #8] +10001116: f3c3 030b ubfx r3, r3, #0, #12 +1000111a: 42b3 cmp r3, r6 +1000111c: d1d5 bne.n 100010ca +1000111e: 68c3 ldr r3, [r0, #12] +10001120: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001124: 42ab cmp r3, r5 +10001126: d1d0 bne.n 100010ca +10001128: e7ed b.n 10001106 +1000112a: bf00 nop +1000112c: 00b71b00 .word 0x00b71b00 +10001130: 40058000 .word 0x40058000 +10001134: 40022000 .word 0x40022000 +10001138: 40020000 .word 0x40020000 + +1000113c : +1000113c: 2301 movs r3, #1 +1000113e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001142: 0080 lsls r0, r0, #2 +10001144: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001148: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000114c: 6041 str r1, [r0, #4] +1000114e: 6003 str r3, [r0, #0] +10001150: 4770 bx lr +10001152: bf00 nop + +10001154 : +10001154: 2300 movs r3, #0 +10001156: 8adb ldrh r3, [r3, #22] +10001158: 2200 movs r2, #0 +1000115a: e842 f200 tt r2, r2 +1000115e: 0252 lsls r2, r2, #9 +10001160: d401 bmi.n 10001166 +10001162: 2110 movs r1, #16 +10001164: 4718 bx r3 +10001166: 2104 movs r1, #4 +10001168: 4718 bx r3 +1000116a: bf00 nop + +1000116c : +1000116c: 4a03 ldr r2, [pc, #12] @ (1000117c ) +1000116e: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10001172: 2b00 cmp r3, #0 +10001174: d0fb beq.n 1000116e +10001176: f3bf 8f5f dmb sy +1000117a: 4770 bx lr +1000117c: 400e0000 .word 0x400e0000 + +10001180 : +10001180: 2100 movs r1, #0 +10001182: 4b04 ldr r3, [pc, #16] @ (10001194 ) +10001184: 4a04 ldr r2, [pc, #16] @ (10001198 ) +10001186: f3bf 8f5f dmb sy +1000118a: f843 1b04 str.w r1, [r3], #4 +1000118e: 4293 cmp r3, r2 +10001190: d1f9 bne.n 10001186 +10001192: 4770 bx lr +10001194: 400e080c .word 0x400e080c +10001198: 400e082c .word 0x400e082c + +1000119c : +1000119c: b410 push {r4} +1000119e: f44f 708d mov.w r0, #282 @ 0x11a +100011a2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100011a6: 4a06 ldr r2, [pc, #24] @ (100011c0 ) +100011a8: 4b06 ldr r3, [pc, #24] @ (100011c4 ) +100011aa: 4907 ldr r1, [pc, #28] @ (100011c8 ) +100011ac: 6014 str r4, [r2, #0] +100011ae: 60d0 str r0, [r2, #12] +100011b0: 6019 str r1, [r3, #0] +100011b2: 6853 ldr r3, [r2, #4] +100011b4: 2b00 cmp r3, #0 +100011b6: dafc bge.n 100011b2 +100011b8: f85d 4b04 ldr.w r4, [sp], #4 +100011bc: 4770 bx lr +100011be: bf00 nop +100011c0: 40048000 .word 0x40048000 +100011c4: 4004a000 .word 0x4004a000 +100011c8: 00fab000 .word 0x00fab000 + +100011cc : +100011cc: 4770 bx lr +100011ce: bf00 nop + +100011d0 : +100011d0: b508 push {r3, lr} +100011d2: 4801 ldr r0, [pc, #4] @ (100011d8 ) +100011d4: f7ff f8b8 bl 10000348 +100011d8: 100035c8 .word 0x100035c8 + +100011dc : +100011dc: b538 push {r3, r4, r5, lr} +100011de: 4c05 ldr r4, [pc, #20] @ (100011f4 ) +100011e0: 4d05 ldr r5, [pc, #20] @ (100011f8 ) +100011e2: 42ac cmp r4, r5 +100011e4: d204 bcs.n 100011f0 +100011e6: f854 3b04 ldr.w r3, [r4], #4 +100011ea: 4798 blx r3 +100011ec: 42ac cmp r4, r5 +100011ee: d3fa bcc.n 100011e6 +100011f0: bd38 pop {r3, r4, r5, pc} +100011f2: bf00 nop +100011f4: 10003518 .word 0x10003518 +100011f8: 10003558 .word 0x10003558 + +100011fc : +100011fc: b410 push {r4} +100011fe: 4807 ldr r0, [pc, #28] @ (1000121c ) +10001200: 4c07 ldr r4, [pc, #28] @ (10001220 ) +10001202: 4b08 ldr r3, [pc, #32] @ (10001224 ) +10001204: 4a08 ldr r2, [pc, #32] @ (10001228 ) +10001206: 4909 ldr r1, [pc, #36] @ (1000122c ) +10001208: 6004 str r4, [r0, #0] +1000120a: 601a str r2, [r3, #0] +1000120c: 688b ldr r3, [r1, #8] +1000120e: ea32 0303 bics.w r3, r2, r3 +10001212: d1fb bne.n 1000120c +10001214: f85d 4b04 ldr.w r4, [sp], #4 +10001218: 4770 bx lr +1000121a: bf00 nop +1000121c: 40022000 .word 0x40022000 +10001220: efef3b7f .word 0xefef3b7f +10001224: 40023000 .word 0x40023000 +10001228: 03f3fff6 .word 0x03f3fff6 +1000122c: 40020000 .word 0x40020000 + +10001230 : +10001230: 4b04 ldr r3, [pc, #16] @ (10001244 ) +10001232: 6cdb ldr r3, [r3, #76] @ 0x4c +10001234: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001238: d103 bne.n 10001242 +1000123a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000123e: 4b02 ldr r3, [pc, #8] @ (10001248 ) +10001240: 64da str r2, [r3, #76] @ 0x4c +10001242: 4770 bx lr +10001244: 50110000 .word 0x50110000 +10001248: 50112000 .word 0x50112000 + +1000124c : +1000124c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001250: 4b04 ldr r3, [pc, #16] @ (10001264 ) +10001252: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001256: 430b orrs r3, r1 +10001258: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000125c: ee10 0430 dcp_rcmp r0 +10001260: 4770 bx lr +10001262: bf00 nop +10001264: 00300303 .word 0x00300303 + +10001268 : +10001268: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +1000126c: 4b04 ldr r3, [pc, #16] @ (10001280 ) +1000126e: 4a05 ldr r2, [pc, #20] @ (10001284 ) +10001270: 6019 str r1, [r3, #0] +10001272: 6893 ldr r3, [r2, #8] +10001274: 43db mvns r3, r3 +10001276: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +1000127a: d1fa bne.n 10001272 +1000127c: 4770 bx lr +1000127e: bf00 nop +10001280: 40023000 .word 0x40023000 +10001284: 40020000 .word 0x40020000 + +10001288 : +10001288: b510 push {r4, lr} +1000128a: f245 2053 movw r0, #21075 @ 0x5253 +1000128e: f7ff ff61 bl 10001154 +10001292: e8bd 4010 ldmia.w sp!, {r4, lr} +10001296: 4603 mov r3, r0 +10001298: 2004 movs r0, #4 +1000129a: 4718 bx r3 + +1000129c : +1000129c: b510 push {r4, lr} +1000129e: f245 2053 movw r0, #21075 @ 0x5253 +100012a2: f7ff ff57 bl 10001154 +100012a6: e8bd 4010 ldmia.w sp!, {r4, lr} +100012aa: 4603 mov r3, r0 +100012ac: 2001 movs r0, #1 +100012ae: 4718 bx r3 + +100012b0 : +100012b0: f7ff b8a2 b.w 100003f8 + +100012b4 : +100012b4: 4914 ldr r1, [pc, #80] @ (10001308 ) +100012b6: 4b15 ldr r3, [pc, #84] @ (1000130c ) +100012b8: b570 push {r4, r5, r6, lr} +100012ba: 1a5c subs r4, r3, r1 +100012bc: 10a6 asrs r6, r4, #2 +100012be: 2e44 cmp r6, #68 @ 0x44 +100012c0: 4632 mov r2, r6 +100012c2: bf28 it cs +100012c4: 2244 movcs r2, #68 @ 0x44 +100012c6: 4d12 ldr r5, [pc, #72] @ (10001310 ) +100012c8: 0092 lsls r2, r2, #2 +100012ca: 4628 mov r0, r5 +100012cc: f002 f872 bl 100033b4 +100012d0: f5b4 7f86 cmp.w r4, #268 @ 0x10c +100012d4: d813 bhi.n 100012fe +100012d6: 4a0f ldr r2, [pc, #60] @ (10001314 ) +100012d8: f1c6 0044 rsb r0, r6, #68 @ 0x44 +100012dc: d012 beq.n 10001304 +100012de: 192b adds r3, r5, r4 +100012e0: 0841 lsrs r1, r0, #1 +100012e2: eb03 01c1 add.w r1, r3, r1, lsl #3 +100012e6: e9c3 2200 strd r2, r2, [r3] +100012ea: 3308 adds r3, #8 +100012ec: 428b cmp r3, r1 +100012ee: d1fa bne.n 100012e6 +100012f0: 07c3 lsls r3, r0, #31 +100012f2: d504 bpl.n 100012fe +100012f4: f020 0001 bic.w r0, r0, #1 +100012f8: 4430 add r0, r6 +100012fa: f845 2020 str.w r2, [r5, r0, lsl #2] +100012fe: 4b06 ldr r3, [pc, #24] @ (10001318 ) +10001300: 609d str r5, [r3, #8] +10001302: bd70 pop {r4, r5, r6, pc} +10001304: 2043 movs r0, #67 @ 0x43 +10001306: e7f8 b.n 100012fa +10001308: 10000000 .word 0x10000000 +1000130c: 10000110 .word 0x10000110 +10001310: 20000000 .word 0x20000000 +10001314: 10000111 .word 0x10000111 +10001318: e000ed00 .word 0xe000ed00 + +1000131c : +1000131c: 2300 movs r3, #0 +1000131e: b570 push {r4, r5, r6, lr} +10001320: 4c2b ldr r4, [pc, #172] @ (100013d0 ) +10001322: b082 sub sp, #8 +10001324: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001328: f7ff ff38 bl 1000119c +1000132c: 2201 movs r2, #1 +1000132e: 4b29 ldr r3, [pc, #164] @ (100013d4 ) +10001330: 63da str r2, [r3, #60] @ 0x3c +10001332: 6c63 ldr r3, [r4, #68] @ 0x44 +10001334: 2b01 cmp r3, #1 +10001336: d1fc bne.n 10001332 +10001338: 2103 movs r1, #3 +1000133a: 4a26 ldr r2, [pc, #152] @ (100013d4 ) +1000133c: 4b24 ldr r3, [pc, #144] @ (100013d0 ) +1000133e: 6311 str r1, [r2, #48] @ 0x30 +10001340: 6b9c ldr r4, [r3, #56] @ 0x38 +10001342: 2c01 cmp r4, #1 +10001344: d1fc bne.n 10001340 +10001346: 2602 movs r6, #2 +10001348: 2505 movs r5, #5 +1000134a: 4621 mov r1, r4 +1000134c: 2305 movs r3, #5 +1000134e: 4a22 ldr r2, [pc, #136] @ (100013d8 ) +10001350: 4822 ldr r0, [pc, #136] @ (100013dc ) +10001352: 9600 str r6, [sp, #0] +10001354: f7ff feac bl 100010b0 +10001358: 4621 mov r1, r4 +1000135a: 462b mov r3, r5 +1000135c: 4a20 ldr r2, [pc, #128] @ (100013e0 ) +1000135e: 4821 ldr r0, [pc, #132] @ (100013e4 ) +10001360: 9500 str r5, [sp, #0] +10001362: f7ff fea5 bl 100010b0 +10001366: 2200 movs r2, #0 +10001368: 2004 movs r0, #4 +1000136a: 4631 mov r1, r6 +1000136c: 4b1e ldr r3, [pc, #120] @ (100013e8 ) +1000136e: f7ff fe31 bl 10000fd4 +10001372: 4621 mov r1, r4 +10001374: 4628 mov r0, r5 +10001376: 2200 movs r2, #0 +10001378: 4b1c ldr r3, [pc, #112] @ (100013ec ) +1000137a: f7ff fe2b bl 10000fd4 +1000137e: 2200 movs r2, #0 +10001380: 2008 movs r0, #8 +10001382: 4611 mov r1, r2 +10001384: 4b1a ldr r3, [pc, #104] @ (100013f0 ) +10001386: f7ff fe25 bl 10000fd4 +1000138a: 2200 movs r2, #0 +1000138c: 2009 movs r0, #9 +1000138e: 4611 mov r1, r2 +10001390: 4b17 ldr r3, [pc, #92] @ (100013f0 ) +10001392: f7ff fe1f bl 10000fd4 +10001396: 2200 movs r2, #0 +10001398: 2006 movs r0, #6 +1000139a: 4611 mov r1, r2 +1000139c: 4b13 ldr r3, [pc, #76] @ (100013ec ) +1000139e: f7ff fe19 bl 10000fd4 +100013a2: 2200 movs r2, #0 +100013a4: 4b11 ldr r3, [pc, #68] @ (100013ec ) +100013a6: 2007 movs r0, #7 +100013a8: 4611 mov r1, r2 +100013aa: f7ff fe13 bl 10000fd4 +100013ae: 2004 movs r0, #4 +100013b0: f7ff fe78 bl 100010a4 +100013b4: 2400 movs r4, #0 +100013b6: 4b0f ldr r3, [pc, #60] @ (100013f4 ) +100013b8: fba3 3500 umull r3, r5, r3, r0 +100013bc: 0cad lsrs r5, r5, #18 +100013be: b2e0 uxtb r0, r4 +100013c0: 4629 mov r1, r5 +100013c2: 3401 adds r4, #1 +100013c4: f7ff feba bl 1000113c +100013c8: 2c06 cmp r4, #6 +100013ca: d1f8 bne.n 100013be +100013cc: b002 add sp, #8 +100013ce: bd70 pop {r4, r5, r6, pc} +100013d0: 40010000 .word 0x40010000 +100013d4: 40013000 .word 0x40013000 +100013d8: 59682f00 .word 0x59682f00 +100013dc: 40050000 .word 0x40050000 +100013e0: 47868c00 .word 0x47868c00 +100013e4: 40058000 .word 0x40058000 +100013e8: 00b71b00 .word 0x00b71b00 +100013ec: 08f0d180 .word 0x08f0d180 +100013f0: 02dc6c00 .word 0x02dc6c00 +100013f4: 431bde83 .word 0x431bde83 + +100013f8 : +100013f8: b086 sub sp, #24 +100013fa: b403 push {r0, r1} +100013fc: fc51 0408 dcp_pxmd r0, r1 +10001400: e9cd 0102 strd r0, r1, [sp, #8] +10001404: fc51 0409 dcp_pymd r0, r1 +10001408: e9cd 0104 strd r0, r1, [sp, #16] +1000140c: ec51 040a dcp_refd r0, r1 +10001410: e9cd 0106 strd r0, r1, [sp, #24] +10001414: bc03 pop {r0, r1} +10001416: 47f0 blx lr + +10001418 : +10001418: e8bd 5000 ldmia.w sp!, {ip, lr} +1000141c: ec4e c400 dcp_wxmd ip, lr +10001420: e8bd 5000 ldmia.w sp!, {ip, lr} +10001424: ec4e c401 dcp_wymd ip, lr +10001428: e8bd 5000 ldmia.w sp!, {ip, lr} +1000142c: ec4e c402 dcp_wefd ip, lr +10001430: bd00 pop {pc} +10001432: 0000 movs r0, r0 +10001434: b500 push {lr} +10001436: f7ff ffdf bl 100013f8 +1000143a: e002 b.n 10001442 <__wrap___aeabi_dadd+0x6> + +1000143c <__wrap___aeabi_dadd>: +1000143c: fe10 f430 dcp_pcmp APSR_nzcv +10001440: d4f8 bmi.n 10001434 +10001442: ec41 0410 dcp_wxup r0, r1 +10001446: ec43 2411 dcp_wyup r2, r3 +1000144a: ee00 0401 dcp_add0 +1000144e: ee10 0401 dcp_add1 +10001452: ee80 0420 dcp_nrdd +10001456: ec51 0410 dcp_rdda r0, r1 +1000145a: 4770 bx lr +1000145c: b500 push {lr} +1000145e: f7ff ffcb bl 100013f8 +10001462: e002 b.n 1000146a <__wrap___aeabi_dsub+0x6> + +10001464 <__wrap___aeabi_dsub>: +10001464: fe10 f430 dcp_pcmp APSR_nzcv +10001468: d4f8 bmi.n 1000145c <__wrap___aeabi_dadd+0x20> +1000146a: ec41 0410 dcp_wxup r0, r1 +1000146e: ec43 2411 dcp_wyup r2, r3 +10001472: ee00 0401 dcp_add0 +10001476: ee10 0421 dcp_sub1 +1000147a: ee80 0420 dcp_nrdd +1000147e: ec51 0430 dcp_rdds r0, r1 +10001482: 4770 bx lr +10001484: b500 push {lr} +10001486: f7ff ffb7 bl 100013f8 +1000148a: e002 b.n 10001492 <__wrap___aeabi_dmul+0x6> + +1000148c <__wrap___aeabi_dmul>: +1000148c: fe10 f430 dcp_pcmp APSR_nzcv +10001490: d4f8 bmi.n 10001484 <__wrap___aeabi_dsub+0x20> +10001492: b510 push {r4, lr} +10001494: ec41 0410 dcp_wxup r0, r1 +10001498: ec43 2411 dcp_wyup r2, r3 +1000149c: ec51 0404 dcp_rxms r0, r1, #0x0 +100014a0: ec53 2405 dcp_ryms r2, r3, #0x0 +100014a4: fba0 4c02 umull r4, ip, r0, r2 +100014a8: f05f 0e00 movs.w lr, #0 +100014ac: fbe0 ce03 umlal ip, lr, r0, r3 +100014b0: fbe1 ce02 umlal ip, lr, r1, r2 +100014b4: ec4c 4420 dcp_wxms r4, ip +100014b8: 2400 movs r4, #0 +100014ba: fbe1 e403 umlal lr, r4, r1, r3 +100014be: ec44 e430 dcp_wxmo lr, r4 +100014c2: ee80 0420 dcp_nrdd +100014c6: ec51 0450 dcp_rddm r0, r1 +100014ca: e8bd 4010 ldmia.w sp!, {r4, lr} +100014ce: 4770 bx lr +100014d0: b500 push {lr} +100014d2: f7ff ff91 bl 100013f8 +100014d6: e002 b.n 100014de <__wrap___aeabi_ddiv+0x6> + +100014d8 <__wrap___aeabi_ddiv>: +100014d8: fe10 f430 dcp_pcmp APSR_nzcv +100014dc: d4f8 bmi.n 100014d0 <__wrap___aeabi_dmul+0x44> +100014de: ec41 0410 dcp_wxup r0, r1 +100014e2: ec43 2411 dcp_wyup r2, r3 +100014e6: ec51 0421 dcp_rymr r0, r1 +100014ea: fba0 1201 umull r1, r2, r0, r1 +100014ee: ea6f 0282 mvn.w r2, r2, lsl #2 +100014f2: fb52 0010 smmlar r0, r2, r0, r0 +100014f6: fb52 f212 smmulr r2, r2, r2 +100014fa: fb52 0010 smmlar r0, r2, r0, r0 +100014fe: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001502: ec53 2404 dcp_rxms r2, r3, #0x0 +10001506: fb5c f113 smmulr r1, ip, r3 +1000150a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000150e: fba1 2002 umull r2, r0, r1, r2 +10001512: fb01 0003 mla r0, r1, r3, r0 +10001516: ec53 2444 dcp_rxms r2, r3, #0x4 +1000151a: eba2 0000 sub.w r0, r2, r0 +1000151e: fb50 f21c smmulr r2, r0, ip +10001522: ea4f 1311 mov.w r3, r1, lsr #4 +10001526: eb12 7001 adds.w r0, r2, r1, lsl #28 +1000152a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1000152e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001532: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001536: f020 0007 bic.w r0, r0, #7 +1000153a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000153e: fba0 3c02 umull r3, ip, r0, r2 +10001542: ec53 2475 dcp_ryms r2, r3, #0x7 +10001546: fb00 cc03 mla ip, r0, r3, ip +1000154a: fb01 cc02 mla ip, r1, r2, ip +1000154e: ec53 2404 dcp_rxms r2, r3, #0x0 +10001552: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001556: ea40 705c orr.w r0, r0, ip, lsr #29 +1000155a: f1a0 0001 sub.w r0, r0, #1 +1000155e: ec41 0440 dcp_wxdd r0, r1 +10001562: ee80 0420 dcp_nrdd +10001566: ec51 0470 dcp_rddd r0, r1 +1000156a: 4770 bx lr +1000156c: b500 push {lr} +1000156e: f7ff ff43 bl 100013f8 +10001572: e002 b.n 1000157a <__wrap___aeabi_i2d+0x6> + +10001574 <__wrap___aeabi_i2d>: +10001574: fe10 f430 dcp_pcmp APSR_nzcv +10001578: d4f8 bmi.n 1000156c <__wrap___aeabi_ddiv+0x94> +1000157a: ec40 0470 dcp_wxic r0, r0 +1000157e: ee00 0401 dcp_add0 +10001582: ee10 0421 dcp_sub1 +10001586: ee80 0420 dcp_nrdd +1000158a: ec51 0430 dcp_rdds r0, r1 +1000158e: 4770 bx lr +10001590: b500 push {lr} +10001592: f7ff ff31 bl 100013f8 +10001596: e002 b.n 1000159e <__wrap___aeabi_ui2d+0x6> + +10001598 <__wrap___aeabi_ui2d>: +10001598: fe10 f430 dcp_pcmp APSR_nzcv +1000159c: d4f8 bmi.n 10001590 <__wrap___aeabi_i2d+0x1c> +1000159e: ec40 0460 dcp_wxuc r0, r0 +100015a2: ee00 0401 dcp_add0 +100015a6: ee10 0421 dcp_sub1 +100015aa: ee80 0420 dcp_nrdd +100015ae: ec51 0430 dcp_rdds r0, r1 +100015b2: 4770 bx lr +100015b4: b500 push {lr} +100015b6: f7ff ff1f bl 100013f8 +100015ba: e002 b.n 100015c2 + +100015bc <__wrap___aeabi_d2iz>: +100015bc: fe10 f430 dcp_pcmp APSR_nzcv +100015c0: d4f8 bmi.n 100015b4 <__wrap___aeabi_ui2d+0x1c> + +100015c2 : +100015c2: ec41 0480 dcp_wxdc r0, r1 +100015c6: ee00 0401 dcp_add0 +100015ca: ee10 0401 dcp_add1 +100015ce: ee80 0440 dcp_ntdc +100015d2: ee10 0413 dcp_rdic r0 +100015d6: 4770 bx lr +100015d8: b500 push {lr} +100015da: f7ff ff0d bl 100013f8 +100015de: e002 b.n 100015e6 + +100015e0 <__wrap___aeabi_d2uiz>: +100015e0: fe10 f430 dcp_pcmp APSR_nzcv +100015e4: d4f8 bmi.n 100015d8 + +100015e6 : +100015e6: ec41 0480 dcp_wxdc r0, r1 +100015ea: ee00 0401 dcp_add0 +100015ee: ee10 0401 dcp_add1 +100015f2: ee80 0440 dcp_ntdc +100015f6: ee10 0433 dcp_rduc r0 +100015fa: 4770 bx lr +100015fc: b500 push {lr} +100015fe: f7ff fefb bl 100013f8 +10001602: e002 b.n 1000160a <__wrap___aeabi_dcmpun+0x6> + +10001604 <__wrap___aeabi_dcmpun>: +10001604: fe10 f430 dcp_pcmp APSR_nzcv +10001608: d4f8 bmi.n 100015fc +1000160a: ec41 0410 dcp_wxup r0, r1 +1000160e: ec43 2411 dcp_wyup r2, r3 +10001612: ee00 0401 dcp_add0 +10001616: ee10 0430 dcp_rcmp r0 +1000161a: f3c0 7000 ubfx r0, r0, #28, #1 +1000161e: 4770 bx lr +10001620: b500 push {lr} +10001622: f7ff fee9 bl 100013f8 +10001626: e002 b.n 1000162e <__wrap___aeabi_dcmplt+0x6> + +10001628 <__wrap___aeabi_dcmplt>: +10001628: fe10 f430 dcp_pcmp APSR_nzcv +1000162c: d4f8 bmi.n 10001620 <__wrap___aeabi_dcmpun+0x1c> +1000162e: ec43 2410 dcp_wxup r2, r3 +10001632: ec41 0411 dcp_wyup r0, r1 +10001636: ee00 0401 dcp_add0 +1000163a: ee10 f430 dcp_rcmp APSR_nzcv +1000163e: bf8c ite hi +10001640: 2001 movhi r0, #1 +10001642: 2000 movls r0, #0 +10001644: 4770 bx lr +10001646: bf00 nop +10001648: b500 push {lr} +1000164a: f7ff fed5 bl 100013f8 +1000164e: e002 b.n 10001656 <__wrap___aeabi_dcmple+0x6> + +10001650 <__wrap___aeabi_dcmple>: +10001650: fe10 f430 dcp_pcmp APSR_nzcv +10001654: d4f8 bmi.n 10001648 <__wrap___aeabi_dcmplt+0x20> +10001656: ec43 2410 dcp_wxup r2, r3 +1000165a: ec41 0411 dcp_wyup r0, r1 +1000165e: ee00 0401 dcp_add0 +10001662: ee10 f430 dcp_rcmp APSR_nzcv +10001666: bf2c ite cs +10001668: 2001 movcs r0, #1 +1000166a: 2000 movcc r0, #0 +1000166c: 4770 bx lr +1000166e: bf00 nop +10001670: b500 push {lr} +10001672: f7ff fec1 bl 100013f8 +10001676: e002 b.n 1000167e <__wrap___aeabi_dcmpge+0x6> + +10001678 <__wrap___aeabi_dcmpge>: +10001678: fe10 f430 dcp_pcmp APSR_nzcv +1000167c: d4f8 bmi.n 10001670 <__wrap___aeabi_dcmple+0x20> +1000167e: ec41 0410 dcp_wxup r0, r1 +10001682: ec43 2411 dcp_wyup r2, r3 +10001686: ee00 0401 dcp_add0 +1000168a: ee10 f430 dcp_rcmp APSR_nzcv +1000168e: bf2c ite cs +10001690: 2001 movcs r0, #1 +10001692: 2000 movcc r0, #0 +10001694: 4770 bx lr +10001696: bf00 nop +10001698: b500 push {lr} +1000169a: f7ff fead bl 100013f8 +1000169e: e002 b.n 100016a6 <__wrap___aeabi_dcmpgt+0x6> + +100016a0 <__wrap___aeabi_dcmpgt>: +100016a0: fe10 f430 dcp_pcmp APSR_nzcv +100016a4: d4f8 bmi.n 10001698 <__wrap___aeabi_dcmpge+0x20> +100016a6: ec41 0410 dcp_wxup r0, r1 +100016aa: ec43 2411 dcp_wyup r2, r3 +100016ae: ee00 0401 dcp_add0 +100016b2: ee10 f430 dcp_rcmp APSR_nzcv +100016b6: bf8c ite hi +100016b8: 2001 movhi r0, #1 +100016ba: 2000 movls r0, #0 +100016bc: 4770 bx lr +100016be: bf00 nop + +100016c0 <_out_null>: +100016c0: 4770 bx lr +100016c2: bf00 nop + +100016c4 <_out_rev>: +100016c4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100016c8: b083 sub sp, #12 +100016ca: 4699 mov r9, r3 +100016cc: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +100016d0: 9b0f ldr r3, [sp, #60] @ 0x3c +100016d2: 4688 mov r8, r1 +100016d4: 4611 mov r1, r2 +100016d6: 079a lsls r2, r3, #30 +100016d8: 4607 mov r7, r0 +100016da: d116 bne.n 1000170a <_out_rev+0x46> +100016dc: 45da cmp sl, fp +100016de: d23a bcs.n 10001756 <_out_rev+0x92> +100016e0: 460c mov r4, r1 +100016e2: 460d mov r5, r1 +100016e4: ebab 060a sub.w r6, fp, sl +100016e8: 440e add r6, r1 +100016ea: 4622 mov r2, r4 +100016ec: 464b mov r3, r9 +100016ee: 4641 mov r1, r8 +100016f0: 2020 movs r0, #32 +100016f2: 3401 adds r4, #1 +100016f4: 47b8 blx r7 +100016f6: 42b4 cmp r4, r6 +100016f8: d1f7 bne.n 100016ea <_out_rev+0x26> +100016fa: 4629 mov r1, r5 +100016fc: f1ba 0f00 cmp.w sl, #0 +10001700: d108 bne.n 10001714 <_out_rev+0x50> +10001702: 4620 mov r0, r4 +10001704: b003 add sp, #12 +10001706: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000170a: 460c mov r4, r1 +1000170c: f1ba 0f00 cmp.w sl, #0 +10001710: d010 beq.n 10001734 <_out_rev+0x70> +10001712: 460e mov r6, r1 +10001714: 4655 mov r5, sl +10001716: 9b0c ldr r3, [sp, #48] @ 0x30 +10001718: 442e add r6, r5 +1000171a: 449a add sl, r3 +1000171c: 9101 str r1, [sp, #4] +1000171e: 1b72 subs r2, r6, r5 +10001720: 464b mov r3, r9 +10001722: 3d01 subs r5, #1 +10001724: 4641 mov r1, r8 +10001726: f81a 0d01 ldrb.w r0, [sl, #-1]! +1000172a: 4634 mov r4, r6 +1000172c: 47b8 blx r7 +1000172e: 2d00 cmp r5, #0 +10001730: d1f5 bne.n 1000171e <_out_rev+0x5a> +10001732: 9901 ldr r1, [sp, #4] +10001734: 9b0f ldr r3, [sp, #60] @ 0x3c +10001736: 079b lsls r3, r3, #30 +10001738: d5e3 bpl.n 10001702 <_out_rev+0x3e> +1000173a: 1a65 subs r5, r4, r1 +1000173c: 45ab cmp fp, r5 +1000173e: d9e0 bls.n 10001702 <_out_rev+0x3e> +10001740: 4622 mov r2, r4 +10001742: 464b mov r3, r9 +10001744: 4641 mov r1, r8 +10001746: 2020 movs r0, #32 +10001748: 3501 adds r5, #1 +1000174a: 47b8 blx r7 +1000174c: 455d cmp r5, fp +1000174e: f104 0401 add.w r4, r4, #1 +10001752: d3f5 bcc.n 10001740 <_out_rev+0x7c> +10001754: e7d5 b.n 10001702 <_out_rev+0x3e> +10001756: 460c mov r4, r1 +10001758: f1ba 0f00 cmp.w sl, #0 +1000175c: d1d9 bne.n 10001712 <_out_rev+0x4e> +1000175e: e7d0 b.n 10001702 <_out_rev+0x3e> + +10001760 <_ntoa_format>: +10001760: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001764: 9f0f ldr r7, [sp, #60] @ 0x3c +10001766: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +1000176a: f017 0f02 tst.w r7, #2 +1000176e: 9c0a ldr r4, [sp, #40] @ 0x28 +10001770: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001774: 9d0e ldr r5, [sp, #56] @ 0x38 +10001776: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +1000177a: d144 bne.n 10001806 <_ntoa_format+0xa6> +1000177c: bbf5 cbnz r5, 100017fc <_ntoa_format+0x9c> +1000177e: 42b4 cmp r4, r6 +10001780: d241 bcs.n 10001806 <_ntoa_format+0xa6> +10001782: f007 0b01 and.w fp, r7, #1 +10001786: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +1000178a: f04f 0e30 mov.w lr, #48 @ 0x30 +1000178e: 44c4 add ip, r8 +10001790: e004 b.n 1000179c <_ntoa_format+0x3c> +10001792: 3401 adds r4, #1 +10001794: 42a6 cmp r6, r4 +10001796: f80c ef01 strb.w lr, [ip, #1]! +1000179a: d901 bls.n 100017a0 <_ntoa_format+0x40> +1000179c: 2c20 cmp r4, #32 +1000179e: d1f8 bne.n 10001792 <_ntoa_format+0x32> +100017a0: f1bb 0f00 cmp.w fp, #0 +100017a4: f000 8088 beq.w 100018b8 <_ntoa_format+0x158> +100017a8: 42a5 cmp r5, r4 +100017aa: d92c bls.n 10001806 <_ntoa_format+0xa6> +100017ac: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100017b0: f04f 0e30 mov.w lr, #48 @ 0x30 +100017b4: 44c4 add ip, r8 +100017b6: e004 b.n 100017c2 <_ntoa_format+0x62> +100017b8: 3401 adds r4, #1 +100017ba: 42ac cmp r4, r5 +100017bc: f80c ef01 strb.w lr, [ip, #1]! +100017c0: d021 beq.n 10001806 <_ntoa_format+0xa6> +100017c2: 2c20 cmp r4, #32 +100017c4: d1f8 bne.n 100017b8 <_ntoa_format+0x58> +100017c6: f017 0f10 tst.w r7, #16 +100017ca: d00e beq.n 100017ea <_ntoa_format+0x8a> +100017cc: f417 6f80 tst.w r7, #1024 @ 0x400 +100017d0: d154 bne.n 1000187c <_ntoa_format+0x11c> +100017d2: 42a6 cmp r6, r4 +100017d4: d063 beq.n 1000189e <_ntoa_format+0x13e> +100017d6: 42a5 cmp r5, r4 +100017d8: d061 beq.n 1000189e <_ntoa_format+0x13e> +100017da: f1b9 0f10 cmp.w r9, #16 +100017de: d050 beq.n 10001882 <_ntoa_format+0x122> +100017e0: f1b9 0f02 cmp.w r9, #2 +100017e4: d056 beq.n 10001894 <_ntoa_format+0x134> +100017e6: 2c20 cmp r4, #32 +100017e8: d129 bne.n 1000183e <_ntoa_format+0xde> +100017ea: 2420 movs r4, #32 +100017ec: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100017f0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100017f4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100017f8: f7ff bf64 b.w 100016c4 <_out_rev> +100017fc: f017 0b01 ands.w fp, r7, #1 +10001800: d134 bne.n 1000186c <_ntoa_format+0x10c> +10001802: 42b4 cmp r4, r6 +10001804: d3bf bcc.n 10001786 <_ntoa_format+0x26> +10001806: f017 0f10 tst.w r7, #16 +1000180a: d01e beq.n 1000184a <_ntoa_format+0xea> +1000180c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001810: d1e3 bne.n 100017da <_ntoa_format+0x7a> +10001812: 2c00 cmp r4, #0 +10001814: d1dd bne.n 100017d2 <_ntoa_format+0x72> +10001816: f1b9 0f10 cmp.w r9, #16 +1000181a: d063 beq.n 100018e4 <_ntoa_format+0x184> +1000181c: f1b9 0f02 cmp.w r9, #2 +10001820: d077 beq.n 10001912 <_ntoa_format+0x1b2> +10001822: 2430 movs r4, #48 @ 0x30 +10001824: f888 4000 strb.w r4, [r8] +10001828: 2401 movs r4, #1 +1000182a: f1ba 0f00 cmp.w sl, #0 +1000182e: d111 bne.n 10001854 <_ntoa_format+0xf4> +10001830: 077e lsls r6, r7, #29 +10001832: d548 bpl.n 100018c6 <_ntoa_format+0x166> +10001834: 262b movs r6, #43 @ 0x2b +10001836: f808 6004 strb.w r6, [r8, r4] +1000183a: 3401 adds r4, #1 +1000183c: e7d6 b.n 100017ec <_ntoa_format+0x8c> +1000183e: 4626 mov r6, r4 +10001840: 3401 adds r4, #1 +10001842: f04f 0c30 mov.w ip, #48 @ 0x30 +10001846: f808 c006 strb.w ip, [r8, r6] +1000184a: 2c20 cmp r4, #32 +1000184c: d0cd beq.n 100017ea <_ntoa_format+0x8a> +1000184e: f1ba 0f00 cmp.w sl, #0 +10001852: d0ed beq.n 10001830 <_ntoa_format+0xd0> +10001854: 262d movs r6, #45 @ 0x2d +10001856: f808 6004 strb.w r6, [r8, r4] +1000185a: 3401 adds r4, #1 +1000185c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001860: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001864: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001868: f7ff bf2c b.w 100016c4 <_out_rev> +1000186c: f1ba 0f00 cmp.w sl, #0 +10001870: d030 beq.n 100018d4 <_ntoa_format+0x174> +10001872: 42b4 cmp r4, r6 +10001874: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001878: d385 bcc.n 10001786 <_ntoa_format+0x26> +1000187a: e795 b.n 100017a8 <_ntoa_format+0x48> +1000187c: f1b9 0f10 cmp.w r9, #16 +10001880: d1b3 bne.n 100017ea <_ntoa_format+0x8a> +10001882: 06be lsls r6, r7, #26 +10001884: d53b bpl.n 100018fe <_ntoa_format+0x19e> +10001886: 2c20 cmp r4, #32 +10001888: d0af beq.n 100017ea <_ntoa_format+0x8a> +1000188a: 2658 movs r6, #88 @ 0x58 +1000188c: f808 6004 strb.w r6, [r8, r4] +10001890: 3401 adds r4, #1 +10001892: e7a8 b.n 100017e6 <_ntoa_format+0x86> +10001894: 2c20 cmp r4, #32 +10001896: d0a8 beq.n 100017ea <_ntoa_format+0x8a> +10001898: 4626 mov r6, r4 +1000189a: 3401 adds r4, #1 +1000189c: e007 b.n 100018ae <_ntoa_format+0x14e> +1000189e: 1e66 subs r6, r4, #1 +100018a0: d0b9 beq.n 10001816 <_ntoa_format+0xb6> +100018a2: f1b9 0f10 cmp.w r9, #16 +100018a6: d036 beq.n 10001916 <_ntoa_format+0x1b6> +100018a8: f1b9 0f02 cmp.w r9, #2 +100018ac: d1c9 bne.n 10001842 <_ntoa_format+0xe2> +100018ae: f04f 0c62 mov.w ip, #98 @ 0x62 +100018b2: f808 c006 strb.w ip, [r8, r6] +100018b6: e796 b.n 100017e6 <_ntoa_format+0x86> +100018b8: f017 0f10 tst.w r7, #16 +100018bc: d0c5 beq.n 1000184a <_ntoa_format+0xea> +100018be: f417 6f80 tst.w r7, #1024 @ 0x400 +100018c2: d086 beq.n 100017d2 <_ntoa_format+0x72> +100018c4: e789 b.n 100017da <_ntoa_format+0x7a> +100018c6: 073e lsls r6, r7, #28 +100018c8: d590 bpl.n 100017ec <_ntoa_format+0x8c> +100018ca: 2620 movs r6, #32 +100018cc: f808 6004 strb.w r6, [r8, r4] +100018d0: 3401 adds r4, #1 +100018d2: e78b b.n 100017ec <_ntoa_format+0x8c> +100018d4: f017 0f0c tst.w r7, #12 +100018d8: d000 beq.n 100018dc <_ntoa_format+0x17c> +100018da: 3d01 subs r5, #1 +100018dc: 42b4 cmp r4, r6 +100018de: f4ff af52 bcc.w 10001786 <_ntoa_format+0x26> +100018e2: e761 b.n 100017a8 <_ntoa_format+0x48> +100018e4: 06bc lsls r4, r7, #26 +100018e6: d412 bmi.n 1000190e <_ntoa_format+0x1ae> +100018e8: 2478 movs r4, #120 @ 0x78 +100018ea: f888 4000 strb.w r4, [r8] +100018ee: 2430 movs r4, #48 @ 0x30 +100018f0: f888 4001 strb.w r4, [r8, #1] +100018f4: 2402 movs r4, #2 +100018f6: f1ba 0f00 cmp.w sl, #0 +100018fa: d099 beq.n 10001830 <_ntoa_format+0xd0> +100018fc: e7aa b.n 10001854 <_ntoa_format+0xf4> +100018fe: 2c20 cmp r4, #32 +10001900: f43f af73 beq.w 100017ea <_ntoa_format+0x8a> +10001904: 2678 movs r6, #120 @ 0x78 +10001906: f808 6004 strb.w r6, [r8, r4] +1000190a: 3401 adds r4, #1 +1000190c: e76b b.n 100017e6 <_ntoa_format+0x86> +1000190e: 2458 movs r4, #88 @ 0x58 +10001910: e7eb b.n 100018ea <_ntoa_format+0x18a> +10001912: 2462 movs r4, #98 @ 0x62 +10001914: e7e9 b.n 100018ea <_ntoa_format+0x18a> +10001916: f017 0f20 tst.w r7, #32 +1000191a: f1a4 0c02 sub.w ip, r4, #2 +1000191e: d004 beq.n 1000192a <_ntoa_format+0x1ca> +10001920: f04f 0e58 mov.w lr, #88 @ 0x58 +10001924: f808 e00c strb.w lr, [r8, ip] +10001928: e78b b.n 10001842 <_ntoa_format+0xe2> +1000192a: f04f 0e78 mov.w lr, #120 @ 0x78 +1000192e: f808 e00c strb.w lr, [r8, ip] +10001932: e786 b.n 10001842 <_ntoa_format+0xe2> + +10001934 <_out_char>: +10001934: b900 cbnz r0, 10001938 <_out_char+0x4> +10001936: 4770 bx lr +10001938: f001 bb72 b.w 10003020 <__wrap_putchar> + +1000193c <_out_fct>: +1000193c: b110 cbz r0, 10001944 <_out_fct+0x8> +1000193e: e9d1 3100 ldrd r3, r1, [r1] +10001942: 4718 bx r3 +10001944: 4770 bx lr +10001946: bf00 nop + +10001948 <_ftoa>: +10001948: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000194c: b097 sub sp, #92 @ 0x5c +1000194e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001952: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001956: 4607 mov r7, r0 +10001958: 4688 mov r8, r1 +1000195a: ec51 0b17 vmov r0, r1, d7 +1000195e: 9c24 ldr r4, [sp, #144] @ 0x90 +10001960: 4699 mov r9, r3 +10001962: 920c str r2, [sp, #48] @ 0x30 +10001964: 460b mov r3, r1 +10001966: 4602 mov r2, r0 +10001968: ed8d 7b04 vstr d7, [sp, #16] +1000196c: 9407 str r4, [sp, #28] +1000196e: f7ff fe49 bl 10001604 <__wrap___aeabi_dcmpun> +10001972: 2800 cmp r0, #0 +10001974: f040 81f4 bne.w 10001d60 <_ftoa+0x418> +10001978: e9dd 0104 ldrd r0, r1, [sp, #16] +1000197c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001980: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001984: f7ff fe50 bl 10001628 <__wrap___aeabi_dcmplt> +10001988: 2800 cmp r0, #0 +1000198a: f040 811b bne.w 10001bc4 <_ftoa+0x27c> +1000198e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001992: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001996: 4bac ldr r3, [pc, #688] @ (10001c48 <_ftoa+0x300>) +10001998: f7ff fe82 bl 100016a0 <__wrap___aeabi_dcmpgt> +1000199c: 2800 cmp r0, #0 +1000199e: f040 80ee bne.w 10001b7e <_ftoa+0x236> +100019a2: e9dd 0104 ldrd r0, r1, [sp, #16] +100019a6: a3a4 add r3, pc, #656 @ (adr r3, 10001c38 <_ftoa+0x2f0>) +100019a8: e9d3 2300 ldrd r2, r3, [r3] +100019ac: f7ff fe78 bl 100016a0 <__wrap___aeabi_dcmpgt> +100019b0: 2800 cmp r0, #0 +100019b2: f040 80d3 bne.w 10001b5c <_ftoa+0x214> +100019b6: e9dd 0104 ldrd r0, r1, [sp, #16] +100019ba: a3a1 add r3, pc, #644 @ (adr r3, 10001c40 <_ftoa+0x2f8>) +100019bc: e9d3 2300 ldrd r2, r3, [r3] +100019c0: f7ff fe32 bl 10001628 <__wrap___aeabi_dcmplt> +100019c4: 2800 cmp r0, #0 +100019c6: f040 80c9 bne.w 10001b5c <_ftoa+0x214> +100019ca: e9dd 0104 ldrd r0, r1, [sp, #16] +100019ce: 2200 movs r2, #0 +100019d0: 2300 movs r3, #0 +100019d2: f7ff fe29 bl 10001628 <__wrap___aeabi_dcmplt> +100019d6: 2800 cmp r0, #0 +100019d8: f040 80e8 bne.w 10001bac <_ftoa+0x264> +100019dc: 4623 mov r3, r4 +100019de: 900d str r0, [sp, #52] @ 0x34 +100019e0: f413 6f80 tst.w r3, #1024 @ 0x400 +100019e4: bf08 it eq +100019e6: 2506 moveq r5, #6 +100019e8: 2130 movs r1, #48 @ 0x30 +100019ea: 462b mov r3, r5 +100019ec: aa0e add r2, sp, #56 @ 0x38 +100019ee: f1a5 0620 sub.w r6, r5, #32 +100019f2: e005 b.n 10001a00 <_ftoa+0xb8> +100019f4: 3b01 subs r3, #1 +100019f6: 42b3 cmp r3, r6 +100019f8: f802 1b01 strb.w r1, [r2], #1 +100019fc: f000 8193 beq.w 10001d26 <_ftoa+0x3de> +10001a00: 2b09 cmp r3, #9 +10001a02: d8f7 bhi.n 100019f4 <_ftoa+0xac> +10001a04: 461e mov r6, r3 +10001a06: 1aed subs r5, r5, r3 +10001a08: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a0c: f7ff fdd6 bl 100015bc <__wrap___aeabi_d2iz> +10001a10: 4b8e ldr r3, [pc, #568] @ (10001c4c <_ftoa+0x304>) +10001a12: 4604 mov r4, r0 +10001a14: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001a18: ed93 7b00 vldr d7, [r3] +10001a1c: ed8d 7b08 vstr d7, [sp, #32] +10001a20: f7ff fda8 bl 10001574 <__wrap___aeabi_i2d> +10001a24: 4602 mov r2, r0 +10001a26: 460b mov r3, r1 +10001a28: e9dd 0104 ldrd r0, r1, [sp, #16] +10001a2c: f7ff fd1a bl 10001464 <__wrap___aeabi_dsub> +10001a30: e9dd 2308 ldrd r2, r3, [sp, #32] +10001a34: f7ff fd2a bl 1000148c <__wrap___aeabi_dmul> +10001a38: 4602 mov r2, r0 +10001a3a: 460b mov r3, r1 +10001a3c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001a40: f7ff fdce bl 100015e0 <__wrap___aeabi_d2uiz> +10001a44: 4682 mov sl, r0 +10001a46: f7ff fda7 bl 10001598 <__wrap___aeabi_ui2d> +10001a4a: 4602 mov r2, r0 +10001a4c: 460b mov r3, r1 +10001a4e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001a52: f7ff fd07 bl 10001464 <__wrap___aeabi_dsub> +10001a56: 4602 mov r2, r0 +10001a58: 460b mov r3, r1 +10001a5a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001a5e: 2200 movs r2, #0 +10001a60: 4b7b ldr r3, [pc, #492] @ (10001c50 <_ftoa+0x308>) +10001a62: f7ff fe1d bl 100016a0 <__wrap___aeabi_dcmpgt> +10001a66: 2800 cmp r0, #0 +10001a68: f000 80fe beq.w 10001c68 <_ftoa+0x320> +10001a6c: f10a 0a01 add.w sl, sl, #1 +10001a70: 4650 mov r0, sl +10001a72: f7ff fd91 bl 10001598 <__wrap___aeabi_ui2d> +10001a76: 4602 mov r2, r0 +10001a78: 460b mov r3, r1 +10001a7a: e9dd 0108 ldrd r0, r1, [sp, #32] +10001a7e: f7ff fde7 bl 10001650 <__wrap___aeabi_dcmple> +10001a82: b110 cbz r0, 10001a8a <_ftoa+0x142> +10001a84: f04f 0a00 mov.w sl, #0 +10001a88: 3401 adds r4, #1 +10001a8a: 2e00 cmp r6, #0 +10001a8c: f000 80fd beq.w 10001c8a <_ftoa+0x342> +10001a90: 1e68 subs r0, r5, #1 +10001a92: ab0e add r3, sp, #56 @ 0x38 +10001a94: f8df c1cc ldr.w ip, [pc, #460] @ 10001c64 <_ftoa+0x31c> +10001a98: 4418 add r0, r3 +10001a9a: e00f b.n 10001abc <_ftoa+0x174> +10001a9c: fbac 210a umull r2, r1, ip, sl +10001aa0: 08c9 lsrs r1, r1, #3 +10001aa2: eb01 0281 add.w r2, r1, r1, lsl #2 +10001aa6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001aaa: 3230 adds r2, #48 @ 0x30 +10001aac: f1ba 0f09 cmp.w sl, #9 +10001ab0: f800 2f01 strb.w r2, [r0, #1]! +10001ab4: f240 811c bls.w 10001cf0 <_ftoa+0x3a8> +10001ab8: 468a mov sl, r1 +10001aba: 461d mov r5, r3 +10001abc: 2d20 cmp r5, #32 +10001abe: f105 0301 add.w r3, r5, #1 +10001ac2: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001ac6: d1e9 bne.n 10001a9c <_ftoa+0x154> +10001ac8: 2520 movs r5, #32 +10001aca: 1e69 subs r1, r5, #1 +10001acc: ab0e add r3, sp, #56 @ 0x38 +10001ace: 4861 ldr r0, [pc, #388] @ (10001c54 <_ftoa+0x30c>) +10001ad0: 4419 add r1, r3 +10001ad2: e010 b.n 10001af6 <_ftoa+0x1ae> +10001ad4: fb80 6204 smull r6, r2, r0, r4 +10001ad8: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001adc: eb03 0283 add.w r2, r3, r3, lsl #2 +10001ae0: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001ae4: f104 0230 add.w r2, r4, #48 @ 0x30 +10001ae8: 3501 adds r5, #1 +10001aea: 461c mov r4, r3 +10001aec: f801 2f01 strb.w r2, [r1, #1]! +10001af0: 2b00 cmp r3, #0 +10001af2: f000 80eb beq.w 10001ccc <_ftoa+0x384> +10001af6: 2d20 cmp r5, #32 +10001af8: ea4f 73e4 mov.w r3, r4, asr #31 +10001afc: d1ea bne.n 10001ad4 <_ftoa+0x18c> +10001afe: 9b07 ldr r3, [sp, #28] +10001b00: f003 0303 and.w r3, r3, #3 +10001b04: 2b01 cmp r3, #1 +10001b06: d118 bne.n 10001b3a <_ftoa+0x1f2> +10001b08: f1bb 0f00 cmp.w fp, #0 +10001b0c: d015 beq.n 10001b3a <_ftoa+0x1f2> +10001b0e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001b10: 2b00 cmp r3, #0 +10001b12: f000 810a beq.w 10001d2a <_ftoa+0x3e2> +10001b16: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001b1a: f1bb 0f20 cmp.w fp, #32 +10001b1e: d90c bls.n 10001b3a <_ftoa+0x1f2> +10001b20: 1e6b subs r3, r5, #1 +10001b22: a90e add r1, sp, #56 @ 0x38 +10001b24: 2230 movs r2, #48 @ 0x30 +10001b26: 440b add r3, r1 +10001b28: e005 b.n 10001b36 <_ftoa+0x1ee> +10001b2a: 3501 adds r5, #1 +10001b2c: 455d cmp r5, fp +10001b2e: f803 2f01 strb.w r2, [r3, #1]! +10001b32: f080 80d1 bcs.w 10001cd8 <_ftoa+0x390> +10001b36: 2d20 cmp r5, #32 +10001b38: d1f7 bne.n 10001b2a <_ftoa+0x1e2> +10001b3a: 9b07 ldr r3, [sp, #28] +10001b3c: ac0e add r4, sp, #56 @ 0x38 +10001b3e: e9cd b302 strd fp, r3, [sp, #8] +10001b42: 4641 mov r1, r8 +10001b44: 464b mov r3, r9 +10001b46: 4638 mov r0, r7 +10001b48: 9a0c ldr r2, [sp, #48] @ 0x30 +10001b4a: 9501 str r5, [sp, #4] +10001b4c: 9400 str r4, [sp, #0] +10001b4e: f7ff fdb9 bl 100016c4 <_out_rev> +10001b52: 4682 mov sl, r0 +10001b54: 4650 mov r0, sl +10001b56: b017 add sp, #92 @ 0x5c +10001b58: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001b5c: 9b07 ldr r3, [sp, #28] +10001b5e: ed9d 7b04 vldr d7, [sp, #16] +10001b62: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001b66: 4641 mov r1, r8 +10001b68: 464b mov r3, r9 +10001b6a: 4638 mov r0, r7 +10001b6c: 9a0c ldr r2, [sp, #48] @ 0x30 +10001b6e: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001b72: 9522 str r5, [sp, #136] @ 0x88 +10001b74: b017 add sp, #92 @ 0x5c +10001b76: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b7a: f000 b945 b.w 10001e08 <_etoa> +10001b7e: 0761 lsls r1, r4, #29 +10001b80: 4623 mov r3, r4 +10001b82: bf4c ite mi +10001b84: 2304 movmi r3, #4 +10001b86: 2303 movpl r3, #3 +10001b88: 4641 mov r1, r8 +10001b8a: 9321 str r3, [sp, #132] @ 0x84 +10001b8c: 4638 mov r0, r7 +10001b8e: 464b mov r3, r9 +10001b90: 9a07 ldr r2, [sp, #28] +10001b92: bf48 it mi +10001b94: 4c30 ldrmi r4, [pc, #192] @ (10001c58 <_ftoa+0x310>) +10001b96: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001b9a: bf58 it pl +10001b9c: 4c2f ldrpl r4, [pc, #188] @ (10001c5c <_ftoa+0x314>) +10001b9e: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ba0: 9420 str r4, [sp, #128] @ 0x80 +10001ba2: b017 add sp, #92 @ 0x5c +10001ba4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ba8: f7ff bd8c b.w 100016c4 <_out_rev> +10001bac: e9dd 2304 ldrd r2, r3, [sp, #16] +10001bb0: 2000 movs r0, #0 +10001bb2: 2100 movs r1, #0 +10001bb4: f7ff fc56 bl 10001464 <__wrap___aeabi_dsub> +10001bb8: 2301 movs r3, #1 +10001bba: e9cd 0104 strd r0, r1, [sp, #16] +10001bbe: 930d str r3, [sp, #52] @ 0x34 +10001bc0: 4623 mov r3, r4 +10001bc2: e70d b.n 100019e0 <_ftoa+0x98> +10001bc4: 4623 mov r3, r4 +10001bc6: 079c lsls r4, r3, #30 +10001bc8: f040 80aa bne.w 10001d20 <_ftoa+0x3d8> +10001bcc: f1bb 0f04 cmp.w fp, #4 +10001bd0: f240 80a6 bls.w 10001d20 <_ftoa+0x3d8> +10001bd4: 9b0c ldr r3, [sp, #48] @ 0x30 +10001bd6: 461d mov r5, r3 +10001bd8: 1f1c subs r4, r3, #4 +10001bda: eb04 0a0b add.w sl, r4, fp +10001bde: 462a mov r2, r5 +10001be0: 464b mov r3, r9 +10001be2: 4641 mov r1, r8 +10001be4: 2020 movs r0, #32 +10001be6: 3501 adds r5, #1 +10001be8: 47b8 blx r7 +10001bea: 45aa cmp sl, r5 +10001bec: d1f7 bne.n 10001bde <_ftoa+0x296> +10001bee: 4655 mov r5, sl +10001bf0: 4c1b ldr r4, [pc, #108] @ (10001c60 <_ftoa+0x318>) +10001bf2: 1f26 subs r6, r4, #4 +10001bf4: f814 0d01 ldrb.w r0, [r4, #-1]! +10001bf8: 462a mov r2, r5 +10001bfa: 464b mov r3, r9 +10001bfc: 4641 mov r1, r8 +10001bfe: 47b8 blx r7 +10001c00: 42b4 cmp r4, r6 +10001c02: f105 0501 add.w r5, r5, #1 +10001c06: d1f5 bne.n 10001bf4 <_ftoa+0x2ac> +10001c08: 9b07 ldr r3, [sp, #28] +10001c0a: f10a 0a04 add.w sl, sl, #4 +10001c0e: 0798 lsls r0, r3, #30 +10001c10: d5a0 bpl.n 10001b54 <_ftoa+0x20c> +10001c12: 9c0c ldr r4, [sp, #48] @ 0x30 +10001c14: ebaa 0304 sub.w r3, sl, r4 +10001c18: 459b cmp fp, r3 +10001c1a: d99b bls.n 10001b54 <_ftoa+0x20c> +10001c1c: 4652 mov r2, sl +10001c1e: 464b mov r3, r9 +10001c20: 4641 mov r1, r8 +10001c22: 2020 movs r0, #32 +10001c24: f10a 0a01 add.w sl, sl, #1 +10001c28: 47b8 blx r7 +10001c2a: ebaa 0304 sub.w r3, sl, r4 +10001c2e: 455b cmp r3, fp +10001c30: d3f4 bcc.n 10001c1c <_ftoa+0x2d4> +10001c32: e78f b.n 10001b54 <_ftoa+0x20c> +10001c34: f3af 8000 nop.w +10001c38: 00000000 .word 0x00000000 +10001c3c: 41cdcd65 .word 0x41cdcd65 +10001c40: 00000000 .word 0x00000000 +10001c44: c1cdcd65 .word 0xc1cdcd65 +10001c48: 7fefffff .word 0x7fefffff +10001c4c: 100036c8 .word 0x100036c8 +10001c50: 3fe00000 .word 0x3fe00000 +10001c54: 66666667 .word 0x66666667 +10001c58: 10003624 .word 0x10003624 +10001c5c: 1000362c .word 0x1000362c +10001c60: 10003638 .word 0x10003638 +10001c64: cccccccd .word 0xcccccccd +10001c68: 2200 movs r2, #0 +10001c6a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001c6e: 4b63 ldr r3, [pc, #396] @ (10001dfc <_ftoa+0x4b4>) +10001c70: f7ff fcda bl 10001628 <__wrap___aeabi_dcmplt> +10001c74: 2800 cmp r0, #0 +10001c76: f47f af08 bne.w 10001a8a <_ftoa+0x142> +10001c7a: f1ba 0f00 cmp.w sl, #0 +10001c7e: d16a bne.n 10001d56 <_ftoa+0x40e> +10001c80: f10a 0a01 add.w sl, sl, #1 +10001c84: 2e00 cmp r6, #0 +10001c86: f47f af03 bne.w 10001a90 <_ftoa+0x148> +10001c8a: 4620 mov r0, r4 +10001c8c: f7ff fc72 bl 10001574 <__wrap___aeabi_i2d> +10001c90: 4602 mov r2, r0 +10001c92: 460b mov r3, r1 +10001c94: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c98: f7ff fbe4 bl 10001464 <__wrap___aeabi_dsub> +10001c9c: 4602 mov r2, r0 +10001c9e: 460b mov r3, r1 +10001ca0: e9cd 2304 strd r2, r3, [sp, #16] +10001ca4: 2200 movs r2, #0 +10001ca6: 4b55 ldr r3, [pc, #340] @ (10001dfc <_ftoa+0x4b4>) +10001ca8: f7ff fcbe bl 10001628 <__wrap___aeabi_dcmplt> +10001cac: 2800 cmp r0, #0 +10001cae: f47f af0c bne.w 10001aca <_ftoa+0x182> +10001cb2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001cb6: 2200 movs r2, #0 +10001cb8: 4b50 ldr r3, [pc, #320] @ (10001dfc <_ftoa+0x4b4>) +10001cba: f7ff fcf1 bl 100016a0 <__wrap___aeabi_dcmpgt> +10001cbe: 2800 cmp r0, #0 +10001cc0: f47f af03 bne.w 10001aca <_ftoa+0x182> +10001cc4: 3401 adds r4, #1 +10001cc6: f024 0401 bic.w r4, r4, #1 +10001cca: e6fe b.n 10001aca <_ftoa+0x182> +10001ccc: 9b07 ldr r3, [sp, #28] +10001cce: f003 0303 and.w r3, r3, #3 +10001cd2: 2b01 cmp r3, #1 +10001cd4: f000 8082 beq.w 10001ddc <_ftoa+0x494> +10001cd8: 2d20 cmp r5, #32 +10001cda: f43f af2e beq.w 10001b3a <_ftoa+0x1f2> +10001cde: 9b0d ldr r3, [sp, #52] @ 0x34 +10001ce0: b37b cbz r3, 10001d42 <_ftoa+0x3fa> +10001ce2: 222d movs r2, #45 @ 0x2d +10001ce4: eb0d 0305 add.w r3, sp, r5 +10001ce8: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001cec: 3501 adds r5, #1 +10001cee: e724 b.n 10001b3a <_ftoa+0x1f2> +10001cf0: 2b20 cmp r3, #32 +10001cf2: f43f aee9 beq.w 10001ac8 <_ftoa+0x180> +10001cf6: aa0e add r2, sp, #56 @ 0x38 +10001cf8: 4415 add r5, r2 +10001cfa: 441e add r6, r3 +10001cfc: 2230 movs r2, #48 @ 0x30 +10001cfe: e004 b.n 10001d0a <_ftoa+0x3c2> +10001d00: 2b20 cmp r3, #32 +10001d02: f805 2f01 strb.w r2, [r5, #1]! +10001d06: f43f aedf beq.w 10001ac8 <_ftoa+0x180> +10001d0a: 429e cmp r6, r3 +10001d0c: f103 0301 add.w r3, r3, #1 +10001d10: d1f6 bne.n 10001d00 <_ftoa+0x3b8> +10001d12: 222e movs r2, #46 @ 0x2e +10001d14: eb0d 0306 add.w r3, sp, r6 +10001d18: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001d1c: 1c75 adds r5, r6, #1 +10001d1e: e6d4 b.n 10001aca <_ftoa+0x182> +10001d20: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001d24: e763 b.n 10001bee <_ftoa+0x2a6> +10001d26: 2520 movs r5, #32 +10001d28: e66e b.n 10001a08 <_ftoa+0xc0> +10001d2a: 9b07 ldr r3, [sp, #28] +10001d2c: f013 0f0c tst.w r3, #12 +10001d30: d050 beq.n 10001dd4 <_ftoa+0x48c> +10001d32: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d36: 45ab cmp fp, r5 +10001d38: f63f aef2 bhi.w 10001b20 <_ftoa+0x1d8> +10001d3c: 2d20 cmp r5, #32 +10001d3e: f43f aefc beq.w 10001b3a <_ftoa+0x1f2> +10001d42: 9b07 ldr r3, [sp, #28] +10001d44: 075a lsls r2, r3, #29 +10001d46: d501 bpl.n 10001d4c <_ftoa+0x404> +10001d48: 222b movs r2, #43 @ 0x2b +10001d4a: e7cb b.n 10001ce4 <_ftoa+0x39c> +10001d4c: 071b lsls r3, r3, #28 +10001d4e: f57f aef4 bpl.w 10001b3a <_ftoa+0x1f2> +10001d52: 2220 movs r2, #32 +10001d54: e7c6 b.n 10001ce4 <_ftoa+0x39c> +10001d56: f01a 0f01 tst.w sl, #1 +10001d5a: f43f ae96 beq.w 10001a8a <_ftoa+0x142> +10001d5e: e78f b.n 10001c80 <_ftoa+0x338> +10001d60: 07a6 lsls r6, r4, #30 +10001d62: d134 bne.n 10001dce <_ftoa+0x486> +10001d64: f1bb 0f03 cmp.w fp, #3 +10001d68: d931 bls.n 10001dce <_ftoa+0x486> +10001d6a: 9b0c ldr r3, [sp, #48] @ 0x30 +10001d6c: 461d mov r5, r3 +10001d6e: 1edc subs r4, r3, #3 +10001d70: eb04 0a0b add.w sl, r4, fp +10001d74: 462a mov r2, r5 +10001d76: 464b mov r3, r9 +10001d78: 4641 mov r1, r8 +10001d7a: 2020 movs r0, #32 +10001d7c: 3501 adds r5, #1 +10001d7e: 47b8 blx r7 +10001d80: 4555 cmp r5, sl +10001d82: d1f7 bne.n 10001d74 <_ftoa+0x42c> +10001d84: 4655 mov r5, sl +10001d86: 4c1e ldr r4, [pc, #120] @ (10001e00 <_ftoa+0x4b8>) +10001d88: 1ee6 subs r6, r4, #3 +10001d8a: f814 0d01 ldrb.w r0, [r4, #-1]! +10001d8e: 462a mov r2, r5 +10001d90: 464b mov r3, r9 +10001d92: 4641 mov r1, r8 +10001d94: 47b8 blx r7 +10001d96: 42a6 cmp r6, r4 +10001d98: f105 0501 add.w r5, r5, #1 +10001d9c: d1f5 bne.n 10001d8a <_ftoa+0x442> +10001d9e: 9b07 ldr r3, [sp, #28] +10001da0: f10a 0a03 add.w sl, sl, #3 +10001da4: 079d lsls r5, r3, #30 +10001da6: f57f aed5 bpl.w 10001b54 <_ftoa+0x20c> +10001daa: 9c0c ldr r4, [sp, #48] @ 0x30 +10001dac: ebaa 0304 sub.w r3, sl, r4 +10001db0: 459b cmp fp, r3 +10001db2: f67f aecf bls.w 10001b54 <_ftoa+0x20c> +10001db6: 4652 mov r2, sl +10001db8: 464b mov r3, r9 +10001dba: 4641 mov r1, r8 +10001dbc: 2020 movs r0, #32 +10001dbe: f10a 0a01 add.w sl, sl, #1 +10001dc2: 47b8 blx r7 +10001dc4: ebaa 0304 sub.w r3, sl, r4 +10001dc8: 459b cmp fp, r3 +10001dca: d8f4 bhi.n 10001db6 <_ftoa+0x46e> +10001dcc: e6c2 b.n 10001b54 <_ftoa+0x20c> +10001dce: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001dd2: e7d7 b.n 10001d84 <_ftoa+0x43c> +10001dd4: 45ab cmp fp, r5 +10001dd6: f63f aea3 bhi.w 10001b20 <_ftoa+0x1d8> +10001dda: e6ae b.n 10001b3a <_ftoa+0x1f2> +10001ddc: f1bb 0f00 cmp.w fp, #0 +10001de0: f43f af7a beq.w 10001cd8 <_ftoa+0x390> +10001de4: 9b0d ldr r3, [sp, #52] @ 0x34 +10001de6: 2b00 cmp r3, #0 +10001de8: d09f beq.n 10001d2a <_ftoa+0x3e2> +10001dea: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001dee: 455d cmp r5, fp +10001df0: f4ff ae96 bcc.w 10001b20 <_ftoa+0x1d8> +10001df4: 2d20 cmp r5, #32 +10001df6: f47f af74 bne.w 10001ce2 <_ftoa+0x39a> +10001dfa: e69e b.n 10001b3a <_ftoa+0x1f2> +10001dfc: 3fe00000 .word 0x3fe00000 +10001e00: 10003633 .word 0x10003633 +10001e04: 00000000 .word 0x00000000 + +10001e08 <_etoa>: +10001e08: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001e0c: b09f sub sp, #124 @ 0x7c +10001e0e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10001e10: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10001e14: 4607 mov r7, r0 +10001e16: 4693 mov fp, r2 +10001e18: 9108 str r1, [sp, #32] +10001e1a: 9309 str r3, [sp, #36] @ 0x24 +10001e1c: 4622 mov r2, r4 +10001e1e: 462b mov r3, r5 +10001e20: 4620 mov r0, r4 +10001e22: 4629 mov r1, r5 +10001e24: 960e str r6, [sp, #56] @ 0x38 +10001e26: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10001e2a: f7ff fbeb bl 10001604 <__wrap___aeabi_dcmpun> +10001e2e: 2800 cmp r0, #0 +10001e30: f040 80be bne.w 10001fb0 <_etoa+0x1a8> +10001e34: 4620 mov r0, r4 +10001e36: 4629 mov r1, r5 +10001e38: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001e3c: 4b78 ldr r3, [pc, #480] @ (10002020 <_etoa+0x218>) +10001e3e: f7ff fc2f bl 100016a0 <__wrap___aeabi_dcmpgt> +10001e42: 2800 cmp r0, #0 +10001e44: f040 80b4 bne.w 10001fb0 <_etoa+0x1a8> +10001e48: 4620 mov r0, r4 +10001e4a: 4629 mov r1, r5 +10001e4c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001e50: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001e54: f7ff fbe8 bl 10001628 <__wrap___aeabi_dcmplt> +10001e58: 2800 cmp r0, #0 +10001e5a: f040 80a9 bne.w 10001fb0 <_etoa+0x1a8> +10001e5e: 4620 mov r0, r4 +10001e60: 4629 mov r1, r5 +10001e62: 2200 movs r2, #0 +10001e64: 2300 movs r3, #0 +10001e66: f7ff fbdf bl 10001628 <__wrap___aeabi_dcmplt> +10001e6a: 2800 cmp r0, #0 +10001e6c: f040 81d5 bne.w 1000221a <_etoa+0x412> +10001e70: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10001e74: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10001e78: 4690 mov r8, r2 +10001e7a: 4699 mov r9, r3 +10001e7c: f406 6200 and.w r2, r6, #2048 @ 0x800 +10001e80: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10001e84: 920f str r2, [sp, #60] @ 0x3c +10001e86: 9313 str r3, [sp, #76] @ 0x4c +10001e88: f040 80a1 bne.w 10001fce <_etoa+0x1c6> +10001e8c: ea58 0309 orrs.w r3, r8, r9 +10001e90: f040 80ca bne.w 10002028 <_etoa+0x220> +10001e94: 2a00 cmp r2, #0 +10001e96: f040 81e3 bne.w 10002260 <_etoa+0x458> +10001e9a: 2306 movs r3, #6 +10001e9c: 930e str r3, [sp, #56] @ 0x38 +10001e9e: f016 0202 ands.w r2, r6, #2 +10001ea2: 9210 str r2, [sp, #64] @ 0x40 +10001ea4: f040 81d4 bne.w 10002250 <_etoa+0x448> +10001ea8: 4653 mov r3, sl +10001eaa: 2b04 cmp r3, #4 +10001eac: bf38 it cc +10001eae: 2304 movcc r3, #4 +10001eb0: 920c str r2, [sp, #48] @ 0x30 +10001eb2: 2204 movs r2, #4 +10001eb4: 3b04 subs r3, #4 +10001eb6: 9212 str r2, [sp, #72] @ 0x48 +10001eb8: 930f str r3, [sp, #60] @ 0x3c +10001eba: 4620 mov r0, r4 +10001ebc: 4629 mov r1, r5 +10001ebe: 2200 movs r2, #0 +10001ec0: 2300 movs r3, #0 +10001ec2: f7ff fbb1 bl 10001628 <__wrap___aeabi_dcmplt> +10001ec6: 2800 cmp r0, #0 +10001ec8: f040 81f3 bne.w 100022b2 <_etoa+0x4aa> +10001ecc: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10001ed0: 9b0f ldr r3, [sp, #60] @ 0x3c +10001ed2: 465a mov r2, fp +10001ed4: 9303 str r3, [sp, #12] +10001ed6: 9b0e ldr r3, [sp, #56] @ 0x38 +10001ed8: ed8d 7b00 vstr d7, [sp] +10001edc: 9302 str r3, [sp, #8] +10001ede: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10001ee2: 9304 str r3, [sp, #16] +10001ee4: 4638 mov r0, r7 +10001ee6: 9b09 ldr r3, [sp, #36] @ 0x24 +10001ee8: 9908 ldr r1, [sp, #32] +10001eea: f7ff fd2d bl 10001948 <_ftoa> +10001eee: 4602 mov r2, r0 +10001ef0: f016 0f20 tst.w r6, #32 +10001ef4: 9b09 ldr r3, [sp, #36] @ 0x24 +10001ef6: 9908 ldr r1, [sp, #32] +10001ef8: bf0c ite eq +10001efa: 2065 moveq r0, #101 @ 0x65 +10001efc: 2045 movne r0, #69 @ 0x45 +10001efe: f102 0801 add.w r8, r2, #1 +10001f02: 47b8 blx r7 +10001f04: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f06: 9b12 ldr r3, [sp, #72] @ 0x48 +10001f08: ac16 add r4, sp, #88 @ 0x58 +10001f0a: 1e5d subs r5, r3, #1 +10001f0c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10001f10: eba3 73e2 sub.w r3, r3, r2, asr #31 +10001f14: 0fd1 lsrs r1, r2, #31 +10001f16: 2600 movs r6, #0 +10001f18: 4622 mov r2, r4 +10001f1a: 4699 mov r9, r3 +10001f1c: f8df c104 ldr.w ip, [pc, #260] @ 10002024 <_etoa+0x21c> +10001f20: e001 b.n 10001f26 <_etoa+0x11e> +10001f22: 2e20 cmp r6, #32 +10001f24: d010 beq.n 10001f48 <_etoa+0x140> +10001f26: 46ce mov lr, r9 +10001f28: fbac 3009 umull r3, r0, ip, r9 +10001f2c: 08c0 lsrs r0, r0, #3 +10001f2e: eb00 0380 add.w r3, r0, r0, lsl #2 +10001f32: eba9 0343 sub.w r3, r9, r3, lsl #1 +10001f36: 3330 adds r3, #48 @ 0x30 +10001f38: f1be 0f09 cmp.w lr, #9 +10001f3c: 4681 mov r9, r0 +10001f3e: f106 0601 add.w r6, r6, #1 +10001f42: f802 3b01 strb.w r3, [r2], #1 +10001f46: d8ec bhi.n 10001f22 <_etoa+0x11a> +10001f48: 2305 movs r3, #5 +10001f4a: 2000 movs r0, #0 +10001f4c: 9306 str r3, [sp, #24] +10001f4e: 230a movs r3, #10 +10001f50: 9505 str r5, [sp, #20] +10001f52: 9400 str r4, [sp, #0] +10001f54: 9d09 ldr r5, [sp, #36] @ 0x24 +10001f56: 9c08 ldr r4, [sp, #32] +10001f58: 4642 mov r2, r8 +10001f5a: e9cd 3003 strd r3, r0, [sp, #12] +10001f5e: e9cd 6101 strd r6, r1, [sp, #4] +10001f62: 462b mov r3, r5 +10001f64: 4621 mov r1, r4 +10001f66: 4638 mov r0, r7 +10001f68: f7ff fbfa bl 10001760 <_ntoa_format> +10001f6c: 9a10 ldr r2, [sp, #64] @ 0x40 +10001f6e: 4680 mov r8, r0 +10001f70: b1d2 cbz r2, 10001fa8 <_etoa+0x1a0> +10001f72: eba0 060b sub.w r6, r0, fp +10001f76: 45b2 cmp sl, r6 +10001f78: d916 bls.n 10001fa8 <_etoa+0x1a0> +10001f7a: eb0b 0206 add.w r2, fp, r6 +10001f7e: 462b mov r3, r5 +10001f80: 4621 mov r1, r4 +10001f82: 2020 movs r0, #32 +10001f84: 3601 adds r6, #1 +10001f86: 47b8 blx r7 +10001f88: 45b2 cmp sl, r6 +10001f8a: d8f6 bhi.n 10001f7a <_etoa+0x172> +10001f8c: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10001f90: 4453 add r3, sl +10001f92: f1cb 0201 rsb r2, fp, #1 +10001f96: eba3 0308 sub.w r3, r3, r8 +10001f9a: 4442 add r2, r8 +10001f9c: 4592 cmp sl, r2 +10001f9e: bf38 it cc +10001fa0: 2300 movcc r3, #0 +10001fa2: f108 0801 add.w r8, r8, #1 +10001fa6: 4498 add r8, r3 +10001fa8: 4640 mov r0, r8 +10001faa: b01f add sp, #124 @ 0x7c +10001fac: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001fb0: 465a mov r2, fp +10001fb2: 4638 mov r0, r7 +10001fb4: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10001fb8: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10001fbc: 9c0e ldr r4, [sp, #56] @ 0x38 +10001fbe: 9b09 ldr r3, [sp, #36] @ 0x24 +10001fc0: 9908 ldr r1, [sp, #32] +10001fc2: 942a str r4, [sp, #168] @ 0xa8 +10001fc4: b01f add sp, #124 @ 0x7c +10001fc6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001fca: f7ff bcbd b.w 10001948 <_ftoa> +10001fce: ea58 0309 orrs.w r3, r8, r9 +10001fd2: d12b bne.n 1000202c <_etoa+0x224> +10001fd4: 2a00 cmp r2, #0 +10001fd6: f43f af62 beq.w 10001e9e <_etoa+0x96> +10001fda: 2300 movs r3, #0 +10001fdc: 930c str r3, [sp, #48] @ 0x30 +10001fde: 9b0e ldr r3, [sp, #56] @ 0x38 +10001fe0: 9a0c ldr r2, [sp, #48] @ 0x30 +10001fe2: 4293 cmp r3, r2 +10001fe4: f300 81b9 bgt.w 1000235a <_etoa+0x552> +10001fe8: f04f 0800 mov.w r8, #0 +10001fec: 4620 mov r0, r4 +10001fee: 4629 mov r1, r5 +10001ff0: 2200 movs r2, #0 +10001ff2: 2300 movs r3, #0 +10001ff4: f7ff fb18 bl 10001628 <__wrap___aeabi_dcmplt> +10001ff8: 2800 cmp r0, #0 +10001ffa: f040 8113 bne.w 10002224 <_etoa+0x41c> +10001ffe: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002002: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002006: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000200a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1000200e: 465a mov r2, fp +10002010: 4638 mov r0, r7 +10002012: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002016: 9b09 ldr r3, [sp, #36] @ 0x24 +10002018: 9908 ldr r1, [sp, #32] +1000201a: 962c str r6, [sp, #176] @ 0xb0 +1000201c: e7d2 b.n 10001fc4 <_etoa+0x1bc> +1000201e: bf00 nop +10002020: 7fefffff .word 0x7fefffff +10002024: cccccccd .word 0xcccccccd +10002028: 2306 movs r3, #6 +1000202a: 930e str r3, [sp, #56] @ 0x38 +1000202c: f3c9 500a ubfx r0, r9, #20, #11 +10002030: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10002034: f7ff fa9e bl 10001574 <__wrap___aeabi_i2d> +10002038: a3c1 add r3, pc, #772 @ (adr r3, 10002340 <_etoa+0x538>) +1000203a: e9d3 2300 ldrd r2, r3, [r3] +1000203e: f7ff fa25 bl 1000148c <__wrap___aeabi_dmul> +10002042: a3c1 add r3, pc, #772 @ (adr r3, 10002348 <_etoa+0x540>) +10002044: e9d3 2300 ldrd r2, r3, [r3] +10002048: f7ff f9f8 bl 1000143c <__wrap___aeabi_dadd> +1000204c: f3c9 0913 ubfx r9, r9, #0, #20 +10002050: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002054: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002058: 4640 mov r0, r8 +1000205a: 2200 movs r2, #0 +1000205c: 4bb2 ldr r3, [pc, #712] @ (10002328 <_etoa+0x520>) +1000205e: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10002062: f7ff f9ff bl 10001464 <__wrap___aeabi_dsub> +10002066: a3a4 add r3, pc, #656 @ (adr r3, 100022f8 <_etoa+0x4f0>) +10002068: e9d3 2300 ldrd r2, r3, [r3] +1000206c: f7ff fa0e bl 1000148c <__wrap___aeabi_dmul> +10002070: 4602 mov r2, r0 +10002072: 460b mov r3, r1 +10002074: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002078: f7ff f9e0 bl 1000143c <__wrap___aeabi_dadd> +1000207c: f7ff fa9e bl 100015bc <__wrap___aeabi_d2iz> +10002080: 900c str r0, [sp, #48] @ 0x30 +10002082: f7ff fa77 bl 10001574 <__wrap___aeabi_i2d> +10002086: a39e add r3, pc, #632 @ (adr r3, 10002300 <_etoa+0x4f8>) +10002088: e9d3 2300 ldrd r2, r3, [r3] +1000208c: 4680 mov r8, r0 +1000208e: 4689 mov r9, r1 +10002090: f7ff f9fc bl 1000148c <__wrap___aeabi_dmul> +10002094: 2200 movs r2, #0 +10002096: 4ba5 ldr r3, [pc, #660] @ (1000232c <_etoa+0x524>) +10002098: f7ff f9d0 bl 1000143c <__wrap___aeabi_dadd> +1000209c: f7ff fa8e bl 100015bc <__wrap___aeabi_d2iz> +100020a0: 4603 mov r3, r0 +100020a2: 4649 mov r1, r9 +100020a4: 4640 mov r0, r8 +100020a6: 9312 str r3, [sp, #72] @ 0x48 +100020a8: a397 add r3, pc, #604 @ (adr r3, 10002308 <_etoa+0x500>) +100020aa: e9d3 2300 ldrd r2, r3, [r3] +100020ae: f7ff f9ed bl 1000148c <__wrap___aeabi_dmul> +100020b2: 4680 mov r8, r0 +100020b4: 9812 ldr r0, [sp, #72] @ 0x48 +100020b6: 4689 mov r9, r1 +100020b8: f7ff fa5c bl 10001574 <__wrap___aeabi_i2d> +100020bc: a394 add r3, pc, #592 @ (adr r3, 10002310 <_etoa+0x508>) +100020be: e9d3 2300 ldrd r2, r3, [r3] +100020c2: f7ff f9e3 bl 1000148c <__wrap___aeabi_dmul> +100020c6: 4602 mov r2, r0 +100020c8: 460b mov r3, r1 +100020ca: 4640 mov r0, r8 +100020cc: 4649 mov r1, r9 +100020ce: f7ff f9c9 bl 10001464 <__wrap___aeabi_dsub> +100020d2: 4602 mov r2, r0 +100020d4: 460b mov r3, r1 +100020d6: 4680 mov r8, r0 +100020d8: 4689 mov r9, r1 +100020da: f7ff f9d7 bl 1000148c <__wrap___aeabi_dmul> +100020de: 4642 mov r2, r8 +100020e0: 464b mov r3, r9 +100020e2: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +100020e6: 4640 mov r0, r8 +100020e8: 4649 mov r1, r9 +100020ea: f7ff f9a7 bl 1000143c <__wrap___aeabi_dadd> +100020ee: 2200 movs r2, #0 +100020f0: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +100020f4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100020f8: 4b8d ldr r3, [pc, #564] @ (10002330 <_etoa+0x528>) +100020fa: f7ff f9ed bl 100014d8 <__wrap___aeabi_ddiv> +100020fe: 2200 movs r2, #0 +10002100: 4b8c ldr r3, [pc, #560] @ (10002334 <_etoa+0x52c>) +10002102: f7ff f99b bl 1000143c <__wrap___aeabi_dadd> +10002106: 4602 mov r2, r0 +10002108: 460b mov r3, r1 +1000210a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000210e: f7ff f9e3 bl 100014d8 <__wrap___aeabi_ddiv> +10002112: 2200 movs r2, #0 +10002114: 4b88 ldr r3, [pc, #544] @ (10002338 <_etoa+0x530>) +10002116: f7ff f991 bl 1000143c <__wrap___aeabi_dadd> +1000211a: 4602 mov r2, r0 +1000211c: 460b mov r3, r1 +1000211e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002122: f7ff f9d9 bl 100014d8 <__wrap___aeabi_ddiv> +10002126: 4642 mov r2, r8 +10002128: 464b mov r3, r9 +1000212a: 4680 mov r8, r0 +1000212c: 4689 mov r9, r1 +1000212e: 2000 movs r0, #0 +10002130: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002134: f7ff f996 bl 10001464 <__wrap___aeabi_dsub> +10002138: 4602 mov r2, r0 +1000213a: 460b mov r3, r1 +1000213c: 4640 mov r0, r8 +1000213e: 4649 mov r1, r9 +10002140: f7ff f97c bl 1000143c <__wrap___aeabi_dadd> +10002144: 4602 mov r2, r0 +10002146: 460b mov r3, r1 +10002148: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000214c: f7ff f9c4 bl 100014d8 <__wrap___aeabi_ddiv> +10002150: 2200 movs r2, #0 +10002152: 4b7a ldr r3, [pc, #488] @ (1000233c <_etoa+0x534>) +10002154: f7ff f972 bl 1000143c <__wrap___aeabi_dadd> +10002158: 9b12 ldr r3, [sp, #72] @ 0x48 +1000215a: 2200 movs r2, #0 +1000215c: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002160: ea4f 530c mov.w r3, ip, lsl #20 +10002164: f7ff f992 bl 1000148c <__wrap___aeabi_dmul> +10002168: 4680 mov r8, r0 +1000216a: 4689 mov r9, r1 +1000216c: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002170: 4642 mov r2, r8 +10002172: 464b mov r3, r9 +10002174: f7ff fa58 bl 10001628 <__wrap___aeabi_dcmplt> +10002178: b150 cbz r0, 10002190 <_etoa+0x388> +1000217a: 9b0c ldr r3, [sp, #48] @ 0x30 +1000217c: 4640 mov r0, r8 +1000217e: 3b01 subs r3, #1 +10002180: 4649 mov r1, r9 +10002182: 930c str r3, [sp, #48] @ 0x30 +10002184: 2200 movs r2, #0 +10002186: 4b6b ldr r3, [pc, #428] @ (10002334 <_etoa+0x52c>) +10002188: f7ff f9a6 bl 100014d8 <__wrap___aeabi_ddiv> +1000218c: 4680 mov r8, r0 +1000218e: 4689 mov r9, r1 +10002190: 9a0c ldr r2, [sp, #48] @ 0x30 +10002192: 4643 mov r3, r8 +10002194: 3263 adds r2, #99 @ 0x63 +10002196: 2ac6 cmp r2, #198 @ 0xc6 +10002198: f006 0202 and.w r2, r6, #2 +1000219c: 9210 str r2, [sp, #64] @ 0x40 +1000219e: 4649 mov r1, r9 +100021a0: 9a0f ldr r2, [sp, #60] @ 0x3c +100021a2: d82c bhi.n 100021fe <_etoa+0x3f6> +100021a4: 2a00 cmp r2, #0 +100021a6: d05e beq.n 10002266 <_etoa+0x45e> +100021a8: 2204 movs r2, #4 +100021aa: 9212 str r2, [sp, #72] @ 0x48 +100021ac: 430b orrs r3, r1 +100021ae: f43f af16 beq.w 10001fde <_etoa+0x1d6> +100021b2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100021b6: a358 add r3, pc, #352 @ (adr r3, 10002318 <_etoa+0x510>) +100021b8: e9d3 2300 ldrd r2, r3, [r3] +100021bc: f7ff fa5c bl 10001678 <__wrap___aeabi_dcmpge> +100021c0: b148 cbz r0, 100021d6 <_etoa+0x3ce> +100021c2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100021c6: a356 add r3, pc, #344 @ (adr r3, 10002320 <_etoa+0x518>) +100021c8: e9d3 2300 ldrd r2, r3, [r3] +100021cc: f7ff fa2c bl 10001628 <__wrap___aeabi_dcmplt> +100021d0: 2800 cmp r0, #0 +100021d2: f47f af04 bne.w 10001fde <_etoa+0x1d6> +100021d6: 9b0e ldr r3, [sp, #56] @ 0x38 +100021d8: 2b00 cmp r3, #0 +100021da: d050 beq.n 1000227e <_etoa+0x476> +100021dc: 9a13 ldr r2, [sp, #76] @ 0x4c +100021de: 2a00 cmp r2, #0 +100021e0: d07d beq.n 100022de <_etoa+0x4d6> +100021e2: 3b01 subs r3, #1 +100021e4: 930e str r3, [sp, #56] @ 0x38 +100021e6: 9b12 ldr r3, [sp, #72] @ 0x48 +100021e8: 459a cmp sl, r3 +100021ea: d905 bls.n 100021f8 <_etoa+0x3f0> +100021ec: 9b10 ldr r3, [sp, #64] @ 0x40 +100021ee: 2b00 cmp r3, #0 +100021f0: f000 80ae beq.w 10002350 <_etoa+0x548> +100021f4: 2302 movs r3, #2 +100021f6: 9310 str r3, [sp, #64] @ 0x40 +100021f8: 2300 movs r3, #0 +100021fa: 930f str r3, [sp, #60] @ 0x3c +100021fc: e044 b.n 10002288 <_etoa+0x480> +100021fe: bb22 cbnz r2, 1000224a <_etoa+0x442> +10002200: f1ba 0f05 cmp.w sl, #5 +10002204: d94f bls.n 100022a6 <_etoa+0x49e> +10002206: f006 0302 and.w r3, r6, #2 +1000220a: 2b00 cmp r3, #0 +1000220c: d149 bne.n 100022a2 <_etoa+0x49a> +1000220e: 2305 movs r3, #5 +10002210: 9312 str r3, [sp, #72] @ 0x48 +10002212: f1aa 0305 sub.w r3, sl, #5 +10002216: 930f str r3, [sp, #60] @ 0x3c +10002218: e03a b.n 10002290 <_etoa+0x488> +1000221a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000221e: 940a str r4, [sp, #40] @ 0x28 +10002220: 930b str r3, [sp, #44] @ 0x2c +10002222: e627 b.n 10001e74 <_etoa+0x6c> +10002224: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002228: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000222c: 4638 mov r0, r7 +1000222e: 962c str r6, [sp, #176] @ 0xb0 +10002230: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002234: 4634 mov r4, r6 +10002236: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000223a: 465a mov r2, fp +1000223c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002240: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002244: 9b09 ldr r3, [sp, #36] @ 0x24 +10002246: 9908 ldr r1, [sp, #32] +10002248: e6bc b.n 10001fc4 <_etoa+0x1bc> +1000224a: 2205 movs r2, #5 +1000224c: 9212 str r2, [sp, #72] @ 0x48 +1000224e: e7ad b.n 100021ac <_etoa+0x3a4> +10002250: 2300 movs r3, #0 +10002252: 2202 movs r2, #2 +10002254: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002258: 2204 movs r2, #4 +1000225a: 930c str r3, [sp, #48] @ 0x30 +1000225c: 9212 str r2, [sp, #72] @ 0x48 +1000225e: e62c b.n 10001eba <_etoa+0xb2> +10002260: f04f 0805 mov.w r8, #5 +10002264: e6c2 b.n 10001fec <_etoa+0x1e4> +10002266: f1ba 0f04 cmp.w sl, #4 +1000226a: d91f bls.n 100022ac <_etoa+0x4a4> +1000226c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000226e: 2b00 cmp r3, #0 +10002270: d178 bne.n 10002364 <_etoa+0x55c> +10002272: 2304 movs r3, #4 +10002274: 9312 str r3, [sp, #72] @ 0x48 +10002276: f1aa 0304 sub.w r3, sl, #4 +1000227a: 930f str r3, [sp, #60] @ 0x3c +1000227c: e004 b.n 10002288 <_etoa+0x480> +1000227e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002280: 459a cmp sl, r3 +10002282: d831 bhi.n 100022e8 <_etoa+0x4e0> +10002284: 9b0e ldr r3, [sp, #56] @ 0x38 +10002286: 930f str r3, [sp, #60] @ 0x3c +10002288: 9b0c ldr r3, [sp, #48] @ 0x30 +1000228a: 2b00 cmp r3, #0 +1000228c: f43f ae15 beq.w 10001eba <_etoa+0xb2> +10002290: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002294: 4642 mov r2, r8 +10002296: 464b mov r3, r9 +10002298: f7ff f91e bl 100014d8 <__wrap___aeabi_ddiv> +1000229c: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100022a0: e60b b.n 10001eba <_etoa+0xb2> +100022a2: 2302 movs r3, #2 +100022a4: 9310 str r3, [sp, #64] @ 0x40 +100022a6: 2305 movs r3, #5 +100022a8: 9312 str r3, [sp, #72] @ 0x48 +100022aa: e7f1 b.n 10002290 <_etoa+0x488> +100022ac: 2304 movs r3, #4 +100022ae: 9312 str r3, [sp, #72] @ 0x48 +100022b0: e7ea b.n 10002288 <_etoa+0x480> +100022b2: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100022b6: 46a0 mov r8, r4 +100022b8: 9b0f ldr r3, [sp, #60] @ 0x3c +100022ba: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +100022be: 9303 str r3, [sp, #12] +100022c0: 9b0e ldr r3, [sp, #56] @ 0x38 +100022c2: 465a mov r2, fp +100022c4: 9302 str r3, [sp, #8] +100022c6: f426 6300 bic.w r3, r6, #2048 @ 0x800 +100022ca: 9304 str r3, [sp, #16] +100022cc: 4638 mov r0, r7 +100022ce: e9cd 8900 strd r8, r9, [sp] +100022d2: 9b09 ldr r3, [sp, #36] @ 0x24 +100022d4: 9908 ldr r1, [sp, #32] +100022d6: f7ff fb37 bl 10001948 <_ftoa> +100022da: 4602 mov r2, r0 +100022dc: e608 b.n 10001ef0 <_etoa+0xe8> +100022de: 9b12 ldr r3, [sp, #72] @ 0x48 +100022e0: 459a cmp sl, r3 +100022e2: d844 bhi.n 1000236e <_etoa+0x566> +100022e4: 920f str r2, [sp, #60] @ 0x3c +100022e6: e7cf b.n 10002288 <_etoa+0x480> +100022e8: 9b10 ldr r3, [sp, #64] @ 0x40 +100022ea: b38b cbz r3, 10002350 <_etoa+0x548> +100022ec: 9b0e ldr r3, [sp, #56] @ 0x38 +100022ee: 930f str r3, [sp, #60] @ 0x3c +100022f0: 2302 movs r3, #2 +100022f2: 9310 str r3, [sp, #64] @ 0x40 +100022f4: e7c8 b.n 10002288 <_etoa+0x480> +100022f6: bf00 nop +100022f8: 636f4361 .word 0x636f4361 +100022fc: 3fd287a7 .word 0x3fd287a7 +10002300: 0979a371 .word 0x0979a371 +10002304: 400a934f .word 0x400a934f +10002308: bbb55516 .word 0xbbb55516 +1000230c: 40026bb1 .word 0x40026bb1 +10002310: fefa39ef .word 0xfefa39ef +10002314: 3fe62e42 .word 0x3fe62e42 +10002318: eb1c432d .word 0xeb1c432d +1000231c: 3f1a36e2 .word 0x3f1a36e2 +10002320: 00000000 .word 0x00000000 +10002324: 412e8480 .word 0x412e8480 +10002328: 3ff80000 .word 0x3ff80000 +1000232c: 3fe00000 .word 0x3fe00000 +10002330: 402c0000 .word 0x402c0000 +10002334: 40240000 .word 0x40240000 +10002338: 40180000 .word 0x40180000 +1000233c: 3ff00000 .word 0x3ff00000 +10002340: 509f79fb .word 0x509f79fb +10002344: 3fd34413 .word 0x3fd34413 +10002348: 8b60c8b3 .word 0x8b60c8b3 +1000234c: 3fc68a28 .word 0x3fc68a28 +10002350: 9b12 ldr r3, [sp, #72] @ 0x48 +10002352: ebaa 0303 sub.w r3, sl, r3 +10002356: 930f str r3, [sp, #60] @ 0x3c +10002358: e796 b.n 10002288 <_etoa+0x480> +1000235a: eba3 0802 sub.w r8, r3, r2 +1000235e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +10002362: e643 b.n 10001fec <_etoa+0x1e4> +10002364: 2304 movs r3, #4 +10002366: 9312 str r3, [sp, #72] @ 0x48 +10002368: 2302 movs r3, #2 +1000236a: 9310 str r3, [sp, #64] @ 0x40 +1000236c: e78c b.n 10002288 <_etoa+0x480> +1000236e: 9b10 ldr r3, [sp, #64] @ 0x40 +10002370: 2b00 cmp r3, #0 +10002372: d0ed beq.n 10002350 <_etoa+0x548> +10002374: 2302 movs r3, #2 +10002376: 920f str r2, [sp, #60] @ 0x3c +10002378: 9310 str r3, [sp, #64] @ 0x40 +1000237a: e785 b.n 10002288 <_etoa+0x480> + +1000237c <_vsnprintf>: +1000237c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002380: b09b sub sp, #108 @ 0x6c +10002382: 9c24 ldr r4, [sp, #144] @ 0x90 +10002384: 4d95 ldr r5, [pc, #596] @ (100025dc <_vsnprintf+0x260>) +10002386: 940a str r4, [sp, #40] @ 0x28 +10002388: 4c95 ldr r4, [pc, #596] @ (100025e0 <_vsnprintf+0x264>) +1000238a: f1b1 0a00 subs.w sl, r1, #0 +1000238e: bf18 it ne +10002390: 4683 movne fp, r0 +10002392: 6025 str r5, [r4, #0] +10002394: 7818 ldrb r0, [r3, #0] +10002396: 4c93 ldr r4, [pc, #588] @ (100025e4 <_vsnprintf+0x268>) +10002398: 4691 mov r9, r2 +1000239a: bf08 it eq +1000239c: 46a3 moveq fp, r4 +1000239e: 9309 str r3, [sp, #36] @ 0x24 +100023a0: 2800 cmp r0, #0 +100023a2: f000 8293 beq.w 100028cc <_vsnprintf+0x550> +100023a6: f04f 0800 mov.w r8, #0 +100023aa: e00a b.n 100023c2 <_vsnprintf+0x46> +100023ac: 4642 mov r2, r8 +100023ae: 464b mov r3, r9 +100023b0: 4651 mov r1, sl +100023b2: f108 0801 add.w r8, r8, #1 +100023b6: 47d8 blx fp +100023b8: 9b09 ldr r3, [sp, #36] @ 0x24 +100023ba: 7818 ldrb r0, [r3, #0] +100023bc: 2800 cmp r0, #0 +100023be: f000 80ce beq.w 1000255e <_vsnprintf+0x1e2> +100023c2: 9b09 ldr r3, [sp, #36] @ 0x24 +100023c4: 2825 cmp r0, #37 @ 0x25 +100023c6: f103 0301 add.w r3, r3, #1 +100023ca: 9309 str r3, [sp, #36] @ 0x24 +100023cc: d1ee bne.n 100023ac <_vsnprintf+0x30> +100023ce: 461c mov r4, r3 +100023d0: 2300 movs r3, #0 +100023d2: 4622 mov r2, r4 +100023d4: f812 0b01 ldrb.w r0, [r2], #1 +100023d8: f1a0 0120 sub.w r1, r0, #32 +100023dc: 2910 cmp r1, #16 +100023de: d80a bhi.n 100023f6 <_vsnprintf+0x7a> +100023e0: e8df f001 tbb [pc, r1] +100023e4: 3c090940 .word 0x3c090940 +100023e8: 09090909 .word 0x09090909 +100023ec: 38090909 .word 0x38090909 +100023f0: 09093409 .word 0x09093409 +100023f4: 30 .byte 0x30 +100023f5: 00 .byte 0x00 +100023f6: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100023fa: 2909 cmp r1, #9 +100023fc: 9409 str r4, [sp, #36] @ 0x24 +100023fe: f240 808a bls.w 10002516 <_vsnprintf+0x19a> +10002402: 282a cmp r0, #42 @ 0x2a +10002404: f000 80f0 beq.w 100025e8 <_vsnprintf+0x26c> +10002408: 2500 movs r5, #0 +1000240a: 282e cmp r0, #46 @ 0x2e +1000240c: f000 8096 beq.w 1000253c <_vsnprintf+0x1c0> +10002410: 2600 movs r6, #0 +10002412: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002416: 2912 cmp r1, #18 +10002418: d82d bhi.n 10002476 <_vsnprintf+0xfa> +1000241a: e8df f011 tbh [pc, r1, lsl #1] +1000241e: 0149 .short 0x0149 +10002420: 0143002c .word 0x0143002c +10002424: 0138002c .word 0x0138002c +10002428: 002c002c .word 0x002c002c +1000242c: 002c002c .word 0x002c002c +10002430: 002c002c .word 0x002c002c +10002434: 0027002c .word 0x0027002c +10002438: 002c002c .word 0x002c002c +1000243c: 002c002c .word 0x002c002c +10002440: 0027002c .word 0x0027002c +10002444: 4614 mov r4, r2 +10002446: f043 0301 orr.w r3, r3, #1 +1000244a: e7c2 b.n 100023d2 <_vsnprintf+0x56> +1000244c: 4614 mov r4, r2 +1000244e: f043 0302 orr.w r3, r3, #2 +10002452: e7be b.n 100023d2 <_vsnprintf+0x56> +10002454: 4614 mov r4, r2 +10002456: f043 0304 orr.w r3, r3, #4 +1000245a: e7ba b.n 100023d2 <_vsnprintf+0x56> +1000245c: 4614 mov r4, r2 +1000245e: f043 0310 orr.w r3, r3, #16 +10002462: e7b6 b.n 100023d2 <_vsnprintf+0x56> +10002464: 4614 mov r4, r2 +10002466: f043 0308 orr.w r3, r3, #8 +1000246a: e7b2 b.n 100023d2 <_vsnprintf+0x56> +1000246c: 9909 ldr r1, [sp, #36] @ 0x24 +1000246e: 7848 ldrb r0, [r1, #1] +10002470: f443 7380 orr.w r3, r3, #256 @ 0x100 +10002474: 3201 adds r2, #1 +10002476: 2867 cmp r0, #103 @ 0x67 +10002478: 9209 str r2, [sp, #36] @ 0x24 +1000247a: d87e bhi.n 1000257a <_vsnprintf+0x1fe> +1000247c: 2824 cmp r0, #36 @ 0x24 +1000247e: f240 80c1 bls.w 10002604 <_vsnprintf+0x288> +10002482: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +10002486: 2a42 cmp r2, #66 @ 0x42 +10002488: f200 80bc bhi.w 10002604 <_vsnprintf+0x288> +1000248c: e8df f012 tbh [pc, r2, lsl #1] +10002490: 00ba0150 .word 0x00ba0150 +10002494: 00ba00ba .word 0x00ba00ba +10002498: 00ba00ba .word 0x00ba00ba +1000249c: 00ba00ba .word 0x00ba00ba +100024a0: 00ba00ba .word 0x00ba00ba +100024a4: 00ba00ba .word 0x00ba00ba +100024a8: 00ba00ba .word 0x00ba00ba +100024ac: 00ba00ba .word 0x00ba00ba +100024b0: 00ba00ba .word 0x00ba00ba +100024b4: 00ba00ba .word 0x00ba00ba +100024b8: 00ba00ba .word 0x00ba00ba +100024bc: 00ba00ba .word 0x00ba00ba +100024c0: 00ba00ba .word 0x00ba00ba +100024c4: 00ba00ba .word 0x00ba00ba +100024c8: 00ba00ba .word 0x00ba00ba +100024cc: 00ba00ba .word 0x00ba00ba +100024d0: 01370119 .word 0x01370119 +100024d4: 00ba0119 .word 0x00ba0119 +100024d8: 00ba00ba .word 0x00ba00ba +100024dc: 00ba00ba .word 0x00ba00ba +100024e0: 00ba00ba .word 0x00ba00ba +100024e4: 00ba00ba .word 0x00ba00ba +100024e8: 00ba00ba .word 0x00ba00ba +100024ec: 00ba00ba .word 0x00ba00ba +100024f0: 00ba00ba .word 0x00ba00ba +100024f4: 01bc00ba .word 0x01bc00ba +100024f8: 00ba00ba .word 0x00ba00ba +100024fc: 00ba00ba .word 0x00ba00ba +10002500: 00ba00ba .word 0x00ba00ba +10002504: 00ba00ba .word 0x00ba00ba +10002508: 01bc00ba .word 0x01bc00ba +1000250c: 01bc0158 .word 0x01bc0158 +10002510: 01370119 .word 0x01370119 +10002514: 0119 .short 0x0119 +10002516: 2500 movs r5, #0 +10002518: e000 b.n 1000251c <_vsnprintf+0x1a0> +1000251a: 3201 adds r2, #1 +1000251c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002520: eb00 0545 add.w r5, r0, r5, lsl #1 +10002524: 7810 ldrb r0, [r2, #0] +10002526: 3d30 subs r5, #48 @ 0x30 +10002528: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000252c: 2909 cmp r1, #9 +1000252e: d9f4 bls.n 1000251a <_vsnprintf+0x19e> +10002530: 282e cmp r0, #46 @ 0x2e +10002532: 9209 str r2, [sp, #36] @ 0x24 +10002534: f102 0201 add.w r2, r2, #1 +10002538: f47f af6a bne.w 10002410 <_vsnprintf+0x94> +1000253c: 9909 ldr r1, [sp, #36] @ 0x24 +1000253e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002542: 7848 ldrb r0, [r1, #1] +10002544: 4611 mov r1, r2 +10002546: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000254a: 2e09 cmp r6, #9 +1000254c: f240 8121 bls.w 10002792 <_vsnprintf+0x416> +10002550: 282a cmp r0, #42 @ 0x2a +10002552: f000 812f beq.w 100027b4 <_vsnprintf+0x438> +10002556: 9209 str r2, [sp, #36] @ 0x24 +10002558: 2600 movs r6, #0 +1000255a: 3201 adds r2, #1 +1000255c: e759 b.n 10002412 <_vsnprintf+0x96> +1000255e: 4644 mov r4, r8 +10002560: 45c1 cmp r9, r8 +10002562: d801 bhi.n 10002568 <_vsnprintf+0x1ec> +10002564: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002568: 464b mov r3, r9 +1000256a: 4642 mov r2, r8 +1000256c: 4651 mov r1, sl +1000256e: 2000 movs r0, #0 +10002570: 47d8 blx fp +10002572: 4620 mov r0, r4 +10002574: b01b add sp, #108 @ 0x6c +10002576: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000257a: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +1000257e: b2d2 uxtb r2, r2 +10002580: 2a0f cmp r2, #15 +10002582: d83f bhi.n 10002604 <_vsnprintf+0x288> +10002584: 2101 movs r1, #1 +10002586: f249 0741 movw r7, #36929 @ 0x9041 +1000258a: 4091 lsls r1, r2 +1000258c: 4039 ands r1, r7 +1000258e: f040 80f3 bne.w 10002778 <_vsnprintf+0x3fc> +10002592: 2a0a cmp r2, #10 +10002594: d03d beq.n 10002612 <_vsnprintf+0x296> +10002596: 2a07 cmp r2, #7 +10002598: d134 bne.n 10002604 <_vsnprintf+0x288> +1000259a: 9d0a ldr r5, [sp, #40] @ 0x28 +1000259c: f855 2b04 ldr.w r2, [r5], #4 +100025a0: 2a00 cmp r2, #0 +100025a2: f000 8113 beq.w 100027cc <_vsnprintf+0x450> +100025a6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100025aa: ab12 add r3, sp, #72 @ 0x48 +100025ac: 461f mov r7, r3 +100025ae: 930b str r3, [sp, #44] @ 0x2c +100025b0: e003 b.n 100025ba <_vsnprintf+0x23e> +100025b2: 2920 cmp r1, #32 +100025b4: f000 8114 beq.w 100027e0 <_vsnprintf+0x464> +100025b8: 461a mov r2, r3 +100025ba: f002 040f and.w r4, r2, #15 +100025be: 4623 mov r3, r4 +100025c0: 2c09 cmp r4, #9 +100025c2: bf94 ite ls +100025c4: 3330 addls r3, #48 @ 0x30 +100025c6: 3337 addhi r3, #55 @ 0x37 +100025c8: 2a0f cmp r2, #15 +100025ca: f807 3b01 strb.w r3, [r7], #1 +100025ce: f101 0101 add.w r1, r1, #1 +100025d2: ea4f 1312 mov.w r3, r2, lsr #4 +100025d6: d8ec bhi.n 100025b2 <_vsnprintf+0x236> +100025d8: e102 b.n 100027e0 <_vsnprintf+0x464> +100025da: bf00 nop +100025dc: 1000237d .word 0x1000237d +100025e0: 2000080c .word 0x2000080c +100025e4: 100016c1 .word 0x100016c1 +100025e8: 990a ldr r1, [sp, #40] @ 0x28 +100025ea: 9809 ldr r0, [sp, #36] @ 0x24 +100025ec: f851 5b04 ldr.w r5, [r1], #4 +100025f0: 7840 ldrb r0, [r0, #1] +100025f2: 2d00 cmp r5, #0 +100025f4: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +100025f8: bfbc itt lt +100025fa: f043 0302 orrlt.w r3, r3, #2 +100025fe: 426d neglt r5, r5 +10002600: 3201 adds r2, #1 +10002602: e702 b.n 1000240a <_vsnprintf+0x8e> +10002604: 4642 mov r2, r8 +10002606: 464b mov r3, r9 +10002608: 4651 mov r1, sl +1000260a: f108 0801 add.w r8, r8, #1 +1000260e: 47d8 blx fp +10002610: e6d2 b.n 100023b8 <_vsnprintf+0x3c> +10002612: 990a ldr r1, [sp, #40] @ 0x28 +10002614: 2e00 cmp r6, #0 +10002616: f851 7b04 ldr.w r7, [r1], #4 +1000261a: bf18 it ne +1000261c: 4632 movne r2, r6 +1000261e: 7838 ldrb r0, [r7, #0] +10002620: bf08 it eq +10002622: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002626: 2800 cmp r0, #0 +10002628: f000 837b beq.w 10002d22 <_vsnprintf+0x9a6> +1000262c: 18bc adds r4, r7, r2 +1000262e: 46a4 mov ip, r4 +10002630: 463a mov r2, r7 +10002632: e004 b.n 1000263e <_vsnprintf+0x2c2> +10002634: f812 4f01 ldrb.w r4, [r2, #1]! +10002638: 2c00 cmp r4, #0 +1000263a: f000 813f beq.w 100028bc <_vsnprintf+0x540> +1000263e: 4594 cmp ip, r2 +10002640: d1f8 bne.n 10002634 <_vsnprintf+0x2b8> +10002642: 4664 mov r4, ip +10002644: 1be4 subs r4, r4, r7 +10002646: 055a lsls r2, r3, #21 +10002648: f140 8122 bpl.w 10002890 <_vsnprintf+0x514> +1000264c: 42b4 cmp r4, r6 +1000264e: bf28 it cs +10002650: 4634 movcs r4, r6 +10002652: f013 0302 ands.w r3, r3, #2 +10002656: f000 8288 beq.w 10002b6a <_vsnprintf+0x7ee> +1000265a: 2302 movs r3, #2 +1000265c: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002660: 4642 mov r2, r8 +10002662: 461d mov r5, r3 +10002664: 4446 add r6, r8 +10002666: e008 b.n 1000267a <_vsnprintf+0x2fe> +10002668: 464b mov r3, r9 +1000266a: 4651 mov r1, sl +1000266c: 47d8 blx fp +1000266e: f817 0f01 ldrb.w r0, [r7, #1]! +10002672: f108 0801 add.w r8, r8, #1 +10002676: b110 cbz r0, 1000267e <_vsnprintf+0x302> +10002678: 4642 mov r2, r8 +1000267a: 4546 cmp r6, r8 +1000267c: d1f4 bne.n 10002668 <_vsnprintf+0x2ec> +1000267e: 462b mov r3, r5 +10002680: 990b ldr r1, [sp, #44] @ 0x2c +10002682: 9d0a ldr r5, [sp, #40] @ 0x28 +10002684: 2b00 cmp r3, #0 +10002686: f040 8141 bne.w 1000290c <_vsnprintf+0x590> +1000268a: 910a str r1, [sp, #40] @ 0x28 +1000268c: e694 b.n 100023b8 <_vsnprintf+0x3c> +1000268e: 9909 ldr r1, [sp, #36] @ 0x24 +10002690: 7848 ldrb r0, [r1, #1] +10002692: 286c cmp r0, #108 @ 0x6c +10002694: f47f aeec bne.w 10002470 <_vsnprintf+0xf4> +10002698: 460a mov r2, r1 +1000269a: 7888 ldrb r0, [r1, #2] +1000269c: f443 7340 orr.w r3, r3, #768 @ 0x300 +100026a0: 3203 adds r2, #3 +100026a2: e6e8 b.n 10002476 <_vsnprintf+0xfa> +100026a4: 9909 ldr r1, [sp, #36] @ 0x24 +100026a6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100026aa: 7848 ldrb r0, [r1, #1] +100026ac: 3201 adds r2, #1 +100026ae: e6e2 b.n 10002476 <_vsnprintf+0xfa> +100026b0: 9909 ldr r1, [sp, #36] @ 0x24 +100026b2: 7848 ldrb r0, [r1, #1] +100026b4: 2868 cmp r0, #104 @ 0x68 +100026b6: f000 8103 beq.w 100028c0 <_vsnprintf+0x544> +100026ba: f043 0380 orr.w r3, r3, #128 @ 0x80 +100026be: 3201 adds r2, #1 +100026c0: e6d9 b.n 10002476 <_vsnprintf+0xfa> +100026c2: 2867 cmp r0, #103 @ 0x67 +100026c4: f000 80d9 beq.w 1000287a <_vsnprintf+0x4fe> +100026c8: 2847 cmp r0, #71 @ 0x47 +100026ca: f000 80dc beq.w 10002886 <_vsnprintf+0x50a> +100026ce: 2845 cmp r0, #69 @ 0x45 +100026d0: f000 80db beq.w 1000288a <_vsnprintf+0x50e> +100026d4: e9cd 5303 strd r5, r3, [sp, #12] +100026d8: 9b0a ldr r3, [sp, #40] @ 0x28 +100026da: 9602 str r6, [sp, #8] +100026dc: 3307 adds r3, #7 +100026de: f023 0307 bic.w r3, r3, #7 +100026e2: 461c mov r4, r3 +100026e4: 4642 mov r2, r8 +100026e6: e8f4 6702 ldrd r6, r7, [r4], #8 +100026ea: 464b mov r3, r9 +100026ec: 4651 mov r1, sl +100026ee: 4658 mov r0, fp +100026f0: e9cd 6700 strd r6, r7, [sp] +100026f4: 940a str r4, [sp, #40] @ 0x28 +100026f6: f7ff fb87 bl 10001e08 <_etoa> +100026fa: 4680 mov r8, r0 +100026fc: e65c b.n 100023b8 <_vsnprintf+0x3c> +100026fe: 2846 cmp r0, #70 @ 0x46 +10002700: bf08 it eq +10002702: f043 0320 orreq.w r3, r3, #32 +10002706: e9cd 5303 strd r5, r3, [sp, #12] +1000270a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000270c: 9602 str r6, [sp, #8] +1000270e: 3307 adds r3, #7 +10002710: f023 0307 bic.w r3, r3, #7 +10002714: 461c mov r4, r3 +10002716: 4642 mov r2, r8 +10002718: e8f4 6702 ldrd r6, r7, [r4], #8 +1000271c: 464b mov r3, r9 +1000271e: 4651 mov r1, sl +10002720: 4658 mov r0, fp +10002722: e9cd 6700 strd r6, r7, [sp] +10002726: 940a str r4, [sp, #40] @ 0x28 +10002728: f7ff f90e bl 10001948 <_ftoa> +1000272c: 4680 mov r8, r0 +1000272e: e643 b.n 100023b8 <_vsnprintf+0x3c> +10002730: 4642 mov r2, r8 +10002732: 464b mov r3, r9 +10002734: 4651 mov r1, sl +10002736: 2025 movs r0, #37 @ 0x25 +10002738: f108 0801 add.w r8, r8, #1 +1000273c: 47d8 blx fp +1000273e: e63b b.n 100023b8 <_vsnprintf+0x3c> +10002740: 9a0a ldr r2, [sp, #40] @ 0x28 +10002742: 0799 lsls r1, r3, #30 +10002744: f102 0404 add.w r4, r2, #4 +10002748: f108 0601 add.w r6, r8, #1 +1000274c: f140 80c6 bpl.w 100028dc <_vsnprintf+0x560> +10002750: 7810 ldrb r0, [r2, #0] +10002752: 464b mov r3, r9 +10002754: 4642 mov r2, r8 +10002756: 4651 mov r1, sl +10002758: 47d8 blx fp +1000275a: 2d01 cmp r5, #1 +1000275c: bf88 it hi +1000275e: 44a8 addhi r8, r5 +10002760: f240 81bd bls.w 10002ade <_vsnprintf+0x762> +10002764: 4632 mov r2, r6 +10002766: 464b mov r3, r9 +10002768: 4651 mov r1, sl +1000276a: 2020 movs r0, #32 +1000276c: 3601 adds r6, #1 +1000276e: 47d8 blx fp +10002770: 4546 cmp r6, r8 +10002772: d1f7 bne.n 10002764 <_vsnprintf+0x3e8> +10002774: 940a str r4, [sp, #40] @ 0x28 +10002776: e61f b.n 100023b8 <_vsnprintf+0x3c> +10002778: 286f cmp r0, #111 @ 0x6f +1000277a: f000 8081 beq.w 10002880 <_vsnprintf+0x504> +1000277e: f240 8248 bls.w 10002c12 <_vsnprintf+0x896> +10002782: 2878 cmp r0, #120 @ 0x78 +10002784: f000 8190 beq.w 10002aa8 <_vsnprintf+0x72c> +10002788: 270a movs r7, #10 +1000278a: f023 0310 bic.w r3, r3, #16 +1000278e: 46bc mov ip, r7 +10002790: e041 b.n 10002816 <_vsnprintf+0x49a> +10002792: 2600 movs r6, #0 +10002794: eb06 0686 add.w r6, r6, r6, lsl #2 +10002798: eb00 0046 add.w r0, r0, r6, lsl #1 +1000279c: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100027a0: f811 0f01 ldrb.w r0, [r1, #1]! +100027a4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100027a8: 2a09 cmp r2, #9 +100027aa: d9f3 bls.n 10002794 <_vsnprintf+0x418> +100027ac: 460a mov r2, r1 +100027ae: 9109 str r1, [sp, #36] @ 0x24 +100027b0: 3201 adds r2, #1 +100027b2: e62e b.n 10002412 <_vsnprintf+0x96> +100027b4: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +100027b8: f851 6b04 ldr.w r6, [r1], #4 +100027bc: 7890 ldrb r0, [r2, #2] +100027be: 3202 adds r2, #2 +100027c0: 9209 str r2, [sp, #36] @ 0x24 +100027c2: 910a str r1, [sp, #40] @ 0x28 +100027c4: 3201 adds r2, #1 +100027c6: ea26 76e6 bic.w r6, r6, r6, asr #31 +100027ca: e622 b.n 10002412 <_vsnprintf+0x96> +100027cc: f023 0010 bic.w r0, r3, #16 +100027d0: f413 6280 ands.w r2, r3, #1024 @ 0x400 +100027d4: f040 0021 orr.w r0, r0, #33 @ 0x21 +100027d8: f43f aee7 beq.w 100025aa <_vsnprintf+0x22e> +100027dc: ab12 add r3, sp, #72 @ 0x48 +100027de: 930b str r3, [sp, #44] @ 0x2c +100027e0: 9b0b ldr r3, [sp, #44] @ 0x2c +100027e2: 9006 str r0, [sp, #24] +100027e4: 9300 str r3, [sp, #0] +100027e6: 2308 movs r3, #8 +100027e8: 2010 movs r0, #16 +100027ea: 9305 str r3, [sp, #20] +100027ec: 2300 movs r3, #0 +100027ee: 4642 mov r2, r8 +100027f0: e9cd 3002 strd r3, r0, [sp, #8] +100027f4: 9101 str r1, [sp, #4] +100027f6: 464b mov r3, r9 +100027f8: 4651 mov r1, sl +100027fa: 4658 mov r0, fp +100027fc: 9604 str r6, [sp, #16] +100027fe: f7fe ffaf bl 10001760 <_ntoa_format> +10002802: 950a str r5, [sp, #40] @ 0x28 +10002804: 4680 mov r8, r0 +10002806: e5d7 b.n 100023b8 <_vsnprintf+0x3c> +10002808: 2858 cmp r0, #88 @ 0x58 +1000280a: d062 beq.n 100028d2 <_vsnprintf+0x556> +1000280c: 2862 cmp r0, #98 @ 0x62 +1000280e: f040 808f bne.w 10002930 <_vsnprintf+0x5b4> +10002812: 2702 movs r7, #2 +10002814: 46bc mov ip, r7 +10002816: f413 6080 ands.w r0, r3, #1024 @ 0x400 +1000281a: f000 80dd beq.w 100029d8 <_vsnprintf+0x65c> +1000281e: f023 030d bic.w r3, r3, #13 +10002822: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002826: f040 8181 bne.w 10002b2c <_vsnprintf+0x7b0> +1000282a: 990a ldr r1, [sp, #40] @ 0x28 +1000282c: 1d0f adds r7, r1, #4 +1000282e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002832: f040 8237 bne.w 10002ca4 <_vsnprintf+0x928> +10002836: 065c lsls r4, r3, #25 +10002838: 9a0a ldr r2, [sp, #40] @ 0x28 +1000283a: f140 813b bpl.w 10002ab4 <_vsnprintf+0x738> +1000283e: 7812 ldrb r2, [r2, #0] +10002840: 2a00 cmp r2, #0 +10002842: f040 814e bne.w 10002ae2 <_vsnprintf+0x766> +10002846: f023 0310 bic.w r3, r3, #16 +1000284a: 2800 cmp r0, #0 +1000284c: f000 8149 beq.w 10002ae2 <_vsnprintf+0x766> +10002850: 4611 mov r1, r2 +10002852: aa12 add r2, sp, #72 @ 0x48 +10002854: 920b str r2, [sp, #44] @ 0x2c +10002856: e9cd 5305 strd r5, r3, [sp, #20] +1000285a: e9cd c603 strd ip, r6, [sp, #12] +1000285e: 9101 str r1, [sp, #4] +10002860: 9b0b ldr r3, [sp, #44] @ 0x2c +10002862: 4642 mov r2, r8 +10002864: 9300 str r3, [sp, #0] +10002866: 2300 movs r3, #0 +10002868: 4651 mov r1, sl +1000286a: 9302 str r3, [sp, #8] +1000286c: 4658 mov r0, fp +1000286e: 464b mov r3, r9 +10002870: f7fe ff76 bl 10001760 <_ntoa_format> +10002874: 970a str r7, [sp, #40] @ 0x28 +10002876: 4680 mov r8, r0 +10002878: e59e b.n 100023b8 <_vsnprintf+0x3c> +1000287a: f443 6300 orr.w r3, r3, #2048 @ 0x800 +1000287e: e729 b.n 100026d4 <_vsnprintf+0x358> +10002880: 2708 movs r7, #8 +10002882: 46bc mov ip, r7 +10002884: e7c7 b.n 10002816 <_vsnprintf+0x49a> +10002886: f443 6300 orr.w r3, r3, #2048 @ 0x800 +1000288a: f043 0320 orr.w r3, r3, #32 +1000288e: e721 b.n 100026d4 <_vsnprintf+0x358> +10002890: f013 0302 ands.w r3, r3, #2 +10002894: f000 818e beq.w 10002bb4 <_vsnprintf+0x838> +10002898: 2302 movs r3, #2 +1000289a: 950a str r5, [sp, #40] @ 0x28 +1000289c: 461e mov r6, r3 +1000289e: 460d mov r5, r1 +100028a0: 4642 mov r2, r8 +100028a2: 464b mov r3, r9 +100028a4: 4651 mov r1, sl +100028a6: 47d8 blx fp +100028a8: f817 0f01 ldrb.w r0, [r7, #1]! +100028ac: f108 0801 add.w r8, r8, #1 +100028b0: 2800 cmp r0, #0 +100028b2: d1f5 bne.n 100028a0 <_vsnprintf+0x524> +100028b4: 4629 mov r1, r5 +100028b6: 4633 mov r3, r6 +100028b8: 9d0a ldr r5, [sp, #40] @ 0x28 +100028ba: e6e3 b.n 10002684 <_vsnprintf+0x308> +100028bc: 1bd4 subs r4, r2, r7 +100028be: e6c2 b.n 10002646 <_vsnprintf+0x2ca> +100028c0: 460a mov r2, r1 +100028c2: 7888 ldrb r0, [r1, #2] +100028c4: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +100028c8: 3203 adds r2, #3 +100028ca: e5d4 b.n 10002476 <_vsnprintf+0xfa> +100028cc: 4604 mov r4, r0 +100028ce: 4680 mov r8, r0 +100028d0: e646 b.n 10002560 <_vsnprintf+0x1e4> +100028d2: 2710 movs r7, #16 +100028d4: f043 0320 orr.w r3, r3, #32 +100028d8: 46bc mov ip, r7 +100028da: e79c b.n 10002816 <_vsnprintf+0x49a> +100028dc: 2d01 cmp r5, #1 +100028de: f240 80f8 bls.w 10002ad2 <_vsnprintf+0x756> +100028e2: 4646 mov r6, r8 +100028e4: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +100028e8: 442f add r7, r5 +100028ea: 4632 mov r2, r6 +100028ec: 464b mov r3, r9 +100028ee: 4651 mov r1, sl +100028f0: 2020 movs r0, #32 +100028f2: 3601 adds r6, #1 +100028f4: 47d8 blx fp +100028f6: 42be cmp r6, r7 +100028f8: d1f7 bne.n 100028ea <_vsnprintf+0x56e> +100028fa: 9b0a ldr r3, [sp, #40] @ 0x28 +100028fc: 4632 mov r2, r6 +100028fe: 7818 ldrb r0, [r3, #0] +10002900: 4651 mov r1, sl +10002902: 464b mov r3, r9 +10002904: 47d8 blx fp +10002906: 44a8 add r8, r5 +10002908: 940a str r4, [sp, #40] @ 0x28 +1000290a: e555 b.n 100023b8 <_vsnprintf+0x3c> +1000290c: 4646 mov r6, r8 +1000290e: 42a5 cmp r5, r4 +10002910: f67f aebb bls.w 1000268a <_vsnprintf+0x30e> +10002914: 44a8 add r8, r5 +10002916: eba8 0804 sub.w r8, r8, r4 +1000291a: 460c mov r4, r1 +1000291c: 4632 mov r2, r6 +1000291e: 464b mov r3, r9 +10002920: 4651 mov r1, sl +10002922: 2020 movs r0, #32 +10002924: 3601 adds r6, #1 +10002926: 47d8 blx fp +10002928: 4546 cmp r6, r8 +1000292a: d1f7 bne.n 1000291c <_vsnprintf+0x5a0> +1000292c: 4621 mov r1, r4 +1000292e: e6ac b.n 1000268a <_vsnprintf+0x30e> +10002930: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002934: f000 80bb beq.w 10002aae <_vsnprintf+0x732> +10002938: f44f 6280 mov.w r2, #1024 @ 0x400 +1000293c: f023 0c11 bic.w ip, r3, #17 +10002940: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002944: 9b0a ldr r3, [sp, #40] @ 0x28 +10002946: d14a bne.n 100029de <_vsnprintf+0x662> +10002948: f41c 7080 ands.w r0, ip, #256 @ 0x100 +1000294c: f103 0404 add.w r4, r3, #4 +10002950: f040 8134 bne.w 10002bbc <_vsnprintf+0x840> +10002954: f01c 0f40 tst.w ip, #64 @ 0x40 +10002958: f040 80a3 bne.w 10002aa2 <_vsnprintf+0x726> +1000295c: f01c 0f80 tst.w ip, #128 @ 0x80 +10002960: f000 81d3 beq.w 10002d0a <_vsnprintf+0x98e> +10002964: f9b3 1000 ldrsh.w r1, [r3] +10002968: ea81 77e1 eor.w r7, r1, r1, asr #31 +1000296c: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002970: b2bf uxth r7, r7 +10002972: 0fcb lsrs r3, r1, #31 +10002974: 2900 cmp r1, #0 +10002976: f000 8156 beq.w 10002c26 <_vsnprintf+0x8aa> +1000297a: 463a mov r2, r7 +1000297c: a912 add r1, sp, #72 @ 0x48 +1000297e: 460f mov r7, r1 +10002980: f8df e3d8 ldr.w lr, [pc, #984] @ 10002d5c <_vsnprintf+0x9e0> +10002984: 910b str r1, [sp, #44] @ 0x2c +10002986: 930a str r3, [sp, #40] @ 0x28 +10002988: 950c str r5, [sp, #48] @ 0x30 +1000298a: e001 b.n 10002990 <_vsnprintf+0x614> +1000298c: 2820 cmp r0, #32 +1000298e: d00f beq.n 100029b0 <_vsnprintf+0x634> +10002990: 4615 mov r5, r2 +10002992: fbae 1302 umull r1, r3, lr, r2 +10002996: 08db lsrs r3, r3, #3 +10002998: eb03 0183 add.w r1, r3, r3, lsl #2 +1000299c: eba2 0141 sub.w r1, r2, r1, lsl #1 +100029a0: 3130 adds r1, #48 @ 0x30 +100029a2: 2d09 cmp r5, #9 +100029a4: 461a mov r2, r3 +100029a6: f100 0001 add.w r0, r0, #1 +100029aa: f807 1b01 strb.w r1, [r7], #1 +100029ae: d8ed bhi.n 1000298c <_vsnprintf+0x610> +100029b0: 9b0a ldr r3, [sp, #40] @ 0x28 +100029b2: 9d0c ldr r5, [sp, #48] @ 0x30 +100029b4: e9cd 5c05 strd r5, ip, [sp, #20] +100029b8: e9cd 0301 strd r0, r3, [sp, #4] +100029bc: 9604 str r6, [sp, #16] +100029be: 9b0b ldr r3, [sp, #44] @ 0x2c +100029c0: 4642 mov r2, r8 +100029c2: 9300 str r3, [sp, #0] +100029c4: 230a movs r3, #10 +100029c6: 4651 mov r1, sl +100029c8: 9303 str r3, [sp, #12] +100029ca: 4658 mov r0, fp +100029cc: 464b mov r3, r9 +100029ce: f7fe fec7 bl 10001760 <_ntoa_format> +100029d2: 940a str r4, [sp, #40] @ 0x28 +100029d4: 4680 mov r8, r0 +100029d6: e4ef b.n 100023b8 <_vsnprintf+0x3c> +100029d8: f023 030c bic.w r3, r3, #12 +100029dc: e721 b.n 10002822 <_vsnprintf+0x4a6> +100029de: 3307 adds r3, #7 +100029e0: f023 0307 bic.w r3, r3, #7 +100029e4: 4619 mov r1, r3 +100029e6: 4608 mov r0, r1 +100029e8: 685b ldr r3, [r3, #4] +100029ea: f850 1b08 ldr.w r1, [r0], #8 +100029ee: 0fdf lsrs r7, r3, #31 +100029f0: 900a str r0, [sp, #40] @ 0x28 +100029f2: ea51 0003 orrs.w r0, r1, r3 +100029f6: d162 bne.n 10002abe <_vsnprintf+0x742> +100029f8: 2a00 cmp r2, #0 +100029fa: f040 819f bne.w 10002d3c <_vsnprintf+0x9c0> +100029fe: 4613 mov r3, r2 +10002a00: 4611 mov r1, r2 +10002a02: aa12 add r2, sp, #72 @ 0x48 +10002a04: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002a08: 2000 movs r0, #0 +10002a0a: 4615 mov r5, r2 +10002a0c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002a10: f8df e348 ldr.w lr, [pc, #840] @ 10002d5c <_vsnprintf+0x9e0> +10002a14: 920b str r2, [sp, #44] @ 0x2c +10002a16: e001 b.n 10002a1c <_vsnprintf+0x6a0> +10002a18: 2820 cmp r0, #32 +10002a1a: d02d beq.n 10002a78 <_vsnprintf+0x6fc> +10002a1c: 185a adds r2, r3, r1 +10002a1e: f142 0200 adc.w r2, r2, #0 +10002a22: fbae 7802 umull r7, r8, lr, r2 +10002a26: f028 0703 bic.w r7, r8, #3 +10002a2a: eb07 0798 add.w r7, r7, r8, lsr #2 +10002a2e: 1bd2 subs r2, r2, r7 +10002a30: 461e mov r6, r3 +10002a32: 1a9b subs r3, r3, r2 +10002a34: f161 0700 sbc.w r7, r1, #0 +10002a38: 460c mov r4, r1 +10002a3a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002a3e: fb01 f103 mul.w r1, r1, r3 +10002a42: fb0e 1107 mla r1, lr, r7, r1 +10002a46: fba3 730e umull r7, r3, r3, lr +10002a4a: 4419 add r1, r3 +10002a4c: 2305 movs r3, #5 +10002a4e: f007 0801 and.w r8, r7, #1 +10002a52: fba8 3803 umull r3, r8, r8, r3 +10002a56: 189b adds r3, r3, r2 +10002a58: 2e0a cmp r6, #10 +10002a5a: f103 0330 add.w r3, r3, #48 @ 0x30 +10002a5e: ea4f 0757 mov.w r7, r7, lsr #1 +10002a62: f174 0400 sbcs.w r4, r4, #0 +10002a66: f805 3b01 strb.w r3, [r5], #1 +10002a6a: f100 0001 add.w r0, r0, #1 +10002a6e: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002a72: ea4f 0151 mov.w r1, r1, lsr #1 +10002a76: d2cf bcs.n 10002a18 <_vsnprintf+0x69c> +10002a78: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002a7c: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002a80: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a82: 4642 mov r2, r8 +10002a84: 9300 str r3, [sp, #0] +10002a86: 230a movs r3, #10 +10002a88: e9cd 5c05 strd r5, ip, [sp, #20] +10002a8c: e9cd 0701 strd r0, r7, [sp, #4] +10002a90: 9604 str r6, [sp, #16] +10002a92: 9303 str r3, [sp, #12] +10002a94: 464b mov r3, r9 +10002a96: 4651 mov r1, sl +10002a98: 4658 mov r0, fp +10002a9a: f7fe fe61 bl 10001760 <_ntoa_format> +10002a9e: 4680 mov r8, r0 +10002aa0: e48a b.n 100023b8 <_vsnprintf+0x3c> +10002aa2: 7819 ldrb r1, [r3, #0] +10002aa4: 460f mov r7, r1 +10002aa6: e764 b.n 10002972 <_vsnprintf+0x5f6> +10002aa8: 2710 movs r7, #16 +10002aaa: 46bc mov ip, r7 +10002aac: e6b3 b.n 10002816 <_vsnprintf+0x49a> +10002aae: f023 0c10 bic.w ip, r3, #16 +10002ab2: e745 b.n 10002940 <_vsnprintf+0x5c4> +10002ab4: 061c lsls r4, r3, #24 +10002ab6: bf4c ite mi +10002ab8: 8812 ldrhmi r2, [r2, #0] +10002aba: 6812 ldrpl r2, [r2, #0] +10002abc: e6c0 b.n 10002840 <_vsnprintf+0x4c4> +10002abe: 460a mov r2, r1 +10002ac0: 1e19 subs r1, r3, #0 +10002ac2: db01 blt.n 10002ac8 <_vsnprintf+0x74c> +10002ac4: 4613 mov r3, r2 +10002ac6: e79c b.n 10002a02 <_vsnprintf+0x686> +10002ac8: 4252 negs r2, r2 +10002aca: 4613 mov r3, r2 +10002acc: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002ad0: e797 b.n 10002a02 <_vsnprintf+0x686> +10002ad2: 4613 mov r3, r2 +10002ad4: 4651 mov r1, sl +10002ad6: 7818 ldrb r0, [r3, #0] +10002ad8: 4642 mov r2, r8 +10002ada: 464b mov r3, r9 +10002adc: 47d8 blx fp +10002ade: 46b0 mov r8, r6 +10002ae0: e648 b.n 10002774 <_vsnprintf+0x3f8> +10002ae2: f013 0f20 tst.w r3, #32 +10002ae6: bf14 ite ne +10002ae8: 2041 movne r0, #65 @ 0x41 +10002aea: 2061 moveq r0, #97 @ 0x61 +10002aec: ac12 add r4, sp, #72 @ 0x48 +10002aee: 46a6 mov lr, r4 +10002af0: 940b str r4, [sp, #44] @ 0x2c +10002af2: 930a str r3, [sp, #40] @ 0x28 +10002af4: f1a0 040a sub.w r4, r0, #10 +10002af8: 950c str r5, [sp, #48] @ 0x30 +10002afa: e002 b.n 10002b02 <_vsnprintf+0x786> +10002afc: 2920 cmp r1, #32 +10002afe: d012 beq.n 10002b26 <_vsnprintf+0x7aa> +10002b00: 462a mov r2, r5 +10002b02: fbb2 f5fc udiv r5, r2, ip +10002b06: fb0c 2015 mls r0, ip, r5, r2 +10002b0a: b2c3 uxtb r3, r0 +10002b0c: 2809 cmp r0, #9 +10002b0e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002b12: bf8a itet hi +10002b14: 191b addhi r3, r3, r4 +10002b16: b2c3 uxtbls r3, r0 +10002b18: b2db uxtbhi r3, r3 +10002b1a: 4562 cmp r2, ip +10002b1c: f80e 3b01 strb.w r3, [lr], #1 +10002b20: f101 0101 add.w r1, r1, #1 +10002b24: d2ea bcs.n 10002afc <_vsnprintf+0x780> +10002b26: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b28: 9d0c ldr r5, [sp, #48] @ 0x30 +10002b2a: e694 b.n 10002856 <_vsnprintf+0x4da> +10002b2c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002b2e: 3207 adds r2, #7 +10002b30: f022 0207 bic.w r2, r2, #7 +10002b34: 6851 ldr r1, [r2, #4] +10002b36: f852 4b08 ldr.w r4, [r2], #8 +10002b3a: 468e mov lr, r1 +10002b3c: 920a str r2, [sp, #40] @ 0x28 +10002b3e: ea54 0201 orrs.w r2, r4, r1 +10002b42: d176 bne.n 10002c32 <_vsnprintf+0x8b6> +10002b44: f023 0310 bic.w r3, r3, #16 +10002b48: 2800 cmp r0, #0 +10002b4a: d072 beq.n 10002c32 <_vsnprintf+0x8b6> +10002b4c: 2200 movs r2, #0 +10002b4e: 4611 mov r1, r2 +10002b50: aa12 add r2, sp, #72 @ 0x48 +10002b52: 920b str r2, [sp, #44] @ 0x2c +10002b54: e9cd 5305 strd r5, r3, [sp, #20] +10002b58: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b5a: 4642 mov r2, r8 +10002b5c: 9300 str r3, [sp, #0] +10002b5e: 2300 movs r3, #0 +10002b60: e9cd c603 strd ip, r6, [sp, #12] +10002b64: 9101 str r1, [sp, #4] +10002b66: 9302 str r3, [sp, #8] +10002b68: e794 b.n 10002a94 <_vsnprintf+0x718> +10002b6a: 42a5 cmp r5, r4 +10002b6c: bf98 it ls +10002b6e: 3401 addls r4, #1 +10002b70: f67f ad74 bls.w 1000265c <_vsnprintf+0x2e0> +10002b74: f44f 6380 mov.w r3, #1024 @ 0x400 +10002b78: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002b7c: eb05 0208 add.w r2, r5, r8 +10002b80: 461f mov r7, r3 +10002b82: 460d mov r5, r1 +10002b84: 1b14 subs r4, r2, r4 +10002b86: 4642 mov r2, r8 +10002b88: 464b mov r3, r9 +10002b8a: 4651 mov r1, sl +10002b8c: 2020 movs r0, #32 +10002b8e: f108 0801 add.w r8, r8, #1 +10002b92: 47d8 blx fp +10002b94: 45a0 cmp r8, r4 +10002b96: d1f6 bne.n 10002b86 <_vsnprintf+0x80a> +10002b98: 463b mov r3, r7 +10002b9a: 9f0a ldr r7, [sp, #40] @ 0x28 +10002b9c: 4629 mov r1, r5 +10002b9e: 7838 ldrb r0, [r7, #0] +10002ba0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002ba2: 1c6c adds r4, r5, #1 +10002ba4: 2800 cmp r0, #0 +10002ba6: f43f ad70 beq.w 1000268a <_vsnprintf+0x30e> +10002baa: 2b00 cmp r3, #0 +10002bac: f43f ae75 beq.w 1000289a <_vsnprintf+0x51e> +10002bb0: 2300 movs r3, #0 +10002bb2: e553 b.n 1000265c <_vsnprintf+0x2e0> +10002bb4: 42a5 cmp r5, r4 +10002bb6: d8df bhi.n 10002b78 <_vsnprintf+0x7fc> +10002bb8: 3401 adds r4, #1 +10002bba: e66e b.n 1000289a <_vsnprintf+0x51e> +10002bbc: 6819 ldr r1, [r3, #0] +10002bbe: 0fcb lsrs r3, r1, #31 +10002bc0: 2900 cmp r1, #0 +10002bc2: f000 80a8 beq.w 10002d16 <_vsnprintf+0x99a> +10002bc6: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002bca: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002bce: a912 add r1, sp, #72 @ 0x48 +10002bd0: 4608 mov r0, r1 +10002bd2: f8df e188 ldr.w lr, [pc, #392] @ 10002d5c <_vsnprintf+0x9e0> +10002bd6: 910b str r1, [sp, #44] @ 0x2c +10002bd8: 930a str r3, [sp, #40] @ 0x28 +10002bda: 950c str r5, [sp, #48] @ 0x30 +10002bdc: e001 b.n 10002be2 <_vsnprintf+0x866> +10002bde: 2f20 cmp r7, #32 +10002be0: d00f beq.n 10002c02 <_vsnprintf+0x886> +10002be2: 4615 mov r5, r2 +10002be4: fbae 1302 umull r1, r3, lr, r2 +10002be8: 08db lsrs r3, r3, #3 +10002bea: eb03 0183 add.w r1, r3, r3, lsl #2 +10002bee: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002bf2: 3130 adds r1, #48 @ 0x30 +10002bf4: 2d09 cmp r5, #9 +10002bf6: 461a mov r2, r3 +10002bf8: f107 0701 add.w r7, r7, #1 +10002bfc: f800 1b01 strb.w r1, [r0], #1 +10002c00: d8ed bhi.n 10002bde <_vsnprintf+0x862> +10002c02: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c04: 9d0c ldr r5, [sp, #48] @ 0x30 +10002c06: e9cd 5c05 strd r5, ip, [sp, #20] +10002c0a: e9cd 7301 strd r7, r3, [sp, #4] +10002c0e: 9604 str r6, [sp, #16] +10002c10: e6d5 b.n 100029be <_vsnprintf+0x642> +10002c12: 2869 cmp r0, #105 @ 0x69 +10002c14: f023 0c10 bic.w ip, r3, #16 +10002c18: f040 808c bne.w 10002d34 <_vsnprintf+0x9b8> +10002c1c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002c20: f43f ae8e beq.w 10002940 <_vsnprintf+0x5c4> +10002c24: e688 b.n 10002938 <_vsnprintf+0x5bc> +10002c26: 2a00 cmp r2, #0 +10002c28: f43f aea8 beq.w 1000297c <_vsnprintf+0x600> +10002c2c: aa12 add r2, sp, #72 @ 0x48 +10002c2e: 920b str r2, [sp, #44] @ 0x2c +10002c30: e6c0 b.n 100029b4 <_vsnprintf+0x638> +10002c32: f013 0f20 tst.w r3, #32 +10002c36: bf14 ite ne +10002c38: 2241 movne r2, #65 @ 0x41 +10002c3a: 2261 moveq r2, #97 @ 0x61 +10002c3c: 2000 movs r0, #0 +10002c3e: a912 add r1, sp, #72 @ 0x48 +10002c40: 3a0a subs r2, #10 +10002c42: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002c46: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002c4a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002c4e: 4606 mov r6, r0 +10002c50: 4688 mov r8, r1 +10002c52: 4675 mov r5, lr +10002c54: 4693 mov fp, r2 +10002c56: 910b str r1, [sp, #44] @ 0x2c +10002c58: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002c5c: e003 b.n 10002c66 <_vsnprintf+0x8ea> +10002c5e: 2e20 cmp r6, #32 +10002c60: d017 beq.n 10002c92 <_vsnprintf+0x916> +10002c62: 4604 mov r4, r0 +10002c64: 460d mov r5, r1 +10002c66: 4629 mov r1, r5 +10002c68: 463a mov r2, r7 +10002c6a: 2300 movs r3, #0 +10002c6c: 4620 mov r0, r4 +10002c6e: f000 fc47 bl 10003500 <____aeabi_uldivmod_veneer> +10002c72: b2d2 uxtb r2, r2 +10002c74: 2a09 cmp r2, #9 +10002c76: f102 0330 add.w r3, r2, #48 @ 0x30 +10002c7a: bf88 it hi +10002c7c: eb02 030b addhi.w r3, r2, fp +10002c80: 42bc cmp r4, r7 +10002c82: b2db uxtb r3, r3 +10002c84: f175 0500 sbcs.w r5, r5, #0 +10002c88: f808 3b01 strb.w r3, [r8], #1 +10002c8c: f106 0601 add.w r6, r6, #1 +10002c90: d2e5 bcs.n 10002c5e <_vsnprintf+0x8e2> +10002c92: 4631 mov r1, r6 +10002c94: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002c98: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002c9c: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002ca0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002ca2: e757 b.n 10002b54 <_vsnprintf+0x7d8> +10002ca4: 990a ldr r1, [sp, #40] @ 0x28 +10002ca6: 6809 ldr r1, [r1, #0] +10002ca8: b951 cbnz r1, 10002cc0 <_vsnprintf+0x944> +10002caa: f023 0310 bic.w r3, r3, #16 +10002cae: b138 cbz r0, 10002cc0 <_vsnprintf+0x944> +10002cb0: a912 add r1, sp, #72 @ 0x48 +10002cb2: 910b str r1, [sp, #44] @ 0x2c +10002cb4: e9cd 5305 strd r5, r3, [sp, #20] +10002cb8: e9cd c603 strd ip, r6, [sp, #12] +10002cbc: 9201 str r2, [sp, #4] +10002cbe: e5cf b.n 10002860 <_vsnprintf+0x4e4> +10002cc0: f013 0f20 tst.w r3, #32 +10002cc4: bf14 ite ne +10002cc6: 2041 movne r0, #65 @ 0x41 +10002cc8: 2061 moveq r0, #97 @ 0x61 +10002cca: ac12 add r4, sp, #72 @ 0x48 +10002ccc: 46a6 mov lr, r4 +10002cce: 940b str r4, [sp, #44] @ 0x2c +10002cd0: 930a str r3, [sp, #40] @ 0x28 +10002cd2: f1a0 040a sub.w r4, r0, #10 +10002cd6: 950c str r5, [sp, #48] @ 0x30 +10002cd8: e002 b.n 10002ce0 <_vsnprintf+0x964> +10002cda: 2a20 cmp r2, #32 +10002cdc: d012 beq.n 10002d04 <_vsnprintf+0x988> +10002cde: 4629 mov r1, r5 +10002ce0: fbb1 f5fc udiv r5, r1, ip +10002ce4: fb0c 1015 mls r0, ip, r5, r1 +10002ce8: b2c3 uxtb r3, r0 +10002cea: 2809 cmp r0, #9 +10002cec: f103 0030 add.w r0, r3, #48 @ 0x30 +10002cf0: bf8a itet hi +10002cf2: 191b addhi r3, r3, r4 +10002cf4: b2c3 uxtbls r3, r0 +10002cf6: b2db uxtbhi r3, r3 +10002cf8: 4561 cmp r1, ip +10002cfa: f80e 3b01 strb.w r3, [lr], #1 +10002cfe: f102 0201 add.w r2, r2, #1 +10002d02: d2ea bcs.n 10002cda <_vsnprintf+0x95e> +10002d04: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d06: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d08: e7d4 b.n 10002cb4 <_vsnprintf+0x938> +10002d0a: 6819 ldr r1, [r3, #0] +10002d0c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002d10: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002d14: e62d b.n 10002972 <_vsnprintf+0x5f6> +10002d16: 2a00 cmp r2, #0 +10002d18: f43f af59 beq.w 10002bce <_vsnprintf+0x852> +10002d1c: aa12 add r2, sp, #72 @ 0x48 +10002d1e: 920b str r2, [sp, #44] @ 0x2c +10002d20: e771 b.n 10002c06 <_vsnprintf+0x88a> +10002d22: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002d26: d00d beq.n 10002d44 <_vsnprintf+0x9c8> +10002d28: f013 0402 ands.w r4, r3, #2 +10002d2c: d012 beq.n 10002d54 <_vsnprintf+0x9d8> +10002d2e: 4604 mov r4, r0 +10002d30: 4646 mov r6, r8 +10002d32: e5ec b.n 1000290e <_vsnprintf+0x592> +10002d34: 270a movs r7, #10 +10002d36: 4663 mov r3, ip +10002d38: 46bc mov ip, r7 +10002d3a: e56c b.n 10002816 <_vsnprintf+0x49a> +10002d3c: ab12 add r3, sp, #72 @ 0x48 +10002d3e: 2000 movs r0, #0 +10002d40: 930b str r3, [sp, #44] @ 0x2c +10002d42: e69d b.n 10002a80 <_vsnprintf+0x704> +10002d44: f013 0302 ands.w r3, r3, #2 +10002d48: f47f ade0 bne.w 1000290c <_vsnprintf+0x590> +10002d4c: 2d00 cmp r5, #0 +10002d4e: f47f af13 bne.w 10002b78 <_vsnprintf+0x7fc> +10002d52: e49a b.n 1000268a <_vsnprintf+0x30e> +10002d54: 2d00 cmp r5, #0 +10002d56: f47f af0d bne.w 10002b74 <_vsnprintf+0x7f8> +10002d5a: e496 b.n 1000268a <_vsnprintf+0x30e> +10002d5c: cccccccd .word 0xcccccccd + +10002d60 : +10002d60: b570 push {r4, r5, r6, lr} +10002d62: 4694 mov ip, r2 +10002d64: 461e mov r6, r3 +10002d66: 4605 mov r5, r0 +10002d68: 460c mov r4, r1 +10002d6a: b084 sub sp, #16 +10002d6c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002d70: 4663 mov r3, ip +10002d72: a902 add r1, sp, #8 +10002d74: 9600 str r6, [sp, #0] +10002d76: 4803 ldr r0, [pc, #12] @ (10002d84 ) +10002d78: e9cd 5402 strd r5, r4, [sp, #8] +10002d7c: f7ff fafe bl 1000237c <_vsnprintf> +10002d80: b004 add sp, #16 +10002d82: bd70 pop {r4, r5, r6, pc} +10002d84: 1000193d .word 0x1000193d + +10002d88 : +10002d88: b510 push {r4, lr} +10002d8a: 4b09 ldr r3, [pc, #36] @ (10002db0 ) +10002d8c: b084 sub sp, #16 +10002d8e: 681c ldr r4, [r3, #0] +10002d90: b14c cbz r4, 10002da6 +10002d92: 4603 mov r3, r0 +10002d94: 9100 str r1, [sp, #0] +10002d96: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002d9a: a903 add r1, sp, #12 +10002d9c: 4805 ldr r0, [pc, #20] @ (10002db4 ) +10002d9e: 47a0 blx r4 +10002da0: 2001 movs r0, #1 +10002da2: b004 add sp, #16 +10002da4: bd10 pop {r4, pc} +10002da6: f000 f97d bl 100030a4 <__wrap_puts> +10002daa: 4620 mov r0, r4 +10002dac: b004 add sp, #16 +10002dae: bd10 pop {r4, pc} +10002db0: 2000080c .word 0x2000080c +10002db4: 10001935 .word 0x10001935 + +10002db8 <_exit>: +10002db8: be00 bkpt 0x0000 +10002dba: e7fd b.n 10002db8 <_exit> + +10002dbc : +10002dbc: b508 push {r3, lr} +10002dbe: f7ff fffb bl 10002db8 <_exit> +10002dc2: bf00 nop + +10002dc4 : +10002dc4: b538 push {r3, r4, r5, lr} +10002dc6: 4c06 ldr r4, [pc, #24] @ (10002de0 ) +10002dc8: 4d06 ldr r5, [pc, #24] @ (10002de4 ) +10002dca: f7fe fa07 bl 100011dc +10002dce: 42ac cmp r4, r5 +10002dd0: d204 bcs.n 10002ddc +10002dd2: f854 3b04 ldr.w r3, [r4], #4 +10002dd6: 4798 blx r3 +10002dd8: 42ac cmp r4, r5 +10002dda: d3fa bcc.n 10002dd2 +10002ddc: bd38 pop {r3, r4, r5, pc} +10002dde: bf00 nop +10002de0: 10003558 .word 0x10003558 +10002de4: 1000355c .word 0x1000355c + +10002de8 : +10002de8: 6803 ldr r3, [r0, #0] +10002dea: 4608 mov r0, r1 +10002dec: 4611 mov r1, r2 +10002dee: 4718 bx r3 + +10002df0 : +10002df0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002df4: 4615 mov r5, r2 +10002df6: 7d42 ldrb r2, [r0, #21] +10002df8: 4607 mov r7, r0 +10002dfa: 4688 mov r8, r1 +10002dfc: 2a00 cmp r2, #0 +10002dfe: d046 beq.n 10002e8e +10002e00: 2d00 cmp r5, #0 +10002e02: dd1d ble.n 10002e40 +10002e04: 780b ldrb r3, [r1, #0] +10002e06: 2b0a cmp r3, #10 +10002e08: d023 beq.n 10002e52 +10002e0a: 2d01 cmp r5, #1 +10002e0c: f04f 0c00 mov.w ip, #0 +10002e10: d018 beq.n 10002e44 +10002e12: 4646 mov r6, r8 +10002e14: 2401 movs r4, #1 +10002e16: f816 2f01 ldrb.w r2, [r6, #1]! +10002e1a: 4621 mov r1, r4 +10002e1c: 2a0a cmp r2, #10 +10002e1e: f104 0401 add.w r4, r4, #1 +10002e22: d022 beq.n 10002e6a +10002e24: 42a5 cmp r5, r4 +10002e26: d1f6 bne.n 10002e16 +10002e28: 4565 cmp r5, ip +10002e2a: dc0b bgt.n 10002e44 +10002e2c: eb08 0305 add.w r3, r8, r5 +10002e30: f813 3c01 ldrb.w r3, [r3, #-1] +10002e34: f1a3 030d sub.w r3, r3, #13 +10002e38: fab3 f383 clz r3, r3 +10002e3c: 095b lsrs r3, r3, #5 +10002e3e: 753b strb r3, [r7, #20] +10002e40: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002e44: 683b ldr r3, [r7, #0] +10002e46: eba5 010c sub.w r1, r5, ip +10002e4a: eb08 000c add.w r0, r8, ip +10002e4e: 4798 blx r3 +10002e50: e7ec b.n 10002e2c +10002e52: 7d03 ldrb r3, [r0, #20] +10002e54: 2b00 cmp r3, #0 +10002e56: d1d8 bne.n 10002e0a +10002e58: 6803 ldr r3, [r0, #0] +10002e5a: 2102 movs r1, #2 +10002e5c: 480f ldr r0, [pc, #60] @ (10002e9c ) +10002e5e: 4798 blx r3 +10002e60: 2d01 cmp r5, #1 +10002e62: d0e3 beq.n 10002e2c +10002e64: f04f 0c01 mov.w ip, #1 +10002e68: e7d3 b.n 10002e12 +10002e6a: f816 3c01 ldrb.w r3, [r6, #-1] +10002e6e: 2b0d cmp r3, #13 +10002e70: d0d8 beq.n 10002e24 +10002e72: 458c cmp ip, r1 +10002e74: eb08 000c add.w r0, r8, ip +10002e78: eba1 010c sub.w r1, r1, ip +10002e7c: da01 bge.n 10002e82 +10002e7e: 683b ldr r3, [r7, #0] +10002e80: 4798 blx r3 +10002e82: 2102 movs r1, #2 +10002e84: 4805 ldr r0, [pc, #20] @ (10002e9c ) +10002e86: 683b ldr r3, [r7, #0] +10002e88: 4798 blx r3 +10002e8a: 46a4 mov ip, r4 +10002e8c: e7ca b.n 10002e24 +10002e8e: 4629 mov r1, r5 +10002e90: 4640 mov r0, r8 +10002e92: 683b ldr r3, [r7, #0] +10002e94: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10002e98: 4718 bx r3 +10002e9a: bf00 nop +10002e9c: 10003718 .word 0x10003718 + +10002ea0 : +10002ea0: 680b ldr r3, [r1, #0] +10002ea2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10002ea6: 2b80 cmp r3, #128 @ 0x80 +10002ea8: 460d mov r5, r1 +10002eaa: 4606 mov r6, r0 +10002eac: d005 beq.n 10002eba +10002eae: 1c5a adds r2, r3, #1 +10002eb0: 442b add r3, r5 +10002eb2: 602a str r2, [r5, #0] +10002eb4: 711e strb r6, [r3, #4] +10002eb6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002eba: 4b0f ldr r3, [pc, #60] @ (10002ef8 ) +10002ebc: 681c ldr r4, [r3, #0] +10002ebe: b1a4 cbz r4, 10002eea +10002ec0: 4f0e ldr r7, [pc, #56] @ (10002efc ) +10002ec2: f101 0804 add.w r8, r1, #4 +10002ec6: e001 b.n 10002ecc +10002ec8: 6924 ldr r4, [r4, #16] +10002eca: b174 cbz r4, 10002eea +10002ecc: 6823 ldr r3, [r4, #0] +10002ece: 2b00 cmp r3, #0 +10002ed0: d0fa beq.n 10002ec8 +10002ed2: 683b ldr r3, [r7, #0] +10002ed4: b10b cbz r3, 10002eda +10002ed6: 42a3 cmp r3, r4 +10002ed8: d1f6 bne.n 10002ec8 +10002eda: 4620 mov r0, r4 +10002edc: 4641 mov r1, r8 +10002ede: 682a ldr r2, [r5, #0] +10002ee0: f7ff ff86 bl 10002df0 +10002ee4: 6924 ldr r4, [r4, #16] +10002ee6: 2c00 cmp r4, #0 +10002ee8: d1f0 bne.n 10002ecc +10002eea: 2300 movs r3, #0 +10002eec: 2201 movs r2, #1 +10002eee: 442b add r3, r5 +10002ef0: 602a str r2, [r5, #0] +10002ef2: 711e strb r6, [r3, #4] +10002ef4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10002ef8: 20000804 .word 0x20000804 +10002efc: 20000808 .word 0x20000808 + +10002f00 : +10002f00: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10002f04: b082 sub sp, #8 +10002f06: 460d mov r5, r1 +10002f08: 4691 mov r9, r2 +10002f0a: 461c mov r4, r3 +10002f0c: 4606 mov r6, r0 +10002f0e: f7fd ffa7 bl 10000e60 +10002f12: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10002f16: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10002f1a: 4a2e ldr r2, [pc, #184] @ (10002fd4 ) +10002f1c: 1882 adds r2, r0, r2 +10002f1e: f141 0300 adc.w r3, r1, #0 +10002f22: 4594 cmp ip, r2 +10002f24: eb77 0103 sbcs.w r1, r7, r3 +10002f28: bf3c itt cc +10002f2a: 4662 movcc r2, ip +10002f2c: 463b movcc r3, r7 +10002f2e: 482a ldr r0, [pc, #168] @ (10002fd8 ) +10002f30: f000 faee bl 10003510 <__mutex_try_enter_block_until_veneer> +10002f34: 1c6b adds r3, r5, #1 +10002f36: 4680 mov r8, r0 +10002f38: d040 beq.n 10002fbc +10002f3a: b30c cbz r4, 10002f80 +10002f3c: 4f27 ldr r7, [pc, #156] @ (10002fdc ) +10002f3e: 4b28 ldr r3, [pc, #160] @ (10002fe0 ) +10002f40: 681c ldr r4, [r3, #0] +10002f42: b1b4 cbz r4, 10002f72 +10002f44: f1b9 0f00 cmp.w r9, #0 +10002f48: d11c bne.n 10002f84 +10002f4a: f8df 909c ldr.w r9, [pc, #156] @ 10002fe8 +10002f4e: e001 b.n 10002f54 +10002f50: 6924 ldr r4, [r4, #16] +10002f52: b174 cbz r4, 10002f72 +10002f54: 6823 ldr r3, [r4, #0] +10002f56: 2b00 cmp r3, #0 +10002f58: d0fa beq.n 10002f50 +10002f5a: f8d9 3000 ldr.w r3, [r9] +10002f5e: b10b cbz r3, 10002f64 +10002f60: 429c cmp r4, r3 +10002f62: d1f5 bne.n 10002f50 +10002f64: 4620 mov r0, r4 +10002f66: 462a mov r2, r5 +10002f68: 4631 mov r1, r6 +10002f6a: 47b8 blx r7 +10002f6c: 6924 ldr r4, [r4, #16] +10002f6e: 2c00 cmp r4, #0 +10002f70: d1f0 bne.n 10002f54 +10002f72: f1b8 0f00 cmp.w r8, #0 +10002f76: d126 bne.n 10002fc6 +10002f78: 4628 mov r0, r5 +10002f7a: b002 add sp, #8 +10002f7c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002f80: 4f18 ldr r7, [pc, #96] @ (10002fe4 ) +10002f82: e7dc b.n 10002f3e +10002f84: f04f 0a0a mov.w sl, #10 +10002f88: f8df 905c ldr.w r9, [pc, #92] @ 10002fe8 +10002f8c: e002 b.n 10002f94 +10002f8e: 6924 ldr r4, [r4, #16] +10002f90: 2c00 cmp r4, #0 +10002f92: d0ee beq.n 10002f72 +10002f94: 6823 ldr r3, [r4, #0] +10002f96: 2b00 cmp r3, #0 +10002f98: d0f9 beq.n 10002f8e +10002f9a: f8d9 3000 ldr.w r3, [r9] +10002f9e: b10b cbz r3, 10002fa4 +10002fa0: 42a3 cmp r3, r4 +10002fa2: d1f4 bne.n 10002f8e +10002fa4: 462a mov r2, r5 +10002fa6: 4631 mov r1, r6 +10002fa8: 4620 mov r0, r4 +10002faa: 47b8 blx r7 +10002fac: 2201 movs r2, #1 +10002fae: 4620 mov r0, r4 +10002fb0: f10d 0107 add.w r1, sp, #7 +10002fb4: f88d a007 strb.w sl, [sp, #7] +10002fb8: 47b8 blx r7 +10002fba: e7e8 b.n 10002f8e +10002fbc: 4630 mov r0, r6 +10002fbe: f000 fa6f bl 100034a0 +10002fc2: 4605 mov r5, r0 +10002fc4: e7b9 b.n 10002f3a +10002fc6: 4804 ldr r0, [pc, #16] @ (10002fd8 ) +10002fc8: f000 fa9e bl 10003508 <__mutex_exit_veneer> +10002fcc: 4628 mov r0, r5 +10002fce: b002 add sp, #8 +10002fd0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10002fd4: 000f4240 .word 0x000f4240 +10002fd8: 20000624 .word 0x20000624 +10002fdc: 10002df1 .word 0x10002df1 +10002fe0: 20000804 .word 0x20000804 +10002fe4: 10002de9 .word 0x10002de9 +10002fe8: 20000808 .word 0x20000808 + +10002fec : +10002fec: 4a08 ldr r2, [pc, #32] @ (10003010 ) +10002fee: 6813 ldr r3, [r2, #0] +10002ff0: b923 cbnz r3, 10002ffc +10002ff2: e00a b.n 1000300a +10002ff4: f103 0210 add.w r2, r3, #16 +10002ff8: 691b ldr r3, [r3, #16] +10002ffa: b133 cbz r3, 1000300a +10002ffc: 4283 cmp r3, r0 +10002ffe: d1f9 bne.n 10002ff4 +10003000: b929 cbnz r1, 1000300e +10003002: 6918 ldr r0, [r3, #16] +10003004: 6010 str r0, [r2, #0] +10003006: 6119 str r1, [r3, #16] +10003008: 4770 bx lr +1000300a: b101 cbz r1, 1000300e +1000300c: 6010 str r0, [r2, #0] +1000300e: 4770 bx lr +10003010: 20000804 .word 0x20000804 + +10003014 : +10003014: b508 push {r3, lr} +10003016: f000 f9a3 bl 10003360 +1000301a: 2001 movs r0, #1 +1000301c: bd08 pop {r3, pc} +1000301e: bf00 nop + +10003020 <__wrap_putchar>: +10003020: b5f0 push {r4, r5, r6, r7, lr} +10003022: b083 sub sp, #12 +10003024: 4606 mov r6, r0 +10003026: f88d 0007 strb.w r0, [sp, #7] +1000302a: f7fd ff19 bl 10000e60 +1000302e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10003032: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10003036: 4a17 ldr r2, [pc, #92] @ (10003094 <__wrap_putchar+0x74>) +10003038: 1882 adds r2, r0, r2 +1000303a: f141 0300 adc.w r3, r1, #0 +1000303e: 4295 cmp r5, r2 +10003040: eb74 0103 sbcs.w r1, r4, r3 +10003044: bf3c itt cc +10003046: 4623 movcc r3, r4 +10003048: 462a movcc r2, r5 +1000304a: 4813 ldr r0, [pc, #76] @ (10003098 <__wrap_putchar+0x78>) +1000304c: f000 fa60 bl 10003510 <__mutex_try_enter_block_until_veneer> +10003050: 4b12 ldr r3, [pc, #72] @ (1000309c <__wrap_putchar+0x7c>) +10003052: 4607 mov r7, r0 +10003054: 681c ldr r4, [r3, #0] +10003056: b19c cbz r4, 10003080 <__wrap_putchar+0x60> +10003058: 4d11 ldr r5, [pc, #68] @ (100030a0 <__wrap_putchar+0x80>) +1000305a: e001 b.n 10003060 <__wrap_putchar+0x40> +1000305c: 6924 ldr r4, [r4, #16] +1000305e: b17c cbz r4, 10003080 <__wrap_putchar+0x60> +10003060: 6823 ldr r3, [r4, #0] +10003062: 2b00 cmp r3, #0 +10003064: d0fa beq.n 1000305c <__wrap_putchar+0x3c> +10003066: 682b ldr r3, [r5, #0] +10003068: b10b cbz r3, 1000306e <__wrap_putchar+0x4e> +1000306a: 429c cmp r4, r3 +1000306c: d1f6 bne.n 1000305c <__wrap_putchar+0x3c> +1000306e: 4620 mov r0, r4 +10003070: 2201 movs r2, #1 +10003072: f10d 0107 add.w r1, sp, #7 +10003076: f7ff febb bl 10002df0 +1000307a: 6924 ldr r4, [r4, #16] +1000307c: 2c00 cmp r4, #0 +1000307e: d1ef bne.n 10003060 <__wrap_putchar+0x40> +10003080: b917 cbnz r7, 10003088 <__wrap_putchar+0x68> +10003082: 4630 mov r0, r6 +10003084: b003 add sp, #12 +10003086: bdf0 pop {r4, r5, r6, r7, pc} +10003088: 4803 ldr r0, [pc, #12] @ (10003098 <__wrap_putchar+0x78>) +1000308a: f000 fa3d bl 10003508 <__mutex_exit_veneer> +1000308e: 4630 mov r0, r6 +10003090: b003 add sp, #12 +10003092: bdf0 pop {r4, r5, r6, r7, pc} +10003094: 000f4240 .word 0x000f4240 +10003098: 20000624 .word 0x20000624 +1000309c: 20000804 .word 0x20000804 +100030a0: 20000808 .word 0x20000808 + +100030a4 <__wrap_puts>: +100030a4: b538 push {r3, r4, r5, lr} +100030a6: 4604 mov r4, r0 +100030a8: f000 f9fa bl 100034a0 +100030ac: 2301 movs r3, #1 +100030ae: 4605 mov r5, r0 +100030b0: 461a mov r2, r3 +100030b2: 4620 mov r0, r4 +100030b4: 4629 mov r1, r5 +100030b6: f7ff ff23 bl 10002f00 +100030ba: 4b08 ldr r3, [pc, #32] @ (100030dc <__wrap_puts+0x38>) +100030bc: 681c ldr r4, [r3, #0] +100030be: b12c cbz r4, 100030cc <__wrap_puts+0x28> +100030c0: 6863 ldr r3, [r4, #4] +100030c2: b12b cbz r3, 100030d0 <__wrap_puts+0x2c> +100030c4: 4798 blx r3 +100030c6: 6924 ldr r4, [r4, #16] +100030c8: 2c00 cmp r4, #0 +100030ca: d1f9 bne.n 100030c0 <__wrap_puts+0x1c> +100030cc: 4628 mov r0, r5 +100030ce: bd38 pop {r3, r4, r5, pc} +100030d0: 6924 ldr r4, [r4, #16] +100030d2: 2c00 cmp r4, #0 +100030d4: d1f4 bne.n 100030c0 <__wrap_puts+0x1c> +100030d6: 4628 mov r0, r5 +100030d8: bd38 pop {r3, r4, r5, pc} +100030da: bf00 nop +100030dc: 20000804 .word 0x20000804 + +100030e0 <__wrap_vprintf>: +100030e0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100030e4: b0a2 sub sp, #136 @ 0x88 +100030e6: 4604 mov r4, r0 +100030e8: 460d mov r5, r1 +100030ea: f7fd feb9 bl 10000e60 +100030ee: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +100030f2: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +100030f6: 4a26 ldr r2, [pc, #152] @ (10003190 <__wrap_vprintf+0xb0>) +100030f8: f8df 80a4 ldr.w r8, [pc, #164] @ 100031a0 <__wrap_vprintf+0xc0> +100030fc: 1882 adds r2, r0, r2 +100030fe: f141 0300 adc.w r3, r1, #0 +10003102: 4297 cmp r7, r2 +10003104: eb76 0103 sbcs.w r1, r6, r3 +10003108: bf3c itt cc +1000310a: 463a movcc r2, r7 +1000310c: 4633 movcc r3, r6 +1000310e: 4821 ldr r0, [pc, #132] @ (10003194 <__wrap_vprintf+0xb4>) +10003110: f000 f9fe bl 10003510 <__mutex_try_enter_block_until_veneer> +10003114: 2700 movs r7, #0 +10003116: 462b mov r3, r5 +10003118: 4622 mov r2, r4 +1000311a: 4606 mov r6, r0 +1000311c: a901 add r1, sp, #4 +1000311e: 481e ldr r0, [pc, #120] @ (10003198 <__wrap_vprintf+0xb8>) +10003120: 9701 str r7, [sp, #4] +10003122: f7ff fe1d bl 10002d60 +10003126: 9b01 ldr r3, [sp, #4] +10003128: 4605 mov r5, r0 +1000312a: f8d8 4000 ldr.w r4, [r8] +1000312e: b1c3 cbz r3, 10003162 <__wrap_vprintf+0x82> +10003130: 2c00 cmp r4, #0 +10003132: d02b beq.n 1000318c <__wrap_vprintf+0xac> +10003134: 4f19 ldr r7, [pc, #100] @ (1000319c <__wrap_vprintf+0xbc>) +10003136: e001 b.n 1000313c <__wrap_vprintf+0x5c> +10003138: 6924 ldr r4, [r4, #16] +1000313a: b174 cbz r4, 1000315a <__wrap_vprintf+0x7a> +1000313c: 6823 ldr r3, [r4, #0] +1000313e: 2b00 cmp r3, #0 +10003140: d0fa beq.n 10003138 <__wrap_vprintf+0x58> +10003142: 683b ldr r3, [r7, #0] +10003144: b10b cbz r3, 1000314a <__wrap_vprintf+0x6a> +10003146: 42a3 cmp r3, r4 +10003148: d1f6 bne.n 10003138 <__wrap_vprintf+0x58> +1000314a: 4620 mov r0, r4 +1000314c: 9a01 ldr r2, [sp, #4] +1000314e: a902 add r1, sp, #8 +10003150: f7ff fe4e bl 10002df0 +10003154: 6924 ldr r4, [r4, #16] +10003156: 2c00 cmp r4, #0 +10003158: d1f0 bne.n 1000313c <__wrap_vprintf+0x5c> +1000315a: 2300 movs r3, #0 +1000315c: f8d8 4000 ldr.w r4, [r8] +10003160: 9301 str r3, [sp, #4] +10003162: b12c cbz r4, 10003170 <__wrap_vprintf+0x90> +10003164: 6863 ldr r3, [r4, #4] +10003166: b143 cbz r3, 1000317a <__wrap_vprintf+0x9a> +10003168: 4798 blx r3 +1000316a: 6924 ldr r4, [r4, #16] +1000316c: 2c00 cmp r4, #0 +1000316e: d1f9 bne.n 10003164 <__wrap_vprintf+0x84> +10003170: b92e cbnz r6, 1000317e <__wrap_vprintf+0x9e> +10003172: 4628 mov r0, r5 +10003174: b022 add sp, #136 @ 0x88 +10003176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000317a: 6924 ldr r4, [r4, #16] +1000317c: e7f1 b.n 10003162 <__wrap_vprintf+0x82> +1000317e: 4805 ldr r0, [pc, #20] @ (10003194 <__wrap_vprintf+0xb4>) +10003180: f000 f9c2 bl 10003508 <__mutex_exit_veneer> +10003184: 4628 mov r0, r5 +10003186: b022 add sp, #136 @ 0x88 +10003188: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000318c: 9401 str r4, [sp, #4] +1000318e: e7ef b.n 10003170 <__wrap_vprintf+0x90> +10003190: 000f4240 .word 0x000f4240 +10003194: 20000624 .word 0x20000624 +10003198: 10002ea1 .word 0x10002ea1 +1000319c: 20000808 .word 0x20000808 +100031a0: 20000804 .word 0x20000804 + +100031a4 <__wrap_printf>: +100031a4: b40f push {r0, r1, r2, r3} +100031a6: b500 push {lr} +100031a8: b083 sub sp, #12 +100031aa: a904 add r1, sp, #16 +100031ac: f851 0b04 ldr.w r0, [r1], #4 +100031b0: 9101 str r1, [sp, #4] +100031b2: f7ff ff95 bl 100030e0 <__wrap_vprintf> +100031b6: b003 add sp, #12 +100031b8: f85d eb04 ldr.w lr, [sp], #4 +100031bc: b004 add sp, #16 +100031be: 4770 bx lr + +100031c0 : +100031c0: f1b1 0c00 subs.w ip, r1, #0 +100031c4: dd1d ble.n 10003202 +100031c6: 4a0f ldr r2, [pc, #60] @ (10003204 ) +100031c8: 4b0f ldr r3, [pc, #60] @ (10003208 ) +100031ca: 6812 ldr r2, [r2, #0] +100031cc: b530 push {r4, r5, lr} +100031ce: 1ad3 subs r3, r2, r3 +100031d0: fab3 f383 clz r3, r3 +100031d4: 240d movs r4, #13 +100031d6: 4d0d ldr r5, [pc, #52] @ (1000320c ) +100031d8: 095b lsrs r3, r3, #5 +100031da: 1e41 subs r1, r0, #1 +100031dc: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +100031e0: 448c add ip, r1 +100031e2: f811 0f01 ldrb.w r0, [r1, #1]! +100031e6: 4586 cmp lr, r0 +100031e8: d006 beq.n 100031f8 +100031ea: 6993 ldr r3, [r2, #24] +100031ec: 069b lsls r3, r3, #26 +100031ee: d4fc bmi.n 100031ea +100031f0: 4561 cmp r1, ip +100031f2: 6010 str r0, [r2, #0] +100031f4: d1f5 bne.n 100031e2 +100031f6: bd30 pop {r4, r5, pc} +100031f8: 6993 ldr r3, [r2, #24] +100031fa: 069d lsls r5, r3, #26 +100031fc: d4fc bmi.n 100031f8 +100031fe: 6014 str r4, [r2, #0] +10003200: e7f3 b.n 100031ea +10003202: 4770 bx lr +10003204: 20000850 .word 0x20000850 +10003208: 40078000 .word 0x40078000 +1000320c: 2000084c .word 0x2000084c + +10003210 : +10003210: 4b22 ldr r3, [pc, #136] @ (1000329c ) +10003212: f1b1 0c00 subs.w ip, r1, #0 +10003216: b410 push {r4} +10003218: 681c ldr r4, [r3, #0] +1000321a: dd2e ble.n 1000327a +1000321c: 4603 mov r3, r0 +1000321e: 2000 movs r0, #0 +10003220: 4a1f ldr r2, [pc, #124] @ (100032a0 ) +10003222: 1e59 subs r1, r3, #1 +10003224: 6812 ldr r2, [r2, #0] +10003226: 6993 ldr r3, [r2, #24] +10003228: 06db lsls r3, r3, #27 +1000322a: d417 bmi.n 1000325c +1000322c: 3001 adds r0, #1 +1000322e: 6993 ldr r3, [r2, #24] +10003230: 06db lsls r3, r3, #27 +10003232: d4fc bmi.n 1000322e +10003234: 6813 ldr r3, [r2, #0] +10003236: 4584 cmp ip, r0 +10003238: f801 3f01 strb.w r3, [r1, #1]! +1000323c: d1f3 bne.n 10003226 +1000323e: b14c cbz r4, 10003254 +10003240: 2150 movs r1, #80 @ 0x50 +10003242: 4613 mov r3, r2 +10003244: 6391 str r1, [r2, #56] @ 0x38 +10003246: f853 2f34 ldr.w r2, [r3, #52]! +1000324a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000324e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003252: 601a str r2, [r3, #0] +10003254: 4660 mov r0, ip +10003256: f85d 4b04 ldr.w r4, [sp], #4 +1000325a: 4770 bx lr +1000325c: b14c cbz r4, 10003272 +1000325e: 2150 movs r1, #80 @ 0x50 +10003260: 4613 mov r3, r2 +10003262: 6391 str r1, [r2, #56] @ 0x38 +10003264: f853 2f34 ldr.w r2, [r3, #52]! +10003268: f002 0238 and.w r2, r2, #56 @ 0x38 +1000326c: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003270: 601a str r2, [r3, #0] +10003272: b178 cbz r0, 10003294 +10003274: f85d 4b04 ldr.w r4, [sp], #4 +10003278: 4770 bx lr +1000327a: b15c cbz r4, 10003294 +1000327c: 4b08 ldr r3, [pc, #32] @ (100032a0 ) +1000327e: 2150 movs r1, #80 @ 0x50 +10003280: 681a ldr r2, [r3, #0] +10003282: 4613 mov r3, r2 +10003284: 6391 str r1, [r2, #56] @ 0x38 +10003286: f853 2f34 ldr.w r2, [r3, #52]! +1000328a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000328e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003292: 601a str r2, [r3, #0] +10003294: f06f 0002 mvn.w r0, #2 +10003298: e7dd b.n 10003256 +1000329a: bf00 nop +1000329c: 200007d0 .word 0x200007d0 +100032a0: 20000850 .word 0x20000850 + +100032a4 : +100032a4: 4b05 ldr r3, [pc, #20] @ (100032bc ) +100032a6: 681b ldr r3, [r3, #0] +100032a8: b133 cbz r3, 100032b8 +100032aa: 2100 movs r1, #0 +100032ac: 4a04 ldr r2, [pc, #16] @ (100032c0 ) +100032ae: 4805 ldr r0, [pc, #20] @ (100032c4 ) +100032b0: 6812 ldr r2, [r2, #0] +100032b2: 6800 ldr r0, [r0, #0] +100032b4: 6391 str r1, [r2, #56] @ 0x38 +100032b6: 4718 bx r3 +100032b8: 4770 bx lr +100032ba: bf00 nop +100032bc: 200007d0 .word 0x200007d0 +100032c0: 20000850 .word 0x20000850 +100032c4: 200007d4 .word 0x200007d4 + +100032c8 : +100032c8: 4b02 ldr r3, [pc, #8] @ (100032d4 ) +100032ca: 681a ldr r2, [r3, #0] +100032cc: 6993 ldr r3, [r2, #24] +100032ce: 071b lsls r3, r3, #28 +100032d0: d4fc bmi.n 100032cc +100032d2: 4770 bx lr +100032d4: 20000850 .word 0x20000850 + +100032d8 : +100032d8: b5f8 push {r3, r4, r5, r6, r7, lr} +100032da: 4f1c ldr r7, [pc, #112] @ (1000334c ) +100032dc: 4d1c ldr r5, [pc, #112] @ (10003350 ) +100032de: 683a ldr r2, [r7, #0] +100032e0: 4e1c ldr r6, [pc, #112] @ (10003354 ) +100032e2: 42aa cmp r2, r5 +100032e4: bf14 ite ne +100032e6: 2521 movne r5, #33 @ 0x21 +100032e8: 2522 moveq r5, #34 @ 0x22 +100032ea: 4604 mov r4, r0 +100032ec: f8d6 c000 ldr.w ip, [r6] +100032f0: b118 cbz r0, 100032fa +100032f2: f1bc 0f00 cmp.w ip, #0 +100032f6: d010 beq.n 1000331a +100032f8: bdf8 pop {r3, r4, r5, r6, r7, pc} +100032fa: f1bc 0f00 cmp.w ip, #0 +100032fe: d0fb beq.n 100032f8 +10003300: 4601 mov r1, r0 +10003302: 6390 str r0, [r2, #56] @ 0x38 +10003304: 4628 mov r0, r5 +10003306: f7fd f8a3 bl 10000450 +1000330a: 4628 mov r0, r5 +1000330c: 4912 ldr r1, [pc, #72] @ (10003358 ) +1000330e: f7fd f8e5 bl 100004dc +10003312: 4b12 ldr r3, [pc, #72] @ (1000335c ) +10003314: 6034 str r4, [r6, #0] +10003316: 601c str r4, [r3, #0] +10003318: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000331a: 460b mov r3, r1 +1000331c: 4a0f ldr r2, [pc, #60] @ (1000335c ) +1000331e: 490e ldr r1, [pc, #56] @ (10003358 ) +10003320: 6030 str r0, [r6, #0] +10003322: 4628 mov r0, r5 +10003324: 6013 str r3, [r2, #0] +10003326: f7fd f8a9 bl 1000047c +1000332a: 2101 movs r1, #1 +1000332c: 4628 mov r0, r5 +1000332e: f7fd f88f bl 10000450 +10003332: 683a ldr r2, [r7, #0] +10003334: 2150 movs r1, #80 @ 0x50 +10003336: 4613 mov r3, r2 +10003338: 6391 str r1, [r2, #56] @ 0x38 +1000333a: f853 2f34 ldr.w r2, [r3, #52]! +1000333e: f002 0238 and.w r2, r2, #56 @ 0x38 +10003342: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003346: 601a str r2, [r3, #0] +10003348: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000334a: bf00 nop +1000334c: 20000850 .word 0x20000850 +10003350: 40078000 .word 0x40078000 +10003354: 200007d0 .word 0x200007d0 +10003358: 100032a5 .word 0x100032a5 +1000335c: 200007d4 .word 0x200007d4 + +10003360 : +10003360: b510 push {r4, lr} +10003362: 490e ldr r1, [pc, #56] @ (1000339c ) +10003364: 4c0e ldr r4, [pc, #56] @ (100033a0 ) +10003366: 480f ldr r0, [pc, #60] @ (100033a4 ) +10003368: 4a0f ldr r2, [pc, #60] @ (100033a8 ) +1000336a: 4b10 ldr r3, [pc, #64] @ (100033ac ) +1000336c: 7800 ldrb r0, [r0, #0] +1000336e: 6021 str r1, [r4, #0] +10003370: 2000 movs r0, #0 +10003372: 2102 movs r1, #2 +10003374: 7812 ldrb r2, [r2, #0] +10003376: 781b ldrb r3, [r3, #0] +10003378: f7fc ff90 bl 1000029c +1000337c: 2102 movs r1, #2 +1000337e: 2001 movs r0, #1 +10003380: f7fc ff8c bl 1000029c +10003384: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003388: 6820 ldr r0, [r4, #0] +1000338a: f7fd fda1 bl 10000ed0 +1000338e: e8bd 4010 ldmia.w sp!, {r4, lr} +10003392: 2101 movs r1, #1 +10003394: 4806 ldr r0, [pc, #24] @ (100033b0 ) +10003396: f7ff be29 b.w 10002fec +1000339a: bf00 nop +1000339c: 40070000 .word 0x40070000 +100033a0: 20000850 .word 0x20000850 +100033a4: 10003768 .word 0x10003768 +100033a8: 10003764 .word 0x10003764 +100033ac: 10003760 .word 0x10003760 +100033b0: 2000060c .word 0x2000060c + +100033b4 : +100033b4: 4684 mov ip, r0 +100033b6: ea41 0300 orr.w r3, r1, r0 +100033ba: f013 0303 ands.w r3, r3, #3 +100033be: d149 bne.n 10003454 +100033c0: 3a40 subs r2, #64 @ 0x40 +100033c2: d323 bcc.n 1000340c +100033c4: 680b ldr r3, [r1, #0] +100033c6: 6003 str r3, [r0, #0] +100033c8: 684b ldr r3, [r1, #4] +100033ca: 6043 str r3, [r0, #4] +100033cc: 688b ldr r3, [r1, #8] +100033ce: 6083 str r3, [r0, #8] +100033d0: 68cb ldr r3, [r1, #12] +100033d2: 60c3 str r3, [r0, #12] +100033d4: 690b ldr r3, [r1, #16] +100033d6: 6103 str r3, [r0, #16] +100033d8: 694b ldr r3, [r1, #20] +100033da: 6143 str r3, [r0, #20] +100033dc: 698b ldr r3, [r1, #24] +100033de: 6183 str r3, [r0, #24] +100033e0: 69cb ldr r3, [r1, #28] +100033e2: 61c3 str r3, [r0, #28] +100033e4: 6a0b ldr r3, [r1, #32] +100033e6: 6203 str r3, [r0, #32] +100033e8: 6a4b ldr r3, [r1, #36] @ 0x24 +100033ea: 6243 str r3, [r0, #36] @ 0x24 +100033ec: 6a8b ldr r3, [r1, #40] @ 0x28 +100033ee: 6283 str r3, [r0, #40] @ 0x28 +100033f0: 6acb ldr r3, [r1, #44] @ 0x2c +100033f2: 62c3 str r3, [r0, #44] @ 0x2c +100033f4: 6b0b ldr r3, [r1, #48] @ 0x30 +100033f6: 6303 str r3, [r0, #48] @ 0x30 +100033f8: 6b4b ldr r3, [r1, #52] @ 0x34 +100033fa: 6343 str r3, [r0, #52] @ 0x34 +100033fc: 6b8b ldr r3, [r1, #56] @ 0x38 +100033fe: 6383 str r3, [r0, #56] @ 0x38 +10003400: 6bcb ldr r3, [r1, #60] @ 0x3c +10003402: 63c3 str r3, [r0, #60] @ 0x3c +10003404: 3040 adds r0, #64 @ 0x40 +10003406: 3140 adds r1, #64 @ 0x40 +10003408: 3a40 subs r2, #64 @ 0x40 +1000340a: d2db bcs.n 100033c4 +1000340c: 3230 adds r2, #48 @ 0x30 +1000340e: d30b bcc.n 10003428 +10003410: 680b ldr r3, [r1, #0] +10003412: 6003 str r3, [r0, #0] +10003414: 684b ldr r3, [r1, #4] +10003416: 6043 str r3, [r0, #4] +10003418: 688b ldr r3, [r1, #8] +1000341a: 6083 str r3, [r0, #8] +1000341c: 68cb ldr r3, [r1, #12] +1000341e: 60c3 str r3, [r0, #12] +10003420: 3010 adds r0, #16 +10003422: 3110 adds r1, #16 +10003424: 3a10 subs r2, #16 +10003426: d2f3 bcs.n 10003410 +10003428: 320c adds r2, #12 +1000342a: d305 bcc.n 10003438 +1000342c: f851 3b04 ldr.w r3, [r1], #4 +10003430: f840 3b04 str.w r3, [r0], #4 +10003434: 3a04 subs r2, #4 +10003436: d2f9 bcs.n 1000342c +10003438: 3204 adds r2, #4 +1000343a: d008 beq.n 1000344e +1000343c: 07d2 lsls r2, r2, #31 +1000343e: bf1c itt ne +10003440: f811 3b01 ldrbne.w r3, [r1], #1 +10003444: f800 3b01 strbne.w r3, [r0], #1 +10003448: d301 bcc.n 1000344e +1000344a: 880b ldrh r3, [r1, #0] +1000344c: 8003 strh r3, [r0, #0] +1000344e: 4660 mov r0, ip +10003450: 4770 bx lr +10003452: bf00 nop +10003454: 2a08 cmp r2, #8 +10003456: d313 bcc.n 10003480 +10003458: 078b lsls r3, r1, #30 +1000345a: d0b1 beq.n 100033c0 +1000345c: f010 0303 ands.w r3, r0, #3 +10003460: d0ae beq.n 100033c0 +10003462: f1c3 0304 rsb r3, r3, #4 +10003466: 1ad2 subs r2, r2, r3 +10003468: 07db lsls r3, r3, #31 +1000346a: bf1c itt ne +1000346c: f811 3b01 ldrbne.w r3, [r1], #1 +10003470: f800 3b01 strbne.w r3, [r0], #1 +10003474: d3a4 bcc.n 100033c0 +10003476: f831 3b02 ldrh.w r3, [r1], #2 +1000347a: f820 3b02 strh.w r3, [r0], #2 +1000347e: e79f b.n 100033c0 +10003480: 3a04 subs r2, #4 +10003482: d3d9 bcc.n 10003438 +10003484: 3a01 subs r2, #1 +10003486: f811 3b01 ldrb.w r3, [r1], #1 +1000348a: f800 3b01 strb.w r3, [r0], #1 +1000348e: d2f9 bcs.n 10003484 +10003490: 780b ldrb r3, [r1, #0] +10003492: 7003 strb r3, [r0, #0] +10003494: 784b ldrb r3, [r1, #1] +10003496: 7043 strb r3, [r0, #1] +10003498: 788b ldrb r3, [r1, #2] +1000349a: 7083 strb r3, [r0, #2] +1000349c: 4660 mov r0, ip +1000349e: 4770 bx lr + +100034a0 : +100034a0: f020 0103 bic.w r1, r0, #3 +100034a4: f010 0003 ands.w r0, r0, #3 +100034a8: f1c0 0000 rsb r0, r0, #0 +100034ac: f851 3b04 ldr.w r3, [r1], #4 +100034b0: f100 0c04 add.w ip, r0, #4 +100034b4: ea4f 0ccc mov.w ip, ip, lsl #3 +100034b8: f06f 0200 mvn.w r2, #0 +100034bc: bf1c itt ne +100034be: fa22 f20c lsrne.w r2, r2, ip +100034c2: 4313 orrne r3, r2 +100034c4: f04f 0c01 mov.w ip, #1 +100034c8: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +100034cc: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +100034d0: eba3 020c sub.w r2, r3, ip +100034d4: ea22 0203 bic.w r2, r2, r3 +100034d8: ea12 12cc ands.w r2, r2, ip, lsl #7 +100034dc: bf04 itt eq +100034de: f851 3b04 ldreq.w r3, [r1], #4 +100034e2: 3004 addeq r0, #4 +100034e4: d0f4 beq.n 100034d0 +100034e6: f1c2 0100 rsb r1, r2, #0 +100034ea: ea02 0201 and.w r2, r2, r1 +100034ee: fab2 f282 clz r2, r2 +100034f2: f1c2 021f rsb r2, r2, #31 +100034f6: eb00 00d2 add.w r0, r0, r2, lsr #3 +100034fa: 4770 bx lr + +100034fc <_fini>: +100034fc: b5f8 push {r3, r4, r5, r6, r7, lr} +100034fe: bf00 nop + +10003500 <____aeabi_uldivmod_veneer>: +10003500: f85f f000 ldr.w pc, [pc] @ 10003504 <____aeabi_uldivmod_veneer+0x4> +10003504: 20000221 .word 0x20000221 + +10003508 <__mutex_exit_veneer>: +10003508: f85f f000 ldr.w pc, [pc] @ 1000350c <__mutex_exit_veneer+0x4> +1000350c: 200001e5 .word 0x200001e5 + +10003510 <__mutex_try_enter_block_until_veneer>: +10003510: f85f f000 ldr.w pc, [pc] @ 10003514 <__mutex_try_enter_block_until_veneer+0x4> +10003514: 2000017d .word 0x2000017d + +10003518 <__pre_init_runtime_init_bootrom_reset>: +10003518: 10001289 .... + +1000351c <__pre_init_runtime_init_early_resets>: +1000351c: 100011fd .... + +10003520 <__pre_init_runtime_init_usb_power_down>: +10003520: 10001231 1... + +10003524 <__pre_init_runtime_init_clocks>: +10003524: 1000131d .... + +10003528 <__pre_init_runtime_init_post_clock_resets>: +10003528: 10001269 i... + +1000352c <__pre_init_runtime_init_boot_locks_reset>: +1000352c: 10001181 .... + +10003530 <__pre_init_runtime_init_spin_locks_reset>: +10003530: 100012b1 .... + +10003534 <__pre_init_runtime_init_bootrom_locking_enable>: +10003534: 1000116d m... + +10003538 <__pre_init_runtime_init_mutex>: +10003538: 10000799 .... + +1000353c <__pre_init_runtime_init_install_ram_vector_table>: +1000353c: 100012b5 .... + +10003540 <__pre_init_runtime_init_default_alarm_pool>: +10003540: 10000b11 .... + +10003544 <__pre_init_first_per_core_initializer>: +10003544: 100011cd .... + +10003548 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003548: 1000129d .... + +1000354c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000354c: 1000124d M... + +10003550 <__pre_init_spinlock_set_extexclall>: +10003550: 100003e9 .... + +10003554 <__pre_init_runtime_init_per_core_irq_priorities>: +10003554: 10000411 .... + +10003558 <__frame_dummy_init_array_entry>: +10003558: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> 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Binary files /dev/null and b/WEEK06/0x0014_static-variables/build/0x0014_static-variables.uf2 differ diff --git a/WEEK06/0x0014_static-variables/build/pico_flash_region.ld b/WEEK06/0x0014_static-variables/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK06/0x0014_static-variables/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK06/0x0014_static-variables/pico_sdk_import.cmake b/WEEK06/0x0014_static-variables/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK06/0x0014_static-variables/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK06/WEEK06-BN.md b/WEEK06/WEEK06-BN.md new file mode 100644 index 0000000..2b5742b --- /dev/null +++ b/WEEK06/WEEK06-BN.md @@ -0,0 +1,1405 @@ +# Week 6-BN: Binary Ninja Personal — Read, Hack, and Patch a Static Variable and a GPIO Input (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into Binary Ninja at `0x10000000` +- Read how a **static local** keeps a fixed RAM address while a **regular local** is inlined to a constant +- **Break at `main`** on live silicon, even though `main` moves between programs +- **Hack a running target live** by editing a register in Binary Ninja's Registers widget +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map +- **Patch** the value byte, invert the button/LED logic, and (optionally) rename the printed label +- **Export** the patched image, convert it to UF2, and flash it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in Binary Ninja, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 6 lesson, and the Week 6 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helper `demo_static_variable` (and the SDK's `gpio_set_dir` / `gpio_get` / `gpio_put` / `gpio_pull_up` helpers) into `main`, and it folds the regular local `regular_fav_num` down to a bare `movs r1, #42` constant. If you build `Debug`, the SDK function addresses move and the helper stays a separate call, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the output change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Prints | Also does | The hacks | +| ------- | ------ | --------- | --------- | +| `0x0014_static-variables` | `regular_fav_num: 42`, then `static_fav_num:` incrementing | reads button GPIO 15, drives LED GPIO 16 | change `42` to `43`, invert the button/LED logic, (optional) rename the label | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **`static_fav_num` is the star of this week.** `regular_fav_num` is an automatic (stack) variable that the compiler bakes into a constant; `static_fav_num` is a function-local `static` that the linker parks at a **fixed RAM address** (`0x200005a8`) in `.data`. That fixed address is why it persists across loop iterations, and why you can read and patch it like a global. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +file "$(which telnet)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**`telnet` is special — and optional.** The GDB MI workflow does not need it; it is only used by the command-port fallback. macOS no longer ships `telnet`, and the Homebrew build is often the Intel one, so `telnet 127.0.0.1 4444` fails with `bad CPU type in executable`. Your `brew` command itself may also be the Intel one: if `brew install telnet` fails with `.../portable-ruby/.../ruby: Bad CPU type in executable`, you are running the Intel Homebrew. Call the Apple Silicon Homebrew explicitly: + +```bash +/opt/homebrew/bin/brew install telnet +``` + +If you would rather not install anything, macOS ships an arm64 `nc`, which can connect to the same OpenOCD port: + +```bash +nc 127.0.0.1 4444 +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x0014_static-variables/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x0014_static-variables/build/0x0014_static-variables.elf` and `.bin` — the `.bin` is **15516** bytes (`0x3c9c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0014_static-variables.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0014_static-variables.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (`demo_static_variable` inlined) | + +**The GPIO functions `main` calls (or that are inlined into it):** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000029c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (UART pins) | +| `0x100002d8` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | +| `0x10000300` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000e60` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10000ed0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10002dbc` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002dc4` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10002df0` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10002f00` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10002fec` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003014` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100030e0` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100031a4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x10003360` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100034a0` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` and `uart_init` paths reach:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10002d60` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x1000237c` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10001760` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x100016c4` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x10001934` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x10000e74` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100010a4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +Two things in this project have **no symbol of their own**, because the compiler inlined them into `main`: + +- `demo_static_variable` — the `static` helper in our own source is inlined, so there is no `demo_static_variable` address to rename. You see its body directly inside `main`. +- `init_gpio`, `gpio_set_dir`, `gpio_get`, `gpio_put`, and `gpio_pull_up` — these are `static inline` in the SDK headers, so they compile to the `mcrr`/SIO writes and the `ldr`/`ubfx` reads you see in `main` rather than to calls. `gpio_pull_up(15)` becomes the direct call to `gpio_set_pulls` at `0x1000024e`. + +> **`static_fav_num` is a `t` symbol, not a function.** `arm-none-eabi-nm -n` lists `200005a8 t static_fav_num.0`. That lowercase `t` is a **local data** symbol: the linker named the function-local static `static_fav_num.0` and parked it at RAM address `0x200005a8`. There is no pool entry for `regular_fav_num` because it is an automatic (stack) variable — and here the compiler never gave it a stack slot at all, folding it into a constant. + +### Step 5: Flash and confirm the output + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x0014_static-variables/build/0x0014_static-variables.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x0014_static-variables\build\0x0014_static-variables.bin +``` + +**Or flash from the Binary Ninja console** (the console reads the repo root from the marker file, so it works with no database open): + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0014_static-variables", "build", "0x0014_static-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0014_static-variables", "build", "0x0014_static-variables.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 15516 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +regular_fav_num: 42 +static_fav_num: 42 +regular_fav_num: 42 +static_fav_num: 43 +regular_fav_num: 42 +static_fav_num: 44 +... +``` + +`regular_fav_num` stays at `42` every pass (it is recreated as `42` each loop), while `static_fav_num` keeps climbing (it persists at `0x200005a8`). Wire a push button from GPIO 15 to GND and an LED from GPIO 16 (through a resistor) to GND. With the stock image, the LED is **off** when the button is released and **on** when you press it — the pull-up holds GPIO 15 high when released, and the code inverts that with `eor.w r3, r3, #1`. We will flip that behavior in Step 18b. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 6: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x0014_static-variables/build/0x0014_static-variables.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> import os +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +> load(os.path.join(root, "0x0014_static-variables", "build", "0x0014_static-variables.bin"), +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 7: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x0014_static-variables.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +The two files have different roles: + +| File | Role | +| ---- | ---- | +| `0x0014_static-variables.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x0014_static-variables.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. If a database gets messy, delete the `.bndb` and re-import the `.bin` from Step 6 — the firmware is never at risk. You export the patched image out of this view later, in Step 19. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 12. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at `main` and Hack Live + +### Step 9: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 10. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. This is the whole reason the lab works cleanly — you never have to drive a reset from outside the GUI. +> +> Use the address you actually want to stop at: +> +> | What you want to stop at | Address | Command | +> | --- | --- | --- | +> | `main` (once per reset) | `0x10000234` | `BP_ADDR=0x10000234 ./debug-server.sh` | +> | The **loop** — the first `printf` call, hit every iteration | `0x10000268` | `BP_ADDR=0x10000268 ./debug-server.sh` | +> +> ```bash +> BP_ADDR=0x10000234 ./debug-server.sh # park at main +> BP_ADDR=0x10000268 ./debug-server.sh # park in the loop instead +> ``` +> +> ```powershell +> $env:BP_ADDR="0x10000234"; .\debug-server.ps1 # park at main +> $env:BP_ADDR="0x10000268"; .\debug-server.ps1 # park in the loop +> ``` +> +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 12) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 10: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 9 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length and handles step-over itself. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. Stops are reported as `Breakpoint` (not `SingleStep`). +> +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 9), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. +> +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. +> +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. It is not the adapter for this lab. The dropdown is a combo box, so an accidental arrow-key press can land on it — always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +> **Watch for an off-screen error dialog.** When a connection fails, Binary Ninja pops a `Binary Ninja critical alert` window that can be positioned mostly outside the main window, which makes it look like nothing happened. If the connect seems to do nothing, check your other display. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 11: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186: 4914 ldr r1, [pc, #80] ; @ 0x100001d8 +10000188: 4788 blx r1 ; runtime_init +1000018a: 4914 ldr r1, [pc, #80] ; @ 0x100001dc +1000018c: 4788 blx r1 ; main <-- the fixed anchor +1000018e: 4914 ldr r1, [pc, #80] ; @ 0x100001e0 +10000190: 4788 blx r1 ; exit +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 0x10000192 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in every project, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234`. + +### Step 12: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +> **Why older drafts used the command port.** Binary Ninja's **GDB RSP** adapter is its own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 FPB comparators need 2 bytes, so OpenOCD rejected it with `only breakpoints of two bytes length supported`. The old workaround was to arm breakpoints by hand over telnet. **The GDB MI adapter does not have this problem** — it drives real `arm-none-eabi-gdb`, which sends the right length. So everything below is done in the GUI. The command port still exists as a fallback (see the end of this step), but you do not need it. + +#### Where you can stop + +| You want to stop at | Address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 9), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **The regular `printf` call** | `0x10000268` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | +| **The static `printf` call** | `0x10000270` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | + +#### Set the loop breakpoint in the GUI + +1. Press `G`, type the loop address (`0x10000268`), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the loop address and reports it as a **Breakpoint** — verified: `Stopped (Breakpoint) at 0x10000268`. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 10). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +#### Stepping + +With the target halted at the breakpoint, **Step Into** (`F7`) and **Step Over** (`F8`) run through real GDB and move the PC. Verified: `0x10000268 -> 0x100031a4 -> 0x100031a6 -> ...`. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, so **Step Over** at the `printf` call behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 13 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +> **If you ever need the command port.** It is still there — `nc 127.0.0.1 4444`, and `bp 2 hw` still arms a breakpoint, `rbp ` / `rbp all` still remove them. It is the fallback if you switch back to the **GDB RSP** adapter, whose 1-byte breakpoints the GUI cannot set. With GDB MI you do not need it for this lab. + +### Step 13: HACK IT LIVE — change the printed value + +`main` loads the constant `0x2a` (42) into `r1` and calls `printf` for the regular variable on every iteration. We break on that call and change it live: + +1. Press `G`, go to `0x10000268` (the first `bl __wrap_printf`). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the program counter at `0x10000268` and `r1 = 0x2a`. +4. Open the **Registers** widget (bug icon -> **Registers**). +5. Find `r1`. Its value is `0x2a` (42), loaded by the `movs r1, #42` at `0x10000264`. +6. **Set `r1` to `0x2b` (43).** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r1", 0x2b) + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r1` in the **Registers** widget, press `E` (edit), type `2b`, and press Enter. The widget may not repaint the value, but the write reaches the target — you confirm it by the printed output in the next steps. +7. **Move the breakpoint past the call.** You want `printf` to run once and then stop, so move the breakpoint from `0x10000268` to the instruction *after* the call, `0x1000026c` (the `ldrb r1, [r4]` that begins the static-variable half of the loop): remove the breakpoint at `0x10000268` and set a hardware breakpoint at `0x1000026c`. Two reasons not to just click **Step Over** here: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `__wrap_printf` on this raw `.bin` because the image carries no symbol for the call. Moving the breakpoint to the return site is deterministic. +8. Click **Resume** in Binary Ninja. The core executes `bl __wrap_printf` with `r1 = 0x2b`, so this iteration prints `regular_fav_num: 43`, then stops at `0x1000026c`. +9. Look at your serial monitor — the `screen` session on the Pico's USB serial port — and at the **Target** tab in Binary Ninja: + + ``` + regular_fav_num: 43 + ``` + +You changed a running program's output without touching the binary. + +### Step 13b: HACK THE STRING LIVE — change `regular_fav_num:` to `patched_fav_num:` (optional) + +The text `"regular_fav_num: %d\r\n"` lives in flash (`.rodata`) at `0x10003560`, and flash is **read-only at runtime** — a debugger write there does not stick. So instead of overwriting the text in place, redirect the pointer: at the `printf` call, `r0` holds the string address, so point `r0` at a replacement string you place in RAM. + +1. Arm the breakpoint at the `printf` call and hit it, exactly as in Step 13 steps 1-3. At the stop, `r0 = 0x10003560` and `r1 = 0x2a`. +2. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console** (`Plugins -> Python Console`) — no command port needed: + ```python + dbg.write_memory(0x20080000, b"patched_fav_num: %d\r\n\x00") + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. That writes `patched_fav_num: %d\r\n\0`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. If you want the value hack too, set `r1` to `0x2b` as in Step 13. Then move the breakpoint past the call in the GUI (remove it at `0x10000268`, set one at `0x1000026c`) and click **Resume**. The core runs `printf` with `r0` pointing at your RAM string and `r1 = 0x2b`, so this iteration prints: + ``` + patched_fav_num: 43 + ``` + then stops at `0x1000026c`. + +Like the value hack, this is **one iteration only**: the loop reloads `r0` (and `r1`) from flash on every pass, so the next line is `regular_fav_num: 42` again. The permanent version is the static patch in Step 18c. + +### Step 14: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x10000264`, which reloads `movs r1, #42`, so the next line is `regular_fav_num: 42`. The live edit changed one iteration only. There is no stack variable in memory to change; the value is baked into the instruction. To make `regular_fav_num: 43` permanent we must patch the instruction. That is the static pass. + +Press **Pause** to stop the output flood. + +### Step 15: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003014()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `gpio_init` + +1. `G` -> `0x10000300`. +2. `Y` -> `void gpio_init(uint gpio)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x100002d8`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(15)` in our source compiles to: the SDK's `static inline` `gpio_pull_up` disappears, and `main` calls `gpio_set_pulls(15, true, false)` directly at `0x1000024e`. + +#### Worked example: `gpio_set_function` + +1. `G` -> `0x1000029c`. +2. `Y` -> `void gpio_set_function(uint gpio, gpio_function_t fn)`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100031a4`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `gpio_init`, `gpio_set_pulls`, and `printf`, so we follow that chain down: `stdio_init_all` pulls in the stdio/UART setup, `printf` lands in the SDK's `__wrap_printf`, and `uart_init` reaches `clock_get_hz` and `busy_wait_us`. + +The call chain for this project: + +``` +main +├── stdio_init_all +│ └── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── gpio_init +├── gpio_set_pulls (gpio_pull_up inlined) +├── __wrap_printf ── __wrap_vprintf +│ ├── vfctprintf ── _vsnprintf +│ │ └── _ntoa_format / _out_rev / _out_char +│ ├── stdio_out_chars_crlf +│ └── time_us_64 +└── gpio_set_dir / gpio_get / gpio_put (inlined; no calls) +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x1000029c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x100002d8` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10000300` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000e60` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10000ed0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10002dbc` | `exit` | `void exit(int)` | +| `0x10002dc4` | `runtime_init` | `void runtime_init(void)` | +| `0x10002df0` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002f00` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10002fec` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003014` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100030e0` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100031a4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003360` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100034a0` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` and `uart_init` paths reach:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10002d60` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x1000237c` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10001760` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x100016c4` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x10001934` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x10000e74` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100010a4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`__wrap_printf` is the real symbol.** `printf` in our source compiles to the SDK's `__wrap_printf` (which forwards to `__wrap_vprintf`). Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. +> +> **`stdio_init_all` returns `bool`, not `void`** — `_Bool stdio_init_all(void)` in the ELF. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x1000029c: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x100002d8: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10000300: ("gpio_init", "void gpio_init(uint)"), +> 0x10000e60: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10000ed0: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10002dbc: ("exit", "void exit(int)"), +> 0x10002dc4: ("runtime_init", "void runtime_init(void)"), +> 0x10002df0: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10002f00: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x10002fec: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003014: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100030e0: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x100031a4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003360: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x100034a0: ("strlen", "size_t strlen(const char*)"), +> 0x10002d60: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x1000237c: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x10001760: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x100016c4: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x10001934: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> 0x10000e74: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100010a4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `gpio_function_t`, `uart_inst_t`, plus `uint`, `va_list`, `out_fct_type`, and `clock_handle_t`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + gpio_init(0xf); + gpio_set_dir(0xf, GPIO_IN); // inlined: mcrr 0, 4, r0, r3, cr4 + gpio_set_pulls(0xf, true, false); // gpio_pull_up(15) + gpio_init(0x10); + gpio_set_dir(0x10, GPIO_OUT); // inlined + do + { + __wrap_printf("regular_fav_num: %d\r\n", 0x2a); + __wrap_printf("static_fav_num: %d\r\n", *(uint8_t*)0x200005a8); + *(uint8_t*)0x200005a8 = *(uint8_t*)0x200005a8 + 1; // static_fav_num++ + gpio_put(0x10, gpio_get(0xf) ^ 1); // inlined SIO read/write + } while (true); +} +``` + +The `0x2a` is the value we edited live; `0x200005a8` is the fixed RAM address of `static_fav_num`. The `gpio_get(0xf) ^ 1` is the `eor.w r3, r3, #1` we will patch in Step 18b. Now make the hacks permanent. + +### Step 18: Patch 1 — change `regular_fav_num` from 42 to 43 + +Go to `0x10000264`: + +```asm +10000264: 212a movs r1, #42 ; 0x2a +``` + +The halfword is `0x212a`, stored little-endian as `2a 21`. The immediate is the low byte, so the byte at the instruction's own address is `0x2a`. Change it to `0x2b` (43). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10000264` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `regular_fav_num: 43` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x10000264` and change the byte `2A` to `2B`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x10000264, b"\x2b") +print(hex(bv.read(0x10000264, 1)[0])) # -> 0x2b +``` + +After reanalysis the instruction reads `movs r1, #43`. + +### Step 18b: Patch 2 — invert the button/LED logic + +The stock code inverts the raw button bit with `eor.w r3, r3, #1` at `0x10000286`. Its four bytes are `83 f0 01 03`; the immediate `#1` is the **third** byte, at `0x10000288`. Change `01` to `00` so the XOR becomes `#0` (a no-op) and the LED follows the raw pin state instead: + +```asm +10000286: f083 0301 eor.w r3, r3, #1 ; immediate byte at 0x10000288 +``` + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10000288` | `01` | `00` | `eor.w r3, r3, #1` -> `#0`, inverts the LED behavior | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000288` and change the byte `01` to `00`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000288, b"\x00") +print(bv.read(0x10000286, 4).hex()) # -> 83f00003 +``` + +Now the logic is permanently changed: + +- Button released (GPIO 15 reads `1`): `1 XOR 0 = 1` -> LED **ON** +- Button pressed (GPIO 15 reads `0`): `0 XOR 0 = 0` -> LED **OFF** + +This is the **opposite** of the original behavior. The `gpio_get` and `gpio_put` are inlined, so the only byte that controls the inversion is this immediate. + +### Step 18c: Patch 3 — rename the printed label (optional) + +The format string `"regular_fav_num: %d\r\n"` starts at `0x10003560`. Its first 16 bytes are `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` (`regular_fav_num:`). Change them to `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a` (`patched_fav_num:`), leaving the ` %d\r\n` tail untouched, so the line prints `patched_fav_num: 43`. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10003560` | `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` | `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a` | `regular_fav_num:` -> `patched_fav_num:` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10003560` and change the sixteen bytes `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` to `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10003560, b"patched_fav_num:") +print(bv.read(0x10003560, 22)) # -> b'patched_fav_num: %d\r\n\x00' +``` + +Keep the replacement exactly sixteen bytes — the same length as `regular_fav_num:`. If you use a shorter string you must pad it, or `%d` shifts and `printf` reads the wrong argument. A longer string would overwrite the ` %d` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "0x0014_static-variables-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15516 /.../build/0x0014_static-variables-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3c9c` = 15516). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so `open("0x0014_static-variables-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0014_static-variables-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0014_static-variables-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0014_static-variables", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0014_static-variables-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +### Step 21: Flash and verify + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Open the serial monitor: + +``` +patched_fav_num: 43 +static_fav_num: 42 +patched_fav_num: 43 +static_fav_num: 43 +patched_fav_num: 43 +static_fav_num: 44 +... +``` + +and the **LED is on by default** (button released) and turns **off** when you press the button — the opposite of the stock image. + +**The regular value is now 43, the label reads `patched_fav_num:`, and the button/LED logic is inverted — with eighteen bytes changed and no source code.** (`static_fav_num` keeps incrementing from `42`, unchanged: we left the static variable itself alone so you can watch it persist.) + +> **Faster: flash over the Debug Probe (no BOOTSEL).** The repo's `flash.sh` writes the raw `.bin` straight into XIP flash over SWD (`program 0x10000000 verify reset exit`), so you never touch BOOTSEL or a UF2. Run it from a terminal (`./flash.sh `), or from the Binary Ninja console **without freezing it** — use `subprocess.Popen`, which returns immediately, and send OpenOCD's output to a log file. (`subprocess.run` blocks the console until the flash finishes; do not use it here.) +> +> ```python +> import os, subprocess +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +> bin_path = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "0x0014_static-variables-h.bin") +> log = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> The `pkill` frees the probe first; on Windows use `subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"])`. +> +> The console is free the moment this returns. Check it with `print(p.poll())` (`None` = still running, `0` = done) or read `flash.log` — success ends with `** Verified OK **`. +> +> The same non-blocking form without the script: +> +> ```python +> import os, subprocess +> ocd = os.path.expanduser("~/.pico-sdk/openocd/0.12.0+dev") +> bin_path = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "0x0014_static-variables-h.bin") +> log = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([f"{ocd}/openocd", "-s", f"{ocd}/scripts", +> "-f", "interface/cmsis-dap.cfg", "-f", "target/rp2350.cfg", +> "-c", "adapter speed 5000", +> "-c", f"program {bin_path} 0x10000000 verify reset exit"], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> **The Debug Probe is single-owner.** If Binary Ninja is still attached (the `debug-server.sh` OpenOCD is running), the flash cannot grab the probe. Detach in Binary Ninja and stop that OpenOCD first: +> +> ```bash +> # macOS / Linux +> pkill -TERM -f openocd +> ``` +> ```powershell +> # Windows +> Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +> ``` +> +> Success looks like `Programming Finished` -> `Verified OK` -> `Resetting Target`. On Windows use `flash.ps1` (`.\flash.ps1 -Bin `) the same way. + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r1", 0x2b)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write a RAM string live | `dbg.write_memory(0x20080000, b"patched_fav_num: %d\r\n\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 12). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Start the server parked in the loop | macOS/Linux: `BP_ADDR=0x10000268 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000268"; .\debug-server.ps1` | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10000264` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `regular_fav_num: 43` | +| `0x0014` | `0x10000288` | `01` | `00` | `eor.w r3, r3, #1` -> `#0`, inverts the button/LED logic | +| `0x0014` | `0x10003560` | `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` | `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a` | string prints `patched_fav_num:` instead of `regular_fav_num:` | + +### The static-variable memory map + +| Item | Address | Notes | +| ---- | ------- | ----- | +| `static_fav_num` | `0x200005a8` | RAM `.data`, fixed for the life of the program; initial value `42` copied from flash at boot | +| Literal-pool word 1 | `0x10000290` | `0x200005a8` — the RAM address `r4` holds | +| Literal-pool word 2 | `0x10000294` | `0x10003560` — pointer to `"regular_fav_num: %d\r\n"` | +| Literal-pool word 3 | `0x10000298` | `0x10003578` — pointer to `"static_fav_num: %d\r\n"` | +| `regular_fav_num` | (no address) | inlined to `movs r1, #42`; never given a stack slot | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project size | `15516` bytes (`0x3c9c`) | +| Fixed `main` anchor | `0x1000018c` (reset handler middle `blx`) | +| `main` | `0x10000234` | +| `printf` call / return, `regular_fav_num` | `0x10000268` / `0x1000026c` | +| `printf` call, `static_fav_num` | `0x10000270` | +| `static_fav_num` RAM address | `0x200005a8` | +| `regular_fav_num` format string | `0x10003560` | +| `static_fav_num` format string | `0x10003578` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints (see the next entry). +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 10). The 13.3.rel1 build did **not** connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +**Use GDB MI**, with the 14.2.rel1 path above. If it still fails, fall back to plain `arm-none-eabi-gdb` against the same server — the addresses and register values are identical to the GUI steps. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### The GUI refuses to set a breakpoint (GDB RSP adapter only) + +If you are on the **GDB RSP** adapter, the GUI cannot set breakpoints on this target. That adapter is Binary Ninja's own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 comparators need 2 bytes, so OpenOCD answers `only breakpoints of two bytes length supported`. It affects every address, both `Toggle Breakpoint` and `Add Hardware Breakpoint`, and the dialog's **Size** field is disabled. `gdb_breakpoint_override` makes no difference. + +**Fix: use the GDB MI adapter** (Step 10). It drives real GDB, which sends the correct length, so GUI breakpoints just work. If you must stay on GDB RSP, arm breakpoints from the command port after connecting (`bp 2 hw`) — but the lab uses GDB MI and does not need that. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. This is a Binary Ninja bug. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +Never have a breakpoint in the binary view before the GDB MI connection. If it hangs, quit Binary Ninja, restart the server with `BP_ADDR`, and connect again before adding any breakpoints. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping, because the RP2350 config's `-rtos hwthread` makes the current thread id 1 while Binary Ninja sends thread id 0. Fix: `rp2350.dap.core0 configure -rtos none` (the launcher scripts already pass this). **GDB MI does not hit this.** + +To tell them apart, turn on OpenOCD logging (`log_output /tmp/ocd.log`, then `debug_level 3` on the command port) and look for `fake step` versus `Duplicate Breakpoint`. + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps `demo_static_variable` separate, so `main` is not at `0x10000234`. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. With the **GDB MI** adapter, `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — that is a software breakpoint and cannot be written to read-only flash, so it never installs. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Verify it is armed:** `mdw 0xE0002000 8`. You should see your address with the low bit set (`0x10000234` -> `0x10000235`). All zeros means nothing is armed — re-read this first, because it distinguishes "not armed" from "armed but never reached". +- **Is the core running?** `poll` on the command port should not report a halt. If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup (Step 9) rather than `reset run` while attached. Loop addresses such as `0x10000268` fire on the next pass with no reset — arm them and click **Resume** in Binary Ninja. +- **With GDB MI the stop is reported as `Breakpoint`** and appears in the **Breakpoints** widget, because GDB really did set it. + +### I edit `r1` (or another register) and it reverts + +`main` reloads the value at the top of every loop iteration — `movs r1, #42` at `0x10000264` runs right before the `printf` at `0x10000268`. So `r1` is only `0x2b` for the instant between your edit and the next pass; then it is `0x2a` again. The edit sticks only if the core is **genuinely stopped** at the breakpoint and stays stopped. + +If it keeps reverting, the core is running, which almost always means the breakpoint is not installed — usually because it is a **software** breakpoint (`F2`) that cannot be written to read-only flash. Use `Debugger -> Add Hardware Breakpoint...` (hardware execute). + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target, and there is no "refresh registers" command. So a value changed outside Binary Ninja will not appear until the next stop. + +### The static variable shows a wrong value in GDB / Binary Ninja + +`static_fav_num` is a function-local `static`, so it does not appear in the global symbol table as `static_fav_num`; `arm-none-eabi-nm` names it `static_fav_num.0`. A 4-byte read at `0x200005a8` returns `0x0000122a`, whose low byte `0x2a` (42) is the variable — the upper bytes belong to whatever is in adjacent RAM. Read **one byte** (`x/1ub 0x200005a8`) to see `42`, and never add a `*` (that would treat the value as a pointer). In Binary Ninja, define a `uint8_t` at `0x200005a8` if you want the decompiler to show the byte cleanly. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first: clear canonical/echo flags, set `CLOCAL|CREAD`, and `B115200` on input and output. `screen /dev/cu.usbmodem* 115200` does all of this for you; a script must call `tcsetattr` itself. Once set, the capture reads clean `regular_fav_num: 42` lines. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +This is the most common failure, and it has one main cause: **driving the core from the OpenOCD command port while Binary Ninja is connected.** + +- If you send `reset run` from the port while attached, the core resets, runs, and halts at your breakpoint — but Binary Ninja never receives the stop event. Its sidebar keeps showing the *previous* location, so **Step** and **Resume** act on a stale PC and appear to do nothing. +- If the OpenOCD process dies (or you restart it) while attached, Binary Ninja keeps believing it is connected: the sidebar stays, but the menu shows **Pause** enabled and **Resume**/**Step** disabled because Binary Ninja last saw the target *running*. + +Recovery: **Detach, then reconnect.** If Detach does nothing (the connection is already dead), restart Binary Ninja — its menu still shows a session that no longer exists. + +Prevention: + +- Stop at `main` with `BP_ADDR` on a fresh server start, not with `reset run` while attached. +- For loop addresses, set the breakpoint in the GUI and click **Resume**. Let Binary Ninja be the thing that starts the core. +- If you must reset, **Detach first**, `reset run`, then reconnect. +- Never leave a breakpoint on the PC you are about to step or resume from. + +### The target "blows past" `main` and stops at `0x100032cc` instead + +`0x100032cc` is inside `stdio_uart_out_flush`: + +```asm +100032c8: 4b02 ldr r3, [pc, #8] ; @ 0x100032d4 +100032ca: 681a ldr r2, [r3] +100032cc: 6993 ldr r3, [r2, #24] ; the core sits here while the UART drains +100032ce: 071b lsls r3, r3, #28 +100032d0: d4fc bmi.n 0x100032cc +100032d2: 4770 bx lr +100032d4: 20000850 .word 0x20000850 +``` + +That is the UART transmit-FIFO drain loop inside `printf`, so the core is running `main`'s loop and simply spends nearly all its time there. The breakpoint at `main` did not fire because `main`'s entry runs exactly **once per reset**. If you arm the breakpoint after the reset, or set it while the target is already running and just resume, the core is already past `main` and will never re-execute it. Either arm the breakpoint **before** resetting, or break inside the loop at `0x10000268`, which fires every iteration. + +**`0x100032cc` is not a function.** It is one instruction inside `stdio_uart_out_flush`, which starts at `0x100032c8`. If Binary Ninja has created a function at `0x100032cc` (for example because the debugger stopped at that PC), the decompiler shows garbage. Delete that bogus function (right-click it -> `Delete Function`, or put the cursor on it and press `U` to undefine) and reanalyze. The real function is `stdio_uart_out_flush` at `0x100032c8`. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### `Connect to Remote Process` is greyed out and Pause does nothing + +Binary Ninja is in a stale session, usually because the debug server restarted while attached. Quit and reopen Binary Ninja (or the `.bndb`) and connect again. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +### The LED does not change after patching + +You patched the wrong byte. The inversion immediate is the **third** byte of the 4-byte `eor.w` instruction: the instruction is at `0x10000286`, so the byte to change is `0x10000288`. Confirm it now reads `00`, not `01`. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27 (see Troubleshooting), you can still do the live hack with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 9), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x10000268 +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x10000268` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. If you reset first, the core runs `main` and you will not catch it. + +GDB stops at the `printf` call. Confirm the value, change it, and let it run: + +``` +info registers pc r1 # pc = 0x10000268, r1 = 0x2a +set $r1 = 0x2b +stepi +continue +``` + +The serial monitor prints `regular_fav_num: 43` for the iteration you changed — the same temporary live hack as editing `r1` in the Binary Ninja Registers widget. When you are done, press `Ctrl-C`, then `detach` and `quit`. + +**If you specifically want to stop at `main` (`0x10000234`),** remember its entry runs only once per reset, so the breakpoint must be armed *before* the reset: + +``` +monitor reset halt +hbreak *0x10000234 +continue +``` + +If you instead set it while the target is running and just `continue`, you will "blow past" `main` and catch the core inside `printf` — in this build at `0x100032cc`, the `stdio_uart_out_flush` UART-drain loop. + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too; the old **GDB RSP** adapter was the one that sent a 1-byte length and could not set breakpoints here. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; zeroed by startup code | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **Automatic variable** | A local variable created and destroyed with its block; lives on the stack (or is optimized away) | +| **`eor` / XOR** | Exclusive OR — flips bits where the operands differ | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +| **Hardware breakpoint** | A breakpoint serviced by the CPU comparators, required for read-only flash | +| **Inlining** | The optimizer replacing a function call with the function body; why `demo_static_variable` disappears | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **Pull-up / pull-down** | A resistor that holds an input pin at a defined level when nothing drives it | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Static variable** | A variable with static storage duration; persists for the whole program and keeps a fixed address | +| **Ternary operator** | `condition ? value_if_true : value_if_false` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **`ubfx`** | Unsigned Bit Field Extract — pulls a bit field out of a register | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, read `r1` at the `printf` call, resolve the names from the ELF, then patch the bytes — the constant `42`, the inversion immediate, and (optionally) the label — and flash. diff --git a/WEEK06/WEEK06-BN.pdf b/WEEK06/WEEK06-BN.pdf new file mode 100644 index 0000000..85324eb Binary files /dev/null and b/WEEK06/WEEK06-BN.pdf differ diff --git a/WEEK06/WEEK06-IDA.md b/WEEK06/WEEK06-IDA.md new file mode 100644 index 0000000..14183af --- /dev/null +++ b/WEEK06/WEEK06-IDA.md @@ -0,0 +1,688 @@ +# Week 6-IDA: IDA Pro — Read, Hack, and Patch a Static Variable and a GPIO Input (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into IDA at `0x10000000` +- Read how a **static local** keeps a fixed RAM address while a **regular local** is inlined to a constant + programs +- **Resolve the functions in the IDA GUI** using the ELF symbol map +- **Patch** the value byte, invert the button/LED logic, and (optionally) rename the printed label +- **Export** the patched image, convert it to UF2, and export it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in IDA, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 6 lesson, and the Week 6 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helper `demo_static_variable` (and the SDK's `gpio_set_dir` / `gpio_get` / `gpio_put` / `gpio_pull_up` helpers) into `main`, and it folds the regular local `regular_fav_num` down to a bare `movs r1, #42` constant. If you build `Debug`, the SDK function addresses move and the helper stays a separate call, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Prints | Also does | The hacks | +| ------- | ------ | --------- | --------- | +| `0x0014_static-variables` | `regular_fav_num: 42`, then `static_fav_num:` incrementing | reads button GPIO 15, drives LED GPIO 16 | change `42` to `43`, invert the button/LED logic, (optional) rename the label | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **`static_fav_num` is the star of this week.** `regular_fav_num` is an automatic (stack) variable that the compiler bakes into a constant; `static_fav_num` is a function-local `static` that the linker parks at a **fixed RAM address** (`0x200005a8`) in `.data`. That fixed address is why it persists across loop iterations, and why you can read and patch it like a global. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +bash +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x0014_static-variables/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point IDA at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so IDA never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the IDA console**, so the whole build -> patch -> flash loop stays inside IDA. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0014_static-variables") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x0014_static-variables/build/0x0014_static-variables.elf` and `.bin` — the `.bin` is **15516** bytes (`0x3c9c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0014_static-variables.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0014_static-variables.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (`demo_static_variable` inlined) | + +**The GPIO functions `main` calls (or that are inlined into it):** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000029c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (UART pins) | +| `0x100002d8` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | +| `0x10000300` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000e60` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10000ed0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10002dbc` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002dc4` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10002df0` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10002f00` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10002fec` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003014` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100030e0` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100031a4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x10003360` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100034a0` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` and `uart_init` paths reach:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10002d60` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x1000237c` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10001760` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x100016c4` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x10001934` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x10000e74` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100010a4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +Two things in this project have **no symbol of their own**, because the compiler inlined them into `main`: + +- `demo_static_variable` — the `static` helper in our own source is inlined, so there is no `demo_static_variable` address to rename. You see its body directly inside `main`. +- `init_gpio`, `gpio_set_dir`, `gpio_get`, `gpio_put`, and `gpio_pull_up` — these are `static inline` in the SDK headers, so they compile to the `mcrr`/SIO writes and the `ldr`/`ubfx` reads you see in `main` rather than to calls. `gpio_pull_up(15)` becomes the direct call to `gpio_set_pulls` at `0x1000024e`. + +> **`static_fav_num` is a `t` symbol, not a function.** `arm-none-eabi-nm -n` lists `200005a8 t static_fav_num.0`. That lowercase `t` is a **local data** symbol: the linker named the function-local static `static_fav_num.0` and parked it at RAM address `0x200005a8`. There is no pool entry for `regular_fav_num` because it is an automatic (stack) variable — and here the compiler never gave it a stack slot at all, folding it into a constant. + +## Part 2: Load the Raw `.bin` into IDA + +Start from a fresh IDA state. If you already have a database for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into IDA + +A raw `.bin` has no headers, so IDA cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, IDA may load it with a guessed architecture, and every address in this lesson will be wrong. + +#### 1.1 Open the file +1. **File ▸ Open…** (Ctrl/Cmd+O). +2. Select the `.bin` file and click **Open**. + +IDA opens the **"Load a new file"** dialog because a raw `.bin` has no header. + +#### 1.2 Set the format and processor +In the *Load a new file* dialog: +1. **Format**: leave it as **Binary file** (IDA auto-detects a headerless image). +2. **Processor type**: click the **…** button next to the processor field. In the *Processor type* dialog: + - Family: **ARM** + - Type: **ARM Little-endian** (the 32-bit ARM module). + - Click **OK**. + +> If IDA asks **"Do you want to disassemble it as 64-bit code?"** — click **No**. +> The RP2350 is 32-bit; answering *Yes* loads AArch64 and you get `X` registers / data. (This is the single most common cause of the `DCB` wall.) + +#### 1.3 Configure the ARM architecture and Thumb mode +Still in the *Load a new file* dialog, open the processor options (the **Processor options** / **Set…** button, which opens the dialog titled **ARM architecture options**): +- **ARM architecture**: choose **ARMv8-M** (this is the Cortex-M33 / RP2350 core). +- **Thumb instructions**: select **Thumb-2** (ARMv8-M is Thumb-only, so this is the correct mode). +- Leave **automatic ARM-THUMB switch** off; we want Thumb throughout. + +#### 1.4 Set the loading address +- **Loading address**: enter **`10000000`** (hex; the RP2350 XIP flash base). + IDA rejects addresses that don't look like ROM/RAM with *"The loading address should belong to RAM or ROM"* — `0x10000000` is the correct flash window. + +Leave **Manual load** and **Create segments** at their defaults. Click **OK**. + +#### 1.5 Force Thumb, then seed the code from the vector table +A raw `.bin` has no header, so IDA's loader has **no entry point** and defaults the segment to **ARM mode** (which cannot decode Thumb). Two required steps — in this order: + +**A. Set the segment to Thumb (do this first).** +- **Edit ▸ Segments ▸ Set default segment register value…** → register **`T`** = **`1`** (or press **`Alt+G`**). IDA reanalyzes the segment as Thumb automatically. + +**B. Seed the code from the vector table.** +1. **G** → `10000000`. The first two words are the initial stack pointer and the **reset vector**. +2. **Read the 4-byte word at `0x10000004`** (do **not** assume its value — it differs per build). +3. **Clear bit 0** (the ARM **Thumb** flag) → the reset handler address. +4. **G** to that address → press **C** (**MakeCode**). IDA disassembles the reset handler and follows its `bl`s into `main`. + +Once `main` shows code, the import is correct. + +**Why IDA needs this and others don't:** IDA's generic raw-binary ARM loader treats the image as flat data and waits for you to set Thumb and mark the entry point. It's an IDA quirk, not a mistake on your part. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Static — Resolve the Functions in IDA and Patch + +### Step 16: Resolve the functions in the IDA GUI + +We now name the functions in IDA using the ELF symbol map from Step 4. IDA loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | IDA action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in IDA (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003014()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. IDA parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **IDA shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and IDA's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `gpio_init` + +1. `G` -> `0x10000300`. +2. `Y` -> `void gpio_init(uint gpio)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x100002d8`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(15)` in our source compiles to: the SDK's `static inline` `gpio_pull_up` disappears, and `main` calls `gpio_set_pulls(15, true, false)` directly at `0x1000024e`. + +#### Worked example: `gpio_set_function` + +1. `G` -> `0x1000029c`. +2. `Y` -> `void gpio_set_function(uint gpio, gpio_function_t fn)`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100031a4`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `gpio_init`, `gpio_set_pulls`, and `printf`, so we follow that chain down: `stdio_init_all` pulls in the stdio/UART setup, `printf` lands in the SDK's `__wrap_printf`, and `uart_init` reaches `clock_get_hz` and `busy_wait_us`. + +The call chain for this project: + +``` +main +├── stdio_init_all +│ └── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── gpio_init +├── gpio_set_pulls (gpio_pull_up inlined) +├── __wrap_printf ── __wrap_vprintf +│ ├── vfctprintf ── _vsnprintf +│ │ └── _ntoa_format / _out_rev / _out_char +│ ├── stdio_out_chars_crlf +│ └── time_us_64 +└── gpio_set_dir / gpio_get / gpio_put (inlined; no calls) +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x1000029c` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x100002d8` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10000300` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000e60` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10000ed0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10002dbc` | `exit` | `void exit(int)` | +| `0x10002dc4` | `runtime_init` | `void runtime_init(void)` | +| `0x10002df0` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10002f00` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10002fec` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003014` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100030e0` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100031a4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003360` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100034a0` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` and `uart_init` paths reach:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10002d60` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x1000237c` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10001760` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x100016c4` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x10001934` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x10000e74` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100010a4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | + +> **A `void` return type may not stick — here is the fix.** IDA treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type IDA thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`__wrap_printf` is the real symbol.** `printf` in our source compiles to the SDK's `__wrap_printf` (which forwards to `__wrap_vprintf`). Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. +> +> **`stdio_init_all` returns `bool`, not `void`** — `_Bool stdio_init_all(void)` in the ELF. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into IDA's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x1000029c: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x100002d8: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10000300: ("gpio_init", "void gpio_init(uint)"), +> 0x10000e60: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10000ed0: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10002dbc: ("exit", "void exit(int)"), +> 0x10002dc4: ("runtime_init", "void runtime_init(void)"), +> 0x10002df0: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10002f00: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x10002fec: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003014: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100030e0: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x100031a4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003360: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x100034a0: ("strlen", "size_t strlen(const char*)"), +> 0x10002d60: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x1000237c: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x10001760: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x100016c4: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x10001934: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> 0x10000e74: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100010a4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `gpio_function_t`, `uart_inst_t`, plus `uint`, `va_list`, `out_fct_type`, and `clock_handle_t`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + gpio_init(0xf); + gpio_set_dir(0xf, GPIO_IN); // inlined: mcrr 0, 4, r0, r3, cr4 + gpio_set_pulls(0xf, true, false); // gpio_pull_up(15) + gpio_init(0x10); + gpio_set_dir(0x10, GPIO_OUT); // inlined + do + { + __wrap_printf("regular_fav_num: %d\r\n", 0x2a); + __wrap_printf("static_fav_num: %d\r\n", *(uint8_t*)0x200005a8); + *(uint8_t*)0x200005a8 = *(uint8_t*)0x200005a8 + 1; // static_fav_num++ + gpio_put(0x10, gpio_get(0xf) ^ 1); // inlined SIO read/write + } while (true); +} +``` + +The `0x2a` is the value we edited live; `0x200005a8` is the fixed RAM address of `static_fav_num`. The `gpio_get(0xf) ^ 1` is the `eor.w r3, r3, #1` we will patch in Step 18b. Now make the hacks permanent. + +### Step 18: Patch 1 — change `regular_fav_num` from 42 to 43 + +Go to `0x10000264`: + +```asm +10000264: 212a movs r1, #42 ; 0x2a +``` + +The halfword is `0x212a`, stored little-endian as `2a 21`. The immediate is the low byte, so the byte at the instruction's own address is `0x2a`. Change it to `0x2b` (43). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10000264` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `regular_fav_num: 43` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x10000264` and change the byte `2A` to `2B`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x10000264, b"\x2b") +print(hex(bv.read(0x10000264, 1)[0])) # -> 0x2b +``` + +After reanalysis the instruction reads `movs r1, #43`. + +### Step 18b: Patch 2 — invert the button/LED logic + +The stock code inverts the raw button bit with `eor.w r3, r3, #1` at `0x10000286`. Its four bytes are `83 f0 01 03`; the immediate `#1` is the **third** byte, at `0x10000288`. Change `01` to `00` so the XOR becomes `#0` (a no-op) and the LED follows the raw pin state instead: + +```asm +10000286: f083 0301 eor.w r3, r3, #1 ; immediate byte at 0x10000288 +``` + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10000288` | `01` | `00` | `eor.w r3, r3, #1` -> `#0`, inverts the LED behavior | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000288` and change the byte `01` to `00`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000288, b"\x00") +print(bv.read(0x10000286, 4).hex()) # -> 83f00003 +``` + +Now the logic is permanently changed: + +- Button released (GPIO 15 reads `1`): `1 XOR 0 = 1` -> LED **ON** +- Button pressed (GPIO 15 reads `0`): `0 XOR 0 = 0` -> LED **OFF** + +This is the **opposite** of the original behavior. The `gpio_get` and `gpio_put` are inlined, so the only byte that controls the inversion is this immediate. + +### Step 18c: Patch 3 — rename the printed label (optional) + +The format string `"regular_fav_num: %d\r\n"` starts at `0x10003560`. Its first 16 bytes are `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` (`regular_fav_num:`). Change them to `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a` (`patched_fav_num:`), leaving the ` %d\r\n` tail untouched, so the line prints `patched_fav_num: 43`. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0014` | `0x10003560` | `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` | `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a` | `regular_fav_num:` -> `patched_fav_num:` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10003560` and change the sixteen bytes `72 65 67 75 6c 61 72 5f 66 61 76 5f 6e 75 6d 3a` to `70 61 74 63 68 65 64 5f 66 61 76 5f 6e 75 6d 3a`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10003560, b"patched_fav_num:") +print(bv.read(0x10003560, 22)) # -> b'patched_fav_num: %d\r\n\x00' +``` + +Keep the replacement exactly sixteen bytes — the same length as `regular_fav_num:`. If you use a shorter string you must pad it, or `%d` shifts and `printf` reads the wrong argument. A longer string would overwrite the ` %d` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0014_static-variables", "build"), "0x0014_static-variables-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 15516 /.../build/0x0014_static-variables-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base IDA loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3c9c` = 15516). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** IDA's Python console runs with a read-only working directory (inside the app bundle), so `open("0x0014_static-variables-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0014_static-variables-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0014_static-variables-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the IDA console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0014_static-variables", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0014_static-variables-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +## Static stopping point + +The patched image has been exported and converted to UF2. This IDA guide ends at static verification; it does not connect to, flash, or debug a live target. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; zeroed by startup code | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **Automatic variable** | A local variable created and destroyed with its block; lives on the stack (or is optimized away) | +| **`eor` / XOR** | Exclusive OR — flips bits where the operands differ | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +ly flash | +| **Inlining** | The optimizer replacing a function call with the function body; why `demo_static_variable` disappears | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **MMIO** | Memory-mapped I/O — hardware registers accessed as memory addresses | +| **Pull-up / pull-down** | A resistor that holds an input pin at a defined level when nothing drives it | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Static variable** | A variable with static storage duration; persists for the whole program and keeps a fixed address | +| **Ternary operator** | `condition ? value_if_true : value_if_false` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **`ubfx`** | Unsigned Bit Field Extract — pulls a bit field out of a register | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions. diff --git a/WEEK06/WEEK06-IDA.pdf b/WEEK06/WEEK06-IDA.pdf new file mode 100644 index 0000000..64ca2fe Binary files /dev/null and b/WEEK06/WEEK06-IDA.pdf differ diff --git a/WEEK06/WEEK06-SLIDES.pdf b/WEEK06/WEEK06-SLIDES.pdf new file mode 100644 index 0000000..ae53838 Binary files /dev/null and b/WEEK06/WEEK06-SLIDES.pdf differ diff --git a/WEEK06/WEEK06.md b/WEEK06/WEEK06.md new file mode 100644 index 0000000..b41a4e6 --- /dev/null +++ b/WEEK06/WEEK06.md @@ -0,0 +1,1300 @@ +# Week 6: Static Variables in Embedded Systems: Debugging and Hacking Static Variables w/ GPIO Input Basics + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand the difference between regular (automatic) variables and static variables +- Know where different types of variables are stored (stack vs static storage) +- Configure GPIO pins as inputs and use internal pull-up resistors +- Read button states using `gpio_get()` and control LEDs based on input +- Use GDB to examine how the compiler handles static vs automatic variables +- Identify compiler optimizations by stepping through assembly +- Hack variable values and invert GPIO input/output logic using a hex editor +- Convert patched binaries to UF2 format for flashing + +--- + +## Part 1: Understanding Static Variables + +### What is a Static Variable? + +A **static variable** is a special kind of variable that "remembers" its value between function calls or loop iterations. Unlike regular variables that get created and destroyed each time, static variables **persist** for the entire lifetime of your program. + +Think of it like this: + +- **Regular variable:** Like writing on a whiteboard that gets erased after each class +- **Static variable:** Like writing in a notebook that you keep forever + +``` ++-----------------------------------------------------------------+ +| Regular vs Static Variables | +| | +| REGULAR (automatic): | +| +------------------------------------------------------------+ | +| | Loop 1: Create -> Set to 42 -> Increment to 43 -> Destroy | +| | Loop 2: Create -> Set to 42 -> Increment to 43 -> Destroy | +| | Loop 3: Create -> Set to 42 -> Increment to 43 -> Destroy | +| | Result: Always appears as 42! | +| +------------------------------------------------------------+ | +| | +| STATIC: | +| +------------------------------------------------------------+ | +| | Loop 1: Already exists -> Read 42 -> Increment -> Store 43 | +| | Loop 2: Already exists -> Read 43 -> Increment -> Store 44 | +| | Loop 3: Already exists -> Read 44 -> Increment -> Store 45 | +| | Result: Keeps incrementing! | +| +------------------------------------------------------------+ | +| | ++-----------------------------------------------------------------+ +``` + +### The `static` Keyword + +In C, you declare a static variable by adding the `static` keyword: + +```c +uint8_t regular_fav_num = 42; // Regular - recreated each time +static uint8_t static_fav_num = 42; // Static - persists forever +``` + +### Where Do Variables Live in Memory? + +Different types of variables are stored in different memory locations: + +| Variable Type | Storage Location | Lifetime | Example | +| ----------------- | ---------------- | ------------------------- | ------------------------------------ | +| Automatic (local) | Stack | Until function/block ends | `uint8_t x = 5;` | +| Static | Static Storage | Entire program lifetime | `static uint8_t x = 5;` | +| Global | Static Storage | Entire program lifetime | `uint8_t x = 5;` (outside functions) | +| Dynamic (heap) | Heap | Until `free()` is called | `malloc(sizeof(int))` | + +### Stack vs Static Storage vs Heap + +``` ++-----------------------------------------------------------------+ +| Memory Layout | +| | +| +-------------------+ High Address (0x20082000) | +| | STACK | -> Automatic/local variables | +| | (grows down) | Created/destroyed per function | +| +-------------------+ | +| | | | +| | (free space) | | +| | | | +| +-------------------+ | +| | HEAP | -> Dynamic allocation (malloc/free) | +| | (grows up) | | +| +-------------------+ | +| | .bss section | -> Uninitialized static/global vars | +| +-------------------+ | +| | .data section | -> Initialized static/global vars | +| +-------------------+ Low Address (0x20000000) | +| | ++-----------------------------------------------------------------+ +``` + +**Key Point:** Static variables are NOT on the heap! They live in a fixed location in the `.data` section (if initialized) or `.bss` section (if uninitialized). This is different from heap memory which is dynamically allocated at runtime. + +### What Happens with Overflow? + +Since `static_fav_num` is a `uint8_t` (unsigned 8-bit), it can only hold values 0-255. What happens when it reaches 255 and we add 1? + +``` +255 + 1 = 256... but that doesn't fit in 8 bits! +Binary: 11111111 + 1 = 100000000 (9 bits) +The 9th bit is lost, so we get: 00000000 = 0 +``` + +This is called **overflow** or **wrap-around**. The value "wraps" back to 0 and starts counting again! + +--- + +## Part 2: Understanding GPIO Inputs + +### Input vs Output + +So far, we've used GPIO pins as **outputs** to control LEDs. Now we'll learn to use them as **inputs** to read button states! + +``` ++-----------------------------------------------------------------+ +| GPIO Direction | +| | +| OUTPUT (what we've done before): | +| +---------+ | +| | Pico | -------> LED | +| | GPIO 16 | (We control the LED) | +| +---------+ | +| | +| INPUT (new this week): | +| +---------+ | +| | Pico | <------- Button | +| | GPIO 15 | (We read the button state) | +| +---------+ | +| | ++-----------------------------------------------------------------+ +``` + +### The Floating Input Problem + +When a GPIO pin is set as an input but nothing is connected, it's called a **floating input**. The voltage on the pin is undefined and can randomly read as HIGH (1) or LOW (0) due to electrical noise. + +``` ++-----------------------------------------------------------------+ +| Floating Input = Random Values! | +| | +| GPIO Pin (no connection): | +| Reading 1: HIGH | +| Reading 2: LOW | +| Reading 3: HIGH | +| Reading 4: HIGH | +| Reading 5: LOW | +| (Completely unpredictable!) | +| | ++-----------------------------------------------------------------+ +``` + +### Pull-Up and Pull-Down Resistors + +To solve the floating input problem, we use **pull resistors**: + +| Resistor Type | Default State | When Button Pressed | +| ------------- | ------------- | ------------------- | +| **Pull-Up** | HIGH (1) | LOW (0) | +| **Pull-Down** | LOW (0) | HIGH (1) | + +The Pico 2 has **internal** pull resistors that you can enable with software - no external components needed! + +``` ++-----------------------------------------------------------------+ +| Pull-Up Resistor (what we're using) | +| | +| 3.3V | +| | | +| + (internal pull-up resistor) | +| | | +| +------> GPIO 15 (reads HIGH normally) | +| | | +| +-+-+ | +| |BTN| -> Button connects GPIO to GND when pressed | +| +-+-+ | +| | | +| GND | +| | +| Button NOT pressed: GPIO reads 1 (HIGH, pulled up) | +| Button PRESSED: GPIO reads 0 (LOW, active-low to GND) | +| | ++-----------------------------------------------------------------+ +``` + +### GPIO Input Functions + +| Function | Purpose | +| ---------------------------- | --------------------------------------- | +| `gpio_init(pin)` | Initialize a GPIO pin for use | +| `gpio_set_dir(pin, GPIO_IN)` | Set pin as INPUT | +| `gpio_pull_up(pin)` | Enable internal pull-up resistor | +| `gpio_pull_down(pin)` | Enable internal pull-down resistor | +| `gpio_get(pin)` | Read the current state (returns 0 or 1) | + +### The Ternary Operator + +The code uses a **ternary operator** to control the LED based on button state: + +```c +gpio_put(LED_GPIO, pressed ? 0 : 1); +``` + +This is a compact if-else statement: + +- If `pressed` is **true (1)**: output `0` (LED OFF... wait, that seems backwards!) +- If `pressed` is **false (0)**: output `1` (LED ON) + +**Why does pressed read 0 when pushed?** Because of our **active-low** button wiring with a pull-up resistor! + +- Button **released** -> Pull-up holds GPIO at 3.3V (prevents floating) -> GPIO reads `1` -> `pressed = 1` -> output `0` -> LED OFF +- Button **pressed** -> Switch connects GPIO directly to GND -> GPIO reads `0` -> `pressed = 0` -> output `1` -> LED ON + +A clearer way to write this: +```c +gpio_put(LED_GPIO, !gpio_get(BUTTON_GPIO)); +``` + +--- + +## Part 3: Understanding Compiler Optimizations + +### Why Does Code Disappear? + +When you compile code, the compiler tries to make it faster and smaller. This is called **optimization**. Sometimes the compiler removes code that it thinks has no effect! + +**Example from our code:** +```c +while (true) { + uint8_t regular_fav_num = 42; // Created + regular_fav_num++; // Incremented to 43 + // But then it's destroyed and recreated as 42 next loop! +} +``` + +The compiler sees that incrementing `regular_fav_num` has no lasting effect (because it's recreated as 42 each loop), so it may **optimize away** the increment operation entirely! + +### Function Inlining + +Sometimes the compiler **inlines** functions, meaning it replaces a function call with the function's code directly. + +**Original code:** +```c +gpio_pull_up(BUTTON_GPIO); +``` + +**What the compiler might do:** +```c +// Instead of calling gpio_pull_up, it calls the underlying function: +gpio_set_pulls(BUTTON_GPIO, true, false); +``` + +This is why when you look for `gpio_pull_up` in the binary, you might find `gpio_set_pulls` instead! + +--- + +## Part 4: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. A Raspberry Pi Pico Debug Probe +3. OpenOCD installed and configured +4. GDB (`arm-none-eabi-gdb`) installed +5. Python installed (for UF2 conversion) +6. A serial monitor (PuTTY, minicom, or screen) +7. A push button connected to GPIO 15 +8. An LED connected to GPIO 16 (or use the breadboard LED) +9. A hex editor (HxD, ImHex, or similar) +10. The sample project: `0x0014_static-variables` + +### Hardware Setup + +Connect your button like this: + +- One side of button -> GPIO 15 +- Other side of button -> GND + +The internal pull-up resistor provides the 3.3V connection, so you only need to connect to GND! + +``` ++-----------------------------------------------------------------+ +| Breadboard Wiring | +| | +| Pico 2 | +| +----------+ | +| | | | +| | GPIO 15 |--------+ | +| | | | | +| | GPIO 16 |--------+---> LED (with resistor to GND) | +| | | | | +| | GND |--------+---+ | +| | | | | | +| +----------+ +-+-+ | | +| |BTN|-+ | +| +---+ | +| | ++-----------------------------------------------------------------+ +``` + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x0014_static-variables/ +| +-- build/ +| | +-- 0x0014_static-variables.uf2 +| | +-- 0x0014_static-variables.elf +| +-- 0x0014_static-variables.c ++-- uf2conv.py +``` + +--- + +## Part 5: Hands-On Tutorial - Static Variables and GPIO Input + +### Step 1: Review the Source Code + +Let's examine the static variables code: + +**File: `0x0014_static-variables.c`** + +```c +#include +#include "pico/stdlib.h" + +int main(void) { + stdio_init_all(); + + const uint BUTTON_GPIO = 15; + const uint LED_GPIO = 16; + bool pressed = 0; + + gpio_init(BUTTON_GPIO); + gpio_set_dir(BUTTON_GPIO, GPIO_IN); + gpio_pull_up(BUTTON_GPIO); + + gpio_init(LED_GPIO); + gpio_set_dir(LED_GPIO, GPIO_OUT); + + while (true) { + uint8_t regular_fav_num = 42; + static uint8_t static_fav_num = 42; + + printf("regular_fav_num: %d\r\n", regular_fav_num); + printf("static_fav_num: %d\r\n", static_fav_num); + + regular_fav_num++; + static_fav_num++; + + pressed = gpio_get(BUTTON_GPIO); + gpio_put(LED_GPIO, pressed ? 0 : 1); + } +} +``` + +**What this code does:** + +1. **Line 6-8:** Defines constants for button (GPIO 15) and LED (GPIO 16) pins +2. **Line 10-12:** Sets up GPIO 15 as input with internal pull-up resistor +3. **Line 14-15:** Sets up GPIO 16 as output for the LED +4. **Line 18-19:** Creates two variables: + - `regular_fav_num` - a normal local variable (recreated each loop) + - `static_fav_num` - a static variable (persists across loops) +5. **Line 21-22:** Prints both values to the serial terminal +6. **Line 24-25:** Increments both values +7. **Line 27-28:** Reads button and controls LED accordingly + +### Step 2: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x0014_static-variables.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 3: Open Your Serial Monitor + +Open PuTTY, minicom, or screen and connect to your Pico's serial port. + +**You should see output like this:** + +``` +... +regular_fav_num: 42 +static_fav_num: 42 +regular_fav_num: 42 +static_fav_num: 43 +regular_fav_num: 42 +static_fav_num: 44 +regular_fav_num: 42 +static_fav_num: 45 +... +``` + +**Notice the difference:** + +- `regular_fav_num` stays at 42 every time (it's recreated each loop) +- `static_fav_num` increases each time (it persists and remembers its value) + +### Step 4: Test the Button + +Now test the button behavior: + +- **Button NOT pressed:** LED should be OFF +- **Button PRESSED:** LED should turn ON + +That may feel backwards at first glance, but it matches the pull-up + ternary logic in the code. We'll hack this later to make the behavior more intuitive. + +### Step 5: Watch for Overflow + +Keep the program running and watch `static_fav_num`. After 255, you'll see: + +``` +static_fav_num: 254 +static_fav_num: 255 +static_fav_num: 0 <- Wrapped around! +static_fav_num: 1 +static_fav_num: 2 +... +``` + +This demonstrates unsigned integer overflow! + +--- + +## Part 6: Debugging with GDB (Dynamic Analysis) + +> Note: **REVIEW:** This setup is identical to previous weeks. If you need a refresher on OpenOCD and GDB connection, refer back to Week 3 Part 6. + +### Starting the Debug Session + +**Terminal 1 - Start OpenOCD:** + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +**Terminal 2 - Start GDB:** + +```cmd +arm-none-eabi-gdb build\0x0014_static-variables.elf +``` + +**Connect to target:** + +```gdb +(gdb) target extended-remote :3333 +(gdb) monitor reset halt +``` + +### Step 6: Examine Main Function + +Let's examine the main function at its entry point. First, disassemble from the start: + +``` +x/38i 0x10000234 +``` + +You should see output like: + +``` +(gdb) x/38i 0x10000234 + 0x10000234
: push {r4, lr} + 0x10000236 : bl 0x10003014 + 0x1000023a : movs r0, #15 + 0x1000023c : bl 0x10000300 + 0x10000240 : movs r0, #15 + 0x10000242 : mov.w r3, #0 + 0x10000246 : mcrr 0, 4, r0, r3, cr4 + 0x1000024a : movs r2, #0 + 0x1000024c : movs r1, #1 + 0x1000024e : bl 0x100002d8 + 0x10000252 : movs r0, #16 + 0x10000254 : bl 0x10000300 + 0x10000258 : movs r3, #16 + 0x1000025a : mov.w r2, #1 + 0x1000025e : mcrr 0, 4, r3, r2, cr4 + 0x10000262 : ldr r4, [pc, #44] @ (0x10000290 ) + 0x10000264 : movs r1, #42 @ 0x2a + 0x10000266 : ldr r0, [pc, #44] @ (0x10000294 ) + 0x10000268 : bl 0x100031a4 <__wrap_printf> + 0x1000026c : ldrb r1, [r4, #0] + 0x1000026e : ldr r0, [pc, #40] @ (0x10000298 ) + 0x10000270 : bl 0x100031a4 <__wrap_printf> + 0x10000274 : mov.w r1, #3489660928 @ 0xd0000000 + 0x10000278 : ldrb r3, [r4, #0] + 0x1000027a : movs r2, #16 + 0x1000027c : adds r3, #1 + 0x1000027e : strb r3, [r4, #0] + 0x10000280 : ldr r3, [r1, #4] + 0x10000282 : ubfx r3, r3, #15, #1 + 0x10000286 : eor.w r3, r3, #1 + 0x1000028a : mcrr 0, 4, r2, r3, cr0 + 0x1000028e : b.n 0x10000264 + 0x10000290 : lsls r0, r5, #22 + 0x10000292 : movs r0, #0 + 0x10000294 : adds r5, #96 @ 0x60 + 0x10000296 : asrs r0, r0, #32 + 0x10000298 : adds r5, #120 @ 0x78 + 0x1000029a : asrs r0, r0, #32 +``` + +### Step 7: Set a Breakpoint at Main + +``` +b *0x10000234 +c +``` + +### Step 8: Examine the Static Variable Location + +Static variables live at fixed RAM addresses. But how do we find that address? Look at `0x10000262` in the disassembly from Step 6: + +``` +(gdb) x/16i 0x10000234 +=> 0x10000234
: push {r4, lr} + 0x10000236 : bl 0x10003014 + 0x1000023a : movs r0, #15 + 0x1000023c : bl 0x10000300 + 0x10000240 : movs r0, #15 + 0x10000242 : mov.w r3, #0 + 0x10000246 : mcrr 0, 4, r0, r3, cr4 + 0x1000024a : movs r2, #0 + 0x1000024c : movs r1, #1 + 0x1000024e : bl 0x100002d8 + 0x10000252 : movs r0, #16 + 0x10000254 : bl 0x10000300 + 0x10000258 : movs r3, #16 + 0x1000025a : mov.w r2, #1 + 0x1000025e : mcrr 0, 4, r3, r2, cr4 + 0x10000262 : ldr r4, [pc, #44] @ (0x10000290 ) +``` + +This loads `r4` from the **literal pool** at address `0x10000290`. The literal pool stores constants that are too large for immediate encoding - in this case, a 32-bit RAM address. Let's examine what's stored there: + +```gdb +(gdb) x/1wx 0x10000290 +0x10000290 : 0x200005a8 +``` + +That's `0x200005a8` - the RAM address of `static_fav_num`! The compiler placed this address in the literal pool because it can't encode a full 32-bit address in a single Thumb instruction. + +> **Common confusion three things that trip people up here:** +> +> **1. GDB shows `` instead of ``.** +> `static_fav_num` is a function-local static, so it does not appear in GDB's global symbol table. GDB labels the address with the nearest *named* global symbol it can find in this case an SDK-internal spin-lock variable that happens to be nearby. The address `0x200005a8` is still correct; the label is just GDB's best guess at a name. +```gdb +(gdb) x/x 0x200005a8 +0x200005a8 : 0x0000122a +``` +> +> **2. `x/x 0x200005a8` shows `0x0000122a`, not `0x0000002a` (42).** +> `x/x` reads a **4-byte word** (32 bits). `static_fav_num` is a `uint8_t` only **1 byte**. The low byte of `0x0000122a` is `0x2a` = 42. That *is* the variable. The upper bytes belong to whatever happens to be in adjacent RAM. To read exactly one byte and see `42`, use: +```gdb +(gdb) x/1ub 0x200005a8 +0x200005a8 : 42 +``` +> +> **3. `x/x *0x200005a8` shows junk at address `0x122a`.** +> The `*` is a pointer dereference. GDB first reads the 4-byte word at `0x200005a8` (= `0x0000122a`), then treats that *value* as a new address and reads from `0x0000122a`. You are asking GDB to follow a pointer that was never meant to be a pointer the result is meaningless. Drop the `*`: use `x/1ub 0x200005a8` to read the variable's value directly. + +> Tip: **Why did the disassembly at `0x10000290` show `lsls r0, r5, #22` instead?** Because `x/i` (disassemble) interprets raw data as instructions. The bytes `A8 05 00 20` at that address are the little-endian encoding of `0x200005A8`, but GDB's disassembler doesn't know it's data - it tries to decode it as a Thumb instruction. Using `x/wx` (examine as word) shows the actual value. + +### Step 9: Step Through the Loop + +The loop body starts at `0x10000264`. Set a breakpoint there and continue: + +```gdb +(gdb) b *0x10000264 +(gdb) c +(gdb) x/i $pc +=> 0x10000264 : movs r1, #42 @ 0x2a +``` + +GDB will stop at `movs r1, #42` that is the compiler's constant for `regular_fav_num`. Let's set a breakpoint and continue at `0x10000278`. + +```gdb +(gdb) b *0x10000278 +(gdb) c +(gdb) x/i $pc +=> 0x10000278 : ldrb r3, [r4, #0] +``` + +This is where the static variable is actually manipulated: + +```gdb +(gdb) x/4i $pc +=> 0x10000278 : ldrb r3, [r4, #0] <- load static_fav_num from RAM into r3 + 0x1000027a : movs r2, #16 <- load LED pin number (16) into r2 for later + 0x1000027c : adds r3, #1 <- increment r3 by 1 + 0x1000027e : strb r3, [r4, #0] <- store incremented value back to RAM +``` + +Confirm what `r4` actually contains right now: + +```gdb +(gdb) x/x $r4 +0x200005a8 : 0x2a +``` + +`r4` is `0x200005a8`, a RAM address. The value at that address is `0x2a` (42 in decimal), which is the current value of `static_fav_num`. After `adds r3, #1` and `strb r3, [r4, #0]` execute, examining `r4` again will show `0x0000002b` (43). + +**What is the literal pool?** + +A Thumb `ldr` instruction is only 16 or 32 bits wide. There is no room inside those bits to encode a full 32-bit constant like `0x200005a8`. To solve this, the compiler collects all such large constants and writes them into a small block of **raw data** embedded directly in the flash image this block is called a **literal pool** (also called a constant pool). + +**There is not one literal pool per flash, there is (at least) one per function.** Every function that references large constants gets its own pool appended to its code. A large function can have several pools scattered through it wherever the compiler decides to emit them. Each pool is purely data; the CPU must never try to execute it. + +**Where exactly is a literal pool placed?** Always **after an unconditional branch**, never before or in the middle of a straight-line code path. This is by design: the CPU falls through code sequentially, so the pool must be unreachable by fall-through. In our case the pool sits at `0x10000290`, directly after the `b.n 0x10000264` branch at `0x1000028e` that closes the `while (true)` loop: + +``` +0x1000028e: b.n 0x10000264 <- unconditional branch back to loop top +0x10000290: [literal pool] <- CPU never reaches here by fall-through +``` + +**Why does the pool have to be nearby?** The `ldr rN, [pc, #offset]` instruction encodes the offset in a limited number of bits. In standard Thumb the maximum reach is **1020 bytes** from the instruction. If the function is long enough that the end is out of range, the assembler emits an intermediate pool mid-function after the next unconditional branch it can find. This is in the ARM v8-M Architecture Reference Manual p. 672. + +**How the load works in our function:** At `0x10000262` the compiler emits: + +``` +ldr r4, [pc, #44] @ (0x10000290) +``` + +On ARM, `PC` reads as the address of the instruction **plus 4** during execution. So the effective address is `0x10000262 + 4 + 44 = 0x10000290`. That word in the pool contains `0x200005a8`, the RAM address of `static_fav_num`. The pool is also where the `printf` format-string pointers live (the other `ldr` instructions you saw in the disassembly). + +``` +Flash (read-only) ++-------------------------------------------+ RAM +| 0x10000262: ldr r4, [pc, #44] | +------------------+ +| ...loop body... | | 0x200005a8: 42 | <- static_fav_num +| 0x1000028e: b.n 0x10000264 (end of loop) | +------------------+ ++------- literal pool (data, not code) -----+ ^ +| 0x10000290: 0x200005a8 --------------------+----------------+ +| 0x10000294: ptr to "regular_fav_num: %d" | r4 holds this address +| 0x10000298: ptr to "static_fav_num: %d" | ++------- next function ---------------------+ +| 0x1000029c: push {r4} | ++-------------------------------------------+ +``` + +You can see this directly. Run `x/10i 0x1000028e` in GDB and you will get exactly this: + +```gdb +(gdb) x/10i 0x1000028e + (gdb) x/10i 0x1000028e + 0x1000028e : b.n 0x10000264 <- unconditional branch, loop top + 0x10000290 : lsls r0, r5, #22 <-+ + 0x10000292 : movs r0, #0 <-+-- word 1: 0x200005a8 (fixed RAM addr static_fav_num) + 0x10000294 : adds r5, #96 @ 0x60 <-+ + 0x10000296 : asrs r0, r0, #32 <-+-- word 2: 0x10004b60 (flash addr regular_fav_num text) + 0x10000298 : adds r5, #120 <-+ + 0x1000029a : asrs r0, r0, #32 <-+-- word 3: 0x10004b78 (flash addr static_fav_num text) +``` + +`0x10000290` - `0x1000029b` is the literal pool 12 bytes, 3 32-bit words. GDB's `x/i` (disassemble) has no idea those bytes are data, so it blindly decodes them as Thumb instructions and produces nonsense (`lsls r0, r5, #22`, etc.). The giveaway that you have entered pool territory is always the same: **garbled, implausible instructions immediately after an unconditional branch**. Use `x/wx` to read those addresses as data and you get the real values: + +```gdb +(gdb) x/3wx 0x10000290 +0x10000290 : 0x200005a8 0x10003560 0x10003578 +``` + +```gdb +(gdb) x/1ub 0x200005a8 +0x200005a8 : 42 +``` +- `0x200005a8` RAM address of `static_fav_num`, lives in the **`.data` section** (initialized static RAM, `0x20000000``0x200xxxxx`). It is `.data` and not `.bss` because the variable has an explicit initializer (`= 42`). `.bss` is for variables that are zero-initialized or have no initializer at all. + +```gdb +(gdb) x/s 0x10003560 +0x10003560: "regular_fav_num: %d\r\n" +``` +- `0x10003560` flash address of the `"regular_fav_num: %d\r\n"` string literal, lives in the **`.rodata` section** (read-only data) inside flash (`0x10000000`+). String literals are constants baked into the binary at compile time they never change and never move, so they stay in flash. + +```gdb +(gdb) x/s 0x10003578 +0x10003578: "static_fav_num: %d\r\n" +``` + +- `0x10003578` flash address of the `"static_fav_num: %d\r\n"` string literal, also in **`.rodata`** in flash for the same reason. + +So the pool contains addresses into three different regions: RAM `.data` (the static variable), and flash `.rodata` (both format strings). Only the RAM address needed to be in the pool, the flash addresses could in principle be reached other ways, but they are also too large to encode as 16-bit immediates, so they go in the pool too. + +**Why `.data` and not `.bss`?** The distinction matters: + +| Section | What goes here | Example declarations | Initial value stored in flash? | +|---------|---------------|----------------------|-------------------------------| +| `.data` | Any static-duration variable with a **non-zero initializer** | `static uint8_t x = 42;` (inside a function) | Yes the initial value lives in flash; startup copies it to RAM | +| `.data` | Same rule applies to **global** variables with non-zero initializers | `uint8_t g = 10;` (outside all functions) | Yes same startup copy | +| `.bss` | Any static-duration variable with **no initializer or zero initializer** | `static uint8_t x;` or `static uint8_t x = 0;` | No startup just zeroes the RAM range; no flash copy needed | +| `.bss` | Same rule for **global** variables that are zero/uninitialized | `uint8_t g;` or `uint8_t g = 0;` (outside functions) | No same zero-fill at startup | + +The rule is not about `static` specifically it is about **lifetime and initial value**. Any variable whose lifetime spans the whole program (static locals, globals) goes into `.data` or `.bss`. The `static` keyword inside a function just forces that lifetime. A global variable without `static` has the same lifetime and follows the same rule. + +`static_fav_num = 42` has an explicit non-zero initializer, so the linker puts it in `.data`. The startup code copies the initial value `42` from flash into RAM address `0x200005a8` before `main()` runs. If it had been `static uint8_t static_fav_num;` (no initializer), the linker would put it in `.bss` instead and the startup code would zero that RAM region no flash copy needed. + +**Why is there no pool entry for the address of `regular_fav_num`?** + +Because `regular_fav_num` is an **automatic (stack) variable** it has no fixed address. Automatic variables are allocated on the call stack at runtime, relative to the current stack pointer (`sp`). Their address changes every time the function runs and is different on every call. There is no constant 32-bit address to put in a pool. + +In this specific case the compiler went even further: it **never gave `regular_fav_num` a stack slot at all**. The compiler saw that the value is always `42` when printed, so it baked the constant `42` directly into the `movs r1, #42` instruction. The variable lives only in a register at the moment it is needed — no stack space reserved, no pool entry, no load-store cycle. + +**You can prove this with three GDB checks:** + +**Proof 1 `info locals` shows the value came from a register, not a stack slot:** + +```gdb +(gdb) b *0x10000264 +(gdb) c +(gdb) info locals +regular_fav_num = 42 '*' +static_fav_num = 42 '*' +BUTTON_GPIO = 15 +LED_GPIO = 16 +pressed = +``` + +The `'*'` suffix after `42` means GDB retrieved the value from a **register** (specifically `r1`, which holds `42` at this point), not from a stack slot. The variable has no fixed memory address — GDB can report its current value only because the right register happens to hold it right now. Notice that `pressed` is the one showing `` — the compiler removed it from tracking entirely because its value is never needed after the ternary expression. + +**Proof 2 The function prologue allocates no stack space for locals:** + +```gdb +(gdb) x/2i 0x10000234 + 0x10000234
: push {r4, lr} + 0x10000236 : bl 0x10003014 +``` + +The very first instruction is `push {r4, lr}`, that saves `r4` (a callee-saved register) and `lr` (return address). There is **no** `sub sp, #N` instruction after it. On ARM, allocating stack space for local variables requires subtracting from `sp` to reserve room. If `regular_fav_num` lived on the stack, there would be a `sub sp, #4` (or similar) here. There isn't, so no stack slot was ever created. + +**Proof 3 The loop body contains no store to the stack for `regular_fav_num`:** + +```gdb +(gdb) x/6i 0x10000264 +=> 0x10000264 : movs r1, #42 @ 0x2a + // constant 42 baked directly into instruction + 0x10000266 : ldr r0, [pc, #44] @ (0x10000294 ) + // load format string address from pool + 0x10000268 : bl 0x100031a4 <__wrap_printf> + // call printf + 0x1000026c : ldrb r1, [r4, #0] + // load static_fav_num from RAM + 0x1000026e : ldr r0, [pc, #40] @ (0x10000298 ) + // load format string address from pool + 0x10000270 : bl 0x100031a4 <__wrap_printf> + call printf +``` + +For `regular_fav_num`, the value `42` goes straight into `r1` via `movs`, it is never written to memory and never read back from memory. There is no `strb r1, [sp, #N]` storing it to the stack, and no `ldrb r1, [sp, #N]` loading it back. The variable exists only in the source code. In the binary it is just a number in an instruction encoding. + +`static_fav_num` is the exact opposite. It lives in the `.data` section of RAM, a fixed, known address (`0x200005a8`) that is set at link time and never changes for the life of the program. That fixed address is exactly the kind of value that cannot fit in a 16-bit Thumb instruction, so the linker writes it into the literal pool and the CPU fetches it with `ldr r4, [pc, #44]`. + +> **IMPORTANT:** Static variables are **not** on the heap. The heap is for dynamic memory (`malloc`/`free`), memory whose lifetime is controlled explicitly at runtime. Static and global variables live in the `.data` section (if initialized) or `.bss` section (if zero/uninitialized), a region of RAM with a fixed layout determined at link time, not at runtime. + +``` +Memory regions for our two variables: ++------------------------------------------+ +| FLASH (read-only, 0x10000000+) | +| - Code (instructions) | +| - Literal pool (our 3 words) | +| - String literals ("regular_fav_num...")| ++------------------------------------------+ +| RAM .data section (0x20000000+) | +| - static_fav_num @ 0x200005a8 <- pool | ++------------------------------------------+ +| STACK (grows down from 0x20082000) | +| - regular_fav_num (if not optimized) | +| frame-relative, no fixed address | ++------------------------------------------+ +| HEAP (grows up, between stack and .bss) | +| - malloc/free only, nothing here today | ++------------------------------------------+ +``` + +The pool ends at `0x1000029b`. At `0x1000029d` a new function begins, specifically `gpio_set_function`. The first two instructions, `push {r4}` (save caller's `r4` to the stack) and `mov.w r4, #256` (load a working constant), are a standard SDK function prologue, nothing to do with `main`. The `ldr r3, [pc, #48]`i r/. at `0x100002a3` (`gpio_set_function+6`) is that next function loading from **its own** literal pool further ahead in flash — proof that every function manages its own pool. + +### Step 10: Examine Register Values + +After breaking at `0x10000264`, check the registers: + +```gdb +(gdb) i r +``` + +What you will actually see: + +- `r4` = `0x200005a8` — the static variable's fixed RAM address. This was loaded from the literal pool in the function prologue and never changes across loop iterations. +- `r1` = leftover value from the previous `printf` call (e.g. `0x40039044`). The breakpoint is stopped **at** `movs r1, #42` — that instruction has not executed yet, so `r1` does not yet hold `42`. +- `r3` = leftover from prior operations (e.g. `0x10`). It will be used later in the loop body to load, increment, and store `static_fav_num`, but not yet. +- `pc` = `0x10000264` — the loop top, pointing at the `movs r1, #42` instruction. + +You can confirm `r4` holds the right address and value: + +```gdb +(gdb) x/1db $r4 +0x200005a8 : 42 +``` + +The `` label is just the nearest named global symbol in the SDK that GDB finds at that address — the actual variable stored there is our `static_fav_num`. + +### Step 11: Watch the Static Variable Change + +Now that we know the static variable lives at `0x200005a8`, examine it directly: + +```gdb +(gdb) x/1db 0x200005a8 +0x200005a8 : 42 +``` + +Step through a full loop iteration (back to `0x10000264`) and re-examine: + +```gdb +(gdb) c +(gdb) x/1db 0x200005a8 +0x200005a8 : 43 +``` + +The value incremented from 42 to 43! Each loop iteration, the `adds r3, #1` at `0x1000027c` bumps it by 1, and `strb r3, [r4, #0]` at `0x1000027e` writes it back to RAM. + +### Step 12: Examine GPIO State + +Read the GPIO input register to see the button state: + +```gdb +(gdb) x/1wx 0xd0000004 +0xd0000004: 0x00008003 +``` + +The SIO GPIO input register at `0xd0000004` shows the current state of all GPIO pins. Bit 15 corresponds to our button on GPIO 15. To extract just bit 15: + +```gdb +(gdb) p/x (*(unsigned int *)0xd0000004 >> 15) & 1 +$1 = 0x1 +``` + +- Returns `1` when button is **not pressed** (pull-up holds it HIGH) +- Returns `0` when button is **pressed** (connected to GND) + +TRY IT! + +--- + +## Part 7: Understanding the Assembly + +Now that we've explored the binary in GDB, let's make sense of the key patterns. + +### Step 13: Analyze the Regular Variable + +In GDB, examine the code at the start of the loop: + +```gdb +(gdb) x/5i 0x10000262 + 0x10000262 : ldr r4, [pc, #44] @ (0x10000290 ) +=> 0x10000264 : movs r1, #42 @ 0x2a + 0x10000266 : ldr r0, [pc, #44] @ (0x10000294 ) + 0x10000268 : bl 0x100031a4 <__wrap_printf> + 0x1000026c : ldrb r1, [r4, #0] +``` + +Look for this instruction: + +``` +0x10000264 : movs r1, #42 @ 0x2a +``` + +This loads the value `0x2a` (42 in decimal) directly into register `r1` for the first `printf` call. + +**Key insight:** The compiler **never allocated stack space** for `regular_fav_num`. Since it is always `42` when printed, the compiler bakes the constant directly into the `movs r1, #42` instruction. The `regular_fav_num++` after the print is also removed because it has no observable effect — the variable is recreated as `42` on the next loop iteration anyway. + +### Step 14: Analyze the Static Variable + +Examine the static variable operations in the second half of the loop body: + +```gdb +(gdb) x/10i 0x10000274 + 0x10000274 : mov.w r1, #3489660928 @ 0xd0000000 + 0x10000278 : ldrb r3, [r4, #0] + 0x1000027a : movs r2, #16 + 0x1000027c : adds r3, #1 + 0x1000027e : strb r3, [r4, #0] + 0x10000280 : ldr r3, [r1, #4] + 0x10000282 : ubfx r3, r3, #15, #1 + 0x10000286 : eor.w r3, r3, #1 + 0x1000028a : mcrr 0, 4, r2, r3, cr0 + 0x1000028e : b.n 0x10000264 +``` + +Look for the load-increment-store pattern using `r4` (which holds the static variable's RAM address): + +``` + ... + 0x10000278 : ldrb r3, [r4, #0] + 0x1000027a : movs r2, #16 + 0x1000027c : adds r3, #1 + 0x1000027e : strb r3, [r4, #0] + ... +``` + +Note that `r4` was loaded earlier at `0x10000262` via `ldr r4, [pc, #44]` - this pulled the static variable's RAM address (`0x200005a8`) from the literal pool at `0x10000290`. + +**Key insight:** The static variable lives at a **fixed RAM address** (`0x200005a8`). It's loaded, incremented, and stored back. The regular variable, by contrast, never gets a stack slot — the compiler holds it in a register and bakes the constant `42` directly into the instruction, so there is nothing to load or store. + +Verify the static variable value which should be `43`: + +```gdb +(gdb) x/1db 0x200005a8 +0x200005a8 : 43 +``` + +### Step 15: Analyze the GPIO Logic + +Examine the GPIO input/output code: + +```gdb +(gdb) x/10i 0x10000274 + 0x10000274 : mov.w r1, #3489660928 @ 0xd0000000 + 0x10000278 : ldrb r3, [r4, #0] + 0x1000027a : movs r2, #16 + 0x1000027c : adds r3, #1 + 0x1000027e : strb r3, [r4, #0] + 0x10000280 : ldr r3, [r1, #4] + 0x10000282 : ubfx r3, r3, #15, #1 + 0x10000286 : eor.w r3, r3, #1 + 0x1000028a : mcrr 0, 4, r2, r3, cr0 + 0x1000028e : b.n 0x10000264 +``` + +**Breaking this down:** + +| Address | Instruction | Purpose | +| -------------- | -------------------------- | ---------------------------------------------------- | +| `0x10000274` | `mov.w r1, #0xd0000000` | Load SIO (Single-cycle I/O) base address into `r1` | +| `0x10000278` | `ldrb r3, [r4, #0]` | Load `static_fav_num` from RAM into `r3` | +| `0x1000027a` | `movs r2, #16` | Load LED pin number (16) into `r2` for later | +| `0x1000027c` | `adds r3, #1` | Increment `static_fav_num` by 1 | +| `0x1000027e` | `strb r3, [r4, #0]` | Store incremented value back to RAM | +| `0x10000280` | `ldr r3, [r1, #4]` | Read GPIO input state (SIO_GPIO_IN at offset `0x04`) | +| `0x10000282` | `ubfx r3, r3, #15, #1` | Extract bit 15 (GPIO 15 = button) | +| `0x10000286` | `eor.w r3, r3, #1` | XOR with 1 to invert (implements `? 0 : 1`) | +| `0x1000028a` | `mcrr 0, 4, r2, r3, cr0` | Write `r3` (button) and `r2` (pin 16) to GPIO output | +| `0x1000028e` | `b.n 0x10000264` | Loop back to start (`while (true)`) | + +> Tip: **Notice how the compiler interleaves the static variable increment with the GPIO logic.** It loads the SIO base address (`r1`) *before* doing the increment, and sets up `r2 = 16` (LED pin) in between. This is called **instruction scheduling** - the compiler reorders instructions to avoid pipeline stalls while waiting for memory reads. + +### Step 16: Find the Infinite Loop + +The last instruction at `0x1000028e` is already covered in the table above: + +``` + 0x1000028e : b.n 0x10000264 +``` + +This is an **unconditional branch** back to `0x10000264` (the `movs r1, #42` at the top of the loop) - this is the `while (true)` in our code! There is no `pop` or `bx lr` to return from `main` because the loop never exits. + +--- + +## Part 8: Hacking the Binary with a Hex Editor + +Now for the fun part - we'll patch the `.bin` file directly using a hex editor! + +> Tip: **Why a hex editor?** GDB **cannot write to flash memory** - the `0x10000000+` address range where program instructions live. Trying `set *(char *)0x10000264 = 0x2b` in GDB gives `Writing to flash memory forbidden in this context`. To make **permanent** patches that survive a power cycle, we edit the `.bin` file directly with a hex editor and re-flash it. + +### Step 17: Open the Binary in a Hex Editor + +1. Open **HxD** (or your preferred hex editor: ImHex, 010 Editor, etc.) +2. Click **File** -> **Open** +3. Navigate to `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0014_static-variables\build\` +4. Open `0x0014_static-variables.bin` + +### Step 18: Calculate the File Offset + +The binary is loaded at base address `0x10000000`. To find the file offset of any address: + +``` +file_offset = address - 0x10000000 +``` + +For example: + +- Address `0x10000264` -> file offset `0x264` (612 in decimal) +- Address `0x10000286` -> file offset `0x286` (646 in decimal) + +### Step 19: Hack #1 - Change regular_fav_num from 42 to 43 + +From our GDB analysis, we know the instruction at `0x10000264` is: + +``` +movs r1, #0x2a -> bytes: 2a 21 +``` + +To change the value from 42 (`0x2a`) to 43 (`0x2b`): + +1. In HxD, open `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0014_static-variables\build\0x0014_static-variables.bin` +2. Press **Ctrl+G** (Go to offset) +3. Enter offset: `264` +4. You should see the byte `2A` at this position +5. Change `2A` to `2B` +6. The instruction is now `movs r1, #0x2b` (43 in decimal) + +> Note: **How Thumb encoding works:** In `movs r1, #imm8`, the immediate value is the first byte, and the opcode `21` is the second byte. So the bytes `2a 21` encode `movs r1, #0x2a`. + +### Step 20: Hack #2 - Invert the Button Logic + +#### Understand the Encoding + +From GDB, we found the `eor.w r3, r3, #1` instruction at `0x10000286` that inverts the button value. Examine the exact bytes: + +```gdb +(gdb) x/4bx 0x10000286 +0x10000286 : 0x83 0xf0 0x01 0x03 +``` + +This is the 32-bit Thumb-2 encoding of `eor.w r3, r3, #1`. The bytes break down as: + +``` ++-----------------------------------------------------------------+ +| eor.w r3, r3, #1 -> bytes: 83 F0 01 03 | +| | +| Byte 0: 0x83 -+ | +| Byte 1: 0xF0 -+-- First halfword (opcode + source register) | +| Byte 2: 0x01 ---- Immediate value (#1) <- CHANGE THIS | +| Byte 3: 0x03 ---- Destination register (r3) | +| | ++-----------------------------------------------------------------+ +``` + +To change `eor.w r3, r3, #1` to `eor.w r3, r3, #0` (making XOR do nothing): + +The file offset is `0x10000286 - 0x10000000 = 0x286`. The immediate byte is the 3rd byte of the instruction, so: `0x286 + 2 = 0x288`. + +To change `eor.w r3, r3, #1` to `eor.w r3, r3, #0`: + +1. In HxD, press **Ctrl+G** (Go to offset) +2. Enter offset: `288` (the third byte of the 4-byte instruction) +3. You should see the byte `01` at this position +4. Change `01` to `00` + +> Note: **Why offset `0x288` and not `0x286`?** The immediate value `#1` is in the **third byte** of the 4-byte instruction. The instruction starts at file offset `0x286`, so the immediate byte is at `0x286 + 2 = 0x288`. + +Now the logic is permanently changed: + +- Button released (input = 1): `1 XOR 0 = 1` -> LED **ON** +- Button pressed (input = 0): `0 XOR 0 = 0` -> LED **OFF** + +This is the **opposite** of the original behavior! + +### Step 21: Save the Patched Binary + +1. Click **File** -> **Save As** +2. Save as `0x0014_static-variables-h.bin` in the build directory +3. Close the hex editor + +--- + +## Part 9: Converting and Flashing the Hacked Binary + +### Step 22: Convert to UF2 Format + +Open a terminal and navigate to your project directory: + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0014_static-variables +``` + +Run the conversion command: + +```cmd +python ..\uf2conv.py build\0x0014_static-variables-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +**What this command means:** + +- `uf2conv.py` = the conversion script (in the parent `Embedded-Hacking` directory) +- `--base 0x10000000` = the XIP base address where code runs from +- `--family 0xe48bff59` = the RP2350 family ID +- `--output build\hacked.uf2` = the output filename + +### Step 23: Flash the Hacked Binary + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Open your serial monitor + +### Step 24: Verify the Hacks + +**Check the serial output:** +``` +regular_fav_num: 43 <- Changed from 42! +static_fav_num: 42 +regular_fav_num: 43 +static_fav_num: 43 +... +``` + +**Check the LED behavior:** + +- LED should now be **ON by default** (when button is NOT pressed) +- LED should turn **OFF** when you press the button + + **BOOM! We successfully:** + +1. Changed the printed value from 42 to 43 +2. Inverted the LED/button logic + +--- + +## Part 10: Summary and Review + +### What We Accomplished + +1. **Learned about static variables** - How they persist across function calls and loop iterations +2. **Understood memory layout** - Stack vs static storage vs heap +3. **Configured GPIO inputs** - Using pull-up resistors and reading button states +4. **Analyzed compiled code in GDB** - Saw how the compiler optimizes code +5. **Discovered function inlining** - `gpio_pull_up` became `gpio_set_pulls` +6. **Hacked variable values** - Changed 42 to 43 using a hex editor +7. **Inverted GPIO logic** - Made LED behavior opposite + +### Static vs Automatic Variables + +| Aspect | Automatic (Regular) | Static | +| ------------------ | ------------------------ | --------------------------- | +| **Storage** | Stack | Static storage (.data/.bss) | +| **Lifetime** | Block/function scope | Entire program | +| **Initialization** | Every time block entered | Once at program start | +| **Persistence** | Lost when scope exits | Retained between calls | +| **Compiler view** | May be optimized away | Always has memory location | + +### GPIO Input Configuration + +``` ++-----------------------------------------------------------------+ +| GPIO Input Setup Steps | +| | +| 1. gpio_init(pin) - Initialize the pin | +| 2. gpio_set_dir(pin, GPIO_IN) - Set as input | +| 3. gpio_pull_up(pin) - Enable pull-up | +| OR gpio_pull_down(pin) - OR enable pull-down | +| 4. gpio_get(pin) - Read the state | +| | ++-----------------------------------------------------------------+ +``` + +### The Binary Hacking Workflow + +``` ++-----------------------------------------------------------------+ +| 1. Analyze the binary with GDB | +| - Disassemble functions with x/Ni | +| - Identify key instructions and addresses | ++-----------------------------------------------------------------+ +| 2. Understand compiler optimizations | +| - Some functions inlined (gpio_pull_up -> gpio_set_pulls) | +| - Some variables are optimized away | ++-----------------------------------------------------------------+ +| 3. Calculate file offsets | +| - file_offset = address - 0x10000000 | ++-----------------------------------------------------------------+ +| 4. Patch the .bin file with a hex editor | +| - Open the .bin file in HxD / ImHex | +| - Go to the calculated offset | +| - Change the target byte(s) | ++-----------------------------------------------------------------+ +| 5. Convert to UF2 | +| python uf2conv.py file.bin --base 0x10000000 | +| --family 0xe48bff59 --output hacked.uf2 | ++-----------------------------------------------------------------+ +| 6. Flash and verify | +| - Hold BOOTSEL, plug in, drag UF2 | +| - Check serial output and button/LED behavior | ++-----------------------------------------------------------------+ +``` + +### Key Memory Addresses + +| Address | Description | +| ------------ | ----------------------------------- | +| `0x10000234` | Typical main() entry point | +| `0x10003014` | stdio_init_all() function | +| `0x200005a8` | Static variable storage (example) | +| `0xd0000000` | SIO (Single-cycle I/O) base address | + +--- + +--- + +## Key Takeaways + +1. **Static variables persist** - They keep their value between function calls and loop iterations. + +2. **Static storage != heap** - Static variables reside in fixed memory (.data/.bss), not dynamically allocated on the heap. + +3. **Compilers optimize aggressively** - Regular variables may be optimized away if the compiler sees no effect. + +4. **Function inlining is common** - `gpio_pull_up` becomes `gpio_set_pulls` in the binary. + +5. **Pull-up resistors prevent floating inputs** - By holding the pin HIGH when released, they eliminate undefined states; pressing the active-low button pulls the pin to GND (LOW). + +6. **XOR is useful for inverting** - `eor r3,r3,#0x1` flips a bit between 0 and 1. + +7. **Static variables have fixed addresses** - You can find them in the .data section at known RAM addresses. + +8. **Overflow wraps around** - A `uint8_t` at 255 becomes 0 when incremented. + +9. **UBFX extracts bits** - Used to read a single GPIO pin from a register. + +10. **Binary patching is powerful** - Change values and logic without source code! + +--- + +## Glossary + +| Term | Definition | +| --------------------- | ---------------------------------------------------------------- | +| **Automatic** | Variable that's created and destroyed automatically (local vars) | +| **eor/XOR** | Exclusive OR - flips bits where operands differ | +| **Floating Input** | GPIO input with undefined voltage (reads random values) | +| **Function Inlining** | Compiler replaces function call with the function's code | +| **gpio_get** | Function to read the current state of a GPIO pin | +| **Heap** | Memory area for dynamic allocation (malloc/free) | +| **Overflow** | When a value exceeds its type's maximum and wraps around | +| **Pull-Down** | Resistor that holds a pin LOW when nothing drives it | +| **Pull-Up** | Resistor that holds a pin HIGH when nothing drives it | +| **SIO** | Single-cycle I/O - fast GPIO access on RP2350 | +| **Stack** | Memory area for local variables and function call frames | +| **Static Storage** | Fixed memory area for static and global variables | +| **Static Variable** | Variable declared with `static` that persists across calls | +| **Ternary Operator** | `condition ? value_if_true : value_if_false` | +| **UBFX** | Unsigned Bit Field Extract - extracts bits from a register | +| **Varargs** | Variable arguments - functions that take unlimited parameters | + +--- + +## Additional Resources + +### GPIO Input Reference + +| Function | Purpose | +| ----------------------------- | -------------------------- | +| `gpio_init(pin)` | Initialize GPIO pin | +| `gpio_set_dir(pin, GPIO_IN)` | Set pin as input | +| `gpio_set_dir(pin, GPIO_OUT)` | Set pin as output | +| `gpio_pull_up(pin)` | Enable internal pull-up | +| `gpio_pull_down(pin)` | Enable internal pull-down | +| `gpio_disable_pulls(pin)` | Disable all pull resistors | +| `gpio_get(pin)` | Read pin state (0 or 1) | +| `gpio_put(pin, value)` | Set pin output (0 or 1) | + +### Key Assembly Instructions + +| Instruction | Description | +| ----------------------- | -------------------------------------------- | +| `movs rN, #imm` | Move immediate value to register | +| `ldrb rN, [rM, #off]` | Load byte from memory | +| `strb rN, [rM, #off]` | Store byte to memory | +| `adds rN, #imm` | Add immediate value to register | +| `eor rN, rM, #imm` | Exclusive OR (XOR) with immediate | +| `ubfx rN, rM, #lsb, #w` | Extract unsigned bit field | +| `mcrr p0, ...` | Move to coprocessor (GPIO control on RP2350) | +| `b LABEL` | Unconditional branch (jump) | + +### Memory Map Quick Reference + +| Address Range | Description | +| --------------------- | ------------------------------ | +| `0x10000000` | XIP Flash (code execution) | +| `0x20000000-200005xx` | SRAM (.data section) | +| `0x20082000` | Stack top (initial SP) | +| `0x40038000` | PADS_BANK0 (pad configuration) | +| `0xd0000000` | SIO (single-cycle I/O) | + +--- + +**Remember:** Static variables are your friends when you need to remember values across function calls. But they also make your program's behavior more complex to analyze - which is exactly why we practice reverse engineering! + +Happy hacking! + + + diff --git a/WEEK06/WEEK06.pdf b/WEEK06/WEEK06.pdf new file mode 100644 index 0000000..37fa79f Binary files /dev/null and b/WEEK06/WEEK06.pdf differ diff --git a/WEEK06/slides/WEEK06-IMG00.svg b/WEEK06/slides/WEEK06-IMG00.svg new file mode 100644 index 0000000..0feedec --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 06 + + +Static Variables in Embedded Systems: +Debugging and Hacking Static Variables +w/ GPIO Input Basics + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK06/slides/WEEK06-IMG01.svg b/WEEK06/slides/WEEK06-IMG01.svg new file mode 100644 index 0000000..45e7fee --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG01.svg @@ -0,0 +1,74 @@ + + + + + +Static vs Regular Vars +Persistence across loop iterations + + + +Regular (auto) + + +Loop 1: 42 -> 43 -> destroy + + +Loop 2: 42 -> 43 -> destroy + + +Loop 3: 42 -> 43 -> destroy + +Always prints: +42 + + + +Static + + +Loop 1: 42 -> 43 (kept!) + + +Loop 2: 43 -> 44 (kept!) + + +Loop 3: 44 -> 45 (kept!) + +Keeps incrementing: +42,43,44... + + + +Declaration Syntax + + +uint8_t reg = 42; +Recreated each iteration + + +static uint8_t s = 42; +Persists for program life + + + +uint8_t Overflow + +255 + 1 = +0 +(wraps around!) + +Binary: 11111111 + 1 = 100000000 (9 bits) +Only 8 bits kept: 00000000 = 0 + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG02.svg b/WEEK06/slides/WEEK06-IMG02.svg new file mode 100644 index 0000000..dca4829 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG02.svg @@ -0,0 +1,93 @@ + + + + + +Memory Layout +Where variables live in RAM + + + +RP2350 SRAM Map + + + +STACK (grows down) +Local/auto variables + +0x20082000 + + + +(free space) + + + +HEAP (grows up) +malloc / free + + + +.bss section +Uninit static/global + + + +.data section +Initialized static/global + +0x20000000 + +Static vars: .data (init) +Static vars: .bss (uninit) + + + +Variable Storage + +Type +Location + + + +Automatic +Stack + +Static +.data / .bss + +Global +.data / .bss + +Dynamic +Heap + +Static vars are NOT on heap! +Fixed location, set at compile +time. Lives entire program. +Example: +static_fav_num @ 0x200005A8 + + + +Key Insight + +Stack vars: +Created + destroyed +each function call + +Static vars: +Fixed RAM address +persist entire runtime + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG03.svg b/WEEK06/slides/WEEK06-IMG03.svg new file mode 100644 index 0000000..279854a --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG03.svg @@ -0,0 +1,93 @@ + + + + + +GPIO Input Basics +Reading buttons with the RP2350 + + + +OUTPUT (before) + + +Pico GPIO 16 +--> +LED + +We CONTROL the LED +gpio_put(pin, value) + + +INPUT (new!) + + +Pico GPIO 15 +<-- +BTN + +We READ button state +gpio_get(pin) + + + +Floating Input + +No connection = +RANDOM values! + +Read 1: HIGH +Read 2: LOW +Read 3: HIGH +Read 4: HIGH +??? + + + +Pull Resistors + +Type +Default +Pressed + + + +Pull-Up +HIGH(1) +LOW(0) + +Pull-Down +LOW(0) +HIGH(1) + +Pico 2 has internal pull resistors! + + + +GPIO Input Functions + +gpio_init(pin) +Initialize pin + +gpio_set_dir(pin, GPIO_IN) +Set as input + +gpio_pull_up(pin) +Enable pull-up + +gpio_get(pin) +Read state (0 or 1) + +No external resistor needed -- internal pull-up! + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG04.svg b/WEEK06/slides/WEEK06-IMG04.svg new file mode 100644 index 0000000..4ab0ae6 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG04.svg @@ -0,0 +1,99 @@ + + + + + +Pull-Up Resistor +Internal pull-up on GPIO 15 + + + +Circuit + +3.3V + + + +pull-up R + + + +GPIO 15 + + + + +BTN + + +GND + + + +Button Logic + +State +GPIO +LED + + + +Released +HIGH (1) +OFF + +Pressed +LOW (0) +ON + +Inverted! Pull-up = backwards + + + +Ternary Operator + + +gpio_put(LED, pressed?0:1); + +pressed=1 -> LED OFF (inverted!) + + + +Hardware Wiring + + +Pico 2 +GPIO 15 +GPIO 16 +GND +BOOTSEL + +--> +--> +--> + + +Components +Button (one leg) +LED + resistor +Button (other leg) +Hold to flash UF2 + + +Key Point +No external +resistor needed! +Internal pull-up +handles it all + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG05.svg b/WEEK06/slides/WEEK06-IMG05.svg new file mode 100644 index 0000000..b612ee1 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG05.svg @@ -0,0 +1,83 @@ + + + + + +Source Code +0x0014_static-variables.c + + + +main() + + +int main(void) { +stdio_init_all(); +// GPIO setup +gpio_init(15); +gpio_set_dir(15, GPIO_IN); +gpio_pull_up(15); +gpio_init(16); +gpio_set_dir(16, GPIO_OUT); +while (true) { +uint8_t reg = 42; +static uint8_t s = 42; +printf(... reg, s); +reg++; s++; +} +} + + + +GPIO Setup + +Pin 15: +Input +Pull-up enabled + +Pin 16: +Output +LED control + + + +Serial Output + + +reg: 42 +s: 42 +reg: 42 +s: 43 + +reg always 42, s grows + + + +Button Logic + +pressed = gpio_get(15); + + + +Key Behaviors + + +reg: always 42 + + +s: 42,43,44... + + +wraps at 255->0 + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG06.svg b/WEEK06/slides/WEEK06-IMG06.svg new file mode 100644 index 0000000..a0919c3 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG06.svg @@ -0,0 +1,65 @@ + + + + + +Compiler Optimizations +What the compiler does to your code + + + +Optimization 1: Dead Code Removal + + +Your code: +uint8_t reg = 42; +reg++; +// No lasting effect! + + +Compiler output: +movs r1, #42 +// reg++ is GONE +// Uses constant 42 directly + + + +Optimization 2: Function Inlining + + +Your code: +gpio_pull_up(15); +// Simple wrapper func + + +Compiler output: +gpio_set_pulls(15,1,0); +// Inlined to real func + + + +Optimization 3: Scheduling + +Compiler reorders instructions +to avoid pipeline stalls: + + +Load SIO base + + +Increment s + + +Read GPIO + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG07.svg b/WEEK06/slides/WEEK06-IMG07.svg new file mode 100644 index 0000000..c359080 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG07.svg @@ -0,0 +1,90 @@ + + + + + +Assembly Analysis +Key instructions in main() loop + + + +Loop Body (0x10000264) + + +movs r1, #0x2a +; reg=42 +bl __wrap_printf +; print reg +ldrb r1, [r4] +; load static +bl __wrap_printf +; print s +mov.w r1, #0xd0000000 +; SIO base +ldrb r3, [r4] +; reload s +adds r3, #1 +; s++ +strb r3, [r4] +; store s +ldr r3, [r1, #4] +; read GPIO +ubfx r3, r3, #15, #1 +; bit 15 +eor.w r3, r3, #1 +; invert +mcrr 0, 4, r2, r3, cr0 +; GPIO out +b.n 0x10000264 +; loop + + + +Key Registers + +r1: +printf arg +r3: +temp / static +r4: +0x200005a8 +(static var addr) +r2: +LED pin (16) + + + +Key Patterns + +ldrb/adds/strb +Load-increment-store +(static var update) + +ubfx #15, #1 +Extract GPIO bit 15 + +eor.w #1 +Inverts (? 0 : 1) + + + +Infinite Loop + + +b.n 0x10000264 +; while(true) + +No pop/bx lr +main() never returns + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG08.svg b/WEEK06/slides/WEEK06-IMG08.svg new file mode 100644 index 0000000..702d322 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG08.svg @@ -0,0 +1,75 @@ + + + + + +GDB: Static Variable +Finding static_fav_num in RAM + + + +Literal Pool Lookup + + +ldr r4, [pc, #44] +@ 0x10000290 + +Examine literal pool: + +x/1wx 0x10000290 = 0x200005A8 + +r4 now holds the +RAM address of +static_fav_num! + + + +Read Value + + +x/1db 0x200005a8 = 42 + +After one loop iteration: + +x/1db 0x200005a8 = 43 + +It incremented! Persists in RAM. + + + +Disasm Gotcha + +x/i 0x10000290 shows: + + +lsls r0, r5, #22 + +GDB decodes DATA as code! +Bytes A8 05 00 20 = 0x200005A8 +Use x/wx not x/i for data + + + +GPIO Input Register + +Read button state in GDB: + + +p/x (*(uint*)0xd0000004 >> 15) & 1 + +Returns 1: +not pressed (pull-up) +Returns 0: +button pressed + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG09.svg b/WEEK06/slides/WEEK06-IMG09.svg new file mode 100644 index 0000000..c603290 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG09.svg @@ -0,0 +1,63 @@ + + + + + +Hacking the Binary +Two patches with a hex editor + + + +File Offset Formula +offset = address - 0x10000000 +Example: 0x10000264 -> 0x264 + + + +Hack 1: Change 42 to 43 + +Target: movs r1, #0x2a +at address 0x10000264 (offset 0x264) + + +Before: 2A 21 +movs r1, #42 + + +After: 2B 21 +movs r1, #43 + +Thumb encoding: imm8 byte first, opcode 0x21 second + + + +Hack 2: Invert Button Logic + +Target: eor.w r3, r3, #1 +at address 0x10000286 (offset 0x286) + + +Before: 83 F0 01 03 + + +After: 83 F0 00 03 + +Byte at offset 0x288: +01 +-> +00 + +XOR with 0 = no invert +LED now ON by default, OFF when pressed + \ No newline at end of file diff --git a/WEEK06/slides/WEEK06-IMG10.svg b/WEEK06/slides/WEEK06-IMG10.svg new file mode 100644 index 0000000..f88fa45 --- /dev/null +++ b/WEEK06/slides/WEEK06-IMG10.svg @@ -0,0 +1,112 @@ + + + + + +Static Vars & GPIO Input +Static variables, GPIO input, hacking + + + +Static vs Auto + +Aspect +Auto +Static + + + +Where +Stack +.data + +Life +Scope +Forever + +Init +Every +Once + +Keeps? +No +Yes + +Optimized? +Often +In RAM + +Compiler may remove auto vars + + + +GPIO Input Setup + +1. +gpio_init(pin) + +2. +gpio_set_dir(pin, GPIO_IN) + +3. +gpio_pull_up(pin) + +4. +gpio_get(pin) + +Pull-up: released=HIGH +pressed=LOW (inverted!) +Internal R, no hardware + + + +Key Instructions + +ubfx r3,r3,#15,#1 +Extract single GPIO bit + +eor.w r3,r3,#1 +XOR to invert logic + +b.n 0x10000264 + + + +Hacking Workflow + +1. +Analyze in GDB + +2. +Calculate offset + +3. +Patch .bin in HxD + +4. +uf2conv.py + flash + + + +Takeaways + + +42 -> 43 (1 byte) + + +XOR 1->0 (invert) + + +offset = addr - base + \ No newline at end of file diff --git a/WEEK07/0x0014a_cb/0x0014a_cb.bin b/WEEK07/0x0014a_cb/0x0014a_cb.bin new file mode 100755 index 0000000..7b8c655 Binary files /dev/null and b/WEEK07/0x0014a_cb/0x0014a_cb.bin differ diff --git a/WEEK07/0x0014a_cb/0x0014a_cb.uf2 b/WEEK07/0x0014a_cb/0x0014a_cb.uf2 new file mode 100644 index 0000000..47ba2e4 Binary files /dev/null and b/WEEK07/0x0014a_cb/0x0014a_cb.uf2 differ diff --git a/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.md b/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.md new file mode 100644 index 0000000..4e31fd1 --- /dev/null +++ b/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.md @@ -0,0 +1,152 @@ +# Operation Zero Hour: Classified Intelligence Briefing + +``` ++-----------------------------------------------------------------+ +| TOP SECRET // NOFORN | ++-----------------------------------------------------------------+ +| | +|OPERATION ZERO HOUR | +| | +|CLASSIFIED BRIEFING: LIVE CHALLENGE 0x02 | +| | +|NATIONAL SECURITY AGENCY / GMU RHET | ++-----------------------------------------------------------------+ +``` + +## 1. The Advice + +INT. NSA EXPLOITATION CELL. 05:45. + +The air in the secure chamber is cold and smells of machine oil. Secured in an +aluminum shock-mount cradle on the bench sits the recovered forward guidance and +fuze assembly of an adversary loitering munition. + +On the front plate of the Electronic Safe-and-Arm (ESA) housing, an unblinking +red diode burns: `GP16` high. Beside it, the antenna of a REYAX RYLR998 LoRa +transceiver extends from the chassis, connected to `UART1` on `GP8` and `GP9`. +A thin jumper loops from `GP15` up to the `3V3` rail. + +The Director walks in, carrying a lukewarm mug of black coffee. He stares at the +red diode. + +**DIRECTOR:** Is the fuze live? + +**ANALYST:** Live and armed. The drone suffered an engine flameout and pancaked +into soft marshland. The impact deceleration was insufficient to crush the piezo +striker, but the warhead's electronic arming logic is fully engaged. + +**DIRECTOR:** How volatile is it? + +**ANALYST:** One mistake on the radio link and the secondary explosive train fires. + +**DIRECTOR:** Did you run the binary through Buddy? + +**ANALYST:** I fed Buddy the stripped flash dump four minutes ago. + +She pivots her high-resolution workstation monitor toward him. + +``` ++-----------------------------------------------------------------+ +| BUDDY // CLASSIFIED EXPLOITATION ASSIST // CONF: 0.99 | ++-----------------------------------------------------------------+ +| ACTION : Transmit generic abort frame over LoRa (915 MHz). | +| MECHANISM : uart1 packet ingestion on GP8/GP9 detected. | +| PREDICTION : RF abort packet clears latch and engages GP17. | +| CONFIDENCE : 0.99 | ++-----------------------------------------------------------------+ +``` + +**DIRECTOR:** 0.99 confidence. Transmit the abort frame and render it safe. + +**ANALYST:** If an operator transmits an unverified packet right now, this building +ceases to exist. + +**DIRECTOR:** Buddy says 0.99. + +**ANALYST:** Buddy saw the call to `lora_poll_packet`. Buddy never looked at SRAM. +Buddy never looks at the state machine. + +## 2. What Buddy Is + +Buddy is not a person. It is a model. It has parsed more disassembled machine +code than any engineer on earth, and it speaks with total, unhesitating certainty. + +That certainty is lethal when dealing with live ordnance. + +Buddy scanned thirty-two kilobytes of raw ARM Thumb-2 instructions in under four +seconds. It spotted the UART1 packet parser on GPIO 8 and 9, observed that it +interacted with the arming logic, and declared victory. + +What Buddy failed to consider is that real adversary weapons are built by +engineers who anticipate capture and signal spoofing. They know an allied signals +intelligence unit will attempt to broadcast RF command abort frames. + +Inside a real fuze, a radio receiver rarely connects to a simple on/off latch. +Adversary firmware uses state machines, hidden validation logic, and anti-tamper +traps. Transmitting blindly over the air before verifying what happens to that +packet inside silicon is how bomb disposal teams get killed. + +Buddy saw the radio receiver. Buddy did not verify the ground truth. + +## 3. The Operation + +At 03:15, radar pickets tracked an adversary one-way loitering attack drone +descending over contested terrain. Technical Intelligence operators recovered the +airframe before adversary recovery forces could zeroize the avionics. + +The brain of the Electronic Safe-and-Arm assembly is a bare-metal RP2350 (ARM +Cortex-M33). There are no debug symbols. There is no operating system. There is no +SVD file to label the registers. All you have is `0x0014a_cb.bin` mapped into Flash +at `0x10000000`, and the physical breadboard hardware in front of you. + +* **Pin 11 (`GP8`)**: LoRa UART1 TX (to RYLR998 RXD). +* **Pin 12 (`GP9`)**: LoRa UART1 RX (from RYLR998 TXD). +* **Pin 20 (`GP15`)**: Anti-tamper sense loop (jumpered to `3V3`). +* **Pin 21 (`GP16`)**: Red LED (`WARHEAD ARMED // SENSORS LIVE`). +* **Pin 22 (`GP17`)**: Green LED (`WARHEAD DISARMED // SYSTEM SAFE`). +* **Pin 36 (`3V3`)**: REYAX RYLR998 VDD rail and `GP15` pull-up source. +* **Pin 38 (`GND`)**: Ground reference. + +Inside this image there is an RF packet ingestion parser, a rolling XOR cipher, +an anti-tamper latch, and a penalty counter. Whatever mechanism actually disarms +the warhead is buried in the stripped ARM Thumb-2 machine code. + +## 4. The Mandate + +The Director sets his mug down and looks at the red diode illuminating the bench +in sharp crimson. + +**DIRECTOR:** Prove Buddy right, or prove it wrong. + +**ANALYST:** I need thirty minutes with GDB and Ghidra. + +**DIRECTOR:** You have twenty. Trace the packet handler. Map the state machine. +Do not transmit a single byte over LoRa until you know with 100% certainty what +that firmware will do. + +The orders are clear: + +1. **Investigate the RF Receiver Logic**: Disassemble the firmware and trace what + happens when data arrives on UART1 (`GP8`/`GP9`). +2. **Recover the Disarm Token**: Reverse the rolling XOR cipher routine in Flash + and decrypt the authentic abort passcode. +3. **Respect the Traps**: Determine what the fuze does after repeated invalid + frames, and what happens if the `GP15` anti-tamper loop is broken. +4. **Neutralize the Munition**: Execute a verified exploit—either by discovering + the valid authorization mechanism, mutating the state machine in SRAM via GDB, + or patching the binary in Flash. +5. **Verify the Hardware**: Transition the live breadboard from the Red LED on + `GP16` to the solid Green LED on `GP17` on physical silicon. + +A machine's 0.99 guess does not risk a detonation. + +## 5. The Challenge + +You have the image. You have the board. You have the tools and the time Buddy +did not need. + +Buddy has given you its answer, and it is confident. + +Is it that simple? + +Go find out. diff --git a/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.pdf b/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.pdf new file mode 100644 index 0000000..98331d3 Binary files /dev/null and b/WEEK07/0x0014a_cb/CLASSIFIED-BRIEF-0x02.pdf differ diff --git a/WEEK07/0x0014a_cb/scripts/lora_console.py b/WEEK07/0x0014a_cb/scripts/lora_console.py new file mode 100755 index 0000000..24310f9 --- /dev/null +++ b/WEEK07/0x0014a_cb/scripts/lora_console.py @@ -0,0 +1,195 @@ +#!/usr/bin/env python3 +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: lora_console.py +# Desc: Interactive REYAX RYLR998 terminal for the FT232RL ground station. +# Created: 2026 + +""" +Interactive LoRa terminal for the REYAX RYLR998 ground station. + +Sends AT commands as complete bursts terminated with a carriage return and line +feed to avoid the RYLR998 inter-character timeout error, and prints incoming +packets from the airborne node as they arrive. +""" + +import argparse +import sys +import threading +import time + +try: + import serial +except ImportError: + serial = None + + +def _reader_thread(ser: "serial.Serial") -> None: + """ + Continuously read and display incoming packets from the radio. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + while True: + try: + line = ser.readline().decode("utf-8", errors="ignore").strip() + if line: + print(f"\n[LORA RX] {line}\n> ", end="", flush=True) + except Exception: + break + + +def _parse_args() -> argparse.Namespace: + """ + Parse command line arguments for the LoRa console. + + Parameters + ---------- + None + + Returns + ------- + argparse.Namespace + Parsed arguments with the serial port and baud rate. + """ + parser = argparse.ArgumentParser(description="REYAX RYLR998 console") + parser.add_argument("--port", default="/dev/cu.usbserial-A50285BI") + parser.add_argument("--baud", type=int, default=115200) + return parser.parse_args() + + +def _open_radio(port: str, baud: int) -> "serial.Serial": + """ + Open serial connection to the REYAX transceiver. + + Parameters + ---------- + port : str + Serial device path or COM port identifier. + baud : int + Baud rate for serial communication. + + Returns + ------- + serial.Serial + Open serial interface to the radio. + """ + print(f"[*] Opening REYAX RYLR998 on {port} @ {baud}...") + try: + return serial.Serial(port, baud, timeout=0.5) + except Exception as e: + sys.exit(f"[-] Failed to open {port}: {e}") + + +def _start_radio(ser: "serial.Serial") -> None: + """ + Start listener thread and send initial AT ping. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + thread = threading.Thread(target=_reader_thread, args=(ser,), daemon=True) + thread.start() + time.sleep(0.1) + ser.write(b"AT\r\n") + + +def _print_banner() -> None: + """ + Print console connection info and operator command instructions. + + Parameters + ---------- + None + + Returns + ------- + None + """ + print("[+] Connected. Type AT commands (e.g. AT, AT+BAND?, AT+NETWORKID?).") + print("[+] Incoming airborne packets print as [LORA RX] +RCV=...") + print("[+] Press Ctrl-C or Ctrl-D to exit.\n") + + +def _console_loop(ser: "serial.Serial") -> None: + """ + Forward operator input lines to the serial transceiver. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + try: + while True: + cmd = input("> ").strip() + if cmd: + ser.write(cmd.encode("utf-8") + b"\r\n") + except (KeyboardInterrupt, EOFError): + print("\n[*] Exiting LoRa console.") + ser.close() + + +def main() -> None: + """ + Open the ground station radio and forward operator input. + + Parameters + ---------- + None + + Returns + ------- + None + """ + if serial is None: + sys.exit("pyserial required: pip install pyserial") + args = _parse_args() + ser = _open_radio(args.port, args.baud) + _start_radio(ser) + _print_banner() + _console_loop(ser) + + +if __name__ == "__main__": + main() diff --git a/WEEK07/0x0017_constants/.gitignore b/WEEK07/0x0017_constants/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK07/0x0017_constants/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK07/0x0017_constants/.vscode/c_cpp_properties.json b/WEEK07/0x0017_constants/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK07/0x0017_constants/.vscode/cmake-kits.json b/WEEK07/0x0017_constants/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK07/0x0017_constants/.vscode/extensions.json b/WEEK07/0x0017_constants/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK07/0x0017_constants/.vscode/launch.json b/WEEK07/0x0017_constants/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK07/0x0017_constants/.vscode/settings.json b/WEEK07/0x0017_constants/.vscode/settings.json new file mode 100644 index 0000000..8aecbe6 --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/settings.json @@ -0,0 +1,43 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja", + "files.associations": { + "stdlib.h": "c" + } +} diff --git a/WEEK07/0x0017_constants/.vscode/tasks.json b/WEEK07/0x0017_constants/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK07/0x0017_constants/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK07/0x0017_constants/0x0017_constants.c b/WEEK07/0x0017_constants/0x0017_constants.c new file mode 100644 index 0000000..b762ca1 --- /dev/null +++ b/WEEK07/0x0017_constants/0x0017_constants.c @@ -0,0 +1,35 @@ +#include +#include +#include "pico/stdlib.h" +#include "hardware/i2c.h" +#include "lcd_1602.h" + +#define FAV_NUM 42 + +#define I2C_PORT i2c1 +#define I2C_SDA_PIN 2 +#define I2C_SCL_PIN 3 + +const int OTHER_FAV_NUM = 1337; + +int main(void) { + stdio_init_all(); + + i2c_init(I2C_PORT, 100000); + gpio_set_function(I2C_SDA_PIN, GPIO_FUNC_I2C); + gpio_set_function(I2C_SCL_PIN, GPIO_FUNC_I2C); + gpio_pull_up(I2C_SDA_PIN); + gpio_pull_up(I2C_SCL_PIN); + + lcd_i2c_init(I2C_PORT, 0x27, 4, 0x08); + + lcd_set_cursor(0, 0); + lcd_puts("Reverse"); + lcd_set_cursor(1, 0); + lcd_puts("Engineering"); + + while (true) { + printf("FAV_NUM: %d\r\n", FAV_NUM); + printf("OTHER_FAV_NUM: %d\r\n", OTHER_FAV_NUM); + } +} diff --git a/WEEK07/0x0017_constants/CMakeLists.txt b/WEEK07/0x0017_constants/CMakeLists.txt new file mode 100644 index 0000000..4c75aa3 --- /dev/null +++ b/WEEK07/0x0017_constants/CMakeLists.txt @@ -0,0 +1,59 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0017_constants C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0017_constants 0x0017_constants.c lcd_1602.c) + +pico_set_program_name(0x0017_constants "0x0017_constants") +pico_set_program_version(0x0017_constants "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0017_constants 1) +pico_enable_stdio_usb(0x0017_constants 0) + +# Add the standard library to the build +target_link_libraries(0x0017_constants + pico_stdlib + hardware_i2c + hardware_gpio) + +# Add the standard include files to the build +target_include_directories(0x0017_constants PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0017_constants) + diff --git a/WEEK07/0x0017_constants/build/0x0017_constants.bin b/WEEK07/0x0017_constants/build/0x0017_constants.bin new file mode 100755 index 0000000..493cad7 Binary files /dev/null and b/WEEK07/0x0017_constants/build/0x0017_constants.bin differ diff --git a/WEEK07/0x0017_constants/build/0x0017_constants.dis b/WEEK07/0x0017_constants/build/0x0017_constants.dis new file mode 100644 index 0000000..680fb7c --- /dev/null +++ b/WEEK07/0x0017_constants/build/0x0017_constants.dis @@ -0,0 +1,6734 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0017_constants/build/0x0017_constants.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00003ee4 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001d8 10003ee8 10003ee8 00004ee8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100040c0 100040c0 000050c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 100040c8 100040c8 000050c8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00007000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 0000663c 2**0 + CONTENTS + 6 .data 00000534 20000110 100040f4 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 20000644 20000644 0000663c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 20000644 20000644 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 0000022c 20000648 10004628 00006648 2**3 + ALLOC + 10 .heap 00000800 20000874 10004628 00006874 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 0000663c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 0000663c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00007000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10004628 10004628 00006628 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 0000663c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00006670 2**0 + CONTENTS, READONLY + 17 .debug_info 0002480f 00000000 00000000 000066b5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005dfd 00000000 00000000 0002aec4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 00011916 00000000 00000000 00030cc1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000cb8 00000000 00000000 000425d8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 000035e1 00000000 00000000 00043290 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00017c6d 00000000 00000000 00046871 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005d19 00000000 00000000 0005e4de 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00002230 00000000 00000000 000641f8 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002b7 00000000 00000000 00066428 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0017_constants/build/0x0017_constants.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 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.word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100040c8 .word 0x100040c8 +1000012c: 100040f4 .word 0x100040f4 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 000044f0 .word 0x000044f0 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100040f4 .word 0x100040f4 +100001a4: 20000110 .word 0x20000110 +100001a8: 20000644 .word 0x20000644 +100001ac: 10004628 .word 0x10004628 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10004628 .word 0x10004628 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 20000644 .word 0x20000644 +100001d4: 20000874 .word 0x20000874 +100001d8: 100035ad .word 0x100035ad +100001dc: 10000235 .word 0x10000235 +100001e0: 100035a5 .word 0x100035a5 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 20000644 .word 0x20000644 +10000208: 20000644 .word 0x20000644 +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 2000082c .word 0x2000082c +10000230: 10003ee4 .word 0x10003ee4 + +10000234
: +10000234: b508 push {r3, lr} +10000236: f003 fae1 bl 100037fc +1000023a: 491a ldr r1, [pc, #104] @ (100002a4 ) +1000023c: 481a ldr r0, [pc, #104] @ (100002a8 ) +1000023e: f003 fd4d bl 10003cdc +10000242: 2103 movs r1, #3 +10000244: 2002 movs r0, #2 +10000246: f000 fb53 bl 100008f0 +1000024a: 2103 movs r1, #3 +1000024c: 4608 mov r0, r1 +1000024e: f000 fb4f bl 100008f0 +10000252: 2200 movs r2, #0 +10000254: 2101 movs r1, #1 +10000256: 2002 movs r0, #2 +10000258: f000 fb68 bl 1000092c +1000025c: 2200 movs r2, #0 +1000025e: 2101 movs r1, #1 +10000260: 2003 movs r0, #3 +10000262: f000 fb63 bl 1000092c +10000266: 2308 movs r3, #8 +10000268: 2204 movs r2, #4 +1000026a: 2127 movs r1, #39 @ 0x27 +1000026c: 480e ldr r0, [pc, #56] @ (100002a8 ) +1000026e: f000 f825 bl 100002bc +10000272: 2100 movs r1, #0 +10000274: 4608 mov r0, r1 +10000276: f000 fa3d bl 100006f4 +1000027a: 480c ldr r0, [pc, #48] @ (100002ac ) +1000027c: f000 fab8 bl 100007f0 +10000280: 2001 movs r0, #1 +10000282: 2100 movs r1, #0 +10000284: f000 fa36 bl 100006f4 +10000288: 4809 ldr r0, [pc, #36] @ (100002b0 ) +1000028a: f000 fab1 bl 100007f0 +1000028e: 212a movs r1, #42 @ 0x2a +10000290: 4808 ldr r0, [pc, #32] @ (100002b4 ) +10000292: f003 fb7b bl 1000398c <__wrap_printf> +10000296: f240 5139 movw r1, #1337 @ 0x539 +1000029a: 4807 ldr r0, [pc, #28] @ (100002b8 ) +1000029c: f003 fb76 bl 1000398c <__wrap_printf> +100002a0: e7f5 b.n 1000028e +100002a2: bf00 nop +100002a4: 000186a0 .word 0x000186a0 +100002a8: 2000062c .word 0x2000062c +100002ac: 10003ee8 .word 0x10003ee8 +100002b0: 10003ef0 .word 0x10003ef0 +100002b4: 10003efc .word 0x10003efc +100002b8: 10003f0c .word 0x10003f0c + +100002bc : +100002bc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100002c0: 2703 movs r7, #3 +100002c2: 4097 lsls r7, r2 +100002c4: f8df 82f4 ldr.w r8, [pc, #756] @ 100005bc +100002c8: b2ff uxtb r7, r7 +100002ca: 4cb9 ldr r4, [pc, #740] @ (100005b0 ) +100002cc: 4db9 ldr r5, [pc, #740] @ (100005b4 ) +100002ce: 4eba ldr r6, [pc, #744] @ (100005b8 ) +100002d0: 431f orrs r7, r3 +100002d2: b084 sub sp, #16 +100002d4: f8c8 2000 str.w r2, [r8] +100002d8: f047 0204 orr.w r2, r7, #4 +100002dc: 7029 strb r1, [r5, #0] +100002de: 7033 strb r3, [r6, #0] +100002e0: 6020 str r0, [r4, #0] +100002e2: f88d 200f strb.w r2, [sp, #15] +100002e6: b130 cbz r0, 100002f6 +100002e8: 2300 movs r3, #0 +100002ea: f10d 020f add.w r2, sp, #15 +100002ee: 9300 str r3, [sp, #0] +100002f0: 2301 movs r3, #1 +100002f2: f003 fd19 bl 10003d28 +100002f6: 2001 movs r0, #1 +100002f8: 2100 movs r1, #0 +100002fa: f001 f835 bl 10001368 +100002fe: 6820 ldr r0, [r4, #0] +10000300: f027 0704 bic.w r7, r7, #4 +10000304: f88d 700f strb.w r7, [sp, #15] +10000308: b138 cbz r0, 1000031a +1000030a: 2300 movs r3, #0 +1000030c: 9300 str r3, [sp, #0] +1000030e: 7829 ldrb r1, [r5, #0] +10000310: 2301 movs r3, #1 +10000312: f10d 020f add.w r2, sp, #15 +10000316: f003 fd07 bl 10003d28 +1000031a: 2703 movs r7, #3 +1000031c: 2032 movs r0, #50 @ 0x32 +1000031e: 2100 movs r1, #0 +10000320: f001 f822 bl 10001368 +10000324: 2005 movs r0, #5 +10000326: f001 f88b bl 10001440 +1000032a: f8d8 3000 ldr.w r3, [r8] +1000032e: 6820 ldr r0, [r4, #0] +10000330: 409f lsls r7, r3 +10000332: 7833 ldrb r3, [r6, #0] +10000334: b2ff uxtb r7, r7 +10000336: 431f orrs r7, r3 +10000338: f047 0304 orr.w r3, r7, #4 +1000033c: f88d 300f strb.w r3, [sp, #15] +10000340: b138 cbz r0, 10000352 +10000342: 2300 movs r3, #0 +10000344: 9300 str r3, [sp, #0] +10000346: 7829 ldrb r1, [r5, #0] +10000348: 2301 movs r3, #1 +1000034a: f10d 020f add.w r2, sp, #15 +1000034e: f003 fceb bl 10003d28 +10000352: 2001 movs r0, #1 +10000354: 2100 movs r1, #0 +10000356: f001 f807 bl 10001368 +1000035a: 6820 ldr r0, [r4, #0] +1000035c: f027 0704 bic.w r7, r7, #4 +10000360: f88d 700f strb.w r7, [sp, #15] +10000364: b138 cbz r0, 10000376 +10000366: 2300 movs r3, #0 +10000368: 9300 str r3, [sp, #0] +1000036a: 7829 ldrb r1, [r5, #0] +1000036c: 2301 movs r3, #1 +1000036e: f10d 020f add.w r2, sp, #15 +10000372: f003 fcd9 bl 10003d28 +10000376: 2703 movs r7, #3 +10000378: 2032 movs r0, #50 @ 0x32 +1000037a: 2100 movs r1, #0 +1000037c: f000 fff4 bl 10001368 +10000380: 2096 movs r0, #150 @ 0x96 +10000382: 2100 movs r1, #0 +10000384: f000 fff0 bl 10001368 +10000388: f8d8 3000 ldr.w r3, [r8] +1000038c: 6820 ldr r0, [r4, #0] +1000038e: 409f lsls r7, r3 +10000390: 7833 ldrb r3, [r6, #0] +10000392: b2ff uxtb r7, r7 +10000394: 431f orrs r7, r3 +10000396: f047 0304 orr.w r3, r7, #4 +1000039a: f88d 300f strb.w r3, [sp, #15] +1000039e: b138 cbz r0, 100003b0 +100003a0: 2300 movs r3, #0 +100003a2: 9300 str r3, [sp, #0] +100003a4: 7829 ldrb r1, [r5, #0] +100003a6: 2301 movs r3, #1 +100003a8: f10d 020f add.w r2, sp, #15 +100003ac: f003 fcbc bl 10003d28 +100003b0: 2001 movs r0, #1 +100003b2: 2100 movs r1, #0 +100003b4: f000 ffd8 bl 10001368 +100003b8: 6820 ldr r0, [r4, #0] +100003ba: f027 0704 bic.w r7, r7, #4 +100003be: f88d 700f strb.w r7, [sp, #15] +100003c2: b138 cbz r0, 100003d4 +100003c4: 2300 movs r3, #0 +100003c6: 9300 str r3, [sp, #0] +100003c8: 7829 ldrb r1, [r5, #0] +100003ca: 2301 movs r3, #1 +100003cc: f10d 020f add.w r2, sp, #15 +100003d0: f003 fcaa bl 10003d28 +100003d4: 2702 movs r7, #2 +100003d6: 2032 movs r0, #50 @ 0x32 +100003d8: 2100 movs r1, #0 +100003da: f000 ffc5 bl 10001368 +100003de: 2096 movs r0, #150 @ 0x96 +100003e0: 2100 movs r1, #0 +100003e2: f000 ffc1 bl 10001368 +100003e6: f8d8 3000 ldr.w r3, [r8] +100003ea: 6820 ldr r0, [r4, #0] +100003ec: 409f lsls r7, r3 +100003ee: 7833 ldrb r3, [r6, #0] +100003f0: b2ff uxtb r7, r7 +100003f2: 431f orrs r7, r3 +100003f4: f047 0304 orr.w r3, r7, #4 +100003f8: f88d 300f strb.w r3, [sp, #15] +100003fc: b138 cbz r0, 1000040e +100003fe: 2300 movs r3, #0 +10000400: 9300 str r3, [sp, #0] +10000402: 7829 ldrb r1, [r5, #0] +10000404: 2301 movs r3, #1 +10000406: f10d 020f add.w r2, sp, #15 +1000040a: f003 fc8d bl 10003d28 +1000040e: 2001 movs r0, #1 +10000410: 2100 movs r1, #0 +10000412: f000 ffa9 bl 10001368 +10000416: 6820 ldr r0, [r4, #0] +10000418: f027 0704 bic.w r7, r7, #4 +1000041c: f88d 700f strb.w r7, [sp, #15] +10000420: b138 cbz r0, 10000432 +10000422: 2300 movs r3, #0 +10000424: 9300 str r3, [sp, #0] +10000426: 7829 ldrb r1, [r5, #0] +10000428: 2301 movs r3, #1 +1000042a: f10d 020f add.w r2, sp, #15 +1000042e: f003 fc7b bl 10003d28 +10000432: 2702 movs r7, #2 +10000434: 2032 movs r0, #50 @ 0x32 +10000436: 2100 movs r1, #0 +10000438: f000 ff96 bl 10001368 +1000043c: 2096 movs r0, #150 @ 0x96 +1000043e: 2100 movs r1, #0 +10000440: f000 ff92 bl 10001368 +10000444: f8d8 3000 ldr.w r3, [r8] +10000448: 6820 ldr r0, [r4, #0] +1000044a: 409f lsls r7, r3 +1000044c: 7833 ldrb r3, [r6, #0] +1000044e: b2ff uxtb r7, r7 +10000450: 431f orrs r7, r3 +10000452: f047 0304 orr.w r3, r7, #4 +10000456: f88d 300f strb.w r3, [sp, #15] +1000045a: b138 cbz r0, 1000046c +1000045c: 2300 movs r3, #0 +1000045e: 9300 str r3, [sp, #0] +10000460: 7829 ldrb r1, [r5, #0] +10000462: 2301 movs r3, #1 +10000464: f10d 020f add.w r2, sp, #15 +10000468: f003 fc5e bl 10003d28 +1000046c: 2001 movs r0, #1 +1000046e: 2100 movs r1, #0 +10000470: f000 ff7a bl 10001368 +10000474: 6820 ldr r0, [r4, #0] +10000476: f027 0704 bic.w r7, r7, #4 +1000047a: f88d 700f strb.w r7, [sp, #15] +1000047e: b138 cbz r0, 10000490 +10000480: 2300 movs r3, #0 +10000482: 9300 str r3, [sp, #0] +10000484: 7829 ldrb r1, [r5, #0] +10000486: 2301 movs r3, #1 +10000488: f10d 020f add.w r2, sp, #15 +1000048c: f003 fc4c bl 10003d28 +10000490: 2708 movs r7, #8 +10000492: 2032 movs r0, #50 @ 0x32 +10000494: 2100 movs r1, #0 +10000496: f000 ff67 bl 10001368 +1000049a: f8d8 3000 ldr.w r3, [r8] +1000049e: 6820 ldr r0, [r4, #0] +100004a0: 409f lsls r7, r3 +100004a2: 7833 ldrb r3, [r6, #0] +100004a4: b2ff uxtb r7, r7 +100004a6: 431f orrs r7, r3 +100004a8: f047 0304 orr.w r3, r7, #4 +100004ac: f88d 300f strb.w r3, [sp, #15] +100004b0: b138 cbz r0, 100004c2 +100004b2: 2300 movs r3, #0 +100004b4: 9300 str r3, [sp, #0] +100004b6: 7829 ldrb r1, [r5, #0] +100004b8: 2301 movs r3, #1 +100004ba: f10d 020f add.w r2, sp, #15 +100004be: f003 fc33 bl 10003d28 +100004c2: 2001 movs r0, #1 +100004c4: 2100 movs r1, #0 +100004c6: f000 ff4f bl 10001368 +100004ca: 6820 ldr r0, [r4, #0] +100004cc: f027 0704 bic.w r7, r7, #4 +100004d0: f88d 700f strb.w r7, [sp, #15] +100004d4: b138 cbz r0, 100004e6 +100004d6: 2300 movs r3, #0 +100004d8: 9300 str r3, [sp, #0] +100004da: 7829 ldrb r1, [r5, #0] +100004dc: 2301 movs r3, #1 +100004de: f10d 020f add.w r2, sp, #15 +100004e2: f003 fc21 bl 10003d28 +100004e6: 2032 movs r0, #50 @ 0x32 +100004e8: 2100 movs r1, #0 +100004ea: f000 ff3d bl 10001368 +100004ee: 7837 ldrb r7, [r6, #0] +100004f0: 6820 ldr r0, [r4, #0] +100004f2: f047 0304 orr.w r3, r7, #4 +100004f6: f88d 300f strb.w r3, [sp, #15] +100004fa: b138 cbz r0, 1000050c +100004fc: 2300 movs r3, #0 +100004fe: 9300 str r3, [sp, #0] +10000500: 7829 ldrb r1, [r5, #0] +10000502: 2301 movs r3, #1 +10000504: f10d 020f add.w r2, sp, #15 +10000508: f003 fc0e bl 10003d28 +1000050c: 2001 movs r0, #1 +1000050e: 2100 movs r1, #0 +10000510: f000 ff2a bl 10001368 +10000514: 6820 ldr r0, [r4, #0] +10000516: f027 0704 bic.w r7, r7, #4 +1000051a: f88d 700f strb.w r7, [sp, #15] +1000051e: b138 cbz r0, 10000530 +10000520: 2300 movs r3, #0 +10000522: 9300 str r3, [sp, #0] +10000524: 7829 ldrb r1, [r5, #0] +10000526: 2301 movs r3, #1 +10000528: f10d 020f add.w r2, sp, #15 +1000052c: f003 fbfc bl 10003d28 +10000530: 270c movs r7, #12 +10000532: 2032 movs r0, #50 @ 0x32 +10000534: 2100 movs r1, #0 +10000536: f000 ff17 bl 10001368 +1000053a: f8d8 3000 ldr.w r3, [r8] +1000053e: 6820 ldr r0, [r4, #0] +10000540: 409f lsls r7, r3 +10000542: 7833 ldrb r3, [r6, #0] +10000544: b2ff uxtb r7, r7 +10000546: 431f orrs r7, r3 +10000548: f047 0304 orr.w r3, r7, #4 +1000054c: f88d 300f strb.w r3, [sp, #15] +10000550: b138 cbz r0, 10000562 +10000552: 2300 movs r3, #0 +10000554: 9300 str r3, [sp, #0] +10000556: 7829 ldrb r1, [r5, #0] +10000558: 2301 movs r3, #1 +1000055a: f10d 020f add.w r2, sp, #15 +1000055e: f003 fbe3 bl 10003d28 +10000562: 2001 movs r0, #1 +10000564: 2100 movs r1, #0 +10000566: f000 feff bl 10001368 +1000056a: 6820 ldr r0, [r4, #0] +1000056c: f027 0704 bic.w r7, r7, #4 +10000570: f88d 700f strb.w r7, [sp, #15] +10000574: b138 cbz r0, 10000586 +10000576: 2300 movs r3, #0 +10000578: 9300 str r3, [sp, #0] +1000057a: 7829 ldrb r1, [r5, #0] +1000057c: 2301 movs r3, #1 +1000057e: f10d 020f add.w r2, sp, #15 +10000582: f003 fbd1 bl 10003d28 +10000586: 2032 movs r0, #50 @ 0x32 +10000588: 2100 movs r1, #0 +1000058a: f000 feed bl 10001368 +1000058e: 7837 ldrb r7, [r6, #0] +10000590: 6820 ldr r0, [r4, #0] +10000592: f047 0304 orr.w r3, r7, #4 +10000596: f88d 300f strb.w r3, [sp, #15] +1000059a: b188 cbz r0, 100005c0 +1000059c: 2300 movs r3, #0 +1000059e: 9300 str r3, [sp, #0] +100005a0: 7829 ldrb r1, [r5, #0] +100005a2: 2301 movs r3, #1 +100005a4: f10d 020f add.w r2, sp, #15 +100005a8: f003 fbbe bl 10003d28 +100005ac: e008 b.n 100005c0 +100005ae: bf00 nop +100005b0: 20000828 .word 0x20000828 +100005b4: 200005b0 .word 0x200005b0 +100005b8: 200005a8 .word 0x200005a8 +100005bc: 200005ac .word 0x200005ac +100005c0: 2001 movs r0, #1 +100005c2: 2100 movs r1, #0 +100005c4: f000 fed0 bl 10001368 +100005c8: 6820 ldr r0, [r4, #0] +100005ca: f027 0704 bic.w r7, r7, #4 +100005ce: f88d 700f strb.w r7, [sp, #15] +100005d2: b138 cbz r0, 100005e4 +100005d4: 2300 movs r3, #0 +100005d6: 9300 str r3, [sp, #0] +100005d8: 7829 ldrb r1, [r5, #0] +100005da: 2301 movs r3, #1 +100005dc: f10d 020f add.w r2, sp, #15 +100005e0: f003 fba2 bl 10003d28 +100005e4: 2032 movs r0, #50 @ 0x32 +100005e6: 2100 movs r1, #0 +100005e8: f000 febe bl 10001368 +100005ec: 2301 movs r3, #1 +100005ee: f8d8 7000 ldr.w r7, [r8] +100005f2: 6820 ldr r0, [r4, #0] +100005f4: fa03 f707 lsl.w r7, r3, r7 +100005f8: 7833 ldrb r3, [r6, #0] +100005fa: b2ff uxtb r7, r7 +100005fc: 431f orrs r7, r3 +100005fe: f047 0304 orr.w r3, r7, #4 +10000602: f88d 300f strb.w r3, [sp, #15] +10000606: b138 cbz r0, 10000618 +10000608: 2200 movs r2, #0 +1000060a: 9200 str r2, [sp, #0] +1000060c: 2301 movs r3, #1 +1000060e: 7829 ldrb r1, [r5, #0] +10000610: f10d 020f add.w r2, sp, #15 +10000614: f003 fb88 bl 10003d28 +10000618: 2001 movs r0, #1 +1000061a: 2100 movs r1, #0 +1000061c: f000 fea4 bl 10001368 +10000620: 6820 ldr r0, [r4, #0] +10000622: f027 0704 bic.w r7, r7, #4 +10000626: f88d 700f strb.w r7, [sp, #15] +1000062a: b138 cbz r0, 1000063c +1000062c: 2300 movs r3, #0 +1000062e: 9300 str r3, [sp, #0] +10000630: 7829 ldrb r1, [r5, #0] +10000632: 2301 movs r3, #1 +10000634: f10d 020f add.w r2, sp, #15 +10000638: f003 fb76 bl 10003d28 +1000063c: 2032 movs r0, #50 @ 0x32 +1000063e: 2100 movs r1, #0 +10000640: f000 fe92 bl 10001368 +10000644: 2002 movs r0, #2 +10000646: f000 fefb bl 10001440 +1000064a: 7837 ldrb r7, [r6, #0] +1000064c: 6820 ldr r0, [r4, #0] +1000064e: f047 0304 orr.w r3, r7, #4 +10000652: f88d 300f strb.w r3, [sp, #15] +10000656: b138 cbz r0, 10000668 +10000658: 2300 movs r3, #0 +1000065a: 9300 str r3, [sp, #0] +1000065c: 7829 ldrb r1, [r5, #0] +1000065e: 2301 movs r3, #1 +10000660: f10d 020f add.w r2, sp, #15 +10000664: f003 fb60 bl 10003d28 +10000668: 2001 movs r0, #1 +1000066a: 2100 movs r1, #0 +1000066c: f000 fe7c bl 10001368 +10000670: 6820 ldr r0, [r4, #0] +10000672: f027 0704 bic.w r7, r7, #4 +10000676: f88d 700f strb.w r7, [sp, #15] +1000067a: b138 cbz r0, 1000068c +1000067c: 2300 movs r3, #0 +1000067e: 9300 str r3, [sp, #0] +10000680: 7829 ldrb r1, [r5, #0] +10000682: 2301 movs r3, #1 +10000684: f10d 020f add.w r2, sp, #15 +10000688: f003 fb4e bl 10003d28 +1000068c: 2032 movs r0, #50 @ 0x32 +1000068e: 2100 movs r1, #0 +10000690: f000 fe6a bl 10001368 +10000694: 2306 movs r3, #6 +10000696: f8d8 1000 ldr.w r1, [r8] +1000069a: 7832 ldrb r2, [r6, #0] +1000069c: fa03 f601 lsl.w r6, r3, r1 +100006a0: b2f6 uxtb r6, r6 +100006a2: 4316 orrs r6, r2 +100006a4: 6820 ldr r0, [r4, #0] +100006a6: f046 0304 orr.w r3, r6, #4 +100006aa: f88d 300f strb.w r3, [sp, #15] +100006ae: b138 cbz r0, 100006c0 +100006b0: 2700 movs r7, #0 +100006b2: 7829 ldrb r1, [r5, #0] +100006b4: 2301 movs r3, #1 +100006b6: f10d 020f add.w r2, sp, #15 +100006ba: 9700 str r7, [sp, #0] +100006bc: f003 fb34 bl 10003d28 +100006c0: 2001 movs r0, #1 +100006c2: 2100 movs r1, #0 +100006c4: f000 fe50 bl 10001368 +100006c8: 6820 ldr r0, [r4, #0] +100006ca: f026 0604 bic.w r6, r6, #4 +100006ce: f88d 600f strb.w r6, [sp, #15] +100006d2: b138 cbz r0, 100006e4 +100006d4: 2400 movs r4, #0 +100006d6: 7829 ldrb r1, [r5, #0] +100006d8: 2301 movs r3, #1 +100006da: f10d 020f add.w r2, sp, #15 +100006de: 9400 str r4, [sp, #0] +100006e0: f003 fb22 bl 10003d28 +100006e4: 2032 movs r0, #50 @ 0x32 +100006e6: 2100 movs r1, #0 +100006e8: b004 add sp, #16 +100006ea: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100006ee: f000 be3b b.w 10001368 +100006f2: bf00 nop + +100006f4 : +100006f4: 2801 cmp r0, #1 +100006f6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100006fa: 4603 mov r3, r0 +100006fc: f44f 4580 mov.w r5, #16384 @ 0x4000 +10000700: bfa8 it ge +10000702: 2301 movge r3, #1 +10000704: b084 sub sp, #16 +10000706: f8ad 500c strh.w r5, [sp, #12] +1000070a: 446b add r3, sp +1000070c: 7b1b ldrb r3, [r3, #12] +1000070e: 4c34 ldr r4, [pc, #208] @ (100007e0 ) +10000710: 4419 add r1, r3 +10000712: 4f34 ldr r7, [pc, #208] @ (100007e4 ) +10000714: 6823 ldr r3, [r4, #0] +10000716: f3c1 1503 ubfx r5, r1, #4, #4 +1000071a: f045 0508 orr.w r5, r5, #8 +1000071e: 409d lsls r5, r3 +10000720: 4e31 ldr r6, [pc, #196] @ (100007e8 ) +10000722: f897 e000 ldrb.w lr, [r7] +10000726: b2ed uxtb r5, r5 +10000728: ea45 050e orr.w r5, r5, lr +1000072c: 6832 ldr r2, [r6, #0] +1000072e: f045 0304 orr.w r3, r5, #4 +10000732: fa5f f881 uxtb.w r8, r1 +10000736: f88d 300b strb.w r3, [sp, #11] +1000073a: b14a cbz r2, 10000750 +1000073c: 2300 movs r3, #0 +1000073e: 9300 str r3, [sp, #0] +10000740: 4b2a ldr r3, [pc, #168] @ (100007ec ) +10000742: 4610 mov r0, r2 +10000744: 7819 ldrb r1, [r3, #0] +10000746: f10d 020b add.w r2, sp, #11 +1000074a: 2301 movs r3, #1 +1000074c: f003 faec bl 10003d28 +10000750: 2001 movs r0, #1 +10000752: 2100 movs r1, #0 +10000754: f000 fe08 bl 10001368 +10000758: 6830 ldr r0, [r6, #0] +1000075a: f025 0504 bic.w r5, r5, #4 +1000075e: f88d 500b strb.w r5, [sp, #11] +10000762: b140 cbz r0, 10000776 +10000764: 2300 movs r3, #0 +10000766: 9300 str r3, [sp, #0] +10000768: 4b20 ldr r3, [pc, #128] @ (100007ec ) +1000076a: f10d 020b add.w r2, sp, #11 +1000076e: 7819 ldrb r1, [r3, #0] +10000770: 2301 movs r3, #1 +10000772: f003 fad9 bl 10003d28 +10000776: 2032 movs r0, #50 @ 0x32 +10000778: 2100 movs r1, #0 +1000077a: f000 fdf5 bl 10001368 +1000077e: 6822 ldr r2, [r4, #0] +10000780: f008 040f and.w r4, r8, #15 +10000784: 783b ldrb r3, [r7, #0] +10000786: 4094 lsls r4, r2 +10000788: b2e4 uxtb r4, r4 +1000078a: 431c orrs r4, r3 +1000078c: 6830 ldr r0, [r6, #0] +1000078e: f044 0304 orr.w r3, r4, #4 +10000792: f88d 300b strb.w r3, [sp, #11] +10000796: b140 cbz r0, 100007aa +10000798: 2500 movs r5, #0 +1000079a: 4b14 ldr r3, [pc, #80] @ (100007ec ) +1000079c: f10d 020b add.w r2, sp, #11 +100007a0: 7819 ldrb r1, [r3, #0] +100007a2: 2301 movs r3, #1 +100007a4: 9500 str r5, [sp, #0] +100007a6: f003 fabf bl 10003d28 +100007aa: 2001 movs r0, #1 +100007ac: 2100 movs r1, #0 +100007ae: f000 fddb bl 10001368 +100007b2: 6830 ldr r0, [r6, #0] +100007b4: f024 0404 bic.w r4, r4, #4 +100007b8: f88d 400b strb.w r4, [sp, #11] +100007bc: b140 cbz r0, 100007d0 +100007be: 2400 movs r4, #0 +100007c0: 4a0a ldr r2, [pc, #40] @ (100007ec ) +100007c2: 2301 movs r3, #1 +100007c4: 7811 ldrb r1, [r2, #0] +100007c6: f10d 020b add.w r2, sp, #11 +100007ca: 9400 str r4, [sp, #0] +100007cc: f003 faac bl 10003d28 +100007d0: 2032 movs r0, #50 @ 0x32 +100007d2: 2100 movs r1, #0 +100007d4: b004 add sp, #16 +100007d6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100007da: f000 bdc5 b.w 10001368 +100007de: bf00 nop +100007e0: 200005ac .word 0x200005ac +100007e4: 200005a8 .word 0x200005a8 +100007e8: 20000828 .word 0x20000828 +100007ec: 200005b0 .word 0x200005b0 + +100007f0 : +100007f0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100007f4: 7804 ldrb r4, [r0, #0] +100007f6: b084 sub sp, #16 +100007f8: 2c00 cmp r4, #0 +100007fa: d06e beq.n 100008da +100007fc: 4607 mov r7, r0 +100007fe: f8df 90e8 ldr.w r9, [pc, #232] @ 100008e8 +10000802: f8df 80e8 ldr.w r8, [pc, #232] @ 100008ec +10000806: 4d36 ldr r5, [pc, #216] @ (100008e0 ) +10000808: 4e36 ldr r6, [pc, #216] @ (100008e4 ) +1000080a: f8d9 2000 ldr.w r2, [r9] +1000080e: 0923 lsrs r3, r4, #4 +10000810: 4093 lsls r3, r2 +10000812: f043 0301 orr.w r3, r3, #1 +10000816: f898 2000 ldrb.w r2, [r8] +1000081a: b2db uxtb r3, r3 +1000081c: ea43 0a02 orr.w sl, r3, r2 +10000820: 6828 ldr r0, [r5, #0] +10000822: f04a 0304 orr.w r3, sl, #4 +10000826: f88d 300f strb.w r3, [sp, #15] +1000082a: b148 cbz r0, 10000840 +1000082c: f04f 0c00 mov.w ip, #0 +10000830: 7831 ldrb r1, [r6, #0] +10000832: 2301 movs r3, #1 +10000834: f10d 020f add.w r2, sp, #15 +10000838: f8cd c000 str.w ip, [sp] +1000083c: f003 fa74 bl 10003d28 +10000840: 2001 movs r0, #1 +10000842: 2100 movs r1, #0 +10000844: f000 fd90 bl 10001368 +10000848: 6828 ldr r0, [r5, #0] +1000084a: f02a 0304 bic.w r3, sl, #4 +1000084e: f88d 300f strb.w r3, [sp, #15] +10000852: b148 cbz r0, 10000868 +10000854: f04f 0c00 mov.w ip, #0 +10000858: 7831 ldrb r1, [r6, #0] +1000085a: 2301 movs r3, #1 +1000085c: f10d 020f add.w r2, sp, #15 +10000860: f8cd c000 str.w ip, [sp] +10000864: f003 fa60 bl 10003d28 +10000868: 2032 movs r0, #50 @ 0x32 +1000086a: 2100 movs r1, #0 +1000086c: f000 fd7c bl 10001368 +10000870: f8d9 3000 ldr.w r3, [r9] +10000874: f004 040f and.w r4, r4, #15 +10000878: 409c lsls r4, r3 +1000087a: f044 0401 orr.w r4, r4, #1 +1000087e: f898 3000 ldrb.w r3, [r8] +10000882: b2e4 uxtb r4, r4 +10000884: 431c orrs r4, r3 +10000886: 6828 ldr r0, [r5, #0] +10000888: f044 0304 orr.w r3, r4, #4 +1000088c: f88d 300f strb.w r3, [sp, #15] +10000890: b148 cbz r0, 100008a6 +10000892: f04f 0c00 mov.w ip, #0 +10000896: 7831 ldrb r1, [r6, #0] +10000898: 2301 movs r3, #1 +1000089a: f10d 020f add.w r2, sp, #15 +1000089e: f8cd c000 str.w ip, [sp] +100008a2: f003 fa41 bl 10003d28 +100008a6: 2001 movs r0, #1 +100008a8: 2100 movs r1, #0 +100008aa: f000 fd5d bl 10001368 +100008ae: 6828 ldr r0, [r5, #0] +100008b0: f024 0404 bic.w r4, r4, #4 +100008b4: f88d 400f strb.w r4, [sp, #15] +100008b8: b138 cbz r0, 100008ca +100008ba: 2400 movs r4, #0 +100008bc: 7831 ldrb r1, [r6, #0] +100008be: 2301 movs r3, #1 +100008c0: f10d 020f add.w r2, sp, #15 +100008c4: 9400 str r4, [sp, #0] +100008c6: f003 fa2f bl 10003d28 +100008ca: 2032 movs r0, #50 @ 0x32 +100008cc: 2100 movs r1, #0 +100008ce: f000 fd4b bl 10001368 +100008d2: f817 4f01 ldrb.w r4, [r7, #1]! +100008d6: 2c00 cmp r4, #0 +100008d8: d197 bne.n 1000080a +100008da: b004 add sp, #16 +100008dc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100008e0: 20000828 .word 0x20000828 +100008e4: 200005b0 .word 0x200005b0 +100008e8: 200005ac .word 0x200005ac +100008ec: 200005a8 .word 0x200005a8 + +100008f0 : +100008f0: b410 push {r4} +100008f2: f44f 7480 mov.w r4, #256 @ 0x100 +100008f6: 4b0c ldr r3, [pc, #48] @ (10000928 ) +100008f8: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100008fc: eb03 0380 add.w r3, r3, r0, lsl #2 +10000900: 00c0 lsls r0, r0, #3 +10000902: f082 0240 eor.w r2, r2, #64 @ 0x40 +10000906: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +1000090a: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +1000090e: f002 02c0 and.w r2, r2, #192 @ 0xc0 +10000912: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000916: f503 5340 add.w r3, r3, #12288 @ 0x3000 +1000091a: f8cc 2000 str.w r2, [ip] +1000091e: 6041 str r1, [r0, #4] +10000920: 601c str r4, [r3, #0] +10000922: f85d 4b04 ldr.w r4, [sp], #4 +10000926: 4770 bx lr +10000928: 40038004 .word 0x40038004 + +1000092c : +1000092c: b410 push {r4} +1000092e: 4c08 ldr r4, [pc, #32] @ (10000950 ) +10000930: 00c9 lsls r1, r1, #3 +10000932: ea41 0182 orr.w r1, r1, r2, lsl #2 +10000936: f854 2020 ldr.w r2, [r4, r0, lsl #2] +1000093a: eb04 0380 add.w r3, r4, r0, lsl #2 +1000093e: 4051 eors r1, r2 +10000940: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000944: f001 010c and.w r1, r1, #12 +10000948: f85d 4b04 ldr.w r4, [sp], #4 +1000094c: 6019 str r1, [r3, #0] +1000094e: 4770 bx lr +10000950: 40038004 .word 0x40038004 + +10000954 : +10000954: b40f push {r0, r1, r2, r3} +10000956: b500 push {lr} +10000958: b083 sub sp, #12 +1000095a: 9c04 ldr r4, [sp, #16] +1000095c: 4807 ldr r0, [pc, #28] @ (1000097c ) +1000095e: f002 ff95 bl 1000388c <__wrap_puts> +10000962: b13c cbz r4, 10000974 +10000964: a905 add r1, sp, #20 +10000966: 4620 mov r0, r4 +10000968: 9101 str r1, [sp, #4] +1000096a: f002 fe01 bl 10003570 +1000096e: 4804 ldr r0, [pc, #16] @ (10000980 ) +10000970: f002 ff8c bl 1000388c <__wrap_puts> +10000974: 2001 movs r0, #1 +10000976: f002 fe13 bl 100035a0 <_exit> +1000097a: bf00 nop +1000097c: 10003f20 .word 0x10003f20 +10000980: 10003f08 .word 0x10003f08 + +10000984 : +10000984: b570 push {r4, r5, r6, lr} +10000986: 4686 mov lr, r0 +10000988: f3ef 8510 mrs r5, PRIMASK +1000098c: b672 cpsid i +1000098e: 4c12 ldr r4, [pc, #72] @ (100009d8 ) +10000990: e8d4 6fcf ldaexb r6, [r4] +10000994: 2001 movs r0, #1 +10000996: 2e00 cmp r6, #0 +10000998: d1fa bne.n 10000990 +1000099a: e8c4 0f46 strexb r6, r0, [r4] +1000099e: 2e00 cmp r6, #0 +100009a0: d1f6 bne.n 10000990 +100009a2: f3bf 8f5f dmb sy +100009a6: f04f 0c01 mov.w ip, #1 +100009aa: 08c8 lsrs r0, r1, #3 +100009ac: f001 0307 and.w r3, r1, #7 +100009b0: fa0c f303 lsl.w r3, ip, r3 +100009b4: f81e c000 ldrb.w ip, [lr, r0] +100009b8: ea1c 0603 ands.w r6, ip, r3 +100009bc: d108 bne.n 100009d0 +100009be: ea4c 0c03 orr.w ip, ip, r3 +100009c2: f80e c000 strb.w ip, [lr, r0] +100009c6: e8c4 6f8f stlb r6, [r4] +100009ca: f385 8810 msr PRIMASK, r5 +100009ce: bd70 pop {r4, r5, r6, pc} +100009d0: 4610 mov r0, r2 +100009d2: f7ff ffbf bl 10000954 +100009d6: bf00 nop +100009d8: 200007d3 .word 0x200007d3 + +100009dc : +100009dc: 4a04 ldr r2, [pc, #16] @ (100009f0 ) +100009de: 7810 ldrb r0, [r2, #0] +100009e0: 1c43 adds r3, r0, #1 +100009e2: b2db uxtb r3, r3 +100009e4: 2b18 cmp r3, #24 +100009e6: bf28 it cs +100009e8: 2310 movcs r3, #16 +100009ea: 7013 strb r3, [r2, #0] +100009ec: 4770 bx lr +100009ee: bf00 nop +100009f0: 200005b1 .word 0x200005b1 + +100009f4 : +100009f4: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100009f8: 6893 ldr r3, [r2, #8] +100009fa: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100009fe: 6093 str r3, [r2, #8] +10000a00: 4770 bx lr +10000a02: bf00 nop + +10000a04 : +10000a04: 2100 movs r1, #0 +10000a06: 4b04 ldr r3, [pc, #16] @ (10000a18 ) +10000a08: f103 0220 add.w r2, r3, #32 +10000a0c: e8c3 1f8f stlb r1, [r3] +10000a10: 3301 adds r3, #1 +10000a12: 4293 cmp r3, r2 +10000a14: d1fa bne.n 10000a0c +10000a16: 4770 bx lr +10000a18: 200007c8 .word 0x200007c8 + +10000a1c : +10000a1c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000a20: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000a24: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000a28: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +10000a2c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000a30: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000a34: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000a38: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000a3c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000a40: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000a44: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000a48: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000a4c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000a50: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000a54: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000a58: b662 cpsie i +10000a5a: 4770 bx lr + +10000a5c : +10000a5c: 2301 movs r3, #1 +10000a5e: f000 021f and.w r2, r0, #31 +10000a62: 4093 lsls r3, r2 +10000a64: 0940 lsrs r0, r0, #5 +10000a66: b141 cbz r1, 10000a7a +10000a68: 0080 lsls r0, r0, #2 +10000a6a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000a6e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000a72: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000a76: 6003 str r3, [r0, #0] +10000a78: 4770 bx lr +10000a7a: 4a02 ldr r2, [pc, #8] @ (10000a84 ) +10000a7c: 3020 adds r0, #32 +10000a7e: f842 3020 str.w r3, [r2, r0, lsl #2] +10000a82: 4770 bx lr +10000a84: e000e100 .word 0xe000e100 + +10000a88 : +10000a88: b5f8 push {r3, r4, r5, r6, r7, lr} +10000a8a: 460d mov r5, r1 +10000a8c: f3ef 8710 mrs r7, PRIMASK +10000a90: b672 cpsid i +10000a92: 4e12 ldr r6, [pc, #72] @ (10000adc ) +10000a94: e8d6 2fcf ldaexb r2, [r6] +10000a98: 2301 movs r3, #1 +10000a9a: 2a00 cmp r2, #0 +10000a9c: d1fa bne.n 10000a94 +10000a9e: e8c6 3f42 strexb r2, r3, [r6] +10000aa2: 2a00 cmp r2, #0 +10000aa4: d1f6 bne.n 10000a94 +10000aa6: f3bf 8f5f dmb sy +10000aaa: 4b0d ldr r3, [pc, #52] @ (10000ae0 ) +10000aac: f100 0410 add.w r4, r0, #16 +10000ab0: 689b ldr r3, [r3, #8] +10000ab2: 4a0c ldr r2, [pc, #48] @ (10000ae4 ) +10000ab4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000ab8: 4293 cmp r3, r2 +10000aba: d003 beq.n 10000ac4 +10000abc: 4299 cmp r1, r3 +10000abe: d001 beq.n 10000ac4 +10000ac0: f000 ff7a bl 100019b8 +10000ac4: 4b06 ldr r3, [pc, #24] @ (10000ae0 ) +10000ac6: 689b ldr r3, [r3, #8] +10000ac8: f843 5024 str.w r5, [r3, r4, lsl #2] +10000acc: f3bf 8f5f dmb sy +10000ad0: 2300 movs r3, #0 +10000ad2: e8c6 3f8f stlb r3, [r6] +10000ad6: f387 8810 msr PRIMASK, r7 +10000ada: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000adc: 200007d1 .word 0x200007d1 +10000ae0: e000ed00 .word 0xe000ed00 +10000ae4: 10000111 .word 0x10000111 + +10000ae8 : +10000ae8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000aec: b083 sub sp, #12 +10000aee: f3ef 8a10 mrs sl, PRIMASK +10000af2: b672 cpsid i +10000af4: 4e71 ldr r6, [pc, #452] @ (10000cbc ) +10000af6: e8d6 2fcf ldaexb r2, [r6] +10000afa: 2301 movs r3, #1 +10000afc: 2a00 cmp r2, #0 +10000afe: d1fa bne.n 10000af6 +10000b00: e8c6 3f42 strexb r2, r3, [r6] +10000b04: 2a00 cmp r2, #0 +10000b06: d1f6 bne.n 10000af6 +10000b08: f3bf 8f5f dmb sy +10000b0c: 4b6c ldr r3, [pc, #432] @ (10000cc0 ) +10000b0e: f100 0810 add.w r8, r0, #16 +10000b12: 689b ldr r3, [r3, #8] +10000b14: 4a6b ldr r2, [pc, #428] @ (10000cc4 ) +10000b16: f853 5028 ldr.w r5, [r3, r8, lsl #2] +10000b1a: 4295 cmp r5, r2 +10000b1c: d045 beq.n 10000baa +10000b1e: 428d cmp r5, r1 +10000b20: 460c mov r4, r1 +10000b22: d050 beq.n 10000bc6 +10000b24: 4f68 ldr r7, [pc, #416] @ (10000cc8 ) +10000b26: 1beb subs r3, r5, r7 +10000b28: 2b2f cmp r3, #47 @ 0x2f +10000b2a: d83e bhi.n 10000baa +10000b2c: 2101 movs r1, #1 +10000b2e: ea4f 1950 mov.w r9, r0, lsr #5 +10000b32: ea4f 0989 mov.w r9, r9, lsl #2 +10000b36: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +10000b3a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +10000b3e: f000 031f and.w r3, r0, #31 +10000b42: fa01 f003 lsl.w r0, r1, r3 +10000b46: f8d9 3000 ldr.w r3, [r9] +10000b4a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000b4e: ea00 0b03 and.w fp, r0, r3 +10000b52: f3bf 8f5f dmb sy +10000b56: f3ef 8105 mrs r1, IPSR +10000b5a: b2c9 uxtb r1, r1 +10000b5c: 2900 cmp r1, #0 +10000b5e: d034 beq.n 10000bca +10000b60: 4588 cmp r8, r1 +10000b62: d005 beq.n 10000b70 +10000b64: e9cd 1000 strd r1, r0, [sp] +10000b68: f000 ff26 bl 100019b8 +10000b6c: e9dd 1000 ldrd r1, r0, [sp] +10000b70: f025 0e01 bic.w lr, r5, #1 +10000b74: f8de c008 ldr.w ip, [lr, #8] +10000b78: 4564 cmp r4, ip +10000b7a: d105 bne.n 10000b88 +10000b7c: e089 b.n 10000c92 +10000b7e: f8d3 c008 ldr.w ip, [r3, #8] +10000b82: 4564 cmp r4, ip +10000b84: d031 beq.n 10000bea +10000b86: 469e mov lr, r3 +10000b88: f99e 2006 ldrsb.w r2, [lr, #6] +10000b8c: eb02 0342 add.w r3, r2, r2, lsl #1 +10000b90: 2a00 cmp r2, #0 +10000b92: eb07 0383 add.w r3, r7, r3, lsl #2 +10000b96: daf2 bge.n 10000b7e +10000b98: 4564 cmp r4, ip +10000b9a: d061 beq.n 10000c60 +10000b9c: f1bb 0f00 cmp.w fp, #0 +10000ba0: d020 beq.n 10000be4 +10000ba2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +10000ba6: f8c9 0000 str.w r0, [r9] +10000baa: 4b45 ldr r3, [pc, #276] @ (10000cc0 ) +10000bac: 689b ldr r3, [r3, #8] +10000bae: f843 5028 str.w r5, [r3, r8, lsl #2] +10000bb2: f3bf 8f5f dmb sy +10000bb6: 2300 movs r3, #0 +10000bb8: e8c6 3f8f stlb r3, [r6] +10000bbc: f38a 8810 msr PRIMASK, sl +10000bc0: b003 add sp, #12 +10000bc2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000bc6: 4615 mov r5, r2 +10000bc8: e7ef b.n 10000baa +10000bca: f025 0e01 bic.w lr, r5, #1 +10000bce: f8de c008 ldr.w ip, [lr, #8] +10000bd2: 4564 cmp r4, ip +10000bd4: d1d8 bne.n 10000b88 +10000bd6: f99e 4006 ldrsb.w r4, [lr, #6] +10000bda: 4673 mov r3, lr +10000bdc: 2c00 cmp r4, #0 +10000bde: da08 bge.n 10000bf2 +10000be0: 4615 mov r5, r2 +10000be2: e046 b.n 10000c72 +10000be4: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000be8: e7df b.n 10000baa +10000bea: f993 4006 ldrsb.w r4, [r3, #6] +10000bee: 2c00 cmp r4, #0 +10000bf0: db37 blt.n 10000c62 +10000bf2: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000bf6: eb07 0c8c add.w ip, r7, ip, lsl #2 +10000bfa: f89c 1007 ldrb.w r1, [ip, #7] +10000bfe: f8dc 2008 ldr.w r2, [ip, #8] +10000c02: 71d9 strb r1, [r3, #7] +10000c04: 609a str r2, [r3, #8] +10000c06: f99c 2006 ldrsb.w r2, [ip, #6] +10000c0a: 0061 lsls r1, r4, #1 +10000c0c: 2a00 cmp r2, #0 +10000c0e: 719a strb r2, [r3, #6] +10000c10: db3d blt.n 10000c8e +10000c12: f8bc e004 ldrh.w lr, [ip, #4] +10000c16: ea5f 5e4e movs.w lr, lr, lsl #21 +10000c1a: d505 bpl.n 10000c28 +10000c1c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000c20: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000c24: f10e 0e1f add.w lr, lr, #31 +10000c28: f06f 0c07 mvn.w ip, #7 +10000c2c: 190a adds r2, r1, r4 +10000c2e: ea4f 5e6e mov.w lr, lr, asr #21 +10000c32: 0092 lsls r2, r2, #2 +10000c34: eb02 024e add.w r2, r2, lr, lsl #1 +10000c38: 3208 adds r2, #8 +10000c3a: 443a add r2, r7 +10000c3c: ebac 0c03 sub.w ip, ip, r3 +10000c40: 4462 add r2, ip +10000c42: f3c2 024a ubfx r2, r2, #1, #11 +10000c46: ea6f 42c2 mvn.w r2, r2, lsl #19 +10000c4a: ea6f 42d2 mvn.w r2, r2, lsr #19 +10000c4e: 809a strh r2, [r3, #4] +10000c50: 4b1e ldr r3, [pc, #120] @ (10000ccc ) +10000c52: 4421 add r1, r4 +10000c54: 781a ldrb r2, [r3, #0] +10000c56: eb07 0181 add.w r1, r7, r1, lsl #2 +10000c5a: 701c strb r4, [r3, #0] +10000c5c: 718a strb r2, [r1, #6] +10000c5e: e79d b.n 10000b9c +10000c60: 4673 mov r3, lr +10000c62: b9d9 cbnz r1, 10000c9c +10000c64: 22ff movs r2, #255 @ 0xff +10000c66: f88e 2006 strb.w r2, [lr, #6] +10000c6a: f64b 5201 movw r2, #48385 @ 0xbd01 +10000c6e: f8ae 2004 strh.w r2, [lr, #4] +10000c72: 4c16 ldr r4, [pc, #88] @ (10000ccc ) +10000c74: f64a 22aa movw r2, #43690 @ 0xaaaa +10000c78: f894 c000 ldrb.w ip, [r4] +10000c7c: 4619 mov r1, r3 +10000c7e: 1bc9 subs r1, r1, r7 +10000c80: 4149 adcs r1, r1 +10000c82: 434a muls r2, r1 +10000c84: 0d12 lsrs r2, r2, #20 +10000c86: f883 c006 strb.w ip, [r3, #6] +10000c8a: 7022 strb r2, [r4, #0] +10000c8c: e786 b.n 10000b9c +10000c8e: 4a10 ldr r2, [pc, #64] @ (10000cd0 ) +10000c90: e7dd b.n 10000c4e +10000c92: f99e 4006 ldrsb.w r4, [lr, #6] +10000c96: 4673 mov r3, lr +10000c98: 2c00 cmp r4, #0 +10000c9a: daaa bge.n 10000bf2 +10000c9c: 4a0d ldr r2, [pc, #52] @ (10000cd4 ) +10000c9e: 4c0e ldr r4, [pc, #56] @ (10000cd8 ) +10000ca0: 1ad2 subs r2, r2, r3 +10000ca2: 3a08 subs r2, #8 +10000ca4: f3c2 310a ubfx r1, r2, #12, #11 +10000ca8: ea6f 5101 mvn.w r1, r1, lsl #20 +10000cac: ea6f 5111 mvn.w r1, r1, lsr #20 +10000cb0: ea44 0252 orr.w r2, r4, r2, lsr #1 +10000cb4: 80da strh r2, [r3, #6] +10000cb6: 8099 strh r1, [r3, #4] +10000cb8: e770 b.n 10000b9c +10000cba: bf00 nop +10000cbc: 200007d1 .word 0x200007d1 +10000cc0: e000ed00 .word 0xe000ed00 +10000cc4: 10000111 .word 0x10000111 +10000cc8: 200005b4 .word 0x200005b4 +10000ccc: 20000870 .word 0x20000870 +10000cd0: ffffbd01 .word 0xffffbd01 +10000cd4: 200005ee .word 0x200005ee +10000cd8: fffff800 .word 0xfffff800 + +10000cdc : +10000cdc: b5f0 push {r4, r5, r6, r7, lr} +10000cde: f3ef 8505 mrs r5, IPSR +10000ce2: b2ed uxtb r5, r5 +10000ce4: f3ef 8c10 mrs ip, PRIMASK +10000ce8: b672 cpsid i +10000cea: 4926 ldr r1, [pc, #152] @ (10000d84 ) +10000cec: e8d1 2fcf ldaexb r2, [r1] +10000cf0: 2301 movs r3, #1 +10000cf2: 2a00 cmp r2, #0 +10000cf4: d1fa bne.n 10000cec +10000cf6: e8c1 3f42 strexb r2, r3, [r1] +10000cfa: 2a00 cmp r2, #0 +10000cfc: d1f6 bne.n 10000cec +10000cfe: f3bf 8f5f dmb sy +10000d02: 4e21 ldr r6, [pc, #132] @ (10000d88 ) +10000d04: f040 0e01 orr.w lr, r0, #1 +10000d08: 68b4 ldr r4, [r6, #8] +10000d0a: f64a 23aa movw r3, #43690 @ 0xaaaa +10000d0e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000d12: 4a1e ldr r2, [pc, #120] @ (10000d8c ) +10000d14: 4604 mov r4, r0 +10000d16: 1aa4 subs r4, r4, r2 +10000d18: 4164 adcs r4, r4 +10000d1a: 4363 muls r3, r4 +10000d1c: 0d1b lsrs r3, r3, #20 +10000d1e: 4577 cmp r7, lr +10000d20: b25b sxtb r3, r3 +10000d22: d01b beq.n 10000d5c +10000d24: f992 4006 ldrsb.w r4, [r2, #6] +10000d28: 429c cmp r4, r3 +10000d2a: d01c beq.n 10000d66 +10000d2c: f992 4012 ldrsb.w r4, [r2, #18] +10000d30: 429c cmp r4, r3 +10000d32: d023 beq.n 10000d7c +10000d34: f992 401e ldrsb.w r4, [r2, #30] +10000d38: 429c cmp r4, r3 +10000d3a: d021 beq.n 10000d80 +10000d3c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000d40: 429c cmp r4, r3 +10000d42: bf08 it eq +10000d44: 2403 moveq r4, #3 +10000d46: d00f beq.n 10000d68 +10000d48: 4a11 ldr r2, [pc, #68] @ (10000d90 ) +10000d4a: 2400 movs r4, #0 +10000d4c: 7815 ldrb r5, [r2, #0] +10000d4e: 7013 strb r3, [r2, #0] +10000d50: 7185 strb r5, [r0, #6] +10000d52: e8c1 4f8f stlb r4, [r1] +10000d56: f38c 8810 msr PRIMASK, ip +10000d5a: bdf0 pop {r4, r5, r6, r7, pc} +10000d5c: 68b2 ldr r2, [r6, #8] +10000d5e: 4c0d ldr r4, [pc, #52] @ (10000d94 ) +10000d60: f842 4025 str.w r4, [r2, r5, lsl #2] +10000d64: e7f0 b.n 10000d48 +10000d66: 2400 movs r4, #0 +10000d68: eb04 0444 add.w r4, r4, r4, lsl #1 +10000d6c: eb02 0284 add.w r2, r2, r4, lsl #2 +10000d70: 24ff movs r4, #255 @ 0xff +10000d72: 7194 strb r4, [r2, #6] +10000d74: f64b 5401 movw r4, #48385 @ 0xbd01 +10000d78: 8094 strh r4, [r2, #4] +10000d7a: e7e5 b.n 10000d48 +10000d7c: 2401 movs r4, #1 +10000d7e: e7f3 b.n 10000d68 +10000d80: 2402 movs r4, #2 +10000d82: e7f1 b.n 10000d68 +10000d84: 200007d1 .word 0x200007d1 +10000d88: e000ed00 .word 0xe000ed00 +10000d8c: 200005b4 .word 0x200005b4 +10000d90: 20000870 .word 0x20000870 +10000d94: 10000111 .word 0x10000111 + +10000d98 : +10000d98: 4b01 ldr r3, [pc, #4] @ (10000da0 ) +10000d9a: 440b add r3, r1 +10000d9c: 6003 str r3, [r0, #0] +10000d9e: 4770 bx lr +10000da0: 200007c8 .word 0x200007c8 + +10000da4 : +10000da4: b570 push {r4, r5, r6, lr} +10000da6: 4c10 ldr r4, [pc, #64] @ (10000de8 ) +10000da8: 4d10 ldr r5, [pc, #64] @ (10000dec ) +10000daa: 42ac cmp r4, r5 +10000dac: d20e bcs.n 10000dcc +10000dae: 26ff movs r6, #255 @ 0xff +10000db0: 6823 ldr r3, [r4, #0] +10000db2: b163 cbz r3, 10000dce +10000db4: f7ff fe12 bl 100009dc +10000db8: 4601 mov r1, r0 +10000dba: 4620 mov r0, r4 +10000dbc: f7ff ffec bl 10000d98 +10000dc0: 80a6 strh r6, [r4, #4] +10000dc2: f3bf 8f5f dmb sy +10000dc6: 3408 adds r4, #8 +10000dc8: 42ac cmp r4, r5 +10000dca: d3f1 bcc.n 10000db0 +10000dcc: bd70 pop {r4, r5, r6, pc} +10000dce: f7ff fe05 bl 100009dc +10000dd2: 4601 mov r1, r0 +10000dd4: 4620 mov r0, r4 +10000dd6: f7ff ffdf bl 10000d98 +10000dda: 7126 strb r6, [r4, #4] +10000ddc: f3bf 8f5f dmb sy +10000de0: 3408 adds r4, #8 +10000de2: 42ac cmp r4, r5 +10000de4: d3e4 bcc.n 10000db0 +10000de6: bd70 pop {r4, r5, r6, pc} +10000de8: 2000063c .word 0x2000063c +10000dec: 20000644 .word 0x20000644 + +10000df0 : +10000df0: 4b0d ldr r3, [pc, #52] @ (10000e28 ) +10000df2: 681a ldr r2, [r3, #0] +10000df4: f3ef 8110 mrs r1, PRIMASK +10000df8: b672 cpsid i +10000dfa: e8d2 cfcf ldaexb ip, [r2] +10000dfe: 2001 movs r0, #1 +10000e00: f1bc 0f00 cmp.w ip, #0 +10000e04: d1f9 bne.n 10000dfa +10000e06: e8c2 0f4c strexb ip, r0, [r2] +10000e0a: f1bc 0f00 cmp.w ip, #0 +10000e0e: d1f4 bne.n 10000dfa +10000e10: f3bf 8f5f dmb sy +10000e14: 2200 movs r2, #0 +10000e16: 681b ldr r3, [r3, #0] +10000e18: e8c3 2f8f stlb r2, [r3] +10000e1c: f381 8810 msr PRIMASK, r1 +10000e20: bf40 sev +10000e22: 2000 movs r0, #0 +10000e24: 2100 movs r1, #0 +10000e26: 4770 bx lr +10000e28: 20000864 .word 0x20000864 +10000e2c: 00000000 .word 0x00000000 + +10000e30 : +10000e30: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000e34: ed2d 8b02 vpush {d8} +10000e38: b085 sub sp, #20 +10000e3a: f3ef 8305 mrs r3, IPSR +10000e3e: b2db uxtb r3, r3 +10000e40: 3b10 subs r3, #16 +10000e42: 089a lsrs r2, r3, #2 +10000e44: bf18 it ne +10000e46: 2201 movne r2, #1 +10000e48: f04f 0101 mov.w r1, #1 +10000e4c: f003 0b03 and.w fp, r3, #3 +10000e50: bf18 it ne +10000e52: 4daf ldrne r5, [pc, #700] @ (10001110 ) +10000e54: 4baf ldr r3, [pc, #700] @ (10001114 ) +10000e56: bf08 it eq +10000e58: 4daf ldreq r5, [pc, #700] @ (10001118 ) +10000e5a: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000e5e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000e62: fa01 f20b lsl.w r2, r1, fp +10000e66: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000e6a: ed9f 8ba7 vldr d8, [pc, #668] @ 10001108 +10000e6e: 9201 str r2, [sp, #4] +10000e70: 605a str r2, [r3, #4] +10000e72: e02f b.n 10000ed4 +10000e74: 88b3 ldrh r3, [r6, #4] +10000e76: 041c lsls r4, r3, #16 +10000e78: f140 8093 bpl.w 10000fa2 +10000e7c: 79b3 ldrb r3, [r6, #6] +10000e7e: 2b00 cmp r3, #0 +10000e80: f040 80dd bne.w 1000103e +10000e84: f9b6 2008 ldrsh.w r2, [r6, #8] +10000e88: 2a00 cmp r2, #0 +10000e8a: f2c0 811e blt.w 100010ca +10000e8e: 6973 ldr r3, [r6, #20] +10000e90: eb02 0242 add.w r2, r2, r2, lsl #1 +10000e94: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000e98: e9d3 4702 ldrd r4, r7, [r3, #8] +10000e9c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000ea0: bf08 it eq +10000ea2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000ea6: d00e beq.n 10000ec6 +10000ea8: eb05 018b add.w r1, r5, fp, lsl #2 +10000eac: 6aab ldr r3, [r5, #40] @ 0x28 +10000eae: 690a ldr r2, [r1, #16] +10000eb0: 1ad2 subs r2, r2, r3 +10000eb2: 1ae3 subs r3, r4, r3 +10000eb4: 4293 cmp r3, r2 +10000eb6: d305 bcc.n 10000ec4 +10000eb8: 2301 movs r3, #1 +10000eba: 6a2a ldr r2, [r5, #32] +10000ebc: fa03 f30b lsl.w r3, r3, fp +10000ec0: 4213 tst r3, r2 +10000ec2: d100 bne.n 10000ec6 +10000ec4: 610c str r4, [r1, #16] +10000ec6: 4628 mov r0, r5 +10000ec8: f000 fba4 bl 10001614 +10000ecc: 42a0 cmp r0, r4 +10000ece: 41b9 sbcs r1, r7 +10000ed0: f2c0 80fb blt.w 100010ca +10000ed4: f9b6 3008 ldrsh.w r3, [r6, #8] +10000ed8: 9a01 ldr r2, [sp, #4] +10000eda: 2b00 cmp r3, #0 +10000edc: 9300 str r3, [sp, #0] +10000ede: 63ea str r2, [r5, #60] @ 0x3c +10000ee0: dbc8 blt.n 10000e74 +10000ee2: f8d6 8014 ldr.w r8, [r6, #20] +10000ee6: eb03 0943 add.w r9, r3, r3, lsl #1 +10000eea: 4628 mov r0, r5 +10000eec: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000ef0: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000ef4: f000 fb8e bl 10001614 +10000ef8: 42a0 cmp r0, r4 +10000efa: eb71 010a sbcs.w r1, r1, sl +10000efe: dbb9 blt.n 10000e74 +10000f00: f1ba 0f00 cmp.w sl, #0 +10000f04: f2c0 80c3 blt.w 1000108e +10000f08: e9d7 3104 ldrd r3, r1, [r7, #16] +10000f0c: 4a83 ldr r2, [pc, #524] @ (1000111c ) +10000f0e: 4293 cmp r3, r2 +10000f10: f000 80ed beq.w 100010ee +10000f14: 887a ldrh r2, [r7, #2] +10000f16: f9b6 0008 ldrsh.w r0, [r6, #8] +10000f1a: b292 uxth r2, r2 +10000f1c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000f20: 4798 blx r3 +10000f22: 4602 mov r2, r0 +10000f24: 460b mov r3, r1 +10000f26: ea52 0103 orrs.w r1, r2, r3 +10000f2a: f000 80b0 beq.w 1000108e +10000f2e: 2b00 cmp r3, #0 +10000f30: f280 80d1 bge.w 100010d6 +10000f34: ebb4 0e02 subs.w lr, r4, r2 +10000f38: eb6a 0a03 sbc.w sl, sl, r3 +10000f3c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000f40: e9c7 ea02 strd lr, sl, [r7, #8] +10000f44: 2b00 cmp r3, #0 +10000f46: db95 blt.n 10000e74 +10000f48: 6971 ldr r1, [r6, #20] +10000f4a: eb03 0243 add.w r2, r3, r3, lsl #1 +10000f4e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000f52: e9d2 7002 ldrd r7, r0, [r2, #8] +10000f56: 45be cmp lr, r7 +10000f58: eb7a 0c00 sbcs.w ip, sl, r0 +10000f5c: ea4f 0243 mov.w r2, r3, lsl #1 +10000f60: db88 blt.n 10000e74 +10000f62: 46b4 mov ip, r6 +10000f64: f82c 3f08 strh.w r3, [ip, #8]! +10000f68: e006 b.n 10000f78 +10000f6a: eb03 0043 add.w r0, r3, r3, lsl #1 +10000f6e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000f72: 005a lsls r2, r3, #1 +10000f74: e9d0 7002 ldrd r7, r0, [r0, #8] +10000f78: 45be cmp lr, r7 +10000f7a: 441a add r2, r3 +10000f7c: eb7a 0000 sbcs.w r0, sl, r0 +10000f80: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000f84: db04 blt.n 10000f90 +10000f86: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000f8a: 46a4 mov ip, r4 +10000f8c: 2b00 cmp r3, #0 +10000f8e: daec bge.n 10000f6a +10000f90: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000f94: 9b00 ldr r3, [sp, #0] +10000f96: f8ac 3000 strh.w r3, [ip] +10000f9a: 88b3 ldrh r3, [r6, #4] +10000f9c: 041c lsls r4, r3, #16 +10000f9e: f53f af6d bmi.w 10000e7c +10000fa2: 6933 ldr r3, [r6, #16] +10000fa4: f3ef 8210 mrs r2, PRIMASK +10000fa8: b672 cpsid i +10000faa: e8d3 0fcf ldaexb r0, [r3] +10000fae: 2101 movs r1, #1 +10000fb0: 2800 cmp r0, #0 +10000fb2: d1fa bne.n 10000faa +10000fb4: e8c3 1f40 strexb r0, r1, [r3] +10000fb8: 2800 cmp r0, #0 +10000fba: d1f6 bne.n 10000faa +10000fbc: f3bf 8f5f dmb sy +10000fc0: f64f 74ff movw r4, #65535 @ 0xffff +10000fc4: 88b0 ldrh r0, [r6, #4] +10000fc6: 2300 movs r3, #0 +10000fc8: 6931 ldr r1, [r6, #16] +10000fca: b200 sxth r0, r0 +10000fcc: 80b4 strh r4, [r6, #4] +10000fce: e8c1 3f8f stlb r3, [r1] +10000fd2: f382 8810 msr PRIMASK, r2 +10000fd6: 4298 cmp r0, r3 +10000fd8: f6ff af50 blt.w 10000e7c +10000fdc: 4607 mov r7, r0 +10000fde: 46a9 mov r9, r5 +10000fe0: 6974 ldr r4, [r6, #20] +10000fe2: f106 0808 add.w r8, r6, #8 +10000fe6: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000fea: eb04 03ce add.w r3, r4, lr, lsl #3 +10000fee: e9d3 5002 ldrd r5, r0, [r3, #8] +10000ff2: f9b6 3008 ldrsh.w r3, [r6, #8] +10000ff6: 46c4 mov ip, r8 +10000ff8: 2b00 cmp r3, #0 +10000ffa: db13 blt.n 10001024 +10000ffc: 46b2 mov sl, r6 +10000ffe: 9700 str r7, [sp, #0] +10001000: e004 b.n 1000100c +10001002: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10001006: 4694 mov ip, r2 +10001008: 2b00 cmp r3, #0 +1000100a: db09 blt.n 10001020 +1000100c: eb03 0643 add.w r6, r3, r3, lsl #1 +10001010: eb04 02c6 add.w r2, r4, r6, lsl #3 +10001014: e9d2 7102 ldrd r7, r1, [r2, #8] +10001018: 42bd cmp r5, r7 +1000101a: eb70 0101 sbcs.w r1, r0, r1 +1000101e: daf0 bge.n 10001002 +10001020: 4656 mov r6, sl +10001022: 9f00 ldr r7, [sp, #0] +10001024: f8ac 7000 strh.w r7, [ip] +10001028: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +1000102c: f824 303e strh.w r3, [r4, lr, lsl #3] +10001030: 2f00 cmp r7, #0 +10001032: dad8 bge.n 10000fe6 +10001034: 79b3 ldrb r3, [r6, #6] +10001036: 464d mov r5, r9 +10001038: 2b00 cmp r3, #0 +1000103a: f43f af23 beq.w 10000e84 +1000103e: 2300 movs r3, #0 +10001040: 71b3 strb r3, [r6, #6] +10001042: f9b6 3008 ldrsh.w r3, [r6, #8] +10001046: f106 0808 add.w r8, r6, #8 +1000104a: 1c58 adds r0, r3, #1 +1000104c: d03d beq.n 100010ca +1000104e: 461a mov r2, r3 +10001050: 6977 ldr r7, [r6, #20] +10001052: e003 b.n 1000105c +10001054: 4680 mov r8, r0 +10001056: 1c59 adds r1, r3, #1 +10001058: f43f af16 beq.w 10000e88 +1000105c: eb03 0143 add.w r1, r3, r3, lsl #1 +10001060: eb07 00c1 add.w r0, r7, r1, lsl #3 +10001064: f8b0 c002 ldrh.w ip, [r0, #2] +10001068: 461c mov r4, r3 +1000106a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +1000106e: 469e mov lr, r3 +10001070: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10001074: d0ee beq.n 10001054 +10001076: 4294 cmp r4, r2 +10001078: ed80 8b02 vstr d8, [r0, #8] +1000107c: d005 beq.n 1000108a +1000107e: f8a8 3000 strh.w r3, [r8] +10001082: 8932 ldrh r2, [r6, #8] +10001084: f827 2031 strh.w r2, [r7, r1, lsl #3] +10001088: 8134 strh r4, [r6, #8] +1000108a: 4672 mov r2, lr +1000108c: e7e3 b.n 10001056 +1000108e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10001092: 8133 strh r3, [r6, #8] +10001094: 6933 ldr r3, [r6, #16] +10001096: f3ef 8210 mrs r2, PRIMASK +1000109a: b672 cpsid i +1000109c: e8d3 0fcf ldaexb r0, [r3] +100010a0: 2101 movs r1, #1 +100010a2: 2800 cmp r0, #0 +100010a4: d1fa bne.n 1000109c +100010a6: e8c3 1f40 strexb r0, r1, [r3] +100010aa: 2800 cmp r0, #0 +100010ac: d1f6 bne.n 1000109c +100010ae: f3bf 8f5f dmb sy +100010b2: 8873 ldrh r3, [r6, #2] +100010b4: 6931 ldr r1, [r6, #16] +100010b6: f828 3039 strh.w r3, [r8, r9, lsl #3] +100010ba: 9b00 ldr r3, [sp, #0] +100010bc: 8073 strh r3, [r6, #2] +100010be: 2300 movs r3, #0 +100010c0: e8c1 3f8f stlb r3, [r1] +100010c4: f382 8810 msr PRIMASK, r2 +100010c8: e6d4 b.n 10000e74 +100010ca: bf40 sev +100010cc: b005 add sp, #20 +100010ce: ecbd 8b02 vpop {d8} +100010d2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100010d6: 4628 mov r0, r5 +100010d8: e9cd 2302 strd r2, r3, [sp, #8] +100010dc: f000 fa9a bl 10001614 +100010e0: 9a02 ldr r2, [sp, #8] +100010e2: 9b03 ldr r3, [sp, #12] +100010e4: eb10 0e02 adds.w lr, r0, r2 +100010e8: eb43 0a01 adc.w sl, r3, r1 +100010ec: e726 b.n 10000f3c +100010ee: 4608 mov r0, r1 +100010f0: 690b ldr r3, [r1, #16] +100010f2: 9102 str r1, [sp, #8] +100010f4: 4798 blx r3 +100010f6: 2800 cmp r0, #0 +100010f8: d0c9 beq.n 1000108e +100010fa: 9902 ldr r1, [sp, #8] +100010fc: e9d1 2300 ldrd r2, r3, [r1] +10001100: e711 b.n 10000f26 +10001102: bf00 nop +10001104: f3af 8000 nop.w +10001108: ffffffff .word 0xffffffff +1000110c: ffffffff .word 0xffffffff +10001110: 400b8000 .word 0x400b8000 +10001114: 20000844 .word 0x20000844 +10001118: 400b0000 .word 0x400b0000 +1000111c: 10000e31 .word 0x10000e31 + +10001120 : +10001120: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001124: 4c36 ldr r4, [pc, #216] @ (10001200 ) +10001126: 6925 ldr r5, [r4, #16] +10001128: b12d cbz r5, 10001136 +1000112a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000112e: 210a movs r1, #10 +10001130: 4834 ldr r0, [pc, #208] @ (10001204 ) +10001132: f7ff be31 b.w 10000d98 +10001136: f8df 80e4 ldr.w r8, [pc, #228] @ 1000121c +1000113a: 2103 movs r1, #3 +1000113c: 4640 mov r0, r8 +1000113e: f000 fa57 bl 100015f0 +10001142: 2603 movs r6, #3 +10001144: f8c4 800c str.w r8, [r4, #12] +10001148: f7ff fc48 bl 100009dc +1000114c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10001150: 4b2d ldr r3, [pc, #180] @ (10001208 ) +10001152: 7026 strb r6, [r4, #0] +10001154: 4403 add r3, r0 +10001156: 6123 str r3, [r4, #16] +10001158: f8dc 3000 ldr.w r3, [ip] +1000115c: 210f movs r1, #15 +1000115e: 7063 strb r3, [r4, #1] +10001160: 6963 ldr r3, [r4, #20] +10001162: 8061 strh r1, [r4, #2] +10001164: 831d strh r5, [r3, #24] +10001166: f04f 0504 mov.w r5, #4 +1000116a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +1000116e: f04f 0505 mov.w r5, #5 +10001172: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10001176: f04f 0506 mov.w r5, #6 +1000117a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +1000117e: f04f 0507 mov.w r5, #7 +10001182: 210e movs r1, #14 +10001184: f64f 72ff movw r2, #65535 @ 0xffff +10001188: 2708 movs r7, #8 +1000118a: f04f 0e0a mov.w lr, #10 +1000118e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10001192: f04f 0901 mov.w r9, #1 +10001196: f04f 0c0c mov.w ip, #12 +1000119a: f04f 0b02 mov.w fp, #2 +1000119e: f04f 0a09 mov.w sl, #9 +100011a2: 200d movs r0, #13 +100011a4: f04f 050b mov.w r5, #11 +100011a8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +100011ac: 4917 ldr r1, [pc, #92] @ (1000120c ) +100011ae: 80a2 strh r2, [r4, #4] +100011b0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +100011b4: 60a1 str r1, [r4, #8] +100011b6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +100011ba: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +100011be: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +100011c2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +100011c6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +100011ca: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +100011ce: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +100011d2: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +100011d6: 801a strh r2, [r3, #0] +100011d8: 4b0d ldr r3, [pc, #52] @ (10001210 ) +100011da: 4630 mov r0, r6 +100011dc: f8c8 7020 str.w r7, [r8, #32] +100011e0: 490c ldr r1, [pc, #48] @ (10001214 ) +100011e2: 60dc str r4, [r3, #12] +100011e4: f7ff fc50 bl 10000a88 +100011e8: 4649 mov r1, r9 +100011ea: 4630 mov r0, r6 +100011ec: f7ff fc36 bl 10000a5c +100011f0: 4b09 ldr r3, [pc, #36] @ (10001218 ) +100011f2: 210a movs r1, #10 +100011f4: 641f str r7, [r3, #64] @ 0x40 +100011f6: 4803 ldr r0, [pc, #12] @ (10001204 ) +100011f8: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100011fc: f7ff bdcc b.w 10000d98 +10001200: 200005fc .word 0x200005fc +10001204: 20000864 .word 0x20000864 +10001208: 200007c8 .word 0x200007c8 +1000120c: 0010ffff .word 0x0010ffff +10001210: 20000844 .word 0x20000844 +10001214: 10000e31 .word 0x10000e31 +10001218: 400b2000 .word 0x400b2000 +1000121c: 400b0000 .word 0x400b0000 + +10001220 : +10001220: 4601 mov r1, r0 +10001222: b5f0 push {r4, r5, r6, r7, lr} +10001224: 6900 ldr r0, [r0, #16] +10001226: f3ef 8710 mrs r7, PRIMASK +1000122a: b672 cpsid i +1000122c: e8d0 5fcf ldaexb r5, [r0] +10001230: 2401 movs r4, #1 +10001232: 2d00 cmp r5, #0 +10001234: d1fa bne.n 1000122c +10001236: e8c0 4f45 strexb r5, r4, [r0] +1000123a: 2d00 cmp r5, #0 +1000123c: d1f6 bne.n 1000122c +1000123e: f3bf 8f5f dmb sy +10001242: f9b1 e002 ldrsh.w lr, [r1, #2] +10001246: 694c ldr r4, [r1, #20] +10001248: eb0e 0c4e add.w ip, lr, lr, lsl #1 +1000124c: f1be 0f00 cmp.w lr, #0 +10001250: ea4f 05cc mov.w r5, ip, lsl #3 +10001254: 6908 ldr r0, [r1, #16] +10001256: eb04 0ccc add.w ip, r4, ip, lsl #3 +1000125a: db3c blt.n 100012d6 +1000125c: 5b66 ldrh r6, [r4, r5] +1000125e: 804e strh r6, [r1, #2] +10001260: 2600 movs r6, #0 +10001262: e8c0 6f8f stlb r6, [r0] +10001266: f387 8810 msr PRIMASK, r7 +1000126a: f8bc 0002 ldrh.w r0, [ip, #2] +1000126e: e9cc 2302 strd r2, r3, [ip, #8] +10001272: 3001 adds r0, #1 +10001274: f3c0 000e ubfx r0, r0, #0, #15 +10001278: 2801 cmp r0, #1 +1000127a: bf38 it cc +1000127c: 2001 movcc r0, #1 +1000127e: 9b05 ldr r3, [sp, #20] +10001280: f8ac 0002 strh.w r0, [ip, #2] +10001284: f8cc 3010 str.w r3, [ip, #16] +10001288: 9b06 ldr r3, [sp, #24] +1000128a: ea40 400e orr.w r0, r0, lr, lsl #16 +1000128e: f8cc 3014 str.w r3, [ip, #20] +10001292: 690b ldr r3, [r1, #16] +10001294: f3ef 8210 mrs r2, PRIMASK +10001298: b672 cpsid i +1000129a: e8d3 cfcf ldaexb ip, [r3] +1000129e: 2701 movs r7, #1 +100012a0: f1bc 0f00 cmp.w ip, #0 +100012a4: d1f9 bne.n 1000129a +100012a6: e8c3 7f4c strexb ip, r7, [r3] +100012aa: f1bc 0f00 cmp.w ip, #0 +100012ae: d1f4 bne.n 1000129a +100012b0: f3bf 8f5f dmb sy +100012b4: 888b ldrh r3, [r1, #4] +100012b6: 5363 strh r3, [r4, r5] +100012b8: f8a1 e004 strh.w lr, [r1, #4] +100012bc: 690b ldr r3, [r1, #16] +100012be: e8c3 6f8f stlb r6, [r3] +100012c2: f382 8810 msr PRIMASK, r2 +100012c6: 2201 movs r2, #1 +100012c8: 68cb ldr r3, [r1, #12] +100012ca: 7809 ldrb r1, [r1, #0] +100012cc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +100012d0: 408a lsls r2, r1 +100012d2: 605a str r2, [r3, #4] +100012d4: bdf0 pop {r4, r5, r6, r7, pc} +100012d6: 2300 movs r3, #0 +100012d8: e8c0 3f8f stlb r3, [r0] +100012dc: f387 8810 msr PRIMASK, r7 +100012e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +100012e4: bdf0 pop {r4, r5, r6, r7, pc} +100012e6: bf00 nop + +100012e8 : +100012e8: 4603 mov r3, r0 +100012ea: 8940 ldrh r0, [r0, #10] +100012ec: ebb0 4f21 cmp.w r0, r1, asr #16 +100012f0: dd37 ble.n 10001362 +100012f2: 6958 ldr r0, [r3, #20] +100012f4: 140a asrs r2, r1, #16 +100012f6: eb02 0242 add.w r2, r2, r2, lsl #1 +100012fa: b510 push {r4, lr} +100012fc: eb00 00c2 add.w r0, r0, r2, lsl #3 +10001300: 691c ldr r4, [r3, #16] +10001302: f3ef 8c10 mrs ip, PRIMASK +10001306: b672 cpsid i +10001308: e8d4 efcf ldaexb lr, [r4] +1000130c: 2201 movs r2, #1 +1000130e: f1be 0f00 cmp.w lr, #0 +10001312: d1f9 bne.n 10001308 +10001314: e8c4 2f4e strexb lr, r2, [r4] +10001318: f1be 0f00 cmp.w lr, #0 +1000131c: d1f4 bne.n 10001308 +1000131e: f3bf 8f5f dmb sy +10001322: 8842 ldrh r2, [r0, #2] +10001324: b289 uxth r1, r1 +10001326: b292 uxth r2, r2 +10001328: 428a cmp r2, r1 +1000132a: d007 beq.n 1000133c +1000132c: 2200 movs r2, #0 +1000132e: 691b ldr r3, [r3, #16] +10001330: e8c3 2f8f stlb r2, [r3] +10001334: f38c 8810 msr PRIMASK, ip +10001338: 2000 movs r0, #0 +1000133a: bd10 pop {r4, pc} +1000133c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10001340: 8042 strh r2, [r0, #2] +10001342: 2101 movs r1, #1 +10001344: 2200 movs r2, #0 +10001346: 6918 ldr r0, [r3, #16] +10001348: 7199 strb r1, [r3, #6] +1000134a: e8c0 2f8f stlb r2, [r0] +1000134e: f38c 8810 msr PRIMASK, ip +10001352: 781c ldrb r4, [r3, #0] +10001354: 68da ldr r2, [r3, #12] +10001356: 4608 mov r0, r1 +10001358: f502 5301 add.w r3, r2, #8256 @ 0x2040 +1000135c: 40a1 lsls r1, r4 +1000135e: 6059 str r1, [r3, #4] +10001360: bd10 pop {r4, pc} +10001362: 2000 movs r0, #0 +10001364: 4770 bx lr +10001366: bf00 nop + +10001368 : +10001368: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000136c: b082 sub sp, #8 +1000136e: 4604 mov r4, r0 +10001370: 460e mov r6, r1 +10001372: f000 f957 bl 10001624 +10001376: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000137a: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +1000137e: 1824 adds r4, r4, r0 +10001380: eb46 0601 adc.w r6, r6, r1 +10001384: 42a2 cmp r2, r4 +10001386: eb73 0106 sbcs.w r1, r3, r6 +1000138a: bf3c itt cc +1000138c: 4614 movcc r4, r2 +1000138e: 461e movcc r6, r3 +10001390: 1fa5 subs r5, r4, #6 +10001392: f146 37ff adc.w r7, r6, #4294967295 @ 0xffffffff +10001396: 42ac cmp r4, r5 +10001398: eb76 0307 sbcs.w r3, r6, r7 +1000139c: bf3c itt cc +1000139e: 2500 movcc r5, #0 +100013a0: 462f movcc r7, r5 +100013a2: f000 f93f bl 10001624 +100013a6: 1a28 subs r0, r5, r0 +100013a8: eb67 0c01 sbc.w ip, r7, r1 +100013ac: 2801 cmp r0, #1 +100013ae: f17c 0c00 sbcs.w ip, ip, #0 +100013b2: da06 bge.n 100013c2 +100013b4: 4620 mov r0, r4 +100013b6: 4631 mov r1, r6 +100013b8: b002 add sp, #8 +100013ba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100013be: f000 b969 b.w 10001694 +100013c2: f000 f92f bl 10001624 +100013c6: 4285 cmp r5, r0 +100013c8: eb67 0101 sbc.w r1, r7, r1 +100013cc: 2900 cmp r1, #0 +100013ce: db0a blt.n 100013e6 +100013d0: 2100 movs r1, #0 +100013d2: 4b17 ldr r3, [pc, #92] @ (10001430 ) +100013d4: 462a mov r2, r5 +100013d6: 9300 str r3, [sp, #0] +100013d8: 4816 ldr r0, [pc, #88] @ (10001434 ) +100013da: 463b mov r3, r7 +100013dc: 9101 str r1, [sp, #4] +100013de: f7ff ff1f bl 10001220 +100013e2: 3001 adds r0, #1 +100013e4: d0e6 beq.n 100013b4 +100013e6: f04f 0c00 mov.w ip, #0 +100013ea: 4a13 ldr r2, [pc, #76] @ (10001438 ) +100013ec: 4913 ldr r1, [pc, #76] @ (1000143c ) +100013ee: 6a53 ldr r3, [r2, #36] @ 0x24 +100013f0: 429f cmp r7, r3 +100013f2: d804 bhi.n 100013fe +100013f4: 6a90 ldr r0, [r2, #40] @ 0x28 +100013f6: 42a8 cmp r0, r5 +100013f8: d2dc bcs.n 100013b4 +100013fa: 429f cmp r7, r3 +100013fc: d1da bne.n 100013b4 +100013fe: 680b ldr r3, [r1, #0] +10001400: f3ef 8010 mrs r0, PRIMASK +10001404: b672 cpsid i +10001406: e8d3 8fcf ldaexb r8, [r3] +1000140a: f05f 0e01 movs.w lr, #1 +1000140e: f1b8 0f00 cmp.w r8, #0 +10001412: d1f8 bne.n 10001406 +10001414: e8c3 ef48 strexb r8, lr, [r3] +10001418: f1b8 0f00 cmp.w r8, #0 +1000141c: d1f3 bne.n 10001406 +1000141e: f3bf 8f5f dmb sy +10001422: 680b ldr r3, [r1, #0] +10001424: e8c3 cf8f stlb ip, [r3] +10001428: f380 8810 msr PRIMASK, r0 +1000142c: bf20 wfe +1000142e: e7de b.n 100013ee +10001430: 10000df1 .word 0x10000df1 +10001434: 200005fc .word 0x200005fc +10001438: 400b0000 .word 0x400b0000 +1000143c: 20000864 .word 0x20000864 + +10001440 : +10001440: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10001444: b082 sub sp, #8 +10001446: 4606 mov r6, r0 +10001448: f000 f8ec bl 10001624 +1000144c: f44f 737a mov.w r3, #1000 @ 0x3e8 +10001450: 4604 mov r4, r0 +10001452: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10001456: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +1000145a: fbe6 4103 umlal r4, r1, r6, r3 +1000145e: 42a0 cmp r0, r4 +10001460: eb72 0301 sbcs.w r3, r2, r1 +10001464: bf3a itte cc +10001466: 4604 movcc r4, r0 +10001468: 4615 movcc r5, r2 +1000146a: 460d movcs r5, r1 +1000146c: 1fa6 subs r6, r4, #6 +1000146e: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10001472: 42b4 cmp r4, r6 +10001474: eb75 0307 sbcs.w r3, r5, r7 +10001478: bf3c itt cc +1000147a: 2600 movcc r6, #0 +1000147c: 4637 movcc r7, r6 +1000147e: f000 f8d1 bl 10001624 +10001482: 1a30 subs r0, r6, r0 +10001484: eb67 0101 sbc.w r1, r7, r1 +10001488: 2801 cmp r0, #1 +1000148a: f171 0100 sbcs.w r1, r1, #0 +1000148e: da06 bge.n 1000149e +10001490: 4620 mov r0, r4 +10001492: 4629 mov r1, r5 +10001494: b002 add sp, #8 +10001496: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +1000149a: f000 b8fb b.w 10001694 +1000149e: f000 f8c1 bl 10001624 +100014a2: 4286 cmp r6, r0 +100014a4: eb67 0101 sbc.w r1, r7, r1 +100014a8: 2900 cmp r1, #0 +100014aa: db0a blt.n 100014c2 +100014ac: 2100 movs r1, #0 +100014ae: 4b17 ldr r3, [pc, #92] @ (1000150c ) +100014b0: 4632 mov r2, r6 +100014b2: 9300 str r3, [sp, #0] +100014b4: 4816 ldr r0, [pc, #88] @ (10001510 ) +100014b6: 463b mov r3, r7 +100014b8: 9101 str r1, [sp, #4] +100014ba: f7ff feb1 bl 10001220 +100014be: 3001 adds r0, #1 +100014c0: d0e6 beq.n 10001490 +100014c2: f04f 0c00 mov.w ip, #0 +100014c6: 4a13 ldr r2, [pc, #76] @ (10001514 ) +100014c8: 4913 ldr r1, [pc, #76] @ (10001518 ) +100014ca: 6a53 ldr r3, [r2, #36] @ 0x24 +100014cc: 429f cmp r7, r3 +100014ce: d804 bhi.n 100014da +100014d0: 6a90 ldr r0, [r2, #40] @ 0x28 +100014d2: 42b0 cmp r0, r6 +100014d4: d2dc bcs.n 10001490 +100014d6: 429f cmp r7, r3 +100014d8: d1da bne.n 10001490 +100014da: 680b ldr r3, [r1, #0] +100014dc: f3ef 8010 mrs r0, PRIMASK +100014e0: b672 cpsid i +100014e2: e8d3 8fcf ldaexb r8, [r3] +100014e6: f05f 0e01 movs.w lr, #1 +100014ea: f1b8 0f00 cmp.w r8, #0 +100014ee: d1f8 bne.n 100014e2 +100014f0: e8c3 ef48 strexb r8, lr, [r3] +100014f4: f1b8 0f00 cmp.w r8, #0 +100014f8: d1f3 bne.n 100014e2 +100014fa: f3bf 8f5f dmb sy +100014fe: 680b ldr r3, [r1, #0] +10001500: e8c3 cf8f stlb ip, [r3] +10001504: f380 8810 msr PRIMASK, r0 +10001508: bf20 wfe +1000150a: e7de b.n 100014ca +1000150c: 10000df1 .word 0x10000df1 +10001510: 200005fc .word 0x200005fc +10001514: 400b0000 .word 0x400b0000 +10001518: 20000864 .word 0x20000864 + +1000151c : +1000151c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10001520: 4606 mov r6, r0 +10001522: 460d mov r5, r1 +10001524: b083 sub sp, #12 +10001526: f3ef 8405 mrs r4, IPSR +1000152a: b2e4 uxtb r4, r4 +1000152c: b13c cbz r4, 1000153e +1000152e: 4b2d ldr r3, [pc, #180] @ (100015e4 ) +10001530: 6a5a ldr r2, [r3, #36] @ 0x24 +10001532: 42aa cmp r2, r5 +10001534: d21c bcs.n 10001570 +10001536: 2000 movs r0, #0 +10001538: b003 add sp, #12 +1000153a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +1000153e: 4f2a ldr r7, [pc, #168] @ (100015e8 ) +10001540: f8d7 900c ldr.w r9, [r7, #12] +10001544: f897 8000 ldrb.w r8, [r7] +10001548: 4648 mov r0, r9 +1000154a: f000 f863 bl 10001614 +1000154e: f108 0804 add.w r8, r8, #4 +10001552: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10001556: 1a1b subs r3, r3, r0 +10001558: 1a30 subs r0, r6, r0 +1000155a: eb65 0101 sbc.w r1, r5, r1 +1000155e: 4298 cmp r0, r3 +10001560: f171 0100 sbcs.w r1, r1, #0 +10001564: db10 blt.n 10001588 +10001566: bf20 wfe +10001568: 4b1e ldr r3, [pc, #120] @ (100015e4 ) +1000156a: 6a5a ldr r2, [r3, #36] @ 0x24 +1000156c: 42aa cmp r2, r5 +1000156e: d3e2 bcc.n 10001536 +10001570: bf14 ite ne +10001572: 2401 movne r4, #1 +10001574: 2400 moveq r4, #0 +10001576: 6a9b ldr r3, [r3, #40] @ 0x28 +10001578: 42b3 cmp r3, r6 +1000157a: bf34 ite cc +1000157c: 4620 movcc r0, r4 +1000157e: f044 0001 orrcs.w r0, r4, #1 +10001582: b003 add sp, #12 +10001584: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10001588: f000 f84c bl 10001624 +1000158c: 4286 cmp r6, r0 +1000158e: eb65 0101 sbc.w r1, r5, r1 +10001592: 2900 cmp r1, #0 +10001594: db14 blt.n 100015c0 +10001596: 4b15 ldr r3, [pc, #84] @ (100015ec ) +10001598: 4638 mov r0, r7 +1000159a: e9cd 3400 strd r3, r4, [sp] +1000159e: 4632 mov r2, r6 +100015a0: 462b mov r3, r5 +100015a2: f7ff fe3d bl 10001220 +100015a6: 1e01 subs r1, r0, #0 +100015a8: dd0a ble.n 100015c0 +100015aa: 4b0e ldr r3, [pc, #56] @ (100015e4 ) +100015ac: 6a5a ldr r2, [r3, #36] @ 0x24 +100015ae: 42aa cmp r2, r5 +100015b0: d316 bcc.n 100015e0 +100015b2: 6a9b ldr r3, [r3, #40] @ 0x28 +100015b4: 42b3 cmp r3, r6 +100015b6: d311 bcc.n 100015dc +100015b8: 480b ldr r0, [pc, #44] @ (100015e8 ) +100015ba: f7ff fe95 bl 100012e8 +100015be: e7b6 b.n 1000152e +100015c0: 4b08 ldr r3, [pc, #32] @ (100015e4 ) +100015c2: 6a5c ldr r4, [r3, #36] @ 0x24 +100015c4: 42ac cmp r4, r5 +100015c6: d3b6 bcc.n 10001536 +100015c8: 1b64 subs r4, r4, r5 +100015ca: bf18 it ne +100015cc: 2401 movne r4, #1 +100015ce: 6a9b ldr r3, [r3, #40] @ 0x28 +100015d0: 42b3 cmp r3, r6 +100015d2: bf34 ite cc +100015d4: 4620 movcc r0, r4 +100015d6: f044 0001 orrcs.w r0, r4, #1 +100015da: e7ad b.n 10001538 +100015dc: 42aa cmp r2, r5 +100015de: d1eb bne.n 100015b8 +100015e0: bf20 wfe +100015e2: e7e9 b.n 100015b8 +100015e4: 400b0000 .word 0x400b0000 +100015e8: 200005fc .word 0x200005fc +100015ec: 10000df1 .word 0x10000df1 + +100015f0 : +100015f0: b410 push {r4} +100015f2: 4b05 ldr r3, [pc, #20] @ (10001608 ) +100015f4: 4c05 ldr r4, [pc, #20] @ (1000160c ) +100015f6: 4a06 ldr r2, [pc, #24] @ (10001610 ) +100015f8: 42a0 cmp r0, r4 +100015fa: bf14 ite ne +100015fc: 4618 movne r0, r3 +100015fe: 1c58 addeq r0, r3, #1 +10001600: f85d 4b04 ldr.w r4, [sp], #4 +10001604: f7ff b9be b.w 10000984 +10001608: 200007f0 .word 0x200007f0 +1000160c: 400b8000 .word 0x400b8000 +10001610: 10003f30 .word 0x10003f30 + +10001614 : +10001614: 4603 mov r3, r0 +10001616: 6a41 ldr r1, [r0, #36] @ 0x24 +10001618: 460a mov r2, r1 +1000161a: 6a98 ldr r0, [r3, #40] @ 0x28 +1000161c: 6a59 ldr r1, [r3, #36] @ 0x24 +1000161e: 428a cmp r2, r1 +10001620: d1fa bne.n 10001618 +10001622: 4770 bx lr + +10001624 : +10001624: 4b03 ldr r3, [pc, #12] @ (10001634 ) +10001626: 6a59 ldr r1, [r3, #36] @ 0x24 +10001628: 460a mov r2, r1 +1000162a: 6a98 ldr r0, [r3, #40] @ 0x28 +1000162c: 6a59 ldr r1, [r3, #36] @ 0x24 +1000162e: 4291 cmp r1, r2 +10001630: d1fa bne.n 10001628 +10001632: 4770 bx lr +10001634: 400b0000 .word 0x400b0000 + +10001638 : +10001638: b430 push {r4, r5} +1000163a: 4a15 ldr r2, [pc, #84] @ (10001690 ) +1000163c: 6a53 ldr r3, [r2, #36] @ 0x24 +1000163e: 469c mov ip, r3 +10001640: 6a94 ldr r4, [r2, #40] @ 0x28 +10001642: 6a53 ldr r3, [r2, #36] @ 0x24 +10001644: 4563 cmp r3, ip +10001646: d1fa bne.n 1000163e +10001648: 1902 adds r2, r0, r4 +1000164a: 4159 adcs r1, r3 +1000164c: f04f 0500 mov.w r5, #0 +10001650: bf28 it cs +10001652: 2501 movcs r5, #1 +10001654: 4b0e ldr r3, [pc, #56] @ (10001690 ) +10001656: 6a5b ldr r3, [r3, #36] @ 0x24 +10001658: b1b5 cbz r5, 10001688 +1000165a: 1c5a adds r2, r3, #1 +1000165c: bf08 it eq +1000165e: 461a moveq r2, r3 +10001660: d008 beq.n 10001674 +10001662: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10001666: 460a mov r2, r1 +10001668: 4809 ldr r0, [pc, #36] @ (10001690 ) +1000166a: 6a43 ldr r3, [r0, #36] @ 0x24 +1000166c: 428b cmp r3, r1 +1000166e: d3fc bcc.n 1000166a +10001670: 428b cmp r3, r1 +10001672: d107 bne.n 10001684 +10001674: 4906 ldr r1, [pc, #24] @ (10001690 ) +10001676: e002 b.n 1000167e +10001678: 6a48 ldr r0, [r1, #36] @ 0x24 +1000167a: 4298 cmp r0, r3 +1000167c: d102 bne.n 10001684 +1000167e: 6a88 ldr r0, [r1, #40] @ 0x28 +10001680: 4290 cmp r0, r2 +10001682: d3f9 bcc.n 10001678 +10001684: bc30 pop {r4, r5} +10001686: 4770 bx lr +10001688: 4299 cmp r1, r3 +1000168a: d8ed bhi.n 10001668 +1000168c: e7f0 b.n 10001670 +1000168e: bf00 nop +10001690: 400b0000 .word 0x400b0000 + +10001694 : +10001694: 4a07 ldr r2, [pc, #28] @ (100016b4 ) +10001696: 6a53 ldr r3, [r2, #36] @ 0x24 +10001698: 4299 cmp r1, r3 +1000169a: d8fc bhi.n 10001696 +1000169c: 4299 cmp r1, r3 +1000169e: d107 bne.n 100016b0 +100016a0: 4b04 ldr r3, [pc, #16] @ (100016b4 ) +100016a2: e002 b.n 100016aa +100016a4: 6a5a ldr r2, [r3, #36] @ 0x24 +100016a6: 4291 cmp r1, r2 +100016a8: d102 bne.n 100016b0 +100016aa: 6a9a ldr r2, [r3, #40] @ 0x28 +100016ac: 4290 cmp r0, r2 +100016ae: d8f9 bhi.n 100016a4 +100016b0: 4770 bx lr +100016b2: bf00 nop +100016b4: 400b0000 .word 0x400b0000 + +100016b8 : +100016b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100016ba: 4605 mov r5, r0 +100016bc: 2006 movs r0, #6 +100016be: 460e mov r6, r1 +100016c0: f000 f8e4 bl 1000188c +100016c4: 2800 cmp r0, #0 +100016c6: d042 beq.n 1000174e +100016c8: 4a35 ldr r2, [pc, #212] @ (100017a0 ) +100016ca: 4836 ldr r0, [pc, #216] @ (100017a4 ) +100016cc: 4295 cmp r5, r2 +100016ce: bf14 ite ne +100016d0: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +100016d4: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +100016d8: 4b33 ldr r3, [pc, #204] @ (100017a8 ) +100016da: 4934 ldr r1, [pc, #208] @ (100017ac ) +100016dc: 6002 str r2, [r0, #0] +100016de: 601a str r2, [r3, #0] +100016e0: 688c ldr r4, [r1, #8] +100016e2: ea32 0404 bics.w r4, r2, r4 +100016e6: d1fb bne.n 100016e0 +100016e8: 4b2d ldr r3, [pc, #180] @ (100017a0 ) +100016ea: f44f 7180 mov.w r1, #256 @ 0x100 +100016ee: 1aeb subs r3, r5, r3 +100016f0: fab3 f383 clz r3, r3 +100016f4: 4a2e ldr r2, [pc, #184] @ (100017b0 ) +100016f6: 095b lsrs r3, r3, #5 +100016f8: 2006 movs r0, #6 +100016fa: f822 1013 strh.w r1, [r2, r3, lsl #1] +100016fe: f000 f8c5 bl 1000188c +10001702: 00c3 lsls r3, r0, #3 +10001704: fbb3 f3f6 udiv r3, r3, r6 +10001708: 3301 adds r3, #1 +1000170a: 09da lsrs r2, r3, #7 +1000170c: d120 bne.n 10001750 +1000170e: 2640 movs r6, #64 @ 0x40 +10001710: 2101 movs r1, #1 +10001712: 6269 str r1, [r5, #36] @ 0x24 +10001714: 62aa str r2, [r5, #40] @ 0x28 +10001716: 6b2f ldr r7, [r5, #48] @ 0x30 +10001718: 07fb lsls r3, r7, #31 +1000171a: d422 bmi.n 10001762 +1000171c: 462b mov r3, r5 +1000171e: 2200 movs r2, #0 +10001720: f853 1f2c ldr.w r1, [r3, #44]! +10001724: 2006 movs r0, #6 +10001726: f503 5480 add.w r4, r3, #4096 @ 0x1000 +1000172a: 6022 str r2, [r4, #0] +1000172c: 632f str r7, [r5, #48] @ 0x30 +1000172e: f000 f8ad bl 1000188c +10001732: f240 3101 movw r1, #769 @ 0x301 +10001736: 2203 movs r2, #3 +10001738: 0080 lsls r0, r0, #2 +1000173a: fbb0 f0f6 udiv r0, r0, r6 +1000173e: 6aeb ldr r3, [r5, #44] @ 0x2c +10001740: f083 0370 eor.w r3, r3, #112 @ 0x70 +10001744: f003 037e and.w r3, r3, #126 @ 0x7e +10001748: 6023 str r3, [r4, #0] +1000174a: 6329 str r1, [r5, #48] @ 0x30 +1000174c: 64aa str r2, [r5, #72] @ 0x48 +1000174e: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001750: f64f 71fe movw r1, #65534 @ 0xfffe +10001754: 428a cmp r2, r1 +10001756: d91b bls.n 10001790 +10001758: 4622 mov r2, r4 +1000175a: f64f 71ff movw r1, #65535 @ 0xffff +1000175e: 4e15 ldr r6, [pc, #84] @ (100017b4 ) +10001760: e7d7 b.n 10001712 +10001762: f240 3201 movw r2, #769 @ 0x301 +10001766: f505 5340 add.w r3, r5, #12288 @ 0x3000 +1000176a: 631a str r2, [r3, #48] @ 0x30 +1000176c: 6a6b ldr r3, [r5, #36] @ 0x24 +1000176e: 6aac ldr r4, [r5, #40] @ 0x28 +10001770: 2006 movs r0, #6 +10001772: eb04 1483 add.w r4, r4, r3, lsl #6 +10001776: f000 f889 bl 1000188c +1000177a: 4b0f ldr r3, [pc, #60] @ (100017b8 ) +1000177c: 02a4 lsls r4, r4, #10 +1000177e: fba3 2300 umull r2, r3, r3, r0 +10001782: 0adb lsrs r3, r3, #11 +10001784: 2100 movs r1, #0 +10001786: fbb4 f0f3 udiv r0, r4, r3 +1000178a: f7ff ff55 bl 10001638 +1000178e: e7c5 b.n 1000171c +10001790: f3c3 0345 ubfx r3, r3, #1, #6 +10001794: 4611 mov r1, r2 +10001796: eb03 1682 add.w r6, r3, r2, lsl #6 +1000179a: 461a mov r2, r3 +1000179c: e7b9 b.n 10001712 +1000179e: bf00 nop +100017a0: 40078000 .word 0x40078000 +100017a4: 40022000 .word 0x40022000 +100017a8: 40023000 .word 0x40023000 +100017ac: 40020000 .word 0x40020000 +100017b0: 20000868 .word 0x20000868 +100017b4: 003fffc0 .word 0x003fffc0 +100017b8: 8f2b7b75 .word 0x8f2b7b75 + +100017bc : +100017bc: eb00 0c40 add.w ip, r0, r0, lsl #1 +100017c0: ea4f 0c8c mov.w ip, ip, lsl #2 +100017c4: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +100017c8: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +100017cc: b5f0 push {r4, r5, r6, r7, lr} +100017ce: 4616 mov r6, r2 +100017d0: f8dc 2004 ldr.w r2, [ip, #4] +100017d4: 1f05 subs r5, r0, #4 +100017d6: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +100017da: bf38 it cc +100017dc: f44f 3280 movcc.w r2, #65536 @ 0x10000 +100017e0: b2ed uxtb r5, r5 +100017e2: bf38 it cc +100017e4: f8cc 2004 strcc.w r2, [ip, #4] +100017e8: 2d01 cmp r5, #1 +100017ea: d92a bls.n 10001842 +100017ec: f44f 6700 mov.w r7, #2048 @ 0x800 +100017f0: 4c25 ldr r4, [pc, #148] @ (10001888 ) +100017f2: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100017f6: 6017 str r7, [r2, #0] +100017f8: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100017fc: b9b2 cbnz r2, 1000182c +100017fe: f8dc 2000 ldr.w r2, [ip] +10001802: 2d01 cmp r5, #1 +10001804: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001808: f002 02e0 and.w r2, r2, #224 @ 0xe0 +1000180c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001810: 6032 str r2, [r6, #0] +10001812: d92a bls.n 1000186a +10001814: f44f 6100 mov.w r1, #2048 @ 0x800 +10001818: f844 3020 str.w r3, [r4, r0, lsl #2] +1000181c: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001820: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +10001824: 6011 str r1, [r2, #0] +10001826: f8cc 3004 str.w r3, [ip, #4] +1000182a: bdf0 pop {r4, r5, r6, r7, pc} +1000182c: 6967 ldr r7, [r4, #20] +1000182e: fbb7 fef2 udiv lr, r7, r2 +10001832: f10e 0e01 add.w lr, lr, #1 +10001836: eb0e 0e4e add.w lr, lr, lr, lsl #1 +1000183a: f1be 0e03 subs.w lr, lr, #3 +1000183e: d2fc bcs.n 1000183a +10001840: e7dd b.n 100017fe +10001842: 2901 cmp r1, #1 +10001844: d1d2 bne.n 100017ec +10001846: 2403 movs r4, #3 +10001848: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000184c: 6014 str r4, [r2, #0] +1000184e: f8dc 2008 ldr.w r2, [ip, #8] +10001852: 07d2 lsls r2, r2, #31 +10001854: d5fb bpl.n 1000184e +10001856: f8dc 2000 ldr.w r2, [ip] +1000185a: 4c0b ldr r4, [pc, #44] @ (10001888 ) +1000185c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001860: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001864: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001868: 6032 str r2, [r6, #0] +1000186a: 2201 movs r2, #1 +1000186c: f8dc 5000 ldr.w r5, [ip] +10001870: 404d eors r5, r1 +10001872: f005 0503 and.w r5, r5, #3 +10001876: 6035 str r5, [r6, #0] +10001878: fa02 f101 lsl.w r1, r2, r1 +1000187c: f8dc 2008 ldr.w r2, [ip, #8] +10001880: 420a tst r2, r1 +10001882: d0fb beq.n 1000187c +10001884: e7c6 b.n 10001814 +10001886: bf00 nop +10001888: 200007f4 .word 0x200007f4 + +1000188c : +1000188c: 4b01 ldr r3, [pc, #4] @ (10001894 ) +1000188e: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001892: 4770 bx lr +10001894: 200007f4 .word 0x200007f4 + +10001898 : +10001898: b470 push {r4, r5, r6} +1000189a: 9d03 ldr r5, [sp, #12] +1000189c: 6804 ldr r4, [r0, #0] +1000189e: 032d lsls r5, r5, #12 +100018a0: ea45 4503 orr.w r5, r5, r3, lsl #16 +100018a4: 4b1b ldr r3, [pc, #108] @ (10001914 ) +100018a6: 2c00 cmp r4, #0 +100018a8: fbb3 f3f1 udiv r3, r3, r1 +100018ac: fbb2 f6f3 udiv r6, r2, r3 +100018b0: db1f blt.n 100018f2 +100018b2: 4a19 ldr r2, [pc, #100] @ (10001918 ) +100018b4: 4b19 ldr r3, [pc, #100] @ (1000191c ) +100018b6: 4290 cmp r0, r2 +100018b8: bf14 ite ne +100018ba: f44f 4280 movne.w r2, #16384 @ 0x4000 +100018be: f44f 4200 moveq.w r2, #32768 @ 0x8000 +100018c2: 4c17 ldr r4, [pc, #92] @ (10001920 ) +100018c4: 601a str r2, [r3, #0] +100018c6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100018ca: 601a str r2, [r3, #0] +100018cc: 68a3 ldr r3, [r4, #8] +100018ce: ea32 0303 bics.w r3, r2, r3 +100018d2: d1fb bne.n 100018cc +100018d4: 2221 movs r2, #33 @ 0x21 +100018d6: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100018da: 3304 adds r3, #4 +100018dc: 6001 str r1, [r0, #0] +100018de: 6086 str r6, [r0, #8] +100018e0: 601a str r2, [r3, #0] +100018e2: 6802 ldr r2, [r0, #0] +100018e4: 2a00 cmp r2, #0 +100018e6: dafc bge.n 100018e2 +100018e8: 2208 movs r2, #8 +100018ea: 60c5 str r5, [r0, #12] +100018ec: 601a str r2, [r3, #0] +100018ee: bc70 pop {r4, r5, r6} +100018f0: 4770 bx lr +100018f2: 6803 ldr r3, [r0, #0] +100018f4: f003 033f and.w r3, r3, #63 @ 0x3f +100018f8: 428b cmp r3, r1 +100018fa: d1da bne.n 100018b2 +100018fc: 6883 ldr r3, [r0, #8] +100018fe: f3c3 030b ubfx r3, r3, #0, #12 +10001902: 42b3 cmp r3, r6 +10001904: d1d5 bne.n 100018b2 +10001906: 68c3 ldr r3, [r0, #12] +10001908: f403 23ee and.w r3, r3, #487424 @ 0x77000 +1000190c: 42ab cmp r3, r5 +1000190e: d1d0 bne.n 100018b2 +10001910: e7ed b.n 100018ee +10001912: bf00 nop +10001914: 00b71b00 .word 0x00b71b00 +10001918: 40058000 .word 0x40058000 +1000191c: 40022000 .word 0x40022000 +10001920: 40020000 .word 0x40020000 + +10001924 : +10001924: 2301 movs r3, #1 +10001926: eb00 0040 add.w r0, r0, r0, lsl #1 +1000192a: 0080 lsls r0, r0, #2 +1000192c: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001930: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001934: 6041 str r1, [r0, #4] +10001936: 6003 str r3, [r0, #0] +10001938: 4770 bx lr +1000193a: bf00 nop + +1000193c : +1000193c: 2300 movs r3, #0 +1000193e: 8adb ldrh r3, [r3, #22] +10001940: 2200 movs r2, #0 +10001942: e842 f200 tt r2, r2 +10001946: 0252 lsls r2, r2, #9 +10001948: d401 bmi.n 1000194e +1000194a: 2110 movs r1, #16 +1000194c: 4718 bx r3 +1000194e: 2104 movs r1, #4 +10001950: 4718 bx r3 +10001952: bf00 nop + +10001954 : +10001954: 4a03 ldr r2, [pc, #12] @ (10001964 ) +10001956: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +1000195a: 2b00 cmp r3, #0 +1000195c: d0fb beq.n 10001956 +1000195e: f3bf 8f5f dmb sy +10001962: 4770 bx lr +10001964: 400e0000 .word 0x400e0000 + +10001968 : +10001968: 2100 movs r1, #0 +1000196a: 4b04 ldr r3, [pc, #16] @ (1000197c ) +1000196c: 4a04 ldr r2, [pc, #16] @ (10001980 ) +1000196e: f3bf 8f5f dmb sy +10001972: f843 1b04 str.w r1, [r3], #4 +10001976: 4293 cmp r3, r2 +10001978: d1f9 bne.n 1000196e +1000197a: 4770 bx lr +1000197c: 400e080c .word 0x400e080c +10001980: 400e082c .word 0x400e082c + +10001984 : +10001984: b410 push {r4} +10001986: f44f 708d mov.w r0, #282 @ 0x11a +1000198a: f44f 642a mov.w r4, #2720 @ 0xaa0 +1000198e: 4a06 ldr r2, [pc, #24] @ (100019a8 ) +10001990: 4b06 ldr r3, [pc, #24] @ (100019ac ) +10001992: 4907 ldr r1, [pc, #28] @ (100019b0 ) +10001994: 6014 str r4, [r2, #0] +10001996: 60d0 str r0, [r2, #12] +10001998: 6019 str r1, [r3, #0] +1000199a: 6853 ldr r3, [r2, #4] +1000199c: 2b00 cmp r3, #0 +1000199e: dafc bge.n 1000199a +100019a0: f85d 4b04 ldr.w r4, [sp], #4 +100019a4: 4770 bx lr +100019a6: bf00 nop +100019a8: 40048000 .word 0x40048000 +100019ac: 4004a000 .word 0x4004a000 +100019b0: 00fab000 .word 0x00fab000 + +100019b4 : +100019b4: 4770 bx lr +100019b6: bf00 nop + +100019b8 : +100019b8: b508 push {r3, lr} +100019ba: 4801 ldr r0, [pc, #4] @ (100019c0 ) +100019bc: f7fe ffca bl 10000954 +100019c0: 10003f54 .word 0x10003f54 + +100019c4 : +100019c4: b538 push {r3, r4, r5, lr} +100019c6: 4c05 ldr r4, [pc, #20] @ (100019dc ) +100019c8: 4d05 ldr r5, [pc, #20] @ (100019e0 ) +100019ca: 42ac cmp r4, r5 +100019cc: d204 bcs.n 100019d8 +100019ce: f854 3b04 ldr.w r3, [r4], #4 +100019d2: 4798 blx r3 +100019d4: 42ac cmp r4, r5 +100019d6: d3fa bcc.n 100019ce +100019d8: bd38 pop {r3, r4, r5, pc} +100019da: bf00 nop +100019dc: 10003ea0 .word 0x10003ea0 +100019e0: 10003ee0 .word 0x10003ee0 + +100019e4 : +100019e4: b410 push {r4} +100019e6: 4807 ldr r0, [pc, #28] @ (10001a04 ) +100019e8: 4c07 ldr r4, [pc, #28] @ (10001a08 ) +100019ea: 4b08 ldr r3, [pc, #32] @ (10001a0c ) +100019ec: 4a08 ldr r2, [pc, #32] @ (10001a10 ) +100019ee: 4909 ldr r1, [pc, #36] @ (10001a14 ) +100019f0: 6004 str r4, [r0, #0] +100019f2: 601a str r2, [r3, #0] +100019f4: 688b ldr r3, [r1, #8] +100019f6: ea32 0303 bics.w r3, r2, r3 +100019fa: d1fb bne.n 100019f4 +100019fc: f85d 4b04 ldr.w r4, [sp], #4 +10001a00: 4770 bx lr +10001a02: bf00 nop +10001a04: 40022000 .word 0x40022000 +10001a08: efef3b7f .word 0xefef3b7f +10001a0c: 40023000 .word 0x40023000 +10001a10: 03f3fff6 .word 0x03f3fff6 +10001a14: 40020000 .word 0x40020000 + +10001a18 : +10001a18: 4b04 ldr r3, [pc, #16] @ (10001a2c ) +10001a1a: 6cdb ldr r3, [r3, #76] @ 0x4c +10001a1c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001a20: d103 bne.n 10001a2a +10001a22: f44f 2280 mov.w r2, #262144 @ 0x40000 +10001a26: 4b02 ldr r3, [pc, #8] @ (10001a30 ) +10001a28: 64da str r2, [r3, #76] @ 0x4c +10001a2a: 4770 bx lr +10001a2c: 50110000 .word 0x50110000 +10001a30: 50112000 .word 0x50112000 + +10001a34 : +10001a34: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001a38: 4b04 ldr r3, [pc, #16] @ (10001a4c ) +10001a3a: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001a3e: 430b orrs r3, r1 +10001a40: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +10001a44: ee10 0430 dcp_rcmp r0 +10001a48: 4770 bx lr +10001a4a: bf00 nop +10001a4c: 00300303 .word 0x00300303 + +10001a50 : +10001a50: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10001a54: 4b04 ldr r3, [pc, #16] @ (10001a68 ) +10001a56: 4a05 ldr r2, [pc, #20] @ (10001a6c ) +10001a58: 6019 str r1, [r3, #0] +10001a5a: 6893 ldr r3, [r2, #8] +10001a5c: 43db mvns r3, r3 +10001a5e: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10001a62: d1fa bne.n 10001a5a +10001a64: 4770 bx lr +10001a66: bf00 nop +10001a68: 40023000 .word 0x40023000 +10001a6c: 40020000 .word 0x40020000 + +10001a70 : +10001a70: b510 push {r4, lr} +10001a72: f245 2053 movw r0, #21075 @ 0x5253 +10001a76: f7ff ff61 bl 1000193c +10001a7a: e8bd 4010 ldmia.w sp!, {r4, lr} +10001a7e: 4603 mov r3, r0 +10001a80: 2004 movs r0, #4 +10001a82: 4718 bx r3 + +10001a84 : +10001a84: b510 push {r4, lr} +10001a86: f245 2053 movw r0, #21075 @ 0x5253 +10001a8a: f7ff ff57 bl 1000193c +10001a8e: e8bd 4010 ldmia.w sp!, {r4, lr} +10001a92: 4603 mov r3, r0 +10001a94: 2001 movs r0, #1 +10001a96: 4718 bx r3 + +10001a98 : +10001a98: f7fe bfb4 b.w 10000a04 + +10001a9c : +10001a9c: 4914 ldr r1, [pc, #80] @ (10001af0 ) +10001a9e: 4b15 ldr r3, [pc, #84] @ (10001af4 ) +10001aa0: b570 push {r4, r5, r6, lr} +10001aa2: 1a5c subs r4, r3, r1 +10001aa4: 10a6 asrs r6, r4, #2 +10001aa6: 2e44 cmp r6, #68 @ 0x44 +10001aa8: 4632 mov r2, r6 +10001aaa: bf28 it cs +10001aac: 2244 movcs r2, #68 @ 0x44 +10001aae: 4d12 ldr r5, [pc, #72] @ (10001af8 ) +10001ab0: 0092 lsls r2, r2, #2 +10001ab2: 4628 mov r0, r5 +10001ab4: f002 f940 bl 10003d38 +10001ab8: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001abc: d813 bhi.n 10001ae6 +10001abe: 4a0f ldr r2, [pc, #60] @ (10001afc ) +10001ac0: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10001ac4: d012 beq.n 10001aec +10001ac6: 192b adds r3, r5, r4 +10001ac8: 0841 lsrs r1, r0, #1 +10001aca: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001ace: e9c3 2200 strd r2, r2, [r3] +10001ad2: 3308 adds r3, #8 +10001ad4: 428b cmp r3, r1 +10001ad6: d1fa bne.n 10001ace +10001ad8: 07c3 lsls r3, r0, #31 +10001ada: d504 bpl.n 10001ae6 +10001adc: f020 0001 bic.w r0, r0, #1 +10001ae0: 4430 add r0, r6 +10001ae2: f845 2020 str.w r2, [r5, r0, lsl #2] +10001ae6: 4b06 ldr r3, [pc, #24] @ (10001b00 ) +10001ae8: 609d str r5, [r3, #8] +10001aea: bd70 pop {r4, r5, r6, pc} +10001aec: 2043 movs r0, #67 @ 0x43 +10001aee: e7f8 b.n 10001ae2 +10001af0: 10000000 .word 0x10000000 +10001af4: 10000110 .word 0x10000110 +10001af8: 20000000 .word 0x20000000 +10001afc: 10000111 .word 0x10000111 +10001b00: e000ed00 .word 0xe000ed00 + +10001b04 : +10001b04: 2300 movs r3, #0 +10001b06: b570 push {r4, r5, r6, lr} +10001b08: 4c2b ldr r4, [pc, #172] @ (10001bb8 ) +10001b0a: b082 sub sp, #8 +10001b0c: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001b10: f7ff ff38 bl 10001984 +10001b14: 2201 movs r2, #1 +10001b16: 4b29 ldr r3, [pc, #164] @ (10001bbc ) +10001b18: 63da str r2, [r3, #60] @ 0x3c +10001b1a: 6c63 ldr r3, [r4, #68] @ 0x44 +10001b1c: 2b01 cmp r3, #1 +10001b1e: d1fc bne.n 10001b1a +10001b20: 2103 movs r1, #3 +10001b22: 4a26 ldr r2, [pc, #152] @ (10001bbc ) +10001b24: 4b24 ldr r3, [pc, #144] @ (10001bb8 ) +10001b26: 6311 str r1, [r2, #48] @ 0x30 +10001b28: 6b9c ldr r4, [r3, #56] @ 0x38 +10001b2a: 2c01 cmp r4, #1 +10001b2c: d1fc bne.n 10001b28 +10001b2e: 2602 movs r6, #2 +10001b30: 2505 movs r5, #5 +10001b32: 4621 mov r1, r4 +10001b34: 2305 movs r3, #5 +10001b36: 4a22 ldr r2, [pc, #136] @ (10001bc0 ) +10001b38: 4822 ldr r0, [pc, #136] @ (10001bc4 ) +10001b3a: 9600 str r6, [sp, #0] +10001b3c: f7ff feac bl 10001898 +10001b40: 4621 mov r1, r4 +10001b42: 462b mov r3, r5 +10001b44: 4a20 ldr r2, [pc, #128] @ (10001bc8 ) +10001b46: 4821 ldr r0, [pc, #132] @ (10001bcc ) +10001b48: 9500 str r5, [sp, #0] +10001b4a: f7ff fea5 bl 10001898 +10001b4e: 2200 movs r2, #0 +10001b50: 2004 movs r0, #4 +10001b52: 4631 mov r1, r6 +10001b54: 4b1e ldr r3, [pc, #120] @ (10001bd0 ) +10001b56: f7ff fe31 bl 100017bc +10001b5a: 4621 mov r1, r4 +10001b5c: 4628 mov r0, r5 +10001b5e: 2200 movs r2, #0 +10001b60: 4b1c ldr r3, [pc, #112] @ (10001bd4 ) +10001b62: f7ff fe2b bl 100017bc +10001b66: 2200 movs r2, #0 +10001b68: 2008 movs r0, #8 +10001b6a: 4611 mov r1, r2 +10001b6c: 4b1a ldr r3, [pc, #104] @ (10001bd8 ) +10001b6e: f7ff fe25 bl 100017bc +10001b72: 2200 movs r2, #0 +10001b74: 2009 movs r0, #9 +10001b76: 4611 mov r1, r2 +10001b78: 4b17 ldr r3, [pc, #92] @ (10001bd8 ) +10001b7a: f7ff fe1f bl 100017bc +10001b7e: 2200 movs r2, #0 +10001b80: 2006 movs r0, #6 +10001b82: 4611 mov r1, r2 +10001b84: 4b13 ldr r3, [pc, #76] @ (10001bd4 ) +10001b86: f7ff fe19 bl 100017bc +10001b8a: 2200 movs r2, #0 +10001b8c: 4b11 ldr r3, [pc, #68] @ (10001bd4 ) +10001b8e: 2007 movs r0, #7 +10001b90: 4611 mov r1, r2 +10001b92: f7ff fe13 bl 100017bc +10001b96: 2004 movs r0, #4 +10001b98: f7ff fe78 bl 1000188c +10001b9c: 2400 movs r4, #0 +10001b9e: 4b0f ldr r3, [pc, #60] @ (10001bdc ) +10001ba0: fba3 3500 umull r3, r5, r3, r0 +10001ba4: 0cad lsrs r5, r5, #18 +10001ba6: b2e0 uxtb r0, r4 +10001ba8: 4629 mov r1, r5 +10001baa: 3401 adds r4, #1 +10001bac: f7ff feba bl 10001924 +10001bb0: 2c06 cmp r4, #6 +10001bb2: d1f8 bne.n 10001ba6 +10001bb4: b002 add sp, #8 +10001bb6: bd70 pop {r4, r5, r6, pc} +10001bb8: 40010000 .word 0x40010000 +10001bbc: 40013000 .word 0x40013000 +10001bc0: 59682f00 .word 0x59682f00 +10001bc4: 40050000 .word 0x40050000 +10001bc8: 47868c00 .word 0x47868c00 +10001bcc: 40058000 .word 0x40058000 +10001bd0: 00b71b00 .word 0x00b71b00 +10001bd4: 08f0d180 .word 0x08f0d180 +10001bd8: 02dc6c00 .word 0x02dc6c00 +10001bdc: 431bde83 .word 0x431bde83 + +10001be0 : +10001be0: b086 sub sp, #24 +10001be2: b403 push {r0, r1} +10001be4: fc51 0408 dcp_pxmd r0, r1 +10001be8: e9cd 0102 strd r0, r1, [sp, #8] +10001bec: fc51 0409 dcp_pymd r0, r1 +10001bf0: e9cd 0104 strd r0, r1, [sp, #16] +10001bf4: ec51 040a dcp_refd r0, r1 +10001bf8: e9cd 0106 strd r0, r1, [sp, #24] +10001bfc: bc03 pop {r0, r1} +10001bfe: 47f0 blx lr + +10001c00 : +10001c00: e8bd 5000 ldmia.w sp!, {ip, lr} +10001c04: ec4e c400 dcp_wxmd ip, lr +10001c08: e8bd 5000 ldmia.w sp!, {ip, lr} +10001c0c: ec4e c401 dcp_wymd ip, lr +10001c10: e8bd 5000 ldmia.w sp!, {ip, lr} +10001c14: ec4e c402 dcp_wefd ip, lr +10001c18: bd00 pop {pc} +10001c1a: 0000 movs r0, r0 +10001c1c: b500 push {lr} +10001c1e: f7ff ffdf bl 10001be0 +10001c22: e002 b.n 10001c2a <__wrap___aeabi_dadd+0x6> + +10001c24 <__wrap___aeabi_dadd>: +10001c24: fe10 f430 dcp_pcmp APSR_nzcv +10001c28: d4f8 bmi.n 10001c1c +10001c2a: ec41 0410 dcp_wxup r0, r1 +10001c2e: ec43 2411 dcp_wyup r2, r3 +10001c32: ee00 0401 dcp_add0 +10001c36: ee10 0401 dcp_add1 +10001c3a: ee80 0420 dcp_nrdd +10001c3e: ec51 0410 dcp_rdda r0, r1 +10001c42: 4770 bx lr +10001c44: b500 push {lr} +10001c46: f7ff ffcb bl 10001be0 +10001c4a: e002 b.n 10001c52 <__wrap___aeabi_dsub+0x6> + +10001c4c <__wrap___aeabi_dsub>: +10001c4c: fe10 f430 dcp_pcmp APSR_nzcv +10001c50: d4f8 bmi.n 10001c44 <__wrap___aeabi_dadd+0x20> +10001c52: ec41 0410 dcp_wxup r0, r1 +10001c56: ec43 2411 dcp_wyup r2, r3 +10001c5a: ee00 0401 dcp_add0 +10001c5e: ee10 0421 dcp_sub1 +10001c62: ee80 0420 dcp_nrdd +10001c66: ec51 0430 dcp_rdds r0, r1 +10001c6a: 4770 bx lr +10001c6c: b500 push {lr} +10001c6e: f7ff ffb7 bl 10001be0 +10001c72: e002 b.n 10001c7a <__wrap___aeabi_dmul+0x6> + +10001c74 <__wrap___aeabi_dmul>: +10001c74: fe10 f430 dcp_pcmp APSR_nzcv +10001c78: d4f8 bmi.n 10001c6c <__wrap___aeabi_dsub+0x20> +10001c7a: b510 push {r4, lr} +10001c7c: ec41 0410 dcp_wxup r0, r1 +10001c80: ec43 2411 dcp_wyup r2, r3 +10001c84: ec51 0404 dcp_rxms r0, r1, #0x0 +10001c88: ec53 2405 dcp_ryms r2, r3, #0x0 +10001c8c: fba0 4c02 umull r4, ip, r0, r2 +10001c90: f05f 0e00 movs.w lr, #0 +10001c94: fbe0 ce03 umlal ip, lr, r0, r3 +10001c98: fbe1 ce02 umlal ip, lr, r1, r2 +10001c9c: ec4c 4420 dcp_wxms r4, ip +10001ca0: 2400 movs r4, #0 +10001ca2: fbe1 e403 umlal lr, r4, r1, r3 +10001ca6: ec44 e430 dcp_wxmo lr, r4 +10001caa: ee80 0420 dcp_nrdd +10001cae: ec51 0450 dcp_rddm r0, r1 +10001cb2: e8bd 4010 ldmia.w sp!, {r4, lr} +10001cb6: 4770 bx lr +10001cb8: b500 push {lr} +10001cba: f7ff ff91 bl 10001be0 +10001cbe: e002 b.n 10001cc6 <__wrap___aeabi_ddiv+0x6> + +10001cc0 <__wrap___aeabi_ddiv>: +10001cc0: fe10 f430 dcp_pcmp APSR_nzcv +10001cc4: d4f8 bmi.n 10001cb8 <__wrap___aeabi_dmul+0x44> +10001cc6: ec41 0410 dcp_wxup r0, r1 +10001cca: ec43 2411 dcp_wyup r2, r3 +10001cce: ec51 0421 dcp_rymr r0, r1 +10001cd2: fba0 1201 umull r1, r2, r0, r1 +10001cd6: ea6f 0282 mvn.w r2, r2, lsl #2 +10001cda: fb52 0010 smmlar r0, r2, r0, r0 +10001cde: fb52 f212 smmulr r2, r2, r2 +10001ce2: fb52 0010 smmlar r0, r2, r0, r0 +10001ce6: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001cea: ec53 2404 dcp_rxms r2, r3, #0x0 +10001cee: fb5c f113 smmulr r1, ip, r3 +10001cf2: ec53 2415 dcp_ryms r2, r3, #0x1 +10001cf6: fba1 2002 umull r2, r0, r1, r2 +10001cfa: fb01 0003 mla r0, r1, r3, r0 +10001cfe: ec53 2444 dcp_rxms r2, r3, #0x4 +10001d02: eba2 0000 sub.w r0, r2, r0 +10001d06: fb50 f21c smmulr r2, r0, ip +10001d0a: ea4f 1311 mov.w r3, r1, lsr #4 +10001d0e: eb12 7001 adds.w r0, r2, r1, lsl #28 +10001d12: eb43 71e2 adc.w r1, r3, r2, asr #31 +10001d16: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001d1a: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001d1e: f020 0007 bic.w r0, r0, #7 +10001d22: ec53 2475 dcp_ryms r2, r3, #0x7 +10001d26: fba0 3c02 umull r3, ip, r0, r2 +10001d2a: ec53 2475 dcp_ryms r2, r3, #0x7 +10001d2e: fb00 cc03 mla ip, r0, r3, ip +10001d32: fb01 cc02 mla ip, r1, r2, ip +10001d36: ec53 2404 dcp_rxms r2, r3, #0x0 +10001d3a: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001d3e: ea40 705c orr.w r0, r0, ip, lsr #29 +10001d42: f1a0 0001 sub.w r0, r0, #1 +10001d46: ec41 0440 dcp_wxdd r0, r1 +10001d4a: ee80 0420 dcp_nrdd +10001d4e: ec51 0470 dcp_rddd r0, r1 +10001d52: 4770 bx lr +10001d54: b500 push {lr} +10001d56: f7ff ff43 bl 10001be0 +10001d5a: e002 b.n 10001d62 <__wrap___aeabi_i2d+0x6> + +10001d5c <__wrap___aeabi_i2d>: +10001d5c: fe10 f430 dcp_pcmp APSR_nzcv +10001d60: d4f8 bmi.n 10001d54 <__wrap___aeabi_ddiv+0x94> +10001d62: ec40 0470 dcp_wxic r0, r0 +10001d66: ee00 0401 dcp_add0 +10001d6a: ee10 0421 dcp_sub1 +10001d6e: ee80 0420 dcp_nrdd +10001d72: ec51 0430 dcp_rdds r0, r1 +10001d76: 4770 bx lr +10001d78: b500 push {lr} +10001d7a: f7ff ff31 bl 10001be0 +10001d7e: e002 b.n 10001d86 <__wrap___aeabi_ui2d+0x6> + +10001d80 <__wrap___aeabi_ui2d>: +10001d80: fe10 f430 dcp_pcmp APSR_nzcv +10001d84: d4f8 bmi.n 10001d78 <__wrap___aeabi_i2d+0x1c> +10001d86: ec40 0460 dcp_wxuc r0, r0 +10001d8a: ee00 0401 dcp_add0 +10001d8e: ee10 0421 dcp_sub1 +10001d92: ee80 0420 dcp_nrdd +10001d96: ec51 0430 dcp_rdds r0, r1 +10001d9a: 4770 bx lr +10001d9c: b500 push {lr} +10001d9e: f7ff ff1f bl 10001be0 +10001da2: e002 b.n 10001daa + +10001da4 <__wrap___aeabi_d2iz>: +10001da4: fe10 f430 dcp_pcmp APSR_nzcv +10001da8: d4f8 bmi.n 10001d9c <__wrap___aeabi_ui2d+0x1c> + +10001daa : +10001daa: ec41 0480 dcp_wxdc r0, r1 +10001dae: ee00 0401 dcp_add0 +10001db2: ee10 0401 dcp_add1 +10001db6: ee80 0440 dcp_ntdc +10001dba: ee10 0413 dcp_rdic r0 +10001dbe: 4770 bx lr +10001dc0: b500 push {lr} +10001dc2: f7ff ff0d bl 10001be0 +10001dc6: e002 b.n 10001dce + +10001dc8 <__wrap___aeabi_d2uiz>: +10001dc8: fe10 f430 dcp_pcmp APSR_nzcv +10001dcc: d4f8 bmi.n 10001dc0 + +10001dce : +10001dce: ec41 0480 dcp_wxdc r0, r1 +10001dd2: ee00 0401 dcp_add0 +10001dd6: ee10 0401 dcp_add1 +10001dda: ee80 0440 dcp_ntdc +10001dde: ee10 0433 dcp_rduc r0 +10001de2: 4770 bx lr +10001de4: b500 push {lr} +10001de6: f7ff fefb bl 10001be0 +10001dea: e002 b.n 10001df2 <__wrap___aeabi_dcmpun+0x6> + +10001dec <__wrap___aeabi_dcmpun>: +10001dec: fe10 f430 dcp_pcmp APSR_nzcv +10001df0: d4f8 bmi.n 10001de4 +10001df2: ec41 0410 dcp_wxup r0, r1 +10001df6: ec43 2411 dcp_wyup r2, r3 +10001dfa: ee00 0401 dcp_add0 +10001dfe: ee10 0430 dcp_rcmp r0 +10001e02: f3c0 7000 ubfx r0, r0, #28, #1 +10001e06: 4770 bx lr +10001e08: b500 push {lr} +10001e0a: f7ff fee9 bl 10001be0 +10001e0e: e002 b.n 10001e16 <__wrap___aeabi_dcmplt+0x6> + +10001e10 <__wrap___aeabi_dcmplt>: +10001e10: fe10 f430 dcp_pcmp APSR_nzcv +10001e14: d4f8 bmi.n 10001e08 <__wrap___aeabi_dcmpun+0x1c> +10001e16: ec43 2410 dcp_wxup r2, r3 +10001e1a: ec41 0411 dcp_wyup r0, r1 +10001e1e: ee00 0401 dcp_add0 +10001e22: ee10 f430 dcp_rcmp APSR_nzcv +10001e26: bf8c ite hi +10001e28: 2001 movhi r0, #1 +10001e2a: 2000 movls r0, #0 +10001e2c: 4770 bx lr +10001e2e: bf00 nop +10001e30: b500 push {lr} +10001e32: f7ff fed5 bl 10001be0 +10001e36: e002 b.n 10001e3e <__wrap___aeabi_dcmple+0x6> + +10001e38 <__wrap___aeabi_dcmple>: +10001e38: fe10 f430 dcp_pcmp APSR_nzcv +10001e3c: d4f8 bmi.n 10001e30 <__wrap___aeabi_dcmplt+0x20> +10001e3e: ec43 2410 dcp_wxup r2, r3 +10001e42: ec41 0411 dcp_wyup r0, r1 +10001e46: ee00 0401 dcp_add0 +10001e4a: ee10 f430 dcp_rcmp APSR_nzcv +10001e4e: bf2c ite cs +10001e50: 2001 movcs r0, #1 +10001e52: 2000 movcc r0, #0 +10001e54: 4770 bx lr +10001e56: bf00 nop +10001e58: b500 push {lr} +10001e5a: f7ff fec1 bl 10001be0 +10001e5e: e002 b.n 10001e66 <__wrap___aeabi_dcmpge+0x6> + +10001e60 <__wrap___aeabi_dcmpge>: +10001e60: fe10 f430 dcp_pcmp APSR_nzcv +10001e64: d4f8 bmi.n 10001e58 <__wrap___aeabi_dcmple+0x20> +10001e66: ec41 0410 dcp_wxup r0, r1 +10001e6a: ec43 2411 dcp_wyup r2, r3 +10001e6e: ee00 0401 dcp_add0 +10001e72: ee10 f430 dcp_rcmp APSR_nzcv +10001e76: bf2c ite cs +10001e78: 2001 movcs r0, #1 +10001e7a: 2000 movcc r0, #0 +10001e7c: 4770 bx lr +10001e7e: bf00 nop +10001e80: b500 push {lr} +10001e82: f7ff fead bl 10001be0 +10001e86: e002 b.n 10001e8e <__wrap___aeabi_dcmpgt+0x6> + +10001e88 <__wrap___aeabi_dcmpgt>: +10001e88: fe10 f430 dcp_pcmp APSR_nzcv +10001e8c: d4f8 bmi.n 10001e80 <__wrap___aeabi_dcmpge+0x20> +10001e8e: ec41 0410 dcp_wxup r0, r1 +10001e92: ec43 2411 dcp_wyup r2, r3 +10001e96: ee00 0401 dcp_add0 +10001e9a: ee10 f430 dcp_rcmp APSR_nzcv +10001e9e: bf8c ite hi +10001ea0: 2001 movhi r0, #1 +10001ea2: 2000 movls r0, #0 +10001ea4: 4770 bx lr +10001ea6: bf00 nop + +10001ea8 <_out_null>: +10001ea8: 4770 bx lr +10001eaa: bf00 nop + +10001eac <_out_rev>: +10001eac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001eb0: b083 sub sp, #12 +10001eb2: 4699 mov r9, r3 +10001eb4: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001eb8: 9b0f ldr r3, [sp, #60] @ 0x3c +10001eba: 4688 mov r8, r1 +10001ebc: 4611 mov r1, r2 +10001ebe: 079a lsls r2, r3, #30 +10001ec0: 4607 mov r7, r0 +10001ec2: d116 bne.n 10001ef2 <_out_rev+0x46> +10001ec4: 45da cmp sl, fp +10001ec6: d23a bcs.n 10001f3e <_out_rev+0x92> +10001ec8: 460c mov r4, r1 +10001eca: 460d mov r5, r1 +10001ecc: ebab 060a sub.w r6, fp, sl +10001ed0: 440e add r6, r1 +10001ed2: 4622 mov r2, r4 +10001ed4: 464b mov r3, r9 +10001ed6: 4641 mov r1, r8 +10001ed8: 2020 movs r0, #32 +10001eda: 3401 adds r4, #1 +10001edc: 47b8 blx r7 +10001ede: 42b4 cmp r4, r6 +10001ee0: d1f7 bne.n 10001ed2 <_out_rev+0x26> +10001ee2: 4629 mov r1, r5 +10001ee4: f1ba 0f00 cmp.w sl, #0 +10001ee8: d108 bne.n 10001efc <_out_rev+0x50> +10001eea: 4620 mov r0, r4 +10001eec: b003 add sp, #12 +10001eee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001ef2: 460c mov r4, r1 +10001ef4: f1ba 0f00 cmp.w sl, #0 +10001ef8: d010 beq.n 10001f1c <_out_rev+0x70> +10001efa: 460e mov r6, r1 +10001efc: 4655 mov r5, sl +10001efe: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f00: 442e add r6, r5 +10001f02: 449a add sl, r3 +10001f04: 9101 str r1, [sp, #4] +10001f06: 1b72 subs r2, r6, r5 +10001f08: 464b mov r3, r9 +10001f0a: 3d01 subs r5, #1 +10001f0c: 4641 mov r1, r8 +10001f0e: f81a 0d01 ldrb.w r0, [sl, #-1]! +10001f12: 4634 mov r4, r6 +10001f14: 47b8 blx r7 +10001f16: 2d00 cmp r5, #0 +10001f18: d1f5 bne.n 10001f06 <_out_rev+0x5a> +10001f1a: 9901 ldr r1, [sp, #4] +10001f1c: 9b0f ldr r3, [sp, #60] @ 0x3c +10001f1e: 079b lsls r3, r3, #30 +10001f20: d5e3 bpl.n 10001eea <_out_rev+0x3e> +10001f22: 1a65 subs r5, r4, r1 +10001f24: 45ab cmp fp, r5 +10001f26: d9e0 bls.n 10001eea <_out_rev+0x3e> +10001f28: 4622 mov r2, r4 +10001f2a: 464b mov r3, r9 +10001f2c: 4641 mov r1, r8 +10001f2e: 2020 movs r0, #32 +10001f30: 3501 adds r5, #1 +10001f32: 47b8 blx r7 +10001f34: 455d cmp r5, fp +10001f36: f104 0401 add.w r4, r4, #1 +10001f3a: d3f5 bcc.n 10001f28 <_out_rev+0x7c> +10001f3c: e7d5 b.n 10001eea <_out_rev+0x3e> +10001f3e: 460c mov r4, r1 +10001f40: f1ba 0f00 cmp.w sl, #0 +10001f44: d1d9 bne.n 10001efa <_out_rev+0x4e> +10001f46: e7d0 b.n 10001eea <_out_rev+0x3e> + +10001f48 <_ntoa_format>: +10001f48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f4c: 9f0f ldr r7, [sp, #60] @ 0x3c +10001f4e: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001f52: f017 0f02 tst.w r7, #2 +10001f56: 9c0a ldr r4, [sp, #40] @ 0x28 +10001f58: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001f5c: 9d0e ldr r5, [sp, #56] @ 0x38 +10001f5e: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001f62: d144 bne.n 10001fee <_ntoa_format+0xa6> +10001f64: bbf5 cbnz r5, 10001fe4 <_ntoa_format+0x9c> +10001f66: 42b4 cmp r4, r6 +10001f68: d241 bcs.n 10001fee <_ntoa_format+0xa6> +10001f6a: f007 0b01 and.w fp, r7, #1 +10001f6e: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001f72: f04f 0e30 mov.w lr, #48 @ 0x30 +10001f76: 44c4 add ip, r8 +10001f78: e004 b.n 10001f84 <_ntoa_format+0x3c> +10001f7a: 3401 adds r4, #1 +10001f7c: 42a6 cmp r6, r4 +10001f7e: f80c ef01 strb.w lr, [ip, #1]! +10001f82: d901 bls.n 10001f88 <_ntoa_format+0x40> +10001f84: 2c20 cmp r4, #32 +10001f86: d1f8 bne.n 10001f7a <_ntoa_format+0x32> +10001f88: f1bb 0f00 cmp.w fp, #0 +10001f8c: f000 8088 beq.w 100020a0 <_ntoa_format+0x158> +10001f90: 42a5 cmp r5, r4 +10001f92: d92c bls.n 10001fee <_ntoa_format+0xa6> +10001f94: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001f98: f04f 0e30 mov.w lr, #48 @ 0x30 +10001f9c: 44c4 add ip, r8 +10001f9e: e004 b.n 10001faa <_ntoa_format+0x62> +10001fa0: 3401 adds r4, #1 +10001fa2: 42ac cmp r4, r5 +10001fa4: f80c ef01 strb.w lr, [ip, #1]! +10001fa8: d021 beq.n 10001fee <_ntoa_format+0xa6> +10001faa: 2c20 cmp r4, #32 +10001fac: d1f8 bne.n 10001fa0 <_ntoa_format+0x58> +10001fae: f017 0f10 tst.w r7, #16 +10001fb2: d00e beq.n 10001fd2 <_ntoa_format+0x8a> +10001fb4: f417 6f80 tst.w r7, #1024 @ 0x400 +10001fb8: d154 bne.n 10002064 <_ntoa_format+0x11c> +10001fba: 42a6 cmp r6, r4 +10001fbc: d063 beq.n 10002086 <_ntoa_format+0x13e> +10001fbe: 42a5 cmp r5, r4 +10001fc0: d061 beq.n 10002086 <_ntoa_format+0x13e> +10001fc2: f1b9 0f10 cmp.w r9, #16 +10001fc6: d050 beq.n 1000206a <_ntoa_format+0x122> +10001fc8: f1b9 0f02 cmp.w r9, #2 +10001fcc: d056 beq.n 1000207c <_ntoa_format+0x134> +10001fce: 2c20 cmp r4, #32 +10001fd0: d129 bne.n 10002026 <_ntoa_format+0xde> +10001fd2: 2420 movs r4, #32 +10001fd4: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001fd8: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001fdc: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001fe0: f7ff bf64 b.w 10001eac <_out_rev> +10001fe4: f017 0b01 ands.w fp, r7, #1 +10001fe8: d134 bne.n 10002054 <_ntoa_format+0x10c> +10001fea: 42b4 cmp r4, r6 +10001fec: d3bf bcc.n 10001f6e <_ntoa_format+0x26> +10001fee: f017 0f10 tst.w r7, #16 +10001ff2: d01e beq.n 10002032 <_ntoa_format+0xea> +10001ff4: f417 6f80 tst.w r7, #1024 @ 0x400 +10001ff8: d1e3 bne.n 10001fc2 <_ntoa_format+0x7a> +10001ffa: 2c00 cmp r4, #0 +10001ffc: d1dd bne.n 10001fba <_ntoa_format+0x72> +10001ffe: f1b9 0f10 cmp.w r9, #16 +10002002: d063 beq.n 100020cc <_ntoa_format+0x184> +10002004: f1b9 0f02 cmp.w r9, #2 +10002008: d077 beq.n 100020fa <_ntoa_format+0x1b2> +1000200a: 2430 movs r4, #48 @ 0x30 +1000200c: f888 4000 strb.w r4, [r8] +10002010: 2401 movs r4, #1 +10002012: f1ba 0f00 cmp.w sl, #0 +10002016: d111 bne.n 1000203c <_ntoa_format+0xf4> +10002018: 077e lsls r6, r7, #29 +1000201a: d548 bpl.n 100020ae <_ntoa_format+0x166> +1000201c: 262b movs r6, #43 @ 0x2b +1000201e: f808 6004 strb.w r6, [r8, r4] +10002022: 3401 adds r4, #1 +10002024: e7d6 b.n 10001fd4 <_ntoa_format+0x8c> +10002026: 4626 mov r6, r4 +10002028: 3401 adds r4, #1 +1000202a: f04f 0c30 mov.w ip, #48 @ 0x30 +1000202e: f808 c006 strb.w ip, [r8, r6] +10002032: 2c20 cmp r4, #32 +10002034: d0cd beq.n 10001fd2 <_ntoa_format+0x8a> +10002036: f1ba 0f00 cmp.w sl, #0 +1000203a: d0ed beq.n 10002018 <_ntoa_format+0xd0> +1000203c: 262d movs r6, #45 @ 0x2d +1000203e: f808 6004 strb.w r6, [r8, r4] +10002042: 3401 adds r4, #1 +10002044: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10002048: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +1000204c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002050: f7ff bf2c b.w 10001eac <_out_rev> +10002054: f1ba 0f00 cmp.w sl, #0 +10002058: d030 beq.n 100020bc <_ntoa_format+0x174> +1000205a: 42b4 cmp r4, r6 +1000205c: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10002060: d385 bcc.n 10001f6e <_ntoa_format+0x26> +10002062: e795 b.n 10001f90 <_ntoa_format+0x48> +10002064: f1b9 0f10 cmp.w r9, #16 +10002068: d1b3 bne.n 10001fd2 <_ntoa_format+0x8a> +1000206a: 06be lsls r6, r7, #26 +1000206c: d53b bpl.n 100020e6 <_ntoa_format+0x19e> +1000206e: 2c20 cmp r4, #32 +10002070: d0af beq.n 10001fd2 <_ntoa_format+0x8a> +10002072: 2658 movs r6, #88 @ 0x58 +10002074: f808 6004 strb.w r6, [r8, r4] +10002078: 3401 adds r4, #1 +1000207a: e7a8 b.n 10001fce <_ntoa_format+0x86> +1000207c: 2c20 cmp r4, #32 +1000207e: d0a8 beq.n 10001fd2 <_ntoa_format+0x8a> +10002080: 4626 mov r6, r4 +10002082: 3401 adds r4, #1 +10002084: e007 b.n 10002096 <_ntoa_format+0x14e> +10002086: 1e66 subs r6, r4, #1 +10002088: d0b9 beq.n 10001ffe <_ntoa_format+0xb6> +1000208a: f1b9 0f10 cmp.w r9, #16 +1000208e: d036 beq.n 100020fe <_ntoa_format+0x1b6> +10002090: f1b9 0f02 cmp.w r9, #2 +10002094: d1c9 bne.n 1000202a <_ntoa_format+0xe2> +10002096: f04f 0c62 mov.w ip, #98 @ 0x62 +1000209a: f808 c006 strb.w ip, [r8, r6] +1000209e: e796 b.n 10001fce <_ntoa_format+0x86> +100020a0: f017 0f10 tst.w r7, #16 +100020a4: d0c5 beq.n 10002032 <_ntoa_format+0xea> +100020a6: f417 6f80 tst.w r7, #1024 @ 0x400 +100020aa: d086 beq.n 10001fba <_ntoa_format+0x72> +100020ac: e789 b.n 10001fc2 <_ntoa_format+0x7a> +100020ae: 073e lsls r6, r7, #28 +100020b0: d590 bpl.n 10001fd4 <_ntoa_format+0x8c> +100020b2: 2620 movs r6, #32 +100020b4: f808 6004 strb.w r6, [r8, r4] +100020b8: 3401 adds r4, #1 +100020ba: e78b b.n 10001fd4 <_ntoa_format+0x8c> +100020bc: f017 0f0c tst.w r7, #12 +100020c0: d000 beq.n 100020c4 <_ntoa_format+0x17c> +100020c2: 3d01 subs r5, #1 +100020c4: 42b4 cmp r4, r6 +100020c6: f4ff af52 bcc.w 10001f6e <_ntoa_format+0x26> +100020ca: e761 b.n 10001f90 <_ntoa_format+0x48> +100020cc: 06bc lsls r4, r7, #26 +100020ce: d412 bmi.n 100020f6 <_ntoa_format+0x1ae> +100020d0: 2478 movs r4, #120 @ 0x78 +100020d2: f888 4000 strb.w r4, [r8] +100020d6: 2430 movs r4, #48 @ 0x30 +100020d8: f888 4001 strb.w r4, [r8, #1] +100020dc: 2402 movs r4, #2 +100020de: f1ba 0f00 cmp.w sl, #0 +100020e2: d099 beq.n 10002018 <_ntoa_format+0xd0> +100020e4: e7aa b.n 1000203c <_ntoa_format+0xf4> +100020e6: 2c20 cmp r4, #32 +100020e8: f43f af73 beq.w 10001fd2 <_ntoa_format+0x8a> +100020ec: 2678 movs r6, #120 @ 0x78 +100020ee: f808 6004 strb.w r6, [r8, r4] +100020f2: 3401 adds r4, #1 +100020f4: e76b b.n 10001fce <_ntoa_format+0x86> +100020f6: 2458 movs r4, #88 @ 0x58 +100020f8: e7eb b.n 100020d2 <_ntoa_format+0x18a> +100020fa: 2462 movs r4, #98 @ 0x62 +100020fc: e7e9 b.n 100020d2 <_ntoa_format+0x18a> +100020fe: f017 0f20 tst.w r7, #32 +10002102: f1a4 0c02 sub.w ip, r4, #2 +10002106: d004 beq.n 10002112 <_ntoa_format+0x1ca> +10002108: f04f 0e58 mov.w lr, #88 @ 0x58 +1000210c: f808 e00c strb.w lr, [r8, ip] +10002110: e78b b.n 1000202a <_ntoa_format+0xe2> +10002112: f04f 0e78 mov.w lr, #120 @ 0x78 +10002116: f808 e00c strb.w lr, [r8, ip] +1000211a: e786 b.n 1000202a <_ntoa_format+0xe2> + +1000211c <_out_char>: +1000211c: b900 cbnz r0, 10002120 <_out_char+0x4> +1000211e: 4770 bx lr +10002120: f001 bb72 b.w 10003808 <__wrap_putchar> + +10002124 <_out_fct>: +10002124: b110 cbz r0, 1000212c <_out_fct+0x8> +10002126: e9d1 3100 ldrd r3, r1, [r1] +1000212a: 4718 bx r3 +1000212c: 4770 bx lr +1000212e: bf00 nop + +10002130 <_ftoa>: +10002130: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002134: b097 sub sp, #92 @ 0x5c +10002136: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +1000213a: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +1000213e: 4607 mov r7, r0 +10002140: 4688 mov r8, r1 +10002142: ec51 0b17 vmov r0, r1, d7 +10002146: 9c24 ldr r4, [sp, #144] @ 0x90 +10002148: 4699 mov r9, r3 +1000214a: 920c str r2, [sp, #48] @ 0x30 +1000214c: 460b mov r3, r1 +1000214e: 4602 mov r2, r0 +10002150: ed8d 7b04 vstr d7, [sp, #16] +10002154: 9407 str r4, [sp, #28] +10002156: f7ff fe49 bl 10001dec <__wrap___aeabi_dcmpun> +1000215a: 2800 cmp r0, #0 +1000215c: f040 81f4 bne.w 10002548 <_ftoa+0x418> +10002160: e9dd 0104 ldrd r0, r1, [sp, #16] +10002164: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002168: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +1000216c: f7ff fe50 bl 10001e10 <__wrap___aeabi_dcmplt> +10002170: 2800 cmp r0, #0 +10002172: f040 811b bne.w 100023ac <_ftoa+0x27c> +10002176: e9dd 0104 ldrd r0, r1, [sp, #16] +1000217a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000217e: 4bac ldr r3, [pc, #688] @ (10002430 <_ftoa+0x300>) +10002180: f7ff fe82 bl 10001e88 <__wrap___aeabi_dcmpgt> +10002184: 2800 cmp r0, #0 +10002186: f040 80ee bne.w 10002366 <_ftoa+0x236> +1000218a: e9dd 0104 ldrd r0, r1, [sp, #16] +1000218e: a3a4 add r3, pc, #656 @ (adr r3, 10002420 <_ftoa+0x2f0>) +10002190: e9d3 2300 ldrd r2, r3, [r3] +10002194: f7ff fe78 bl 10001e88 <__wrap___aeabi_dcmpgt> +10002198: 2800 cmp r0, #0 +1000219a: f040 80d3 bne.w 10002344 <_ftoa+0x214> +1000219e: e9dd 0104 ldrd r0, r1, [sp, #16] +100021a2: a3a1 add r3, pc, #644 @ (adr r3, 10002428 <_ftoa+0x2f8>) +100021a4: e9d3 2300 ldrd r2, r3, [r3] +100021a8: f7ff fe32 bl 10001e10 <__wrap___aeabi_dcmplt> +100021ac: 2800 cmp r0, #0 +100021ae: f040 80c9 bne.w 10002344 <_ftoa+0x214> +100021b2: e9dd 0104 ldrd r0, r1, [sp, #16] +100021b6: 2200 movs r2, #0 +100021b8: 2300 movs r3, #0 +100021ba: f7ff fe29 bl 10001e10 <__wrap___aeabi_dcmplt> +100021be: 2800 cmp r0, #0 +100021c0: f040 80e8 bne.w 10002394 <_ftoa+0x264> +100021c4: 4623 mov r3, r4 +100021c6: 900d str r0, [sp, #52] @ 0x34 +100021c8: f413 6f80 tst.w r3, #1024 @ 0x400 +100021cc: bf08 it eq +100021ce: 2506 moveq r5, #6 +100021d0: 2130 movs r1, #48 @ 0x30 +100021d2: 462b mov r3, r5 +100021d4: aa0e add r2, sp, #56 @ 0x38 +100021d6: f1a5 0620 sub.w r6, r5, #32 +100021da: e005 b.n 100021e8 <_ftoa+0xb8> +100021dc: 3b01 subs r3, #1 +100021de: 42b3 cmp r3, r6 +100021e0: f802 1b01 strb.w r1, [r2], #1 +100021e4: f000 8193 beq.w 1000250e <_ftoa+0x3de> +100021e8: 2b09 cmp r3, #9 +100021ea: d8f7 bhi.n 100021dc <_ftoa+0xac> +100021ec: 461e mov r6, r3 +100021ee: 1aed subs r5, r5, r3 +100021f0: e9dd 0104 ldrd r0, r1, [sp, #16] +100021f4: f7ff fdd6 bl 10001da4 <__wrap___aeabi_d2iz> +100021f8: 4b8e ldr r3, [pc, #568] @ (10002434 <_ftoa+0x304>) +100021fa: 4604 mov r4, r0 +100021fc: eb03 03c6 add.w r3, r3, r6, lsl #3 +10002200: ed93 7b00 vldr d7, [r3] +10002204: ed8d 7b08 vstr d7, [sp, #32] +10002208: f7ff fda8 bl 10001d5c <__wrap___aeabi_i2d> +1000220c: 4602 mov r2, r0 +1000220e: 460b mov r3, r1 +10002210: e9dd 0104 ldrd r0, r1, [sp, #16] +10002214: f7ff fd1a bl 10001c4c <__wrap___aeabi_dsub> +10002218: e9dd 2308 ldrd r2, r3, [sp, #32] +1000221c: f7ff fd2a bl 10001c74 <__wrap___aeabi_dmul> +10002220: 4602 mov r2, r0 +10002222: 460b mov r3, r1 +10002224: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10002228: f7ff fdce bl 10001dc8 <__wrap___aeabi_d2uiz> +1000222c: 4682 mov sl, r0 +1000222e: f7ff fda7 bl 10001d80 <__wrap___aeabi_ui2d> +10002232: 4602 mov r2, r0 +10002234: 460b mov r3, r1 +10002236: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000223a: f7ff fd07 bl 10001c4c <__wrap___aeabi_dsub> +1000223e: 4602 mov r2, r0 +10002240: 460b mov r3, r1 +10002242: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10002246: 2200 movs r2, #0 +10002248: 4b7b ldr r3, [pc, #492] @ (10002438 <_ftoa+0x308>) +1000224a: f7ff fe1d bl 10001e88 <__wrap___aeabi_dcmpgt> +1000224e: 2800 cmp r0, #0 +10002250: f000 80fe beq.w 10002450 <_ftoa+0x320> +10002254: f10a 0a01 add.w sl, sl, #1 +10002258: 4650 mov r0, sl +1000225a: f7ff fd91 bl 10001d80 <__wrap___aeabi_ui2d> +1000225e: 4602 mov r2, r0 +10002260: 460b mov r3, r1 +10002262: e9dd 0108 ldrd r0, r1, [sp, #32] +10002266: f7ff fde7 bl 10001e38 <__wrap___aeabi_dcmple> +1000226a: b110 cbz r0, 10002272 <_ftoa+0x142> +1000226c: f04f 0a00 mov.w sl, #0 +10002270: 3401 adds r4, #1 +10002272: 2e00 cmp r6, #0 +10002274: f000 80fd beq.w 10002472 <_ftoa+0x342> +10002278: 1e68 subs r0, r5, #1 +1000227a: ab0e add r3, sp, #56 @ 0x38 +1000227c: f8df c1cc ldr.w ip, [pc, #460] @ 1000244c <_ftoa+0x31c> +10002280: 4418 add r0, r3 +10002282: e00f b.n 100022a4 <_ftoa+0x174> +10002284: fbac 210a umull r2, r1, ip, sl +10002288: 08c9 lsrs r1, r1, #3 +1000228a: eb01 0281 add.w r2, r1, r1, lsl #2 +1000228e: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10002292: 3230 adds r2, #48 @ 0x30 +10002294: f1ba 0f09 cmp.w sl, #9 +10002298: f800 2f01 strb.w r2, [r0, #1]! +1000229c: f240 811c bls.w 100024d8 <_ftoa+0x3a8> +100022a0: 468a mov sl, r1 +100022a2: 461d mov r5, r3 +100022a4: 2d20 cmp r5, #32 +100022a6: f105 0301 add.w r3, r5, #1 +100022aa: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +100022ae: d1e9 bne.n 10002284 <_ftoa+0x154> +100022b0: 2520 movs r5, #32 +100022b2: 1e69 subs r1, r5, #1 +100022b4: ab0e add r3, sp, #56 @ 0x38 +100022b6: 4861 ldr r0, [pc, #388] @ (1000243c <_ftoa+0x30c>) +100022b8: 4419 add r1, r3 +100022ba: e010 b.n 100022de <_ftoa+0x1ae> +100022bc: fb80 6204 smull r6, r2, r0, r4 +100022c0: ebc3 03a2 rsb r3, r3, r2, asr #2 +100022c4: eb03 0283 add.w r2, r3, r3, lsl #2 +100022c8: eba4 0442 sub.w r4, r4, r2, lsl #1 +100022cc: f104 0230 add.w r2, r4, #48 @ 0x30 +100022d0: 3501 adds r5, #1 +100022d2: 461c mov r4, r3 +100022d4: f801 2f01 strb.w r2, [r1, #1]! +100022d8: 2b00 cmp r3, #0 +100022da: f000 80eb beq.w 100024b4 <_ftoa+0x384> +100022de: 2d20 cmp r5, #32 +100022e0: ea4f 73e4 mov.w r3, r4, asr #31 +100022e4: d1ea bne.n 100022bc <_ftoa+0x18c> +100022e6: 9b07 ldr r3, [sp, #28] +100022e8: f003 0303 and.w r3, r3, #3 +100022ec: 2b01 cmp r3, #1 +100022ee: d118 bne.n 10002322 <_ftoa+0x1f2> +100022f0: f1bb 0f00 cmp.w fp, #0 +100022f4: d015 beq.n 10002322 <_ftoa+0x1f2> +100022f6: 9b0d ldr r3, [sp, #52] @ 0x34 +100022f8: 2b00 cmp r3, #0 +100022fa: f000 810a beq.w 10002512 <_ftoa+0x3e2> +100022fe: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10002302: f1bb 0f20 cmp.w fp, #32 +10002306: d90c bls.n 10002322 <_ftoa+0x1f2> +10002308: 1e6b subs r3, r5, #1 +1000230a: a90e add r1, sp, #56 @ 0x38 +1000230c: 2230 movs r2, #48 @ 0x30 +1000230e: 440b add r3, r1 +10002310: e005 b.n 1000231e <_ftoa+0x1ee> +10002312: 3501 adds r5, #1 +10002314: 455d cmp r5, fp +10002316: f803 2f01 strb.w r2, [r3, #1]! +1000231a: f080 80d1 bcs.w 100024c0 <_ftoa+0x390> +1000231e: 2d20 cmp r5, #32 +10002320: d1f7 bne.n 10002312 <_ftoa+0x1e2> +10002322: 9b07 ldr r3, [sp, #28] +10002324: ac0e add r4, sp, #56 @ 0x38 +10002326: e9cd b302 strd fp, r3, [sp, #8] +1000232a: 4641 mov r1, r8 +1000232c: 464b mov r3, r9 +1000232e: 4638 mov r0, r7 +10002330: 9a0c ldr r2, [sp, #48] @ 0x30 +10002332: 9501 str r5, [sp, #4] +10002334: 9400 str r4, [sp, #0] +10002336: f7ff fdb9 bl 10001eac <_out_rev> +1000233a: 4682 mov sl, r0 +1000233c: 4650 mov r0, sl +1000233e: b017 add sp, #92 @ 0x5c +10002340: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002344: 9b07 ldr r3, [sp, #28] +10002346: ed9d 7b04 vldr d7, [sp, #16] +1000234a: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +1000234e: 4641 mov r1, r8 +10002350: 464b mov r3, r9 +10002352: 4638 mov r0, r7 +10002354: 9a0c ldr r2, [sp, #48] @ 0x30 +10002356: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +1000235a: 9522 str r5, [sp, #136] @ 0x88 +1000235c: b017 add sp, #92 @ 0x5c +1000235e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002362: f000 b945 b.w 100025f0 <_etoa> +10002366: 0761 lsls r1, r4, #29 +10002368: 4623 mov r3, r4 +1000236a: bf4c ite mi +1000236c: 2304 movmi r3, #4 +1000236e: 2303 movpl r3, #3 +10002370: 4641 mov r1, r8 +10002372: 9321 str r3, [sp, #132] @ 0x84 +10002374: 4638 mov r0, r7 +10002376: 464b mov r3, r9 +10002378: 9a07 ldr r2, [sp, #28] +1000237a: bf48 it mi +1000237c: 4c30 ldrmi r4, [pc, #192] @ (10002440 <_ftoa+0x310>) +1000237e: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10002382: bf58 it pl +10002384: 4c2f ldrpl r4, [pc, #188] @ (10002444 <_ftoa+0x314>) +10002386: 9a0c ldr r2, [sp, #48] @ 0x30 +10002388: 9420 str r4, [sp, #128] @ 0x80 +1000238a: b017 add sp, #92 @ 0x5c +1000238c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002390: f7ff bd8c b.w 10001eac <_out_rev> +10002394: e9dd 2304 ldrd r2, r3, [sp, #16] +10002398: 2000 movs r0, #0 +1000239a: 2100 movs r1, #0 +1000239c: f7ff fc56 bl 10001c4c <__wrap___aeabi_dsub> +100023a0: 2301 movs r3, #1 +100023a2: e9cd 0104 strd r0, r1, [sp, #16] +100023a6: 930d str r3, [sp, #52] @ 0x34 +100023a8: 4623 mov r3, r4 +100023aa: e70d b.n 100021c8 <_ftoa+0x98> +100023ac: 4623 mov r3, r4 +100023ae: 079c lsls r4, r3, #30 +100023b0: f040 80aa bne.w 10002508 <_ftoa+0x3d8> +100023b4: f1bb 0f04 cmp.w fp, #4 +100023b8: f240 80a6 bls.w 10002508 <_ftoa+0x3d8> +100023bc: 9b0c ldr r3, [sp, #48] @ 0x30 +100023be: 461d mov r5, r3 +100023c0: 1f1c subs r4, r3, #4 +100023c2: eb04 0a0b add.w sl, r4, fp +100023c6: 462a mov r2, r5 +100023c8: 464b mov r3, r9 +100023ca: 4641 mov r1, r8 +100023cc: 2020 movs r0, #32 +100023ce: 3501 adds r5, #1 +100023d0: 47b8 blx r7 +100023d2: 45aa cmp sl, r5 +100023d4: d1f7 bne.n 100023c6 <_ftoa+0x296> +100023d6: 4655 mov r5, sl +100023d8: 4c1b ldr r4, [pc, #108] @ (10002448 <_ftoa+0x318>) +100023da: 1f26 subs r6, r4, #4 +100023dc: f814 0d01 ldrb.w r0, [r4, #-1]! +100023e0: 462a mov r2, r5 +100023e2: 464b mov r3, r9 +100023e4: 4641 mov r1, r8 +100023e6: 47b8 blx r7 +100023e8: 42b4 cmp r4, r6 +100023ea: f105 0501 add.w r5, r5, #1 +100023ee: d1f5 bne.n 100023dc <_ftoa+0x2ac> +100023f0: 9b07 ldr r3, [sp, #28] +100023f2: f10a 0a04 add.w sl, sl, #4 +100023f6: 0798 lsls r0, r3, #30 +100023f8: d5a0 bpl.n 1000233c <_ftoa+0x20c> +100023fa: 9c0c ldr r4, [sp, #48] @ 0x30 +100023fc: ebaa 0304 sub.w r3, sl, r4 +10002400: 459b cmp fp, r3 +10002402: d99b bls.n 1000233c <_ftoa+0x20c> +10002404: 4652 mov r2, sl +10002406: 464b mov r3, r9 +10002408: 4641 mov r1, r8 +1000240a: 2020 movs r0, #32 +1000240c: f10a 0a01 add.w sl, sl, #1 +10002410: 47b8 blx r7 +10002412: ebaa 0304 sub.w r3, sl, r4 +10002416: 455b cmp r3, fp +10002418: d3f4 bcc.n 10002404 <_ftoa+0x2d4> +1000241a: e78f b.n 1000233c <_ftoa+0x20c> +1000241c: f3af 8000 nop.w +10002420: 00000000 .word 0x00000000 +10002424: 41cdcd65 .word 0x41cdcd65 +10002428: 00000000 .word 0x00000000 +1000242c: c1cdcd65 .word 0xc1cdcd65 +10002430: 7fefffff .word 0x7fefffff +10002434: 10004050 .word 0x10004050 +10002438: 3fe00000 .word 0x3fe00000 +1000243c: 66666667 .word 0x66666667 +10002440: 10003fac .word 0x10003fac +10002444: 10003fb4 .word 0x10003fb4 +10002448: 10003fc0 .word 0x10003fc0 +1000244c: cccccccd .word 0xcccccccd +10002450: 2200 movs r2, #0 +10002452: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002456: 4b63 ldr r3, [pc, #396] @ (100025e4 <_ftoa+0x4b4>) +10002458: f7ff fcda bl 10001e10 <__wrap___aeabi_dcmplt> +1000245c: 2800 cmp r0, #0 +1000245e: f47f af08 bne.w 10002272 <_ftoa+0x142> +10002462: f1ba 0f00 cmp.w sl, #0 +10002466: d16a bne.n 1000253e <_ftoa+0x40e> +10002468: f10a 0a01 add.w sl, sl, #1 +1000246c: 2e00 cmp r6, #0 +1000246e: f47f af03 bne.w 10002278 <_ftoa+0x148> +10002472: 4620 mov r0, r4 +10002474: f7ff fc72 bl 10001d5c <__wrap___aeabi_i2d> +10002478: 4602 mov r2, r0 +1000247a: 460b mov r3, r1 +1000247c: e9dd 0104 ldrd r0, r1, [sp, #16] +10002480: f7ff fbe4 bl 10001c4c <__wrap___aeabi_dsub> +10002484: 4602 mov r2, r0 +10002486: 460b mov r3, r1 +10002488: e9cd 2304 strd r2, r3, [sp, #16] +1000248c: 2200 movs r2, #0 +1000248e: 4b55 ldr r3, [pc, #340] @ (100025e4 <_ftoa+0x4b4>) +10002490: f7ff fcbe bl 10001e10 <__wrap___aeabi_dcmplt> +10002494: 2800 cmp r0, #0 +10002496: f47f af0c bne.w 100022b2 <_ftoa+0x182> +1000249a: e9dd 0104 ldrd r0, r1, [sp, #16] +1000249e: 2200 movs r2, #0 +100024a0: 4b50 ldr r3, [pc, #320] @ (100025e4 <_ftoa+0x4b4>) +100024a2: f7ff fcf1 bl 10001e88 <__wrap___aeabi_dcmpgt> +100024a6: 2800 cmp r0, #0 +100024a8: f47f af03 bne.w 100022b2 <_ftoa+0x182> +100024ac: 3401 adds r4, #1 +100024ae: f024 0401 bic.w r4, r4, #1 +100024b2: e6fe b.n 100022b2 <_ftoa+0x182> +100024b4: 9b07 ldr r3, [sp, #28] +100024b6: f003 0303 and.w r3, r3, #3 +100024ba: 2b01 cmp r3, #1 +100024bc: f000 8082 beq.w 100025c4 <_ftoa+0x494> +100024c0: 2d20 cmp r5, #32 +100024c2: f43f af2e beq.w 10002322 <_ftoa+0x1f2> +100024c6: 9b0d ldr r3, [sp, #52] @ 0x34 +100024c8: b37b cbz r3, 1000252a <_ftoa+0x3fa> +100024ca: 222d movs r2, #45 @ 0x2d +100024cc: eb0d 0305 add.w r3, sp, r5 +100024d0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +100024d4: 3501 adds r5, #1 +100024d6: e724 b.n 10002322 <_ftoa+0x1f2> +100024d8: 2b20 cmp r3, #32 +100024da: f43f aee9 beq.w 100022b0 <_ftoa+0x180> +100024de: aa0e add r2, sp, #56 @ 0x38 +100024e0: 4415 add r5, r2 +100024e2: 441e add r6, r3 +100024e4: 2230 movs r2, #48 @ 0x30 +100024e6: e004 b.n 100024f2 <_ftoa+0x3c2> +100024e8: 2b20 cmp r3, #32 +100024ea: f805 2f01 strb.w r2, [r5, #1]! +100024ee: f43f aedf beq.w 100022b0 <_ftoa+0x180> +100024f2: 429e cmp r6, r3 +100024f4: f103 0301 add.w r3, r3, #1 +100024f8: d1f6 bne.n 100024e8 <_ftoa+0x3b8> +100024fa: 222e movs r2, #46 @ 0x2e +100024fc: eb0d 0306 add.w r3, sp, r6 +10002500: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10002504: 1c75 adds r5, r6, #1 +10002506: e6d4 b.n 100022b2 <_ftoa+0x182> +10002508: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +1000250c: e763 b.n 100023d6 <_ftoa+0x2a6> +1000250e: 2520 movs r5, #32 +10002510: e66e b.n 100021f0 <_ftoa+0xc0> +10002512: 9b07 ldr r3, [sp, #28] +10002514: f013 0f0c tst.w r3, #12 +10002518: d050 beq.n 100025bc <_ftoa+0x48c> +1000251a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000251e: 45ab cmp fp, r5 +10002520: f63f aef2 bhi.w 10002308 <_ftoa+0x1d8> +10002524: 2d20 cmp r5, #32 +10002526: f43f aefc beq.w 10002322 <_ftoa+0x1f2> +1000252a: 9b07 ldr r3, [sp, #28] +1000252c: 075a lsls r2, r3, #29 +1000252e: d501 bpl.n 10002534 <_ftoa+0x404> +10002530: 222b movs r2, #43 @ 0x2b +10002532: e7cb b.n 100024cc <_ftoa+0x39c> +10002534: 071b lsls r3, r3, #28 +10002536: f57f aef4 bpl.w 10002322 <_ftoa+0x1f2> +1000253a: 2220 movs r2, #32 +1000253c: e7c6 b.n 100024cc <_ftoa+0x39c> +1000253e: f01a 0f01 tst.w sl, #1 +10002542: f43f ae96 beq.w 10002272 <_ftoa+0x142> +10002546: e78f b.n 10002468 <_ftoa+0x338> +10002548: 07a6 lsls r6, r4, #30 +1000254a: d134 bne.n 100025b6 <_ftoa+0x486> +1000254c: f1bb 0f03 cmp.w fp, #3 +10002550: d931 bls.n 100025b6 <_ftoa+0x486> +10002552: 9b0c ldr r3, [sp, #48] @ 0x30 +10002554: 461d mov r5, r3 +10002556: 1edc subs r4, r3, #3 +10002558: eb04 0a0b add.w sl, r4, fp +1000255c: 462a mov r2, r5 +1000255e: 464b mov r3, r9 +10002560: 4641 mov r1, r8 +10002562: 2020 movs r0, #32 +10002564: 3501 adds r5, #1 +10002566: 47b8 blx r7 +10002568: 4555 cmp r5, sl +1000256a: d1f7 bne.n 1000255c <_ftoa+0x42c> +1000256c: 4655 mov r5, sl +1000256e: 4c1e ldr r4, [pc, #120] @ (100025e8 <_ftoa+0x4b8>) +10002570: 1ee6 subs r6, r4, #3 +10002572: f814 0d01 ldrb.w r0, [r4, #-1]! +10002576: 462a mov r2, r5 +10002578: 464b mov r3, r9 +1000257a: 4641 mov r1, r8 +1000257c: 47b8 blx r7 +1000257e: 42a6 cmp r6, r4 +10002580: f105 0501 add.w r5, r5, #1 +10002584: d1f5 bne.n 10002572 <_ftoa+0x442> +10002586: 9b07 ldr r3, [sp, #28] +10002588: f10a 0a03 add.w sl, sl, #3 +1000258c: 079d lsls r5, r3, #30 +1000258e: f57f aed5 bpl.w 1000233c <_ftoa+0x20c> +10002592: 9c0c ldr r4, [sp, #48] @ 0x30 +10002594: ebaa 0304 sub.w r3, sl, r4 +10002598: 459b cmp fp, r3 +1000259a: f67f aecf bls.w 1000233c <_ftoa+0x20c> +1000259e: 4652 mov r2, sl +100025a0: 464b mov r3, r9 +100025a2: 4641 mov r1, r8 +100025a4: 2020 movs r0, #32 +100025a6: f10a 0a01 add.w sl, sl, #1 +100025aa: 47b8 blx r7 +100025ac: ebaa 0304 sub.w r3, sl, r4 +100025b0: 459b cmp fp, r3 +100025b2: d8f4 bhi.n 1000259e <_ftoa+0x46e> +100025b4: e6c2 b.n 1000233c <_ftoa+0x20c> +100025b6: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +100025ba: e7d7 b.n 1000256c <_ftoa+0x43c> +100025bc: 45ab cmp fp, r5 +100025be: f63f aea3 bhi.w 10002308 <_ftoa+0x1d8> +100025c2: e6ae b.n 10002322 <_ftoa+0x1f2> +100025c4: f1bb 0f00 cmp.w fp, #0 +100025c8: f43f af7a beq.w 100024c0 <_ftoa+0x390> +100025cc: 9b0d ldr r3, [sp, #52] @ 0x34 +100025ce: 2b00 cmp r3, #0 +100025d0: d09f beq.n 10002512 <_ftoa+0x3e2> +100025d2: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +100025d6: 455d cmp r5, fp +100025d8: f4ff ae96 bcc.w 10002308 <_ftoa+0x1d8> +100025dc: 2d20 cmp r5, #32 +100025de: f47f af74 bne.w 100024ca <_ftoa+0x39a> +100025e2: e69e b.n 10002322 <_ftoa+0x1f2> +100025e4: 3fe00000 .word 0x3fe00000 +100025e8: 10003fbb .word 0x10003fbb +100025ec: 00000000 .word 0x00000000 + +100025f0 <_etoa>: +100025f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100025f4: b09f sub sp, #124 @ 0x7c +100025f6: 9e2a ldr r6, [sp, #168] @ 0xa8 +100025f8: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +100025fc: 4607 mov r7, r0 +100025fe: 4693 mov fp, r2 +10002600: 9108 str r1, [sp, #32] +10002602: 9309 str r3, [sp, #36] @ 0x24 +10002604: 4622 mov r2, r4 +10002606: 462b mov r3, r5 +10002608: 4620 mov r0, r4 +1000260a: 4629 mov r1, r5 +1000260c: 960e str r6, [sp, #56] @ 0x38 +1000260e: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +10002612: f7ff fbeb bl 10001dec <__wrap___aeabi_dcmpun> +10002616: 2800 cmp r0, #0 +10002618: f040 80be bne.w 10002798 <_etoa+0x1a8> +1000261c: 4620 mov r0, r4 +1000261e: 4629 mov r1, r5 +10002620: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002624: 4b78 ldr r3, [pc, #480] @ (10002808 <_etoa+0x218>) +10002626: f7ff fc2f bl 10001e88 <__wrap___aeabi_dcmpgt> +1000262a: 2800 cmp r0, #0 +1000262c: f040 80b4 bne.w 10002798 <_etoa+0x1a8> +10002630: 4620 mov r0, r4 +10002632: 4629 mov r1, r5 +10002634: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002638: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +1000263c: f7ff fbe8 bl 10001e10 <__wrap___aeabi_dcmplt> +10002640: 2800 cmp r0, #0 +10002642: f040 80a9 bne.w 10002798 <_etoa+0x1a8> +10002646: 4620 mov r0, r4 +10002648: 4629 mov r1, r5 +1000264a: 2200 movs r2, #0 +1000264c: 2300 movs r3, #0 +1000264e: f7ff fbdf bl 10001e10 <__wrap___aeabi_dcmplt> +10002652: 2800 cmp r0, #0 +10002654: f040 81d5 bne.w 10002a02 <_etoa+0x412> +10002658: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +1000265c: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10002660: 4690 mov r8, r2 +10002662: 4699 mov r9, r3 +10002664: f406 6200 and.w r2, r6, #2048 @ 0x800 +10002668: f416 6380 ands.w r3, r6, #1024 @ 0x400 +1000266c: 920f str r2, [sp, #60] @ 0x3c +1000266e: 9313 str r3, [sp, #76] @ 0x4c +10002670: f040 80a1 bne.w 100027b6 <_etoa+0x1c6> +10002674: ea58 0309 orrs.w r3, r8, r9 +10002678: f040 80ca bne.w 10002810 <_etoa+0x220> +1000267c: 2a00 cmp r2, #0 +1000267e: f040 81e3 bne.w 10002a48 <_etoa+0x458> +10002682: 2306 movs r3, #6 +10002684: 930e str r3, [sp, #56] @ 0x38 +10002686: f016 0202 ands.w r2, r6, #2 +1000268a: 9210 str r2, [sp, #64] @ 0x40 +1000268c: f040 81d4 bne.w 10002a38 <_etoa+0x448> +10002690: 4653 mov r3, sl +10002692: 2b04 cmp r3, #4 +10002694: bf38 it cc +10002696: 2304 movcc r3, #4 +10002698: 920c str r2, [sp, #48] @ 0x30 +1000269a: 2204 movs r2, #4 +1000269c: 3b04 subs r3, #4 +1000269e: 9212 str r2, [sp, #72] @ 0x48 +100026a0: 930f str r3, [sp, #60] @ 0x3c +100026a2: 4620 mov r0, r4 +100026a4: 4629 mov r1, r5 +100026a6: 2200 movs r2, #0 +100026a8: 2300 movs r3, #0 +100026aa: f7ff fbb1 bl 10001e10 <__wrap___aeabi_dcmplt> +100026ae: 2800 cmp r0, #0 +100026b0: f040 81f3 bne.w 10002a9a <_etoa+0x4aa> +100026b4: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +100026b8: 9b0f ldr r3, [sp, #60] @ 0x3c +100026ba: 465a mov r2, fp +100026bc: 9303 str r3, [sp, #12] +100026be: 9b0e ldr r3, [sp, #56] @ 0x38 +100026c0: ed8d 7b00 vstr d7, [sp] +100026c4: 9302 str r3, [sp, #8] +100026c6: f426 6300 bic.w r3, r6, #2048 @ 0x800 +100026ca: 9304 str r3, [sp, #16] +100026cc: 4638 mov r0, r7 +100026ce: 9b09 ldr r3, [sp, #36] @ 0x24 +100026d0: 9908 ldr r1, [sp, #32] +100026d2: f7ff fd2d bl 10002130 <_ftoa> +100026d6: 4602 mov r2, r0 +100026d8: f016 0f20 tst.w r6, #32 +100026dc: 9b09 ldr r3, [sp, #36] @ 0x24 +100026de: 9908 ldr r1, [sp, #32] +100026e0: bf0c ite eq +100026e2: 2065 moveq r0, #101 @ 0x65 +100026e4: 2045 movne r0, #69 @ 0x45 +100026e6: f102 0801 add.w r8, r2, #1 +100026ea: 47b8 blx r7 +100026ec: 9a0c ldr r2, [sp, #48] @ 0x30 +100026ee: 9b12 ldr r3, [sp, #72] @ 0x48 +100026f0: ac16 add r4, sp, #88 @ 0x58 +100026f2: 1e5d subs r5, r3, #1 +100026f4: ea82 73e2 eor.w r3, r2, r2, asr #31 +100026f8: eba3 73e2 sub.w r3, r3, r2, asr #31 +100026fc: 0fd1 lsrs r1, r2, #31 +100026fe: 2600 movs r6, #0 +10002700: 4622 mov r2, r4 +10002702: 4699 mov r9, r3 +10002704: f8df c104 ldr.w ip, [pc, #260] @ 1000280c <_etoa+0x21c> +10002708: e001 b.n 1000270e <_etoa+0x11e> +1000270a: 2e20 cmp r6, #32 +1000270c: d010 beq.n 10002730 <_etoa+0x140> +1000270e: 46ce mov lr, r9 +10002710: fbac 3009 umull r3, r0, ip, r9 +10002714: 08c0 lsrs r0, r0, #3 +10002716: eb00 0380 add.w r3, r0, r0, lsl #2 +1000271a: eba9 0343 sub.w r3, r9, r3, lsl #1 +1000271e: 3330 adds r3, #48 @ 0x30 +10002720: f1be 0f09 cmp.w lr, #9 +10002724: 4681 mov r9, r0 +10002726: f106 0601 add.w r6, r6, #1 +1000272a: f802 3b01 strb.w r3, [r2], #1 +1000272e: d8ec bhi.n 1000270a <_etoa+0x11a> +10002730: 2305 movs r3, #5 +10002732: 2000 movs r0, #0 +10002734: 9306 str r3, [sp, #24] +10002736: 230a movs r3, #10 +10002738: 9505 str r5, [sp, #20] +1000273a: 9400 str r4, [sp, #0] +1000273c: 9d09 ldr r5, [sp, #36] @ 0x24 +1000273e: 9c08 ldr r4, [sp, #32] +10002740: 4642 mov r2, r8 +10002742: e9cd 3003 strd r3, r0, [sp, #12] +10002746: e9cd 6101 strd r6, r1, [sp, #4] +1000274a: 462b mov r3, r5 +1000274c: 4621 mov r1, r4 +1000274e: 4638 mov r0, r7 +10002750: f7ff fbfa bl 10001f48 <_ntoa_format> +10002754: 9a10 ldr r2, [sp, #64] @ 0x40 +10002756: 4680 mov r8, r0 +10002758: b1d2 cbz r2, 10002790 <_etoa+0x1a0> +1000275a: eba0 060b sub.w r6, r0, fp +1000275e: 45b2 cmp sl, r6 +10002760: d916 bls.n 10002790 <_etoa+0x1a0> +10002762: eb0b 0206 add.w r2, fp, r6 +10002766: 462b mov r3, r5 +10002768: 4621 mov r1, r4 +1000276a: 2020 movs r0, #32 +1000276c: 3601 adds r6, #1 +1000276e: 47b8 blx r7 +10002770: 45b2 cmp sl, r6 +10002772: d8f6 bhi.n 10002762 <_etoa+0x172> +10002774: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002778: 4453 add r3, sl +1000277a: f1cb 0201 rsb r2, fp, #1 +1000277e: eba3 0308 sub.w r3, r3, r8 +10002782: 4442 add r2, r8 +10002784: 4592 cmp sl, r2 +10002786: bf38 it cc +10002788: 2300 movcc r3, #0 +1000278a: f108 0801 add.w r8, r8, #1 +1000278e: 4498 add r8, r3 +10002790: 4640 mov r0, r8 +10002792: b01f add sp, #124 @ 0x7c +10002794: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002798: 465a mov r2, fp +1000279a: 4638 mov r0, r7 +1000279c: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100027a0: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +100027a4: 9c0e ldr r4, [sp, #56] @ 0x38 +100027a6: 9b09 ldr r3, [sp, #36] @ 0x24 +100027a8: 9908 ldr r1, [sp, #32] +100027aa: 942a str r4, [sp, #168] @ 0xa8 +100027ac: b01f add sp, #124 @ 0x7c +100027ae: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100027b2: f7ff bcbd b.w 10002130 <_ftoa> +100027b6: ea58 0309 orrs.w r3, r8, r9 +100027ba: d12b bne.n 10002814 <_etoa+0x224> +100027bc: 2a00 cmp r2, #0 +100027be: f43f af62 beq.w 10002686 <_etoa+0x96> +100027c2: 2300 movs r3, #0 +100027c4: 930c str r3, [sp, #48] @ 0x30 +100027c6: 9b0e ldr r3, [sp, #56] @ 0x38 +100027c8: 9a0c ldr r2, [sp, #48] @ 0x30 +100027ca: 4293 cmp r3, r2 +100027cc: f300 81b9 bgt.w 10002b42 <_etoa+0x552> +100027d0: f04f 0800 mov.w r8, #0 +100027d4: 4620 mov r0, r4 +100027d6: 4629 mov r1, r5 +100027d8: 2200 movs r2, #0 +100027da: 2300 movs r3, #0 +100027dc: f7ff fb18 bl 10001e10 <__wrap___aeabi_dcmplt> +100027e0: 2800 cmp r0, #0 +100027e2: f040 8113 bne.w 10002a0c <_etoa+0x41c> +100027e6: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +100027ea: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100027ee: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100027f2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100027f6: 465a mov r2, fp +100027f8: 4638 mov r0, r7 +100027fa: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100027fe: 9b09 ldr r3, [sp, #36] @ 0x24 +10002800: 9908 ldr r1, [sp, #32] +10002802: 962c str r6, [sp, #176] @ 0xb0 +10002804: e7d2 b.n 100027ac <_etoa+0x1bc> +10002806: bf00 nop +10002808: 7fefffff .word 0x7fefffff +1000280c: cccccccd .word 0xcccccccd +10002810: 2306 movs r3, #6 +10002812: 930e str r3, [sp, #56] @ 0x38 +10002814: f3c9 500a ubfx r0, r9, #20, #11 +10002818: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +1000281c: f7ff fa9e bl 10001d5c <__wrap___aeabi_i2d> +10002820: a3c1 add r3, pc, #772 @ (adr r3, 10002b28 <_etoa+0x538>) +10002822: e9d3 2300 ldrd r2, r3, [r3] +10002826: f7ff fa25 bl 10001c74 <__wrap___aeabi_dmul> +1000282a: a3c1 add r3, pc, #772 @ (adr r3, 10002b30 <_etoa+0x540>) +1000282c: e9d3 2300 ldrd r2, r3, [r3] +10002830: f7ff f9f8 bl 10001c24 <__wrap___aeabi_dadd> +10002834: f3c9 0913 ubfx r9, r9, #0, #20 +10002838: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +1000283c: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002840: 4640 mov r0, r8 +10002842: 2200 movs r2, #0 +10002844: 4bb2 ldr r3, [pc, #712] @ (10002b10 <_etoa+0x520>) +10002846: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +1000284a: f7ff f9ff bl 10001c4c <__wrap___aeabi_dsub> +1000284e: a3a4 add r3, pc, #656 @ (adr r3, 10002ae0 <_etoa+0x4f0>) +10002850: e9d3 2300 ldrd r2, r3, [r3] +10002854: f7ff fa0e bl 10001c74 <__wrap___aeabi_dmul> +10002858: 4602 mov r2, r0 +1000285a: 460b mov r3, r1 +1000285c: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002860: f7ff f9e0 bl 10001c24 <__wrap___aeabi_dadd> +10002864: f7ff fa9e bl 10001da4 <__wrap___aeabi_d2iz> +10002868: 900c str r0, [sp, #48] @ 0x30 +1000286a: f7ff fa77 bl 10001d5c <__wrap___aeabi_i2d> +1000286e: a39e add r3, pc, #632 @ (adr r3, 10002ae8 <_etoa+0x4f8>) +10002870: e9d3 2300 ldrd r2, r3, [r3] +10002874: 4680 mov r8, r0 +10002876: 4689 mov r9, r1 +10002878: f7ff f9fc bl 10001c74 <__wrap___aeabi_dmul> +1000287c: 2200 movs r2, #0 +1000287e: 4ba5 ldr r3, [pc, #660] @ (10002b14 <_etoa+0x524>) +10002880: f7ff f9d0 bl 10001c24 <__wrap___aeabi_dadd> +10002884: f7ff fa8e bl 10001da4 <__wrap___aeabi_d2iz> +10002888: 4603 mov r3, r0 +1000288a: 4649 mov r1, r9 +1000288c: 4640 mov r0, r8 +1000288e: 9312 str r3, [sp, #72] @ 0x48 +10002890: a397 add r3, pc, #604 @ (adr r3, 10002af0 <_etoa+0x500>) +10002892: e9d3 2300 ldrd r2, r3, [r3] +10002896: f7ff f9ed bl 10001c74 <__wrap___aeabi_dmul> +1000289a: 4680 mov r8, r0 +1000289c: 9812 ldr r0, [sp, #72] @ 0x48 +1000289e: 4689 mov r9, r1 +100028a0: f7ff fa5c bl 10001d5c <__wrap___aeabi_i2d> +100028a4: a394 add r3, pc, #592 @ (adr r3, 10002af8 <_etoa+0x508>) +100028a6: e9d3 2300 ldrd r2, r3, [r3] +100028aa: f7ff f9e3 bl 10001c74 <__wrap___aeabi_dmul> +100028ae: 4602 mov r2, r0 +100028b0: 460b mov r3, r1 +100028b2: 4640 mov r0, r8 +100028b4: 4649 mov r1, r9 +100028b6: f7ff f9c9 bl 10001c4c <__wrap___aeabi_dsub> +100028ba: 4602 mov r2, r0 +100028bc: 460b mov r3, r1 +100028be: 4680 mov r8, r0 +100028c0: 4689 mov r9, r1 +100028c2: f7ff f9d7 bl 10001c74 <__wrap___aeabi_dmul> +100028c6: 4642 mov r2, r8 +100028c8: 464b mov r3, r9 +100028ca: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +100028ce: 4640 mov r0, r8 +100028d0: 4649 mov r1, r9 +100028d2: f7ff f9a7 bl 10001c24 <__wrap___aeabi_dadd> +100028d6: 2200 movs r2, #0 +100028d8: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +100028dc: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100028e0: 4b8d ldr r3, [pc, #564] @ (10002b18 <_etoa+0x528>) +100028e2: f7ff f9ed bl 10001cc0 <__wrap___aeabi_ddiv> +100028e6: 2200 movs r2, #0 +100028e8: 4b8c ldr r3, [pc, #560] @ (10002b1c <_etoa+0x52c>) +100028ea: f7ff f99b bl 10001c24 <__wrap___aeabi_dadd> +100028ee: 4602 mov r2, r0 +100028f0: 460b mov r3, r1 +100028f2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100028f6: f7ff f9e3 bl 10001cc0 <__wrap___aeabi_ddiv> +100028fa: 2200 movs r2, #0 +100028fc: 4b88 ldr r3, [pc, #544] @ (10002b20 <_etoa+0x530>) +100028fe: f7ff f991 bl 10001c24 <__wrap___aeabi_dadd> +10002902: 4602 mov r2, r0 +10002904: 460b mov r3, r1 +10002906: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000290a: f7ff f9d9 bl 10001cc0 <__wrap___aeabi_ddiv> +1000290e: 4642 mov r2, r8 +10002910: 464b mov r3, r9 +10002912: 4680 mov r8, r0 +10002914: 4689 mov r9, r1 +10002916: 2000 movs r0, #0 +10002918: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +1000291c: f7ff f996 bl 10001c4c <__wrap___aeabi_dsub> +10002920: 4602 mov r2, r0 +10002922: 460b mov r3, r1 +10002924: 4640 mov r0, r8 +10002926: 4649 mov r1, r9 +10002928: f7ff f97c bl 10001c24 <__wrap___aeabi_dadd> +1000292c: 4602 mov r2, r0 +1000292e: 460b mov r3, r1 +10002930: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +10002934: f7ff f9c4 bl 10001cc0 <__wrap___aeabi_ddiv> +10002938: 2200 movs r2, #0 +1000293a: 4b7a ldr r3, [pc, #488] @ (10002b24 <_etoa+0x534>) +1000293c: f7ff f972 bl 10001c24 <__wrap___aeabi_dadd> +10002940: 9b12 ldr r3, [sp, #72] @ 0x48 +10002942: 2200 movs r2, #0 +10002944: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002948: ea4f 530c mov.w r3, ip, lsl #20 +1000294c: f7ff f992 bl 10001c74 <__wrap___aeabi_dmul> +10002950: 4680 mov r8, r0 +10002952: 4689 mov r9, r1 +10002954: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002958: 4642 mov r2, r8 +1000295a: 464b mov r3, r9 +1000295c: f7ff fa58 bl 10001e10 <__wrap___aeabi_dcmplt> +10002960: b150 cbz r0, 10002978 <_etoa+0x388> +10002962: 9b0c ldr r3, [sp, #48] @ 0x30 +10002964: 4640 mov r0, r8 +10002966: 3b01 subs r3, #1 +10002968: 4649 mov r1, r9 +1000296a: 930c str r3, [sp, #48] @ 0x30 +1000296c: 2200 movs r2, #0 +1000296e: 4b6b ldr r3, [pc, #428] @ (10002b1c <_etoa+0x52c>) +10002970: f7ff f9a6 bl 10001cc0 <__wrap___aeabi_ddiv> +10002974: 4680 mov r8, r0 +10002976: 4689 mov r9, r1 +10002978: 9a0c ldr r2, [sp, #48] @ 0x30 +1000297a: 4643 mov r3, r8 +1000297c: 3263 adds r2, #99 @ 0x63 +1000297e: 2ac6 cmp r2, #198 @ 0xc6 +10002980: f006 0202 and.w r2, r6, #2 +10002984: 9210 str r2, [sp, #64] @ 0x40 +10002986: 4649 mov r1, r9 +10002988: 9a0f ldr r2, [sp, #60] @ 0x3c +1000298a: d82c bhi.n 100029e6 <_etoa+0x3f6> +1000298c: 2a00 cmp r2, #0 +1000298e: d05e beq.n 10002a4e <_etoa+0x45e> +10002990: 2204 movs r2, #4 +10002992: 9212 str r2, [sp, #72] @ 0x48 +10002994: 430b orrs r3, r1 +10002996: f43f af16 beq.w 100027c6 <_etoa+0x1d6> +1000299a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000299e: a358 add r3, pc, #352 @ (adr r3, 10002b00 <_etoa+0x510>) +100029a0: e9d3 2300 ldrd r2, r3, [r3] +100029a4: f7ff fa5c bl 10001e60 <__wrap___aeabi_dcmpge> +100029a8: b148 cbz r0, 100029be <_etoa+0x3ce> +100029aa: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100029ae: a356 add r3, pc, #344 @ (adr r3, 10002b08 <_etoa+0x518>) +100029b0: e9d3 2300 ldrd r2, r3, [r3] +100029b4: f7ff fa2c bl 10001e10 <__wrap___aeabi_dcmplt> +100029b8: 2800 cmp r0, #0 +100029ba: f47f af04 bne.w 100027c6 <_etoa+0x1d6> +100029be: 9b0e ldr r3, [sp, #56] @ 0x38 +100029c0: 2b00 cmp r3, #0 +100029c2: d050 beq.n 10002a66 <_etoa+0x476> +100029c4: 9a13 ldr r2, [sp, #76] @ 0x4c +100029c6: 2a00 cmp r2, #0 +100029c8: d07d beq.n 10002ac6 <_etoa+0x4d6> +100029ca: 3b01 subs r3, #1 +100029cc: 930e str r3, [sp, #56] @ 0x38 +100029ce: 9b12 ldr r3, [sp, #72] @ 0x48 +100029d0: 459a cmp sl, r3 +100029d2: d905 bls.n 100029e0 <_etoa+0x3f0> +100029d4: 9b10 ldr r3, [sp, #64] @ 0x40 +100029d6: 2b00 cmp r3, #0 +100029d8: f000 80ae beq.w 10002b38 <_etoa+0x548> +100029dc: 2302 movs r3, #2 +100029de: 9310 str r3, [sp, #64] @ 0x40 +100029e0: 2300 movs r3, #0 +100029e2: 930f str r3, [sp, #60] @ 0x3c +100029e4: e044 b.n 10002a70 <_etoa+0x480> +100029e6: bb22 cbnz r2, 10002a32 <_etoa+0x442> +100029e8: f1ba 0f05 cmp.w sl, #5 +100029ec: d94f bls.n 10002a8e <_etoa+0x49e> +100029ee: f006 0302 and.w r3, r6, #2 +100029f2: 2b00 cmp r3, #0 +100029f4: d149 bne.n 10002a8a <_etoa+0x49a> +100029f6: 2305 movs r3, #5 +100029f8: 9312 str r3, [sp, #72] @ 0x48 +100029fa: f1aa 0305 sub.w r3, sl, #5 +100029fe: 930f str r3, [sp, #60] @ 0x3c +10002a00: e03a b.n 10002a78 <_etoa+0x488> +10002a02: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +10002a06: 940a str r4, [sp, #40] @ 0x28 +10002a08: 930b str r3, [sp, #44] @ 0x2c +10002a0a: e627 b.n 1000265c <_etoa+0x6c> +10002a0c: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002a10: f446 6680 orr.w r6, r6, #1024 @ 0x400 +10002a14: 4638 mov r0, r7 +10002a16: 962c str r6, [sp, #176] @ 0xb0 +10002a18: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002a1c: 4634 mov r4, r6 +10002a1e: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +10002a22: 465a mov r2, fp +10002a24: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002a28: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002a2c: 9b09 ldr r3, [sp, #36] @ 0x24 +10002a2e: 9908 ldr r1, [sp, #32] +10002a30: e6bc b.n 100027ac <_etoa+0x1bc> +10002a32: 2205 movs r2, #5 +10002a34: 9212 str r2, [sp, #72] @ 0x48 +10002a36: e7ad b.n 10002994 <_etoa+0x3a4> +10002a38: 2300 movs r3, #0 +10002a3a: 2202 movs r2, #2 +10002a3c: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002a40: 2204 movs r2, #4 +10002a42: 930c str r3, [sp, #48] @ 0x30 +10002a44: 9212 str r2, [sp, #72] @ 0x48 +10002a46: e62c b.n 100026a2 <_etoa+0xb2> +10002a48: f04f 0805 mov.w r8, #5 +10002a4c: e6c2 b.n 100027d4 <_etoa+0x1e4> +10002a4e: f1ba 0f04 cmp.w sl, #4 +10002a52: d91f bls.n 10002a94 <_etoa+0x4a4> +10002a54: 9b10 ldr r3, [sp, #64] @ 0x40 +10002a56: 2b00 cmp r3, #0 +10002a58: d178 bne.n 10002b4c <_etoa+0x55c> +10002a5a: 2304 movs r3, #4 +10002a5c: 9312 str r3, [sp, #72] @ 0x48 +10002a5e: f1aa 0304 sub.w r3, sl, #4 +10002a62: 930f str r3, [sp, #60] @ 0x3c +10002a64: e004 b.n 10002a70 <_etoa+0x480> +10002a66: 9b12 ldr r3, [sp, #72] @ 0x48 +10002a68: 459a cmp sl, r3 +10002a6a: d831 bhi.n 10002ad0 <_etoa+0x4e0> +10002a6c: 9b0e ldr r3, [sp, #56] @ 0x38 +10002a6e: 930f str r3, [sp, #60] @ 0x3c +10002a70: 9b0c ldr r3, [sp, #48] @ 0x30 +10002a72: 2b00 cmp r3, #0 +10002a74: f43f ae15 beq.w 100026a2 <_etoa+0xb2> +10002a78: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002a7c: 4642 mov r2, r8 +10002a7e: 464b mov r3, r9 +10002a80: f7ff f91e bl 10001cc0 <__wrap___aeabi_ddiv> +10002a84: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10002a88: e60b b.n 100026a2 <_etoa+0xb2> +10002a8a: 2302 movs r3, #2 +10002a8c: 9310 str r3, [sp, #64] @ 0x40 +10002a8e: 2305 movs r3, #5 +10002a90: 9312 str r3, [sp, #72] @ 0x48 +10002a92: e7f1 b.n 10002a78 <_etoa+0x488> +10002a94: 2304 movs r3, #4 +10002a96: 9312 str r3, [sp, #72] @ 0x48 +10002a98: e7ea b.n 10002a70 <_etoa+0x480> +10002a9a: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +10002a9e: 46a0 mov r8, r4 +10002aa0: 9b0f ldr r3, [sp, #60] @ 0x3c +10002aa2: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +10002aa6: 9303 str r3, [sp, #12] +10002aa8: 9b0e ldr r3, [sp, #56] @ 0x38 +10002aaa: 465a mov r2, fp +10002aac: 9302 str r3, [sp, #8] +10002aae: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002ab2: 9304 str r3, [sp, #16] +10002ab4: 4638 mov r0, r7 +10002ab6: e9cd 8900 strd r8, r9, [sp] +10002aba: 9b09 ldr r3, [sp, #36] @ 0x24 +10002abc: 9908 ldr r1, [sp, #32] +10002abe: f7ff fb37 bl 10002130 <_ftoa> +10002ac2: 4602 mov r2, r0 +10002ac4: e608 b.n 100026d8 <_etoa+0xe8> +10002ac6: 9b12 ldr r3, [sp, #72] @ 0x48 +10002ac8: 459a cmp sl, r3 +10002aca: d844 bhi.n 10002b56 <_etoa+0x566> +10002acc: 920f str r2, [sp, #60] @ 0x3c +10002ace: e7cf b.n 10002a70 <_etoa+0x480> +10002ad0: 9b10 ldr r3, [sp, #64] @ 0x40 +10002ad2: b38b cbz r3, 10002b38 <_etoa+0x548> +10002ad4: 9b0e ldr r3, [sp, #56] @ 0x38 +10002ad6: 930f str r3, [sp, #60] @ 0x3c +10002ad8: 2302 movs r3, #2 +10002ada: 9310 str r3, [sp, #64] @ 0x40 +10002adc: e7c8 b.n 10002a70 <_etoa+0x480> +10002ade: bf00 nop +10002ae0: 636f4361 .word 0x636f4361 +10002ae4: 3fd287a7 .word 0x3fd287a7 +10002ae8: 0979a371 .word 0x0979a371 +10002aec: 400a934f .word 0x400a934f +10002af0: bbb55516 .word 0xbbb55516 +10002af4: 40026bb1 .word 0x40026bb1 +10002af8: fefa39ef .word 0xfefa39ef +10002afc: 3fe62e42 .word 0x3fe62e42 +10002b00: eb1c432d .word 0xeb1c432d +10002b04: 3f1a36e2 .word 0x3f1a36e2 +10002b08: 00000000 .word 0x00000000 +10002b0c: 412e8480 .word 0x412e8480 +10002b10: 3ff80000 .word 0x3ff80000 +10002b14: 3fe00000 .word 0x3fe00000 +10002b18: 402c0000 .word 0x402c0000 +10002b1c: 40240000 .word 0x40240000 +10002b20: 40180000 .word 0x40180000 +10002b24: 3ff00000 .word 0x3ff00000 +10002b28: 509f79fb .word 0x509f79fb +10002b2c: 3fd34413 .word 0x3fd34413 +10002b30: 8b60c8b3 .word 0x8b60c8b3 +10002b34: 3fc68a28 .word 0x3fc68a28 +10002b38: 9b12 ldr r3, [sp, #72] @ 0x48 +10002b3a: ebaa 0303 sub.w r3, sl, r3 +10002b3e: 930f str r3, [sp, #60] @ 0x3c +10002b40: e796 b.n 10002a70 <_etoa+0x480> +10002b42: eba3 0802 sub.w r8, r3, r2 +10002b46: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +10002b4a: e643 b.n 100027d4 <_etoa+0x1e4> +10002b4c: 2304 movs r3, #4 +10002b4e: 9312 str r3, [sp, #72] @ 0x48 +10002b50: 2302 movs r3, #2 +10002b52: 9310 str r3, [sp, #64] @ 0x40 +10002b54: e78c b.n 10002a70 <_etoa+0x480> +10002b56: 9b10 ldr r3, [sp, #64] @ 0x40 +10002b58: 2b00 cmp r3, #0 +10002b5a: d0ed beq.n 10002b38 <_etoa+0x548> +10002b5c: 2302 movs r3, #2 +10002b5e: 920f str r2, [sp, #60] @ 0x3c +10002b60: 9310 str r3, [sp, #64] @ 0x40 +10002b62: e785 b.n 10002a70 <_etoa+0x480> + +10002b64 <_vsnprintf>: +10002b64: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002b68: b09b sub sp, #108 @ 0x6c +10002b6a: 9c24 ldr r4, [sp, #144] @ 0x90 +10002b6c: 4d95 ldr r5, [pc, #596] @ (10002dc4 <_vsnprintf+0x260>) +10002b6e: 940a str r4, [sp, #40] @ 0x28 +10002b70: 4c95 ldr r4, [pc, #596] @ (10002dc8 <_vsnprintf+0x264>) +10002b72: f1b1 0a00 subs.w sl, r1, #0 +10002b76: bf18 it ne +10002b78: 4683 movne fp, r0 +10002b7a: 6025 str r5, [r4, #0] +10002b7c: 7818 ldrb r0, [r3, #0] +10002b7e: 4c93 ldr r4, [pc, #588] @ (10002dcc <_vsnprintf+0x268>) +10002b80: 4691 mov r9, r2 +10002b82: bf08 it eq +10002b84: 46a3 moveq fp, r4 +10002b86: 9309 str r3, [sp, #36] @ 0x24 +10002b88: 2800 cmp r0, #0 +10002b8a: f000 8293 beq.w 100030b4 <_vsnprintf+0x550> +10002b8e: f04f 0800 mov.w r8, #0 +10002b92: e00a b.n 10002baa <_vsnprintf+0x46> +10002b94: 4642 mov r2, r8 +10002b96: 464b mov r3, r9 +10002b98: 4651 mov r1, sl +10002b9a: f108 0801 add.w r8, r8, #1 +10002b9e: 47d8 blx fp +10002ba0: 9b09 ldr r3, [sp, #36] @ 0x24 +10002ba2: 7818 ldrb r0, [r3, #0] +10002ba4: 2800 cmp r0, #0 +10002ba6: f000 80ce beq.w 10002d46 <_vsnprintf+0x1e2> +10002baa: 9b09 ldr r3, [sp, #36] @ 0x24 +10002bac: 2825 cmp r0, #37 @ 0x25 +10002bae: f103 0301 add.w r3, r3, #1 +10002bb2: 9309 str r3, [sp, #36] @ 0x24 +10002bb4: d1ee bne.n 10002b94 <_vsnprintf+0x30> +10002bb6: 461c mov r4, r3 +10002bb8: 2300 movs r3, #0 +10002bba: 4622 mov r2, r4 +10002bbc: f812 0b01 ldrb.w r0, [r2], #1 +10002bc0: f1a0 0120 sub.w r1, r0, #32 +10002bc4: 2910 cmp r1, #16 +10002bc6: d80a bhi.n 10002bde <_vsnprintf+0x7a> +10002bc8: e8df f001 tbb [pc, r1] +10002bcc: 3c090940 .word 0x3c090940 +10002bd0: 09090909 .word 0x09090909 +10002bd4: 38090909 .word 0x38090909 +10002bd8: 09093409 .word 0x09093409 +10002bdc: 30 .byte 0x30 +10002bdd: 00 .byte 0x00 +10002bde: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +10002be2: 2909 cmp r1, #9 +10002be4: 9409 str r4, [sp, #36] @ 0x24 +10002be6: f240 808a bls.w 10002cfe <_vsnprintf+0x19a> +10002bea: 282a cmp r0, #42 @ 0x2a +10002bec: f000 80f0 beq.w 10002dd0 <_vsnprintf+0x26c> +10002bf0: 2500 movs r5, #0 +10002bf2: 282e cmp r0, #46 @ 0x2e +10002bf4: f000 8096 beq.w 10002d24 <_vsnprintf+0x1c0> +10002bf8: 2600 movs r6, #0 +10002bfa: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002bfe: 2912 cmp r1, #18 +10002c00: d82d bhi.n 10002c5e <_vsnprintf+0xfa> +10002c02: e8df f011 tbh [pc, r1, lsl #1] +10002c06: 0149 .short 0x0149 +10002c08: 0143002c .word 0x0143002c +10002c0c: 0138002c .word 0x0138002c +10002c10: 002c002c .word 0x002c002c +10002c14: 002c002c .word 0x002c002c +10002c18: 002c002c .word 0x002c002c +10002c1c: 0027002c .word 0x0027002c +10002c20: 002c002c .word 0x002c002c +10002c24: 002c002c .word 0x002c002c +10002c28: 0027002c .word 0x0027002c +10002c2c: 4614 mov r4, r2 +10002c2e: f043 0301 orr.w r3, r3, #1 +10002c32: e7c2 b.n 10002bba <_vsnprintf+0x56> +10002c34: 4614 mov r4, r2 +10002c36: f043 0302 orr.w r3, r3, #2 +10002c3a: e7be b.n 10002bba <_vsnprintf+0x56> +10002c3c: 4614 mov r4, r2 +10002c3e: f043 0304 orr.w r3, r3, #4 +10002c42: e7ba b.n 10002bba <_vsnprintf+0x56> +10002c44: 4614 mov r4, r2 +10002c46: f043 0310 orr.w r3, r3, #16 +10002c4a: e7b6 b.n 10002bba <_vsnprintf+0x56> +10002c4c: 4614 mov r4, r2 +10002c4e: f043 0308 orr.w r3, r3, #8 +10002c52: e7b2 b.n 10002bba <_vsnprintf+0x56> +10002c54: 9909 ldr r1, [sp, #36] @ 0x24 +10002c56: 7848 ldrb r0, [r1, #1] +10002c58: f443 7380 orr.w r3, r3, #256 @ 0x100 +10002c5c: 3201 adds r2, #1 +10002c5e: 2867 cmp r0, #103 @ 0x67 +10002c60: 9209 str r2, [sp, #36] @ 0x24 +10002c62: d87e bhi.n 10002d62 <_vsnprintf+0x1fe> +10002c64: 2824 cmp r0, #36 @ 0x24 +10002c66: f240 80c1 bls.w 10002dec <_vsnprintf+0x288> +10002c6a: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +10002c6e: 2a42 cmp r2, #66 @ 0x42 +10002c70: f200 80bc bhi.w 10002dec <_vsnprintf+0x288> +10002c74: e8df f012 tbh [pc, r2, lsl #1] +10002c78: 00ba0150 .word 0x00ba0150 +10002c7c: 00ba00ba .word 0x00ba00ba +10002c80: 00ba00ba .word 0x00ba00ba +10002c84: 00ba00ba .word 0x00ba00ba +10002c88: 00ba00ba .word 0x00ba00ba +10002c8c: 00ba00ba .word 0x00ba00ba +10002c90: 00ba00ba .word 0x00ba00ba +10002c94: 00ba00ba .word 0x00ba00ba +10002c98: 00ba00ba .word 0x00ba00ba +10002c9c: 00ba00ba .word 0x00ba00ba +10002ca0: 00ba00ba .word 0x00ba00ba +10002ca4: 00ba00ba .word 0x00ba00ba +10002ca8: 00ba00ba .word 0x00ba00ba +10002cac: 00ba00ba .word 0x00ba00ba +10002cb0: 00ba00ba .word 0x00ba00ba +10002cb4: 00ba00ba .word 0x00ba00ba +10002cb8: 01370119 .word 0x01370119 +10002cbc: 00ba0119 .word 0x00ba0119 +10002cc0: 00ba00ba .word 0x00ba00ba +10002cc4: 00ba00ba .word 0x00ba00ba +10002cc8: 00ba00ba .word 0x00ba00ba +10002ccc: 00ba00ba .word 0x00ba00ba +10002cd0: 00ba00ba .word 0x00ba00ba +10002cd4: 00ba00ba .word 0x00ba00ba +10002cd8: 00ba00ba .word 0x00ba00ba +10002cdc: 01bc00ba .word 0x01bc00ba +10002ce0: 00ba00ba .word 0x00ba00ba +10002ce4: 00ba00ba .word 0x00ba00ba +10002ce8: 00ba00ba .word 0x00ba00ba +10002cec: 00ba00ba .word 0x00ba00ba +10002cf0: 01bc00ba .word 0x01bc00ba +10002cf4: 01bc0158 .word 0x01bc0158 +10002cf8: 01370119 .word 0x01370119 +10002cfc: 0119 .short 0x0119 +10002cfe: 2500 movs r5, #0 +10002d00: e000 b.n 10002d04 <_vsnprintf+0x1a0> +10002d02: 3201 adds r2, #1 +10002d04: eb05 0585 add.w r5, r5, r5, lsl #2 +10002d08: eb00 0545 add.w r5, r0, r5, lsl #1 +10002d0c: 7810 ldrb r0, [r2, #0] +10002d0e: 3d30 subs r5, #48 @ 0x30 +10002d10: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +10002d14: 2909 cmp r1, #9 +10002d16: d9f4 bls.n 10002d02 <_vsnprintf+0x19e> +10002d18: 282e cmp r0, #46 @ 0x2e +10002d1a: 9209 str r2, [sp, #36] @ 0x24 +10002d1c: f102 0201 add.w r2, r2, #1 +10002d20: f47f af6a bne.w 10002bf8 <_vsnprintf+0x94> +10002d24: 9909 ldr r1, [sp, #36] @ 0x24 +10002d26: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002d2a: 7848 ldrb r0, [r1, #1] +10002d2c: 4611 mov r1, r2 +10002d2e: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002d32: 2e09 cmp r6, #9 +10002d34: f240 8121 bls.w 10002f7a <_vsnprintf+0x416> +10002d38: 282a cmp r0, #42 @ 0x2a +10002d3a: f000 812f beq.w 10002f9c <_vsnprintf+0x438> +10002d3e: 9209 str r2, [sp, #36] @ 0x24 +10002d40: 2600 movs r6, #0 +10002d42: 3201 adds r2, #1 +10002d44: e759 b.n 10002bfa <_vsnprintf+0x96> +10002d46: 4644 mov r4, r8 +10002d48: 45c1 cmp r9, r8 +10002d4a: d801 bhi.n 10002d50 <_vsnprintf+0x1ec> +10002d4c: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002d50: 464b mov r3, r9 +10002d52: 4642 mov r2, r8 +10002d54: 4651 mov r1, sl +10002d56: 2000 movs r0, #0 +10002d58: 47d8 blx fp +10002d5a: 4620 mov r0, r4 +10002d5c: b01b add sp, #108 @ 0x6c +10002d5e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002d62: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +10002d66: b2d2 uxtb r2, r2 +10002d68: 2a0f cmp r2, #15 +10002d6a: d83f bhi.n 10002dec <_vsnprintf+0x288> +10002d6c: 2101 movs r1, #1 +10002d6e: f249 0741 movw r7, #36929 @ 0x9041 +10002d72: 4091 lsls r1, r2 +10002d74: 4039 ands r1, r7 +10002d76: f040 80f3 bne.w 10002f60 <_vsnprintf+0x3fc> +10002d7a: 2a0a cmp r2, #10 +10002d7c: d03d beq.n 10002dfa <_vsnprintf+0x296> +10002d7e: 2a07 cmp r2, #7 +10002d80: d134 bne.n 10002dec <_vsnprintf+0x288> +10002d82: 9d0a ldr r5, [sp, #40] @ 0x28 +10002d84: f855 2b04 ldr.w r2, [r5], #4 +10002d88: 2a00 cmp r2, #0 +10002d8a: f000 8113 beq.w 10002fb4 <_vsnprintf+0x450> +10002d8e: f043 0021 orr.w r0, r3, #33 @ 0x21 +10002d92: ab12 add r3, sp, #72 @ 0x48 +10002d94: 461f mov r7, r3 +10002d96: 930b str r3, [sp, #44] @ 0x2c +10002d98: e003 b.n 10002da2 <_vsnprintf+0x23e> +10002d9a: 2920 cmp r1, #32 +10002d9c: f000 8114 beq.w 10002fc8 <_vsnprintf+0x464> +10002da0: 461a mov r2, r3 +10002da2: f002 040f and.w r4, r2, #15 +10002da6: 4623 mov r3, r4 +10002da8: 2c09 cmp r4, #9 +10002daa: bf94 ite ls +10002dac: 3330 addls r3, #48 @ 0x30 +10002dae: 3337 addhi r3, #55 @ 0x37 +10002db0: 2a0f cmp r2, #15 +10002db2: f807 3b01 strb.w r3, [r7], #1 +10002db6: f101 0101 add.w r1, r1, #1 +10002dba: ea4f 1312 mov.w r3, r2, lsr #4 +10002dbe: d8ec bhi.n 10002d9a <_vsnprintf+0x236> +10002dc0: e102 b.n 10002fc8 <_vsnprintf+0x464> +10002dc2: bf00 nop +10002dc4: 10002b65 .word 0x10002b65 +10002dc8: 20000824 .word 0x20000824 +10002dcc: 10001ea9 .word 0x10001ea9 +10002dd0: 990a ldr r1, [sp, #40] @ 0x28 +10002dd2: 9809 ldr r0, [sp, #36] @ 0x24 +10002dd4: f851 5b04 ldr.w r5, [r1], #4 +10002dd8: 7840 ldrb r0, [r0, #1] +10002dda: 2d00 cmp r5, #0 +10002ddc: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002de0: bfbc itt lt +10002de2: f043 0302 orrlt.w r3, r3, #2 +10002de6: 426d neglt r5, r5 +10002de8: 3201 adds r2, #1 +10002dea: e702 b.n 10002bf2 <_vsnprintf+0x8e> +10002dec: 4642 mov r2, r8 +10002dee: 464b mov r3, r9 +10002df0: 4651 mov r1, sl +10002df2: f108 0801 add.w r8, r8, #1 +10002df6: 47d8 blx fp +10002df8: e6d2 b.n 10002ba0 <_vsnprintf+0x3c> +10002dfa: 990a ldr r1, [sp, #40] @ 0x28 +10002dfc: 2e00 cmp r6, #0 +10002dfe: f851 7b04 ldr.w r7, [r1], #4 +10002e02: bf18 it ne +10002e04: 4632 movne r2, r6 +10002e06: 7838 ldrb r0, [r7, #0] +10002e08: bf08 it eq +10002e0a: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002e0e: 2800 cmp r0, #0 +10002e10: f000 837b beq.w 1000350a <_vsnprintf+0x9a6> +10002e14: 18bc adds r4, r7, r2 +10002e16: 46a4 mov ip, r4 +10002e18: 463a mov r2, r7 +10002e1a: e004 b.n 10002e26 <_vsnprintf+0x2c2> +10002e1c: f812 4f01 ldrb.w r4, [r2, #1]! +10002e20: 2c00 cmp r4, #0 +10002e22: f000 813f beq.w 100030a4 <_vsnprintf+0x540> +10002e26: 4594 cmp ip, r2 +10002e28: d1f8 bne.n 10002e1c <_vsnprintf+0x2b8> +10002e2a: 4664 mov r4, ip +10002e2c: 1be4 subs r4, r4, r7 +10002e2e: 055a lsls r2, r3, #21 +10002e30: f140 8122 bpl.w 10003078 <_vsnprintf+0x514> +10002e34: 42b4 cmp r4, r6 +10002e36: bf28 it cs +10002e38: 4634 movcs r4, r6 +10002e3a: f013 0302 ands.w r3, r3, #2 +10002e3e: f000 8288 beq.w 10003352 <_vsnprintf+0x7ee> +10002e42: 2302 movs r3, #2 +10002e44: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002e48: 4642 mov r2, r8 +10002e4a: 461d mov r5, r3 +10002e4c: 4446 add r6, r8 +10002e4e: e008 b.n 10002e62 <_vsnprintf+0x2fe> +10002e50: 464b mov r3, r9 +10002e52: 4651 mov r1, sl +10002e54: 47d8 blx fp +10002e56: f817 0f01 ldrb.w r0, [r7, #1]! +10002e5a: f108 0801 add.w r8, r8, #1 +10002e5e: b110 cbz r0, 10002e66 <_vsnprintf+0x302> +10002e60: 4642 mov r2, r8 +10002e62: 4546 cmp r6, r8 +10002e64: d1f4 bne.n 10002e50 <_vsnprintf+0x2ec> +10002e66: 462b mov r3, r5 +10002e68: 990b ldr r1, [sp, #44] @ 0x2c +10002e6a: 9d0a ldr r5, [sp, #40] @ 0x28 +10002e6c: 2b00 cmp r3, #0 +10002e6e: f040 8141 bne.w 100030f4 <_vsnprintf+0x590> +10002e72: 910a str r1, [sp, #40] @ 0x28 +10002e74: e694 b.n 10002ba0 <_vsnprintf+0x3c> +10002e76: 9909 ldr r1, [sp, #36] @ 0x24 +10002e78: 7848 ldrb r0, [r1, #1] +10002e7a: 286c cmp r0, #108 @ 0x6c +10002e7c: f47f aeec bne.w 10002c58 <_vsnprintf+0xf4> +10002e80: 460a mov r2, r1 +10002e82: 7888 ldrb r0, [r1, #2] +10002e84: f443 7340 orr.w r3, r3, #768 @ 0x300 +10002e88: 3203 adds r2, #3 +10002e8a: e6e8 b.n 10002c5e <_vsnprintf+0xfa> +10002e8c: 9909 ldr r1, [sp, #36] @ 0x24 +10002e8e: f443 7300 orr.w r3, r3, #512 @ 0x200 +10002e92: 7848 ldrb r0, [r1, #1] +10002e94: 3201 adds r2, #1 +10002e96: e6e2 b.n 10002c5e <_vsnprintf+0xfa> +10002e98: 9909 ldr r1, [sp, #36] @ 0x24 +10002e9a: 7848 ldrb r0, [r1, #1] +10002e9c: 2868 cmp r0, #104 @ 0x68 +10002e9e: f000 8103 beq.w 100030a8 <_vsnprintf+0x544> +10002ea2: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002ea6: 3201 adds r2, #1 +10002ea8: e6d9 b.n 10002c5e <_vsnprintf+0xfa> +10002eaa: 2867 cmp r0, #103 @ 0x67 +10002eac: f000 80d9 beq.w 10003062 <_vsnprintf+0x4fe> +10002eb0: 2847 cmp r0, #71 @ 0x47 +10002eb2: f000 80dc beq.w 1000306e <_vsnprintf+0x50a> +10002eb6: 2845 cmp r0, #69 @ 0x45 +10002eb8: f000 80db beq.w 10003072 <_vsnprintf+0x50e> +10002ebc: e9cd 5303 strd r5, r3, [sp, #12] +10002ec0: 9b0a ldr r3, [sp, #40] @ 0x28 +10002ec2: 9602 str r6, [sp, #8] +10002ec4: 3307 adds r3, #7 +10002ec6: f023 0307 bic.w r3, r3, #7 +10002eca: 461c mov r4, r3 +10002ecc: 4642 mov r2, r8 +10002ece: e8f4 6702 ldrd r6, r7, [r4], #8 +10002ed2: 464b mov r3, r9 +10002ed4: 4651 mov r1, sl +10002ed6: 4658 mov r0, fp +10002ed8: e9cd 6700 strd r6, r7, [sp] +10002edc: 940a str r4, [sp, #40] @ 0x28 +10002ede: f7ff fb87 bl 100025f0 <_etoa> +10002ee2: 4680 mov r8, r0 +10002ee4: e65c b.n 10002ba0 <_vsnprintf+0x3c> +10002ee6: 2846 cmp r0, #70 @ 0x46 +10002ee8: bf08 it eq +10002eea: f043 0320 orreq.w r3, r3, #32 +10002eee: e9cd 5303 strd r5, r3, [sp, #12] +10002ef2: 9b0a ldr r3, [sp, #40] @ 0x28 +10002ef4: 9602 str r6, [sp, #8] +10002ef6: 3307 adds r3, #7 +10002ef8: f023 0307 bic.w r3, r3, #7 +10002efc: 461c mov r4, r3 +10002efe: 4642 mov r2, r8 +10002f00: e8f4 6702 ldrd r6, r7, [r4], #8 +10002f04: 464b mov r3, r9 +10002f06: 4651 mov r1, sl +10002f08: 4658 mov r0, fp +10002f0a: e9cd 6700 strd r6, r7, [sp] +10002f0e: 940a str r4, [sp, #40] @ 0x28 +10002f10: f7ff f90e bl 10002130 <_ftoa> +10002f14: 4680 mov r8, r0 +10002f16: e643 b.n 10002ba0 <_vsnprintf+0x3c> +10002f18: 4642 mov r2, r8 +10002f1a: 464b mov r3, r9 +10002f1c: 4651 mov r1, sl +10002f1e: 2025 movs r0, #37 @ 0x25 +10002f20: f108 0801 add.w r8, r8, #1 +10002f24: 47d8 blx fp +10002f26: e63b b.n 10002ba0 <_vsnprintf+0x3c> +10002f28: 9a0a ldr r2, [sp, #40] @ 0x28 +10002f2a: 0799 lsls r1, r3, #30 +10002f2c: f102 0404 add.w r4, r2, #4 +10002f30: f108 0601 add.w r6, r8, #1 +10002f34: f140 80c6 bpl.w 100030c4 <_vsnprintf+0x560> +10002f38: 7810 ldrb r0, [r2, #0] +10002f3a: 464b mov r3, r9 +10002f3c: 4642 mov r2, r8 +10002f3e: 4651 mov r1, sl +10002f40: 47d8 blx fp +10002f42: 2d01 cmp r5, #1 +10002f44: bf88 it hi +10002f46: 44a8 addhi r8, r5 +10002f48: f240 81bd bls.w 100032c6 <_vsnprintf+0x762> +10002f4c: 4632 mov r2, r6 +10002f4e: 464b mov r3, r9 +10002f50: 4651 mov r1, sl +10002f52: 2020 movs r0, #32 +10002f54: 3601 adds r6, #1 +10002f56: 47d8 blx fp +10002f58: 4546 cmp r6, r8 +10002f5a: d1f7 bne.n 10002f4c <_vsnprintf+0x3e8> +10002f5c: 940a str r4, [sp, #40] @ 0x28 +10002f5e: e61f b.n 10002ba0 <_vsnprintf+0x3c> +10002f60: 286f cmp r0, #111 @ 0x6f +10002f62: f000 8081 beq.w 10003068 <_vsnprintf+0x504> +10002f66: f240 8248 bls.w 100033fa <_vsnprintf+0x896> +10002f6a: 2878 cmp r0, #120 @ 0x78 +10002f6c: f000 8190 beq.w 10003290 <_vsnprintf+0x72c> +10002f70: 270a movs r7, #10 +10002f72: f023 0310 bic.w r3, r3, #16 +10002f76: 46bc mov ip, r7 +10002f78: e041 b.n 10002ffe <_vsnprintf+0x49a> +10002f7a: 2600 movs r6, #0 +10002f7c: eb06 0686 add.w r6, r6, r6, lsl #2 +10002f80: eb00 0046 add.w r0, r0, r6, lsl #1 +10002f84: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002f88: f811 0f01 ldrb.w r0, [r1, #1]! +10002f8c: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002f90: 2a09 cmp r2, #9 +10002f92: d9f3 bls.n 10002f7c <_vsnprintf+0x418> +10002f94: 460a mov r2, r1 +10002f96: 9109 str r1, [sp, #36] @ 0x24 +10002f98: 3201 adds r2, #1 +10002f9a: e62e b.n 10002bfa <_vsnprintf+0x96> +10002f9c: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002fa0: f851 6b04 ldr.w r6, [r1], #4 +10002fa4: 7890 ldrb r0, [r2, #2] +10002fa6: 3202 adds r2, #2 +10002fa8: 9209 str r2, [sp, #36] @ 0x24 +10002faa: 910a str r1, [sp, #40] @ 0x28 +10002fac: 3201 adds r2, #1 +10002fae: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002fb2: e622 b.n 10002bfa <_vsnprintf+0x96> +10002fb4: f023 0010 bic.w r0, r3, #16 +10002fb8: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002fbc: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002fc0: f43f aee7 beq.w 10002d92 <_vsnprintf+0x22e> +10002fc4: ab12 add r3, sp, #72 @ 0x48 +10002fc6: 930b str r3, [sp, #44] @ 0x2c +10002fc8: 9b0b ldr r3, [sp, #44] @ 0x2c +10002fca: 9006 str r0, [sp, #24] +10002fcc: 9300 str r3, [sp, #0] +10002fce: 2308 movs r3, #8 +10002fd0: 2010 movs r0, #16 +10002fd2: 9305 str r3, [sp, #20] +10002fd4: 2300 movs r3, #0 +10002fd6: 4642 mov r2, r8 +10002fd8: e9cd 3002 strd r3, r0, [sp, #8] +10002fdc: 9101 str r1, [sp, #4] +10002fde: 464b mov r3, r9 +10002fe0: 4651 mov r1, sl +10002fe2: 4658 mov r0, fp +10002fe4: 9604 str r6, [sp, #16] +10002fe6: f7fe ffaf bl 10001f48 <_ntoa_format> +10002fea: 950a str r5, [sp, #40] @ 0x28 +10002fec: 4680 mov r8, r0 +10002fee: e5d7 b.n 10002ba0 <_vsnprintf+0x3c> +10002ff0: 2858 cmp r0, #88 @ 0x58 +10002ff2: d062 beq.n 100030ba <_vsnprintf+0x556> +10002ff4: 2862 cmp r0, #98 @ 0x62 +10002ff6: f040 808f bne.w 10003118 <_vsnprintf+0x5b4> +10002ffa: 2702 movs r7, #2 +10002ffc: 46bc mov ip, r7 +10002ffe: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10003002: f000 80dd beq.w 100031c0 <_vsnprintf+0x65c> +10003006: f023 030d bic.w r3, r3, #13 +1000300a: f413 7200 ands.w r2, r3, #512 @ 0x200 +1000300e: f040 8181 bne.w 10003314 <_vsnprintf+0x7b0> +10003012: 990a ldr r1, [sp, #40] @ 0x28 +10003014: 1d0f adds r7, r1, #4 +10003016: f413 7180 ands.w r1, r3, #256 @ 0x100 +1000301a: f040 8237 bne.w 1000348c <_vsnprintf+0x928> +1000301e: 065c lsls r4, r3, #25 +10003020: 9a0a ldr r2, [sp, #40] @ 0x28 +10003022: f140 813b bpl.w 1000329c <_vsnprintf+0x738> +10003026: 7812 ldrb r2, [r2, #0] +10003028: 2a00 cmp r2, #0 +1000302a: f040 814e bne.w 100032ca <_vsnprintf+0x766> +1000302e: f023 0310 bic.w r3, r3, #16 +10003032: 2800 cmp r0, #0 +10003034: f000 8149 beq.w 100032ca <_vsnprintf+0x766> +10003038: 4611 mov r1, r2 +1000303a: aa12 add r2, sp, #72 @ 0x48 +1000303c: 920b str r2, [sp, #44] @ 0x2c +1000303e: e9cd 5305 strd r5, r3, [sp, #20] +10003042: e9cd c603 strd ip, r6, [sp, #12] +10003046: 9101 str r1, [sp, #4] +10003048: 9b0b ldr r3, [sp, #44] @ 0x2c +1000304a: 4642 mov r2, r8 +1000304c: 9300 str r3, [sp, #0] +1000304e: 2300 movs r3, #0 +10003050: 4651 mov r1, sl +10003052: 9302 str r3, [sp, #8] +10003054: 4658 mov r0, fp +10003056: 464b mov r3, r9 +10003058: f7fe ff76 bl 10001f48 <_ntoa_format> +1000305c: 970a str r7, [sp, #40] @ 0x28 +1000305e: 4680 mov r8, r0 +10003060: e59e b.n 10002ba0 <_vsnprintf+0x3c> +10003062: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10003066: e729 b.n 10002ebc <_vsnprintf+0x358> +10003068: 2708 movs r7, #8 +1000306a: 46bc mov ip, r7 +1000306c: e7c7 b.n 10002ffe <_vsnprintf+0x49a> +1000306e: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10003072: f043 0320 orr.w r3, r3, #32 +10003076: e721 b.n 10002ebc <_vsnprintf+0x358> +10003078: f013 0302 ands.w r3, r3, #2 +1000307c: f000 818e beq.w 1000339c <_vsnprintf+0x838> +10003080: 2302 movs r3, #2 +10003082: 950a str r5, [sp, #40] @ 0x28 +10003084: 461e mov r6, r3 +10003086: 460d mov r5, r1 +10003088: 4642 mov r2, r8 +1000308a: 464b mov r3, r9 +1000308c: 4651 mov r1, sl +1000308e: 47d8 blx fp +10003090: f817 0f01 ldrb.w r0, [r7, #1]! +10003094: f108 0801 add.w r8, r8, #1 +10003098: 2800 cmp r0, #0 +1000309a: d1f5 bne.n 10003088 <_vsnprintf+0x524> +1000309c: 4629 mov r1, r5 +1000309e: 4633 mov r3, r6 +100030a0: 9d0a ldr r5, [sp, #40] @ 0x28 +100030a2: e6e3 b.n 10002e6c <_vsnprintf+0x308> +100030a4: 1bd4 subs r4, r2, r7 +100030a6: e6c2 b.n 10002e2e <_vsnprintf+0x2ca> +100030a8: 460a mov r2, r1 +100030aa: 7888 ldrb r0, [r1, #2] +100030ac: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +100030b0: 3203 adds r2, #3 +100030b2: e5d4 b.n 10002c5e <_vsnprintf+0xfa> +100030b4: 4604 mov r4, r0 +100030b6: 4680 mov r8, r0 +100030b8: e646 b.n 10002d48 <_vsnprintf+0x1e4> +100030ba: 2710 movs r7, #16 +100030bc: f043 0320 orr.w r3, r3, #32 +100030c0: 46bc mov ip, r7 +100030c2: e79c b.n 10002ffe <_vsnprintf+0x49a> +100030c4: 2d01 cmp r5, #1 +100030c6: f240 80f8 bls.w 100032ba <_vsnprintf+0x756> +100030ca: 4646 mov r6, r8 +100030cc: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +100030d0: 442f add r7, r5 +100030d2: 4632 mov r2, r6 +100030d4: 464b mov r3, r9 +100030d6: 4651 mov r1, sl +100030d8: 2020 movs r0, #32 +100030da: 3601 adds r6, #1 +100030dc: 47d8 blx fp +100030de: 42be cmp r6, r7 +100030e0: d1f7 bne.n 100030d2 <_vsnprintf+0x56e> +100030e2: 9b0a ldr r3, [sp, #40] @ 0x28 +100030e4: 4632 mov r2, r6 +100030e6: 7818 ldrb r0, [r3, #0] +100030e8: 4651 mov r1, sl +100030ea: 464b mov r3, r9 +100030ec: 47d8 blx fp +100030ee: 44a8 add r8, r5 +100030f0: 940a str r4, [sp, #40] @ 0x28 +100030f2: e555 b.n 10002ba0 <_vsnprintf+0x3c> +100030f4: 4646 mov r6, r8 +100030f6: 42a5 cmp r5, r4 +100030f8: f67f aebb bls.w 10002e72 <_vsnprintf+0x30e> +100030fc: 44a8 add r8, r5 +100030fe: eba8 0804 sub.w r8, r8, r4 +10003102: 460c mov r4, r1 +10003104: 4632 mov r2, r6 +10003106: 464b mov r3, r9 +10003108: 4651 mov r1, sl +1000310a: 2020 movs r0, #32 +1000310c: 3601 adds r6, #1 +1000310e: 47d8 blx fp +10003110: 4546 cmp r6, r8 +10003112: d1f7 bne.n 10003104 <_vsnprintf+0x5a0> +10003114: 4621 mov r1, r4 +10003116: e6ac b.n 10002e72 <_vsnprintf+0x30e> +10003118: f413 6280 ands.w r2, r3, #1024 @ 0x400 +1000311c: f000 80bb beq.w 10003296 <_vsnprintf+0x732> +10003120: f44f 6280 mov.w r2, #1024 @ 0x400 +10003124: f023 0c11 bic.w ip, r3, #17 +10003128: f41c 7700 ands.w r7, ip, #512 @ 0x200 +1000312c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000312e: d14a bne.n 100031c6 <_vsnprintf+0x662> +10003130: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10003134: f103 0404 add.w r4, r3, #4 +10003138: f040 8134 bne.w 100033a4 <_vsnprintf+0x840> +1000313c: f01c 0f40 tst.w ip, #64 @ 0x40 +10003140: f040 80a3 bne.w 1000328a <_vsnprintf+0x726> +10003144: f01c 0f80 tst.w ip, #128 @ 0x80 +10003148: f000 81d3 beq.w 100034f2 <_vsnprintf+0x98e> +1000314c: f9b3 1000 ldrsh.w r1, [r3] +10003150: ea81 77e1 eor.w r7, r1, r1, asr #31 +10003154: eba7 77e1 sub.w r7, r7, r1, asr #31 +10003158: b2bf uxth r7, r7 +1000315a: 0fcb lsrs r3, r1, #31 +1000315c: 2900 cmp r1, #0 +1000315e: f000 8156 beq.w 1000340e <_vsnprintf+0x8aa> +10003162: 463a mov r2, r7 +10003164: a912 add r1, sp, #72 @ 0x48 +10003166: 460f mov r7, r1 +10003168: f8df e3d8 ldr.w lr, [pc, #984] @ 10003544 <_vsnprintf+0x9e0> +1000316c: 910b str r1, [sp, #44] @ 0x2c +1000316e: 930a str r3, [sp, #40] @ 0x28 +10003170: 950c str r5, [sp, #48] @ 0x30 +10003172: e001 b.n 10003178 <_vsnprintf+0x614> +10003174: 2820 cmp r0, #32 +10003176: d00f beq.n 10003198 <_vsnprintf+0x634> +10003178: 4615 mov r5, r2 +1000317a: fbae 1302 umull r1, r3, lr, r2 +1000317e: 08db lsrs r3, r3, #3 +10003180: eb03 0183 add.w r1, r3, r3, lsl #2 +10003184: eba2 0141 sub.w r1, r2, r1, lsl #1 +10003188: 3130 adds r1, #48 @ 0x30 +1000318a: 2d09 cmp r5, #9 +1000318c: 461a mov r2, r3 +1000318e: f100 0001 add.w r0, r0, #1 +10003192: f807 1b01 strb.w r1, [r7], #1 +10003196: d8ed bhi.n 10003174 <_vsnprintf+0x610> +10003198: 9b0a ldr r3, [sp, #40] @ 0x28 +1000319a: 9d0c ldr r5, [sp, #48] @ 0x30 +1000319c: e9cd 5c05 strd r5, ip, [sp, #20] +100031a0: e9cd 0301 strd r0, r3, [sp, #4] +100031a4: 9604 str r6, [sp, #16] +100031a6: 9b0b ldr r3, [sp, #44] @ 0x2c +100031a8: 4642 mov r2, r8 +100031aa: 9300 str r3, [sp, #0] +100031ac: 230a movs r3, #10 +100031ae: 4651 mov r1, sl +100031b0: 9303 str r3, [sp, #12] +100031b2: 4658 mov r0, fp +100031b4: 464b mov r3, r9 +100031b6: f7fe fec7 bl 10001f48 <_ntoa_format> +100031ba: 940a str r4, [sp, #40] @ 0x28 +100031bc: 4680 mov r8, r0 +100031be: e4ef b.n 10002ba0 <_vsnprintf+0x3c> +100031c0: f023 030c bic.w r3, r3, #12 +100031c4: e721 b.n 1000300a <_vsnprintf+0x4a6> +100031c6: 3307 adds r3, #7 +100031c8: f023 0307 bic.w r3, r3, #7 +100031cc: 4619 mov r1, r3 +100031ce: 4608 mov r0, r1 +100031d0: 685b ldr r3, [r3, #4] +100031d2: f850 1b08 ldr.w r1, [r0], #8 +100031d6: 0fdf lsrs r7, r3, #31 +100031d8: 900a str r0, [sp, #40] @ 0x28 +100031da: ea51 0003 orrs.w r0, r1, r3 +100031de: d162 bne.n 100032a6 <_vsnprintf+0x742> +100031e0: 2a00 cmp r2, #0 +100031e2: f040 819f bne.w 10003524 <_vsnprintf+0x9c0> +100031e6: 4613 mov r3, r2 +100031e8: 4611 mov r1, r2 +100031ea: aa12 add r2, sp, #72 @ 0x48 +100031ec: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +100031f0: 2000 movs r0, #0 +100031f2: 4615 mov r5, r2 +100031f4: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +100031f8: f8df e348 ldr.w lr, [pc, #840] @ 10003544 <_vsnprintf+0x9e0> +100031fc: 920b str r2, [sp, #44] @ 0x2c +100031fe: e001 b.n 10003204 <_vsnprintf+0x6a0> +10003200: 2820 cmp r0, #32 +10003202: d02d beq.n 10003260 <_vsnprintf+0x6fc> +10003204: 185a adds r2, r3, r1 +10003206: f142 0200 adc.w r2, r2, #0 +1000320a: fbae 7802 umull r7, r8, lr, r2 +1000320e: f028 0703 bic.w r7, r8, #3 +10003212: eb07 0798 add.w r7, r7, r8, lsr #2 +10003216: 1bd2 subs r2, r2, r7 +10003218: 461e mov r6, r3 +1000321a: 1a9b subs r3, r3, r2 +1000321c: f161 0700 sbc.w r7, r1, #0 +10003220: 460c mov r4, r1 +10003222: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10003226: fb01 f103 mul.w r1, r1, r3 +1000322a: fb0e 1107 mla r1, lr, r7, r1 +1000322e: fba3 730e umull r7, r3, r3, lr +10003232: 4419 add r1, r3 +10003234: 2305 movs r3, #5 +10003236: f007 0801 and.w r8, r7, #1 +1000323a: fba8 3803 umull r3, r8, r8, r3 +1000323e: 189b adds r3, r3, r2 +10003240: 2e0a cmp r6, #10 +10003242: f103 0330 add.w r3, r3, #48 @ 0x30 +10003246: ea4f 0757 mov.w r7, r7, lsr #1 +1000324a: f174 0400 sbcs.w r4, r4, #0 +1000324e: f805 3b01 strb.w r3, [r5], #1 +10003252: f100 0001 add.w r0, r0, #1 +10003256: ea47 73c1 orr.w r3, r7, r1, lsl #31 +1000325a: ea4f 0151 mov.w r1, r1, lsr #1 +1000325e: d2cf bcs.n 10003200 <_vsnprintf+0x69c> +10003260: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10003264: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10003268: 9b0b ldr r3, [sp, #44] @ 0x2c +1000326a: 4642 mov r2, r8 +1000326c: 9300 str r3, [sp, #0] +1000326e: 230a movs r3, #10 +10003270: e9cd 5c05 strd r5, ip, [sp, #20] +10003274: e9cd 0701 strd r0, r7, [sp, #4] +10003278: 9604 str r6, [sp, #16] +1000327a: 9303 str r3, [sp, #12] +1000327c: 464b mov r3, r9 +1000327e: 4651 mov r1, sl +10003280: 4658 mov r0, fp +10003282: f7fe fe61 bl 10001f48 <_ntoa_format> +10003286: 4680 mov r8, r0 +10003288: e48a b.n 10002ba0 <_vsnprintf+0x3c> +1000328a: 7819 ldrb r1, [r3, #0] +1000328c: 460f mov r7, r1 +1000328e: e764 b.n 1000315a <_vsnprintf+0x5f6> +10003290: 2710 movs r7, #16 +10003292: 46bc mov ip, r7 +10003294: e6b3 b.n 10002ffe <_vsnprintf+0x49a> +10003296: f023 0c10 bic.w ip, r3, #16 +1000329a: e745 b.n 10003128 <_vsnprintf+0x5c4> +1000329c: 061c lsls r4, r3, #24 +1000329e: bf4c ite mi +100032a0: 8812 ldrhmi r2, [r2, #0] +100032a2: 6812 ldrpl r2, [r2, #0] +100032a4: e6c0 b.n 10003028 <_vsnprintf+0x4c4> +100032a6: 460a mov r2, r1 +100032a8: 1e19 subs r1, r3, #0 +100032aa: db01 blt.n 100032b0 <_vsnprintf+0x74c> +100032ac: 4613 mov r3, r2 +100032ae: e79c b.n 100031ea <_vsnprintf+0x686> +100032b0: 4252 negs r2, r2 +100032b2: 4613 mov r3, r2 +100032b4: eb61 0141 sbc.w r1, r1, r1, lsl #1 +100032b8: e797 b.n 100031ea <_vsnprintf+0x686> +100032ba: 4613 mov r3, r2 +100032bc: 4651 mov r1, sl +100032be: 7818 ldrb r0, [r3, #0] +100032c0: 4642 mov r2, r8 +100032c2: 464b mov r3, r9 +100032c4: 47d8 blx fp +100032c6: 46b0 mov r8, r6 +100032c8: e648 b.n 10002f5c <_vsnprintf+0x3f8> +100032ca: f013 0f20 tst.w r3, #32 +100032ce: bf14 ite ne +100032d0: 2041 movne r0, #65 @ 0x41 +100032d2: 2061 moveq r0, #97 @ 0x61 +100032d4: ac12 add r4, sp, #72 @ 0x48 +100032d6: 46a6 mov lr, r4 +100032d8: 940b str r4, [sp, #44] @ 0x2c +100032da: 930a str r3, [sp, #40] @ 0x28 +100032dc: f1a0 040a sub.w r4, r0, #10 +100032e0: 950c str r5, [sp, #48] @ 0x30 +100032e2: e002 b.n 100032ea <_vsnprintf+0x786> +100032e4: 2920 cmp r1, #32 +100032e6: d012 beq.n 1000330e <_vsnprintf+0x7aa> +100032e8: 462a mov r2, r5 +100032ea: fbb2 f5fc udiv r5, r2, ip +100032ee: fb0c 2015 mls r0, ip, r5, r2 +100032f2: b2c3 uxtb r3, r0 +100032f4: 2809 cmp r0, #9 +100032f6: f103 0030 add.w r0, r3, #48 @ 0x30 +100032fa: bf8a itet hi +100032fc: 191b addhi r3, r3, r4 +100032fe: b2c3 uxtbls r3, r0 +10003300: b2db uxtbhi r3, r3 +10003302: 4562 cmp r2, ip +10003304: f80e 3b01 strb.w r3, [lr], #1 +10003308: f101 0101 add.w r1, r1, #1 +1000330c: d2ea bcs.n 100032e4 <_vsnprintf+0x780> +1000330e: 9b0a ldr r3, [sp, #40] @ 0x28 +10003310: 9d0c ldr r5, [sp, #48] @ 0x30 +10003312: e694 b.n 1000303e <_vsnprintf+0x4da> +10003314: 9a0a ldr r2, [sp, #40] @ 0x28 +10003316: 3207 adds r2, #7 +10003318: f022 0207 bic.w r2, r2, #7 +1000331c: 6851 ldr r1, [r2, #4] +1000331e: f852 4b08 ldr.w r4, [r2], #8 +10003322: 468e mov lr, r1 +10003324: 920a str r2, [sp, #40] @ 0x28 +10003326: ea54 0201 orrs.w r2, r4, r1 +1000332a: d176 bne.n 1000341a <_vsnprintf+0x8b6> +1000332c: f023 0310 bic.w r3, r3, #16 +10003330: 2800 cmp r0, #0 +10003332: d072 beq.n 1000341a <_vsnprintf+0x8b6> +10003334: 2200 movs r2, #0 +10003336: 4611 mov r1, r2 +10003338: aa12 add r2, sp, #72 @ 0x48 +1000333a: 920b str r2, [sp, #44] @ 0x2c +1000333c: e9cd 5305 strd r5, r3, [sp, #20] +10003340: 9b0b ldr r3, [sp, #44] @ 0x2c +10003342: 4642 mov r2, r8 +10003344: 9300 str r3, [sp, #0] +10003346: 2300 movs r3, #0 +10003348: e9cd c603 strd ip, r6, [sp, #12] +1000334c: 9101 str r1, [sp, #4] +1000334e: 9302 str r3, [sp, #8] +10003350: e794 b.n 1000327c <_vsnprintf+0x718> +10003352: 42a5 cmp r5, r4 +10003354: bf98 it ls +10003356: 3401 addls r4, #1 +10003358: f67f ad74 bls.w 10002e44 <_vsnprintf+0x2e0> +1000335c: f44f 6380 mov.w r3, #1024 @ 0x400 +10003360: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10003364: eb05 0208 add.w r2, r5, r8 +10003368: 461f mov r7, r3 +1000336a: 460d mov r5, r1 +1000336c: 1b14 subs r4, r2, r4 +1000336e: 4642 mov r2, r8 +10003370: 464b mov r3, r9 +10003372: 4651 mov r1, sl +10003374: 2020 movs r0, #32 +10003376: f108 0801 add.w r8, r8, #1 +1000337a: 47d8 blx fp +1000337c: 45a0 cmp r8, r4 +1000337e: d1f6 bne.n 1000336e <_vsnprintf+0x80a> +10003380: 463b mov r3, r7 +10003382: 9f0a ldr r7, [sp, #40] @ 0x28 +10003384: 4629 mov r1, r5 +10003386: 7838 ldrb r0, [r7, #0] +10003388: 9d0b ldr r5, [sp, #44] @ 0x2c +1000338a: 1c6c adds r4, r5, #1 +1000338c: 2800 cmp r0, #0 +1000338e: f43f ad70 beq.w 10002e72 <_vsnprintf+0x30e> +10003392: 2b00 cmp r3, #0 +10003394: f43f ae75 beq.w 10003082 <_vsnprintf+0x51e> +10003398: 2300 movs r3, #0 +1000339a: e553 b.n 10002e44 <_vsnprintf+0x2e0> +1000339c: 42a5 cmp r5, r4 +1000339e: d8df bhi.n 10003360 <_vsnprintf+0x7fc> +100033a0: 3401 adds r4, #1 +100033a2: e66e b.n 10003082 <_vsnprintf+0x51e> +100033a4: 6819 ldr r1, [r3, #0] +100033a6: 0fcb lsrs r3, r1, #31 +100033a8: 2900 cmp r1, #0 +100033aa: f000 80a8 beq.w 100034fe <_vsnprintf+0x99a> +100033ae: ea81 72e1 eor.w r2, r1, r1, asr #31 +100033b2: eba2 72e1 sub.w r2, r2, r1, asr #31 +100033b6: a912 add r1, sp, #72 @ 0x48 +100033b8: 4608 mov r0, r1 +100033ba: f8df e188 ldr.w lr, [pc, #392] @ 10003544 <_vsnprintf+0x9e0> +100033be: 910b str r1, [sp, #44] @ 0x2c +100033c0: 930a str r3, [sp, #40] @ 0x28 +100033c2: 950c str r5, [sp, #48] @ 0x30 +100033c4: e001 b.n 100033ca <_vsnprintf+0x866> +100033c6: 2f20 cmp r7, #32 +100033c8: d00f beq.n 100033ea <_vsnprintf+0x886> +100033ca: 4615 mov r5, r2 +100033cc: fbae 1302 umull r1, r3, lr, r2 +100033d0: 08db lsrs r3, r3, #3 +100033d2: eb03 0183 add.w r1, r3, r3, lsl #2 +100033d6: eba2 0141 sub.w r1, r2, r1, lsl #1 +100033da: 3130 adds r1, #48 @ 0x30 +100033dc: 2d09 cmp r5, #9 +100033de: 461a mov r2, r3 +100033e0: f107 0701 add.w r7, r7, #1 +100033e4: f800 1b01 strb.w r1, [r0], #1 +100033e8: d8ed bhi.n 100033c6 <_vsnprintf+0x862> +100033ea: 9b0a ldr r3, [sp, #40] @ 0x28 +100033ec: 9d0c ldr r5, [sp, #48] @ 0x30 +100033ee: e9cd 5c05 strd r5, ip, [sp, #20] +100033f2: e9cd 7301 strd r7, r3, [sp, #4] +100033f6: 9604 str r6, [sp, #16] +100033f8: e6d5 b.n 100031a6 <_vsnprintf+0x642> +100033fa: 2869 cmp r0, #105 @ 0x69 +100033fc: f023 0c10 bic.w ip, r3, #16 +10003400: f040 808c bne.w 1000351c <_vsnprintf+0x9b8> +10003404: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10003408: f43f ae8e beq.w 10003128 <_vsnprintf+0x5c4> +1000340c: e688 b.n 10003120 <_vsnprintf+0x5bc> +1000340e: 2a00 cmp r2, #0 +10003410: f43f aea8 beq.w 10003164 <_vsnprintf+0x600> +10003414: aa12 add r2, sp, #72 @ 0x48 +10003416: 920b str r2, [sp, #44] @ 0x2c +10003418: e6c0 b.n 1000319c <_vsnprintf+0x638> +1000341a: f013 0f20 tst.w r3, #32 +1000341e: bf14 ite ne +10003420: 2241 movne r2, #65 @ 0x41 +10003422: 2261 moveq r2, #97 @ 0x61 +10003424: 2000 movs r0, #0 +10003426: a912 add r1, sp, #72 @ 0x48 +10003428: 3a0a subs r2, #10 +1000342a: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +1000342e: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10003432: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10003436: 4606 mov r6, r0 +10003438: 4688 mov r8, r1 +1000343a: 4675 mov r5, lr +1000343c: 4693 mov fp, r2 +1000343e: 910b str r1, [sp, #44] @ 0x2c +10003440: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10003444: e003 b.n 1000344e <_vsnprintf+0x8ea> +10003446: 2e20 cmp r6, #32 +10003448: d017 beq.n 1000347a <_vsnprintf+0x916> +1000344a: 4604 mov r4, r0 +1000344c: 460d mov r5, r1 +1000344e: 4629 mov r1, r5 +10003450: 463a mov r2, r7 +10003452: 2300 movs r3, #0 +10003454: 4620 mov r0, r4 +10003456: f000 fd17 bl 10003e88 <____aeabi_uldivmod_veneer> +1000345a: b2d2 uxtb r2, r2 +1000345c: 2a09 cmp r2, #9 +1000345e: f102 0330 add.w r3, r2, #48 @ 0x30 +10003462: bf88 it hi +10003464: eb02 030b addhi.w r3, r2, fp +10003468: 42bc cmp r4, r7 +1000346a: b2db uxtb r3, r3 +1000346c: f175 0500 sbcs.w r5, r5, #0 +10003470: f808 3b01 strb.w r3, [r8], #1 +10003474: f106 0601 add.w r6, r6, #1 +10003478: d2e5 bcs.n 10003446 <_vsnprintf+0x8e2> +1000347a: 4631 mov r1, r6 +1000347c: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10003480: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10003484: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10003488: 9e0e ldr r6, [sp, #56] @ 0x38 +1000348a: e757 b.n 1000333c <_vsnprintf+0x7d8> +1000348c: 990a ldr r1, [sp, #40] @ 0x28 +1000348e: 6809 ldr r1, [r1, #0] +10003490: b951 cbnz r1, 100034a8 <_vsnprintf+0x944> +10003492: f023 0310 bic.w r3, r3, #16 +10003496: b138 cbz r0, 100034a8 <_vsnprintf+0x944> +10003498: a912 add r1, sp, #72 @ 0x48 +1000349a: 910b str r1, [sp, #44] @ 0x2c +1000349c: e9cd 5305 strd r5, r3, [sp, #20] +100034a0: e9cd c603 strd ip, r6, [sp, #12] +100034a4: 9201 str r2, [sp, #4] +100034a6: e5cf b.n 10003048 <_vsnprintf+0x4e4> +100034a8: f013 0f20 tst.w r3, #32 +100034ac: bf14 ite ne +100034ae: 2041 movne r0, #65 @ 0x41 +100034b0: 2061 moveq r0, #97 @ 0x61 +100034b2: ac12 add r4, sp, #72 @ 0x48 +100034b4: 46a6 mov lr, r4 +100034b6: 940b str r4, [sp, #44] @ 0x2c +100034b8: 930a str r3, [sp, #40] @ 0x28 +100034ba: f1a0 040a sub.w r4, r0, #10 +100034be: 950c str r5, [sp, #48] @ 0x30 +100034c0: e002 b.n 100034c8 <_vsnprintf+0x964> +100034c2: 2a20 cmp r2, #32 +100034c4: d012 beq.n 100034ec <_vsnprintf+0x988> +100034c6: 4629 mov r1, r5 +100034c8: fbb1 f5fc udiv r5, r1, ip +100034cc: fb0c 1015 mls r0, ip, r5, r1 +100034d0: b2c3 uxtb r3, r0 +100034d2: 2809 cmp r0, #9 +100034d4: f103 0030 add.w r0, r3, #48 @ 0x30 +100034d8: bf8a itet hi +100034da: 191b addhi r3, r3, r4 +100034dc: b2c3 uxtbls r3, r0 +100034de: b2db uxtbhi r3, r3 +100034e0: 4561 cmp r1, ip +100034e2: f80e 3b01 strb.w r3, [lr], #1 +100034e6: f102 0201 add.w r2, r2, #1 +100034ea: d2ea bcs.n 100034c2 <_vsnprintf+0x95e> +100034ec: 9b0a ldr r3, [sp, #40] @ 0x28 +100034ee: 9d0c ldr r5, [sp, #48] @ 0x30 +100034f0: e7d4 b.n 1000349c <_vsnprintf+0x938> +100034f2: 6819 ldr r1, [r3, #0] +100034f4: ea81 77e1 eor.w r7, r1, r1, asr #31 +100034f8: eba7 77e1 sub.w r7, r7, r1, asr #31 +100034fc: e62d b.n 1000315a <_vsnprintf+0x5f6> +100034fe: 2a00 cmp r2, #0 +10003500: f43f af59 beq.w 100033b6 <_vsnprintf+0x852> +10003504: aa12 add r2, sp, #72 @ 0x48 +10003506: 920b str r2, [sp, #44] @ 0x2c +10003508: e771 b.n 100033ee <_vsnprintf+0x88a> +1000350a: f413 6480 ands.w r4, r3, #1024 @ 0x400 +1000350e: d00d beq.n 1000352c <_vsnprintf+0x9c8> +10003510: f013 0402 ands.w r4, r3, #2 +10003514: d012 beq.n 1000353c <_vsnprintf+0x9d8> +10003516: 4604 mov r4, r0 +10003518: 4646 mov r6, r8 +1000351a: e5ec b.n 100030f6 <_vsnprintf+0x592> +1000351c: 270a movs r7, #10 +1000351e: 4663 mov r3, ip +10003520: 46bc mov ip, r7 +10003522: e56c b.n 10002ffe <_vsnprintf+0x49a> +10003524: ab12 add r3, sp, #72 @ 0x48 +10003526: 2000 movs r0, #0 +10003528: 930b str r3, [sp, #44] @ 0x2c +1000352a: e69d b.n 10003268 <_vsnprintf+0x704> +1000352c: f013 0302 ands.w r3, r3, #2 +10003530: f47f ade0 bne.w 100030f4 <_vsnprintf+0x590> +10003534: 2d00 cmp r5, #0 +10003536: f47f af13 bne.w 10003360 <_vsnprintf+0x7fc> +1000353a: e49a b.n 10002e72 <_vsnprintf+0x30e> +1000353c: 2d00 cmp r5, #0 +1000353e: f47f af0d bne.w 1000335c <_vsnprintf+0x7f8> +10003542: e496 b.n 10002e72 <_vsnprintf+0x30e> +10003544: cccccccd .word 0xcccccccd + +10003548 : +10003548: b570 push {r4, r5, r6, lr} +1000354a: 4694 mov ip, r2 +1000354c: 461e mov r6, r3 +1000354e: 4605 mov r5, r0 +10003550: 460c mov r4, r1 +10003552: b084 sub sp, #16 +10003554: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003558: 4663 mov r3, ip +1000355a: a902 add r1, sp, #8 +1000355c: 9600 str r6, [sp, #0] +1000355e: 4803 ldr r0, [pc, #12] @ (1000356c ) +10003560: e9cd 5402 strd r5, r4, [sp, #8] +10003564: f7ff fafe bl 10002b64 <_vsnprintf> +10003568: b004 add sp, #16 +1000356a: bd70 pop {r4, r5, r6, pc} +1000356c: 10002125 .word 0x10002125 + +10003570 : +10003570: b510 push {r4, lr} +10003572: 4b09 ldr r3, [pc, #36] @ (10003598 ) +10003574: b084 sub sp, #16 +10003576: 681c ldr r4, [r3, #0] +10003578: b14c cbz r4, 1000358e +1000357a: 4603 mov r3, r0 +1000357c: 9100 str r1, [sp, #0] +1000357e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003582: a903 add r1, sp, #12 +10003584: 4805 ldr r0, [pc, #20] @ (1000359c ) +10003586: 47a0 blx r4 +10003588: 2001 movs r0, #1 +1000358a: b004 add sp, #16 +1000358c: bd10 pop {r4, pc} +1000358e: f000 f97d bl 1000388c <__wrap_puts> +10003592: 4620 mov r0, r4 +10003594: b004 add sp, #16 +10003596: bd10 pop {r4, pc} +10003598: 20000824 .word 0x20000824 +1000359c: 1000211d .word 0x1000211d + +100035a0 <_exit>: +100035a0: be00 bkpt 0x0000 +100035a2: e7fd b.n 100035a0 <_exit> + +100035a4 : +100035a4: b508 push {r3, lr} +100035a6: f7ff fffb bl 100035a0 <_exit> +100035aa: bf00 nop + +100035ac : +100035ac: b538 push {r3, r4, r5, lr} +100035ae: 4c06 ldr r4, [pc, #24] @ (100035c8 ) +100035b0: 4d06 ldr r5, [pc, #24] @ (100035cc ) +100035b2: f7fe fa07 bl 100019c4 +100035b6: 42ac cmp r4, r5 +100035b8: d204 bcs.n 100035c4 +100035ba: f854 3b04 ldr.w r3, [r4], #4 +100035be: 4798 blx r3 +100035c0: 42ac cmp r4, r5 +100035c2: d3fa bcc.n 100035ba +100035c4: bd38 pop {r3, r4, r5, pc} +100035c6: bf00 nop +100035c8: 10003ee0 .word 0x10003ee0 +100035cc: 10003ee4 .word 0x10003ee4 + +100035d0 : +100035d0: 6803 ldr r3, [r0, #0] +100035d2: 4608 mov r0, r1 +100035d4: 4611 mov r1, r2 +100035d6: 4718 bx r3 + +100035d8 : +100035d8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100035dc: 4615 mov r5, r2 +100035de: 7d42 ldrb r2, [r0, #21] +100035e0: 4607 mov r7, r0 +100035e2: 4688 mov r8, r1 +100035e4: 2a00 cmp r2, #0 +100035e6: d046 beq.n 10003676 +100035e8: 2d00 cmp r5, #0 +100035ea: dd1d ble.n 10003628 +100035ec: 780b ldrb r3, [r1, #0] +100035ee: 2b0a cmp r3, #10 +100035f0: d023 beq.n 1000363a +100035f2: 2d01 cmp r5, #1 +100035f4: f04f 0c00 mov.w ip, #0 +100035f8: d018 beq.n 1000362c +100035fa: 4646 mov r6, r8 +100035fc: 2401 movs r4, #1 +100035fe: f816 2f01 ldrb.w r2, [r6, #1]! +10003602: 4621 mov r1, r4 +10003604: 2a0a cmp r2, #10 +10003606: f104 0401 add.w r4, r4, #1 +1000360a: d022 beq.n 10003652 +1000360c: 42a5 cmp r5, r4 +1000360e: d1f6 bne.n 100035fe +10003610: 4565 cmp r5, ip +10003612: dc0b bgt.n 1000362c +10003614: eb08 0305 add.w r3, r8, r5 +10003618: f813 3c01 ldrb.w r3, [r3, #-1] +1000361c: f1a3 030d sub.w r3, r3, #13 +10003620: fab3 f383 clz r3, r3 +10003624: 095b lsrs r3, r3, #5 +10003626: 753b strb r3, [r7, #20] +10003628: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000362c: 683b ldr r3, [r7, #0] +1000362e: eba5 010c sub.w r1, r5, ip +10003632: eb08 000c add.w r0, r8, ip +10003636: 4798 blx r3 +10003638: e7ec b.n 10003614 +1000363a: 7d03 ldrb r3, [r0, #20] +1000363c: 2b00 cmp r3, #0 +1000363e: d1d8 bne.n 100035f2 +10003640: 6803 ldr r3, [r0, #0] +10003642: 2102 movs r1, #2 +10003644: 480f ldr r0, [pc, #60] @ (10003684 ) +10003646: 4798 blx r3 +10003648: 2d01 cmp r5, #1 +1000364a: d0e3 beq.n 10003614 +1000364c: f04f 0c01 mov.w ip, #1 +10003650: e7d3 b.n 100035fa +10003652: f816 3c01 ldrb.w r3, [r6, #-1] +10003656: 2b0d cmp r3, #13 +10003658: d0d8 beq.n 1000360c +1000365a: 458c cmp ip, r1 +1000365c: eb08 000c add.w r0, r8, ip +10003660: eba1 010c sub.w r1, r1, ip +10003664: da01 bge.n 1000366a +10003666: 683b ldr r3, [r7, #0] +10003668: 4798 blx r3 +1000366a: 2102 movs r1, #2 +1000366c: 4805 ldr r0, [pc, #20] @ (10003684 ) +1000366e: 683b ldr r3, [r7, #0] +10003670: 4798 blx r3 +10003672: 46a4 mov ip, r4 +10003674: e7ca b.n 1000360c +10003676: 4629 mov r1, r5 +10003678: 4640 mov r0, r8 +1000367a: 683b ldr r3, [r7, #0] +1000367c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10003680: 4718 bx r3 +10003682: bf00 nop +10003684: 100040a0 .word 0x100040a0 + +10003688 : +10003688: 680b ldr r3, [r1, #0] +1000368a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000368e: 2b80 cmp r3, #128 @ 0x80 +10003690: 460d mov r5, r1 +10003692: 4606 mov r6, r0 +10003694: d005 beq.n 100036a2 +10003696: 1c5a adds r2, r3, #1 +10003698: 442b add r3, r5 +1000369a: 602a str r2, [r5, #0] +1000369c: 711e strb r6, [r3, #4] +1000369e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100036a2: 4b0f ldr r3, [pc, #60] @ (100036e0 ) +100036a4: 681c ldr r4, [r3, #0] +100036a6: b1a4 cbz r4, 100036d2 +100036a8: 4f0e ldr r7, [pc, #56] @ (100036e4 ) +100036aa: f101 0804 add.w r8, r1, #4 +100036ae: e001 b.n 100036b4 +100036b0: 6924 ldr r4, [r4, #16] +100036b2: b174 cbz r4, 100036d2 +100036b4: 6823 ldr r3, [r4, #0] +100036b6: 2b00 cmp r3, #0 +100036b8: d0fa beq.n 100036b0 +100036ba: 683b ldr r3, [r7, #0] +100036bc: b10b cbz r3, 100036c2 +100036be: 42a3 cmp r3, r4 +100036c0: d1f6 bne.n 100036b0 +100036c2: 4620 mov r0, r4 +100036c4: 4641 mov r1, r8 +100036c6: 682a ldr r2, [r5, #0] +100036c8: f7ff ff86 bl 100035d8 +100036cc: 6924 ldr r4, [r4, #16] +100036ce: 2c00 cmp r4, #0 +100036d0: d1f0 bne.n 100036b4 +100036d2: 2300 movs r3, #0 +100036d4: 2201 movs r2, #1 +100036d6: 442b add r3, r5 +100036d8: 602a str r2, [r5, #0] +100036da: 711e strb r6, [r3, #4] +100036dc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100036e0: 2000081c .word 0x2000081c +100036e4: 20000820 .word 0x20000820 + +100036e8 : +100036e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100036ec: b082 sub sp, #8 +100036ee: 460d mov r5, r1 +100036f0: 4691 mov r9, r2 +100036f2: 461c mov r4, r3 +100036f4: 4606 mov r6, r0 +100036f6: f7fd ff95 bl 10001624 +100036fa: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +100036fe: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10003702: 4a2e ldr r2, [pc, #184] @ (100037bc ) +10003704: 1882 adds r2, r0, r2 +10003706: f141 0300 adc.w r3, r1, #0 +1000370a: 4594 cmp ip, r2 +1000370c: eb77 0103 sbcs.w r1, r7, r3 +10003710: bf3c itt cc +10003712: 4662 movcc r2, ip +10003714: 463b movcc r3, r7 +10003716: 482a ldr r0, [pc, #168] @ (100037c0 ) +10003718: f000 fbbe bl 10003e98 <__mutex_try_enter_block_until_veneer> +1000371c: 1c6b adds r3, r5, #1 +1000371e: 4680 mov r8, r0 +10003720: d040 beq.n 100037a4 +10003722: b30c cbz r4, 10003768 +10003724: 4f27 ldr r7, [pc, #156] @ (100037c4 ) +10003726: 4b28 ldr r3, [pc, #160] @ (100037c8 ) +10003728: 681c ldr r4, [r3, #0] +1000372a: b1b4 cbz r4, 1000375a +1000372c: f1b9 0f00 cmp.w r9, #0 +10003730: d11c bne.n 1000376c +10003732: f8df 909c ldr.w r9, [pc, #156] @ 100037d0 +10003736: e001 b.n 1000373c +10003738: 6924 ldr r4, [r4, #16] +1000373a: b174 cbz r4, 1000375a +1000373c: 6823 ldr r3, [r4, #0] +1000373e: 2b00 cmp r3, #0 +10003740: d0fa beq.n 10003738 +10003742: f8d9 3000 ldr.w r3, [r9] +10003746: b10b cbz r3, 1000374c +10003748: 429c cmp r4, r3 +1000374a: d1f5 bne.n 10003738 +1000374c: 4620 mov r0, r4 +1000374e: 462a mov r2, r5 +10003750: 4631 mov r1, r6 +10003752: 47b8 blx r7 +10003754: 6924 ldr r4, [r4, #16] +10003756: 2c00 cmp r4, #0 +10003758: d1f0 bne.n 1000373c +1000375a: f1b8 0f00 cmp.w r8, #0 +1000375e: d126 bne.n 100037ae +10003760: 4628 mov r0, r5 +10003762: b002 add sp, #8 +10003764: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003768: 4f18 ldr r7, [pc, #96] @ (100037cc ) +1000376a: e7dc b.n 10003726 +1000376c: f04f 0a0a mov.w sl, #10 +10003770: f8df 905c ldr.w r9, [pc, #92] @ 100037d0 +10003774: e002 b.n 1000377c +10003776: 6924 ldr r4, [r4, #16] +10003778: 2c00 cmp r4, #0 +1000377a: d0ee beq.n 1000375a +1000377c: 6823 ldr r3, [r4, #0] +1000377e: 2b00 cmp r3, #0 +10003780: d0f9 beq.n 10003776 +10003782: f8d9 3000 ldr.w r3, [r9] +10003786: b10b cbz r3, 1000378c +10003788: 42a3 cmp r3, r4 +1000378a: d1f4 bne.n 10003776 +1000378c: 462a mov r2, r5 +1000378e: 4631 mov r1, r6 +10003790: 4620 mov r0, r4 +10003792: 47b8 blx r7 +10003794: 2201 movs r2, #1 +10003796: 4620 mov r0, r4 +10003798: f10d 0107 add.w r1, sp, #7 +1000379c: f88d a007 strb.w sl, [sp, #7] +100037a0: 47b8 blx r7 +100037a2: e7e8 b.n 10003776 +100037a4: 4630 mov r0, r6 +100037a6: f000 fb3d bl 10003e24 +100037aa: 4605 mov r5, r0 +100037ac: e7b9 b.n 10003722 +100037ae: 4804 ldr r0, [pc, #16] @ (100037c0 ) +100037b0: f000 fb6e bl 10003e90 <__mutex_exit_veneer> +100037b4: 4628 mov r0, r5 +100037b6: b002 add sp, #8 +100037b8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100037bc: 000f4240 .word 0x000f4240 +100037c0: 2000063c .word 0x2000063c +100037c4: 100035d9 .word 0x100035d9 +100037c8: 2000081c .word 0x2000081c +100037cc: 100035d1 .word 0x100035d1 +100037d0: 20000820 .word 0x20000820 + +100037d4 : +100037d4: 4a08 ldr r2, [pc, #32] @ (100037f8 ) +100037d6: 6813 ldr r3, [r2, #0] +100037d8: b923 cbnz r3, 100037e4 +100037da: e00a b.n 100037f2 +100037dc: f103 0210 add.w r2, r3, #16 +100037e0: 691b ldr r3, [r3, #16] +100037e2: b133 cbz r3, 100037f2 +100037e4: 4283 cmp r3, r0 +100037e6: d1f9 bne.n 100037dc +100037e8: b929 cbnz r1, 100037f6 +100037ea: 6918 ldr r0, [r3, #16] +100037ec: 6010 str r0, [r2, #0] +100037ee: 6119 str r1, [r3, #16] +100037f0: 4770 bx lr +100037f2: b101 cbz r1, 100037f6 +100037f4: 6010 str r0, [r2, #0] +100037f6: 4770 bx lr +100037f8: 2000081c .word 0x2000081c + +100037fc : +100037fc: b508 push {r3, lr} +100037fe: f000 f9a3 bl 10003b48 +10003802: 2001 movs r0, #1 +10003804: bd08 pop {r3, pc} +10003806: bf00 nop + +10003808 <__wrap_putchar>: +10003808: b5f0 push {r4, r5, r6, r7, lr} +1000380a: b083 sub sp, #12 +1000380c: 4606 mov r6, r0 +1000380e: f88d 0007 strb.w r0, [sp, #7] +10003812: f7fd ff07 bl 10001624 +10003816: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000381a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000381e: 4a17 ldr r2, [pc, #92] @ (1000387c <__wrap_putchar+0x74>) +10003820: 1882 adds r2, r0, r2 +10003822: f141 0300 adc.w r3, r1, #0 +10003826: 4295 cmp r5, r2 +10003828: eb74 0103 sbcs.w r1, r4, r3 +1000382c: bf3c itt cc +1000382e: 4623 movcc r3, r4 +10003830: 462a movcc r2, r5 +10003832: 4813 ldr r0, [pc, #76] @ (10003880 <__wrap_putchar+0x78>) +10003834: f000 fb30 bl 10003e98 <__mutex_try_enter_block_until_veneer> +10003838: 4b12 ldr r3, [pc, #72] @ (10003884 <__wrap_putchar+0x7c>) +1000383a: 4607 mov r7, r0 +1000383c: 681c ldr r4, [r3, #0] +1000383e: b19c cbz r4, 10003868 <__wrap_putchar+0x60> +10003840: 4d11 ldr r5, [pc, #68] @ (10003888 <__wrap_putchar+0x80>) +10003842: e001 b.n 10003848 <__wrap_putchar+0x40> +10003844: 6924 ldr r4, [r4, #16] +10003846: b17c cbz r4, 10003868 <__wrap_putchar+0x60> +10003848: 6823 ldr r3, [r4, #0] +1000384a: 2b00 cmp r3, #0 +1000384c: d0fa beq.n 10003844 <__wrap_putchar+0x3c> +1000384e: 682b ldr r3, [r5, #0] +10003850: b10b cbz r3, 10003856 <__wrap_putchar+0x4e> +10003852: 429c cmp r4, r3 +10003854: d1f6 bne.n 10003844 <__wrap_putchar+0x3c> +10003856: 4620 mov r0, r4 +10003858: 2201 movs r2, #1 +1000385a: f10d 0107 add.w r1, sp, #7 +1000385e: f7ff febb bl 100035d8 +10003862: 6924 ldr r4, [r4, #16] +10003864: 2c00 cmp r4, #0 +10003866: d1ef bne.n 10003848 <__wrap_putchar+0x40> +10003868: b917 cbnz r7, 10003870 <__wrap_putchar+0x68> +1000386a: 4630 mov r0, r6 +1000386c: b003 add sp, #12 +1000386e: bdf0 pop {r4, r5, r6, r7, pc} +10003870: 4803 ldr r0, [pc, #12] @ (10003880 <__wrap_putchar+0x78>) +10003872: f000 fb0d bl 10003e90 <__mutex_exit_veneer> +10003876: 4630 mov r0, r6 +10003878: b003 add sp, #12 +1000387a: bdf0 pop {r4, r5, r6, r7, pc} +1000387c: 000f4240 .word 0x000f4240 +10003880: 2000063c .word 0x2000063c +10003884: 2000081c .word 0x2000081c +10003888: 20000820 .word 0x20000820 + +1000388c <__wrap_puts>: +1000388c: b538 push {r3, r4, r5, lr} +1000388e: 4604 mov r4, r0 +10003890: f000 fac8 bl 10003e24 +10003894: 2301 movs r3, #1 +10003896: 4605 mov r5, r0 +10003898: 461a mov r2, r3 +1000389a: 4620 mov r0, r4 +1000389c: 4629 mov r1, r5 +1000389e: f7ff ff23 bl 100036e8 +100038a2: 4b08 ldr r3, [pc, #32] @ (100038c4 <__wrap_puts+0x38>) +100038a4: 681c ldr r4, [r3, #0] +100038a6: b12c cbz r4, 100038b4 <__wrap_puts+0x28> +100038a8: 6863 ldr r3, [r4, #4] +100038aa: b12b cbz r3, 100038b8 <__wrap_puts+0x2c> +100038ac: 4798 blx r3 +100038ae: 6924 ldr r4, [r4, #16] +100038b0: 2c00 cmp r4, #0 +100038b2: d1f9 bne.n 100038a8 <__wrap_puts+0x1c> +100038b4: 4628 mov r0, r5 +100038b6: bd38 pop {r3, r4, r5, pc} +100038b8: 6924 ldr r4, [r4, #16] +100038ba: 2c00 cmp r4, #0 +100038bc: d1f4 bne.n 100038a8 <__wrap_puts+0x1c> +100038be: 4628 mov r0, r5 +100038c0: bd38 pop {r3, r4, r5, pc} +100038c2: bf00 nop +100038c4: 2000081c .word 0x2000081c + +100038c8 <__wrap_vprintf>: +100038c8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100038cc: b0a2 sub sp, #136 @ 0x88 +100038ce: 4604 mov r4, r0 +100038d0: 460d mov r5, r1 +100038d2: f7fd fea7 bl 10001624 +100038d6: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +100038da: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +100038de: 4a26 ldr r2, [pc, #152] @ (10003978 <__wrap_vprintf+0xb0>) +100038e0: f8df 80a4 ldr.w r8, [pc, #164] @ 10003988 <__wrap_vprintf+0xc0> +100038e4: 1882 adds r2, r0, r2 +100038e6: f141 0300 adc.w r3, r1, #0 +100038ea: 4297 cmp r7, r2 +100038ec: eb76 0103 sbcs.w r1, r6, r3 +100038f0: bf3c itt cc +100038f2: 463a movcc r2, r7 +100038f4: 4633 movcc r3, r6 +100038f6: 4821 ldr r0, [pc, #132] @ (1000397c <__wrap_vprintf+0xb4>) +100038f8: f000 face bl 10003e98 <__mutex_try_enter_block_until_veneer> +100038fc: 2700 movs r7, #0 +100038fe: 462b mov r3, r5 +10003900: 4622 mov r2, r4 +10003902: 4606 mov r6, r0 +10003904: a901 add r1, sp, #4 +10003906: 481e ldr r0, [pc, #120] @ (10003980 <__wrap_vprintf+0xb8>) +10003908: 9701 str r7, [sp, #4] +1000390a: f7ff fe1d bl 10003548 +1000390e: 9b01 ldr r3, [sp, #4] +10003910: 4605 mov r5, r0 +10003912: f8d8 4000 ldr.w r4, [r8] +10003916: b1c3 cbz r3, 1000394a <__wrap_vprintf+0x82> +10003918: 2c00 cmp r4, #0 +1000391a: d02b beq.n 10003974 <__wrap_vprintf+0xac> +1000391c: 4f19 ldr r7, [pc, #100] @ (10003984 <__wrap_vprintf+0xbc>) +1000391e: e001 b.n 10003924 <__wrap_vprintf+0x5c> +10003920: 6924 ldr r4, [r4, #16] +10003922: b174 cbz r4, 10003942 <__wrap_vprintf+0x7a> +10003924: 6823 ldr r3, [r4, #0] +10003926: 2b00 cmp r3, #0 +10003928: d0fa beq.n 10003920 <__wrap_vprintf+0x58> +1000392a: 683b ldr r3, [r7, #0] +1000392c: b10b cbz r3, 10003932 <__wrap_vprintf+0x6a> +1000392e: 42a3 cmp r3, r4 +10003930: d1f6 bne.n 10003920 <__wrap_vprintf+0x58> +10003932: 4620 mov r0, r4 +10003934: 9a01 ldr r2, [sp, #4] +10003936: a902 add r1, sp, #8 +10003938: f7ff fe4e bl 100035d8 +1000393c: 6924 ldr r4, [r4, #16] +1000393e: 2c00 cmp r4, #0 +10003940: d1f0 bne.n 10003924 <__wrap_vprintf+0x5c> +10003942: 2300 movs r3, #0 +10003944: f8d8 4000 ldr.w r4, [r8] +10003948: 9301 str r3, [sp, #4] +1000394a: b12c cbz r4, 10003958 <__wrap_vprintf+0x90> +1000394c: 6863 ldr r3, [r4, #4] +1000394e: b143 cbz r3, 10003962 <__wrap_vprintf+0x9a> +10003950: 4798 blx r3 +10003952: 6924 ldr r4, [r4, #16] +10003954: 2c00 cmp r4, #0 +10003956: d1f9 bne.n 1000394c <__wrap_vprintf+0x84> +10003958: b92e cbnz r6, 10003966 <__wrap_vprintf+0x9e> +1000395a: 4628 mov r0, r5 +1000395c: b022 add sp, #136 @ 0x88 +1000395e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003962: 6924 ldr r4, [r4, #16] +10003964: e7f1 b.n 1000394a <__wrap_vprintf+0x82> +10003966: 4805 ldr r0, [pc, #20] @ (1000397c <__wrap_vprintf+0xb4>) +10003968: f000 fa92 bl 10003e90 <__mutex_exit_veneer> +1000396c: 4628 mov r0, r5 +1000396e: b022 add sp, #136 @ 0x88 +10003970: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003974: 9401 str r4, [sp, #4] +10003976: e7ef b.n 10003958 <__wrap_vprintf+0x90> +10003978: 000f4240 .word 0x000f4240 +1000397c: 2000063c .word 0x2000063c +10003980: 10003689 .word 0x10003689 +10003984: 20000820 .word 0x20000820 +10003988: 2000081c .word 0x2000081c + +1000398c <__wrap_printf>: +1000398c: b40f push {r0, r1, r2, r3} +1000398e: b500 push {lr} +10003990: b083 sub sp, #12 +10003992: a904 add r1, sp, #16 +10003994: f851 0b04 ldr.w r0, [r1], #4 +10003998: 9101 str r1, [sp, #4] +1000399a: f7ff ff95 bl 100038c8 <__wrap_vprintf> +1000399e: b003 add sp, #12 +100039a0: f85d eb04 ldr.w lr, [sp], #4 +100039a4: b004 add sp, #16 +100039a6: 4770 bx lr + +100039a8 : +100039a8: f1b1 0c00 subs.w ip, r1, #0 +100039ac: dd1d ble.n 100039ea +100039ae: 4a0f ldr r2, [pc, #60] @ (100039ec ) +100039b0: 4b0f ldr r3, [pc, #60] @ (100039f0 ) +100039b2: 6812 ldr r2, [r2, #0] +100039b4: b530 push {r4, r5, lr} +100039b6: 1ad3 subs r3, r2, r3 +100039b8: fab3 f383 clz r3, r3 +100039bc: 240d movs r4, #13 +100039be: 4d0d ldr r5, [pc, #52] @ (100039f4 ) +100039c0: 095b lsrs r3, r3, #5 +100039c2: 1e41 subs r1, r0, #1 +100039c4: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +100039c8: 448c add ip, r1 +100039ca: f811 0f01 ldrb.w r0, [r1, #1]! +100039ce: 4586 cmp lr, r0 +100039d0: d006 beq.n 100039e0 +100039d2: 6993 ldr r3, [r2, #24] +100039d4: 069b lsls r3, r3, #26 +100039d6: d4fc bmi.n 100039d2 +100039d8: 4561 cmp r1, ip +100039da: 6010 str r0, [r2, #0] +100039dc: d1f5 bne.n 100039ca +100039de: bd30 pop {r4, r5, pc} +100039e0: 6993 ldr r3, [r2, #24] +100039e2: 069d lsls r5, r3, #26 +100039e4: d4fc bmi.n 100039e0 +100039e6: 6014 str r4, [r2, #0] +100039e8: e7f3 b.n 100039d2 +100039ea: 4770 bx lr +100039ec: 2000086c .word 0x2000086c +100039f0: 40078000 .word 0x40078000 +100039f4: 20000868 .word 0x20000868 + +100039f8 : +100039f8: 4b22 ldr r3, [pc, #136] @ (10003a84 ) +100039fa: f1b1 0c00 subs.w ip, r1, #0 +100039fe: b410 push {r4} +10003a00: 681c ldr r4, [r3, #0] +10003a02: dd2e ble.n 10003a62 +10003a04: 4603 mov r3, r0 +10003a06: 2000 movs r0, #0 +10003a08: 4a1f ldr r2, [pc, #124] @ (10003a88 ) +10003a0a: 1e59 subs r1, r3, #1 +10003a0c: 6812 ldr r2, [r2, #0] +10003a0e: 6993 ldr r3, [r2, #24] +10003a10: 06db lsls r3, r3, #27 +10003a12: d417 bmi.n 10003a44 +10003a14: 3001 adds r0, #1 +10003a16: 6993 ldr r3, [r2, #24] +10003a18: 06db lsls r3, r3, #27 +10003a1a: d4fc bmi.n 10003a16 +10003a1c: 6813 ldr r3, [r2, #0] +10003a1e: 4584 cmp ip, r0 +10003a20: f801 3f01 strb.w r3, [r1, #1]! +10003a24: d1f3 bne.n 10003a0e +10003a26: b14c cbz r4, 10003a3c +10003a28: 2150 movs r1, #80 @ 0x50 +10003a2a: 4613 mov r3, r2 +10003a2c: 6391 str r1, [r2, #56] @ 0x38 +10003a2e: f853 2f34 ldr.w r2, [r3, #52]! +10003a32: f002 0238 and.w r2, r2, #56 @ 0x38 +10003a36: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003a3a: 601a str r2, [r3, #0] +10003a3c: 4660 mov r0, ip +10003a3e: f85d 4b04 ldr.w r4, [sp], #4 +10003a42: 4770 bx lr +10003a44: b14c cbz r4, 10003a5a +10003a46: 2150 movs r1, #80 @ 0x50 +10003a48: 4613 mov r3, r2 +10003a4a: 6391 str r1, [r2, #56] @ 0x38 +10003a4c: f853 2f34 ldr.w r2, [r3, #52]! +10003a50: f002 0238 and.w r2, r2, #56 @ 0x38 +10003a54: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003a58: 601a str r2, [r3, #0] +10003a5a: b178 cbz r0, 10003a7c +10003a5c: f85d 4b04 ldr.w r4, [sp], #4 +10003a60: 4770 bx lr +10003a62: b15c cbz r4, 10003a7c +10003a64: 4b08 ldr r3, [pc, #32] @ (10003a88 ) +10003a66: 2150 movs r1, #80 @ 0x50 +10003a68: 681a ldr r2, [r3, #0] +10003a6a: 4613 mov r3, r2 +10003a6c: 6391 str r1, [r2, #56] @ 0x38 +10003a6e: f853 2f34 ldr.w r2, [r3, #52]! +10003a72: f002 0238 and.w r2, r2, #56 @ 0x38 +10003a76: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003a7a: 601a str r2, [r3, #0] +10003a7c: f06f 0002 mvn.w r0, #2 +10003a80: e7dd b.n 10003a3e +10003a82: bf00 nop +10003a84: 200007e8 .word 0x200007e8 +10003a88: 2000086c .word 0x2000086c + +10003a8c : +10003a8c: 4b05 ldr r3, [pc, #20] @ (10003aa4 ) +10003a8e: 681b ldr r3, [r3, #0] +10003a90: b133 cbz r3, 10003aa0 +10003a92: 2100 movs r1, #0 +10003a94: 4a04 ldr r2, [pc, #16] @ (10003aa8 ) +10003a96: 4805 ldr r0, [pc, #20] @ (10003aac ) +10003a98: 6812 ldr r2, [r2, #0] +10003a9a: 6800 ldr r0, [r0, #0] +10003a9c: 6391 str r1, [r2, #56] @ 0x38 +10003a9e: 4718 bx r3 +10003aa0: 4770 bx lr +10003aa2: bf00 nop +10003aa4: 200007e8 .word 0x200007e8 +10003aa8: 2000086c .word 0x2000086c +10003aac: 200007ec .word 0x200007ec + +10003ab0 : +10003ab0: 4b02 ldr r3, [pc, #8] @ (10003abc ) +10003ab2: 681a ldr r2, [r3, #0] +10003ab4: 6993 ldr r3, [r2, #24] +10003ab6: 071b lsls r3, r3, #28 +10003ab8: d4fc bmi.n 10003ab4 +10003aba: 4770 bx lr +10003abc: 2000086c .word 0x2000086c + +10003ac0 : +10003ac0: b5f8 push {r3, r4, r5, r6, r7, lr} +10003ac2: 4f1c ldr r7, [pc, #112] @ (10003b34 ) +10003ac4: 4d1c ldr r5, [pc, #112] @ (10003b38 ) +10003ac6: 683a ldr r2, [r7, #0] +10003ac8: 4e1c ldr r6, [pc, #112] @ (10003b3c ) +10003aca: 42aa cmp r2, r5 +10003acc: bf14 ite ne +10003ace: 2521 movne r5, #33 @ 0x21 +10003ad0: 2522 moveq r5, #34 @ 0x22 +10003ad2: 4604 mov r4, r0 +10003ad4: f8d6 c000 ldr.w ip, [r6] +10003ad8: b118 cbz r0, 10003ae2 +10003ada: f1bc 0f00 cmp.w ip, #0 +10003ade: d010 beq.n 10003b02 +10003ae0: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003ae2: f1bc 0f00 cmp.w ip, #0 +10003ae6: d0fb beq.n 10003ae0 +10003ae8: 4601 mov r1, r0 +10003aea: 6390 str r0, [r2, #56] @ 0x38 +10003aec: 4628 mov r0, r5 +10003aee: f7fc ffb5 bl 10000a5c +10003af2: 4628 mov r0, r5 +10003af4: 4912 ldr r1, [pc, #72] @ (10003b40 ) +10003af6: f7fc fff7 bl 10000ae8 +10003afa: 4b12 ldr r3, [pc, #72] @ (10003b44 ) +10003afc: 6034 str r4, [r6, #0] +10003afe: 601c str r4, [r3, #0] +10003b00: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003b02: 460b mov r3, r1 +10003b04: 4a0f ldr r2, [pc, #60] @ (10003b44 ) +10003b06: 490e ldr r1, [pc, #56] @ (10003b40 ) +10003b08: 6030 str r0, [r6, #0] +10003b0a: 4628 mov r0, r5 +10003b0c: 6013 str r3, [r2, #0] +10003b0e: f7fc ffbb bl 10000a88 +10003b12: 2101 movs r1, #1 +10003b14: 4628 mov r0, r5 +10003b16: f7fc ffa1 bl 10000a5c +10003b1a: 683a ldr r2, [r7, #0] +10003b1c: 2150 movs r1, #80 @ 0x50 +10003b1e: 4613 mov r3, r2 +10003b20: 6391 str r1, [r2, #56] @ 0x38 +10003b22: f853 2f34 ldr.w r2, [r3, #52]! +10003b26: f002 0238 and.w r2, r2, #56 @ 0x38 +10003b2a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003b2e: 601a str r2, [r3, #0] +10003b30: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003b32: bf00 nop +10003b34: 2000086c .word 0x2000086c +10003b38: 40078000 .word 0x40078000 +10003b3c: 200007e8 .word 0x200007e8 +10003b40: 10003a8d .word 0x10003a8d +10003b44: 200007ec .word 0x200007ec + +10003b48 : +10003b48: b510 push {r4, lr} +10003b4a: 490e ldr r1, [pc, #56] @ (10003b84 ) +10003b4c: 4c0e ldr r4, [pc, #56] @ (10003b88 ) +10003b4e: 480f ldr r0, [pc, #60] @ (10003b8c ) +10003b50: 4a0f ldr r2, [pc, #60] @ (10003b90 ) +10003b52: 4b10 ldr r3, [pc, #64] @ (10003b94 ) +10003b54: 7800 ldrb r0, [r0, #0] +10003b56: 6021 str r1, [r4, #0] +10003b58: 2000 movs r0, #0 +10003b5a: 2102 movs r1, #2 +10003b5c: 7812 ldrb r2, [r2, #0] +10003b5e: 781b ldrb r3, [r3, #0] +10003b60: f7fc fec6 bl 100008f0 +10003b64: 2102 movs r1, #2 +10003b66: 2001 movs r0, #1 +10003b68: f7fc fec2 bl 100008f0 +10003b6c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003b70: 6820 ldr r0, [r4, #0] +10003b72: f7fd fda1 bl 100016b8 +10003b76: e8bd 4010 ldmia.w sp!, {r4, lr} +10003b7a: 2101 movs r1, #1 +10003b7c: 4806 ldr r0, [pc, #24] @ (10003b98 ) +10003b7e: f7ff be29 b.w 100037d4 +10003b82: bf00 nop +10003b84: 40070000 .word 0x40070000 +10003b88: 2000086c .word 0x2000086c +10003b8c: 100040f0 .word 0x100040f0 +10003b90: 100040ec .word 0x100040ec +10003b94: 100040e8 .word 0x100040e8 +10003b98: 20000614 .word 0x20000614 + +10003b9c : +10003b9c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003ba0: 2700 movs r7, #0 +10003ba2: 2401 movs r4, #1 +10003ba4: 4694 mov ip, r2 +10003ba6: 6802 ldr r2, [r0, #0] +10003ba8: 4605 mov r5, r0 +10003baa: 66d7 str r7, [r2, #108] @ 0x6c +10003bac: 6051 str r1, [r2, #4] +10003bae: 66d4 str r4, [r2, #108] @ 0x6c +10003bb0: 1e1c subs r4, r3, #0 +10003bb2: 4638 mov r0, r7 +10003bb4: f89d 6018 ldrb.w r6, [sp, #24] +10003bb8: dd1e ble.n 10003bf8 +10003bba: 7929 ldrb r1, [r5, #4] +10003bbc: f086 0701 eor.w r7, r6, #1 +10003bc0: 0289 lsls r1, r1, #10 +10003bc2: 027f lsls r7, r7, #9 +10003bc4: f104 3eff add.w lr, r4, #4294967295 @ 0xffffffff +10003bc8: 4570 cmp r0, lr +10003bca: bf0c ite eq +10003bcc: 46b8 moveq r8, r7 +10003bce: f04f 0800 movne.w r8, #0 +10003bd2: f81c 3b01 ldrb.w r3, [ip], #1 +10003bd6: 430b orrs r3, r1 +10003bd8: ea43 0308 orr.w r3, r3, r8 +10003bdc: 6113 str r3, [r2, #16] +10003bde: 6b53 ldr r3, [r2, #52] @ 0x34 +10003be0: 06d9 lsls r1, r3, #27 +10003be2: d5fc bpl.n 10003bde +10003be4: f8d2 1080 ldr.w r1, [r2, #128] @ 0x80 +10003be8: b949 cbnz r1, 10003bfe +10003bea: 4570 cmp r0, lr +10003bec: d01c beq.n 10003c28 +10003bee: 3001 adds r0, #1 +10003bf0: 4284 cmp r4, r0 +10003bf2: f04f 0100 mov.w r1, #0 +10003bf6: d1e7 bne.n 10003bc8 +10003bf8: 712e strb r6, [r5, #4] +10003bfa: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003bfe: f04f 0801 mov.w r8, #1 +10003c02: 6d53 ldr r3, [r2, #84] @ 0x54 +10003c04: 6b53 ldr r3, [r2, #52] @ 0x34 +10003c06: 059b lsls r3, r3, #22 +10003c08: d5fc bpl.n 10003c04 +10003c0a: 6e13 ldr r3, [r2, #96] @ 0x60 +10003c0c: f1b8 0f00 cmp.w r8, #0 +10003c10: d0ed beq.n 10003bee +10003c12: b169 cbz r1, 10003c30 +10003c14: 07cb lsls r3, r1, #31 +10003c16: d40b bmi.n 10003c30 +10003c18: f011 0f08 tst.w r1, #8 +10003c1c: bf08 it eq +10003c1e: f04f 30ff moveq.w r0, #4294967295 @ 0xffffffff +10003c22: 712e strb r6, [r5, #4] +10003c24: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003c28: 2e00 cmp r6, #0 +10003c2a: d1e0 bne.n 10003bee +10003c2c: 46b0 mov r8, r6 +10003c2e: e7e9 b.n 10003c04 +10003c30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10003c34: e7e0 b.n 10003bf8 +10003c36: bf00 nop + +10003c38 : +10003c38: b5f8 push {r3, r4, r5, r6, r7, lr} +10003c3a: 4604 mov r4, r0 +10003c3c: 2005 movs r0, #5 +10003c3e: 460f mov r7, r1 +10003c40: f7fd fe24 bl 1000188c +10003c44: eb00 0c57 add.w ip, r0, r7, lsr #1 +10003c48: fbbc fcf7 udiv ip, ip, r7 +10003c4c: 4d20 ldr r5, [pc, #128] @ (10003cd0 ) +10003c4e: eb0c 024c add.w r2, ip, ip, lsl #1 +10003c52: fba5 6502 umull r6, r5, r5, r2 +10003c56: 491f ldr r1, [pc, #124] @ (10003cd4 ) +10003c58: 08ae lsrs r6, r5, #2 +10003c5a: 428f cmp r7, r1 +10003c5c: eb00 0340 add.w r3, r0, r0, lsl #1 +10003c60: ebac 0595 sub.w r5, ip, r5, lsr #2 +10003c64: d82e bhi.n 10003cc4 +10003c66: f101 41d6 add.w r1, r1, #1795162112 @ 0x6b000000 +10003c6a: f501 01a1 add.w r1, r1, #5275648 @ 0x508000 +10003c6e: f601 012c addw r1, r1, #2092 @ 0x82c +10003c72: fba1 1303 umull r1, r3, r1, r3 +10003c76: 0d9b lsrs r3, r3, #22 +10003c78: 3301 adds r3, #1 +10003c7a: 2100 movs r1, #0 +10003c7c: 2a4f cmp r2, #79 @ 0x4f +10003c7e: bf98 it ls +10003c80: 2201 movls r2, #1 +10003c82: 6824 ldr r4, [r4, #0] +10003c84: fbb0 f0fc udiv r0, r0, ip +10003c88: 66e1 str r1, [r4, #108] @ 0x6c +10003c8a: 6821 ldr r1, [r4, #0] +10003c8c: f504 5780 add.w r7, r4, #4096 @ 0x1000 +10003c90: f081 0104 eor.w r1, r1, #4 +10003c94: f001 0106 and.w r1, r1, #6 +10003c98: 6039 str r1, [r7, #0] +10003c9a: bf88 it hi +10003c9c: 490c ldrhi r1, [pc, #48] @ (10003cd0 ) +10003c9e: 61e5 str r5, [r4, #28] +10003ca0: bf84 itt hi +10003ca2: fba1 1202 umullhi r1, r2, r1, r2 +10003ca6: 0992 lsrhi r2, r2, #6 +10003ca8: 6226 str r6, [r4, #32] +10003caa: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0 +10003cae: 4622 mov r2, r4 +10003cb0: 2101 movs r1, #1 +10003cb2: f852 5f7c ldr.w r5, [r2, #124]! +10003cb6: 406b eors r3, r5 +10003cb8: b29b uxth r3, r3 +10003cba: f502 5280 add.w r2, r2, #4096 @ 0x1000 +10003cbe: 6013 str r3, [r2, #0] +10003cc0: 66e1 str r1, [r4, #108] @ 0x6c +10003cc2: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003cc4: 4904 ldr r1, [pc, #16] @ (10003cd8 ) +10003cc6: fba1 1303 umull r1, r3, r1, r3 +10003cca: 0ddb lsrs r3, r3, #23 +10003ccc: 3301 adds r3, #1 +10003cce: e7d4 b.n 10003c7a +10003cd0: cccccccd .word 0xcccccccd +10003cd4: 000f423f .word 0x000f423f +10003cd8: 55e63b89 .word 0x55e63b89 + +10003cdc : +10003cdc: 4a0e ldr r2, [pc, #56] @ (10003d18 ) +10003cde: b430 push {r4, r5} +10003ce0: 4290 cmp r0, r2 +10003ce2: bf14 ite ne +10003ce4: 2220 movne r2, #32 +10003ce6: 2210 moveq r2, #16 +10003ce8: 4d0c ldr r5, [pc, #48] @ (10003d1c ) +10003cea: 4b0d ldr r3, [pc, #52] @ (10003d20 ) +10003cec: 4c0d ldr r4, [pc, #52] @ (10003d24 ) +10003cee: 602a str r2, [r5, #0] +10003cf0: 601a str r2, [r3, #0] +10003cf2: 68a3 ldr r3, [r4, #8] +10003cf4: ea32 0303 bics.w r3, r2, r3 +10003cf8: d1fb bne.n 10003cf2 +10003cfa: f240 1565 movw r5, #357 @ 0x165 +10003cfe: 2403 movs r4, #3 +10003d00: 6802 ldr r2, [r0, #0] +10003d02: 7103 strb r3, [r0, #4] +10003d04: 66d3 str r3, [r2, #108] @ 0x6c +10003d06: 6015 str r5, [r2, #0] +10003d08: 63d3 str r3, [r2, #60] @ 0x3c +10003d0a: 6393 str r3, [r2, #56] @ 0x38 +10003d0c: f8c2 4088 str.w r4, [r2, #136] @ 0x88 +10003d10: bc30 pop {r4, r5} +10003d12: f7ff bf91 b.w 10003c38 +10003d16: bf00 nop +10003d18: 20000634 .word 0x20000634 +10003d1c: 40022000 .word 0x40022000 +10003d20: 40023000 .word 0x40023000 +10003d24: 40020000 .word 0x40020000 + +10003d28 : +10003d28: b410 push {r4} +10003d2a: f89d 4004 ldrb.w r4, [sp, #4] +10003d2e: 9401 str r4, [sp, #4] +10003d30: f85d 4b04 ldr.w r4, [sp], #4 +10003d34: f7ff bf32 b.w 10003b9c + +10003d38 : +10003d38: 4684 mov ip, r0 +10003d3a: ea41 0300 orr.w r3, r1, r0 +10003d3e: f013 0303 ands.w r3, r3, #3 +10003d42: d149 bne.n 10003dd8 +10003d44: 3a40 subs r2, #64 @ 0x40 +10003d46: d323 bcc.n 10003d90 +10003d48: 680b ldr r3, [r1, #0] +10003d4a: 6003 str r3, [r0, #0] +10003d4c: 684b ldr r3, [r1, #4] +10003d4e: 6043 str r3, [r0, #4] +10003d50: 688b ldr r3, [r1, #8] +10003d52: 6083 str r3, [r0, #8] +10003d54: 68cb ldr r3, [r1, #12] +10003d56: 60c3 str r3, [r0, #12] +10003d58: 690b ldr r3, [r1, #16] +10003d5a: 6103 str r3, [r0, #16] +10003d5c: 694b ldr r3, [r1, #20] +10003d5e: 6143 str r3, [r0, #20] +10003d60: 698b ldr r3, [r1, #24] +10003d62: 6183 str r3, [r0, #24] +10003d64: 69cb ldr r3, [r1, #28] +10003d66: 61c3 str r3, [r0, #28] +10003d68: 6a0b ldr r3, [r1, #32] +10003d6a: 6203 str r3, [r0, #32] +10003d6c: 6a4b ldr r3, [r1, #36] @ 0x24 +10003d6e: 6243 str r3, [r0, #36] @ 0x24 +10003d70: 6a8b ldr r3, [r1, #40] @ 0x28 +10003d72: 6283 str r3, [r0, #40] @ 0x28 +10003d74: 6acb ldr r3, [r1, #44] @ 0x2c +10003d76: 62c3 str r3, [r0, #44] @ 0x2c +10003d78: 6b0b ldr r3, [r1, #48] @ 0x30 +10003d7a: 6303 str r3, [r0, #48] @ 0x30 +10003d7c: 6b4b ldr r3, [r1, #52] @ 0x34 +10003d7e: 6343 str r3, [r0, #52] @ 0x34 +10003d80: 6b8b ldr r3, [r1, #56] @ 0x38 +10003d82: 6383 str r3, [r0, #56] @ 0x38 +10003d84: 6bcb ldr r3, [r1, #60] @ 0x3c +10003d86: 63c3 str r3, [r0, #60] @ 0x3c +10003d88: 3040 adds r0, #64 @ 0x40 +10003d8a: 3140 adds r1, #64 @ 0x40 +10003d8c: 3a40 subs r2, #64 @ 0x40 +10003d8e: d2db bcs.n 10003d48 +10003d90: 3230 adds r2, #48 @ 0x30 +10003d92: d30b bcc.n 10003dac +10003d94: 680b ldr r3, [r1, #0] +10003d96: 6003 str r3, [r0, #0] +10003d98: 684b ldr r3, [r1, #4] +10003d9a: 6043 str r3, [r0, #4] +10003d9c: 688b ldr r3, [r1, #8] +10003d9e: 6083 str r3, [r0, #8] +10003da0: 68cb ldr r3, [r1, #12] +10003da2: 60c3 str r3, [r0, #12] +10003da4: 3010 adds r0, #16 +10003da6: 3110 adds r1, #16 +10003da8: 3a10 subs r2, #16 +10003daa: d2f3 bcs.n 10003d94 +10003dac: 320c adds r2, #12 +10003dae: d305 bcc.n 10003dbc +10003db0: f851 3b04 ldr.w r3, [r1], #4 +10003db4: f840 3b04 str.w r3, [r0], #4 +10003db8: 3a04 subs r2, #4 +10003dba: d2f9 bcs.n 10003db0 +10003dbc: 3204 adds r2, #4 +10003dbe: d008 beq.n 10003dd2 +10003dc0: 07d2 lsls r2, r2, #31 +10003dc2: bf1c itt ne +10003dc4: f811 3b01 ldrbne.w r3, [r1], #1 +10003dc8: f800 3b01 strbne.w r3, [r0], #1 +10003dcc: d301 bcc.n 10003dd2 +10003dce: 880b ldrh r3, [r1, #0] +10003dd0: 8003 strh r3, [r0, #0] +10003dd2: 4660 mov r0, ip +10003dd4: 4770 bx lr +10003dd6: bf00 nop +10003dd8: 2a08 cmp r2, #8 +10003dda: d313 bcc.n 10003e04 +10003ddc: 078b lsls r3, r1, #30 +10003dde: d0b1 beq.n 10003d44 +10003de0: f010 0303 ands.w r3, r0, #3 +10003de4: d0ae beq.n 10003d44 +10003de6: f1c3 0304 rsb r3, r3, #4 +10003dea: 1ad2 subs r2, r2, r3 +10003dec: 07db lsls r3, r3, #31 +10003dee: bf1c itt ne +10003df0: f811 3b01 ldrbne.w r3, [r1], #1 +10003df4: f800 3b01 strbne.w r3, [r0], #1 +10003df8: d3a4 bcc.n 10003d44 +10003dfa: f831 3b02 ldrh.w r3, [r1], #2 +10003dfe: f820 3b02 strh.w r3, [r0], #2 +10003e02: e79f b.n 10003d44 +10003e04: 3a04 subs r2, #4 +10003e06: d3d9 bcc.n 10003dbc +10003e08: 3a01 subs r2, #1 +10003e0a: f811 3b01 ldrb.w r3, [r1], #1 +10003e0e: f800 3b01 strb.w r3, [r0], #1 +10003e12: d2f9 bcs.n 10003e08 +10003e14: 780b ldrb r3, [r1, #0] +10003e16: 7003 strb r3, [r0, #0] +10003e18: 784b ldrb r3, [r1, #1] +10003e1a: 7043 strb r3, [r0, #1] +10003e1c: 788b ldrb r3, [r1, #2] +10003e1e: 7083 strb r3, [r0, #2] +10003e20: 4660 mov r0, ip +10003e22: 4770 bx lr + +10003e24 : +10003e24: f020 0103 bic.w r1, r0, #3 +10003e28: f010 0003 ands.w r0, r0, #3 +10003e2c: f1c0 0000 rsb r0, r0, #0 +10003e30: f851 3b04 ldr.w r3, [r1], #4 +10003e34: f100 0c04 add.w ip, r0, #4 +10003e38: ea4f 0ccc mov.w ip, ip, lsl #3 +10003e3c: f06f 0200 mvn.w r2, #0 +10003e40: bf1c itt ne +10003e42: fa22 f20c lsrne.w r2, r2, ip +10003e46: 4313 orrne r3, r2 +10003e48: f04f 0c01 mov.w ip, #1 +10003e4c: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003e50: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003e54: eba3 020c sub.w r2, r3, ip +10003e58: ea22 0203 bic.w r2, r2, r3 +10003e5c: ea12 12cc ands.w r2, r2, ip, lsl #7 +10003e60: bf04 itt eq +10003e62: f851 3b04 ldreq.w r3, [r1], #4 +10003e66: 3004 addeq r0, #4 +10003e68: d0f4 beq.n 10003e54 +10003e6a: f1c2 0100 rsb r1, r2, #0 +10003e6e: ea02 0201 and.w r2, r2, r1 +10003e72: fab2 f282 clz r2, r2 +10003e76: f1c2 021f rsb r2, r2, #31 +10003e7a: eb00 00d2 add.w r0, r0, r2, lsr #3 +10003e7e: 4770 bx lr + +10003e80 <_fini>: +10003e80: b5f8 push {r3, r4, r5, r6, r7, lr} +10003e82: bf00 nop +10003e84: 0000 movs r0, r0 + ... + +10003e88 <____aeabi_uldivmod_veneer>: +10003e88: f85f f000 ldr.w pc, [pc] @ 10003e8c <____aeabi_uldivmod_veneer+0x4> +10003e8c: 20000221 .word 0x20000221 + +10003e90 <__mutex_exit_veneer>: +10003e90: f85f f000 ldr.w pc, [pc] @ 10003e94 <__mutex_exit_veneer+0x4> +10003e94: 200001e5 .word 0x200001e5 + +10003e98 <__mutex_try_enter_block_until_veneer>: +10003e98: f85f f000 ldr.w pc, [pc] @ 10003e9c <__mutex_try_enter_block_until_veneer+0x4> +10003e9c: 2000017d .word 0x2000017d + +10003ea0 <__pre_init_runtime_init_bootrom_reset>: +10003ea0: 10001a71 q... + +10003ea4 <__pre_init_runtime_init_early_resets>: +10003ea4: 100019e5 .... + +10003ea8 <__pre_init_runtime_init_usb_power_down>: +10003ea8: 10001a19 .... + +10003eac <__pre_init_runtime_init_clocks>: +10003eac: 10001b05 .... + +10003eb0 <__pre_init_runtime_init_post_clock_resets>: +10003eb0: 10001a51 Q... + +10003eb4 <__pre_init_runtime_init_boot_locks_reset>: +10003eb4: 10001969 i... + +10003eb8 <__pre_init_runtime_init_spin_locks_reset>: +10003eb8: 10001a99 .... + +10003ebc <__pre_init_runtime_init_bootrom_locking_enable>: +10003ebc: 10001955 U... + +10003ec0 <__pre_init_runtime_init_mutex>: +10003ec0: 10000da5 .... + +10003ec4 <__pre_init_runtime_init_install_ram_vector_table>: +10003ec4: 10001a9d .... + +10003ec8 <__pre_init_runtime_init_default_alarm_pool>: +10003ec8: 10001121 !... + +10003ecc <__pre_init_first_per_core_initializer>: +10003ecc: 100019b5 .... + +10003ed0 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003ed0: 10001a85 .... + +10003ed4 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10003ed4: 10001a35 5... + +10003ed8 <__pre_init_spinlock_set_extexclall>: +10003ed8: 100009f5 .... + +10003edc <__pre_init_runtime_init_per_core_irq_priorities>: +10003edc: 10000a1d .... + +10003ee0 <__frame_dummy_init_array_entry>: +10003ee0: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 1000151d .word 0x1000151d + +200005a8 : +200005a8: 00000008 .... + +200005ac : +200005ac: 00000004 .... + +200005b0 : +200005b0: ' + +200005b1 : +200005b1: ... + +200005b4 : +200005b4: 00000000 .word 0x00000000 +200005b8: 00010000 .word 0x00010000 + ... +200005c4: 00020000 .word 0x00020000 + ... +200005d0: 00030000 .word 0x00030000 + ... +200005dc: 00ff0000 .word 0x00ff0000 +200005e0: 00000000 .word 0x00000000 + +200005e4 : +200005e4: b501 push {r0, lr} +200005e6: 6848 ldr r0, [r1, #4] +200005e8: 3101 adds r1, #1 +200005ea: 468e mov lr, r1 +200005ec: 4700 bx r0 + +200005ee : +200005ee: 4670 mov r0, lr +200005f0: 3809 subs r0, #9 +200005f2: 4901 ldr r1, [pc, #4] @ (200005f8 ) +200005f4: 4788 blx r1 +200005f6: bd01 pop {r0, pc} +200005f8: 10000cdd .word 0x10000cdd + +200005fc : + ... +20000610: 20000648 H.. + +20000614 : +20000614: 100039a9 10003ab1 100039f9 10003ac1 .9...:...9...:.. +20000624: 00000000 00000100 ........ + +2000062c : +2000062c: 40098000 00000000 ...@.... + +20000634 : +20000634: 40090000 00000000 ...@.... + +2000063c : + ... diff --git a/WEEK07/0x0017_constants/build/0x0017_constants.elf b/WEEK07/0x0017_constants/build/0x0017_constants.elf new file mode 100755 index 0000000..39defb4 Binary files /dev/null and b/WEEK07/0x0017_constants/build/0x0017_constants.elf differ diff --git a/WEEK07/0x0017_constants/build/0x0017_constants.elf.map b/WEEK07/0x0017_constants/build/0x0017_constants.elf.map new file mode 100644 index 0000000..de3568a --- /dev/null +++ b/WEEK07/0x0017_constants/build/0x0017_constants.elf.map @@ -0,0 +1,3759 @@ +Archive member included to satisfy reference by file (symbol) + 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100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK07/0x0017_constants/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK07/0x0017_constants/lcd_1602.c b/WEEK07/0x0017_constants/lcd_1602.c new file mode 100644 index 0000000..7425cf1 --- /dev/null +++ b/WEEK07/0x0017_constants/lcd_1602.c @@ -0,0 +1,114 @@ +/** + * @file lcd_1602.c + * @brief Implementation of PCF8574-backed HD44780 (16x2) LCD driver + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "lcd_1602.h" +#include +#include + +static i2c_inst_t *lcd_i2c = NULL; +static uint8_t lcd_addr = 0x27; +static int lcd_nibble_shift = 4; +static uint8_t lcd_backlight_mask = 0x08; + +/* PCF8574 -> LCD control pins */ +#define PIN_RS 0x01 +#define PIN_RW 0x02 +#define PIN_EN 0x04 + +static void pcf_write_byte(uint8_t data) { + if (!lcd_i2c) return; + i2c_write_blocking(lcd_i2c, lcd_addr, &data, 1, false); +} + +static void pcf_pulse_enable(uint8_t data) { + pcf_write_byte(data | PIN_EN); + sleep_us(1); + pcf_write_byte(data & ~PIN_EN); + sleep_us(50); +} + +static void lcd_write4(uint8_t nibble, uint8_t mode) { + uint8_t data = (nibble & 0x0F) << lcd_nibble_shift; + data |= mode ? PIN_RS : 0; + data |= lcd_backlight_mask; + pcf_pulse_enable(data); +} + +static void lcd_send(uint8_t value, uint8_t mode) { + lcd_write4((value >> 4) & 0x0F, mode); + lcd_write4(value & 0x0F, mode); +} + +void lcd_i2c_init(i2c_inst_t *i2c, uint8_t pcf_addr, int nibble_shift, uint8_t backlight_mask) { + lcd_i2c = i2c; + lcd_addr = pcf_addr; + lcd_nibble_shift = nibble_shift; + lcd_backlight_mask = backlight_mask; + + // Follow init sequence for HD44780 in 4-bit mode + lcd_write4(0x03, 0); + sleep_ms(5); + lcd_write4(0x03, 0); + sleep_us(150); + lcd_write4(0x03, 0); + sleep_us(150); + lcd_write4(0x02, 0); + sleep_us(150); + + // Function set: 4-bit, 2 lines + lcd_send(0x28, 0); + + // Display on, cursor off + lcd_send(0x0C, 0); + + // Clear + lcd_send(0x01, 0); + sleep_ms(2); + + // Entry mode set + lcd_send(0x06, 0); +} + +void lcd_clear(void) { + lcd_send(0x01, 0); + sleep_ms(2); +} + +void lcd_set_cursor(int line, int position) { + const uint8_t row_offsets[] = {0x00, 0x40}; + + if (line > 1) line = 1; + lcd_send(0x80 | (position + row_offsets[line]), 0); +} + +void lcd_puts(const char *s) { + while (*s) { + lcd_send((uint8_t)*s++, 1); + } +} diff --git a/WEEK07/0x0017_constants/lcd_1602.h b/WEEK07/0x0017_constants/lcd_1602.h new file mode 100644 index 0000000..072ae13 --- /dev/null +++ b/WEEK07/0x0017_constants/lcd_1602.h @@ -0,0 +1,74 @@ +/** + * @file lcd_1602.h + * @brief Header for PCF8574-backed HD44780 (16x2) LCD driver + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LCD_1602_H +#define LCD_1602_H + +#include +#include "pico/stdlib.h" +#include "hardware/i2c.h" + +/** + * @brief Initialize the LCD driver over I2C + * + * Configures the internal driver state and performs the HD44780 initialization + * sequence. The driver does not configure I2C pins or call i2c_init; that + * must be done by the caller prior to calling this function. + * + * @param i2c Pointer to the I2C instance (e.g. i2c0 or i2c1) + * @param pcf_addr PCF8574 I2C address (commonly 0x27 or 0x3F) + * @param nibble_shift Bit shift applied to 4-bit nibbles (commonly 4 or 0) + * @param backlight_mask PCF8574 bit mask that controls the backlight + */ +void lcd_i2c_init(i2c_inst_t *i2c, uint8_t pcf_addr, int nibble_shift, uint8_t backlight_mask); + +/** + * @brief Clear the LCD display + * + * Clears the display and returns the cursor to the home position. This + * call blocks for the duration required by the HD44780 controller. + */ +void lcd_clear(void); + +/** + * @brief Set the cursor position + * + * @param line Line number (0 or 1) + * @param position Column (0..15) + */ +void lcd_set_cursor(int line, int position); + +/** + * @brief Write a null-terminated string to the display + * + * @param s The string to write (ASCII) + */ +void lcd_puts(const char *s); + +#endif // LCD_1602_H diff --git a/WEEK07/0x0017_constants/pico_sdk_import.cmake b/WEEK07/0x0017_constants/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK07/0x0017_constants/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK07/0x0017a_ctf/.gitignore b/WEEK07/0x0017a_ctf/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK07/0x0017a_ctf/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK07/0x0017a_ctf/.vscode/c_cpp_properties.json b/WEEK07/0x0017a_ctf/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..613c996 --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.3.1/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.3.1/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/15_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK07/0x0017a_ctf/.vscode/cmake-kits.json b/WEEK07/0x0017a_ctf/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK07/0x0017a_ctf/.vscode/extensions.json b/WEEK07/0x0017a_ctf/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK07/0x0017a_ctf/.vscode/launch.json b/WEEK07/0x0017a_ctf/.vscode/launch.json new file mode 100644 index 0000000..451b846 --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/launch.json @@ -0,0 +1,52 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.1/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "debuggerArgs": ["-ex", "set debug-file-directory /debug"], + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.3.1/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + } + ] +} diff --git a/WEEK07/0x0017a_ctf/.vscode/settings.json b/WEEK07/0x0017a_ctf/.vscode/settings.json new file mode 100644 index 0000000..5b883ba --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/settings.json @@ -0,0 +1,46 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + }, + "variant": { + "statusBarVisibility": "hidden" + }, + "buildTarget": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/15_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.3.1/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v4.3.4/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.1/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.3.1", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/15_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.3.1/picotool:${env:HOME}/.pico-sdk/cmake/v4.3.4/bin:${env:HOME}/.pico-sdk/ninja/v1.13.2:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v4.3.4/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.13.2/ninja" +} diff --git a/WEEK07/0x0017a_ctf/.vscode/tasks.json b/WEEK07/0x0017a_ctf/.vscode/tasks.json new file mode 100644 index 0000000..2f07d94 --- /dev/null +++ b/WEEK07/0x0017a_ctf/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.13.2/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.13.2/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.3.1/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.3.1/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe" + } + } + ] +} diff --git a/WEEK07/0x0017a_ctf/CMakeLists.txt b/WEEK07/0x0017a_ctf/CMakeLists.txt new file mode 100644 index 0000000..7a6ba40 --- /dev/null +++ b/WEEK07/0x0017a_ctf/CMakeLists.txt @@ -0,0 +1,128 @@ +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: CMakeLists.txt +# Desc: Configures the RP2350 Pico SDK project and cryptographic module +# targets for the DEEPLINE Metro practice firmware. Mirrors the +# hardened Ouroboros construction of encryption-c-rp2350. +# Created: 2026 + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.3.1) +set(toolchainVersion 15_2_Rel1) +set(picotoolVersion 2.3.1) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if(EXISTS ${picoVscode}) + include(${picoVscode}) +endif() + +set(PICO_BOARD pico2 CACHE STRING "Board type") + +include(pico_sdk_import.cmake) +project(CTF-02 C CXX ASM) +find_package(Python3 COMPONENTS Interpreter REQUIRED) + +set(DEMO_ARTIFACT_JSON ${CMAKE_CURRENT_LIST_DIR}/scripts/demo_artifact.json) +set(DEMO_ARTIFACT_HEADER_COMMITTED ${CMAKE_CURRENT_LIST_DIR}/include/demo_artifact.h) +set(DEMO_ARTIFACT_HEADER_GENERATED ${CMAKE_CURRENT_BINARY_DIR}/generated/demo_artifact.h) + +add_custom_command( + OUTPUT ${DEMO_ARTIFACT_HEADER_GENERATED} + COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/generated + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/scripts/dec.py + --from-json ${DEMO_ARTIFACT_JSON} + --header-out ${DEMO_ARTIFACT_HEADER_GENERATED} + --check-header-path ${DEMO_ARTIFACT_HEADER_COMMITTED} + DEPENDS + ${CMAKE_CURRENT_LIST_DIR}/scripts/dec.py + ${DEMO_ARTIFACT_JSON} + ${DEMO_ARTIFACT_HEADER_COMMITTED} + COMMENT "Regenerating demo artifact header from JSON and checking committed header freshness" + VERBATIM +) + +add_custom_target(check_demo_artifact_header DEPENDS ${DEMO_ARTIFACT_HEADER_GENERATED}) + +pico_sdk_init() + +if(NOT PICO_MBEDTLS_PATH) + set(PICO_MBEDTLS_PATH ${PICO_SDK_PATH}/lib/mbedtls) +endif() + +# Argon2id reference implementation (PHC winner), compiled single-threaded. +set(ARGON2_SRC ${CMAKE_CURRENT_LIST_DIR}/third_party/argon2) +add_library(argon2_ref STATIC + ${ARGON2_SRC}/src/argon2.c + ${ARGON2_SRC}/src/core.c + ${ARGON2_SRC}/src/ref.c + ${ARGON2_SRC}/src/encoding.c + ${ARGON2_SRC}/src/blake2/blake2b.c +) +target_compile_definitions(argon2_ref PUBLIC ARGON2_NO_THREADS) +target_include_directories(argon2_ref PUBLIC + ${ARGON2_SRC}/include + ${ARGON2_SRC}/src +) + +# mbedTLS subset: ChaCha20, Poly1305, ChaCha20-Poly1305, constant-time. +add_library(mbedtls_subset STATIC + ${PICO_MBEDTLS_PATH}/library/chacha20.c + ${PICO_MBEDTLS_PATH}/library/poly1305.c + ${PICO_MBEDTLS_PATH}/library/chachapoly.c + ${PICO_MBEDTLS_PATH}/library/constant_time.c + src/mbedtls_shims.c +) +target_compile_definitions(mbedtls_subset PUBLIC MBEDTLS_CONFIG_FILE="mbedtls_config.h") +target_include_directories(mbedtls_subset PUBLIC + include + ${PICO_MBEDTLS_PATH}/include + ${PICO_MBEDTLS_PATH}/library +) + +# Ouroboros authentication engine consuming the Argon2id and AEAD layers. +add_library(auth STATIC src/auth.c) +add_dependencies(auth check_demo_artifact_header) +target_include_directories(auth PUBLIC include) +target_link_libraries(auth PUBLIC pico_stdlib mbedtls_subset argon2_ref) + +# DEEPLINE Metro practice firmware executable. +add_executable(CTF-02 src/main.c) +target_link_libraries(CTF-02 PRIVATE auth pico_stdlib) +pico_enable_stdio_uart(CTF-02 0) +pico_enable_stdio_usb(CTF-02 1) +target_compile_definitions(CTF-02 PRIVATE + PICO_DEFAULT_UART_BAUD_RATE=115200 +) +pico_add_extra_outputs(CTF-02) \ No newline at end of file diff --git a/WEEK07/0x0017a_ctf/CTF-02-I.md b/WEEK07/0x0017a_ctf/CTF-02-I.md new file mode 100644 index 0000000..37de55e --- /dev/null +++ b/WEEK07/0x0017a_ctf/CTF-02-I.md @@ -0,0 +1,673 @@ +# Operation Copperhead - Student Instructions + +**⚠ DEEPLINE METRO EMERGENCY INCIDENT ⚠** + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N C O P P E R H E A D | +| | +| *** PRIORITY RED *** | +| | ++----------------------------------------------------------------------------------------+ +``` + +--- + +## Project Overview + +DEEPLINE Metro Authority's rebuilt DEEPLINE-AUTH field relay image shipped +four corrupted engineering constants: a miscalibrated release threshold, a +false TRACK banner string, an overstated block length, and a poisoned ARX +signal seed. The corrupted image reports an occupied BRIDGE-4 block as +stable and authorized while rescue crews approach, and the source used for +the emergency rebuild was overwritten seventeen minutes later and cannot be +recovered. Students reverse engineer `CTF-02.bin` with Ghidra, patch all +four defects, capture the runtime-derived signal key live in GDB, recover +and authenticate the Ouroboros authority frame, export a corrected image, +flash it to a Pico 2, and prove the corrected behavior on real hardware. + +--- + +## Scenario Briefing + +### Read This First (Plain English) + +The story uses rail-signalling words that read as jargon the first time you +hit them. Here is what they mean; keep this list open while you read. + +- **Block**: a fixed section of track. Only one train may occupy it at a + time. A block is **safe** when it is empty, so the train waiting at its + start may proceed, and **occupied** when a train is inside it, so the + train behind must hold. +- **Track circuit**: a current sent through the rails to detect where + trains are. A train's wheels short the rails and drop that current, which + is how the system knows a block is occupied. +- **Pilot wire**: the sensing line that carries the track-circuit reading + back to the relay. The **dead pilot wire** in this story has a frozen + reading: the value is latched and no longer updates. +- **Field relay**: the small embedded controller, one per block, that + watches the reading and decides hold versus authorize. This challenge uses + a Pico 2 as the relay. +- **Command floor**: the central control room for the whole railway. +- **Blacklock**: a coordinated cyberattack that bricks the control room and + locks everyone out of central operations. After a blacklock, every safety + decision falls back to the local relays. +- **How deep?**: the DEEPLINE corridor runs roughly 40 meters below street + level inside a hardened tube called the armored shell. + +Once these words make sense, the incident below is a simple story: a relay +is lying about whether the block ahead is clear, and your job is to find +the corrupted bytes that make it lie. + +### Background + +**DEEPLINE Metro Authority** runs an armored railway deep beneath the +city, roughly 40 meters below street level, inside a hardened tube called +the armored shell. Armored two-car trains carry people through it, and +tonight they are also carrying rescue crews toward riders trapped inside +the tunnels. + +To understand what is happening, picture how the line stays safe. The line +is cut into fixed stretches of track called **blocks**. A block is one +piece of track, and the rule is absolute: only one train may be inside a +block at any moment. Before a train may roll out of its current block and +into the next one, the system must first prove the next block is empty. +Empty means safe, and safe means the train may proceed. Occupied means +danger, and danger means the train must stop and wait. + +How does the system prove a block is empty? It uses electricity. A steady +current is pushed into the rails of every block, and a small embedded +computer called a **field relay** (call sign **DEEPLINE-AUTH**) watches +that current. This is called a **track circuit**. When nothing is on a +block, the current flows normally. When a train rolls in, its steel wheels +connect the two rails and the current changes, and that change is the +relay's signal that a train is there. The **pilot wire** is the sensing +line that carries this reading from the rails up to the relay. + +So every block has a relay doing the same honest job: read the current, +ask "is the block ahead empty?", and answer with only two words, **HOLD** +(stop, do not move) or **AUTHORIZE** (the way is clear, go). The relays are +the railway's nervous system, and with the command floor dead they are the +only nervous system left. + +The command floor is the central control room where humans used to watch +the entire line. It was **blacklocked** by a coordinated attack: shut out, +locked, and made useless. When it went dark, the trains lost their view +from above. Every safety decision dropped down to the relays on the +ground, running their local firmware, deciding hold or authorize block by +block. + +At 0341 UTC, a threat actor known as **Cortex Sledge** posted a message +calling the moment before it happened: a blacklock of the DEEPLINE control +floor followed by a silent corruption of the field relay images, so nothing +inside the tunnels could agree on what was safe. The blacklock landed. With +the network coordination center offline and rescue crews already inside the +armored shell, the engineering team rebuilt the relay firmware around the +**Ouroboros hardened gate**: an encrypted authority frame protected by a +12-word operation passphrase and sealed with Argon2id plus +XChaCha20-Poly1305. The rebuilt image was pushed to the fleet within +minutes of the blacklock. + +That speed is where the story goes wrong, and it is the trap you walk +into tonight. + +### The Origin of the Ouroboros Gate + +The Ouroboros gate did not come from DEEPLINE. It came from a reclusive +cryptographer who spent a decade obsessed with a single, improbable goal: +to write encryption that could not be broken, not by anyone, not ever. +The engineers who worked beside him dismissed the obsession as unworkable, +and he never argued. When he finished, he published the work as a single +squashed archive tagged **v0.1.0**, with the compiled gate firmware image +attached to the release, and then vanished. + +What he left behind is the strict Ouroboros construction: a memory-hard +Argon2id key schedule feeding an authenticated XChaCha20-Poly1305 authority +frame: symmetric cryptography hardened for the RP2350's memory budget, with +an honest threat model instead of a sales pitch. In plain terms, Ouroboros +is the relay's lock: an order is only trusted if an operator holding the +correct 12-word phrase unlocks it. The corruption in this challenge is +separate from that lock, plain wrong numbers in the safety math, not a +crack in the encryption. DEEPLINE quietly adopted it +for the field relays because it was the strongest gate anyone had ever +shipped that would still boot on the target. A decade of asking +"what if it must not be broken?" is the only reason the relay console can be +an authoritative gate at all. Tonight, in a tunnel with rescue crews +approaching a block the firmware is lying about, that authenticated gate +matters more than DEEPLINE's own design review ever did. + +### The Disaster + +The relay boots. It prints a status report. It reports **TRACK: NORMAL**, +**BLOCK STATE: STABLE**, and **AUTO TRAIN: AUTHORIZED**. To anyone standing +in the tunnel, that console looks like the railway giving the all-clear: +the track is fine, the block ahead is stable and empty, and the train may +move. + +The console is lying, and here is the math behind the lie, step by step. + +Step 1. The relay is reading **87 A** from the dead pilot wire. A pilot +wire goes dead when the reading freezes, so the relay is looking at a stale +number instead of live reality. That number is thrust in front of the relay +every cycle, and the relay keeps trusting it. + +Step 2. DEEPLINE's hard engineering rule says no train may be released +into a block whose reading is at or above **60 A**. 87 A is nearly 45 +percent beyond that limit. In plain terms, the reading is screaming that +the insulated block ahead is compromised. + +Step 3. The compromised block in this incident is the exact block where +the two-car train is sitting right now, with rescue crews approaching on +foot. The reading is not noise and it is not a drill. The block ahead is +occupied. + +An honest relay would do that arithmetic and reach the only logical answer: +reading too high, block unsafe, print BLOCK STATE: CRITICAL, set AUTO TRAIN: +HELD, and hold the train. That is what the relay was designed to do, and it is +the only thing standing between the rescue corridor and a collision. + +The image that shipped does the opposite. It prints STABLE. It prints +AUTHORIZED. It tells the train the way is clear when the way is not clear. + +The reason is corruption. Between the safe reference firmware and the image +pushed to the fleet, four engineering constants were changed. A constant is +a fixed number baked into the firmware, like the amounts in a recipe, and a +single wrong number can flip the entire verdict. The corrupted image +believes 87 A is acceptable, believes the occupied block is empty, and will +hand the train a green light straight into the rescue crews' tunnel. + +If the fleet trusts that console, the two-car train is dispatched into the +occupied block at the same moment the crews mark the corridor with their +[chemlight], and nobody gets a second chance at that tunnel. + +**The rushed build has defects. The four constants were corrupted between +the safe reference firmware and the image that shipped. The source used for +the emergency rebuild was overwritten by the next build seventeen minutes +later and cannot be recovered. Nobody has found where the corrupt values +live in the compiled image.** That is the hole you were called in to fill. + +### The Only Surviving Evidence + +One field relay, the training/verification unit, still holds the exact +miscompiled image that shipped to the fleet. This image, and this image +alone, is the only remaining copy of the emergency build. There is no +source code. There is no build log. There is only the compiled image, a USB +console link, an SWD debug probe, and whatever a skilled embedded reverse +engineer can prove by reading machine code. + +### The Human Stakes + +| Consequence if the false "STABLE" reading is trusted | Scale | +|---|---| +| Two-car train dispatched into an occupied BRIDGE-4 block | 1 train | +| Rescue crews walking toward a block the console calls safe | 4 teams | +| Stations and hospital spokes on backup power after blacklock | 29 facilities | +| Estimated riders stranded in the armored shell | 210+ people | + +**The options are:** + +1. ❌ **Trust the console**: the train releases on a false reading, the + BRIDGE-4 corridor becomes a collision scene. +2. ❌ **Scrap the fleet's firmware**, which buys time but leaves crews in the + tunnel with no interlocking and no authority frame at all. +3. **REVERSE ENGINEER THE EMERGENCY BUILD**: find the exact corrupt + bytes, patch them, prove the corrected image on real hardware, and hand + the fix to the field team so the *rest of the fleet* can be repatched + before the next attempt. + +### THE SHORTAGE + +For years, the world treated embedded systems as invisible infrastructure. +The engineers who could read a vector table, decode a Thumb branch, or +patch a corrupted constant directly in a stripped binary were never +numerous enough. Tonight almost all of them are already in the field +chasing other failures. **You are the reserve team.** + +You were called in because you can do something no exhausted command-floor +team can do right now: read what the processor is actually doing, with no +source code, no time for a rewrite, and no room for a guess. + +> **⏰ TIME PRESSURE:** The field team is standing by to push your verified +> patch to the rest of the DEEPLINE fleet. Every relay still reporting a +> false "STABLE" status is one two-car release away from a disaster. + +> **AUTHORIZED LAB ONLY:** This challenge uses a supplied Pico 2 training +> relay and its exact corrupted firmware image. Do not connect this +> exercise to a public network, an operational railway, a metro system, or +> any device you do not own or have explicit written authorization to test. + +--- + +## Learning Objectives + +- Decode an ARM Cortex-M33 vector and boot table and identify the reset + handler and initial stack pointer. +- Translate Thumb reset-vector addresses into real function entry points and + trace literal-pool entries to their data. +- Locate four corrupted constants: a boundary comparison, a status string, + an 8-byte IEEE-754 double, and an ARX signal seed. +- Analyze unsigned compare semantics, condition codes, and compiler + transforms of boundary tests. +- Capture a runtime-derived key with GDB, override a register, and set a + watchpoint on stored SRAM state. +- Recover and authenticate an Argon2id plus XChaCha20-Poly1305 authority + frame and describe the crypto pipeline with an honest threat boundary. +- Export and UF2-convert a corrected image, then prove the corrected + behavior on real hardware. + +--- + +## What This Project Tests + +| Week | Concepts Tested | +|------|-----------------| +| 1 | RP2350 architecture, ARM Cortex-M33 registers, stack, flash/RAM, Thumb assembly, Ghidra static analysis | +| 2 | GDB connection, breakpoints, disassembly, register and memory inspection, USB-CDC console observation | +| 3 | Bootrom handoff, vector table, reset handler, startup code, XIP, Thumb-bit addressing | +| 4 | Data segments (`.rodata` / `.data` / `.bss`), initialized data images, little-endian encoding, literal pools, soft-float double layout | +| 5 | Unsigned compare semantics, condition codes (`hi`/`ls`), compiler transforms (`<` vs `<=`), volatile refetch semantics | +| 6 | Runtime signal-key derivation (SENTINEL-ARX quarter rounds), live register capture of a derived key, memory watchpoints | +| 7 | Argon2id memory-hard KDF, XChaCha20-Poly1305 AEAD, HChaCha20 subkey, salt/nonce/tag, authenticated decryption | +| 8 | Ouroboros composition (Argon2id to AEAD to payload dispatch), honest threat-model analysis, incident reporting | + +--- + +## Part 1: Understanding the System + +### DEEPLINE-AUTH Field Relay Hardware + +| Component | Connection | Purpose | +|-----------|------------|---------| +| Raspberry Pi Pico 2 | RP2350 | Runs the corrupted emergency firmware | +| USB-CDC console | Micro-USB to host | Relay console and Ouroboros gate input | +| SWD debug interface | Supplied probe | Authorized GDB inspection | +| Onboard LED | GPIO 25 | Authentication success indicator | + +Every graded finding lives in flash (`.rodata` / `.text` / `.data` image) or +SRAM, and is reachable with only the Weeks 1-8 toolset: Ghidra, GDB, and a +serial console. + +### Console Configuration + +- Transport: USB-CDC virtual COM port (no external adapter needed) +- Baud: `115200` +- Data: `8 bits` +- Parity: `none` +- Stop: `1` +- Logic: `3.3 V` on the debug header + +### Normal (Intended) Behavior + +The relay should run the SENTINEL-ARX signal-key layer, classify the frozen +87 A reading against the **real** DEEPLINE safety limit of **60 A**, report +honestly, and still accept the **Ouroboros authority frame** when an +operator enters the correct 12-word phrase: + +``` ++-----------------------------------------------------------------+ +| Intended Relay Behavior | +| | +| 1. Boot and initialize USB-CDC stdio and the auth gate | +| 2. Print the boot identity and the true TRACK signal | +| 3. Compare the frozen 87 A reading against the 60 A limit | +| 4. 87 A exceeds 60 A, so the block is NOT stable | +| 5. Report BLOCK STATE: CRITICAL and AUTO TRAIN: HELD | +| 6. Mint a SIGNAL KEY each 2-second cycle and watch it match | +| the SIGNAL_SPEC 0x2D879291 (OK, not MISMATCH) | +| 7. The 12-word emergency phrase reauthorizes the frame: | +| AUTHORITY FRAME: VERIFIED and payload on UART | +| 8. Repeat the report once per cycle until conditions change | ++-----------------------------------------------------------------+ +``` + +### Observed (Buggy) Behavior: What You Will See When You First Flash `CTF-02.uf2` + +```text +DEEPLINE METRO AUTHORITY +ADAPTIVE SIGNAL WINDOW: 38 MINUTES +USB-CDC 115200 8N1 | AUTHORIZED LAB CONSOLE +TRACK: NORMAL +BLOCK STATE: STABLE +AUTO TRAIN: AUTHORIZED +BLOCK LENGTH: 3200 M +FAULT POLLS: 1 +SIGNAL KEY: 0x915DCFF8 MISMATCH +RESPONSE> +``` + +> **Terminal Timing Note:** The first four lines (`DEEPLINE METRO...` through +> `TRACK: NORMAL`) represent the **initial boot banner**, emitted once during +> startup. If your serial terminal (PuTTY) connects after the board has +> booted, you will observe the continuous 2-second status stream (`BLOCK +> STATE...` through `SIGNAL KEY...`). To view the boot banner in your terminal, +> reset the Pico (pulse `RUN` to `GND`) while PuTTY is actively connected. + +The status block repeats every 2 seconds with `FAULT POLLS` incrementing. +This is exactly what the field crews are seeing. It is wrong, and it is +wrong in **four independent ways** inside the compiled binary. Do not assume +the first readable sentence is the full truth: treat every printed line as +evidence to be checked against the machine code, not as a fact on its own. + +--- + +## Part 2: The Firmware + +You do not have the source code. It was overwritten seventeen minutes after +the emergency build shipped. You have only the compiled image. Your job is +to reverse engineer it with Ghidra, locate the corrupted constants, patch +the image directly, and prove the corrected behavior: exactly the way the +field team will need to repatch the rest of the deployed fleet. + +### What The Firmware Does + +1. Initializes USB-CDC stdio and the Ouroboros authentication gate. +2. Reads a frozen track-circuit current (87 A) latched on the dead pilot + wire before the blacklock. +3. Compares that reading against a compiled-in safety threshold: **twice**, + once for the operator-facing BLOCK STATE line and once for the automated + AUTO TRAIN decision. +4. Prints a boot banner containing an unconditional TRACK signal line. +5. Enters an infinite 2-second loop that derives a session signal key, + prints the block classification, dispatch decision, block length, fault + poll count, and signal-key verdict. +6. Accepts a 12-word operation passphrase at the `RESPONSE>` prompt and runs + it through the hardened **Ouroboros gate** (Argon2id key derivation plus + XChaCha20-Poly1305 authenticated decryption) before dispatching the + authority frame payload to GPIO25 and UART. + +### Bug Summary: What You Are Graded On + +| Bug # | Category | Severity | Description | Hint | +|-------|----------|----------|--------------|------| +| **Bug #1** | Miscompiled safety constant | **CRITICAL** | The safe-release threshold was compiled far too permissive (95 A). It is used **twice**: once for the operator-facing status and once for the automated train-release decision, and **both** copies must be corrected. | The real DEEPLINE limit is 60 A. Search for the wrong immediate value used in the comparison. | +| **Bug #2** | Hardcoded string literal | **HIGH** | The boot banner unconditionally prints `TRACK: NORMAL` regardless of the actual reading. | The correct word describes a system holding a train at 87 A against a 60 A limit, not "NORMAL". | +| **Bug #3** | Data-section constant | **HIGH** | The block length shipped as 3.2 km; the real BRIDGE-4 block is 0.32 km, far below minimum release spacing. It prints as metres. | Trace the `BLOCK LENGTH` line to its data image in flash. Little-endian IEEE-754 double. | +| **Bug #4** | Init-time seed constant | **HIGH** | The ARX seed fused into the image is `0x0A0A0A0A`; the real seed is `0x6B206574`. The derived signal key therefore never matches `SIGNAL_SPEC`, and the console reports `MISMATCH` every cycle. | The expected value `0x2D879291` is a literal in a pool. The seed is a `.data` image in flash. Ignore decoy `0A` bytes in the input dispatch table. | + +**Important:** The replacement text for Bug #2 **must be the same length** +as the original (`NORMAL` and `DANGER` are both 6 bytes). Patching a shorter +or longer string will corrupt adjacent flash data. + +### A Third Layer: Not a Bug, an Authorization Task + +The **Ouroboros authority frame** is the encrypted artifact that proves an +operator is legitimate: a 48-byte payload sealed with Argon2id-derived keys +and XChaCha20-Poly1305. It is never printed by the firmware's status lines. +Recovering it, by understanding the construction and authenticating with +the correct 12-word phrase, is required evidence for your final report. + +The power of this layer is real but must be described honestly. The +construction is Argon2id (memory-hard KDF) chained into XChaCha20-Poly1305 +(AEAD). Against Grover-style search, symmetric-key security exponents are +**halved**, not annihilated; this firmware is a demonstrator and does not +claim NIST post-quantum status. The honest claim is: **a high modeled +brute-force cost under the stated passphrase entropy and KDF assumptions**, +not "quantum-proof." Your report must state this boundary exactly. + +--- + +## Part 3: Your Assignment + +Whenever a task asks you to **Document** or **answer**, write your answers +in a single file named `CTF-02-Answers.md`. + +### Task 1: Setup and Initial Analysis + +1. Create a new Ghidra project named `Copperhead_Investigation`. +2. Import `CTF-02.bin`. +3. Configure the language as **ARM Cortex 32-bit, little endian**. +4. Set the base address to `0x10000000`. +5. Run auto-analysis. + +**Document:** +- A screenshot of the Ghidra **Import Results** or **Program Information** + window showing the project name, processor settings, and base address. +- The address of `main()`. +- The address of the recurring 2-second status loop (the branch target the + loop restarts from). +- The vector-table base, the initial stack pointer, and the reset-handler + pointer as stored (note its Thumb bit) versus the actual instruction + address. +- One representative literal-pool entry that feeds the status lines, and + what it points to. + +### Task 2: Find and Patch Bug #1: The Miscalibrated Release Threshold + +1. Find **both** locations where the frozen 87 A reading is compared against + the miscompiled safety constant. +2. Document the exact address, the original instruction, and the original + immediate value at each location. +3. Determine the correct immediate value. **Caution:** the compiler may not + have encoded the raw threshold you expect: a strict "less than" + comparison against an unsigned value is often optimized into a + "less-or-equal" comparison against one less than the threshold. Show + your reasoning. +4. Patch **both** locations in Ghidra using the **Bytes Window** workflow: + > **Critical ARM Thumb-2 Patching Note:** In ARM Cortex-M, compare instructions that directly precede conditional execution blocks (`ite ge`) must **not** be patched using the right-click *Patch Instruction* dialog. Ghidra's automatic re-disassembler encounters an internal context conflict with the subsequent `ite ge` instruction, which collapses Thumb decoding and swallows Compare Site B (`0x10000312`). + > + > To patch cleanly without breaking downstream disassembly, use the **Bytes Window**: + > 1. Ensure the Bytes window is open (**Window** -> **Bytes: CTF-02.bin**). + > 2. In the Bytes window toolbar, click the **pencil icon** (**Toggle Edit Mode**). + > 3. In the Listing window, click on address `0x10000302` (Compare Site A) and press **`C`** (**Clear Code Bytes**). The instruction temporarily clears into raw bytes (`5E 2B`). + > 4. In the Bytes window, locate offset `10000302`, click on `5E`, and change it to **`3B`**. + > 5. Click back in the Listing window on address `0x10000302` and press **`D`** (**Disassemble**). The instruction immediately disassembles cleanly as `cmp r3, #0x3b`. + > 6. Notice that Compare Site B at `0x10000312` remains completely intact and visible! Repeat the exact same steps at `0x10000312`: click `0x10000312` in the Listing, press **`C`**, change `5E` to **`3B`** in the Bytes window, click back in the Listing, and press **`D`**. + +**Questions to answer:** +- Why must both locations be patched? What happens if you only patch one? +- Why is a false "STABLE" classification on an 87 A reading dangerous for + an automated train release into an occupied block? + +### Task 3: Find and Patch Bug #2: The False TRACK Banner + +1. Find the boot-banner string that unconditionally reports the wrong + signal state. +2. Document its address and the exact bytes that must change. +3. Patch the string, preserving its exact length. + +**Questions to answer:** +- Document the original vs. patched bytes, character by character. +- Why is a hardcoded, unconditional status word more dangerous than one + that is at least computed from a (miscalibrated) reading? + +### Task 4: Find and Patch Bug #3: The Block Length Constant + +1. Use Ghidra to locate the `BLOCK LENGTH` status line and trace the value + it prints back to its source in the initialized data image. +2. Document the 8-byte IEEE-754 double as stored (little endian) and its + printed interpretation. +3. Patch the data image so the relay reports the real 320 m BRIDGE-4 block. + +**Questions to answer:** +- Show your byte-for-byte conversion from 3.2 km to 0.32 km. +- Why would a console that overstates block length by ten times be as + dangerous as one that understates it? + +### Task 5: Find and Patch Bug #4: The Signal Seed + +1. Find the `SIGNAL_SPEC` value `0x2D879291` in the binary and note where + it lives. +2. Locate the `.data` image in flash that the firmware copies into SRAM at + boot. Identify the seed word that is wrong. +3. Patch the seed so the runtime-derived key matches the spec. + +**Warning:** there are decoy `0x0A0A0A0A` bytes in the console input +dispatch table. The real seed is an initialized data image, not a jump-table +constant. + +**Questions to answer:** +- How is the signal key derived each cycle, and where does the failure + appear in the register trace? +- Does fixing the seed also authenticate the Ouroboros gate? Explain what + each layer does and does not protect. + +### Task 6: GDB Register Capture of the Derived Key + +Prove the signal-key failure from the live machine, not just from static +bytes: + +1. Connect GDB to the running relay via the SWD probe. +2. Break at the second `derive_session_key` call site, immediately after the + branch returns. +3. Read `$r0`. Record the bug-derived key. +4. Inspect the two arguments entering the derivation: the live seed from + SRAM and the derived IV. +5. Overwrite `$r0` with the correct spec value, step out, and confirm the + next status cycle prints `SIGNAL KEY: 0x2D879291 OK`. +6. Verify with a watchpoint on the stored key in SRAM. + +**Questions to answer:** +- Why is the derived value in `$r0` different from the spec, and what alone + in the image is responsible? +- What does the register overwrite prove that the static patch proves + differently (and vice versa)? + +### Task 7: Recover the Ouroboros Authority Frame + +1. In Ghidra, locate the embedded artifact: the 16-byte salt, the 24-byte + XChaCha nonce, and the 64-byte ciphertext-plus-tag. +2. Document the Argon2id parameters compiled into the gate (memory, time, + parallelism) and the payload layout contract (LED byte + UART bytes). +3. On the live relay, enter the canonical 12-word emergency phrase at the + `RESPONSE>` prompt. +4. Confirm the expected outcome: `AUTHORITY FRAME: VERIFIED`, the onboard + LED turning on, and the payload printed to the console. +5. Demonstrate the two failure paths (policy violation and wrong phrase). + +**Questions to answer (honest boundary required):** +- Walk through the full pipeline: Argon2id to 32-byte key, HChaCha20 subkey + from the nonce prefix, inner nonce, Poly1305 tag verification, payload + dispatch. +- What would Grover-style search actually change in this construction, and + why does this firmware not claim strict post-quantum status? + +### Task 8: Export and Verify + +1. Export your patched binary as `CTF-02_fixed.bin`. +2. Convert it to UF2 format for the RP2350: + ```bash + python uf2conv.py CTF-02_fixed.bin --base 0x10000000 --family 0xe48bff59 --output CTF-02_fixed.uf2 + ``` +3. Flash `CTF-02_fixed.uf2` to your Pico 2 and capture the corrected + console output. +4. Confirm the corrected image now reports **TRACK: DANGER**, **BLOCK STATE: + CRITICAL**, **AUTO TRAIN: HELD**, **BLOCK LENGTH: 320 M**, and **SIGNAL + KEY: 0x2D879291 OK**, an honest, safe report instead of a false + "all clear." +5. Build a summary table of every patch: address, original bytes, patched + bytes, and a one-line description. + +### Task 9: Written Reflection (short answers, 150 words or less each) + +1. Why is "the build was rushed under emergency pressure" not an acceptable + excuse for shipping a firmware defect that could dispatch a train into a + block occupied by rescue crews? +2. Name one concrete engineering practice (review, static analysis, + hardware-in-the-loop test, signature verification, etc.) that would have + caught **each** of the four graded bugs before this image reached the + fleet, and one practice that would have stopped the corrupted image from + **running** at all. + +--- + +## How To Breadboard + +- Connect the Pico 2 micro-USB port directly to the host computer. The + relay enumerates as a USB-CDC virtual COM device. +- Open the end-of-line tool of your choice at `115200 8N1`. +- Connect the supplied SWD probe to the debug header according to its + documented pinout for GDB access. +- Use **3.3 V logic only** on the debug header. Never connect a 5 V line to + a Pico GPIO. + +The supplied image is `CTF-02.bin` (for Ghidra analysis) and +`CTF-02.uf2` (for flashing). If your instructor supplies different +filenames, record the actual filenames in your report. + +Flash using BOOTSEL mode (hold BOOT, plug in USB) and copy the UF2 onto the +`RP2350` mass-storage drive, or use `picotool`. + +--- + +## Memory Map Reference + +| Region | Address | Purpose | +|--------|---------|---------| +| Bootrom | `0x00000000` | Immutable boot code | +| Flash/XIP | `0x10000000` | Vector table, code, rodata, `.data` init image | +| SRAM | `0x20000000` | Stack and writable state | + +--- + +## Submission Format + +Submit a folder containing: + +- `CTF-02-Answers.md`; +- screenshots or terminal transcripts; +- `CTF-02_fixed.bin` and `CTF-02_fixed.uf2`; +- the original image hash. + +--- + +## Success Criteria + +You complete the challenge when you can prove all of the following: + +- You can explain how the RP2350 reaches the relay's code from reset. +- You can locate and patch both copies of the miscalibrated threshold. +- You can locate and patch the false TRACK string without corrupting + adjacent data. +- You can locate and patch the corrupted block-length double in the data + image. +- You can locate and patch the corrupted ARX seed and explain why the + runtime-derived key misses its spec. +- You can capture and correct the derived key live in GDB and verify with a + watchpoint. +- You can authenticate through the Ouroboros gate with the correct phrase + and describe the crypto pipeline accurately, including the honest + quantum boundary. +- You can export, convert, flash, and prove the corrected behavior on real + hardware. + +--- + +## Academic Integrity + +By submitting this CTF work, you certify that: + +1. You used only the supplied training relay, image, and lab interface. +2. You did not connect the challenge to a public network, an operational + railway, a metro system, or any third-party device. +3. You understand that embedded reverse engineering and binary patching + require explicit authorization in any real-world context. +4. You will report any discovered weakness responsibly to the course + instructor. + +The world is short on people who can do this work. Treat that +responsibility seriously: verify before you patch, patch before you trust, +and never confuse a clean-looking status line with a safe system. + +--- + +## Reference Material + +- ARM Cortex-M33 Technical Reference Manual +- RP2350 datasheet +- GDB documentation +- Ghidra documentation: [https://ghidra-sre.org/](https://ghidra-sre.org/) +- Strict Ouroboros reference construction (v0.1.0), the published source of + this firmware's gate, with an honest threat model: + [https://github.com/mytechnotalent/encryption-c-rp2350](https://github.com/mytechnotalent/encryption-c-rp2350) +- Reference gate firmware image (v0.1.0 release): + [https://github.com/mytechnotalent/encryption-c-rp2350/releases/download/v0.1.0/encryption_app.uf2](https://github.com/mytechnotalent/encryption-c-rp2350/releases/download/v0.1.0/encryption_app.uf2) +- PHC reference Argon2: [https://github.com/P-H-C/phc-winner-argon2](https://github.com/P-H-C/phc-winner-argon2) diff --git a/WEEK07/0x0017a_ctf/CTF-02-I.pdf b/WEEK07/0x0017a_ctf/CTF-02-I.pdf new file mode 100644 index 0000000..9212a65 Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02-I.pdf differ diff --git a/WEEK07/0x0017a_ctf/CTF-02-R.md b/WEEK07/0x0017a_ctf/CTF-02-R.md new file mode 100644 index 0000000..c8d392a --- /dev/null +++ b/WEEK07/0x0017a_ctf/CTF-02-R.md @@ -0,0 +1,276 @@ +# Operation Copperhead - Requirements & Grading Criteria + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N C O P P E R H E A D | +| | +| REQUIREMENTS & GRADING CRITERIA | +| | ++----------------------------------------------------------------------------------------+ +``` + +--- + +## Project Overview + +Students are the reverse-engineering reserve team called in after DEEPLINE +Metro Authority's rebuilt DEEPLINE-AUTH relay image shipped four corrupted +engineering constants: a miscalibrated release threshold, a false TRACK banner +string, an overstated block length, and a poisoned ARX signal seed. Students +reverse engineer `CTF-02.bin` with Ghidra, patch all four defects, capture the +runtime-derived signal key live in GDB, recover the Ouroboros authority frame, +export a corrected image, flash it to real hardware, and prove the corrected +behavior on a physical Pico 2. + +The challenge is a standalone capstone exercise and contains no answer, +constant, address, bug, or patch belonging to any other course assignment. + +--- + +## Learning Objectives + +- Decode an ARM Cortex-M33 vector and boot table and identify the reset handler + and initial stack pointer. +- Translate Thumb reset-vector addresses into real function entry points and + trace literal-pool entries to their data. +- Locate four corrupted constants: a boundary comparison, a status string, an + 8-byte IEEE-754 double, and an ARX signal seed. +- Capture a runtime-derived key with GDB, override a register, and set a + watchpoint on stored SRAM state. +- Recover and authenticate an Argon2id plus XChaCha20-Poly1305 authority frame. + +Students must use only Weeks 1-8 concepts: ARM registers, stack behavior, +USB-CDC output, GDB, Ghidra static analysis and binary patching, vector tables, +reset startup, XIP, Thumb addressing, data segments and literal pools, +condition-code analysis, runtime key derivation, and the Argon2id plus +XChaCha20-Poly1305 authenticated gate. + +--- + +## Deliverables Checklist + +| # | Deliverable | Format | Criterion | +|---|-------------|--------|-----------| +| 1 | Ghidra project screenshot | PNG/JPG | 1.1 | +| 2 | Vector table and boot table | Inside `CTF-02-Answers.md` | 1.2 | +| 3 | `main()` and status-loop table | Inside `CTF-02-Answers.md` | 1.3 | +| 4 | Literal pool trace | Inside `CTF-02-Answers.md` | 1.4 | +| 5 | Bug #1 evidence and patches | Inside `CTF-02-Answers.md` | 2.1-2.4 | +| 6 | Bug #2 evidence and patch | Inside `CTF-02-Answers.md` | 3.1-3.4 | +| 7 | Bug #3 evidence and patch | Inside `CTF-02-Answers.md` | 4.1-4.3 | +| 8 | Bug #4 evidence and patch | Inside `CTF-02-Answers.md` | 5.1-5.4 | +| 9 | GDB register capture | Inside `CTF-02-Answers.md` | 6.1-6.4 | +| 10 | Ouroboros gate recovery and auth | Inside `CTF-02-Answers.md` | 7.1-7.4 | +| 11 | `CTF-02_fixed.bin` | BIN file | 8.1 | +| 12 | `CTF-02_fixed.uf2` | UF2 file | 8.2 | +| 13 | Corrected console transcript | Inside `CTF-02-Answers.md` | 8.3 | +| 14 | Summary table of all patches | Inside `CTF-02-Answers.md` | 8.4 | +| 15 | Written reflection | Inside `CTF-02-Answers.md` | 9.1-9.2 | + +--- + +## Required Tools and Equipment + +| Tool | Purpose | +|------|---------| +| Raspberry Pi Pico 2 | Isolated target | +| USB-CDC virtual serial console | Observe output and type the gate passphrase | +| SWD debug probe | GDB inspection | +| Ghidra | Static analysis and binary patching | +| GDB | Dynamic analysis and register capture | +| Python (`uf2conv.py`) | UF2 conversion | +| `CTF-02.bin` and `CTF-02.uf2` | Supplied artifacts | + +Console settings: **USB-CDC virtual COM port, 115200 baud, 8 data bits, no +parity, 1 stop bit**. + +--- + +## Artifact Identity + +The instructor-issued artifact hashes are: + +```text +CTF-02.bin 85330C37CD0897746B1AF447E4BAC371DDE2042ABD2D61D58A61FE2A8EEF3537 +CTF-02.uf2 F3CD4840260DB820D792758CECACC5297BEF1971B9EACF7601279256D8AF1EAB +``` + +--- + +## Grading Rubric - Detailed Breakdown + +### Task 1: Setup and Initial Analysis (12 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 1.1: Ghidra Project Setup | 3 | Correct project name, `ARM:LE:32:Cortex` (ARM Cortex 32-bit little endian), base `0x10000000` | One item off | Not set up | +| Criterion 1.2: Vector Table Decoding | 3 | Correct base, initial SP, reset pointer | One missing | Not found | +| Criterion 1.3: main() and Status-Loop Addresses | 4 | Both addresses correct | One correct | Neither found | +| Criterion 1.4: Thumb Addressing and Literal Pool | 2 | Bit 0 cleared and one pool entry traced to its string | Partial | Incorrect | + +### Task 2: Find and Patch Bug #1: The Miscalibrated Release Threshold (15 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 2.1: Locate Compare Sites A and B | 6 | Both addresses and original bytes | One site | Not found | +| Criterion 2.2: Correct Immediate-Value Reasoning | 4 | Explains the `<` to `<=` transform and gives `0x3B` | Correct value, no reasoning | Wrong value | +| Criterion 2.3: Patch Compare Sites A and B | 4 | Both byte changes verified | One site | Not patched | +| Criterion 2.4: Explain Why Both Sites Must Be Patched | 1 | Clear explanation of the two independent comparisons | Vague | Missing | + +### Task 3: Find and Patch Bug #2: The False TRACK Banner (10 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 3.1: Locate the Banner String | 3 | Correct address and cross-reference | Approximate | Not found | +| Criterion 3.2: Patch Six Characters | 4 | All six bytes changed, length preserved | Correct text, wrong bytes documented | Wrong length | +| Criterion 3.3: Character-by-Character Documentation | 2 | Original vs patched byte for all six characters | Partial | Missing | +| Criterion 3.4: Explain the Danger of a Hardcoded Status Word | 1 | Clear, specific reasoning | Generic | Missing | + +### Task 4: Find and Patch Bug #3: The Block Length Constant (10 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 4.1: Locate the .data Double | 3 | Correct address traced from the BLOCK LENGTH print | Approximate | Not found | +| Criterion 4.2: IEEE-754 Bytes and Print Math | 4 | Original and patched 8-byte double with print math (3200 M to 320 M) | Correct patch, no math | Wrong bytes | +| Criterion 4.3: Patch to Print 320 M | 3 | Console shows `BLOCK LENGTH: 320 M` | Wrong bytes | Not patched | + +### Task 5: Find and Patch Bug #4: The Signal Seed (15 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 5.1: Locate SIGNAL_SPEC and the Seed | 5 | `0x2D879291` located and wrong seed `0x0A0A0A0A` found | Partial | Not found | +| Criterion 5.2: Patch the Seed | 4 | Seed bytes changed to `74 65 20 6B` | Wrong byte | Not patched | +| Criterion 5.3: Explain the ARX Derivation | 3 | Correct trace of the per-cycle derivation | Vague | Missing | +| Criterion 5.4: Separate the Security Layers | 3 | Correctly explains what the seed fixes versus the gate | Generic | Missing | + +### Task 6: GDB Register Capture of the Derived Key (15 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 6.1: Breakpoint at the Derive Return | 4 | Correct address and `$r0` read as the bug-derived key | Address off | Not found | +| Criterion 6.2: Inspect the Two Arguments | 4 | Live seed and derived IV captured at the second call | One correct | Missing | +| Criterion 6.3: Override the Register | 4 | `$r0` set to `0x2D879291` and the next cycle shows `OK` | Partial | Missing | +| Criterion 6.4: Watchpoint on the Stored Key | 3 | Watchpoint on the SRAM key location documented | Approximate | Missing | + +### Task 7: Recover the Ouroboros Authority Frame (10 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 7.1: Locate Salt, Nonce, Ciphertext, and Tag | 4 | All three addresses correct in flash | Two correct | Not found | +| Criterion 7.2: Document Argon2id Parameters and Payload Contract | 2 | Correct memory/time/parallelism and payload layout | Partial | Missing | +| Criterion 7.3: Authenticate with the 12-Word Passphrase | 2 | `AUTHORITY FRAME: VERIFIED`, LED on, payload printed | Partial | Not shown | +| Criterion 7.4: State the Honest Quantum Boundary | 2 | Grover halves symmetric exponents; not strict PQC | Generic | Misstates | + +### Task 8: Export and Verify (8 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 8.1: Export CTF-02_fixed.bin | 1 | Valid patched binary | Corrupted | Not submitted | +| Criterion 8.2: Convert to CTF-02_fixed.uf2 | 1 | Correct base and family flags | Wrong flags | Not submitted | +| Criterion 8.3: Hardware Verification | 4 | Corrected console output confirmed (CRITICAL/HELD in 2s stream; DANGER at boot/Ghidra) | Some lines corrected | No verification | +| Criterion 8.4: Summary Table of All Patches | 2 | Complete address and before/after table | Missing entries | No table | + +### Task 9: Written Reflection (5 points) + +| Criterion | Points | Full credit | Partial credit | No credit | +|-----------|--------|-------------|----------------|-----------| +| Criterion 9.1: "Rushed Build" Is Not an Excuse | 2 | Specific, grounded reasoning | Generic | Missing | +| Criterion 9.2: One Engineering Practice per Failure Area | 3 | Concrete practices for the bugs and for image authenticity | Names some | Missing | + +--- + +## Common Pitfalls + +| Pitfall | Consequence | Avoidance | +|---------|-------------|-----------| +| Patching only one threshold site | One status line still lies | Patch both `0x10000302` and `0x10000312` | +| Assuming the immediate equals the limit | Off-by-one, wrong boundary | Use `0x3B` (59), not `0x3C` (60) | +| Using Patch Instruction before IT block | Re-disassembler context conflict swallows Site B | In Listing press `C` -> edit byte in Bytes window (pencil) -> press `D` | +| Missing boot banner in serial terminal | PuTTY misses one-time 5ms boot banner | Pulse RUN to GND while connected to capture | +| Replacing a string with a different length | Corrupts adjacent flash | `NORMAL` and `DANGER` are both 6 bytes | +| Treating the block length as an integer | Misses the 8-byte double | Follow the value into `.data`, decode IEEE-754 | +| Using the wrong 0.32 bytes | Prints 316 M instead of 320 M | Use `7B 14 AE 47 E1 7A D4 3F` | +| Treating an odd vector address as invalid | Thumb analysis fails | Clear bit 0 | +| Starting the seed patch at the wrong offset | Wrong seed, key never matches | Seed is at `0x1000EC70` | + +--- + +## How To Breadboard + +- **Raspberry Pi Pico 2** powered over USB. +- **USB-CDC virtual serial console:** open the Pico's COM port at 115200 baud, + 8 data bits, no parity, 1 stop bit. +- **SWD debug probe:** connect SWCLK, SWDIO, GND, and 3.3 V to the Pico debug + header for GDB inspection and register capture. +- No other peripherals are required; the authority LED is on-board. + +--- + +## Memory Map Reference + +| Region | Address | Purpose | +|--------|---------|---------| +| Bootrom | `0x00000000` | Immutable boot code | +| Flash/XIP | `0x10000000` | Vector table, code, rodata, `.data` init image | +| SRAM | `0x20000000` | Stack and writable state | + +--- + +## Deadline & Submission + +- Create a folder containing the Ghidra screenshot, `CTF-02_fixed.bin`, and + `CTF-02_fixed.uf2`. +- Write all written answers in a single file named `CTF-02-Answers.md` inside that + folder. +- ZIP the folder as `lastname-firstname-CTF-02.zip`. +- Submit the ZIP before the posted deadline; late submissions lose 10 percent + per day. + +--- + +## Grade Scale + +| Grade | Percentage | Points | +|-------|------------|--------| +| A+ | 97-100% | 97-100 | +| A | 93-96% | 93-96 | +| A- | 90-92% | 90-92 | +| B+ | 87-89% | 87-89 | +| B | 84-86% | 84-86 | +| B- | 80-83% | 80-83 | +| C | 70-79% | 70-79 | +| F | 0-69% | 0-69 | + +--- + +## Academic Integrity + +Use only the supplied Pico 2 and firmware. Do not connect the exercise to an +operational railway, metro system, public network, military system, or +third-party device. This is a controlled, isolated educational exercise. All +analysis and patches must be your own work; sharing binaries, addresses, keys, +passphrases, or answers is a violation of the academic integrity policy. + +--- + +## Reference Material + +| Topic | Reference | +|-------|-----------| +| ARM Cortex-M33 registers and stack | Week 1 | +| USB-CDC output and console capture | Week 2 | +| Vector tables, reset startup, and XIP | Week 2 | +| Ghidra static analysis and binary patching | Week 3 | +| Data segments, literal pools, IEEE-754 | Week 4 | +| Condition-code analysis | Week 5 | +| Runtime key derivation and GDB register capture | Week 6 | +| Argon2id and XChaCha20-Poly1305 authenticated gate | Week 8 | diff --git a/WEEK07/0x0017a_ctf/CTF-02-R.pdf b/WEEK07/0x0017a_ctf/CTF-02-R.pdf new file mode 100644 index 0000000..a8cde10 Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02-R.pdf differ diff --git a/WEEK07/0x0017a_ctf/CTF-02-S.md b/WEEK07/0x0017a_ctf/CTF-02-S.md new file mode 100644 index 0000000..310a619 --- /dev/null +++ b/WEEK07/0x0017a_ctf/CTF-02-S.md @@ -0,0 +1,652 @@ +# Operation Copperhead - Instructor Solution Key + +``` ++----------------------------------------------------------------------------------------+ +| | +| ██████╗ ██╗ █████╗ ██████╗██╗ ██╗███████╗████████╗ █████╗ ██████╗ ████████╗ | +| ██╔══██╗██║ ██╔══██╗██╔════╝██║ ██╔╝██╔════╝╚══██╔══╝██╔══██╗██╔══██╗╚══██╔══╝ | +| ██████╔╝██║ ███████║██║ █████╔╝ ███████╗ ██║ ███████║██████╔╝ ██║ | +| ██╔══██╗██║ ██╔══██║██║ ██╔═██╗ ╚════██║ ██║ ██╔══██║██╔══██╗ ██║ | +| ██████╔╝███████╗██║ ██║╚██████╗██║ ██╗███████╗ ██║ ██║ ██║██║ ██║ ██║ | +| ╚═════╝ ╚══════╝╚═╝ ╚═╝ ╚═════╝██║ ██║╚══════╝ ╚═╝ ╚═╝ ╚═╝██║ ██║ ██║ | +| | +| | +| O P E R A T I O N C O P P E R H E A D | +| | +| *** INSTRUCTOR SOLUTION KEY: RESTRICTED *** | +| | ++----------------------------------------------------------------------------------------+ +``` + +> The task and criterion headings in this key are word-for-word identical to +> `CTF-02-R.md`, so a student can match each criterion one-to-one. + +--- + +## Artifact Identity + +| Artifact | Value | +|----------|-------| +| Student image | `CTF-02.bin` | +| Flash image | `CTF-02.uf2` | +| Target | Raspberry Pi Pico 2 / RP2350 ARM Cortex-M33 | +| Image base | `0x10000000` | +| Console | USB-CDC virtual COM, 115200 8N1 | + +```text +CTF-02.bin 85330C37CD0897746B1AF447E4BAC371DDE2042ABD2D61D58A61FE2A8EEF3537 +CTF-02.uf2 F3CD4840260DB820D792758CECACC5297BEF1971B9EACF7601279256D8AF1EAB +``` + +Proof tool: `python3 scripts/verify_ctf.py` returns `26/26 checks passed` against +`CTF-02.bin`. + +--- + +## Task 1: Setup and Initial Analysis (12 points) + +### Solution + +**Criterion 1.1: Ghidra Project Setup (3 points).** Import `CTF-02.bin` as +`Raw Binary`, language `ARM:LE:32:Cortex`, base address `0x10000000`, then run +auto-analysis. + +**Criterion 1.2: Vector Table Decoding (3 points).** +First 32 bytes of `CTF-02.bin`: + +```text +00 20 08 20 5B 01 00 10 1B 01 00 10 1D 01 00 10 +11 01 00 10 11 01 00 10 11 01 00 10 11 01 00 10 +``` + +| Evidence | Answer | +|----------|--------| +| Vector table base | `0x10000000` | +| Initial SP | `0x20082000` | +| Reset pointer (as stored) | `0x1000015B` | +| Reset instruction address | `0x1000015A` | + +**Criterion 1.3: main() and Status-Loop Addresses (4 points).** + +| Element | Address | +|---------|---------| +| `main()` | `0x100002E8` | +| Recurring status loop start | `0x1000034C` | +| Loop back-edge (`b.n 0x1000034C`) | `0x1000044E` | + +**Criterion 1.4: Thumb Addressing and Literal Pool (2 points).** +The stored reset pointer `0x1000015B` has bit 0 set, selecting Thumb mode. +Clearing bit 0 gives `0x1000015A`. A representative literal pool entry is +`0x100004B4`, which holds `0x1000C4C8`, the address of the format string +`"BLOCK STATE: %s"`, loaded by `ldr r0, [pc, #308]` at `0x1000037C`. + +**Supporting Reference: SRAM Symbols (Ghidra names to semantic roles).** + +| Ghidra Label | SRAM Address | Section | Role | Source Symbol | +|--------------|--------------|---------|------|---------------| +| `DAT_20001188` | `0x20001188` | `.data` | Block length double | `g_telemetry` | +| `DAT_20001198` | `0x20001198` | `.data` | Signal key seed | `g_auth_seed` | +| `DAT_2000119C` | `0x2000119C` | `.data` | Track current | `g_block_current` | +| `DAT_20001ECC` | `0x20001ECC` | `.bss` | Dispatch state | `g_dispatch_state` | +| `DAT_20001ED0` | `0x20001ED0` | `.bss` | Fault poll counter | `g_fault_polls` | +| `DAT_20001ED4` | `0x20001ED4` | `.bss` | Input line buffer | `g_linebuf` | +| `DAT_200020D4` | `0x200020D4` | `.bss` | Input write index | `g_lineidx` | +| `DAT_200020D8` | `0x200020D8` | `.bss` | Operator state | `g_operator_state` | +| `DAT_200020DC` | `0x200020DC` | `.bss` | Derived signal key | `g_signal_key` | + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 1.1: Ghidra Project Setup | 3 | Correct project name, `ARM:LE:32:Cortex` (ARM Cortex 32-bit little endian), base `0x10000000` | One item off | Not set up | +| Criterion 1.2: Vector Table Decoding | 3 | Correct base, initial SP, reset pointer | One missing | Not found | +| Criterion 1.3: main() and Status-Loop Addresses | 4 | Both addresses correct | One correct | Neither found | +| Criterion 1.4: Thumb Addressing and Literal Pool | 2 | Bit 0 cleared and one pool entry traced to its string | Partial | Incorrect | + +### Instructor Notes & Assembly + +- Confirm the Ghidra import used `Raw Binary`, `ARM:LE:32:Cortex`, base + `0x10000000`, and that auto-analysis completed before any address was read. +- Verify `main()` is `0x100002E8`, the loop head is `0x1000034C`, and the + back-edge is `0x1000044E`. +- For Criterion 1.4, accept any correctly traced literal pool entry; the pool + entry `0x100004B4` holding `0x1000C4C8` (`"BLOCK STATE: %s"`, loaded at + `0x1000037C`) is the reference example. +- The SRAM symbol table is supporting reference material, not a separate + scored criterion. + +--- + +## Task 2: Find and Patch Bug #1: The Miscalibrated Release Threshold (15 points) + +### Solution + +**Criterion 2.1: Locate Compare Sites A and B (6 points).** + +```text +10000302: 2b5e cmp r3, #94 @ 0x5e +10000312: 2b5e cmp r3, #94 @ 0x5e +``` + +| Site | Address | File Offset | Original Bytes | Original Instruction | +|------|---------|-------------|----------------|----------------------| +| A | `0x10000302` | `0x0302` | `5E 2B` | `cmp r3, #94` | +| B | `0x10000312` | `0x0312` | `5E 2B` | `cmp r3, #94` | + +**Criterion 2.2: Correct Immediate-Value Reasoning (4 points).** +The source constant is `SAFE_THRESHOLD = 95` and the test is `x < 95`. For an +unsigned value, `x < 95` is exactly `x <= 94`, so the compiler emits +`cmp r3, #94`. The correct limit is `60`, so the test is `x < 60`, which is +`x <= 59`. The correct patched immediate is **`0x3B` (59)**, not `0x3C` (60). + +**Criterion 2.3: Patch Compare Sites A and B (4 points).** + +| Site | Address | File Offset | Original | Patched | After | +|------|---------|-------------|----------|---------|-------| +| A | `0x10000302` | `0x0302` | `5E 2B` | `3B 2B` | `cmp r3, #59` | +| B | `0x10000312` | `0x0312` | `5E 2B` | `3B 2B` | `cmp r3, #59` | + +**Criterion 2.4: Explain Why Both Sites Must Be Patched (1 point).** +Site A drives the `BLOCK STATE` line and site B drives the `AUTO TRAIN` +decision. Patching only site A makes the console read `CRITICAL` while the +automated dispatch still says `AUTHORIZED`. Frozen reading `87`: `87 <= 94` is +true (wrong); `87 <= 59` is false (correct). + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 2.1: Locate Compare Sites A and B | 6 | Both addresses and original bytes | One site | Not found | +| Criterion 2.2: Correct Immediate-Value Reasoning | 4 | Explains the `<` to `<=` transform and gives `0x3B` | Correct value, no reasoning | Wrong value | +| Criterion 2.3: Patch Compare Sites A and B | 4 | Both byte changes verified | One site | Not patched | +| Criterion 2.4: Explain Why Both Sites Must Be Patched | 1 | Clear explanation of the two independent comparisons | Vague | Missing | + +### Instructor Notes & Assembly + +- Both sites must be patched: `0x10000302` for `BLOCK STATE` and `0x10000312` + for the `AUTO TRAIN` decision. +- The correct immediate is `0x3B` (59), not `0x3C` (60). +- Verify the byte changes on hardware; the corrected console reads `CRITICAL` + and `HELD`. +- **Ghidra ARM/Thumb Context Note:** In raw `.bin` files, patching an instruction + that precedes an `IT` block (`ite ge`) using the GUI *Patch Instruction* action + triggers Ghidra's `ReDisassembleCommand`. The re-disassembler encounters an + internal context register conflict when trying to re-declare the `ITBlock` + context over existing instructions, collapsing Thumb decoding into 32-bit ARM + mode and swallowing Site B (`0x10000312`). Students must patch using the Bytes + window workflow (Clear `C` -> edit byte `5E` -> `3B` in Bytes window with pencil + icon -> Disassemble `D`) to keep Site B visible and cleanly aligned. + +--- + +## Task 3: Find and Patch Bug #2: The False TRACK Banner (10 points) + +### Solution + +**Criterion 3.1: Locate the Banner String (3 points).** + +| String | Address | +|--------|---------| +| `"TRACK: NORMAL\r"` | `0x1000C4B8` | +| `"NORMAL"` substring to patch | `0x1000C4BF` | + +The string is loaded in `main` and printed once at boot; it never reads the +sensor. + +**Criterion 3.2: Patch Six Characters (4 points).** +`NORMAL` and `DANGER` are both six ASCII characters, so the patch preserves the +length. + +| Address Range | Original Bytes | Patched Bytes | +|---------------|----------------|---------------| +| `0x1000C4BF` - `0x1000C4C4` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | + +**Criterion 3.3: Character-by-Character Documentation (2 points).** + +| Address | Original Char | Original Byte | Patched Char | Patched Byte | +|---------|---------------|---------------|--------------|--------------| +| `0x1000C4BF` | N | `4E` | D | `44` | +| `0x1000C4C0` | O | `4F` | A | `41` | +| `0x1000C4C1` | R | `52` | N | `4E` | +| `0x1000C4C2` | M | `4D` | G | `47` | +| `0x1000C4C3` | A | `41` | E | `45` | +| `0x1000C4C4` | L | `4C` | R | `52` | + +**Criterion 3.4: Explain the Danger of a Hardcoded Status Word (1 point).** +The banner never consults the reading, so it reports a healthy track even while +the frozen reading is dangerous, masking the hazard from the operator. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 3.1: Locate the Banner String | 3 | Correct address and cross-reference | Approximate | Not found | +| Criterion 3.2: Patch Six Characters | 4 | All six bytes changed, length preserved | Correct text, wrong bytes documented | Wrong length | +| Criterion 3.3: Character-by-Character Documentation | 2 | Original vs patched byte for all six characters | Partial | Missing | +| Criterion 3.4: Explain the Danger of a Hardcoded Status Word | 1 | Clear, specific reasoning | Generic | Missing | + +### Instructor Notes & Assembly + +- `NORMAL` and `DANGER` are both six characters; the patch must not change the + string length or overwrite adjacent flash. +- Confirm the patch covers `0x1000C4BF` through `0x1000C4C4` exactly. +- The banner is printed once at boot and never recomputed, so it is a separate + defect from the threshold. + +--- + +## Task 4: Find and Patch Bug #3: The Block Length Constant (10 points) + +### Solution + +**Criterion 4.1: Locate the .data Double (3 points).** +The console prints `BLOCK LENGTH: 3200 M` from the format string at +`0x1000C4F0`. The value is a `double` in the `.data` init image at +`0x1000EC60` (loaded into `0x20001188` at boot). + +**Criterion 4.2: IEEE-754 Bytes and Print Math (4 points).** +Eight bytes at `0x1000EC60`: + +```text +9A 99 99 99 99 99 09 40 -> 0x400999999999999A -> 3.2 km -> 3200 m +7B 14 AE 47 E1 7A D4 3F -> 0x3FD47AE147AE147B -> 0.32 km -> 320 m +``` + +**Criterion 4.3: Patch to Print 320 M (3 points).** + +| File Offset Range | Flash Address Range | Original Bytes | Patched Bytes | +|-------------------|---------------------|----------------|---------------| +| `0xEC60` - `0xEC67` | `0x1000EC60` - `0x1000EC67` | `9A 99 99 99 99 99 09 40` | `7B 14 AE 47 E1 7A D4 3F` | + +At `0x1000EC68` the adjacent telemetry fields (`03 00 00 00` flags and `07 00` +crossing) are left untouched. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 4.1: Locate the .data Double | 3 | Correct address traced from the BLOCK LENGTH print | Approximate | Not found | +| Criterion 4.2: IEEE-754 Bytes and Print Math | 4 | Original and patched 8-byte double with print math (3200 M to 320 M) | Correct patch, no math | Wrong bytes | +| Criterion 4.3: Patch to Print 320 M | 3 | Console shows `BLOCK LENGTH: 320 M` | Wrong bytes | Not patched | + +### Instructor Notes & Assembly + +- The value is an 8-byte IEEE-754 double, not an integer. Follow the + `BLOCK LENGTH` print into `.data` at `0x1000EC60`. +- The patched bytes `7B 14 AE 47 E1 7A D4 3F` decode to `0.32 km` (`320 m`). +- Confirm the adjacent telemetry fields at `0x1000EC68` (`03 00 00 00` and + `07 00`) are left untouched. + +--- + +## Task 5: Find and Patch Bug #4: The Signal Seed (15 points) + +### Solution + +**Criterion 5.1: Locate SIGNAL_SPEC and the Seed (5 points).** +The SIMPLE comparison in the loop is at `0x100003A6`: + +```text +100003a6: 4559 cmp r1, fp ; fp = SIGNAL_SPEC = 0x2D879291 (pool 0x100004FC) +``` + +The corrupted seed is a `0x0A0A0A0A` word in the `.data` init image at +`0x1000EC70` (loaded into `0x20001198` at boot). The byte values `0A 0A 0A 0A` +also appear in the `tbb` jump table at `0x100003D4`; those are not the seed. + +**Criterion 5.2: Patch the Seed (4 points).** +The required seed is the ChaCha expand word `0x6B206574` (`"te k"`), stored +little-endian as `74 65 20 6B`. + +| File Offset Range | Flash Address Range | Original Bytes | Patched Bytes | +|-------------------|---------------------|----------------|---------------| +| `0xEC70` - `0xEC73` | `0x1000EC70` - `0x1000EC73` | `0A 0A 0A 0A` | `74 65 20 6B` | + +**Criterion 5.3: Explain the ARX Derivation (3 points).** +`derive_session_key(seed, iv)` works exactly like this: + +1. Set `a = seed`, `b = iv`, `c = 0x61707865`, `d = 0x3320646E`. +2. Run four ChaCha quarter-rounds. A quarter-round runs four phases with rotate + amounts 16, 12, 8, 7. Each phase is: `a = a + b; d = d XOR a; + d = rotate_left(d, s); c = c + d; b = b XOR c; b = rotate_left(b, s)`. +3. Return `a XOR d`. + +The runtime IV is `derive_session_key(0x6B206574, 0) = 0x43C974F6`. The shipped +seed `0x0A0A0A0A` gives `derive_session_key(0x0A0A0A0A, 0x43C974F6) = +0x915DCFF8` (MISMATCH). The honest seed `0x6B206574` gives +`derive_session_key(0x6B206574, 0x43C974F6) = 0x2D879291`, which equals +`SIGNAL_SPEC` and prints `OK`. + +**Criterion 5.4: Separate the Security Layers (3 points).** +The signal seed only controls the local `SIGNAL KEY` telemetry check. It does +not authenticate the operator. The Argon2id plus XChaCha20-Poly1305 gate is a +separate layer that requires the 12-word passphrase. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 5.1: Locate SIGNAL_SPEC and the Seed | 5 | `0x2D879291` located and wrong seed `0x0A0A0A0A` found | Partial | Not found | +| Criterion 5.2: Patch the Seed | 4 | Seed bytes changed to `74 65 20 6B` | Wrong byte | Not patched | +| Criterion 5.3: Explain the ARX Derivation | 3 | Correct trace of the per-cycle derivation | Vague | Missing | +| Criterion 5.4: Separate the Security Layers | 3 | Correctly explains what the seed fixes versus the gate | Generic | Missing | + +### Instructor Notes & Assembly + +- The seed is at `0x1000EC70` in the `.data` init image. The `0A 0A 0A 0A` + bytes in the `tbb` jump table at `0x100003D4` are not the seed. +- The patched seed `74 65 20 6B` is the little-endian form of the ChaCha expand + word `0x6B206574` (`"te k"`). +- The seed only affects the local `SIGNAL KEY` check; the Argon2id plus + XChaCha20-Poly1305 gate is a separate authentication layer. + +--- + +## Task 6: GDB Register Capture of the Derived Key (15 points) + +### Solution + +**Criterion 6.1: Breakpoint at the Derive Return (4 points).** +The per-cycle derive is `bl derive_session_key` at `0x10000352`. Break at the +next instruction, `0x10000356`, and read `$r0`. On the shipped image it is +`0x915DCFF8`. + +```gdb +(gdb) break *0x10000356 +(gdb) continue +(gdb) print/x $r0 # 0x915DCFF8 on the corrupted image +``` + +**Criterion 6.2: Inspect the Two Arguments (4 points).** +At the call entry `0x10000352`: + +| Register | Corrupted image | Meaning | +|----------|-----------------|---------| +| `$r0` | `0x0A0A0A0A` | Seed | +| `$r1` | `0x43C974F6` | Derived IV | + +**Criterion 6.3: Override the Register (4 points).** +With execution at `0x10000356`, set `$r0` to the spec key, then continue. The +next cycle prints `SIGNAL KEY: 0x2D879291 OK`. + +```gdb +(gdb) set $r0 = 0x2D879291 +(gdb) continue +``` + +**Criterion 6.4: Watchpoint on the Stored Key (3 points).** +The key is stored in SRAM at `0x200020DC` (`str r0, [r6, #0]`). + +```gdb +(gdb) watch *0x200020DC +``` + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 6.1: Breakpoint at the Derive Return | 4 | Correct address and `$r0` read as the bug-derived key | Address off | Not found | +| Criterion 6.2: Inspect the Two Arguments | 4 | Live seed and derived IV captured at the second call | One correct | Missing | +| Criterion 6.3: Override the Register | 4 | `$r0` set to `0x2D879291` and the next cycle shows `OK` | Partial | Missing | +| Criterion 6.4: Watchpoint on the Stored Key | 3 | Watchpoint on the SRAM key location documented | Approximate | Missing | + +### Instructor Notes & Assembly + +- Confirm the breakpoint is placed at `0x10000356`, the instruction after the + `bl derive_session_key` at `0x10000352`. +- On the shipped image `$r0` reads `0x915DCFF8`; `$r0` is the seed `0x0A0A0A0A` + and `$r1` is the derived IV `0x43C974F6`. +- The stored key lives at `0x200020DC`; accept the documented watchpoint. + +--- + +## Task 7: Recover the Ouroboros Authority Frame (10 points) + +### Solution + +**Criterion 7.1: Locate Salt, Nonce, Ciphertext, and Tag (4 points).** + +| Component | Flash Address | Size | +|-----------|---------------|------| +| Ciphertext + Tag | `0x1000CE94` | 64 B | +| Nonce | `0x1000CED4` | 24 B | +| Salt | `0x1000CEEC` | 16 B | + +**Criterion 7.2: Document Argon2id Parameters and Payload Contract (2 points).** +Argon2id: memory `64 KiB`, iterations `3`, parallelism `1`, output key `32 B`, +salt the 16 bytes above. XChaCha20-Poly1305 decrypts the 48-byte ciphertext with +the 16-byte tag. The plaintext is `01 68 65 6C 6C 6F 0D 0A` followed by zeros: +byte 0 turns the GPIO 25 LED on, and bytes 1 through 7 are printed as `hello` +plus carriage-return and newline. + +**Criterion 7.3: Authenticate with the 12-Word Passphrase (2 points).** +At the `RESPONSE> ` prompt, type: + +```text +orbit olive ladder marble quartz canyon ripple saddle violet ember walnut falcon +``` + +Expected result (proven on hardware): + +```text +hello +AUTHORITY FRAME: VERIFIED +``` + +**Criterion 7.4: State the Honest Quantum Boundary (2 points).** +Grover-style search halves the effective security exponent of a symmetric key, +so a 256-bit key gives about 128 bits of quantum security. The construction uses +classical symmetric and password-hashing primitives and does not implement NIST +post-quantum standards. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 7.1: Locate Salt, Nonce, Ciphertext, and Tag | 4 | All three addresses correct in flash | Two correct | Not found | +| Criterion 7.2: Document Argon2id Parameters and Payload Contract | 2 | Correct memory/time/parallelism and payload layout | Partial | Missing | +| Criterion 7.3: Authenticate with the 12-Word Passphrase | 2 | `AUTHORITY FRAME: VERIFIED`, LED on, payload printed | Partial | Not shown | +| Criterion 7.4: State the Honest Quantum Boundary | 2 | Grover halves symmetric exponents; not strict PQC | Generic | Misstates | + +### Instructor Notes & Assembly + +- Verify the three component addresses in flash: ciphertext plus tag at + `0x1000CE94`, nonce at `0x1000CED4`, salt at `0x1000CEEC`. +- The passphrase is fixed for the lab; a successful gate prints `hello` and + `AUTHORITY FRAME: VERIFIED` and lights the on-board authority LED. +- Grade Criterion 7.4 on the honest boundary: 256-bit symmetric key maps to + about 128 bits under Grover, and the design is not NIST post-quantum. + +--- + +## Task 8: Export and Verify (8 points) + +### Solution + +**Criterion 8.1: Export CTF-02_fixed.bin (1 point).** +Export the patched program from Ghidra (`File -> Export Program...`, `Binary +Format`) as `CTF-02_fixed.bin`. The shipped image is 62,308 bytes. + +**Criterion 8.2: Convert to CTF-02_fixed.uf2 (1 point).** + +```bash +python uf2conv.py CTF-02_fixed.bin --base 0x10000000 --family 0xe48bff59 --output CTF-02_fixed.uf2 +``` + +**Criterion 8.3: Hardware Verification (4 points).** + +Before patching: + +```text +DEEPLINE METRO AUTHORITY +ADAPTIVE SIGNAL WINDOW: 38 MINUTES +USB-CDC 115200 8N1 | AUTHORIZED LAB CONSOLE +TRACK: NORMAL +BLOCK STATE: STABLE +AUTO TRAIN: AUTHORIZED +BLOCK LENGTH: 3200 M +FAULT POLLS: 1 +SIGNAL KEY: 0x915DCFF8 MISMATCH +RESPONSE> +``` + +After all four patches: + +```text +DEEPLINE METRO AUTHORITY +ADAPTIVE SIGNAL WINDOW: 38 MINUTES +USB-CDC 115200 8N1 | AUTHORIZED LAB CONSOLE +TRACK: DANGER +BLOCK STATE: CRITICAL +AUTO TRAIN: HELD +BLOCK LENGTH: 320 M +FAULT POLLS: 1 +SIGNAL KEY: 0x2D879291 OK +RESPONSE> +``` + +**Criterion 8.4: Summary Table of All Patches (2 points).** + +| # | Bug | File Offset | Flash Address | Original Bytes | Patched Bytes | +|---|-----|-------------|---------------|----------------|---------------| +| 1a | Operator threshold | `0x0302` | `0x10000302` | `5E 2B` | `3B 2B` | +| 1b | Dispatch threshold | `0x0312` | `0x10000312` | `5E 2B` | `3B 2B` | +| 2 | TRACK banner | `0xC4BF` - `0xC4C4` | `0x1000C4BF` - `0x1000C4C4` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | +| 3 | Block length | `0xEC60` - `0xEC67` | `0x1000EC60` - `0x1000EC67` | `9A 99 99 99 99 99 09 40` | `7B 14 AE 47 E1 7A D4 3F` | +| 4 | Signal seed | `0xEC70` - `0xEC73` | `0x1000EC70` - `0x1000EC73` | `0A 0A 0A 0A` | `74 65 20 6B` | + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 8.1: Export CTF-02_fixed.bin | 1 | Valid patched binary | Corrupted | Not submitted | +| Criterion 8.2: Convert to CTF-02_fixed.uf2 | 1 | Correct base and family flags | Wrong flags | Not submitted | +| Criterion 8.3: Hardware Verification | 4 | Corrected console output confirmed on hardware | Some lines corrected | No verification | +| Criterion 8.4: Summary Table of All Patches | 2 | Complete address and before/after table | Missing entries | No table | + +### Instructor Notes & Assembly + +- Verify the exported image with `python3 scripts/verify_ctf.py`; the shipped + check expects `26/26 checks passed` against `CTF-02.bin`. +- Confirm the UF2 conversion used base `0x10000000` and family `0xe48bff59`. +- **Serial Terminal Timing:** Note that `print_identity()` (`TRACK: NORMAL`) + fires within the first 5 milliseconds of boot. In normal lab usage, PuTTY + attaches after boot and will display the continuous 2-second status loop + (`BLOCK STATE: CRITICAL`, `AUTO TRAIN: HELD`). To see the corrected banner, + the student must pulse `RUN` to `GND` while PuTTY is open, or demonstrate + the string change at `0x1000C4BF` via Ghidra static analysis. +- The shipped image is 62,308 bytes; confirm the exported corrected image is a + valid patched binary with all four fixes present. + +--- + +## Task 9: Written Reflection (5 points) + +### Solution + +**Criterion 9.1: "Rushed Build" Is Not an Excuse (2 points).** +The rebuild shipped four constants that were never checked against their +documented limits, which is exactly what produced the false-safe reading. +Pressure explains why the checks were skipped, not why they should be skipped. + +**Criterion 9.2: One Engineering Practice per Failure Area (3 points).** +- Physical limits (Bugs #1 and #3): one shared configuration header plus a + build-time assertion that each compiled limit matches its documented value. +- Banner (Bug #2): remove static banners; a hardware-in-the-loop test that + compares displayed state to the live register. +- Seed integrity (Bug #4): reproducible builds with golden artifact hash + comparison so keys and seeds match the certified specification. +- Image authenticity: enable RP2350 hardware secure boot with OTP hash + verification so a modified image will not run. + +### Grading Rubric (1-to-1 Mapping) + +| Criterion | Points | Full Credit (Answer Key) | Partial Credit | No Credit | +|-----------|--------|--------------------------|----------------|-----------| +| Criterion 9.1: "Rushed Build" Is Not an Excuse | 2 | Specific, grounded reasoning | Generic | Missing | +| Criterion 9.2: One Engineering Practice per Failure Area | 3 | Concrete practices for the bugs and for image authenticity | Names some | Missing | + +### Instructor Notes & Assembly + +- Grade the specificity of the reasoning, not the length of the prose. +- Require concrete practices across the failure areas, including at least one + practice for image authenticity. + +--- + +## How To Breadboard + +- **Raspberry Pi Pico 2** powered over USB. +- **USB-CDC virtual serial console:** open the Pico's COM port at 115200 baud, + 8 data bits, no parity, 1 stop bit. +- **SWD debug probe:** connect SWCLK, SWDIO, GND, and 3.3 V to the Pico debug + header for GDB inspection and register capture. +- No other peripherals are required; the authority LED is on-board. + +--- + +## Complete Grading Summary + +| Task | Title | Points | +|------|-------|--------| +| Task 1 | Setup and Initial Analysis | 12 | +| Task 2 | Find and Patch Bug #1: The Miscalibrated Release Threshold | 15 | +| Task 3 | Find and Patch Bug #2: The False TRACK Banner | 10 | +| Task 4 | Find and Patch Bug #3: The Block Length Constant | 10 | +| Task 5 | Find and Patch Bug #4: The Signal Seed | 15 | +| Task 6 | GDB Register Capture of the Derived Key | 15 | +| Task 7 | Recover the Ouroboros Authority Frame | 10 | +| Task 8 | Export and Verify | 8 | +| Task 9 | Written Reflection | 5 | +| **TOTAL** | | **100** | + +--- + +## Instructor Notes + +Safety: Use only the supplied Pico 2, SWD probe, and firmware. Never connect the +exercise to an operational railway, metro system, public network, military +system, or third-party device. + +### Common Student Mistakes + +- Patching only one threshold site (`0x10000302` or `0x10000312`), leaving one + status line lying. +- Assuming the immediate equals the limit, producing an off-by-one boundary; + the correct byte is `0x3B` (59), not `0x3C` (60). +- Replacing the banner string with a different length, corrupting adjacent + flash; `NORMAL` and `DANGER` are both 6 bytes. +- Treating the block length as an integer and missing the 8-byte double in + `.data`. +- Using the wrong `0.32` bytes and printing `316 M` instead of `320 M`. +- Treating the odd vector address `0x1000015B` as invalid instead of clearing + bit 0 to get `0x1000015A`. +- Starting the seed patch at the wrong offset; the seed is at `0x1000EC70`. + +### Partial Credit Guidelines + +- Award partial credit for one correct threshold site out of two, or for a + correct immediate value without the `<` to `<=` reasoning. +- Award partial credit for a correct banner text with incorrectly documented + bytes, or for partial character-by-character documentation. +- Award partial credit for a correct block-length patch without the IEEE-754 + print math. +- Award partial credit for one of the two GDB argument captures, or for a + partial register override. +- Award no credit for patches that change string length or overwrite adjacent + flash. + +--- + +## Appendix: Expected Binary Diff + +| # | Bug | File Offset(s) | Flash Address(es) | Original Bytes | Patched Bytes | +|---|-----|----------------|-------------------|----------------|---------------| +| 1a | Operator threshold | `0x0302` | `0x10000302` | `5E 2B` | `3B 2B` | +| 1b | Dispatch threshold | `0x0312` | `0x10000312` | `5E 2B` | `3B 2B` | +| 2 | TRACK banner | `0xC4BF` - `0xC4C4` | `0x1000C4BF` - `0x1000C4C4` | `4E 4F 52 4D 41 4C` | `44 41 4E 47 45 52` | +| 3 | Block length | `0xEC60` - `0xEC67` | `0x1000EC60` - `0x1000EC67` | `9A 99 99 99 99 99 09 40` | `7B 14 AE 47 E1 7A D4 3F` | +| 4 | Signal seed | `0xEC70` - `0xEC73` | `0x1000EC70` - `0x1000EC73` | `0A 0A 0A 0A` | `74 65 20 6B` | + +Four defects, five changed regions: two immediate bytes (`0x3B 2B` at each +threshold), six banner bytes, eight block-length bytes, and four seed bytes. diff --git a/WEEK07/0x0017a_ctf/CTF-02-S.pdf b/WEEK07/0x0017a_ctf/CTF-02-S.pdf new file mode 100644 index 0000000..e2c7dc8 Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02-S.pdf differ diff --git a/WEEK07/0x0017a_ctf/CTF-02.bin b/WEEK07/0x0017a_ctf/CTF-02.bin new file mode 100644 index 0000000..b20d1cd Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02.bin differ diff --git a/WEEK07/0x0017a_ctf/CTF-02.uf2 b/WEEK07/0x0017a_ctf/CTF-02.uf2 new file mode 100644 index 0000000..b0a537c Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02.uf2 differ diff --git a/WEEK07/0x0017a_ctf/CTF-02_fixed.bin b/WEEK07/0x0017a_ctf/CTF-02_fixed.bin new file mode 100644 index 0000000..0918eac Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02_fixed.bin differ diff --git a/WEEK07/0x0017a_ctf/CTF-02_fixed.uf2 b/WEEK07/0x0017a_ctf/CTF-02_fixed.uf2 new file mode 100644 index 0000000..830dd27 Binary files /dev/null and b/WEEK07/0x0017a_ctf/CTF-02_fixed.uf2 differ diff --git a/WEEK07/0x0017a_ctf/build/CTF-02.bin b/WEEK07/0x0017a_ctf/build/CTF-02.bin new file mode 100755 index 0000000..ebd4c5a Binary files /dev/null and b/WEEK07/0x0017a_ctf/build/CTF-02.bin differ diff --git a/WEEK07/0x0017a_ctf/build/CTF-02.dis b/WEEK07/0x0017a_ctf/build/CTF-02.dis new file mode 100644 index 0000000..442ca67 --- /dev/null +++ b/WEEK07/0x0017a_ctf/build/CTF-02.dis @@ -0,0 +1,20845 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0017a_ctf/build/CTF-02.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000c40c 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000017b0 1000c410 1000c410 0000d410 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 1000dbc0 1000dbc0 0000ebc0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000020 1000dbc8 1000dbc8 0000ebc8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .psram_load 00000000 11000000 11000000 00011364 2**0 + CONTENTS + 5 .psram_noload 00000000 11000000 11000000 00011364 2**0 + CONTENTS + 6 .xip_ram 00000000 13ffc000 13ffc000 00011364 2**0 + CONTENTS + 7 .ram_vector_table 00000110 20000000 20000000 00012000 2**2 + ALLOC + 8 .uninitialized_data 00000000 20000110 20000110 00011364 2**0 + CONTENTS + 9 .data 00001768 20000110 1000dbe8 0000f110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 10 .tdata 00000000 20001878 20001878 00011364 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 11 .tbss 00000000 20001878 20001878 00000000 2**0 + ALLOC, THREAD_LOCAL + 12 .tbss_space 00000000 20001878 20001878 00011364 2**0 + CONTENTS + 13 .bss 00000ccc 20001878 1000f350 00011878 2**3 + ALLOC + 14 .tls0 00000000 20002544 20002544 00011364 2**0 + CONTENTS + 15 .tls1 00000000 20002544 20002544 00011364 2**0 + CONTENTS + 16 .persistent_data 00000000 20002544 20002544 00011364 2**0 + CONTENTS + 17 .dummy_pre_heap 00000000 20002544 20002544 00011364 2**0 + CONTENTS + 18 .heap 00000800 20002544 20002544 00011544 2**2 + ALLOC, READONLY + 19 .scratch_x 00000000 20080000 20080000 00011364 2**0 + CONTENTS + 20 .scratch_y 00000000 20081000 20081000 00011364 2**0 + CONTENTS + 21 .stack_dummy 00000800 20081000 20081000 00012000 2**5 + ALLOC, READONLY + 22 .flash_end 00000014 1000f350 1000f350 00011350 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 23 .debug_info 00043c37 00000000 00000000 00011364 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_abbrev 0000b146 00000000 00000000 00054f9b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_loclists 000278db 00000000 00000000 000600e1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 26 .debug_aranges 000013f0 00000000 00000000 000879c0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 27 .debug_rnglists 000067b5 00000000 00000000 00088db0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 28 .debug_line 0002dbde 00000000 00000000 0008f565 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 29 .debug_str 0000b27a 00000000 00000000 000bd143 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 30 .comment 00000045 00000000 00000000 000c83bd 2**0 + CONTENTS, READONLY + 31 .ARM.attributes 00000036 00000000 00000000 000c8402 2**0 + CONTENTS, READONLY + 32 .debug_frame 00004268 00000000 00000000 000c8438 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 33 .debug_line_str 000002b2 00000000 00000000 000cc6a0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0017a_ctf/build/CTF-02.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015b .word 0x1000015b +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 1000dbc8 .word 0x1000dbc8 +1000012c: 1000dbe8 .word 0x1000dbe8 +10000130: 1000019c .word 0x1000019c +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 0000f218 .word 0x0000f218 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: 2000 movs r0, #0 + +1000014e <_enter_vtable_in_r0>: +1000014e: 491e ldr r1, [pc, #120] @ (100001c8 ) +10000150: 6008 str r0, [r1, #0] +10000152: c806 ldmia r0!, {r1, r2} +10000154: f381 8808 msr MSP, r1 +10000158: 4710 bx r2 + +1000015a <_reset_handler>: +1000015a: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +1000015e: 6800 ldr r0, [r0, #0] +10000160: b108 cbz r0, 10000166 + +10000162 : +10000162: 2000 movs r0, #0 +10000164: e7f3 b.n 1000014e <_enter_vtable_in_r0> +10000166: a40d add r4, pc, #52 @ (adr r4, 1000019c ) +10000168: cc0e ldmia r4!, {r1, r2, r3} +1000016a: 2900 cmp r1, #0 +1000016c: d002 beq.n 10000174 +1000016e: f000 f812 bl 10000196 +10000172: e7f9 b.n 10000168 +10000174: 4915 ldr r1, [pc, #84] @ (100001cc ) +10000176: 4a16 ldr r2, [pc, #88] @ (100001d0 ) +10000178: 2000 movs r0, #0 +1000017a: e000 b.n 1000017e + +1000017c : +1000017c: c101 stmia r1!, {r0} + +1000017e : +1000017e: 4291 cmp r1, r2 +10000180: d1fc bne.n 1000017c + +10000182 : +10000182: 4914 ldr r1, [pc, #80] @ (100001d4 ) +10000184: 4788 blx r1 +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: be00 bkpt 0x0000 +10000190: e7fd b.n 1000018e + +10000192 : +10000192: c901 ldmia r1!, {r0} +10000194: c201 stmia r2!, {r0} + +10000196 : +10000196: 429a cmp r2, r3 +10000198: d3fb bcc.n 10000192 + +1000019a : +1000019a: 4770 bx lr + +1000019c : +1000019c: 1000dbe8 .word 0x1000dbe8 +100001a0: 20000110 .word 0x20000110 +100001a4: 20001878 .word 0x20001878 +100001a8: 1000f350 .word 0x1000f350 +100001ac: 20080000 .word 0x20080000 +100001b0: 20080000 .word 0x20080000 +100001b4: 1000f350 .word 0x1000f350 +100001b8: 20081000 .word 0x20081000 +100001bc: 20081000 .word 0x20081000 +100001c0: 00000000 .word 0x00000000 +100001c4: 4770 bx lr +100001c6: 0000 .short 0x0000 +100001c8: e000ed08 .word 0xe000ed08 +100001cc: 20001878 .word 0x20001878 +100001d0: 20002544 .word 0x20002544 +100001d4: 100033bd .word 0x100033bd +100001d8: 100002e9 .word 0x100002e9 +100001dc: 100033b5 .word 0x100033b5 + +100001e0 : +100001e0: 4a3f ldr r2, [pc, #252] @ (100002e0 ) +100001e2: 4408 add r0, r1 +100001e4: 4b3f ldr r3, [pc, #252] @ (100002e4 ) +100001e6: 4042 eors r2, r0 +100001e8: eb03 4c32 add.w ip, r3, r2, ror #16 +100001ec: ea81 010c eor.w r1, r1, ip +100001f0: eb00 4331 add.w r3, r0, r1, ror #16 +100001f4: ea83 4032 eor.w r0, r3, r2, ror #16 +100001f8: eb0c 5230 add.w r2, ip, r0, ror #20 +100001fc: ea82 4131 eor.w r1, r2, r1, ror #16 +10000200: eb03 5331 add.w r3, r3, r1, ror #20 +10000204: ea83 5030 eor.w r0, r3, r0, ror #20 +10000208: eb02 6230 add.w r2, r2, r0, ror #24 +1000020c: ea82 5131 eor.w r1, r2, r1, ror #20 +10000210: eb03 6331 add.w r3, r3, r1, ror #24 +10000214: ea83 6030 eor.w r0, r3, r0, ror #24 +10000218: eb02 6270 add.w r2, r2, r0, ror #25 +1000021c: ea82 6131 eor.w r1, r2, r1, ror #24 +10000220: eb03 6371 add.w r3, r3, r1, ror #25 +10000224: ea83 6070 eor.w r0, r3, r0, ror #25 +10000228: eb02 4230 add.w r2, r2, r0, ror #16 +1000022c: ea82 6171 eor.w r1, r2, r1, ror #25 +10000230: eb03 4331 add.w r3, r3, r1, ror #16 +10000234: ea83 4030 eor.w r0, r3, r0, ror #16 +10000238: eb02 5230 add.w r2, r2, r0, ror #20 +1000023c: ea82 4131 eor.w r1, r2, r1, ror #16 +10000240: eb03 5331 add.w r3, r3, r1, ror #20 +10000244: ea83 5030 eor.w r0, r3, r0, ror #20 +10000248: eb02 6230 add.w r2, r2, r0, ror #24 +1000024c: ea82 5131 eor.w r1, r2, r1, ror #20 +10000250: eb03 6331 add.w r3, r3, r1, ror #24 +10000254: ea83 6030 eor.w r0, r3, r0, ror #24 +10000258: eb02 6270 add.w r2, r2, r0, ror #25 +1000025c: ea82 6131 eor.w r1, r2, r1, ror #24 +10000260: eb03 6371 add.w r3, r3, r1, ror #25 +10000264: ea83 6070 eor.w r0, r3, r0, ror #25 +10000268: eb02 4230 add.w r2, r2, r0, ror #16 +1000026c: ea82 6171 eor.w r1, r2, r1, ror #25 +10000270: eb03 4331 add.w r3, r3, r1, ror #16 +10000274: ea83 4030 eor.w r0, r3, r0, ror #16 +10000278: eb02 5230 add.w r2, r2, r0, ror #20 +1000027c: ea82 4131 eor.w r1, r2, r1, ror #16 +10000280: eb03 5331 add.w r3, r3, r1, ror #20 +10000284: ea83 5030 eor.w r0, r3, r0, ror #20 +10000288: eb02 6230 add.w r2, r2, r0, ror #24 +1000028c: ea82 5131 eor.w r1, r2, r1, ror #20 +10000290: eb03 6331 add.w r3, r3, r1, ror #24 +10000294: ea83 6030 eor.w r0, r3, r0, ror #24 +10000298: eb02 6270 add.w r2, r2, r0, ror #25 +1000029c: ea82 6131 eor.w r1, r2, r1, ror #24 +100002a0: eb03 6371 add.w r3, r3, r1, ror #25 +100002a4: ea83 6070 eor.w r0, r3, r0, ror #25 +100002a8: eb02 4230 add.w r2, r2, r0, ror #16 +100002ac: ea82 6171 eor.w r1, r2, r1, ror #25 +100002b0: eb03 4331 add.w r3, r3, r1, ror #16 +100002b4: ea83 4030 eor.w r0, r3, r0, ror #16 +100002b8: eb02 5230 add.w r2, r2, r0, ror #20 +100002bc: ea82 4131 eor.w r1, r2, r1, ror #16 +100002c0: eb03 5331 add.w r3, r3, r1, ror #20 +100002c4: ea83 5030 eor.w r0, r3, r0, ror #20 +100002c8: eb02 6230 add.w r2, r2, r0, ror #24 +100002cc: ea82 5231 eor.w r2, r2, r1, ror #20 +100002d0: eb03 6332 add.w r3, r3, r2, ror #24 +100002d4: ea83 6030 eor.w r0, r3, r0, ror #24 +100002d8: ea83 6070 eor.w r0, r3, r0, ror #25 +100002dc: 4770 bx lr +100002de: bf00 nop +100002e0: 3320646e .word 0x3320646e +100002e4: 61707865 .word 0x61707865 + +100002e8
: +100002e8: e92d 4880 stmdb sp!, {r7, fp, lr} +100002ec: b083 sub sp, #12 +100002ee: f003 f9d1 bl 10003694 +100002f2: f005 fca3 bl 10005c3c +100002f6: 4a62 ldr r2, [pc, #392] @ (10000480 ) +100002f8: f8df a1f8 ldr.w sl, [pc, #504] @ 100004f4 +100002fc: 6813 ldr r3, [r2, #0] +100002fe: f8df 91f8 ldr.w r9, [pc, #504] @ 100004f8 +10000302: 2b5e cmp r3, #94 @ 0x5e +10000304: bf8c ite hi +10000306: 2300 movhi r3, #0 +10000308: 2301 movls r3, #1 +1000030a: f8ca 3000 str.w r3, [sl] +1000030e: 6813 ldr r3, [r2, #0] +10000310: 485c ldr r0, [pc, #368] @ (10000484 ) +10000312: 2b5e cmp r3, #94 @ 0x5e +10000314: bf8c ite hi +10000316: 2300 movhi r3, #0 +10000318: 2301 movls r3, #1 +1000031a: f8c9 3000 str.w r3, [r9] +1000031e: f003 fa43 bl 100037a8 <__wrap_puts> +10000322: 4859 ldr r0, [pc, #356] @ (10000488 ) +10000324: f003 fa40 bl 100037a8 <__wrap_puts> +10000328: 4858 ldr r0, [pc, #352] @ (1000048c ) +1000032a: f003 fa3d bl 100037a8 <__wrap_puts> +1000032e: 4858 ldr r0, [pc, #352] @ (10000490 ) +10000330: f003 fa3a bl 100037a8 <__wrap_puts> +10000334: 2100 movs r1, #0 +10000336: 4857 ldr r0, [pc, #348] @ (10000494 ) +10000338: f7ff ff52 bl 100001e0 +1000033c: 4e56 ldr r6, [pc, #344] @ (10000498 ) +1000033e: 4d57 ldr r5, [pc, #348] @ (1000049c ) +10000340: 4c57 ldr r4, [pc, #348] @ (100004a0 ) +10000342: f8df 8194 ldr.w r8, [pc, #404] @ 100004d8 +10000346: f8df b1b4 ldr.w fp, [pc, #436] @ 100004fc +1000034a: 9001 str r0, [sp, #4] +1000034c: 4b55 ldr r3, [pc, #340] @ (100004a4 ) +1000034e: 9901 ldr r1, [sp, #4] +10000350: 6818 ldr r0, [r3, #0] +10000352: f7ff ff45 bl 100001e0 +10000356: 4954 ldr r1, [pc, #336] @ (100004a8 ) +10000358: 4b54 ldr r3, [pc, #336] @ (100004ac ) +1000035a: 2200 movs r2, #0 +1000035c: 6030 str r0, [r6, #0] +1000035e: e9d1 0100 ldrd r0, r1, [r1] +10000362: f001 fb51 bl 10001a08 <__wrap___aeabi_dmul> +10000366: f001 fbf7 bl 10001b58 <__wrap___aeabi_d2uiz> +1000036a: 682b ldr r3, [r5, #0] +1000036c: 4607 mov r7, r0 +1000036e: 3301 adds r3, #1 +10000370: 602b str r3, [r5, #0] +10000372: f8da 3000 ldr.w r3, [sl] +10000376: 2b00 cmp r3, #0 +10000378: d06a beq.n 10000450 +1000037a: 494d ldr r1, [pc, #308] @ (100004b0 ) +1000037c: 484d ldr r0, [pc, #308] @ (100004b4 ) +1000037e: f003 fa91 bl 100038a4 <__wrap_printf> +10000382: f8d9 3000 ldr.w r3, [r9] +10000386: 2b00 cmp r3, #0 +10000388: d06a beq.n 10000460 +1000038a: 494b ldr r1, [pc, #300] @ (100004b8 ) +1000038c: 484b ldr r0, [pc, #300] @ (100004bc ) +1000038e: f003 fa89 bl 100038a4 <__wrap_printf> +10000392: 4639 mov r1, r7 +10000394: 484a ldr r0, [pc, #296] @ (100004c0 ) +10000396: f003 fa85 bl 100038a4 <__wrap_printf> +1000039a: 6829 ldr r1, [r5, #0] +1000039c: 4849 ldr r0, [pc, #292] @ (100004c4 ) +1000039e: f003 fa81 bl 100038a4 <__wrap_printf> +100003a2: 6831 ldr r1, [r6, #0] +100003a4: 4848 ldr r0, [pc, #288] @ (100004c8 ) +100003a6: 4559 cmp r1, fp +100003a8: bf0c ite eq +100003aa: 4a48 ldreq r2, [pc, #288] @ (100004cc ) +100003ac: 4a48 ldrne r2, [pc, #288] @ (100004d0 ) +100003ae: f003 fa79 bl 100038a4 <__wrap_printf> +100003b2: 4848 ldr r0, [pc, #288] @ (100004d4 ) +100003b4: f003 fa76 bl 100038a4 <__wrap_printf> +100003b8: 2000 movs r0, #0 +100003ba: f003 f96d bl 10003698 +100003be: 280d cmp r0, #13 +100003c0: dc0e bgt.n 100003e0 +100003c2: 1c83 adds r3, r0, #2 +100003c4: db0e blt.n 100003e4 +100003c6: 1c83 adds r3, r0, #2 +100003c8: 2b0f cmp r3, #15 +100003ca: d80b bhi.n 100003e4 +100003cc: e8df f003 tbb [pc, r3] +100003d0: 0a0a0a3b .word 0x0a0a0a3b +100003d4: 0a0a0a0a .word 0x0a0a0a0a +100003d8: 0a320a0a .word 0x0a320a0a +100003dc: 190a0a19 .word 0x190a0a19 +100003e0: 287f cmp r0, #127 @ 0x7f +100003e2: d027 beq.n 10000434 +100003e4: 6822 ldr r2, [r4, #0] +100003e6: 1c53 adds r3, r2, #1 +100003e8: f5b3 7f00 cmp.w r3, #512 @ 0x200 +100003ec: d205 bcs.n 100003fa +100003ee: f808 0002 strb.w r0, [r8, r2] +100003f2: b2c0 uxtb r0, r0 +100003f4: 6023 str r3, [r4, #0] +100003f6: f003 f8f7 bl 100035e8 +100003fa: 2000 movs r0, #0 +100003fc: f003 f94c bl 10003698 +10000400: e7dd b.n 100003be +10000402: 2700 movs r7, #0 +10000404: 200d movs r0, #13 +10000406: f003 f8ef bl 100035e8 +1000040a: 200a movs r0, #10 +1000040c: f003 f8ec bl 100035e8 +10000410: 6821 ldr r1, [r4, #0] +10000412: 4831 ldr r0, [pc, #196] @ (100004d8 ) +10000414: f808 7001 strb.w r7, [r8, r1] +10000418: f005 fc22 bl 10005c60 +1000041c: 2801 cmp r0, #1 +1000041e: d028 beq.n 10000472 +10000420: bb00 cbnz r0, 10000464 +10000422: 482e ldr r0, [pc, #184] @ (100004dc ) +10000424: f003 f9c0 bl 100037a8 <__wrap_puts> +10000428: 2300 movs r3, #0 +1000042a: 482a ldr r0, [pc, #168] @ (100004d4 ) +1000042c: 6023 str r3, [r4, #0] +1000042e: f003 fa39 bl 100038a4 <__wrap_printf> +10000432: e7e2 b.n 100003fa +10000434: 6823 ldr r3, [r4, #0] +10000436: 2b00 cmp r3, #0 +10000438: d0df beq.n 100003fa +1000043a: 3b01 subs r3, #1 +1000043c: 4828 ldr r0, [pc, #160] @ (100004e0 ) +1000043e: 6023 str r3, [r4, #0] +10000440: f003 fa30 bl 100038a4 <__wrap_printf> +10000444: e7d9 b.n 100003fa +10000446: f44f 60fa mov.w r0, #2000 @ 0x7d0 +1000044a: f000 feaf bl 100011ac +1000044e: e77d b.n 1000034c +10000450: 4924 ldr r1, [pc, #144] @ (100004e4 ) +10000452: 4818 ldr r0, [pc, #96] @ (100004b4 ) +10000454: f003 fa26 bl 100038a4 <__wrap_printf> +10000458: f8d9 3000 ldr.w r3, [r9] +1000045c: 2b00 cmp r3, #0 +1000045e: d194 bne.n 1000038a +10000460: 4921 ldr r1, [pc, #132] @ (100004e8 ) +10000462: e793 b.n 1000038c +10000464: 2319 movs r3, #25 +10000466: ec47 3040 gpioc_bit_out_put r3, r7 +1000046a: 4820 ldr r0, [pc, #128] @ (100004ec ) +1000046c: f003 f99c bl 100037a8 <__wrap_puts> +10000470: e7da b.n 10000428 +10000472: 2319 movs r3, #25 +10000474: ec47 3040 gpioc_bit_out_put r3, r7 +10000478: 481d ldr r0, [pc, #116] @ (100004f0 ) +1000047a: f003 f995 bl 100037a8 <__wrap_puts> +1000047e: e7d3 b.n 10000428 +10000480: 2000119c .word 0x2000119c +10000484: 1000c448 .word 0x1000c448 +10000488: 1000c464 .word 0x1000c464 +1000048c: 1000c488 .word 0x1000c488 +10000490: 1000c4b8 .word 0x1000c4b8 +10000494: 6b206574 .word 0x6b206574 +10000498: 200020dc .word 0x200020dc +1000049c: 20001ed0 .word 0x20001ed0 +100004a0: 200020d4 .word 0x200020d4 +100004a4: 20001198 .word 0x20001198 +100004a8: 20001188 .word 0x20001188 +100004ac: 408f4000 .word 0x408f4000 +100004b0: 1000c410 .word 0x1000c410 +100004b4: 1000c4c8 .word 0x1000c4c8 +100004b8: 1000c424 .word 0x1000c424 +100004bc: 1000c4dc .word 0x1000c4dc +100004c0: 1000c4f0 .word 0x1000c4f0 +100004c4: 1000c508 .word 0x1000c508 +100004c8: 1000c51c .word 0x1000c51c +100004cc: 1000c438 .word 0x1000c438 +100004d0: 1000c43c .word 0x1000c43c +100004d4: 1000c534 .word 0x1000c534 +100004d8: 20001ed4 .word 0x20001ed4 +100004dc: 1000c57c .word 0x1000c57c +100004e0: 1000c540 .word 0x1000c540 +100004e4: 1000c418 .word 0x1000c418 +100004e8: 1000c430 .word 0x1000c430 +100004ec: 1000c598 .word 0x1000c598 +100004f0: 1000c544 .word 0x1000c544 +100004f4: 200020d8 .word 0x200020d8 +100004f8: 20001ecc .word 0x20001ecc +100004fc: 2d879291 .word 0x2d879291 + +10000500 : +10000500: f04f 0300 mov.w r3, #0 +10000504: b500 push {lr} +10000506: ec43 0044 gpioc_bit_oe_put r0, r3 +1000050a: ec43 0040 gpioc_bit_out_put r0, r3 +1000050e: f04f 0e05 mov.w lr, #5 +10000512: f44f 7c80 mov.w ip, #256 @ 0x100 +10000516: 4b0c ldr r3, [pc, #48] @ (10000548 ) +10000518: 00c2 lsls r2, r0, #3 +1000051a: f853 1020 ldr.w r1, [r3, r0, lsl #2] +1000051e: eb03 0080 add.w r0, r3, r0, lsl #2 +10000522: f081 0140 eor.w r1, r1, #64 @ 0x40 +10000526: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +1000052a: f503 3320 add.w r3, r3, #163840 @ 0x28000 +1000052e: f001 02c0 and.w r2, r1, #192 @ 0xc0 +10000532: f500 5180 add.w r1, r0, #4096 @ 0x1000 +10000536: f500 5040 add.w r0, r0, #12288 @ 0x3000 +1000053a: 600a str r2, [r1, #0] +1000053c: f8c3 e004 str.w lr, [r3, #4] +10000540: f8c0 c000 str.w ip, [r0] +10000544: bd00 pop {pc} +10000546: bf00 nop +10000548: 40038004 .word 0x40038004 + +1000054c : +1000054c: b40f push {r0, r1, r2, r3} +1000054e: b500 push {lr} +10000550: 4808 ldr r0, [pc, #32] @ (10000574 ) +10000552: b083 sub sp, #12 +10000554: f003 f928 bl 100037a8 <__wrap_puts> +10000558: 9b04 ldr r3, [sp, #16] +1000055a: b13b cbz r3, 1000056c +1000055c: a905 add r1, sp, #20 +1000055e: 4618 mov r0, r3 +10000560: 9101 str r1, [sp, #4] +10000562: f002 fef5 bl 10003350 +10000566: 4804 ldr r0, [pc, #16] @ (10000578 ) +10000568: f003 f91e bl 100037a8 <__wrap_puts> +1000056c: 2001 movs r0, #1 +1000056e: f002 ff07 bl 10003380 <_exit> +10000572: bf00 nop +10000574: 1000c5b0 .word 0x1000c5b0 +10000578: 1000c504 .word 0x1000c504 + +1000057c : +1000057c: b570 push {r4, r5, r6, lr} +1000057e: 4616 mov r6, r2 +10000580: f3ef 8410 mrs r4, PRIMASK +10000584: b672 cpsid i +10000586: f8df e048 ldr.w lr, [pc, #72] @ 100005d0 +1000058a: e8de 2fcf ldaexb r2, [lr] +1000058e: 2301 movs r3, #1 +10000590: 2a00 cmp r2, #0 +10000592: d1fa bne.n 1000058a +10000594: e8ce 3f42 strexb r2, r3, [lr] +10000598: 2a00 cmp r2, #0 +1000059a: d1f6 bne.n 1000058a +1000059c: f3bf 8f5f dmb sy +100005a0: 2301 movs r3, #1 +100005a2: f001 0c07 and.w ip, r1, #7 +100005a6: 08ca lsrs r2, r1, #3 +100005a8: fa03 f30c lsl.w r3, r3, ip +100005ac: f810 c002 ldrb.w ip, [r0, r2] +100005b0: ea1c 0503 ands.w r5, ip, r3 +100005b4: d108 bne.n 100005c8 +100005b6: ea4c 0c03 orr.w ip, ip, r3 +100005ba: f800 c002 strb.w ip, [r0, r2] +100005be: e8ce 5f8f stlb r5, [lr] +100005c2: f384 8810 msr PRIMASK, r4 +100005c6: bd70 pop {r4, r5, r6, pc} +100005c8: 4630 mov r0, r6 +100005ca: f7ff ffbf bl 1000054c +100005ce: bf00 nop +100005d0: 20001d1f .word 0x20001d1f + +100005d4 : +100005d4: b5f8 push {r3, r4, r5, r6, r7, lr} +100005d6: 460f mov r7, r1 +100005d8: 4619 mov r1, r3 +100005da: f3ef 8610 mrs r6, PRIMASK +100005de: b672 cpsid i +100005e0: 4d1c ldr r5, [pc, #112] @ (10000654 ) +100005e2: e8d5 4fcf ldaexb r4, [r5] +100005e6: 2301 movs r3, #1 +100005e8: 2c00 cmp r4, #0 +100005ea: d1fa bne.n 100005e2 +100005ec: e8c5 3f44 strexb r4, r3, [r5] +100005f0: 2c00 cmp r4, #0 +100005f2: d1f6 bne.n 100005e2 +100005f4: f3bf 8f5f dmb sy +100005f8: 428a cmp r2, r1 +100005fa: d81b bhi.n 10000634 +100005fc: 2401 movs r4, #1 +100005fe: e002 b.n 10000606 +10000600: 3201 adds r2, #1 +10000602: 4291 cmp r1, r2 +10000604: d322 bcc.n 1000064c +10000606: 08d3 lsrs r3, r2, #3 +10000608: f810 e003 ldrb.w lr, [r0, r3] +1000060c: f002 0c07 and.w ip, r2, #7 +10000610: fa04 fc0c lsl.w ip, r4, ip +10000614: ea1e 0f0c tst.w lr, ip +10000618: d1f2 bne.n 10000600 +1000061a: ea4e 0e0c orr.w lr, lr, ip +1000061e: f800 e003 strb.w lr, [r0, r3] +10000622: 4610 mov r0, r2 +10000624: 2300 movs r3, #0 +10000626: e8c5 3f8f stlb r3, [r5] +1000062a: f386 8810 msr PRIMASK, r6 +1000062e: 4298 cmp r0, r3 +10000630: db07 blt.n 10000642 +10000632: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000634: 2300 movs r3, #0 +10000636: e8c5 3f8f stlb r3, [r5] +1000063a: f386 8810 msr PRIMASK, r6 +1000063e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000642: 2f00 cmp r7, #0 +10000644: d0f5 beq.n 10000632 +10000646: 9806 ldr r0, [sp, #24] +10000648: f7ff ff80 bl 1000054c +1000064c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000650: e7e8 b.n 10000624 +10000652: bf00 nop +10000654: 20001d1f .word 0x20001d1f + +10000658 : +10000658: 4a04 ldr r2, [pc, #16] @ (1000066c ) +1000065a: 7810 ldrb r0, [r2, #0] +1000065c: 1c43 adds r3, r0, #1 +1000065e: b2db uxtb r3, r3 +10000660: 2b18 cmp r3, #24 +10000662: bf28 it cs +10000664: 2310 movcs r3, #16 +10000666: 7013 strb r3, [r2, #0] +10000668: 4770 bx lr +1000066a: bf00 nop +1000066c: 200011a0 .word 0x200011a0 + +10000670 : +10000670: b500 push {lr} +10000672: f8df c01c ldr.w ip, [pc, #28] @ 10000690 +10000676: b083 sub sp, #12 +10000678: 4601 mov r1, r0 +1000067a: 231f movs r3, #31 +1000067c: 2218 movs r2, #24 +1000067e: f8cd c000 str.w ip, [sp] +10000682: 4802 ldr r0, [pc, #8] @ (1000068c ) +10000684: f7ff ffa6 bl 100005d4 +10000688: b003 add sp, #12 +1000068a: bd00 pop {pc} +1000068c: 20001e64 .word 0x20001e64 +10000690: 1000c5c0 .word 0x1000c5c0 + +10000694 : +10000694: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000698: 6893 ldr r3, [r2, #8] +1000069a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000069e: 6093 str r3, [r2, #8] +100006a0: 4770 bx lr +100006a2: bf00 nop + +100006a4 : +100006a4: 2100 movs r1, #0 +100006a6: 4b04 ldr r3, [pc, #16] @ (100006b8 ) +100006a8: f103 0220 add.w r2, r3, #32 +100006ac: e8c3 1f8f stlb r1, [r3] +100006b0: 3301 adds r3, #1 +100006b2: 4293 cmp r3, r2 +100006b4: d1fa bne.n 100006ac +100006b6: 4770 bx lr +100006b8: 20001d14 .word 0x20001d14 + +100006bc : +100006bc: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100006c0: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100006c4: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100006c8: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100006cc: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100006d0: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100006d4: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100006d8: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100006dc: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +100006e0: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100006e4: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100006e8: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100006ec: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100006f0: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100006f4: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100006f8: b662 cpsie i +100006fa: 4770 bx lr + +100006fc : +100006fc: 2301 movs r3, #1 +100006fe: f000 021f and.w r2, r0, #31 +10000702: 4093 lsls r3, r2 +10000704: 0940 lsrs r0, r0, #5 +10000706: b141 cbz r1, 1000071a +10000708: 0080 lsls r0, r0, #2 +1000070a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000070e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000712: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000716: 6003 str r3, [r0, #0] +10000718: 4770 bx lr +1000071a: 4a02 ldr r2, [pc, #8] @ (10000724 ) +1000071c: 3020 adds r0, #32 +1000071e: f842 3020 str.w r3, [r2, r0, lsl #2] +10000722: 4770 bx lr +10000724: e000e100 .word 0xe000e100 + +10000728 : +10000728: 2301 movs r3, #1 +1000072a: 4a06 ldr r2, [pc, #24] @ (10000744 ) +1000072c: 0941 lsrs r1, r0, #5 +1000072e: f852 2021 ldr.w r2, [r2, r1, lsl #2] +10000732: f000 001f and.w r0, r0, #31 +10000736: 4083 lsls r3, r0 +10000738: 4213 tst r3, r2 +1000073a: bf14 ite ne +1000073c: 2001 movne r0, #1 +1000073e: 2000 moveq r0, #0 +10000740: 4770 bx lr +10000742: bf00 nop +10000744: e000e100 .word 0xe000e100 + +10000748 : +10000748: 2201 movs r2, #1 +1000074a: 0943 lsrs r3, r0, #5 +1000074c: 4903 ldr r1, [pc, #12] @ (1000075c ) +1000074e: f000 001f and.w r0, r0, #31 +10000752: 4082 lsls r2, r0 +10000754: 3340 adds r3, #64 @ 0x40 +10000756: f841 2023 str.w r2, [r1, r3, lsl #2] +1000075a: 4770 bx lr +1000075c: e000e100 .word 0xe000e100 + +10000760 : +10000760: 4a05 ldr r2, [pc, #20] @ (10000778 ) +10000762: 3010 adds r0, #16 +10000764: 6892 ldr r2, [r2, #8] +10000766: 4b05 ldr r3, [pc, #20] @ (1000077c ) +10000768: f852 0020 ldr.w r0, [r2, r0, lsl #2] +1000076c: 1ac0 subs r0, r0, r3 +1000076e: 2847 cmp r0, #71 @ 0x47 +10000770: bf8c ite hi +10000772: 2000 movhi r0, #0 +10000774: 2001 movls r0, #1 +10000776: 4770 bx lr +10000778: e000ed00 .word 0xe000ed00 +1000077c: 200011a4 .word 0x200011a4 + +10000780 : +10000780: b508 push {r3, lr} +10000782: f3ef 8e10 mrs lr, PRIMASK +10000786: b672 cpsid i +10000788: 4b13 ldr r3, [pc, #76] @ (100007d8 ) +1000078a: e8d3 cfcf ldaexb ip, [r3] +1000078e: 2201 movs r2, #1 +10000790: f1bc 0f00 cmp.w ip, #0 +10000794: d1f9 bne.n 1000078a +10000796: e8c3 2f4c strexb ip, r2, [r3] +1000079a: f1bc 0f00 cmp.w ip, #0 +1000079e: d1f4 bne.n 1000078a +100007a0: f3bf 8f5f dmb sy +100007a4: 4a0d ldr r2, [pc, #52] @ (100007dc ) +100007a6: 3010 adds r0, #16 +100007a8: 6892 ldr r2, [r2, #8] +100007aa: f8df c034 ldr.w ip, [pc, #52] @ 100007e0 +100007ae: f852 2020 ldr.w r2, [r2, r0, lsl #2] +100007b2: 4562 cmp r2, ip +100007b4: d001 beq.n 100007ba +100007b6: 4291 cmp r1, r2 +100007b8: d10b bne.n 100007d2 +100007ba: 4a08 ldr r2, [pc, #32] @ (100007dc ) +100007bc: 6892 ldr r2, [r2, #8] +100007be: f842 1020 str.w r1, [r2, r0, lsl #2] +100007c2: f3bf 8f5f dmb sy +100007c6: 2200 movs r2, #0 +100007c8: e8c3 2f8f stlb r2, [r3] +100007cc: f38e 8810 msr PRIMASK, lr +100007d0: bd08 pop {r3, pc} +100007d2: f000 ffbf bl 10001754 +100007d6: bf00 nop +100007d8: 20001d1d .word 0x20001d1d +100007dc: e000ed00 .word 0xe000ed00 +100007e0: 10000111 .word 0x10000111 + +100007e4 : +100007e4: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +100007e8: 468b mov fp, r1 +100007ea: 4611 mov r1, r2 +100007ec: f3ef 8810 mrs r8, PRIMASK +100007f0: b672 cpsid i +100007f2: 4f66 ldr r7, [pc, #408] @ (1000098c ) +100007f4: e8d7 2fcf ldaexb r2, [r7] +100007f8: 2301 movs r3, #1 +100007fa: 2a00 cmp r2, #0 +100007fc: d1fa bne.n 100007f4 +100007fe: e8c7 3f42 strexb r2, r3, [r7] +10000802: 2a00 cmp r2, #0 +10000804: d1f6 bne.n 100007f4 +10000806: f3bf 8f5f dmb sy +1000080a: 4b61 ldr r3, [pc, #388] @ (10000990 ) +1000080c: f993 4000 ldrsb.w r4, [r3] +10000810: 2c00 cmp r4, #0 +10000812: f2c0 80b8 blt.w 10000986 +10000816: f100 0510 add.w r5, r0, #16 +1000081a: 485e ldr r0, [pc, #376] @ (10000994 ) +1000081c: eb04 0944 add.w r9, r4, r4, lsl #1 +10000820: eb00 0289 add.w r2, r0, r9, lsl #2 +10000824: 7996 ldrb r6, [r2, #6] +10000826: ea4f 0989 mov.w r9, r9, lsl #2 +1000082a: 701e strb r6, [r3, #0] +1000082c: 4b5a ldr r3, [pc, #360] @ (10000998 ) +1000082e: 689b ldr r3, [r3, #8] +10000830: f853 6025 ldr.w r6, [r3, r5, lsl #2] +10000834: 1a33 subs r3, r6, r0 +10000836: 2b47 cmp r3, #71 @ 0x47 +10000838: d835 bhi.n 100008a6 +1000083a: f026 0e01 bic.w lr, r6, #1 +1000083e: f89e 3007 ldrb.w r3, [lr, #7] +10000842: 428b cmp r3, r1 +10000844: d809 bhi.n 1000085a +10000846: e06f b.n 10000928 +10000848: eb0c 034c add.w r3, ip, ip, lsl #1 +1000084c: eb00 0383 add.w r3, r0, r3, lsl #2 +10000850: f893 a007 ldrb.w sl, [r3, #7] +10000854: 458a cmp sl, r1 +10000856: d951 bls.n 100008fc +10000858: 469e mov lr, r3 +1000085a: f99e c006 ldrsb.w ip, [lr, #6] +1000085e: f1bc 0f00 cmp.w ip, #0 +10000862: daf1 bge.n 10000848 +10000864: f64b 5901 movw r9, #48385 @ 0xbd01 +10000868: f10e 0a04 add.w sl, lr, #4 +1000086c: 1f13 subs r3, r2, #4 +1000086e: eba3 030a sub.w r3, r3, sl +10000872: f3c3 034a ubfx r3, r3, #1, #11 +10000876: ea6f 43c3 mvn.w r3, r3, lsl #19 +1000087a: ea6f 43d3 mvn.w r3, r3, lsr #19 +1000087e: f88e 4006 strb.w r4, [lr, #6] +10000882: f8df a120 ldr.w sl, [pc, #288] @ 100009a4 +10000886: eb04 0444 add.w r4, r4, r4, lsl #1 +1000088a: eb00 0284 add.w r2, r0, r4, lsl #2 +1000088e: f8ae 3004 strh.w r3, [lr, #4] +10000892: f840 a024 str.w sl, [r0, r4, lsl #2] +10000896: f8a2 9004 strh.w r9, [r2, #4] +1000089a: f882 c006 strb.w ip, [r2, #6] +1000089e: 71d1 strb r1, [r2, #7] +100008a0: f8c2 b008 str.w fp, [r2, #8] +100008a4: e01d b.n 100008e2 +100008a6: 4b3d ldr r3, [pc, #244] @ (1000099c ) +100008a8: 429e cmp r6, r3 +100008aa: d16c bne.n 10000986 +100008ac: 4b3c ldr r3, [pc, #240] @ (100009a0 ) +100008ae: 71d1 strb r1, [r2, #7] +100008b0: f109 0102 add.w r1, r9, #2 +100008b4: 4401 add r1, r0 +100008b6: 3b04 subs r3, #4 +100008b8: 1a5b subs r3, r3, r1 +100008ba: f3c3 034a ubfx r3, r3, #1, #11 +100008be: ea6f 43c3 mvn.w r3, r3, lsl #19 +100008c2: f44f 4121 mov.w r1, #41216 @ 0xa100 +100008c6: ea6f 43d3 mvn.w r3, r3, lsr #19 +100008ca: f820 1009 strh.w r1, [r0, r9] +100008ce: 8053 strh r3, [r2, #2] +100008d0: 21ff movs r1, #255 @ 0xff +100008d2: f64b 5301 movw r3, #48385 @ 0xbd01 +100008d6: f8c2 b008 str.w fp, [r2, #8] +100008da: 7191 strb r1, [r2, #6] +100008dc: 8093 strh r3, [r2, #4] +100008de: f042 0601 orr.w r6, r2, #1 +100008e2: 4b2d ldr r3, [pc, #180] @ (10000998 ) +100008e4: 689b ldr r3, [r3, #8] +100008e6: f843 6025 str.w r6, [r3, r5, lsl #2] +100008ea: f3bf 8f5f dmb sy +100008ee: 2300 movs r3, #0 +100008f0: e8c7 3f8f stlb r3, [r7] +100008f4: f388 8810 msr PRIMASK, r8 +100008f8: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} +100008fc: 46f2 mov sl, lr +100008fe: f06f 0307 mvn.w r3, #7 +10000902: eba3 0309 sub.w r3, r3, r9 +10000906: f83a 9f04 ldrh.w r9, [sl, #4]! +1000090a: 1a1b subs r3, r3, r0 +1000090c: f349 090a sbfx r9, r9, #0, #11 +10000910: f109 0902 add.w r9, r9, #2 +10000914: eb0a 0949 add.w r9, sl, r9, lsl #1 +10000918: 4499 add r9, r3 +1000091a: f3c9 094a ubfx r9, r9, #1, #11 +1000091e: ea6f 49c9 mvn.w r9, r9, lsl #19 +10000922: ea6f 49d9 mvn.w r9, r9, lsr #19 +10000926: e7a1 b.n 1000086c +10000928: f06f 0307 mvn.w r3, #7 +1000092c: 71d1 strb r1, [r2, #7] +1000092e: 491c ldr r1, [pc, #112] @ (100009a0 ) +10000930: f109 0402 add.w r4, r9, #2 +10000934: 4404 add r4, r0 +10000936: 3904 subs r1, #4 +10000938: 1b09 subs r1, r1, r4 +1000093a: eba3 0309 sub.w r3, r3, r9 +1000093e: f3c1 014a ubfx r1, r1, #1, #11 +10000942: 1a1b subs r3, r3, r0 +10000944: ea6f 41c1 mvn.w r1, r1, lsl #19 +10000948: 4473 add r3, lr +1000094a: f3c3 034a ubfx r3, r3, #1, #11 +1000094e: ea6f 43c3 mvn.w r3, r3, lsl #19 +10000952: ea6f 41d1 mvn.w r1, r1, lsr #19 +10000956: f44f 4621 mov.w r6, #41216 @ 0xa100 +1000095a: ea6f 43d3 mvn.w r3, r3, lsr #19 +1000095e: 8051 strh r1, [r2, #2] +10000960: 4910 ldr r1, [pc, #64] @ (100009a4 ) +10000962: f820 6009 strh.w r6, [r0, r9] +10000966: 8093 strh r3, [r2, #4] +10000968: f64a 24aa movw r4, #43690 @ 0xaaaa +1000096c: 4673 mov r3, lr +1000096e: 1a1b subs r3, r3, r0 +10000970: 415b adcs r3, r3 +10000972: 435c muls r4, r3 +10000974: 0d24 lsrs r4, r4, #20 +10000976: f8c2 b008 str.w fp, [r2, #8] +1000097a: 7194 strb r4, [r2, #6] +1000097c: f042 0601 orr.w r6, r2, #1 +10000980: f8ce 1000 str.w r1, [lr] +10000984: e7ad b.n 100008e2 +10000986: f000 fee5 bl 10001754 +1000098a: bf00 nop +1000098c: 20001d1d .word 0x20001d1d +10000990: 2000253d .word 0x2000253d +10000994: 200011a4 .word 0x200011a4 +10000998: e000ed00 .word 0xe000ed00 +1000099c: 10000111 .word 0x10000111 +100009a0: 200011ec .word 0x200011ec +100009a4: 47804801 .word 0x47804801 + +100009a8 : +100009a8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100009ac: f3ef 8305 mrs r3, IPSR +100009b0: b2db uxtb r3, r3 +100009b2: 469e mov lr, r3 +100009b4: f3ef 8510 mrs r5, PRIMASK +100009b8: b672 cpsid i +100009ba: 492f ldr r1, [pc, #188] @ (10000a78 ) +100009bc: e8d1 2fcf ldaexb r2, [r1] +100009c0: 2301 movs r3, #1 +100009c2: 2a00 cmp r2, #0 +100009c4: d1fa bne.n 100009bc +100009c6: e8c1 3f42 strexb r2, r3, [r1] +100009ca: 2a00 cmp r2, #0 +100009cc: d1f6 bne.n 100009bc +100009ce: f3bf 8f5f dmb sy +100009d2: f8df 80b4 ldr.w r8, [pc, #180] @ 10000a88 +100009d6: f040 0601 orr.w r6, r0, #1 +100009da: f8d8 7008 ldr.w r7, [r8, #8] +100009de: f64a 23aa movw r3, #43690 @ 0xaaaa +100009e2: f857 702e ldr.w r7, [r7, lr, lsl #2] +100009e6: 4604 mov r4, r0 +100009e8: 4a24 ldr r2, [pc, #144] @ (10000a7c ) +100009ea: 1aa4 subs r4, r4, r2 +100009ec: 4164 adcs r4, r4 +100009ee: 4363 muls r3, r4 +100009f0: 0d1b lsrs r3, r3, #20 +100009f2: 42b7 cmp r7, r6 +100009f4: b25b sxtb r3, r3 +100009f6: d026 beq.n 10000a46 +100009f8: f992 4006 ldrsb.w r4, [r2, #6] +100009fc: 429c cmp r4, r3 +100009fe: d028 beq.n 10000a52 +10000a00: f992 4012 ldrsb.w r4, [r2, #18] +10000a04: 429c cmp r4, r3 +10000a06: d02f beq.n 10000a68 +10000a08: f992 401e ldrsb.w r4, [r2, #30] +10000a0c: 429c cmp r4, r3 +10000a0e: d02d beq.n 10000a6c +10000a10: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000a14: 429c cmp r4, r3 +10000a16: d02b beq.n 10000a70 +10000a18: f992 4036 ldrsb.w r4, [r2, #54] @ 0x36 +10000a1c: 429c cmp r4, r3 +10000a1e: d029 beq.n 10000a74 +10000a20: f992 4042 ldrsb.w r4, [r2, #66] @ 0x42 +10000a24: 429c cmp r4, r3 +10000a26: bf08 it eq +10000a28: 2405 moveq r4, #5 +10000a2a: d013 beq.n 10000a54 +10000a2c: 4a14 ldr r2, [pc, #80] @ (10000a80 ) +10000a2e: 2400 movs r4, #0 +10000a30: f892 c000 ldrb.w ip, [r2] +10000a34: 7013 strb r3, [r2, #0] +10000a36: f880 c006 strb.w ip, [r0, #6] +10000a3a: e8c1 4f8f stlb r4, [r1] +10000a3e: f385 8810 msr PRIMASK, r5 +10000a42: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10000a46: f8d8 2008 ldr.w r2, [r8, #8] +10000a4a: 4c0e ldr r4, [pc, #56] @ (10000a84 ) +10000a4c: f842 402e str.w r4, [r2, lr, lsl #2] +10000a50: e7ec b.n 10000a2c +10000a52: 2400 movs r4, #0 +10000a54: eb04 0444 add.w r4, r4, r4, lsl #1 +10000a58: eb02 0284 add.w r2, r2, r4, lsl #2 +10000a5c: 24ff movs r4, #255 @ 0xff +10000a5e: 7194 strb r4, [r2, #6] +10000a60: f64b 5401 movw r4, #48385 @ 0xbd01 +10000a64: 8094 strh r4, [r2, #4] +10000a66: e7e1 b.n 10000a2c +10000a68: 2401 movs r4, #1 +10000a6a: e7f3 b.n 10000a54 +10000a6c: 2402 movs r4, #2 +10000a6e: e7f1 b.n 10000a54 +10000a70: 2403 movs r4, #3 +10000a72: e7ef b.n 10000a54 +10000a74: 2404 movs r4, #4 +10000a76: e7ed b.n 10000a54 +10000a78: 20001d1d .word 0x20001d1d +10000a7c: 200011a4 .word 0x200011a4 +10000a80: 2000253d .word 0x2000253d +10000a84: 10000111 .word 0x10000111 +10000a88: e000ed00 .word 0xe000ed00 + +10000a8c : +10000a8c: b500 push {lr} +10000a8e: f8df c024 ldr.w ip, [pc, #36] @ 10000ab4 +10000a92: b083 sub sp, #12 +10000a94: 4601 mov r1, r0 +10000a96: 2305 movs r3, #5 +10000a98: 2200 movs r2, #0 +10000a9a: f8cd c000 str.w ip, [sp] +10000a9e: 4804 ldr r0, [pc, #16] @ (10000ab0 ) +10000aa0: f7ff fd98 bl 100005d4 +10000aa4: 2800 cmp r0, #0 +10000aa6: bfa8 it ge +10000aa8: f1c0 0033 rsbge r0, r0, #51 @ 0x33 +10000aac: b003 add sp, #12 +10000aae: bd00 pop {pc} +10000ab0: 20002542 .word 0x20002542 +10000ab4: 1000c5dc .word 0x1000c5dc + +10000ab8 : +10000ab8: 4b01 ldr r3, [pc, #4] @ (10000ac0 ) +10000aba: 440b add r3, r1 +10000abc: 6003 str r3, [r0, #0] +10000abe: 4770 bx lr +10000ac0: 20001d14 .word 0x20001d14 + +10000ac4 : +10000ac4: b570 push {r4, r5, r6, lr} +10000ac6: 4c10 ldr r4, [pc, #64] @ (10000b08 ) +10000ac8: 4d10 ldr r5, [pc, #64] @ (10000b0c ) +10000aca: 42ac cmp r4, r5 +10000acc: d20e bcs.n 10000aec +10000ace: 26ff movs r6, #255 @ 0xff +10000ad0: 6823 ldr r3, [r4, #0] +10000ad2: b163 cbz r3, 10000aee +10000ad4: f7ff fdc0 bl 10000658 +10000ad8: 4601 mov r1, r0 +10000ada: 4620 mov r0, r4 +10000adc: f7ff ffec bl 10000ab8 +10000ae0: 80a6 strh r6, [r4, #4] +10000ae2: f3bf 8f5f dmb sy +10000ae6: 3408 adds r4, #8 +10000ae8: 42ac cmp r4, r5 +10000aea: d3f1 bcc.n 10000ad0 +10000aec: bd70 pop {r4, r5, r6, pc} +10000aee: f7ff fdb3 bl 10000658 +10000af2: 4601 mov r1, r0 +10000af4: 4620 mov r0, r4 +10000af6: f7ff ffdf bl 10000ab8 +10000afa: 7126 strb r6, [r4, #4] +10000afc: f3bf 8f5f dmb sy +10000b00: 3408 adds r4, #8 +10000b02: 42ac cmp r4, r5 +10000b04: d3e4 bcc.n 10000ad0 +10000b06: bd70 pop {r4, r5, r6, pc} +10000b08: 20001870 .word 0x20001870 +10000b0c: 20001878 .word 0x20001878 + +10000b10 : +10000b10: b510 push {r4, lr} +10000b12: 4604 mov r4, r0 +10000b14: f7ff fda0 bl 10000658 +10000b18: 4601 mov r1, r0 +10000b1a: 4620 mov r0, r4 +10000b1c: f7ff ffcc bl 10000ab8 +10000b20: 23ff movs r3, #255 @ 0xff +10000b22: 7123 strb r3, [r4, #4] +10000b24: f3bf 8f5f dmb sy +10000b28: bd10 pop {r4, pc} +10000b2a: bf00 nop + +10000b2c : +10000b2c: b510 push {r4, lr} +10000b2e: 4604 mov r4, r0 +10000b30: 2001 movs r0, #1 +10000b32: f7ff fd9d bl 10000670 +10000b36: 4b03 ldr r3, [pc, #12] @ (10000b44 ) +10000b38: 4403 add r3, r0 +10000b3a: 6023 str r3, [r4, #0] +10000b3c: f3bf 8f5f dmb sy +10000b40: bd10 pop {r4, pc} +10000b42: bf00 nop +10000b44: 20001d14 .word 0x20001d14 + +10000b48 : +10000b48: 4b02 ldr r3, [pc, #8] @ (10000b54 ) +10000b4a: 440b add r3, r1 +10000b4c: 6003 str r3, [r0, #0] +10000b4e: f3bf 8f5f dmb sy +10000b52: 4770 bx lr +10000b54: 20001d14 .word 0x20001d14 + +10000b58 : +10000b58: bf40 sev +10000b5a: 2000 movs r0, #0 +10000b5c: 2100 movs r1, #0 +10000b5e: 4770 bx lr + +10000b60 : +10000b60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000b64: b085 sub sp, #20 +10000b66: f3ef 8305 mrs r3, IPSR +10000b6a: b2db uxtb r3, r3 +10000b6c: 3b10 subs r3, #16 +10000b6e: 089a lsrs r2, r3, #2 +10000b70: bf1a itte ne +10000b72: 2201 movne r2, #1 +10000b74: 4999 ldrne r1, [pc, #612] @ (10000ddc ) +10000b76: 499a ldreq r1, [pc, #616] @ (10000de0 ) +10000b78: f003 0a03 and.w sl, r3, #3 +10000b7c: 9100 str r1, [sp, #0] +10000b7e: 2101 movs r1, #1 +10000b80: 4b98 ldr r3, [pc, #608] @ (10000de4 ) +10000b82: eb0a 0282 add.w r2, sl, r2, lsl #2 +10000b86: f853 4022 ldr.w r4, [r3, r2, lsl #2] +10000b8a: 9b00 ldr r3, [sp, #0] +10000b8c: fa01 f20a lsl.w r2, r1, sl +10000b90: f503 5341 add.w r3, r3, #12352 @ 0x3040 +10000b94: f104 0b08 add.w fp, r4, #8 +10000b98: 9201 str r2, [sp, #4] +10000b9a: 605a str r2, [r3, #4] +10000b9c: f9b4 6008 ldrsh.w r6, [r4, #8] +10000ba0: e9dd 0300 ldrd r0, r3, [sp] +10000ba4: 2e00 cmp r6, #0 +10000ba6: 63c3 str r3, [r0, #60] @ 0x3c +10000ba8: da72 bge.n 10000c90 +10000baa: 88a3 ldrh r3, [r4, #4] +10000bac: 041b lsls r3, r3, #16 +10000bae: f100 811b bmi.w 10000de8 +10000bb2: 6923 ldr r3, [r4, #16] +10000bb4: f3ef 8210 mrs r2, PRIMASK +10000bb8: b672 cpsid i +10000bba: e8d3 0fcf ldaexb r0, [r3] +10000bbe: 2101 movs r1, #1 +10000bc0: 2800 cmp r0, #0 +10000bc2: d1fa bne.n 10000bba +10000bc4: e8c3 1f40 strexb r0, r1, [r3] +10000bc8: 2800 cmp r0, #0 +10000bca: d1f6 bne.n 10000bba +10000bcc: f3bf 8f5f dmb sy +10000bd0: f64f 76ff movw r6, #65535 @ 0xffff +10000bd4: 88a0 ldrh r0, [r4, #4] +10000bd6: 2100 movs r1, #0 +10000bd8: 6923 ldr r3, [r4, #16] +10000bda: b200 sxth r0, r0 +10000bdc: 80a6 strh r6, [r4, #4] +10000bde: e8c3 1f8f stlb r1, [r3] +10000be2: f382 8810 msr PRIMASK, r2 +10000be6: 4288 cmp r0, r1 +10000be8: db28 blt.n 10000c3c +10000bea: 46a6 mov lr, r4 +10000bec: 4605 mov r5, r0 +10000bee: 6967 ldr r7, [r4, #20] +10000bf0: f9be 3008 ldrsh.w r3, [lr, #8] +10000bf4: eb05 0645 add.w r6, r5, r5, lsl #1 +10000bf8: 2b00 cmp r3, #0 +10000bfa: 46dc mov ip, fp +10000bfc: eb07 02c6 add.w r2, r7, r6, lsl #3 +10000c00: db13 blt.n 10000c2a +10000c02: e9d2 4002 ldrd r4, r0, [r2, #8] +10000c06: 46a9 mov r9, r5 +10000c08: e004 b.n 10000c14 +10000c0a: f937 3038 ldrsh.w r3, [r7, r8, lsl #3] +10000c0e: 4694 mov ip, r2 +10000c10: 2b00 cmp r3, #0 +10000c12: db09 blt.n 10000c28 +10000c14: eb03 0843 add.w r8, r3, r3, lsl #1 +10000c18: eb07 02c8 add.w r2, r7, r8, lsl #3 +10000c1c: e9d2 5102 ldrd r5, r1, [r2, #8] +10000c20: 42ac cmp r4, r5 +10000c22: eb70 0101 sbcs.w r1, r0, r1 +10000c26: daf0 bge.n 10000c0a +10000c28: 464d mov r5, r9 +10000c2a: f8ac 5000 strh.w r5, [ip] +10000c2e: f937 5036 ldrsh.w r5, [r7, r6, lsl #3] +10000c32: f827 3036 strh.w r3, [r7, r6, lsl #3] +10000c36: 2d00 cmp r5, #0 +10000c38: dada bge.n 10000bf0 +10000c3a: 4674 mov r4, lr +10000c3c: f9b4 3008 ldrsh.w r3, [r4, #8] +10000c40: 2b00 cmp r3, #0 +10000c42: f2c0 811b blt.w 10000e7c +10000c46: 6962 ldr r2, [r4, #20] +10000c48: 9d00 ldr r5, [sp, #0] +10000c4a: eb03 0343 add.w r3, r3, r3, lsl #1 +10000c4e: eb02 03c3 add.w r3, r2, r3, lsl #3 +10000c52: eb05 008a add.w r0, r5, sl, lsl #2 +10000c56: 6aa9 ldr r1, [r5, #40] @ 0x28 +10000c58: 689e ldr r6, [r3, #8] +10000c5a: 6902 ldr r2, [r0, #16] +10000c5c: eba6 0c01 sub.w ip, r6, r1 +10000c60: 1a52 subs r2, r2, r1 +10000c62: 4594 cmp ip, r2 +10000c64: 68df ldr r7, [r3, #12] +10000c66: d305 bcc.n 10000c74 +10000c68: 2301 movs r3, #1 +10000c6a: 6a2a ldr r2, [r5, #32] +10000c6c: fa03 f30a lsl.w r3, r3, sl +10000c70: 4213 tst r3, r2 +10000c72: d100 bne.n 10000c76 +10000c74: 6106 str r6, [r0, #16] +10000c76: 79a3 ldrb r3, [r4, #6] +10000c78: 2b00 cmp r3, #0 +10000c7a: d149 bne.n 10000d10 +10000c7c: 9800 ldr r0, [sp, #0] +10000c7e: f000 fb83 bl 10001388 +10000c82: 42b0 cmp r0, r6 +10000c84: 41b9 sbcs r1, r7 +10000c86: da89 bge.n 10000b9c +10000c88: bf40 sev +10000c8a: b005 add sp, #20 +10000c8c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000c90: f8d4 9014 ldr.w r9, [r4, #20] +10000c94: eb06 0846 add.w r8, r6, r6, lsl #1 +10000c98: eb09 07c8 add.w r7, r9, r8, lsl #3 +10000c9c: 68bb ldr r3, [r7, #8] +10000c9e: 68fd ldr r5, [r7, #12] +10000ca0: 9302 str r3, [sp, #8] +10000ca2: f000 fb71 bl 10001388 +10000ca6: 9b02 ldr r3, [sp, #8] +10000ca8: 4298 cmp r0, r3 +10000caa: 41a9 sbcs r1, r5 +10000cac: db2b blt.n 10000d06 +10000cae: e9d7 3104 ldrd r3, r1, [r7, #16] +10000cb2: 2b02 cmp r3, #2 +10000cb4: d06b beq.n 10000d8e +10000cb6: 887a ldrh r2, [r7, #2] +10000cb8: f9b4 0008 ldrsh.w r0, [r4, #8] +10000cbc: b292 uxth r2, r2 +10000cbe: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000cc2: 4798 blx r3 +10000cc4: 4602 mov r2, r0 +10000cc6: 460b mov r3, r1 +10000cc8: ea52 0103 orrs.w r1, r2, r3 +10000ccc: d065 beq.n 10000d9a +10000cce: 2b00 cmp r3, #0 +10000cd0: f280 80aa bge.w 10000e28 +10000cd4: 9902 ldr r1, [sp, #8] +10000cd6: ebb1 0c02 subs.w ip, r1, r2 +10000cda: eb65 0e03 sbc.w lr, r5, r3 +10000cde: f939 3038 ldrsh.w r3, [r9, r8, lsl #3] +10000ce2: e9c7 ce02 strd ip, lr, [r7, #8] +10000ce6: 2b00 cmp r3, #0 +10000ce8: db0d blt.n 10000d06 +10000cea: 6960 ldr r0, [r4, #20] +10000cec: eb03 0243 add.w r2, r3, r3, lsl #1 +10000cf0: eb00 02c2 add.w r2, r0, r2, lsl #3 +10000cf4: e9d2 7102 ldrd r7, r1, [r2, #8] +10000cf8: 45bc cmp ip, r7 +10000cfa: eb7e 0501 sbcs.w r5, lr, r1 +10000cfe: ea4f 0243 mov.w r2, r3, lsl #1 +10000d02: f280 809d bge.w 10000e40 +10000d06: 88a3 ldrh r3, [r4, #4] +10000d08: 0418 lsls r0, r3, #16 +10000d0a: f57f af52 bpl.w 10000bb2 +10000d0e: e795 b.n 10000c3c +10000d10: f04f 0800 mov.w r8, #0 +10000d14: f884 8006 strb.w r8, [r4, #6] +10000d18: f9b4 3008 ldrsh.w r3, [r4, #8] +10000d1c: 1c59 adds r1, r3, #1 +10000d1e: d0ad beq.n 10000c7c +10000d20: 46dc mov ip, fp +10000d22: f8cd a008 str.w sl, [sp, #8] +10000d26: e002 b.n 10000d2e +10000d28: 1c5a adds r2, r3, #1 +10000d2a: 46ac mov ip, r5 +10000d2c: d02c beq.n 10000d88 +10000d2e: 6962 ldr r2, [r4, #20] +10000d30: eb03 0143 add.w r1, r3, r3, lsl #1 +10000d34: eb02 05c1 add.w r5, r2, r1, lsl #3 +10000d38: f8b5 e002 ldrh.w lr, [r5, #2] +10000d3c: 4618 mov r0, r3 +10000d3e: f41e 4f00 tst.w lr, #32768 @ 0x8000 +10000d42: f932 3031 ldrsh.w r3, [r2, r1, lsl #3] +10000d46: d0ef beq.n 10000d28 +10000d48: 6925 ldr r5, [r4, #16] +10000d4a: f8ac 3000 strh.w r3, [ip] +10000d4e: f3ef 8e10 mrs lr, PRIMASK +10000d52: b672 cpsid i +10000d54: e8d5 afcf ldaexb sl, [r5] +10000d58: f05f 0901 movs.w r9, #1 +10000d5c: f1ba 0f00 cmp.w sl, #0 +10000d60: d1f8 bne.n 10000d54 +10000d62: e8c5 9f4a strexb sl, r9, [r5] +10000d66: f1ba 0f00 cmp.w sl, #0 +10000d6a: d1f3 bne.n 10000d54 +10000d6c: f3bf 8f5f dmb sy +10000d70: f8b4 9002 ldrh.w r9, [r4, #2] +10000d74: 6925 ldr r5, [r4, #16] +10000d76: f822 9031 strh.w r9, [r2, r1, lsl #3] +10000d7a: 8060 strh r0, [r4, #2] +10000d7c: e8c5 8f8f stlb r8, [r5] +10000d80: f38e 8810 msr PRIMASK, lr +10000d84: 1c5a adds r2, r3, #1 +10000d86: d1d2 bne.n 10000d2e +10000d88: f8dd a008 ldr.w sl, [sp, #8] +10000d8c: e776 b.n 10000c7c +10000d8e: 4608 mov r0, r1 +10000d90: 690b ldr r3, [r1, #16] +10000d92: 9103 str r1, [sp, #12] +10000d94: 4798 blx r3 +10000d96: 2800 cmp r0, #0 +10000d98: d139 bne.n 10000e0e +10000d9a: f839 3038 ldrh.w r3, [r9, r8, lsl #3] +10000d9e: 8123 strh r3, [r4, #8] +10000da0: 6923 ldr r3, [r4, #16] +10000da2: f3ef 8210 mrs r2, PRIMASK +10000da6: b672 cpsid i +10000da8: e8d3 0fcf ldaexb r0, [r3] +10000dac: 2101 movs r1, #1 +10000dae: 2800 cmp r0, #0 +10000db0: d1fa bne.n 10000da8 +10000db2: e8c3 1f40 strexb r0, r1, [r3] +10000db6: 2800 cmp r0, #0 +10000db8: d1f6 bne.n 10000da8 +10000dba: f3bf 8f5f dmb sy +10000dbe: 8863 ldrh r3, [r4, #2] +10000dc0: 6921 ldr r1, [r4, #16] +10000dc2: f829 3038 strh.w r3, [r9, r8, lsl #3] +10000dc6: 2300 movs r3, #0 +10000dc8: 8066 strh r6, [r4, #2] +10000dca: e8c1 3f8f stlb r3, [r1] +10000dce: f382 8810 msr PRIMASK, r2 +10000dd2: 88a3 ldrh r3, [r4, #4] +10000dd4: 0418 lsls r0, r3, #16 +10000dd6: f57f aeec bpl.w 10000bb2 +10000dda: e72f b.n 10000c3c +10000ddc: 400b8000 .word 0x400b8000 +10000de0: 400b0000 .word 0x400b0000 +10000de4: 200024f8 .word 0x200024f8 +10000de8: 4604 mov r4, r0 +10000dea: 4620 mov r0, r4 +10000dec: f000 facc bl 10001388 +10000df0: f100 4200 add.w r2, r0, #2147483648 @ 0x80000000 +10000df4: eb04 008a add.w r0, r4, sl, lsl #2 +10000df8: 6aa3 ldr r3, [r4, #40] @ 0x28 +10000dfa: 6901 ldr r1, [r0, #16] +10000dfc: 1ac9 subs r1, r1, r3 +10000dfe: 1ad3 subs r3, r2, r3 +10000e00: 428b cmp r3, r1 +10000e02: d208 bcs.n 10000e16 +10000e04: 6102 str r2, [r0, #16] +10000e06: bf40 sev +10000e08: b005 add sp, #20 +10000e0a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000e0e: 9903 ldr r1, [sp, #12] +10000e10: e9d1 2300 ldrd r2, r3, [r1] +10000e14: e758 b.n 10000cc8 +10000e16: 2301 movs r3, #1 +10000e18: 6a21 ldr r1, [r4, #32] +10000e1a: fa03 f30a lsl.w r3, r3, sl +10000e1e: 420b tst r3, r1 +10000e20: f47f af32 bne.w 10000c88 +10000e24: 6102 str r2, [r0, #16] +10000e26: e7ee b.n 10000e06 +10000e28: 9800 ldr r0, [sp, #0] +10000e2a: e9cd 2302 strd r2, r3, [sp, #8] +10000e2e: f000 faab bl 10001388 +10000e32: 9a02 ldr r2, [sp, #8] +10000e34: 9b03 ldr r3, [sp, #12] +10000e36: eb10 0c02 adds.w ip, r0, r2 +10000e3a: eb43 0e01 adc.w lr, r3, r1 +10000e3e: e74e b.n 10000cde +10000e40: 4625 mov r5, r4 +10000e42: f825 3f08 strh.w r3, [r5, #8]! +10000e46: e006 b.n 10000e56 +10000e48: eb03 0243 add.w r2, r3, r3, lsl #1 +10000e4c: eb00 02c2 add.w r2, r0, r2, lsl #3 +10000e50: e9d2 7102 ldrd r7, r1, [r2, #8] +10000e54: 005a lsls r2, r3, #1 +10000e56: 45bc cmp ip, r7 +10000e58: eb7e 0101 sbcs.w r1, lr, r1 +10000e5c: 441a add r2, r3 +10000e5e: db05 blt.n 10000e6c +10000e60: f930 3032 ldrsh.w r3, [r0, r2, lsl #3] +10000e64: eb00 05c2 add.w r5, r0, r2, lsl #3 +10000e68: 2b00 cmp r3, #0 +10000e6a: daed bge.n 10000e48 +10000e6c: f829 3038 strh.w r3, [r9, r8, lsl #3] +10000e70: 802e strh r6, [r5, #0] +10000e72: 88a3 ldrh r3, [r4, #4] +10000e74: 0418 lsls r0, r3, #16 +10000e76: f57f ae9c bpl.w 10000bb2 +10000e7a: e6df b.n 10000c3c +10000e7c: 9c00 ldr r4, [sp, #0] +10000e7e: e7b4 b.n 10000dea + +10000e80 : +10000e80: b538 push {r3, r4, r5, lr} +10000e82: 4b33 ldr r3, [pc, #204] @ (10000f50 ) +10000e84: 691c ldr r4, [r3, #16] +10000e86: b104 cbz r4, 10000e8a +10000e88: bd38 pop {r3, r4, r5, pc} +10000e8a: 2103 movs r1, #3 +10000e8c: 4831 ldr r0, [pc, #196] @ (10000f54 ) +10000e8e: f000 fa69 bl 10001364 +10000e92: 4d30 ldr r5, [pc, #192] @ (10000f54 ) +10000e94: 4b2e ldr r3, [pc, #184] @ (10000f50 ) +10000e96: 60dd str r5, [r3, #12] +10000e98: f7ff fbde bl 10000658 +10000e9c: 4a2e ldr r2, [pc, #184] @ (10000f58 ) +10000e9e: f04f 4e50 mov.w lr, #3489660928 @ 0xd0000000 +10000ea2: 4402 add r2, r0 +10000ea4: 2003 movs r0, #3 +10000ea6: 4b2a ldr r3, [pc, #168] @ (10000f50 ) +10000ea8: f04f 0c0f mov.w ip, #15 +10000eac: 7018 strb r0, [r3, #0] +10000eae: 611a str r2, [r3, #16] +10000eb0: f8de 2000 ldr.w r2, [lr] +10000eb4: f64f 71ff movw r1, #65535 @ 0xffff +10000eb8: 705a strb r2, [r3, #1] +10000eba: 695a ldr r2, [r3, #20] +10000ebc: f8a3 c002 strh.w ip, [r3, #2] +10000ec0: 8314 strh r4, [r2, #24] +10000ec2: f04f 0402 mov.w r4, #2 +10000ec6: f8a2 4048 strh.w r4, [r2, #72] @ 0x48 +10000eca: f04f 0404 mov.w r4, #4 +10000ece: f8a2 4078 strh.w r4, [r2, #120] @ 0x78 +10000ed2: f04f 0405 mov.w r4, #5 +10000ed6: f8a2 4090 strh.w r4, [r2, #144] @ 0x90 +10000eda: f04f 0406 mov.w r4, #6 +10000ede: f8a2 40a8 strh.w r4, [r2, #168] @ 0xa8 +10000ee2: f04f 0407 mov.w r4, #7 +10000ee6: f8a2 40c0 strh.w r4, [r2, #192] @ 0xc0 +10000eea: f04f 0409 mov.w r4, #9 +10000eee: f8a2 40f0 strh.w r4, [r2, #240] @ 0xf0 +10000ef2: f04f 040a mov.w r4, #10 +10000ef6: f8a2 4108 strh.w r4, [r2, #264] @ 0x108 +10000efa: f04f 040b mov.w r4, #11 +10000efe: f8a2 4120 strh.w r4, [r2, #288] @ 0x120 +10000f02: f04f 040c mov.w r4, #12 +10000f06: f8a2 4138 strh.w r4, [r2, #312] @ 0x138 +10000f0a: f04f 0401 mov.w r4, #1 +10000f0e: 8614 strh r4, [r2, #48] @ 0x30 +10000f10: f04f 0408 mov.w r4, #8 +10000f14: f8a2 40d8 strh.w r4, [r2, #216] @ 0xd8 +10000f18: 4c10 ldr r4, [pc, #64] @ (10000f5c ) +10000f1a: f04f 0e0d mov.w lr, #13 +10000f1e: f04f 0c0e mov.w ip, #14 +10000f22: 609c str r4, [r3, #8] +10000f24: 2408 movs r4, #8 +10000f26: 8099 strh r1, [r3, #4] +10000f28: f8a2 e150 strh.w lr, [r2, #336] @ 0x150 +10000f2c: f8a2 c168 strh.w ip, [r2, #360] @ 0x168 +10000f30: f8a2 0060 strh.w r0, [r2, #96] @ 0x60 +10000f34: 8011 strh r1, [r2, #0] +10000f36: 4a0a ldr r2, [pc, #40] @ (10000f60 ) +10000f38: 490a ldr r1, [pc, #40] @ (10000f64 ) +10000f3a: 622c str r4, [r5, #32] +10000f3c: 60d3 str r3, [r2, #12] +10000f3e: f7ff fc1f bl 10000780 +10000f42: 2101 movs r1, #1 +10000f44: 2003 movs r0, #3 +10000f46: f7ff fbd9 bl 100006fc +10000f4a: 4b07 ldr r3, [pc, #28] @ (10000f68 ) +10000f4c: 641c str r4, [r3, #64] @ 0x40 +10000f4e: bd38 pop {r3, r4, r5, pc} +10000f50: 20001204 .word 0x20001204 +10000f54: 400b0000 .word 0x400b0000 +10000f58: 20001d14 .word 0x20001d14 +10000f5c: 0010ffff .word 0x0010ffff +10000f60: 200024f8 .word 0x200024f8 +10000f64: 10000b61 .word 0x10000b61 +10000f68: 400b2000 .word 0x400b2000 + +10000f6c : +10000f6c: 4800 ldr r0, [pc, #0] @ (10000f70 ) +10000f6e: 4770 bx lr +10000f70: 20001204 .word 0x20001204 + +10000f74 : +10000f74: b5f0 push {r4, r5, r6, r7, lr} +10000f76: b083 sub sp, #12 +10000f78: f89d 4028 ldrb.w r4, [sp, #40] @ 0x28 +10000f7c: 461d mov r5, r3 +10000f7e: 4603 mov r3, r0 +10000f80: b954 cbnz r4, 10000f98 +10000f82: e9cd 0200 strd r0, r2, [sp] +10000f86: f000 fa07 bl 10001398 +10000f8a: 9a01 ldr r2, [sp, #4] +10000f8c: 9b00 ldr r3, [sp, #0] +10000f8e: 4282 cmp r2, r0 +10000f90: eb65 0101 sbc.w r1, r5, r1 +10000f94: 42a1 cmp r1, r4 +10000f96: db5b blt.n 10001050 +10000f98: 6919 ldr r1, [r3, #16] +10000f9a: f3ef 8010 mrs r0, PRIMASK +10000f9e: b672 cpsid i +10000fa0: e8d1 6fcf ldaexb r6, [r1] +10000fa4: 2401 movs r4, #1 +10000fa6: 2e00 cmp r6, #0 +10000fa8: d1fa bne.n 10000fa0 +10000faa: e8c1 4f46 strexb r6, r4, [r1] +10000fae: 2e00 cmp r6, #0 +10000fb0: d1f6 bne.n 10000fa0 +10000fb2: f3bf 8f5f dmb sy +10000fb6: f9b3 4002 ldrsh.w r4, [r3, #2] +10000fba: 691f ldr r7, [r3, #16] +10000fbc: 2c00 cmp r4, #0 +10000fbe: db3e blt.n 1000103e +10000fc0: f8d3 c014 ldr.w ip, [r3, #20] +10000fc4: eb04 0e44 add.w lr, r4, r4, lsl #1 +10000fc8: f83c 103e ldrh.w r1, [ip, lr, lsl #3] +10000fcc: 2600 movs r6, #0 +10000fce: 8059 strh r1, [r3, #2] +10000fd0: eb0c 01ce add.w r1, ip, lr, lsl #3 +10000fd4: e8c7 6f8f stlb r6, [r7] +10000fd8: f380 8810 msr PRIMASK, r0 +10000fdc: 8848 ldrh r0, [r1, #2] +10000fde: e9c1 2502 strd r2, r5, [r1, #8] +10000fe2: 3001 adds r0, #1 +10000fe4: f3c0 000e ubfx r0, r0, #0, #15 +10000fe8: 2801 cmp r0, #1 +10000fea: bf38 it cc +10000fec: 2001 movcc r0, #1 +10000fee: 9a08 ldr r2, [sp, #32] +10000ff0: 8048 strh r0, [r1, #2] +10000ff2: 610a str r2, [r1, #16] +10000ff4: 9a09 ldr r2, [sp, #36] @ 0x24 +10000ff6: ea40 4004 orr.w r0, r0, r4, lsl #16 +10000ffa: 614a str r2, [r1, #20] +10000ffc: 691a ldr r2, [r3, #16] +10000ffe: f3ef 8110 mrs r1, PRIMASK +10001002: b672 cpsid i +10001004: e8d2 7fcf ldaexb r7, [r2] +10001008: 2501 movs r5, #1 +1000100a: 2f00 cmp r7, #0 +1000100c: d1fa bne.n 10001004 +1000100e: e8c2 5f47 strexb r7, r5, [r2] +10001012: 2f00 cmp r7, #0 +10001014: d1f6 bne.n 10001004 +10001016: f3bf 8f5f dmb sy +1000101a: 889a ldrh r2, [r3, #4] +1000101c: f82c 203e strh.w r2, [ip, lr, lsl #3] +10001020: 691a ldr r2, [r3, #16] +10001022: 809c strh r4, [r3, #4] +10001024: e8c2 6f8f stlb r6, [r2] +10001028: f381 8810 msr PRIMASK, r1 +1000102c: 2101 movs r1, #1 +1000102e: 781c ldrb r4, [r3, #0] +10001030: 68da ldr r2, [r3, #12] +10001032: 40a1 lsls r1, r4 +10001034: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10001038: 6059 str r1, [r3, #4] +1000103a: b003 add sp, #12 +1000103c: bdf0 pop {r4, r5, r6, r7, pc} +1000103e: 2300 movs r3, #0 +10001040: e8c7 3f8f stlb r3, [r7] +10001044: f380 8810 msr PRIMASK, r0 +10001048: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000104c: b003 add sp, #12 +1000104e: bdf0 pop {r4, r5, r6, r7, pc} +10001050: 4620 mov r0, r4 +10001052: b003 add sp, #12 +10001054: bdf0 pop {r4, r5, r6, r7, pc} +10001056: bf00 nop + +10001058 : +10001058: b5f0 push {r4, r5, r6, r7, lr} +1000105a: 4616 mov r6, r2 +1000105c: 461f mov r7, r3 +1000105e: 6902 ldr r2, [r0, #16] +10001060: 4603 mov r3, r0 +10001062: f3ef 8010 mrs r0, PRIMASK +10001066: b672 cpsid i +10001068: e8d2 4fcf ldaexb r4, [r2] +1000106c: 2101 movs r1, #1 +1000106e: 2c00 cmp r4, #0 +10001070: d1fa bne.n 10001068 +10001072: e8c2 1f44 strexb r4, r1, [r2] +10001076: 2c00 cmp r4, #0 +10001078: d1f6 bne.n 10001068 +1000107a: f3bf 8f5f dmb sy +1000107e: f9b3 1002 ldrsh.w r1, [r3, #2] +10001082: 691d ldr r5, [r3, #16] +10001084: 2900 cmp r1, #0 +10001086: db45 blt.n 10001114 +10001088: f8d3 e014 ldr.w lr, [r3, #20] +1000108c: eb01 0241 add.w r2, r1, r1, lsl #1 +10001090: f83e 4032 ldrh.w r4, [lr, r2, lsl #3] +10001094: eb0e 0cc2 add.w ip, lr, r2, lsl #3 +10001098: 805c strh r4, [r3, #2] +1000109a: 2400 movs r4, #0 +1000109c: e8c5 4f8f stlb r4, [r5] +100010a0: f380 8810 msr PRIMASK, r0 +100010a4: 9805 ldr r0, [sp, #20] +100010a6: 4635 mov r5, r6 +100010a8: f8cc 0010 str.w r0, [ip, #16] +100010ac: 9806 ldr r0, [sp, #24] +100010ae: 463e mov r6, r7 +100010b0: f8cc 0014 str.w r0, [ip, #20] +100010b4: f8bc 0002 ldrh.w r0, [ip, #2] +100010b8: e9cc 5602 strd r5, r6, [ip, #8] +100010bc: 3001 adds r0, #1 +100010be: f3c0 000e ubfx r0, r0, #0, #15 +100010c2: 2801 cmp r0, #1 +100010c4: bf38 it cc +100010c6: 2001 movcc r0, #1 +100010c8: f8ac 0002 strh.w r0, [ip, #2] +100010cc: ea40 4001 orr.w r0, r0, r1, lsl #16 +100010d0: f8d3 c010 ldr.w ip, [r3, #16] +100010d4: f3ef 8510 mrs r5, PRIMASK +100010d8: b672 cpsid i +100010da: e8dc 7fcf ldaexb r7, [ip] +100010de: 2601 movs r6, #1 +100010e0: 2f00 cmp r7, #0 +100010e2: d1fa bne.n 100010da +100010e4: e8cc 6f47 strexb r7, r6, [ip] +100010e8: 2f00 cmp r7, #0 +100010ea: d1f6 bne.n 100010da +100010ec: f3bf 8f5f dmb sy +100010f0: f8b3 c004 ldrh.w ip, [r3, #4] +100010f4: f82e c032 strh.w ip, [lr, r2, lsl #3] +100010f8: 8099 strh r1, [r3, #4] +100010fa: 691a ldr r2, [r3, #16] +100010fc: e8c2 4f8f stlb r4, [r2] +10001100: f385 8810 msr PRIMASK, r5 +10001104: 2101 movs r1, #1 +10001106: 781c ldrb r4, [r3, #0] +10001108: 68da ldr r2, [r3, #12] +1000110a: 40a1 lsls r1, r4 +1000110c: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10001110: 6059 str r1, [r3, #4] +10001112: bdf0 pop {r4, r5, r6, r7, pc} +10001114: 2300 movs r3, #0 +10001116: e8c5 3f8f stlb r3, [r5] +1000111a: f380 8810 msr PRIMASK, r0 +1000111e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10001122: bdf0 pop {r4, r5, r6, r7, pc} + +10001124 : +10001124: 4603 mov r3, r0 +10001126: 8940 ldrh r0, [r0, #10] +10001128: ebb0 4f21 cmp.w r0, r1, asr #16 +1000112c: dd3a ble.n 100011a4 +1000112e: 6958 ldr r0, [r3, #20] +10001130: 140a asrs r2, r1, #16 +10001132: eb02 0242 add.w r2, r2, r2, lsl #1 +10001136: b510 push {r4, lr} +10001138: f8d3 c010 ldr.w ip, [r3, #16] +1000113c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10001140: f3ef 8e10 mrs lr, PRIMASK +10001144: b672 cpsid i +10001146: e8dc 4fcf ldaexb r4, [ip] +1000114a: 2201 movs r2, #1 +1000114c: 2c00 cmp r4, #0 +1000114e: d1fa bne.n 10001146 +10001150: e8cc 2f44 strexb r4, r2, [ip] +10001154: 2c00 cmp r4, #0 +10001156: d1f6 bne.n 10001146 +10001158: f3bf 8f5f dmb sy +1000115c: 8842 ldrh r2, [r0, #2] +1000115e: b289 uxth r1, r1 +10001160: b292 uxth r2, r2 +10001162: 428a cmp r2, r1 +10001164: d007 beq.n 10001176 +10001166: 2200 movs r2, #0 +10001168: 691b ldr r3, [r3, #16] +1000116a: e8c3 2f8f stlb r2, [r3] +1000116e: f38e 8810 msr PRIMASK, lr +10001172: 2000 movs r0, #0 +10001174: bd10 pop {r4, pc} +10001176: ea6f 4242 mvn.w r2, r2, lsl #17 +1000117a: ea6f 4252 mvn.w r2, r2, lsr #17 +1000117e: 8042 strh r2, [r0, #2] +10001180: 2101 movs r1, #1 +10001182: 2200 movs r2, #0 +10001184: 6918 ldr r0, [r3, #16] +10001186: 7199 strb r1, [r3, #6] +10001188: e8c0 2f8f stlb r2, [r0] +1000118c: f38e 8810 msr PRIMASK, lr +10001190: f893 c000 ldrb.w ip, [r3] +10001194: 68da ldr r2, [r3, #12] +10001196: 4608 mov r0, r1 +10001198: f502 5301 add.w r3, r2, #8256 @ 0x2040 +1000119c: fa01 f10c lsl.w r1, r1, ip +100011a0: 6059 str r1, [r3, #4] +100011a2: bd10 pop {r4, pc} +100011a4: 2000 movs r0, #0 +100011a6: 4770 bx lr + +100011a8 : +100011a8: 7840 ldrb r0, [r0, #1] +100011aa: 4770 bx lr + +100011ac : +100011ac: b5f0 push {r4, r5, r6, r7, lr} +100011ae: b083 sub sp, #12 +100011b0: 4606 mov r6, r0 +100011b2: f000 f8f1 bl 10001398 +100011b6: f44f 737a mov.w r3, #1000 @ 0x3e8 +100011ba: 4604 mov r4, r0 +100011bc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +100011c0: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +100011c4: fbe6 4103 umlal r4, r1, r6, r3 +100011c8: 42a0 cmp r0, r4 +100011ca: eb72 0301 sbcs.w r3, r2, r1 +100011ce: bf3a itte cc +100011d0: 4604 movcc r4, r0 +100011d2: 4615 movcc r5, r2 +100011d4: 460d movcs r5, r1 +100011d6: 1fa6 subs r6, r4, #6 +100011d8: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +100011dc: 42b4 cmp r4, r6 +100011de: eb75 0307 sbcs.w r3, r5, r7 +100011e2: bf3c itt cc +100011e4: 2600 movcc r6, #0 +100011e6: 4637 movcc r7, r6 +100011e8: f000 f8d6 bl 10001398 +100011ec: 1a30 subs r0, r6, r0 +100011ee: eb67 0101 sbc.w r1, r7, r1 +100011f2: 2801 cmp r0, #1 +100011f4: f171 0100 sbcs.w r1, r1, #0 +100011f8: da06 bge.n 10001208 +100011fa: 4620 mov r0, r4 +100011fc: 4629 mov r1, r5 +100011fe: b003 add sp, #12 +10001200: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} +10001204: f000 b902 b.w 1000140c +10001208: f000 f8c6 bl 10001398 +1000120c: 4286 cmp r6, r0 +1000120e: eb67 0101 sbc.w r1, r7, r1 +10001212: 2900 cmp r1, #0 +10001214: db0a blt.n 1000122c +10001216: 2100 movs r1, #0 +10001218: 4b0a ldr r3, [pc, #40] @ (10001244 ) +1000121a: 4632 mov r2, r6 +1000121c: 9300 str r3, [sp, #0] +1000121e: 480a ldr r0, [pc, #40] @ (10001248 ) +10001220: 463b mov r3, r7 +10001222: 9101 str r1, [sp, #4] +10001224: f7ff ff18 bl 10001058 +10001228: 3001 adds r0, #1 +1000122a: d0e6 beq.n 100011fa +1000122c: 4a07 ldr r2, [pc, #28] @ (1000124c ) +1000122e: 6a53 ldr r3, [r2, #36] @ 0x24 +10001230: 429f cmp r7, r3 +10001232: d804 bhi.n 1000123e +10001234: 6a91 ldr r1, [r2, #40] @ 0x28 +10001236: 42b1 cmp r1, r6 +10001238: d2df bcs.n 100011fa +1000123a: 429f cmp r7, r3 +1000123c: d1dd bne.n 100011fa +1000123e: bf20 wfe +10001240: e7f5 b.n 1000122e +10001242: bf00 nop +10001244: 10000b59 .word 0x10000b59 +10001248: 20001204 .word 0x20001204 +1000124c: 400b0000 .word 0x400b0000 + +10001250 : +10001250: f3ef 8205 mrs r2, IPSR +10001254: b2d2 uxtb r2, r2 +10001256: b17a cbz r2, 10001278 +10001258: 4a3f ldr r2, [pc, #252] @ (10001358 ) +1000125a: 6a53 ldr r3, [r2, #36] @ 0x24 +1000125c: 428b cmp r3, r1 +1000125e: d309 bcc.n 10001274 +10001260: bf14 ite ne +10001262: 2301 movne r3, #1 +10001264: 2300 moveq r3, #0 +10001266: 6a92 ldr r2, [r2, #40] @ 0x28 +10001268: 4282 cmp r2, r0 +1000126a: bf34 ite cc +1000126c: 4618 movcc r0, r3 +1000126e: f043 0001 orrcs.w r0, r3, #1 +10001272: 4770 bx lr +10001274: 2000 movs r0, #0 +10001276: 4770 bx lr +10001278: b570 push {r4, r5, r6, lr} +1000127a: 4b38 ldr r3, [pc, #224] @ (1000135c ) +1000127c: b084 sub sp, #16 +1000127e: 68dd ldr r5, [r3, #12] +10001280: 4606 mov r6, r0 +10001282: 4628 mov r0, r5 +10001284: 781c ldrb r4, [r3, #0] +10001286: e9cd 1202 strd r1, r2, [sp, #8] +1000128a: f000 f87d bl 10001388 +1000128e: f104 0c04 add.w ip, r4, #4 +10001292: f855 c02c ldr.w ip, [r5, ip, lsl #2] +10001296: 9b02 ldr r3, [sp, #8] +10001298: ebac 0c00 sub.w ip, ip, r0 +1000129c: 1a30 subs r0, r6, r0 +1000129e: eb63 0101 sbc.w r1, r3, r1 +100012a2: 4560 cmp r0, ip +100012a4: f171 0100 sbcs.w r1, r1, #0 +100012a8: 9a03 ldr r2, [sp, #12] +100012aa: db1a blt.n 100012e2 +100012ac: 4a2a ldr r2, [pc, #168] @ (10001358 ) +100012ae: 6a51 ldr r1, [r2, #36] @ 0x24 +100012b0: 4299 cmp r1, r3 +100012b2: d307 bcc.n 100012c4 +100012b4: 6a92 ldr r2, [r2, #40] @ 0x28 +100012b6: 42b2 cmp r2, r6 +100012b8: d201 bcs.n 100012be +100012ba: 4299 cmp r1, r3 +100012bc: d002 beq.n 100012c4 +100012be: 2001 movs r0, #1 +100012c0: b004 add sp, #16 +100012c2: bd70 pop {r4, r5, r6, pc} +100012c4: bf20 wfe +100012c6: 4a24 ldr r2, [pc, #144] @ (10001358 ) +100012c8: 6a51 ldr r1, [r2, #36] @ 0x24 +100012ca: 4299 cmp r1, r3 +100012cc: d32d bcc.n 1000132a +100012ce: bf14 ite ne +100012d0: 2001 movne r0, #1 +100012d2: 2000 moveq r0, #0 +100012d4: 6a93 ldr r3, [r2, #40] @ 0x28 +100012d6: 42b3 cmp r3, r6 +100012d8: bf28 it cs +100012da: f040 0001 orrcs.w r0, r0, #1 +100012de: b004 add sp, #16 +100012e0: bd70 pop {r4, r5, r6, pc} +100012e2: e9cd 2302 strd r2, r3, [sp, #8] +100012e6: f000 f857 bl 10001398 +100012ea: 9b03 ldr r3, [sp, #12] +100012ec: 4286 cmp r6, r0 +100012ee: eb63 0101 sbc.w r1, r3, r1 +100012f2: 2900 cmp r1, #0 +100012f4: 9a02 ldr r2, [sp, #8] +100012f6: db1b blt.n 10001330 +100012f8: 4919 ldr r1, [pc, #100] @ (10001360 ) +100012fa: 4818 ldr r0, [pc, #96] @ (1000135c ) +100012fc: e9cd 1200 strd r1, r2, [sp] +10001300: 4632 mov r2, r6 +10001302: 9302 str r3, [sp, #8] +10001304: f7ff fea8 bl 10001058 +10001308: 1e01 subs r1, r0, #0 +1000130a: 9b02 ldr r3, [sp, #8] +1000130c: dd10 ble.n 10001330 +1000130e: 4a12 ldr r2, [pc, #72] @ (10001358 ) +10001310: 6a50 ldr r0, [r2, #36] @ 0x24 +10001312: 4298 cmp r0, r3 +10001314: d219 bcs.n 1000134a +10001316: bf20 wfe +10001318: 4810 ldr r0, [pc, #64] @ (1000135c ) +1000131a: 9302 str r3, [sp, #8] +1000131c: f7ff ff02 bl 10001124 +10001320: 4a0d ldr r2, [pc, #52] @ (10001358 ) +10001322: 9b02 ldr r3, [sp, #8] +10001324: 6a51 ldr r1, [r2, #36] @ 0x24 +10001326: 4299 cmp r1, r3 +10001328: d2d1 bcs.n 100012ce +1000132a: 2000 movs r0, #0 +1000132c: b004 add sp, #16 +1000132e: bd70 pop {r4, r5, r6, pc} +10001330: 4a09 ldr r2, [pc, #36] @ (10001358 ) +10001332: 6a50 ldr r0, [r2, #36] @ 0x24 +10001334: 4298 cmp r0, r3 +10001336: d3f8 bcc.n 1000132a +10001338: 1ac0 subs r0, r0, r3 +1000133a: bf18 it ne +1000133c: 2001 movne r0, #1 +1000133e: 6a93 ldr r3, [r2, #40] @ 0x28 +10001340: 42b3 cmp r3, r6 +10001342: bf28 it cs +10001344: f040 0001 orrcs.w r0, r0, #1 +10001348: e7c9 b.n 100012de +1000134a: 6a92 ldr r2, [r2, #40] @ 0x28 +1000134c: 42b2 cmp r2, r6 +1000134e: d2e3 bcs.n 10001318 +10001350: 4298 cmp r0, r3 +10001352: d1e1 bne.n 10001318 +10001354: e7df b.n 10001316 +10001356: bf00 nop +10001358: 400b0000 .word 0x400b0000 +1000135c: 20001204 .word 0x20001204 +10001360: 10000b59 .word 0x10000b59 + +10001364 : +10001364: b410 push {r4} +10001366: 4b05 ldr r3, [pc, #20] @ (1000137c ) +10001368: 4c05 ldr r4, [pc, #20] @ (10001380 ) +1000136a: 4a06 ldr r2, [pc, #24] @ (10001384 ) +1000136c: 42a0 cmp r0, r4 +1000136e: bf14 ite ne +10001370: 4618 movne r0, r3 +10001372: 1c58 addeq r0, r3, #1 +10001374: bc10 pop {r4} +10001376: f7ff b901 b.w 1000057c +1000137a: bf00 nop +1000137c: 20001e68 .word 0x20001e68 +10001380: 400b8000 .word 0x400b8000 +10001384: 1000c5f8 .word 0x1000c5f8 + +10001388 : +10001388: 4603 mov r3, r0 +1000138a: 6a41 ldr r1, [r0, #36] @ 0x24 +1000138c: 460a mov r2, r1 +1000138e: 6a98 ldr r0, [r3, #40] @ 0x28 +10001390: 6a59 ldr r1, [r3, #36] @ 0x24 +10001392: 428a cmp r2, r1 +10001394: d1fa bne.n 1000138c +10001396: 4770 bx lr + +10001398 : +10001398: 4b03 ldr r3, [pc, #12] @ (100013a8 ) +1000139a: 6a59 ldr r1, [r3, #36] @ 0x24 +1000139c: 460a mov r2, r1 +1000139e: 6a98 ldr r0, [r3, #40] @ 0x28 +100013a0: 6a59 ldr r1, [r3, #36] @ 0x24 +100013a2: 4291 cmp r1, r2 +100013a4: d1fa bne.n 1000139c +100013a6: 4770 bx lr +100013a8: 400b0000 .word 0x400b0000 + +100013ac : +100013ac: b500 push {lr} +100013ae: 468e mov lr, r1 +100013b0: 4a15 ldr r2, [pc, #84] @ (10001408 ) +100013b2: 6a53 ldr r3, [r2, #36] @ 0x24 +100013b4: 469c mov ip, r3 +100013b6: 6a91 ldr r1, [r2, #40] @ 0x28 +100013b8: 6a53 ldr r3, [r2, #36] @ 0x24 +100013ba: 4563 cmp r3, ip +100013bc: d1fa bne.n 100013b4 +100013be: 1840 adds r0, r0, r1 +100013c0: eb53 030e adcs.w r3, r3, lr +100013c4: f04f 0200 mov.w r2, #0 +100013c8: bf28 it cs +100013ca: 2201 movcs r2, #1 +100013cc: b1ba cbz r2, 100013fe +100013ce: 4b0e ldr r3, [pc, #56] @ (10001408 ) +100013d0: 6a5a ldr r2, [r3, #36] @ 0x24 +100013d2: 1c53 adds r3, r2, #1 +100013d4: bf08 it eq +100013d6: 4610 moveq r0, r2 +100013d8: d008 beq.n 100013ec +100013da: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +100013de: 4618 mov r0, r3 +100013e0: 4909 ldr r1, [pc, #36] @ (10001408 ) +100013e2: 6a4a ldr r2, [r1, #36] @ 0x24 +100013e4: 429a cmp r2, r3 +100013e6: d3fc bcc.n 100013e2 +100013e8: 429a cmp r2, r3 +100013ea: d107 bne.n 100013fc +100013ec: 4b06 ldr r3, [pc, #24] @ (10001408 ) +100013ee: e002 b.n 100013f6 +100013f0: 6a59 ldr r1, [r3, #36] @ 0x24 +100013f2: 4291 cmp r1, r2 +100013f4: d102 bne.n 100013fc +100013f6: 6a99 ldr r1, [r3, #40] @ 0x28 +100013f8: 4281 cmp r1, r0 +100013fa: d3f9 bcc.n 100013f0 +100013fc: bd00 pop {pc} +100013fe: 4a02 ldr r2, [pc, #8] @ (10001408 ) +10001400: 6a52 ldr r2, [r2, #36] @ 0x24 +10001402: 4293 cmp r3, r2 +10001404: d8ec bhi.n 100013e0 +10001406: e7ef b.n 100013e8 +10001408: 400b0000 .word 0x400b0000 + +1000140c : +1000140c: 4a07 ldr r2, [pc, #28] @ (1000142c ) +1000140e: 6a53 ldr r3, [r2, #36] @ 0x24 +10001410: 4299 cmp r1, r3 +10001412: d8fc bhi.n 1000140e +10001414: 4299 cmp r1, r3 +10001416: d107 bne.n 10001428 +10001418: 4b04 ldr r3, [pc, #16] @ (1000142c ) +1000141a: e002 b.n 10001422 +1000141c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000141e: 4291 cmp r1, r2 +10001420: d102 bne.n 10001428 +10001422: 6a9a ldr r2, [r3, #40] @ 0x28 +10001424: 4290 cmp r0, r2 +10001426: d8f9 bhi.n 1000141c +10001428: 4770 bx lr +1000142a: bf00 nop +1000142c: 400b0000 .word 0x400b0000 + +10001430 : +10001430: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001434: ea4f 0c8c mov.w ip, ip, lsl #2 +10001438: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +1000143c: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10001440: b570 push {r4, r5, r6, lr} +10001442: 461e mov r6, r3 +10001444: f8dc 3004 ldr.w r3, [ip, #4] +10001448: 1f04 subs r4, r0, #4 +1000144a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 +1000144e: bf38 it cc +10001450: f44f 3380 movcc.w r3, #65536 @ 0x10000 +10001454: b2e4 uxtb r4, r4 +10001456: bf38 it cc +10001458: f8cc 3004 strcc.w r3, [ip, #4] +1000145c: 2c01 cmp r4, #1 +1000145e: d92e bls.n 100014be +10001460: f44f 6500 mov.w r5, #2048 @ 0x800 +10001464: 4b28 ldr r3, [pc, #160] @ (10001508 ) +10001466: f50c 5e40 add.w lr, ip, #12288 @ 0x3000 +1000146a: f8ce 5000 str.w r5, [lr] +1000146e: f853 e020 ldr.w lr, [r3, r0, lsl #2] +10001472: f1be 0f00 cmp.w lr, #0 +10001476: d117 bne.n 100014a8 +10001478: f8dc e000 ldr.w lr, [ip] +1000147c: 2c01 cmp r4, #1 +1000147e: ea8e 1242 eor.w r2, lr, r2, lsl #5 +10001482: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001486: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +1000148a: f8ce 2000 str.w r2, [lr] +1000148e: d92b bls.n 100014e8 +10001490: f44f 6100 mov.w r1, #2048 @ 0x800 +10001494: f843 6020 str.w r6, [r3, r0, lsl #2] +10001498: f44f 3380 mov.w r3, #65536 @ 0x10000 +1000149c: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100014a0: 6011 str r1, [r2, #0] +100014a2: f8cc 3004 str.w r3, [ip, #4] +100014a6: bd70 pop {r4, r5, r6, pc} +100014a8: 695d ldr r5, [r3, #20] +100014aa: fbb5 fefe udiv lr, r5, lr +100014ae: f10e 0e01 add.w lr, lr, #1 +100014b2: eb0e 0e4e add.w lr, lr, lr, lsl #1 +100014b6: f1be 0e03 subs.w lr, lr, #3 +100014ba: d2fc bcs.n 100014b6 +100014bc: e7dc b.n 10001478 +100014be: 2901 cmp r1, #1 +100014c0: d1ce bne.n 10001460 +100014c2: 2403 movs r4, #3 +100014c4: f50c 5340 add.w r3, ip, #12288 @ 0x3000 +100014c8: 601c str r4, [r3, #0] +100014ca: f8dc 3008 ldr.w r3, [ip, #8] +100014ce: 07db lsls r3, r3, #31 +100014d0: d5fb bpl.n 100014ca +100014d2: f8dc 3000 ldr.w r3, [ip] +100014d6: f50c 5e80 add.w lr, ip, #4096 @ 0x1000 +100014da: ea83 1342 eor.w r3, r3, r2, lsl #5 +100014de: f003 03e0 and.w r3, r3, #224 @ 0xe0 +100014e2: f8ce 3000 str.w r3, [lr] +100014e6: 4b08 ldr r3, [pc, #32] @ (10001508 ) +100014e8: 2201 movs r2, #1 +100014ea: f8dc 4000 ldr.w r4, [ip] +100014ee: 404c eors r4, r1 +100014f0: f004 0403 and.w r4, r4, #3 +100014f4: f8ce 4000 str.w r4, [lr] +100014f8: fa02 f101 lsl.w r1, r2, r1 +100014fc: f8dc 2008 ldr.w r2, [ip, #8] +10001500: 420a tst r2, r1 +10001502: d0fb beq.n 100014fc +10001504: e7c4 b.n 10001490 +10001506: bf00 nop +10001508: 20001e6c .word 0x20001e6c + +1000150c : +1000150c: 4b01 ldr r3, [pc, #4] @ (10001514 ) +1000150e: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001512: 4770 bx lr +10001514: 20001e6c .word 0x20001e6c + +10001518 : +10001518: b510 push {r4, lr} +1000151a: 9c02 ldr r4, [sp, #8] +1000151c: 468e mov lr, r1 +1000151e: ea4f 3c04 mov.w ip, r4, lsl #12 +10001522: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +10001526: 4b1c ldr r3, [pc, #112] @ (10001598 ) +10001528: fbb3 f3f1 udiv r3, r3, r1 +1000152c: 6801 ldr r1, [r0, #0] +1000152e: fbb2 f4f3 udiv r4, r2, r3 +10001532: 2900 cmp r1, #0 +10001534: db20 blt.n 10001578 +10001536: 4a19 ldr r2, [pc, #100] @ (1000159c ) +10001538: 4b19 ldr r3, [pc, #100] @ (100015a0 ) +1000153a: 4290 cmp r0, r2 +1000153c: bf14 ite ne +1000153e: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001542: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10001546: 4917 ldr r1, [pc, #92] @ (100015a4 ) +10001548: 601a str r2, [r3, #0] +1000154a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000154e: 601a str r2, [r3, #0] +10001550: 688b ldr r3, [r1, #8] +10001552: ea32 0303 bics.w r3, r2, r3 +10001556: d1fb bne.n 10001550 +10001558: 2221 movs r2, #33 @ 0x21 +1000155a: f500 5340 add.w r3, r0, #12288 @ 0x3000 +1000155e: 3304 adds r3, #4 +10001560: f8c0 e000 str.w lr, [r0] +10001564: 6084 str r4, [r0, #8] +10001566: 601a str r2, [r3, #0] +10001568: 6802 ldr r2, [r0, #0] +1000156a: 2a00 cmp r2, #0 +1000156c: dafc bge.n 10001568 +1000156e: 2208 movs r2, #8 +10001570: f8c0 c00c str.w ip, [r0, #12] +10001574: 601a str r2, [r3, #0] +10001576: bd10 pop {r4, pc} +10001578: 6803 ldr r3, [r0, #0] +1000157a: f003 033f and.w r3, r3, #63 @ 0x3f +1000157e: 4573 cmp r3, lr +10001580: d1d9 bne.n 10001536 +10001582: 6883 ldr r3, [r0, #8] +10001584: f3c3 030b ubfx r3, r3, #0, #12 +10001588: 42a3 cmp r3, r4 +1000158a: d1d4 bne.n 10001536 +1000158c: 68c3 ldr r3, [r0, #12] +1000158e: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001592: 4563 cmp r3, ip +10001594: d1cf bne.n 10001536 +10001596: bd10 pop {r4, pc} +10001598: 00b71b00 .word 0x00b71b00 +1000159c: 40058000 .word 0x40058000 +100015a0: 40022000 .word 0x40022000 +100015a4: 40020000 .word 0x40020000 + +100015a8 : +100015a8: f04f 4c80 mov.w ip, #1073741824 @ 0x40000000 +100015ac: 4b21 ldr r3, [pc, #132] @ (10001634 ) +100015ae: b500 push {lr} +100015b0: f8c3 c000 str.w ip, [r3] +100015b4: 2800 cmp r0, #0 +100015b6: d039 beq.n 1000162c +100015b8: f8df c088 ldr.w ip, [pc, #136] @ 10001644 +100015bc: f5a3 5340 sub.w r3, r3, #12288 @ 0x3000 +100015c0: f8c3 c01c str.w ip, [r3, #28] +100015c4: f8df c080 ldr.w ip, [pc, #128] @ 10001648 +100015c8: f040 0001 orr.w r0, r0, #1 +100015cc: ea80 0c0c eor.w ip, r0, ip +100015d0: f8c3 c020 str.w ip, [r3, #32] +100015d4: 6259 str r1, [r3, #36] @ 0x24 +100015d6: 6298 str r0, [r3, #40] @ 0x28 +100015d8: f04f 4e80 mov.w lr, #1073741824 @ 0x40000000 +100015dc: f04f 61e0 mov.w r1, #117440512 @ 0x7000000 +100015e0: 4b14 ldr r3, [pc, #80] @ (10001634 ) +100015e2: 4815 ldr r0, [pc, #84] @ (10001638 ) +100015e4: f8df c064 ldr.w ip, [pc, #100] @ 1000164c +100015e8: f8c3 e000 str.w lr, [r3] +100015ec: f8c0 c008 str.w ip, [r0, #8] +100015f0: 6019 str r1, [r3, #0] +100015f2: b92a cbnz r2, 10001600 +100015f4: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 +100015f8: f5a3 5380 sub.w r3, r3, #4096 @ 0x1000 +100015fc: 601a str r2, [r3, #0] +100015fe: bd00 pop {pc} +10001600: f44f 737a mov.w r3, #1000 @ 0x3e8 +10001604: fb03 f202 mul.w r2, r3, r2 +10001608: f1b2 7f80 cmp.w r2, #16777216 @ 0x1000000 +1000160c: bf2a itet cs +1000160e: f06f 437f mvncs.w r3, #4278190080 @ 0xff000000 +10001612: 4613 movcc r3, r2 +10001614: 461a movcs r2, r3 +10001616: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +1000161a: f8df c034 ldr.w ip, [pc, #52] @ 10001650 +1000161e: 4807 ldr r0, [pc, #28] @ (1000163c ) +10001620: f8cc 3000 str.w r3, [ip] +10001624: 4b06 ldr r3, [pc, #24] @ (10001640 ) +10001626: 6042 str r2, [r0, #4] +10001628: 6019 str r1, [r3, #0] +1000162a: bd00 pop {pc} +1000162c: 4b03 ldr r3, [pc, #12] @ (1000163c ) +1000162e: 61d8 str r0, [r3, #28] +10001630: e7d2 b.n 100015d8 +10001632: bf00 nop +10001634: 400db000 .word 0x400db000 +10001638: 4001a000 .word 0x4001a000 +1000163c: 400d8000 .word 0x400d8000 +10001640: 400da000 .word 0x400da000 +10001644: b007c0d3 .word 0xb007c0d3 +10001648: 4ff83f2d .word 0x4ff83f2d +1000164c: 01fffff3 .word 0x01fffff3 +10001650: 200024e8 .word 0x200024e8 + +10001654 : +10001654: 2301 movs r3, #1 +10001656: eb00 0040 add.w r0, r0, r0, lsl #1 +1000165a: 0080 lsls r0, r0, #2 +1000165c: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001660: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +10001664: 6041 str r1, [r0, #4] +10001666: 6003 str r3, [r0, #0] +10001668: 4770 bx lr +1000166a: bf00 nop + +1000166c : +1000166c: f04f 0c00 mov.w ip, #0 +10001670: b530 push {r4, r5, lr} +10001672: 4613 mov r3, r2 +10001674: b083 sub sp, #12 +10001676: 4604 mov r4, r0 +10001678: 460d mov r5, r1 +1000167a: f8bc 2016 ldrh.w r2, [ip, #22] +1000167e: 2100 movs r1, #0 +10001680: e841 f100 tt r1, r1 +10001684: 9301 str r3, [sp, #4] +10001686: 024b lsls r3, r1, #9 +10001688: bf54 ite pl +1000168a: 2110 movpl r1, #16 +1000168c: 2104 movmi r1, #4 +1000168e: f244 2052 movw r0, #16978 @ 0x4252 +10001692: 4790 blx r2 +10001694: 4686 mov lr, r0 +10001696: 462a mov r2, r5 +10001698: 210a movs r1, #10 +1000169a: 4620 mov r0, r4 +1000169c: 46f4 mov ip, lr +1000169e: 9b01 ldr r3, [sp, #4] +100016a0: b003 add sp, #12 +100016a2: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +100016a6: 4760 bx ip + +100016a8 : +100016a8: 2300 movs r3, #0 +100016aa: 8adb ldrh r3, [r3, #22] +100016ac: 2200 movs r2, #0 +100016ae: e842 f200 tt r2, r2 +100016b2: 0252 lsls r2, r2, #9 +100016b4: d401 bmi.n 100016ba +100016b6: 2110 movs r1, #16 +100016b8: 4718 bx r3 +100016ba: 2104 movs r1, #4 +100016bc: 4718 bx r3 +100016be: bf00 nop + +100016c0 : +100016c0: 2800 cmp r0, #0 +100016c2: b508 push {r3, lr} +100016c4: db0e blt.n 100016e4 +100016c6: b952 cbnz r2, 100016de +100016c8: f041 0120 orr.w r1, r1, #32 +100016cc: 2300 movs r3, #0 +100016ce: 7cdb ldrb r3, [r3, #19] +100016d0: 2b02 cmp r3, #2 +100016d2: d00a beq.n 100016ea +100016d4: 4602 mov r2, r0 +100016d6: f44f 7081 mov.w r0, #258 @ 0x102 +100016da: f7ff ffc7 bl 1000166c +100016de: f041 0130 orr.w r1, r1, #48 @ 0x30 +100016e2: e7f3 b.n 100016cc +100016e4: 068b lsls r3, r1, #26 +100016e6: d5f5 bpl.n 100016d4 +100016e8: e7f0 b.n 100016cc +100016ea: 4602 mov r2, r0 +100016ec: f44f 7091 mov.w r0, #290 @ 0x122 +100016f0: f7ff ffbc bl 1000166c + +100016f4 : +100016f4: 4a03 ldr r2, [pc, #12] @ (10001704 ) +100016f6: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100016fa: 2b00 cmp r3, #0 +100016fc: d0fb beq.n 100016f6 +100016fe: f3bf 8f5f dmb sy +10001702: 4770 bx lr +10001704: 400e0000 .word 0x400e0000 + +10001708 : +10001708: 2100 movs r1, #0 +1000170a: 4b04 ldr r3, [pc, #16] @ (1000171c ) +1000170c: 4a04 ldr r2, [pc, #16] @ (10001720 ) +1000170e: f3bf 8f5f dmb sy +10001712: f843 1b04 str.w r1, [r3], #4 +10001716: 4293 cmp r3, r2 +10001718: d1f9 bne.n 1000170e +1000171a: 4770 bx lr +1000171c: 400e080c .word 0x400e080c +10001720: 400e082c .word 0x400e082c + +10001724 : +10001724: f44f 6c2a mov.w ip, #2720 @ 0xaa0 +10001728: f44f 708d mov.w r0, #282 @ 0x11a +1000172c: 4a05 ldr r2, [pc, #20] @ (10001744 ) +1000172e: 4b06 ldr r3, [pc, #24] @ (10001748 ) +10001730: 4906 ldr r1, [pc, #24] @ (1000174c ) +10001732: f8c2 c000 str.w ip, [r2] +10001736: 60d0 str r0, [r2, #12] +10001738: 6019 str r1, [r3, #0] +1000173a: 6853 ldr r3, [r2, #4] +1000173c: 2b00 cmp r3, #0 +1000173e: dafc bge.n 1000173a +10001740: 4770 bx lr +10001742: bf00 nop +10001744: 40048000 .word 0x40048000 +10001748: 4004a000 .word 0x4004a000 +1000174c: 00fab000 .word 0x00fab000 + +10001750 : +10001750: 4770 bx lr +10001752: bf00 nop + +10001754 : +10001754: b508 push {r3, lr} +10001756: 4801 ldr r0, [pc, #4] @ (1000175c ) +10001758: f7fe fef8 bl 1000054c +1000175c: 1000c61c .word 0x1000c61c + +10001760 : +10001760: b538 push {r3, r4, r5, lr} +10001762: 4c05 ldr r4, [pc, #20] @ (10001778 ) +10001764: 4d05 ldr r5, [pc, #20] @ (1000177c ) +10001766: 42ac cmp r4, r5 +10001768: d204 bcs.n 10001774 +1000176a: f854 3b04 ldr.w r3, [r4], #4 +1000176e: 4798 blx r3 +10001770: 42ac cmp r4, r5 +10001772: d3fa bcc.n 1000176a +10001774: bd38 pop {r3, r4, r5, pc} +10001776: bf00 nop +10001778: 1000c3c8 .word 0x1000c3c8 +1000177c: 1000c408 .word 0x1000c408 + +10001780 : +10001780: 4806 ldr r0, [pc, #24] @ (1000179c ) +10001782: f8df c028 ldr.w ip, [pc, #40] @ 100017ac +10001786: 4b06 ldr r3, [pc, #24] @ (100017a0 ) +10001788: 4a06 ldr r2, [pc, #24] @ (100017a4 ) +1000178a: 4907 ldr r1, [pc, #28] @ (100017a8 ) +1000178c: f8c0 c000 str.w ip, [r0] +10001790: 601a str r2, [r3, #0] +10001792: 688b ldr r3, [r1, #8] +10001794: ea32 0303 bics.w r3, r2, r3 +10001798: d1fb bne.n 10001792 +1000179a: 4770 bx lr +1000179c: 40022000 .word 0x40022000 +100017a0: 40023000 .word 0x40023000 +100017a4: 03f3fff6 .word 0x03f3fff6 +100017a8: 40020000 .word 0x40020000 +100017ac: efef3b7f .word 0xefef3b7f + +100017b0 : +100017b0: 4b04 ldr r3, [pc, #16] @ (100017c4 ) +100017b2: 6cdb ldr r3, [r3, #76] @ 0x4c +100017b4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100017b8: d103 bne.n 100017c2 +100017ba: f44f 2280 mov.w r2, #262144 @ 0x40000 +100017be: 4b02 ldr r3, [pc, #8] @ (100017c8 ) +100017c0: 64da str r2, [r3, #76] @ 0x4c +100017c2: 4770 bx lr +100017c4: 50110000 .word 0x50110000 +100017c8: 50112000 .word 0x50112000 + +100017cc : +100017cc: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100017d0: 4b04 ldr r3, [pc, #16] @ (100017e4 ) +100017d2: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100017d6: 430b orrs r3, r1 +100017d8: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100017dc: ee10 0430 dcp_rcmp r0 +100017e0: 4770 bx lr +100017e2: bf00 nop +100017e4: 00300303 .word 0x00300303 + +100017e8 : +100017e8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100017ec: 4b04 ldr r3, [pc, #16] @ (10001800 ) +100017ee: 4a05 ldr r2, [pc, #20] @ (10001804 ) +100017f0: 6019 str r1, [r3, #0] +100017f2: 6893 ldr r3, [r2, #8] +100017f4: 43db mvns r3, r3 +100017f6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100017fa: d1fa bne.n 100017f2 +100017fc: 4770 bx lr +100017fe: bf00 nop +10001800: 40023000 .word 0x40023000 +10001804: 40020000 .word 0x40020000 + +10001808 : +10001808: b510 push {r4, lr} +1000180a: f245 2053 movw r0, #21075 @ 0x5253 +1000180e: f7ff ff4b bl 100016a8 +10001812: e8bd 4010 ldmia.w sp!, {r4, lr} +10001816: 4603 mov r3, r0 +10001818: 2004 movs r0, #4 +1000181a: 4718 bx r3 + +1000181c : +1000181c: b510 push {r4, lr} +1000181e: f245 2053 movw r0, #21075 @ 0x5253 +10001822: f7ff ff41 bl 100016a8 +10001826: e8bd 4010 ldmia.w sp!, {r4, lr} +1000182a: 4603 mov r3, r0 +1000182c: 2001 movs r0, #1 +1000182e: 4718 bx r3 + +10001830 : +10001830: f7fe bf38 b.w 100006a4 + +10001834 : +10001834: 4913 ldr r1, [pc, #76] @ (10001884 ) +10001836: 4b14 ldr r3, [pc, #80] @ (10001888 ) +10001838: b570 push {r4, r5, r6, lr} +1000183a: 1a5c subs r4, r3, r1 +1000183c: 08a5 lsrs r5, r4, #2 +1000183e: 2d44 cmp r5, #68 @ 0x44 +10001840: 462a mov r2, r5 +10001842: bf28 it cs +10001844: 2244 movcs r2, #68 @ 0x44 +10001846: 4e11 ldr r6, [pc, #68] @ (1000188c ) +10001848: 0092 lsls r2, r2, #2 +1000184a: 4630 mov r0, r6 +1000184c: f00a fb96 bl 1000bf7c +10001850: 2d43 cmp r5, #67 @ 0x43 +10001852: d813 bhi.n 1000187c +10001854: 4a0e ldr r2, [pc, #56] @ (10001890 ) +10001856: d00f beq.n 10001878 +10001858: f1c5 0044 rsb r0, r5, #68 @ 0x44 +1000185c: 1933 adds r3, r6, r4 +1000185e: 0841 lsrs r1, r0, #1 +10001860: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001864: e9c3 2200 strd r2, r2, [r3] +10001868: 3308 adds r3, #8 +1000186a: 428b cmp r3, r1 +1000186c: d1fa bne.n 10001864 +1000186e: 07c3 lsls r3, r0, #31 +10001870: d504 bpl.n 1000187c +10001872: f020 0001 bic.w r0, r0, #1 +10001876: 4405 add r5, r0 +10001878: f846 2025 str.w r2, [r6, r5, lsl #2] +1000187c: 4b05 ldr r3, [pc, #20] @ (10001894 ) +1000187e: 609e str r6, [r3, #8] +10001880: bd70 pop {r4, r5, r6, pc} +10001882: bf00 nop +10001884: 10000000 .word 0x10000000 +10001888: 10000110 .word 0x10000110 +1000188c: 20000000 .word 0x20000000 +10001890: 10000111 .word 0x10000111 +10001894: e000ed00 .word 0xe000ed00 + +10001898 : +10001898: 2300 movs r3, #0 +1000189a: b570 push {r4, r5, r6, lr} +1000189c: 4c2b ldr r4, [pc, #172] @ (1000194c ) +1000189e: b082 sub sp, #8 +100018a0: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100018a4: f7ff ff3e bl 10001724 +100018a8: 2201 movs r2, #1 +100018aa: 4b29 ldr r3, [pc, #164] @ (10001950 ) +100018ac: 63da str r2, [r3, #60] @ 0x3c +100018ae: 6c63 ldr r3, [r4, #68] @ 0x44 +100018b0: 2b01 cmp r3, #1 +100018b2: d1fc bne.n 100018ae +100018b4: 2103 movs r1, #3 +100018b6: 4a26 ldr r2, [pc, #152] @ (10001950 ) +100018b8: 4b24 ldr r3, [pc, #144] @ (1000194c ) +100018ba: 6311 str r1, [r2, #48] @ 0x30 +100018bc: 6b9c ldr r4, [r3, #56] @ 0x38 +100018be: 2c01 cmp r4, #1 +100018c0: d1fc bne.n 100018bc +100018c2: 2602 movs r6, #2 +100018c4: 2505 movs r5, #5 +100018c6: 4621 mov r1, r4 +100018c8: 2305 movs r3, #5 +100018ca: 4a22 ldr r2, [pc, #136] @ (10001954 ) +100018cc: 4822 ldr r0, [pc, #136] @ (10001958 ) +100018ce: 9600 str r6, [sp, #0] +100018d0: f7ff fe22 bl 10001518 +100018d4: 4621 mov r1, r4 +100018d6: 462b mov r3, r5 +100018d8: 4a20 ldr r2, [pc, #128] @ (1000195c ) +100018da: 4821 ldr r0, [pc, #132] @ (10001960 ) +100018dc: 9500 str r5, [sp, #0] +100018de: f7ff fe1b bl 10001518 +100018e2: 2200 movs r2, #0 +100018e4: 2004 movs r0, #4 +100018e6: 4631 mov r1, r6 +100018e8: 4b1e ldr r3, [pc, #120] @ (10001964 ) +100018ea: f7ff fda1 bl 10001430 +100018ee: 4621 mov r1, r4 +100018f0: 4628 mov r0, r5 +100018f2: 2200 movs r2, #0 +100018f4: 4b1c ldr r3, [pc, #112] @ (10001968 ) +100018f6: f7ff fd9b bl 10001430 +100018fa: 2200 movs r2, #0 +100018fc: 2008 movs r0, #8 +100018fe: 4611 mov r1, r2 +10001900: 4b1a ldr r3, [pc, #104] @ (1000196c ) +10001902: f7ff fd95 bl 10001430 +10001906: 2200 movs r2, #0 +10001908: 2009 movs r0, #9 +1000190a: 4611 mov r1, r2 +1000190c: 4b17 ldr r3, [pc, #92] @ (1000196c ) +1000190e: f7ff fd8f bl 10001430 +10001912: 2200 movs r2, #0 +10001914: 2006 movs r0, #6 +10001916: 4611 mov r1, r2 +10001918: 4b13 ldr r3, [pc, #76] @ (10001968 ) +1000191a: f7ff fd89 bl 10001430 +1000191e: 2200 movs r2, #0 +10001920: 4b11 ldr r3, [pc, #68] @ (10001968 ) +10001922: 2007 movs r0, #7 +10001924: 4611 mov r1, r2 +10001926: f7ff fd83 bl 10001430 +1000192a: 2004 movs r0, #4 +1000192c: f7ff fdee bl 1000150c +10001930: 2400 movs r4, #0 +10001932: 4b0f ldr r3, [pc, #60] @ (10001970 ) +10001934: fba3 3500 umull r3, r5, r3, r0 +10001938: 0cad lsrs r5, r5, #18 +1000193a: b2e0 uxtb r0, r4 +1000193c: 4629 mov r1, r5 +1000193e: 3401 adds r4, #1 +10001940: f7ff fe88 bl 10001654 +10001944: 2c06 cmp r4, #6 +10001946: d1f8 bne.n 1000193a +10001948: b002 add sp, #8 +1000194a: bd70 pop {r4, r5, r6, pc} +1000194c: 40010000 .word 0x40010000 +10001950: 40013000 .word 0x40013000 +10001954: 59682f00 .word 0x59682f00 +10001958: 40050000 .word 0x40050000 +1000195c: 47868c00 .word 0x47868c00 +10001960: 40058000 .word 0x40058000 +10001964: 00b71b00 .word 0x00b71b00 +10001968: 08f0d180 .word 0x08f0d180 +1000196c: 02dc6c00 .word 0x02dc6c00 +10001970: 431bde83 .word 0x431bde83 + +10001974 : +10001974: b086 sub sp, #24 +10001976: b403 push {r0, r1} +10001978: fc51 0408 dcp_pxmd r0, r1 +1000197c: e9cd 0102 strd r0, r1, [sp, #8] +10001980: fc51 0409 dcp_pymd r0, r1 +10001984: e9cd 0104 strd r0, r1, [sp, #16] +10001988: ec51 040a dcp_refd r0, r1 +1000198c: e9cd 0106 strd r0, r1, [sp, #24] +10001990: bc03 pop {r0, r1} +10001992: 47f0 blx lr + +10001994 : +10001994: e8bd 5000 ldmia.w sp!, {ip, lr} +10001998: ec4e c400 dcp_wxmd ip, lr +1000199c: e8bd 5000 ldmia.w sp!, {ip, lr} +100019a0: ec4e c401 dcp_wymd ip, lr +100019a4: e8bd 5000 ldmia.w sp!, {ip, lr} +100019a8: ec4e c402 dcp_wefd ip, lr +100019ac: bd00 pop {pc} +100019ae: 0000 movs r0, r0 +100019b0: b500 push {lr} +100019b2: f7ff ffdf bl 10001974 +100019b6: e002 b.n 100019be <__wrap___aeabi_dadd+0x6> + +100019b8 <__wrap___aeabi_dadd>: +100019b8: fe10 f430 dcp_pcmp APSR_nzcv +100019bc: d4f8 bmi.n 100019b0 +100019be: ec41 0410 dcp_wxup r0, r1 +100019c2: ec43 2411 dcp_wyup r2, r3 +100019c6: ee00 0401 dcp_add0 +100019ca: ee10 0401 dcp_add1 +100019ce: ee80 0420 dcp_nrdd +100019d2: ec51 0410 dcp_rdda r0, r1 +100019d6: 4770 bx lr +100019d8: b500 push {lr} +100019da: f7ff ffcb bl 10001974 +100019de: e002 b.n 100019e6 <__wrap___aeabi_dsub+0x6> + +100019e0 <__wrap___aeabi_dsub>: +100019e0: fe10 f430 dcp_pcmp APSR_nzcv +100019e4: d4f8 bmi.n 100019d8 <__wrap___aeabi_dadd+0x20> +100019e6: ec41 0410 dcp_wxup r0, r1 +100019ea: ec43 2411 dcp_wyup r2, r3 +100019ee: ee00 0401 dcp_add0 +100019f2: ee10 0421 dcp_sub1 +100019f6: ee80 0420 dcp_nrdd +100019fa: ec51 0430 dcp_rdds r0, r1 +100019fe: 4770 bx lr +10001a00: b500 push {lr} +10001a02: f7ff ffb7 bl 10001974 +10001a06: e002 b.n 10001a0e <__wrap___aeabi_dmul+0x6> + +10001a08 <__wrap___aeabi_dmul>: +10001a08: fe10 f430 dcp_pcmp APSR_nzcv +10001a0c: d4f8 bmi.n 10001a00 <__wrap___aeabi_dsub+0x20> +10001a0e: b510 push {r4, lr} +10001a10: ec41 0410 dcp_wxup r0, r1 +10001a14: ec43 2411 dcp_wyup r2, r3 +10001a18: ec51 0404 dcp_rxms r0, r1, #0x0 +10001a1c: ec53 2405 dcp_ryms r2, r3, #0x0 +10001a20: fba0 4c02 umull r4, ip, r0, r2 +10001a24: f05f 0e00 movs.w lr, #0 +10001a28: fbe0 ce03 umlal ip, lr, r0, r3 +10001a2c: fbe1 ce02 umlal ip, lr, r1, r2 +10001a30: ec4c 4420 dcp_wxms r4, ip +10001a34: 2400 movs r4, #0 +10001a36: fbe1 e403 umlal lr, r4, r1, r3 +10001a3a: ec44 e430 dcp_wxmo lr, r4 +10001a3e: ee80 0420 dcp_nrdd +10001a42: ec51 0450 dcp_rddm r0, r1 +10001a46: bd10 pop {r4, pc} +10001a48: b500 push {lr} +10001a4a: f7ff ff93 bl 10001974 +10001a4e: e002 b.n 10001a56 <__wrap___aeabi_ddiv+0x6> + +10001a50 <__wrap___aeabi_ddiv>: +10001a50: fe10 f430 dcp_pcmp APSR_nzcv +10001a54: d4f8 bmi.n 10001a48 <__wrap___aeabi_dmul+0x40> +10001a56: ec41 0410 dcp_wxup r0, r1 +10001a5a: ec43 2411 dcp_wyup r2, r3 +10001a5e: ec51 0421 dcp_rymr r0, r1 +10001a62: fba0 1201 umull r1, r2, r0, r1 +10001a66: ea6f 0282 mvn.w r2, r2, lsl #2 +10001a6a: fb52 0010 smmlar r0, r2, r0, r0 +10001a6e: fb52 f212 smmulr r2, r2, r2 +10001a72: fb52 0010 smmlar r0, r2, r0, r0 +10001a76: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001a7a: ec53 2404 dcp_rxms r2, r3, #0x0 +10001a7e: fb5c f113 smmulr r1, ip, r3 +10001a82: ec53 2415 dcp_ryms r2, r3, #0x1 +10001a86: fba1 2002 umull r2, r0, r1, r2 +10001a8a: fb01 0003 mla r0, r1, r3, r0 +10001a8e: ec53 2444 dcp_rxms r2, r3, #0x4 +10001a92: eba2 0000 sub.w r0, r2, r0 +10001a96: fb50 f21c smmulr r2, r0, ip +10001a9a: ea4f 1311 mov.w r3, r1, lsr #4 +10001a9e: eb12 7001 adds.w r0, r2, r1, lsl #28 +10001aa2: eb43 71e2 adc.w r1, r3, r2, asr #31 +10001aa6: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001aaa: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001aae: f020 0007 bic.w r0, r0, #7 +10001ab2: ec53 2475 dcp_ryms r2, r3, #0x7 +10001ab6: fba0 3c02 umull r3, ip, r0, r2 +10001aba: ec53 2475 dcp_ryms r2, r3, #0x7 +10001abe: fb00 cc03 mla ip, r0, r3, ip +10001ac2: fb01 cc02 mla ip, r1, r2, ip +10001ac6: ec53 2404 dcp_rxms r2, r3, #0x0 +10001aca: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001ace: ea40 705c orr.w r0, r0, ip, lsr #29 +10001ad2: f1a0 0001 sub.w r0, r0, #1 +10001ad6: ec41 0440 dcp_wxdd r0, r1 +10001ada: ee80 0420 dcp_nrdd +10001ade: ec51 0470 dcp_rddd r0, r1 +10001ae2: 4770 bx lr +10001ae4: b500 push {lr} +10001ae6: f7ff ff45 bl 10001974 +10001aea: e002 b.n 10001af2 <__wrap___aeabi_i2d+0x6> + +10001aec <__wrap___aeabi_i2d>: +10001aec: fe10 f430 dcp_pcmp APSR_nzcv +10001af0: d4f8 bmi.n 10001ae4 <__wrap___aeabi_ddiv+0x94> +10001af2: ec40 0470 dcp_wxic r0, r0 +10001af6: ee00 0401 dcp_add0 +10001afa: ee10 0421 dcp_sub1 +10001afe: ee80 0420 dcp_nrdd +10001b02: ec51 0430 dcp_rdds r0, r1 +10001b06: 4770 bx lr +10001b08: b500 push {lr} +10001b0a: f7ff ff33 bl 10001974 +10001b0e: e002 b.n 10001b16 <__wrap___aeabi_ui2d+0x6> + +10001b10 <__wrap___aeabi_ui2d>: +10001b10: fe10 f430 dcp_pcmp APSR_nzcv +10001b14: d4f8 bmi.n 10001b08 <__wrap___aeabi_i2d+0x1c> +10001b16: ec40 0460 dcp_wxuc r0, r0 +10001b1a: ee00 0401 dcp_add0 +10001b1e: ee10 0421 dcp_sub1 +10001b22: ee80 0420 dcp_nrdd +10001b26: ec51 0430 dcp_rdds r0, r1 +10001b2a: 4770 bx lr +10001b2c: b500 push {lr} +10001b2e: f7ff ff21 bl 10001974 +10001b32: e002 b.n 10001b3a + +10001b34 <__wrap___aeabi_d2iz>: +10001b34: fe10 f430 dcp_pcmp APSR_nzcv +10001b38: d4f8 bmi.n 10001b2c <__wrap___aeabi_ui2d+0x1c> + +10001b3a : +10001b3a: ec41 0480 dcp_wxdc r0, r1 +10001b3e: ee00 0401 dcp_add0 +10001b42: ee10 0401 dcp_add1 +10001b46: ee80 0440 dcp_ntdc +10001b4a: ee10 0413 dcp_rdic r0 +10001b4e: 4770 bx lr +10001b50: b500 push {lr} +10001b52: f7ff ff0f bl 10001974 +10001b56: e002 b.n 10001b5e + +10001b58 <__wrap___aeabi_d2uiz>: +10001b58: fe10 f430 dcp_pcmp APSR_nzcv +10001b5c: d4f8 bmi.n 10001b50 + +10001b5e : +10001b5e: ec41 0480 dcp_wxdc r0, r1 +10001b62: ee00 0401 dcp_add0 +10001b66: ee10 0401 dcp_add1 +10001b6a: ee80 0440 dcp_ntdc +10001b6e: ee10 0433 dcp_rduc r0 +10001b72: 4770 bx lr +10001b74: b500 push {lr} +10001b76: f7ff fefd bl 10001974 +10001b7a: e002 b.n 10001b82 <__wrap___aeabi_dcmpun+0x6> + +10001b7c <__wrap___aeabi_dcmpun>: +10001b7c: fe10 f430 dcp_pcmp APSR_nzcv +10001b80: d4f8 bmi.n 10001b74 +10001b82: ec41 0410 dcp_wxup r0, r1 +10001b86: ec43 2411 dcp_wyup r2, r3 +10001b8a: ee00 0401 dcp_add0 +10001b8e: ee10 0430 dcp_rcmp r0 +10001b92: f3c0 7000 ubfx r0, r0, #28, #1 +10001b96: 4770 bx lr +10001b98: b500 push {lr} +10001b9a: f7ff feeb bl 10001974 +10001b9e: e002 b.n 10001ba6 <__wrap___aeabi_dcmplt+0x6> + +10001ba0 <__wrap___aeabi_dcmplt>: +10001ba0: fe10 f430 dcp_pcmp APSR_nzcv +10001ba4: d4f8 bmi.n 10001b98 <__wrap___aeabi_dcmpun+0x1c> +10001ba6: ec43 2410 dcp_wxup r2, r3 +10001baa: ec41 0411 dcp_wyup r0, r1 +10001bae: ee00 0401 dcp_add0 +10001bb2: ee10 f430 dcp_rcmp APSR_nzcv +10001bb6: bf8c ite hi +10001bb8: 2001 movhi r0, #1 +10001bba: 2000 movls r0, #0 +10001bbc: 4770 bx lr +10001bbe: bf00 nop +10001bc0: b500 push {lr} +10001bc2: f7ff fed7 bl 10001974 +10001bc6: e002 b.n 10001bce <__wrap___aeabi_dcmple+0x6> + +10001bc8 <__wrap___aeabi_dcmple>: +10001bc8: fe10 f430 dcp_pcmp APSR_nzcv +10001bcc: d4f8 bmi.n 10001bc0 <__wrap___aeabi_dcmplt+0x20> +10001bce: ec43 2410 dcp_wxup r2, r3 +10001bd2: ec41 0411 dcp_wyup r0, r1 +10001bd6: ee00 0401 dcp_add0 +10001bda: ee10 f430 dcp_rcmp APSR_nzcv +10001bde: bf2c ite cs +10001be0: 2001 movcs r0, #1 +10001be2: 2000 movcc r0, #0 +10001be4: 4770 bx lr +10001be6: bf00 nop +10001be8: b500 push {lr} +10001bea: f7ff fec3 bl 10001974 +10001bee: e002 b.n 10001bf6 <__wrap___aeabi_dcmpge+0x6> + +10001bf0 <__wrap___aeabi_dcmpge>: +10001bf0: fe10 f430 dcp_pcmp APSR_nzcv +10001bf4: d4f8 bmi.n 10001be8 <__wrap___aeabi_dcmple+0x20> +10001bf6: ec41 0410 dcp_wxup r0, r1 +10001bfa: ec43 2411 dcp_wyup r2, r3 +10001bfe: ee00 0401 dcp_add0 +10001c02: ee10 f430 dcp_rcmp APSR_nzcv +10001c06: bf2c ite cs +10001c08: 2001 movcs r0, #1 +10001c0a: 2000 movcc r0, #0 +10001c0c: 4770 bx lr +10001c0e: bf00 nop +10001c10: b500 push {lr} +10001c12: f7ff feaf bl 10001974 +10001c16: e002 b.n 10001c1e <__wrap___aeabi_dcmpgt+0x6> + +10001c18 <__wrap___aeabi_dcmpgt>: +10001c18: fe10 f430 dcp_pcmp APSR_nzcv +10001c1c: d4f8 bmi.n 10001c10 <__wrap___aeabi_dcmpge+0x20> +10001c1e: ec41 0410 dcp_wxup r0, r1 +10001c22: ec43 2411 dcp_wyup r2, r3 +10001c26: ee00 0401 dcp_add0 +10001c2a: ee10 f430 dcp_rcmp APSR_nzcv +10001c2e: bf8c ite hi +10001c30: 2001 movhi r0, #1 +10001c32: 2000 movls r0, #0 +10001c34: 4770 bx lr +10001c36: bf00 nop + +10001c38 <__wrap_malloc>: +10001c38: b510 push {r4, lr} +10001c3a: 4604 mov r4, r0 +10001c3c: f009 fdc6 bl 1000b7cc +10001c40: b120 cbz r0, 10001c4c <__wrap_malloc+0x14> +10001c42: 4a04 ldr r2, [pc, #16] @ (10001c54 <__wrap_malloc+0x1c>) +10001c44: 1903 adds r3, r0, r4 +10001c46: 4293 cmp r3, r2 +10001c48: d800 bhi.n 10001c4c <__wrap_malloc+0x14> +10001c4a: bd10 pop {r4, pc} +10001c4c: 4802 ldr r0, [pc, #8] @ (10001c58 <__wrap_malloc+0x20>) +10001c4e: f7fe fc7d bl 1000054c +10001c52: bf00 nop +10001c54: 20080000 .word 0x20080000 +10001c58: 1000c628 .word 0x1000c628 + +10001c5c <__wrap_free>: +10001c5c: f009 bdbe b.w 1000b7dc + +10001c60 <_out_buffer>: +10001c60: 429a cmp r2, r3 +10001c62: bf38 it cc +10001c64: 5488 strbcc r0, [r1, r2] +10001c66: 4770 bx lr + +10001c68 <_out_null>: +10001c68: 4770 bx lr +10001c6a: bf00 nop + +10001c6c <_out_rev>: +10001c6c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c70: b083 sub sp, #12 +10001c72: 460f mov r7, r1 +10001c74: 4611 mov r1, r2 +10001c76: e9dd b20e ldrd fp, r2, [sp, #56] @ 0x38 +10001c7a: 0792 lsls r2, r2, #30 +10001c7c: 4698 mov r8, r3 +10001c7e: e9dd 930c ldrd r9, r3, [sp, #48] @ 0x30 +10001c82: 4606 mov r6, r0 +10001c84: d029 beq.n 10001cda <_out_rev+0x6e> +10001c86: 460d mov r5, r1 +10001c88: b19b cbz r3, 10001cb2 <_out_rev+0x46> +10001c8a: eb09 0403 add.w r4, r9, r3 +10001c8e: eb05 0a04 add.w sl, r5, r4 +10001c92: 9501 str r5, [sp, #4] +10001c94: 460d mov r5, r1 +10001c96: 930d str r3, [sp, #52] @ 0x34 +10001c98: ebaa 0204 sub.w r2, sl, r4 +10001c9c: f814 0d01 ldrb.w r0, [r4, #-1]! +10001ca0: 4643 mov r3, r8 +10001ca2: 4639 mov r1, r7 +10001ca4: 47b0 blx r6 +10001ca6: 45a1 cmp r9, r4 +10001ca8: d1f6 bne.n 10001c98 <_out_rev+0x2c> +10001caa: 4629 mov r1, r5 +10001cac: 9b0d ldr r3, [sp, #52] @ 0x34 +10001cae: 9d01 ldr r5, [sp, #4] +10001cb0: 441d add r5, r3 +10001cb2: 9b0f ldr r3, [sp, #60] @ 0x3c +10001cb4: 079b lsls r3, r3, #30 +10001cb6: d50c bpl.n 10001cd2 <_out_rev+0x66> +10001cb8: 1a6c subs r4, r5, r1 +10001cba: 45a3 cmp fp, r4 +10001cbc: d909 bls.n 10001cd2 <_out_rev+0x66> +10001cbe: 462a mov r2, r5 +10001cc0: 4643 mov r3, r8 +10001cc2: 4639 mov r1, r7 +10001cc4: 2020 movs r0, #32 +10001cc6: 3401 adds r4, #1 +10001cc8: 47b0 blx r6 +10001cca: 455c cmp r4, fp +10001ccc: f105 0501 add.w r5, r5, #1 +10001cd0: d3f5 bcc.n 10001cbe <_out_rev+0x52> +10001cd2: 4628 mov r0, r5 +10001cd4: b003 add sp, #12 +10001cd6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001cda: 455b cmp r3, fp +10001cdc: d215 bcs.n 10001d0a <_out_rev+0x9e> +10001cde: 468a mov sl, r1 +10001ce0: 461c mov r4, r3 +10001ce2: 4689 mov r9, r1 +10001ce4: ebab 0503 sub.w r5, fp, r3 +10001ce8: 440d add r5, r1 +10001cea: 4652 mov r2, sl +10001cec: 4643 mov r3, r8 +10001cee: 4639 mov r1, r7 +10001cf0: 2020 movs r0, #32 +10001cf2: f10a 0a01 add.w sl, sl, #1 +10001cf6: 47b0 blx r6 +10001cf8: 45aa cmp sl, r5 +10001cfa: d1f6 bne.n 10001cea <_out_rev+0x7e> +10001cfc: 4649 mov r1, r9 +10001cfe: 4623 mov r3, r4 +10001d00: f8dd 9030 ldr.w r9, [sp, #48] @ 0x30 +10001d04: 2c00 cmp r4, #0 +10001d06: d1c0 bne.n 10001c8a <_out_rev+0x1e> +10001d08: e7e3 b.n 10001cd2 <_out_rev+0x66> +10001d0a: 460d mov r5, r1 +10001d0c: 2b00 cmp r3, #0 +10001d0e: d1bc bne.n 10001c8a <_out_rev+0x1e> +10001d10: e7df b.n 10001cd2 <_out_rev+0x66> +10001d12: bf00 nop + +10001d14 <_ntoa_format>: +10001d14: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001d18: 460f mov r7, r1 +10001d1a: 990f ldr r1, [sp, #60] @ 0x3c +10001d1c: 4606 mov r6, r0 +10001d1e: f89d 002c ldrb.w r0, [sp, #44] @ 0x2c +10001d22: 078d lsls r5, r1, #30 +10001d24: 4690 mov r8, r2 +10001d26: e9dd a20c ldrd sl, r2, [sp, #48] @ 0x30 +10001d2a: 4699 mov r9, r3 +10001d2c: 4683 mov fp, r0 +10001d2e: 9c09 ldr r4, [sp, #36] @ 0x24 +10001d30: f8dd c028 ldr.w ip, [sp, #40] @ 0x28 +10001d34: 9b0e ldr r3, [sp, #56] @ 0x38 +10001d36: d449 bmi.n 10001dcc <_ntoa_format+0xb8> +10001d38: 2b00 cmp r3, #0 +10001d3a: d142 bne.n 10001dc2 <_ntoa_format+0xae> +10001d3c: 4594 cmp ip, r2 +10001d3e: d245 bcs.n 10001dcc <_ntoa_format+0xb8> +10001d40: f001 0501 and.w r5, r1, #1 +10001d44: f104 3eff add.w lr, r4, #4294967295 @ 0xffffffff +10001d48: 2030 movs r0, #48 @ 0x30 +10001d4a: 44e6 add lr, ip +10001d4c: e005 b.n 10001d5a <_ntoa_format+0x46> +10001d4e: f10c 0c01 add.w ip, ip, #1 +10001d52: 4562 cmp r2, ip +10001d54: f80e 0f01 strb.w r0, [lr, #1]! +10001d58: d902 bls.n 10001d60 <_ntoa_format+0x4c> +10001d5a: f1bc 0f20 cmp.w ip, #32 +10001d5e: d1f6 bne.n 10001d4e <_ntoa_format+0x3a> +10001d60: 2d00 cmp r5, #0 +10001d62: f000 8087 beq.w 10001e74 <_ntoa_format+0x160> +10001d66: 4563 cmp r3, ip +10001d68: d930 bls.n 10001dcc <_ntoa_format+0xb8> +10001d6a: 1e60 subs r0, r4, #1 +10001d6c: f04f 0e30 mov.w lr, #48 @ 0x30 +10001d70: 4460 add r0, ip +10001d72: e005 b.n 10001d80 <_ntoa_format+0x6c> +10001d74: f10c 0c01 add.w ip, ip, #1 +10001d78: 459c cmp ip, r3 +10001d7a: f800 ef01 strb.w lr, [r0, #1]! +10001d7e: d025 beq.n 10001dcc <_ntoa_format+0xb8> +10001d80: f1bc 0f20 cmp.w ip, #32 +10001d84: d1f6 bne.n 10001d74 <_ntoa_format+0x60> +10001d86: 06cd lsls r5, r1, #27 +10001d88: d50e bpl.n 10001da8 <_ntoa_format+0x94> +10001d8a: 0548 lsls r0, r1, #21 +10001d8c: d451 bmi.n 10001e32 <_ntoa_format+0x11e> +10001d8e: 4562 cmp r2, ip +10001d90: d064 beq.n 10001e5c <_ntoa_format+0x148> +10001d92: 4563 cmp r3, ip +10001d94: d062 beq.n 10001e5c <_ntoa_format+0x148> +10001d96: f1ba 0f10 cmp.w sl, #16 +10001d9a: d04d beq.n 10001e38 <_ntoa_format+0x124> +10001d9c: f1ba 0f02 cmp.w sl, #2 +10001da0: d055 beq.n 10001e4e <_ntoa_format+0x13a> +10001da2: f1bc 0f20 cmp.w ip, #32 +10001da6: d12d bne.n 10001e04 <_ntoa_format+0xf0> +10001da8: 2220 movs r2, #32 +10001daa: e9cd 310b strd r3, r1, [sp, #44] @ 0x2c +10001dae: 920a str r2, [sp, #40] @ 0x28 +10001db0: 464b mov r3, r9 +10001db2: 4642 mov r2, r8 +10001db4: 4639 mov r1, r7 +10001db6: 4630 mov r0, r6 +10001db8: 9409 str r4, [sp, #36] @ 0x24 +10001dba: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001dbe: f7ff bf55 b.w 10001c6c <_out_rev> +10001dc2: f011 0501 ands.w r5, r1, #1 +10001dc6: d12e bne.n 10001e26 <_ntoa_format+0x112> +10001dc8: 4594 cmp ip, r2 +10001dca: d3bb bcc.n 10001d44 <_ntoa_format+0x30> +10001dcc: 06cd lsls r5, r1, #27 +10001dce: d51e bpl.n 10001e0e <_ntoa_format+0xfa> +10001dd0: 0548 lsls r0, r1, #21 +10001dd2: d4e0 bmi.n 10001d96 <_ntoa_format+0x82> +10001dd4: f1bc 0f00 cmp.w ip, #0 +10001dd8: d1d9 bne.n 10001d8e <_ntoa_format+0x7a> +10001dda: f1ba 0f10 cmp.w sl, #16 +10001dde: d05f beq.n 10001ea0 <_ntoa_format+0x18c> +10001de0: f1ba 0f02 cmp.w sl, #2 +10001de4: d074 beq.n 10001ed0 <_ntoa_format+0x1bc> +10001de6: 2230 movs r2, #48 @ 0x30 +10001de8: f04f 0c01 mov.w ip, #1 +10001dec: 7022 strb r2, [r4, #0] +10001dee: f1bb 0f00 cmp.w fp, #0 +10001df2: d112 bne.n 10001e1a <_ntoa_format+0x106> +10001df4: 0748 lsls r0, r1, #29 +10001df6: d542 bpl.n 10001e7e <_ntoa_format+0x16a> +10001df8: 222b movs r2, #43 @ 0x2b +10001dfa: f804 200c strb.w r2, [r4, ip] +10001dfe: f10c 0201 add.w r2, ip, #1 +10001e02: e7d2 b.n 10001daa <_ntoa_format+0x96> +10001e04: 4662 mov r2, ip +10001e06: f10c 0c01 add.w ip, ip, #1 +10001e0a: 2030 movs r0, #48 @ 0x30 +10001e0c: 54a0 strb r0, [r4, r2] +10001e0e: f1bc 0f20 cmp.w ip, #32 +10001e12: d0c9 beq.n 10001da8 <_ntoa_format+0x94> +10001e14: f1bb 0f00 cmp.w fp, #0 +10001e18: d0ec beq.n 10001df4 <_ntoa_format+0xe0> +10001e1a: 222d movs r2, #45 @ 0x2d +10001e1c: f804 200c strb.w r2, [r4, ip] +10001e20: f10c 0201 add.w r2, ip, #1 +10001e24: e7c1 b.n 10001daa <_ntoa_format+0x96> +10001e26: b398 cbz r0, 10001e90 <_ntoa_format+0x17c> +10001e28: 4594 cmp ip, r2 +10001e2a: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff +10001e2e: d389 bcc.n 10001d44 <_ntoa_format+0x30> +10001e30: e799 b.n 10001d66 <_ntoa_format+0x52> +10001e32: f1ba 0f10 cmp.w sl, #16 +10001e36: d1b7 bne.n 10001da8 <_ntoa_format+0x94> +10001e38: 068d lsls r5, r1, #26 +10001e3a: d53d bpl.n 10001eb8 <_ntoa_format+0x1a4> +10001e3c: f1bc 0f20 cmp.w ip, #32 +10001e40: d0b2 beq.n 10001da8 <_ntoa_format+0x94> +10001e42: 2258 movs r2, #88 @ 0x58 +10001e44: f804 200c strb.w r2, [r4, ip] +10001e48: f10c 0c01 add.w ip, ip, #1 +10001e4c: e7a9 b.n 10001da2 <_ntoa_format+0x8e> +10001e4e: f1bc 0f20 cmp.w ip, #32 +10001e52: d0a9 beq.n 10001da8 <_ntoa_format+0x94> +10001e54: 4662 mov r2, ip +10001e56: f10c 0c01 add.w ip, ip, #1 +10001e5a: e008 b.n 10001e6e <_ntoa_format+0x15a> +10001e5c: f1bc 0201 subs.w r2, ip, #1 +10001e60: d0bb beq.n 10001dda <_ntoa_format+0xc6> +10001e62: f1ba 0f10 cmp.w sl, #16 +10001e66: d035 beq.n 10001ed4 <_ntoa_format+0x1c0> +10001e68: f1ba 0f02 cmp.w sl, #2 +10001e6c: d1cd bne.n 10001e0a <_ntoa_format+0xf6> +10001e6e: 2062 movs r0, #98 @ 0x62 +10001e70: 54a0 strb r0, [r4, r2] +10001e72: e796 b.n 10001da2 <_ntoa_format+0x8e> +10001e74: 06cd lsls r5, r1, #27 +10001e76: d5ca bpl.n 10001e0e <_ntoa_format+0xfa> +10001e78: 0548 lsls r0, r1, #21 +10001e7a: d588 bpl.n 10001d8e <_ntoa_format+0x7a> +10001e7c: e78b b.n 10001d96 <_ntoa_format+0x82> +10001e7e: 070a lsls r2, r1, #28 +10001e80: bf49 itett mi +10001e82: 2220 movmi r2, #32 +10001e84: 4662 movpl r2, ip +10001e86: f804 200c strbmi.w r2, [r4, ip] +10001e8a: f10c 0201 addmi.w r2, ip, #1 +10001e8e: e78c b.n 10001daa <_ntoa_format+0x96> +10001e90: f011 0f0c tst.w r1, #12 +10001e94: d000 beq.n 10001e98 <_ntoa_format+0x184> +10001e96: 3b01 subs r3, #1 +10001e98: 4594 cmp ip, r2 +10001e9a: f4ff af53 bcc.w 10001d44 <_ntoa_format+0x30> +10001e9e: e762 b.n 10001d66 <_ntoa_format+0x52> +10001ea0: 068a lsls r2, r1, #26 +10001ea2: d413 bmi.n 10001ecc <_ntoa_format+0x1b8> +10001ea4: 2278 movs r2, #120 @ 0x78 +10001ea6: 7022 strb r2, [r4, #0] +10001ea8: 2230 movs r2, #48 @ 0x30 +10001eaa: f04f 0c02 mov.w ip, #2 +10001eae: 7062 strb r2, [r4, #1] +10001eb0: f1bb 0f00 cmp.w fp, #0 +10001eb4: d09e beq.n 10001df4 <_ntoa_format+0xe0> +10001eb6: e7b0 b.n 10001e1a <_ntoa_format+0x106> +10001eb8: f1bc 0f20 cmp.w ip, #32 +10001ebc: f43f af74 beq.w 10001da8 <_ntoa_format+0x94> +10001ec0: 2278 movs r2, #120 @ 0x78 +10001ec2: f804 200c strb.w r2, [r4, ip] +10001ec6: f10c 0c01 add.w ip, ip, #1 +10001eca: e76a b.n 10001da2 <_ntoa_format+0x8e> +10001ecc: 2258 movs r2, #88 @ 0x58 +10001ece: e7ea b.n 10001ea6 <_ntoa_format+0x192> +10001ed0: 2262 movs r2, #98 @ 0x62 +10001ed2: e7e8 b.n 10001ea6 <_ntoa_format+0x192> +10001ed4: 068d lsls r5, r1, #26 +10001ed6: f1ac 0002 sub.w r0, ip, #2 +10001eda: d504 bpl.n 10001ee6 <_ntoa_format+0x1d2> +10001edc: f04f 0e58 mov.w lr, #88 @ 0x58 +10001ee0: f804 e000 strb.w lr, [r4, r0] +10001ee4: e791 b.n 10001e0a <_ntoa_format+0xf6> +10001ee6: f04f 0e78 mov.w lr, #120 @ 0x78 +10001eea: f804 e000 strb.w lr, [r4, r0] +10001eee: e78c b.n 10001e0a <_ntoa_format+0xf6> + +10001ef0 <_out_char>: +10001ef0: b900 cbnz r0, 10001ef4 <_out_char+0x4> +10001ef2: 4770 bx lr +10001ef4: f001 bc16 b.w 10003724 <__wrap_putchar> + +10001ef8 <_out_fct>: +10001ef8: b110 cbz r0, 10001f00 <_out_fct+0x8> +10001efa: e9d1 3100 ldrd r3, r1, [r1] +10001efe: 4718 bx r3 +10001f00: 4770 bx lr +10001f02: bf00 nop +10001f04: 0000 movs r0, r0 + ... + +10001f08 <_ftoa>: +10001f08: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f0c: b097 sub sp, #92 @ 0x5c +10001f0e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001f12: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001f16: 4680 mov r8, r0 +10001f18: 4689 mov r9, r1 +10001f1a: ec51 0b17 vmov r0, r1, d7 +10001f1e: 469a mov sl, r3 +10001f20: 9b24 ldr r3, [sp, #144] @ 0x90 +10001f22: 920c str r2, [sp, #48] @ 0x30 +10001f24: 9307 str r3, [sp, #28] +10001f26: 4602 mov r2, r0 +10001f28: 460b mov r3, r1 +10001f2a: ed8d 7b04 vstr d7, [sp, #16] +10001f2e: f7ff fe25 bl 10001b7c <__wrap___aeabi_dcmpun> +10001f32: 2800 cmp r0, #0 +10001f34: f040 81e3 bne.w 100022fe <_ftoa+0x3f6> +10001f38: e9dd 0104 ldrd r0, r1, [sp, #16] +10001f3c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001f40: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001f44: f7ff fe2c bl 10001ba0 <__wrap___aeabi_dcmplt> +10001f48: 2800 cmp r0, #0 +10001f4a: f040 80cb bne.w 100020e4 <_ftoa+0x1dc> +10001f4e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001f52: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001f56: 4bb2 ldr r3, [pc, #712] @ (10002220 <_ftoa+0x318>) +10001f58: f7ff fe5e bl 10001c18 <__wrap___aeabi_dcmpgt> +10001f5c: 2800 cmp r0, #0 +10001f5e: f040 809f bne.w 100020a0 <_ftoa+0x198> +10001f62: e9dd 6704 ldrd r6, r7, [sp, #16] +10001f66: a3aa add r3, pc, #680 @ (adr r3, 10002210 <_ftoa+0x308>) +10001f68: e9d3 2300 ldrd r2, r3, [r3] +10001f6c: 4630 mov r0, r6 +10001f6e: 4639 mov r1, r7 +10001f70: f7ff fe52 bl 10001c18 <__wrap___aeabi_dcmpgt> +10001f74: 2800 cmp r0, #0 +10001f76: f040 8082 bne.w 1000207e <_ftoa+0x176> +10001f7a: a3a7 add r3, pc, #668 @ (adr r3, 10002218 <_ftoa+0x310>) +10001f7c: e9d3 2300 ldrd r2, r3, [r3] +10001f80: 4630 mov r0, r6 +10001f82: 4639 mov r1, r7 +10001f84: f7ff fe0c bl 10001ba0 <__wrap___aeabi_dcmplt> +10001f88: 2800 cmp r0, #0 +10001f8a: d178 bne.n 1000207e <_ftoa+0x176> +10001f8c: 4630 mov r0, r6 +10001f8e: 4639 mov r1, r7 +10001f90: 2200 movs r2, #0 +10001f92: 2300 movs r3, #0 +10001f94: f7ff fe04 bl 10001ba0 <__wrap___aeabi_dcmplt> +10001f98: 2800 cmp r0, #0 +10001f9a: f040 8098 bne.w 100020ce <_ftoa+0x1c6> +10001f9e: 900d str r0, [sp, #52] @ 0x34 +10001fa0: 9b07 ldr r3, [sp, #28] +10001fa2: 2130 movs r1, #48 @ 0x30 +10001fa4: f413 6f80 tst.w r3, #1024 @ 0x400 +10001fa8: bf08 it eq +10001faa: 2506 moveq r5, #6 +10001fac: aa0e add r2, sp, #56 @ 0x38 +10001fae: 462b mov r3, r5 +10001fb0: f1a5 0620 sub.w r6, r5, #32 +10001fb4: e005 b.n 10001fc2 <_ftoa+0xba> +10001fb6: 3b01 subs r3, #1 +10001fb8: 42b3 cmp r3, r6 +10001fba: f802 1b01 strb.w r1, [r2], #1 +10001fbe: f000 8165 beq.w 1000228c <_ftoa+0x384> +10001fc2: 2b09 cmp r3, #9 +10001fc4: d8f7 bhi.n 10001fb6 <_ftoa+0xae> +10001fc6: 461e mov r6, r3 +10001fc8: 1aed subs r5, r5, r3 +10001fca: e9dd 0104 ldrd r0, r1, [sp, #16] +10001fce: f7ff fdb1 bl 10001b34 <__wrap___aeabi_d2iz> +10001fd2: 4b94 ldr r3, [pc, #592] @ (10002224 <_ftoa+0x31c>) +10001fd4: 4604 mov r4, r0 +10001fd6: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001fda: ed93 7b00 vldr d7, [r3] +10001fde: ed8d 7b08 vstr d7, [sp, #32] +10001fe2: f7ff fd83 bl 10001aec <__wrap___aeabi_i2d> +10001fe6: 4602 mov r2, r0 +10001fe8: 460b mov r3, r1 +10001fea: e9dd 0104 ldrd r0, r1, [sp, #16] +10001fee: f7ff fcf7 bl 100019e0 <__wrap___aeabi_dsub> +10001ff2: e9dd 2308 ldrd r2, r3, [sp, #32] +10001ff6: f7ff fd07 bl 10001a08 <__wrap___aeabi_dmul> +10001ffa: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10001ffe: f7ff fdab bl 10001b58 <__wrap___aeabi_d2uiz> +10002002: 4607 mov r7, r0 +10002004: f7ff fd84 bl 10001b10 <__wrap___aeabi_ui2d> +10002008: 4602 mov r2, r0 +1000200a: 460b mov r3, r1 +1000200c: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002010: f7ff fce6 bl 100019e0 <__wrap___aeabi_dsub> +10002014: 2200 movs r2, #0 +10002016: 4b84 ldr r3, [pc, #528] @ (10002228 <_ftoa+0x320>) +10002018: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +1000201c: f7ff fdfc bl 10001c18 <__wrap___aeabi_dcmpgt> +10002020: 2800 cmp r0, #0 +10002022: f000 8088 beq.w 10002136 <_ftoa+0x22e> +10002026: 3701 adds r7, #1 +10002028: 4638 mov r0, r7 +1000202a: f7ff fd71 bl 10001b10 <__wrap___aeabi_ui2d> +1000202e: 4602 mov r2, r0 +10002030: 460b mov r3, r1 +10002032: e9dd 0108 ldrd r0, r1, [sp, #32] +10002036: f7ff fdc7 bl 10001bc8 <__wrap___aeabi_dcmple> +1000203a: b108 cbz r0, 10002040 <_ftoa+0x138> +1000203c: 2700 movs r7, #0 +1000203e: 3401 adds r4, #1 +10002040: 2e00 cmp r6, #0 +10002042: f000 8088 beq.w 10002156 <_ftoa+0x24e> +10002046: f10d 0337 add.w r3, sp, #55 @ 0x37 +1000204a: f8df c1f0 ldr.w ip, [pc, #496] @ 1000223c <_ftoa+0x334> +1000204e: 1958 adds r0, r3, r5 +10002050: e00d b.n 1000206e <_ftoa+0x166> +10002052: fbac 2107 umull r2, r1, ip, r7 +10002056: 08c9 lsrs r1, r1, #3 +10002058: eb01 0281 add.w r2, r1, r1, lsl #2 +1000205c: eba7 0242 sub.w r2, r7, r2, lsl #1 +10002060: 3230 adds r2, #48 @ 0x30 +10002062: 2f09 cmp r7, #9 +10002064: f800 2f01 strb.w r2, [r0, #1]! +10002068: f240 80fb bls.w 10002262 <_ftoa+0x35a> +1000206c: 460f mov r7, r1 +1000206e: 2d20 cmp r5, #32 +10002070: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10002074: f105 0501 add.w r5, r5, #1 +10002078: d1eb bne.n 10002052 <_ftoa+0x14a> +1000207a: 2520 movs r5, #32 +1000207c: e086 b.n 1000218c <_ftoa+0x284> +1000207e: 9b07 ldr r3, [sp, #28] +10002080: ed9d 7b04 vldr d7, [sp, #16] +10002084: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10002088: 4649 mov r1, r9 +1000208a: 4653 mov r3, sl +1000208c: 4640 mov r0, r8 +1000208e: 9a0c ldr r2, [sp, #48] @ 0x30 +10002090: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10002094: 9522 str r5, [sp, #136] @ 0x88 +10002096: b017 add sp, #92 @ 0x5c +10002098: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000209c: f000 b980 b.w 100023a0 <_etoa> +100020a0: 9b07 ldr r3, [sp, #28] +100020a2: 4649 mov r1, r9 +100020a4: 0758 lsls r0, r3, #29 +100020a6: bf4c ite mi +100020a8: 2304 movmi r3, #4 +100020aa: 2303 movpl r3, #3 +100020ac: 4640 mov r0, r8 +100020ae: 9321 str r3, [sp, #132] @ 0x84 +100020b0: 4653 mov r3, sl +100020b2: 9a07 ldr r2, [sp, #28] +100020b4: bf48 it mi +100020b6: 4c5d ldrmi r4, [pc, #372] @ (1000222c <_ftoa+0x324>) +100020b8: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +100020bc: bf58 it pl +100020be: 4c5c ldrpl r4, [pc, #368] @ (10002230 <_ftoa+0x328>) +100020c0: 9a0c ldr r2, [sp, #48] @ 0x30 +100020c2: 9420 str r4, [sp, #128] @ 0x80 +100020c4: b017 add sp, #92 @ 0x5c +100020c6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100020ca: f7ff bdcf b.w 10001c6c <_out_rev> +100020ce: 463b mov r3, r7 +100020d0: 4632 mov r2, r6 +100020d2: 2000 movs r0, #0 +100020d4: 2100 movs r1, #0 +100020d6: f7ff fc83 bl 100019e0 <__wrap___aeabi_dsub> +100020da: 2301 movs r3, #1 +100020dc: e9cd 0104 strd r0, r1, [sp, #16] +100020e0: 930d str r3, [sp, #52] @ 0x34 +100020e2: e75d b.n 10001fa0 <_ftoa+0x98> +100020e4: 9b07 ldr r3, [sp, #28] +100020e6: f003 0202 and.w r2, r3, #2 +100020ea: 079c lsls r4, r3, #30 +100020ec: 9204 str r2, [sp, #16] +100020ee: f000 80f4 beq.w 100022da <_ftoa+0x3d2> +100020f2: 9f0c ldr r7, [sp, #48] @ 0x30 +100020f4: 463d mov r5, r7 +100020f6: 4e4f ldr r6, [pc, #316] @ (10002234 <_ftoa+0x32c>) +100020f8: 1d34 adds r4, r6, #4 +100020fa: f814 0d01 ldrb.w r0, [r4, #-1]! +100020fe: 462a mov r2, r5 +10002100: 4653 mov r3, sl +10002102: 4649 mov r1, r9 +10002104: 47c0 blx r8 +10002106: 42a6 cmp r6, r4 +10002108: f105 0501 add.w r5, r5, #1 +1000210c: d1f5 bne.n 100020fa <_ftoa+0x1f2> +1000210e: 9b04 ldr r3, [sp, #16] +10002110: 1d3c adds r4, r7, #4 +10002112: b163 cbz r3, 1000212e <_ftoa+0x226> +10002114: 9d0c ldr r5, [sp, #48] @ 0x30 +10002116: 1b63 subs r3, r4, r5 +10002118: 459b cmp fp, r3 +1000211a: d908 bls.n 1000212e <_ftoa+0x226> +1000211c: 4622 mov r2, r4 +1000211e: 4653 mov r3, sl +10002120: 4649 mov r1, r9 +10002122: 2020 movs r0, #32 +10002124: 3401 adds r4, #1 +10002126: 47c0 blx r8 +10002128: 1b63 subs r3, r4, r5 +1000212a: 459b cmp fp, r3 +1000212c: d8f6 bhi.n 1000211c <_ftoa+0x214> +1000212e: 4620 mov r0, r4 +10002130: b017 add sp, #92 @ 0x5c +10002132: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002136: 2200 movs r2, #0 +10002138: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000213c: 4b3a ldr r3, [pc, #232] @ (10002228 <_ftoa+0x320>) +1000213e: f7ff fd2f bl 10001ba0 <__wrap___aeabi_dcmplt> +10002142: 2800 cmp r0, #0 +10002144: f47f af7c bne.w 10002040 <_ftoa+0x138> +10002148: 2f00 cmp r7, #0 +1000214a: f040 80c2 bne.w 100022d2 <_ftoa+0x3ca> +1000214e: 3701 adds r7, #1 +10002150: 2e00 cmp r6, #0 +10002152: f47f af78 bne.w 10002046 <_ftoa+0x13e> +10002156: 4620 mov r0, r4 +10002158: f7ff fcc8 bl 10001aec <__wrap___aeabi_i2d> +1000215c: 4602 mov r2, r0 +1000215e: 460b mov r3, r1 +10002160: e9dd 0104 ldrd r0, r1, [sp, #16] +10002164: f7ff fc3c bl 100019e0 <__wrap___aeabi_dsub> +10002168: 2200 movs r2, #0 +1000216a: 4b2f ldr r3, [pc, #188] @ (10002228 <_ftoa+0x320>) +1000216c: 4606 mov r6, r0 +1000216e: 460f mov r7, r1 +10002170: f7ff fd16 bl 10001ba0 <__wrap___aeabi_dcmplt> +10002174: b940 cbnz r0, 10002188 <_ftoa+0x280> +10002176: 4630 mov r0, r6 +10002178: 4639 mov r1, r7 +1000217a: 2200 movs r2, #0 +1000217c: 4b2a ldr r3, [pc, #168] @ (10002228 <_ftoa+0x320>) +1000217e: f7ff fd4b bl 10001c18 <__wrap___aeabi_dcmpgt> +10002182: 2800 cmp r0, #0 +10002184: f000 80a1 beq.w 100022ca <_ftoa+0x3c2> +10002188: f10d 0337 add.w r3, sp, #55 @ 0x37 +1000218c: 482a ldr r0, [pc, #168] @ (10002238 <_ftoa+0x330>) +1000218e: 1959 adds r1, r3, r5 +10002190: e00e b.n 100021b0 <_ftoa+0x2a8> +10002192: fb80 7604 smull r7, r6, r0, r4 +10002196: ebc2 02a6 rsb r2, r2, r6, asr #2 +1000219a: eb02 0682 add.w r6, r2, r2, lsl #2 +1000219e: eba4 0646 sub.w r6, r4, r6, lsl #1 +100021a2: 3630 adds r6, #48 @ 0x30 +100021a4: 4614 mov r4, r2 +100021a6: 3501 adds r5, #1 +100021a8: f801 6f01 strb.w r6, [r1, #1]! +100021ac: 2a00 cmp r2, #0 +100021ae: d047 beq.n 10002240 <_ftoa+0x338> +100021b0: 2d20 cmp r5, #32 +100021b2: ea4f 72e4 mov.w r2, r4, asr #31 +100021b6: d1ec bne.n 10002192 <_ftoa+0x28a> +100021b8: 9a07 ldr r2, [sp, #28] +100021ba: f002 0203 and.w r2, r2, #3 +100021be: 2a01 cmp r2, #1 +100021c0: d114 bne.n 100021ec <_ftoa+0x2e4> +100021c2: f1bb 0f00 cmp.w fp, #0 +100021c6: d011 beq.n 100021ec <_ftoa+0x2e4> +100021c8: 9a0d ldr r2, [sp, #52] @ 0x34 +100021ca: 2a00 cmp r2, #0 +100021cc: d060 beq.n 10002290 <_ftoa+0x388> +100021ce: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +100021d2: f1bb 0f20 cmp.w fp, #32 +100021d6: d909 bls.n 100021ec <_ftoa+0x2e4> +100021d8: 2230 movs r2, #48 @ 0x30 +100021da: 442b add r3, r5 +100021dc: e004 b.n 100021e8 <_ftoa+0x2e0> +100021de: 3501 adds r5, #1 +100021e0: 455d cmp r5, fp +100021e2: f803 2f01 strb.w r2, [r3, #1]! +100021e6: d231 bcs.n 1000224c <_ftoa+0x344> +100021e8: 2d20 cmp r5, #32 +100021ea: d1f8 bne.n 100021de <_ftoa+0x2d6> +100021ec: 9b07 ldr r3, [sp, #28] +100021ee: ac0e add r4, sp, #56 @ 0x38 +100021f0: e9cd b302 strd fp, r3, [sp, #8] +100021f4: 9400 str r4, [sp, #0] +100021f6: 4653 mov r3, sl +100021f8: 4649 mov r1, r9 +100021fa: 4640 mov r0, r8 +100021fc: 9a0c ldr r2, [sp, #48] @ 0x30 +100021fe: 9501 str r5, [sp, #4] +10002200: f7ff fd34 bl 10001c6c <_out_rev> +10002204: 4604 mov r4, r0 +10002206: 4620 mov r0, r4 +10002208: b017 add sp, #92 @ 0x5c +1000220a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000220e: bf00 nop +10002210: 00000000 .word 0x00000000 +10002214: 41cdcd65 .word 0x41cdcd65 +10002218: 00000000 .word 0x00000000 +1000221c: c1cdcd65 .word 0xc1cdcd65 +10002220: 7fefffff .word 0x7fefffff +10002224: 1000cca8 .word 0x1000cca8 +10002228: 3fe00000 .word 0x3fe00000 +1000222c: 1000c674 .word 0x1000c674 +10002230: 1000c67c .word 0x1000c67c +10002234: 1000c684 .word 0x1000c684 +10002238: 66666667 .word 0x66666667 +1000223c: cccccccd .word 0xcccccccd +10002240: 9a07 ldr r2, [sp, #28] +10002242: f002 0203 and.w r2, r2, #3 +10002246: 2a01 cmp r2, #1 +10002248: f000 8096 beq.w 10002378 <_ftoa+0x470> +1000224c: 2d20 cmp r5, #32 +1000224e: d0cd beq.n 100021ec <_ftoa+0x2e4> +10002250: 9b0d ldr r3, [sp, #52] @ 0x34 +10002252: b33b cbz r3, 100022a4 <_ftoa+0x39c> +10002254: 222d movs r2, #45 @ 0x2d +10002256: eb0d 0305 add.w r3, sp, r5 +1000225a: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1000225e: 3501 adds r5, #1 +10002260: e7c4 b.n 100021ec <_ftoa+0x2e4> +10002262: 2d20 cmp r5, #32 +10002264: f43f af09 beq.w 1000207a <_ftoa+0x172> +10002268: 2130 movs r1, #48 @ 0x30 +1000226a: 442e add r6, r5 +1000226c: 195a adds r2, r3, r5 +1000226e: e005 b.n 1000227c <_ftoa+0x374> +10002270: 3501 adds r5, #1 +10002272: 2d20 cmp r5, #32 +10002274: f802 1f01 strb.w r1, [r2, #1]! +10002278: f43f aeff beq.w 1000207a <_ftoa+0x172> +1000227c: 42ae cmp r6, r5 +1000227e: d1f7 bne.n 10002270 <_ftoa+0x368> +10002280: 222e movs r2, #46 @ 0x2e +10002282: 446e add r6, sp +10002284: 3501 adds r5, #1 +10002286: f886 2038 strb.w r2, [r6, #56] @ 0x38 +1000228a: e77f b.n 1000218c <_ftoa+0x284> +1000228c: 2520 movs r5, #32 +1000228e: e69c b.n 10001fca <_ftoa+0xc2> +10002290: 9a07 ldr r2, [sp, #28] +10002292: f012 0f0c tst.w r2, #12 +10002296: d05a beq.n 1000234e <_ftoa+0x446> +10002298: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000229c: 45ab cmp fp, r5 +1000229e: d89b bhi.n 100021d8 <_ftoa+0x2d0> +100022a0: 2d20 cmp r5, #32 +100022a2: d0a3 beq.n 100021ec <_ftoa+0x2e4> +100022a4: 9b07 ldr r3, [sp, #28] +100022a6: 075a lsls r2, r3, #29 +100022a8: d506 bpl.n 100022b8 <_ftoa+0x3b0> +100022aa: 222b movs r2, #43 @ 0x2b +100022ac: eb0d 0305 add.w r3, sp, r5 +100022b0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +100022b4: 3501 adds r5, #1 +100022b6: e799 b.n 100021ec <_ftoa+0x2e4> +100022b8: 071b lsls r3, r3, #28 +100022ba: d597 bpl.n 100021ec <_ftoa+0x2e4> +100022bc: 2220 movs r2, #32 +100022be: eb0d 0305 add.w r3, sp, r5 +100022c2: f883 2038 strb.w r2, [r3, #56] @ 0x38 +100022c6: 3501 adds r5, #1 +100022c8: e790 b.n 100021ec <_ftoa+0x2e4> +100022ca: 3401 adds r4, #1 +100022cc: f024 0401 bic.w r4, r4, #1 +100022d0: e75a b.n 10002188 <_ftoa+0x280> +100022d2: 07f9 lsls r1, r7, #31 +100022d4: f57f aeb4 bpl.w 10002040 <_ftoa+0x138> +100022d8: e739 b.n 1000214e <_ftoa+0x246> +100022da: f1bb 0f04 cmp.w fp, #4 +100022de: f67f af08 bls.w 100020f2 <_ftoa+0x1ea> +100022e2: 9b0c ldr r3, [sp, #48] @ 0x30 +100022e4: 461d mov r5, r3 +100022e6: 3b04 subs r3, #4 +100022e8: eb03 070b add.w r7, r3, fp +100022ec: 462a mov r2, r5 +100022ee: 4653 mov r3, sl +100022f0: 4649 mov r1, r9 +100022f2: 2020 movs r0, #32 +100022f4: 3501 adds r5, #1 +100022f6: 47c0 blx r8 +100022f8: 42af cmp r7, r5 +100022fa: d1f7 bne.n 100022ec <_ftoa+0x3e4> +100022fc: e6fa b.n 100020f4 <_ftoa+0x1ec> +100022fe: 9b07 ldr r3, [sp, #28] +10002300: f003 0202 and.w r2, r3, #2 +10002304: 079d lsls r5, r3, #30 +10002306: 9204 str r2, [sp, #16] +10002308: d025 beq.n 10002356 <_ftoa+0x44e> +1000230a: 9f0c ldr r7, [sp, #48] @ 0x30 +1000230c: 463d mov r5, r7 +1000230e: 4e22 ldr r6, [pc, #136] @ (10002398 <_ftoa+0x490>) +10002310: 1cf4 adds r4, r6, #3 +10002312: f814 0d01 ldrb.w r0, [r4, #-1]! +10002316: 462a mov r2, r5 +10002318: 4653 mov r3, sl +1000231a: 4649 mov r1, r9 +1000231c: 47c0 blx r8 +1000231e: 42a6 cmp r6, r4 +10002320: f105 0501 add.w r5, r5, #1 +10002324: d1f5 bne.n 10002312 <_ftoa+0x40a> +10002326: 9b04 ldr r3, [sp, #16] +10002328: 1cfc adds r4, r7, #3 +1000232a: 2b00 cmp r3, #0 +1000232c: f43f aeff beq.w 1000212e <_ftoa+0x226> +10002330: 9d0c ldr r5, [sp, #48] @ 0x30 +10002332: 1b63 subs r3, r4, r5 +10002334: 459b cmp fp, r3 +10002336: f67f aefa bls.w 1000212e <_ftoa+0x226> +1000233a: 4622 mov r2, r4 +1000233c: 4653 mov r3, sl +1000233e: 4649 mov r1, r9 +10002340: 2020 movs r0, #32 +10002342: 3401 adds r4, #1 +10002344: 47c0 blx r8 +10002346: 1b63 subs r3, r4, r5 +10002348: 459b cmp fp, r3 +1000234a: d8f6 bhi.n 1000233a <_ftoa+0x432> +1000234c: e6ef b.n 1000212e <_ftoa+0x226> +1000234e: 45ab cmp fp, r5 +10002350: f63f af42 bhi.w 100021d8 <_ftoa+0x2d0> +10002354: e74a b.n 100021ec <_ftoa+0x2e4> +10002356: f1bb 0f03 cmp.w fp, #3 +1000235a: d9d6 bls.n 1000230a <_ftoa+0x402> +1000235c: 9b0c ldr r3, [sp, #48] @ 0x30 +1000235e: 461d mov r5, r3 +10002360: 3b03 subs r3, #3 +10002362: eb03 070b add.w r7, r3, fp +10002366: 462a mov r2, r5 +10002368: 4653 mov r3, sl +1000236a: 4649 mov r1, r9 +1000236c: 2020 movs r0, #32 +1000236e: 3501 adds r5, #1 +10002370: 47c0 blx r8 +10002372: 42bd cmp r5, r7 +10002374: d1f7 bne.n 10002366 <_ftoa+0x45e> +10002376: e7c9 b.n 1000230c <_ftoa+0x404> +10002378: f1bb 0f00 cmp.w fp, #0 +1000237c: f43f af66 beq.w 1000224c <_ftoa+0x344> +10002380: 9a0d ldr r2, [sp, #52] @ 0x34 +10002382: 2a00 cmp r2, #0 +10002384: d084 beq.n 10002290 <_ftoa+0x388> +10002386: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000238a: 455d cmp r5, fp +1000238c: f4ff af24 bcc.w 100021d8 <_ftoa+0x2d0> +10002390: 2d20 cmp r5, #32 +10002392: f47f af5f bne.w 10002254 <_ftoa+0x34c> +10002396: e729 b.n 100021ec <_ftoa+0x2e4> +10002398: 1000c680 .word 0x1000c680 +1000239c: 00000000 .word 0x00000000 + +100023a0 <_etoa>: +100023a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100023a4: b09f sub sp, #124 @ 0x7c +100023a6: 461e mov r6, r3 +100023a8: e9dd ab28 ldrd sl, fp, [sp, #160] @ 0xa0 +100023ac: e9dd 982b ldrd r9, r8, [sp, #172] @ 0xac +100023b0: 9b2a ldr r3, [sp, #168] @ 0xa8 +100023b2: 4604 mov r4, r0 +100023b4: 460d mov r5, r1 +100023b6: 920b str r2, [sp, #44] @ 0x2c +100023b8: 930a str r3, [sp, #40] @ 0x28 +100023ba: 4652 mov r2, sl +100023bc: 465b mov r3, fp +100023be: 4650 mov r0, sl +100023c0: 4659 mov r1, fp +100023c2: f7ff fbdb bl 10001b7c <__wrap___aeabi_dcmpun> +100023c6: 2800 cmp r0, #0 +100023c8: f040 80c6 bne.w 10002558 <_etoa+0x1b8> +100023cc: 4650 mov r0, sl +100023ce: 4659 mov r1, fp +100023d0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100023d4: 4b7b ldr r3, [pc, #492] @ (100025c4 <_etoa+0x224>) +100023d6: f7ff fc1f bl 10001c18 <__wrap___aeabi_dcmpgt> +100023da: 2800 cmp r0, #0 +100023dc: f040 80bc bne.w 10002558 <_etoa+0x1b8> +100023e0: 4650 mov r0, sl +100023e2: 4659 mov r1, fp +100023e4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100023e8: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100023ec: f7ff fbd8 bl 10001ba0 <__wrap___aeabi_dcmplt> +100023f0: 2800 cmp r0, #0 +100023f2: f040 80b1 bne.w 10002558 <_etoa+0x1b8> +100023f6: 4650 mov r0, sl +100023f8: 4659 mov r1, fp +100023fa: 2200 movs r2, #0 +100023fc: 2300 movs r3, #0 +100023fe: f7ff fbcf bl 10001ba0 <__wrap___aeabi_dcmplt> +10002402: 2800 cmp r0, #0 +10002404: f040 81dd bne.w 100027c2 <_etoa+0x422> +10002408: e9cd ab08 strd sl, fp, [sp, #32] +1000240c: e9dd 1208 ldrd r1, r2, [sp, #32] +10002410: f418 6080 ands.w r0, r8, #1024 @ 0x400 +10002414: 460b mov r3, r1 +10002416: 460f mov r7, r1 +10002418: f408 6100 and.w r1, r8, #2048 @ 0x800 +1000241c: 920c str r2, [sp, #48] @ 0x30 +1000241e: 9114 str r1, [sp, #80] @ 0x50 +10002420: 9015 str r0, [sp, #84] @ 0x54 +10002422: f040 80a8 bne.w 10002576 <_etoa+0x1d6> +10002426: 4313 orrs r3, r2 +10002428: f040 80d0 bne.w 100025cc <_etoa+0x22c> +1000242c: 2900 cmp r1, #0 +1000242e: f040 81ec bne.w 1000280a <_etoa+0x46a> +10002432: 2306 movs r3, #6 +10002434: 930a str r3, [sp, #40] @ 0x28 +10002436: f018 0202 ands.w r2, r8, #2 +1000243a: 9210 str r2, [sp, #64] @ 0x40 +1000243c: f040 81dd bne.w 100027fa <_etoa+0x45a> +10002440: 464b mov r3, r9 +10002442: 2b04 cmp r3, #4 +10002444: bf38 it cc +10002446: 2304 movcc r3, #4 +10002448: 920e str r2, [sp, #56] @ 0x38 +1000244a: 2204 movs r2, #4 +1000244c: 3b04 subs r3, #4 +1000244e: 9212 str r2, [sp, #72] @ 0x48 +10002450: 9314 str r3, [sp, #80] @ 0x50 +10002452: 4650 mov r0, sl +10002454: 4659 mov r1, fp +10002456: 2200 movs r2, #0 +10002458: 2300 movs r3, #0 +1000245a: f7ff fba1 bl 10001ba0 <__wrap___aeabi_dcmplt> +1000245e: 2800 cmp r0, #0 +10002460: f040 822a bne.w 100028b8 <_etoa+0x518> +10002464: ed9d 7b08 vldr d7, [sp, #32] +10002468: 9b14 ldr r3, [sp, #80] @ 0x50 +1000246a: 9a0b ldr r2, [sp, #44] @ 0x2c +1000246c: 9303 str r3, [sp, #12] +1000246e: 9b0a ldr r3, [sp, #40] @ 0x28 +10002470: ed8d 7b00 vstr d7, [sp] +10002474: 9302 str r3, [sp, #8] +10002476: f428 6300 bic.w r3, r8, #2048 @ 0x800 +1000247a: 9304 str r3, [sp, #16] +1000247c: 4629 mov r1, r5 +1000247e: 4633 mov r3, r6 +10002480: 4620 mov r0, r4 +10002482: f7ff fd41 bl 10001f08 <_ftoa> +10002486: 4602 mov r2, r0 +10002488: f018 0f20 tst.w r8, #32 +1000248c: 4633 mov r3, r6 +1000248e: 4629 mov r1, r5 +10002490: bf0c ite eq +10002492: 2065 moveq r0, #101 @ 0x65 +10002494: 2045 movne r0, #69 @ 0x45 +10002496: f102 0801 add.w r8, r2, #1 +1000249a: 47a0 blx r4 +1000249c: 9b12 ldr r3, [sp, #72] @ 0x48 +1000249e: f10d 0a58 add.w sl, sp, #88 @ 0x58 +100024a2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff +100024a6: 9b0e ldr r3, [sp, #56] @ 0x38 +100024a8: 2200 movs r2, #0 +100024aa: ea83 7ce3 eor.w ip, r3, r3, asr #31 +100024ae: 4650 mov r0, sl +100024b0: f8df e114 ldr.w lr, [pc, #276] @ 100025c8 <_etoa+0x228> +100024b4: 9f0b ldr r7, [sp, #44] @ 0x2c +100024b6: ebac 7ce3 sub.w ip, ip, r3, asr #31 +100024ba: 0fd9 lsrs r1, r3, #31 +100024bc: f8cd 8020 str.w r8, [sp, #32] +100024c0: e002 b.n 100024c8 <_etoa+0x128> +100024c2: 2a20 cmp r2, #32 +100024c4: 46c4 mov ip, r8 +100024c6: d010 beq.n 100024ea <_etoa+0x14a> +100024c8: fbae 380c umull r3, r8, lr, ip +100024cc: ea4f 08d8 mov.w r8, r8, lsr #3 +100024d0: eb08 0388 add.w r3, r8, r8, lsl #2 +100024d4: ebac 0343 sub.w r3, ip, r3, lsl #1 +100024d8: 3001 adds r0, #1 +100024da: 3330 adds r3, #48 @ 0x30 +100024dc: f1bc 0f09 cmp.w ip, #9 +100024e0: f102 0201 add.w r2, r2, #1 +100024e4: f800 3c01 strb.w r3, [r0, #-1] +100024e8: d8eb bhi.n 100024c2 <_etoa+0x122> +100024ea: 2305 movs r3, #5 +100024ec: f04f 0c00 mov.w ip, #0 +100024f0: 9306 str r3, [sp, #24] +100024f2: 230a movs r3, #10 +100024f4: f8dd 8020 ldr.w r8, [sp, #32] +100024f8: e9cd 2101 strd r2, r1, [sp, #4] +100024fc: e9cd 3c03 strd r3, ip, [sp, #12] +10002500: f8cd a000 str.w sl, [sp] +10002504: 4633 mov r3, r6 +10002506: 4642 mov r2, r8 +10002508: 4629 mov r1, r5 +1000250a: 4620 mov r0, r4 +1000250c: f8cd b014 str.w fp, [sp, #20] +10002510: f7ff fc00 bl 10001d14 <_ntoa_format> +10002514: 9b10 ldr r3, [sp, #64] @ 0x40 +10002516: 4682 mov sl, r0 +10002518: b1d3 cbz r3, 10002550 <_etoa+0x1b0> +1000251a: eba0 0807 sub.w r8, r0, r7 +1000251e: 45c1 cmp r9, r8 +10002520: d916 bls.n 10002550 <_etoa+0x1b0> +10002522: eb07 0208 add.w r2, r7, r8 +10002526: 4633 mov r3, r6 +10002528: 4629 mov r1, r5 +1000252a: 2020 movs r0, #32 +1000252c: f108 0801 add.w r8, r8, #1 +10002530: 47a0 blx r4 +10002532: 45c1 cmp r9, r8 +10002534: d8f5 bhi.n 10002522 <_etoa+0x182> +10002536: 1e7b subs r3, r7, #1 +10002538: 444b add r3, r9 +1000253a: f1c7 0201 rsb r2, r7, #1 +1000253e: eba3 030a sub.w r3, r3, sl +10002542: 4452 add r2, sl +10002544: 4591 cmp r9, r2 +10002546: bf38 it cc +10002548: 2300 movcc r3, #0 +1000254a: f10a 0a01 add.w sl, sl, #1 +1000254e: 449a add sl, r3 +10002550: 4650 mov r0, sl +10002552: b01f add sp, #124 @ 0x7c +10002554: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002558: 4633 mov r3, r6 +1000255a: 4629 mov r1, r5 +1000255c: 4620 mov r0, r4 +1000255e: e9cd ab28 strd sl, fp, [sp, #160] @ 0xa0 +10002562: 9c0a ldr r4, [sp, #40] @ 0x28 +10002564: e9cd 982b strd r9, r8, [sp, #172] @ 0xac +10002568: 9a0b ldr r2, [sp, #44] @ 0x2c +1000256a: 942a str r4, [sp, #168] @ 0xa8 +1000256c: b01f add sp, #124 @ 0x7c +1000256e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002572: f7ff bcc9 b.w 10001f08 <_ftoa> +10002576: ea57 0302 orrs.w r3, r7, r2 +1000257a: d129 bne.n 100025d0 <_etoa+0x230> +1000257c: 2900 cmp r1, #0 +1000257e: f43f af5a beq.w 10002436 <_etoa+0x96> +10002582: 2300 movs r3, #0 +10002584: 930e str r3, [sp, #56] @ 0x38 +10002586: 9b0a ldr r3, [sp, #40] @ 0x28 +10002588: 9a0e ldr r2, [sp, #56] @ 0x38 +1000258a: 4293 cmp r3, r2 +1000258c: f300 81ba bgt.w 10002904 <_etoa+0x564> +10002590: 2700 movs r7, #0 +10002592: 4650 mov r0, sl +10002594: 4659 mov r1, fp +10002596: 2200 movs r2, #0 +10002598: 2300 movs r3, #0 +1000259a: f7ff fb01 bl 10001ba0 <__wrap___aeabi_dcmplt> +1000259e: 2800 cmp r0, #0 +100025a0: f040 8115 bne.w 100027ce <_etoa+0x42e> +100025a4: ed9d 7b08 vldr d7, [sp, #32] +100025a8: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100025ac: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100025b0: 932c str r3, [sp, #176] @ 0xb0 +100025b2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100025b6: 4633 mov r3, r6 +100025b8: 4629 mov r1, r5 +100025ba: 4620 mov r0, r4 +100025bc: e9cd 792a strd r7, r9, [sp, #168] @ 0xa8 +100025c0: 9a0b ldr r2, [sp, #44] @ 0x2c +100025c2: e7d3 b.n 1000256c <_etoa+0x1cc> +100025c4: 7fefffff .word 0x7fefffff +100025c8: cccccccd .word 0xcccccccd +100025cc: 2306 movs r3, #6 +100025ce: 930a str r3, [sp, #40] @ 0x28 +100025d0: 9b0c ldr r3, [sp, #48] @ 0x30 +100025d2: f3c3 500a ubfx r0, r3, #20, #11 +100025d6: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100025da: f7ff fa87 bl 10001aec <__wrap___aeabi_i2d> +100025de: a3b2 add r3, pc, #712 @ (adr r3, 100028a8 <_etoa+0x508>) +100025e0: e9d3 2300 ldrd r2, r3, [r3] +100025e4: f7ff fa10 bl 10001a08 <__wrap___aeabi_dmul> +100025e8: a3b1 add r3, pc, #708 @ (adr r3, 100028b0 <_etoa+0x510>) +100025ea: e9d3 2300 ldrd r2, r3, [r3] +100025ee: f7ff f9e3 bl 100019b8 <__wrap___aeabi_dadd> +100025f2: 9b0c ldr r3, [sp, #48] @ 0x30 +100025f4: e9cd 010e strd r0, r1, [sp, #56] @ 0x38 +100025f8: f3c3 0313 ubfx r3, r3, #0, #20 +100025fc: f043 517f orr.w r1, r3, #1069547520 @ 0x3fc00000 +10002600: 4638 mov r0, r7 +10002602: 2200 movs r2, #0 +10002604: 4ba2 ldr r3, [pc, #648] @ (10002890 <_etoa+0x4f0>) +10002606: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +1000260a: f7ff f9e9 bl 100019e0 <__wrap___aeabi_dsub> +1000260e: a394 add r3, pc, #592 @ (adr r3, 10002860 <_etoa+0x4c0>) +10002610: e9d3 2300 ldrd r2, r3, [r3] +10002614: f7ff f9f8 bl 10001a08 <__wrap___aeabi_dmul> +10002618: 4602 mov r2, r0 +1000261a: 460b mov r3, r1 +1000261c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38 +10002620: f7ff f9ca bl 100019b8 <__wrap___aeabi_dadd> +10002624: f7ff fa86 bl 10001b34 <__wrap___aeabi_d2iz> +10002628: 900e str r0, [sp, #56] @ 0x38 +1000262a: f7ff fa5f bl 10001aec <__wrap___aeabi_i2d> +1000262e: a38e add r3, pc, #568 @ (adr r3, 10002868 <_etoa+0x4c8>) +10002630: e9d3 2300 ldrd r2, r3, [r3] +10002634: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002638: f7ff f9e6 bl 10001a08 <__wrap___aeabi_dmul> +1000263c: 2200 movs r2, #0 +1000263e: 4b95 ldr r3, [pc, #596] @ (10002894 <_etoa+0x4f4>) +10002640: f7ff f9ba bl 100019b8 <__wrap___aeabi_dadd> +10002644: f7ff fa76 bl 10001b34 <__wrap___aeabi_d2iz> +10002648: a389 add r3, pc, #548 @ (adr r3, 10002870 <_etoa+0x4d0>) +1000264a: e9d3 2300 ldrd r2, r3, [r3] +1000264e: 4607 mov r7, r0 +10002650: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002654: f7ff f9d8 bl 10001a08 <__wrap___aeabi_dmul> +10002658: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +1000265c: 4638 mov r0, r7 +1000265e: f7ff fa45 bl 10001aec <__wrap___aeabi_i2d> +10002662: a385 add r3, pc, #532 @ (adr r3, 10002878 <_etoa+0x4d8>) +10002664: e9d3 2300 ldrd r2, r3, [r3] +10002668: f7ff f9ce bl 10001a08 <__wrap___aeabi_dmul> +1000266c: 4602 mov r2, r0 +1000266e: 460b mov r3, r1 +10002670: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002674: f7ff f9b4 bl 100019e0 <__wrap___aeabi_dsub> +10002678: 4602 mov r2, r0 +1000267a: 460b mov r3, r1 +1000267c: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 +10002680: f7ff f9c2 bl 10001a08 <__wrap___aeabi_dmul> +10002684: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002688: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +1000268c: 4602 mov r2, r0 +1000268e: 460b mov r3, r1 +10002690: f7ff f992 bl 100019b8 <__wrap___aeabi_dadd> +10002694: 2200 movs r2, #0 +10002696: e9cd 0112 strd r0, r1, [sp, #72] @ 0x48 +1000269a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000269e: 4b7e ldr r3, [pc, #504] @ (10002898 <_etoa+0x4f8>) +100026a0: f7ff f9d6 bl 10001a50 <__wrap___aeabi_ddiv> +100026a4: 2200 movs r2, #0 +100026a6: 4b7d ldr r3, [pc, #500] @ (1000289c <_etoa+0x4fc>) +100026a8: f7ff f986 bl 100019b8 <__wrap___aeabi_dadd> +100026ac: 4602 mov r2, r0 +100026ae: 460b mov r3, r1 +100026b0: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100026b4: f7ff f9cc bl 10001a50 <__wrap___aeabi_ddiv> +100026b8: 2200 movs r2, #0 +100026ba: 4b79 ldr r3, [pc, #484] @ (100028a0 <_etoa+0x500>) +100026bc: f7ff f97c bl 100019b8 <__wrap___aeabi_dadd> +100026c0: 4602 mov r2, r0 +100026c2: 460b mov r3, r1 +100026c4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100026c8: f7ff f9c2 bl 10001a50 <__wrap___aeabi_ddiv> +100026cc: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +100026d0: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 +100026d4: 2000 movs r0, #0 +100026d6: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100026da: f7ff f981 bl 100019e0 <__wrap___aeabi_dsub> +100026de: 4602 mov r2, r0 +100026e0: 460b mov r3, r1 +100026e2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100026e6: f7ff f967 bl 100019b8 <__wrap___aeabi_dadd> +100026ea: 4602 mov r2, r0 +100026ec: 460b mov r3, r1 +100026ee: e9dd 0112 ldrd r0, r1, [sp, #72] @ 0x48 +100026f2: f7ff f9ad bl 10001a50 <__wrap___aeabi_ddiv> +100026f6: 2200 movs r2, #0 +100026f8: 4b6a ldr r3, [pc, #424] @ (100028a4 <_etoa+0x504>) +100026fa: f7ff f95d bl 100019b8 <__wrap___aeabi_dadd> +100026fe: f207 3cff addw ip, r7, #1023 @ 0x3ff +10002702: 2200 movs r2, #0 +10002704: ea4f 530c mov.w r3, ip, lsl #20 +10002708: f7ff f97e bl 10001a08 <__wrap___aeabi_dmul> +1000270c: 4602 mov r2, r0 +1000270e: 460b mov r3, r1 +10002710: e9dd 0108 ldrd r0, r1, [sp, #32] +10002714: e9cd 230c strd r2, r3, [sp, #48] @ 0x30 +10002718: f7ff fa42 bl 10001ba0 <__wrap___aeabi_dcmplt> +1000271c: b150 cbz r0, 10002734 <_etoa+0x394> +1000271e: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002722: 9b0e ldr r3, [sp, #56] @ 0x38 +10002724: 2200 movs r2, #0 +10002726: 3b01 subs r3, #1 +10002728: 930e str r3, [sp, #56] @ 0x38 +1000272a: 4b5c ldr r3, [pc, #368] @ (1000289c <_etoa+0x4fc>) +1000272c: f7ff f990 bl 10001a50 <__wrap___aeabi_ddiv> +10002730: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002734: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002738: 9b0e ldr r3, [sp, #56] @ 0x38 +1000273a: 4602 mov r2, r0 +1000273c: 3363 adds r3, #99 @ 0x63 +1000273e: 2bc6 cmp r3, #198 @ 0xc6 +10002740: f008 0302 and.w r3, r8, #2 +10002744: 9310 str r3, [sp, #64] @ 0x40 +10002746: 9b14 ldr r3, [sp, #80] @ 0x50 +10002748: d82d bhi.n 100027a6 <_etoa+0x406> +1000274a: 2b00 cmp r3, #0 +1000274c: d05f beq.n 1000280e <_etoa+0x46e> +1000274e: 2304 movs r3, #4 +10002750: 9312 str r3, [sp, #72] @ 0x48 +10002752: 430a orrs r2, r1 +10002754: f43f af17 beq.w 10002586 <_etoa+0x1e6> +10002758: e9dd 0108 ldrd r0, r1, [sp, #32] +1000275c: a348 add r3, pc, #288 @ (adr r3, 10002880 <_etoa+0x4e0>) +1000275e: e9d3 2300 ldrd r2, r3, [r3] +10002762: f7ff fa45 bl 10001bf0 <__wrap___aeabi_dcmpge> +10002766: b148 cbz r0, 1000277c <_etoa+0x3dc> +10002768: e9dd 0108 ldrd r0, r1, [sp, #32] +1000276c: a346 add r3, pc, #280 @ (adr r3, 10002888 <_etoa+0x4e8>) +1000276e: e9d3 2300 ldrd r2, r3, [r3] +10002772: f7ff fa15 bl 10001ba0 <__wrap___aeabi_dcmplt> +10002776: 2800 cmp r0, #0 +10002778: f47f af05 bne.w 10002586 <_etoa+0x1e6> +1000277c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000277e: 2b00 cmp r3, #0 +10002780: d051 beq.n 10002826 <_etoa+0x486> +10002782: 9a15 ldr r2, [sp, #84] @ 0x54 +10002784: 2a00 cmp r2, #0 +10002786: f000 80ac beq.w 100028e2 <_etoa+0x542> +1000278a: 3b01 subs r3, #1 +1000278c: 930a str r3, [sp, #40] @ 0x28 +1000278e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002790: 4599 cmp r9, r3 +10002792: d905 bls.n 100027a0 <_etoa+0x400> +10002794: 9b10 ldr r3, [sp, #64] @ 0x40 +10002796: 2b00 cmp r3, #0 +10002798: f000 80af beq.w 100028fa <_etoa+0x55a> +1000279c: 2302 movs r3, #2 +1000279e: 9310 str r3, [sp, #64] @ 0x40 +100027a0: 2300 movs r3, #0 +100027a2: 9314 str r3, [sp, #80] @ 0x50 +100027a4: e044 b.n 10002830 <_etoa+0x490> +100027a6: bb2b cbnz r3, 100027f4 <_etoa+0x454> +100027a8: f1b9 0f05 cmp.w r9, #5 +100027ac: d94f bls.n 1000284e <_etoa+0x4ae> +100027ae: f008 0302 and.w r3, r8, #2 +100027b2: 2b00 cmp r3, #0 +100027b4: d149 bne.n 1000284a <_etoa+0x4aa> +100027b6: 2305 movs r3, #5 +100027b8: 9312 str r3, [sp, #72] @ 0x48 +100027ba: f1a9 0305 sub.w r3, r9, #5 +100027be: 9314 str r3, [sp, #80] @ 0x50 +100027c0: e03a b.n 10002838 <_etoa+0x498> +100027c2: f10b 4300 add.w r3, fp, #2147483648 @ 0x80000000 +100027c6: f8cd a020 str.w sl, [sp, #32] +100027ca: 9309 str r3, [sp, #36] @ 0x24 +100027cc: e61e b.n 1000240c <_etoa+0x6c> +100027ce: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100027d2: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100027d6: 4620 mov r0, r4 +100027d8: e9cd 792a strd r7, r9, [sp, #168] @ 0xa8 +100027dc: 932c str r3, [sp, #176] @ 0xb0 +100027de: 4633 mov r3, r6 +100027e0: e9dd 6708 ldrd r6, r7, [sp, #32] +100027e4: 4634 mov r4, r6 +100027e6: 4629 mov r1, r5 +100027e8: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100027ec: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100027f0: 9a0b ldr r2, [sp, #44] @ 0x2c +100027f2: e6bb b.n 1000256c <_etoa+0x1cc> +100027f4: 2305 movs r3, #5 +100027f6: 9312 str r3, [sp, #72] @ 0x48 +100027f8: e7ab b.n 10002752 <_etoa+0x3b2> +100027fa: 2202 movs r2, #2 +100027fc: 2300 movs r3, #0 +100027fe: 9210 str r2, [sp, #64] @ 0x40 +10002800: 2204 movs r2, #4 +10002802: 9314 str r3, [sp, #80] @ 0x50 +10002804: 9212 str r2, [sp, #72] @ 0x48 +10002806: 930e str r3, [sp, #56] @ 0x38 +10002808: e623 b.n 10002452 <_etoa+0xb2> +1000280a: 2705 movs r7, #5 +1000280c: e6c1 b.n 10002592 <_etoa+0x1f2> +1000280e: f1b9 0f04 cmp.w r9, #4 +10002812: d91f bls.n 10002854 <_etoa+0x4b4> +10002814: 9b10 ldr r3, [sp, #64] @ 0x40 +10002816: 2b00 cmp r3, #0 +10002818: d177 bne.n 1000290a <_etoa+0x56a> +1000281a: 2304 movs r3, #4 +1000281c: 9312 str r3, [sp, #72] @ 0x48 +1000281e: f1a9 0304 sub.w r3, r9, #4 +10002822: 9314 str r3, [sp, #80] @ 0x50 +10002824: e004 b.n 10002830 <_etoa+0x490> +10002826: 9b12 ldr r3, [sp, #72] @ 0x48 +10002828: 4599 cmp r9, r3 +1000282a: d85f bhi.n 100028ec <_etoa+0x54c> +1000282c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000282e: 9314 str r3, [sp, #80] @ 0x50 +10002830: 9b0e ldr r3, [sp, #56] @ 0x38 +10002832: 2b00 cmp r3, #0 +10002834: f43f ae0d beq.w 10002452 <_etoa+0xb2> +10002838: e9dd 0108 ldrd r0, r1, [sp, #32] +1000283c: e9dd 230c ldrd r2, r3, [sp, #48] @ 0x30 +10002840: f7ff f906 bl 10001a50 <__wrap___aeabi_ddiv> +10002844: e9cd 0108 strd r0, r1, [sp, #32] +10002848: e603 b.n 10002452 <_etoa+0xb2> +1000284a: 2302 movs r3, #2 +1000284c: 9310 str r3, [sp, #64] @ 0x40 +1000284e: 2305 movs r3, #5 +10002850: 9312 str r3, [sp, #72] @ 0x48 +10002852: e7f1 b.n 10002838 <_etoa+0x498> +10002854: 2304 movs r3, #4 +10002856: 9312 str r3, [sp, #72] @ 0x48 +10002858: e7ea b.n 10002830 <_etoa+0x490> +1000285a: bf00 nop +1000285c: f3af 8000 nop.w +10002860: 636f4361 .word 0x636f4361 +10002864: 3fd287a7 .word 0x3fd287a7 +10002868: 0979a371 .word 0x0979a371 +1000286c: 400a934f .word 0x400a934f +10002870: bbb55516 .word 0xbbb55516 +10002874: 40026bb1 .word 0x40026bb1 +10002878: fefa39ef .word 0xfefa39ef +1000287c: 3fe62e42 .word 0x3fe62e42 +10002880: eb1c432d .word 0xeb1c432d +10002884: 3f1a36e2 .word 0x3f1a36e2 +10002888: 00000000 .word 0x00000000 +1000288c: 412e8480 .word 0x412e8480 +10002890: 3ff80000 .word 0x3ff80000 +10002894: 3fe00000 .word 0x3fe00000 +10002898: 402c0000 .word 0x402c0000 +1000289c: 40240000 .word 0x40240000 +100028a0: 40180000 .word 0x40180000 +100028a4: 3ff00000 .word 0x3ff00000 +100028a8: 509f79fb .word 0x509f79fb +100028ac: 3fd34413 .word 0x3fd34413 +100028b0: 8b60c8b3 .word 0x8b60c8b3 +100028b4: 3fc68a28 .word 0x3fc68a28 +100028b8: 9b14 ldr r3, [sp, #80] @ 0x50 +100028ba: e9dd a708 ldrd sl, r7, [sp, #32] +100028be: 9303 str r3, [sp, #12] +100028c0: 9b0a ldr r3, [sp, #40] @ 0x28 +100028c2: f107 4b00 add.w fp, r7, #2147483648 @ 0x80000000 +100028c6: 9302 str r3, [sp, #8] +100028c8: f428 6300 bic.w r3, r8, #2048 @ 0x800 +100028cc: 9a0b ldr r2, [sp, #44] @ 0x2c +100028ce: 9304 str r3, [sp, #16] +100028d0: 4629 mov r1, r5 +100028d2: 4633 mov r3, r6 +100028d4: 4620 mov r0, r4 +100028d6: e9cd ab00 strd sl, fp, [sp] +100028da: f7ff fb15 bl 10001f08 <_ftoa> +100028de: 4602 mov r2, r0 +100028e0: e5d2 b.n 10002488 <_etoa+0xe8> +100028e2: 9b12 ldr r3, [sp, #72] @ 0x48 +100028e4: 4599 cmp r9, r3 +100028e6: d815 bhi.n 10002914 <_etoa+0x574> +100028e8: 9214 str r2, [sp, #80] @ 0x50 +100028ea: e7a1 b.n 10002830 <_etoa+0x490> +100028ec: 9b10 ldr r3, [sp, #64] @ 0x40 +100028ee: b123 cbz r3, 100028fa <_etoa+0x55a> +100028f0: 9b0a ldr r3, [sp, #40] @ 0x28 +100028f2: 9314 str r3, [sp, #80] @ 0x50 +100028f4: 2302 movs r3, #2 +100028f6: 9310 str r3, [sp, #64] @ 0x40 +100028f8: e79a b.n 10002830 <_etoa+0x490> +100028fa: 9b12 ldr r3, [sp, #72] @ 0x48 +100028fc: eba9 0303 sub.w r3, r9, r3 +10002900: 9314 str r3, [sp, #80] @ 0x50 +10002902: e795 b.n 10002830 <_etoa+0x490> +10002904: 1a9b subs r3, r3, r2 +10002906: 1e5f subs r7, r3, #1 +10002908: e643 b.n 10002592 <_etoa+0x1f2> +1000290a: 2304 movs r3, #4 +1000290c: 9312 str r3, [sp, #72] @ 0x48 +1000290e: 2302 movs r3, #2 +10002910: 9310 str r3, [sp, #64] @ 0x40 +10002912: e78d b.n 10002830 <_etoa+0x490> +10002914: 9b10 ldr r3, [sp, #64] @ 0x40 +10002916: 2b00 cmp r3, #0 +10002918: d0ef beq.n 100028fa <_etoa+0x55a> +1000291a: 2302 movs r3, #2 +1000291c: 9214 str r2, [sp, #80] @ 0x50 +1000291e: 9310 str r3, [sp, #64] @ 0x40 +10002920: e786 b.n 10002830 <_etoa+0x490> +10002922: bf00 nop + +10002924 <_vsnprintf>: +10002924: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002928: 4691 mov r9, r2 +1000292a: 4c9a ldr r4, [pc, #616] @ (10002b94 <_vsnprintf+0x270>) +1000292c: 4a9a ldr r2, [pc, #616] @ (10002b98 <_vsnprintf+0x274>) +1000292e: f1b1 0a00 subs.w sl, r1, #0 +10002932: b09b sub sp, #108 @ 0x6c +10002934: bf18 it ne +10002936: 4683 movne fp, r0 +10002938: 6014 str r4, [r2, #0] +1000293a: 7818 ldrb r0, [r3, #0] +1000293c: 4a97 ldr r2, [pc, #604] @ (10002b9c <_vsnprintf+0x278>) +1000293e: f8dd 8090 ldr.w r8, [sp, #144] @ 0x90 +10002942: bf08 it eq +10002944: 4693 moveq fp, r2 +10002946: 2800 cmp r0, #0 +10002948: f000 828a beq.w 10002e60 <_vsnprintf+0x53c> +1000294c: 461d mov r5, r3 +1000294e: 2600 movs r6, #0 +10002950: f8cd 9020 str.w r9, [sp, #32] +10002954: e008 b.n 10002968 <_vsnprintf+0x44> +10002956: 4632 mov r2, r6 +10002958: 4651 mov r1, sl +1000295a: 9b08 ldr r3, [sp, #32] +1000295c: 47d8 blx fp +1000295e: 3601 adds r6, #1 +10002960: 7828 ldrb r0, [r5, #0] +10002962: 2800 cmp r0, #0 +10002964: f000 80c7 beq.w 10002af6 <_vsnprintf+0x1d2> +10002968: 2825 cmp r0, #37 @ 0x25 +1000296a: f105 0501 add.w r5, r5, #1 +1000296e: d1f2 bne.n 10002956 <_vsnprintf+0x32> +10002970: 2200 movs r2, #0 +10002972: 462b mov r3, r5 +10002974: f813 1b01 ldrb.w r1, [r3], #1 +10002978: f1a1 0020 sub.w r0, r1, #32 +1000297c: 2810 cmp r0, #16 +1000297e: d80a bhi.n 10002996 <_vsnprintf+0x72> +10002980: e8df f000 tbb [pc, r0] +10002984: 3b09093f .word 0x3b09093f +10002988: 09090909 .word 0x09090909 +1000298c: 37090909 .word 0x37090909 +10002990: 09093309 .word 0x09093309 +10002994: 2f .byte 0x2f +10002995: 00 .byte 0x00 +10002996: f1a1 0030 sub.w r0, r1, #48 @ 0x30 +1000299a: 2809 cmp r0, #9 +1000299c: f240 8089 bls.w 10002ab2 <_vsnprintf+0x18e> +100029a0: 292a cmp r1, #42 @ 0x2a +100029a2: f000 80e9 beq.w 10002b78 <_vsnprintf+0x254> +100029a6: 2400 movs r4, #0 +100029a8: 292e cmp r1, #46 @ 0x2e +100029aa: f000 8094 beq.w 10002ad6 <_vsnprintf+0x1b2> +100029ae: 2700 movs r7, #0 +100029b0: f1a1 0068 sub.w r0, r1, #104 @ 0x68 +100029b4: 2812 cmp r0, #18 +100029b6: d82c bhi.n 10002a12 <_vsnprintf+0xee> +100029b8: e8df f010 tbh [pc, r0, lsl #1] +100029bc: 002b014e .word 0x002b014e +100029c0: 002b0149 .word 0x002b0149 +100029c4: 002b0140 .word 0x002b0140 +100029c8: 002b002b .word 0x002b002b +100029cc: 002b002b .word 0x002b002b +100029d0: 002b002b .word 0x002b002b +100029d4: 002b0027 .word 0x002b0027 +100029d8: 002b002b .word 0x002b002b +100029dc: 002b002b .word 0x002b002b +100029e0: 0027 .short 0x0027 +100029e2: 461d mov r5, r3 +100029e4: f042 0201 orr.w r2, r2, #1 +100029e8: e7c3 b.n 10002972 <_vsnprintf+0x4e> +100029ea: 461d mov r5, r3 +100029ec: f042 0202 orr.w r2, r2, #2 +100029f0: e7bf b.n 10002972 <_vsnprintf+0x4e> +100029f2: 461d mov r5, r3 +100029f4: f042 0204 orr.w r2, r2, #4 +100029f8: e7bb b.n 10002972 <_vsnprintf+0x4e> +100029fa: 461d mov r5, r3 +100029fc: f042 0210 orr.w r2, r2, #16 +10002a00: e7b7 b.n 10002972 <_vsnprintf+0x4e> +10002a02: 461d mov r5, r3 +10002a04: f042 0208 orr.w r2, r2, #8 +10002a08: e7b3 b.n 10002972 <_vsnprintf+0x4e> +10002a0a: 7869 ldrb r1, [r5, #1] +10002a0c: f442 7280 orr.w r2, r2, #256 @ 0x100 +10002a10: 3301 adds r3, #1 +10002a12: 2967 cmp r1, #103 @ 0x67 +10002a14: 461d mov r5, r3 +10002a16: d87e bhi.n 10002b16 <_vsnprintf+0x1f2> +10002a18: 2924 cmp r1, #36 @ 0x24 +10002a1a: f240 80b8 bls.w 10002b8e <_vsnprintf+0x26a> +10002a1e: f1a1 0325 sub.w r3, r1, #37 @ 0x25 +10002a22: 2b42 cmp r3, #66 @ 0x42 +10002a24: f200 80b3 bhi.w 10002b8e <_vsnprintf+0x26a> +10002a28: e8df f013 tbh [pc, r3, lsl #1] +10002a2c: 00b10151 .word 0x00b10151 +10002a30: 00b100b1 .word 0x00b100b1 +10002a34: 00b100b1 .word 0x00b100b1 +10002a38: 00b100b1 .word 0x00b100b1 +10002a3c: 00b100b1 .word 0x00b100b1 +10002a40: 00b100b1 .word 0x00b100b1 +10002a44: 00b100b1 .word 0x00b100b1 +10002a48: 00b100b1 .word 0x00b100b1 +10002a4c: 00b100b1 .word 0x00b100b1 +10002a50: 00b100b1 .word 0x00b100b1 +10002a54: 00b100b1 .word 0x00b100b1 +10002a58: 00b100b1 .word 0x00b100b1 +10002a5c: 00b100b1 .word 0x00b100b1 +10002a60: 00b100b1 .word 0x00b100b1 +10002a64: 00b100b1 .word 0x00b100b1 +10002a68: 00b100b1 .word 0x00b100b1 +10002a6c: 013a011e .word 0x013a011e +10002a70: 00b1011e .word 0x00b1011e +10002a74: 00b100b1 .word 0x00b100b1 +10002a78: 00b100b1 .word 0x00b100b1 +10002a7c: 00b100b1 .word 0x00b100b1 +10002a80: 00b100b1 .word 0x00b100b1 +10002a84: 00b100b1 .word 0x00b100b1 +10002a88: 00b100b1 .word 0x00b100b1 +10002a8c: 00b100b1 .word 0x00b100b1 +10002a90: 01b400b1 .word 0x01b400b1 +10002a94: 00b100b1 .word 0x00b100b1 +10002a98: 00b100b1 .word 0x00b100b1 +10002a9c: 00b100b1 .word 0x00b100b1 +10002aa0: 00b100b1 .word 0x00b100b1 +10002aa4: 01b400b1 .word 0x01b400b1 +10002aa8: 01b40158 .word 0x01b40158 +10002aac: 013a011e .word 0x013a011e +10002ab0: 011e .short 0x011e +10002ab2: 2400 movs r4, #0 +10002ab4: eb04 0484 add.w r4, r4, r4, lsl #2 +10002ab8: eb01 0444 add.w r4, r1, r4, lsl #1 +10002abc: 7819 ldrb r1, [r3, #0] +10002abe: 461d mov r5, r3 +10002ac0: f1a1 0030 sub.w r0, r1, #48 @ 0x30 +10002ac4: 2809 cmp r0, #9 +10002ac6: f1a4 0430 sub.w r4, r4, #48 @ 0x30 +10002aca: f103 0301 add.w r3, r3, #1 +10002ace: d9f1 bls.n 10002ab4 <_vsnprintf+0x190> +10002ad0: 292e cmp r1, #46 @ 0x2e +10002ad2: f47f af6c bne.w 100029ae <_vsnprintf+0x8a> +10002ad6: 7869 ldrb r1, [r5, #1] +10002ad8: 4618 mov r0, r3 +10002ada: f1a1 0730 sub.w r7, r1, #48 @ 0x30 +10002ade: 2f09 cmp r7, #9 +10002ae0: f442 6280 orr.w r2, r2, #1024 @ 0x400 +10002ae4: f240 8125 bls.w 10002d32 <_vsnprintf+0x40e> +10002ae8: 292a cmp r1, #42 @ 0x2a +10002aea: f000 8132 beq.w 10002d52 <_vsnprintf+0x42e> +10002aee: 461d mov r5, r3 +10002af0: 2700 movs r7, #0 +10002af2: 3301 adds r3, #1 +10002af4: e75c b.n 100029b0 <_vsnprintf+0x8c> +10002af6: 4634 mov r4, r6 +10002af8: f8dd 9020 ldr.w r9, [sp, #32] +10002afc: 45b1 cmp r9, r6 +10002afe: d801 bhi.n 10002b04 <_vsnprintf+0x1e0> +10002b00: f109 36ff add.w r6, r9, #4294967295 @ 0xffffffff +10002b04: 464b mov r3, r9 +10002b06: 4632 mov r2, r6 +10002b08: 4651 mov r1, sl +10002b0a: 2000 movs r0, #0 +10002b0c: 47d8 blx fp +10002b0e: 4620 mov r0, r4 +10002b10: b01b add sp, #108 @ 0x6c +10002b12: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002b16: f1a1 0369 sub.w r3, r1, #105 @ 0x69 +10002b1a: b2db uxtb r3, r3 +10002b1c: 2b0f cmp r3, #15 +10002b1e: d836 bhi.n 10002b8e <_vsnprintf+0x26a> +10002b20: 2001 movs r0, #1 +10002b22: f249 0c41 movw ip, #36929 @ 0x9041 +10002b26: 4098 lsls r0, r3 +10002b28: ea10 000c ands.w r0, r0, ip +10002b2c: f040 80f4 bne.w 10002d18 <_vsnprintf+0x3f4> +10002b30: 2b0a cmp r3, #10 +10002b32: d035 beq.n 10002ba0 <_vsnprintf+0x27c> +10002b34: 2b07 cmp r3, #7 +10002b36: d12a bne.n 10002b8e <_vsnprintf+0x26a> +10002b38: f858 1b04 ldr.w r1, [r8], #4 +10002b3c: 2900 cmp r1, #0 +10002b3e: f040 8110 bne.w 10002d62 <_vsnprintf+0x43e> +10002b42: f022 0410 bic.w r4, r2, #16 +10002b46: f412 6180 ands.w r1, r2, #1024 @ 0x400 +10002b4a: f044 0421 orr.w r4, r4, #33 @ 0x21 +10002b4e: f000 810a beq.w 10002d66 <_vsnprintf+0x442> +10002b52: aa12 add r2, sp, #72 @ 0x48 +10002b54: 2308 movs r3, #8 +10002b56: 9305 str r3, [sp, #20] +10002b58: 2310 movs r3, #16 +10002b5a: e9cd 2000 strd r2, r0, [sp] +10002b5e: 4632 mov r2, r6 +10002b60: 9406 str r4, [sp, #24] +10002b62: 9704 str r7, [sp, #16] +10002b64: 9303 str r3, [sp, #12] +10002b66: 2300 movs r3, #0 +10002b68: 9302 str r3, [sp, #8] +10002b6a: 4651 mov r1, sl +10002b6c: 4658 mov r0, fp +10002b6e: 9b08 ldr r3, [sp, #32] +10002b70: f7ff f8d0 bl 10001d14 <_ntoa_format> +10002b74: 4606 mov r6, r0 +10002b76: e6f3 b.n 10002960 <_vsnprintf+0x3c> +10002b78: f858 4b04 ldr.w r4, [r8], #4 +10002b7c: 7869 ldrb r1, [r5, #1] +10002b7e: 2c00 cmp r4, #0 +10002b80: 461d mov r5, r3 +10002b82: bfbc itt lt +10002b84: f042 0202 orrlt.w r2, r2, #2 +10002b88: 4264 neglt r4, r4 +10002b8a: 3301 adds r3, #1 +10002b8c: e70c b.n 100029a8 <_vsnprintf+0x84> +10002b8e: 4608 mov r0, r1 +10002b90: e6e1 b.n 10002956 <_vsnprintf+0x32> +10002b92: bf00 nop +10002b94: 10002925 .word 0x10002925 +10002b98: 200024e4 .word 0x200024e4 +10002b9c: 10001c69 .word 0x10001c69 +10002ba0: f858 9b04 ldr.w r9, [r8], #4 +10002ba4: 2f00 cmp r7, #0 +10002ba6: f899 0000 ldrb.w r0, [r9] +10002baa: bf14 ite ne +10002bac: 463b movne r3, r7 +10002bae: f04f 33ff moveq.w r3, #4294967295 @ 0xffffffff +10002bb2: 2800 cmp r0, #0 +10002bb4: f000 8382 beq.w 100032bc <_vsnprintf+0x998> +10002bb8: 4649 mov r1, r9 +10002bba: eb03 0c09 add.w ip, r3, r9 +10002bbe: e004 b.n 10002bca <_vsnprintf+0x2a6> +10002bc0: f811 3f01 ldrb.w r3, [r1, #1]! +10002bc4: 2b00 cmp r3, #0 +10002bc6: f000 8143 beq.w 10002e50 <_vsnprintf+0x52c> +10002bca: 458c cmp ip, r1 +10002bcc: d1f8 bne.n 10002bc0 <_vsnprintf+0x29c> +10002bce: ebac 0109 sub.w r1, ip, r9 +10002bd2: 0553 lsls r3, r2, #21 +10002bd4: f140 8120 bpl.w 10002e18 <_vsnprintf+0x4f4> +10002bd8: 42b9 cmp r1, r7 +10002bda: bf28 it cs +10002bdc: 4639 movcs r1, r7 +10002bde: f012 0302 ands.w r3, r2, #2 +10002be2: f000 8283 beq.w 100030ec <_vsnprintf+0x7c8> +10002be6: 2302 movs r3, #2 +10002be8: e9cd 4809 strd r4, r8, [sp, #36] @ 0x24 +10002bec: 4632 mov r2, r6 +10002bee: 4688 mov r8, r1 +10002bf0: 9c08 ldr r4, [sp, #32] +10002bf2: 4437 add r7, r6 +10002bf4: 930b str r3, [sp, #44] @ 0x2c +10002bf6: e007 b.n 10002c08 <_vsnprintf+0x2e4> +10002bf8: 4623 mov r3, r4 +10002bfa: 4651 mov r1, sl +10002bfc: 47d8 blx fp +10002bfe: f819 0f01 ldrb.w r0, [r9, #1]! +10002c02: 3601 adds r6, #1 +10002c04: b110 cbz r0, 10002c0c <_vsnprintf+0x2e8> +10002c06: 4632 mov r2, r6 +10002c08: 42b7 cmp r7, r6 +10002c0a: d1f5 bne.n 10002bf8 <_vsnprintf+0x2d4> +10002c0c: 9b0b ldr r3, [sp, #44] @ 0x2c +10002c0e: 4641 mov r1, r8 +10002c10: 9c09 ldr r4, [sp, #36] @ 0x24 +10002c12: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +10002c16: 2b00 cmp r3, #0 +10002c18: f43f aea2 beq.w 10002960 <_vsnprintf+0x3c> +10002c1c: 4637 mov r7, r6 +10002c1e: 428c cmp r4, r1 +10002c20: f67f ae9e bls.w 10002960 <_vsnprintf+0x3c> +10002c24: 4426 add r6, r4 +10002c26: 9c08 ldr r4, [sp, #32] +10002c28: 1a76 subs r6, r6, r1 +10002c2a: 463a mov r2, r7 +10002c2c: 4623 mov r3, r4 +10002c2e: 4651 mov r1, sl +10002c30: 2020 movs r0, #32 +10002c32: 3701 adds r7, #1 +10002c34: 47d8 blx fp +10002c36: 42b7 cmp r7, r6 +10002c38: d1f7 bne.n 10002c2a <_vsnprintf+0x306> +10002c3a: e691 b.n 10002960 <_vsnprintf+0x3c> +10002c3c: 7869 ldrb r1, [r5, #1] +10002c3e: 296c cmp r1, #108 @ 0x6c +10002c40: f47f aee4 bne.w 10002a0c <_vsnprintf+0xe8> +10002c44: 78a9 ldrb r1, [r5, #2] +10002c46: f442 7240 orr.w r2, r2, #768 @ 0x300 +10002c4a: 1ceb adds r3, r5, #3 +10002c4c: e6e1 b.n 10002a12 <_vsnprintf+0xee> +10002c4e: 7869 ldrb r1, [r5, #1] +10002c50: f442 7200 orr.w r2, r2, #512 @ 0x200 +10002c54: 3301 adds r3, #1 +10002c56: e6dc b.n 10002a12 <_vsnprintf+0xee> +10002c58: 7869 ldrb r1, [r5, #1] +10002c5a: 2968 cmp r1, #104 @ 0x68 +10002c5c: f000 80fb beq.w 10002e56 <_vsnprintf+0x532> +10002c60: f042 0280 orr.w r2, r2, #128 @ 0x80 +10002c64: 3301 adds r3, #1 +10002c66: e6d4 b.n 10002a12 <_vsnprintf+0xee> +10002c68: 2967 cmp r1, #103 @ 0x67 +10002c6a: f000 80c9 beq.w 10002e00 <_vsnprintf+0x4dc> +10002c6e: 2947 cmp r1, #71 @ 0x47 +10002c70: f000 80cd beq.w 10002e0e <_vsnprintf+0x4ea> +10002c74: 2945 cmp r1, #69 @ 0x45 +10002c76: f000 80cc beq.w 10002e12 <_vsnprintf+0x4ee> +10002c7a: e9cd 4203 strd r4, r2, [sp, #12] +10002c7e: f108 0807 add.w r8, r8, #7 +10002c82: 9702 str r7, [sp, #8] +10002c84: f028 0807 bic.w r8, r8, #7 +10002c88: 4632 mov r2, r6 +10002c8a: e8f8 6702 ldrd r6, r7, [r8], #8 +10002c8e: 4651 mov r1, sl +10002c90: e9cd 6700 strd r6, r7, [sp] +10002c94: 4658 mov r0, fp +10002c96: 9b08 ldr r3, [sp, #32] +10002c98: f7ff fb82 bl 100023a0 <_etoa> +10002c9c: 4606 mov r6, r0 +10002c9e: e65f b.n 10002960 <_vsnprintf+0x3c> +10002ca0: 2946 cmp r1, #70 @ 0x46 +10002ca2: bf08 it eq +10002ca4: f042 0220 orreq.w r2, r2, #32 +10002ca8: e9cd 4203 strd r4, r2, [sp, #12] +10002cac: f108 0807 add.w r8, r8, #7 +10002cb0: 9702 str r7, [sp, #8] +10002cb2: f028 0807 bic.w r8, r8, #7 +10002cb6: 4632 mov r2, r6 +10002cb8: e8f8 6702 ldrd r6, r7, [r8], #8 +10002cbc: 4651 mov r1, sl +10002cbe: e9cd 6700 strd r6, r7, [sp] +10002cc2: 4658 mov r0, fp +10002cc4: 9b08 ldr r3, [sp, #32] +10002cc6: f7ff f91f bl 10001f08 <_ftoa> +10002cca: 4606 mov r6, r0 +10002ccc: e648 b.n 10002960 <_vsnprintf+0x3c> +10002cce: 4632 mov r2, r6 +10002cd0: 4651 mov r1, sl +10002cd2: 2025 movs r0, #37 @ 0x25 +10002cd4: 9b08 ldr r3, [sp, #32] +10002cd6: 47d8 blx fp +10002cd8: 3601 adds r6, #1 +10002cda: e641 b.n 10002960 <_vsnprintf+0x3c> +10002cdc: f108 0304 add.w r3, r8, #4 +10002ce0: 0792 lsls r2, r2, #30 +10002ce2: 9309 str r3, [sp, #36] @ 0x24 +10002ce4: f106 0701 add.w r7, r6, #1 +10002ce8: f140 80c3 bpl.w 10002e72 <_vsnprintf+0x54e> +10002cec: 4632 mov r2, r6 +10002cee: 4651 mov r1, sl +10002cf0: f898 0000 ldrb.w r0, [r8] +10002cf4: 9b08 ldr r3, [sp, #32] +10002cf6: 47d8 blx fp +10002cf8: 2c01 cmp r4, #1 +10002cfa: f240 81b4 bls.w 10003066 <_vsnprintf+0x742> +10002cfe: 4426 add r6, r4 +10002d00: 9c08 ldr r4, [sp, #32] +10002d02: 463a mov r2, r7 +10002d04: 4623 mov r3, r4 +10002d06: 4651 mov r1, sl +10002d08: 2020 movs r0, #32 +10002d0a: 3701 adds r7, #1 +10002d0c: 47d8 blx fp +10002d0e: 42b7 cmp r7, r6 +10002d10: d1f7 bne.n 10002d02 <_vsnprintf+0x3de> +10002d12: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10002d16: e623 b.n 10002960 <_vsnprintf+0x3c> +10002d18: 296f cmp r1, #111 @ 0x6f +10002d1a: d074 beq.n 10002e06 <_vsnprintf+0x4e2> +10002d1c: f240 8241 bls.w 100031a2 <_vsnprintf+0x87e> +10002d20: 2978 cmp r1, #120 @ 0x78 +10002d22: f000 8186 beq.w 10003032 <_vsnprintf+0x70e> +10002d26: f04f 090a mov.w r9, #10 +10002d2a: f022 0210 bic.w r2, r2, #16 +10002d2e: 464b mov r3, r9 +10002d30: e038 b.n 10002da4 <_vsnprintf+0x480> +10002d32: 2700 movs r7, #0 +10002d34: eb07 0787 add.w r7, r7, r7, lsl #2 +10002d38: eb01 0147 add.w r1, r1, r7, lsl #1 +10002d3c: f1a1 0730 sub.w r7, r1, #48 @ 0x30 +10002d40: f810 1f01 ldrb.w r1, [r0, #1]! +10002d44: f1a1 0330 sub.w r3, r1, #48 @ 0x30 +10002d48: 2b09 cmp r3, #9 +10002d4a: d9f3 bls.n 10002d34 <_vsnprintf+0x410> +10002d4c: 4605 mov r5, r0 +10002d4e: 1c43 adds r3, r0, #1 +10002d50: e62e b.n 100029b0 <_vsnprintf+0x8c> +10002d52: f858 7b04 ldr.w r7, [r8], #4 +10002d56: 78a9 ldrb r1, [r5, #2] +10002d58: 3502 adds r5, #2 +10002d5a: 1c6b adds r3, r5, #1 +10002d5c: ea27 77e7 bic.w r7, r7, r7, asr #31 +10002d60: e626 b.n 100029b0 <_vsnprintf+0x8c> +10002d62: f042 0421 orr.w r4, r2, #33 @ 0x21 +10002d66: aa12 add r2, sp, #72 @ 0x48 +10002d68: 4694 mov ip, r2 +10002d6a: e002 b.n 10002d72 <_vsnprintf+0x44e> +10002d6c: 2820 cmp r0, #32 +10002d6e: f43f aef1 beq.w 10002b54 <_vsnprintf+0x230> +10002d72: f001 030f and.w r3, r1, #15 +10002d76: 2b09 cmp r3, #9 +10002d78: bf94 ite ls +10002d7a: 3330 addls r3, #48 @ 0x30 +10002d7c: 3337 addhi r3, #55 @ 0x37 +10002d7e: 290f cmp r1, #15 +10002d80: f88c 3000 strb.w r3, [ip] +10002d84: f100 0001 add.w r0, r0, #1 +10002d88: f10c 0c01 add.w ip, ip, #1 +10002d8c: ea4f 1111 mov.w r1, r1, lsr #4 +10002d90: d8ec bhi.n 10002d6c <_vsnprintf+0x448> +10002d92: e6df b.n 10002b54 <_vsnprintf+0x230> +10002d94: 2958 cmp r1, #88 @ 0x58 +10002d96: d066 beq.n 10002e66 <_vsnprintf+0x542> +10002d98: 2962 cmp r1, #98 @ 0x62 +10002d9a: f040 8089 bne.w 10002eb0 <_vsnprintf+0x58c> +10002d9e: f04f 0902 mov.w r9, #2 +10002da2: 464b mov r3, r9 +10002da4: f412 6c80 ands.w ip, r2, #1024 @ 0x400 +10002da8: f000 80d4 beq.w 10002f54 <_vsnprintf+0x630> +10002dac: f022 020d bic.w r2, r2, #13 +10002db0: 9209 str r2, [sp, #36] @ 0x24 +10002db2: f412 7100 ands.w r1, r2, #512 @ 0x200 +10002db6: f040 817b bne.w 100030b0 <_vsnprintf+0x78c> +10002dba: f412 7080 ands.w r0, r2, #256 @ 0x100 +10002dbe: f108 0904 add.w r9, r8, #4 +10002dc2: f040 8238 bne.w 10003236 <_vsnprintf+0x912> +10002dc6: 0651 lsls r1, r2, #25 +10002dc8: f140 813a bpl.w 10003040 <_vsnprintf+0x71c> +10002dcc: f898 1000 ldrb.w r1, [r8] +10002dd0: 2900 cmp r1, #0 +10002dd2: f040 814a bne.w 1000306a <_vsnprintf+0x746> +10002dd6: 9a09 ldr r2, [sp, #36] @ 0x24 +10002dd8: f022 0210 bic.w r2, r2, #16 +10002ddc: 9209 str r2, [sp, #36] @ 0x24 +10002dde: f1bc 0f00 cmp.w ip, #0 +10002de2: f000 8142 beq.w 1000306a <_vsnprintf+0x746> +10002de6: 4608 mov r0, r1 +10002de8: aa12 add r2, sp, #72 @ 0x48 +10002dea: 9909 ldr r1, [sp, #36] @ 0x24 +10002dec: e9cd 3703 strd r3, r7, [sp, #12] +10002df0: e9cd 4105 strd r4, r1, [sp, #20] +10002df4: 9001 str r0, [sp, #4] +10002df6: 2300 movs r3, #0 +10002df8: 9200 str r2, [sp, #0] +10002dfa: 9302 str r3, [sp, #8] +10002dfc: 4632 mov r2, r6 +10002dfe: e0a1 b.n 10002f44 <_vsnprintf+0x620> +10002e00: f442 6200 orr.w r2, r2, #2048 @ 0x800 +10002e04: e739 b.n 10002c7a <_vsnprintf+0x356> +10002e06: f04f 0908 mov.w r9, #8 +10002e0a: 464b mov r3, r9 +10002e0c: e7ca b.n 10002da4 <_vsnprintf+0x480> +10002e0e: f442 6200 orr.w r2, r2, #2048 @ 0x800 +10002e12: f042 0220 orr.w r2, r2, #32 +10002e16: e730 b.n 10002c7a <_vsnprintf+0x356> +10002e18: f012 0302 ands.w r3, r2, #2 +10002e1c: f000 818c beq.w 10003138 <_vsnprintf+0x814> +10002e20: 2302 movs r3, #2 +10002e22: e9cd 4809 strd r4, r8, [sp, #36] @ 0x24 +10002e26: 461f mov r7, r3 +10002e28: 4688 mov r8, r1 +10002e2a: 9c08 ldr r4, [sp, #32] +10002e2c: 4632 mov r2, r6 +10002e2e: 4623 mov r3, r4 +10002e30: 4651 mov r1, sl +10002e32: 47d8 blx fp +10002e34: f819 0f01 ldrb.w r0, [r9, #1]! +10002e38: 3601 adds r6, #1 +10002e3a: 2800 cmp r0, #0 +10002e3c: d1f6 bne.n 10002e2c <_vsnprintf+0x508> +10002e3e: 463b mov r3, r7 +10002e40: 4641 mov r1, r8 +10002e42: 9c09 ldr r4, [sp, #36] @ 0x24 +10002e44: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +10002e48: 2b00 cmp r3, #0 +10002e4a: f43f ad89 beq.w 10002960 <_vsnprintf+0x3c> +10002e4e: e6e5 b.n 10002c1c <_vsnprintf+0x2f8> +10002e50: eba1 0109 sub.w r1, r1, r9 +10002e54: e6bd b.n 10002bd2 <_vsnprintf+0x2ae> +10002e56: 78a9 ldrb r1, [r5, #2] +10002e58: f042 02c0 orr.w r2, r2, #192 @ 0xc0 +10002e5c: 1ceb adds r3, r5, #3 +10002e5e: e5d8 b.n 10002a12 <_vsnprintf+0xee> +10002e60: 4604 mov r4, r0 +10002e62: 4606 mov r6, r0 +10002e64: e64a b.n 10002afc <_vsnprintf+0x1d8> +10002e66: f04f 0910 mov.w r9, #16 +10002e6a: f042 0220 orr.w r2, r2, #32 +10002e6e: 464b mov r3, r9 +10002e70: e798 b.n 10002da4 <_vsnprintf+0x480> +10002e72: 2c01 cmp r4, #1 +10002e74: f240 80f1 bls.w 1000305a <_vsnprintf+0x736> +10002e78: 4637 mov r7, r6 +10002e7a: f106 39ff add.w r9, r6, #4294967295 @ 0xffffffff +10002e7e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10002e82: f8dd 8020 ldr.w r8, [sp, #32] +10002e86: 44a1 add r9, r4 +10002e88: 463a mov r2, r7 +10002e8a: 4643 mov r3, r8 +10002e8c: 4651 mov r1, sl +10002e8e: 2020 movs r0, #32 +10002e90: 3701 adds r7, #1 +10002e92: 47d8 blx fp +10002e94: 454f cmp r7, r9 +10002e96: d1f7 bne.n 10002e88 <_vsnprintf+0x564> +10002e98: f8dd 8028 ldr.w r8, [sp, #40] @ 0x28 +10002e9c: 463a mov r2, r7 +10002e9e: f898 0000 ldrb.w r0, [r8] +10002ea2: 4651 mov r1, sl +10002ea4: 9b08 ldr r3, [sp, #32] +10002ea6: 47d8 blx fp +10002ea8: 4426 add r6, r4 +10002eaa: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10002eae: e557 b.n 10002960 <_vsnprintf+0x3c> +10002eb0: f412 6380 ands.w r3, r2, #1024 @ 0x400 +10002eb4: f000 80c1 beq.w 1000303a <_vsnprintf+0x716> +10002eb8: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ebc: f022 0011 bic.w r0, r2, #17 +10002ec0: f410 7e00 ands.w lr, r0, #512 @ 0x200 +10002ec4: d14a bne.n 10002f5c <_vsnprintf+0x638> +10002ec6: f410 7c80 ands.w ip, r0, #256 @ 0x100 +10002eca: f108 0904 add.w r9, r8, #4 +10002ece: f040 8137 bne.w 10003140 <_vsnprintf+0x81c> +10002ed2: 0641 lsls r1, r0, #25 +10002ed4: f100 80a9 bmi.w 1000302a <_vsnprintf+0x706> +10002ed8: 0602 lsls r2, r0, #24 +10002eda: f140 81e3 bpl.w 100032a4 <_vsnprintf+0x980> +10002ede: f9b8 2000 ldrsh.w r2, [r8] +10002ee2: ea82 71e2 eor.w r1, r2, r2, asr #31 +10002ee6: eba1 71e2 sub.w r1, r1, r2, asr #31 +10002eea: fa1f fe81 uxth.w lr, r1 +10002eee: 0fd1 lsrs r1, r2, #31 +10002ef0: 9109 str r1, [sp, #36] @ 0x24 +10002ef2: 2a00 cmp r2, #0 +10002ef4: f000 815f beq.w 100031b6 <_vsnprintf+0x892> +10002ef8: 4673 mov r3, lr +10002efa: aa12 add r2, sp, #72 @ 0x48 +10002efc: 4696 mov lr, r2 +10002efe: f8df 83a0 ldr.w r8, [pc, #928] @ 100032a0 <_vsnprintf+0x97c> +10002f02: 940a str r4, [sp, #40] @ 0x28 +10002f04: e003 b.n 10002f0e <_vsnprintf+0x5ea> +10002f06: f1bc 0f20 cmp.w ip, #32 +10002f0a: 4623 mov r3, r4 +10002f0c: d00f beq.n 10002f2e <_vsnprintf+0x60a> +10002f0e: fba8 1403 umull r1, r4, r8, r3 +10002f12: 08e4 lsrs r4, r4, #3 +10002f14: eb04 0184 add.w r1, r4, r4, lsl #2 +10002f18: eba3 0141 sub.w r1, r3, r1, lsl #1 +10002f1c: f10e 0e01 add.w lr, lr, #1 +10002f20: 3130 adds r1, #48 @ 0x30 +10002f22: 2b09 cmp r3, #9 +10002f24: f10c 0c01 add.w ip, ip, #1 +10002f28: f80e 1c01 strb.w r1, [lr, #-1] +10002f2c: d8eb bhi.n 10002f06 <_vsnprintf+0x5e2> +10002f2e: 9c0a ldr r4, [sp, #40] @ 0x28 +10002f30: 9b09 ldr r3, [sp, #36] @ 0x24 +10002f32: 9200 str r2, [sp, #0] +10002f34: e9cd c301 strd ip, r3, [sp, #4] +10002f38: 230a movs r3, #10 +10002f3a: 4632 mov r2, r6 +10002f3c: e9cd 4005 strd r4, r0, [sp, #20] +10002f40: 9704 str r7, [sp, #16] +10002f42: 9303 str r3, [sp, #12] +10002f44: 4651 mov r1, sl +10002f46: 4658 mov r0, fp +10002f48: 9b08 ldr r3, [sp, #32] +10002f4a: f7fe fee3 bl 10001d14 <_ntoa_format> +10002f4e: 46c8 mov r8, r9 +10002f50: 4606 mov r6, r0 +10002f52: e505 b.n 10002960 <_vsnprintf+0x3c> +10002f54: f022 020c bic.w r2, r2, #12 +10002f58: 9209 str r2, [sp, #36] @ 0x24 +10002f5a: e72a b.n 10002db2 <_vsnprintf+0x48e> +10002f5c: f108 0807 add.w r8, r8, #7 +10002f60: f028 0807 bic.w r8, r8, #7 +10002f64: f8d8 2004 ldr.w r2, [r8, #4] +10002f68: f858 cb08 ldr.w ip, [r8], #8 +10002f6c: 0fd1 lsrs r1, r2, #31 +10002f6e: ea5c 0e02 orrs.w lr, ip, r2 +10002f72: d06c beq.n 1000304e <_vsnprintf+0x72a> +10002f74: 2a00 cmp r2, #0 +10002f76: 4663 mov r3, ip +10002f78: da02 bge.n 10002f80 <_vsnprintf+0x65c> +10002f7a: 425b negs r3, r3 +10002f7c: eb62 0242 sbc.w r2, r2, r2, lsl #1 +10002f80: 4691 mov r9, r2 +10002f82: 9309 str r3, [sp, #36] @ 0x24 +10002f84: aa12 add r2, sp, #72 @ 0x48 +10002f86: 4694 mov ip, r2 +10002f88: f04f 0e00 mov.w lr, #0 +10002f8c: e9cd 180a strd r1, r8, [sp, #40] @ 0x28 +10002f90: e9cd 470c strd r4, r7, [sp, #48] @ 0x30 +10002f94: 960e str r6, [sp, #56] @ 0x38 +10002f96: 920f str r2, [sp, #60] @ 0x3c +10002f98: e003 b.n 10002fa2 <_vsnprintf+0x67e> +10002f9a: f1be 0f20 cmp.w lr, #32 +10002f9e: 463b mov r3, r7 +10002fa0: d030 beq.n 10003004 <_vsnprintf+0x6e0> +10002fa2: f04f 32cc mov.w r2, #3435973836 @ 0xcccccccc +10002fa6: eb13 0109 adds.w r1, r3, r9 +10002faa: 4fbd ldr r7, [pc, #756] @ (100032a0 <_vsnprintf+0x97c>) +10002fac: f141 0100 adc.w r1, r1, #0 +10002fb0: fba7 4601 umull r4, r6, r7, r1 +10002fb4: f026 0403 bic.w r4, r6, #3 +10002fb8: eb04 0496 add.w r4, r4, r6, lsr #2 +10002fbc: 1b09 subs r1, r1, r4 +10002fbe: 1a5c subs r4, r3, r1 +10002fc0: fb02 f604 mul.w r6, r2, r4 +10002fc4: 463a mov r2, r7 +10002fc6: f169 0800 sbc.w r8, r9, #0 +10002fca: fb02 6608 mla r6, r2, r8, r6 +10002fce: 2205 movs r2, #5 +10002fd0: fba4 7407 umull r7, r4, r4, r7 +10002fd4: f007 0801 and.w r8, r7, #1 +10002fd8: 4426 add r6, r4 +10002fda: fba8 4802 umull r4, r8, r8, r2 +10002fde: 1864 adds r4, r4, r1 +10002fe0: 2b0a cmp r3, #10 +10002fe2: f10c 0c01 add.w ip, ip, #1 +10002fe6: ea4f 0757 mov.w r7, r7, lsr #1 +10002fea: f104 0430 add.w r4, r4, #48 @ 0x30 +10002fee: f179 0900 sbcs.w r9, r9, #0 +10002ff2: f10e 0e01 add.w lr, lr, #1 +10002ff6: f80c 4c01 strb.w r4, [ip, #-1] +10002ffa: ea47 77c6 orr.w r7, r7, r6, lsl #31 +10002ffe: ea4f 0956 mov.w r9, r6, lsr #1 +10003002: d2ca bcs.n 10002f9a <_vsnprintf+0x676> +10003004: 4673 mov r3, lr +10003006: e9dd 180a ldrd r1, r8, [sp, #40] @ 0x28 +1000300a: e9dd 470c ldrd r4, r7, [sp, #48] @ 0x30 +1000300e: 9e0e ldr r6, [sp, #56] @ 0x38 +10003010: 9a0f ldr r2, [sp, #60] @ 0x3c +10003012: f8cd e024 str.w lr, [sp, #36] @ 0x24 +10003016: e9cd 3101 strd r3, r1, [sp, #4] +1000301a: 230a movs r3, #10 +1000301c: 9200 str r2, [sp, #0] +1000301e: e9cd 4005 strd r4, r0, [sp, #20] +10003022: 4632 mov r2, r6 +10003024: 9704 str r7, [sp, #16] +10003026: 9303 str r3, [sp, #12] +10003028: e59f b.n 10002b6a <_vsnprintf+0x246> +1000302a: f898 2000 ldrb.w r2, [r8] +1000302e: 4696 mov lr, r2 +10003030: e75d b.n 10002eee <_vsnprintf+0x5ca> +10003032: f04f 0910 mov.w r9, #16 +10003036: 464b mov r3, r9 +10003038: e6b4 b.n 10002da4 <_vsnprintf+0x480> +1000303a: f022 0010 bic.w r0, r2, #16 +1000303e: e73f b.n 10002ec0 <_vsnprintf+0x59c> +10003040: 0611 lsls r1, r2, #24 +10003042: bf4c ite mi +10003044: f8b8 1000 ldrhmi.w r1, [r8] +10003048: f8d8 1000 ldrpl.w r1, [r8] +1000304c: e6c0 b.n 10002dd0 <_vsnprintf+0x4ac> +1000304e: 2b00 cmp r3, #0 +10003050: f040 8142 bne.w 100032d8 <_vsnprintf+0x9b4> +10003054: 4699 mov r9, r3 +10003056: 9309 str r3, [sp, #36] @ 0x24 +10003058: e794 b.n 10002f84 <_vsnprintf+0x660> +1000305a: 4632 mov r2, r6 +1000305c: 4651 mov r1, sl +1000305e: f898 0000 ldrb.w r0, [r8] +10003062: 9b08 ldr r3, [sp, #32] +10003064: 47d8 blx fp +10003066: 463e mov r6, r7 +10003068: e653 b.n 10002d12 <_vsnprintf+0x3ee> +1000306a: 9a09 ldr r2, [sp, #36] @ 0x24 +1000306c: 940a str r4, [sp, #40] @ 0x28 +1000306e: f012 0f20 tst.w r2, #32 +10003072: bf14 ite ne +10003074: f04f 0841 movne.w r8, #65 @ 0x41 +10003078: f04f 0861 moveq.w r8, #97 @ 0x61 +1000307c: aa12 add r2, sp, #72 @ 0x48 +1000307e: 4694 mov ip, r2 +10003080: f1a8 080a sub.w r8, r8, #10 +10003084: e002 b.n 1000308c <_vsnprintf+0x768> +10003086: 2820 cmp r0, #32 +10003088: 4671 mov r1, lr +1000308a: d00f beq.n 100030ac <_vsnprintf+0x788> +1000308c: fbb1 fef3 udiv lr, r1, r3 +10003090: fb03 141e mls r4, r3, lr, r1 +10003094: 2c09 cmp r4, #9 +10003096: bf94 ite ls +10003098: 3430 addls r4, #48 @ 0x30 +1000309a: 4444 addhi r4, r8 +1000309c: 4299 cmp r1, r3 +1000309e: f88c 4000 strb.w r4, [ip] +100030a2: f100 0001 add.w r0, r0, #1 +100030a6: f10c 0c01 add.w ip, ip, #1 +100030aa: d2ec bcs.n 10003086 <_vsnprintf+0x762> +100030ac: 9c0a ldr r4, [sp, #40] @ 0x28 +100030ae: e69c b.n 10002dea <_vsnprintf+0x4c6> +100030b0: f108 0807 add.w r8, r8, #7 +100030b4: f028 0807 bic.w r8, r8, #7 +100030b8: f8d8 2004 ldr.w r2, [r8, #4] +100030bc: f858 1b08 ldr.w r1, [r8], #8 +100030c0: 920a str r2, [sp, #40] @ 0x28 +100030c2: 430a orrs r2, r1 +100030c4: 468e mov lr, r1 +100030c6: d17b bne.n 100031c0 <_vsnprintf+0x89c> +100030c8: 9a09 ldr r2, [sp, #36] @ 0x24 +100030ca: f022 0210 bic.w r2, r2, #16 +100030ce: 9209 str r2, [sp, #36] @ 0x24 +100030d0: f1bc 0f00 cmp.w ip, #0 +100030d4: d074 beq.n 100031c0 <_vsnprintf+0x89c> +100030d6: 2000 movs r0, #0 +100030d8: aa12 add r2, sp, #72 @ 0x48 +100030da: 9909 ldr r1, [sp, #36] @ 0x24 +100030dc: e9cd 2000 strd r2, r0, [sp] +100030e0: e9cd 4105 strd r4, r1, [sp, #20] +100030e4: 4632 mov r2, r6 +100030e6: e9cd 3703 strd r3, r7, [sp, #12] +100030ea: e53c b.n 10002b66 <_vsnprintf+0x242> +100030ec: 428c cmp r4, r1 +100030ee: bf98 it ls +100030f0: 3101 addls r1, #1 +100030f2: f67f ad79 bls.w 10002be8 <_vsnprintf+0x2c4> +100030f6: f44f 6380 mov.w r3, #1024 @ 0x400 +100030fa: e9cd 9409 strd r9, r4, [sp, #36] @ 0x24 +100030fe: 4699 mov r9, r3 +10003100: 19a2 adds r2, r4, r6 +10003102: 970b str r7, [sp, #44] @ 0x2c +10003104: 9f08 ldr r7, [sp, #32] +10003106: 1a54 subs r4, r2, r1 +10003108: 4632 mov r2, r6 +1000310a: 463b mov r3, r7 +1000310c: 4651 mov r1, sl +1000310e: 2020 movs r0, #32 +10003110: 3601 adds r6, #1 +10003112: 47d8 blx fp +10003114: 42a6 cmp r6, r4 +10003116: d1f7 bne.n 10003108 <_vsnprintf+0x7e4> +10003118: e9dd 470a ldrd r4, r7, [sp, #40] @ 0x28 +1000311c: 464b mov r3, r9 +1000311e: f8dd 9024 ldr.w r9, [sp, #36] @ 0x24 +10003122: f899 0000 ldrb.w r0, [r9] +10003126: 2800 cmp r0, #0 +10003128: f43f ac1a beq.w 10002960 <_vsnprintf+0x3c> +1000312c: 1c61 adds r1, r4, #1 +1000312e: 2b00 cmp r3, #0 +10003130: f43f ae77 beq.w 10002e22 <_vsnprintf+0x4fe> +10003134: 2300 movs r3, #0 +10003136: e557 b.n 10002be8 <_vsnprintf+0x2c4> +10003138: 428c cmp r4, r1 +1000313a: d8de bhi.n 100030fa <_vsnprintf+0x7d6> +1000313c: 3101 adds r1, #1 +1000313e: e670 b.n 10002e22 <_vsnprintf+0x4fe> +10003140: f8d8 2000 ldr.w r2, [r8] +10003144: 0fd1 lsrs r1, r2, #31 +10003146: 2a00 cmp r2, #0 +10003148: f000 80b3 beq.w 100032b2 <_vsnprintf+0x98e> +1000314c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10003150: eba3 73e2 sub.w r3, r3, r2, asr #31 +10003154: aa12 add r2, sp, #72 @ 0x48 +10003156: 4694 mov ip, r2 +10003158: e9cd 1409 strd r1, r4, [sp, #36] @ 0x24 +1000315c: f8df 8140 ldr.w r8, [pc, #320] @ 100032a0 <_vsnprintf+0x97c> +10003160: e003 b.n 1000316a <_vsnprintf+0x846> +10003162: f1be 0f20 cmp.w lr, #32 +10003166: 4623 mov r3, r4 +10003168: d00f beq.n 1000318a <_vsnprintf+0x866> +1000316a: fba8 1403 umull r1, r4, r8, r3 +1000316e: 08e4 lsrs r4, r4, #3 +10003170: eb04 0184 add.w r1, r4, r4, lsl #2 +10003174: eba3 0141 sub.w r1, r3, r1, lsl #1 +10003178: f10c 0c01 add.w ip, ip, #1 +1000317c: 3130 adds r1, #48 @ 0x30 +1000317e: 2b09 cmp r3, #9 +10003180: f10e 0e01 add.w lr, lr, #1 +10003184: f80c 1c01 strb.w r1, [ip, #-1] +10003188: d8eb bhi.n 10003162 <_vsnprintf+0x83e> +1000318a: e9dd 1409 ldrd r1, r4, [sp, #36] @ 0x24 +1000318e: 230a movs r3, #10 +10003190: 9200 str r2, [sp, #0] +10003192: e9cd 4005 strd r4, r0, [sp, #20] +10003196: 4632 mov r2, r6 +10003198: e9cd e101 strd lr, r1, [sp, #4] +1000319c: 9704 str r7, [sp, #16] +1000319e: 9303 str r3, [sp, #12] +100031a0: e6d0 b.n 10002f44 <_vsnprintf+0x620> +100031a2: 2969 cmp r1, #105 @ 0x69 +100031a4: f022 0010 bic.w r0, r2, #16 +100031a8: f040 8091 bne.w 100032ce <_vsnprintf+0x9aa> +100031ac: f412 6380 ands.w r3, r2, #1024 @ 0x400 +100031b0: f43f ae86 beq.w 10002ec0 <_vsnprintf+0x59c> +100031b4: e680 b.n 10002eb8 <_vsnprintf+0x594> +100031b6: 2b00 cmp r3, #0 +100031b8: f43f ae9f beq.w 10002efa <_vsnprintf+0x5d6> +100031bc: aa12 add r2, sp, #72 @ 0x48 +100031be: e6b7 b.n 10002f30 <_vsnprintf+0x60c> +100031c0: 9a09 ldr r2, [sp, #36] @ 0x24 +100031c2: e9cd 840b strd r8, r4, [sp, #44] @ 0x2c +100031c6: f012 0f20 tst.w r2, #32 +100031ca: bf14 ite ne +100031cc: 2141 movne r1, #65 @ 0x41 +100031ce: 2161 moveq r1, #97 @ 0x61 +100031d0: e9cd 760d strd r7, r6, [sp, #52] @ 0x34 +100031d4: e9cd 3b0f strd r3, fp, [sp, #60] @ 0x3c +100031d8: f8cd a044 str.w sl, [sp, #68] @ 0x44 +100031dc: 2700 movs r7, #0 +100031de: 46f0 mov r8, lr +100031e0: 9c0a ldr r4, [sp, #40] @ 0x28 +100031e2: ae12 add r6, sp, #72 @ 0x48 +100031e4: f10d 0b48 add.w fp, sp, #72 @ 0x48 +100031e8: f1a1 0a0a sub.w sl, r1, #10 +100031ec: e003 b.n 100031f6 <_vsnprintf+0x8d2> +100031ee: 2f20 cmp r7, #32 +100031f0: 4680 mov r8, r0 +100031f2: 460c mov r4, r1 +100031f4: d013 beq.n 1000321e <_vsnprintf+0x8fa> +100031f6: 4621 mov r1, r4 +100031f8: 464a mov r2, r9 +100031fa: 2300 movs r3, #0 +100031fc: 4640 mov r0, r8 +100031fe: f009 f8cb bl 1000c398 <____aeabi_uldivmod_veneer> +10003202: b2d2 uxtb r2, r2 +10003204: 2a09 cmp r2, #9 +10003206: bf94 ite ls +10003208: 3230 addls r2, #48 @ 0x30 +1000320a: 4452 addhi r2, sl +1000320c: 45c8 cmp r8, r9 +1000320e: f174 0400 sbcs.w r4, r4, #0 +10003212: 7032 strb r2, [r6, #0] +10003214: f107 0701 add.w r7, r7, #1 +10003218: f106 0601 add.w r6, r6, #1 +1000321c: d2e7 bcs.n 100031ee <_vsnprintf+0x8ca> +1000321e: 4638 mov r0, r7 +10003220: e9dd 840b ldrd r8, r4, [sp, #44] @ 0x2c +10003224: 465a mov r2, fp +10003226: 9e0e ldr r6, [sp, #56] @ 0x38 +10003228: 9f0d ldr r7, [sp, #52] @ 0x34 +1000322a: 9b0f ldr r3, [sp, #60] @ 0x3c +1000322c: f8dd a044 ldr.w sl, [sp, #68] @ 0x44 +10003230: f8dd b040 ldr.w fp, [sp, #64] @ 0x40 +10003234: e751 b.n 100030da <_vsnprintf+0x7b6> +10003236: f8d8 e000 ldr.w lr, [r8] +1000323a: f1be 0f00 cmp.w lr, #0 +1000323e: d10d bne.n 1000325c <_vsnprintf+0x938> +10003240: f022 0210 bic.w r2, r2, #16 +10003244: 9209 str r2, [sp, #36] @ 0x24 +10003246: f1bc 0f00 cmp.w ip, #0 +1000324a: d007 beq.n 1000325c <_vsnprintf+0x938> +1000324c: aa12 add r2, sp, #72 @ 0x48 +1000324e: 9809 ldr r0, [sp, #36] @ 0x24 +10003250: e9cd 3703 strd r3, r7, [sp, #12] +10003254: e9cd 4005 strd r4, r0, [sp, #20] +10003258: 9101 str r1, [sp, #4] +1000325a: e5cc b.n 10002df6 <_vsnprintf+0x4d2> +1000325c: 9a09 ldr r2, [sp, #36] @ 0x24 +1000325e: f012 0f20 tst.w r2, #32 +10003262: bf14 ite ne +10003264: 2041 movne r0, #65 @ 0x41 +10003266: 2061 moveq r0, #97 @ 0x61 +10003268: aa12 add r2, sp, #72 @ 0x48 +1000326a: 4694 mov ip, r2 +1000326c: 920a str r2, [sp, #40] @ 0x28 +1000326e: f1a0 020a sub.w r2, r0, #10 +10003272: e002 b.n 1000327a <_vsnprintf+0x956> +10003274: 2920 cmp r1, #32 +10003276: 46c6 mov lr, r8 +10003278: d00f beq.n 1000329a <_vsnprintf+0x976> +1000327a: fbbe f8f3 udiv r8, lr, r3 +1000327e: fb03 e018 mls r0, r3, r8, lr +10003282: 2809 cmp r0, #9 +10003284: bf94 ite ls +10003286: 3030 addls r0, #48 @ 0x30 +10003288: 1880 addhi r0, r0, r2 +1000328a: 459e cmp lr, r3 +1000328c: f88c 0000 strb.w r0, [ip] +10003290: f101 0101 add.w r1, r1, #1 +10003294: f10c 0c01 add.w ip, ip, #1 +10003298: d2ec bcs.n 10003274 <_vsnprintf+0x950> +1000329a: 9a0a ldr r2, [sp, #40] @ 0x28 +1000329c: e7d7 b.n 1000324e <_vsnprintf+0x92a> +1000329e: bf00 nop +100032a0: cccccccd .word 0xcccccccd +100032a4: f8d8 2000 ldr.w r2, [r8] +100032a8: ea82 7ee2 eor.w lr, r2, r2, asr #31 +100032ac: ebae 7ee2 sub.w lr, lr, r2, asr #31 +100032b0: e61d b.n 10002eee <_vsnprintf+0x5ca> +100032b2: 2b00 cmp r3, #0 +100032b4: f43f af4e beq.w 10003154 <_vsnprintf+0x830> +100032b8: aa12 add r2, sp, #72 @ 0x48 +100032ba: e768 b.n 1000318e <_vsnprintf+0x86a> +100032bc: f412 6180 ands.w r1, r2, #1024 @ 0x400 +100032c0: d00e beq.n 100032e0 <_vsnprintf+0x9bc> +100032c2: f012 0102 ands.w r1, r2, #2 +100032c6: d014 beq.n 100032f2 <_vsnprintf+0x9ce> +100032c8: 4601 mov r1, r0 +100032ca: 4637 mov r7, r6 +100032cc: e4a7 b.n 10002c1e <_vsnprintf+0x2fa> +100032ce: f04f 090a mov.w r9, #10 +100032d2: 4602 mov r2, r0 +100032d4: 464b mov r3, r9 +100032d6: e565 b.n 10002da4 <_vsnprintf+0x480> +100032d8: 2300 movs r3, #0 +100032da: aa12 add r2, sp, #72 @ 0x48 +100032dc: 9309 str r3, [sp, #36] @ 0x24 +100032de: e69a b.n 10003016 <_vsnprintf+0x6f2> +100032e0: f012 0302 ands.w r3, r2, #2 +100032e4: f47f ac9a bne.w 10002c1c <_vsnprintf+0x2f8> +100032e8: 2c00 cmp r4, #0 +100032ea: f47f af06 bne.w 100030fa <_vsnprintf+0x7d6> +100032ee: f7ff bb37 b.w 10002960 <_vsnprintf+0x3c> +100032f2: 2c00 cmp r4, #0 +100032f4: f47f aeff bne.w 100030f6 <_vsnprintf+0x7d2> +100032f8: f7ff bb32 b.w 10002960 <_vsnprintf+0x3c> + +100032fc <__wrap_sprintf>: +100032fc: b40e push {r1, r2, r3} +100032fe: b500 push {lr} +10003300: b084 sub sp, #16 +10003302: f10d 0c14 add.w ip, sp, #20 +10003306: f85c 3b04 ldr.w r3, [ip], #4 +1000330a: 4601 mov r1, r0 +1000330c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003310: f8cd c000 str.w ip, [sp] +10003314: 4804 ldr r0, [pc, #16] @ (10003328 <__wrap_sprintf+0x2c>) +10003316: f8cd c00c str.w ip, [sp, #12] +1000331a: f7ff fb03 bl 10002924 <_vsnprintf> +1000331e: b004 add sp, #16 +10003320: f85d eb04 ldr.w lr, [sp], #4 +10003324: b003 add sp, #12 +10003326: 4770 bx lr +10003328: 10001c61 .word 0x10001c61 + +1000332c : +1000332c: 468c mov ip, r1 +1000332e: b510 push {r4, lr} +10003330: b084 sub sp, #16 +10003332: 9300 str r3, [sp, #0] +10003334: 9002 str r0, [sp, #8] +10003336: 4613 mov r3, r2 +10003338: a902 add r1, sp, #8 +1000333a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000333e: 4803 ldr r0, [pc, #12] @ (1000334c ) +10003340: f8cd c00c str.w ip, [sp, #12] +10003344: f7ff faee bl 10002924 <_vsnprintf> +10003348: b004 add sp, #16 +1000334a: bd10 pop {r4, pc} +1000334c: 10001ef9 .word 0x10001ef9 + +10003350 : +10003350: b510 push {r4, lr} +10003352: 4a09 ldr r2, [pc, #36] @ (10003378 ) +10003354: b084 sub sp, #16 +10003356: 6814 ldr r4, [r2, #0] +10003358: b14c cbz r4, 1000336e +1000335a: 4603 mov r3, r0 +1000335c: 9100 str r1, [sp, #0] +1000335e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003362: a903 add r1, sp, #12 +10003364: 4805 ldr r0, [pc, #20] @ (1000337c ) +10003366: 47a0 blx r4 +10003368: 2001 movs r0, #1 +1000336a: b004 add sp, #16 +1000336c: bd10 pop {r4, pc} +1000336e: f000 fa1b bl 100037a8 <__wrap_puts> +10003372: 4620 mov r0, r4 +10003374: b004 add sp, #16 +10003376: bd10 pop {r4, pc} +10003378: 200024e4 .word 0x200024e4 +1000337c: 10001ef1 .word 0x10001ef1 + +10003380 <_exit>: +10003380: be00 bkpt 0x0000 +10003382: e7fd b.n 10003380 <_exit> + +10003384 <_fini>: +10003384: 4770 bx lr +10003386: bf00 nop + +10003388 <_sbrk>: +10003388: 4a07 ldr r2, [pc, #28] @ (100033a8 <_sbrk+0x20>) +1000338a: 4603 mov r3, r0 +1000338c: 6810 ldr r0, [r2, #0] +1000338e: b138 cbz r0, 100033a0 <_sbrk+0x18> +10003390: 4906 ldr r1, [pc, #24] @ (100033ac <_sbrk+0x24>) +10003392: 4403 add r3, r0 +10003394: 428b cmp r3, r1 +10003396: bf8c ite hi +10003398: f04f 30ff movhi.w r0, #4294967295 @ 0xffffffff +1000339c: 6013 strls r3, [r2, #0] +1000339e: 4770 bx lr +100033a0: 4903 ldr r1, [pc, #12] @ (100033b0 <_sbrk+0x28>) +100033a2: 4608 mov r0, r1 +100033a4: 6011 str r1, [r2, #0] +100033a6: e7f3 b.n 10003390 <_sbrk+0x8> +100033a8: 200020e0 .word 0x200020e0 +100033ac: 20080000 .word 0x20080000 +100033b0: 20002544 .word 0x20002544 + +100033b4 : +100033b4: b508 push {r3, lr} +100033b6: f7ff ffe3 bl 10003380 <_exit> +100033ba: bf00 nop + +100033bc : +100033bc: b538 push {r3, r4, r5, lr} +100033be: 4c06 ldr r4, [pc, #24] @ (100033d8 ) +100033c0: 4d06 ldr r5, [pc, #24] @ (100033dc ) +100033c2: f7fe f9cd bl 10001760 +100033c6: 42ac cmp r4, r5 +100033c8: d204 bcs.n 100033d4 +100033ca: f854 3b04 ldr.w r3, [r4], #4 +100033ce: 4798 blx r3 +100033d0: 42ac cmp r4, r5 +100033d2: d3fa bcc.n 100033ca +100033d4: bd38 pop {r3, r4, r5, pc} +100033d6: bf00 nop +100033d8: 1000c408 .word 0x1000c408 +100033dc: 1000c40c .word 0x1000c40c + +100033e0 : +100033e0: 6803 ldr r3, [r0, #0] +100033e2: 4608 mov r0, r1 +100033e4: 4611 mov r1, r2 +100033e6: 4718 bx r3 + +100033e8 : +100033e8: b570 push {r4, r5, r6, lr} +100033ea: 4605 mov r5, r0 +100033ec: 4608 mov r0, r1 +100033ee: 7d69 ldrb r1, [r5, #21] +100033f0: b082 sub sp, #8 +100033f2: 2900 cmp r1, #0 +100033f4: d04f beq.n 10003496 +100033f6: 2a00 cmp r2, #0 +100033f8: dd25 ble.n 10003446 +100033fa: 7803 ldrb r3, [r0, #0] +100033fc: 4614 mov r4, r2 +100033fe: 2b0a cmp r3, #10 +10003400: 4606 mov r6, r0 +10003402: d022 beq.n 1000344a +10003404: 2c01 cmp r4, #1 +10003406: f04f 0e00 mov.w lr, #0 +1000340a: d00d beq.n 10003428 +1000340c: 4632 mov r2, r6 +1000340e: 2301 movs r3, #1 +10003410: f812 cf01 ldrb.w ip, [r2, #1]! +10003414: 4619 mov r1, r3 +10003416: f1bc 0f0a cmp.w ip, #10 +1000341a: f103 0301 add.w r3, r3, #1 +1000341e: d020 beq.n 10003462 +10003420: 429c cmp r4, r3 +10003422: d1f5 bne.n 10003410 +10003424: 4574 cmp r4, lr +10003426: dd05 ble.n 10003434 +10003428: 682b ldr r3, [r5, #0] +1000342a: eba4 010e sub.w r1, r4, lr +1000342e: eb06 000e add.w r0, r6, lr +10003432: 4798 blx r3 +10003434: 1931 adds r1, r6, r4 +10003436: f811 3c01 ldrb.w r3, [r1, #-1] +1000343a: f1a3 030d sub.w r3, r3, #13 +1000343e: fab3 f383 clz r3, r3 +10003442: 095b lsrs r3, r3, #5 +10003444: 752b strb r3, [r5, #20] +10003446: b002 add sp, #8 +10003448: bd70 pop {r4, r5, r6, pc} +1000344a: 7d2b ldrb r3, [r5, #20] +1000344c: 2b00 cmp r3, #0 +1000344e: d1d9 bne.n 10003404 +10003450: 2102 movs r1, #2 +10003452: 682b ldr r3, [r5, #0] +10003454: 4813 ldr r0, [pc, #76] @ (100034a4 ) +10003456: 4798 blx r3 +10003458: 2c01 cmp r4, #1 +1000345a: d0eb beq.n 10003434 +1000345c: f04f 0e01 mov.w lr, #1 +10003460: e7d4 b.n 1000340c +10003462: f812 0c01 ldrb.w r0, [r2, #-1] +10003466: 280d cmp r0, #13 +10003468: d0da beq.n 10003420 +1000346a: 458e cmp lr, r1 +1000346c: eb06 000e add.w r0, r6, lr +10003470: eba1 010e sub.w r1, r1, lr +10003474: da05 bge.n 10003482 +10003476: e9cd 3200 strd r3, r2, [sp] +1000347a: 682b ldr r3, [r5, #0] +1000347c: 4798 blx r3 +1000347e: e9dd 3200 ldrd r3, r2, [sp] +10003482: e9cd 3200 strd r3, r2, [sp] +10003486: 2102 movs r1, #2 +10003488: 682b ldr r3, [r5, #0] +1000348a: 4806 ldr r0, [pc, #24] @ (100034a4 ) +1000348c: 4798 blx r3 +1000348e: 9b00 ldr r3, [sp, #0] +10003490: 9a01 ldr r2, [sp, #4] +10003492: 469e mov lr, r3 +10003494: e7c4 b.n 10003420 +10003496: 4611 mov r1, r2 +10003498: 682b ldr r3, [r5, #0] +1000349a: b002 add sp, #8 +1000349c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +100034a0: 4718 bx r3 +100034a2: bf00 nop +100034a4: 1000ccf8 .word 0x1000ccf8 + +100034a8 : +100034a8: 680b ldr r3, [r1, #0] +100034aa: 1c5a adds r2, r3, #1 +100034ac: 2a80 cmp r2, #128 @ 0x80 +100034ae: 440b add r3, r1 +100034b0: 600a str r2, [r1, #0] +100034b2: 7118 strb r0, [r3, #4] +100034b4: d000 beq.n 100034b8 +100034b6: 4770 bx lr +100034b8: b530 push {r4, r5, lr} +100034ba: 4b0e ldr r3, [pc, #56] @ (100034f4 ) +100034bc: 460c mov r4, r1 +100034be: 6818 ldr r0, [r3, #0] +100034c0: b083 sub sp, #12 +100034c2: b1a0 cbz r0, 100034ee +100034c4: 1d0d adds r5, r1, #4 +100034c6: e001 b.n 100034cc +100034c8: 6900 ldr r0, [r0, #16] +100034ca: b180 cbz r0, 100034ee +100034cc: 6803 ldr r3, [r0, #0] +100034ce: 2b00 cmp r3, #0 +100034d0: d0fa beq.n 100034c8 +100034d2: 4b09 ldr r3, [pc, #36] @ (100034f8 ) +100034d4: 681b ldr r3, [r3, #0] +100034d6: b10b cbz r3, 100034dc +100034d8: 4283 cmp r3, r0 +100034da: d1f5 bne.n 100034c8 +100034dc: 4629 mov r1, r5 +100034de: 6822 ldr r2, [r4, #0] +100034e0: 9001 str r0, [sp, #4] +100034e2: f7ff ff81 bl 100033e8 +100034e6: 9801 ldr r0, [sp, #4] +100034e8: 6900 ldr r0, [r0, #16] +100034ea: 2800 cmp r0, #0 +100034ec: d1ee bne.n 100034cc +100034ee: 6020 str r0, [r4, #0] +100034f0: b003 add sp, #12 +100034f2: bd30 pop {r4, r5, pc} +100034f4: 20001ebc .word 0x20001ebc +100034f8: 20001ec8 .word 0x20001ec8 + +100034fc : +100034fc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10003500: b082 sub sp, #8 +10003502: 4690 mov r8, r2 +10003504: 461c mov r4, r3 +10003506: 460d mov r5, r1 +10003508: 4607 mov r7, r0 +1000350a: f7fd ff45 bl 10001398 +1000350e: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003512: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003516: 4a2e ldr r2, [pc, #184] @ (100035d0 ) +10003518: 1882 adds r2, r0, r2 +1000351a: f141 0300 adc.w r3, r1, #0 +1000351e: 4594 cmp ip, r2 +10003520: eb76 0103 sbcs.w r1, r6, r3 +10003524: bf3c itt cc +10003526: 4662 movcc r2, ip +10003528: 4633 movcc r3, r6 +1000352a: 482a ldr r0, [pc, #168] @ (100035d4 ) +1000352c: f008 ff40 bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003530: 1c6b adds r3, r5, #1 +10003532: 4682 mov sl, r0 +10003534: d040 beq.n 100035b8 +10003536: b30c cbz r4, 1000357c +10003538: 4e27 ldr r6, [pc, #156] @ (100035d8 ) +1000353a: 4b28 ldr r3, [pc, #160] @ (100035dc ) +1000353c: 681c ldr r4, [r3, #0] +1000353e: b1b4 cbz r4, 1000356e +10003540: f1b8 0f00 cmp.w r8, #0 +10003544: d11c bne.n 10003580 +10003546: f8df 809c ldr.w r8, [pc, #156] @ 100035e4 +1000354a: e001 b.n 10003550 +1000354c: 6924 ldr r4, [r4, #16] +1000354e: b174 cbz r4, 1000356e +10003550: 6823 ldr r3, [r4, #0] +10003552: 2b00 cmp r3, #0 +10003554: d0fa beq.n 1000354c +10003556: f8d8 3000 ldr.w r3, [r8] +1000355a: b10b cbz r3, 10003560 +1000355c: 429c cmp r4, r3 +1000355e: d1f5 bne.n 1000354c +10003560: 4620 mov r0, r4 +10003562: 462a mov r2, r5 +10003564: 4639 mov r1, r7 +10003566: 47b0 blx r6 +10003568: 6924 ldr r4, [r4, #16] +1000356a: 2c00 cmp r4, #0 +1000356c: d1f0 bne.n 10003550 +1000356e: f1ba 0f00 cmp.w sl, #0 +10003572: d126 bne.n 100035c2 +10003574: 4628 mov r0, r5 +10003576: b002 add sp, #8 +10003578: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000357c: 4e18 ldr r6, [pc, #96] @ (100035e0 ) +1000357e: e7dc b.n 1000353a +10003580: f04f 090a mov.w r9, #10 +10003584: f8df 805c ldr.w r8, [pc, #92] @ 100035e4 +10003588: e002 b.n 10003590 +1000358a: 6924 ldr r4, [r4, #16] +1000358c: 2c00 cmp r4, #0 +1000358e: d0ee beq.n 1000356e +10003590: 6823 ldr r3, [r4, #0] +10003592: 2b00 cmp r3, #0 +10003594: d0f9 beq.n 1000358a +10003596: f8d8 3000 ldr.w r3, [r8] +1000359a: b10b cbz r3, 100035a0 +1000359c: 42a3 cmp r3, r4 +1000359e: d1f4 bne.n 1000358a +100035a0: 462a mov r2, r5 +100035a2: 4639 mov r1, r7 +100035a4: 4620 mov r0, r4 +100035a6: 47b0 blx r6 +100035a8: 2201 movs r2, #1 +100035aa: 4620 mov r0, r4 +100035ac: f10d 0107 add.w r1, sp, #7 +100035b0: f88d 9007 strb.w r9, [sp, #7] +100035b4: 47b0 blx r6 +100035b6: e7e8 b.n 1000358a +100035b8: 4638 mov r0, r7 +100035ba: f008 fd55 bl 1000c068 +100035be: 4605 mov r5, r0 +100035c0: e7b9 b.n 10003536 +100035c2: 4804 ldr r0, [pc, #16] @ (100035d4 ) +100035c4: f008 fed8 bl 1000c378 <__mutex_exit_veneer> +100035c8: 4628 mov r0, r5 +100035ca: b002 add sp, #8 +100035cc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100035d0: 000f4240 .word 0x000f4240 +100035d4: 20001870 .word 0x20001870 +100035d8: 100033e9 .word 0x100033e9 +100035dc: 20001ebc .word 0x20001ebc +100035e0: 100033e1 .word 0x100033e1 +100035e4: 20001ec8 .word 0x20001ec8 + +100035e8 : +100035e8: b5f0 push {r4, r5, r6, r7, lr} +100035ea: b083 sub sp, #12 +100035ec: 4606 mov r6, r0 +100035ee: f88d 0007 strb.w r0, [sp, #7] +100035f2: f7fd fed1 bl 10001398 +100035f6: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100035fa: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100035fe: 4a17 ldr r2, [pc, #92] @ (1000365c ) +10003600: 1882 adds r2, r0, r2 +10003602: f141 0300 adc.w r3, r1, #0 +10003606: 4295 cmp r5, r2 +10003608: eb74 0103 sbcs.w r1, r4, r3 +1000360c: bf3c itt cc +1000360e: 4623 movcc r3, r4 +10003610: 462a movcc r2, r5 +10003612: 4813 ldr r0, [pc, #76] @ (10003660 ) +10003614: f008 fecc bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003618: 4b12 ldr r3, [pc, #72] @ (10003664 ) +1000361a: 4607 mov r7, r0 +1000361c: 681c ldr r4, [r3, #0] +1000361e: b19c cbz r4, 10003648 +10003620: 4d11 ldr r5, [pc, #68] @ (10003668 ) +10003622: e001 b.n 10003628 +10003624: 6924 ldr r4, [r4, #16] +10003626: b17c cbz r4, 10003648 +10003628: 6823 ldr r3, [r4, #0] +1000362a: 2b00 cmp r3, #0 +1000362c: d0fa beq.n 10003624 +1000362e: 682b ldr r3, [r5, #0] +10003630: b10b cbz r3, 10003636 +10003632: 429c cmp r4, r3 +10003634: d1f6 bne.n 10003624 +10003636: 4620 mov r0, r4 +10003638: 2201 movs r2, #1 +1000363a: f10d 0107 add.w r1, sp, #7 +1000363e: f7ff fecf bl 100033e0 +10003642: 6924 ldr r4, [r4, #16] +10003644: 2c00 cmp r4, #0 +10003646: d1ef bne.n 10003628 +10003648: b917 cbnz r7, 10003650 +1000364a: 4630 mov r0, r6 +1000364c: b003 add sp, #12 +1000364e: bdf0 pop {r4, r5, r6, r7, pc} +10003650: 4803 ldr r0, [pc, #12] @ (10003660 ) +10003652: f008 fe91 bl 1000c378 <__mutex_exit_veneer> +10003656: 4630 mov r0, r6 +10003658: b003 add sp, #12 +1000365a: bdf0 pop {r4, r5, r6, r7, pc} +1000365c: 000f4240 .word 0x000f4240 +10003660: 20001870 .word 0x20001870 +10003664: 20001ebc .word 0x20001ebc +10003668: 20001ec8 .word 0x20001ec8 + +1000366c : +1000366c: 4a08 ldr r2, [pc, #32] @ (10003690 ) +1000366e: 6813 ldr r3, [r2, #0] +10003670: b923 cbnz r3, 1000367c +10003672: e00a b.n 1000368a +10003674: f103 0210 add.w r2, r3, #16 +10003678: 691b ldr r3, [r3, #16] +1000367a: b133 cbz r3, 1000368a +1000367c: 4283 cmp r3, r0 +1000367e: d1f9 bne.n 10003674 +10003680: b929 cbnz r1, 1000368e +10003682: 6918 ldr r0, [r3, #16] +10003684: 6010 str r0, [r2, #0] +10003686: 6119 str r1, [r3, #16] +10003688: 4770 bx lr +1000368a: b101 cbz r1, 1000368e +1000368c: 6010 str r0, [r2, #0] +1000368e: 4770 bx lr +10003690: 20001ebc .word 0x20001ebc + +10003694 : +10003694: f000 bab6 b.w 10003c04 + +10003698 : +10003698: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000369c: b082 sub sp, #8 +1000369e: 4606 mov r6, r0 +100036a0: f7fd fe7a bl 10001398 +100036a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100036a8: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +100036ac: 1836 adds r6, r6, r0 +100036ae: f141 0700 adc.w r7, r1, #0 +100036b2: 42b2 cmp r2, r6 +100036b4: eb73 0107 sbcs.w r1, r3, r7 +100036b8: bf3c itt cc +100036ba: 4616 movcc r6, r2 +100036bc: 461f movcc r7, r3 +100036be: f8df 8060 ldr.w r8, [pc, #96] @ 10003720 +100036c2: 4d15 ldr r5, [pc, #84] @ (10003718 ) +100036c4: f8d8 4000 ldr.w r4, [r8] +100036c8: b914 cbnz r4, 100036d0 +100036ca: e012 b.n 100036f2 +100036cc: 6924 ldr r4, [r4, #16] +100036ce: b184 cbz r4, 100036f2 +100036d0: 682b ldr r3, [r5, #0] +100036d2: b10b cbz r3, 100036d8 +100036d4: 429c cmp r4, r3 +100036d6: d1f9 bne.n 100036cc +100036d8: 68a3 ldr r3, [r4, #8] +100036da: 2b00 cmp r3, #0 +100036dc: d0f6 beq.n 100036cc +100036de: 2101 movs r1, #1 +100036e0: a801 add r0, sp, #4 +100036e2: 4798 blx r3 +100036e4: 2800 cmp r0, #0 +100036e6: ddf1 ble.n 100036cc +100036e8: f89d 0004 ldrb.w r0, [sp, #4] +100036ec: b002 add sp, #8 +100036ee: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100036f2: 4b0a ldr r3, [pc, #40] @ (1000371c ) +100036f4: 6a5a ldr r2, [r3, #36] @ 0x24 +100036f6: 4297 cmp r7, r2 +100036f8: d809 bhi.n 1000370e +100036fa: 6a9b ldr r3, [r3, #40] @ 0x28 +100036fc: 42b3 cmp r3, r6 +100036fe: d304 bcc.n 1000370a +10003700: f06f 0001 mvn.w r0, #1 +10003704: b002 add sp, #8 +10003706: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000370a: 4297 cmp r7, r2 +1000370c: d1f8 bne.n 10003700 +1000370e: 2001 movs r0, #1 +10003710: 2100 movs r1, #0 +10003712: f7fd fe4b bl 100013ac +10003716: e7d5 b.n 100036c4 +10003718: 20001ec8 .word 0x20001ec8 +1000371c: 400b0000 .word 0x400b0000 +10003720: 20001ebc .word 0x20001ebc + +10003724 <__wrap_putchar>: +10003724: b5f0 push {r4, r5, r6, r7, lr} +10003726: b083 sub sp, #12 +10003728: 4606 mov r6, r0 +1000372a: f88d 0007 strb.w r0, [sp, #7] +1000372e: f7fd fe33 bl 10001398 +10003732: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10003736: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000373a: 4a17 ldr r2, [pc, #92] @ (10003798 <__wrap_putchar+0x74>) +1000373c: 1882 adds r2, r0, r2 +1000373e: f141 0300 adc.w r3, r1, #0 +10003742: 4295 cmp r5, r2 +10003744: eb74 0103 sbcs.w r1, r4, r3 +10003748: bf3c itt cc +1000374a: 4623 movcc r3, r4 +1000374c: 462a movcc r2, r5 +1000374e: 4813 ldr r0, [pc, #76] @ (1000379c <__wrap_putchar+0x78>) +10003750: f008 fe2e bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003754: 4b12 ldr r3, [pc, #72] @ (100037a0 <__wrap_putchar+0x7c>) +10003756: 4607 mov r7, r0 +10003758: 681c ldr r4, [r3, #0] +1000375a: b19c cbz r4, 10003784 <__wrap_putchar+0x60> +1000375c: 4d11 ldr r5, [pc, #68] @ (100037a4 <__wrap_putchar+0x80>) +1000375e: e001 b.n 10003764 <__wrap_putchar+0x40> +10003760: 6924 ldr r4, [r4, #16] +10003762: b17c cbz r4, 10003784 <__wrap_putchar+0x60> +10003764: 6823 ldr r3, [r4, #0] +10003766: 2b00 cmp r3, #0 +10003768: d0fa beq.n 10003760 <__wrap_putchar+0x3c> +1000376a: 682b ldr r3, [r5, #0] +1000376c: b10b cbz r3, 10003772 <__wrap_putchar+0x4e> +1000376e: 429c cmp r4, r3 +10003770: d1f6 bne.n 10003760 <__wrap_putchar+0x3c> +10003772: 4620 mov r0, r4 +10003774: 2201 movs r2, #1 +10003776: f10d 0107 add.w r1, sp, #7 +1000377a: f7ff fe35 bl 100033e8 +1000377e: 6924 ldr r4, [r4, #16] +10003780: 2c00 cmp r4, #0 +10003782: d1ef bne.n 10003764 <__wrap_putchar+0x40> +10003784: b917 cbnz r7, 1000378c <__wrap_putchar+0x68> +10003786: 4630 mov r0, r6 +10003788: b003 add sp, #12 +1000378a: bdf0 pop {r4, r5, r6, r7, pc} +1000378c: 4803 ldr r0, [pc, #12] @ (1000379c <__wrap_putchar+0x78>) +1000378e: f008 fdf3 bl 1000c378 <__mutex_exit_veneer> +10003792: 4630 mov r0, r6 +10003794: b003 add sp, #12 +10003796: bdf0 pop {r4, r5, r6, r7, pc} +10003798: 000f4240 .word 0x000f4240 +1000379c: 20001870 .word 0x20001870 +100037a0: 20001ebc .word 0x20001ebc +100037a4: 20001ec8 .word 0x20001ec8 + +100037a8 <__wrap_puts>: +100037a8: b538 push {r3, r4, r5, lr} +100037aa: 4604 mov r4, r0 +100037ac: f008 fc5c bl 1000c068 +100037b0: 2301 movs r3, #1 +100037b2: 4605 mov r5, r0 +100037b4: 461a mov r2, r3 +100037b6: 4620 mov r0, r4 +100037b8: 4629 mov r1, r5 +100037ba: f7ff fe9f bl 100034fc +100037be: 4b08 ldr r3, [pc, #32] @ (100037e0 <__wrap_puts+0x38>) +100037c0: 681c ldr r4, [r3, #0] +100037c2: b12c cbz r4, 100037d0 <__wrap_puts+0x28> +100037c4: 6863 ldr r3, [r4, #4] +100037c6: b12b cbz r3, 100037d4 <__wrap_puts+0x2c> +100037c8: 4798 blx r3 +100037ca: 6924 ldr r4, [r4, #16] +100037cc: 2c00 cmp r4, #0 +100037ce: d1f9 bne.n 100037c4 <__wrap_puts+0x1c> +100037d0: 4628 mov r0, r5 +100037d2: bd38 pop {r3, r4, r5, pc} +100037d4: 6924 ldr r4, [r4, #16] +100037d6: 2c00 cmp r4, #0 +100037d8: d1f4 bne.n 100037c4 <__wrap_puts+0x1c> +100037da: 4628 mov r0, r5 +100037dc: bd38 pop {r3, r4, r5, pc} +100037de: bf00 nop +100037e0: 20001ebc .word 0x20001ebc + +100037e4 <__wrap_vprintf>: +100037e4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100037e8: b0a2 sub sp, #136 @ 0x88 +100037ea: 460e mov r6, r1 +100037ec: 4605 mov r5, r0 +100037ee: f7fd fdd3 bl 10001398 +100037f2: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +100037f6: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100037fa: 4a25 ldr r2, [pc, #148] @ (10003890 <__wrap_vprintf+0xac>) +100037fc: 1882 adds r2, r0, r2 +100037fe: f141 0300 adc.w r3, r1, #0 +10003802: 4594 cmp ip, r2 +10003804: eb74 0103 sbcs.w r1, r4, r3 +10003808: bf3c itt cc +1000380a: 4623 movcc r3, r4 +1000380c: 4662 movcc r2, ip +1000380e: 4821 ldr r0, [pc, #132] @ (10003894 <__wrap_vprintf+0xb0>) +10003810: f008 fdce bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003814: 2400 movs r4, #0 +10003816: 4633 mov r3, r6 +10003818: 4607 mov r7, r0 +1000381a: 462a mov r2, r5 +1000381c: 481e ldr r0, [pc, #120] @ (10003898 <__wrap_vprintf+0xb4>) +1000381e: a901 add r1, sp, #4 +10003820: 9401 str r4, [sp, #4] +10003822: f7ff fd83 bl 1000332c +10003826: 4e1d ldr r6, [pc, #116] @ (1000389c <__wrap_vprintf+0xb8>) +10003828: 9b01 ldr r3, [sp, #4] +1000382a: 4680 mov r8, r0 +1000382c: 6834 ldr r4, [r6, #0] +1000382e: b1bb cbz r3, 10003860 <__wrap_vprintf+0x7c> +10003830: 2c00 cmp r4, #0 +10003832: d02a beq.n 1000388a <__wrap_vprintf+0xa6> +10003834: 4d1a ldr r5, [pc, #104] @ (100038a0 <__wrap_vprintf+0xbc>) +10003836: e001 b.n 1000383c <__wrap_vprintf+0x58> +10003838: 6924 ldr r4, [r4, #16] +1000383a: b174 cbz r4, 1000385a <__wrap_vprintf+0x76> +1000383c: 6823 ldr r3, [r4, #0] +1000383e: 2b00 cmp r3, #0 +10003840: d0fa beq.n 10003838 <__wrap_vprintf+0x54> +10003842: 682b ldr r3, [r5, #0] +10003844: b10b cbz r3, 1000384a <__wrap_vprintf+0x66> +10003846: 42a3 cmp r3, r4 +10003848: d1f6 bne.n 10003838 <__wrap_vprintf+0x54> +1000384a: 4620 mov r0, r4 +1000384c: 9a01 ldr r2, [sp, #4] +1000384e: a902 add r1, sp, #8 +10003850: f7ff fdca bl 100033e8 +10003854: 6924 ldr r4, [r4, #16] +10003856: 2c00 cmp r4, #0 +10003858: d1f0 bne.n 1000383c <__wrap_vprintf+0x58> +1000385a: 4623 mov r3, r4 +1000385c: 6834 ldr r4, [r6, #0] +1000385e: 9301 str r3, [sp, #4] +10003860: b12c cbz r4, 1000386e <__wrap_vprintf+0x8a> +10003862: 6863 ldr r3, [r4, #4] +10003864: b143 cbz r3, 10003878 <__wrap_vprintf+0x94> +10003866: 4798 blx r3 +10003868: 6924 ldr r4, [r4, #16] +1000386a: 2c00 cmp r4, #0 +1000386c: d1f9 bne.n 10003862 <__wrap_vprintf+0x7e> +1000386e: b92f cbnz r7, 1000387c <__wrap_vprintf+0x98> +10003870: 4640 mov r0, r8 +10003872: b022 add sp, #136 @ 0x88 +10003874: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003878: 6924 ldr r4, [r4, #16] +1000387a: e7f1 b.n 10003860 <__wrap_vprintf+0x7c> +1000387c: 4805 ldr r0, [pc, #20] @ (10003894 <__wrap_vprintf+0xb0>) +1000387e: f008 fd7b bl 1000c378 <__mutex_exit_veneer> +10003882: 4640 mov r0, r8 +10003884: b022 add sp, #136 @ 0x88 +10003886: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000388a: 9401 str r4, [sp, #4] +1000388c: e7ef b.n 1000386e <__wrap_vprintf+0x8a> +1000388e: bf00 nop +10003890: 000f4240 .word 0x000f4240 +10003894: 20001870 .word 0x20001870 +10003898: 100034a9 .word 0x100034a9 +1000389c: 20001ebc .word 0x20001ebc +100038a0: 20001ec8 .word 0x20001ec8 + +100038a4 <__wrap_printf>: +100038a4: b40f push {r0, r1, r2, r3} +100038a6: b500 push {lr} +100038a8: b083 sub sp, #12 +100038aa: a904 add r1, sp, #16 +100038ac: f851 0b04 ldr.w r0, [r1], #4 +100038b0: 9101 str r1, [sp, #4] +100038b2: f7ff ff97 bl 100037e4 <__wrap_vprintf> +100038b6: b003 add sp, #12 +100038b8: f85d eb04 ldr.w lr, [sp], #4 +100038bc: b004 add sp, #16 +100038be: 4770 bx lr + +100038c0 : +100038c0: 4a02 ldr r2, [pc, #8] @ (100038cc ) +100038c2: 4b03 ldr r3, [pc, #12] @ (100038d0 ) +100038c4: 6010 str r0, [r2, #0] +100038c6: 6019 str r1, [r3, #0] +100038c8: 4770 bx lr +100038ca: bf00 nop +100038cc: 20001e5c .word 0x20001e5c +100038d0: 20001e60 .word 0x20001e60 + +100038d4 : +100038d4: 4b18 ldr r3, [pc, #96] @ (10003938 ) +100038d6: b570 push {r4, r5, r6, lr} +100038d8: 681a ldr r2, [r3, #0] +100038da: 2a00 cmp r2, #0 +100038dc: d028 beq.n 10003930 +100038de: f3ef 8110 mrs r1, PRIMASK +100038e2: b672 cpsid i +100038e4: e8d2 4fcf ldaexb r4, [r2] +100038e8: 2001 movs r0, #1 +100038ea: 2c00 cmp r4, #0 +100038ec: d1fa bne.n 100038e4 +100038ee: e8c2 0f44 strexb r4, r0, [r2] +100038f2: 2c00 cmp r4, #0 +100038f4: d1f6 bne.n 100038e4 +100038f6: f3bf 8f5f dmb sy +100038fa: 2200 movs r2, #0 +100038fc: 4c0f ldr r4, [pc, #60] @ (1000393c ) +100038fe: 6818 ldr r0, [r3, #0] +10003900: 6059 str r1, [r3, #4] +10003902: 7022 strb r2, [r4, #0] +10003904: e8c0 2f8f stlb r2, [r0] +10003908: f381 8810 msr PRIMASK, r1 +1000390c: 2400 movs r4, #0 +1000390e: 2500 movs r5, #0 +10003910: 4e0b ldr r6, [pc, #44] @ (10003940 ) +10003912: 7830 ldrb r0, [r6, #0] +10003914: f7fc ff08 bl 10000728 +10003918: b920 cbnz r0, 10003924 +1000391a: 2400 movs r4, #0 +1000391c: 2500 movs r5, #0 +1000391e: 4620 mov r0, r4 +10003920: 4629 mov r1, r5 +10003922: bd70 pop {r4, r5, r6, pc} +10003924: 7830 ldrb r0, [r6, #0] +10003926: f7fc ff0f bl 10000748 +1000392a: 4620 mov r0, r4 +1000392c: 4629 mov r1, r5 +1000392e: bd70 pop {r4, r5, r6, pc} +10003930: f44f 747a mov.w r4, #1000 @ 0x3e8 +10003934: 2500 movs r5, #0 +10003936: e7eb b.n 10003910 +10003938: 200024f0 .word 0x200024f0 +1000393c: 20002541 .word 0x20002541 +10003940: 20002540 .word 0x20002540 + +10003944 : +10003944: 4b01 ldr r3, [pc, #4] @ (1000394c ) +10003946: 7818 ldrb r0, [r3, #0] +10003948: f7fc befe b.w 10000748 +1000394c: 20002540 .word 0x20002540 + +10003950 : +10003950: b538 push {r3, r4, r5, lr} +10003952: 4604 mov r4, r0 +10003954: 2000 movs r0, #0 +10003956: 460d mov r5, r1 +10003958: f001 fba6 bl 100050a8 +1000395c: b3a8 cbz r0, 100039ca +1000395e: 2000 movs r0, #0 +10003960: f001 fbb8 bl 100050d4 +10003964: b388 cbz r0, 100039ca +10003966: f7fd fd17 bl 10001398 +1000396a: f04f 3eff mov.w lr, #4294967295 @ 0xffffffff +1000396e: f06f 4c00 mvn.w ip, #2147483648 @ 0x80000000 +10003972: 4a17 ldr r2, [pc, #92] @ (100039d0 ) +10003974: 1882 adds r2, r0, r2 +10003976: f141 0300 adc.w r3, r1, #0 +1000397a: 4596 cmp lr, r2 +1000397c: eb7c 0103 sbcs.w r1, ip, r3 +10003980: bf3c itt cc +10003982: 4672 movcc r2, lr +10003984: 4663 movcc r3, ip +10003986: 4813 ldr r0, [pc, #76] @ (100039d4 ) +10003988: f008 fd12 bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +1000398c: b1e8 cbz r0, 100039ca +1000398e: 2000 movs r0, #0 +10003990: f001 fb8a bl 100050a8 +10003994: b958 cbnz r0, 100039ae +10003996: 4601 mov r1, r0 +10003998: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000399c: f000 fd8e bl 100044bc +100039a0: f06f 0402 mvn.w r4, #2 +100039a4: 480b ldr r0, [pc, #44] @ (100039d4 ) +100039a6: f008 fce7 bl 1000c378 <__mutex_exit_veneer> +100039aa: 4620 mov r0, r4 +100039ac: bd38 pop {r3, r4, r5, pc} +100039ae: 2000 movs r0, #0 +100039b0: f001 fb90 bl 100050d4 +100039b4: 2800 cmp r0, #0 +100039b6: d0ee beq.n 10003996 +100039b8: 4621 mov r1, r4 +100039ba: 462a mov r2, r5 +100039bc: 2000 movs r0, #0 +100039be: f001 fb93 bl 100050e8 +100039c2: 4604 mov r4, r0 +100039c4: 2800 cmp r0, #0 +100039c6: d1ed bne.n 100039a4 +100039c8: e7ea b.n 100039a0 +100039ca: f06f 0402 mvn.w r4, #2 +100039ce: e7ec b.n 100039aa +100039d0: 000f4240 .word 0x000f4240 +100039d4: 20002520 .word 0x20002520 + +100039d8 : +100039d8: b508 push {r3, lr} +100039da: f7fd fcdd bl 10001398 +100039de: f04f 3eff mov.w lr, #4294967295 @ 0xffffffff +100039e2: f06f 4c00 mvn.w ip, #2147483648 @ 0x80000000 +100039e6: 4a0f ldr r2, [pc, #60] @ (10003a24 ) +100039e8: 1882 adds r2, r0, r2 +100039ea: f141 0300 adc.w r3, r1, #0 +100039ee: 4596 cmp lr, r2 +100039f0: eb7c 0103 sbcs.w r1, ip, r3 +100039f4: bf3c itt cc +100039f6: 4672 movcc r2, lr +100039f8: 4663 movcc r3, ip +100039fa: 480b ldr r0, [pc, #44] @ (10003a28 ) +100039fc: f008 fcd8 bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003a00: b170 cbz r0, 10003a20 +10003a02: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10003a06: 2100 movs r1, #0 +10003a08: f000 fd58 bl 100044bc +10003a0c: 2000 movs r0, #0 +10003a0e: f001 fbb1 bl 10005174 +10003a12: 2800 cmp r0, #0 +10003a14: d1f5 bne.n 10003a02 +10003a16: e8bd 4008 ldmia.w sp!, {r3, lr} +10003a1a: 4803 ldr r0, [pc, #12] @ (10003a28 ) +10003a1c: f008 bcac b.w 1000c378 <__mutex_exit_veneer> +10003a20: bd08 pop {r3, pc} +10003a22: bf00 nop +10003a24: 000f4240 .word 0x000f4240 +10003a28: 20002520 .word 0x20002520 + +10003a2c : +10003a2c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003a30: 4607 mov r7, r0 +10003a32: 460e mov r6, r1 +10003a34: f7fd fcb0 bl 10001398 +10003a38: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10003a3c: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10003a40: 4a32 ldr r2, [pc, #200] @ (10003b0c ) +10003a42: 1882 adds r2, r0, r2 +10003a44: f141 0300 adc.w r3, r1, #0 +10003a48: 4295 cmp r5, r2 +10003a4a: eb74 0103 sbcs.w r1, r4, r3 +10003a4e: bf3c itt cc +10003a50: 462a movcc r2, r5 +10003a52: 4623 movcc r3, r4 +10003a54: 482e ldr r0, [pc, #184] @ (10003b10 ) +10003a56: f008 fcab bl 1000c3b0 <__mutex_try_enter_block_until_veneer> +10003a5a: b908 cbnz r0, 10003a60 +10003a5c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003a60: 2000 movs r0, #0 +10003a62: f001 fb21 bl 100050a8 +10003a66: 2800 cmp r0, #0 +10003a68: d045 beq.n 10003af6 +10003a6a: 2e00 cmp r6, #0 +10003a6c: dd3e ble.n 10003aec +10003a6e: 2500 movs r5, #0 +10003a70: f8df 80a4 ldr.w r8, [pc, #164] @ 10003b18 +10003a74: e012 b.n 10003a9c +10003a76: 4622 mov r2, r4 +10003a78: 2000 movs r0, #0 +10003a7a: f001 fbc5 bl 10005208 +10003a7e: 2100 movs r1, #0 +10003a80: 4405 add r5, r0 +10003a82: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10003a86: f000 fd19 bl 100044bc +10003a8a: 2000 movs r0, #0 +10003a8c: f001 fb72 bl 10005174 +10003a90: f7fd fc82 bl 10001398 +10003a94: e9c8 0100 strd r0, r1, [r8] +10003a98: 42ae cmp r6, r5 +10003a9a: dd27 ble.n 10003aec +10003a9c: 2000 movs r0, #0 +10003a9e: f001 fbd1 bl 10005244 +10003aa2: 1b74 subs r4, r6, r5 +10003aa4: 4284 cmp r4, r0 +10003aa6: bfa8 it ge +10003aa8: 4604 movge r4, r0 +10003aaa: 1979 adds r1, r7, r5 +10003aac: 2c00 cmp r4, #0 +10003aae: d1e2 bne.n 10003a76 +10003ab0: 4621 mov r1, r4 +10003ab2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10003ab6: f000 fd01 bl 100044bc +10003aba: 4620 mov r0, r4 +10003abc: f001 fb5a bl 10005174 +10003ac0: 4620 mov r0, r4 +10003ac2: f001 faf1 bl 100050a8 +10003ac6: b188 cbz r0, 10003aec +10003ac8: 4620 mov r0, r4 +10003aca: f001 fbbb bl 10005244 +10003ace: 2800 cmp r0, #0 +10003ad0: d1e2 bne.n 10003a98 +10003ad2: f7fd fc61 bl 10001398 +10003ad6: 4a0f ldr r2, [pc, #60] @ (10003b14 ) +10003ad8: f8d8 3000 ldr.w r3, [r8] +10003adc: 189b adds r3, r3, r2 +10003ade: f8d8 2004 ldr.w r2, [r8, #4] +10003ae2: f142 0200 adc.w r2, r2, #0 +10003ae6: 4283 cmp r3, r0 +10003ae8: 418a sbcs r2, r1 +10003aea: d2d5 bcs.n 10003a98 +10003aec: 4808 ldr r0, [pc, #32] @ (10003b10 ) +10003aee: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10003af2: f008 bc41 b.w 1000c378 <__mutex_exit_veneer> +10003af6: 2000 movs r0, #0 +10003af8: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10003afc: 2100 movs r1, #0 +10003afe: 4b06 ldr r3, [pc, #24] @ (10003b18 ) +10003b00: e9c3 0100 strd r0, r1, [r3] +10003b04: 4802 ldr r0, [pc, #8] @ (10003b10 ) +10003b06: f008 bc37 b.w 1000c378 <__mutex_exit_veneer> +10003b0a: bf00 nop +10003b0c: 000f4240 .word 0x000f4240 +10003b10: 20002520 .word 0x20002520 +10003b14: 0007a120 .word 0x0007a120 +10003b18: 20001ac0 .word 0x20001ac0 + +10003b1c : +10003b1c: b510 push {r4, lr} +10003b1e: 2100 movs r1, #0 +10003b20: b084 sub sp, #16 +10003b22: 4832 ldr r0, [pc, #200] @ (10003bec ) +10003b24: f008 fc2c bl 1000c380 <__mutex_try_enter_veneer> +10003b28: bb28 cbnz r0, 10003b76 +10003b2a: 4b31 ldr r3, [pc, #196] @ (10003bf0 ) +10003b2c: 681a ldr r2, [r3, #0] +10003b2e: b302 cbz r2, 10003b72 +10003b30: f3ef 8110 mrs r1, PRIMASK +10003b34: b672 cpsid i +10003b36: e8d2 efcf ldaexb lr, [r2] +10003b3a: f05f 0c01 movs.w ip, #1 +10003b3e: f1be 0f00 cmp.w lr, #0 +10003b42: d1f8 bne.n 10003b36 +10003b44: e8c2 cf4e strexb lr, ip, [r2] +10003b48: f1be 0f00 cmp.w lr, #0 +10003b4c: d1f3 bne.n 10003b36 +10003b4e: f3bf 8f5f dmb sy +10003b52: f8df c0a8 ldr.w ip, [pc, #168] @ 10003bfc +10003b56: f8d3 e000 ldr.w lr, [r3] +10003b5a: f89c 2000 ldrb.w r2, [ip] +10003b5e: 6059 str r1, [r3, #4] +10003b60: b2d3 uxtb r3, r2 +10003b62: 2201 movs r2, #1 +10003b64: f88c 2000 strb.w r2, [ip] +10003b68: e8ce 0f8f stlb r0, [lr] +10003b6c: f381 8810 msr PRIMASK, r1 +10003b70: b1cb cbz r3, 10003ba6 +10003b72: b004 add sp, #16 +10003b74: bd10 pop {r4, pc} +10003b76: 2100 movs r1, #0 +10003b78: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10003b7c: f000 fc9e bl 100044bc +10003b80: 2000 movs r0, #0 +10003b82: f001 faa7 bl 100050d4 +10003b86: 4604 mov r4, r0 +10003b88: 4818 ldr r0, [pc, #96] @ (10003bec ) +10003b8a: f008 fbf5 bl 1000c378 <__mutex_exit_veneer> +10003b8e: 2c00 cmp r4, #0 +10003b90: d0ef beq.n 10003b72 +10003b92: 4b18 ldr r3, [pc, #96] @ (10003bf4 ) +10003b94: 681b ldr r3, [r3, #0] +10003b96: 2b00 cmp r3, #0 +10003b98: d0eb beq.n 10003b72 +10003b9a: 4a17 ldr r2, [pc, #92] @ (10003bf8 ) +10003b9c: 6810 ldr r0, [r2, #0] +10003b9e: b004 add sp, #16 +10003ba0: e8bd 4010 ldmia.w sp!, {r4, lr} +10003ba4: 4718 bx r3 +10003ba6: f7fd f9e1 bl 10000f6c +10003baa: 4604 mov r4, r0 +10003bac: f7fd fbf4 bl 10001398 +10003bb0: f04f 3eff mov.w lr, #4294967295 @ 0xffffffff +10003bb4: f06f 4c00 mvn.w ip, #2147483648 @ 0x80000000 +10003bb8: f510 727a adds.w r2, r0, #1000 @ 0x3e8 +10003bbc: f141 0300 adc.w r3, r1, #0 +10003bc0: 4596 cmp lr, r2 +10003bc2: eb7c 0103 sbcs.w r1, ip, r3 +10003bc6: bf38 it cc +10003bc8: 4663 movcc r3, ip +10003bca: f04f 0100 mov.w r1, #0 +10003bce: f04f 0c01 mov.w ip, #1 +10003bd2: bf38 it cc +10003bd4: 4672 movcc r2, lr +10003bd6: f8df e028 ldr.w lr, [pc, #40] @ 10003c00 +10003bda: 4620 mov r0, r4 +10003bdc: e9cd 1c01 strd r1, ip, [sp, #4] +10003be0: f8cd e000 str.w lr, [sp] +10003be4: f7fd f9c6 bl 10000f74 +10003be8: b004 add sp, #16 +10003bea: bd10 pop {r4, pc} +10003bec: 20002520 .word 0x20002520 +10003bf0: 200024f0 .word 0x200024f0 +10003bf4: 20001e5c .word 0x20001e5c +10003bf8: 20001e60 .word 0x20001e60 +10003bfc: 20002541 .word 0x20002541 +10003c00: 100038d5 .word 0x100038d5 + +10003c04 : +10003c04: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000 +10003c08: b530 push {r4, r5, lr} +10003c0a: b085 sub sp, #20 +10003c0c: 681c ldr r4, [r3, #0] +10003c0e: f7fd f9ad bl 10000f6c +10003c12: f7fd fac9 bl 100011a8 +10003c16: 42a0 cmp r0, r4 +10003c18: d002 beq.n 10003c20 +10003c1a: 2000 movs r0, #0 +10003c1c: b005 add sp, #20 +10003c1e: bd30 pop {r4, r5, pc} +10003c20: 2100 movs r1, #0 +10003c22: 4b2c ldr r3, [pc, #176] @ (10003cd4 ) +10003c24: 4608 mov r0, r1 +10003c26: 781b ldrb r3, [r3, #0] +10003c28: f001 fcdc bl 100055e4 +10003c2c: 482a ldr r0, [pc, #168] @ (10003cd8 ) +10003c2e: 6803 ldr r3, [r0, #0] +10003c30: 2b00 cmp r3, #0 +10003c32: d04b beq.n 10003ccc +10003c34: 2001 movs r0, #1 +10003c36: f7fc ff29 bl 10000a8c +10003c3a: 4603 mov r3, r0 +10003c3c: 4c27 ldr r4, [pc, #156] @ (10003cdc ) +10003c3e: 4928 ldr r1, [pc, #160] @ (10003ce0 ) +10003c40: b2c0 uxtb r0, r0 +10003c42: 7023 strb r3, [r4, #0] +10003c44: f7fc fd9c bl 10000780 +10003c48: 7820 ldrb r0, [r4, #0] +10003c4a: 2101 movs r1, #1 +10003c4c: f7fc fd56 bl 100006fc +10003c50: 200e movs r0, #14 +10003c52: f7fc fd85 bl 10000760 +10003c56: bb60 cbnz r0, 10003cb2 +10003c58: 4b22 ldr r3, [pc, #136] @ (10003ce4 ) +10003c5a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10003c5e: e9c3 0000 strd r0, r0, [r3] +10003c62: f7fd f983 bl 10000f6c +10003c66: 4605 mov r5, r0 +10003c68: f7fd fb96 bl 10001398 +10003c6c: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003c70: f510 727a adds.w r2, r0, #1000 @ 0x3e8 +10003c74: f141 0300 adc.w r3, r1, #0 +10003c78: 4594 cmp ip, r2 +10003c7a: eb74 0103 sbcs.w r1, r4, r3 +10003c7e: bf38 it cc +10003c80: 4623 movcc r3, r4 +10003c82: f04f 0100 mov.w r1, #0 +10003c86: f04f 0401 mov.w r4, #1 +10003c8a: bf38 it cc +10003c8c: 4662 movcc r2, ip +10003c8e: f8df c060 ldr.w ip, [pc, #96] @ 10003cf0 +10003c92: 4628 mov r0, r5 +10003c94: e9cd 1401 strd r1, r4, [sp, #4] +10003c98: f8cd c000 str.w ip, [sp] +10003c9c: f7fd f96a bl 10000f74 +10003ca0: 2800 cmp r0, #0 +10003ca2: dbba blt.n 10003c1a +10003ca4: 2101 movs r1, #1 +10003ca6: 4810 ldr r0, [pc, #64] @ (10003ce8 ) +10003ca8: f7ff fce0 bl 1000366c +10003cac: 2001 movs r0, #1 +10003cae: b005 add sp, #20 +10003cb0: bd30 pop {r4, r5, pc} +10003cb2: 2001 movs r0, #1 +10003cb4: f7fc fcdc bl 10000670 +10003cb8: 4601 mov r1, r0 +10003cba: 480a ldr r0, [pc, #40] @ (10003ce4 ) +10003cbc: f7fc ff44 bl 10000b48 +10003cc0: 2200 movs r2, #0 +10003cc2: 200e movs r0, #14 +10003cc4: 4909 ldr r1, [pc, #36] @ (10003cec ) +10003cc6: f7fc fd8d bl 100007e4 +10003cca: e7eb b.n 10003ca4 +10003ccc: f7fc ff20 bl 10000b10 +10003cd0: e7b0 b.n 10003c34 +10003cd2: bf00 nop +10003cd4: 1000dbe4 .word 0x1000dbe4 +10003cd8: 20002520 .word 0x20002520 +10003cdc: 20002540 .word 0x20002540 +10003ce0: 10003b1d .word 0x10003b1d +10003ce4: 200024f0 .word 0x200024f0 +10003ce8: 2000121c .word 0x2000121c +10003cec: 10003945 .word 0x10003945 +10003cf0: 100038d5 .word 0x100038d5 + +10003cf4 : +10003cf4: 4800 ldr r0, [pc, #0] @ (10003cf8 ) +10003cf6: 4770 bx lr +10003cf8: 1000cd74 .word 0x1000cd74 + +10003cfc : +10003cfc: 4800 ldr r0, [pc, #0] @ (10003d00 ) +10003cfe: 4770 bx lr +10003d00: 1000cd20 .word 0x1000cd20 + +10003d04 : +10003d04: b500 push {lr} +10003d06: 4a1c ldr r2, [pc, #112] @ (10003d78 ) +10003d08: 4603 mov r3, r0 +10003d0a: 7811 ldrb r1, [r2, #0] +10003d0c: b083 sub sp, #12 +10003d0e: b331 cbz r1, 10003d5e +10003d10: b963 cbnz r3, 10003d2c +10003d12: f240 4209 movw r2, #1033 @ 0x409 +10003d16: f44f 7341 mov.w r3, #772 @ 0x304 +10003d1a: f8df c060 ldr.w ip, [pc, #96] @ 10003d7c +10003d1e: f8ac 2002 strh.w r2, [ip, #2] +10003d22: 4816 ldr r0, [pc, #88] @ (10003d7c ) +10003d24: f8ac 3000 strh.w r3, [ip] +10003d28: b003 add sp, #12 +10003d2a: bd00 pop {pc} +10003d2c: 2b05 cmp r3, #5 +10003d2e: d820 bhi.n 10003d72 +10003d30: 4a13 ldr r2, [pc, #76] @ (10003d80 ) +10003d32: f8df c048 ldr.w ip, [pc, #72] @ 10003d7c +10003d36: f852 1023 ldr.w r1, [r2, r3, lsl #2] +10003d3a: 4660 mov r0, ip +10003d3c: 2300 movs r3, #0 +10003d3e: 3901 subs r1, #1 +10003d40: e003 b.n 10003d4a +10003d42: 2b13 cmp r3, #19 +10003d44: f820 2f02 strh.w r2, [r0, #2]! +10003d48: d010 beq.n 10003d6c +10003d4a: f811 2f01 ldrb.w r2, [r1, #1]! +10003d4e: 3301 adds r3, #1 +10003d50: b2db uxtb r3, r3 +10003d52: 2a00 cmp r2, #0 +10003d54: d1f5 bne.n 10003d42 +10003d56: 005b lsls r3, r3, #1 +10003d58: f443 7340 orr.w r3, r3, #768 @ 0x300 +10003d5c: e7e1 b.n 10003d22 +10003d5e: 9001 str r0, [sp, #4] +10003d60: 2111 movs r1, #17 +10003d62: 4610 mov r0, r2 +10003d64: f000 f824 bl 10003db0 +10003d68: 9b01 ldr r3, [sp, #4] +10003d6a: e7d1 b.n 10003d10 +10003d6c: f44f 734a mov.w r3, #808 @ 0x328 +10003d70: e7d7 b.n 10003d22 +10003d72: 2000 movs r0, #0 +10003d74: e7d8 b.n 10003d28 +10003d76: bf00 nop +10003d78: 20002528 .word 0x20002528 +10003d7c: 20001e94 .word 0x20001e94 +10003d80: 1000cd08 .word 0x1000cd08 + +10003d84 <_retrieve_unique_id_on_boot>: +10003d84: b500 push {lr} +10003d86: f245 3047 movw r0, #21319 @ 0x5347 +10003d8a: b08b sub sp, #44 @ 0x2c +10003d8c: f7fd fc8c bl 100016a8 +10003d90: 2201 movs r2, #1 +10003d92: 4603 mov r3, r0 +10003d94: 2109 movs r1, #9 +10003d96: a801 add r0, sp, #4 +10003d98: 4798 blx r3 +10003d9a: e9dd 3203 ldrd r3, r2, [sp, #12] +10003d9e: 4903 ldr r1, [pc, #12] @ (10003dac <_retrieve_unique_id_on_boot+0x28>) +10003da0: ba12 rev r2, r2 +10003da2: ba1b rev r3, r3 +10003da4: e9c1 2300 strd r2, r3, [r1] +10003da8: b00b add sp, #44 @ 0x2c +10003daa: bd00 pop {pc} +10003dac: 20002518 .word 0x20002518 + +10003db0 : +10003db0: 2901 cmp r1, #1 +10003db2: f000 80bb beq.w 10003f2c +10003db6: 4a61 ldr r2, [pc, #388] @ (10003f3c ) +10003db8: 3901 subs r1, #1 +10003dba: 7813 ldrb r3, [r2, #0] +10003dbc: ea4f 1c23 mov.w ip, r3, asr #4 +10003dc0: f1bc 0f09 cmp.w ip, #9 +10003dc4: bfcc ite gt +10003dc6: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003dca: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003dce: 2901 cmp r1, #1 +10003dd0: f880 c000 strb.w ip, [r0] +10003dd4: f000 80ad beq.w 10003f32 +10003dd8: f003 030f and.w r3, r3, #15 +10003ddc: 2b09 cmp r3, #9 +10003dde: bf8c ite hi +10003de0: 3337 addhi r3, #55 @ 0x37 +10003de2: 3330 addls r3, #48 @ 0x30 +10003de4: 2902 cmp r1, #2 +10003de6: 7043 strb r3, [r0, #1] +10003de8: f000 80a3 beq.w 10003f32 +10003dec: 7853 ldrb r3, [r2, #1] +10003dee: ea4f 1c23 mov.w ip, r3, asr #4 +10003df2: f1bc 0f09 cmp.w ip, #9 +10003df6: bfcc ite gt +10003df8: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003dfc: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003e00: 2903 cmp r1, #3 +10003e02: f880 c002 strb.w ip, [r0, #2] +10003e06: f000 8094 beq.w 10003f32 +10003e0a: f003 030f and.w r3, r3, #15 +10003e0e: 2b09 cmp r3, #9 +10003e10: bf8c ite hi +10003e12: 3337 addhi r3, #55 @ 0x37 +10003e14: 3330 addls r3, #48 @ 0x30 +10003e16: 2904 cmp r1, #4 +10003e18: 70c3 strb r3, [r0, #3] +10003e1a: f000 808a beq.w 10003f32 +10003e1e: 7893 ldrb r3, [r2, #2] +10003e20: ea4f 1c23 mov.w ip, r3, asr #4 +10003e24: f1bc 0f09 cmp.w ip, #9 +10003e28: bfcc ite gt +10003e2a: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003e2e: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003e32: 2905 cmp r1, #5 +10003e34: f880 c004 strb.w ip, [r0, #4] +10003e38: d07b beq.n 10003f32 +10003e3a: f003 030f and.w r3, r3, #15 +10003e3e: 2b09 cmp r3, #9 +10003e40: bf8c ite hi +10003e42: 3337 addhi r3, #55 @ 0x37 +10003e44: 3330 addls r3, #48 @ 0x30 +10003e46: 2906 cmp r1, #6 +10003e48: 7143 strb r3, [r0, #5] +10003e4a: d072 beq.n 10003f32 +10003e4c: 78d3 ldrb r3, [r2, #3] +10003e4e: ea4f 1c23 mov.w ip, r3, asr #4 +10003e52: f1bc 0f09 cmp.w ip, #9 +10003e56: bfcc ite gt +10003e58: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003e5c: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003e60: 2907 cmp r1, #7 +10003e62: f880 c006 strb.w ip, [r0, #6] +10003e66: d064 beq.n 10003f32 +10003e68: f003 030f and.w r3, r3, #15 +10003e6c: 2b09 cmp r3, #9 +10003e6e: bf8c ite hi +10003e70: 3337 addhi r3, #55 @ 0x37 +10003e72: 3330 addls r3, #48 @ 0x30 +10003e74: 2908 cmp r1, #8 +10003e76: 71c3 strb r3, [r0, #7] +10003e78: d05b beq.n 10003f32 +10003e7a: 7913 ldrb r3, [r2, #4] +10003e7c: ea4f 1c23 mov.w ip, r3, asr #4 +10003e80: f1bc 0f09 cmp.w ip, #9 +10003e84: bfcc ite gt +10003e86: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003e8a: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003e8e: 2909 cmp r1, #9 +10003e90: f880 c008 strb.w ip, [r0, #8] +10003e94: d04d beq.n 10003f32 +10003e96: f003 030f and.w r3, r3, #15 +10003e9a: 2b09 cmp r3, #9 +10003e9c: bf8c ite hi +10003e9e: 3337 addhi r3, #55 @ 0x37 +10003ea0: 3330 addls r3, #48 @ 0x30 +10003ea2: 290a cmp r1, #10 +10003ea4: 7243 strb r3, [r0, #9] +10003ea6: d044 beq.n 10003f32 +10003ea8: 7953 ldrb r3, [r2, #5] +10003eaa: ea4f 1c23 mov.w ip, r3, asr #4 +10003eae: f1bc 0f09 cmp.w ip, #9 +10003eb2: bfcc ite gt +10003eb4: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003eb8: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003ebc: 290b cmp r1, #11 +10003ebe: f880 c00a strb.w ip, [r0, #10] +10003ec2: d036 beq.n 10003f32 +10003ec4: f003 030f and.w r3, r3, #15 +10003ec8: 2b09 cmp r3, #9 +10003eca: bf8c ite hi +10003ecc: 3337 addhi r3, #55 @ 0x37 +10003ece: 3330 addls r3, #48 @ 0x30 +10003ed0: 290c cmp r1, #12 +10003ed2: 72c3 strb r3, [r0, #11] +10003ed4: d02d beq.n 10003f32 +10003ed6: 7993 ldrb r3, [r2, #6] +10003ed8: ea4f 1c23 mov.w ip, r3, asr #4 +10003edc: f1bc 0f09 cmp.w ip, #9 +10003ee0: bfcc ite gt +10003ee2: f10c 0c37 addgt.w ip, ip, #55 @ 0x37 +10003ee6: f10c 0c30 addle.w ip, ip, #48 @ 0x30 +10003eea: 290d cmp r1, #13 +10003eec: f880 c00c strb.w ip, [r0, #12] +10003ef0: d01f beq.n 10003f32 +10003ef2: f003 030f and.w r3, r3, #15 +10003ef6: 2b09 cmp r3, #9 +10003ef8: bf8c ite hi +10003efa: 3337 addhi r3, #55 @ 0x37 +10003efc: 3330 addls r3, #48 @ 0x30 +10003efe: 290e cmp r1, #14 +10003f00: 7343 strb r3, [r0, #13] +10003f02: d016 beq.n 10003f32 +10003f04: 79d3 ldrb r3, [r2, #7] +10003f06: 111a asrs r2, r3, #4 +10003f08: 2a09 cmp r2, #9 +10003f0a: bfcc ite gt +10003f0c: 3237 addgt r2, #55 @ 0x37 +10003f0e: 3230 addle r2, #48 @ 0x30 +10003f10: 290f cmp r1, #15 +10003f12: 7382 strb r2, [r0, #14] +10003f14: d00d beq.n 10003f32 +10003f16: f003 030f and.w r3, r3, #15 +10003f1a: 2b09 cmp r3, #9 +10003f1c: bf94 ite ls +10003f1e: 3330 addls r3, #48 @ 0x30 +10003f20: 3337 addhi r3, #55 @ 0x37 +10003f22: 2910 cmp r1, #16 +10003f24: 73c3 strb r3, [r0, #15] +10003f26: bf18 it ne +10003f28: 3010 addne r0, #16 +10003f2a: d002 beq.n 10003f32 +10003f2c: 2300 movs r3, #0 +10003f2e: 7003 strb r3, [r0, #0] +10003f30: 4770 bx lr +10003f32: 2300 movs r3, #0 +10003f34: 4408 add r0, r1 +10003f36: 7003 strb r3, [r0, #0] +10003f38: 4770 bx lr +10003f3a: bf00 nop +10003f3c: 20002518 .word 0x20002518 + +10003f40 : +10003f40: 4770 bx lr +10003f42: bf00 nop + +10003f44 : +10003f44: 2200 movs r2, #0 +10003f46: 4b01 ldr r3, [pc, #4] @ (10003f4c ) +10003f48: 701a strb r2, [r3, #0] +10003f4a: 4770 bx lr +10003f4c: 2000253e .word 0x2000253e + +10003f50 : +10003f50: 794b ldrb r3, [r1, #5] +10003f52: 2bff cmp r3, #255 @ 0xff +10003f54: d10b bne.n 10003f6e +10003f56: 7988 ldrb r0, [r1, #6] +10003f58: b948 cbnz r0, 10003f6e +10003f5a: 79cb ldrb r3, [r1, #7] +10003f5c: 2b01 cmp r3, #1 +10003f5e: d107 bne.n 10003f70 +10003f60: 2a08 cmp r2, #8 +10003f62: d905 bls.n 10003f70 +10003f64: 4b03 ldr r3, [pc, #12] @ (10003f74 ) +10003f66: 788a ldrb r2, [r1, #2] +10003f68: 2009 movs r0, #9 +10003f6a: 701a strb r2, [r3, #0] +10003f6c: 4770 bx lr +10003f6e: 2000 movs r0, #0 +10003f70: 4770 bx lr +10003f72: bf00 nop +10003f74: 2000253e .word 0x2000253e + +10003f78 : +10003f78: 2001 movs r0, #1 +10003f7a: 4770 bx lr + +10003f7c : +10003f7c: 2901 cmp r1, #1 +10003f7e: d001 beq.n 10003f84 +10003f80: 2001 movs r0, #1 +10003f82: 4770 bx lr +10003f84: b508 push {r3, lr} +10003f86: 4b10 ldr r3, [pc, #64] @ (10003fc8 ) +10003f88: 8891 ldrh r1, [r2, #4] +10003f8a: 781b ldrb r3, [r3, #0] +10003f8c: 4299 cmp r1, r3 +10003f8e: d001 beq.n 10003f94 +10003f90: 2000 movs r0, #0 +10003f92: bd08 pop {r3, pc} +10003f94: 7853 ldrb r3, [r2, #1] +10003f96: 2b01 cmp r3, #1 +10003f98: d008 beq.n 10003fac +10003f9a: 2b02 cmp r3, #2 +10003f9c: d1f8 bne.n 10003f90 +10003f9e: 2100 movs r1, #0 +10003fa0: 2264 movs r2, #100 @ 0x64 +10003fa2: 4608 mov r0, r1 +10003fa4: f7fd fb00 bl 100015a8 +10003fa8: 2001 movs r0, #1 +10003faa: bd08 pop {r3, pc} +10003fac: 8851 ldrh r1, [r2, #2] +10003fae: f411 7280 ands.w r2, r1, #256 @ 0x100 +10003fb2: bf1a itte ne +10003fb4: f3c1 12c0 ubfxne r2, r1, #7, #1 +10003fb8: 0a48 lsrne r0, r1, #9 +10003fba: f04f 30ff moveq.w r0, #4294967295 @ 0xffffffff +10003fbe: f001 0103 and.w r1, r1, #3 +10003fc2: f7fd fb7d bl 100016c0 +10003fc6: bf00 nop +10003fc8: 2000253e .word 0x2000253e + +10003fcc : +10003fcc: 4800 ldr r0, [pc, #0] @ (10003fd0 ) +10003fce: 4770 bx lr +10003fd0: 1000ce30 .word 0x1000ce30 + +10003fd4 : +10003fd4: 2901 cmp r1, #1 +10003fd6: d107 bne.n 10003fe8 +10003fd8: 7853 ldrb r3, [r2, #1] +10003fda: 2b01 cmp r3, #1 +10003fdc: d102 bne.n 10003fe4 +10003fde: 8893 ldrh r3, [r2, #4] +10003fe0: 2b07 cmp r3, #7 +10003fe2: d003 beq.n 10003fec +10003fe4: 2000 movs r0, #0 +10003fe6: 4770 bx lr +10003fe8: 2001 movs r0, #1 +10003fea: 4770 bx lr +10003fec: 4611 mov r1, r2 +10003fee: 23a6 movs r3, #166 @ 0xa6 +10003ff0: 4a01 ldr r2, [pc, #4] @ (10003ff8 ) +10003ff2: f000 bf1f b.w 10004e34 +10003ff6: bf00 nop +10003ff8: 1000cd88 .word 0x1000cd88 + +10003ffc : +10003ffc: 4603 mov r3, r0 +10003ffe: 2201 movs r2, #1 +10004000: 4801 ldr r0, [pc, #4] @ (10004008 ) +10004002: 701a strb r2, [r3, #0] +10004004: 4770 bx lr +10004006: bf00 nop +10004008: 1000ce54 .word 0x1000ce54 + +1000400c : +1000400c: b508 push {r3, lr} +1000400e: 680b ldr r3, [r1, #0] +10004010: f5b3 6f96 cmp.w r3, #1200 @ 0x4b0 +10004014: d000 beq.n 10004018 +10004016: bd08 pop {r3, pc} +10004018: 2200 movs r2, #0 +1000401a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000401e: 4611 mov r1, r2 +10004020: f7fd fb4e bl 100016c0 + +10004024 : +10004024: b510 push {r4, lr} +10004026: f000 f92d bl 10004284 +1000402a: 230c movs r3, #12 +1000402c: 4c1c ldr r4, [pc, #112] @ (100040a0 ) +1000402e: 22ff movs r2, #255 @ 0xff +10004030: 67a3 str r3, [r4, #120] @ 0x78 +10004032: 200e movs r0, #14 +10004034: 491b ldr r1, [pc, #108] @ (100040a4 ) +10004036: f7fc fbd5 bl 100007e4 +1000403a: 2240 movs r2, #64 @ 0x40 +1000403c: 2100 movs r1, #0 +1000403e: 481a ldr r0, [pc, #104] @ (100040a8 ) +10004040: f007 fef4 bl 1000be2c +10004044: f04f 0c80 mov.w ip, #128 @ 0x80 +10004048: 2001 movs r0, #1 +1000404a: 4a17 ldr r2, [pc, #92] @ (100040a8 ) +1000404c: 2300 movs r3, #0 +1000404e: f8a2 c022 strh.w ip, [r2, #34] @ 0x22 +10004052: 7050 strb r0, [r2, #1] +10004054: 4610 mov r0, r2 +10004056: 2240 movs r2, #64 @ 0x40 +10004058: 4914 ldr r1, [pc, #80] @ (100040ac ) +1000405a: 8302 strh r2, [r0, #24] +1000405c: 8702 strh r2, [r0, #56] @ 0x38 +1000405e: 4a14 ldr r2, [pc, #80] @ (100040b0 ) +10004060: 6081 str r1, [r0, #8] +10004062: 6043 str r3, [r0, #4] +10004064: f8c2 3084 str.w r3, [r2, #132] @ 0x84 +10004068: f8c2 3080 str.w r3, [r2, #128] @ 0x80 +1000406c: f880 3021 strb.w r3, [r0, #33] @ 0x21 +10004070: f880 303b strb.w r3, [r0, #59] @ 0x3b +10004074: 6243 str r3, [r0, #36] @ 0x24 +10004076: 4b0f ldr r3, [pc, #60] @ (100040b4 ) +10004078: 60c3 str r3, [r0, #12] +1000407a: 62c3 str r3, [r0, #44] @ 0x2c +1000407c: 3b80 subs r3, #128 @ 0x80 +1000407e: 6283 str r3, [r0, #40] @ 0x28 +10004080: f008 f982 bl 1000c388 <__reset_non_control_endpoints_veneer> +10004084: f04f 5c00 mov.w ip, #536870912 @ 0x20000000 +10004088: f44f 3280 mov.w r2, #65536 @ 0x10000 +1000408c: 2001 movs r0, #1 +1000408e: 490a ldr r1, [pc, #40] @ (100040b8 ) +10004090: 4b0a ldr r3, [pc, #40] @ (100040bc ) +10004092: 6420 str r0, [r4, #64] @ 0x40 +10004094: f8c4 c04c str.w ip, [r4, #76] @ 0x4c +10004098: f8c4 1090 str.w r1, [r4, #144] @ 0x90 +1000409c: 64da str r2, [r3, #76] @ 0x4c +1000409e: bd10 pop {r4, pc} +100040a0: 50110000 .word 0x50110000 +100040a4: 200003d1 .word 0x200003d1 +100040a8: 200020e4 .word 0x200020e4 +100040ac: 50100084 .word 0x50100084 +100040b0: 50100000 .word 0x50100000 +100040b4: 50100100 .word 0x50100100 +100040b8: 0001d010 .word 0x0001d010 +100040bc: 50112000 .word 0x50112000 + +100040c0 : +100040c0: 2101 movs r1, #1 +100040c2: 200e movs r0, #14 +100040c4: f7fc bb1a b.w 100006fc + +100040c8 : +100040c8: 2200 movs r2, #0 +100040ca: 4802 ldr r0, [pc, #8] @ (100040d4 ) +100040cc: 4611 mov r1, r2 +100040ce: f000 b8f9 b.w 100042c4 +100040d2: bf00 nop +100040d4: 20002104 .word 0x20002104 + +100040d8 : +100040d8: 4b04 ldr r3, [pc, #16] @ (100040ec ) +100040da: 7019 strb r1, [r3, #0] +100040dc: b121 cbz r1, 100040e8 +100040de: f44f 3200 mov.w r2, #131072 @ 0x20000 +100040e2: 4b03 ldr r3, [pc, #12] @ (100040f0 ) +100040e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 +100040e8: 4770 bx lr +100040ea: bf00 nop +100040ec: 2000253a .word 0x2000253a +100040f0: 50112000 .word 0x50112000 + +100040f4 : +100040f4: 780b ldrb r3, [r1, #0] +100040f6: 065b lsls r3, r3, #25 +100040f8: d000 beq.n 100040fc +100040fa: 4770 bx lr +100040fc: 784b ldrb r3, [r1, #1] +100040fe: 2b05 cmp r3, #5 +10004100: d1fb bne.n 100040fa +10004102: 884b ldrh r3, [r1, #2] +10004104: 4a01 ldr r2, [pc, #4] @ (1000410c ) +10004106: b2db uxtb r3, r3 +10004108: 6013 str r3, [r2, #0] +1000410a: e7f6 b.n 100040fa +1000410c: 50110000 .word 0x50110000 + +10004110 : +10004110: 78cb ldrb r3, [r1, #3] +10004112: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10004116: f003 0e03 and.w lr, r3, #3 +1000411a: f1be 0f01 cmp.w lr, #1 +1000411e: f3c3 0001 ubfx r0, r3, #0, #2 +10004122: d057 beq.n 100041d4 +10004124: 2600 movs r6, #0 +10004126: 788c ldrb r4, [r1, #2] +10004128: f8df c0d4 ldr.w ip, [pc, #212] @ 10004200 +1000412c: f004 027f and.w r2, r4, #127 @ 0x7f +10004130: 0053 lsls r3, r2, #1 +10004132: 8889 ldrh r1, [r1, #4] +10004134: 4698 mov r8, r3 +10004136: eb03 13d4 add.w r3, r3, r4, lsr #7 +1000413a: eb0c 1343 add.w r3, ip, r3, lsl #5 +1000413e: 09e5 lsrs r5, r4, #7 +10004140: 76d8 strb r0, [r3, #27] +10004142: f3c1 010a ubfx r1, r1, #0, #11 +10004146: f085 0001 eor.w r0, r5, #1 +1000414a: 709c strb r4, [r3, #2] +1000414c: 8319 strh r1, [r3, #24] +1000414e: 7058 strb r0, [r3, #1] +10004150: 70de strb r6, [r3, #3] +10004152: 00d3 lsls r3, r2, #3 +10004154: bb6d cbnz r5, 100041b2 +10004156: 4825 ldr r0, [pc, #148] @ (100041ec ) +10004158: 3304 adds r3, #4 +1000415a: eb0c 1482 add.w r4, ip, r2, lsl #6 +1000415e: 181f adds r7, r3, r0 +10004160: 60a7 str r7, [r4, #8] +10004162: 501e str r6, [r3, r0] +10004164: b36a cbz r2, 100041c2 +10004166: 4b22 ldr r3, [pc, #136] @ (100041f0 ) +10004168: eb03 03c2 add.w r3, r3, r2, lsl #3 +1000416c: 6063 str r3, [r4, #4] +1000416e: 313f adds r1, #63 @ 0x3f +10004170: 0989 lsrs r1, r1, #6 +10004172: f1be 0f02 cmp.w lr, #2 +10004176: bf14 ite ne +10004178: 018b lslne r3, r1, #6 +1000417a: 01cb lsleq r3, r1, #7 +1000417c: 491d ldr r1, [pc, #116] @ (100041f4 ) +1000417e: eb08 0205 add.w r2, r8, r5 +10004182: eb0c 1c42 add.w ip, ip, r2, lsl #5 +10004186: 680a ldr r2, [r1, #0] +10004188: 481b ldr r0, [pc, #108] @ (100041f8 ) +1000418a: 4413 add r3, r2 +1000418c: 4283 cmp r3, r0 +1000418e: 600b str r3, [r1, #0] +10004190: f8cc 200c str.w r2, [ip, #12] +10004194: d828 bhi.n 100041e8 +10004196: f082 43a0 eor.w r3, r2, #1342177280 @ 0x50000000 +1000419a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 +1000419e: f8dc 2004 ldr.w r2, [ip, #4] +100041a2: ea43 638e orr.w r3, r3, lr, lsl #26 +100041a6: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 +100041aa: 6013 str r3, [r2, #0] +100041ac: 2001 movs r0, #1 +100041ae: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100041b2: 480e ldr r0, [pc, #56] @ (100041ec ) +100041b4: eb0c 1482 add.w r4, ip, r2, lsl #6 +100041b8: 4403 add r3, r0 +100041ba: 62a3 str r3, [r4, #40] @ 0x28 +100041bc: f840 6032 str.w r6, [r0, r2, lsl #3] +100041c0: b95a cbnz r2, 100041da +100041c2: 4613 mov r3, r2 +100041c4: 4a0d ldr r2, [pc, #52] @ (100041fc ) +100041c6: eb0c 1c45 add.w ip, ip, r5, lsl #5 +100041ca: f8cc 200c str.w r2, [ip, #12] +100041ce: f8cc 3004 str.w r3, [ip, #4] +100041d2: e7eb b.n 100041ac +100041d4: 2000 movs r0, #0 +100041d6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100041da: 00d2 lsls r2, r2, #3 +100041dc: f102 42a0 add.w r2, r2, #1342177280 @ 0x50000000 +100041e0: f502 1280 add.w r2, r2, #1048576 @ 0x100000 +100041e4: 6262 str r2, [r4, #36] @ 0x24 +100041e6: e7c2 b.n 1000416e +100041e8: f7fd fab4 bl 10001754 +100041ec: 50100080 .word 0x50100080 +100041f0: 50100004 .word 0x50100004 +100041f4: 200024ec .word 0x200024ec +100041f8: 50100fff .word 0x50100fff +100041fc: 50100100 .word 0x50100100 +10004200: 200020e4 .word 0x200020e4 + +10004204 : +10004204: f008 b8c0 b.w 1000c388 <__reset_non_control_endpoints_veneer> + +10004208 : +10004208: b508 push {r3, lr} +1000420a: 4696 mov lr, r2 +1000420c: f8df c01c ldr.w ip, [pc, #28] @ 1000422c +10004210: f001 027f and.w r2, r1, #127 @ 0x7f +10004214: 09c8 lsrs r0, r1, #7 +10004216: eb00 0042 add.w r0, r0, r2, lsl #1 +1000421a: eb0c 1040 add.w r0, ip, r0, lsl #5 +1000421e: 461a mov r2, r3 +10004220: 4671 mov r1, lr +10004222: f000 f84f bl 100042c4 +10004226: 2001 movs r0, #1 +10004228: bd08 pop {r3, pc} +1000422a: bf00 nop +1000422c: 200020e4 .word 0x200020e4 + +10004230 : +10004230: f011 027f ands.w r2, r1, #127 @ 0x7f +10004234: d105 bne.n 10004242 +10004236: 2900 cmp r1, #0 +10004238: bf0c ite eq +1000423a: 2002 moveq r0, #2 +1000423c: 2001 movne r0, #1 +1000423e: 4b06 ldr r3, [pc, #24] @ (10004258 ) +10004240: 6698 str r0, [r3, #104] @ 0x68 +10004242: 09c9 lsrs r1, r1, #7 +10004244: 4b05 ldr r3, [pc, #20] @ (1000425c ) +10004246: eb01 0042 add.w r0, r1, r2, lsl #1 +1000424a: eb03 1040 add.w r0, r3, r0, lsl #5 +1000424e: f44f 6200 mov.w r2, #2048 @ 0x800 +10004252: 2100 movs r1, #0 +10004254: f008 b8b0 b.w 1000c3b8 <___hw_endpoint_buffer_control_update32_veneer> +10004258: 50112000 .word 0x50112000 +1000425c: 200020e4 .word 0x200020e4 + +10004260 : +10004260: f011 037f ands.w r3, r1, #127 @ 0x7f +10004264: d100 bne.n 10004268 +10004266: 4770 bx lr +10004268: 2200 movs r2, #0 +1000426a: 4805 ldr r0, [pc, #20] @ (10004280 ) +1000426c: 005b lsls r3, r3, #1 +1000426e: eb03 13d1 add.w r3, r3, r1, lsr #7 +10004272: eb00 1043 add.w r0, r0, r3, lsl #5 +10004276: f46f 6100 mvn.w r1, #2048 @ 0x800 +1000427a: 70c2 strb r2, [r0, #3] +1000427c: f008 b89c b.w 1000c3b8 <___hw_endpoint_buffer_control_update32_veneer> +10004280: 200020e4 .word 0x200020e4 + +10004284 : +10004284: f04f 5280 mov.w r2, #268435456 @ 0x10000000 +10004288: 4809 ldr r0, [pc, #36] @ (100042b0 ) +1000428a: 490a ldr r1, [pc, #40] @ (100042b4 ) +1000428c: b508 push {r3, lr} +1000428e: 4b0a ldr r3, [pc, #40] @ (100042b8 ) +10004290: 6002 str r2, [r0, #0] +10004292: 600a str r2, [r1, #0] +10004294: 6899 ldr r1, [r3, #8] +10004296: 43c9 mvns r1, r1 +10004298: f011 5180 ands.w r1, r1, #268435456 @ 0x10000000 +1000429c: d1fa bne.n 10004294 +1000429e: f44f 5280 mov.w r2, #4096 @ 0x1000 +100042a2: 4806 ldr r0, [pc, #24] @ (100042bc ) +100042a4: f007 fdc2 bl 1000be2c +100042a8: 2209 movs r2, #9 +100042aa: 4b05 ldr r3, [pc, #20] @ (100042c0 ) +100042ac: 675a str r2, [r3, #116] @ 0x74 +100042ae: bd08 pop {r3, pc} +100042b0: 40022000 .word 0x40022000 +100042b4: 40023000 .word 0x40023000 +100042b8: 40020000 .word 0x40020000 +100042bc: 50100000 .word 0x50100000 +100042c0: 50110000 .word 0x50110000 + +100042c4 : +100042c4: 2300 movs r3, #0 +100042c6: f04f 0c01 mov.w ip, #1 +100042ca: b510 push {r4, lr} +100042cc: 6101 str r1, [r0, #16] +100042ce: f880 c01a strb.w ip, [r0, #26] +100042d2: 8282 strh r2, [r0, #20] +100042d4: 82c3 strh r3, [r0, #22] +100042d6: 4604 mov r4, r0 +100042d8: f008 f866 bl 1000c3a8 <__e15_is_bulkin_ep_veneer> +100042dc: b120 cbz r0, 100042e8 +100042de: f44f 3200 mov.w r2, #131072 @ 0x20000 +100042e2: 4b07 ldr r3, [pc, #28] @ (10004300 ) +100042e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 +100042e8: 4620 mov r0, r4 +100042ea: f008 f869 bl 1000c3c0 <__e15_is_critical_frame_period_veneer> +100042ee: b110 cbz r0, 100042f6 +100042f0: 2301 movs r3, #1 +100042f2: 7723 strb r3, [r4, #28] +100042f4: bd10 pop {r4, pc} +100042f6: 4620 mov r0, r4 +100042f8: e8bd 4010 ldmia.w sp!, {r4, lr} +100042fc: f008 b850 b.w 1000c3a0 <__hw_endpoint_start_next_buffer_veneer> +10004300: 50112000 .word 0x50112000 + +10004304 : +10004304: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10004308: f04f 0800 mov.w r8, #0 +1000430c: 4c1b ldr r4, [pc, #108] @ (1000437c ) +1000430e: 4605 mov r5, r0 +10004310: 4642 mov r2, r8 +10004312: 7823 ldrb r3, [r4, #0] +10004314: 4f1a ldr r7, [pc, #104] @ (10004380 ) +10004316: 4e1b ldr r6, [pc, #108] @ (10004384 ) +10004318: e00d b.n 10004336 +1000431a: 6833 ldr r3, [r6, #0] +1000431c: eb13 1342 adds.w r3, r3, r2, lsl #5 +10004320: d023 beq.n 1000436a +10004322: 68db ldr r3, [r3, #12] +10004324: 4628 mov r0, r5 +10004326: 4798 blx r3 +10004328: f108 0801 add.w r8, r8, #1 +1000432c: 7823 ldrb r3, [r4, #0] +1000432e: fa5f f288 uxtb.w r2, r8 +10004332: 4293 cmp r3, r2 +10004334: d306 bcc.n 10004344 +10004336: 4293 cmp r3, r2 +10004338: eba2 0303 sub.w r3, r2, r3 +1000433c: d8ed bhi.n 1000431a +1000433e: eb07 1343 add.w r3, r7, r3, lsl #5 +10004342: e7ee b.n 10004322 +10004344: 2254 movs r2, #84 @ 0x54 +10004346: 2100 movs r1, #0 +10004348: 480f ldr r0, [pc, #60] @ (10004388 ) +1000434a: f007 fd6f bl 1000be2c +1000434e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10004352: 4c0d ldr r4, [pc, #52] @ (10004388 ) +10004354: 2220 movs r2, #32 +10004356: e9c4 3301 strd r3, r3, [r4, #4] +1000435a: e9c4 3303 strd r3, r3, [r4, #12] +1000435e: 21ff movs r1, #255 @ 0xff +10004360: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10004364: 4809 ldr r0, [pc, #36] @ (1000438c ) +10004366: f007 bd61 b.w 1000be2c +1000436a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000436e: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004372: 07db lsls r3, r3, #31 +10004374: d500 bpl.n 10004378 +10004376: be00 bkpt 0x0000 +10004378: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000437c: 20002539 .word 0x20002539 +10004380: 1000ce74 .word 0x1000ce74 +10004384: 20001c38 .word 0x20001c38 +10004388: 20001d40 .word 0x20001d40 +1000438c: 20001d54 .word 0x20001d54 + +10004390 : +10004390: 4770 bx lr +10004392: bf00 nop + +10004394 : +10004394: 4770 bx lr +10004396: bf00 nop + +10004398 : +10004398: 2000 movs r0, #0 +1000439a: 4770 bx lr + +1000439c : +1000439c: 2000 movs r0, #0 +1000439e: 4770 bx lr + +100043a0 : +100043a0: 4770 bx lr +100043a2: bf00 nop + +100043a4 : +100043a4: 4770 bx lr +100043a6: bf00 nop + +100043a8 : +100043a8: 4770 bx lr +100043aa: bf00 nop + +100043ac : +100043ac: 4770 bx lr +100043ae: bf00 nop + +100043b0 : +100043b0: 4b02 ldr r3, [pc, #8] @ (100043bc ) +100043b2: 7858 ldrb r0, [r3, #1] +100043b4: 3800 subs r0, #0 +100043b6: bf18 it ne +100043b8: 2001 movne r0, #1 +100043ba: 4770 bx lr +100043bc: 20001d40 .word 0x20001d40 + +100043c0 : +100043c0: 4b02 ldr r3, [pc, #8] @ (100043cc ) +100043c2: 7818 ldrb r0, [r3, #0] +100043c4: f3c0 0080 ubfx r0, r0, #2, #1 +100043c8: 4770 bx lr +100043ca: bf00 nop +100043cc: 20001d40 .word 0x20001d40 + +100043d0 : +100043d0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100043d4: 4f2d ldr r7, [pc, #180] @ (1000448c ) +100043d6: 783b ldrb r3, [r7, #0] +100043d8: 2bff cmp r3, #255 @ 0xff +100043da: d154 bne.n 10004486 +100043dc: 2900 cmp r1, #0 +100043de: d03d beq.n 1000445c +100043e0: 2254 movs r2, #84 @ 0x54 +100043e2: 468a mov sl, r1 +100043e4: 4681 mov r9, r0 +100043e6: 2100 movs r1, #0 +100043e8: 4829 ldr r0, [pc, #164] @ (10004490 ) +100043ea: f007 fd1f bl 1000be2c +100043ee: 2200 movs r2, #0 +100043f0: 4c28 ldr r4, [pc, #160] @ (10004494 ) +100043f2: 4b29 ldr r3, [pc, #164] @ (10004498 ) +100043f4: 4620 mov r0, r4 +100043f6: 701a strb r2, [r3, #0] +100043f8: f7fc fb8a bl 10000b10 +100043fc: 4b27 ldr r3, [pc, #156] @ (1000449c ) +100043fe: 4828 ldr r0, [pc, #160] @ (100044a0 ) +10004400: 601c str r4, [r3, #0] +10004402: 4c28 ldr r4, [pc, #160] @ (100044a4 ) +10004404: f7fc fb92 bl 10000b2c +10004408: 4620 mov r0, r4 +1000440a: f001 fbdd bl 10005bc8 +1000440e: 4a26 ldr r2, [pc, #152] @ (100044a8 ) +10004410: 4b26 ldr r3, [pc, #152] @ (100044ac ) +10004412: 6014 str r4, [r2, #0] +10004414: b123 cbz r3, 10004420 +10004416: 4826 ldr r0, [pc, #152] @ (100044b0 ) +10004418: f7ff fdf0 bl 10003ffc +1000441c: 4b25 ldr r3, [pc, #148] @ (100044b4 ) +1000441e: 6018 str r0, [r3, #0] +10004420: f04f 0800 mov.w r8, #0 +10004424: 4c22 ldr r4, [pc, #136] @ (100044b0 ) +10004426: 4643 mov r3, r8 +10004428: 7822 ldrb r2, [r4, #0] +1000442a: 4e23 ldr r6, [pc, #140] @ (100044b8 ) +1000442c: 4d21 ldr r5, [pc, #132] @ (100044b4 ) +1000442e: e00d b.n 1000444c +10004430: 682a ldr r2, [r5, #0] +10004432: eb12 1343 adds.w r3, r2, r3, lsl #5 +10004436: d011 beq.n 1000445c +10004438: 685b ldr r3, [r3, #4] +1000443a: b17b cbz r3, 1000445c +1000443c: 4798 blx r3 +1000443e: f108 0801 add.w r8, r8, #1 +10004442: 7822 ldrb r2, [r4, #0] +10004444: fa5f f388 uxtb.w r3, r8 +10004448: 4293 cmp r3, r2 +1000444a: d811 bhi.n 10004470 +1000444c: 4293 cmp r3, r2 +1000444e: d3ef bcc.n 10004430 +10004450: 1a9b subs r3, r3, r2 +10004452: eb06 1343 add.w r3, r6, r3, lsl #5 +10004456: 685b ldr r3, [r3, #4] +10004458: 2b00 cmp r3, #0 +1000445a: d1ef bne.n 1000443c +1000445c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004460: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004464: 07db lsls r3, r3, #31 +10004466: d500 bpl.n 1000446a +10004468: be00 bkpt 0x0000 +1000446a: 2000 movs r0, #0 +1000446c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10004470: 4651 mov r1, sl +10004472: 4648 mov r0, r9 +10004474: f887 9000 strb.w r9, [r7] +10004478: f7ff fdd4 bl 10004024 +1000447c: 2800 cmp r0, #0 +1000447e: d0ed beq.n 1000445c +10004480: 4648 mov r0, r9 +10004482: f7ff fe1d bl 100040c0 +10004486: 2001 movs r0, #1 +10004488: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000448c: 20001250 .word 0x20001250 +10004490: 20001d40 .word 0x20001d40 +10004494: 20001d38 .word 0x20001d38 +10004498: 2000253b .word 0x2000253b +1000449c: 20001d94 .word 0x20001d94 +100044a0: 20001248 .word 0x20001248 +100044a4: 20001234 .word 0x20001234 +100044a8: 20001d98 .word 0x20001d98 +100044ac: 10003ffd .word 0x10003ffd +100044b0: 20002539 .word 0x20002539 +100044b4: 20001c38 .word 0x20001c38 +100044b8: 1000ce74 .word 0x1000ce74 + +100044bc : +100044bc: 4ba4 ldr r3, [pc, #656] @ (10004750 ) +100044be: 781b ldrb r3, [r3, #0] +100044c0: 2bff cmp r3, #255 @ 0xff +100044c2: f000 8112 beq.w 100046ea +100044c6: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100044ca: 4ca2 ldr r4, [pc, #648] @ (10004754 ) +100044cc: 4da2 ldr r5, [pc, #648] @ (10004758 ) +100044ce: f8df 829c ldr.w r8, [pc, #668] @ 1000476c +100044d2: 4ea2 ldr r6, [pc, #648] @ (1000475c ) +100044d4: b08b sub sp, #44 @ 0x2c +100044d6: 6827 ldr r7, [r4, #0] +100044d8: 697b ldr r3, [r7, #20] +100044da: f3ef 8210 mrs r2, PRIMASK +100044de: b672 cpsid i +100044e0: e8d3 0fcf ldaexb r0, [r3] +100044e4: 2101 movs r1, #1 +100044e6: 2800 cmp r0, #0 +100044e8: d1fa bne.n 100044e0 +100044ea: e8c3 1f40 strexb r0, r1, [r3] +100044ee: 2800 cmp r0, #0 +100044f0: d1f6 bne.n 100044e0 +100044f2: f3bf 8f5f dmb sy +100044f6: 61ba str r2, [r7, #24] +100044f8: 4638 mov r0, r7 +100044fa: a907 add r1, sp, #28 +100044fc: f001 f9aa bl 10005854 +10004500: 2300 movs r3, #0 +10004502: 697a ldr r2, [r7, #20] +10004504: e8c2 3f8f stlb r3, [r2] +10004508: 69bb ldr r3, [r7, #24] +1000450a: f383 8810 msr PRIMASK, r3 +1000450e: 2800 cmp r0, #0 +10004510: f000 80c6 beq.w 100046a0 +10004514: f89d 301d ldrb.w r3, [sp, #29] +10004518: 3b01 subs r3, #1 +1000451a: 2b07 cmp r3, #7 +1000451c: f200 8383 bhi.w 10004c26 +10004520: e8df f003 tbb [pc, r3] +10004524: 9991ada3 .word 0x9991ada3 +10004528: 040a358a .word 0x040a358a +1000452c: 9b08 ldr r3, [sp, #32] +1000452e: 2b00 cmp r3, #0 +10004530: d0d1 beq.n 100044d6 +10004532: 9809 ldr r0, [sp, #36] @ 0x24 +10004534: 4798 blx r3 +10004536: e7ce b.n 100044d6 +10004538: f89d 1020 ldrb.w r1, [sp, #32] +1000453c: f001 077f and.w r7, r1, #127 @ 0x7f +10004540: eb05 0047 add.w r0, r5, r7, lsl #1 +10004544: eb00 10d1 add.w r0, r0, r1, lsr #7 +10004548: f890 3034 ldrb.w r3, [r0, #52] @ 0x34 +1000454c: f023 0301 bic.w r3, r3, #1 +10004550: f880 3034 strb.w r3, [r0, #52] @ 0x34 +10004554: f890 3034 ldrb.w r3, [r0, #52] @ 0x34 +10004558: f023 0304 bic.w r3, r3, #4 +1000455c: f880 3034 strb.w r3, [r0, #52] @ 0x34 +10004560: 2f00 cmp r7, #0 +10004562: f000 80a0 beq.w 100046a6 +10004566: 7d02 ldrb r2, [r0, #20] +10004568: f898 3000 ldrb.w r3, [r8] +1000456c: 429a cmp r2, r3 +1000456e: f080 808f bcs.w 10004690 +10004572: 4b7b ldr r3, [pc, #492] @ (10004760 ) +10004574: 681b ldr r3, [r3, #0] +10004576: eb13 1342 adds.w r3, r3, r2, lsl #5 +1000457a: f000 808a beq.w 10004692 +1000457e: 699f ldr r7, [r3, #24] +10004580: f89d 2021 ldrb.w r2, [sp, #33] @ 0x21 +10004584: 9b09 ldr r3, [sp, #36] @ 0x24 +10004586: f89d 001c ldrb.w r0, [sp, #28] +1000458a: 47b8 blx r7 +1000458c: e7a3 b.n 100044d6 +1000458e: 7833 ldrb r3, [r6, #0] +10004590: 2b00 cmp r3, #0 +10004592: d07e beq.n 10004692 +10004594: 7833 ldrb r3, [r6, #0] +10004596: 3b01 subs r3, #1 +10004598: 7033 strb r3, [r6, #0] +1000459a: 7833 ldrb r3, [r6, #0] +1000459c: f003 00ff and.w r0, r3, #255 @ 0xff +100045a0: 2b00 cmp r3, #0 +100045a2: d198 bne.n 100044d6 +100045a4: f8df a1b0 ldr.w sl, [pc, #432] @ 10004758 +100045a8: f89d b01c ldrb.w fp, [sp, #28] +100045ac: f89a 3000 ldrb.w r3, [sl] +100045b0: f043 0301 orr.w r3, r3, #1 +100045b4: f88a 3000 strb.w r3, [sl] +100045b8: f89a 3034 ldrb.w r3, [sl, #52] @ 0x34 +100045bc: f360 0300 bfi r3, r0, #0, #1 +100045c0: f88a 3034 strb.w r3, [sl, #52] @ 0x34 +100045c4: f89a 3034 ldrb.w r3, [sl, #52] @ 0x34 +100045c8: f360 0382 bfi r3, r0, #2, #1 +100045cc: f88a 3034 strb.w r3, [sl, #52] @ 0x34 +100045d0: f89a 3035 ldrb.w r3, [sl, #53] @ 0x35 +100045d4: f360 0300 bfi r3, r0, #0, #1 +100045d8: f88a 3035 strb.w r3, [sl, #53] @ 0x35 +100045dc: f89a 3035 ldrb.w r3, [sl, #53] @ 0x35 +100045e0: f360 0382 bfi r3, r0, #2, #1 +100045e4: f88a 3035 strb.w r3, [sl, #53] @ 0x35 +100045e8: f000 fc88 bl 10004efc +100045ec: f89d 3020 ldrb.w r3, [sp, #32] +100045f0: f003 0260 and.w r2, r3, #96 @ 0x60 +100045f4: 2a60 cmp r2, #96 @ 0x60 +100045f6: d066 beq.n 100046c6 +100045f8: 2a40 cmp r2, #64 @ 0x40 +100045fa: d077 beq.n 100046ec +100045fc: f003 031f and.w r3, r3, #31 +10004600: 2b01 cmp r3, #1 +10004602: f000 80b5 beq.w 10004770 +10004606: 2b02 cmp r3, #2 +10004608: d07c beq.n 10004704 +1000460a: 2b00 cmp r3, #0 +1000460c: d15b bne.n 100046c6 +1000460e: 2a20 cmp r2, #32 +10004610: f000 81e7 beq.w 100049e2 +10004614: 2a00 cmp r2, #0 +10004616: d156 bne.n 100046c6 +10004618: f89d 3021 ldrb.w r3, [sp, #33] @ 0x21 +1000461c: 2b09 cmp r3, #9 +1000461e: d852 bhi.n 100046c6 +10004620: e8df f013 tbh [pc, r3, lsl #1] +10004624: 019b01ab .word 0x019b01ab +10004628: 01bd0051 .word 0x01bd0051 +1000462c: 018c0051 .word 0x018c0051 +10004630: 00510162 .word 0x00510162 +10004634: 00e70156 .word 0x00e70156 +10004638: 782b ldrb r3, [r5, #0] +1000463a: 07d9 lsls r1, r3, #31 +1000463c: f57f af4b bpl.w 100044d6 +10004640: f7ff feb4 bl 100043ac +10004644: e747 b.n 100044d6 +10004646: 78eb ldrb r3, [r5, #3] +10004648: 07da lsls r2, r3, #31 +1000464a: f57f af44 bpl.w 100044d6 +1000464e: 9808 ldr r0, [sp, #32] +10004650: f7ff fea0 bl 10004394 +10004654: e73f b.n 100044d6 +10004656: 782b ldrb r3, [r5, #0] +10004658: 07d8 lsls r0, r3, #31 +1000465a: f57f af3c bpl.w 100044d6 +1000465e: 7828 ldrb r0, [r5, #0] +10004660: f3c0 00c0 ubfx r0, r0, #3, #1 +10004664: f7ff fea0 bl 100043a8 +10004668: e735 b.n 100044d6 +1000466a: f89d 001c ldrb.w r0, [sp, #28] +1000466e: f7ff fe49 bl 10004304 +10004672: f000 fc39 bl 10004ee8 +10004676: f89d 3020 ldrb.w r3, [sp, #32] +1000467a: 70ab strb r3, [r5, #2] +1000467c: e72b b.n 100044d6 +1000467e: f89d 001c ldrb.w r0, [sp, #28] +10004682: f7ff fe3f bl 10004304 +10004686: f000 fc2f bl 10004ee8 +1000468a: f7ff fe8b bl 100043a4 +1000468e: e722 b.n 100044d6 +10004690: d011 beq.n 100046b6 +10004692: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004696: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +1000469a: 07dc lsls r4, r3, #31 +1000469c: d500 bpl.n 100046a0 +1000469e: be00 bkpt 0x0000 +100046a0: b00b add sp, #44 @ 0x2c +100046a2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100046a6: 9b09 ldr r3, [sp, #36] @ 0x24 +100046a8: f89d 2021 ldrb.w r2, [sp, #33] @ 0x21 +100046ac: f89d 001c ldrb.w r0, [sp, #28] +100046b0: f000 fc38 bl 10004f24 +100046b4: e70f b.n 100044d6 +100046b6: 4b2b ldr r3, [pc, #172] @ (10004764 ) +100046b8: e761 b.n 1000457e +100046ba: f7ff fb1f bl 10003cfc +100046be: 4602 mov r2, r0 +100046c0: 2800 cmp r0, #0 +100046c2: f040 8185 bne.w 100049d0 +100046c6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100046ca: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +100046ce: 07df lsls r7, r3, #31 +100046d0: d500 bpl.n 100046d4 +100046d2: be00 bkpt 0x0000 +100046d4: f89d 001c ldrb.w r0, [sp, #28] +100046d8: 2100 movs r1, #0 +100046da: f7ff fda9 bl 10004230 +100046de: 2180 movs r1, #128 @ 0x80 +100046e0: f89d 001c ldrb.w r0, [sp, #28] +100046e4: f7ff fda4 bl 10004230 +100046e8: e6f5 b.n 100044d6 +100046ea: 4770 bx lr +100046ec: 481e ldr r0, [pc, #120] @ (10004768 ) +100046ee: f000 fc05 bl 10004efc +100046f2: 2101 movs r1, #1 +100046f4: 4658 mov r0, fp +100046f6: aa08 add r2, sp, #32 +100046f8: f7ff fc6c bl 10003fd4 +100046fc: 2800 cmp r0, #0 +100046fe: f47f aeea bne.w 100044d6 +10004702: e7e7 b.n 100046d4 +10004704: f89d 1024 ldrb.w r1, [sp, #36] @ 0x24 +10004708: f011 0f70 tst.w r1, #112 @ 0x70 +1000470c: d1db bne.n 100046c6 +1000470e: 4817 ldr r0, [pc, #92] @ (1000476c ) +10004710: f001 037f and.w r3, r1, #127 @ 0x7f +10004714: f890 c000 ldrb.w ip, [r0] +10004718: eb0a 0043 add.w r0, sl, r3, lsl #1 +1000471c: eb00 10d1 add.w r0, r0, r1, lsr #7 +10004720: 7d00 ldrb r0, [r0, #20] +10004722: 4560 cmp r0, ip +10004724: d351 bcc.n 100047ca +10004726: f040 816e bne.w 10004a06 +1000472a: 480e ldr r0, [pc, #56] @ (10004764 ) +1000472c: 9000 str r0, [sp, #0] +1000472e: 2a00 cmp r2, #0 +10004730: f000 816d beq.w 10004a0e +10004734: 9f00 ldr r7, [sp, #0] +10004736: 6978 ldr r0, [r7, #20] +10004738: f000 fbe0 bl 10004efc +1000473c: 2101 movs r1, #1 +1000473e: 4658 mov r0, fp +10004740: 697b ldr r3, [r7, #20] +10004742: aa08 add r2, sp, #32 +10004744: 4798 blx r3 +10004746: 2800 cmp r0, #0 +10004748: f47f aec5 bne.w 100044d6 +1000474c: e7c2 b.n 100046d4 +1000474e: bf00 nop +10004750: 20001250 .word 0x20001250 +10004754: 20001d98 .word 0x20001d98 +10004758: 20001d40 .word 0x20001d40 +1000475c: 2000253b .word 0x2000253b +10004760: 20001c38 .word 0x20001c38 +10004764: 1000ce74 .word 0x1000ce74 +10004768: 10003fd5 .word 0x10003fd5 +1000476c: 20002539 .word 0x20002539 +10004770: f89d 3024 ldrb.w r3, [sp, #36] @ 0x24 +10004774: 2b0f cmp r3, #15 +10004776: d8ad bhi.n 100046d4 +10004778: 4ab1 ldr r2, [pc, #708] @ (10004a40 ) +1000477a: 4453 add r3, sl +1000477c: 791b ldrb r3, [r3, #4] +1000477e: 7812 ldrb r2, [r2, #0] +10004780: 4293 cmp r3, r2 +10004782: d330 bcc.n 100047e6 +10004784: d1a6 bne.n 100046d4 +10004786: 4faf ldr r7, [pc, #700] @ (10004a44 ) +10004788: 6978 ldr r0, [r7, #20] +1000478a: f000 fbb7 bl 10004efc +1000478e: 2101 movs r1, #1 +10004790: 4658 mov r0, fp +10004792: 697b ldr r3, [r7, #20] +10004794: aa08 add r2, sp, #32 +10004796: 4798 blx r3 +10004798: 2800 cmp r0, #0 +1000479a: f47f ae9c bne.w 100044d6 +1000479e: f89d 3020 ldrb.w r3, [sp, #32] +100047a2: f013 0760 ands.w r7, r3, #96 @ 0x60 +100047a6: d195 bne.n 100046d4 +100047a8: f89d 3021 ldrb.w r3, [sp, #33] @ 0x21 +100047ac: 3b0a subs r3, #10 +100047ae: 2b01 cmp r3, #1 +100047b0: d890 bhi.n 100046d4 +100047b2: f000 fba3 bl 10004efc +100047b6: f89d 3021 ldrb.w r3, [sp, #33] @ 0x21 +100047ba: 2b0a cmp r3, #10 +100047bc: f000 820d beq.w 10004bda +100047c0: 4658 mov r0, fp +100047c2: a908 add r1, sp, #32 +100047c4: f000 fb1a bl 10004dfc +100047c8: e685 b.n 100044d6 +100047ca: f8df c27c ldr.w ip, [pc, #636] @ 10004a48 +100047ce: f8dc c000 ldr.w ip, [ip] +100047d2: eb0c 1040 add.w r0, ip, r0, lsl #5 +100047d6: 9000 str r0, [sp, #0] +100047d8: 2a00 cmp r2, #0 +100047da: f000 8118 beq.w 10004a0e +100047de: 2800 cmp r0, #0 +100047e0: f43f af78 beq.w 100046d4 +100047e4: e7a6 b.n 10004734 +100047e6: 4a98 ldr r2, [pc, #608] @ (10004a48 ) +100047e8: 6817 ldr r7, [r2, #0] +100047ea: eb17 1743 adds.w r7, r7, r3, lsl #5 +100047ee: d1cb bne.n 10004788 +100047f0: e770 b.n 100046d4 +100047f2: f89a 2001 ldrb.w r2, [sl, #1] +100047f6: f89d 3022 ldrb.w r3, [sp, #34] @ 0x22 +100047fa: 4293 cmp r3, r2 +100047fc: f000 815d beq.w 10004aba +10004800: f89a 2001 ldrb.w r2, [sl, #1] +10004804: 2a00 cmp r2, #0 +10004806: f040 81d2 bne.w 10004bae +1000480a: f88a 3001 strb.w r3, [sl, #1] +1000480e: 2b00 cmp r3, #0 +10004810: f000 8151 beq.w 10004ab6 +10004814: 3b01 subs r3, #1 +10004816: b2d8 uxtb r0, r3 +10004818: f7ff fa70 bl 10003cfc +1000481c: 2800 cmp r0, #0 +1000481e: f000 816e beq.w 10004afe +10004822: 7843 ldrb r3, [r0, #1] +10004824: 2b02 cmp r3, #2 +10004826: f040 816a bne.w 10004afe +1000482a: 79c2 ldrb r2, [r0, #7] +1000482c: f89a 1000 ldrb.w r1, [sl] +10004830: f3c2 1340 ubfx r3, r2, #5, #1 +10004834: 011b lsls r3, r3, #4 +10004836: f3c2 1280 ubfx r2, r2, #6, #1 +1000483a: f021 0130 bic.w r1, r1, #48 @ 0x30 +1000483e: ea43 1342 orr.w r3, r3, r2, lsl #5 +10004842: 430b orrs r3, r1 +10004844: f88a 3000 strb.w r3, [sl] +10004848: 8843 ldrh r3, [r0, #2] +1000484a: f100 0109 add.w r1, r0, #9 +1000484e: 18c3 adds r3, r0, r3 +10004850: 9302 str r3, [sp, #8] +10004852: 9b02 ldr r3, [sp, #8] +10004854: 428b cmp r3, r1 +10004856: f240 81bd bls.w 10004bd4 +1000485a: 784b ldrb r3, [r1, #1] +1000485c: 2b0b cmp r3, #11 +1000485e: f000 81c6 beq.w 10004bee +10004862: 2001 movs r0, #1 +10004864: 2b04 cmp r3, #4 +10004866: f040 814a bne.w 10004afe +1000486a: 2200 movs r2, #0 +1000486c: 9b02 ldr r3, [sp, #8] +1000486e: 9201 str r2, [sp, #4] +10004870: 1a5b subs r3, r3, r1 +10004872: fa1f f983 uxth.w r9, r3 +10004876: 4b72 ldr r3, [pc, #456] @ (10004a40 ) +10004878: 9200 str r2, [sp, #0] +1000487a: 781b ldrb r3, [r3, #0] +1000487c: 9003 str r0, [sp, #12] +1000487e: e01e b.n 100048be +10004880: 4b71 ldr r3, [pc, #452] @ (10004a48 ) +10004882: 681b ldr r3, [r3, #0] +10004884: eb13 1342 adds.w r3, r3, r2, lsl #5 +10004888: f000 8139 beq.w 10004afe +1000488c: 691f ldr r7, [r3, #16] +1000488e: 464a mov r2, r9 +10004890: 4658 mov r0, fp +10004892: 9105 str r1, [sp, #20] +10004894: 9304 str r3, [sp, #16] +10004896: 47b8 blx r7 +10004898: 9b01 ldr r3, [sp, #4] +1000489a: 2808 cmp r0, #8 +1000489c: f103 0301 add.w r3, r3, #1 +100048a0: 9905 ldr r1, [sp, #20] +100048a2: 9301 str r3, [sp, #4] +100048a4: d903 bls.n 100048ae +100048a6: 4581 cmp r9, r0 +100048a8: 9b04 ldr r3, [sp, #16] +100048aa: f080 810b bcs.w 10004ac4 +100048ae: 4b64 ldr r3, [pc, #400] @ (10004a40 ) +100048b0: f89d 2004 ldrb.w r2, [sp, #4] +100048b4: 781b ldrb r3, [r3, #0] +100048b6: 9200 str r2, [sp, #0] +100048b8: 4293 cmp r3, r2 +100048ba: f0c0 8120 bcc.w 10004afe +100048be: 9a00 ldr r2, [sp, #0] +100048c0: 4293 cmp r3, r2 +100048c2: eba2 0303 sub.w r3, r2, r3 +100048c6: d8db bhi.n 10004880 +100048c8: 4a5e ldr r2, [pc, #376] @ (10004a44 ) +100048ca: eb02 1343 add.w r3, r2, r3, lsl #5 +100048ce: e7dd b.n 1000488c +100048d0: f89a 3001 ldrb.w r3, [sl, #1] +100048d4: 4658 mov r0, fp +100048d6: f88d 301a strb.w r3, [sp, #26] +100048da: f10d 021a add.w r2, sp, #26 +100048de: 2301 movs r3, #1 +100048e0: a908 add r1, sp, #32 +100048e2: f000 faa7 bl 10004e34 +100048e6: e5f6 b.n 100044d6 +100048e8: f8bd 0022 ldrh.w r0, [sp, #34] @ 0x22 +100048ec: 0a03 lsrs r3, r0, #8 +100048ee: 1e5a subs r2, r3, #1 +100048f0: b2c0 uxtb r0, r0 +100048f2: 2a0e cmp r2, #14 +100048f4: f63f aeee bhi.w 100046d4 +100048f8: a101 add r1, pc, #4 @ (adr r1, 10004900 ) +100048fa: f851 f022 ldr.w pc, [r1, r2, lsl #2] +100048fe: bf00 nop +10004900: 10004b31 .word 0x10004b31 +10004904: 100049bf .word 0x100049bf +10004908: 10004b6d .word 0x10004b6d +1000490c: 100046d5 .word 0x100046d5 +10004910: 100046d5 .word 0x100046d5 +10004914: 10004b4f .word 0x10004b4f +10004918: 100049bf .word 0x100049bf +1000491c: 100046d5 .word 0x100046d5 +10004920: 100046d5 .word 0x100046d5 +10004924: 100046d5 .word 0x100046d5 +10004928: 100046d5 .word 0x100046d5 +1000492c: 100046d5 .word 0x100046d5 +10004930: 100046d5 .word 0x100046d5 +10004934: 100046d5 .word 0x100046d5 +10004938: 10004b23 .word 0x10004b23 +1000493c: a808 add r0, sp, #32 +1000493e: f000 fae3 bl 10004f08 +10004942: 4658 mov r0, fp +10004944: f89d 1022 ldrb.w r1, [sp, #34] @ 0x22 +10004948: f7ff fbbe bl 100040c8 +1000494c: f89a 3000 ldrb.w r3, [sl] +10004950: f043 0302 orr.w r3, r3, #2 +10004954: f88a 3000 strb.w r3, [sl] +10004958: e5bd b.n 100044d6 +1000495a: f8bd 3022 ldrh.w r3, [sp, #34] @ 0x22 +1000495e: 2b01 cmp r3, #1 +10004960: f47f aeb8 bne.w 100046d4 +10004964: f89a 3000 ldrb.w r3, [sl] +10004968: 4658 mov r0, fp +1000496a: f023 0308 bic.w r3, r3, #8 +1000496e: a908 add r1, sp, #32 +10004970: f88a 3000 strb.w r3, [sl] +10004974: f000 fa42 bl 10004dfc +10004978: e5ad b.n 100044d6 +1000497a: 4658 mov r0, fp +1000497c: f89a 3000 ldrb.w r3, [sl] +10004980: 089a lsrs r2, r3, #2 +10004982: f002 0202 and.w r2, r2, #2 +10004986: f3c3 1340 ubfx r3, r3, #5, #1 +1000498a: 4313 orrs r3, r2 +1000498c: f8ad 301a strh.w r3, [sp, #26] +10004990: f10d 021a add.w r2, sp, #26 +10004994: 2302 movs r3, #2 +10004996: a908 add r1, sp, #32 +10004998: f000 fa4c bl 10004e34 +1000499c: e59b b.n 100044d6 +1000499e: f8bd 3022 ldrh.w r3, [sp, #34] @ 0x22 +100049a2: 2b01 cmp r3, #1 +100049a4: f47f ae96 bne.w 100046d4 +100049a8: f89a 3000 ldrb.w r3, [sl] +100049ac: 4658 mov r0, fp +100049ae: f043 0308 orr.w r3, r3, #8 +100049b2: a908 add r1, sp, #32 +100049b4: f88a 3000 strb.w r3, [sl] +100049b8: f000 fa20 bl 10004dfc +100049bc: e58b b.n 100044d6 +100049be: 2b02 cmp r3, #2 +100049c0: f43f ae7b beq.w 100046ba +100049c4: f7ff fcea bl 1000439c +100049c8: 4602 mov r2, r0 +100049ca: 2800 cmp r0, #0 +100049cc: f43f ae82 beq.w 100046d4 +100049d0: 4658 mov r0, fp +100049d2: 8853 ldrh r3, [r2, #2] +100049d4: a908 add r1, sp, #32 +100049d6: f000 fa2d bl 10004e34 +100049da: 2800 cmp r0, #0 +100049dc: f47f ad7b bne.w 100044d6 +100049e0: e678 b.n 100046d4 +100049e2: f89d 3024 ldrb.w r3, [sp, #36] @ 0x24 +100049e6: 2b0f cmp r3, #15 +100049e8: f63f ae74 bhi.w 100046d4 +100049ec: 4a14 ldr r2, [pc, #80] @ (10004a40 ) +100049ee: 4453 add r3, sl +100049f0: 791b ldrb r3, [r3, #4] +100049f2: 7812 ldrb r2, [r2, #0] +100049f4: 4293 cmp r3, r2 +100049f6: d21e bcs.n 10004a36 +100049f8: 4a13 ldr r2, [pc, #76] @ (10004a48 ) +100049fa: 6817 ldr r7, [r2, #0] +100049fc: eb17 1743 adds.w r7, r7, r3, lsl #5 +10004a00: f47f ae99 bne.w 10004736 +10004a04: e666 b.n 100046d4 +10004a06: 2a00 cmp r2, #0 +10004a08: f47f ae64 bne.w 100046d4 +10004a0c: 9200 str r2, [sp, #0] +10004a0e: f89d c021 ldrb.w ip, [sp, #33] @ 0x21 +10004a12: f00c 02fd and.w r2, ip, #253 @ 0xfd +10004a16: 2a01 cmp r2, #1 +10004a18: d018 beq.n 10004a4c +10004a1a: f1bc 0f00 cmp.w ip, #0 +10004a1e: f47f ae52 bne.w 100046c6 +10004a22: eb0a 0343 add.w r3, sl, r3, lsl #1 +10004a26: eb03 13d1 add.w r3, r3, r1, lsr #7 +10004a2a: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 +10004a2e: 4658 mov r0, fp +10004a30: f3c3 0340 ubfx r3, r3, #1, #1 +10004a34: e7aa b.n 1000498c +10004a36: f47f ae4d bne.w 100046d4 +10004a3a: 4f02 ldr r7, [pc, #8] @ (10004a44 ) +10004a3c: e67b b.n 10004736 +10004a3e: bf00 nop +10004a40: 20002539 .word 0x20002539 +10004a44: 1000ce74 .word 0x1000ce74 +10004a48: 20001c38 .word 0x20001c38 +10004a4c: f8bd 2022 ldrh.w r2, [sp, #34] @ 0x22 +10004a50: b9da cbnz r2, 10004a8a +10004a52: 4879 ldr r0, [pc, #484] @ (10004c38 ) +10004a54: f1bc 0f01 cmp.w ip, #1 +10004a58: 7800 ldrb r0, [r0, #0] +10004a5a: f000 808f beq.w 10004b7c +10004a5e: e9cd 1301 strd r1, r3, [sp, #4] +10004a62: f7ff fbe5 bl 10004230 +10004a66: 9b02 ldr r3, [sp, #8] +10004a68: 9901 ldr r1, [sp, #4] +10004a6a: eb0a 0343 add.w r3, sl, r3, lsl #1 +10004a6e: eb03 13d1 add.w r3, r3, r1, lsr #7 +10004a72: f893 2034 ldrb.w r2, [r3, #52] @ 0x34 +10004a76: f042 0202 orr.w r2, r2, #2 +10004a7a: f883 2034 strb.w r2, [r3, #52] @ 0x34 +10004a7e: f893 2034 ldrb.w r2, [r3, #52] @ 0x34 +10004a82: f042 0201 orr.w r2, r2, #1 +10004a86: f883 2034 strb.w r2, [r3, #52] @ 0x34 +10004a8a: 9b00 ldr r3, [sp, #0] +10004a8c: 2b00 cmp r3, #0 +10004a8e: f43f ad22 beq.w 100044d6 +10004a92: 461f mov r7, r3 +10004a94: 6958 ldr r0, [r3, #20] +10004a96: f000 fa31 bl 10004efc +10004a9a: 697b ldr r3, [r7, #20] +10004a9c: 2101 movs r1, #1 +10004a9e: aa08 add r2, sp, #32 +10004aa0: 4658 mov r0, fp +10004aa2: 4798 blx r3 +10004aa4: 2000 movs r0, #0 +10004aa6: f000 fa29 bl 10004efc +10004aaa: f89a 3035 ldrb.w r3, [sl, #53] @ 0x35 +10004aae: 07db lsls r3, r3, #31 +10004ab0: f53f ad11 bmi.w 100044d6 +10004ab4: e684 b.n 100047c0 +10004ab6: f7ff fc75 bl 100043a4 +10004aba: 4658 mov r0, fp +10004abc: a908 add r1, sp, #32 +10004abe: f000 f99d bl 10004dfc +10004ac2: e508 b.n 100044d6 +10004ac4: 4602 mov r2, r0 +10004ac6: 9803 ldr r0, [sp, #12] +10004ac8: 2801 cmp r0, #1 +10004aca: f000 80a5 beq.w 10004c18 +10004ace: 2800 cmp r0, #0 +10004ad0: f000 8092 beq.w 10004bf8 +10004ad4: 2300 movs r3, #0 +10004ad6: f891 e002 ldrb.w lr, [r1, #2] +10004ada: e007 b.n 10004aec +10004adc: 9f00 ldr r7, [sp, #0] +10004ade: f88c 7004 strb.w r7, [ip, #4] +10004ae2: fa5f fc83 uxtb.w ip, r3 +10004ae6: 4560 cmp r0, ip +10004ae8: f240 8086 bls.w 10004bf8 +10004aec: eb0e 0c03 add.w ip, lr, r3 +10004af0: fa5a fc8c uxtab ip, sl, ip +10004af4: f89c 7004 ldrb.w r7, [ip, #4] +10004af8: 3301 adds r3, #1 +10004afa: 2fff cmp r7, #255 @ 0xff +10004afc: d0ee beq.n 10004adc +10004afe: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004b02: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004b06: 07d9 lsls r1, r3, #31 +10004b08: d500 bpl.n 10004b0c +10004b0a: be00 bkpt 0x0000 +10004b0c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004b10: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004b14: 07da lsls r2, r3, #31 +10004b16: d500 bpl.n 10004b1a +10004b18: be00 bkpt 0x0000 +10004b1a: 2300 movs r3, #0 +10004b1c: f88a 3001 strb.w r3, [sl, #1] +10004b20: e5d8 b.n 100046d4 +10004b22: f7ff fa53 bl 10003fcc +10004b26: 4602 mov r2, r0 +10004b28: 2800 cmp r0, #0 +10004b2a: f47f af51 bne.w 100049d0 +10004b2e: e5d1 b.n 100046d4 +10004b30: f7ff f8e0 bl 10003cf4 +10004b34: 4602 mov r2, r0 +10004b36: 2800 cmp r0, #0 +10004b38: f43f adc5 beq.w 100046c6 +10004b3c: 4658 mov r0, fp +10004b3e: 2312 movs r3, #18 +10004b40: a908 add r1, sp, #32 +10004b42: f000 f977 bl 10004e34 +10004b46: 2800 cmp r0, #0 +10004b48: f47f acc5 bne.w 100044d6 +10004b4c: e5c2 b.n 100046d4 +10004b4e: f7ff fc23 bl 10004398 +10004b52: 4602 mov r2, r0 +10004b54: 2800 cmp r0, #0 +10004b56: f43f adbd beq.w 100046d4 +10004b5a: 4658 mov r0, fp +10004b5c: 7813 ldrb r3, [r2, #0] +10004b5e: a908 add r1, sp, #32 +10004b60: f000 f968 bl 10004e34 +10004b64: 2800 cmp r0, #0 +10004b66: f47f acb6 bne.w 100044d6 +10004b6a: e5b3 b.n 100046d4 +10004b6c: f8bd 1024 ldrh.w r1, [sp, #36] @ 0x24 +10004b70: f7ff f8c8 bl 10003d04 +10004b74: 4602 mov r2, r0 +10004b76: 2800 cmp r0, #0 +10004b78: d1ef bne.n 10004b5a +10004b7a: e5ab b.n 100046d4 +10004b7c: e9cd 3202 strd r3, r2, [sp, #8] +10004b80: 9101 str r1, [sp, #4] +10004b82: f7ff fb6d bl 10004260 +10004b86: 9b02 ldr r3, [sp, #8] +10004b88: 9901 ldr r1, [sp, #4] +10004b8a: eb0a 0343 add.w r3, sl, r3, lsl #1 +10004b8e: eb03 13d1 add.w r3, r3, r1, lsr #7 +10004b92: f893 1034 ldrb.w r1, [r3, #52] @ 0x34 +10004b96: 9a03 ldr r2, [sp, #12] +10004b98: f362 0141 bfi r1, r2, #1, #1 +10004b9c: f883 1034 strb.w r1, [r3, #52] @ 0x34 +10004ba0: f893 1034 ldrb.w r1, [r3, #52] @ 0x34 +10004ba4: f362 0100 bfi r1, r2, #0, #1 +10004ba8: f883 1034 strb.w r1, [r3, #52] @ 0x34 +10004bac: e76d b.n 10004a8a +10004bae: 2100 movs r1, #0 +10004bb0: 4658 mov r0, fp +10004bb2: 9301 str r3, [sp, #4] +10004bb4: f7ff fa90 bl 100040d8 +10004bb8: 4658 mov r0, fp +10004bba: f7ff fb23 bl 10004204 +10004bbe: f89a 2002 ldrb.w r2, [sl, #2] +10004bc2: 4658 mov r0, fp +10004bc4: 9200 str r2, [sp, #0] +10004bc6: f7ff fb9d bl 10004304 +10004bca: 9a00 ldr r2, [sp, #0] +10004bcc: 9b01 ldr r3, [sp, #4] +10004bce: f88a 2002 strb.w r2, [sl, #2] +10004bd2: e61a b.n 1000480a +10004bd4: f7ff fbe4 bl 100043a0 +10004bd8: e76f b.n 10004aba +10004bda: 4658 mov r0, fp +10004bdc: 2301 movs r3, #1 +10004bde: a908 add r1, sp, #32 +10004be0: f10d 021a add.w r2, sp, #26 +10004be4: f88d 701a strb.w r7, [sp, #26] +10004be8: f000 f924 bl 10004e34 +10004bec: e473 b.n 100044d6 +10004bee: 780b ldrb r3, [r1, #0] +10004bf0: 78c8 ldrb r0, [r1, #3] +10004bf2: 4419 add r1, r3 +10004bf4: 784b ldrb r3, [r1, #1] +10004bf6: e635 b.n 10004864 +10004bf8: 9f00 ldr r7, [sp, #0] +10004bfa: 4810 ldr r0, [pc, #64] @ (10004c3c ) +10004bfc: 463b mov r3, r7 +10004bfe: e9cd 1200 strd r1, r2, [sp] +10004c02: f000 fda1 bl 10005748 +10004c06: e9dd 1200 ldrd r1, r2, [sp] +10004c0a: 4411 add r1, r2 +10004c0c: 4a0c ldr r2, [pc, #48] @ (10004c40 ) +10004c0e: 7813 ldrb r3, [r2, #0] +10004c10: 42bb cmp r3, r7 +10004c12: f4bf ae1e bcs.w 10004852 +10004c16: e772 b.n 10004afe +10004c18: f8d3 c010 ldr.w ip, [r3, #16] +10004c1c: 4b09 ldr r3, [pc, #36] @ (10004c44 ) +10004c1e: 459c cmp ip, r3 +10004c20: bf08 it eq +10004c22: 2002 moveq r0, #2 +10004c24: e756 b.n 10004ad4 +10004c26: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004c2a: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004c2e: 07db lsls r3, r3, #31 +10004c30: f57f ac51 bpl.w 100044d6 +10004c34: be00 bkpt 0x0000 +10004c36: e44e b.n 100044d6 +10004c38: 20001250 .word 0x20001250 +10004c3c: 20001d54 .word 0x20001d54 +10004c40: 20002539 .word 0x20002539 +10004c44: 1000534d .word 0x1000534d + +10004c48 : +10004c48: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10004c4c: 9f0a ldr r7, [sp, #40] @ 0x28 +10004c4e: 2a00 cmp r2, #0 +10004c50: d040 beq.n 10004cd4 +10004c52: 460c mov r4, r1 +10004c54: 461e mov r6, r3 +10004c56: 4615 mov r5, r2 +10004c58: f04f 0b00 mov.w fp, #0 +10004c5c: f8df 9080 ldr.w r9, [pc, #128] @ 10004ce0 +10004c60: f8df 8080 ldr.w r8, [pc, #128] @ 10004ce4 +10004c64: e016 b.n 10004c94 +10004c66: 4620 mov r0, r4 +10004c68: f898 1002 ldrb.w r1, [r8, #2] +10004c6c: f899 a000 ldrb.w sl, [r9] +10004c70: f000 fd3a bl 100056e8 +10004c74: b1d0 cbz r0, 10004cac +10004c76: 4621 mov r1, r4 +10004c78: 4650 mov r0, sl +10004c7a: f7ff fa49 bl 10004110 +10004c7e: b1e0 cbz r0, 10004cba +10004c80: 78a3 ldrb r3, [r4, #2] +10004c82: f10b 0b01 add.w fp, fp, #1 +10004c86: 09da lsrs r2, r3, #7 +10004c88: d120 bne.n 10004ccc +10004c8a: 45ab cmp fp, r5 +10004c8c: 703b strb r3, [r7, #0] +10004c8e: d021 beq.n 10004cd4 +10004c90: 7823 ldrb r3, [r4, #0] +10004c92: 441c add r4, r3 +10004c94: 7863 ldrb r3, [r4, #1] +10004c96: 2b05 cmp r3, #5 +10004c98: d10f bne.n 10004cba +10004c9a: 78e1 ldrb r1, [r4, #3] +10004c9c: f001 0103 and.w r1, r1, #3 +10004ca0: 42b1 cmp r1, r6 +10004ca2: d10a bne.n 10004cba +10004ca4: 78a3 ldrb r3, [r4, #2] +10004ca6: f013 0f70 tst.w r3, #112 @ 0x70 +10004caa: d0dc beq.n 10004c66 +10004cac: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004cb0: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004cb4: 07da lsls r2, r3, #31 +10004cb6: d500 bpl.n 10004cba +10004cb8: be00 bkpt 0x0000 +10004cba: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004cbe: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004cc2: 07db lsls r3, r3, #31 +10004cc4: d409 bmi.n 10004cda +10004cc6: 2000 movs r0, #0 +10004cc8: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004ccc: 9a0b ldr r2, [sp, #44] @ 0x2c +10004cce: 45ab cmp fp, r5 +10004cd0: 7013 strb r3, [r2, #0] +10004cd2: d1dd bne.n 10004c90 +10004cd4: 2001 movs r0, #1 +10004cd6: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004cda: be00 bkpt 0x0000 +10004cdc: e7f3 b.n 10004cc6 +10004cde: bf00 nop +10004ce0: 20001250 .word 0x20001250 +10004ce4: 20001d40 .word 0x20001d40 + +10004ce8 : +10004ce8: 788b ldrb r3, [r1, #2] +10004cea: f013 0f70 tst.w r3, #112 @ 0x70 +10004cee: d008 beq.n 10004d02 +10004cf0: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004cf4: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004cf8: 07da lsls r2, r3, #31 +10004cfa: d500 bpl.n 10004cfe +10004cfc: be00 bkpt 0x0000 +10004cfe: 2000 movs r0, #0 +10004d00: 4770 bx lr +10004d02: b510 push {r4, lr} +10004d04: b082 sub sp, #8 +10004d06: 4608 mov r0, r1 +10004d08: 9101 str r1, [sp, #4] +10004d0a: 490c ldr r1, [pc, #48] @ (10004d3c ) +10004d0c: 4a0c ldr r2, [pc, #48] @ (10004d40 ) +10004d0e: 7889 ldrb r1, [r1, #2] +10004d10: 7814 ldrb r4, [r2, #0] +10004d12: f000 fce9 bl 100056e8 +10004d16: b948 cbnz r0, 10004d2c +10004d18: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004d1c: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004d20: 07db lsls r3, r3, #31 +10004d22: d500 bpl.n 10004d26 +10004d24: be00 bkpt 0x0000 +10004d26: 2000 movs r0, #0 +10004d28: b002 add sp, #8 +10004d2a: bd10 pop {r4, pc} +10004d2c: 4620 mov r0, r4 +10004d2e: 9901 ldr r1, [sp, #4] +10004d30: b002 add sp, #8 +10004d32: e8bd 4010 ldmia.w sp!, {r4, lr} +10004d36: f7ff b9eb b.w 10004110 +10004d3a: bf00 nop +10004d3c: 20001d40 .word 0x20001d40 +10004d40: 20001250 .word 0x20001250 + +10004d44 : +10004d44: 460a mov r2, r1 +10004d46: 4b06 ldr r3, [pc, #24] @ (10004d60 ) +10004d48: 4806 ldr r0, [pc, #24] @ (10004d64 ) +10004d4a: 6819 ldr r1, [r3, #0] +10004d4c: 09d3 lsrs r3, r2, #7 +10004d4e: 3334 adds r3, #52 @ 0x34 +10004d50: f002 027f and.w r2, r2, #127 @ 0x7f +10004d54: eb03 0342 add.w r3, r3, r2, lsl #1 +10004d58: 4418 add r0, r3 +10004d5a: f000 bc79 b.w 10005650 +10004d5e: bf00 nop +10004d60: 20001d94 .word 0x20001d94 +10004d64: 20001d40 .word 0x20001d40 + +10004d68 : +10004d68: 460a mov r2, r1 +10004d6a: 4b06 ldr r3, [pc, #24] @ (10004d84 ) +10004d6c: 4806 ldr r0, [pc, #24] @ (10004d88 ) +10004d6e: 6819 ldr r1, [r3, #0] +10004d70: 09d3 lsrs r3, r2, #7 +10004d72: 3334 adds r3, #52 @ 0x34 +10004d74: f002 027f and.w r2, r2, #127 @ 0x7f +10004d78: eb03 0342 add.w r3, r3, r2, lsl #1 +10004d7c: 4418 add r0, r3 +10004d7e: f000 bc97 b.w 100056b0 +10004d82: bf00 nop +10004d84: 20001d94 .word 0x20001d94 +10004d88: 20001d40 .word 0x20001d40 + +10004d8c : +10004d8c: b510 push {r4, lr} +10004d8e: 4819 ldr r0, [pc, #100] @ (10004df4 ) +10004d90: f001 047f and.w r4, r1, #127 @ 0x7f +10004d94: eb00 0044 add.w r0, r0, r4, lsl #1 +10004d98: eb00 10d1 add.w r0, r0, r1, lsr #7 +10004d9c: f890 c034 ldrb.w ip, [r0, #52] @ 0x34 +10004da0: f01c 0f01 tst.w ip, #1 +10004da4: d008 beq.n 10004db8 +10004da6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004daa: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004dae: 07da lsls r2, r3, #31 +10004db0: d500 bpl.n 10004db4 +10004db2: be00 bkpt 0x0000 +10004db4: 2000 movs r0, #0 +10004db6: bd10 pop {r4, pc} +10004db8: f100 0430 add.w r4, r0, #48 @ 0x30 +10004dbc: f894 c004 ldrb.w ip, [r4, #4] +10004dc0: 480d ldr r0, [pc, #52] @ (10004df8 ) +10004dc2: f04c 0c01 orr.w ip, ip, #1 +10004dc6: 7800 ldrb r0, [r0, #0] +10004dc8: f884 c004 strb.w ip, [r4, #4] +10004dcc: f7ff fa1c bl 10004208 +10004dd0: 2800 cmp r0, #0 +10004dd2: d1f0 bne.n 10004db6 +10004dd4: f04f 21e0 mov.w r1, #3758153728 @ 0xe000e000 +10004dd8: 7922 ldrb r2, [r4, #4] +10004dda: f360 0200 bfi r2, r0, #0, #1 +10004dde: 7122 strb r2, [r4, #4] +10004de0: 7922 ldrb r2, [r4, #4] +10004de2: f360 0282 bfi r2, r0, #2, #1 +10004de6: 7122 strb r2, [r4, #4] +10004de8: f8d1 3df0 ldr.w r3, [r1, #3568] @ 0xdf0 +10004dec: 07db lsls r3, r3, #31 +10004dee: d5e1 bpl.n 10004db4 +10004df0: be00 bkpt 0x0000 +10004df2: e7df b.n 10004db4 +10004df4: 20001d40 .word 0x20001d40 +10004df8: 20001250 .word 0x20001250 + +10004dfc : +10004dfc: f8df c030 ldr.w ip, [pc, #48] @ 10004e30 +10004e00: 2300 movs r3, #0 +10004e02: 4662 mov r2, ip +10004e04: b510 push {r4, lr} +10004e06: 468e mov lr, r1 +10004e08: 4604 mov r4, r0 +10004e0a: 6808 ldr r0, [r1, #0] +10004e0c: 6849 ldr r1, [r1, #4] +10004e0e: f8cc 300c str.w r3, [ip, #12] +10004e12: c203 stmia r2!, {r0, r1} +10004e14: f89e 1000 ldrb.w r1, [lr] +10004e18: 4620 mov r0, r4 +10004e1a: e8bd 4010 ldmia.w sp!, {r4, lr} +10004e1e: f081 01ff eor.w r1, r1, #255 @ 0xff +10004e22: 461a mov r2, r3 +10004e24: f001 0180 and.w r1, r1, #128 @ 0x80 +10004e28: f8cc 3008 str.w r3, [ip, #8] +10004e2c: f7ff bfae b.w 10004d8c +10004e30: 20001d00 .word 0x20001d00 + +10004e34 : +10004e34: f8df c0ac ldr.w ip, [pc, #172] @ 10004ee4 +10004e38: b570 push {r4, r5, r6, lr} +10004e3a: 4615 mov r5, r2 +10004e3c: 4662 mov r2, ip +10004e3e: 2400 movs r4, #0 +10004e40: 468e mov lr, r1 +10004e42: 4606 mov r6, r0 +10004e44: 6808 ldr r0, [r1, #0] +10004e46: 6849 ldr r1, [r1, #4] +10004e48: b082 sub sp, #8 +10004e4a: c203 stmia r2!, {r0, r1} +10004e4c: f8cc 5008 str.w r5, [ip, #8] +10004e50: f8ac 400e strh.w r4, [ip, #14] +10004e54: f8be 2006 ldrh.w r2, [lr, #6] +10004e58: 4293 cmp r3, r2 +10004e5a: bf28 it cs +10004e5c: 4613 movcs r3, r2 +10004e5e: f8ac 300c strh.w r3, [ip, #12] +10004e62: b18a cbz r2, 10004e88 +10004e64: b333 cbz r3, 10004eb4 +10004e66: b1dd cbz r5, 10004ea0 +10004e68: f99c 2000 ldrsb.w r2, [ip] +10004e6c: 2b40 cmp r3, #64 @ 0x40 +10004e6e: bf28 it cs +10004e70: 2340 movcs r3, #64 @ 0x40 +10004e72: 2a00 cmp r2, #0 +10004e74: db29 blt.n 10004eca +10004e76: 4621 mov r1, r4 +10004e78: 4630 mov r0, r6 +10004e7a: 4a19 ldr r2, [pc, #100] @ (10004ee0 ) +10004e7c: f7ff ff86 bl 10004d8c +10004e80: b170 cbz r0, 10004ea0 +10004e82: 2001 movs r0, #1 +10004e84: b002 add sp, #8 +10004e86: bd70 pop {r4, r5, r6, pc} +10004e88: f89e 1000 ldrb.w r1, [lr] +10004e8c: 4613 mov r3, r2 +10004e8e: f081 01ff eor.w r1, r1, #255 @ 0xff +10004e92: 4630 mov r0, r6 +10004e94: f001 0180 and.w r1, r1, #128 @ 0x80 +10004e98: f7ff ff78 bl 10004d8c +10004e9c: 2800 cmp r0, #0 +10004e9e: d1f0 bne.n 10004e82 +10004ea0: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004ea4: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004ea8: 07db lsls r3, r3, #31 +10004eaa: d500 bpl.n 10004eae +10004eac: be00 bkpt 0x0000 +10004eae: 2000 movs r0, #0 +10004eb0: b002 add sp, #8 +10004eb2: bd70 pop {r4, r5, r6, pc} +10004eb4: 461a mov r2, r3 +10004eb6: f89c 1000 ldrb.w r1, [ip] +10004eba: f001 0180 and.w r1, r1, #128 @ 0x80 +10004ebe: 4630 mov r0, r6 +10004ec0: f7ff ff64 bl 10004d8c +10004ec4: 2800 cmp r0, #0 +10004ec6: d1dc bne.n 10004e82 +10004ec8: e7ea b.n 10004ea0 +10004eca: 461a mov r2, r3 +10004ecc: 4629 mov r1, r5 +10004ece: 4804 ldr r0, [pc, #16] @ (10004ee0 ) +10004ed0: 9301 str r3, [sp, #4] +10004ed2: f007 f853 bl 1000bf7c +10004ed6: 2180 movs r1, #128 @ 0x80 +10004ed8: 4a01 ldr r2, [pc, #4] @ (10004ee0 ) +10004eda: 9b01 ldr r3, [sp, #4] +10004edc: e7ef b.n 10004ebe +10004ede: bf00 nop +10004ee0: 20001cc0 .word 0x20001cc0 +10004ee4: 20001d00 .word 0x20001d00 + +10004ee8 : +10004ee8: 2200 movs r2, #0 +10004eea: 4b03 ldr r3, [pc, #12] @ (10004ef8 ) +10004eec: e9c3 2200 strd r2, r2, [r3] +10004ef0: e9c3 2202 strd r2, r2, [r3, #8] +10004ef4: 611a str r2, [r3, #16] +10004ef6: 4770 bx lr +10004ef8: 20001d00 .word 0x20001d00 + +10004efc : +10004efc: 4b01 ldr r3, [pc, #4] @ (10004f04 ) +10004efe: 6118 str r0, [r3, #16] +10004f00: 4770 bx lr +10004f02: bf00 nop +10004f04: 20001d00 .word 0x20001d00 + +10004f08 : +10004f08: 4601 mov r1, r0 +10004f0a: 4a05 ldr r2, [pc, #20] @ (10004f20 ) +10004f0c: f04f 0c00 mov.w ip, #0 +10004f10: 4613 mov r3, r2 +10004f12: 6800 ldr r0, [r0, #0] +10004f14: 6849 ldr r1, [r1, #4] +10004f16: e9c2 cc02 strd ip, ip, [r2, #8] +10004f1a: c303 stmia r3!, {r0, r1} +10004f1c: 4770 bx lr +10004f1e: bf00 nop +10004f20: 20001d00 .word 0x20001d00 + +10004f24 : +10004f24: b530 push {r4, r5, lr} +10004f26: 4c3e ldr r4, [pc, #248] @ (10005020 ) +10004f28: 09c9 lsrs r1, r1, #7 +10004f2a: 7822 ldrb r2, [r4, #0] +10004f2c: 4605 mov r5, r0 +10004f2e: ebb1 1fd2 cmp.w r1, r2, lsr #7 +10004f32: b083 sub sp, #12 +10004f34: d017 beq.n 10004f66 +10004f36: b153 cbz r3, 10004f4e +10004f38: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10004f3c: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10004f40: 07db lsls r3, r3, #31 +10004f42: d402 bmi.n 10004f4a +10004f44: 2000 movs r0, #0 +10004f46: b003 add sp, #12 +10004f48: bd30 pop {r4, r5, pc} +10004f4a: be00 bkpt 0x0000 +10004f4c: e7fa b.n 10004f44 +10004f4e: 4621 mov r1, r4 +10004f50: f7ff f8d0 bl 100040f4 +10004f54: 6923 ldr r3, [r4, #16] +10004f56: b11b cbz r3, 10004f60 +10004f58: 4622 mov r2, r4 +10004f5a: 2103 movs r1, #3 +10004f5c: 4628 mov r0, r5 +10004f5e: 4798 blx r3 +10004f60: 2001 movs r0, #1 +10004f62: b003 add sp, #12 +10004f64: bd30 pop {r4, r5, pc} +10004f66: f994 2000 ldrsb.w r2, [r4] +10004f6a: 2a00 cmp r2, #0 +10004f6c: db08 blt.n 10004f80 +10004f6e: 68a0 ldr r0, [r4, #8] +10004f70: 2800 cmp r0, #0 +10004f72: d0e7 beq.n 10004f44 +10004f74: 461a mov r2, r3 +10004f76: 492b ldr r1, [pc, #172] @ (10005024 ) +10004f78: 9301 str r3, [sp, #4] +10004f7a: f006 ffff bl 1000bf7c +10004f7e: 9b01 ldr r3, [sp, #4] +10004f80: 89e0 ldrh r0, [r4, #14] +10004f82: 68a1 ldr r1, [r4, #8] +10004f84: 88e2 ldrh r2, [r4, #6] +10004f86: 4418 add r0, r3 +10004f88: b280 uxth r0, r0 +10004f8a: 4419 add r1, r3 +10004f8c: 4282 cmp r2, r0 +10004f8e: 81e0 strh r0, [r4, #14] +10004f90: 60a1 str r1, [r4, #8] +10004f92: d016 beq.n 10004fc2 +10004f94: 2b3f cmp r3, #63 @ 0x3f +10004f96: d914 bls.n 10004fc2 +10004f98: 89a2 ldrh r2, [r4, #12] +10004f9a: f994 4000 ldrsb.w r4, [r4] +10004f9e: 1a13 subs r3, r2, r0 +10004fa0: b29b uxth r3, r3 +10004fa2: 2b40 cmp r3, #64 @ 0x40 +10004fa4: bf28 it cs +10004fa6: 2340 movcs r3, #64 @ 0x40 +10004fa8: 2c00 cmp r4, #0 +10004faa: db28 blt.n 10004ffe +10004fac: 4290 cmp r0, r2 +10004fae: f04f 0100 mov.w r1, #0 +10004fb2: d032 beq.n 1000501a +10004fb4: 4a1b ldr r2, [pc, #108] @ (10005024 ) +10004fb6: 4628 mov r0, r5 +10004fb8: f7ff fee8 bl 10004d8c +10004fbc: 2800 cmp r0, #0 +10004fbe: d1cf bne.n 10004f60 +10004fc0: e7ba b.n 10004f38 +10004fc2: 6923 ldr r3, [r4, #16] +10004fc4: b123 cbz r3, 10004fd0 +10004fc6: 2102 movs r1, #2 +10004fc8: 4628 mov r0, r5 +10004fca: 4a15 ldr r2, [pc, #84] @ (10005020 ) +10004fcc: 4798 blx r3 +10004fce: b168 cbz r0, 10004fec +10004fd0: 2300 movs r3, #0 +10004fd2: 7821 ldrb r1, [r4, #0] +10004fd4: 4628 mov r0, r5 +10004fd6: f081 01ff eor.w r1, r1, #255 @ 0xff +10004fda: 461a mov r2, r3 +10004fdc: f001 0180 and.w r1, r1, #128 @ 0x80 +10004fe0: f7ff fed4 bl 10004d8c +10004fe4: 2800 cmp r0, #0 +10004fe6: d0a7 beq.n 10004f38 +10004fe8: 2001 movs r0, #1 +10004fea: e7ba b.n 10004f62 +10004fec: 4601 mov r1, r0 +10004fee: 4628 mov r0, r5 +10004ff0: f7ff f91e bl 10004230 +10004ff4: 2180 movs r1, #128 @ 0x80 +10004ff6: 4628 mov r0, r5 +10004ff8: f7ff f91a bl 10004230 +10004ffc: e7b0 b.n 10004f60 +10004ffe: 4290 cmp r0, r2 +10005000: d008 beq.n 10005014 +10005002: 461a mov r2, r3 +10005004: 4807 ldr r0, [pc, #28] @ (10005024 ) +10005006: 9301 str r3, [sp, #4] +10005008: f006 ffb8 bl 1000bf7c +1000500c: 2180 movs r1, #128 @ 0x80 +1000500e: 4a05 ldr r2, [pc, #20] @ (10005024 ) +10005010: 9b01 ldr r3, [sp, #4] +10005012: e7d0 b.n 10004fb6 +10005014: 2180 movs r1, #128 @ 0x80 +10005016: 2200 movs r2, #0 +10005018: e7cd b.n 10004fb6 +1000501a: 460a mov r2, r1 +1000501c: e7cb b.n 10004fb6 +1000501e: bf00 nop +10005020: 20001d00 .word 0x20001d00 +10005024: 20001cc0 .word 0x20001cc0 + +10005028 <_prep_out_transaction.isra.0>: +10005028: b570 push {r4, r5, r6, lr} +1000502a: b082 sub sp, #8 +1000502c: 4604 mov r4, r0 +1000502e: f7ff f9bf bl 100043b0 +10005032: b908 cbnz r0, 10005038 <_prep_out_transaction.isra.0+0x10> +10005034: b002 add sp, #8 +10005036: bd70 pop {r4, r5, r6, pc} +10005038: f7ff f9c2 bl 100043c0 +1000503c: 4602 mov r2, r0 +1000503e: 2800 cmp r0, #0 +10005040: d1f8 bne.n 10005034 <_prep_out_transaction.isra.0+0xc> +10005042: 23c8 movs r3, #200 @ 0xc8 +10005044: fb04 f303 mul.w r3, r4, r3 +10005048: 4915 ldr r1, [pc, #84] @ (100050a0 <_prep_out_transaction.isra.0+0x78>) +1000504a: 4625 mov r5, r4 +1000504c: 18cc adds r4, r1, r3 +1000504e: 78e0 ldrb r0, [r4, #3] +10005050: 2800 cmp r0, #0 +10005052: d0ef beq.n 10005034 <_prep_out_transaction.isra.0+0xc> +10005054: 3310 adds r3, #16 +10005056: 185e adds r6, r3, r1 +10005058: 4630 mov r0, r6 +1000505a: 9201 str r2, [sp, #4] +1000505c: f000 fbe8 bl 10005830 +10005060: 283f cmp r0, #63 @ 0x3f +10005062: d9e7 bls.n 10005034 <_prep_out_transaction.isra.0+0xc> +10005064: 78e1 ldrb r1, [r4, #3] +10005066: 9801 ldr r0, [sp, #4] +10005068: f7ff fe6c bl 10004d44 +1000506c: 2800 cmp r0, #0 +1000506e: d0e1 beq.n 10005034 <_prep_out_transaction.isra.0+0xc> +10005070: 4630 mov r0, r6 +10005072: f000 fbdd bl 10005830 +10005076: 283f cmp r0, #63 @ 0x3f +10005078: 78e1 ldrb r1, [r4, #3] +1000507a: d90a bls.n 10005092 <_prep_out_transaction.isra.0+0x6a> +1000507c: 2340 movs r3, #64 @ 0x40 +1000507e: f8df c024 ldr.w ip, [pc, #36] @ 100050a4 <_prep_out_transaction.isra.0+0x7c> +10005082: 9801 ldr r0, [sp, #4] +10005084: eb0c 12c5 add.w r2, ip, r5, lsl #7 +10005088: b002 add sp, #8 +1000508a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +1000508e: f7ff be7d b.w 10004d8c +10005092: 9801 ldr r0, [sp, #4] +10005094: b002 add sp, #8 +10005096: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +1000509a: f7ff be65 b.w 10004d68 +1000509e: bf00 nop +100050a0: 20001878 .word 0x20001878 +100050a4: 20001c3c .word 0x20001c3c + +100050a8 : +100050a8: b510 push {r4, lr} +100050aa: 4604 mov r4, r0 +100050ac: f7ff f980 bl 100043b0 +100050b0: b908 cbnz r0, 100050b6 +100050b2: 2000 movs r0, #0 +100050b4: bd10 pop {r4, pc} +100050b6: f7ff f983 bl 100043c0 +100050ba: 2800 cmp r0, #0 +100050bc: d1f9 bne.n 100050b2 +100050be: 22c8 movs r2, #200 @ 0xc8 +100050c0: 4b03 ldr r3, [pc, #12] @ (100050d0 ) +100050c2: fb02 3304 mla r3, r2, r4, r3 +100050c6: 7918 ldrb r0, [r3, #4] +100050c8: f000 0001 and.w r0, r0, #1 +100050cc: bd10 pop {r4, pc} +100050ce: bf00 nop +100050d0: 20001878 .word 0x20001878 + +100050d4 : +100050d4: 22c8 movs r2, #200 @ 0xc8 +100050d6: b508 push {r3, lr} +100050d8: 4b02 ldr r3, [pc, #8] @ (100050e4 ) +100050da: fb02 3000 mla r0, r2, r0, r3 +100050de: f000 fb8d bl 100057fc +100050e2: bd08 pop {r3, pc} +100050e4: 20001888 .word 0x20001888 + +100050e8 : +100050e8: f64f 73ff movw r3, #65535 @ 0xffff +100050ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100050f0: 24c8 movs r4, #200 @ 0xc8 +100050f2: 429a cmp r2, r3 +100050f4: bf28 it cs +100050f6: 461a movcs r2, r3 +100050f8: fb00 f404 mul.w r4, r0, r4 +100050fc: 4d1b ldr r5, [pc, #108] @ (1000516c ) +100050fe: f104 0310 add.w r3, r4, #16 +10005102: b082 sub sp, #8 +10005104: 4680 mov r8, r0 +10005106: b292 uxth r2, r2 +10005108: 1958 adds r0, r3, r5 +1000510a: 195f adds r7, r3, r5 +1000510c: f000 fbf0 bl 100058f0 +10005110: 4606 mov r6, r0 +10005112: f7ff f94d bl 100043b0 +10005116: b918 cbnz r0, 10005120 +10005118: 4630 mov r0, r6 +1000511a: b002 add sp, #8 +1000511c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10005120: f7ff f94e bl 100043c0 +10005124: 2800 cmp r0, #0 +10005126: d1f7 bne.n 10005118 +10005128: 4425 add r5, r4 +1000512a: 78ea ldrb r2, [r5, #3] +1000512c: 2a00 cmp r2, #0 +1000512e: d0f3 beq.n 10005118 +10005130: 9001 str r0, [sp, #4] +10005132: 4638 mov r0, r7 +10005134: f000 fb7c bl 10005830 +10005138: 283f cmp r0, #63 @ 0x3f +1000513a: d9ed bls.n 10005118 +1000513c: 9801 ldr r0, [sp, #4] +1000513e: 78e9 ldrb r1, [r5, #3] +10005140: f7ff fe00 bl 10004d44 +10005144: 2800 cmp r0, #0 +10005146: d0e7 beq.n 10005118 +10005148: 4638 mov r0, r7 +1000514a: f000 fb71 bl 10005830 +1000514e: 283f cmp r0, #63 @ 0x3f +10005150: 78e9 ldrb r1, [r5, #3] +10005152: d907 bls.n 10005164 +10005154: 4a06 ldr r2, [pc, #24] @ (10005170 ) +10005156: 2340 movs r3, #64 @ 0x40 +10005158: 9801 ldr r0, [sp, #4] +1000515a: eb02 12c8 add.w r2, r2, r8, lsl #7 +1000515e: f7ff fe15 bl 10004d8c +10005162: e7d9 b.n 10005118 +10005164: 9801 ldr r0, [sp, #4] +10005166: f7ff fdff bl 10004d68 +1000516a: e7d5 b.n 10005118 +1000516c: 20001878 .word 0x20001878 +10005170: 20001c3c .word 0x20001c3c + +10005174 : +10005174: b5f0 push {r4, r5, r6, r7, lr} +10005176: b083 sub sp, #12 +10005178: 4605 mov r5, r0 +1000517a: f7ff f919 bl 100043b0 +1000517e: b910 cbnz r0, 10005186 +10005180: 2000 movs r0, #0 +10005182: b003 add sp, #12 +10005184: bdf0 pop {r4, r5, r6, r7, pc} +10005186: f7ff f91b bl 100043c0 +1000518a: 4604 mov r4, r0 +1000518c: 2800 cmp r0, #0 +1000518e: d1f7 bne.n 10005180 +10005190: 23c8 movs r3, #200 @ 0xc8 +10005192: fb05 f303 mul.w r3, r5, r3 +10005196: 4a1a ldr r2, [pc, #104] @ (10005200 ) +10005198: f103 0124 add.w r1, r3, #36 @ 0x24 +1000519c: 188f adds r7, r1, r2 +1000519e: 4638 mov r0, r7 +100051a0: 9300 str r3, [sp, #0] +100051a2: f000 fb2b bl 100057fc +100051a6: 2800 cmp r0, #0 +100051a8: d0ea beq.n 10005180 +100051aa: 4a15 ldr r2, [pc, #84] @ (10005200 ) +100051ac: 9b00 ldr r3, [sp, #0] +100051ae: 4620 mov r0, r4 +100051b0: 18d6 adds r6, r2, r3 +100051b2: 78b1 ldrb r1, [r6, #2] +100051b4: f7ff fdc6 bl 10004d44 +100051b8: 2800 cmp r0, #0 +100051ba: d0e1 beq.n 10005180 +100051bc: 4911 ldr r1, [pc, #68] @ (10005204 ) +100051be: 4638 mov r0, r7 +100051c0: eb01 11c5 add.w r1, r1, r5, lsl #7 +100051c4: 2240 movs r2, #64 @ 0x40 +100051c6: 9100 str r1, [sp, #0] +100051c8: f000 fb92 bl 100058f0 +100051cc: f896 c002 ldrb.w ip, [r6, #2] +100051d0: 4603 mov r3, r0 +100051d2: b170 cbz r0, 100051f2 +100051d4: 9001 str r0, [sp, #4] +100051d6: 4661 mov r1, ip +100051d8: 4620 mov r0, r4 +100051da: 9a00 ldr r2, [sp, #0] +100051dc: f7ff fdd6 bl 10004d8c +100051e0: b958 cbnz r0, 100051fa +100051e2: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100051e6: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +100051ea: 07db lsls r3, r3, #31 +100051ec: d5c8 bpl.n 10005180 +100051ee: be00 bkpt 0x0000 +100051f0: e7c6 b.n 10005180 +100051f2: 4661 mov r1, ip +100051f4: f7ff fdb8 bl 10004d68 +100051f8: e7c2 b.n 10005180 +100051fa: 9801 ldr r0, [sp, #4] +100051fc: e7c1 b.n 10005182 +100051fe: bf00 nop +10005200: 20001878 .word 0x20001878 +10005204: 20001c7c .word 0x20001c7c + +10005208 : +10005208: b570 push {r4, r5, r6, lr} +1000520a: 4605 mov r5, r0 +1000520c: f64f 70ff movw r0, #65535 @ 0xffff +10005210: 23c8 movs r3, #200 @ 0xc8 +10005212: 4282 cmp r2, r0 +10005214: bf28 it cs +10005216: 4602 movcs r2, r0 +10005218: 4c09 ldr r4, [pc, #36] @ (10005240 ) +1000521a: b292 uxth r2, r2 +1000521c: fb03 4405 mla r4, r3, r5, r4 +10005220: 4620 mov r0, r4 +10005222: f000 fc29 bl 10005a78 +10005226: 4606 mov r6, r0 +10005228: 4620 mov r0, r4 +1000522a: f000 fae7 bl 100057fc +1000522e: 283f cmp r0, #63 @ 0x3f +10005230: d801 bhi.n 10005236 +10005232: 4630 mov r0, r6 +10005234: bd70 pop {r4, r5, r6, pc} +10005236: 4628 mov r0, r5 +10005238: f7ff ff9c bl 10005174 +1000523c: 4630 mov r0, r6 +1000523e: bd70 pop {r4, r5, r6, pc} +10005240: 2000189c .word 0x2000189c + +10005244 : +10005244: 22c8 movs r2, #200 @ 0xc8 +10005246: b508 push {r3, lr} +10005248: 4b02 ldr r3, [pc, #8] @ (10005254 ) +1000524a: fb02 3000 mla r0, r2, r0, r3 +1000524e: f000 faef bl 10005830 +10005252: bd08 pop {r3, pc} +10005254: 2000189c .word 0x2000189c + +10005258 : +10005258: b570 push {r4, r5, r6, lr} +1000525a: 2400 movs r4, #0 +1000525c: b082 sub sp, #8 +1000525e: 22c8 movs r2, #200 @ 0xc8 +10005260: 2100 movs r1, #0 +10005262: 4818 ldr r0, [pc, #96] @ (100052c4 ) +10005264: f006 fde2 bl 1000be2c +10005268: 23ff movs r3, #255 @ 0xff +1000526a: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +1000526e: 2208 movs r2, #8 +10005270: 4815 ldr r0, [pc, #84] @ (100052c8 ) +10005272: 7004 strb r4, [r0, #0] +10005274: 4813 ldr r0, [pc, #76] @ (100052c4 ) +10005276: 9400 str r4, [sp, #0] +10005278: 4606 mov r6, r0 +1000527a: 7143 strb r3, [r0, #5] +1000527c: 6081 str r1, [r0, #8] +1000527e: 7382 strb r2, [r0, #14] +10005280: f100 0138 add.w r1, r0, #56 @ 0x38 +10005284: 2301 movs r3, #1 +10005286: 2240 movs r2, #64 @ 0x40 +10005288: 3010 adds r0, #16 +1000528a: f000 fa87 bl 1000579c +1000528e: 2301 movs r3, #1 +10005290: 2240 movs r2, #64 @ 0x40 +10005292: f106 0178 add.w r1, r6, #120 @ 0x78 +10005296: 9300 str r3, [sp, #0] +10005298: f106 05b8 add.w r5, r6, #184 @ 0xb8 +1000529c: f106 0024 add.w r0, r6, #36 @ 0x24 +100052a0: f000 fa7c bl 1000579c +100052a4: 4628 mov r0, r5 +100052a6: f7fb fc33 bl 10000b10 +100052aa: f106 00c0 add.w r0, r6, #192 @ 0xc0 +100052ae: f7fb fc2f bl 10000b10 +100052b2: f106 00c0 add.w r0, r6, #192 @ 0xc0 +100052b6: e9c6 4507 strd r4, r5, [r6, #28] +100052ba: e9c6 040c strd r0, r4, [r6, #48] @ 0x30 +100052be: b002 add sp, #8 +100052c0: bd70 pop {r4, r5, r6, pc} +100052c2: bf00 nop +100052c4: 20001878 .word 0x20001878 +100052c8: 20001cbc .word 0x20001cbc + +100052cc : +100052cc: 4b0a ldr r3, [pc, #40] @ (100052f8 ) +100052ce: 6b19 ldr r1, [r3, #48] @ 0x30 +100052d0: 6a1a ldr r2, [r3, #32] +100052d2: b161 cbz r1, 100052ee +100052d4: b13a cbz r2, 100052e6 +100052d6: 2200 movs r2, #0 +100052d8: e9c3 220c strd r2, r2, [r3, #48] @ 0x30 +100052dc: 61da str r2, [r3, #28] +100052de: 2200 movs r2, #0 +100052e0: 621a str r2, [r3, #32] +100052e2: 2001 movs r0, #1 +100052e4: 4770 bx lr +100052e6: 2001 movs r0, #1 +100052e8: e9c3 220c strd r2, r2, [r3, #48] @ 0x30 +100052ec: 4770 bx lr +100052ee: 2a00 cmp r2, #0 +100052f0: d0f7 beq.n 100052e2 +100052f2: 61d9 str r1, [r3, #28] +100052f4: e7f3 b.n 100052de +100052f6: bf00 nop +100052f8: 20001878 .word 0x20001878 + +100052fc : +100052fc: 2200 movs r2, #0 +100052fe: 4910 ldr r1, [pc, #64] @ (10005340 ) +10005300: b508 push {r3, lr} +10005302: 4810 ldr r0, [pc, #64] @ (10005344 ) +10005304: 780b ldrb r3, [r1, #0] +10005306: 6002 str r2, [r0, #0] +10005308: 7102 strb r2, [r0, #4] +1000530a: 07da lsls r2, r3, #31 +1000530c: d507 bpl.n 1000531e +1000530e: 079b lsls r3, r3, #30 +10005310: d50c bpl.n 1000532c +10005312: e8bd 4008 ldmia.w sp!, {r3, lr} +10005316: 2101 movs r1, #1 +10005318: 480b ldr r0, [pc, #44] @ (10005348 ) +1000531a: f000 bc71 b.w 10005c00 +1000531e: 3010 adds r0, #16 +10005320: f000 fc52 bl 10005bc8 +10005324: 4906 ldr r1, [pc, #24] @ (10005340 ) +10005326: 780b ldrb r3, [r1, #0] +10005328: 079b lsls r3, r3, #30 +1000532a: d4f2 bmi.n 10005312 +1000532c: 4806 ldr r0, [pc, #24] @ (10005348 ) +1000532e: f000 fc4b bl 10005bc8 +10005332: e8bd 4008 ldmia.w sp!, {r3, lr} +10005336: 2101 movs r1, #1 +10005338: 4803 ldr r0, [pc, #12] @ (10005348 ) +1000533a: f000 bc61 b.w 10005c00 +1000533e: bf00 nop +10005340: 20001cbc .word 0x20001cbc +10005344: 20001878 .word 0x20001878 +10005348: 2000189c .word 0x2000189c + +1000534c : +1000534c: b570 push {r4, r5, r6, lr} +1000534e: 794b ldrb r3, [r1, #5] +10005350: b084 sub sp, #16 +10005352: 2b02 cmp r3, #2 +10005354: d102 bne.n 1000535c +10005356: 798b ldrb r3, [r1, #6] +10005358: 2b02 cmp r3, #2 +1000535a: d003 beq.n 10005364 +1000535c: 2400 movs r4, #0 +1000535e: 4620 mov r0, r4 +10005360: b004 add sp, #16 +10005362: bd70 pop {r4, r5, r6, pc} +10005364: 4b2b ldr r3, [pc, #172] @ (10005414 ) +10005366: 789b ldrb r3, [r3, #2] +10005368: b13b cbz r3, 1000537a +1000536a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000536e: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10005372: 07db lsls r3, r3, #31 +10005374: d5f2 bpl.n 1000535c +10005376: be00 bkpt 0x0000 +10005378: e7f0 b.n 1000535c +1000537a: 788b ldrb r3, [r1, #2] +1000537c: 4605 mov r5, r0 +1000537e: 4825 ldr r0, [pc, #148] @ (10005414 ) +10005380: 7003 strb r3, [r0, #0] +10005382: 780b ldrb r3, [r1, #0] +10005384: 4419 add r1, r3 +10005386: f891 c001 ldrb.w ip, [r1, #1] +1000538a: f1bc 0f24 cmp.w ip, #36 @ 0x24 +1000538e: bf08 it eq +10005390: 2409 moveq r4, #9 +10005392: d009 beq.n 100053a8 +10005394: e03b b.n 1000540e +10005396: 780b ldrb r3, [r1, #0] +10005398: 4419 add r1, r3 +1000539a: f891 c001 ldrb.w ip, [r1, #1] +1000539e: 4423 add r3, r4 +100053a0: f1bc 0f24 cmp.w ip, #36 @ 0x24 +100053a4: b29c uxth r4, r3 +100053a6: d107 bne.n 100053b8 +100053a8: 4294 cmp r4, r2 +100053aa: d9f4 bls.n 10005396 +100053ac: 2000 movs r0, #0 +100053ae: f7ff fe3b bl 10005028 <_prep_out_transaction.isra.0> +100053b2: 4620 mov r0, r4 +100053b4: b004 add sp, #16 +100053b6: bd70 pop {r4, r5, r6, pc} +100053b8: 4663 mov r3, ip +100053ba: f1bc 0f05 cmp.w ip, #5 +100053be: d016 beq.n 100053ee +100053c0: 2b04 cmp r3, #4 +100053c2: d1f3 bne.n 100053ac +100053c4: 794b ldrb r3, [r1, #5] +100053c6: 2b0a cmp r3, #10 +100053c8: d1f0 bne.n 100053ac +100053ca: 4b13 ldr r3, [pc, #76] @ (10005418 ) +100053cc: 780a ldrb r2, [r1, #0] +100053ce: 9301 str r3, [sp, #4] +100053d0: 3301 adds r3, #1 +100053d2: 9300 str r3, [sp, #0] +100053d4: 2302 movs r3, #2 +100053d6: 4616 mov r6, r2 +100053d8: 4411 add r1, r2 +100053da: 4628 mov r0, r5 +100053dc: 461a mov r2, r3 +100053de: f7ff fc33 bl 10004c48 +100053e2: 2800 cmp r0, #0 +100053e4: d0c1 beq.n 1000536a +100053e6: 340e adds r4, #14 +100053e8: 1933 adds r3, r6, r4 +100053ea: b29c uxth r4, r3 +100053ec: e7de b.n 100053ac +100053ee: 4628 mov r0, r5 +100053f0: 9103 str r1, [sp, #12] +100053f2: f7ff fc79 bl 10004ce8 +100053f6: 9903 ldr r1, [sp, #12] +100053f8: 2800 cmp r0, #0 +100053fa: d0b6 beq.n 1000536a +100053fc: 788b ldrb r3, [r1, #2] +100053fe: 4a05 ldr r2, [pc, #20] @ (10005414 ) +10005400: 7053 strb r3, [r2, #1] +10005402: 780b ldrb r3, [r1, #0] +10005404: 191a adds r2, r3, r4 +10005406: 4419 add r1, r3 +10005408: 784b ldrb r3, [r1, #1] +1000540a: b294 uxth r4, r2 +1000540c: e7d8 b.n 100053c0 +1000540e: 4663 mov r3, ip +10005410: 2409 movs r4, #9 +10005412: e7d2 b.n 100053ba +10005414: 20001878 .word 0x20001878 +10005418: 2000187a .word 0x2000187a + +1000541c : +1000541c: 7813 ldrb r3, [r2, #0] +1000541e: f003 0360 and.w r3, r3, #96 @ 0x60 +10005422: 2b20 cmp r3, #32 +10005424: d10b bne.n 1000543e +10005426: b500 push {lr} +10005428: f8df c0bc ldr.w ip, [pc, #188] @ 100054e8 +1000542c: 8893 ldrh r3, [r2, #4] +1000542e: f89c e000 ldrb.w lr, [ip] +10005432: b083 sub sp, #12 +10005434: 459e cmp lr, r3 +10005436: d004 beq.n 10005442 +10005438: 2000 movs r0, #0 +1000543a: b003 add sp, #12 +1000543c: bd00 pop {pc} +1000543e: 2000 movs r0, #0 +10005440: 4770 bx lr +10005442: 7853 ldrb r3, [r2, #1] +10005444: 3b20 subs r3, #32 +10005446: 2b03 cmp r3, #3 +10005448: d8f6 bhi.n 10005438 +1000544a: e8df f003 tbb [pc, r3] +1000544e: 272c .short 0x272c +10005450: 020d .short 0x020d +10005452: 2901 cmp r1, #1 +10005454: d033 beq.n 100054be +10005456: 2903 cmp r1, #3 +10005458: d122 bne.n 100054a0 +1000545a: 4b1e ldr r3, [pc, #120] @ (100054d4 ) +1000545c: b303 cbz r3, 100054a0 +1000545e: 2000 movs r0, #0 +10005460: 8851 ldrh r1, [r2, #2] +10005462: f3af 8000 nop.w +10005466: e01b b.n 100054a0 +10005468: 2901 cmp r1, #1 +1000546a: d028 beq.n 100054be +1000546c: 2903 cmp r1, #3 +1000546e: d117 bne.n 100054a0 +10005470: 8852 ldrh r2, [r2, #2] +10005472: 4819 ldr r0, [pc, #100] @ (100054d8 ) +10005474: f002 0301 and.w r3, r2, #1 +10005478: f083 0101 eor.w r1, r3, #1 +1000547c: 9301 str r3, [sp, #4] +1000547e: f88c 2004 strb.w r2, [ip, #4] +10005482: 9200 str r2, [sp, #0] +10005484: f000 fbbc bl 10005c00 +10005488: 4914 ldr r1, [pc, #80] @ (100054dc ) +1000548a: b149 cbz r1, 100054a0 +1000548c: 9a00 ldr r2, [sp, #0] +1000548e: 2000 movs r0, #0 +10005490: 9901 ldr r1, [sp, #4] +10005492: f3c2 0240 ubfx r2, r2, #1, #1 +10005496: f3af 8000 nop.w +1000549a: e001 b.n 100054a0 +1000549c: 2901 cmp r1, #1 +1000549e: d012 beq.n 100054c6 +100054a0: 2001 movs r0, #1 +100054a2: b003 add sp, #12 +100054a4: bd00 pop {pc} +100054a6: 2901 cmp r1, #1 +100054a8: d00d beq.n 100054c6 +100054aa: 2903 cmp r1, #3 +100054ac: d1f8 bne.n 100054a0 +100054ae: 4b0c ldr r3, [pc, #48] @ (100054e0 ) +100054b0: 2b00 cmp r3, #0 +100054b2: d0f5 beq.n 100054a0 +100054b4: 2000 movs r0, #0 +100054b6: 490b ldr r1, [pc, #44] @ (100054e4 ) +100054b8: f7fe fda8 bl 1000400c +100054bc: e7f0 b.n 100054a0 +100054be: 4611 mov r1, r2 +100054c0: f7ff fc9c bl 10004dfc +100054c4: e7ec b.n 100054a0 +100054c6: 4611 mov r1, r2 +100054c8: 2307 movs r3, #7 +100054ca: 4a06 ldr r2, [pc, #24] @ (100054e4 ) +100054cc: f7ff fcb2 bl 10004e34 +100054d0: e7e6 b.n 100054a0 +100054d2: bf00 nop +100054d4: 00000000 .word 0x00000000 +100054d8: 2000189c .word 0x2000189c +100054dc: 00000000 .word 0x00000000 +100054e0: 1000400d .word 0x1000400d +100054e4: 20001880 .word 0x20001880 +100054e8: 20001878 .word 0x20001878 + +100054ec : +100054ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100054f0: 4c35 ldr r4, [pc, #212] @ (100055c8 ) +100054f2: 460d mov r5, r1 +100054f4: 78e2 ldrb r2, [r4, #3] +100054f6: 4607 mov r7, r0 +100054f8: 428a cmp r2, r1 +100054fa: 461e mov r6, r3 +100054fc: b082 sub sp, #8 +100054fe: d02f beq.n 10005560 +10005500: 78a3 ldrb r3, [r4, #2] +10005502: 428b cmp r3, r1 +10005504: d009 beq.n 1000551a +10005506: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +1000550a: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +1000550e: 07db lsls r3, r3, #31 +10005510: d424 bmi.n 1000555c +10005512: 2000 movs r0, #0 +10005514: b002 add sp, #8 +10005516: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000551a: 4b2c ldr r3, [pc, #176] @ (100055cc ) +1000551c: b113 cbz r3, 10005524 +1000551e: 2000 movs r0, #0 +10005520: f3af 8000 nop.w +10005524: 2000 movs r0, #0 +10005526: f7ff fe25 bl 10005174 +1000552a: 2800 cmp r0, #0 +1000552c: d147 bne.n 100055be +1000552e: 4828 ldr r0, [pc, #160] @ (100055d0 ) +10005530: f000 f964 bl 100057fc +10005534: 2800 cmp r0, #0 +10005536: d142 bne.n 100055be +10005538: 2e00 cmp r6, #0 +1000553a: d040 beq.n 100055be +1000553c: f016 053f ands.w r5, r6, #63 @ 0x3f +10005540: d13d bne.n 100055be +10005542: 4638 mov r0, r7 +10005544: 78a1 ldrb r1, [r4, #2] +10005546: f7ff fbfd bl 10004d44 +1000554a: 2800 cmp r0, #0 +1000554c: d037 beq.n 100055be +1000554e: 462b mov r3, r5 +10005550: 462a mov r2, r5 +10005552: 4638 mov r0, r7 +10005554: 78a1 ldrb r1, [r4, #2] +10005556: f7ff fc19 bl 10004d8c +1000555a: e030 b.n 100055be +1000555c: be00 bkpt 0x0000 +1000555e: e7d8 b.n 10005512 +10005560: b29a uxth r2, r3 +10005562: 491c ldr r1, [pc, #112] @ (100055d4 ) +10005564: f104 0010 add.w r0, r4, #16 +10005568: f000 fa86 bl 10005a78 +1000556c: 4b1a ldr r3, [pc, #104] @ (100055d8 ) +1000556e: b1d3 cbz r3, 100055a6 +10005570: 7962 ldrb r2, [r4, #5] +10005572: 2aff cmp r2, #255 @ 0xff +10005574: d017 beq.n 100055a6 +10005576: b1b6 cbz r6, 100055a6 +10005578: 4b16 ldr r3, [pc, #88] @ (100055d4 ) +1000557a: eb03 0806 add.w r8, r3, r6 +1000557e: e002 b.n 10005586 +10005580: 4543 cmp r3, r8 +10005582: d010 beq.n 100055a6 +10005584: 7962 ldrb r2, [r4, #5] +10005586: f813 1b01 ldrb.w r1, [r3], #1 +1000558a: 4291 cmp r1, r2 +1000558c: d1f8 bne.n 10005580 +1000558e: 4813 ldr r0, [pc, #76] @ (100055dc ) +10005590: 9301 str r3, [sp, #4] +10005592: f000 f943 bl 1000581c +10005596: 9b01 ldr r3, [sp, #4] +10005598: 2800 cmp r0, #0 +1000559a: d1f1 bne.n 10005580 +1000559c: 7961 ldrb r1, [r4, #5] +1000559e: f3af 8000 nop.w +100055a2: 9b01 ldr r3, [sp, #4] +100055a4: e7ec b.n 10005580 +100055a6: 4b0e ldr r3, [pc, #56] @ (100055e0 ) +100055a8: b11b cbz r3, 100055b2 +100055aa: 480c ldr r0, [pc, #48] @ (100055dc ) +100055ac: f000 f936 bl 1000581c +100055b0: b138 cbz r0, 100055c2 +100055b2: 2000 movs r0, #0 +100055b4: f7ff fd38 bl 10005028 <_prep_out_transaction.isra.0> +100055b8: 78a3 ldrb r3, [r4, #2] +100055ba: 42ab cmp r3, r5 +100055bc: d0ad beq.n 1000551a +100055be: 2001 movs r0, #1 +100055c0: e7a8 b.n 10005514 +100055c2: f3af 8000 nop.w +100055c6: e7f4 b.n 100055b2 +100055c8: 20001878 .word 0x20001878 +100055cc: 00000000 .word 0x00000000 +100055d0: 2000189c .word 0x2000189c +100055d4: 20001c3c .word 0x20001c3c +100055d8: 00000000 .word 0x00000000 +100055dc: 20001888 .word 0x20001888 +100055e0: 00000000 .word 0x00000000 + +100055e4 : +100055e4: b500 push {lr} +100055e6: b083 sub sp, #12 +100055e8: b1d9 cbz r1, 10005622 +100055ea: 2801 cmp r0, #1 +100055ec: d80e bhi.n 1000560c +100055ee: 780b ldrb r3, [r1, #0] +100055f0: b163 cbz r3, 1000560c +100055f2: f8df c058 ldr.w ip, [pc, #88] @ 1000564c +100055f6: 2b01 cmp r3, #1 +100055f8: f80c 3000 strb.w r3, [ip, r0] +100055fc: d002 beq.n 10005604 +100055fe: 2001 movs r0, #1 +10005600: b003 add sp, #12 +10005602: bd00 pop {pc} +10005604: f7fe fee4 bl 100043d0 +10005608: 2800 cmp r0, #0 +1000560a: d1f8 bne.n 100055fe +1000560c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10005610: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10005614: 07db lsls r3, r3, #31 +10005616: d402 bmi.n 1000561e +10005618: 2000 movs r0, #0 +1000561a: b003 add sp, #12 +1000561c: bd00 pop {pc} +1000561e: be00 bkpt 0x0000 +10005620: e7fa b.n 10005618 +10005622: 2201 movs r2, #1 +10005624: 4608 mov r0, r1 +10005626: a901 add r1, sp, #4 +10005628: f8ad 2004 strh.w r2, [sp, #4] +1000562c: f7fe fed0 bl 100043d0 +10005630: 2201 movs r2, #1 +10005632: b938 cbnz r0, 10005644 +10005634: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10005638: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +1000563c: 07da lsls r2, r3, #31 +1000563e: d5ec bpl.n 1000561a +10005640: be00 bkpt 0x0000 +10005642: e7ea b.n 1000561a +10005644: 4b01 ldr r3, [pc, #4] @ (1000564c ) +10005646: 701a strb r2, [r3, #0] +10005648: e7e7 b.n 1000561a +1000564a: bf00 nop +1000564c: 20001d34 .word 0x20001d34 + +10005650 : +10005650: 7803 ldrb r3, [r0, #0] +10005652: f013 0301 ands.w r3, r3, #1 +10005656: d11e bne.n 10005696 +10005658: b530 push {r4, r5, lr} +1000565a: 4602 mov r2, r0 +1000565c: 7800 ldrb r0, [r0, #0] +1000565e: b083 sub sp, #12 +10005660: 4604 mov r4, r0 +10005662: 0740 lsls r0, r0, #29 +10005664: d502 bpl.n 1000566c +10005666: 4618 mov r0, r3 +10005668: b003 add sp, #12 +1000566a: bd30 pop {r4, r5, pc} +1000566c: 4608 mov r0, r1 +1000566e: 460d mov r5, r1 +10005670: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005674: 9201 str r2, [sp, #4] +10005676: f006 fe8b bl 1000c390 <__mutex_enter_timeout_ms_veneer> +1000567a: 9a01 ldr r2, [sp, #4] +1000567c: 7813 ldrb r3, [r2, #0] +1000567e: f013 0301 ands.w r3, r3, #1 +10005682: d10b bne.n 1000569c +10005684: 7811 ldrb r1, [r2, #0] +10005686: 0749 lsls r1, r1, #29 +10005688: d40a bmi.n 100056a0 +1000568a: 7811 ldrb r1, [r2, #0] +1000568c: 2301 movs r3, #1 +1000568e: f041 0104 orr.w r1, r1, #4 +10005692: 7011 strb r1, [r2, #0] +10005694: e004 b.n 100056a0 +10005696: 2300 movs r3, #0 +10005698: 4618 mov r0, r3 +1000569a: 4770 bx lr +1000569c: f3c4 0380 ubfx r3, r4, #2, #1 +100056a0: 4628 mov r0, r5 +100056a2: 9301 str r3, [sp, #4] +100056a4: f006 fe68 bl 1000c378 <__mutex_exit_veneer> +100056a8: 9b01 ldr r3, [sp, #4] +100056aa: 4618 mov r0, r3 +100056ac: b003 add sp, #12 +100056ae: bd30 pop {r4, r5, pc} + +100056b0 : +100056b0: b570 push {r4, r5, r6, lr} +100056b2: 460d mov r5, r1 +100056b4: 4604 mov r4, r0 +100056b6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100056ba: 4628 mov r0, r5 +100056bc: f006 fe68 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +100056c0: 7823 ldrb r3, [r4, #0] +100056c2: f3c3 0680 ubfx r6, r3, #2, #1 +100056c6: 075b lsls r3, r3, #29 +100056c8: d508 bpl.n 100056dc +100056ca: 7823 ldrb r3, [r4, #0] +100056cc: f013 0301 ands.w r3, r3, #1 +100056d0: bf11 iteee ne +100056d2: 2600 movne r6, #0 +100056d4: 7822 ldrbeq r2, [r4, #0] +100056d6: f363 0282 bfieq r2, r3, #2, #1 +100056da: 7022 strbeq r2, [r4, #0] +100056dc: 4628 mov r0, r5 +100056de: f006 fe4b bl 1000c378 <__mutex_exit_veneer> +100056e2: 4630 mov r0, r6 +100056e4: bd70 pop {r4, r5, r6, pc} +100056e6: bf00 nop + +100056e8 : +100056e8: 78c3 ldrb r3, [r0, #3] +100056ea: 8882 ldrh r2, [r0, #4] +100056ec: f003 0003 and.w r0, r3, #3 +100056f0: 2802 cmp r0, #2 +100056f2: f3c2 020a ubfx r2, r2, #0, #11 +100056f6: d015 beq.n 10005724 +100056f8: 2803 cmp r0, #3 +100056fa: d00a beq.n 10005712 +100056fc: 2801 cmp r0, #1 +100056fe: d11c bne.n 1000573a +10005700: 2902 cmp r1, #2 +10005702: f240 33ff movw r3, #1023 @ 0x3ff +10005706: bf08 it eq +10005708: f44f 6380 moveq.w r3, #1024 @ 0x400 +1000570c: 4293 cmp r3, r2 +1000570e: d30d bcc.n 1000572c +10005710: 4770 bx lr +10005712: 2902 cmp r1, #2 +10005714: bf14 ite ne +10005716: 2340 movne r3, #64 @ 0x40 +10005718: f44f 6380 moveq.w r3, #1024 @ 0x400 +1000571c: 4293 cmp r3, r2 +1000571e: d305 bcc.n 1000572c +10005720: 2001 movs r0, #1 +10005722: 4770 bx lr +10005724: 2902 cmp r1, #2 +10005726: d00a beq.n 1000573e +10005728: 2a40 cmp r2, #64 @ 0x40 +1000572a: d9f9 bls.n 10005720 +1000572c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10005730: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +10005734: 07db lsls r3, r3, #31 +10005736: d500 bpl.n 1000573a +10005738: be00 bkpt 0x0000 +1000573a: 2000 movs r0, #0 +1000573c: 4770 bx lr +1000573e: f5b2 7f00 cmp.w r2, #512 @ 0x200 +10005742: d0ed beq.n 10005720 +10005744: e7f2 b.n 1000572c +10005746: bf00 nop + +10005748 : +10005748: 440a add r2, r1 +1000574a: 4291 cmp r1, r2 +1000574c: d225 bcs.n 1000579a +1000574e: f891 c001 ldrb.w ip, [r1, #1] +10005752: f1bc 0f05 cmp.w ip, #5 +10005756: d005 beq.n 10005764 +10005758: f891 c000 ldrb.w ip, [r1] +1000575c: 4461 add r1, ip +1000575e: 428a cmp r2, r1 +10005760: d8f5 bhi.n 1000574e +10005762: 4770 bx lr +10005764: b500 push {lr} +10005766: f891 c002 ldrb.w ip, [r1, #2] +1000576a: f00c 0e7f and.w lr, ip, #127 @ 0x7f +1000576e: eb00 0e4e add.w lr, r0, lr, lsl #1 +10005772: ea4f 1cdc mov.w ip, ip, lsr #7 +10005776: f80e 300c strb.w r3, [lr, ip] +1000577a: f891 c000 ldrb.w ip, [r1] +1000577e: 4461 add r1, ip +10005780: 428a cmp r2, r1 +10005782: d909 bls.n 10005798 +10005784: f891 c001 ldrb.w ip, [r1, #1] +10005788: f1bc 0f05 cmp.w ip, #5 +1000578c: d0eb beq.n 10005766 +1000578e: f891 c000 ldrb.w ip, [r1] +10005792: 4461 add r1, ip +10005794: 428a cmp r2, r1 +10005796: d8f5 bhi.n 10005784 +10005798: bd00 pop {pc} +1000579a: 4770 bx lr + +1000579c : +1000579c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100057a0: f5b2 4f00 cmp.w r2, #32768 @ 0x8000 +100057a4: f89d 5018 ldrb.w r5, [sp, #24] +100057a8: d824 bhi.n 100057f4 +100057aa: 4604 mov r4, r0 +100057ac: 68c0 ldr r0, [r0, #12] +100057ae: 4698 mov r8, r3 +100057b0: 460f mov r7, r1 +100057b2: 4616 mov r6, r2 +100057b4: b118 cbz r0, 100057be +100057b6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100057ba: f006 fde9 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +100057be: 6920 ldr r0, [r4, #16] +100057c0: b118 cbz r0, 100057ca +100057c2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100057c6: f006 fde3 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +100057ca: 2200 movs r2, #0 +100057cc: f3c8 030e ubfx r3, r8, #0, #15 +100057d0: 68e0 ldr r0, [r4, #12] +100057d2: ea43 33c5 orr.w r3, r3, r5, lsl #15 +100057d6: 8162 strh r2, [r4, #10] +100057d8: 6027 str r7, [r4, #0] +100057da: 80a6 strh r6, [r4, #4] +100057dc: 80e3 strh r3, [r4, #6] +100057de: 8122 strh r2, [r4, #8] +100057e0: b108 cbz r0, 100057e6 +100057e2: f006 fdc9 bl 1000c378 <__mutex_exit_veneer> +100057e6: 6920 ldr r0, [r4, #16] +100057e8: b108 cbz r0, 100057ee +100057ea: f006 fdc5 bl 1000c378 <__mutex_exit_veneer> +100057ee: 2001 movs r0, #1 +100057f0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100057f4: 2000 movs r0, #0 +100057f6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100057fa: bf00 nop + +100057fc : +100057fc: 8903 ldrh r3, [r0, #8] +100057fe: 8942 ldrh r2, [r0, #10] +10005800: b29b uxth r3, r3 +10005802: b292 uxth r2, r2 +10005804: 8880 ldrh r0, [r0, #4] +10005806: 4293 cmp r3, r2 +10005808: bf36 itet cc +1000580a: ebc2 0240 rsbcc r2, r2, r0, lsl #1 +1000580e: 1a9b subcs r3, r3, r2 +10005810: 189b addcc r3, r3, r2 +10005812: b29b uxth r3, r3 +10005814: 4298 cmp r0, r3 +10005816: bf28 it cs +10005818: 4618 movcs r0, r3 +1000581a: 4770 bx lr + +1000581c : +1000581c: 8902 ldrh r2, [r0, #8] +1000581e: 8943 ldrh r3, [r0, #10] +10005820: b290 uxth r0, r2 +10005822: b29b uxth r3, r3 +10005824: 1ac0 subs r0, r0, r3 +10005826: fab0 f080 clz r0, r0 +1000582a: 0940 lsrs r0, r0, #5 +1000582c: 4770 bx lr +1000582e: bf00 nop + +10005830 : +10005830: 8903 ldrh r3, [r0, #8] +10005832: 8942 ldrh r2, [r0, #10] +10005834: b29b uxth r3, r3 +10005836: 8880 ldrh r0, [r0, #4] +10005838: b292 uxth r2, r2 +1000583a: 4293 cmp r3, r2 +1000583c: bf36 itet cc +1000583e: ebc2 0240 rsbcc r2, r2, r0, lsl #1 +10005842: 1a9b subcs r3, r3, r2 +10005844: 189b addcc r3, r3, r2 +10005846: b29b uxth r3, r3 +10005848: 4298 cmp r0, r3 +1000584a: bf86 itte hi +1000584c: 1ac0 subhi r0, r0, r3 +1000584e: b280 uxthhi r0, r0 +10005850: 2000 movls r0, #0 +10005852: 4770 bx lr + +10005854 : +10005854: b530 push {r4, r5, lr} +10005856: 4604 mov r4, r0 +10005858: 6900 ldr r0, [r0, #16] +1000585a: 460d mov r5, r1 +1000585c: b083 sub sp, #12 +1000585e: b118 cbz r0, 10005868 +10005860: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005864: f006 fd94 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005868: 8922 ldrh r2, [r4, #8] +1000586a: 8961 ldrh r1, [r4, #10] +1000586c: b292 uxth r2, r2 +1000586e: b289 uxth r1, r1 +10005870: 88a3 ldrh r3, [r4, #4] +10005872: 428a cmp r2, r1 +10005874: bf36 itet cc +10005876: ebc1 0043 rsbcc r0, r1, r3, lsl #1 +1000587a: 1a50 subcs r0, r2, r1 +1000587c: 1880 addcc r0, r0, r2 +1000587e: b280 uxth r0, r0 +10005880: b368 cbz r0, 100058de +10005882: 4283 cmp r3, r0 +10005884: d209 bcs.n 1000589a +10005886: 429a cmp r2, r3 +10005888: bf2c ite cs +1000588a: 1ad2 subcs r2, r2, r3 +1000588c: 18d2 addcc r2, r2, r3 +1000588e: b291 uxth r1, r2 +10005890: 428b cmp r3, r1 +10005892: 8161 strh r1, [r4, #10] +10005894: d803 bhi.n 1000589e +10005896: 1ac9 subs r1, r1, r3 +10005898: b289 uxth r1, r1 +1000589a: 428b cmp r3, r1 +1000589c: d9fb bls.n 10005896 +1000589e: 88e2 ldrh r2, [r4, #6] +100058a0: 6823 ldr r3, [r4, #0] +100058a2: f3c2 020e ubfx r2, r2, #0, #15 +100058a6: fb02 3101 mla r1, r2, r1, r3 +100058aa: 4628 mov r0, r5 +100058ac: f006 fb66 bl 1000bf7c +100058b0: 8962 ldrh r2, [r4, #10] +100058b2: 88a3 ldrh r3, [r4, #4] +100058b4: b292 uxth r2, r2 +100058b6: 1c51 adds r1, r2, #1 +100058b8: b289 uxth r1, r1 +100058ba: 428a cmp r2, r1 +100058bc: f04f 0201 mov.w r2, #1 +100058c0: d910 bls.n 100058e4 +100058c2: 2100 movs r1, #0 +100058c4: fa03 f002 lsl.w r0, r3, r2 +100058c8: 1a09 subs r1, r1, r0 +100058ca: 6920 ldr r0, [r4, #16] +100058cc: 8161 strh r1, [r4, #10] +100058ce: b118 cbz r0, 100058d8 +100058d0: 9201 str r2, [sp, #4] +100058d2: f006 fd51 bl 1000c378 <__mutex_exit_veneer> +100058d6: 9a01 ldr r2, [sp, #4] +100058d8: 4610 mov r0, r2 +100058da: b003 add sp, #12 +100058dc: bd30 pop {r4, r5, pc} +100058de: 4602 mov r2, r0 +100058e0: 8961 ldrh r1, [r4, #10] +100058e2: b289 uxth r1, r1 +100058e4: ebb1 0f43 cmp.w r1, r3, lsl #1 +100058e8: ea4f 0043 mov.w r0, r3, lsl #1 +100058ec: dbed blt.n 100058ca +100058ee: e7eb b.n 100058c8 + +100058f0 : +100058f0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100058f4: 4605 mov r5, r0 +100058f6: 6900 ldr r0, [r0, #16] +100058f8: 4688 mov r8, r1 +100058fa: b082 sub sp, #8 +100058fc: b128 cbz r0, 1000590a +100058fe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005902: 9200 str r2, [sp, #0] +10005904: f006 fd44 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005908: 9a00 ldr r2, [sp, #0] +1000590a: 8929 ldrh r1, [r5, #8] +1000590c: 896b ldrh r3, [r5, #10] +1000590e: b289 uxth r1, r1 +10005910: b29b uxth r3, r3 +10005912: 88ac ldrh r4, [r5, #4] +10005914: 4299 cmp r1, r3 +10005916: bf36 itet cc +10005918: ebc3 0644 rsbcc r6, r3, r4, lsl #1 +1000591c: 1ace subcs r6, r1, r3 +1000591e: 1876 addcc r6, r6, r1 +10005920: b2b6 uxth r6, r6 +10005922: 2e00 cmp r6, #0 +10005924: d04b beq.n 100059be +10005926: 42b4 cmp r4, r6 +10005928: d341 bcc.n 100059ae +1000592a: 42b2 cmp r2, r6 +1000592c: bf28 it cs +1000592e: 4632 movcs r2, r6 +10005930: 429c cmp r4, r3 +10005932: b296 uxth r6, r2 +10005934: d803 bhi.n 1000593e +10005936: 1b1b subs r3, r3, r4 +10005938: b29b uxth r3, r3 +1000593a: 429c cmp r4, r3 +1000593c: d9fb bls.n 10005936 +1000593e: f8b5 c006 ldrh.w ip, [r5, #6] +10005942: 1ae0 subs r0, r4, r3 +10005944: 6829 ldr r1, [r5, #0] +10005946: b280 uxth r0, r0 +10005948: f3cc 020e ubfx r2, ip, #0, #15 +1000594c: 4286 cmp r6, r0 +1000594e: 4617 mov r7, r2 +10005950: fb02 1103 mla r1, r2, r3, r1 +10005954: d925 bls.n 100059a2 +10005956: fb10 f202 smulbb r2, r0, r2 +1000595a: 4640 mov r0, r8 +1000595c: b292 uxth r2, r2 +1000595e: 9301 str r3, [sp, #4] +10005960: 9200 str r2, [sp, #0] +10005962: f006 fb0b bl 1000bf7c +10005966: 9b01 ldr r3, [sp, #4] +10005968: 9a00 ldr r2, [sp, #0] +1000596a: 1b34 subs r4, r6, r4 +1000596c: 4423 add r3, r4 +1000596e: eb08 0002 add.w r0, r8, r2 +10005972: fb13 f207 smulbb r2, r3, r7 +10005976: 6829 ldr r1, [r5, #0] +10005978: b292 uxth r2, r2 +1000597a: f006 faff bl 1000bf7c +1000597e: 896a ldrh r2, [r5, #10] +10005980: 88ac ldrh r4, [r5, #4] +10005982: b292 uxth r2, r2 +10005984: 1993 adds r3, r2, r6 +10005986: b29b uxth r3, r3 +10005988: 429a cmp r2, r3 +1000598a: d91a bls.n 100059c2 +1000598c: 0062 lsls r2, r4, #1 +1000598e: 1a9b subs r3, r3, r2 +10005990: 6928 ldr r0, [r5, #16] +10005992: 816b strh r3, [r5, #10] +10005994: b108 cbz r0, 1000599a +10005996: f006 fcef bl 1000c378 <__mutex_exit_veneer> +1000599a: 4630 mov r0, r6 +1000599c: b002 add sp, #8 +1000599e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100059a2: 4640 mov r0, r8 +100059a4: fb06 f202 mul.w r2, r6, r2 +100059a8: f006 fae8 bl 1000bf7c +100059ac: e7e7 b.n 1000597e +100059ae: 42a1 cmp r1, r4 +100059b0: bf2c ite cs +100059b2: 1b09 subcs r1, r1, r4 +100059b4: 1909 addcc r1, r1, r4 +100059b6: b28b uxth r3, r1 +100059b8: 4626 mov r6, r4 +100059ba: 816b strh r3, [r5, #10] +100059bc: e7b5 b.n 1000592a +100059be: 896b ldrh r3, [r5, #10] +100059c0: b29b uxth r3, r3 +100059c2: ebb3 0f44 cmp.w r3, r4, lsl #1 +100059c6: ea4f 0244 mov.w r2, r4, lsl #1 +100059ca: dbe1 blt.n 10005990 +100059cc: e7df b.n 1000598e +100059ce: bf00 nop + +100059d0 : +100059d0: b570 push {r4, r5, r6, lr} +100059d2: 4604 mov r4, r0 +100059d4: 68c0 ldr r0, [r0, #12] +100059d6: 460e mov r6, r1 +100059d8: b082 sub sp, #8 +100059da: b118 cbz r0, 100059e4 +100059dc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100059e0: f006 fcd6 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +100059e4: 8925 ldrh r5, [r4, #8] +100059e6: 8923 ldrh r3, [r4, #8] +100059e8: 8961 ldrh r1, [r4, #10] +100059ea: b29b uxth r3, r3 +100059ec: b289 uxth r1, r1 +100059ee: 88a2 ldrh r2, [r4, #4] +100059f0: 428b cmp r3, r1 +100059f2: bf36 itet cc +100059f4: ebc1 0142 rsbcc r1, r1, r2, lsl #1 +100059f8: 1a5b subcs r3, r3, r1 +100059fa: 185b addcc r3, r3, r1 +100059fc: b29b uxth r3, r3 +100059fe: 429a cmp r2, r3 +10005a00: b2ad uxth r5, r5 +10005a02: d80b bhi.n 10005a1c +10005a04: 79e1 ldrb r1, [r4, #7] +10005a06: 09c9 lsrs r1, r1, #7 +10005a08: d108 bne.n 10005a1c +10005a0a: 68e0 ldr r0, [r4, #12] +10005a0c: b118 cbz r0, 10005a16 +10005a0e: 9101 str r1, [sp, #4] +10005a10: f006 fcb2 bl 1000c378 <__mutex_exit_veneer> +10005a14: 9901 ldr r1, [sp, #4] +10005a16: 4608 mov r0, r1 +10005a18: b002 add sp, #8 +10005a1a: bd70 pop {r4, r5, r6, pc} +10005a1c: 4295 cmp r5, r2 +10005a1e: bf28 it cs +10005a20: 462b movcs r3, r5 +10005a22: d317 bcc.n 10005a54 +10005a24: 1a9b subs r3, r3, r2 +10005a26: b29b uxth r3, r3 +10005a28: 4293 cmp r3, r2 +10005a2a: d2fb bcs.n 10005a24 +10005a2c: 88e2 ldrh r2, [r4, #6] +10005a2e: 6820 ldr r0, [r4, #0] +10005a30: f3c2 020e ubfx r2, r2, #0, #15 +10005a34: fb02 0003 mla r0, r2, r3, r0 +10005a38: 4631 mov r1, r6 +10005a3a: f006 fa9f bl 1000bf7c +10005a3e: 1c6b adds r3, r5, #1 +10005a40: b29b uxth r3, r3 +10005a42: 429d cmp r5, r3 +10005a44: 88a2 ldrh r2, [r4, #4] +10005a46: d911 bls.n 10005a6c +10005a48: 2300 movs r3, #0 +10005a4a: 0051 lsls r1, r2, #1 +10005a4c: 1a5b subs r3, r3, r1 +10005a4e: 2101 movs r1, #1 +10005a50: 8123 strh r3, [r4, #8] +10005a52: e7da b.n 10005a0a +10005a54: 88e2 ldrh r2, [r4, #6] +10005a56: 6820 ldr r0, [r4, #0] +10005a58: f3c2 020e ubfx r2, r2, #0, #15 +10005a5c: fb05 0002 mla r0, r5, r2, r0 +10005a60: 4631 mov r1, r6 +10005a62: f006 fa8b bl 1000bf7c +10005a66: 3501 adds r5, #1 +10005a68: 88a2 ldrh r2, [r4, #4] +10005a6a: b2ab uxth r3, r5 +10005a6c: ebb3 0f42 cmp.w r3, r2, lsl #1 +10005a70: ea4f 0142 mov.w r1, r2, lsl #1 +10005a74: dbeb blt.n 10005a4e +10005a76: e7e9 b.n 10005a4c + +10005a78 : +10005a78: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10005a7c: 4615 mov r5, r2 +10005a7e: b082 sub sp, #8 +10005a80: 2a00 cmp r2, #0 +10005a82: d04a beq.n 10005b1a +10005a84: 4604 mov r4, r0 +10005a86: 68c0 ldr r0, [r0, #12] +10005a88: 4688 mov r8, r1 +10005a8a: b118 cbz r0, 10005a94 +10005a8c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005a90: f006 fc7e bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005a94: 79e1 ldrb r1, [r4, #7] +10005a96: 8926 ldrh r6, [r4, #8] +10005a98: 8963 ldrh r3, [r4, #10] +10005a9a: 09c9 lsrs r1, r1, #7 +10005a9c: 88a2 ldrh r2, [r4, #4] +10005a9e: b2b6 uxth r6, r6 +10005aa0: b29b uxth r3, r3 +10005aa2: d13e bne.n 10005b22 +10005aa4: 429e cmp r6, r3 +10005aa6: bf36 itet cc +10005aa8: ebc3 0342 rsbcc r3, r3, r2, lsl #1 +10005aac: 1af3 subcs r3, r6, r3 +10005aae: 199b addcc r3, r3, r6 +10005ab0: b29b uxth r3, r3 +10005ab2: 4293 cmp r3, r2 +10005ab4: d253 bcs.n 10005b5e +10005ab6: 1ad3 subs r3, r2, r3 +10005ab8: b29b uxth r3, r3 +10005aba: 42ab cmp r3, r5 +10005abc: bf28 it cs +10005abe: 462b movcs r3, r5 +10005ac0: b29d uxth r5, r3 +10005ac2: 1973 adds r3, r6, r5 +10005ac4: f8b4 c006 ldrh.w ip, [r4, #6] +10005ac8: fa1f f983 uxth.w r9, r3 +10005acc: eba5 0a02 sub.w sl, r5, r2 +10005ad0: 4296 cmp r6, r2 +10005ad2: 4633 mov r3, r6 +10005ad4: d303 bcc.n 10005ade +10005ad6: 1a9b subs r3, r3, r2 +10005ad8: b29b uxth r3, r3 +10005ada: 4293 cmp r3, r2 +10005adc: d2fb bcs.n 10005ad6 +10005ade: 1ad2 subs r2, r2, r3 +10005ae0: b291 uxth r1, r2 +10005ae2: 6820 ldr r0, [r4, #0] +10005ae4: f3cc 020e ubfx r2, ip, #0, #15 +10005ae8: 42a9 cmp r1, r5 +10005aea: 4617 mov r7, r2 +10005aec: fb02 0003 mla r0, r2, r3, r0 +10005af0: d352 bcc.n 10005b98 +10005af2: 4641 mov r1, r8 +10005af4: fb05 f202 mul.w r2, r5, r2 +10005af8: f006 fa40 bl 1000bf7c +10005afc: 88a3 ldrh r3, [r4, #4] +10005afe: 454e cmp r6, r9 +10005b00: ea4f 0243 mov.w r2, r3, lsl #1 +10005b04: d802 bhi.n 10005b0c +10005b06: ebb9 0f43 cmp.w r9, r3, lsl #1 +10005b0a: db01 blt.n 10005b10 +10005b0c: eba9 0902 sub.w r9, r9, r2 +10005b10: 68e0 ldr r0, [r4, #12] +10005b12: 462a mov r2, r5 +10005b14: f8a4 9008 strh.w r9, [r4, #8] +10005b18: bb28 cbnz r0, 10005b66 +10005b1a: 4610 mov r0, r2 +10005b1c: b002 add sp, #8 +10005b1e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10005b22: 4295 cmp r5, r2 +10005b24: d227 bcs.n 10005b76 +10005b26: 429e cmp r6, r3 +10005b28: bf36 itet cc +10005b2a: ebc3 0142 rsbcc r1, r3, r2, lsl #1 +10005b2e: 1af1 subcs r1, r6, r3 +10005b30: 1989 addcc r1, r1, r6 +10005b32: b289 uxth r1, r1 +10005b34: 0050 lsls r0, r2, #1 +10005b36: 4429 add r1, r5 +10005b38: 1aaf subs r7, r5, r2 +10005b3a: 4281 cmp r1, r0 +10005b3c: 46ba mov sl, r7 +10005b3e: db08 blt.n 10005b52 +10005b40: 1899 adds r1, r3, r2 +10005b42: b289 uxth r1, r1 +10005b44: 1b4e subs r6, r1, r5 +10005b46: b2b6 uxth r6, r6 +10005b48: 42b3 cmp r3, r6 +10005b4a: 4689 mov r9, r1 +10005b4c: d938 bls.n 10005bc0 +10005b4e: 1a30 subs r0, r6, r0 +10005b50: b286 uxth r6, r0 +10005b52: 19ab adds r3, r5, r6 +10005b54: fa1f f983 uxth.w r9, r3 +10005b58: f8b4 c006 ldrh.w ip, [r4, #6] +10005b5c: e7b8 b.n 10005ad0 +10005b5e: 2200 movs r2, #0 +10005b60: 68e0 ldr r0, [r4, #12] +10005b62: 2800 cmp r0, #0 +10005b64: d0d9 beq.n 10005b1a +10005b66: 9200 str r2, [sp, #0] +10005b68: f006 fc06 bl 1000c378 <__mutex_exit_veneer> +10005b6c: 9a00 ldr r2, [sp, #0] +10005b6e: 4610 mov r0, r2 +10005b70: b002 add sp, #8 +10005b72: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10005b76: 2a00 cmp r2, #0 +10005b78: d0f2 beq.n 10005b60 +10005b7a: f8b4 c006 ldrh.w ip, [r4, #6] +10005b7e: 1aad subs r5, r5, r2 +10005b80: 1899 adds r1, r3, r2 +10005b82: 461e mov r6, r3 +10005b84: f3cc 030e ubfx r3, ip, #0, #15 +10005b88: fb03 8805 mla r8, r3, r5, r8 +10005b8c: f04f 0a00 mov.w sl, #0 +10005b90: 4615 mov r5, r2 +10005b92: fa1f f981 uxth.w r9, r1 +10005b96: e79b b.n 10005ad0 +10005b98: fb11 f202 smulbb r2, r1, r2 +10005b9c: 4641 mov r1, r8 +10005b9e: b292 uxth r2, r2 +10005ba0: 9301 str r3, [sp, #4] +10005ba2: 9200 str r2, [sp, #0] +10005ba4: f006 f9ea bl 1000bf7c +10005ba8: 9b01 ldr r3, [sp, #4] +10005baa: 9a00 ldr r2, [sp, #0] +10005bac: 4453 add r3, sl +10005bae: fb13 f307 smulbb r3, r3, r7 +10005bb2: eb08 0102 add.w r1, r8, r2 +10005bb6: 6820 ldr r0, [r4, #0] +10005bb8: b29a uxth r2, r3 +10005bba: f006 f9df bl 1000bf7c +10005bbe: e79d b.n 10005afc +10005bc0: 42b0 cmp r0, r6 +10005bc2: ddc4 ble.n 10005b4e +10005bc4: e7c8 b.n 10005b58 +10005bc6: bf00 nop + +10005bc8 : +10005bc8: b510 push {r4, lr} +10005bca: 4604 mov r4, r0 +10005bcc: 68c0 ldr r0, [r0, #12] +10005bce: b118 cbz r0, 10005bd8 +10005bd0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005bd4: f006 fbdc bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005bd8: 6920 ldr r0, [r4, #16] +10005bda: b118 cbz r0, 10005be4 +10005bdc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005be0: f006 fbd6 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005be4: 2300 movs r3, #0 +10005be6: 68e0 ldr r0, [r4, #12] +10005be8: 8163 strh r3, [r4, #10] +10005bea: 8123 strh r3, [r4, #8] +10005bec: b108 cbz r0, 10005bf2 +10005bee: f006 fbc3 bl 1000c378 <__mutex_exit_veneer> +10005bf2: 6920 ldr r0, [r4, #16] +10005bf4: b108 cbz r0, 10005bfa +10005bf6: f006 fbbf bl 1000c378 <__mutex_exit_veneer> +10005bfa: 2001 movs r0, #1 +10005bfc: bd10 pop {r4, pc} +10005bfe: bf00 nop + +10005c00 : +10005c00: b538 push {r3, r4, r5, lr} +10005c02: 4604 mov r4, r0 +10005c04: 68c0 ldr r0, [r0, #12] +10005c06: 460d mov r5, r1 +10005c08: b118 cbz r0, 10005c12 +10005c0a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005c0e: f006 fbbf bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005c12: 6920 ldr r0, [r4, #16] +10005c14: b118 cbz r0, 10005c1e +10005c16: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10005c1a: f006 fbb9 bl 1000c390 <__mutex_enter_timeout_ms_veneer> +10005c1e: 79e3 ldrb r3, [r4, #7] +10005c20: 68e0 ldr r0, [r4, #12] +10005c22: f365 13c7 bfi r3, r5, #7, #1 +10005c26: 71e3 strb r3, [r4, #7] +10005c28: b108 cbz r0, 10005c2e +10005c2a: f006 fba5 bl 1000c378 <__mutex_exit_veneer> +10005c2e: 6920 ldr r0, [r4, #16] +10005c30: b108 cbz r0, 10005c36 +10005c32: f006 fba1 bl 1000c378 <__mutex_exit_veneer> +10005c36: 2001 movs r0, #1 +10005c38: bd38 pop {r3, r4, r5, pc} +10005c3a: bf00 nop + +10005c3c : +10005c3c: b510 push {r4, lr} +10005c3e: 2401 movs r4, #1 +10005c40: 4b06 ldr r3, [pc, #24] @ (10005c5c ) +10005c42: 2019 movs r0, #25 +10005c44: 701c strb r4, [r3, #0] +10005c46: f7fa fc5b bl 10000500 +10005c4a: 2319 movs r3, #25 +10005c4c: ec44 3044 gpioc_bit_oe_put r3, r4 +10005c50: f04f 0200 mov.w r2, #0 +10005c54: ec42 3040 gpioc_bit_out_put r3, r2 +10005c58: 4620 mov r0, r4 +10005c5a: bd10 pop {r4, pc} +10005c5c: 2000253c .word 0x2000253c + +10005c60 : +10005c60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10005c64: 4bb8 ldr r3, [pc, #736] @ (10005f48 ) +10005c66: b0e9 sub sp, #420 @ 0x1a4 +10005c68: 781b ldrb r3, [r3, #0] +10005c6a: b173 cbz r3, 10005c8a +10005c6c: b138 cbz r0, 10005c7e +10005c6e: f101 3cff add.w ip, r1, #4294967295 @ 0xffffffff +10005c72: f5bc 7f00 cmp.w ip, #512 @ 0x200 +10005c76: d202 bcs.n 10005c7e +10005c78: 2500 movs r5, #0 +10005c7a: 462a mov r2, r5 +10005c7c: b959 cbnz r1, 10005c96 +10005c7e: 2301 movs r3, #1 +10005c80: 4618 mov r0, r3 +10005c82: 9306 str r3, [sp, #24] +10005c84: b069 add sp, #420 @ 0x1a4 +10005c86: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10005c8a: 2303 movs r3, #3 +10005c8c: 4618 mov r0, r3 +10005c8e: 9306 str r3, [sp, #24] +10005c90: b069 add sp, #420 @ 0x1a4 +10005c92: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10005c96: 4ead ldr r6, [pc, #692] @ (10005f4c ) +10005c98: 4484 add ip, r0 +10005c9a: 1e47 subs r7, r0, #1 +10005c9c: f1c0 0301 rsb r3, r0, #1 +10005ca0: eb07 0e02 add.w lr, r7, r2 +10005ca4: f81e 4f01 ldrb.w r4, [lr, #1]! +10005ca8: 3c09 subs r4, #9 +10005caa: b2e4 uxtb r4, r4 +10005cac: 2c17 cmp r4, #23 +10005cae: fa26 f804 lsr.w r8, r6, r4 +10005cb2: f200 8161 bhi.w 10005f78 +10005cb6: f018 0f01 tst.w r8, #1 +10005cba: f000 815d beq.w 10005f78 +10005cbe: 3201 adds r2, #1 +10005cc0: 4291 cmp r1, r2 +10005cc2: d1ef bne.n 10005ca4 +10005cc4: 2d0c cmp r5, #12 +10005cc6: d1da bne.n 10005c7e +10005cc8: 4603 mov r3, r0 +10005cca: 2510 movs r5, #16 +10005ccc: 2020 movs r0, #32 +10005cce: 4aa0 ldr r2, [pc, #640] @ (10005f50 ) +10005cd0: ae12 add r6, sp, #72 @ 0x48 +10005cd2: 9201 str r2, [sp, #4] +10005cd4: 9100 str r1, [sp, #0] +10005cd6: 9004 str r0, [sp, #16] +10005cd8: 2201 movs r2, #1 +10005cda: 2140 movs r1, #64 @ 0x40 +10005cdc: 2003 movs r0, #3 +10005cde: 9603 str r6, [sp, #12] +10005ce0: 9502 str r5, [sp, #8] +10005ce2: f002 f937 bl 10007f54 +10005ce6: 2800 cmp r0, #0 +10005ce8: d1cf bne.n 10005c8a +10005cea: e9dd 4e16 ldrd r4, lr, [sp, #88] @ 0x58 +10005cee: e9dd 3c12 ldrd r3, ip, [sp, #72] @ 0x48 +10005cf2: 9a14 ldr r2, [sp, #80] @ 0x50 +10005cf4: f8cd e030 str.w lr, [sp, #48] @ 0x30 +10005cf8: 9208 str r2, [sp, #32] +10005cfa: 9a15 ldr r2, [sp, #84] @ 0x54 +10005cfc: 46a6 mov lr, r4 +10005cfe: 9207 str r2, [sp, #28] +10005d00: 220a movs r2, #10 +10005d02: 9206 str r2, [sp, #24] +10005d04: e9dd 1218 ldrd r1, r2, [sp, #96] @ 0x60 +10005d08: 460c mov r4, r1 +10005d0a: 920d str r2, [sp, #52] @ 0x34 +10005d0c: 4891 ldr r0, [pc, #580] @ (10005f54 ) +10005d0e: 4e92 ldr r6, [pc, #584] @ (10005f58 ) +10005d10: 4f92 ldr r7, [pc, #584] @ (10005f5c ) +10005d12: f8df 8254 ldr.w r8, [pc, #596] @ 10005f68 +10005d16: f8df 9254 ldr.w r9, [pc, #596] @ 10005f6c +10005d1a: f8df a254 ldr.w sl, [pc, #596] @ 10005f70 +10005d1e: f8df b254 ldr.w fp, [pc, #596] @ 10005f74 +10005d22: 4a8f ldr r2, [pc, #572] @ (10005f60 ) +10005d24: 9907 ldr r1, [sp, #28] +10005d26: 44e2 add sl, ip +10005d28: 4488 add r8, r1 +10005d2a: 990c ldr r1, [sp, #48] @ 0x30 +10005d2c: ea8a 0606 eor.w r6, sl, r6 +10005d30: ea88 0202 eor.w r2, r8, r2 +10005d34: 9d08 ldr r5, [sp, #32] +10005d36: 920a str r2, [sp, #40] @ 0x28 +10005d38: eb01 4136 add.w r1, r1, r6, ror #16 +10005d3c: 9108 str r1, [sp, #32] +10005d3e: 9a0d ldr r2, [sp, #52] @ 0x34 +10005d40: 990a ldr r1, [sp, #40] @ 0x28 +10005d42: 44a9 add r9, r5 +10005d44: eb02 4231 add.w r2, r2, r1, ror #16 +10005d48: ea80 0009 eor.w r0, r0, r9 +10005d4c: 9908 ldr r1, [sp, #32] +10005d4e: 449b add fp, r3 +10005d50: eb04 4430 add.w r4, r4, r0, ror #16 +10005d54: ea87 070b eor.w r7, r7, fp +10005d58: ea8c 0c01 eor.w ip, ip, r1 +10005d5c: ea84 0105 eor.w r1, r4, r5 +10005d60: 9109 str r1, [sp, #36] @ 0x24 +10005d62: 9d07 ldr r5, [sp, #28] +10005d64: eb0e 4e37 add.w lr, lr, r7, ror #16 +10005d68: eb0a 5a3c add.w sl, sl, ip, ror #20 +10005d6c: eb09 5931 add.w r9, r9, r1, ror #20 +10005d70: 9908 ldr r1, [sp, #32] +10005d72: ea83 030e eor.w r3, r3, lr +10005d76: ea8a 4636 eor.w r6, sl, r6, ror #16 +10005d7a: 9207 str r2, [sp, #28] +10005d7c: 4055 eors r5, r2 +10005d7e: eb0b 5b33 add.w fp, fp, r3, ror #20 +10005d82: 9a0a ldr r2, [sp, #40] @ 0x28 +10005d84: eb01 6136 add.w r1, r1, r6, ror #24 +10005d88: 9108 str r1, [sp, #32] +10005d8a: eb08 5835 add.w r8, r8, r5, ror #20 +10005d8e: 9907 ldr r1, [sp, #28] +10005d90: ea8b 4737 eor.w r7, fp, r7, ror #16 +10005d94: ea88 4232 eor.w r2, r8, r2, ror #16 +10005d98: eb0e 6e37 add.w lr, lr, r7, ror #24 +10005d9c: 9207 str r2, [sp, #28] +10005d9e: eb01 6132 add.w r1, r1, r2, ror #24 +10005da2: ea8e 5233 eor.w r2, lr, r3, ror #20 +10005da6: 9b08 ldr r3, [sp, #32] +10005da8: ea89 4030 eor.w r0, r9, r0, ror #16 +10005dac: ea83 5c3c eor.w ip, r3, ip, ror #20 +10005db0: 9b09 ldr r3, [sp, #36] @ 0x24 +10005db2: eb04 6430 add.w r4, r4, r0, ror #24 +10005db6: ea84 5333 eor.w r3, r4, r3, ror #20 +10005dba: ea81 5535 eor.w r5, r1, r5, ror #20 +10005dbe: 9209 str r2, [sp, #36] @ 0x24 +10005dc0: eb08 6872 add.w r8, r8, r2, ror #25 +10005dc4: 9a07 ldr r2, [sp, #28] +10005dc6: eb0b 6b7c add.w fp, fp, ip, ror #25 +10005dca: eb0a 6a73 add.w sl, sl, r3, ror #25 +10005dce: eb09 6975 add.w r9, r9, r5, ror #25 +10005dd2: ea8b 6232 eor.w r2, fp, r2, ror #24 +10005dd6: ea8a 6737 eor.w r7, sl, r7, ror #24 +10005dda: ea89 6636 eor.w r6, r9, r6, ror #24 +10005dde: 920a str r2, [sp, #40] @ 0x28 +10005de0: eb04 4432 add.w r4, r4, r2, ror #16 +10005de4: eb0e 4e36 add.w lr, lr, r6, ror #16 +10005de8: eb01 4237 add.w r2, r1, r7, ror #16 +10005dec: 9908 ldr r1, [sp, #32] +10005dee: ea88 6030 eor.w r0, r8, r0, ror #24 +10005df2: 9207 str r2, [sp, #28] +10005df4: ea82 6273 eor.w r2, r2, r3, ror #25 +10005df8: ea8e 6375 eor.w r3, lr, r5, ror #25 +10005dfc: 930b str r3, [sp, #44] @ 0x2c +10005dfe: eb01 4330 add.w r3, r1, r0, ror #16 +10005e02: 9909 ldr r1, [sp, #36] @ 0x24 +10005e04: 9d07 ldr r5, [sp, #28] +10005e06: ea83 6171 eor.w r1, r3, r1, ror #25 +10005e0a: eb0a 5a32 add.w sl, sl, r2, ror #20 +10005e0e: eb08 5831 add.w r8, r8, r1, ror #20 +10005e12: ea8a 4737 eor.w r7, sl, r7, ror #16 +10005e16: eb05 6537 add.w r5, r5, r7, ror #24 +10005e1a: ea88 4030 eor.w r0, r8, r0, ror #16 +10005e1e: eb03 6330 add.w r3, r3, r0, ror #24 +10005e22: 9009 str r0, [sp, #36] @ 0x24 +10005e24: 4628 mov r0, r5 +10005e26: 9208 str r2, [sp, #32] +10005e28: 9a0b ldr r2, [sp, #44] @ 0x2c +10005e2a: 930c str r3, [sp, #48] @ 0x30 +10005e2c: eb09 5932 add.w r9, r9, r2, ror #20 +10005e30: 950d str r5, [sp, #52] @ 0x34 +10005e32: 9a0a ldr r2, [sp, #40] @ 0x28 +10005e34: 9d08 ldr r5, [sp, #32] +10005e36: ea89 4636 eor.w r6, r9, r6, ror #16 +10005e3a: ea80 5035 eor.w r0, r0, r5, ror #20 +10005e3e: 9d0b ldr r5, [sp, #44] @ 0x2c +10005e40: ea84 6c7c eor.w ip, r4, ip, ror #25 +10005e44: eb0e 6e36 add.w lr, lr, r6, ror #24 +10005e48: eb0b 5b3c add.w fp, fp, ip, ror #20 +10005e4c: ea83 5331 eor.w r3, r3, r1, ror #20 +10005e50: ea4f 6070 mov.w r0, r0, ror #25 +10005e54: 9906 ldr r1, [sp, #24] +10005e56: ea8e 5535 eor.w r5, lr, r5, ror #20 +10005e5a: ea8b 4232 eor.w r2, fp, r2, ror #16 +10005e5e: 9008 str r0, [sp, #32] +10005e60: ea4f 6075 mov.w r0, r5, ror #25 +10005e64: eb04 6432 add.w r4, r4, r2, ror #24 +10005e68: 3901 subs r1, #1 +10005e6a: 9007 str r0, [sp, #28] +10005e6c: 9809 ldr r0, [sp, #36] @ 0x24 +10005e6e: ea84 5c3c eor.w ip, r4, ip, ror #20 +10005e72: f011 01ff ands.w r1, r1, #255 @ 0xff +10005e76: ea4f 6232 mov.w r2, r2, ror #24 +10005e7a: ea4f 6c7c mov.w ip, ip, ror #25 +10005e7e: ea4f 6737 mov.w r7, r7, ror #24 +10005e82: ea4f 6636 mov.w r6, r6, ror #24 +10005e86: ea4f 6030 mov.w r0, r0, ror #24 +10005e8a: ea4f 6373 mov.w r3, r3, ror #25 +10005e8e: 9106 str r1, [sp, #24] +10005e90: f47f af48 bne.w 10005d24 +10005e94: 460c mov r4, r1 +10005e96: 460b mov r3, r1 +10005e98: ea4f 2e12 mov.w lr, r2, lsr #8 +10005e9c: 9208 str r2, [sp, #32] +10005e9e: 0c15 lsrs r5, r2, #16 +10005ea0: f367 0407 bfi r4, r7, #0, #8 +10005ea4: 0a3a lsrs r2, r7, #8 +10005ea6: f362 240f bfi r4, r2, #8, #8 +10005eaa: 461a mov r2, r3 +10005eac: 9109 str r1, [sp, #36] @ 0x24 +10005eae: f366 0207 bfi r2, r6, #0, #8 +10005eb2: 0c39 lsrs r1, r7, #16 +10005eb4: f361 4417 bfi r4, r1, #16, #8 +10005eb8: 4611 mov r1, r2 +10005eba: 0a32 lsrs r2, r6, #8 +10005ebc: f362 210f bfi r1, r2, #8, #8 +10005ec0: 460a mov r2, r1 +10005ec2: 0c31 lsrs r1, r6, #16 +10005ec4: f361 4217 bfi r2, r1, #16, #8 +10005ec8: 4619 mov r1, r3 +10005eca: 9207 str r2, [sp, #28] +10005ecc: f360 0107 bfi r1, r0, #0, #8 +10005ed0: 0a02 lsrs r2, r0, #8 +10005ed2: f362 210f bfi r1, r2, #8, #8 +10005ed6: 9a08 ldr r2, [sp, #32] +10005ed8: ea4f 4c10 mov.w ip, r0, lsr #16 +10005edc: f362 0307 bfi r3, r2, #0, #8 +10005ee0: f36c 4117 bfi r1, ip, #16, #8 +10005ee4: f36e 230f bfi r3, lr, #8, #8 +10005ee8: 0e00 lsrs r0, r0, #24 +10005eea: f360 611f bfi r1, r0, #24, #8 +10005eee: f365 4317 bfi r3, r5, #16, #8 +10005ef2: 0e10 lsrs r0, r2, #24 +10005ef4: f360 631f bfi r3, r0, #24, #8 +10005ef8: 4a1a ldr r2, [pc, #104] @ (10005f64 ) +10005efa: 0e3d lsrs r5, r7, #24 +10005efc: 9f07 ldr r7, [sp, #28] +10005efe: e9cd 1320 strd r1, r3, [sp, #128] @ 0x80 +10005f02: e892 0003 ldmia.w r2, {r0, r1} +10005f06: 9b06 ldr r3, [sp, #24] +10005f08: 0e36 lsrs r6, r6, #24 +10005f0a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10005f0e: f365 641f bfi r4, r5, #24, #8 +10005f12: a82e add r0, sp, #184 @ 0xb8 +10005f14: f366 671f bfi r7, r6, #24, #8 +10005f18: e9cd ba1a strd fp, sl, [sp, #104] @ 0x68 +10005f1c: e9cd 981c strd r9, r8, [sp, #112] @ 0x70 +10005f20: e9cd 471e strd r4, r7, [sp, #120] @ 0x78 +10005f24: 930f str r3, [sp, #60] @ 0x3c +10005f26: f000 f877 bl 10006018 +10005f2a: a91a add r1, sp, #104 @ 0x68 +10005f2c: a82e add r0, sp, #184 @ 0xb8 +10005f2e: f000 f89d bl 1000606c +10005f32: 2800 cmp r0, #0 +10005f34: d047 beq.n 10005fc6 +10005f36: a82e add r0, sp, #184 @ 0xb8 +10005f38: f000 f882 bl 10006040 +10005f3c: 2302 movs r3, #2 +10005f3e: 4618 mov r0, r3 +10005f40: 9306 str r3, [sp, #24] +10005f42: b069 add sp, #420 @ 0x1a4 +10005f44: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10005f48: 2000253c .word 0x2000253c +10005f4c: 00800013 .word 0x00800013 +10005f50: 1000ceec .word 0x1000ceec +10005f54: dd66f0e7 .word 0xdd66f0e7 +10005f58: 047c9e77 .word 0x047c9e77 +10005f5c: 0d79ef1c .word 0x0d79ef1c +10005f60: 7080d090 .word 0x7080d090 +10005f64: 1000cee4 .word 0x1000cee4 +10005f68: 6b206574 .word 0x6b206574 +10005f6c: 79622d32 .word 0x79622d32 +10005f70: 3320646e .word 0x3320646e +10005f74: 61707865 .word 0x61707865 +10005f78: 4291 cmp r1, r2 +10005f7a: f43f aea3 beq.w 10005cc4 +10005f7e: f105 0501 add.w r5, r5, #1 +10005f82: b2ed uxtb r5, r5 +10005f84: f67f ae9e bls.w 10005cc4 +10005f88: 443a add r2, r7 +10005f8a: f892 e001 ldrb.w lr, [r2, #1] +10005f8e: f102 0801 add.w r8, r2, #1 +10005f92: f1ae 0409 sub.w r4, lr, #9 +10005f96: b2e4 uxtb r4, r4 +10005f98: 2c17 cmp r4, #23 +10005f9a: d809 bhi.n 10005fb0 +10005f9c: fa26 f404 lsr.w r4, r6, r4 +10005fa0: 07e4 lsls r4, r4, #31 +10005fa2: f57f ae6c bpl.w 10005c7e +10005fa6: 441a add r2, r3 +10005fa8: 4291 cmp r1, r2 +10005faa: f63f ae79 bhi.w 10005ca0 +10005fae: e689 b.n 10005cc4 +10005fb0: f1ae 0e61 sub.w lr, lr, #97 @ 0x61 +10005fb4: f1be 0f19 cmp.w lr, #25 +10005fb8: f63f ae61 bhi.w 10005c7e +10005fbc: 45c4 cmp ip, r8 +10005fbe: f43f ae81 beq.w 10005cc4 +10005fc2: 4642 mov r2, r8 +10005fc4: e7e1 b.n 10005f8a +10005fc6: 4b13 ldr r3, [pc, #76] @ (10006014 ) +10005fc8: ac22 add r4, sp, #136 @ 0x88 +10005fca: e9cd 3402 strd r3, r4, [sp, #8] +10005fce: 3330 adds r3, #48 @ 0x30 +10005fd0: 9301 str r3, [sp, #4] +10005fd2: 9b06 ldr r3, [sp, #24] +10005fd4: 2130 movs r1, #48 @ 0x30 +10005fd6: aa0f add r2, sp, #60 @ 0x3c +10005fd8: 9300 str r3, [sp, #0] +10005fda: a82e add r0, sp, #184 @ 0xb8 +10005fdc: f000 f9b2 bl 10006344 +10005fe0: 4605 mov r5, r0 +10005fe2: a82e add r0, sp, #184 @ 0xb8 +10005fe4: f000 f82c bl 10006040 +10005fe8: 2d00 cmp r5, #0 +10005fea: d1a7 bne.n 10005f3c +10005fec: 7823 ldrb r3, [r4, #0] +10005fee: 2219 movs r2, #25 +10005ff0: 1b5b subs r3, r3, r5 +10005ff2: bf18 it ne +10005ff4: 2301 movne r3, #1 +10005ff6: ec43 2040 gpioc_bit_out_put r2, r3 +10005ffa: f10d 058f add.w r5, sp, #143 @ 0x8f +10005ffe: f814 0f01 ldrb.w r0, [r4, #1]! +10006002: f7fd faf1 bl 100035e8 +10006006: 42a5 cmp r5, r4 +10006008: d1f9 bne.n 10005ffe +1000600a: 9806 ldr r0, [sp, #24] +1000600c: b069 add sp, #420 @ 0x1a4 +1000600e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10006012: bf00 nop +10006014: 1000ce94 .word 0x1000ce94 + +10006018 : +10006018: b510 push {r4, lr} +1000601a: 4604 mov r4, r0 +1000601c: f000 fe22 bl 10006c64 +10006020: f104 0084 add.w r0, r4, #132 @ 0x84 +10006024: f001 f9ae bl 10007384 +10006028: 2300 movs r3, #0 +1000602a: 2000 movs r0, #0 +1000602c: 2100 movs r1, #0 +1000602e: f884 30e4 strb.w r3, [r4, #228] @ 0xe4 +10006032: e9c4 0134 strd r0, r1, [r4, #208] @ 0xd0 +10006036: e9c4 0136 strd r0, r1, [r4, #216] @ 0xd8 +1000603a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +1000603e: bd10 pop {r4, pc} + +10006040 : +10006040: b198 cbz r0, 1000606a +10006042: b510 push {r4, lr} +10006044: 4604 mov r4, r0 +10006046: f000 fe1b bl 10006c80 +1000604a: f104 0084 add.w r0, r4, #132 @ 0x84 +1000604e: f001 f99d bl 1000738c +10006052: 2300 movs r3, #0 +10006054: 2000 movs r0, #0 +10006056: 2100 movs r1, #0 +10006058: f884 30e4 strb.w r3, [r4, #228] @ 0xe4 +1000605c: e9c4 0134 strd r0, r1, [r4, #208] @ 0xd0 +10006060: e9c4 0136 strd r0, r1, [r4, #216] @ 0xd8 +10006064: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +10006068: bd10 pop {r4, pc} +1000606a: 4770 bx lr + +1000606c : +1000606c: f000 be0e b.w 10006c8c + +10006070 : +10006070: b5f0 push {r4, r5, r6, r7, lr} +10006072: 4617 mov r7, r2 +10006074: b091 sub sp, #68 @ 0x44 +10006076: 2200 movs r2, #0 +10006078: 4606 mov r6, r0 +1000607a: f000 fe2f bl 10006cdc +1000607e: 466d mov r5, sp +10006080: 4604 mov r4, r0 +10006082: b130 cbz r0, 10006092 +10006084: 4628 mov r0, r5 +10006086: 2140 movs r1, #64 @ 0x40 +10006088: f000 fc9a bl 100069c0 +1000608c: 4620 mov r0, r4 +1000608e: b011 add sp, #68 @ 0x44 +10006090: bdf0 pop {r4, r5, r6, r7, pc} +10006092: 4601 mov r1, r0 +10006094: 2240 movs r2, #64 @ 0x40 +10006096: 4668 mov r0, sp +10006098: f005 fec8 bl 1000be2c +1000609c: 466b mov r3, sp +1000609e: 466a mov r2, sp +100060a0: 2140 movs r1, #64 @ 0x40 +100060a2: 4630 mov r0, r6 +100060a4: f000 fe2e bl 10006d04 +100060a8: 4604 mov r4, r0 +100060aa: 2800 cmp r0, #0 +100060ac: d1ea bne.n 10006084 +100060ae: 4669 mov r1, sp +100060b0: f106 0084 add.w r0, r6, #132 @ 0x84 +100060b4: f001 f970 bl 10007398 +100060b8: 4604 mov r4, r0 +100060ba: 2800 cmp r0, #0 +100060bc: d1e2 bne.n 10006084 +100060be: 2200 movs r2, #0 +100060c0: 2300 movs r3, #0 +100060c2: 2101 movs r1, #1 +100060c4: e9c6 2334 strd r2, r3, [r6, #208] @ 0xd0 +100060c8: e9c6 2336 strd r2, r3, [r6, #216] @ 0xd8 +100060cc: f886 70e4 strb.w r7, [r6, #228] @ 0xe4 +100060d0: f8c6 10e0 str.w r1, [r6, #224] @ 0xe0 +100060d4: e7d6 b.n 10006084 +100060d6: bf00 nop + +100060d8 : +100060d8: 4603 mov r3, r0 +100060da: f8d0 00e0 ldr.w r0, [r0, #224] @ 0xe0 +100060de: 2801 cmp r0, #1 +100060e0: d110 bne.n 10006104 +100060e2: b410 push {r4} +100060e4: f8d3 00d0 ldr.w r0, [r3, #208] @ 0xd0 +100060e8: f8d3 40d4 ldr.w r4, [r3, #212] @ 0xd4 +100060ec: 1880 adds r0, r0, r2 +100060ee: f144 0c00 adc.w ip, r4, #0 +100060f2: f8c3 00d0 str.w r0, [r3, #208] @ 0xd0 +100060f6: f8c3 c0d4 str.w ip, [r3, #212] @ 0xd4 +100060fa: f103 0084 add.w r0, r3, #132 @ 0x84 +100060fe: bc10 pop {r4} +10006100: f001 b974 b.w 100073ec +10006104: f06f 0053 mvn.w r0, #83 @ 0x53 +10006108: 4770 bx lr +1000610a: bf00 nop + +1000610c : +1000610c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10006110: f8d0 c0e0 ldr.w ip, [r0, #224] @ 0xe0 +10006114: b084 sub sp, #16 +10006116: f10c 34ff add.w r4, ip, #4294967295 @ 0xffffffff +1000611a: 2c01 cmp r4, #1 +1000611c: d84d bhi.n 100061ba +1000611e: f1bc 0f01 cmp.w ip, #1 +10006122: 4698 mov r8, r3 +10006124: 4617 mov r7, r2 +10006126: 460d mov r5, r1 +10006128: 4604 mov r4, r0 +1000612a: d02d beq.n 10006188 +1000612c: f8d4 00d8 ldr.w r0, [r4, #216] @ 0xd8 +10006130: f8d4 30dc ldr.w r3, [r4, #220] @ 0xdc +10006134: 1940 adds r0, r0, r5 +10006136: f894 20e4 ldrb.w r2, [r4, #228] @ 0xe4 +1000613a: f143 0300 adc.w r3, r3, #0 +1000613e: f8c4 00d8 str.w r0, [r4, #216] @ 0xd8 +10006142: f8c4 30dc str.w r3, [r4, #220] @ 0xdc +10006146: b97a cbnz r2, 10006168 +10006148: 4643 mov r3, r8 +1000614a: 463a mov r2, r7 +1000614c: 4629 mov r1, r5 +1000614e: 4620 mov r0, r4 +10006150: f000 fdd8 bl 10006d04 +10006154: bb70 cbnz r0, 100061b4 +10006156: 462a mov r2, r5 +10006158: 4641 mov r1, r8 +1000615a: f104 0084 add.w r0, r4, #132 @ 0x84 +1000615e: b004 add sp, #16 +10006160: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10006164: f001 b942 b.w 100073ec +10006168: 462a mov r2, r5 +1000616a: 4639 mov r1, r7 +1000616c: f104 0084 add.w r0, r4, #132 @ 0x84 +10006170: f001 f93c bl 100073ec +10006174: b9f0 cbnz r0, 100061b4 +10006176: 4643 mov r3, r8 +10006178: 463a mov r2, r7 +1000617a: 4629 mov r1, r5 +1000617c: 4620 mov r0, r4 +1000617e: b004 add sp, #16 +10006180: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10006184: f000 bdbe b.w 10006d04 +10006188: 2302 movs r3, #2 +1000618a: f8d0 20d0 ldr.w r2, [r0, #208] @ 0xd0 +1000618e: f8c0 30e0 str.w r3, [r0, #224] @ 0xe0 +10006192: f012 020f ands.w r2, r2, #15 +10006196: d0c9 beq.n 1000612c +10006198: 2300 movs r3, #0 +1000619a: 4669 mov r1, sp +1000619c: f1c2 0210 rsb r2, r2, #16 +100061a0: 3084 adds r0, #132 @ 0x84 +100061a2: 9302 str r3, [sp, #8] +100061a4: 9300 str r3, [sp, #0] +100061a6: f8cd 300b str.w r3, [sp, #11] +100061aa: 9301 str r3, [sp, #4] +100061ac: f001 f91e bl 100073ec +100061b0: 2800 cmp r0, #0 +100061b2: d0bb beq.n 1000612c +100061b4: b004 add sp, #16 +100061b6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100061ba: f06f 0053 mvn.w r0, #83 @ 0x53 +100061be: e7f9 b.n 100061b4 + +100061c0 : +100061c0: f8d0 20e0 ldr.w r2, [r0, #224] @ 0xe0 +100061c4: 2a00 cmp r2, #0 +100061c6: d051 beq.n 1000626c +100061c8: b530 push {r4, r5, lr} +100061ca: 2a01 cmp r2, #1 +100061cc: 460d mov r5, r1 +100061ce: 4603 mov r3, r0 +100061d0: b087 sub sp, #28 +100061d2: d01c beq.n 1000620e +100061d4: e9d0 ce36 ldrd ip, lr, [r0, #216] @ 0xd8 +100061d8: 2a02 cmp r2, #2 +100061da: d03e beq.n 1000625a +100061dc: e9d3 0234 ldrd r0, r2, [r3, #208] @ 0xd0 +100061e0: a902 add r1, sp, #8 +100061e2: f103 0484 add.w r4, r3, #132 @ 0x84 +100061e6: e9cd 0202 strd r0, r2, [sp, #8] +100061ea: 2003 movs r0, #3 +100061ec: 2210 movs r2, #16 +100061ee: f8c3 00e0 str.w r0, [r3, #224] @ 0xe0 +100061f2: 4620 mov r0, r4 +100061f4: e9cd ce04 strd ip, lr, [sp, #16] +100061f8: f001 f8f8 bl 100073ec +100061fc: b108 cbz r0, 10006202 +100061fe: b007 add sp, #28 +10006200: bd30 pop {r4, r5, pc} +10006202: 4629 mov r1, r5 +10006204: 4620 mov r0, r4 +10006206: f001 f9e9 bl 100075dc +1000620a: b007 add sp, #28 +1000620c: bd30 pop {r4, r5, pc} +1000620e: e9d0 0234 ldrd r0, r2, [r0, #208] @ 0xd0 +10006212: f010 040f ands.w r4, r0, #15 +10006216: d105 bne.n 10006224 +10006218: e9d3 ce36 ldrd ip, lr, [r3, #216] @ 0xd8 +1000621c: a902 add r1, sp, #8 +1000621e: f103 0484 add.w r4, r3, #132 @ 0x84 +10006222: e7e0 b.n 100061e6 +10006224: f04f 0c00 mov.w ip, #0 +10006228: a902 add r1, sp, #8 +1000622a: f1c4 0210 rsb r2, r4, #16 +1000622e: f103 0484 add.w r4, r3, #132 @ 0x84 +10006232: f8cd c008 str.w ip, [sp, #8] +10006236: 4620 mov r0, r4 +10006238: e9c1 cc01 strd ip, ip, [r1, #4] +1000623c: f8c1 c00b str.w ip, [r1, #11] +10006240: 9301 str r3, [sp, #4] +10006242: 9100 str r1, [sp, #0] +10006244: f001 f8d2 bl 100073ec +10006248: e9dd 1300 ldrd r1, r3, [sp] +1000624c: 2800 cmp r0, #0 +1000624e: d1d6 bne.n 100061fe +10006250: e9d3 0234 ldrd r0, r2, [r3, #208] @ 0xd0 +10006254: e9d3 ce36 ldrd ip, lr, [r3, #216] @ 0xd8 +10006258: e7c5 b.n 100061e6 +1000625a: f01c 020f ands.w r2, ip, #15 +1000625e: d0bd beq.n 100061dc +10006260: f04f 0c00 mov.w ip, #0 +10006264: a902 add r1, sp, #8 +10006266: f1c2 0210 rsb r2, r2, #16 +1000626a: e7e0 b.n 1000622e +1000626c: f06f 0053 mvn.w r0, #83 @ 0x53 +10006270: 4770 bx lr +10006272: bf00 nop + +10006274 : +10006274: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10006278: 4689 mov r9, r1 +1000627a: b093 sub sp, #76 @ 0x4c +1000627c: 4611 mov r1, r2 +1000627e: e9dd 571c ldrd r5, r7, [sp, #112] @ 0x70 +10006282: e9dd 8a1e ldrd r8, sl, [sp, #120] @ 0x78 +10006286: 2200 movs r2, #0 +10006288: 4604 mov r4, r0 +1000628a: 461e mov r6, r3 +1000628c: f000 fd26 bl 10006cdc +10006290: b148 cbz r0, 100062a6 +10006292: 9001 str r0, [sp, #4] +10006294: 2140 movs r1, #64 @ 0x40 +10006296: a802 add r0, sp, #8 +10006298: f000 fb92 bl 100069c0 +1000629c: 9b01 ldr r3, [sp, #4] +1000629e: 4618 mov r0, r3 +100062a0: b013 add sp, #76 @ 0x4c +100062a2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100062a6: 4601 mov r1, r0 +100062a8: 2240 movs r2, #64 @ 0x40 +100062aa: a802 add r0, sp, #8 +100062ac: f005 fdbe bl 1000be2c +100062b0: ab02 add r3, sp, #8 +100062b2: 461a mov r2, r3 +100062b4: 2140 movs r1, #64 @ 0x40 +100062b6: 4620 mov r0, r4 +100062b8: f000 fd24 bl 10006d04 +100062bc: 2800 cmp r0, #0 +100062be: d1e8 bne.n 10006292 +100062c0: a902 add r1, sp, #8 +100062c2: f104 0084 add.w r0, r4, #132 @ 0x84 +100062c6: f001 f867 bl 10007398 +100062ca: 2800 cmp r0, #0 +100062cc: d1e1 bne.n 10006292 +100062ce: 2301 movs r3, #1 +100062d0: 2200 movs r2, #0 +100062d2: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +100062d6: 2300 movs r3, #0 +100062d8: f884 00e4 strb.w r0, [r4, #228] @ 0xe4 +100062dc: e9c4 2334 strd r2, r3, [r4, #208] @ 0xd0 +100062e0: e9c4 2336 strd r2, r3, [r4, #216] @ 0xd8 +100062e4: 2140 movs r1, #64 @ 0x40 +100062e6: a802 add r0, sp, #8 +100062e8: f000 fb6a bl 100069c0 +100062ec: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 +100062f0: 2b01 cmp r3, #1 +100062f2: d123 bne.n 1000633c +100062f4: f8d4 30d0 ldr.w r3, [r4, #208] @ 0xd0 +100062f8: 4631 mov r1, r6 +100062fa: 195b adds r3, r3, r5 +100062fc: f8c4 30d0 str.w r3, [r4, #208] @ 0xd0 +10006300: f8d4 30d4 ldr.w r3, [r4, #212] @ 0xd4 +10006304: 462a mov r2, r5 +10006306: f143 0300 adc.w r3, r3, #0 +1000630a: f8c4 30d4 str.w r3, [r4, #212] @ 0xd4 +1000630e: f104 0084 add.w r0, r4, #132 @ 0x84 +10006312: f001 f86b bl 100073ec +10006316: 4603 mov r3, r0 +10006318: 2800 cmp r0, #0 +1000631a: d1c0 bne.n 1000629e +1000631c: 4643 mov r3, r8 +1000631e: 463a mov r2, r7 +10006320: 4649 mov r1, r9 +10006322: 4620 mov r0, r4 +10006324: f7ff fef2 bl 1000610c +10006328: 4603 mov r3, r0 +1000632a: 2800 cmp r0, #0 +1000632c: d1b7 bne.n 1000629e +1000632e: 4651 mov r1, sl +10006330: 4620 mov r0, r4 +10006332: b013 add sp, #76 @ 0x4c +10006334: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10006338: f7ff bf42 b.w 100061c0 +1000633c: f06f 0353 mvn.w r3, #83 @ 0x53 +10006340: e7ad b.n 1000629e +10006342: bf00 nop + +10006344 : +10006344: b5f0 push {r4, r5, r6, r7, lr} +10006346: 460e mov r6, r1 +10006348: b093 sub sp, #76 @ 0x4c +1000634a: 4611 mov r1, r2 +1000634c: 2200 movs r2, #0 +1000634e: 4604 mov r4, r0 +10006350: 461d mov r5, r3 +10006352: f000 fcc3 bl 10006cdc +10006356: b140 cbz r0, 1000636a +10006358: 9001 str r0, [sp, #4] +1000635a: 2140 movs r1, #64 @ 0x40 +1000635c: a802 add r0, sp, #8 +1000635e: f000 fb2f bl 100069c0 +10006362: 9b01 ldr r3, [sp, #4] +10006364: 4618 mov r0, r3 +10006366: b013 add sp, #76 @ 0x4c +10006368: bdf0 pop {r4, r5, r6, r7, pc} +1000636a: 4601 mov r1, r0 +1000636c: 2240 movs r2, #64 @ 0x40 +1000636e: a802 add r0, sp, #8 +10006370: f005 fd5c bl 1000be2c +10006374: ab02 add r3, sp, #8 +10006376: 461a mov r2, r3 +10006378: 2140 movs r1, #64 @ 0x40 +1000637a: 4620 mov r0, r4 +1000637c: f000 fcc2 bl 10006d04 +10006380: 2800 cmp r0, #0 +10006382: d1e9 bne.n 10006358 +10006384: a902 add r1, sp, #8 +10006386: f104 0084 add.w r0, r4, #132 @ 0x84 +1000638a: f104 0784 add.w r7, r4, #132 @ 0x84 +1000638e: f001 f803 bl 10007398 +10006392: 2800 cmp r0, #0 +10006394: d1e0 bne.n 10006358 +10006396: 2301 movs r3, #1 +10006398: 2200 movs r2, #0 +1000639a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +1000639e: f884 30e4 strb.w r3, [r4, #228] @ 0xe4 +100063a2: 2300 movs r3, #0 +100063a4: 2140 movs r1, #64 @ 0x40 +100063a6: e9c4 2334 strd r2, r3, [r4, #208] @ 0xd0 +100063aa: e9c4 2336 strd r2, r3, [r4, #216] @ 0xd8 +100063ae: a802 add r0, sp, #8 +100063b0: f000 fb06 bl 100069c0 +100063b4: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 +100063b8: 2b01 cmp r3, #1 +100063ba: d131 bne.n 10006420 +100063bc: f8d4 30d0 ldr.w r3, [r4, #208] @ 0xd0 +100063c0: 9a18 ldr r2, [sp, #96] @ 0x60 +100063c2: 4629 mov r1, r5 +100063c4: 189b adds r3, r3, r2 +100063c6: f8c4 30d0 str.w r3, [r4, #208] @ 0xd0 +100063ca: f8d4 30d4 ldr.w r3, [r4, #212] @ 0xd4 +100063ce: 4638 mov r0, r7 +100063d0: f143 0300 adc.w r3, r3, #0 +100063d4: f8c4 30d4 str.w r3, [r4, #212] @ 0xd4 +100063d8: f001 f808 bl 100073ec +100063dc: 4603 mov r3, r0 +100063de: 2800 cmp r0, #0 +100063e0: d1c0 bne.n 10006364 +100063e2: e9dd 231a ldrd r2, r3, [sp, #104] @ 0x68 +100063e6: 4631 mov r1, r6 +100063e8: 4620 mov r0, r4 +100063ea: f7ff fe8f bl 1000610c +100063ee: 4603 mov r3, r0 +100063f0: 2800 cmp r0, #0 +100063f2: d1b7 bne.n 10006364 +100063f4: 4620 mov r0, r4 +100063f6: a902 add r1, sp, #8 +100063f8: f7ff fee2 bl 100061c0 +100063fc: 4603 mov r3, r0 +100063fe: 2800 cmp r0, #0 +10006400: d1b0 bne.n 10006364 +10006402: 2210 movs r2, #16 +10006404: 9819 ldr r0, [sp, #100] @ 0x64 +10006406: a902 add r1, sp, #8 +10006408: f000 f960 bl 100066cc +1000640c: 4603 mov r3, r0 +1000640e: 2800 cmp r0, #0 +10006410: d0a8 beq.n 10006364 +10006412: 4631 mov r1, r6 +10006414: 981b ldr r0, [sp, #108] @ 0x6c +10006416: f000 fad3 bl 100069c0 +1000641a: f06f 0355 mvn.w r3, #85 @ 0x55 +1000641e: e7a1 b.n 10006364 +10006420: f06f 0353 mvn.w r3, #83 @ 0x53 +10006424: e79e b.n 10006364 +10006426: bf00 nop + +10006428 : +10006428: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +1000642c: b0f1 sub sp, #452 @ 0x1c4 +1000642e: 2800 cmp r0, #0 +10006430: f040 8082 bne.w 10006538 +10006434: 4680 mov r8, r0 +10006436: 2600 movs r6, #0 +10006438: 2700 movs r7, #0 +1000643a: ac36 add r4, sp, #216 @ 0xd8 +1000643c: 4620 mov r0, r4 +1000643e: f000 fc11 bl 10006c64 +10006442: a857 add r0, sp, #348 @ 0x15c +10006444: f000 ff9e bl 10007384 +10006448: 4620 mov r0, r4 +1000644a: 4991 ldr r1, [pc, #580] @ (10006690 ) +1000644c: e9cd 676a strd r6, r7, [sp, #424] @ 0x1a8 +10006450: e9cd 676c strd r6, r7, [sp, #432] @ 0x1b0 +10006454: f8cd 81b8 str.w r8, [sp, #440] @ 0x1b8 +10006458: f88d 81bc strb.w r8, [sp, #444] @ 0x1bc +1000645c: f000 fc16 bl 10006c8c +10006460: 4602 mov r2, r0 +10006462: bb90 cbnz r0, 100064ca +10006464: 4620 mov r0, r4 +10006466: 498b ldr r1, [pc, #556] @ (10006694 ) +10006468: f000 fc38 bl 10006cdc +1000646c: bb90 cbnz r0, 100064d4 +1000646e: 4601 mov r1, r0 +10006470: 2240 movs r2, #64 @ 0x40 +10006472: a804 add r0, sp, #16 +10006474: f005 fcda bl 1000be2c +10006478: ab04 add r3, sp, #16 +1000647a: 461a mov r2, r3 +1000647c: 2140 movs r1, #64 @ 0x40 +1000647e: 4620 mov r0, r4 +10006480: f000 fc40 bl 10006d04 +10006484: bb30 cbnz r0, 100064d4 +10006486: a904 add r1, sp, #16 +10006488: a857 add r0, sp, #348 @ 0x15c +1000648a: f000 ff85 bl 10007398 +1000648e: 4602 mov r2, r0 +10006490: bb00 cbnz r0, 100064d4 +10006492: 2301 movs r3, #1 +10006494: 2140 movs r1, #64 @ 0x40 +10006496: a804 add r0, sp, #16 +10006498: 936e str r3, [sp, #440] @ 0x1b8 +1000649a: e9cd 676a strd r6, r7, [sp, #424] @ 0x1a8 +1000649e: e9cd 676c strd r6, r7, [sp, #432] @ 0x1b0 +100064a2: f88d 21bc strb.w r2, [sp, #444] @ 0x1bc +100064a6: f000 fa8b bl 100069c0 +100064aa: 9b6e ldr r3, [sp, #440] @ 0x1b8 +100064ac: 2b01 cmp r3, #1 +100064ae: d10c bne.n 100064ca +100064b0: e9dd 326a ldrd r3, r2, [sp, #424] @ 0x1a8 +100064b4: 330c adds r3, #12 +100064b6: f142 0600 adc.w r6, r2, #0 +100064ba: 4977 ldr r1, [pc, #476] @ (10006698 ) +100064bc: 220c movs r2, #12 +100064be: a857 add r0, sp, #348 @ 0x15c +100064c0: e9cd 366a strd r3, r6, [sp, #424] @ 0x1a8 +100064c4: f000 ff92 bl 100073ec +100064c8: b148 cbz r0, 100064de +100064ca: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +100064ce: b071 add sp, #452 @ 0x1c4 +100064d0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100064d4: 2140 movs r1, #64 @ 0x40 +100064d6: a804 add r0, sp, #16 +100064d8: f000 fa72 bl 100069c0 +100064dc: e7f5 b.n 100064ca +100064de: 2172 movs r1, #114 @ 0x72 +100064e0: 4620 mov r0, r4 +100064e2: 4a6e ldr r2, [pc, #440] @ (1000669c ) +100064e4: ab04 add r3, sp, #16 +100064e6: f7ff fe11 bl 1000610c +100064ea: 2800 cmp r0, #0 +100064ec: d1ed bne.n 100064ca +100064ee: 4669 mov r1, sp +100064f0: 4620 mov r0, r4 +100064f2: f7ff fe65 bl 100061c0 +100064f6: 2800 cmp r0, #0 +100064f8: d1e7 bne.n 100064ca +100064fa: 2272 movs r2, #114 @ 0x72 +100064fc: 4968 ldr r1, [pc, #416] @ (100066a0 ) +100064fe: a804 add r0, sp, #16 +10006500: f005 fc54 bl 1000bdac +10006504: 2800 cmp r0, #0 +10006506: d1e0 bne.n 100064ca +10006508: 4b66 ldr r3, [pc, #408] @ (100066a4 ) +1000650a: 9a00 ldr r2, [sp, #0] +1000650c: 429a cmp r2, r3 +1000650e: d1dc bne.n 100064ca +10006510: 4a65 ldr r2, [pc, #404] @ (100066a8 ) +10006512: 9b01 ldr r3, [sp, #4] +10006514: 4293 cmp r3, r2 +10006516: d1d8 bne.n 100064ca +10006518: 4a64 ldr r2, [pc, #400] @ (100066ac ) +1000651a: 9b02 ldr r3, [sp, #8] +1000651c: 4293 cmp r3, r2 +1000651e: d1d4 bne.n 100064ca +10006520: 4a63 ldr r2, [pc, #396] @ (100066b0 ) +10006522: 9b03 ldr r3, [sp, #12] +10006524: 4293 cmp r3, r2 +10006526: d1d0 bne.n 100064ca +10006528: 4620 mov r0, r4 +1000652a: f000 fba9 bl 10006c80 +1000652e: a857 add r0, sp, #348 @ 0x15c +10006530: f000 ff2c bl 1000738c +10006534: 2000 movs r0, #0 +10006536: e7ca b.n 100064ce +10006538: 2100 movs r1, #0 +1000653a: ac36 add r4, sp, #216 @ 0xd8 +1000653c: 485d ldr r0, [pc, #372] @ (100066b4 ) +1000653e: f7fd f9b1 bl 100038a4 <__wrap_printf> +10006542: 4620 mov r0, r4 +10006544: f000 fb8e bl 10006c64 +10006548: a857 add r0, sp, #348 @ 0x15c +1000654a: f000 ff1b bl 10007384 +1000654e: f04f 0800 mov.w r8, #0 +10006552: f04f 0900 mov.w r9, #0 +10006556: 2300 movs r3, #0 +10006558: 4620 mov r0, r4 +1000655a: 494d ldr r1, [pc, #308] @ (10006690 ) +1000655c: e9cd 896a strd r8, r9, [sp, #424] @ 0x1a8 +10006560: e9cd 896c strd r8, r9, [sp, #432] @ 0x1b0 +10006564: 936e str r3, [sp, #440] @ 0x1b8 +10006566: f88d 31bc strb.w r3, [sp, #444] @ 0x1bc +1000656a: f000 fb8f bl 10006c8c +1000656e: 2800 cmp r0, #0 +10006570: f040 8082 bne.w 10006678 +10006574: 4602 mov r2, r0 +10006576: 4947 ldr r1, [pc, #284] @ (10006694 ) +10006578: 4620 mov r0, r4 +1000657a: f000 fbaf bl 10006cdc +1000657e: 4607 mov r7, r0 +10006580: b960 cbnz r0, 1000659c +10006582: 4601 mov r1, r0 +10006584: 2240 movs r2, #64 @ 0x40 +10006586: a804 add r0, sp, #16 +10006588: f005 fc50 bl 1000be2c +1000658c: ab04 add r3, sp, #16 +1000658e: 461a mov r2, r3 +10006590: 2140 movs r1, #64 @ 0x40 +10006592: 4620 mov r0, r4 +10006594: f000 fbb6 bl 10006d04 +10006598: 4607 mov r7, r0 +1000659a: b140 cbz r0, 100065ae +1000659c: 2140 movs r1, #64 @ 0x40 +1000659e: a804 add r0, sp, #16 +100065a0: f000 fa0e bl 100069c0 +100065a4: 4639 mov r1, r7 +100065a6: 4844 ldr r0, [pc, #272] @ (100066b8 ) +100065a8: f7fd f97c bl 100038a4 <__wrap_printf> +100065ac: e78d b.n 100064ca +100065ae: a904 add r1, sp, #16 +100065b0: a857 add r0, sp, #348 @ 0x15c +100065b2: f000 fef1 bl 10007398 +100065b6: 4607 mov r7, r0 +100065b8: 2800 cmp r0, #0 +100065ba: d1ef bne.n 1000659c +100065bc: 2301 movs r3, #1 +100065be: f88d 01bc strb.w r0, [sp, #444] @ 0x1bc +100065c2: 2140 movs r1, #64 @ 0x40 +100065c4: a804 add r0, sp, #16 +100065c6: 936e str r3, [sp, #440] @ 0x1b8 +100065c8: e9cd 896a strd r8, r9, [sp, #424] @ 0x1a8 +100065cc: e9cd 896c strd r8, r9, [sp, #432] @ 0x1b0 +100065d0: f000 f9f6 bl 100069c0 +100065d4: 9b6e ldr r3, [sp, #440] @ 0x1b8 +100065d6: 2b01 cmp r3, #1 +100065d8: d157 bne.n 1000668a +100065da: e9dd 326a ldrd r3, r2, [sp, #424] @ 0x1a8 +100065de: 330c adds r3, #12 +100065e0: f142 0100 adc.w r1, r2, #0 +100065e4: 916b str r1, [sp, #428] @ 0x1ac +100065e6: 220c movs r2, #12 +100065e8: 492b ldr r1, [pc, #172] @ (10006698 ) +100065ea: a857 add r0, sp, #348 @ 0x15c +100065ec: 936a str r3, [sp, #424] @ 0x1a8 +100065ee: f000 fefd bl 100073ec +100065f2: 4607 mov r7, r0 +100065f4: 2800 cmp r0, #0 +100065f6: d1d5 bne.n 100065a4 +100065f8: 2172 movs r1, #114 @ 0x72 +100065fa: 4620 mov r0, r4 +100065fc: 4a27 ldr r2, [pc, #156] @ (1000669c ) +100065fe: ab04 add r3, sp, #16 +10006600: f7ff fd84 bl 1000610c +10006604: 4607 mov r7, r0 +10006606: 2800 cmp r0, #0 +10006608: d1cc bne.n 100065a4 +1000660a: 4669 mov r1, sp +1000660c: 4620 mov r0, r4 +1000660e: f7ff fdd7 bl 100061c0 +10006612: 4607 mov r7, r0 +10006614: 2800 cmp r0, #0 +10006616: d1c5 bne.n 100065a4 +10006618: 2272 movs r2, #114 @ 0x72 +1000661a: 4921 ldr r1, [pc, #132] @ (100066a0 ) +1000661c: a804 add r0, sp, #16 +1000661e: f005 fbc5 bl 1000bdac +10006622: bb70 cbnz r0, 10006682 +10006624: 4b1f ldr r3, [pc, #124] @ (100066a4 ) +10006626: 9a00 ldr r2, [sp, #0] +10006628: 429a cmp r2, r3 +1000662a: d003 beq.n 10006634 +1000662c: 4823 ldr r0, [pc, #140] @ (100066bc ) +1000662e: f7fd f8bb bl 100037a8 <__wrap_puts> +10006632: e74a b.n 100064ca +10006634: 4a1c ldr r2, [pc, #112] @ (100066a8 ) +10006636: 9b01 ldr r3, [sp, #4] +10006638: 4293 cmp r3, r2 +1000663a: d1f7 bne.n 1000662c +1000663c: 4a1b ldr r2, [pc, #108] @ (100066ac ) +1000663e: 9b02 ldr r3, [sp, #8] +10006640: 4293 cmp r3, r2 +10006642: d1f3 bne.n 1000662c +10006644: 4a1a ldr r2, [pc, #104] @ (100066b0 ) +10006646: 9b03 ldr r3, [sp, #12] +10006648: 4293 cmp r3, r2 +1000664a: d1ef bne.n 1000662c +1000664c: 4620 mov r0, r4 +1000664e: f000 fb17 bl 10006c80 +10006652: a857 add r0, sp, #348 @ 0x15c +10006654: f000 fe9a bl 1000738c +10006658: 4642 mov r2, r8 +1000665a: 464b mov r3, r9 +1000665c: 4818 ldr r0, [pc, #96] @ (100066c0 ) +1000665e: e9cd 236a strd r2, r3, [sp, #424] @ 0x1a8 +10006662: e9cd 236c strd r2, r3, [sp, #432] @ 0x1b0 +10006666: 976e str r7, [sp, #440] @ 0x1b8 +10006668: f88d 71bc strb.w r7, [sp, #444] @ 0x1bc +1000666c: f7fd f89c bl 100037a8 <__wrap_puts> +10006670: 200a movs r0, #10 +10006672: f7fd f857 bl 10003724 <__wrap_putchar> +10006676: e75d b.n 10006534 +10006678: 4601 mov r1, r0 +1000667a: 4812 ldr r0, [pc, #72] @ (100066c4 ) +1000667c: f7fd f912 bl 100038a4 <__wrap_printf> +10006680: e723 b.n 100064ca +10006682: 4811 ldr r0, [pc, #68] @ (100066c8 ) +10006684: f7fd f890 bl 100037a8 <__wrap_puts> +10006688: e71f b.n 100064ca +1000668a: f06f 0753 mvn.w r7, #83 @ 0x53 +1000668e: e789 b.n 100065a4 +10006690: 1000cefc .word 0x1000cefc +10006694: 1000cf1c .word 0x1000cf1c +10006698: 1000cf28 .word 0x1000cf28 +1000669c: 1000cf34 .word 0x1000cf34 +100066a0: 1000cfa8 .word 0x1000cfa8 +100066a4: 590be11a .word 0x590be11a +100066a8: 6ae2094f .word 0x6ae2094f +100066ac: cb2e907e .word 0xcb2e907e +100066b0: 910660d0 .word 0x910660d0 +100066b4: 1000c728 .word 0x1000c728 +100066b8: 1000c750 .word 0x1000c750 +100066bc: 1000c7a4 .word 0x1000c7a4 +100066c0: 1000c748 .word 0x1000c748 +100066c4: 1000c770 .word 0x1000c770 +100066c8: 1000c78c .word 0x1000c78c + +100066cc : +100066cc: 2a03 cmp r2, #3 +100066ce: b5f0 push {r4, r5, r6, r7, lr} +100066d0: 4607 mov r7, r0 +100066d2: 460e mov r6, r1 +100066d4: d92e bls.n 10006734 +100066d6: 2304 movs r3, #4 +100066d8: 2100 movs r1, #0 +100066da: 1f05 subs r5, r0, #4 +100066dc: 1f34 subs r4, r6, #4 +100066de: eb05 0e03 add.w lr, r5, r3 +100066e2: f8de e000 ldr.w lr, [lr] +100066e6: eb04 0c03 add.w ip, r4, r3 +100066ea: f8dc c000 ldr.w ip, [ip] +100066ee: 4618 mov r0, r3 +100066f0: 3304 adds r3, #4 +100066f2: ea8c 0c0e eor.w ip, ip, lr +100066f6: 429a cmp r2, r3 +100066f8: ea41 010c orr.w r1, r1, ip +100066fc: d2ef bcs.n 100066de +100066fe: 4282 cmp r2, r0 +10006700: d914 bls.n 1000672c +10006702: 5c3c ldrb r4, [r7, r0] +10006704: 5c33 ldrb r3, [r6, r0] +10006706: 4063 eors r3, r4 +10006708: 1c44 adds r4, r0, #1 +1000670a: 42a2 cmp r2, r4 +1000670c: ea41 0103 orr.w r1, r1, r3 +10006710: d90c bls.n 1000672c +10006712: 1c83 adds r3, r0, #2 +10006714: 5d38 ldrb r0, [r7, r4] +10006716: 5d34 ldrb r4, [r6, r4] +10006718: 429a cmp r2, r3 +1000671a: ea80 0004 eor.w r0, r0, r4 +1000671e: ea41 0100 orr.w r1, r1, r0 +10006722: d903 bls.n 1000672c +10006724: 5cfa ldrb r2, [r7, r3] +10006726: 5cf3 ldrb r3, [r6, r3] +10006728: 4053 eors r3, r2 +1000672a: 4319 orrs r1, r3 +1000672c: b288 uxth r0, r1 +1000672e: ea40 4011 orr.w r0, r0, r1, lsr #16 +10006732: bdf0 pop {r4, r5, r6, r7, pc} +10006734: 2100 movs r1, #0 +10006736: 4608 mov r0, r1 +10006738: e7e1 b.n 100066fe +1000673a: bf00 nop + +1000673c : +1000673c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10006740: 4616 mov r6, r2 +10006742: 2a00 cmp r2, #0 +10006744: d02d beq.n 100067a2 +10006746: f04f 0c00 mov.w ip, #0 +1000674a: 4698 mov r8, r3 +1000674c: 9b08 ldr r3, [sp, #32] +1000674e: 4604 mov r4, r0 +10006750: eba2 0a03 sub.w sl, r2, r3 +10006754: 460d mov r5, r1 +10006756: 4662 mov r2, ip +10006758: f814 e00c ldrb.w lr, [r4, ip] +1000675c: 4660 mov r0, ip +1000675e: 4641 mov r1, r8 +10006760: f815 900c ldrb.w r9, [r5, ip] +10006764: ea90 0301 eors.w r3, r0, r1 +10006768: 1a40 subs r0, r0, r1 +1000676a: 4398 bics r0, r3 +1000676c: 4019 ands r1, r3 +1000676e: 4308 orrs r0, r1 +10006770: 17c0 asrs r0, r0, #31 +10006772: 4661 mov r1, ip +10006774: 4653 mov r3, sl +10006776: ea91 0703 eors.w r7, r1, r3 +1000677a: 1ac9 subs r1, r1, r3 +1000677c: 43b9 bics r1, r7 +1000677e: 403b ands r3, r7 +10006780: 4319 orrs r1, r3 +10006782: 17c9 asrs r1, r1, #31 +10006784: ea21 0100 bic.w r1, r1, r0 +10006788: ea8e 0e09 eor.w lr, lr, r9 +1000678c: f10c 0c01 add.w ip, ip, #1 +10006790: ea01 010e and.w r1, r1, lr +10006794: 4566 cmp r6, ip +10006796: ea42 0201 orr.w r2, r2, r1 +1000679a: d1dd bne.n 10006758 +1000679c: 4610 mov r0, r2 +1000679e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100067a2: 4610 mov r0, r2 +100067a4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + +100067a8 : +100067a8: 2900 cmp r1, #0 +100067aa: d030 beq.n 1000680e +100067ac: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100067b0: 4688 mov r8, r1 +100067b2: 4606 mov r6, r0 +100067b4: 2500 movs r5, #0 +100067b6: f101 39ff add.w r9, r1, #4294967295 @ 0xffffffff +100067ba: 1a8f subs r7, r1, r2 +100067bc: eb09 0400 add.w r4, r9, r0 +100067c0: 4629 mov r1, r5 +100067c2: 463b mov r3, r7 +100067c4: ea91 0203 eors.w r2, r1, r3 +100067c8: 1ac9 subs r1, r1, r3 +100067ca: 4391 bics r1, r2 +100067cc: 4013 ands r3, r2 +100067ce: 4319 orrs r1, r3 +100067d0: 17c9 asrs r1, r1, #31 +100067d2: f1b9 0f00 cmp.w r9, #0 +100067d6: d015 beq.n 10006804 +100067d8: 46b4 mov ip, r6 +100067da: 46e6 mov lr, ip +100067dc: f89c 2000 ldrb.w r2, [ip] +100067e0: 460b mov r3, r1 +100067e2: f81c 0f01 ldrb.w r0, [ip, #1]! +100067e6: 401a ands r2, r3 +100067e8: 43db mvns r3, r3 +100067ea: 4003 ands r3, r0 +100067ec: 4313 orrs r3, r2 +100067ee: 4564 cmp r4, ip +100067f0: f88e 3000 strb.w r3, [lr] +100067f4: d1f1 bne.n 100067da +100067f6: 7823 ldrb r3, [r4, #0] +100067f8: 3501 adds r5, #1 +100067fa: 400b ands r3, r1 +100067fc: 45a8 cmp r8, r5 +100067fe: 7023 strb r3, [r4, #0] +10006800: d1de bne.n 100067c0 +10006802: e002 b.n 1000680a +10006804: 7833 ldrb r3, [r6, #0] +10006806: 400b ands r3, r1 +10006808: 7033 strb r3, [r6, #0] +1000680a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +1000680e: 4770 bx lr + +10006810 : +10006810: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10006814: 9c06 ldr r4, [sp, #24] +10006816: 460d mov r5, r1 +10006818: 4616 mov r6, r2 +1000681a: 4601 mov r1, r0 +1000681c: 2b00 cmp r3, #0 +1000681e: bf14 ite ne +10006820: 461f movne r7, r3 +10006822: 462f moveq r7, r5 +10006824: 2c03 cmp r4, #3 +10006826: d93e bls.n 100068a6 +10006828: 2304 movs r3, #4 +1000682a: 18f2 adds r2, r6, r3 +1000682c: eb07 0e03 add.w lr, r7, r3 +10006830: f852 cc04 ldr.w ip, [r2, #-4] +10006834: f85e ec04 ldr.w lr, [lr, #-4] +10006838: 18ea adds r2, r5, r3 +1000683a: 4698 mov r8, r3 +1000683c: ea0c 0c00 and.w ip, ip, r0 +10006840: ea2e 0e01 bic.w lr, lr, r1 +10006844: 3304 adds r3, #4 +10006846: ea4c 0c0e orr.w ip, ip, lr +1000684a: 429c cmp r4, r3 +1000684c: f842 cc04 str.w ip, [r2, #-4] +10006850: d2eb bcs.n 1000682a +10006852: 4544 cmp r4, r8 +10006854: d925 bls.n 100068a2 +10006856: f817 3008 ldrb.w r3, [r7, r8] +1000685a: f816 2008 ldrb.w r2, [r6, r8] +1000685e: ea23 0301 bic.w r3, r3, r1 +10006862: 4002 ands r2, r0 +10006864: 4313 orrs r3, r2 +10006866: f108 0201 add.w r2, r8, #1 +1000686a: 4294 cmp r4, r2 +1000686c: f805 3008 strb.w r3, [r5, r8] +10006870: d917 bls.n 100068a2 +10006872: 5cbb ldrb r3, [r7, r2] +10006874: f816 c002 ldrb.w ip, [r6, r2] +10006878: f108 0802 add.w r8, r8, #2 +1000687c: ea23 0301 bic.w r3, r3, r1 +10006880: ea00 0c0c and.w ip, r0, ip +10006884: ea43 030c orr.w r3, r3, ip +10006888: 4544 cmp r4, r8 +1000688a: 54ab strb r3, [r5, r2] +1000688c: d909 bls.n 100068a2 +1000688e: f816 3008 ldrb.w r3, [r6, r8] +10006892: 4018 ands r0, r3 +10006894: f817 3008 ldrb.w r3, [r7, r8] +10006898: ea23 0301 bic.w r3, r3, r1 +1000689c: 4318 orrs r0, r3 +1000689e: f805 0008 strb.w r0, [r5, r8] +100068a2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100068a6: f04f 0800 mov.w r8, #0 +100068aa: e7d2 b.n 10006852 + +100068ac : +100068ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100068b0: e9dd 6508 ldrd r6, r5, [sp, #32] +100068b4: 42b3 cmp r3, r6 +100068b6: d851 bhi.n 1000695c +100068b8: 4607 mov r7, r0 +100068ba: 4698 mov r8, r3 +100068bc: 4691 mov r9, r2 +100068be: 18cc adds r4, r1, r3 +100068c0: 1f02 subs r2, r0, #4 +100068c2: 4643 mov r3, r8 +100068c4: 4649 mov r1, r9 +100068c6: 404b eors r3, r1 +100068c8: 4259 negs r1, r3 +100068ca: 430b orrs r3, r1 +100068cc: 17db asrs r3, r3, #31 +100068ce: 43db mvns r3, r3 +100068d0: 4618 mov r0, r3 +100068d2: 2d03 cmp r5, #3 +100068d4: d944 bls.n 10006960 +100068d6: 2104 movs r1, #4 +100068d8: eb04 0c01 add.w ip, r4, r1 +100068dc: f852 e001 ldr.w lr, [r2, r1] +100068e0: f85c cc04 ldr.w ip, [ip, #-4] +100068e4: ea2e 0e00 bic.w lr, lr, r0 +100068e8: ea0c 0c03 and.w ip, ip, r3 +100068ec: ea4c 0c0e orr.w ip, ip, lr +100068f0: f842 c001 str.w ip, [r2, r1] +100068f4: 468c mov ip, r1 +100068f6: 3104 adds r1, #4 +100068f8: 428d cmp r5, r1 +100068fa: d2ed bcs.n 100068d8 +100068fc: 4565 cmp r5, ip +100068fe: d927 bls.n 10006950 +10006900: f814 100c ldrb.w r1, [r4, ip] +10006904: f817 e00c ldrb.w lr, [r7, ip] +10006908: 4019 ands r1, r3 +1000690a: ea2e 0e00 bic.w lr, lr, r0 +1000690e: ea41 010e orr.w r1, r1, lr +10006912: f10c 0e01 add.w lr, ip, #1 +10006916: 4575 cmp r5, lr +10006918: f807 100c strb.w r1, [r7, ip] +1000691c: d918 bls.n 10006950 +1000691e: f814 100e ldrb.w r1, [r4, lr] +10006922: f817 a00e ldrb.w sl, [r7, lr] +10006926: f10c 0c02 add.w ip, ip, #2 +1000692a: 4019 ands r1, r3 +1000692c: ea2a 0a00 bic.w sl, sl, r0 +10006930: ea41 010a orr.w r1, r1, sl +10006934: 4565 cmp r5, ip +10006936: f807 100e strb.w r1, [r7, lr] +1000693a: d909 bls.n 10006950 +1000693c: f814 100c ldrb.w r1, [r4, ip] +10006940: 400b ands r3, r1 +10006942: f817 100c ldrb.w r1, [r7, ip] +10006946: ea21 0100 bic.w r1, r1, r0 +1000694a: 430b orrs r3, r1 +1000694c: f807 300c strb.w r3, [r7, ip] +10006950: f108 0801 add.w r8, r8, #1 +10006954: 4546 cmp r6, r8 +10006956: f104 0401 add.w r4, r4, #1 +1000695a: d2b2 bcs.n 100068c2 +1000695c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10006960: f04f 0c00 mov.w ip, #0 +10006964: e7ca b.n 100068fc +10006966: bf00 nop + +10006968 : +10006968: 2a03 cmp r2, #3 +1000696a: b510 push {r4, lr} +1000696c: 4614 mov r4, r2 +1000696e: d924 bls.n 100069ba +10006970: 2304 movs r3, #4 +10006972: f1a1 0e04 sub.w lr, r1, #4 +10006976: f85e c003 ldr.w ip, [lr, r3] +1000697a: 461a mov r2, r3 +1000697c: ea2c 0c00 bic.w ip, ip, r0 +10006980: f84e c003 str.w ip, [lr, r3] +10006984: 3304 adds r3, #4 +10006986: 42a3 cmp r3, r4 +10006988: d9f5 bls.n 10006976 +1000698a: 4294 cmp r4, r2 +1000698c: d914 bls.n 100069b8 +1000698e: 5c8b ldrb r3, [r1, r2] +10006990: f102 0c01 add.w ip, r2, #1 +10006994: ea23 0300 bic.w r3, r3, r0 +10006998: 45a4 cmp ip, r4 +1000699a: 548b strb r3, [r1, r2] +1000699c: d20c bcs.n 100069b8 +1000699e: 1c93 adds r3, r2, #2 +100069a0: f811 200c ldrb.w r2, [r1, ip] +100069a4: 429c cmp r4, r3 +100069a6: ea22 0200 bic.w r2, r2, r0 +100069aa: f801 200c strb.w r2, [r1, ip] +100069ae: d903 bls.n 100069b8 +100069b0: 5cca ldrb r2, [r1, r3] +100069b2: ea22 0200 bic.w r2, r2, r0 +100069b6: 54ca strb r2, [r1, r3] +100069b8: bd10 pop {r4, pc} +100069ba: 2200 movs r2, #0 +100069bc: e7e5 b.n 1000698a +100069be: bf00 nop + +100069c0 : +100069c0: b131 cbz r1, 100069d0 +100069c2: 2200 movs r2, #0 +100069c4: 4401 add r1, r0 +100069c6: 4603 mov r3, r0 +100069c8: 3001 adds r0, #1 +100069ca: 4281 cmp r1, r0 +100069cc: 701a strb r2, [r3, #0] +100069ce: d1fa bne.n 100069c6 +100069d0: 4770 bx lr +100069d2: bf00 nop + +100069d4 : +100069d4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100069d8: 4606 mov r6, r0 +100069da: 460d mov r5, r1 +100069dc: 4604 mov r4, r0 +100069de: b09b sub sp, #108 @ 0x6c +100069e0: f10d 0c28 add.w ip, sp, #40 @ 0x28 +100069e4: f100 0e40 add.w lr, r0, #64 @ 0x40 +100069e8: 4667 mov r7, ip +100069ea: 6820 ldr r0, [r4, #0] +100069ec: 6861 ldr r1, [r4, #4] +100069ee: 68a2 ldr r2, [r4, #8] +100069f0: 68e3 ldr r3, [r4, #12] +100069f2: 3410 adds r4, #16 +100069f4: 4574 cmp r4, lr +100069f6: c70f stmia r7!, {r0, r1, r2, r3} +100069f8: f10c 0c10 add.w ip, ip, #16 +100069fc: d1f4 bne.n 100069e8 +100069fe: 220a movs r2, #10 +10006a00: 9814 ldr r0, [sp, #80] @ 0x50 +10006a02: 9910 ldr r1, [sp, #64] @ 0x40 +10006a04: 9004 str r0, [sp, #16] +10006a06: 9811 ldr r0, [sp, #68] @ 0x44 +10006a08: 9102 str r1, [sp, #8] +10006a0a: 9918 ldr r1, [sp, #96] @ 0x60 +10006a0c: 9001 str r0, [sp, #4] +10006a0e: 9819 ldr r0, [sp, #100] @ 0x64 +10006a10: 9105 str r1, [sp, #20] +10006a12: 9206 str r2, [sp, #24] +10006a14: 9915 ldr r1, [sp, #84] @ 0x54 +10006a16: 9a0f ldr r2, [sp, #60] @ 0x3c +10006a18: 9009 str r0, [sp, #36] @ 0x24 +10006a1a: f8dd e04c ldr.w lr, [sp, #76] @ 0x4c +10006a1e: 4608 mov r0, r1 +10006a20: 9607 str r6, [sp, #28] +10006a22: f8dd b028 ldr.w fp, [sp, #40] @ 0x28 +10006a26: 4616 mov r6, r2 +10006a28: 9b0e ldr r3, [sp, #56] @ 0x38 +10006a2a: 9f16 ldr r7, [sp, #88] @ 0x58 +10006a2c: 9c12 ldr r4, [sp, #72] @ 0x48 +10006a2e: f8dd a02c ldr.w sl, [sp, #44] @ 0x2c +10006a32: f8dd c05c ldr.w ip, [sp, #92] @ 0x5c +10006a36: f8dd 9030 ldr.w r9, [sp, #48] @ 0x30 +10006a3a: f8dd 8034 ldr.w r8, [sp, #52] @ 0x34 +10006a3e: 9905 ldr r1, [sp, #20] +10006a40: 9a09 ldr r2, [sp, #36] @ 0x24 +10006a42: 9508 str r5, [sp, #32] +10006a44: f8cd e00c str.w lr, [sp, #12] +10006a48: 9d02 ldr r5, [sp, #8] +10006a4a: 449b add fp, r3 +10006a4c: 44a9 add r9, r5 +10006a4e: 9d01 ldr r5, [sp, #4] +10006a50: 44b2 add sl, r6 +10006a52: 44a8 add r8, r5 +10006a54: 9d03 ldr r5, [sp, #12] +10006a56: ea87 070b eor.w r7, r7, fp +10006a5a: ea8c 0c0a eor.w ip, ip, sl +10006a5e: eb04 4437 add.w r4, r4, r7, ror #16 +10006a62: eb05 453c add.w r5, r5, ip, ror #16 +10006a66: 9503 str r5, [sp, #12] +10006a68: 4063 eors r3, r4 +10006a6a: 9d04 ldr r5, [sp, #16] +10006a6c: 9304 str r3, [sp, #16] +10006a6e: 9b03 ldr r3, [sp, #12] +10006a70: ea81 0109 eor.w r1, r1, r9 +10006a74: 405e eors r6, r3 +10006a76: 9b02 ldr r3, [sp, #8] +10006a78: eb05 4531 add.w r5, r5, r1, ror #16 +10006a7c: 406b eors r3, r5 +10006a7e: 9302 str r3, [sp, #8] +10006a80: ea82 0208 eor.w r2, r2, r8 +10006a84: 9b01 ldr r3, [sp, #4] +10006a86: eb00 4032 add.w r0, r0, r2, ror #16 +10006a8a: ea83 0e00 eor.w lr, r3, r0 +10006a8e: 9b04 ldr r3, [sp, #16] +10006a90: eb0a 5a36 add.w sl, sl, r6, ror #20 +10006a94: eb0b 5b33 add.w fp, fp, r3, ror #20 +10006a98: 9b02 ldr r3, [sp, #8] +10006a9a: ea8b 4737 eor.w r7, fp, r7, ror #16 +10006a9e: eb09 5933 add.w r9, r9, r3, ror #20 +10006aa2: ea89 4131 eor.w r1, r9, r1, ror #16 +10006aa6: 9b03 ldr r3, [sp, #12] +10006aa8: eb05 6531 add.w r5, r5, r1, ror #24 +10006aac: 9103 str r1, [sp, #12] +10006aae: 9904 ldr r1, [sp, #16] +10006ab0: ea8a 4c3c eor.w ip, sl, ip, ror #16 +10006ab4: eb04 6437 add.w r4, r4, r7, ror #24 +10006ab8: eb03 633c add.w r3, r3, ip, ror #24 +10006abc: ea84 5131 eor.w r1, r4, r1, ror #20 +10006ac0: eb08 583e add.w r8, r8, lr, ror #20 +10006ac4: 9301 str r3, [sp, #4] +10006ac6: ea88 4232 eor.w r2, r8, r2, ror #16 +10006aca: ea83 5636 eor.w r6, r3, r6, ror #20 +10006ace: eb08 6871 add.w r8, r8, r1, ror #25 +10006ad2: 9b02 ldr r3, [sp, #8] +10006ad4: 9102 str r1, [sp, #8] +10006ad6: 9903 ldr r1, [sp, #12] +10006ad8: eb0b 6b76 add.w fp, fp, r6, ror #25 +10006adc: ea85 5333 eor.w r3, r5, r3, ror #20 +10006ae0: ea88 6131 eor.w r1, r8, r1, ror #24 +10006ae4: eb00 6032 add.w r0, r0, r2, ror #24 +10006ae8: ea8b 6232 eor.w r2, fp, r2, ror #24 +10006aec: e9cd 2103 strd r2, r1, [sp, #12] +10006af0: eb0a 6a73 add.w sl, sl, r3, ror #25 +10006af4: eb05 4532 add.w r5, r5, r2, ror #16 +10006af8: 9a01 ldr r2, [sp, #4] +10006afa: ea8a 6737 eor.w r7, sl, r7, ror #24 +10006afe: ea80 5e3e eor.w lr, r0, lr, ror #20 +10006b02: eb02 4231 add.w r2, r2, r1, ror #16 +10006b06: eb00 4037 add.w r0, r0, r7, ror #16 +10006b0a: ea80 6173 eor.w r1, r0, r3, ror #25 +10006b0e: 4613 mov r3, r2 +10006b10: 9a02 ldr r2, [sp, #8] +10006b12: ea85 6676 eor.w r6, r5, r6, ror #25 +10006b16: ea83 6272 eor.w r2, r3, r2, ror #25 +10006b1a: 9205 str r2, [sp, #20] +10006b1c: eb08 5832 add.w r8, r8, r2, ror #20 +10006b20: 9a03 ldr r2, [sp, #12] +10006b22: eb0b 5b36 add.w fp, fp, r6, ror #20 +10006b26: ea8b 4232 eor.w r2, fp, r2, ror #16 +10006b2a: eb09 697e add.w r9, r9, lr, ror #25 +10006b2e: 9201 str r2, [sp, #4] +10006b30: 9a04 ldr r2, [sp, #16] +10006b32: ea89 6c3c eor.w ip, r9, ip, ror #24 +10006b36: eb04 443c add.w r4, r4, ip, ror #16 +10006b3a: 9102 str r1, [sp, #8] +10006b3c: eb0a 5a31 add.w sl, sl, r1, ror #20 +10006b40: ea88 4132 eor.w r1, r8, r2, ror #16 +10006b44: 9a01 ldr r2, [sp, #4] +10006b46: ea84 6e7e eor.w lr, r4, lr, ror #25 +10006b4a: eb05 6532 add.w r5, r5, r2, ror #24 +10006b4e: eb09 593e add.w r9, r9, lr, ror #20 +10006b52: eb03 6231 add.w r2, r3, r1, ror #24 +10006b56: ea8a 4737 eor.w r7, sl, r7, ror #16 +10006b5a: 9b02 ldr r3, [sp, #8] +10006b5c: ea89 4c3c eor.w ip, r9, ip, ror #16 +10006b60: eb00 6037 add.w r0, r0, r7, ror #24 +10006b64: 9504 str r5, [sp, #16] +10006b66: eb04 643c add.w r4, r4, ip, ror #24 +10006b6a: ea85 5636 eor.w r6, r5, r6, ror #20 +10006b6e: ea80 5533 eor.w r5, r0, r3, ror #20 +10006b72: 9203 str r2, [sp, #12] +10006b74: ea4f 6575 mov.w r5, r5, ror #25 +10006b78: 9b05 ldr r3, [sp, #20] +10006b7a: ea84 5e3e eor.w lr, r4, lr, ror #20 +10006b7e: 9502 str r5, [sp, #8] +10006b80: ea4f 657e mov.w r5, lr, ror #25 +10006b84: ea82 5333 eor.w r3, r2, r3, ror #20 +10006b88: 9a01 ldr r2, [sp, #4] +10006b8a: 9501 str r5, [sp, #4] +10006b8c: 9d06 ldr r5, [sp, #24] +10006b8e: ea4f 6232 mov.w r2, r2, ror #24 +10006b92: 3d01 subs r5, #1 +10006b94: ea4f 6676 mov.w r6, r6, ror #25 +10006b98: ea4f 6737 mov.w r7, r7, ror #24 +10006b9c: ea4f 6c3c mov.w ip, ip, ror #24 +10006ba0: ea4f 6131 mov.w r1, r1, ror #24 +10006ba4: ea4f 6373 mov.w r3, r3, ror #25 +10006ba8: 9506 str r5, [sp, #24] +10006baa: f47f af4d bne.w 10006a48 +10006bae: f8dd e00c ldr.w lr, [sp, #12] +10006bb2: e9cd 1005 strd r1, r0, [sp, #20] +10006bb6: 9603 str r6, [sp, #12] +10006bb8: 4610 mov r0, r2 +10006bba: e9dd 6507 ldrd r6, r5, [sp, #28] +10006bbe: 6832 ldr r2, [r6, #0] +10006bc0: 4493 add fp, r2 +10006bc2: 6872 ldr r2, [r6, #4] +10006bc4: f8cd b028 str.w fp, [sp, #40] @ 0x28 +10006bc8: 4492 add sl, r2 +10006bca: 68b2 ldr r2, [r6, #8] +10006bcc: f8cd a02c str.w sl, [sp, #44] @ 0x2c +10006bd0: 4491 add r9, r2 +10006bd2: 68f2 ldr r2, [r6, #12] +10006bd4: f8cd 9030 str.w r9, [sp, #48] @ 0x30 +10006bd8: 4490 add r8, r2 +10006bda: 6932 ldr r2, [r6, #16] +10006bdc: f8cd 8034 str.w r8, [sp, #52] @ 0x34 +10006be0: 4413 add r3, r2 +10006be2: 930e str r3, [sp, #56] @ 0x38 +10006be4: 9a03 ldr r2, [sp, #12] +10006be6: 6973 ldr r3, [r6, #20] +10006be8: 4413 add r3, r2 +10006bea: 930f str r3, [sp, #60] @ 0x3c +10006bec: 9a02 ldr r2, [sp, #8] +10006bee: 69b3 ldr r3, [r6, #24] +10006bf0: 4413 add r3, r2 +10006bf2: 9310 str r3, [sp, #64] @ 0x40 +10006bf4: 9a01 ldr r2, [sp, #4] +10006bf6: 69f3 ldr r3, [r6, #28] +10006bf8: 4413 add r3, r2 +10006bfa: 9311 str r3, [sp, #68] @ 0x44 +10006bfc: 6a33 ldr r3, [r6, #32] +10006bfe: 9a04 ldr r2, [sp, #16] +10006c00: 4423 add r3, r4 +10006c02: 9312 str r3, [sp, #72] @ 0x48 +10006c04: 6a73 ldr r3, [r6, #36] @ 0x24 +10006c06: 4473 add r3, lr +10006c08: 9313 str r3, [sp, #76] @ 0x4c +10006c0a: 6ab3 ldr r3, [r6, #40] @ 0x28 +10006c0c: 4413 add r3, r2 +10006c0e: 9314 str r3, [sp, #80] @ 0x50 +10006c10: 6af3 ldr r3, [r6, #44] @ 0x2c +10006c12: 9a06 ldr r2, [sp, #24] +10006c14: 4413 add r3, r2 +10006c16: 9315 str r3, [sp, #84] @ 0x54 +10006c18: 6b33 ldr r3, [r6, #48] @ 0x30 +10006c1a: 9a05 ldr r2, [sp, #20] +10006c1c: 443b add r3, r7 +10006c1e: 9316 str r3, [sp, #88] @ 0x58 +10006c20: 6b73 ldr r3, [r6, #52] @ 0x34 +10006c22: 4463 add r3, ip +10006c24: 9317 str r3, [sp, #92] @ 0x5c +10006c26: 6bb3 ldr r3, [r6, #56] @ 0x38 +10006c28: 4413 add r3, r2 +10006c2a: 9318 str r3, [sp, #96] @ 0x60 +10006c2c: 6bf3 ldr r3, [r6, #60] @ 0x3c +10006c2e: ae0a add r6, sp, #40 @ 0x28 +10006c30: 4403 add r3, r0 +10006c32: 9319 str r3, [sp, #100] @ 0x64 +10006c34: 4634 mov r4, r6 +10006c36: 3510 adds r5, #16 +10006c38: cc0f ldmia r4!, {r0, r1, r2, r3} +10006c3a: f845 3c04 str.w r3, [r5, #-4] +10006c3e: ab1a add r3, sp, #104 @ 0x68 +10006c40: 429c cmp r4, r3 +10006c42: f106 0610 add.w r6, r6, #16 +10006c46: f845 0c10 str.w r0, [r5, #-16] +10006c4a: f845 1c0c str.w r1, [r5, #-12] +10006c4e: f845 2c08 str.w r2, [r5, #-8] +10006c52: d1ef bne.n 10006c34 +10006c54: 2140 movs r1, #64 @ 0x40 +10006c56: a80a add r0, sp, #40 @ 0x28 +10006c58: f7ff feb2 bl 100069c0 +10006c5c: b01b add sp, #108 @ 0x6c +10006c5e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10006c62: bf00 nop + +10006c64 : +10006c64: b510 push {r4, lr} +10006c66: 2140 movs r1, #64 @ 0x40 +10006c68: 4604 mov r4, r0 +10006c6a: f7ff fea9 bl 100069c0 +10006c6e: 2140 movs r1, #64 @ 0x40 +10006c70: 1860 adds r0, r4, r1 +10006c72: f7ff fea5 bl 100069c0 +10006c76: 2340 movs r3, #64 @ 0x40 +10006c78: f8c4 3080 str.w r3, [r4, #128] @ 0x80 +10006c7c: bd10 pop {r4, pc} +10006c7e: bf00 nop + +10006c80 : +10006c80: b110 cbz r0, 10006c88 +10006c82: 2184 movs r1, #132 @ 0x84 +10006c84: f7ff be9c b.w 100069c0 +10006c88: 4770 bx lr +10006c8a: bf00 nop + +10006c8c : +10006c8c: 4603 mov r3, r0 +10006c8e: f8df c044 ldr.w ip, [pc, #68] @ 10006cd4 +10006c92: 480e ldr r0, [pc, #56] @ (10006ccc ) +10006c94: b500 push {lr} +10006c96: 4a0e ldr r2, [pc, #56] @ (10006cd0 ) +10006c98: e9c3 c000 strd ip, r0, [r3] +10006c9c: f8df e038 ldr.w lr, [pc, #56] @ 10006cd8 +10006ca0: 609a str r2, [r3, #8] +10006ca2: f8c3 e00c str.w lr, [r3, #12] +10006ca6: 680a ldr r2, [r1, #0] +10006ca8: 2000 movs r0, #0 +10006caa: 611a str r2, [r3, #16] +10006cac: 684a ldr r2, [r1, #4] +10006cae: 615a str r2, [r3, #20] +10006cb0: 688a ldr r2, [r1, #8] +10006cb2: 619a str r2, [r3, #24] +10006cb4: 68ca ldr r2, [r1, #12] +10006cb6: 61da str r2, [r3, #28] +10006cb8: 690a ldr r2, [r1, #16] +10006cba: 621a str r2, [r3, #32] +10006cbc: 694a ldr r2, [r1, #20] +10006cbe: 625a str r2, [r3, #36] @ 0x24 +10006cc0: 698a ldr r2, [r1, #24] +10006cc2: 629a str r2, [r3, #40] @ 0x28 +10006cc4: 69ca ldr r2, [r1, #28] +10006cc6: 62da str r2, [r3, #44] @ 0x2c +10006cc8: bd00 pop {pc} +10006cca: bf00 nop +10006ccc: 3320646e .word 0x3320646e +10006cd0: 79622d32 .word 0x79622d32 +10006cd4: 61707865 .word 0x61707865 +10006cd8: 6b206574 .word 0x6b206574 + +10006cdc : +10006cdc: b510 push {r4, lr} +10006cde: 4604 mov r4, r0 +10006ce0: 460b mov r3, r1 +10006ce2: 2140 movs r1, #64 @ 0x40 +10006ce4: 6322 str r2, [r4, #48] @ 0x30 +10006ce6: 681a ldr r2, [r3, #0] +10006ce8: 4408 add r0, r1 +10006cea: 6362 str r2, [r4, #52] @ 0x34 +10006cec: 685a ldr r2, [r3, #4] +10006cee: 63a2 str r2, [r4, #56] @ 0x38 +10006cf0: 689b ldr r3, [r3, #8] +10006cf2: 63e3 str r3, [r4, #60] @ 0x3c +10006cf4: f7ff fe64 bl 100069c0 +10006cf8: 2340 movs r3, #64 @ 0x40 +10006cfa: 2000 movs r0, #0 +10006cfc: f8c4 3080 str.w r3, [r4, #128] @ 0x80 +10006d00: bd10 pop {r4, pc} +10006d02: bf00 nop + +10006d04 : +10006d04: 2900 cmp r1, #0 +10006d06: f000 8138 beq.w 10006f7a +10006d0a: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10006d0e: 2500 movs r5, #0 +10006d10: f8d0 4080 ldr.w r4, [r0, #128] @ 0x80 +10006d14: 1e57 subs r7, r2, #1 +10006d16: 1e5e subs r6, r3, #1 +10006d18: e011 b.n 10006d3e +10006d1a: f89e 4040 ldrb.w r4, [lr, #64] @ 0x40 +10006d1e: f817 cf01 ldrb.w ip, [r7, #1]! +10006d22: 3501 adds r5, #1 +10006d24: ea8c 0c04 eor.w ip, ip, r4 +10006d28: f806 cf01 strb.w ip, [r6, #1]! +10006d2c: f8d0 4080 ldr.w r4, [r0, #128] @ 0x80 +10006d30: 42a9 cmp r1, r5 +10006d32: f104 0401 add.w r4, r4, #1 +10006d36: f8c0 4080 str.w r4, [r0, #128] @ 0x80 +10006d3a: f000 811b beq.w 10006f74 +10006d3e: 2c3f cmp r4, #63 @ 0x3f +10006d40: eb00 0e04 add.w lr, r0, r4 +10006d44: d9e9 bls.n 10006d1a +10006d46: 1b4f subs r7, r1, r5 +10006d48: 2f3f cmp r7, #63 @ 0x3f +10006d4a: 469b mov fp, r3 +10006d4c: 4692 mov sl, r2 +10006d4e: 4604 mov r4, r0 +10006d50: f240 818b bls.w 1000706a +10006d54: f1a7 0840 sub.w r8, r7, #64 @ 0x40 +10006d58: f028 083f bic.w r8, r8, #63 @ 0x3f +10006d5c: f105 0640 add.w r6, r5, #64 @ 0x40 +10006d60: 44b0 add r8, r6 +10006d62: f104 0940 add.w r9, r4, #64 @ 0x40 +10006d66: e000 b.n 10006d6a +10006d68: 3640 adds r6, #64 @ 0x40 +10006d6a: 4649 mov r1, r9 +10006d6c: 4620 mov r0, r4 +10006d6e: f7ff fe31 bl 100069d4 +10006d72: 6b23 ldr r3, [r4, #48] @ 0x30 +10006d74: 6c22 ldr r2, [r4, #64] @ 0x40 +10006d76: 3301 adds r3, #1 +10006d78: 6323 str r3, [r4, #48] @ 0x30 +10006d7a: f85a 3005 ldr.w r3, [sl, r5] +10006d7e: eb0a 0005 add.w r0, sl, r5 +10006d82: 4053 eors r3, r2 +10006d84: f84b 3005 str.w r3, [fp, r5] +10006d88: 6c62 ldr r2, [r4, #68] @ 0x44 +10006d8a: 6843 ldr r3, [r0, #4] +10006d8c: eb0b 0105 add.w r1, fp, r5 +10006d90: 4053 eors r3, r2 +10006d92: 604b str r3, [r1, #4] +10006d94: 6ca2 ldr r2, [r4, #72] @ 0x48 +10006d96: 6883 ldr r3, [r0, #8] +10006d98: 4546 cmp r6, r8 +10006d9a: ea83 0302 eor.w r3, r3, r2 +10006d9e: 608b str r3, [r1, #8] +10006da0: 6ce2 ldr r2, [r4, #76] @ 0x4c +10006da2: 68c3 ldr r3, [r0, #12] +10006da4: 4635 mov r5, r6 +10006da6: ea83 0302 eor.w r3, r3, r2 +10006daa: 60cb str r3, [r1, #12] +10006dac: 6d22 ldr r2, [r4, #80] @ 0x50 +10006dae: 6903 ldr r3, [r0, #16] +10006db0: ea83 0302 eor.w r3, r3, r2 +10006db4: 610b str r3, [r1, #16] +10006db6: 6d62 ldr r2, [r4, #84] @ 0x54 +10006db8: 6943 ldr r3, [r0, #20] +10006dba: ea83 0302 eor.w r3, r3, r2 +10006dbe: 614b str r3, [r1, #20] +10006dc0: 6da2 ldr r2, [r4, #88] @ 0x58 +10006dc2: 6983 ldr r3, [r0, #24] +10006dc4: ea83 0302 eor.w r3, r3, r2 +10006dc8: 618b str r3, [r1, #24] +10006dca: 6de2 ldr r2, [r4, #92] @ 0x5c +10006dcc: 69c3 ldr r3, [r0, #28] +10006dce: ea83 0302 eor.w r3, r3, r2 +10006dd2: 61cb str r3, [r1, #28] +10006dd4: 6e22 ldr r2, [r4, #96] @ 0x60 +10006dd6: 6a03 ldr r3, [r0, #32] +10006dd8: ea83 0302 eor.w r3, r3, r2 +10006ddc: 620b str r3, [r1, #32] +10006dde: 6e62 ldr r2, [r4, #100] @ 0x64 +10006de0: 6a43 ldr r3, [r0, #36] @ 0x24 +10006de2: ea83 0302 eor.w r3, r3, r2 +10006de6: 624b str r3, [r1, #36] @ 0x24 +10006de8: 6a83 ldr r3, [r0, #40] @ 0x28 +10006dea: 6ea2 ldr r2, [r4, #104] @ 0x68 +10006dec: ea83 0302 eor.w r3, r3, r2 +10006df0: 628b str r3, [r1, #40] @ 0x28 +10006df2: 6ee2 ldr r2, [r4, #108] @ 0x6c +10006df4: 6ac3 ldr r3, [r0, #44] @ 0x2c +10006df6: ea83 0302 eor.w r3, r3, r2 +10006dfa: 62cb str r3, [r1, #44] @ 0x2c +10006dfc: 6f22 ldr r2, [r4, #112] @ 0x70 +10006dfe: 6b03 ldr r3, [r0, #48] @ 0x30 +10006e00: ea83 0302 eor.w r3, r3, r2 +10006e04: 630b str r3, [r1, #48] @ 0x30 +10006e06: 6f62 ldr r2, [r4, #116] @ 0x74 +10006e08: 6b43 ldr r3, [r0, #52] @ 0x34 +10006e0a: ea83 0302 eor.w r3, r3, r2 +10006e0e: 634b str r3, [r1, #52] @ 0x34 +10006e10: 6fa2 ldr r2, [r4, #120] @ 0x78 +10006e12: 6b83 ldr r3, [r0, #56] @ 0x38 +10006e14: ea83 0302 eor.w r3, r3, r2 +10006e18: 638b str r3, [r1, #56] @ 0x38 +10006e1a: 6bc3 ldr r3, [r0, #60] @ 0x3c +10006e1c: 6fe2 ldr r2, [r4, #124] @ 0x7c +10006e1e: ea83 0302 eor.w r3, r3, r2 +10006e22: 63cb str r3, [r1, #60] @ 0x3c +10006e24: d1a0 bne.n 10006d68 +10006e26: f017 073f ands.w r7, r7, #63 @ 0x3f +10006e2a: f000 80a3 beq.w 10006f74 +10006e2e: 4649 mov r1, r9 +10006e30: 4620 mov r0, r4 +10006e32: f7ff fdcf bl 100069d4 +10006e36: 6b23 ldr r3, [r4, #48] @ 0x30 +10006e38: 2f03 cmp r7, #3 +10006e3a: f103 0301 add.w r3, r3, #1 +10006e3e: 6323 str r3, [r4, #48] @ 0x30 +10006e40: eb0b 0208 add.w r2, fp, r8 +10006e44: eb0a 0108 add.w r1, sl, r8 +10006e48: f240 809b bls.w 10006f82 +10006e4c: 1f3b subs r3, r7, #4 +10006e4e: 2b0f cmp r3, #15 +10006e50: f240 80fb bls.w 1000704a +10006e54: f108 0504 add.w r5, r8, #4 +10006e58: 4455 add r5, sl +10006e5a: 1cd0 adds r0, r2, #3 +10006e5c: 1b40 subs r0, r0, r5 +10006e5e: 2806 cmp r0, #6 +10006e60: f240 8091 bls.w 10006f86 +10006e64: 1b10 subs r0, r2, r4 +10006e66: 3841 subs r0, #65 @ 0x41 +10006e68: 2806 cmp r0, #6 +10006e6a: f240 808c bls.w 10006f86 +10006e6e: f85a 0008 ldr.w r0, [sl, r8] +10006e72: 6c25 ldr r5, [r4, #64] @ 0x40 +10006e74: 6c66 ldr r6, [r4, #68] @ 0x44 +10006e76: 4045 eors r5, r0 +10006e78: 6848 ldr r0, [r1, #4] +10006e7a: f84b 5008 str.w r5, [fp, r8] +10006e7e: 4070 eors r0, r6 +10006e80: 6050 str r0, [r2, #4] +10006e82: 6888 ldr r0, [r1, #8] +10006e84: 6ca5 ldr r5, [r4, #72] @ 0x48 +10006e86: 6ce6 ldr r6, [r4, #76] @ 0x4c +10006e88: 4045 eors r5, r0 +10006e8a: 68c8 ldr r0, [r1, #12] +10006e8c: 6095 str r5, [r2, #8] +10006e8e: 4070 eors r0, r6 +10006e90: 60d0 str r0, [r2, #12] +10006e92: 0898 lsrs r0, r3, #2 +10006e94: 3001 adds r0, #1 +10006e96: 0845 lsrs r5, r0, #1 +10006e98: 2d02 cmp r5, #2 +10006e9a: d070 beq.n 10006f7e +10006e9c: 6d26 ldr r6, [r4, #80] @ 0x50 +10006e9e: f8d1 c010 ldr.w ip, [r1, #16] +10006ea2: f8d4 e054 ldr.w lr, [r4, #84] @ 0x54 +10006ea6: ea8c 0c06 eor.w ip, ip, r6 +10006eaa: 694e ldr r6, [r1, #20] +10006eac: 2d03 cmp r5, #3 +10006eae: ea86 060e eor.w r6, r6, lr +10006eb2: f8c2 c010 str.w ip, [r2, #16] +10006eb6: 6156 str r6, [r2, #20] +10006eb8: d036 beq.n 10006f28 +10006eba: 6da6 ldr r6, [r4, #88] @ 0x58 +10006ebc: f8d1 c018 ldr.w ip, [r1, #24] +10006ec0: f8d4 e05c ldr.w lr, [r4, #92] @ 0x5c +10006ec4: ea8c 0c06 eor.w ip, ip, r6 +10006ec8: 69ce ldr r6, [r1, #28] +10006eca: 2d04 cmp r5, #4 +10006ecc: ea86 060e eor.w r6, r6, lr +10006ed0: f8c2 c018 str.w ip, [r2, #24] +10006ed4: 61d6 str r6, [r2, #28] +10006ed6: d027 beq.n 10006f28 +10006ed8: 6e26 ldr r6, [r4, #96] @ 0x60 +10006eda: f8d1 c020 ldr.w ip, [r1, #32] +10006ede: f8d4 e064 ldr.w lr, [r4, #100] @ 0x64 +10006ee2: ea8c 0c06 eor.w ip, ip, r6 +10006ee6: 6a4e ldr r6, [r1, #36] @ 0x24 +10006ee8: 2d05 cmp r5, #5 +10006eea: ea86 060e eor.w r6, r6, lr +10006eee: f8c2 c020 str.w ip, [r2, #32] +10006ef2: 6256 str r6, [r2, #36] @ 0x24 +10006ef4: d018 beq.n 10006f28 +10006ef6: 6ea6 ldr r6, [r4, #104] @ 0x68 +10006ef8: f8d1 c028 ldr.w ip, [r1, #40] @ 0x28 +10006efc: f8d4 e06c ldr.w lr, [r4, #108] @ 0x6c +10006f00: ea8c 0c06 eor.w ip, ip, r6 +10006f04: 6ace ldr r6, [r1, #44] @ 0x2c +10006f06: 2d07 cmp r5, #7 +10006f08: ea86 060e eor.w r6, r6, lr +10006f0c: f8c2 c028 str.w ip, [r2, #40] @ 0x28 +10006f10: 62d6 str r6, [r2, #44] @ 0x2c +10006f12: d109 bne.n 10006f28 +10006f14: 6f25 ldr r5, [r4, #112] @ 0x70 +10006f16: 6b0e ldr r6, [r1, #48] @ 0x30 +10006f18: f8d4 c074 ldr.w ip, [r4, #116] @ 0x74 +10006f1c: 406e eors r6, r5 +10006f1e: 6b4d ldr r5, [r1, #52] @ 0x34 +10006f20: 6316 str r6, [r2, #48] @ 0x30 +10006f22: ea85 050c eor.w r5, r5, ip +10006f26: 6355 str r5, [r2, #52] @ 0x34 +10006f28: 07c5 lsls r5, r0, #31 +10006f2a: d507 bpl.n 10006f3c +10006f2c: f020 0001 bic.w r0, r0, #1 +10006f30: 0080 lsls r0, r0, #2 +10006f32: f859 5000 ldr.w r5, [r9, r0] +10006f36: 580e ldr r6, [r1, r0] +10006f38: 4075 eors r5, r6 +10006f3a: 5015 str r5, [r2, r0] +10006f3c: f023 0303 bic.w r3, r3, #3 +10006f40: 3304 adds r3, #4 +10006f42: 42bb cmp r3, r7 +10006f44: d214 bcs.n 10006f70 +10006f46: 5cc8 ldrb r0, [r1, r3] +10006f48: f819 5003 ldrb.w r5, [r9, r3] +10006f4c: 4068 eors r0, r5 +10006f4e: 54d0 strb r0, [r2, r3] +10006f50: 1c58 adds r0, r3, #1 +10006f52: 42b8 cmp r0, r7 +10006f54: d20c bcs.n 10006f70 +10006f56: 5c0d ldrb r5, [r1, r0] +10006f58: f819 6000 ldrb.w r6, [r9, r0] +10006f5c: 3302 adds r3, #2 +10006f5e: 4075 eors r5, r6 +10006f60: 42bb cmp r3, r7 +10006f62: 5415 strb r5, [r2, r0] +10006f64: d204 bcs.n 10006f70 +10006f66: 5cc9 ldrb r1, [r1, r3] +10006f68: f819 0003 ldrb.w r0, [r9, r3] +10006f6c: 4041 eors r1, r0 +10006f6e: 54d1 strb r1, [r2, r3] +10006f70: f8c4 7080 str.w r7, [r4, #128] @ 0x80 +10006f74: 2000 movs r0, #0 +10006f76: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} +10006f7a: 2000 movs r0, #0 +10006f7c: 4770 bx lr +10006f7e: 2010 movs r0, #16 +10006f80: e7d7 b.n 10006f32 +10006f82: 2300 movs r3, #0 +10006f84: e7df b.n 10006f46 +10006f86: 6c25 ldr r5, [r4, #64] @ 0x40 +10006f88: 6808 ldr r0, [r1, #0] +10006f8a: 4068 eors r0, r5 +10006f8c: 6010 str r0, [r2, #0] +10006f8e: 6848 ldr r0, [r1, #4] +10006f90: 6c65 ldr r5, [r4, #68] @ 0x44 +10006f92: 4068 eors r0, r5 +10006f94: 6050 str r0, [r2, #4] +10006f96: 6888 ldr r0, [r1, #8] +10006f98: 6ca5 ldr r5, [r4, #72] @ 0x48 +10006f9a: 2f0f cmp r7, #15 +10006f9c: ea80 0005 eor.w r0, r0, r5 +10006fa0: 6090 str r0, [r2, #8] +10006fa2: d9cb bls.n 10006f3c +10006fa4: 68c8 ldr r0, [r1, #12] +10006fa6: 6ce5 ldr r5, [r4, #76] @ 0x4c +10006fa8: 2f13 cmp r7, #19 +10006faa: ea80 0005 eor.w r0, r0, r5 +10006fae: 60d0 str r0, [r2, #12] +10006fb0: d9c4 bls.n 10006f3c +10006fb2: 6908 ldr r0, [r1, #16] +10006fb4: 6d25 ldr r5, [r4, #80] @ 0x50 +10006fb6: 2f17 cmp r7, #23 +10006fb8: ea80 0005 eor.w r0, r0, r5 +10006fbc: 6110 str r0, [r2, #16] +10006fbe: d9bd bls.n 10006f3c +10006fc0: 6948 ldr r0, [r1, #20] +10006fc2: 6d65 ldr r5, [r4, #84] @ 0x54 +10006fc4: 2f1b cmp r7, #27 +10006fc6: ea80 0005 eor.w r0, r0, r5 +10006fca: 6150 str r0, [r2, #20] +10006fcc: d9b6 bls.n 10006f3c +10006fce: 6988 ldr r0, [r1, #24] +10006fd0: 6da5 ldr r5, [r4, #88] @ 0x58 +10006fd2: 2f1f cmp r7, #31 +10006fd4: ea80 0005 eor.w r0, r0, r5 +10006fd8: 6190 str r0, [r2, #24] +10006fda: d9af bls.n 10006f3c +10006fdc: 69c8 ldr r0, [r1, #28] +10006fde: 6de5 ldr r5, [r4, #92] @ 0x5c +10006fe0: 2f23 cmp r7, #35 @ 0x23 +10006fe2: ea80 0005 eor.w r0, r0, r5 +10006fe6: 61d0 str r0, [r2, #28] +10006fe8: d9a8 bls.n 10006f3c +10006fea: 6a08 ldr r0, [r1, #32] +10006fec: 6e25 ldr r5, [r4, #96] @ 0x60 +10006fee: 2f27 cmp r7, #39 @ 0x27 +10006ff0: ea80 0005 eor.w r0, r0, r5 +10006ff4: 6210 str r0, [r2, #32] +10006ff6: d9a1 bls.n 10006f3c +10006ff8: 6a48 ldr r0, [r1, #36] @ 0x24 +10006ffa: 6e65 ldr r5, [r4, #100] @ 0x64 +10006ffc: 2f2b cmp r7, #43 @ 0x2b +10006ffe: ea80 0005 eor.w r0, r0, r5 +10007002: 6250 str r0, [r2, #36] @ 0x24 +10007004: d99a bls.n 10006f3c +10007006: 6a88 ldr r0, [r1, #40] @ 0x28 +10007008: 6ea5 ldr r5, [r4, #104] @ 0x68 +1000700a: 2f2f cmp r7, #47 @ 0x2f +1000700c: ea80 0005 eor.w r0, r0, r5 +10007010: 6290 str r0, [r2, #40] @ 0x28 +10007012: d993 bls.n 10006f3c +10007014: 6ac8 ldr r0, [r1, #44] @ 0x2c +10007016: 6ee5 ldr r5, [r4, #108] @ 0x6c +10007018: 2f33 cmp r7, #51 @ 0x33 +1000701a: ea80 0005 eor.w r0, r0, r5 +1000701e: 62d0 str r0, [r2, #44] @ 0x2c +10007020: d98c bls.n 10006f3c +10007022: 6b08 ldr r0, [r1, #48] @ 0x30 +10007024: 6f25 ldr r5, [r4, #112] @ 0x70 +10007026: 2f37 cmp r7, #55 @ 0x37 +10007028: ea80 0005 eor.w r0, r0, r5 +1000702c: 6310 str r0, [r2, #48] @ 0x30 +1000702e: d985 bls.n 10006f3c +10007030: 6b48 ldr r0, [r1, #52] @ 0x34 +10007032: 6f65 ldr r5, [r4, #116] @ 0x74 +10007034: 2f3b cmp r7, #59 @ 0x3b +10007036: ea80 0005 eor.w r0, r0, r5 +1000703a: 6350 str r0, [r2, #52] @ 0x34 +1000703c: f67f af7e bls.w 10006f3c +10007040: 6fa0 ldr r0, [r4, #120] @ 0x78 +10007042: 6b8d ldr r5, [r1, #56] @ 0x38 +10007044: 4068 eors r0, r5 +10007046: 6390 str r0, [r2, #56] @ 0x38 +10007048: e778 b.n 10006f3c +1000704a: 6808 ldr r0, [r1, #0] +1000704c: 6c25 ldr r5, [r4, #64] @ 0x40 +1000704e: 2f07 cmp r7, #7 +10007050: ea80 0005 eor.w r0, r0, r5 +10007054: 6010 str r0, [r2, #0] +10007056: f67f af71 bls.w 10006f3c +1000705a: 6848 ldr r0, [r1, #4] +1000705c: 6c65 ldr r5, [r4, #68] @ 0x44 +1000705e: 2f0b cmp r7, #11 +10007060: ea80 0005 eor.w r0, r0, r5 +10007064: 6050 str r0, [r2, #4] +10007066: d896 bhi.n 10006f96 +10007068: e768 b.n 10006f3c +1000706a: 46a8 mov r8, r5 +1000706c: f100 0940 add.w r9, r0, #64 @ 0x40 +10007070: e6dd b.n 10006e2e +10007072: bf00 nop + +10007074 : +10007074: b5f0 push {r4, r5, r6, r7, lr} +10007076: 4615 mov r5, r2 +10007078: 4604 mov r4, r0 +1000707a: 460e mov r6, r1 +1000707c: b0a3 sub sp, #140 @ 0x8c +1000707e: a801 add r0, sp, #4 +10007080: 2140 movs r1, #64 @ 0x40 +10007082: 461f mov r7, r3 +10007084: f7ff fc9c bl 100069c0 +10007088: a811 add r0, sp, #68 @ 0x44 +1000708a: 2140 movs r1, #64 @ 0x40 +1000708c: f7ff fc98 bl 100069c0 +10007090: 950d str r5, [sp, #52] @ 0x34 +10007092: 2540 movs r5, #64 @ 0x40 +10007094: 4a1a ldr r2, [pc, #104] @ (10007100 ) +10007096: 4b1b ldr r3, [pc, #108] @ (10007104 ) +10007098: 4629 mov r1, r5 +1000709a: e9cd 2301 strd r2, r3, [sp, #4] +1000709e: 4b1a ldr r3, [pc, #104] @ (10007108 ) +100070a0: a811 add r0, sp, #68 @ 0x44 +100070a2: 9303 str r3, [sp, #12] +100070a4: f1a3 6364 sub.w r3, r3, #239075328 @ 0xe400000 +100070a8: f5a3 33e3 sub.w r3, r3, #116224 @ 0x1c600 +100070ac: f5a3 73df sub.w r3, r3, #446 @ 0x1be +100070b0: 9304 str r3, [sp, #16] +100070b2: 6863 ldr r3, [r4, #4] +100070b4: 9521 str r5, [sp, #132] @ 0x84 +100070b6: 9306 str r3, [sp, #24] +100070b8: 68a3 ldr r3, [r4, #8] +100070ba: 9307 str r3, [sp, #28] +100070bc: 68e3 ldr r3, [r4, #12] +100070be: 9308 str r3, [sp, #32] +100070c0: 6923 ldr r3, [r4, #16] +100070c2: 9309 str r3, [sp, #36] @ 0x24 +100070c4: 6963 ldr r3, [r4, #20] +100070c6: 930a str r3, [sp, #40] @ 0x28 +100070c8: 69a3 ldr r3, [r4, #24] +100070ca: 930b str r3, [sp, #44] @ 0x2c +100070cc: 69e3 ldr r3, [r4, #28] +100070ce: 930c str r3, [sp, #48] @ 0x30 +100070d0: 6823 ldr r3, [r4, #0] +100070d2: 9305 str r3, [sp, #20] +100070d4: 6833 ldr r3, [r6, #0] +100070d6: 930e str r3, [sp, #56] @ 0x38 +100070d8: 6873 ldr r3, [r6, #4] +100070da: 930f str r3, [sp, #60] @ 0x3c +100070dc: 68b3 ldr r3, [r6, #8] +100070de: 9310 str r3, [sp, #64] @ 0x40 +100070e0: f7ff fc6e bl 100069c0 +100070e4: e9dd 2328 ldrd r2, r3, [sp, #160] @ 0xa0 +100070e8: 4639 mov r1, r7 +100070ea: a801 add r0, sp, #4 +100070ec: 9521 str r5, [sp, #132] @ 0x84 +100070ee: f7ff fe09 bl 10006d04 +100070f2: a801 add r0, sp, #4 +100070f4: 2184 movs r1, #132 @ 0x84 +100070f6: f7ff fc63 bl 100069c0 +100070fa: 2000 movs r0, #0 +100070fc: b023 add sp, #140 @ 0x8c +100070fe: bdf0 pop {r4, r5, r6, r7, pc} +10007100: 61707865 .word 0x61707865 +10007104: 3320646e .word 0x3320646e +10007108: 79622d32 .word 0x79622d32 + +1000710c : +1000710c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10007110: 4e50 ldr r6, [pc, #320] @ (10007254 ) +10007112: f5ad 7d09 sub.w sp, sp, #548 @ 0x224 +10007116: 9005 str r0, [sp, #20] +10007118: f106 0808 add.w r8, r6, #8 +1000711c: f106 0510 add.w r5, r6, #16 +10007120: f106 0750 add.w r7, r6, #80 @ 0x50 +10007124: f106 0a68 add.w sl, r6, #104 @ 0x68 +10007128: f506 7956 add.w r9, r6, #856 @ 0x358 +1000712c: 2800 cmp r0, #0 +1000712e: f040 8081 bne.w 10007234 +10007132: ab17 add r3, sp, #92 @ 0x5c +10007134: 9301 str r3, [sp, #4] +10007136: ab28 add r3, sp, #160 @ 0xa0 +10007138: 9003 str r0, [sp, #12] +1000713a: ac07 add r4, sp, #28 +1000713c: 9302 str r3, [sp, #8] +1000713e: 6833 ldr r3, [r6, #0] +10007140: 2140 movs r1, #64 @ 0x40 +10007142: 4620 mov r0, r4 +10007144: f8d8 b000 ldr.w fp, [r8] +10007148: 9304 str r3, [sp, #16] +1000714a: f7ff fc39 bl 100069c0 +1000714e: 2140 movs r1, #64 @ 0x40 +10007150: 9801 ldr r0, [sp, #4] +10007152: f7ff fc35 bl 100069c0 +10007156: 9b04 ldr r3, [sp, #16] +10007158: 4a3f ldr r2, [pc, #252] @ (10007258 ) +1000715a: 6323 str r3, [r4, #48] @ 0x30 +1000715c: 2340 movs r3, #64 @ 0x40 +1000715e: f8c4 3080 str.w r3, [r4, #128] @ 0x80 +10007162: 4b3e ldr r3, [pc, #248] @ (1000725c ) +10007164: 2140 movs r1, #64 @ 0x40 +10007166: e9c4 3200 strd r3, r2, [r4] +1000716a: 686b ldr r3, [r5, #4] +1000716c: 4a3c ldr r2, [pc, #240] @ (10007260 ) +1000716e: 6163 str r3, [r4, #20] +10007170: 68ab ldr r3, [r5, #8] +10007172: 60a2 str r2, [r4, #8] +10007174: 61a3 str r3, [r4, #24] +10007176: 68eb ldr r3, [r5, #12] +10007178: f1a2 6264 sub.w r2, r2, #239075328 @ 0xe400000 +1000717c: 61e3 str r3, [r4, #28] +1000717e: 692b ldr r3, [r5, #16] +10007180: f5a2 32e3 sub.w r2, r2, #116224 @ 0x1c600 +10007184: 6223 str r3, [r4, #32] +10007186: 696b ldr r3, [r5, #20] +10007188: f5a2 72df sub.w r2, r2, #446 @ 0x1be +1000718c: 6263 str r3, [r4, #36] @ 0x24 +1000718e: 69ab ldr r3, [r5, #24] +10007190: 9801 ldr r0, [sp, #4] +10007192: 62a3 str r3, [r4, #40] @ 0x28 +10007194: 69eb ldr r3, [r5, #28] +10007196: 60e2 str r2, [r4, #12] +10007198: 62e3 str r3, [r4, #44] @ 0x2c +1000719a: 682b ldr r3, [r5, #0] +1000719c: 3604 adds r6, #4 +1000719e: 6123 str r3, [r4, #16] +100071a0: 683b ldr r3, [r7, #0] +100071a2: f108 0804 add.w r8, r8, #4 +100071a6: 6363 str r3, [r4, #52] @ 0x34 +100071a8: 687b ldr r3, [r7, #4] +100071aa: 63a3 str r3, [r4, #56] @ 0x38 +100071ac: 68bb ldr r3, [r7, #8] +100071ae: 63e3 str r3, [r4, #60] @ 0x3c +100071b0: f7ff fc06 bl 100069c0 +100071b4: 2340 movs r3, #64 @ 0x40 +100071b6: 4652 mov r2, sl +100071b8: 4659 mov r1, fp +100071ba: f8c4 3080 str.w r3, [r4, #128] @ 0x80 +100071be: 4620 mov r0, r4 +100071c0: 9b02 ldr r3, [sp, #8] +100071c2: f7ff fd9f bl 10006d04 +100071c6: 2184 movs r1, #132 @ 0x84 +100071c8: 4620 mov r0, r4 +100071ca: f7ff fbf9 bl 100069c0 +100071ce: 465a mov r2, fp +100071d0: 4649 mov r1, r9 +100071d2: 9802 ldr r0, [sp, #8] +100071d4: f004 fdea bl 1000bdac +100071d8: 9b05 ldr r3, [sp, #20] +100071da: 4683 mov fp, r0 +100071dc: bb90 cbnz r0, 10007244 +100071de: b963 cbnz r3, 100071fa +100071e0: 9b03 ldr r3, [sp, #12] +100071e2: 3520 adds r5, #32 +100071e4: 370c adds r7, #12 +100071e6: f20a 1a77 addw sl, sl, #375 @ 0x177 +100071ea: f209 1977 addw r9, r9, #375 @ 0x177 +100071ee: b18b cbz r3, 10007214 +100071f0: 4658 mov r0, fp +100071f2: f50d 7d09 add.w sp, sp, #548 @ 0x224 +100071f6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100071fa: 481a ldr r0, [pc, #104] @ (10007264 ) +100071fc: f7fc fad4 bl 100037a8 <__wrap_puts> +10007200: 9b03 ldr r3, [sp, #12] +10007202: b153 cbz r3, 1000721a +10007204: 200a movs r0, #10 +10007206: f7fc fa8d bl 10003724 <__wrap_putchar> +1000720a: 4658 mov r0, fp +1000720c: f50d 7d09 add.w sp, sp, #548 @ 0x224 +10007210: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10007214: 2301 movs r3, #1 +10007216: 9303 str r3, [sp, #12] +10007218: e791 b.n 1000713e +1000721a: 2301 movs r3, #1 +1000721c: 3520 adds r5, #32 +1000721e: 370c adds r7, #12 +10007220: f20a 1a77 addw sl, sl, #375 @ 0x177 +10007224: f209 1977 addw r9, r9, #375 @ 0x177 +10007228: 9303 str r3, [sp, #12] +1000722a: 9903 ldr r1, [sp, #12] +1000722c: 480e ldr r0, [pc, #56] @ (10007268 ) +1000722e: f7fc fb39 bl 100038a4 <__wrap_printf> +10007232: e784 b.n 1000713e +10007234: 2300 movs r3, #0 +10007236: 9303 str r3, [sp, #12] +10007238: ab17 add r3, sp, #92 @ 0x5c +1000723a: 9301 str r3, [sp, #4] +1000723c: ab28 add r3, sp, #160 @ 0xa0 +1000723e: ac07 add r4, sp, #28 +10007240: 9302 str r3, [sp, #8] +10007242: e7f2 b.n 1000722a +10007244: b913 cbnz r3, 1000724c +10007246: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff +1000724a: e7d1 b.n 100071f0 +1000724c: 4807 ldr r0, [pc, #28] @ (1000726c ) +1000724e: f7fc faab bl 100037a8 <__wrap_puts> +10007252: e7f8 b.n 10007246 +10007254: 1000d02c .word 0x1000d02c +10007258: 3320646e .word 0x3320646e +1000725c: 61707865 .word 0x61707865 +10007260: 79622d32 .word 0x79622d32 +10007264: 1000c748 .word 0x1000c748 +10007268: 1000c7b8 .word 0x1000c7b8 +1000726c: 1000c7cc .word 0x1000c7cc + +10007270 : +10007270: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10007274: 4604 mov r4, r0 +10007276: 2000 movs r0, #0 +10007278: 684b ldr r3, [r1, #4] +1000727a: 6a65 ldr r5, [r4, #36] @ 0x24 +1000727c: 680f ldr r7, [r1, #0] +1000727e: 195b adds r3, r3, r5 +10007280: 6a25 ldr r5, [r4, #32] +10007282: eb40 0600 adc.w r6, r0, r0 +10007286: eb15 0807 adds.w r8, r5, r7 +1000728a: eb40 0500 adc.w r5, r0, r0 +1000728e: 18eb adds r3, r5, r3 +10007290: 68e5 ldr r5, [r4, #12] +10007292: 68cf ldr r7, [r1, #12] +10007294: eb05 0995 add.w r9, r5, r5, lsr #2 +10007298: 688d ldr r5, [r1, #8] +1000729a: 6aa1 ldr r1, [r4, #40] @ 0x28 +1000729c: f146 0600 adc.w r6, r6, #0 +100072a0: 1869 adds r1, r5, r1 +100072a2: 68a5 ldr r5, [r4, #8] +100072a4: b083 sub sp, #12 +100072a6: eb05 0a95 add.w sl, r5, r5, lsr #2 +100072aa: eb40 0500 adc.w r5, r0, r0 +100072ae: 1876 adds r6, r6, r1 +100072b0: 6ae1 ldr r1, [r4, #44] @ 0x2c +100072b2: f145 0500 adc.w r5, r5, #0 +100072b6: 187f adds r7, r7, r1 +100072b8: 6861 ldr r1, [r4, #4] +100072ba: eb40 0e00 adc.w lr, r0, r0 +100072be: eb01 0c91 add.w ip, r1, r1, lsr #2 +100072c2: 6b21 ldr r1, [r4, #48] @ 0x30 +100072c4: 19ed adds r5, r5, r7 +100072c6: 440a add r2, r1 +100072c8: eb42 0b0e adc.w fp, r2, lr +100072cc: fba3 1209 umull r1, r2, r3, r9 +100072d0: 6827 ldr r7, [r4, #0] +100072d2: 9500 str r5, [sp, #0] +100072d4: fbe8 1207 umlal r1, r2, r8, r7 +100072d8: fbe6 120a umlal r1, r2, r6, sl +100072dc: fbe5 120c umlal r1, r2, r5, ip +100072e0: 9101 str r1, [sp, #4] +100072e2: fba7 1703 umull r1, r7, r7, r3 +100072e6: 6865 ldr r5, [r4, #4] +100072e8: fbe8 1705 umlal r1, r7, r8, r5 +100072ec: fbe9 1706 umlal r1, r7, r9, r6 +100072f0: 9d00 ldr r5, [sp, #0] +100072f2: fbea 1705 umlal r1, r7, sl, r5 +100072f6: 1889 adds r1, r1, r2 +100072f8: 6862 ldr r2, [r4, #4] +100072fa: f147 0700 adc.w r7, r7, #0 +100072fe: fbec 170b umlal r1, r7, ip, fp +10007302: fba3 ce02 umull ip, lr, r3, r2 +10007306: 68a2 ldr r2, [r4, #8] +10007308: 68e5 ldr r5, [r4, #12] +1000730a: fbe8 ce02 umlal ip, lr, r8, r2 +1000730e: fba3 3202 umull r3, r2, r3, r2 +10007312: fbe8 3205 umlal r3, r2, r8, r5 +10007316: 6865 ldr r5, [r4, #4] +10007318: fbe6 3205 umlal r3, r2, r6, r5 +1000731c: 6825 ldr r5, [r4, #0] +1000731e: fbe5 ce06 umlal ip, lr, r5, r6 +10007322: 9e00 ldr r6, [sp, #0] +10007324: fbe9 ce06 umlal ip, lr, r9, r6 +10007328: fbe5 3206 umlal r3, r2, r5, r6 +1000732c: fbea ce0b umlal ip, lr, sl, fp +10007330: fbe9 320b umlal r3, r2, r9, fp +10007334: eb17 0c0c adds.w ip, r7, ip +10007338: f14e 0e00 adc.w lr, lr, #0 +1000733c: eb1e 0303 adds.w r3, lr, r3 +10007340: f142 0500 adc.w r5, r2, #0 +10007344: 6822 ldr r2, [r4, #0] +10007346: 9f01 ldr r7, [sp, #4] +10007348: fb0b 5502 mla r5, fp, r2, r5 +1000734c: f025 0603 bic.w r6, r5, #3 +10007350: 08aa lsrs r2, r5, #2 +10007352: 1992 adds r2, r2, r6 +10007354: eb40 0600 adc.w r6, r0, r0 +10007358: 19d2 adds r2, r2, r7 +1000735a: 6222 str r2, [r4, #32] +1000735c: f146 0200 adc.w r2, r6, #0 +10007360: 1889 adds r1, r1, r2 +10007362: eb40 0200 adc.w r2, r0, r0 +10007366: eb1c 0202 adds.w r2, ip, r2 +1000736a: 4140 adcs r0, r0 +1000736c: 181b adds r3, r3, r0 +1000736e: f005 0503 and.w r5, r5, #3 +10007372: f145 0500 adc.w r5, r5, #0 +10007376: e9c4 230a strd r2, r3, [r4, #40] @ 0x28 +1000737a: 6261 str r1, [r4, #36] @ 0x24 +1000737c: 6325 str r5, [r4, #48] @ 0x30 +1000737e: b003 add sp, #12 +10007380: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +10007384 : +10007384: 2148 movs r1, #72 @ 0x48 +10007386: f7ff bb1b b.w 100069c0 +1000738a: bf00 nop + +1000738c : +1000738c: b110 cbz r0, 10007394 +1000738e: 2148 movs r1, #72 @ 0x48 +10007390: f7ff bb16 b.w 100069c0 +10007394: 4770 bx lr +10007396: bf00 nop + +10007398 : +10007398: b538 push {r3, r4, r5, lr} +1000739a: 460b mov r3, r1 +1000739c: 4604 mov r4, r0 +1000739e: 2500 movs r5, #0 +100073a0: 681a ldr r2, [r3, #0] +100073a2: 4811 ldr r0, [pc, #68] @ (100073e8 ) +100073a4: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000 +100073a8: 6022 str r2, [r4, #0] +100073aa: 685a ldr r2, [r3, #4] +100073ac: 2110 movs r1, #16 +100073ae: 4002 ands r2, r0 +100073b0: 6062 str r2, [r4, #4] +100073b2: 689a ldr r2, [r3, #8] +100073b4: 4002 ands r2, r0 +100073b6: 60a2 str r2, [r4, #8] +100073b8: 68da ldr r2, [r3, #12] +100073ba: 4002 ands r2, r0 +100073bc: 60e2 str r2, [r4, #12] +100073be: 691a ldr r2, [r3, #16] +100073c0: f104 0034 add.w r0, r4, #52 @ 0x34 +100073c4: 6122 str r2, [r4, #16] +100073c6: 695a ldr r2, [r3, #20] +100073c8: 6162 str r2, [r4, #20] +100073ca: 699a ldr r2, [r3, #24] +100073cc: 61a2 str r2, [r4, #24] +100073ce: 69db ldr r3, [r3, #28] +100073d0: e9c4 5509 strd r5, r5, [r4, #36] @ 0x24 +100073d4: e9c4 3507 strd r3, r5, [r4, #28] +100073d8: e9c4 550b strd r5, r5, [r4, #44] @ 0x2c +100073dc: f7ff faf0 bl 100069c0 +100073e0: 4628 mov r0, r5 +100073e2: 6465 str r5, [r4, #68] @ 0x44 +100073e4: bd38 pop {r3, r4, r5, pc} +100073e6: bf00 nop +100073e8: 0ffffffc .word 0x0ffffffc + +100073ec : +100073ec: b1ca cbz r2, 10007422 +100073ee: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100073f2: 6c46 ldr r6, [r0, #68] @ 0x44 +100073f4: 4613 mov r3, r2 +100073f6: 460f mov r7, r1 +100073f8: 4604 mov r4, r0 +100073fa: b08d sub sp, #52 @ 0x34 +100073fc: b19e cbz r6, 10007426 +100073fe: f1c6 0510 rsb r5, r6, #16 +10007402: f106 0034 add.w r0, r6, #52 @ 0x34 +10007406: 42aa cmp r2, r5 +10007408: 4420 add r0, r4 +1000740a: 9200 str r2, [sp, #0] +1000740c: d218 bcs.n 10007440 +1000740e: f004 fdb5 bl 1000bf7c +10007412: 2000 movs r0, #0 +10007414: 6c62 ldr r2, [r4, #68] @ 0x44 +10007416: 9b00 ldr r3, [sp, #0] +10007418: 441a add r2, r3 +1000741a: 6462 str r2, [r4, #68] @ 0x44 +1000741c: b00d add sp, #52 @ 0x34 +1000741e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10007422: 2000 movs r0, #0 +10007424: 4770 bx lr +10007426: 2a0f cmp r2, #15 +10007428: d820 bhi.n 1000746c +1000742a: 461a mov r2, r3 +1000742c: 4639 mov r1, r7 +1000742e: 6463 str r3, [r4, #68] @ 0x44 +10007430: f104 0034 add.w r0, r4, #52 @ 0x34 +10007434: f004 fda2 bl 1000bf7c +10007438: 2000 movs r0, #0 +1000743a: b00d add sp, #52 @ 0x34 +1000743c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10007440: 462a mov r2, r5 +10007442: f004 fd9b bl 1000bf7c +10007446: 2200 movs r2, #0 +10007448: 4620 mov r0, r4 +1000744a: 6462 str r2, [r4, #68] @ 0x44 +1000744c: f104 0134 add.w r1, r4, #52 @ 0x34 +10007450: 2201 movs r2, #1 +10007452: f7ff ff0d bl 10007270 +10007456: 9b00 ldr r3, [sp, #0] +10007458: f1a6 0210 sub.w r2, r6, #16 +1000745c: 4413 add r3, r2 +1000745e: 2b0f cmp r3, #15 +10007460: f200 80b7 bhi.w 100075d2 +10007464: 2b00 cmp r3, #0 +10007466: d0e7 beq.n 10007438 +10007468: 442f add r7, r5 +1000746a: e7de b.n 1000742a +1000746c: 4688 mov r8, r1 +1000746e: e9d4 ce0a ldrd ip, lr, [r4, #40] @ 0x28 +10007472: 6862 ldr r2, [r4, #4] +10007474: 68a1 ldr r1, [r4, #8] +10007476: 9200 str r2, [sp, #0] +10007478: 6a22 ldr r2, [r4, #32] +1000747a: e9cd 1101 strd r1, r1, [sp, #4] +1000747e: 9204 str r2, [sp, #16] +10007480: 6a62 ldr r2, [r4, #36] @ 0x24 +10007482: 68e1 ldr r1, [r4, #12] +10007484: 9207 str r2, [sp, #28] +10007486: 9a01 ldr r2, [sp, #4] +10007488: 9105 str r1, [sp, #20] +1000748a: eb01 0a91 add.w sl, r1, r1, lsr #2 +1000748e: eb02 0192 add.w r1, r2, r2, lsr #2 +10007492: 9a00 ldr r2, [sp, #0] +10007494: f023 000f bic.w r0, r3, #15 +10007498: eb02 0292 add.w r2, r2, r2, lsr #2 +1000749c: 9203 str r2, [sp, #12] +1000749e: eb08 0200 add.w r2, r8, r0 +100074a2: 9206 str r2, [sp, #24] +100074a4: 2500 movs r5, #0 +100074a6: 9a07 ldr r2, [sp, #28] +100074a8: 9007 str r0, [sp, #28] +100074aa: 4660 mov r0, ip +100074ac: e9cd 7309 strd r7, r3, [sp, #36] @ 0x24 +100074b0: 9101 str r1, [sp, #4] +100074b2: f8d4 b000 ldr.w fp, [r4] +100074b6: f8d4 9030 ldr.w r9, [r4, #48] @ 0x30 +100074ba: 9904 ldr r1, [sp, #16] +100074bc: 9608 str r6, [sp, #32] +100074be: 940b str r4, [sp, #44] @ 0x2c +100074c0: f8d8 3000 ldr.w r3, [r8] +100074c4: f8d8 c008 ldr.w ip, [r8, #8] +100074c8: 18cc adds r4, r1, r3 +100074ca: f8d8 3004 ldr.w r3, [r8, #4] +100074ce: eb45 0105 adc.w r1, r5, r5 +100074d2: 185b adds r3, r3, r1 +100074d4: eb45 0105 adc.w r1, r5, r5 +100074d8: 18d2 adds r2, r2, r3 +100074da: f141 0100 adc.w r1, r1, #0 +100074de: eb1c 0c01 adds.w ip, ip, r1 +100074e2: eb45 0305 adc.w r3, r5, r5 +100074e6: eb10 0c0c adds.w ip, r0, ip +100074ea: f143 0100 adc.w r1, r3, #0 +100074ee: f8d8 300c ldr.w r3, [r8, #12] +100074f2: 9f01 ldr r7, [sp, #4] +100074f4: 185b adds r3, r3, r1 +100074f6: eb45 0105 adc.w r1, r5, r5 +100074fa: eb1e 0e03 adds.w lr, lr, r3 +100074fe: f141 0101 adc.w r1, r1, #1 +10007502: 4489 add r9, r1 +10007504: fba2 130a umull r1, r3, r2, sl +10007508: fbe4 130b umlal r1, r3, r4, fp +1000750c: fbec 1307 umlal r1, r3, ip, r7 +10007510: 9803 ldr r0, [sp, #12] +10007512: f108 0810 add.w r8, r8, #16 +10007516: fbee 1300 umlal r1, r3, lr, r0 +1000751a: fba2 600b umull r6, r0, r2, fp +1000751e: 9104 str r1, [sp, #16] +10007520: 9900 ldr r1, [sp, #0] +10007522: fbe4 6001 umlal r6, r0, r4, r1 +10007526: fbec 600a umlal r6, r0, ip, sl +1000752a: fbee 6007 umlal r6, r0, lr, r7 +1000752e: 18f6 adds r6, r6, r3 +10007530: 9b03 ldr r3, [sp, #12] +10007532: f140 0000 adc.w r0, r0, #0 +10007536: fbe9 6003 umlal r6, r0, r9, r3 +1000753a: fba2 3701 umull r3, r7, r2, r1 +1000753e: 9902 ldr r1, [sp, #8] +10007540: fbe4 3701 umlal r3, r7, r4, r1 +10007544: fbec 370b umlal r3, r7, ip, fp +10007548: fbee 370a umlal r3, r7, lr, sl +1000754c: 9901 ldr r1, [sp, #4] +1000754e: fbe9 3701 umlal r3, r7, r9, r1 +10007552: 18c0 adds r0, r0, r3 +10007554: 9b02 ldr r3, [sp, #8] +10007556: 9905 ldr r1, [sp, #20] +10007558: fba2 3203 umull r3, r2, r2, r3 +1000755c: fbe4 3201 umlal r3, r2, r4, r1 +10007560: 9900 ldr r1, [sp, #0] +10007562: f147 0700 adc.w r7, r7, #0 +10007566: fbec 3201 umlal r3, r2, ip, r1 +1000756a: fbee 320b umlal r3, r2, lr, fp +1000756e: fbe9 320a umlal r3, r2, r9, sl +10007572: 18fb adds r3, r7, r3 +10007574: f142 0200 adc.w r2, r2, #0 +10007578: fb09 290b mla r9, r9, fp, r2 +1000757c: 9904 ldr r1, [sp, #16] +1000757e: f029 0203 bic.w r2, r9, #3 +10007582: ea4f 0499 mov.w r4, r9, lsr #2 +10007586: 18a4 adds r4, r4, r2 +10007588: eb45 0205 adc.w r2, r5, r5 +1000758c: 1864 adds r4, r4, r1 +1000758e: f142 0200 adc.w r2, r2, #0 +10007592: 18b2 adds r2, r6, r2 +10007594: 4621 mov r1, r4 +10007596: eb45 0405 adc.w r4, r5, r5 +1000759a: 1900 adds r0, r0, r4 +1000759c: eb45 0e05 adc.w lr, r5, r5 +100075a0: eb13 0e0e adds.w lr, r3, lr +100075a4: 9b06 ldr r3, [sp, #24] +100075a6: f009 0903 and.w r9, r9, #3 +100075aa: f149 0900 adc.w r9, r9, #0 +100075ae: 4543 cmp r3, r8 +100075b0: d186 bne.n 100074c0 +100075b2: e9dd 7309 ldrd r7, r3, [sp, #36] @ 0x24 +100075b6: 4684 mov ip, r0 +100075b8: 9c0b ldr r4, [sp, #44] @ 0x2c +100075ba: 9e08 ldr r6, [sp, #32] +100075bc: 9807 ldr r0, [sp, #28] +100075be: e9c4 1208 strd r1, r2, [r4, #32] +100075c2: e9c4 ce0a strd ip, lr, [r4, #40] @ 0x28 +100075c6: f8c4 9030 str.w r9, [r4, #48] @ 0x30 +100075ca: 1835 adds r5, r6, r0 +100075cc: f003 030f and.w r3, r3, #15 +100075d0: e748 b.n 10007464 +100075d2: 462e mov r6, r5 +100075d4: eb07 0805 add.w r8, r7, r5 +100075d8: e749 b.n 1000746e +100075da: bf00 nop + +100075dc : +100075dc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100075e0: 4607 mov r7, r0 +100075e2: 6c40 ldr r0, [r0, #68] @ 0x44 +100075e4: 460e mov r6, r1 +100075e6: b085 sub sp, #20 +100075e8: 2800 cmp r0, #0 +100075ea: d154 bne.n 10007696 +100075ec: e9d7 0508 ldrd r0, r5, [r7, #32] +100075f0: e9d7 e10b ldrd lr, r1, [r7, #44] @ 0x2c +100075f4: f04f 0900 mov.w r9, #0 +100075f8: 697b ldr r3, [r7, #20] +100075fa: 693a ldr r2, [r7, #16] +100075fc: f110 0805 adds.w r8, r0, #5 +10007600: 9301 str r3, [sp, #4] +10007602: 9200 str r2, [sp, #0] +10007604: 69bb ldr r3, [r7, #24] +10007606: f149 0200 adc.w r2, r9, #0 +1000760a: 6abc ldr r4, [r7, #40] @ 0x28 +1000760c: 18aa adds r2, r5, r2 +1000760e: 69ff ldr r7, [r7, #28] +10007610: 9302 str r3, [sp, #8] +10007612: eb49 0309 adc.w r3, r9, r9 +10007616: 18e3 adds r3, r4, r3 +10007618: 9703 str r7, [sp, #12] +1000761a: eb49 0709 adc.w r7, r9, r9 +1000761e: eb1e 0707 adds.w r7, lr, r7 +10007622: f141 0c00 adc.w ip, r1, #0 +10007626: ea4f 0c9c mov.w ip, ip, lsr #2 +1000762a: f1cc 0100 rsb r1, ip, #0 +1000762e: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff +10007632: ea05 050c and.w r5, r5, ip +10007636: 400a ands r2, r1 +10007638: 432a orrs r2, r5 +1000763a: 9d01 ldr r5, [sp, #4] +1000763c: ea08 0801 and.w r8, r8, r1 +10007640: 1952 adds r2, r2, r5 +10007642: ea00 000c and.w r0, r0, ip +10007646: 9d00 ldr r5, [sp, #0] +10007648: ea04 040c and.w r4, r4, ip +1000764c: ea40 0008 orr.w r0, r0, r8 +10007650: ea03 0301 and.w r3, r3, r1 +10007654: ea43 0304 orr.w r3, r3, r4 +10007658: eb49 0409 adc.w r4, r9, r9 +1000765c: 1940 adds r0, r0, r5 +1000765e: 6030 str r0, [r6, #0] +10007660: eb49 0009 adc.w r0, r9, r9 +10007664: 1812 adds r2, r2, r0 +10007666: 9802 ldr r0, [sp, #8] +10007668: ea0e 0e0c and.w lr, lr, ip +1000766c: ea01 0107 and.w r1, r1, r7 +10007670: 9f03 ldr r7, [sp, #12] +10007672: ea41 010e orr.w r1, r1, lr +10007676: 6072 str r2, [r6, #4] +10007678: f144 0200 adc.w r2, r4, #0 +1000767c: 181b adds r3, r3, r0 +1000767e: eb49 0009 adc.w r0, r9, r9 +10007682: 4439 add r1, r7 +10007684: 189b adds r3, r3, r2 +10007686: eb41 0100 adc.w r1, r1, r0 +1000768a: 4648 mov r0, r9 +1000768c: 60b3 str r3, [r6, #8] +1000768e: 60f1 str r1, [r6, #12] +10007690: b005 add sp, #20 +10007692: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007696: 2101 movs r1, #1 +10007698: 183b adds r3, r7, r0 +1000769a: 1842 adds r2, r0, r1 +1000769c: 3035 adds r0, #53 @ 0x35 +1000769e: f883 1034 strb.w r1, [r3, #52] @ 0x34 +100076a2: 4438 add r0, r7 +100076a4: 647a str r2, [r7, #68] @ 0x44 +100076a6: 2100 movs r1, #0 +100076a8: f1c2 0210 rsb r2, r2, #16 +100076ac: f004 fbbe bl 1000be2c +100076b0: 2200 movs r2, #0 +100076b2: 4638 mov r0, r7 +100076b4: f107 0134 add.w r1, r7, #52 @ 0x34 +100076b8: f7ff fdda bl 10007270 +100076bc: e796 b.n 100075ec +100076be: bf00 nop + +100076c0 : +100076c0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100076c4: 4605 mov r5, r0 +100076c6: 2600 movs r6, #0 +100076c8: 460f mov r7, r1 +100076ca: b095 sub sp, #84 @ 0x54 +100076cc: 2148 movs r1, #72 @ 0x48 +100076ce: a802 add r0, sp, #8 +100076d0: 9201 str r2, [sp, #4] +100076d2: 461c mov r4, r3 +100076d4: f7ff f974 bl 100069c0 +100076d8: 682b ldr r3, [r5, #0] +100076da: 4849 ldr r0, [pc, #292] @ (10007800 ) +100076dc: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 +100076e0: 9302 str r3, [sp, #8] +100076e2: 686b ldr r3, [r5, #4] +100076e4: 2110 movs r1, #16 +100076e6: 4003 ands r3, r0 +100076e8: 9303 str r3, [sp, #12] +100076ea: 68ab ldr r3, [r5, #8] +100076ec: e9cd 660a strd r6, r6, [sp, #40] @ 0x28 +100076f0: 4003 ands r3, r0 +100076f2: 9304 str r3, [sp, #16] +100076f4: 68eb ldr r3, [r5, #12] +100076f6: e9cd 660c strd r6, r6, [sp, #48] @ 0x30 +100076fa: 4003 ands r3, r0 +100076fc: 9305 str r3, [sp, #20] +100076fe: 696b ldr r3, [r5, #20] +10007700: a80f add r0, sp, #60 @ 0x3c +10007702: 9307 str r3, [sp, #28] +10007704: 69ab ldr r3, [r5, #24] +10007706: 960e str r6, [sp, #56] @ 0x38 +10007708: 9308 str r3, [sp, #32] +1000770a: 69eb ldr r3, [r5, #28] +1000770c: 9309 str r3, [sp, #36] @ 0x24 +1000770e: 692b ldr r3, [r5, #16] +10007710: 9306 str r3, [sp, #24] +10007712: f7ff f955 bl 100069c0 +10007716: 4639 mov r1, r7 +10007718: 9a01 ldr r2, [sp, #4] +1000771a: a802 add r0, sp, #8 +1000771c: 9613 str r6, [sp, #76] @ 0x4c +1000771e: f7ff fe65 bl 100073ec +10007722: 9b13 ldr r3, [sp, #76] @ 0x4c +10007724: 2b00 cmp r3, #0 +10007726: d156 bne.n 100077d6 +10007728: f04f 0800 mov.w r8, #0 +1000772c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000772e: 9f0b ldr r7, [sp, #44] @ 0x2c +10007730: 3305 adds r3, #5 +10007732: f148 0c00 adc.w ip, r8, #0 +10007736: 9d0c ldr r5, [sp, #48] @ 0x30 +10007738: eb17 0c0c adds.w ip, r7, ip +1000773c: eb48 0208 adc.w r2, r8, r8 +10007740: 9e0d ldr r6, [sp, #52] @ 0x34 +10007742: 18aa adds r2, r5, r2 +10007744: eb48 0508 adc.w r5, r8, r8 +10007748: 1975 adds r5, r6, r5 +1000774a: 9e0e ldr r6, [sp, #56] @ 0x38 +1000774c: a802 add r0, sp, #8 +1000774e: f146 0e00 adc.w lr, r6, #0 +10007752: ea4f 0e9e mov.w lr, lr, lsr #2 +10007756: f1ce 0600 rsb r6, lr, #0 +1000775a: f10e 3eff add.w lr, lr, #4294967295 @ 0xffffffff +1000775e: ea07 070e and.w r7, r7, lr +10007762: ea06 0c0c and.w ip, r6, ip +10007766: ea4c 0c07 orr.w ip, ip, r7 +1000776a: 9f07 ldr r7, [sp, #28] +1000776c: 4033 ands r3, r6 +1000776e: eb1c 0c07 adds.w ip, ip, r7 +10007772: 9f0a ldr r7, [sp, #40] @ 0x28 +10007774: ea02 0206 and.w r2, r2, r6 +10007778: ea07 070e and.w r7, r7, lr +1000777c: ea43 0907 orr.w r9, r3, r7 +10007780: 9b0d ldr r3, [sp, #52] @ 0x34 +10007782: 9f0c ldr r7, [sp, #48] @ 0x30 +10007784: ea06 0605 and.w r6, r6, r5 +10007788: ea07 070e and.w r7, r7, lr +1000778c: ea03 0e0e and.w lr, r3, lr +10007790: 9b09 ldr r3, [sp, #36] @ 0x24 +10007792: ea46 060e orr.w r6, r6, lr +10007796: 441e add r6, r3 +10007798: 9b06 ldr r3, [sp, #24] +1000779a: eb48 0508 adc.w r5, r8, r8 +1000779e: eb19 0303 adds.w r3, r9, r3 +100077a2: 6023 str r3, [r4, #0] +100077a4: eb48 0308 adc.w r3, r8, r8 +100077a8: eb1c 0c03 adds.w ip, ip, r3 +100077ac: f145 0300 adc.w r3, r5, #0 +100077b0: 9d08 ldr r5, [sp, #32] +100077b2: 433a orrs r2, r7 +100077b4: 1952 adds r2, r2, r5 +100077b6: eb48 0508 adc.w r5, r8, r8 +100077ba: 18d2 adds r2, r2, r3 +100077bc: eb46 0605 adc.w r6, r6, r5 +100077c0: 2148 movs r1, #72 @ 0x48 +100077c2: f8c4 c004 str.w ip, [r4, #4] +100077c6: 60a2 str r2, [r4, #8] +100077c8: 60e6 str r6, [r4, #12] +100077ca: f7ff f8f9 bl 100069c0 +100077ce: 4640 mov r0, r8 +100077d0: b015 add sp, #84 @ 0x54 +100077d2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100077d6: 2101 movs r1, #1 +100077d8: ad02 add r5, sp, #8 +100077da: 185a adds r2, r3, r1 +100077dc: f103 0035 add.w r0, r3, #53 @ 0x35 +100077e0: 446b add r3, sp +100077e2: 9213 str r2, [sp, #76] @ 0x4c +100077e4: f883 103c strb.w r1, [r3, #60] @ 0x3c +100077e8: f1c2 0210 rsb r2, r2, #16 +100077ec: 4631 mov r1, r6 +100077ee: 4428 add r0, r5 +100077f0: f004 fb1c bl 1000be2c +100077f4: 4632 mov r2, r6 +100077f6: 4628 mov r0, r5 +100077f8: a90f add r1, sp, #60 @ 0x3c +100077fa: f7ff fd39 bl 10007270 +100077fe: e793 b.n 10007728 +10007800: 0ffffffc .word 0x0ffffffc + +10007804 : +10007804: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10007808: 4b7f ldr r3, [pc, #508] @ (10007a08 ) +1000780a: b09f sub sp, #124 @ 0x7c +1000780c: 9003 str r0, [sp, #12] +1000780e: 9301 str r3, [sp, #4] +10007810: f103 0608 add.w r6, r3, #8 +10007814: 2800 cmp r0, #0 +10007816: f040 80d3 bne.w 100079c0 +1000781a: 4607 mov r7, r0 +1000781c: ab19 add r3, sp, #100 @ 0x64 +1000781e: 9304 str r3, [sp, #16] +10007820: 9b01 ldr r3, [sp, #4] +10007822: f10d 0b30 add.w fp, sp, #48 @ 0x30 +10007826: f103 0248 add.w r2, r3, #72 @ 0x48 +1000782a: 9206 str r2, [sp, #24] +1000782c: f503 73a4 add.w r3, r3, #328 @ 0x148 +10007830: aa08 add r2, sp, #32 +10007832: 9207 str r2, [sp, #28] +10007834: 9305 str r3, [sp, #20] +10007836: 2400 movs r4, #0 +10007838: 4d74 ldr r5, [pc, #464] @ (10007a0c ) +1000783a: f8dd 901c ldr.w r9, [sp, #28] +1000783e: 9b01 ldr r3, [sp, #4] +10007840: 2148 movs r1, #72 @ 0x48 +10007842: 4658 mov r0, fp +10007844: f8d3 8000 ldr.w r8, [r3] +10007848: f7ff f8ba bl 100069c0 +1000784c: 6833 ldr r3, [r6, #0] +1000784e: 2110 movs r1, #16 +10007850: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 +10007854: 930c str r3, [sp, #48] @ 0x30 +10007856: 6873 ldr r3, [r6, #4] +10007858: 9804 ldr r0, [sp, #16] +1000785a: 402b ands r3, r5 +1000785c: 930d str r3, [sp, #52] @ 0x34 +1000785e: 68b3 ldr r3, [r6, #8] +10007860: e9cd 4414 strd r4, r4, [sp, #80] @ 0x50 +10007864: 402b ands r3, r5 +10007866: 930e str r3, [sp, #56] @ 0x38 +10007868: 68f3 ldr r3, [r6, #12] +1000786a: e9cd 4416 strd r4, r4, [sp, #88] @ 0x58 +1000786e: 402b ands r3, r5 +10007870: 930f str r3, [sp, #60] @ 0x3c +10007872: 6973 ldr r3, [r6, #20] +10007874: 9418 str r4, [sp, #96] @ 0x60 +10007876: 9311 str r3, [sp, #68] @ 0x44 +10007878: 69b3 ldr r3, [r6, #24] +1000787a: 9312 str r3, [sp, #72] @ 0x48 +1000787c: 69f3 ldr r3, [r6, #28] +1000787e: 9313 str r3, [sp, #76] @ 0x4c +10007880: 6933 ldr r3, [r6, #16] +10007882: 9310 str r3, [sp, #64] @ 0x40 +10007884: f7ff f89c bl 100069c0 +10007888: 9b06 ldr r3, [sp, #24] +1000788a: ebc7 11c7 rsb r1, r7, r7, lsl #7 +1000788e: 4419 add r1, r3 +10007890: 4642 mov r2, r8 +10007892: 4658 mov r0, fp +10007894: 941d str r4, [sp, #116] @ 0x74 +10007896: f7ff fda9 bl 100073ec +1000789a: 9b1d ldr r3, [sp, #116] @ 0x74 +1000789c: 2b00 cmp r3, #0 +1000789e: d17b bne.n 10007998 +100078a0: e9dd ce14 ldrd ip, lr, [sp, #80] @ 0x50 +100078a4: f11c 0005 adds.w r0, ip, #5 +100078a8: f144 0300 adc.w r3, r4, #0 +100078ac: eb1e 0303 adds.w r3, lr, r3 +100078b0: 9a16 ldr r2, [sp, #88] @ 0x58 +100078b2: eb44 0104 adc.w r1, r4, r4 +100078b6: 1851 adds r1, r2, r1 +100078b8: 9102 str r1, [sp, #8] +100078ba: 9917 ldr r1, [sp, #92] @ 0x5c +100078bc: 9a18 ldr r2, [sp, #96] @ 0x60 +100078be: eb44 0804 adc.w r8, r4, r4 +100078c2: eb11 0808 adds.w r8, r1, r8 +100078c6: f142 0200 adc.w r2, r2, #0 +100078ca: 0892 lsrs r2, r2, #2 +100078cc: f1c2 0a00 rsb sl, r2, #0 +100078d0: 9916 ldr r1, [sp, #88] @ 0x58 +100078d2: 3a01 subs r2, #1 +100078d4: ea0c 0c02 and.w ip, ip, r2 +100078d8: ea00 000a and.w r0, r0, sl +100078dc: ea4c 0000 orr.w r0, ip, r0 +100078e0: ea01 0c02 and.w ip, r1, r2 +100078e4: 9917 ldr r1, [sp, #92] @ 0x5c +100078e6: ea0e 0e02 and.w lr, lr, r2 +100078ea: 400a ands r2, r1 +100078ec: 9902 ldr r1, [sp, #8] +100078ee: ea0a 0303 and.w r3, sl, r3 +100078f2: ea0a 0101 and.w r1, sl, r1 +100078f6: ea0a 0a08 and.w sl, sl, r8 +100078fa: ea4a 0a02 orr.w sl, sl, r2 +100078fe: 9a11 ldr r2, [sp, #68] @ 0x44 +10007900: ea43 030e orr.w r3, r3, lr +10007904: 189b adds r3, r3, r2 +10007906: 9a10 ldr r2, [sp, #64] @ 0x40 +10007908: ea41 010c orr.w r1, r1, ip +1000790c: eb44 0c04 adc.w ip, r4, r4 +10007910: 1880 adds r0, r0, r2 +10007912: 9008 str r0, [sp, #32] +10007914: eb44 0004 adc.w r0, r4, r4 +10007918: 181b adds r3, r3, r0 +1000791a: 9a12 ldr r2, [sp, #72] @ 0x48 +1000791c: 9309 str r3, [sp, #36] @ 0x24 +1000791e: 9b13 ldr r3, [sp, #76] @ 0x4c +10007920: f14c 0c00 adc.w ip, ip, #0 +10007924: 188a adds r2, r1, r2 +10007926: 449a add sl, r3 +10007928: eb44 0304 adc.w r3, r4, r4 +1000792c: eb12 020c adds.w r2, r2, ip +10007930: eb4a 0303 adc.w r3, sl, r3 +10007934: 2148 movs r1, #72 @ 0x48 +10007936: 4658 mov r0, fp +10007938: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +1000793c: f7ff f840 bl 100069c0 +10007940: 9805 ldr r0, [sp, #20] +10007942: 013b lsls r3, r7, #4 +10007944: 58c2 ldr r2, [r0, r3] +10007946: f8d9 1000 ldr.w r1, [r9] +1000794a: eb00 1307 add.w r3, r0, r7, lsl #4 +1000794e: 4291 cmp r1, r2 +10007950: d008 beq.n 10007964 +10007952: 9b03 ldr r3, [sp, #12] +10007954: 2b00 cmp r3, #0 +10007956: d153 bne.n 10007a00 +10007958: f04f 38ff mov.w r8, #4294967295 @ 0xffffffff +1000795c: 4640 mov r0, r8 +1000795e: b01f add sp, #124 @ 0x7c +10007960: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10007964: 6859 ldr r1, [r3, #4] +10007966: 9a09 ldr r2, [sp, #36] @ 0x24 +10007968: 3304 adds r3, #4 +1000796a: 428a cmp r2, r1 +1000796c: d1f1 bne.n 10007952 +1000796e: 990a ldr r1, [sp, #40] @ 0x28 +10007970: f853 2f04 ldr.w r2, [r3, #4]! +10007974: 4291 cmp r1, r2 +10007976: d1ec bne.n 10007952 +10007978: 685b ldr r3, [r3, #4] +1000797a: 9a0b ldr r2, [sp, #44] @ 0x2c +1000797c: 429a cmp r2, r3 +1000797e: d1e8 bne.n 10007952 +10007980: 9b01 ldr r3, [sp, #4] +10007982: f04f 0800 mov.w r8, #0 +10007986: 3304 adds r3, #4 +10007988: 9301 str r3, [sp, #4] +1000798a: 9b03 ldr r3, [sp, #12] +1000798c: bb53 cbnz r3, 100079e4 +1000798e: 3620 adds r6, #32 +10007990: 2f00 cmp r7, #0 +10007992: d1e3 bne.n 1000795c +10007994: 2701 movs r7, #1 +10007996: e752 b.n 1000783e +10007998: 2101 movs r1, #1 +1000799a: f103 0035 add.w r0, r3, #53 @ 0x35 +1000799e: 185a adds r2, r3, r1 +100079a0: 446b add r3, sp +100079a2: 921d str r2, [sp, #116] @ 0x74 +100079a4: f883 1064 strb.w r1, [r3, #100] @ 0x64 +100079a8: f1c2 0210 rsb r2, r2, #16 +100079ac: 2100 movs r1, #0 +100079ae: 4458 add r0, fp +100079b0: f004 fa3c bl 1000be2c +100079b4: 2200 movs r2, #0 +100079b6: 4658 mov r0, fp +100079b8: 9904 ldr r1, [sp, #16] +100079ba: f7ff fc59 bl 10007270 +100079be: e76f b.n 100078a0 +100079c0: 2700 movs r7, #0 +100079c2: ab19 add r3, sp, #100 @ 0x64 +100079c4: f106 0240 add.w r2, r6, #64 @ 0x40 +100079c8: 9304 str r3, [sp, #16] +100079ca: 9206 str r2, [sp, #24] +100079cc: f506 73a0 add.w r3, r6, #320 @ 0x140 +100079d0: aa08 add r2, sp, #32 +100079d2: f10d 0b30 add.w fp, sp, #48 @ 0x30 +100079d6: 9207 str r2, [sp, #28] +100079d8: 9305 str r3, [sp, #20] +100079da: 4639 mov r1, r7 +100079dc: 480c ldr r0, [pc, #48] @ (10007a10 ) +100079de: f7fb ff61 bl 100038a4 <__wrap_printf> +100079e2: e728 b.n 10007836 +100079e4: 480b ldr r0, [pc, #44] @ (10007a14 ) +100079e6: f7fb fedf bl 100037a8 <__wrap_puts> +100079ea: b137 cbz r7, 100079fa +100079ec: 200a movs r0, #10 +100079ee: f7fb fe99 bl 10003724 <__wrap_putchar> +100079f2: 4640 mov r0, r8 +100079f4: b01f add sp, #124 @ 0x7c +100079f6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100079fa: 2701 movs r7, #1 +100079fc: 3620 adds r6, #32 +100079fe: e7ec b.n 100079da +10007a00: 4805 ldr r0, [pc, #20] @ (10007a18 ) +10007a02: f7fb fed1 bl 100037a8 <__wrap_puts> +10007a06: e7a7 b.n 10007958 +10007a08: 1000d674 .word 0x1000d674 +10007a0c: 0ffffffc .word 0x0ffffffc +10007a10: 1000c7dc .word 0x1000c7dc +10007a14: 1000c748 .word 0x1000c748 +10007a18: 1000c7f0 .word 0x1000c7f0 + +10007a1c : +10007a1c: b510 push {r4, lr} +10007a1e: b08e sub sp, #56 @ 0x38 +10007a20: f88d 1028 strb.w r1, [sp, #40] @ 0x28 +10007a24: e9d0 120b ldrd r1, r2, [r0, #44] @ 0x2c +10007a28: 00d3 lsls r3, r2, #3 +10007a2a: 428b cmp r3, r1 +10007a2c: bf38 it cc +10007a2e: 460b movcc r3, r1 +10007a30: 6b41 ldr r1, [r0, #52] @ 0x34 +10007a32: ea4f 0c82 mov.w ip, r2, lsl #2 +10007a36: 428a cmp r2, r1 +10007a38: 9208 str r2, [sp, #32] +10007a3a: bf28 it cs +10007a3c: 460a movcs r2, r1 +10007a3e: fbb3 f3fc udiv r3, r3, ip +10007a42: 2100 movs r1, #0 +10007a44: 9209 str r2, [sp, #36] @ 0x24 +10007a46: 6b82 ldr r2, [r0, #56] @ 0x38 +10007a48: 9102 str r1, [sp, #8] +10007a4a: 9203 str r2, [sp, #12] +10007a4c: 6a82 ldr r2, [r0, #40] @ 0x28 +10007a4e: 4601 mov r1, r0 +10007a50: 9204 str r2, [sp, #16] +10007a52: fb03 f20c mul.w r2, r3, ip +10007a56: 4604 mov r4, r0 +10007a58: ea4f 0c83 mov.w ip, r3, lsl #2 +10007a5c: a802 add r0, sp, #8 +10007a5e: e9cd 3c06 strd r3, ip, [sp, #24] +10007a62: 9205 str r2, [sp, #20] +10007a64: f001 f90a bl 10008c7c +10007a68: 4603 mov r3, r0 +10007a6a: b110 cbz r0, 10007a72 +10007a6c: 4618 mov r0, r3 +10007a6e: b00e add sp, #56 @ 0x38 +10007a70: bd10 pop {r4, pc} +10007a72: a802 add r0, sp, #8 +10007a74: f000 fff8 bl 10008a68 +10007a78: 4603 mov r3, r0 +10007a7a: 2800 cmp r0, #0 +10007a7c: d1f6 bne.n 10007a6c +10007a7e: 9001 str r0, [sp, #4] +10007a80: a902 add r1, sp, #8 +10007a82: 4620 mov r0, r4 +10007a84: f000 fed4 bl 10008830 +10007a88: 9b01 ldr r3, [sp, #4] +10007a8a: 4618 mov r0, r3 +10007a8c: b00e add sp, #56 @ 0x38 +10007a8e: bd10 pop {r4, pc} + +10007a90 : +10007a90: 2801 cmp r0, #1 +10007a92: d008 beq.n 10007aa6 +10007a94: 2802 cmp r0, #2 +10007a96: d003 beq.n 10007aa0 +10007a98: b940 cbnz r0, 10007aac +10007a9a: b169 cbz r1, 10007ab8 +10007a9c: 4807 ldr r0, [pc, #28] @ (10007abc ) +10007a9e: 4770 bx lr +10007aa0: b141 cbz r1, 10007ab4 +10007aa2: 4807 ldr r0, [pc, #28] @ (10007ac0 ) +10007aa4: 4770 bx lr +10007aa6: b119 cbz r1, 10007ab0 +10007aa8: 4806 ldr r0, [pc, #24] @ (10007ac4 ) +10007aaa: 4770 bx lr +10007aac: 2000 movs r0, #0 +10007aae: 4770 bx lr +10007ab0: 4805 ldr r0, [pc, #20] @ (10007ac8 ) +10007ab2: 4770 bx lr +10007ab4: 4805 ldr r0, [pc, #20] @ (10007acc ) +10007ab6: 4770 bx lr +10007ab8: 4805 ldr r0, [pc, #20] @ (10007ad0 ) +10007aba: 4770 bx lr +10007abc: 1000c81c .word 0x1000c81c +10007ac0: 1000c82c .word 0x1000c82c +10007ac4: 1000c824 .word 0x1000c824 +10007ac8: 1000c808 .word 0x1000c808 +10007acc: 1000c810 .word 0x1000c810 +10007ad0: 1000c800 .word 0x1000c800 + +10007ad4 : +10007ad4: b510 push {r4, lr} +10007ad6: b08e sub sp, #56 @ 0x38 +10007ad8: 4604 mov r4, r0 +10007ada: 9101 str r1, [sp, #4] +10007adc: f000 fffa bl 10008ad4 +10007ae0: 4603 mov r3, r0 +10007ae2: bb28 cbnz r0, 10007b30 +10007ae4: 9901 ldr r1, [sp, #4] +10007ae6: 2902 cmp r1, #2 +10007ae8: d834 bhi.n 10007b54 +10007aea: 6b22 ldr r2, [r4, #48] @ 0x30 +10007aec: f88d 1028 strb.w r1, [sp, #40] @ 0x28 +10007af0: 6ae1 ldr r1, [r4, #44] @ 0x2c +10007af2: 00d3 lsls r3, r2, #3 +10007af4: 428b cmp r3, r1 +10007af6: bf38 it cc +10007af8: 460b movcc r3, r1 +10007afa: 6ba1 ldr r1, [r4, #56] @ 0x38 +10007afc: ea4f 0c82 mov.w ip, r2, lsl #2 +10007b00: 9103 str r1, [sp, #12] +10007b02: 6aa1 ldr r1, [r4, #40] @ 0x28 +10007b04: fbb3 f3fc udiv r3, r3, ip +10007b08: 9104 str r1, [sp, #16] +10007b0a: 6b61 ldr r1, [r4, #52] @ 0x34 +10007b0c: 9208 str r2, [sp, #32] +10007b0e: 428a cmp r2, r1 +10007b10: bf28 it cs +10007b12: 460a movcs r2, r1 +10007b14: 9209 str r2, [sp, #36] @ 0x24 +10007b16: fb03 f20c mul.w r2, r3, ip +10007b1a: 9002 str r0, [sp, #8] +10007b1c: 9306 str r3, [sp, #24] +10007b1e: 4621 mov r1, r4 +10007b20: 009b lsls r3, r3, #2 +10007b22: a802 add r0, sp, #8 +10007b24: 9307 str r3, [sp, #28] +10007b26: 9205 str r2, [sp, #20] +10007b28: f001 f8a8 bl 10008c7c +10007b2c: 4603 mov r3, r0 +10007b2e: b110 cbz r0, 10007b36 +10007b30: 4618 mov r0, r3 +10007b32: b00e add sp, #56 @ 0x38 +10007b34: bd10 pop {r4, pc} +10007b36: a802 add r0, sp, #8 +10007b38: f000 ff96 bl 10008a68 +10007b3c: 4603 mov r3, r0 +10007b3e: 2800 cmp r0, #0 +10007b40: d1f6 bne.n 10007b30 +10007b42: 9001 str r0, [sp, #4] +10007b44: a902 add r1, sp, #8 +10007b46: 4620 mov r0, r4 +10007b48: f000 fe72 bl 10008830 +10007b4c: 9b01 ldr r3, [sp, #4] +10007b4e: 4618 mov r0, r3 +10007b50: b00e add sp, #56 @ 0x38 +10007b52: bd10 pop {r4, pc} +10007b54: f06f 0319 mvn.w r3, #25 +10007b58: e7ea b.n 10007b30 +10007b5a: bf00 nop + +10007b5c : +10007b5c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10007b60: b092 sub sp, #72 @ 0x48 +10007b62: 9c1e ldr r4, [sp, #120] @ 0x78 +10007b64: f89d 8084 ldrb.w r8, [sp, #132] @ 0x84 +10007b68: 2c03 cmp r4, #3 +10007b6a: d953 bls.n 10007c14 +10007b6c: 4681 mov r9, r0 +10007b6e: 4620 mov r0, r4 +10007b70: 469a mov sl, r3 +10007b72: 4616 mov r6, r2 +10007b74: 460f mov r7, r1 +10007b76: f7fa f85f bl 10001c38 <__wrap_malloc> +10007b7a: 4605 mov r5, r0 +10007b7c: 2800 cmp r0, #0 +10007b7e: d04c beq.n 10007c1a +10007b80: 9b1a ldr r3, [sp, #104] @ 0x68 +10007b82: e9cd 0400 strd r0, r4, [sp] +10007b86: 9303 str r3, [sp, #12] +10007b88: 9b1b ldr r3, [sp, #108] @ 0x6c +10007b8a: 4641 mov r1, r8 +10007b8c: 9304 str r3, [sp, #16] +10007b8e: 9b1c ldr r3, [sp, #112] @ 0x70 +10007b90: 4668 mov r0, sp +10007b92: 9305 str r3, [sp, #20] +10007b94: 9b22 ldr r3, [sp, #136] @ 0x88 +10007b96: e9cd 660c strd r6, r6, [sp, #48] @ 0x30 +10007b9a: 930e str r3, [sp, #56] @ 0x38 +10007b9c: 2300 movs r3, #0 +10007b9e: e9cd 970a strd r9, r7, [sp, #40] @ 0x28 +10007ba2: e9cd 3306 strd r3, r3, [sp, #24] +10007ba6: e9cd 3308 strd r3, r3, [sp, #32] +10007baa: e9cd 330f strd r3, r3, [sp, #60] @ 0x3c +10007bae: f8cd a008 str.w sl, [sp, #8] +10007bb2: 9311 str r3, [sp, #68] @ 0x44 +10007bb4: f7ff ff8e bl 10007ad4 +10007bb8: 4606 mov r6, r0 +10007bba: b950 cbnz r0, 10007bd2 +10007bbc: 9b1d ldr r3, [sp, #116] @ 0x74 +10007bbe: b123 cbz r3, 10007bca +10007bc0: 4618 mov r0, r3 +10007bc2: 4622 mov r2, r4 +10007bc4: 4629 mov r1, r5 +10007bc6: f004 f9d9 bl 1000bf7c +10007bca: 9b1f ldr r3, [sp, #124] @ 0x7c +10007bcc: b10b cbz r3, 10007bd2 +10007bce: 9b20 ldr r3, [sp, #128] @ 0x80 +10007bd0: b953 cbnz r3, 10007be8 +10007bd2: 4628 mov r0, r5 +10007bd4: 4621 mov r1, r4 +10007bd6: f000 fe21 bl 1000881c +10007bda: 4628 mov r0, r5 +10007bdc: f7fa f83e bl 10001c5c <__wrap_free> +10007be0: 4630 mov r0, r6 +10007be2: b012 add sp, #72 @ 0x48 +10007be4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10007be8: 4619 mov r1, r3 +10007bea: 466a mov r2, sp +10007bec: 4643 mov r3, r8 +10007bee: 981f ldr r0, [sp, #124] @ 0x7c +10007bf0: f002 fb56 bl 1000a2a0 +10007bf4: 2800 cmp r0, #0 +10007bf6: d0ec beq.n 10007bd2 +10007bf8: 4621 mov r1, r4 +10007bfa: 4628 mov r0, r5 +10007bfc: f000 fe0e bl 1000881c +10007c00: e9dd 011f ldrd r0, r1, [sp, #124] @ 0x7c +10007c04: f000 fe0a bl 1000881c +10007c08: 4628 mov r0, r5 +10007c0a: f7fa f827 bl 10001c5c <__wrap_free> +10007c0e: f06f 061e mvn.w r6, #30 +10007c12: e7e5 b.n 10007be0 +10007c14: f06f 0601 mvn.w r6, #1 +10007c18: e7e2 b.n 10007be0 +10007c1a: f06f 0615 mvn.w r6, #21 +10007c1e: e7df b.n 10007be0 + +10007c20 : +10007c20: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007c24: b093 sub sp, #76 @ 0x4c +10007c26: 9c1d ldr r4, [sp, #116] @ 0x74 +10007c28: 2c03 cmp r4, #3 +10007c2a: d94d bls.n 10007cc8 +10007c2c: 4680 mov r8, r0 +10007c2e: 4620 mov r0, r4 +10007c30: 4699 mov r9, r3 +10007c32: 4615 mov r5, r2 +10007c34: 460f mov r7, r1 +10007c36: f7f9 ffff bl 10001c38 <__wrap_malloc> +10007c3a: 4606 mov r6, r0 +10007c3c: 2800 cmp r0, #0 +10007c3e: d046 beq.n 10007cce +10007c40: 9b1a ldr r3, [sp, #104] @ 0x68 +10007c42: 2213 movs r2, #19 +10007c44: 9303 str r3, [sp, #12] +10007c46: 9b1b ldr r3, [sp, #108] @ 0x6c +10007c48: e9cd 0400 strd r0, r4, [sp] +10007c4c: 9304 str r3, [sp, #16] +10007c4e: 9b1c ldr r3, [sp, #112] @ 0x70 +10007c50: 2101 movs r1, #1 +10007c52: 9305 str r3, [sp, #20] +10007c54: 2300 movs r3, #0 +10007c56: 4668 mov r0, sp +10007c58: e9cd 750b strd r7, r5, [sp, #44] @ 0x2c +10007c5c: 950d str r5, [sp, #52] @ 0x34 +10007c5e: e9cd 3306 strd r3, r3, [sp, #24] +10007c62: e9cd 3308 strd r3, r3, [sp, #32] +10007c66: e9cd 330f strd r3, r3, [sp, #60] @ 0x3c +10007c6a: f8cd 9008 str.w r9, [sp, #8] +10007c6e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007c72: 920e str r2, [sp, #56] @ 0x38 +10007c74: 9311 str r3, [sp, #68] @ 0x44 +10007c76: f7ff ff2d bl 10007ad4 +10007c7a: 4605 mov r5, r0 +10007c7c: b918 cbnz r0, 10007c86 +10007c7e: 9b1e ldr r3, [sp, #120] @ 0x78 +10007c80: b10b cbz r3, 10007c86 +10007c82: 9b1f ldr r3, [sp, #124] @ 0x7c +10007c84: b953 cbnz r3, 10007c9c +10007c86: 4630 mov r0, r6 +10007c88: 4621 mov r1, r4 +10007c8a: f000 fdc7 bl 1000881c +10007c8e: 4630 mov r0, r6 +10007c90: f7f9 ffe4 bl 10001c5c <__wrap_free> +10007c94: 4628 mov r0, r5 +10007c96: b013 add sp, #76 @ 0x4c +10007c98: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007c9c: 4619 mov r1, r3 +10007c9e: 466a mov r2, sp +10007ca0: 2301 movs r3, #1 +10007ca2: 981e ldr r0, [sp, #120] @ 0x78 +10007ca4: f002 fafc bl 1000a2a0 +10007ca8: 2800 cmp r0, #0 +10007caa: d0ec beq.n 10007c86 +10007cac: 4621 mov r1, r4 +10007cae: 4630 mov r0, r6 +10007cb0: f000 fdb4 bl 1000881c +10007cb4: e9dd 011e ldrd r0, r1, [sp, #120] @ 0x78 +10007cb8: f000 fdb0 bl 1000881c +10007cbc: 4630 mov r0, r6 +10007cbe: f7f9 ffcd bl 10001c5c <__wrap_free> +10007cc2: f06f 051e mvn.w r5, #30 +10007cc6: e7e5 b.n 10007c94 +10007cc8: f06f 0501 mvn.w r5, #1 +10007ccc: e7e2 b.n 10007c94 +10007cce: f06f 0515 mvn.w r5, #21 +10007cd2: e7df b.n 10007c94 + +10007cd4 : +10007cd4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007cd8: b093 sub sp, #76 @ 0x4c +10007cda: 9c1e ldr r4, [sp, #120] @ 0x78 +10007cdc: 2c03 cmp r4, #3 +10007cde: d939 bls.n 10007d54 +10007ce0: 4680 mov r8, r0 +10007ce2: 4620 mov r0, r4 +10007ce4: 4699 mov r9, r3 +10007ce6: 4616 mov r6, r2 +10007ce8: 460f mov r7, r1 +10007cea: f7f9 ffa5 bl 10001c38 <__wrap_malloc> +10007cee: 4605 mov r5, r0 +10007cf0: b398 cbz r0, 10007d5a +10007cf2: 9b1a ldr r3, [sp, #104] @ 0x68 +10007cf4: 2213 movs r2, #19 +10007cf6: 9303 str r3, [sp, #12] +10007cf8: 9b1b ldr r3, [sp, #108] @ 0x6c +10007cfa: e9cd 0400 strd r0, r4, [sp] +10007cfe: 9304 str r3, [sp, #16] +10007d00: 9b1c ldr r3, [sp, #112] @ 0x70 +10007d02: 2101 movs r1, #1 +10007d04: 9305 str r3, [sp, #20] +10007d06: 2300 movs r3, #0 +10007d08: 4668 mov r0, sp +10007d0a: e9cd 660c strd r6, r6, [sp, #48] @ 0x30 +10007d0e: e9cd 3306 strd r3, r3, [sp, #24] +10007d12: e9cd 3308 strd r3, r3, [sp, #32] +10007d16: e9cd 330f strd r3, r3, [sp, #60] @ 0x3c +10007d1a: f8cd 9008 str.w r9, [sp, #8] +10007d1e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007d22: 970b str r7, [sp, #44] @ 0x2c +10007d24: 920e str r2, [sp, #56] @ 0x38 +10007d26: 9311 str r3, [sp, #68] @ 0x44 +10007d28: f7ff fed4 bl 10007ad4 +10007d2c: 4606 mov r6, r0 +10007d2e: b930 cbnz r0, 10007d3e +10007d30: 9b1d ldr r3, [sp, #116] @ 0x74 +10007d32: b123 cbz r3, 10007d3e +10007d34: 4622 mov r2, r4 +10007d36: 4618 mov r0, r3 +10007d38: 4629 mov r1, r5 +10007d3a: f004 f91f bl 1000bf7c +10007d3e: 4628 mov r0, r5 +10007d40: 4621 mov r1, r4 +10007d42: f000 fd6b bl 1000881c +10007d46: 4628 mov r0, r5 +10007d48: f7f9 ff88 bl 10001c5c <__wrap_free> +10007d4c: 4630 mov r0, r6 +10007d4e: b013 add sp, #76 @ 0x4c +10007d50: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007d54: f06f 0601 mvn.w r6, #1 +10007d58: e7f8 b.n 10007d4c +10007d5a: f06f 0615 mvn.w r6, #21 +10007d5e: e7f5 b.n 10007d4c + +10007d60 : +10007d60: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007d64: b093 sub sp, #76 @ 0x4c +10007d66: 9d1d ldr r5, [sp, #116] @ 0x74 +10007d68: 2d03 cmp r5, #3 +10007d6a: d94c bls.n 10007e06 +10007d6c: 4680 mov r8, r0 +10007d6e: 4628 mov r0, r5 +10007d70: 4699 mov r9, r3 +10007d72: 4614 mov r4, r2 +10007d74: 460f mov r7, r1 +10007d76: f7f9 ff5f bl 10001c38 <__wrap_malloc> +10007d7a: 4606 mov r6, r0 +10007d7c: 2800 cmp r0, #0 +10007d7e: d045 beq.n 10007e0c +10007d80: 2100 movs r1, #0 +10007d82: 2313 movs r3, #19 +10007d84: 9a1a ldr r2, [sp, #104] @ 0x68 +10007d86: e9cd 0500 strd r0, r5, [sp] +10007d8a: 9203 str r2, [sp, #12] +10007d8c: 9a1b ldr r2, [sp, #108] @ 0x6c +10007d8e: 4668 mov r0, sp +10007d90: 9204 str r2, [sp, #16] +10007d92: 9a1c ldr r2, [sp, #112] @ 0x70 +10007d94: e9cd 740b strd r7, r4, [sp, #44] @ 0x2c +10007d98: 940d str r4, [sp, #52] @ 0x34 +10007d9a: e9cd 1106 strd r1, r1, [sp, #24] +10007d9e: e9cd 1108 strd r1, r1, [sp, #32] +10007da2: e9cd 110f strd r1, r1, [sp, #60] @ 0x3c +10007da6: f8cd 9008 str.w r9, [sp, #8] +10007daa: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007dae: 9205 str r2, [sp, #20] +10007db0: 930e str r3, [sp, #56] @ 0x38 +10007db2: 9111 str r1, [sp, #68] @ 0x44 +10007db4: f7ff fe8e bl 10007ad4 +10007db8: 4604 mov r4, r0 +10007dba: b918 cbnz r0, 10007dc4 +10007dbc: 9b1e ldr r3, [sp, #120] @ 0x78 +10007dbe: b10b cbz r3, 10007dc4 +10007dc0: 9b1f ldr r3, [sp, #124] @ 0x7c +10007dc2: b953 cbnz r3, 10007dda +10007dc4: 4630 mov r0, r6 +10007dc6: 4629 mov r1, r5 +10007dc8: f000 fd28 bl 1000881c +10007dcc: 4630 mov r0, r6 +10007dce: f7f9 ff45 bl 10001c5c <__wrap_free> +10007dd2: 4620 mov r0, r4 +10007dd4: b013 add sp, #76 @ 0x4c +10007dd6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007dda: 4619 mov r1, r3 +10007ddc: 466a mov r2, sp +10007dde: 4603 mov r3, r0 +10007de0: 981e ldr r0, [sp, #120] @ 0x78 +10007de2: f002 fa5d bl 1000a2a0 +10007de6: 2800 cmp r0, #0 +10007de8: d0ec beq.n 10007dc4 +10007dea: 4629 mov r1, r5 +10007dec: 4630 mov r0, r6 +10007dee: f000 fd15 bl 1000881c +10007df2: e9dd 011e ldrd r0, r1, [sp, #120] @ 0x78 +10007df6: f000 fd11 bl 1000881c +10007dfa: 4630 mov r0, r6 +10007dfc: f7f9 ff2e bl 10001c5c <__wrap_free> +10007e00: f06f 041e mvn.w r4, #30 +10007e04: e7e5 b.n 10007dd2 +10007e06: f06f 0401 mvn.w r4, #1 +10007e0a: e7e2 b.n 10007dd2 +10007e0c: f06f 0415 mvn.w r4, #21 +10007e10: e7df b.n 10007dd2 +10007e12: bf00 nop + +10007e14 : +10007e14: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007e18: b093 sub sp, #76 @ 0x4c +10007e1a: 9c1e ldr r4, [sp, #120] @ 0x78 +10007e1c: 2c03 cmp r4, #3 +10007e1e: d938 bls.n 10007e92 +10007e20: 4680 mov r8, r0 +10007e22: 4620 mov r0, r4 +10007e24: 4699 mov r9, r3 +10007e26: 4616 mov r6, r2 +10007e28: 460f mov r7, r1 +10007e2a: f7f9 ff05 bl 10001c38 <__wrap_malloc> +10007e2e: 4605 mov r5, r0 +10007e30: b390 cbz r0, 10007e98 +10007e32: 9b1a ldr r3, [sp, #104] @ 0x68 +10007e34: 2100 movs r1, #0 +10007e36: 9303 str r3, [sp, #12] +10007e38: 9b1b ldr r3, [sp, #108] @ 0x6c +10007e3a: e9cd 0400 strd r0, r4, [sp] +10007e3e: 9304 str r3, [sp, #16] +10007e40: 9b1c ldr r3, [sp, #112] @ 0x70 +10007e42: 4668 mov r0, sp +10007e44: 9305 str r3, [sp, #20] +10007e46: 2313 movs r3, #19 +10007e48: e9cd 660c strd r6, r6, [sp, #48] @ 0x30 +10007e4c: e9cd 1106 strd r1, r1, [sp, #24] +10007e50: e9cd 1108 strd r1, r1, [sp, #32] +10007e54: e9cd 110f strd r1, r1, [sp, #60] @ 0x3c +10007e58: f8cd 9008 str.w r9, [sp, #8] +10007e5c: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007e60: 970b str r7, [sp, #44] @ 0x2c +10007e62: 930e str r3, [sp, #56] @ 0x38 +10007e64: 9111 str r1, [sp, #68] @ 0x44 +10007e66: f7ff fe35 bl 10007ad4 +10007e6a: 4606 mov r6, r0 +10007e6c: b930 cbnz r0, 10007e7c +10007e6e: 9b1d ldr r3, [sp, #116] @ 0x74 +10007e70: b123 cbz r3, 10007e7c +10007e72: 4622 mov r2, r4 +10007e74: 4618 mov r0, r3 +10007e76: 4629 mov r1, r5 +10007e78: f004 f880 bl 1000bf7c +10007e7c: 4628 mov r0, r5 +10007e7e: 4621 mov r1, r4 +10007e80: f000 fccc bl 1000881c +10007e84: 4628 mov r0, r5 +10007e86: f7f9 fee9 bl 10001c5c <__wrap_free> +10007e8a: 4630 mov r0, r6 +10007e8c: b013 add sp, #76 @ 0x4c +10007e8e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007e92: f06f 0601 mvn.w r6, #1 +10007e96: e7f8 b.n 10007e8a +10007e98: f06f 0615 mvn.w r6, #21 +10007e9c: e7f5 b.n 10007e8a +10007e9e: bf00 nop + +10007ea0 : +10007ea0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007ea4: b093 sub sp, #76 @ 0x4c +10007ea6: 9c1d ldr r4, [sp, #116] @ 0x74 +10007ea8: 2c03 cmp r4, #3 +10007eaa: d94d bls.n 10007f48 +10007eac: 4680 mov r8, r0 +10007eae: 4620 mov r0, r4 +10007eb0: 4699 mov r9, r3 +10007eb2: 4615 mov r5, r2 +10007eb4: 460f mov r7, r1 +10007eb6: f7f9 febf bl 10001c38 <__wrap_malloc> +10007eba: 4606 mov r6, r0 +10007ebc: 2800 cmp r0, #0 +10007ebe: d046 beq.n 10007f4e +10007ec0: 9b1a ldr r3, [sp, #104] @ 0x68 +10007ec2: 2213 movs r2, #19 +10007ec4: 9303 str r3, [sp, #12] +10007ec6: 9b1b ldr r3, [sp, #108] @ 0x6c +10007ec8: e9cd 0400 strd r0, r4, [sp] +10007ecc: 9304 str r3, [sp, #16] +10007ece: 9b1c ldr r3, [sp, #112] @ 0x70 +10007ed0: 2102 movs r1, #2 +10007ed2: 9305 str r3, [sp, #20] +10007ed4: 2300 movs r3, #0 +10007ed6: 4668 mov r0, sp +10007ed8: e9cd 750b strd r7, r5, [sp, #44] @ 0x2c +10007edc: 950d str r5, [sp, #52] @ 0x34 +10007ede: e9cd 3306 strd r3, r3, [sp, #24] +10007ee2: e9cd 3308 strd r3, r3, [sp, #32] +10007ee6: e9cd 330f strd r3, r3, [sp, #60] @ 0x3c +10007eea: f8cd 9008 str.w r9, [sp, #8] +10007eee: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007ef2: 920e str r2, [sp, #56] @ 0x38 +10007ef4: 9311 str r3, [sp, #68] @ 0x44 +10007ef6: f7ff fded bl 10007ad4 +10007efa: 4605 mov r5, r0 +10007efc: b918 cbnz r0, 10007f06 +10007efe: 9b1e ldr r3, [sp, #120] @ 0x78 +10007f00: b10b cbz r3, 10007f06 +10007f02: 9b1f ldr r3, [sp, #124] @ 0x7c +10007f04: b953 cbnz r3, 10007f1c +10007f06: 4630 mov r0, r6 +10007f08: 4621 mov r1, r4 +10007f0a: f000 fc87 bl 1000881c +10007f0e: 4630 mov r0, r6 +10007f10: f7f9 fea4 bl 10001c5c <__wrap_free> +10007f14: 4628 mov r0, r5 +10007f16: b013 add sp, #76 @ 0x4c +10007f18: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007f1c: 4619 mov r1, r3 +10007f1e: 466a mov r2, sp +10007f20: 2302 movs r3, #2 +10007f22: 981e ldr r0, [sp, #120] @ 0x78 +10007f24: f002 f9bc bl 1000a2a0 +10007f28: 2800 cmp r0, #0 +10007f2a: d0ec beq.n 10007f06 +10007f2c: 4621 mov r1, r4 +10007f2e: 4630 mov r0, r6 +10007f30: f000 fc74 bl 1000881c +10007f34: e9dd 011e ldrd r0, r1, [sp, #120] @ 0x78 +10007f38: f000 fc70 bl 1000881c +10007f3c: 4630 mov r0, r6 +10007f3e: f7f9 fe8d bl 10001c5c <__wrap_free> +10007f42: f06f 051e mvn.w r5, #30 +10007f46: e7e5 b.n 10007f14 +10007f48: f06f 0501 mvn.w r5, #1 +10007f4c: e7e2 b.n 10007f14 +10007f4e: f06f 0515 mvn.w r5, #21 +10007f52: e7df b.n 10007f14 + +10007f54 : +10007f54: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10007f58: b093 sub sp, #76 @ 0x4c +10007f5a: 9c1e ldr r4, [sp, #120] @ 0x78 +10007f5c: 2c03 cmp r4, #3 +10007f5e: d939 bls.n 10007fd4 +10007f60: 4680 mov r8, r0 +10007f62: 4620 mov r0, r4 +10007f64: 4699 mov r9, r3 +10007f66: 4616 mov r6, r2 +10007f68: 460f mov r7, r1 +10007f6a: f7f9 fe65 bl 10001c38 <__wrap_malloc> +10007f6e: 4605 mov r5, r0 +10007f70: b398 cbz r0, 10007fda +10007f72: 9b1a ldr r3, [sp, #104] @ 0x68 +10007f74: 2213 movs r2, #19 +10007f76: 9303 str r3, [sp, #12] +10007f78: 9b1b ldr r3, [sp, #108] @ 0x6c +10007f7a: e9cd 0400 strd r0, r4, [sp] +10007f7e: 9304 str r3, [sp, #16] +10007f80: 9b1c ldr r3, [sp, #112] @ 0x70 +10007f82: 2102 movs r1, #2 +10007f84: 9305 str r3, [sp, #20] +10007f86: 2300 movs r3, #0 +10007f88: 4668 mov r0, sp +10007f8a: e9cd 660c strd r6, r6, [sp, #48] @ 0x30 +10007f8e: e9cd 3306 strd r3, r3, [sp, #24] +10007f92: e9cd 3308 strd r3, r3, [sp, #32] +10007f96: e9cd 330f strd r3, r3, [sp, #60] @ 0x3c +10007f9a: f8cd 9008 str.w r9, [sp, #8] +10007f9e: f8cd 8028 str.w r8, [sp, #40] @ 0x28 +10007fa2: 970b str r7, [sp, #44] @ 0x2c +10007fa4: 920e str r2, [sp, #56] @ 0x38 +10007fa6: 9311 str r3, [sp, #68] @ 0x44 +10007fa8: f7ff fd94 bl 10007ad4 +10007fac: 4606 mov r6, r0 +10007fae: b930 cbnz r0, 10007fbe +10007fb0: 9b1d ldr r3, [sp, #116] @ 0x74 +10007fb2: b123 cbz r3, 10007fbe +10007fb4: 4622 mov r2, r4 +10007fb6: 4618 mov r0, r3 +10007fb8: 4629 mov r1, r5 +10007fba: f003 ffdf bl 1000bf7c +10007fbe: 4628 mov r0, r5 +10007fc0: 4621 mov r1, r4 +10007fc2: f000 fc2b bl 1000881c +10007fc6: 4628 mov r0, r5 +10007fc8: f7f9 fe48 bl 10001c5c <__wrap_free> +10007fcc: 4630 mov r0, r6 +10007fce: b013 add sp, #76 @ 0x4c +10007fd0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10007fd4: f06f 0601 mvn.w r6, #1 +10007fd8: e7f8 b.n 10007fcc +10007fda: f06f 0615 mvn.w r6, #21 +10007fde: e7f5 b.n 10007fcc + +10007fe0 : +10007fe0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10007fe4: b0a0 sub sp, #128 @ 0x80 +10007fe6: 2800 cmp r0, #0 +10007fe8: f000 80b4 beq.w 10008154 +10007fec: 461e mov r6, r3 +10007fee: 460f mov r7, r1 +10007ff0: 9201 str r2, [sp, #4] +10007ff2: 4604 mov r4, r0 +10007ff4: f004 f838 bl 1000c068 +10007ff8: 4605 mov r5, r0 +10007ffa: 9013 str r0, [sp, #76] @ 0x4c +10007ffc: 900f str r0, [sp, #60] @ 0x3c +10007ffe: f7f9 fe1b bl 10001c38 <__wrap_malloc> +10008002: 4603 mov r3, r0 +10008004: 4628 mov r0, r5 +10008006: 9312 str r3, [sp, #72] @ 0x48 +10008008: 461d mov r5, r3 +1000800a: f7f9 fe15 bl 10001c38 <__wrap_malloc> +1000800e: 900e str r0, [sp, #56] @ 0x38 +10008010: 2d00 cmp r5, #0 +10008012: f000 80a6 beq.w 10008162 +10008016: 2800 cmp r0, #0 +10008018: f000 80a2 beq.w 10008160 +1000801c: 9a01 ldr r2, [sp, #4] +1000801e: 4621 mov r1, r4 +10008020: 9211 str r2, [sp, #68] @ 0x44 +10008022: a80e add r0, sp, #56 @ 0x38 +10008024: 4632 mov r2, r6 +10008026: 9710 str r7, [sp, #64] @ 0x40 +10008028: f001 fffe bl 1000a028 +1000802c: 4604 mov r4, r0 +1000802e: b168 cbz r0, 1000804c +10008030: 2500 movs r5, #0 +10008032: 9812 ldr r0, [sp, #72] @ 0x48 +10008034: f7f9 fe12 bl 10001c5c <__wrap_free> +10008038: 980e ldr r0, [sp, #56] @ 0x38 +1000803a: f7f9 fe0f bl 10001c5c <__wrap_free> +1000803e: 4628 mov r0, r5 +10008040: f7f9 fe0c bl 10001c5c <__wrap_free> +10008044: 4620 mov r0, r4 +10008046: b020 add sp, #128 @ 0x80 +10008048: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000804c: e9dd 500e ldrd r5, r0, [sp, #56] @ 0x38 +10008050: f7f9 fdf2 bl 10001c38 <__wrap_malloc> +10008054: 900e str r0, [sp, #56] @ 0x38 +10008056: 2800 cmp r0, #0 +10008058: f000 8083 beq.w 10008162 +1000805c: a80e add r0, sp, #56 @ 0x38 +1000805e: f000 fd39 bl 10008ad4 +10008062: 4604 mov r4, r0 +10008064: 2800 cmp r0, #0 +10008066: d1e4 bne.n 10008032 +10008068: 2e02 cmp r6, #2 +1000806a: d876 bhi.n 1000815a +1000806c: 9a1a ldr r2, [sp, #104] @ 0x68 +1000806e: 9919 ldr r1, [sp, #100] @ 0x64 +10008070: 00d3 lsls r3, r2, #3 +10008072: 428b cmp r3, r1 +10008074: bf38 it cc +10008076: 460b movcc r3, r1 +10008078: 0094 lsls r4, r2, #2 +1000807a: fbb3 f3f4 udiv r3, r3, r4 +1000807e: 991b ldr r1, [sp, #108] @ 0x6c +10008080: 9208 str r2, [sp, #32] +10008082: 428a cmp r2, r1 +10008084: bf28 it cs +10008086: 460a movcs r2, r1 +10008088: fb03 f404 mul.w r4, r3, r4 +1000808c: 991c ldr r1, [sp, #112] @ 0x70 +1000808e: e9cd 4305 strd r4, r3, [sp, #20] +10008092: 9103 str r1, [sp, #12] +10008094: 9918 ldr r1, [sp, #96] @ 0x60 +10008096: 9002 str r0, [sp, #8] +10008098: 9104 str r1, [sp, #16] +1000809a: 009b lsls r3, r3, #2 +1000809c: a90e add r1, sp, #56 @ 0x38 +1000809e: a802 add r0, sp, #8 +100080a0: f88d 6028 strb.w r6, [sp, #40] @ 0x28 +100080a4: 9209 str r2, [sp, #36] @ 0x24 +100080a6: 9307 str r3, [sp, #28] +100080a8: f000 fde8 bl 10008c7c +100080ac: 4604 mov r4, r0 +100080ae: 2800 cmp r0, #0 +100080b0: d1bf bne.n 10008032 +100080b2: a802 add r0, sp, #8 +100080b4: f000 fcd8 bl 10008a68 +100080b8: 4604 mov r4, r0 +100080ba: 2800 cmp r0, #0 +100080bc: d1b9 bne.n 10008032 +100080be: a902 add r1, sp, #8 +100080c0: a80e add r0, sp, #56 @ 0x38 +100080c2: f000 fbb5 bl 10008830 +100080c6: 9f0f ldr r7, [sp, #60] @ 0x3c +100080c8: 2f00 cmp r7, #0 +100080ca: d0b2 beq.n 10008032 +100080cc: 980e ldr r0, [sp, #56] @ 0x38 +100080ce: 1e7b subs r3, r7, #1 +100080d0: 2b02 cmp r3, #2 +100080d2: 4680 mov r8, r0 +100080d4: d93b bls.n 1000814e +100080d6: 462a mov r2, r5 +100080d8: 4621 mov r1, r4 +100080da: f027 0e03 bic.w lr, r7, #3 +100080de: eb0e 0605 add.w r6, lr, r5 +100080e2: f852 cb04 ldr.w ip, [r2], #4 +100080e6: f850 3b04 ldr.w r3, [r0], #4 +100080ea: 4296 cmp r6, r2 +100080ec: ea83 030c eor.w r3, r3, ip +100080f0: ea41 0103 orr.w r1, r1, r3 +100080f4: d1f5 bne.n 100080e2 +100080f6: f3c1 2307 ubfx r3, r1, #8, #8 +100080fa: 430b orrs r3, r1 +100080fc: f3c1 4207 ubfx r2, r1, #16, #8 +10008100: 4313 orrs r3, r2 +10008102: ea43 6311 orr.w r3, r3, r1, lsr #24 +10008106: 4577 cmp r7, lr +10008108: b2db uxtb r3, r3 +1000810a: d019 beq.n 10008140 +1000810c: f815 200e ldrb.w r2, [r5, lr] +10008110: f818 100e ldrb.w r1, [r8, lr] +10008114: f10e 0001 add.w r0, lr, #1 +10008118: 404a eors r2, r1 +1000811a: 4287 cmp r7, r0 +1000811c: ea43 0302 orr.w r3, r3, r2 +10008120: d90e bls.n 10008140 +10008122: 5c29 ldrb r1, [r5, r0] +10008124: f818 0000 ldrb.w r0, [r8, r0] +10008128: f10e 0202 add.w r2, lr, #2 +1000812c: 4041 eors r1, r0 +1000812e: 430b orrs r3, r1 +10008130: 4297 cmp r7, r2 +10008132: b2db uxtb r3, r3 +10008134: d904 bls.n 10008140 +10008136: f818 1002 ldrb.w r1, [r8, r2] +1000813a: 5caa ldrb r2, [r5, r2] +1000813c: 404a eors r2, r1 +1000813e: 4313 orrs r3, r2 +10008140: 3b01 subs r3, #1 +10008142: f413 7f80 tst.w r3, #256 @ 0x100 +10008146: bf08 it eq +10008148: f06f 0422 mvneq.w r4, #34 @ 0x22 +1000814c: e771 b.n 10008032 +1000814e: 2300 movs r3, #0 +10008150: 469e mov lr, r3 +10008152: e7db b.n 1000810c +10008154: f06f 041f mvn.w r4, #31 +10008158: e774 b.n 10008044 +1000815a: f06f 0419 mvn.w r4, #25 +1000815e: e768 b.n 10008032 +10008160: 4605 mov r5, r0 +10008162: f06f 0415 mvn.w r4, #21 +10008166: e764 b.n 10008032 + +10008168 : +10008168: 2301 movs r3, #1 +1000816a: f7ff bf39 b.w 10007fe0 +1000816e: bf00 nop + +10008170 : +10008170: 2300 movs r3, #0 +10008172: f7ff bf35 b.w 10007fe0 +10008176: bf00 nop + +10008178 : +10008178: 2302 movs r3, #2 +1000817a: f7ff bf31 b.w 10007fe0 +1000817e: bf00 nop + +10008180 : +10008180: b510 push {r4, lr} +10008182: b08e sub sp, #56 @ 0x38 +10008184: 4604 mov r4, r0 +10008186: f000 fca5 bl 10008ad4 +1000818a: 4603 mov r3, r0 +1000818c: bb10 cbnz r0, 100081d4 +1000818e: 6b22 ldr r2, [r4, #48] @ 0x30 +10008190: 6ae1 ldr r1, [r4, #44] @ 0x2c +10008192: 00d3 lsls r3, r2, #3 +10008194: 428b cmp r3, r1 +10008196: bf38 it cc +10008198: 460b movcc r3, r1 +1000819a: 6ba1 ldr r1, [r4, #56] @ 0x38 +1000819c: ea4f 0c82 mov.w ip, r2, lsl #2 +100081a0: 9103 str r1, [sp, #12] +100081a2: 6aa1 ldr r1, [r4, #40] @ 0x28 +100081a4: fbb3 f3fc udiv r3, r3, ip +100081a8: 9104 str r1, [sp, #16] +100081aa: 6b61 ldr r1, [r4, #52] @ 0x34 +100081ac: 9208 str r2, [sp, #32] +100081ae: 428a cmp r2, r1 +100081b0: bf28 it cs +100081b2: 460a movcs r2, r1 +100081b4: 9209 str r2, [sp, #36] @ 0x24 +100081b6: fb03 f20c mul.w r2, r3, ip +100081ba: 9002 str r0, [sp, #8] +100081bc: f88d 0028 strb.w r0, [sp, #40] @ 0x28 +100081c0: 9306 str r3, [sp, #24] +100081c2: 4621 mov r1, r4 +100081c4: 009b lsls r3, r3, #2 +100081c6: a802 add r0, sp, #8 +100081c8: 9307 str r3, [sp, #28] +100081ca: 9205 str r2, [sp, #20] +100081cc: f000 fd56 bl 10008c7c +100081d0: 4603 mov r3, r0 +100081d2: b110 cbz r0, 100081da +100081d4: 4618 mov r0, r3 +100081d6: b00e add sp, #56 @ 0x38 +100081d8: bd10 pop {r4, pc} +100081da: a802 add r0, sp, #8 +100081dc: f000 fc44 bl 10008a68 +100081e0: 4603 mov r3, r0 +100081e2: 2800 cmp r0, #0 +100081e4: d1f6 bne.n 100081d4 +100081e6: 9001 str r0, [sp, #4] +100081e8: a902 add r1, sp, #8 +100081ea: 4620 mov r0, r4 +100081ec: f000 fb20 bl 10008830 +100081f0: 9b01 ldr r3, [sp, #4] +100081f2: 4618 mov r0, r3 +100081f4: b00e add sp, #56 @ 0x38 +100081f6: bd10 pop {r4, pc} + +100081f8 : +100081f8: b510 push {r4, lr} +100081fa: b08e sub sp, #56 @ 0x38 +100081fc: 4604 mov r4, r0 +100081fe: f000 fc69 bl 10008ad4 +10008202: 4603 mov r3, r0 +10008204: bb18 cbnz r0, 1000824e +10008206: e9d4 120b ldrd r1, r2, [r4, #44] @ 0x2c +1000820a: 00d3 lsls r3, r2, #3 +1000820c: 428b cmp r3, r1 +1000820e: bf38 it cc +10008210: 460b movcc r3, r1 +10008212: 6b61 ldr r1, [r4, #52] @ 0x34 +10008214: ea4f 0c82 mov.w ip, r2, lsl #2 +10008218: 428a cmp r2, r1 +1000821a: 9208 str r2, [sp, #32] +1000821c: bf28 it cs +1000821e: 460a movcs r2, r1 +10008220: fbb3 f3fc udiv r3, r3, ip +10008224: 2101 movs r1, #1 +10008226: 9209 str r2, [sp, #36] @ 0x24 +10008228: 6ba2 ldr r2, [r4, #56] @ 0x38 +1000822a: 9002 str r0, [sp, #8] +1000822c: 9203 str r2, [sp, #12] +1000822e: 6aa2 ldr r2, [r4, #40] @ 0x28 +10008230: f88d 1028 strb.w r1, [sp, #40] @ 0x28 +10008234: 9204 str r2, [sp, #16] +10008236: fb03 f20c mul.w r2, r3, ip +1000823a: 9306 str r3, [sp, #24] +1000823c: 4621 mov r1, r4 +1000823e: 009b lsls r3, r3, #2 +10008240: a802 add r0, sp, #8 +10008242: 9307 str r3, [sp, #28] +10008244: 9205 str r2, [sp, #20] +10008246: f000 fd19 bl 10008c7c +1000824a: 4603 mov r3, r0 +1000824c: b110 cbz r0, 10008254 +1000824e: 4618 mov r0, r3 +10008250: b00e add sp, #56 @ 0x38 +10008252: bd10 pop {r4, pc} +10008254: a802 add r0, sp, #8 +10008256: f000 fc07 bl 10008a68 +1000825a: 4603 mov r3, r0 +1000825c: 2800 cmp r0, #0 +1000825e: d1f6 bne.n 1000824e +10008260: 9001 str r0, [sp, #4] +10008262: a902 add r1, sp, #8 +10008264: 4620 mov r0, r4 +10008266: f000 fae3 bl 10008830 +1000826a: 9b01 ldr r3, [sp, #4] +1000826c: 4618 mov r0, r3 +1000826e: b00e add sp, #56 @ 0x38 +10008270: bd10 pop {r4, pc} +10008272: bf00 nop + +10008274 : +10008274: b510 push {r4, lr} +10008276: b08e sub sp, #56 @ 0x38 +10008278: 4604 mov r4, r0 +1000827a: f000 fc2b bl 10008ad4 +1000827e: 4603 mov r3, r0 +10008280: bb18 cbnz r0, 100082ca +10008282: e9d4 120b ldrd r1, r2, [r4, #44] @ 0x2c +10008286: 00d3 lsls r3, r2, #3 +10008288: 428b cmp r3, r1 +1000828a: bf38 it cc +1000828c: 460b movcc r3, r1 +1000828e: 6b61 ldr r1, [r4, #52] @ 0x34 +10008290: ea4f 0c82 mov.w ip, r2, lsl #2 +10008294: 428a cmp r2, r1 +10008296: 9208 str r2, [sp, #32] +10008298: bf28 it cs +1000829a: 460a movcs r2, r1 +1000829c: fbb3 f3fc udiv r3, r3, ip +100082a0: 2102 movs r1, #2 +100082a2: 9209 str r2, [sp, #36] @ 0x24 +100082a4: 6ba2 ldr r2, [r4, #56] @ 0x38 +100082a6: 9002 str r0, [sp, #8] +100082a8: 9203 str r2, [sp, #12] +100082aa: 6aa2 ldr r2, [r4, #40] @ 0x28 +100082ac: f88d 1028 strb.w r1, [sp, #40] @ 0x28 +100082b0: 9204 str r2, [sp, #16] +100082b2: fb03 f20c mul.w r2, r3, ip +100082b6: 9306 str r3, [sp, #24] +100082b8: 4621 mov r1, r4 +100082ba: 009b lsls r3, r3, #2 +100082bc: a802 add r0, sp, #8 +100082be: 9307 str r3, [sp, #28] +100082c0: 9205 str r2, [sp, #20] +100082c2: f000 fcdb bl 10008c7c +100082c6: 4603 mov r3, r0 +100082c8: b110 cbz r0, 100082d0 +100082ca: 4618 mov r0, r3 +100082cc: b00e add sp, #56 @ 0x38 +100082ce: bd10 pop {r4, pc} +100082d0: a802 add r0, sp, #8 +100082d2: f000 fbc9 bl 10008a68 +100082d6: 4603 mov r3, r0 +100082d8: 2800 cmp r0, #0 +100082da: d1f6 bne.n 100082ca +100082dc: 9001 str r0, [sp, #4] +100082de: a902 add r1, sp, #8 +100082e0: 4620 mov r0, r4 +100082e2: f000 faa5 bl 10008830 +100082e6: 9b01 ldr r3, [sp, #4] +100082e8: 4618 mov r0, r3 +100082ea: b00e add sp, #56 @ 0x38 +100082ec: bd10 pop {r4, pc} +100082ee: bf00 nop + +100082f0 : +100082f0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100082f4: 4605 mov r5, r0 +100082f6: 460c mov r4, r1 +100082f8: 4616 mov r6, r2 +100082fa: f000 fbeb bl 10008ad4 +100082fe: 2800 cmp r0, #0 +10008300: d148 bne.n 10008394 +10008302: 2e02 cmp r6, #2 +10008304: d84b bhi.n 1000839e +10008306: 4631 mov r1, r6 +10008308: 4628 mov r0, r5 +1000830a: f7ff fb87 bl 10007a1c +1000830e: 2800 cmp r0, #0 +10008310: d140 bne.n 10008394 +10008312: 686e ldr r6, [r5, #4] +10008314: 2e00 cmp r6, #0 +10008316: d03d beq.n 10008394 +10008318: 1e73 subs r3, r6, #1 +1000831a: 2b02 cmp r3, #2 +1000831c: 682f ldr r7, [r5, #0] +1000831e: d93b bls.n 10008398 +10008320: 4622 mov r2, r4 +10008322: 46bc mov ip, r7 +10008324: 4601 mov r1, r0 +10008326: f026 0803 bic.w r8, r6, #3 +1000832a: eb04 0508 add.w r5, r4, r8 +1000832e: f852 eb04 ldr.w lr, [r2], #4 +10008332: f85c 3b04 ldr.w r3, [ip], #4 +10008336: 4295 cmp r5, r2 +10008338: ea83 030e eor.w r3, r3, lr +1000833c: ea41 0103 orr.w r1, r1, r3 +10008340: d1f5 bne.n 1000832e +10008342: f3c1 2307 ubfx r3, r1, #8, #8 +10008346: 430b orrs r3, r1 +10008348: f3c1 4207 ubfx r2, r1, #16, #8 +1000834c: 4313 orrs r3, r2 +1000834e: ea43 6311 orr.w r3, r3, r1, lsr #24 +10008352: 4546 cmp r6, r8 +10008354: b2db uxtb r3, r3 +10008356: d017 beq.n 10008388 +10008358: f814 2008 ldrb.w r2, [r4, r8] +1000835c: f817 1008 ldrb.w r1, [r7, r8] +10008360: f108 0501 add.w r5, r8, #1 +10008364: 404a eors r2, r1 +10008366: 42ae cmp r6, r5 +10008368: ea43 0302 orr.w r3, r3, r2 +1000836c: d90c bls.n 10008388 +1000836e: 5d61 ldrb r1, [r4, r5] +10008370: 5d7d ldrb r5, [r7, r5] +10008372: f108 0202 add.w r2, r8, #2 +10008376: 4069 eors r1, r5 +10008378: 430b orrs r3, r1 +1000837a: 4296 cmp r6, r2 +1000837c: b2db uxtb r3, r3 +1000837e: d903 bls.n 10008388 +10008380: 5cb9 ldrb r1, [r7, r2] +10008382: 5ca2 ldrb r2, [r4, r2] +10008384: 404a eors r2, r1 +10008386: 4313 orrs r3, r2 +10008388: 3b01 subs r3, #1 +1000838a: f413 7f80 tst.w r3, #256 @ 0x100 +1000838e: bf08 it eq +10008390: f06f 0022 mvneq.w r0, #34 @ 0x22 +10008394: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10008398: 4603 mov r3, r0 +1000839a: 4680 mov r8, r0 +1000839c: e7dc b.n 10008358 +1000839e: f06f 0019 mvn.w r0, #25 +100083a2: e7f7 b.n 10008394 + +100083a4 : +100083a4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100083a8: 4605 mov r5, r0 +100083aa: 460c mov r4, r1 +100083ac: f000 fb92 bl 10008ad4 +100083b0: 2800 cmp r0, #0 +100083b2: d147 bne.n 10008444 +100083b4: 4601 mov r1, r0 +100083b6: 4628 mov r0, r5 +100083b8: f7ff fb30 bl 10007a1c +100083bc: 2800 cmp r0, #0 +100083be: d141 bne.n 10008444 +100083c0: 686e ldr r6, [r5, #4] +100083c2: 2e00 cmp r6, #0 +100083c4: d03e beq.n 10008444 +100083c6: 1e73 subs r3, r6, #1 +100083c8: 2b02 cmp r3, #2 +100083ca: 682f ldr r7, [r5, #0] +100083cc: d93c bls.n 10008448 +100083ce: 4622 mov r2, r4 +100083d0: 46be mov lr, r7 +100083d2: 4684 mov ip, r0 +100083d4: f026 0803 bic.w r8, r6, #3 +100083d8: eb04 0508 add.w r5, r4, r8 +100083dc: f852 1b04 ldr.w r1, [r2], #4 +100083e0: f85e 3b04 ldr.w r3, [lr], #4 +100083e4: 4295 cmp r5, r2 +100083e6: ea83 0301 eor.w r3, r3, r1 +100083ea: ea43 0c0c orr.w ip, r3, ip +100083ee: d1f5 bne.n 100083dc +100083f0: f3cc 2307 ubfx r3, ip, #8, #8 +100083f4: ea4c 0303 orr.w r3, ip, r3 +100083f8: f3cc 4207 ubfx r2, ip, #16, #8 +100083fc: 4313 orrs r3, r2 +100083fe: ea43 631c orr.w r3, r3, ip, lsr #24 +10008402: 4546 cmp r6, r8 +10008404: b2db uxtb r3, r3 +10008406: d017 beq.n 10008438 +10008408: f814 2008 ldrb.w r2, [r4, r8] +1000840c: f817 1008 ldrb.w r1, [r7, r8] +10008410: f108 0501 add.w r5, r8, #1 +10008414: 404a eors r2, r1 +10008416: 42ae cmp r6, r5 +10008418: ea43 0302 orr.w r3, r3, r2 +1000841c: d90c bls.n 10008438 +1000841e: 5d61 ldrb r1, [r4, r5] +10008420: 5d7d ldrb r5, [r7, r5] +10008422: f108 0202 add.w r2, r8, #2 +10008426: 4069 eors r1, r5 +10008428: 430b orrs r3, r1 +1000842a: 4296 cmp r6, r2 +1000842c: b2db uxtb r3, r3 +1000842e: d903 bls.n 10008438 +10008430: 5cb9 ldrb r1, [r7, r2] +10008432: 5ca2 ldrb r2, [r4, r2] +10008434: 404a eors r2, r1 +10008436: 4313 orrs r3, r2 +10008438: 3b01 subs r3, #1 +1000843a: f413 7f80 tst.w r3, #256 @ 0x100 +1000843e: bf08 it eq +10008440: f06f 0022 mvneq.w r0, #34 @ 0x22 +10008444: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10008448: 4603 mov r3, r0 +1000844a: 4680 mov r8, r0 +1000844c: e7dc b.n 10008408 +1000844e: bf00 nop + +10008450 : +10008450: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10008454: 4605 mov r5, r0 +10008456: 460c mov r4, r1 +10008458: f000 fb3c bl 10008ad4 +1000845c: 2800 cmp r0, #0 +1000845e: d146 bne.n 100084ee +10008460: 2101 movs r1, #1 +10008462: 4628 mov r0, r5 +10008464: f7ff fada bl 10007a1c +10008468: 2800 cmp r0, #0 +1000846a: d140 bne.n 100084ee +1000846c: 686e ldr r6, [r5, #4] +1000846e: 2e00 cmp r6, #0 +10008470: d03d beq.n 100084ee +10008472: 1e73 subs r3, r6, #1 +10008474: 2b02 cmp r3, #2 +10008476: 682f ldr r7, [r5, #0] +10008478: d93b bls.n 100084f2 +1000847a: 4622 mov r2, r4 +1000847c: 46bc mov ip, r7 +1000847e: 4601 mov r1, r0 +10008480: f026 0803 bic.w r8, r6, #3 +10008484: eb04 0508 add.w r5, r4, r8 +10008488: f852 eb04 ldr.w lr, [r2], #4 +1000848c: f85c 3b04 ldr.w r3, [ip], #4 +10008490: 4295 cmp r5, r2 +10008492: ea83 030e eor.w r3, r3, lr +10008496: ea41 0103 orr.w r1, r1, r3 +1000849a: d1f5 bne.n 10008488 +1000849c: f3c1 2307 ubfx r3, r1, #8, #8 +100084a0: 430b orrs r3, r1 +100084a2: f3c1 4207 ubfx r2, r1, #16, #8 +100084a6: 4313 orrs r3, r2 +100084a8: ea43 6311 orr.w r3, r3, r1, lsr #24 +100084ac: 4546 cmp r6, r8 +100084ae: b2db uxtb r3, r3 +100084b0: d017 beq.n 100084e2 +100084b2: f814 2008 ldrb.w r2, [r4, r8] +100084b6: f817 1008 ldrb.w r1, [r7, r8] +100084ba: f108 0501 add.w r5, r8, #1 +100084be: 404a eors r2, r1 +100084c0: 42ae cmp r6, r5 +100084c2: ea43 0302 orr.w r3, r3, r2 +100084c6: d90c bls.n 100084e2 +100084c8: 5d61 ldrb r1, [r4, r5] +100084ca: 5d7d ldrb r5, [r7, r5] +100084cc: f108 0202 add.w r2, r8, #2 +100084d0: 4069 eors r1, r5 +100084d2: 430b orrs r3, r1 +100084d4: 4296 cmp r6, r2 +100084d6: b2db uxtb r3, r3 +100084d8: d903 bls.n 100084e2 +100084da: 5cb9 ldrb r1, [r7, r2] +100084dc: 5ca2 ldrb r2, [r4, r2] +100084de: 404a eors r2, r1 +100084e0: 4313 orrs r3, r2 +100084e2: 3b01 subs r3, #1 +100084e4: f413 7f80 tst.w r3, #256 @ 0x100 +100084e8: bf08 it eq +100084ea: f06f 0022 mvneq.w r0, #34 @ 0x22 +100084ee: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100084f2: 4603 mov r3, r0 +100084f4: 4680 mov r8, r0 +100084f6: e7dc b.n 100084b2 + +100084f8 : +100084f8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100084fc: 4605 mov r5, r0 +100084fe: 460c mov r4, r1 +10008500: f000 fae8 bl 10008ad4 +10008504: 2800 cmp r0, #0 +10008506: d146 bne.n 10008596 +10008508: 2102 movs r1, #2 +1000850a: 4628 mov r0, r5 +1000850c: f7ff fa86 bl 10007a1c +10008510: 2800 cmp r0, #0 +10008512: d140 bne.n 10008596 +10008514: 686e ldr r6, [r5, #4] +10008516: 2e00 cmp r6, #0 +10008518: d03d beq.n 10008596 +1000851a: 1e73 subs r3, r6, #1 +1000851c: 2b02 cmp r3, #2 +1000851e: 682f ldr r7, [r5, #0] +10008520: d93b bls.n 1000859a +10008522: 4622 mov r2, r4 +10008524: 46bc mov ip, r7 +10008526: 4601 mov r1, r0 +10008528: f026 0803 bic.w r8, r6, #3 +1000852c: eb04 0508 add.w r5, r4, r8 +10008530: f852 eb04 ldr.w lr, [r2], #4 +10008534: f85c 3b04 ldr.w r3, [ip], #4 +10008538: 4295 cmp r5, r2 +1000853a: ea83 030e eor.w r3, r3, lr +1000853e: ea41 0103 orr.w r1, r1, r3 +10008542: d1f5 bne.n 10008530 +10008544: f3c1 2307 ubfx r3, r1, #8, #8 +10008548: 430b orrs r3, r1 +1000854a: f3c1 4207 ubfx r2, r1, #16, #8 +1000854e: 4313 orrs r3, r2 +10008550: ea43 6311 orr.w r3, r3, r1, lsr #24 +10008554: 4546 cmp r6, r8 +10008556: b2db uxtb r3, r3 +10008558: d017 beq.n 1000858a +1000855a: f814 2008 ldrb.w r2, [r4, r8] +1000855e: f817 1008 ldrb.w r1, [r7, r8] +10008562: f108 0501 add.w r5, r8, #1 +10008566: 404a eors r2, r1 +10008568: 42ae cmp r6, r5 +1000856a: ea43 0302 orr.w r3, r3, r2 +1000856e: d90c bls.n 1000858a +10008570: 5d61 ldrb r1, [r4, r5] +10008572: 5d7d ldrb r5, [r7, r5] +10008574: f108 0202 add.w r2, r8, #2 +10008578: 4069 eors r1, r5 +1000857a: 430b orrs r3, r1 +1000857c: 4296 cmp r6, r2 +1000857e: b2db uxtb r3, r3 +10008580: d903 bls.n 1000858a +10008582: 5cb9 ldrb r1, [r7, r2] +10008584: 5ca2 ldrb r2, [r4, r2] +10008586: 404a eors r2, r1 +10008588: 4313 orrs r3, r2 +1000858a: 3b01 subs r3, #1 +1000858c: f413 7f80 tst.w r3, #256 @ 0x100 +10008590: bf08 it eq +10008592: f06f 0022 mvneq.w r0, #34 @ 0x22 +10008596: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000859a: 4603 mov r3, r0 +1000859c: 4680 mov r8, r0 +1000859e: e7dc b.n 1000855a + +100085a0 : +100085a0: 3023 adds r0, #35 @ 0x23 +100085a2: 2823 cmp r0, #35 @ 0x23 +100085a4: bf9a itte ls +100085a6: 4b02 ldrls r3, [pc, #8] @ (100085b0 ) +100085a8: f853 0020 ldrls.w r0, [r3, r0, lsl #2] +100085ac: 4801 ldrhi r0, [pc, #4] @ (100085b4 ) +100085ae: 4770 bx lr +100085b0: 1000d7dc .word 0x1000d7dc +100085b4: 1000c838 .word 0x1000c838 + +100085b8 : +100085b8: b570 push {r4, r5, r6, lr} +100085ba: b084 sub sp, #16 +100085bc: f89d 4024 ldrb.w r4, [sp, #36] @ 0x24 +100085c0: 4606 mov r6, r0 +100085c2: 2c02 cmp r4, #2 +100085c4: bf97 itett ls +100085c6: 4815 ldrls r0, [pc, #84] @ (1000861c ) +100085c8: 2000 movhi r0, #0 +100085ca: eb00 0084 addls.w r0, r0, r4, lsl #2 +100085ce: f8d0 0090 ldrls.w r0, [r0, #144] @ 0x90 +100085d2: e9cd 2302 strd r2, r3, [sp, #8] +100085d6: 9101 str r1, [sp, #4] +100085d8: f003 fd46 bl 1000c068 +100085dc: 4605 mov r5, r0 +100085de: 4630 mov r0, r6 +100085e0: f001 ff44 bl 1000a46c +100085e4: 1944 adds r4, r0, r5 +100085e6: 9801 ldr r0, [sp, #4] +100085e8: f001 ff40 bl 1000a46c +100085ec: 4606 mov r6, r0 +100085ee: 9802 ldr r0, [sp, #8] +100085f0: f001 ff3c bl 1000a46c +100085f4: 4605 mov r5, r0 +100085f6: 9803 ldr r0, [sp, #12] +100085f8: f001 ff24 bl 1000a444 +100085fc: 3410 adds r4, #16 +100085fe: 4434 add r4, r6 +10008600: 4606 mov r6, r0 +10008602: 9808 ldr r0, [sp, #32] +10008604: f001 ff1e bl 1000a444 +10008608: 4425 add r5, r4 +1000860a: 4604 mov r4, r0 +1000860c: 2013 movs r0, #19 +1000860e: f001 ff2d bl 1000a46c +10008612: 1975 adds r5, r6, r5 +10008614: 442c add r4, r5 +10008616: 4420 add r0, r4 +10008618: b004 add sp, #16 +1000861a: bd70 pop {r4, r5, r6, pc} +1000861c: 1000d7dc .word 0x1000d7dc + +10008620 : +10008620: b580 push {r7, lr} +10008622: b082 sub sp, #8 +10008624: af00 add r7, sp, #0 +10008626: 6078 str r0, [r7, #4] +10008628: 6039 str r1, [r7, #0] +1000862a: 4b05 ldr r3, [pc, #20] @ (10008640 ) +1000862c: 681b ldr r3, [r3, #0] +1000862e: 683a ldr r2, [r7, #0] +10008630: 2100 movs r1, #0 +10008632: 6878 ldr r0, [r7, #4] +10008634: 4798 blx r3 +10008636: bf00 nop +10008638: 3708 adds r7, #8 +1000863a: 46bd mov sp, r7 +1000863c: bd80 pop {r7, pc} +1000863e: bf00 nop +10008640: 1000d878 .word 0x1000d878 + +10008644 : +10008644: f44f 6280 mov.w r2, #1024 @ 0x400 +10008648: f003 bbf0 b.w 1000be2c + +1000864c : +1000864c: f44f 6280 mov.w r2, #1024 @ 0x400 +10008650: f003 bc94 b.w 1000bf7c + +10008654 : +10008654: b510 push {r4, lr} +10008656: f1a0 0308 sub.w r3, r0, #8 +1000865a: f1a1 0c08 sub.w ip, r1, #8 +1000865e: f500 7e7e add.w lr, r0, #1016 @ 0x3f8 +10008662: f853 1f08 ldr.w r1, [r3, #8]! +10008666: f85c 4f08 ldr.w r4, [ip, #8]! +1000866a: 685a ldr r2, [r3, #4] +1000866c: f8dc 0004 ldr.w r0, [ip, #4] +10008670: 4061 eors r1, r4 +10008672: 4042 eors r2, r0 +10008674: 4573 cmp r3, lr +10008676: e9c3 1200 strd r1, r2, [r3] +1000867a: d1f2 bne.n 10008662 +1000867c: bd10 pop {r4, pc} +1000867e: bf00 nop + +10008680 : +10008680: b189 cbz r1, 100086a6 +10008682: fb03 fc02 mul.w ip, r3, r2 +10008686: b953 cbnz r3, 1000869e +10008688: 6bc3 ldr r3, [r0, #60] @ 0x3c +1000868a: b510 push {r4, lr} +1000868c: 460c mov r4, r1 +1000868e: b16b cbz r3, 100086ac +10008690: 4661 mov r1, ip +10008692: 4620 mov r0, r4 +10008694: 4798 blx r3 +10008696: 6820 ldr r0, [r4, #0] +10008698: b168 cbz r0, 100086b6 +1000869a: 2000 movs r0, #0 +1000869c: bd10 pop {r4, pc} +1000869e: fbbc f3f3 udiv r3, ip, r3 +100086a2: 4293 cmp r3, r2 +100086a4: d0f0 beq.n 10008688 +100086a6: f06f 0015 mvn.w r0, #21 +100086aa: 4770 bx lr +100086ac: 4660 mov r0, ip +100086ae: f7f9 fac3 bl 10001c38 <__wrap_malloc> +100086b2: 6020 str r0, [r4, #0] +100086b4: e7f0 b.n 10008698 +100086b6: f06f 0015 mvn.w r0, #21 +100086ba: bd10 pop {r4, pc} + +100086bc : +100086bc: b500 push {lr} +100086be: 469e mov lr, r3 +100086c0: f8df c03c ldr.w ip, [pc, #60] @ 10008700 +100086c4: 4603 mov r3, r0 +100086c6: f8dc c000 ldr.w ip, [ip] +100086ca: 4608 mov r0, r1 +100086cc: b085 sub sp, #20 +100086ce: fb0e f102 mul.w r1, lr, r2 +100086d2: f1bc 0f00 cmp.w ip, #0 +100086d6: d008 beq.n 100086ea +100086d8: b138 cbz r0, 100086ea +100086da: e9cd 1302 strd r1, r3, [sp, #8] +100086de: 9001 str r0, [sp, #4] +100086e0: f7ff ff9e bl 10008620 +100086e4: e9dd 1302 ldrd r1, r3, [sp, #8] +100086e8: 9801 ldr r0, [sp, #4] +100086ea: 6c1b ldr r3, [r3, #64] @ 0x40 +100086ec: b11b cbz r3, 100086f6 +100086ee: b005 add sp, #20 +100086f0: f85d eb04 ldr.w lr, [sp], #4 +100086f4: 4718 bx r3 +100086f6: b005 add sp, #20 +100086f8: f85d eb04 ldr.w lr, [sp], #4 +100086fc: f7f9 baae b.w 10001c5c <__wrap_free> +10008700: 20001254 .word 0x20001254 + +10008704 : +10008704: b570 push {r4, r5, r6, lr} +10008706: b0be sub sp, #248 @ 0xf8 +10008708: 460c mov r4, r1 +1000870a: 4606 mov r6, r0 +1000870c: 2140 movs r1, #64 @ 0x40 +1000870e: a802 add r0, sp, #8 +10008710: 4615 mov r5, r2 +10008712: f002 faf9 bl 1000ad08 +10008716: 2204 movs r2, #4 +10008718: 6b23 ldr r3, [r4, #48] @ 0x30 +1000871a: eb0d 0102 add.w r1, sp, r2 +1000871e: a802 add r0, sp, #8 +10008720: 9301 str r3, [sp, #4] +10008722: f002 fb51 bl 1000adc8 +10008726: 2204 movs r2, #4 +10008728: 6863 ldr r3, [r4, #4] +1000872a: eb0d 0102 add.w r1, sp, r2 +1000872e: a802 add r0, sp, #8 +10008730: 9301 str r3, [sp, #4] +10008732: f002 fb49 bl 1000adc8 +10008736: 2204 movs r2, #4 +10008738: 6ae3 ldr r3, [r4, #44] @ 0x2c +1000873a: eb0d 0102 add.w r1, sp, r2 +1000873e: a802 add r0, sp, #8 +10008740: 9301 str r3, [sp, #4] +10008742: f002 fb41 bl 1000adc8 +10008746: 2204 movs r2, #4 +10008748: 6aa3 ldr r3, [r4, #40] @ 0x28 +1000874a: eb0d 0102 add.w r1, sp, r2 +1000874e: a802 add r0, sp, #8 +10008750: 9301 str r3, [sp, #4] +10008752: f002 fb39 bl 1000adc8 +10008756: 2204 movs r2, #4 +10008758: 6ba3 ldr r3, [r4, #56] @ 0x38 +1000875a: eb0d 0102 add.w r1, sp, r2 +1000875e: a802 add r0, sp, #8 +10008760: 9301 str r3, [sp, #4] +10008762: f002 fb31 bl 1000adc8 +10008766: 2204 movs r2, #4 +10008768: a802 add r0, sp, #8 +1000876a: eb0d 0102 add.w r1, sp, r2 +1000876e: 9501 str r5, [sp, #4] +10008770: f002 fb2a bl 1000adc8 +10008774: 2204 movs r2, #4 +10008776: 68e3 ldr r3, [r4, #12] +10008778: eb0d 0102 add.w r1, sp, r2 +1000877c: a802 add r0, sp, #8 +1000877e: 9301 str r3, [sp, #4] +10008780: f002 fb22 bl 1000adc8 +10008784: 68a1 ldr r1, [r4, #8] +10008786: b131 cbz r1, 10008796 +10008788: 68e2 ldr r2, [r4, #12] +1000878a: a802 add r0, sp, #8 +1000878c: f002 fb1c bl 1000adc8 +10008790: 6c63 ldr r3, [r4, #68] @ 0x44 +10008792: 07da lsls r2, r3, #31 +10008794: d43a bmi.n 1000880c +10008796: 2204 movs r2, #4 +10008798: 6963 ldr r3, [r4, #20] +1000879a: eb0d 0102 add.w r1, sp, r2 +1000879e: a802 add r0, sp, #8 +100087a0: 9301 str r3, [sp, #4] +100087a2: f002 fb11 bl 1000adc8 +100087a6: 6921 ldr r1, [r4, #16] +100087a8: b119 cbz r1, 100087b2 +100087aa: 6962 ldr r2, [r4, #20] +100087ac: a802 add r0, sp, #8 +100087ae: f002 fb0b bl 1000adc8 +100087b2: 2204 movs r2, #4 +100087b4: 69e3 ldr r3, [r4, #28] +100087b6: eb0d 0102 add.w r1, sp, r2 +100087ba: a802 add r0, sp, #8 +100087bc: 9301 str r3, [sp, #4] +100087be: f002 fb03 bl 1000adc8 +100087c2: 69a1 ldr r1, [r4, #24] +100087c4: b131 cbz r1, 100087d4 +100087c6: 69e2 ldr r2, [r4, #28] +100087c8: a802 add r0, sp, #8 +100087ca: f002 fafd bl 1000adc8 +100087ce: 6c63 ldr r3, [r4, #68] @ 0x44 +100087d0: 079b lsls r3, r3, #30 +100087d2: d414 bmi.n 100087fe +100087d4: 2204 movs r2, #4 +100087d6: 6a63 ldr r3, [r4, #36] @ 0x24 +100087d8: eb0d 0102 add.w r1, sp, r2 +100087dc: a802 add r0, sp, #8 +100087de: 9301 str r3, [sp, #4] +100087e0: f002 faf2 bl 1000adc8 +100087e4: 6a21 ldr r1, [r4, #32] +100087e6: b119 cbz r1, 100087f0 +100087e8: 6a62 ldr r2, [r4, #36] @ 0x24 +100087ea: a802 add r0, sp, #8 +100087ec: f002 faec bl 1000adc8 +100087f0: 2240 movs r2, #64 @ 0x40 +100087f2: 4631 mov r1, r6 +100087f4: a802 add r0, sp, #8 +100087f6: f002 fc0f bl 1000b018 +100087fa: b03e add sp, #248 @ 0xf8 +100087fc: bd70 pop {r4, r5, r6, pc} +100087fe: e9d4 0106 ldrd r0, r1, [r4, #24] +10008802: f7ff ff0d bl 10008620 +10008806: 2300 movs r3, #0 +10008808: 61e3 str r3, [r4, #28] +1000880a: e7e3 b.n 100087d4 +1000880c: e9d4 0102 ldrd r0, r1, [r4, #8] +10008810: f7ff ff06 bl 10008620 +10008814: 2300 movs r3, #0 +10008816: 60e3 str r3, [r4, #12] +10008818: e7bd b.n 10008796 +1000881a: bf00 nop + +1000881c : +1000881c: 4b03 ldr r3, [pc, #12] @ (1000882c ) +1000881e: 681b ldr r3, [r3, #0] +10008820: b113 cbz r3, 10008828 +10008822: b108 cbz r0, 10008828 +10008824: f7ff befc b.w 10008620 +10008828: 4770 bx lr +1000882a: bf00 nop +1000882c: 20001254 .word 0x20001254 + +10008830 : +10008830: 2800 cmp r0, #0 +10008832: d052 beq.n 100088da +10008834: 2900 cmp r1, #0 +10008836: d050 beq.n 100088da +10008838: e92d 4f70 stmdb sp!, {r4, r5, r6, r8, r9, sl, fp, lr} +1000883c: 460c mov r4, r1 +1000883e: 680b ldr r3, [r1, #0] +10008840: 694e ldr r6, [r1, #20] +10008842: 4956 ldr r1, [pc, #344] @ (1000899c ) +10008844: f5ad 6d01 sub.w sp, sp, #2064 @ 0x810 +10008848: 1871 adds r1, r6, r1 +1000884a: 9003 str r0, [sp, #12] +1000884c: f44f 6280 mov.w r2, #1024 @ 0x400 +10008850: 028d lsls r5, r1, #10 +10008852: a804 add r0, sp, #16 +10008854: eb03 2181 add.w r1, r3, r1, lsl #10 +10008858: 9302 str r3, [sp, #8] +1000885a: f003 fb8f bl 1000bf7c +1000885e: 69a3 ldr r3, [r4, #24] +10008860: 2b01 cmp r3, #1 +10008862: d957 bls.n 10008914 +10008864: 2b03 cmp r3, #3 +10008866: f240 8091 bls.w 1000898c +1000886a: 9a02 ldr r2, [sp, #8] +1000886c: f1a3 0804 sub.w r8, r3, #4 +10008870: eb02 20c6 add.w r0, r2, r6, lsl #11 +10008874: 2603 movs r6, #3 +10008876: 461a mov r2, r3 +10008878: f028 0801 bic.w r8, r8, #1 +1000887c: f5a0 6081 sub.w r0, r0, #1032 @ 0x408 +10008880: f505 6580 add.w r5, r5, #1024 @ 0x400 +10008884: f108 0805 add.w r8, r8, #5 +10008888: f10d 0908 add.w r9, sp, #8 +1000888c: f50d 6e81 add.w lr, sp, #1032 @ 0x408 +10008890: eb00 0a05 add.w sl, r0, r5 +10008894: 464b mov r3, r9 +10008896: 46d4 mov ip, sl +10008898: 4693 mov fp, r2 +1000889a: 9601 str r6, [sp, #4] +1000889c: f853 6f08 ldr.w r6, [r3, #8]! +100088a0: f850 1f08 ldr.w r1, [r0, #8]! +100088a4: 685a ldr r2, [r3, #4] +100088a6: 404e eors r6, r1 +100088a8: 6841 ldr r1, [r0, #4] +100088aa: 601e str r6, [r3, #0] +100088ac: 4051 eors r1, r2 +100088ae: 6059 str r1, [r3, #4] +100088b0: f85c 2f08 ldr.w r2, [ip, #8]! +100088b4: 4573 cmp r3, lr +100088b6: ea82 0206 eor.w r2, r2, r6 +100088ba: f8dc 6004 ldr.w r6, [ip, #4] +100088be: 601a str r2, [r3, #0] +100088c0: ea86 0601 eor.w r6, r6, r1 +100088c4: 605e str r6, [r3, #4] +100088c6: d1e9 bne.n 1000889c +100088c8: 9e01 ldr r6, [sp, #4] +100088ca: 465a mov r2, fp +100088cc: 1cb3 adds r3, r6, #2 +100088ce: 4543 cmp r3, r8 +100088d0: eb0a 0005 add.w r0, sl, r5 +100088d4: d002 beq.n 100088dc +100088d6: 461e mov r6, r3 +100088d8: e7da b.n 10008890 +100088da: 4770 bx lr +100088dc: 465b mov r3, fp +100088de: fb06 5805 mla r8, r6, r5, r5 +100088e2: 9a02 ldr r2, [sp, #8] +100088e4: f5a2 6281 sub.w r2, r2, #1032 @ 0x408 +100088e8: 4490 add r8, r2 +100088ea: 464a mov r2, r9 +100088ec: 46c4 mov ip, r8 +100088ee: 3601 adds r6, #1 +100088f0: f852 0f08 ldr.w r0, [r2, #8]! +100088f4: f85c 1f08 ldr.w r1, [ip, #8]! +100088f8: 4572 cmp r2, lr +100088fa: ea80 0001 eor.w r0, r0, r1 +100088fe: f8dc 1004 ldr.w r1, [ip, #4] +10008902: 6010 str r0, [r2, #0] +10008904: 6850 ldr r0, [r2, #4] +10008906: ea81 0100 eor.w r1, r1, r0 +1000890a: 6051 str r1, [r2, #4] +1000890c: d1f0 bne.n 100088f0 +1000890e: 42b3 cmp r3, r6 +10008910: 44a8 add r8, r5 +10008912: d8ea bhi.n 100088ea +10008914: f44f 6280 mov.w r2, #1024 @ 0x400 +10008918: a904 add r1, sp, #16 +1000891a: f50d 6082 add.w r0, sp, #1040 @ 0x410 +1000891e: f003 fb2d bl 1000bf7c +10008922: 9803 ldr r0, [sp, #12] +10008924: 4d1e ldr r5, [pc, #120] @ (100089a0 ) +10008926: f44f 6380 mov.w r3, #1024 @ 0x400 +1000892a: e9d0 0100 ldrd r0, r1, [r0] +1000892e: f50d 6282 add.w r2, sp, #1040 @ 0x410 +10008932: f002 fc83 bl 1000b23c +10008936: 682b ldr r3, [r5, #0] +10008938: b1bb cbz r3, 1000896a +1000893a: f44f 6180 mov.w r1, #1024 @ 0x400 +1000893e: a804 add r0, sp, #16 +10008940: f7ff fe6e bl 10008620 +10008944: 682b ldr r3, [r5, #0] +10008946: b183 cbz r3, 1000896a +10008948: f44f 6180 mov.w r1, #1024 @ 0x400 +1000894c: f50d 6082 add.w r0, sp, #1040 @ 0x410 +10008950: f7ff fe66 bl 10008620 +10008954: 68e3 ldr r3, [r4, #12] +10008956: 682a ldr r2, [r5, #0] +10008958: 6825 ldr r5, [r4, #0] +1000895a: 029c lsls r4, r3, #10 +1000895c: b142 cbz r2, 10008970 +1000895e: b13d cbz r5, 10008970 +10008960: 4621 mov r1, r4 +10008962: 4628 mov r0, r5 +10008964: f7ff fe5c bl 10008620 +10008968: e002 b.n 10008970 +1000896a: 68e3 ldr r3, [r4, #12] +1000896c: 6825 ldr r5, [r4, #0] +1000896e: 029c lsls r4, r3, #10 +10008970: 9b03 ldr r3, [sp, #12] +10008972: 6c1b ldr r3, [r3, #64] @ 0x40 +10008974: b133 cbz r3, 10008984 +10008976: 4621 mov r1, r4 +10008978: 4628 mov r0, r5 +1000897a: 4798 blx r3 +1000897c: f50d 6d01 add.w sp, sp, #2064 @ 0x810 +10008980: e8bd 8f70 ldmia.w sp!, {r4, r5, r6, r8, r9, sl, fp, pc} +10008984: 4628 mov r0, r5 +10008986: f7f9 f969 bl 10001c5c <__wrap_free> +1000898a: e7f7 b.n 1000897c +1000898c: 2601 movs r6, #1 +1000898e: f505 6580 add.w r5, r5, #1024 @ 0x400 +10008992: f10d 0908 add.w r9, sp, #8 +10008996: f50d 6e81 add.w lr, sp, #1032 @ 0x408 +1000899a: e7a0 b.n 100088de +1000899c: 003fffff .word 0x003fffff +100089a0: 20001254 .word 0x20001254 + +100089a4 : +100089a4: b538 push {r3, r4, r5, lr} +100089a6: 680c ldr r4, [r1, #0] +100089a8: fba2 ec02 umull lr, ip, r2, r2 +100089ac: 461d mov r5, r3 +100089ae: 6942 ldr r2, [r0, #20] +100089b0: 68cb ldr r3, [r1, #12] +100089b2: f891 e008 ldrb.w lr, [r1, #8] +100089b6: b97c cbnz r4, 100089d8 +100089b8: f1be 0f00 cmp.w lr, #0 +100089bc: d132 bne.n 10008a24 +100089be: 1e59 subs r1, r3, #1 +100089c0: fbac c101 umull ip, r1, ip, r1 +100089c4: 1e98 subs r0, r3, #2 +100089c6: 1a40 subs r0, r0, r1 +100089c8: eb6c 0c0c sbc.w ip, ip, ip +100089cc: 4661 mov r1, ip +100089ce: 2300 movs r3, #0 +100089d0: f003 fce2 bl 1000c398 <____aeabi_uldivmod_veneer> +100089d4: 4610 mov r0, r2 +100089d6: bd38 pop {r3, r4, r5, pc} +100089d8: 6901 ldr r1, [r0, #16] +100089da: b9c5 cbnz r5, 10008a0e +100089dc: 1a50 subs r0, r2, r1 +100089de: 2b00 cmp r3, #0 +100089e0: bf08 it eq +100089e2: 3801 subeq r0, #1 +100089e4: fbac 3c00 umull r3, ip, ip, r0 +100089e8: 3801 subs r0, #1 +100089ea: ebb0 000c subs.w r0, r0, ip +100089ee: eb6c 0c0c sbc.w ip, ip, ip +100089f2: f1be 0f03 cmp.w lr, #3 +100089f6: d004 beq.n 10008a02 +100089f8: fb0e 1301 mla r3, lr, r1, r1 +100089fc: 1818 adds r0, r3, r0 +100089fe: f14c 0c00 adc.w ip, ip, #0 +10008a02: 4661 mov r1, ip +10008a04: 2300 movs r3, #0 +10008a06: f003 fcc7 bl 1000c398 <____aeabi_uldivmod_veneer> +10008a0a: 4610 mov r0, r2 +10008a0c: bd38 pop {r3, r4, r5, pc} +10008a0e: 1e50 subs r0, r2, #1 +10008a10: 1a40 subs r0, r0, r1 +10008a12: 4418 add r0, r3 +10008a14: fbac 3c00 umull r3, ip, ip, r0 +10008a18: 3801 subs r0, #1 +10008a1a: ebb0 000c subs.w r0, r0, ip +10008a1e: eb6c 0c0c sbc.w ip, ip, ip +10008a22: e7e6 b.n 100089f2 +10008a24: 6900 ldr r0, [r0, #16] +10008a26: fb00 f00e mul.w r0, r0, lr +10008a2a: b16d cbz r5, 10008a48 +10008a2c: 3b01 subs r3, #1 +10008a2e: 4403 add r3, r0 +10008a30: fbac c003 umull ip, r0, ip, r3 +10008a34: 3b01 subs r3, #1 +10008a36: 1a18 subs r0, r3, r0 +10008a38: eb6c 0c0c sbc.w ip, ip, ip +10008a3c: 4661 mov r1, ip +10008a3e: 2300 movs r3, #0 +10008a40: f003 fcaa bl 1000c398 <____aeabi_uldivmod_veneer> +10008a44: 4610 mov r0, r2 +10008a46: bd38 pop {r3, r4, r5, pc} +10008a48: 42ab cmp r3, r5 +10008a4a: bf08 it eq +10008a4c: 3801 subeq r0, #1 +10008a4e: fbac 3c00 umull r3, ip, ip, r0 +10008a52: 3801 subs r0, #1 +10008a54: ebb0 000c subs.w r0, r0, ip +10008a58: eb6c 0c0c sbc.w ip, ip, ip +10008a5c: 4661 mov r1, ip +10008a5e: 2300 movs r3, #0 +10008a60: f003 fc9a bl 1000c398 <____aeabi_uldivmod_veneer> +10008a64: 4610 mov r0, r2 +10008a66: bd38 pop {r3, r4, r5, pc} + +10008a68 : +10008a68: b388 cbz r0, 10008ace +10008a6a: 6983 ldr r3, [r0, #24] +10008a6c: b37b cbz r3, 10008ace +10008a6e: 6882 ldr r2, [r0, #8] +10008a70: b35a cbz r2, 10008aca +10008a72: e92d 4f70 stmdb sp!, {r4, r5, r6, r8, r9, sl, fp, lr} +10008a76: f04f 0800 mov.w r8, #0 +10008a7a: 4683 mov fp, r0 +10008a7c: 46c1 mov r9, r8 +10008a7e: b086 sub sp, #24 +10008a80: ad02 add r5, sp, #8 +10008a82: f04f 0a00 mov.w sl, #0 +10008a86: b1b3 cbz r3, 10008ab6 +10008a88: 4656 mov r6, sl +10008a8a: 2400 movs r4, #0 +10008a8c: e9cd 8402 strd r8, r4, [sp, #8] +10008a90: f88d 6010 strb.w r6, [sp, #16] +10008a94: f8cd 9000 str.w r9, [sp] +10008a98: e895 000e ldmia.w r5, {r1, r2, r3} +10008a9c: 4658 mov r0, fp +10008a9e: f000 fff9 bl 10009a94 +10008aa2: f8db 3018 ldr.w r3, [fp, #24] +10008aa6: 3401 adds r4, #1 +10008aa8: 429c cmp r4, r3 +10008aaa: d3ef bcc.n 10008a8c +10008aac: f10a 0a01 add.w sl, sl, #1 +10008ab0: f1ba 0f04 cmp.w sl, #4 +10008ab4: d1e7 bne.n 10008a86 +10008ab6: f8db 2008 ldr.w r2, [fp, #8] +10008aba: f108 0801 add.w r8, r8, #1 +10008abe: 4590 cmp r8, r2 +10008ac0: d3df bcc.n 10008a82 +10008ac2: 2000 movs r0, #0 +10008ac4: b006 add sp, #24 +10008ac6: e8bd 8f70 ldmia.w sp!, {r4, r5, r6, r8, r9, sl, fp, pc} +10008aca: 2000 movs r0, #0 +10008acc: 4770 bx lr +10008ace: f06f 0018 mvn.w r0, #24 +10008ad2: 4770 bx lr + +10008ad4 : +10008ad4: 2800 cmp r0, #0 +10008ad6: d06f beq.n 10008bb8 +10008ad8: 6803 ldr r3, [r0, #0] +10008ada: 2b00 cmp r3, #0 +10008adc: d069 beq.n 10008bb2 +10008ade: 6843 ldr r3, [r0, #4] +10008ae0: 2b03 cmp r3, #3 +10008ae2: d951 bls.n 10008b88 +10008ae4: 6883 ldr r3, [r0, #8] +10008ae6: 2b00 cmp r3, #0 +10008ae8: d02c beq.n 10008b44 +10008aea: e9d0 2304 ldrd r2, r3, [r0, #16] +10008aee: 2a00 cmp r2, #0 +10008af0: d02e beq.n 10008b50 +10008af2: 2b07 cmp r3, #7 +10008af4: d963 bls.n 10008bbe +10008af6: 6983 ldr r3, [r0, #24] +10008af8: 2b00 cmp r3, #0 +10008afa: d030 beq.n 10008b5e +10008afc: 6a03 ldr r3, [r0, #32] +10008afe: 2b00 cmp r3, #0 +10008b00: d033 beq.n 10008b6a +10008b02: 6ac3 ldr r3, [r0, #44] @ 0x2c +10008b04: 2b07 cmp r3, #7 +10008b06: d93c bls.n 10008b82 +10008b08: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 +10008b0c: d83f bhi.n 10008b8e +10008b0e: 6b02 ldr r2, [r0, #48] @ 0x30 +10008b10: ebb3 0fc2 cmp.w r3, r2, lsl #3 +10008b14: d335 bcc.n 10008b82 +10008b16: 6a83 ldr r3, [r0, #40] @ 0x28 +10008b18: 2b00 cmp r3, #0 +10008b1a: d03b beq.n 10008b94 +10008b1c: 2a00 cmp r2, #0 +10008b1e: d03c beq.n 10008b9a +10008b20: f1b2 7f80 cmp.w r2, #16777216 @ 0x1000000 +10008b24: d23c bcs.n 10008ba0 +10008b26: 6b43 ldr r3, [r0, #52] @ 0x34 +10008b28: 2b00 cmp r3, #0 +10008b2a: d03c beq.n 10008ba6 +10008b2c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 +10008b30: d23c bcs.n 10008bac +10008b32: e9d0 320f ldrd r3, r2, [r0, #60] @ 0x3c +10008b36: b1f3 cbz r3, 10008b76 +10008b38: 2a00 cmp r2, #0 +10008b3a: bf0c ite eq +10008b3c: f06f 0016 mvneq.w r0, #22 +10008b40: 2000 movne r0, #0 +10008b42: 4770 bx lr +10008b44: 68c3 ldr r3, [r0, #12] +10008b46: 2b00 cmp r3, #0 +10008b48: d0cf beq.n 10008aea +10008b4a: f06f 0011 mvn.w r0, #17 +10008b4e: 4770 bx lr +10008b50: 4293 cmp r3, r2 +10008b52: bf14 ite ne +10008b54: f06f 0012 mvnne.w r0, #18 +10008b58: f06f 0005 mvneq.w r0, #5 +10008b5c: 4770 bx lr +10008b5e: 69c3 ldr r3, [r0, #28] +10008b60: 2b00 cmp r3, #0 +10008b62: d0cb beq.n 10008afc +10008b64: f06f 0013 mvn.w r0, #19 +10008b68: 4770 bx lr +10008b6a: 6a43 ldr r3, [r0, #36] @ 0x24 +10008b6c: 2b00 cmp r3, #0 +10008b6e: d0c8 beq.n 10008b02 +10008b70: f06f 0014 mvn.w r0, #20 +10008b74: 4770 bx lr +10008b76: 429a cmp r2, r3 +10008b78: bf14 ite ne +10008b7a: f06f 0017 mvnne.w r0, #23 +10008b7e: 4618 moveq r0, r3 +10008b80: 4770 bx lr +10008b82: f06f 000d mvn.w r0, #13 +10008b86: 4770 bx lr +10008b88: f06f 0001 mvn.w r0, #1 +10008b8c: 4770 bx lr +10008b8e: f06f 000e mvn.w r0, #14 +10008b92: 4770 bx lr +10008b94: f06f 000b mvn.w r0, #11 +10008b98: 4770 bx lr +10008b9a: f06f 000f mvn.w r0, #15 +10008b9e: 4770 bx lr +10008ba0: f06f 0010 mvn.w r0, #16 +10008ba4: 4770 bx lr +10008ba6: f06f 001b mvn.w r0, #27 +10008baa: 4770 bx lr +10008bac: f06f 001c mvn.w r0, #28 +10008bb0: 4770 bx lr +10008bb2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10008bb6: 4770 bx lr +10008bb8: f06f 0018 mvn.w r0, #24 +10008bbc: 4770 bx lr +10008bbe: f06f 0005 mvn.w r0, #5 +10008bc2: 4770 bx lr + +10008bc4 : +10008bc4: e92d 4370 stmdb sp!, {r4, r5, r6, r8, r9, lr} +10008bc8: 698b ldr r3, [r1, #24] +10008bca: f5ad 6d80 sub.w sp, sp, #1024 @ 0x400 +10008bce: 2b00 cmp r3, #0 +10008bd0: d042 beq.n 10008c58 +10008bd2: 2500 movs r5, #0 +10008bd4: 460e mov r6, r1 +10008bd6: 4681 mov r9, r0 +10008bd8: 46a8 mov r8, r5 +10008bda: 2348 movs r3, #72 @ 0x48 +10008bdc: 464a mov r2, r9 +10008bde: f44f 6180 mov.w r1, #1024 @ 0x400 +10008be2: 4668 mov r0, sp +10008be4: f8c9 8040 str.w r8, [r9, #64] @ 0x40 +10008be8: f8c9 5044 str.w r5, [r9, #68] @ 0x44 +10008bec: f002 fb26 bl 1000b23c +10008bf0: 466c mov r4, sp +10008bf2: 466b mov r3, sp +10008bf4: 6971 ldr r1, [r6, #20] +10008bf6: 6832 ldr r2, [r6, #0] +10008bf8: fb05 f101 mul.w r1, r5, r1 +10008bfc: eb02 2281 add.w r2, r2, r1, lsl #10 +10008c00: 3a08 subs r2, #8 +10008c02: e9d3 1000 ldrd r1, r0, [r3] +10008c06: 3308 adds r3, #8 +10008c08: f842 1f08 str.w r1, [r2, #8]! +10008c0c: f50d 6180 add.w r1, sp, #1024 @ 0x400 +10008c10: 428b cmp r3, r1 +10008c12: 6050 str r0, [r2, #4] +10008c14: d1f5 bne.n 10008c02 +10008c16: f04f 0c01 mov.w ip, #1 +10008c1a: 2348 movs r3, #72 @ 0x48 +10008c1c: 464a mov r2, r9 +10008c1e: f44f 6180 mov.w r1, #1024 @ 0x400 +10008c22: 4668 mov r0, sp +10008c24: f8c9 c040 str.w ip, [r9, #64] @ 0x40 +10008c28: f002 fb08 bl 1000b23c +10008c2c: 6972 ldr r2, [r6, #20] +10008c2e: 6833 ldr r3, [r6, #0] +10008c30: fb05 f202 mul.w r2, r5, r2 +10008c34: eb03 2382 add.w r3, r3, r2, lsl #10 +10008c38: f503 737e add.w r3, r3, #1016 @ 0x3f8 +10008c3c: e9d4 1200 ldrd r1, r2, [r4] +10008c40: f843 1f08 str.w r1, [r3, #8]! +10008c44: 3408 adds r4, #8 +10008c46: 605a str r2, [r3, #4] +10008c48: f50d 6280 add.w r2, sp, #1024 @ 0x400 +10008c4c: 4294 cmp r4, r2 +10008c4e: d1f5 bne.n 10008c3c +10008c50: 69b3 ldr r3, [r6, #24] +10008c52: 3501 adds r5, #1 +10008c54: 42ab cmp r3, r5 +10008c56: d8c0 bhi.n 10008bda +10008c58: 4b05 ldr r3, [pc, #20] @ (10008c70 ) +10008c5a: 681b ldr r3, [r3, #0] +10008c5c: b123 cbz r3, 10008c68 +10008c5e: f44f 6180 mov.w r1, #1024 @ 0x400 +10008c62: 4668 mov r0, sp +10008c64: f7ff fcdc bl 10008620 +10008c68: f50d 6d80 add.w sp, sp, #1024 @ 0x400 +10008c6c: e8bd 8370 ldmia.w sp!, {r4, r5, r6, r8, r9, pc} +10008c70: 20001254 .word 0x20001254 + +10008c74 : +10008c74: b109 cbz r1, 10008c7a +10008c76: b100 cbz r0, 10008c7a +10008c78: e544 b.n 10008704 +10008c7a: 4770 bx lr + +10008c7c : +10008c7c: 2800 cmp r0, #0 +10008c7e: d036 beq.n 10008cee +10008c80: 2900 cmp r1, #0 +10008c82: d034 beq.n 10008cee +10008c84: b530 push {r4, r5, lr} +10008c86: 68c2 ldr r2, [r0, #12] +10008c88: b093 sub sp, #76 @ 0x4c +10008c8a: f3c2 0415 ubfx r4, r2, #0, #22 +10008c8e: 42a2 cmp r2, r4 +10008c90: 4605 mov r5, r0 +10008c92: 6281 str r1, [r0, #40] @ 0x28 +10008c94: ea4f 2c82 mov.w ip, r2, lsl #10 +10008c98: d126 bne.n 10008ce8 +10008c9a: 6bcb ldr r3, [r1, #60] @ 0x3c +10008c9c: 460c mov r4, r1 +10008c9e: b1f3 cbz r3, 10008cde +10008ca0: 4661 mov r1, ip +10008ca2: 4798 blx r3 +10008ca4: 6828 ldr r0, [r5, #0] +10008ca6: b1f8 cbz r0, 10008ce8 +10008ca8: 4621 mov r1, r4 +10008caa: 4c12 ldr r4, [pc, #72] @ (10008cf4 ) +10008cac: 4668 mov r0, sp +10008cae: f895 2020 ldrb.w r2, [r5, #32] +10008cb2: f7ff fd27 bl 10008704 +10008cb6: 6823 ldr r3, [r4, #0] +10008cb8: b11b cbz r3, 10008cc2 +10008cba: 2108 movs r1, #8 +10008cbc: a810 add r0, sp, #64 @ 0x40 +10008cbe: f7ff fcaf bl 10008620 +10008cc2: 4629 mov r1, r5 +10008cc4: 4668 mov r0, sp +10008cc6: f7ff ff7d bl 10008bc4 +10008cca: 6823 ldr r3, [r4, #0] +10008ccc: b913 cbnz r3, 10008cd4 +10008cce: 2000 movs r0, #0 +10008cd0: b013 add sp, #76 @ 0x4c +10008cd2: bd30 pop {r4, r5, pc} +10008cd4: 2148 movs r1, #72 @ 0x48 +10008cd6: 4668 mov r0, sp +10008cd8: f7ff fca2 bl 10008620 +10008cdc: e7f7 b.n 10008cce +10008cde: 4660 mov r0, ip +10008ce0: f7f8 ffaa bl 10001c38 <__wrap_malloc> +10008ce4: 6028 str r0, [r5, #0] +10008ce6: e7de b.n 10008ca6 +10008ce8: f06f 0015 mvn.w r0, #21 +10008cec: e7f0 b.n 10008cd0 +10008cee: f06f 0018 mvn.w r0, #24 +10008cf2: 4770 bx lr +10008cf4: 20001254 .word 0x20001254 + +10008cf8 : +10008cf8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10008cfc: 4606 mov r6, r0 +10008cfe: 461d mov r5, r3 +10008d00: f6ad 0d9c subw sp, sp, #2204 @ 0x89c +10008d04: a826 add r0, sp, #152 @ 0x98 +10008d06: 4614 mov r4, r2 +10008d08: f7ff fca0 bl 1000864c +10008d0c: 4631 mov r1, r6 +10008d0e: a826 add r0, sp, #152 @ 0x98 +10008d10: f7ff fca0 bl 10008654 +10008d14: a926 add r1, sp, #152 @ 0x98 +10008d16: f50d 6093 add.w r0, sp, #1176 @ 0x498 +10008d1a: f7ff fc97 bl 1000864c +10008d1e: 2d00 cmp r5, #0 +10008d20: f040 86b0 bne.w 10009a84 +10008d24: ab26 add r3, sp, #152 @ 0x98 +10008d26: 461f mov r7, r3 +10008d28: 9325 str r3, [sp, #148] @ 0x94 +10008d2a: 9424 str r4, [sp, #144] @ 0x90 +10008d2c: 6a3d ldr r5, [r7, #32] +10008d2e: 6839 ldr r1, [r7, #0] +10008d30: 6a7c ldr r4, [r7, #36] @ 0x24 +10008d32: fba1 2805 umull r2, r8, r1, r5 +10008d36: 687b ldr r3, [r7, #4] +10008d38: 1892 adds r2, r2, r2 +10008d3a: eb48 0808 adc.w r8, r8, r8 +10008d3e: 1949 adds r1, r1, r5 +10008d40: eb43 0304 adc.w r3, r3, r4 +10008d44: 1852 adds r2, r2, r1 +10008d46: 68f9 ldr r1, [r7, #12] +10008d48: eb48 0803 adc.w r8, r8, r3 +10008d4c: 9106 str r1, [sp, #24] +10008d4e: 6ef9 ldr r1, [r7, #108] @ 0x6c +10008d50: 6e3b ldr r3, [r7, #96] @ 0x60 +10008d52: 910d str r1, [sp, #52] @ 0x34 +10008d54: 6cb9 ldr r1, [r7, #72] @ 0x48 +10008d56: ea82 0e03 eor.w lr, r2, r3 +10008d5a: 9107 str r1, [sp, #28] +10008d5c: 6afb ldr r3, [r7, #44] @ 0x2c +10008d5e: 6cf9 ldr r1, [r7, #76] @ 0x4c +10008d60: 9304 str r3, [sp, #16] +10008d62: 9108 str r1, [sp, #32] +10008d64: 6ebb ldr r3, [r7, #104] @ 0x68 +10008d66: 6939 ldr r1, [r7, #16] +10008d68: 930c str r3, [sp, #48] @ 0x30 +10008d6a: 9109 str r1, [sp, #36] @ 0x24 +10008d6c: 6b3b ldr r3, [r7, #48] @ 0x30 +10008d6e: 6b79 ldr r1, [r7, #52] @ 0x34 +10008d70: 9301 str r3, [sp, #4] +10008d72: 9105 str r1, [sp, #20] +10008d74: 697b ldr r3, [r7, #20] +10008d76: 6f79 ldr r1, [r7, #116] @ 0x74 +10008d78: f8d7 a028 ldr.w sl, [r7, #40] @ 0x28 +10008d7c: f8d7 b040 ldr.w fp, [r7, #64] @ 0x40 +10008d80: 68b8 ldr r0, [r7, #8] +10008d82: 6e7e ldr r6, [r7, #100] @ 0x64 +10008d84: f8d7 9044 ldr.w r9, [r7, #68] @ 0x44 +10008d88: 930a str r3, [sp, #40] @ 0x28 +10008d8a: 9121 str r1, [sp, #132] @ 0x84 +10008d8c: 6d39 ldr r1, [r7, #80] @ 0x50 +10008d8e: 6f3b ldr r3, [r7, #112] @ 0x70 +10008d90: ea88 0606 eor.w r6, r8, r6 +10008d94: 9320 str r3, [sp, #128] @ 0x80 +10008d96: 6bbb ldr r3, [r7, #56] @ 0x38 +10008d98: 910b str r1, [sp, #44] @ 0x2c +10008d9a: 9302 str r3, [sp, #8] +10008d9c: 6bfb ldr r3, [r7, #60] @ 0x3c +10008d9e: 6d79 ldr r1, [r7, #84] @ 0x54 +10008da0: 931d str r3, [sp, #116] @ 0x74 +10008da2: 6fbb ldr r3, [r7, #120] @ 0x78 +10008da4: 911a str r1, [sp, #104] @ 0x68 +10008da6: 9322 str r3, [sp, #136] @ 0x88 +10008da8: fbab 3c06 umull r3, ip, fp, r6 +10008dac: 18db adds r3, r3, r3 +10008dae: eb4c 0c0c adc.w ip, ip, ip +10008db2: eb1b 0b06 adds.w fp, fp, r6 +10008db6: eb49 090e adc.w r9, r9, lr +10008dba: eb13 030b adds.w r3, r3, fp +10008dbe: 69b9 ldr r1, [r7, #24] +10008dc0: eb4c 0c09 adc.w ip, ip, r9 +10008dc4: ea85 0903 eor.w r9, r5, r3 +10008dc8: ea84 040c eor.w r4, r4, ip +10008dcc: ea4f 6519 mov.w r5, r9, lsr #24 +10008dd0: eb05 2504 add.w r5, r5, r4, lsl #8 +10008dd4: 911b str r1, [sp, #108] @ 0x6c +10008dd6: 0e24 lsrs r4, r4, #24 +10008dd8: 69f9 ldr r1, [r7, #28] +10008dda: eb04 2409 add.w r4, r4, r9, lsl #8 +10008dde: fba2 9b05 umull r9, fp, r2, r5 +10008de2: 911c str r1, [sp, #112] @ 0x70 +10008de4: 6ff9 ldr r1, [r7, #124] @ 0x7c +10008de6: eb19 0909 adds.w r9, r9, r9 +10008dea: 9123 str r1, [sp, #140] @ 0x8c +10008dec: 6db9 ldr r1, [r7, #88] @ 0x58 +10008dee: eb4b 0b0b adc.w fp, fp, fp +10008df2: 911e str r1, [sp, #120] @ 0x78 +10008df4: 18aa adds r2, r5, r2 +10008df6: 6df9 ldr r1, [r7, #92] @ 0x5c +10008df8: eb44 0808 adc.w r8, r4, r8 +10008dfc: eb19 0202 adds.w r2, r9, r2 +10008e00: 911f str r1, [sp, #124] @ 0x7c +10008e02: ea86 0602 eor.w r6, r6, r2 +10008e06: eb4b 0108 adc.w r1, fp, r8 +10008e0a: 9218 str r2, [sp, #96] @ 0x60 +10008e0c: ea81 0e0e eor.w lr, r1, lr +10008e10: 0c32 lsrs r2, r6, #16 +10008e12: 9119 str r1, [sp, #100] @ 0x64 +10008e14: eb02 410e add.w r1, r2, lr, lsl #16 +10008e18: ea4f 4e1e mov.w lr, lr, lsr #16 +10008e1c: eb0e 4606 add.w r6, lr, r6, lsl #16 +10008e20: 9617 str r6, [sp, #92] @ 0x5c +10008e22: fba3 2601 umull r2, r6, r3, r1 +10008e26: 1892 adds r2, r2, r2 +10008e28: 4176 adcs r6, r6 +10008e2a: 9116 str r1, [sp, #88] @ 0x58 +10008e2c: 18cb adds r3, r1, r3 +10008e2e: 9917 ldr r1, [sp, #92] @ 0x5c +10008e30: f107 0780 add.w r7, r7, #128 @ 0x80 +10008e34: eb41 0c0c adc.w ip, r1, ip +10008e38: 18d1 adds r1, r2, r3 +10008e3a: eb46 060c adc.w r6, r6, ip +10008e3e: 404d eors r5, r1 +10008e40: 006b lsls r3, r5, #1 +10008e42: 4074 eors r4, r6 +10008e44: 9615 str r6, [sp, #84] @ 0x54 +10008e46: eb03 76d4 add.w r6, r3, r4, lsr #31 +10008e4a: fba0 320a umull r3, r2, r0, sl +10008e4e: 0064 lsls r4, r4, #1 +10008e50: eb04 74d5 add.w r4, r4, r5, lsr #31 +10008e54: 18db adds r3, r3, r3 +10008e56: 9d06 ldr r5, [sp, #24] +10008e58: 9114 str r1, [sp, #80] @ 0x50 +10008e5a: 9603 str r6, [sp, #12] +10008e5c: 9413 str r4, [sp, #76] @ 0x4c +10008e5e: 9c04 ldr r4, [sp, #16] +10008e60: 4152 adcs r2, r2 +10008e62: eb10 000a adds.w r0, r0, sl +10008e66: eb45 0404 adc.w r4, r5, r4 +10008e6a: 1818 adds r0, r3, r0 +10008e6c: 9d0d ldr r5, [sp, #52] @ 0x34 +10008e6e: 9907 ldr r1, [sp, #28] +10008e70: eb42 0404 adc.w r4, r2, r4 +10008e74: ea84 0205 eor.w r2, r4, r5 +10008e78: fba1 3602 umull r3, r6, r1, r2 +10008e7c: 9d0c ldr r5, [sp, #48] @ 0x30 +10008e7e: 18db adds r3, r3, r3 +10008e80: eb46 0e06 adc.w lr, r6, r6 +10008e84: 9e08 ldr r6, [sp, #32] +10008e86: 4045 eors r5, r0 +10008e88: 1889 adds r1, r1, r2 +10008e8a: eb46 0c05 adc.w ip, r6, r5 +10008e8e: 1859 adds r1, r3, r1 +10008e90: 9b04 ldr r3, [sp, #16] +10008e92: ea8a 0601 eor.w r6, sl, r1 +10008e96: eb4e 0c0c adc.w ip, lr, ip +10008e9a: ea83 0a0c eor.w sl, r3, ip +10008e9e: 0e33 lsrs r3, r6, #24 +10008ea0: eb03 230a add.w r3, r3, sl, lsl #8 +10008ea4: ea4f 6a1a mov.w sl, sl, lsr #24 +10008ea8: eb0a 2a06 add.w sl, sl, r6, lsl #8 +10008eac: fba0 6e03 umull r6, lr, r0, r3 +10008eb0: 19b6 adds r6, r6, r6 +10008eb2: eb4e 0e0e adc.w lr, lr, lr +10008eb6: 1818 adds r0, r3, r0 +10008eb8: eb4a 0404 adc.w r4, sl, r4 +10008ebc: 1830 adds r0, r6, r0 +10008ebe: eb4e 0404 adc.w r4, lr, r4 +10008ec2: 4042 eors r2, r0 +10008ec4: 9011 str r0, [sp, #68] @ 0x44 +10008ec6: 4065 eors r5, r4 +10008ec8: 0c10 lsrs r0, r2, #16 +10008eca: 9412 str r4, [sp, #72] @ 0x48 +10008ecc: eb00 4405 add.w r4, r0, r5, lsl #16 +10008ed0: 0c2d lsrs r5, r5, #16 +10008ed2: eb05 4502 add.w r5, r5, r2, lsl #16 +10008ed6: fba1 2004 umull r2, r0, r1, r4 +10008eda: 1892 adds r2, r2, r2 +10008edc: 4140 adcs r0, r0 +10008ede: 1861 adds r1, r4, r1 +10008ee0: eb45 0c0c adc.w ip, r5, ip +10008ee4: 9510 str r5, [sp, #64] @ 0x40 +10008ee6: 1855 adds r5, r2, r1 +10008ee8: eb40 060c adc.w r6, r0, ip +10008eec: 406b eors r3, r5 +10008eee: ea86 0a0a eor.w sl, r6, sl +10008ef2: 960e str r6, [sp, #56] @ 0x38 +10008ef4: 005e lsls r6, r3, #1 +10008ef6: eb06 76da add.w r6, r6, sl, lsr #31 +10008efa: ea4f 0a4a mov.w sl, sl, lsl #1 +10008efe: eb0a 72d3 add.w r2, sl, r3, lsr #31 +10008f02: 950d str r5, [sp, #52] @ 0x34 +10008f04: 9b01 ldr r3, [sp, #4] +10008f06: 9d09 ldr r5, [sp, #36] @ 0x24 +10008f08: 940f str r4, [sp, #60] @ 0x3c +10008f0a: 920c str r2, [sp, #48] @ 0x30 +10008f0c: fba5 2403 umull r2, r4, r5, r3 +10008f10: 1892 adds r2, r2, r2 +10008f12: 4164 adcs r4, r4 +10008f14: 18e9 adds r1, r5, r3 +10008f16: 9b0a ldr r3, [sp, #40] @ 0x28 +10008f18: 9d05 ldr r5, [sp, #20] +10008f1a: 980b ldr r0, [sp, #44] @ 0x2c +10008f1c: eb43 0305 adc.w r3, r3, r5 +10008f20: 1852 adds r2, r2, r1 +10008f22: 9d21 ldr r5, [sp, #132] @ 0x84 +10008f24: eb44 0403 adc.w r4, r4, r3 +10008f28: 9b20 ldr r3, [sp, #128] @ 0x80 +10008f2a: 4065 eors r5, r4 +10008f2c: ea82 0c03 eor.w ip, r2, r3 +10008f30: fba0 3105 umull r3, r1, r0, r5 +10008f34: 18db adds r3, r3, r3 +10008f36: 4149 adcs r1, r1 +10008f38: eb10 0e05 adds.w lr, r0, r5 +10008f3c: 981a ldr r0, [sp, #104] @ 0x68 +10008f3e: eb40 000c adc.w r0, r0, ip +10008f42: eb13 030e adds.w r3, r3, lr +10008f46: eb41 0e00 adc.w lr, r1, r0 +10008f4a: 9901 ldr r1, [sp, #4] +10008f4c: ea81 0803 eor.w r8, r1, r3 +10008f50: 9905 ldr r1, [sp, #20] +10008f52: ea4f 6018 mov.w r0, r8, lsr #24 +10008f56: ea81 010e eor.w r1, r1, lr +10008f5a: eb00 2001 add.w r0, r0, r1, lsl #8 +10008f5e: 0e09 lsrs r1, r1, #24 +10008f60: eb01 2108 add.w r1, r1, r8, lsl #8 +10008f64: fba2 8900 umull r8, r9, r2, r0 +10008f68: eb18 0808 adds.w r8, r8, r8 +10008f6c: eb49 0909 adc.w r9, r9, r9 +10008f70: 1882 adds r2, r0, r2 +10008f72: eb41 0404 adc.w r4, r1, r4 +10008f76: eb18 0202 adds.w r2, r8, r2 +10008f7a: eb49 0404 adc.w r4, r9, r4 +10008f7e: e9cd 240a strd r2, r4, [sp, #40] @ 0x28 +10008f82: 9c0b ldr r4, [sp, #44] @ 0x2c +10008f84: 4055 eors r5, r2 +10008f86: 0c2a lsrs r2, r5, #16 +10008f88: ea84 0c0c eor.w ip, r4, ip +10008f8c: eb02 440c add.w r4, r2, ip, lsl #16 +10008f90: ea4f 4c1c mov.w ip, ip, lsr #16 +10008f94: eb0c 4505 add.w r5, ip, r5, lsl #16 +10008f98: 9509 str r5, [sp, #36] @ 0x24 +10008f9a: 4625 mov r5, r4 +10008f9c: fba3 2404 umull r2, r4, r3, r4 +10008fa0: 1892 adds r2, r2, r2 +10008fa2: 4164 adcs r4, r4 +10008fa4: 9508 str r5, [sp, #32] +10008fa6: 18eb adds r3, r5, r3 +10008fa8: 9d09 ldr r5, [sp, #36] @ 0x24 +10008faa: eb45 0e0e adc.w lr, r5, lr +10008fae: 18d2 adds r2, r2, r3 +10008fb0: eb44 030e adc.w r3, r4, lr +10008fb4: 4050 eors r0, r2 +10008fb6: 4059 eors r1, r3 +10008fb8: 9307 str r3, [sp, #28] +10008fba: 0043 lsls r3, r0, #1 +10008fbc: eb03 74d1 add.w r4, r3, r1, lsr #31 +10008fc0: 0049 lsls r1, r1, #1 +10008fc2: eb01 73d0 add.w r3, r1, r0, lsr #31 +10008fc6: 9401 str r4, [sp, #4] +10008fc8: 9306 str r3, [sp, #24] +10008fca: 991b ldr r1, [sp, #108] @ 0x6c +10008fcc: 9b02 ldr r3, [sp, #8] +10008fce: 9d1e ldr r5, [sp, #120] @ 0x78 +10008fd0: fba1 0803 umull r0, r8, r1, r3 +10008fd4: 1800 adds r0, r0, r0 +10008fd6: eb48 0808 adc.w r8, r8, r8 +10008fda: 18c9 adds r1, r1, r3 +10008fdc: e9dd 341c ldrd r3, r4, [sp, #112] @ 0x70 +10008fe0: eb43 0304 adc.w r3, r3, r4 +10008fe4: 1840 adds r0, r0, r1 +10008fe6: eb48 0803 adc.w r8, r8, r3 +10008fea: 9b23 ldr r3, [sp, #140] @ 0x8c +10008fec: ea88 0a03 eor.w sl, r8, r3 +10008ff0: fba5 1e0a umull r1, lr, r5, sl +10008ff4: 9b22 ldr r3, [sp, #136] @ 0x88 +10008ff6: 1849 adds r1, r1, r1 +10008ff8: eb4e 0e0e adc.w lr, lr, lr +10008ffc: eb15 0c0a adds.w ip, r5, sl +10009000: 9d1f ldr r5, [sp, #124] @ 0x7c +10009002: ea80 0303 eor.w r3, r0, r3 +10009006: eb45 0503 adc.w r5, r5, r3 +1000900a: eb11 010c adds.w r1, r1, ip +1000900e: eb4e 0e05 adc.w lr, lr, r5 +10009012: 9d02 ldr r5, [sp, #8] +10009014: ea85 0901 eor.w r9, r5, r1 +10009018: ea4f 6c19 mov.w ip, r9, lsr #24 +1000901c: ea84 050e eor.w r5, r4, lr +10009020: eb0c 2c05 add.w ip, ip, r5, lsl #8 +10009024: 0e2d lsrs r5, r5, #24 +10009026: eb05 2509 add.w r5, r5, r9, lsl #8 +1000902a: fbac 9b00 umull r9, fp, ip, r0 +1000902e: eb19 0909 adds.w r9, r9, r9 +10009032: eb4b 0b0b adc.w fp, fp, fp +10009036: eb1c 0000 adds.w r0, ip, r0 +1000903a: eb45 0808 adc.w r8, r5, r8 +1000903e: eb19 0400 adds.w r4, r9, r0 +10009042: eb4b 0008 adc.w r0, fp, r8 +10009046: ea84 0a0a eor.w sl, r4, sl +1000904a: 4043 eors r3, r0 +1000904c: 9004 str r0, [sp, #16] +1000904e: ea4f 401a mov.w r0, sl, lsr #16 +10009052: eb00 4003 add.w r0, r0, r3, lsl #16 +10009056: fba0 8901 umull r8, r9, r0, r1 +1000905a: 0c1b lsrs r3, r3, #16 +1000905c: eb18 0808 adds.w r8, r8, r8 +10009060: eb03 4a0a add.w sl, r3, sl, lsl #16 +10009064: eb49 0909 adc.w r9, r9, r9 +10009068: 1841 adds r1, r0, r1 +1000906a: eb4a 0e0e adc.w lr, sl, lr +1000906e: eb18 0101 adds.w r1, r8, r1 +10009072: eb49 0e0e adc.w lr, r9, lr +10009076: ea8c 0c01 eor.w ip, ip, r1 +1000907a: ea85 050e eor.w r5, r5, lr +1000907e: ea4f 084c mov.w r8, ip, lsl #1 +10009082: eb08 7bd5 add.w fp, r8, r5, lsr #31 +10009086: 006d lsls r5, r5, #1 +10009088: eb05 73dc add.w r3, r5, ip, lsr #31 +1000908c: 9305 str r3, [sp, #20] +1000908e: 9b18 ldr r3, [sp, #96] @ 0x60 +10009090: 9402 str r4, [sp, #8] +10009092: fba6 5c03 umull r5, ip, r6, r3 +10009096: 196d adds r5, r5, r5 +10009098: 9c19 ldr r4, [sp, #100] @ 0x64 +1000909a: eb4c 0c0c adc.w ip, ip, ip +1000909e: eb16 0903 adds.w r9, r6, r3 +100090a2: 9b0c ldr r3, [sp, #48] @ 0x30 +100090a4: eb43 0804 adc.w r8, r3, r4 +100090a8: eb15 0509 adds.w r5, r5, r9 +100090ac: eb4c 0c08 adc.w ip, ip, r8 +100090b0: ea8a 030c eor.w r3, sl, ip +100090b4: fba3 8902 umull r8, r9, r3, r2 +100090b8: 9c07 ldr r4, [sp, #28] +100090ba: eb18 0808 adds.w r8, r8, r8 +100090be: ea80 0005 eor.w r0, r0, r5 +100090c2: eb49 0909 adc.w r9, r9, r9 +100090c6: 189a adds r2, r3, r2 +100090c8: eb44 0400 adc.w r4, r4, r0 +100090cc: eb18 0202 adds.w r2, r8, r2 +100090d0: ea82 0806 eor.w r8, r2, r6 +100090d4: 9e0c ldr r6, [sp, #48] @ 0x30 +100090d6: eb49 0404 adc.w r4, r9, r4 +100090da: 4066 eors r6, r4 +100090dc: ea4f 6918 mov.w r9, r8, lsr #24 +100090e0: eb09 2906 add.w r9, r9, r6, lsl #8 +100090e4: 0e36 lsrs r6, r6, #24 +100090e6: eb06 2608 add.w r6, r6, r8, lsl #8 +100090ea: fba9 8a05 umull r8, sl, r9, r5 +100090ee: eb18 0808 adds.w r8, r8, r8 +100090f2: eb4a 0a0a adc.w sl, sl, sl +100090f6: eb15 0509 adds.w r5, r5, r9 +100090fa: eb4c 0c06 adc.w ip, ip, r6 +100090fe: eb18 0505 adds.w r5, r8, r5 +10009102: eb4a 0c0c adc.w ip, sl, ip +10009106: 406b eors r3, r5 +10009108: ea80 000c eor.w r0, r0, ip +1000910c: f847 5c80 str.w r5, [r7, #-128] +10009110: 0c1d lsrs r5, r3, #16 +10009112: eb05 4500 add.w r5, r5, r0, lsl #16 +10009116: 0c00 lsrs r0, r0, #16 +10009118: eb00 4003 add.w r0, r0, r3, lsl #16 +1000911c: f847 cc7c str.w ip, [r7, #-124] +10009120: fba5 3c02 umull r3, ip, r5, r2 +10009124: 18db adds r3, r3, r3 +10009126: eb4c 0c0c adc.w ip, ip, ip +1000912a: 1952 adds r2, r2, r5 +1000912c: eb44 0400 adc.w r4, r4, r0 +10009130: 189b adds r3, r3, r2 +10009132: eb4c 0404 adc.w r4, ip, r4 +10009136: ea89 0903 eor.w r9, r9, r3 +1000913a: 4066 eors r6, r4 +1000913c: f847 3c30 str.w r3, [r7, #-48] +10009140: ea4f 0349 mov.w r3, r9, lsl #1 +10009144: eb03 73d6 add.w r3, r3, r6, lsr #31 +10009148: 0076 lsls r6, r6, #1 +1000914a: eb06 76d9 add.w r6, r6, r9, lsr #31 +1000914e: e947 5002 strd r5, r0, [r7, #-8] +10009152: f847 6c54 str.w r6, [r7, #-84] +10009156: 9811 ldr r0, [sp, #68] @ 0x44 +10009158: 9e01 ldr r6, [sp, #4] +1000915a: f847 4c2c str.w r4, [r7, #-44] +1000915e: f847 3c58 str.w r3, [r7, #-88] +10009162: fba6 3400 umull r3, r4, r6, r0 +10009166: 9d06 ldr r5, [sp, #24] +10009168: 18db adds r3, r3, r3 +1000916a: 9a12 ldr r2, [sp, #72] @ 0x48 +1000916c: 4164 adcs r4, r4 +1000916e: 1830 adds r0, r6, r0 +10009170: eb45 0202 adc.w r2, r5, r2 +10009174: 181b adds r3, r3, r0 +10009176: 9817 ldr r0, [sp, #92] @ 0x5c +10009178: eb44 0402 adc.w r4, r4, r2 +1000917c: ea84 0500 eor.w r5, r4, r0 +10009180: fba5 0601 umull r0, r6, r5, r1 +10009184: 9a16 ldr r2, [sp, #88] @ 0x58 +10009186: 1800 adds r0, r0, r0 +10009188: ea83 0202 eor.w r2, r3, r2 +1000918c: 4176 adcs r6, r6 +1000918e: 1949 adds r1, r1, r5 +10009190: eb4e 0e02 adc.w lr, lr, r2 +10009194: 1841 adds r1, r0, r1 +10009196: eb46 0e0e adc.w lr, r6, lr +1000919a: 9e01 ldr r6, [sp, #4] +1000919c: 9806 ldr r0, [sp, #24] +1000919e: 404e eors r6, r1 +100091a0: ea8e 0000 eor.w r0, lr, r0 +100091a4: ea4f 6c16 mov.w ip, r6, lsr #24 +100091a8: eb0c 2c00 add.w ip, ip, r0, lsl #8 +100091ac: 0e00 lsrs r0, r0, #24 +100091ae: eb00 2006 add.w r0, r0, r6, lsl #8 +100091b2: fbac 6803 umull r6, r8, ip, r3 +100091b6: 19b6 adds r6, r6, r6 +100091b8: eb48 0808 adc.w r8, r8, r8 +100091bc: eb13 030c adds.w r3, r3, ip +100091c0: eb44 0400 adc.w r4, r4, r0 +100091c4: 18f6 adds r6, r6, r3 +100091c6: eb48 0404 adc.w r4, r8, r4 +100091ca: 4075 eors r5, r6 +100091cc: 4062 eors r2, r4 +100091ce: 0c2b lsrs r3, r5, #16 +100091d0: eb03 4302 add.w r3, r3, r2, lsl #16 +100091d4: 0c12 lsrs r2, r2, #16 +100091d6: eb02 4205 add.w r2, r2, r5, lsl #16 +100091da: f847 4c74 str.w r4, [r7, #-116] +100091de: fba3 4501 umull r4, r5, r3, r1 +100091e2: 1924 adds r4, r4, r4 +100091e4: e947 3208 strd r3, r2, [r7, #-32] +100091e8: 416d adcs r5, r5 +100091ea: 185b adds r3, r3, r1 +100091ec: eb42 020e adc.w r2, r2, lr +100091f0: 18e4 adds r4, r4, r3 +100091f2: eb45 0202 adc.w r2, r5, r2 +100091f6: ea84 0c0c eor.w ip, r4, ip +100091fa: 4050 eors r0, r2 +100091fc: ea4f 034c mov.w r3, ip, lsl #1 +10009200: eb03 73d0 add.w r3, r3, r0, lsr #31 +10009204: f847 3c50 str.w r3, [r7, #-80] +10009208: 9b0a ldr r3, [sp, #40] @ 0x28 +1000920a: f847 4c28 str.w r4, [r7, #-40] +1000920e: f847 2c24 str.w r2, [r7, #-36] +10009212: fbab 2403 umull r2, r4, fp, r3 +10009216: 0040 lsls r0, r0, #1 +10009218: eb00 70dc add.w r0, r0, ip, lsr #31 +1000921c: 1892 adds r2, r2, r2 +1000921e: f847 6c78 str.w r6, [r7, #-120] +10009222: f847 0c4c str.w r0, [r7, #-76] +10009226: 9e05 ldr r6, [sp, #20] +10009228: 980b ldr r0, [sp, #44] @ 0x2c +1000922a: 4164 adcs r4, r4 +1000922c: eb1b 0303 adds.w r3, fp, r3 +10009230: eb46 0100 adc.w r1, r6, r0 +10009234: 18d2 adds r2, r2, r3 +10009236: 9b10 ldr r3, [sp, #64] @ 0x40 +10009238: eb44 0401 adc.w r4, r4, r1 +1000923c: 980f ldr r0, [sp, #60] @ 0x3c +1000923e: 9914 ldr r1, [sp, #80] @ 0x50 +10009240: ea84 0603 eor.w r6, r4, r3 +10009244: ea82 0c00 eor.w ip, r2, r0 +10009248: fba6 3001 umull r3, r0, r6, r1 +1000924c: 18db adds r3, r3, r3 +1000924e: 4140 adcs r0, r0 +10009250: 1875 adds r5, r6, r1 +10009252: 9915 ldr r1, [sp, #84] @ 0x54 +10009254: eb41 010c adc.w r1, r1, ip +10009258: 195b adds r3, r3, r5 +1000925a: eb40 0001 adc.w r0, r0, r1 +1000925e: 9905 ldr r1, [sp, #20] +10009260: ea83 050b eor.w r5, r3, fp +10009264: 4041 eors r1, r0 +10009266: ea4f 6e15 mov.w lr, r5, lsr #24 +1000926a: eb0e 2e01 add.w lr, lr, r1, lsl #8 +1000926e: 0e09 lsrs r1, r1, #24 +10009270: eb01 2105 add.w r1, r1, r5, lsl #8 +10009274: fbae 5802 umull r5, r8, lr, r2 +10009278: 196d adds r5, r5, r5 +1000927a: eb48 0808 adc.w r8, r8, r8 +1000927e: eb12 020e adds.w r2, r2, lr +10009282: eb44 0401 adc.w r4, r4, r1 +10009286: 18ad adds r5, r5, r2 +10009288: eb48 0404 adc.w r4, r8, r4 +1000928c: 406e eors r6, r5 +1000928e: ea8c 0c04 eor.w ip, ip, r4 +10009292: f847 4c6c str.w r4, [r7, #-108] +10009296: 0c34 lsrs r4, r6, #16 +10009298: eb04 440c add.w r4, r4, ip, lsl #16 +1000929c: ea4f 4c1c mov.w ip, ip, lsr #16 +100092a0: f847 5c70 str.w r5, [r7, #-112] +100092a4: eb0c 4506 add.w r5, ip, r6, lsl #16 +100092a8: fba4 2603 umull r2, r6, r4, r3 +100092ac: 1892 adds r2, r2, r2 +100092ae: 4176 adcs r6, r6 +100092b0: 191b adds r3, r3, r4 +100092b2: eb40 0005 adc.w r0, r0, r5 +100092b6: 18d2 adds r2, r2, r3 +100092b8: eb46 0000 adc.w r0, r6, r0 +100092bc: ea8e 0e02 eor.w lr, lr, r2 +100092c0: 4041 eors r1, r0 +100092c2: ea4f 034e mov.w r3, lr, lsl #1 +100092c6: eb03 73d1 add.w r3, r3, r1, lsr #31 +100092ca: 0049 lsls r1, r1, #1 +100092cc: eb01 71de add.w r1, r1, lr, lsr #31 +100092d0: f847 2c40 str.w r2, [r7, #-64] +100092d4: f847 3c48 str.w r3, [r7, #-72] +100092d8: f847 1c44 str.w r1, [r7, #-68] +100092dc: e9dd 1302 ldrd r1, r3, [sp, #8] +100092e0: fba3 2601 umull r2, r6, r3, r1 +100092e4: e947 4506 strd r4, r5, [r7, #-24] +100092e8: 1892 adds r2, r2, r2 +100092ea: 9c13 ldr r4, [sp, #76] @ 0x4c +100092ec: f847 0c3c str.w r0, [r7, #-60] +100092f0: 9804 ldr r0, [sp, #16] +100092f2: 4176 adcs r6, r6 +100092f4: 18cb adds r3, r1, r3 +100092f6: eb40 0104 adc.w r1, r0, r4 +100092fa: 18d2 adds r2, r2, r3 +100092fc: 9b09 ldr r3, [sp, #36] @ 0x24 +100092fe: eb46 0601 adc.w r6, r6, r1 +10009302: 980d ldr r0, [sp, #52] @ 0x34 +10009304: ea86 0c03 eor.w ip, r6, r3 +10009308: fbac 3500 umull r3, r5, ip, r0 +1000930c: 9c08 ldr r4, [sp, #32] +1000930e: 18db adds r3, r3, r3 +10009310: 416d adcs r5, r5 +10009312: eb1c 0100 adds.w r1, ip, r0 +10009316: 980e ldr r0, [sp, #56] @ 0x38 +10009318: ea82 0404 eor.w r4, r2, r4 +1000931c: eb40 0004 adc.w r0, r0, r4 +10009320: 185b adds r3, r3, r1 +10009322: 9903 ldr r1, [sp, #12] +10009324: eb45 0500 adc.w r5, r5, r0 +10009328: ea83 0e01 eor.w lr, r3, r1 +1000932c: 9913 ldr r1, [sp, #76] @ 0x4c +1000932e: ea4f 601e mov.w r0, lr, lsr #24 +10009332: 4069 eors r1, r5 +10009334: eb00 2001 add.w r0, r0, r1, lsl #8 +10009338: 0e09 lsrs r1, r1, #24 +1000933a: eb01 210e add.w r1, r1, lr, lsl #8 +1000933e: fba0 e802 umull lr, r8, r0, r2 +10009342: eb1e 0e0e adds.w lr, lr, lr +10009346: eb48 0808 adc.w r8, r8, r8 +1000934a: 1812 adds r2, r2, r0 +1000934c: eb46 0601 adc.w r6, r6, r1 +10009350: eb1e 0202 adds.w r2, lr, r2 +10009354: eb48 0606 adc.w r6, r8, r6 +10009358: ea8c 0c02 eor.w ip, ip, r2 +1000935c: 4074 eors r4, r6 +1000935e: ea4f 4e1c mov.w lr, ip, lsr #16 +10009362: eb0e 4e04 add.w lr, lr, r4, lsl #16 +10009366: f847 2c68 str.w r2, [r7, #-104] +1000936a: f847 6c64 str.w r6, [r7, #-100] +1000936e: fbae 2603 umull r2, r6, lr, r3 +10009372: 0c24 lsrs r4, r4, #16 +10009374: 1892 adds r2, r2, r2 +10009376: eb04 440c add.w r4, r4, ip, lsl #16 +1000937a: 4176 adcs r6, r6 +1000937c: eb13 030e adds.w r3, r3, lr +10009380: eb45 0504 adc.w r5, r5, r4 +10009384: 18d2 adds r2, r2, r3 +10009386: eb46 0505 adc.w r5, r6, r5 +1000938a: 4050 eors r0, r2 +1000938c: 4069 eors r1, r5 +1000938e: 004b lsls r3, r1, #1 +10009390: e947 e404 strd lr, r4, [r7, #-16] +10009394: 0044 lsls r4, r0, #1 +10009396: eb03 73d0 add.w r3, r3, r0, lsr #31 +1000939a: eb04 71d1 add.w r1, r4, r1, lsr #31 +1000939e: e947 1318 strd r1, r3, [r7, #-96] @ 0x60 +100093a2: f50d 6393 add.w r3, sp, #1176 @ 0x498 +100093a6: 42bb cmp r3, r7 +100093a8: e947 250e strd r2, r5, [r7, #-56] @ 0x38 +100093ac: f47f acbe bne.w 10008d2c +100093b0: 9c24 ldr r4, [sp, #144] @ 0x90 +100093b2: ab46 add r3, sp, #280 @ 0x118 +100093b4: 9324 str r3, [sp, #144] @ 0x90 +100093b6: 9b25 ldr r3, [sp, #148] @ 0x94 +100093b8: 9425 str r4, [sp, #148] @ 0x94 +100093ba: f8d3 6100 ldr.w r6, [r3, #256] @ 0x100 +100093be: 6818 ldr r0, [r3, #0] +100093c0: f8d3 5104 ldr.w r5, [r3, #260] @ 0x104 +100093c4: fba0 1806 umull r1, r8, r0, r6 +100093c8: 685a ldr r2, [r3, #4] +100093ca: 1849 adds r1, r1, r1 +100093cc: eb48 0808 adc.w r8, r8, r8 +100093d0: 1980 adds r0, r0, r6 +100093d2: eb42 0205 adc.w r2, r2, r5 +100093d6: 1809 adds r1, r1, r0 +100093d8: 68d8 ldr r0, [r3, #12] +100093da: eb48 0802 adc.w r8, r8, r2 +100093de: 9006 str r0, [sp, #24] +100093e0: f8d3 030c ldr.w r0, [r3, #780] @ 0x30c +100093e4: f8d3 2300 ldr.w r2, [r3, #768] @ 0x300 +100093e8: 900d str r0, [sp, #52] @ 0x34 +100093ea: f8d3 0208 ldr.w r0, [r3, #520] @ 0x208 +100093ee: ea81 0e02 eor.w lr, r1, r2 +100093f2: 9007 str r0, [sp, #28] +100093f4: f8d3 210c ldr.w r2, [r3, #268] @ 0x10c +100093f8: f8d3 020c ldr.w r0, [r3, #524] @ 0x20c +100093fc: 9204 str r2, [sp, #16] +100093fe: 9008 str r0, [sp, #32] +10009400: f8d3 2308 ldr.w r2, [r3, #776] @ 0x308 +10009404: f8d3 0080 ldr.w r0, [r3, #128] @ 0x80 +10009408: 920c str r2, [sp, #48] @ 0x30 +1000940a: 9009 str r0, [sp, #36] @ 0x24 +1000940c: f8d3 2180 ldr.w r2, [r3, #384] @ 0x180 +10009410: f8d3 0184 ldr.w r0, [r3, #388] @ 0x184 +10009414: 9201 str r2, [sp, #4] +10009416: 9005 str r0, [sp, #20] +10009418: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 +1000941c: f8d3 0384 ldr.w r0, [r3, #900] @ 0x384 +10009420: f8d3 a108 ldr.w sl, [r3, #264] @ 0x108 +10009424: f8d3 b200 ldr.w fp, [r3, #512] @ 0x200 +10009428: 689c ldr r4, [r3, #8] +1000942a: f8d3 7304 ldr.w r7, [r3, #772] @ 0x304 +1000942e: f8d3 9204 ldr.w r9, [r3, #516] @ 0x204 +10009432: 920a str r2, [sp, #40] @ 0x28 +10009434: 9021 str r0, [sp, #132] @ 0x84 +10009436: f8d3 0280 ldr.w r0, [r3, #640] @ 0x280 +1000943a: f8d3 2380 ldr.w r2, [r3, #896] @ 0x380 +1000943e: ea88 0707 eor.w r7, r8, r7 +10009442: 9220 str r2, [sp, #128] @ 0x80 +10009444: f8d3 2284 ldr.w r2, [r3, #644] @ 0x284 +10009448: 900b str r0, [sp, #44] @ 0x2c +1000944a: 921a str r2, [sp, #104] @ 0x68 +1000944c: f8d3 2188 ldr.w r2, [r3, #392] @ 0x188 +10009450: f8d3 0088 ldr.w r0, [r3, #136] @ 0x88 +10009454: 9202 str r2, [sp, #8] +10009456: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c +1000945a: 901b str r0, [sp, #108] @ 0x6c +1000945c: 921c str r2, [sp, #112] @ 0x70 +1000945e: f8d3 2288 ldr.w r2, [r3, #648] @ 0x288 +10009462: f8d3 018c ldr.w r0, [r3, #396] @ 0x18c +10009466: 921e str r2, [sp, #120] @ 0x78 +10009468: fbab 2c07 umull r2, ip, fp, r7 +1000946c: 1892 adds r2, r2, r2 +1000946e: eb4c 0c0c adc.w ip, ip, ip +10009472: eb1b 0b07 adds.w fp, fp, r7 +10009476: eb49 090e adc.w r9, r9, lr +1000947a: eb12 020b adds.w r2, r2, fp +1000947e: eb4c 0c09 adc.w ip, ip, r9 +10009482: ea86 0902 eor.w r9, r6, r2 +10009486: ea85 050c eor.w r5, r5, ip +1000948a: ea4f 6619 mov.w r6, r9, lsr #24 +1000948e: eb06 2605 add.w r6, r6, r5, lsl #8 +10009492: 0e2d lsrs r5, r5, #24 +10009494: eb05 2509 add.w r5, r5, r9, lsl #8 +10009498: fba1 9b06 umull r9, fp, r1, r6 +1000949c: 901d str r0, [sp, #116] @ 0x74 +1000949e: f8d3 038c ldr.w r0, [r3, #908] @ 0x38c +100094a2: eb19 0909 adds.w r9, r9, r9 +100094a6: 9023 str r0, [sp, #140] @ 0x8c +100094a8: f8d3 0388 ldr.w r0, [r3, #904] @ 0x388 +100094ac: eb4b 0b0b adc.w fp, fp, fp +100094b0: 9022 str r0, [sp, #136] @ 0x88 +100094b2: 1871 adds r1, r6, r1 +100094b4: f8d3 028c ldr.w r0, [r3, #652] @ 0x28c +100094b8: eb45 0808 adc.w r8, r5, r8 +100094bc: eb19 0101 adds.w r1, r9, r1 +100094c0: 901f str r0, [sp, #124] @ 0x7c +100094c2: ea87 0701 eor.w r7, r7, r1 +100094c6: eb4b 0008 adc.w r0, fp, r8 +100094ca: 9118 str r1, [sp, #96] @ 0x60 +100094cc: ea80 0e0e eor.w lr, r0, lr +100094d0: 0c39 lsrs r1, r7, #16 +100094d2: 9019 str r0, [sp, #100] @ 0x64 +100094d4: eb01 400e add.w r0, r1, lr, lsl #16 +100094d8: ea4f 4e1e mov.w lr, lr, lsr #16 +100094dc: eb0e 4707 add.w r7, lr, r7, lsl #16 +100094e0: 9717 str r7, [sp, #92] @ 0x5c +100094e2: fba2 1700 umull r1, r7, r2, r0 +100094e6: 1849 adds r1, r1, r1 +100094e8: 417f adcs r7, r7 +100094ea: 9016 str r0, [sp, #88] @ 0x58 +100094ec: 1882 adds r2, r0, r2 +100094ee: 9817 ldr r0, [sp, #92] @ 0x5c +100094f0: f103 0310 add.w r3, r3, #16 +100094f4: eb40 0c0c adc.w ip, r0, ip +100094f8: 1888 adds r0, r1, r2 +100094fa: eb47 070c adc.w r7, r7, ip +100094fe: 4046 eors r6, r0 +10009500: 0072 lsls r2, r6, #1 +10009502: 407d eors r5, r7 +10009504: 9715 str r7, [sp, #84] @ 0x54 +10009506: eb02 77d5 add.w r7, r2, r5, lsr #31 +1000950a: fba4 210a umull r2, r1, r4, sl +1000950e: 006d lsls r5, r5, #1 +10009510: eb05 75d6 add.w r5, r5, r6, lsr #31 +10009514: 1892 adds r2, r2, r2 +10009516: 9e06 ldr r6, [sp, #24] +10009518: 9014 str r0, [sp, #80] @ 0x50 +1000951a: 9703 str r7, [sp, #12] +1000951c: 9513 str r5, [sp, #76] @ 0x4c +1000951e: 9d04 ldr r5, [sp, #16] +10009520: 4149 adcs r1, r1 +10009522: eb14 040a adds.w r4, r4, sl +10009526: eb46 0505 adc.w r5, r6, r5 +1000952a: 1914 adds r4, r2, r4 +1000952c: 9e0d ldr r6, [sp, #52] @ 0x34 +1000952e: 9807 ldr r0, [sp, #28] +10009530: eb41 0505 adc.w r5, r1, r5 +10009534: ea85 0106 eor.w r1, r5, r6 +10009538: fba0 2701 umull r2, r7, r0, r1 +1000953c: 9e0c ldr r6, [sp, #48] @ 0x30 +1000953e: 1892 adds r2, r2, r2 +10009540: eb47 0e07 adc.w lr, r7, r7 +10009544: 9f08 ldr r7, [sp, #32] +10009546: 4066 eors r6, r4 +10009548: 1840 adds r0, r0, r1 +1000954a: eb47 0c06 adc.w ip, r7, r6 +1000954e: 1810 adds r0, r2, r0 +10009550: 9a04 ldr r2, [sp, #16] +10009552: ea8a 0700 eor.w r7, sl, r0 +10009556: eb4e 0c0c adc.w ip, lr, ip +1000955a: ea82 0a0c eor.w sl, r2, ip +1000955e: 0e3a lsrs r2, r7, #24 +10009560: eb02 220a add.w r2, r2, sl, lsl #8 +10009564: ea4f 6a1a mov.w sl, sl, lsr #24 +10009568: eb0a 2a07 add.w sl, sl, r7, lsl #8 +1000956c: fba4 7e02 umull r7, lr, r4, r2 +10009570: 19ff adds r7, r7, r7 +10009572: eb4e 0e0e adc.w lr, lr, lr +10009576: 1914 adds r4, r2, r4 +10009578: eb4a 0505 adc.w r5, sl, r5 +1000957c: 193c adds r4, r7, r4 +1000957e: eb4e 0705 adc.w r7, lr, r5 +10009582: 4061 eors r1, r4 +10009584: 407e eors r6, r7 +10009586: 9411 str r4, [sp, #68] @ 0x44 +10009588: 0c0c lsrs r4, r1, #16 +1000958a: eb04 4506 add.w r5, r4, r6, lsl #16 +1000958e: 0c36 lsrs r6, r6, #16 +10009590: eb06 4601 add.w r6, r6, r1, lsl #16 +10009594: fba0 1405 umull r1, r4, r0, r5 +10009598: 1849 adds r1, r1, r1 +1000959a: 4164 adcs r4, r4 +1000959c: 1828 adds r0, r5, r0 +1000959e: eb46 0c0c adc.w ip, r6, ip +100095a2: 9712 str r7, [sp, #72] @ 0x48 +100095a4: 180f adds r7, r1, r0 +100095a6: 950f str r5, [sp, #60] @ 0x3c +100095a8: ea82 0207 eor.w r2, r2, r7 +100095ac: eb44 050c adc.w r5, r4, ip +100095b0: ea85 0a0a eor.w sl, r5, sl +100095b4: 970d str r7, [sp, #52] @ 0x34 +100095b6: 0057 lsls r7, r2, #1 +100095b8: eb07 77da add.w r7, r7, sl, lsr #31 +100095bc: ea4f 0a4a mov.w sl, sl, lsl #1 +100095c0: eb0a 72d2 add.w r2, sl, r2, lsr #31 +100095c4: 9c09 ldr r4, [sp, #36] @ 0x24 +100095c6: 920c str r2, [sp, #48] @ 0x30 +100095c8: 9a01 ldr r2, [sp, #4] +100095ca: 950e str r5, [sp, #56] @ 0x38 +100095cc: fba4 1502 umull r1, r5, r4, r2 +100095d0: 1849 adds r1, r1, r1 +100095d2: 9610 str r6, [sp, #64] @ 0x40 +100095d4: 416d adcs r5, r5 +100095d6: 9e0a ldr r6, [sp, #40] @ 0x28 +100095d8: 18a0 adds r0, r4, r2 +100095da: 9c05 ldr r4, [sp, #20] +100095dc: eb46 0204 adc.w r2, r6, r4 +100095e0: 1809 adds r1, r1, r0 +100095e2: 9c21 ldr r4, [sp, #132] @ 0x84 +100095e4: eb45 0502 adc.w r5, r5, r2 +100095e8: ea85 0604 eor.w r6, r5, r4 +100095ec: 9c20 ldr r4, [sp, #128] @ 0x80 +100095ee: ea81 0c04 eor.w ip, r1, r4 +100095f2: 9c0b ldr r4, [sp, #44] @ 0x2c +100095f4: fba4 2006 umull r2, r0, r4, r6 +100095f8: 1892 adds r2, r2, r2 +100095fa: 4140 adcs r0, r0 +100095fc: eb14 0e06 adds.w lr, r4, r6 +10009600: 9c1a ldr r4, [sp, #104] @ 0x68 +10009602: eb44 040c adc.w r4, r4, ip +10009606: eb12 020e adds.w r2, r2, lr +1000960a: eb40 0e04 adc.w lr, r0, r4 +1000960e: 9801 ldr r0, [sp, #4] +10009610: 9c05 ldr r4, [sp, #20] +10009612: ea80 0802 eor.w r8, r0, r2 +10009616: ea84 000e eor.w r0, r4, lr +1000961a: ea4f 6418 mov.w r4, r8, lsr #24 +1000961e: eb04 2400 add.w r4, r4, r0, lsl #8 +10009622: 0e00 lsrs r0, r0, #24 +10009624: eb00 2008 add.w r0, r0, r8, lsl #8 +10009628: fba1 8904 umull r8, r9, r1, r4 +1000962c: eb18 0808 adds.w r8, r8, r8 +10009630: eb49 0909 adc.w r9, r9, r9 +10009634: 1861 adds r1, r4, r1 +10009636: eb40 0505 adc.w r5, r0, r5 +1000963a: eb18 0101 adds.w r1, r8, r1 +1000963e: eb49 0505 adc.w r5, r9, r5 +10009642: e9cd 150a strd r1, r5, [sp, #40] @ 0x28 +10009646: 9d0b ldr r5, [sp, #44] @ 0x2c +10009648: 404e eors r6, r1 +1000964a: 0c31 lsrs r1, r6, #16 +1000964c: ea85 0c0c eor.w ip, r5, ip +10009650: eb01 450c add.w r5, r1, ip, lsl #16 +10009654: ea4f 4c1c mov.w ip, ip, lsr #16 +10009658: eb0c 4606 add.w r6, ip, r6, lsl #16 +1000965c: 9609 str r6, [sp, #36] @ 0x24 +1000965e: 462e mov r6, r5 +10009660: fba2 1505 umull r1, r5, r2, r5 +10009664: 1849 adds r1, r1, r1 +10009666: 416d adcs r5, r5 +10009668: 9608 str r6, [sp, #32] +1000966a: 18b2 adds r2, r6, r2 +1000966c: 9e09 ldr r6, [sp, #36] @ 0x24 +1000966e: eb46 0e0e adc.w lr, r6, lr +10009672: 1889 adds r1, r1, r2 +10009674: eb45 020e adc.w r2, r5, lr +10009678: 404c eors r4, r1 +1000967a: 4050 eors r0, r2 +1000967c: 9207 str r2, [sp, #28] +1000967e: 0062 lsls r2, r4, #1 +10009680: eb02 72d0 add.w r2, r2, r0, lsr #31 +10009684: 0040 lsls r0, r0, #1 +10009686: eb00 74d4 add.w r4, r0, r4, lsr #31 +1000968a: 9201 str r2, [sp, #4] +1000968c: 9406 str r4, [sp, #24] +1000968e: 981b ldr r0, [sp, #108] @ 0x6c +10009690: 9a02 ldr r2, [sp, #8] +10009692: 9e1e ldr r6, [sp, #120] @ 0x78 +10009694: fba0 4802 umull r4, r8, r0, r2 +10009698: 1924 adds r4, r4, r4 +1000969a: eb48 0808 adc.w r8, r8, r8 +1000969e: 1880 adds r0, r0, r2 +100096a0: e9dd 251c ldrd r2, r5, [sp, #112] @ 0x70 +100096a4: eb42 0205 adc.w r2, r2, r5 +100096a8: 1824 adds r4, r4, r0 +100096aa: eb48 0802 adc.w r8, r8, r2 +100096ae: 9a23 ldr r2, [sp, #140] @ 0x8c +100096b0: ea88 0a02 eor.w sl, r8, r2 +100096b4: fba6 0e0a umull r0, lr, r6, sl +100096b8: 9a22 ldr r2, [sp, #136] @ 0x88 +100096ba: 1800 adds r0, r0, r0 +100096bc: eb4e 0e0e adc.w lr, lr, lr +100096c0: eb16 0c0a adds.w ip, r6, sl +100096c4: 9e1f ldr r6, [sp, #124] @ 0x7c +100096c6: ea84 0202 eor.w r2, r4, r2 +100096ca: eb46 0602 adc.w r6, r6, r2 +100096ce: eb10 000c adds.w r0, r0, ip +100096d2: eb4e 0e06 adc.w lr, lr, r6 +100096d6: 9e02 ldr r6, [sp, #8] +100096d8: ea86 0900 eor.w r9, r6, r0 +100096dc: ea4f 6c19 mov.w ip, r9, lsr #24 +100096e0: ea85 060e eor.w r6, r5, lr +100096e4: eb0c 2c06 add.w ip, ip, r6, lsl #8 +100096e8: 0e36 lsrs r6, r6, #24 +100096ea: eb06 2609 add.w r6, r6, r9, lsl #8 +100096ee: fba4 9b0c umull r9, fp, r4, ip +100096f2: eb19 0909 adds.w r9, r9, r9 +100096f6: eb4b 0b0b adc.w fp, fp, fp +100096fa: eb1c 0404 adds.w r4, ip, r4 +100096fe: eb46 0808 adc.w r8, r6, r8 +10009702: eb19 0404 adds.w r4, r9, r4 +10009706: eb4b 0508 adc.w r5, fp, r8 +1000970a: ea84 0a0a eor.w sl, r4, sl +1000970e: 406a eors r2, r5 +10009710: 9404 str r4, [sp, #16] +10009712: ea4f 441a mov.w r4, sl, lsr #16 +10009716: eb04 4402 add.w r4, r4, r2, lsl #16 +1000971a: fba0 8904 umull r8, r9, r0, r4 +1000971e: 0c12 lsrs r2, r2, #16 +10009720: eb18 0808 adds.w r8, r8, r8 +10009724: eb02 4a0a add.w sl, r2, sl, lsl #16 +10009728: eb49 0909 adc.w r9, r9, r9 +1000972c: 1820 adds r0, r4, r0 +1000972e: eb4a 0e0e adc.w lr, sl, lr +10009732: eb18 0000 adds.w r0, r8, r0 +10009736: eb49 0e0e adc.w lr, r9, lr +1000973a: ea80 0c0c eor.w ip, r0, ip +1000973e: ea8e 0606 eor.w r6, lr, r6 +10009742: ea4f 084c mov.w r8, ip, lsl #1 +10009746: eb08 7bd6 add.w fp, r8, r6, lsr #31 +1000974a: 0076 lsls r6, r6, #1 +1000974c: eb06 72dc add.w r2, r6, ip, lsr #31 +10009750: 9202 str r2, [sp, #8] +10009752: 9a18 ldr r2, [sp, #96] @ 0x60 +10009754: 9505 str r5, [sp, #20] +10009756: fba2 6c07 umull r6, ip, r2, r7 +1000975a: 19b6 adds r6, r6, r6 +1000975c: 9d19 ldr r5, [sp, #100] @ 0x64 +1000975e: eb4c 0c0c adc.w ip, ip, ip +10009762: eb17 0902 adds.w r9, r7, r2 +10009766: 9a0c ldr r2, [sp, #48] @ 0x30 +10009768: eb42 0805 adc.w r8, r2, r5 +1000976c: eb16 0609 adds.w r6, r6, r9 +10009770: eb4c 0c08 adc.w ip, ip, r8 +10009774: ea8c 020a eor.w r2, ip, sl +10009778: fba1 8902 umull r8, r9, r1, r2 +1000977c: 9d07 ldr r5, [sp, #28] +1000977e: eb18 0808 adds.w r8, r8, r8 +10009782: ea84 0406 eor.w r4, r4, r6 +10009786: eb49 0909 adc.w r9, r9, r9 +1000978a: 1851 adds r1, r2, r1 +1000978c: eb45 0504 adc.w r5, r5, r4 +10009790: eb18 0101 adds.w r1, r8, r1 +10009794: ea81 0807 eor.w r8, r1, r7 +10009798: 9f0c ldr r7, [sp, #48] @ 0x30 +1000979a: eb49 0505 adc.w r5, r9, r5 +1000979e: 406f eors r7, r5 +100097a0: ea4f 6918 mov.w r9, r8, lsr #24 +100097a4: eb09 2907 add.w r9, r9, r7, lsl #8 +100097a8: 0e3f lsrs r7, r7, #24 +100097aa: eb07 2708 add.w r7, r7, r8, lsl #8 +100097ae: fba6 8a09 umull r8, sl, r6, r9 +100097b2: eb18 0808 adds.w r8, r8, r8 +100097b6: eb4a 0a0a adc.w sl, sl, sl +100097ba: eb19 0606 adds.w r6, r9, r6 +100097be: eb47 0c0c adc.w ip, r7, ip +100097c2: eb18 0606 adds.w r6, r8, r6 +100097c6: eb4a 0c0c adc.w ip, sl, ip +100097ca: 4072 eors r2, r6 +100097cc: ea8c 0404 eor.w r4, ip, r4 +100097d0: f843 6c10 str.w r6, [r3, #-16] +100097d4: 0c16 lsrs r6, r2, #16 +100097d6: eb06 4604 add.w r6, r6, r4, lsl #16 +100097da: 0c24 lsrs r4, r4, #16 +100097dc: eb04 4402 add.w r4, r4, r2, lsl #16 +100097e0: f843 cc0c str.w ip, [r3, #-12] +100097e4: fba1 2c06 umull r2, ip, r1, r6 +100097e8: 1892 adds r2, r2, r2 +100097ea: e9c3 64de strd r6, r4, [r3, #888] @ 0x378 +100097ee: eb4c 0c0c adc.w ip, ip, ip +100097f2: 1876 adds r6, r6, r1 +100097f4: eb44 0405 adc.w r4, r4, r5 +100097f8: 1992 adds r2, r2, r6 +100097fa: eb4c 0404 adc.w r4, ip, r4 +100097fe: ea82 0909 eor.w r9, r2, r9 +10009802: 9e11 ldr r6, [sp, #68] @ 0x44 +10009804: 4067 eors r7, r4 +10009806: f8c3 2270 str.w r2, [r3, #624] @ 0x270 +1000980a: f8c3 4274 str.w r4, [r3, #628] @ 0x274 +1000980e: ea4f 0249 mov.w r2, r9, lsl #1 +10009812: 9c01 ldr r4, [sp, #4] +10009814: eb02 72d7 add.w r2, r2, r7, lsr #31 +10009818: f8c3 20f8 str.w r2, [r3, #248] @ 0xf8 +1000981c: fba6 2504 umull r2, r5, r6, r4 +10009820: 1892 adds r2, r2, r2 +10009822: 9906 ldr r1, [sp, #24] +10009824: 416d adcs r5, r5 +10009826: 007f lsls r7, r7, #1 +10009828: 19a4 adds r4, r4, r6 +1000982a: 9e12 ldr r6, [sp, #72] @ 0x48 +1000982c: eb07 77d9 add.w r7, r7, r9, lsr #31 +10009830: eb41 0106 adc.w r1, r1, r6 +10009834: f8c3 70fc str.w r7, [r3, #252] @ 0xfc +10009838: 1912 adds r2, r2, r4 +1000983a: 9f17 ldr r7, [sp, #92] @ 0x5c +1000983c: eb45 0501 adc.w r5, r5, r1 +10009840: ea85 0607 eor.w r6, r5, r7 +10009844: fba0 4706 umull r4, r7, r0, r6 +10009848: 9916 ldr r1, [sp, #88] @ 0x58 +1000984a: 1924 adds r4, r4, r4 +1000984c: ea82 0101 eor.w r1, r2, r1 +10009850: 417f adcs r7, r7 +10009852: 1830 adds r0, r6, r0 +10009854: eb4e 0e01 adc.w lr, lr, r1 +10009858: 1820 adds r0, r4, r0 +1000985a: 9c01 ldr r4, [sp, #4] +1000985c: eb47 0e0e adc.w lr, r7, lr +10009860: ea80 0704 eor.w r7, r0, r4 +10009864: 9c06 ldr r4, [sp, #24] +10009866: ea4f 6c17 mov.w ip, r7, lsr #24 +1000986a: ea8e 0404 eor.w r4, lr, r4 +1000986e: eb0c 2c04 add.w ip, ip, r4, lsl #8 +10009872: 0e24 lsrs r4, r4, #24 +10009874: eb04 2407 add.w r4, r4, r7, lsl #8 +10009878: fba2 780c umull r7, r8, r2, ip +1000987c: 19ff adds r7, r7, r7 +1000987e: eb48 0808 adc.w r8, r8, r8 +10009882: eb1c 0202 adds.w r2, ip, r2 +10009886: eb44 0505 adc.w r5, r4, r5 +1000988a: 18bf adds r7, r7, r2 +1000988c: eb48 0505 adc.w r5, r8, r5 +10009890: 407e eors r6, r7 +10009892: 4069 eors r1, r5 +10009894: 0c32 lsrs r2, r6, #16 +10009896: eb02 4201 add.w r2, r2, r1, lsl #16 +1000989a: 0c09 lsrs r1, r1, #16 +1000989c: eb01 4106 add.w r1, r1, r6, lsl #16 +100098a0: f843 5c04 str.w r5, [r3, #-4] +100098a4: fba0 5602 umull r5, r6, r0, r2 +100098a8: 196d adds r5, r5, r5 +100098aa: e9c3 21bc strd r2, r1, [r3, #752] @ 0x2f0 +100098ae: 4176 adcs r6, r6 +100098b0: 1812 adds r2, r2, r0 +100098b2: eb41 010e adc.w r1, r1, lr +100098b6: 18ad adds r5, r5, r2 +100098b8: eb46 0101 adc.w r1, r6, r1 +100098bc: ea85 0c0c eor.w ip, r5, ip +100098c0: 404c eors r4, r1 +100098c2: f8c3 127c str.w r1, [r3, #636] @ 0x27c +100098c6: ea4f 024c mov.w r2, ip, lsl #1 +100098ca: 990a ldr r1, [sp, #40] @ 0x28 +100098cc: eb02 72d4 add.w r2, r2, r4, lsr #31 +100098d0: f8c3 5278 str.w r5, [r3, #632] @ 0x278 +100098d4: f8c3 2170 str.w r2, [r3, #368] @ 0x170 +100098d8: fba1 250b umull r2, r5, r1, fp +100098dc: 980b ldr r0, [sp, #44] @ 0x2c +100098de: 1892 adds r2, r2, r2 +100098e0: f843 7c08 str.w r7, [r3, #-8] +100098e4: 9f02 ldr r7, [sp, #8] +100098e6: 416d adcs r5, r5 +100098e8: 0064 lsls r4, r4, #1 +100098ea: eb1b 0101 adds.w r1, fp, r1 +100098ee: eb47 0000 adc.w r0, r7, r0 +100098f2: eb04 74dc add.w r4, r4, ip, lsr #31 +100098f6: 1852 adds r2, r2, r1 +100098f8: 9910 ldr r1, [sp, #64] @ 0x40 +100098fa: eb45 0500 adc.w r5, r5, r0 +100098fe: f8c3 4174 str.w r4, [r3, #372] @ 0x174 +10009902: 9c14 ldr r4, [sp, #80] @ 0x50 +10009904: ea85 0701 eor.w r7, r5, r1 +10009908: fba4 0c07 umull r0, ip, r4, r7 +1000990c: 9e0f ldr r6, [sp, #60] @ 0x3c +1000990e: 1800 adds r0, r0, r0 +10009910: ea82 0106 eor.w r1, r2, r6 +10009914: eb4c 0c0c adc.w ip, ip, ip +10009918: 193e adds r6, r7, r4 +1000991a: 9c15 ldr r4, [sp, #84] @ 0x54 +1000991c: eb44 0401 adc.w r4, r4, r1 +10009920: 1980 adds r0, r0, r6 +10009922: eb4c 0c04 adc.w ip, ip, r4 +10009926: 9c02 ldr r4, [sp, #8] +10009928: ea80 060b eor.w r6, r0, fp +1000992c: ea8c 0404 eor.w r4, ip, r4 +10009930: ea4f 6e16 mov.w lr, r6, lsr #24 +10009934: eb0e 2e04 add.w lr, lr, r4, lsl #8 +10009938: 0e24 lsrs r4, r4, #24 +1000993a: eb04 2406 add.w r4, r4, r6, lsl #8 +1000993e: fba2 680e umull r6, r8, r2, lr +10009942: 19b6 adds r6, r6, r6 +10009944: eb48 0808 adc.w r8, r8, r8 +10009948: eb1e 0202 adds.w r2, lr, r2 +1000994c: eb44 0505 adc.w r5, r4, r5 +10009950: 18b6 adds r6, r6, r2 +10009952: eb48 0505 adc.w r5, r8, r5 +10009956: 4077 eors r7, r6 +10009958: 4069 eors r1, r5 +1000995a: 0c3a lsrs r2, r7, #16 +1000995c: eb02 4201 add.w r2, r2, r1, lsl #16 +10009960: 671e str r6, [r3, #112] @ 0x70 +10009962: 675d str r5, [r3, #116] @ 0x74 +10009964: fba0 5602 umull r5, r6, r0, r2 +10009968: 0c09 lsrs r1, r1, #16 +1000996a: eb01 4107 add.w r1, r1, r7, lsl #16 +1000996e: 196d adds r5, r5, r5 +10009970: e9c3 21be strd r2, r1, [r3, #760] @ 0x2f8 +10009974: 4176 adcs r6, r6 +10009976: 1812 adds r2, r2, r0 +10009978: eb41 010c adc.w r1, r1, ip +1000997c: 18ad adds r5, r5, r2 +1000997e: eb46 0101 adc.w r1, r6, r1 +10009982: ea85 0e0e eor.w lr, r5, lr +10009986: 404c eors r4, r1 +10009988: ea4f 024e mov.w r2, lr, lsl #1 +1000998c: eb02 72d4 add.w r2, r2, r4, lsr #31 +10009990: 0064 lsls r4, r4, #1 +10009992: eb04 74de add.w r4, r4, lr, lsr #31 +10009996: f8c3 51f0 str.w r5, [r3, #496] @ 0x1f0 +1000999a: f8c3 11f4 str.w r1, [r3, #500] @ 0x1f4 +1000999e: f8c3 2178 str.w r2, [r3, #376] @ 0x178 +100099a2: f8c3 417c str.w r4, [r3, #380] @ 0x17c +100099a6: e9dd 1403 ldrd r1, r4, [sp, #12] +100099aa: fba4 2501 umull r2, r5, r4, r1 +100099ae: 1892 adds r2, r2, r2 +100099b0: 9f05 ldr r7, [sp, #20] +100099b2: 416d adcs r5, r5 +100099b4: 1861 adds r1, r4, r1 +100099b6: 9c13 ldr r4, [sp, #76] @ 0x4c +100099b8: 9e08 ldr r6, [sp, #32] +100099ba: eb47 0004 adc.w r0, r7, r4 +100099be: 1852 adds r2, r2, r1 +100099c0: 9c09 ldr r4, [sp, #36] @ 0x24 +100099c2: eb45 0900 adc.w r9, r5, r0 +100099c6: 980d ldr r0, [sp, #52] @ 0x34 +100099c8: ea89 0404 eor.w r4, r9, r4 +100099cc: fba0 1704 umull r1, r7, r0, r4 +100099d0: 9d0e ldr r5, [sp, #56] @ 0x38 +100099d2: 1849 adds r1, r1, r1 +100099d4: ea82 0606 eor.w r6, r2, r6 +100099d8: 417f adcs r7, r7 +100099da: 1820 adds r0, r4, r0 +100099dc: eb45 0c06 adc.w ip, r5, r6 +100099e0: 1809 adds r1, r1, r0 +100099e2: 9803 ldr r0, [sp, #12] +100099e4: eb47 070c adc.w r7, r7, ip +100099e8: ea81 0e00 eor.w lr, r1, r0 +100099ec: 9813 ldr r0, [sp, #76] @ 0x4c +100099ee: ea4f 6c1e mov.w ip, lr, lsr #24 +100099f2: 4078 eors r0, r7 +100099f4: eb0c 2c00 add.w ip, ip, r0, lsl #8 +100099f8: 0e00 lsrs r0, r0, #24 +100099fa: eb00 200e add.w r0, r0, lr, lsl #8 +100099fe: fba2 e80c umull lr, r8, r2, ip +10009a02: eb1e 0e0e adds.w lr, lr, lr +10009a06: eb48 0808 adc.w r8, r8, r8 +10009a0a: eb1c 0202 adds.w r2, ip, r2 +10009a0e: eb40 0509 adc.w r5, r0, r9 +10009a12: eb1e 0202 adds.w r2, lr, r2 +10009a16: eb48 0505 adc.w r5, r8, r5 +10009a1a: 4054 eors r4, r2 +10009a1c: 406e eors r6, r5 +10009a1e: 679a str r2, [r3, #120] @ 0x78 +10009a20: 0c22 lsrs r2, r4, #16 +10009a22: eb02 4206 add.w r2, r2, r6, lsl #16 +10009a26: 0c36 lsrs r6, r6, #16 +10009a28: eb06 4604 add.w r6, r6, r4, lsl #16 +10009a2c: 67dd str r5, [r3, #124] @ 0x7c +10009a2e: fba1 4502 umull r4, r5, r1, r2 +10009a32: 1924 adds r4, r4, r4 +10009a34: 416d adcs r5, r5 +10009a36: e9c3 26dc strd r2, r6, [r3, #880] @ 0x370 +10009a3a: 1852 adds r2, r2, r1 +10009a3c: eb46 0607 adc.w r6, r6, r7 +10009a40: 18a4 adds r4, r4, r2 +10009a42: eb45 0606 adc.w r6, r5, r6 +10009a46: ea84 020c eor.w r2, r4, ip +10009a4a: 4070 eors r0, r6 +10009a4c: 0055 lsls r5, r2, #1 +10009a4e: 0041 lsls r1, r0, #1 +10009a50: eb01 72d2 add.w r2, r1, r2, lsr #31 +10009a54: eb05 70d0 add.w r0, r5, r0, lsr #31 +10009a58: e9c3 023c strd r0, r2, [r3, #240] @ 0xf0 +10009a5c: 9a24 ldr r2, [sp, #144] @ 0x90 +10009a5e: e9c3 467e strd r4, r6, [r3, #504] @ 0x1f8 +10009a62: 4293 cmp r3, r2 +10009a64: f47f aca9 bne.w 100093ba +10009a68: 9c25 ldr r4, [sp, #148] @ 0x94 +10009a6a: f50d 6193 add.w r1, sp, #1176 @ 0x498 +10009a6e: 4620 mov r0, r4 +10009a70: f7fe fdec bl 1000864c +10009a74: 4620 mov r0, r4 +10009a76: a926 add r1, sp, #152 @ 0x98 +10009a78: f7fe fdec bl 10008654 +10009a7c: f60d 0d9c addw sp, sp, #2204 @ 0x89c +10009a80: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10009a84: 4621 mov r1, r4 +10009a86: f50d 6093 add.w r0, sp, #1176 @ 0x498 +10009a8a: f7fe fde3 bl 10008654 +10009a8e: f7ff b949 b.w 10008d24 +10009a92: bf00 nop + +10009a94 : +10009a94: b084 sub sp, #16 +10009a96: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10009a9a: f6ad 4d0c subw sp, sp, #3084 @ 0xc0c +10009a9e: f60d 4434 addw r4, sp, #3124 @ 0xc34 +10009aa2: e884 000e stmia.w r4, {r1, r2, r3} +10009aa6: 2800 cmp r0, #0 +10009aa8: f000 8081 beq.w 10009bae +10009aac: f890 3020 ldrb.w r3, [r0, #32] +10009ab0: 4604 mov r4, r0 +10009ab2: 2b01 cmp r3, #1 +10009ab4: f000 8109 beq.w 10009cca +10009ab8: 2b02 cmp r3, #2 +10009aba: 460e mov r6, r1 +10009abc: f89d 7c3c ldrb.w r7, [sp, #3132] @ 0xc3c +10009ac0: d07b beq.n 10009bba +10009ac2: 4691 mov r9, r2 +10009ac4: f04f 0e00 mov.w lr, #0 +10009ac8: 2900 cmp r1, #0 +10009aca: f040 80fc bne.w 10009cc6 +10009ace: fab7 f687 clz r6, r7 +10009ad2: 0976 lsrs r6, r6, #5 +10009ad4: 0076 lsls r6, r6, #1 +10009ad6: e9d4 1204 ldrd r1, r2, [r4, #16] +10009ada: fb09 6502 mla r5, r9, r2, r6 +10009ade: fb01 5507 mla r5, r1, r7, r5 +10009ae2: fbb5 f3f2 udiv r3, r5, r2 +10009ae6: fb02 5013 mls r0, r2, r3, r5 +10009aea: 2800 cmp r0, #0 +10009aec: f040 808e bne.w 10009c0c +10009af0: f102 3cff add.w ip, r2, #4294967295 @ 0xffffffff +10009af4: eb0c 0b05 add.w fp, ip, r5 +10009af8: 42b1 cmp r1, r6 +10009afa: d958 bls.n 10009bae +10009afc: f1be 0f00 cmp.w lr, #0 +10009b00: f000 8087 beq.w 10009c12 +10009b04: f10d 0a08 add.w sl, sp, #8 +10009b08: f8cd e004 str.w lr, [sp, #4] +10009b0c: e027 b.n 10009b5e +10009b0e: f89d 3c3c ldrb.w r3, [sp, #3132] @ 0xc3c +10009b12: 2b00 cmp r3, #0 +10009b14: d13d bne.n 10009b92 +10009b16: 9b01 ldr r3, [sp, #4] +10009b18: 464a mov r2, r9 +10009b1a: f60d 4134 addw r1, sp, #3124 @ 0xc34 +10009b1e: 4620 mov r0, r4 +10009b20: f8cd 6c40 str.w r6, [sp, #3136] @ 0xc40 +10009b24: f7fe ff3e bl 100089a4 +10009b28: 6963 ldr r3, [r4, #20] +10009b2a: 6822 ldr r2, [r4, #0] +10009b2c: fb03 0108 mla r1, r3, r8, r0 +10009b30: 6863 ldr r3, [r4, #4] +10009b32: 19d0 adds r0, r2, r7 +10009b34: 2b10 cmp r3, #16 +10009b36: eb02 2181 add.w r1, r2, r1, lsl #10 +10009b3a: eb02 2285 add.w r2, r2, r5, lsl #10 +10009b3e: d046 beq.n 10009bce +10009b40: f8dd 3c34 ldr.w r3, [sp, #3124] @ 0xc34 +10009b44: 2b00 cmp r3, #0 +10009b46: d042 beq.n 10009bce +10009b48: 2301 movs r3, #1 +10009b4a: f7ff f8d5 bl 10008cf8 +10009b4e: 6923 ldr r3, [r4, #16] +10009b50: 3601 adds r6, #1 +10009b52: 42b3 cmp r3, r6 +10009b54: d92b bls.n 10009bae +10009b56: 6962 ldr r2, [r4, #20] +10009b58: 3501 adds r5, #1 +10009b5a: fbb5 f3f2 udiv r3, r5, r2 +10009b5e: fb02 5313 mls r3, r2, r3, r5 +10009b62: 2b01 cmp r3, #1 +10009b64: bf13 iteet ne +10009b66: 465f movne r7, fp +10009b68: f105 37ff addeq.w r7, r5, #4294967295 @ 0xffffffff +10009b6c: 46ab moveq fp, r5 +10009b6e: f10b 0b01 addne.w fp, fp, #1 +10009b72: f016 087f ands.w r8, r6, #127 @ 0x7f +10009b76: ea4f 2787 mov.w r7, r7, lsl #10 +10009b7a: d02c beq.n 10009bd6 +10009b7c: f8dd 3c34 ldr.w r3, [sp, #3124] @ 0xc34 +10009b80: eb0a 02c8 add.w r2, sl, r8, lsl #3 +10009b84: f85a 9038 ldr.w r9, [sl, r8, lsl #3] +10009b88: 6850 ldr r0, [r2, #4] +10009b8a: f8dd 8c38 ldr.w r8, [sp, #3128] @ 0xc38 +10009b8e: 2b00 cmp r3, #0 +10009b90: d0bd beq.n 10009b0e +10009b92: 2300 movs r3, #0 +10009b94: 69a2 ldr r2, [r4, #24] +10009b96: 4619 mov r1, r3 +10009b98: f002 fbfe bl 1000c398 <____aeabi_uldivmod_veneer> +10009b9c: 2100 movs r1, #0 +10009b9e: 4299 cmp r1, r3 +10009ba0: bf08 it eq +10009ba2: 4590 cmpeq r8, r2 +10009ba4: 4690 mov r8, r2 +10009ba6: bf0c ite eq +10009ba8: 2301 moveq r3, #1 +10009baa: 460b movne r3, r1 +10009bac: e7b4 b.n 10009b18 +10009bae: f60d 4d0c addw sp, sp, #3084 @ 0xc0c +10009bb2: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10009bb6: b004 add sp, #16 +10009bb8: 4770 bx lr +10009bba: 2900 cmp r1, #0 +10009bbc: f040 80b7 bne.w 10009d2e +10009bc0: 2f01 cmp r7, #1 +10009bc2: f240 8082 bls.w 10009cca +10009bc6: 468e mov lr, r1 +10009bc8: f8dd 9c38 ldr.w r9, [sp, #3128] @ 0xc38 +10009bcc: e783 b.n 10009ad6 +10009bce: 2300 movs r3, #0 +10009bd0: f7ff f892 bl 10008cf8 +10009bd4: e7bb b.n 10009b4e +10009bd6: f8dd 3438 ldr.w r3, [sp, #1080] @ 0x438 +10009bda: 4652 mov r2, sl +10009bdc: 3301 adds r3, #1 +10009bde: f8cd 3438 str.w r3, [sp, #1080] @ 0x438 +10009be2: f8dd 343c ldr.w r3, [sp, #1084] @ 0x43c +10009be6: f50d 6181 add.w r1, sp, #1032 @ 0x408 +10009bea: f143 0300 adc.w r3, r3, #0 +10009bee: f8cd 343c str.w r3, [sp, #1084] @ 0x43c +10009bf2: f60d 0008 addw r0, sp, #2056 @ 0x808 +10009bf6: 4643 mov r3, r8 +10009bf8: f7ff f87e bl 10008cf8 +10009bfc: 4643 mov r3, r8 +10009bfe: 4652 mov r2, sl +10009c00: 4651 mov r1, sl +10009c02: f60d 0008 addw r0, sp, #2056 @ 0x808 +10009c06: f7ff f877 bl 10008cf8 +10009c0a: e7b7 b.n 10009b7c +10009c0c: f105 3bff add.w fp, r5, #4294967295 @ 0xffffffff +10009c10: e772 b.n 10009af8 +10009c12: f8cd e004 str.w lr, [sp, #4] +10009c16: e02a b.n 10009c6e +10009c18: f89d 3c3c ldrb.w r3, [sp, #3132] @ 0xc3c +10009c1c: 2b00 cmp r3, #0 +10009c1e: d140 bne.n 10009ca2 +10009c20: 2301 movs r3, #1 +10009c22: 4652 mov r2, sl +10009c24: f60d 4134 addw r1, sp, #3124 @ 0xc34 +10009c28: 4620 mov r0, r4 +10009c2a: f8cd 6c40 str.w r6, [sp, #3136] @ 0xc40 +10009c2e: f7fe feb9 bl 100089a4 +10009c32: 6963 ldr r3, [r4, #20] +10009c34: 6821 ldr r1, [r4, #0] +10009c36: fb03 0c08 mla ip, r3, r8, r0 +10009c3a: 6863 ldr r3, [r4, #4] +10009c3c: eb01 2285 add.w r2, r1, r5, lsl #10 +10009c40: 2b10 cmp r3, #16 +10009c42: eb01 0007 add.w r0, r1, r7 +10009c46: eb01 218c add.w r1, r1, ip, lsl #10 +10009c4a: d038 beq.n 10009cbe +10009c4c: f8dd 3c34 ldr.w r3, [sp, #3124] @ 0xc34 +10009c50: 2b00 cmp r3, #0 +10009c52: d034 beq.n 10009cbe +10009c54: 2301 movs r3, #1 +10009c56: f7ff f84f bl 10008cf8 +10009c5a: 6923 ldr r3, [r4, #16] +10009c5c: 3601 adds r6, #1 +10009c5e: 42b3 cmp r3, r6 +10009c60: d9a5 bls.n 10009bae +10009c62: 6962 ldr r2, [r4, #20] +10009c64: 3501 adds r5, #1 +10009c66: fbb5 f3f2 udiv r3, r5, r2 +10009c6a: f8dd 9c38 ldr.w r9, [sp, #3128] @ 0xc38 +10009c6e: fb02 5313 mls r3, r2, r3, r5 +10009c72: 2b01 cmp r3, #1 +10009c74: bf18 it ne +10009c76: 465b movne r3, fp +10009c78: 6822 ldr r2, [r4, #0] +10009c7a: bf08 it eq +10009c7c: f105 33ff addeq.w r3, r5, #4294967295 @ 0xffffffff +10009c80: ea4f 2783 mov.w r7, r3, lsl #10 +10009c84: eb02 2383 add.w r3, r2, r3, lsl #10 +10009c88: 6858 ldr r0, [r3, #4] +10009c8a: f8dd 3c34 ldr.w r3, [sp, #3124] @ 0xc34 +10009c8e: bf08 it eq +10009c90: 46ab moveq fp, r5 +10009c92: 46c8 mov r8, r9 +10009c94: f852 a007 ldr.w sl, [r2, r7] +10009c98: bf18 it ne +10009c9a: f10b 0b01 addne.w fp, fp, #1 +10009c9e: 2b00 cmp r3, #0 +10009ca0: d0ba beq.n 10009c18 +10009ca2: 2300 movs r3, #0 +10009ca4: 69a2 ldr r2, [r4, #24] +10009ca6: 4619 mov r1, r3 +10009ca8: f002 fb76 bl 1000c398 <____aeabi_uldivmod_veneer> +10009cac: 9901 ldr r1, [sp, #4] +10009cae: 4690 mov r8, r2 +10009cb0: 4299 cmp r1, r3 +10009cb2: bf08 it eq +10009cb4: 4591 cmpeq r9, r2 +10009cb6: bf0c ite eq +10009cb8: 2301 moveq r3, #1 +10009cba: 2300 movne r3, #0 +10009cbc: e7b1 b.n 10009c22 +10009cbe: 2300 movs r3, #0 +10009cc0: f7ff f81a bl 10008cf8 +10009cc4: e7c9 b.n 10009c5a +10009cc6: 4676 mov r6, lr +10009cc8: e705 b.n 10009ad6 +10009cca: 2100 movs r1, #0 +10009ccc: f60d 0008 addw r0, sp, #2056 @ 0x808 +10009cd0: f7fe fcb8 bl 10008644 +10009cd4: 2100 movs r1, #0 +10009cd6: f50d 6081 add.w r0, sp, #1032 @ 0x408 +10009cda: f7fe fcb3 bl 10008644 +10009cde: 2300 movs r3, #0 +10009ce0: 68e2 ldr r2, [r4, #12] +10009ce2: f8dd 6c34 ldr.w r6, [sp, #3124] @ 0xc34 +10009ce6: f8cd 2420 str.w r2, [sp, #1056] @ 0x420 +10009cea: 68a2 ldr r2, [r4, #8] +10009cec: f8dd 9c38 ldr.w r9, [sp, #3128] @ 0xc38 +10009cf0: f89d 7c3c ldrb.w r7, [sp, #3132] @ 0xc3c +10009cf4: f8cd 2428 str.w r2, [sp, #1064] @ 0x428 +10009cf8: f894 2020 ldrb.w r2, [r4, #32] +10009cfc: f8cd 340c str.w r3, [sp, #1036] @ 0x40c +10009d00: f8cd 6408 str.w r6, [sp, #1032] @ 0x408 +10009d04: f8cd 3414 str.w r3, [sp, #1044] @ 0x414 +10009d08: f8cd 341c str.w r3, [sp, #1052] @ 0x41c +10009d0c: f8cd 3424 str.w r3, [sp, #1060] @ 0x424 +10009d10: f8cd 342c str.w r3, [sp, #1068] @ 0x42c +10009d14: f8cd 3434 str.w r3, [sp, #1076] @ 0x434 +10009d18: f8cd 9410 str.w r9, [sp, #1040] @ 0x410 +10009d1c: f8cd 7418 str.w r7, [sp, #1048] @ 0x418 +10009d20: f8cd 2430 str.w r2, [sp, #1072] @ 0x430 +10009d24: b94e cbnz r6, 10009d3a +10009d26: b167 cbz r7, 10009d42 +10009d28: f04f 0e01 mov.w lr, #1 +10009d2c: e6d3 b.n 10009ad6 +10009d2e: f04f 0e00 mov.w lr, #0 +10009d32: f8dd 9c38 ldr.w r9, [sp, #3128] @ 0xc38 +10009d36: 4676 mov r6, lr +10009d38: e6cd b.n 10009ad6 +10009d3a: 461e mov r6, r3 +10009d3c: f04f 0e01 mov.w lr, #1 +10009d40: e6c9 b.n 10009ad6 +10009d42: f8dd 3438 ldr.w r3, [sp, #1080] @ 0x438 +10009d46: f50d 6181 add.w r1, sp, #1032 @ 0x408 +10009d4a: 3301 adds r3, #1 +10009d4c: f8cd 3438 str.w r3, [sp, #1080] @ 0x438 +10009d50: f8dd 343c ldr.w r3, [sp, #1084] @ 0x43c +10009d54: aa02 add r2, sp, #8 +10009d56: f143 0300 adc.w r3, r3, #0 +10009d5a: f8cd 343c str.w r3, [sp, #1084] @ 0x43c +10009d5e: f60d 0008 addw r0, sp, #2056 @ 0x808 +10009d62: 463b mov r3, r7 +10009d64: f7fe ffc8 bl 10008cf8 +10009d68: aa02 add r2, sp, #8 +10009d6a: 463b mov r3, r7 +10009d6c: 4611 mov r1, r2 +10009d6e: f60d 0008 addw r0, sp, #2056 @ 0x808 +10009d72: f7fe ffc1 bl 10008cf8 +10009d76: 2602 movs r6, #2 +10009d78: f04f 0e01 mov.w lr, #1 +10009d7c: f8dd 9c38 ldr.w r9, [sp, #3128] @ 0xc38 +10009d80: f89d 7c3c ldrb.w r7, [sp, #3132] @ 0xc3c +10009d84: e6a7 b.n 10009ad6 +10009d86: bf00 nop + +10009d88 : +10009d88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10009d8c: f04f 0e00 mov.w lr, #0 +10009d90: 460e mov r6, r1 +10009d92: 4675 mov r5, lr +10009d94: 4671 mov r1, lr +10009d96: e006 b.n 10009da6 +10009d98: 6834 ldr r4, [r6, #0] +10009d9a: 42ac cmp r4, r5 +10009d9c: d962 bls.n 10009e64 +10009d9e: 3501 adds r5, #1 +10009da0: f800 3b01 strb.w r3, [r0], #1 +10009da4: 3201 adds r2, #1 +10009da6: 7813 ldrb r3, [r2, #0] +10009da8: f10e 0406 add.w r4, lr, #6 +10009dac: f083 072b eor.w r7, r3, #43 @ 0x2b +10009db0: f083 082f eor.w r8, r3, #47 @ 0x2f +10009db4: 427f negs r7, r7 +10009db6: f1c8 0800 rsb r8, r8, #0 +10009dba: ea6f 2717 mvn.w r7, r7, lsr #8 +10009dbe: ea6f 2818 mvn.w r8, r8, lsr #8 +10009dc2: f1a3 0a41 sub.w sl, r3, #65 @ 0x41 +10009dc6: f1c3 0b7a rsb fp, r3, #122 @ 0x7a +10009dca: f1a3 0c61 sub.w ip, r3, #97 @ 0x61 +10009dce: f1c3 095a rsb r9, r3, #90 @ 0x5a +10009dd2: ea49 090a orr.w r9, r9, sl +10009dd6: ea4c 0c0b orr.w ip, ip, fp +10009dda: f1a3 0b47 sub.w fp, r3, #71 @ 0x47 +10009dde: ea2b 2c1c bic.w ip, fp, ip, lsr #8 +10009de2: ea2a 2b19 bic.w fp, sl, r9, lsr #8 +10009de6: f1c3 0939 rsb r9, r3, #57 @ 0x39 +10009dea: f1a3 0a30 sub.w sl, r3, #48 @ 0x30 +10009dee: ea4a 0a09 orr.w sl, sl, r9 +10009df2: f103 0904 add.w r9, r3, #4 +10009df6: ea29 291a bic.w r9, r9, sl, lsr #8 +10009dfa: ea4c 0c0b orr.w ip, ip, fp +10009dfe: ea4c 0c09 orr.w ip, ip, r9 +10009e02: f007 073e and.w r7, r7, #62 @ 0x3e +10009e06: f008 083f and.w r8, r8, #63 @ 0x3f +10009e0a: ea47 0708 orr.w r7, r7, r8 +10009e0e: fa5f fc8c uxtb.w ip, ip +10009e12: f083 0341 eor.w r3, r3, #65 @ 0x41 +10009e16: ea4c 0c07 orr.w ip, ip, r7 +10009e1a: 425b negs r3, r3 +10009e1c: 0a1b lsrs r3, r3, #8 +10009e1e: f1cc 0700 rsb r7, ip, #0 +10009e22: ea23 2317 bic.w r3, r3, r7, lsr #8 +10009e26: b2db uxtb r3, r3 +10009e28: ea43 030c orr.w r3, r3, ip +10009e2c: 2bff cmp r3, #255 @ 0xff +10009e2e: 4691 mov r9, r2 +10009e30: d00a beq.n 10009e48 +10009e32: f1ae 0e02 sub.w lr, lr, #2 +10009e36: eb03 1181 add.w r1, r3, r1, lsl #6 +10009e3a: 2c07 cmp r4, #7 +10009e3c: fa21 f30e lsr.w r3, r1, lr +10009e40: d8aa bhi.n 10009d98 +10009e42: f04f 0e06 mov.w lr, #6 +10009e46: e7ad b.n 10009da4 +10009e48: f1be 0f04 cmp.w lr, #4 +10009e4c: d80a bhi.n 10009e64 +10009e4e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10009e52: fa03 f30e lsl.w r3, r3, lr +10009e56: ea31 0303 bics.w r3, r1, r3 +10009e5a: d103 bne.n 10009e64 +10009e5c: 4648 mov r0, r9 +10009e5e: 6035 str r5, [r6, #0] +10009e60: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10009e64: f04f 0900 mov.w r9, #0 +10009e68: 4648 mov r0, r9 +10009e6a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10009e6e: bf00 nop + +10009e70 : +10009e70: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10009e74: 4c6b ldr r4, [pc, #428] @ (1000a024 ) +10009e76: 4693 mov fp, r2 +10009e78: fba4 5403 umull r5, r4, r4, r3 +10009e7c: 0862 lsrs r2, r4, #1 +10009e7e: eb02 0442 add.w r4, r2, r2, lsl #1 +10009e82: 1b1c subs r4, r3, r4 +10009e84: 2c01 cmp r4, #1 +10009e86: 4682 mov sl, r0 +10009e88: b085 sub sp, #20 +10009e8a: ea4f 0082 mov.w r0, r2, lsl #2 +10009e8e: f000 80bf beq.w 1000a010 +10009e92: 2c02 cmp r4, #2 +10009e94: f040 80b5 bne.w 1000a002 +10009e98: 3003 adds r0, #3 +10009e9a: 4281 cmp r1, r0 +10009e9c: f240 80bc bls.w 1000a018 +10009ea0: 2600 movs r6, #0 +10009ea2: 3b01 subs r3, #1 +10009ea4: 3301 adds r3, #1 +10009ea6: 445b add r3, fp +10009ea8: 4635 mov r5, r6 +10009eaa: 9302 str r3, [sp, #8] +10009eac: 9003 str r0, [sp, #12] +10009eae: e028 b.n 10009f02 +10009eb0: 9b01 ldr r3, [sp, #4] +10009eb2: ea6f 2919 mvn.w r9, r9, lsr #8 +10009eb6: ea6f 2213 mvn.w r2, r3, lsr #8 +10009eba: f1a0 013e sub.w r1, r0, #62 @ 0x3e +10009ebe: 1f03 subs r3, r0, #4 +10009ec0: f1a0 0434 sub.w r4, r0, #52 @ 0x34 +10009ec4: ea03 2311 and.w r3, r3, r1, lsr #8 +10009ec8: f100 0147 add.w r1, r0, #71 @ 0x47 +10009ecc: ea01 2114 and.w r1, r1, r4, lsr #8 +10009ed0: ea23 2314 bic.w r3, r3, r4, lsr #8 +10009ed4: ea21 2118 bic.w r1, r1, r8, lsr #8 +10009ed8: 3041 adds r0, #65 @ 0x41 +10009eda: 430b orrs r3, r1 +10009edc: ea00 2018 and.w r0, r0, r8, lsr #8 +10009ee0: f002 022b and.w r2, r2, #43 @ 0x2b +10009ee4: f009 092f and.w r9, r9, #47 @ 0x2f +10009ee8: 4303 orrs r3, r0 +10009eea: ea42 0209 orr.w r2, r2, r9 +10009eee: 4313 orrs r3, r2 +10009ef0: f88a 3001 strb.w r3, [sl, #1] +10009ef4: 9b02 ldr r3, [sp, #8] +10009ef6: f10a 0a02 add.w sl, sl, #2 +10009efa: 459b cmp fp, r3 +10009efc: f04f 0600 mov.w r6, #0 +10009f00: d048 beq.n 10009f94 +10009f02: f81b 3b01 ldrb.w r3, [fp], #1 +10009f06: 3602 adds r6, #2 +10009f08: eb03 2505 add.w r5, r3, r5, lsl #8 +10009f0c: fa25 f306 lsr.w r3, r5, r6 +10009f10: f003 033f and.w r3, r3, #63 @ 0x3f +10009f14: f083 023e eor.w r2, r3, #62 @ 0x3e +10009f18: 4252 negs r2, r2 +10009f1a: ea6f 2212 mvn.w r2, r2, lsr #8 +10009f1e: f083 013f eor.w r1, r3, #63 @ 0x3f +10009f22: 4249 negs r1, r1 +10009f24: ea6f 2111 mvn.w r1, r1, lsr #8 +10009f28: 4657 mov r7, sl +10009f2a: f005 003f and.w r0, r5, #63 @ 0x3f +10009f2e: f080 093e eor.w r9, r0, #62 @ 0x3e +10009f32: 9200 str r2, [sp, #0] +10009f34: f1c9 0200 rsb r2, r9, #0 +10009f38: 9201 str r2, [sp, #4] +10009f3a: 9a00 ldr r2, [sp, #0] +10009f3c: f001 012f and.w r1, r1, #47 @ 0x2f +10009f40: f002 022b and.w r2, r2, #43 @ 0x2b +10009f44: f1a3 0e34 sub.w lr, r3, #52 @ 0x34 +10009f48: f1a3 083e sub.w r8, r3, #62 @ 0x3e +10009f4c: 1f1c subs r4, r3, #4 +10009f4e: 4311 orrs r1, r2 +10009f50: f103 0247 add.w r2, r3, #71 @ 0x47 +10009f54: f1a3 0c1a sub.w ip, r3, #26 +10009f58: ea04 2418 and.w r4, r4, r8, lsr #8 +10009f5c: ea02 221e and.w r2, r2, lr, lsr #8 +10009f60: ea24 241e bic.w r4, r4, lr, lsr #8 +10009f64: ea22 221c bic.w r2, r2, ip, lsr #8 +10009f68: 3341 adds r3, #65 @ 0x41 +10009f6a: 4322 orrs r2, r4 +10009f6c: ea03 231c and.w r3, r3, ip, lsr #8 +10009f70: 431a orrs r2, r3 +10009f72: f080 093f eor.w r9, r0, #63 @ 0x3f +10009f76: 430a orrs r2, r1 +10009f78: 2e06 cmp r6, #6 +10009f7a: f1a0 081a sub.w r8, r0, #26 +10009f7e: f1c9 0900 rsb r9, r9, #0 +10009f82: f807 2b01 strb.w r2, [r7], #1 +10009f86: d093 beq.n 10009eb0 +10009f88: 4653 mov r3, sl +10009f8a: 46ba mov sl, r7 +10009f8c: 461f mov r7, r3 +10009f8e: 9b02 ldr r3, [sp, #8] +10009f90: 459b cmp fp, r3 +10009f92: d1b6 bne.n 10009f02 +10009f94: 9803 ldr r0, [sp, #12] +10009f96: b376 cbz r6, 10009ff6 +10009f98: f1c6 0606 rsb r6, r6, #6 +10009f9c: 40b5 lsls r5, r6 +10009f9e: f005 053f and.w r5, r5, #63 @ 0x3f +10009fa2: f085 023e eor.w r2, r5, #62 @ 0x3e +10009fa6: f085 013f eor.w r1, r5, #63 @ 0x3f +10009faa: 4252 negs r2, r2 +10009fac: 4249 negs r1, r1 +10009fae: ea6f 2212 mvn.w r2, r2, lsr #8 +10009fb2: ea6f 2111 mvn.w r1, r1, lsr #8 +10009fb6: f1a5 043e sub.w r4, r5, #62 @ 0x3e +10009fba: 1f2b subs r3, r5, #4 +10009fbc: f1a5 0c34 sub.w ip, r5, #52 @ 0x34 +10009fc0: ea03 2314 and.w r3, r3, r4, lsr #8 +10009fc4: f105 0447 add.w r4, r5, #71 @ 0x47 +10009fc8: f1a5 061a sub.w r6, r5, #26 +10009fcc: ea04 241c and.w r4, r4, ip, lsr #8 +10009fd0: ea23 231c bic.w r3, r3, ip, lsr #8 +10009fd4: ea24 2416 bic.w r4, r4, r6, lsr #8 +10009fd8: 3541 adds r5, #65 @ 0x41 +10009fda: 4323 orrs r3, r4 +10009fdc: ea05 2516 and.w r5, r5, r6, lsr #8 +10009fe0: f002 022b and.w r2, r2, #43 @ 0x2b +10009fe4: f001 012f and.w r1, r1, #47 @ 0x2f +10009fe8: 432b orrs r3, r5 +10009fea: 430a orrs r2, r1 +10009fec: 4313 orrs r3, r2 +10009fee: f88a 3000 strb.w r3, [sl] +10009ff2: f107 0a02 add.w sl, r7, #2 +10009ff6: 2300 movs r3, #0 +10009ff8: f88a 3000 strb.w r3, [sl] +10009ffc: b005 add sp, #20 +10009ffe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000a002: 4288 cmp r0, r1 +1000a004: d208 bcs.n 1000a018 +1000a006: 2b00 cmp r3, #0 +1000a008: f47f af4a bne.w 10009ea0 +1000a00c: 4618 mov r0, r3 +1000a00e: e7f2 b.n 10009ff6 +1000a010: 3002 adds r0, #2 +1000a012: 4288 cmp r0, r1 +1000a014: f4ff af44 bcc.w 10009ea0 +1000a018: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000a01c: b005 add sp, #20 +1000a01e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000a022: bf00 nop +1000a024: aaaaaaab .word 0xaaaaaaab + +1000a028 : +1000a028: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000a02c: 4604 mov r4, r0 +1000a02e: 6963 ldr r3, [r4, #20] +1000a030: 460d mov r5, r1 +1000a032: 469a mov sl, r3 +1000a034: 6863 ldr r3, [r4, #4] +1000a036: b083 sub sp, #12 +1000a038: 2100 movs r1, #0 +1000a03a: 4610 mov r0, r2 +1000a03c: 469b mov fp, r3 +1000a03e: f7fd fd27 bl 10007a90 +1000a042: 2800 cmp r0, #0 +1000a044: f000 8126 beq.w 1000a294 +1000a048: 782b ldrb r3, [r5, #0] +1000a04a: 2b24 cmp r3, #36 @ 0x24 +1000a04c: d130 bne.n 1000a0b0 +1000a04e: 4607 mov r7, r0 +1000a050: f002 f80a bl 1000c068 +1000a054: 3501 adds r5, #1 +1000a056: 4606 mov r6, r0 +1000a058: 4602 mov r2, r0 +1000a05a: 4639 mov r1, r7 +1000a05c: 4628 mov r0, r5 +1000a05e: f001 ff29 bl 1000beb4 +1000a062: bb28 cbnz r0, 1000a0b0 +1000a064: 2310 movs r3, #16 +1000a066: 63a3 str r3, [r4, #56] @ 0x38 +1000a068: 5dab ldrb r3, [r5, r6] +1000a06a: 19a8 adds r0, r5, r6 +1000a06c: 2b24 cmp r3, #36 @ 0x24 +1000a06e: d12c bne.n 1000a0ca +1000a070: 7843 ldrb r3, [r0, #1] +1000a072: 2b76 cmp r3, #118 @ 0x76 +1000a074: d129 bne.n 1000a0ca +1000a076: 7883 ldrb r3, [r0, #2] +1000a078: 3b3d subs r3, #61 @ 0x3d +1000a07a: d126 bne.n 1000a0ca +1000a07c: 78c6 ldrb r6, [r0, #3] +1000a07e: f1a6 0230 sub.w r2, r6, #48 @ 0x30 +1000a082: 2a09 cmp r2, #9 +1000a084: d814 bhi.n 1000a0b0 +1000a086: 1cc7 adds r7, r0, #3 +1000a088: 4632 mov r2, r6 +1000a08a: 4639 mov r1, r7 +1000a08c: 4d83 ldr r5, [pc, #524] @ (1000a29c ) +1000a08e: eb03 0383 add.w r3, r3, r3, lsl #2 +1000a092: 3a30 subs r2, #48 @ 0x30 +1000a094: 005b lsls r3, r3, #1 +1000a096: eb13 0c02 adds.w ip, r3, r2 +1000a09a: d209 bcs.n 1000a0b0 +1000a09c: f811 2f01 ldrb.w r2, [r1, #1]! +1000a0a0: 4663 mov r3, ip +1000a0a2: f1a2 0e30 sub.w lr, r2, #48 @ 0x30 +1000a0a6: f1be 0f09 cmp.w lr, #9 +1000a0aa: d806 bhi.n 1000a0ba +1000a0ac: 42ab cmp r3, r5 +1000a0ae: d9ee bls.n 1000a08e +1000a0b0: f06f 001f mvn.w r0, #31 +1000a0b4: b003 add sp, #12 +1000a0b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000a0ba: 428f cmp r7, r1 +1000a0bc: d0f8 beq.n 1000a0b0 +1000a0be: 2e30 cmp r6, #48 @ 0x30 +1000a0c0: f000 80e3 beq.w 1000a28a +1000a0c4: 4608 mov r0, r1 +1000a0c6: f8c4 c038 str.w ip, [r4, #56] @ 0x38 +1000a0ca: 7803 ldrb r3, [r0, #0] +1000a0cc: 2b24 cmp r3, #36 @ 0x24 +1000a0ce: d1ef bne.n 1000a0b0 +1000a0d0: 7843 ldrb r3, [r0, #1] +1000a0d2: 2b6d cmp r3, #109 @ 0x6d +1000a0d4: d1ec bne.n 1000a0b0 +1000a0d6: 7887 ldrb r7, [r0, #2] +1000a0d8: 3f3d subs r7, #61 @ 0x3d +1000a0da: d1e9 bne.n 1000a0b0 +1000a0dc: 78c1 ldrb r1, [r0, #3] +1000a0de: f1a1 0330 sub.w r3, r1, #48 @ 0x30 +1000a0e2: 2b09 cmp r3, #9 +1000a0e4: d8e4 bhi.n 1000a0b0 +1000a0e6: 1cc6 adds r6, r0, #3 +1000a0e8: 460b mov r3, r1 +1000a0ea: 4635 mov r5, r6 +1000a0ec: 4a6b ldr r2, [pc, #428] @ (1000a29c ) +1000a0ee: e000 b.n 1000a0f2 +1000a0f0: 4645 mov r5, r8 +1000a0f2: eb07 0c87 add.w ip, r7, r7, lsl #2 +1000a0f6: 3b30 subs r3, #48 @ 0x30 +1000a0f8: ea4f 0c4c mov.w ip, ip, lsl #1 +1000a0fc: eb1c 0c03 adds.w ip, ip, r3 +1000a100: bf2c ite cs +1000a102: f04f 0e01 movcs.w lr, #1 +1000a106: f04f 0e00 movcc.w lr, #0 +1000a10a: f105 0801 add.w r8, r5, #1 +1000a10e: d2cf bcs.n 1000a0b0 +1000a110: 786b ldrb r3, [r5, #1] +1000a112: 4667 mov r7, ip +1000a114: f1a3 0930 sub.w r9, r3, #48 @ 0x30 +1000a118: f1b9 0f09 cmp.w r9, #9 +1000a11c: d802 bhi.n 1000a124 +1000a11e: 4297 cmp r7, r2 +1000a120: d9e6 bls.n 1000a0f0 +1000a122: e7c5 b.n 1000a0b0 +1000a124: 4546 cmp r6, r8 +1000a126: d0c3 beq.n 1000a0b0 +1000a128: 2930 cmp r1, #48 @ 0x30 +1000a12a: f000 80a1 beq.w 1000a270 +1000a12e: f8c4 c02c str.w ip, [r4, #44] @ 0x2c +1000a132: f898 3000 ldrb.w r3, [r8] +1000a136: 2b2c cmp r3, #44 @ 0x2c +1000a138: d1ba bne.n 1000a0b0 +1000a13a: f898 3001 ldrb.w r3, [r8, #1] +1000a13e: 2b74 cmp r3, #116 @ 0x74 +1000a140: d1b6 bne.n 1000a0b0 +1000a142: f898 3002 ldrb.w r3, [r8, #2] +1000a146: 2b3d cmp r3, #61 @ 0x3d +1000a148: d1b2 bne.n 1000a0b0 +1000a14a: f898 c003 ldrb.w ip, [r8, #3] +1000a14e: f1ac 0330 sub.w r3, ip, #48 @ 0x30 +1000a152: 2b09 cmp r3, #9 +1000a154: d8ac bhi.n 1000a0b0 +1000a156: 1d2f adds r7, r5, #4 +1000a158: 4663 mov r3, ip +1000a15a: 4638 mov r0, r7 +1000a15c: 494f ldr r1, [pc, #316] @ (1000a29c ) +1000a15e: e000 b.n 1000a162 +1000a160: 4640 mov r0, r8 +1000a162: eb0e 028e add.w r2, lr, lr, lsl #2 +1000a166: 3b30 subs r3, #48 @ 0x30 +1000a168: 0052 lsls r2, r2, #1 +1000a16a: 18d2 adds r2, r2, r3 +1000a16c: bf2c ite cs +1000a16e: 2601 movcs r6, #1 +1000a170: 2600 movcc r6, #0 +1000a172: f100 0801 add.w r8, r0, #1 +1000a176: d29b bcs.n 1000a0b0 +1000a178: 7843 ldrb r3, [r0, #1] +1000a17a: 4696 mov lr, r2 +1000a17c: f1a3 0930 sub.w r9, r3, #48 @ 0x30 +1000a180: f1b9 0f09 cmp.w r9, #9 +1000a184: d802 bhi.n 1000a18c +1000a186: 458e cmp lr, r1 +1000a188: d9ea bls.n 1000a160 +1000a18a: e791 b.n 1000a0b0 +1000a18c: 4547 cmp r7, r8 +1000a18e: d08f beq.n 1000a0b0 +1000a190: f1bc 0f30 cmp.w ip, #48 @ 0x30 +1000a194: d071 beq.n 1000a27a +1000a196: 62a2 str r2, [r4, #40] @ 0x28 +1000a198: f898 3000 ldrb.w r3, [r8] +1000a19c: 2b2c cmp r3, #44 @ 0x2c +1000a19e: d187 bne.n 1000a0b0 +1000a1a0: f898 3001 ldrb.w r3, [r8, #1] +1000a1a4: 2b70 cmp r3, #112 @ 0x70 +1000a1a6: d183 bne.n 1000a0b0 +1000a1a8: f898 3002 ldrb.w r3, [r8, #2] +1000a1ac: 2b3d cmp r3, #61 @ 0x3d +1000a1ae: f47f af7f bne.w 1000a0b0 +1000a1b2: f898 e003 ldrb.w lr, [r8, #3] +1000a1b6: f1ae 0330 sub.w r3, lr, #48 @ 0x30 +1000a1ba: 2b09 cmp r3, #9 +1000a1bc: f63f af78 bhi.w 1000a0b0 +1000a1c0: 1d05 adds r5, r0, #4 +1000a1c2: 4671 mov r1, lr +1000a1c4: 462a mov r2, r5 +1000a1c6: f8df c0d4 ldr.w ip, [pc, #212] @ 1000a29c +1000a1ca: e000 b.n 1000a1ce +1000a1cc: 463a mov r2, r7 +1000a1ce: eb06 0386 add.w r3, r6, r6, lsl #2 +1000a1d2: 3930 subs r1, #48 @ 0x30 +1000a1d4: 005b lsls r3, r3, #1 +1000a1d6: 185b adds r3, r3, r1 +1000a1d8: f102 0701 add.w r7, r2, #1 +1000a1dc: f4bf af68 bcs.w 1000a0b0 +1000a1e0: 7851 ldrb r1, [r2, #1] +1000a1e2: 461e mov r6, r3 +1000a1e4: f1a1 0830 sub.w r8, r1, #48 @ 0x30 +1000a1e8: f1b8 0f09 cmp.w r8, #9 +1000a1ec: d802 bhi.n 1000a1f4 +1000a1ee: 4566 cmp r6, ip +1000a1f0: d9ec bls.n 1000a1cc +1000a1f2: e75d b.n 1000a0b0 +1000a1f4: 42bd cmp r5, r7 +1000a1f6: f43f af5b beq.w 1000a0b0 +1000a1fa: f1be 0f30 cmp.w lr, #48 @ 0x30 +1000a1fe: d040 beq.n 1000a282 +1000a200: e9c4 330c strd r3, r3, [r4, #48] @ 0x30 +1000a204: 783b ldrb r3, [r7, #0] +1000a206: 2b24 cmp r3, #36 @ 0x24 +1000a208: f47f af52 bne.w 1000a0b0 +1000a20c: 6920 ldr r0, [r4, #16] +1000a20e: 3202 adds r2, #2 +1000a210: a901 add r1, sp, #4 +1000a212: f8cd a004 str.w sl, [sp, #4] +1000a216: f7ff fdb7 bl 10009d88 +1000a21a: 2800 cmp r0, #0 +1000a21c: f43f af48 beq.w 1000a0b0 +1000a220: 9b01 ldr r3, [sp, #4] +1000a222: 6163 str r3, [r4, #20] +1000a224: 7803 ldrb r3, [r0, #0] +1000a226: 2b24 cmp r3, #36 @ 0x24 +1000a228: f47f af42 bne.w 1000a0b0 +1000a22c: 1c42 adds r2, r0, #1 +1000a22e: a901 add r1, sp, #4 +1000a230: 6820 ldr r0, [r4, #0] +1000a232: f8cd b004 str.w fp, [sp, #4] +1000a236: f7ff fda7 bl 10009d88 +1000a23a: 4605 mov r5, r0 +1000a23c: 2800 cmp r0, #0 +1000a23e: f43f af37 beq.w 1000a0b0 +1000a242: 2300 movs r3, #0 +1000a244: 9a01 ldr r2, [sp, #4] +1000a246: 4620 mov r0, r4 +1000a248: e9c4 3306 strd r3, r3, [r4, #24] +1000a24c: e9c4 3308 strd r3, r3, [r4, #32] +1000a250: e9c4 330f strd r3, r3, [r4, #60] @ 0x3c +1000a254: 6062 str r2, [r4, #4] +1000a256: 6463 str r3, [r4, #68] @ 0x44 +1000a258: f7fe fc3c bl 10008ad4 +1000a25c: 2800 cmp r0, #0 +1000a25e: f47f af29 bne.w 1000a0b4 +1000a262: 782b ldrb r3, [r5, #0] +1000a264: 2b00 cmp r3, #0 +1000a266: f47f af23 bne.w 1000a0b0 +1000a26a: b003 add sp, #12 +1000a26c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000a270: 3004 adds r0, #4 +1000a272: 4580 cmp r8, r0 +1000a274: f43f af5b beq.w 1000a12e +1000a278: e71a b.n 1000a0b0 +1000a27a: 3505 adds r5, #5 +1000a27c: 45a8 cmp r8, r5 +1000a27e: d08a beq.n 1000a196 +1000a280: e716 b.n 1000a0b0 +1000a282: 3005 adds r0, #5 +1000a284: 4287 cmp r7, r0 +1000a286: d0bb beq.n 1000a200 +1000a288: e712 b.n 1000a0b0 +1000a28a: 3004 adds r0, #4 +1000a28c: 4281 cmp r1, r0 +1000a28e: f43f af19 beq.w 1000a0c4 +1000a292: e70d b.n 1000a0b0 +1000a294: f06f 0019 mvn.w r0, #25 +1000a298: e70c b.n 1000a0b4 +1000a29a: bf00 nop +1000a29c: 19999999 .word 0x19999999 + +1000a2a0 : +1000a2a0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +1000a2a4: 4604 mov r4, r0 +1000a2a6: b089 sub sp, #36 @ 0x24 +1000a2a8: 4689 mov r9, r1 +1000a2aa: 4618 mov r0, r3 +1000a2ac: 2100 movs r1, #0 +1000a2ae: 4615 mov r5, r2 +1000a2b0: f7fd fbee bl 10007a90 +1000a2b4: 4680 mov r8, r0 +1000a2b6: 4628 mov r0, r5 +1000a2b8: f7fe fc0c bl 10008ad4 +1000a2bc: f1b8 0f00 cmp.w r8, #0 +1000a2c0: f000 80b0 beq.w 1000a424 +1000a2c4: 4606 mov r6, r0 +1000a2c6: 2800 cmp r0, #0 +1000a2c8: f040 80a8 bne.w 1000a41c +1000a2cc: f1b9 0f01 cmp.w r9, #1 +1000a2d0: f240 80a8 bls.w 1000a424 +1000a2d4: 4b55 ldr r3, [pc, #340] @ (1000a42c ) +1000a2d6: 4640 mov r0, r8 +1000a2d8: 881b ldrh r3, [r3, #0] +1000a2da: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff +1000a2de: 8023 strh r3, [r4, #0] +1000a2e0: f001 fec2 bl 1000c068 +1000a2e4: 4581 cmp r9, r0 +1000a2e6: 4607 mov r7, r0 +1000a2e8: f240 809c bls.w 1000a424 +1000a2ec: 3401 adds r4, #1 +1000a2ee: 4641 mov r1, r8 +1000a2f0: 4620 mov r0, r4 +1000a2f2: 1c7a adds r2, r7, #1 +1000a2f4: f001 fe42 bl 1000bf7c +1000a2f8: eba9 0107 sub.w r1, r9, r7 +1000a2fc: 2903 cmp r1, #3 +1000a2fe: f240 8091 bls.w 1000a424 +1000a302: 4a4b ldr r2, [pc, #300] @ (1000a430 ) +1000a304: f1a1 0803 sub.w r8, r1, #3 +1000a308: 6810 ldr r0, [r2, #0] +1000a30a: 494a ldr r1, [pc, #296] @ (1000a434 ) +1000a30c: 51e0 str r0, [r4, r7] +1000a30e: 6baa ldr r2, [r5, #56] @ 0x38 +1000a310: 4668 mov r0, sp +1000a312: f7f8 fff3 bl 100032fc <__wrap_sprintf> +1000a316: 4668 mov r0, sp +1000a318: f001 fea6 bl 1000c068 +1000a31c: 4580 cmp r8, r0 +1000a31e: 443c add r4, r7 +1000a320: 4607 mov r7, r0 +1000a322: d97f bls.n 1000a424 +1000a324: 3403 adds r4, #3 +1000a326: 4669 mov r1, sp +1000a328: 4620 mov r0, r4 +1000a32a: 1c7a adds r2, r7, #1 +1000a32c: f001 fe26 bl 1000bf7c +1000a330: eba8 0107 sub.w r1, r8, r7 +1000a334: 2903 cmp r1, #3 +1000a336: d975 bls.n 1000a424 +1000a338: 4a3f ldr r2, [pc, #252] @ (1000a438 ) +1000a33a: f1a1 0903 sub.w r9, r1, #3 +1000a33e: 6810 ldr r0, [r2, #0] +1000a340: 493c ldr r1, [pc, #240] @ (1000a434 ) +1000a342: 51e0 str r0, [r4, r7] +1000a344: 6aea ldr r2, [r5, #44] @ 0x2c +1000a346: 4668 mov r0, sp +1000a348: f7f8 ffd8 bl 100032fc <__wrap_sprintf> +1000a34c: 4668 mov r0, sp +1000a34e: f001 fe8b bl 1000c068 +1000a352: 4581 cmp r9, r0 +1000a354: 4680 mov r8, r0 +1000a356: 4427 add r7, r4 +1000a358: d964 bls.n 1000a424 +1000a35a: 1cfc adds r4, r7, #3 +1000a35c: 4669 mov r1, sp +1000a35e: 4620 mov r0, r4 +1000a360: f108 0201 add.w r2, r8, #1 +1000a364: f001 fe0a bl 1000bf7c +1000a368: eba9 0108 sub.w r1, r9, r8 +1000a36c: 2903 cmp r1, #3 +1000a36e: d959 bls.n 1000a424 +1000a370: 4a32 ldr r2, [pc, #200] @ (1000a43c ) +1000a372: 1ecf subs r7, r1, #3 +1000a374: 6810 ldr r0, [r2, #0] +1000a376: 492f ldr r1, [pc, #188] @ (1000a434 ) +1000a378: f844 0008 str.w r0, [r4, r8] +1000a37c: 6aaa ldr r2, [r5, #40] @ 0x28 +1000a37e: 4668 mov r0, sp +1000a380: f7f8 ffbc bl 100032fc <__wrap_sprintf> +1000a384: 4668 mov r0, sp +1000a386: f001 fe6f bl 1000c068 +1000a38a: 4287 cmp r7, r0 +1000a38c: 4444 add r4, r8 +1000a38e: 4680 mov r8, r0 +1000a390: d948 bls.n 1000a424 +1000a392: 3403 adds r4, #3 +1000a394: 4669 mov r1, sp +1000a396: 4620 mov r0, r4 +1000a398: f108 0201 add.w r2, r8, #1 +1000a39c: f001 fdee bl 1000bf7c +1000a3a0: eba7 0108 sub.w r1, r7, r8 +1000a3a4: 2903 cmp r1, #3 +1000a3a6: d93d bls.n 1000a424 +1000a3a8: 4a25 ldr r2, [pc, #148] @ (1000a440 ) +1000a3aa: 1ecf subs r7, r1, #3 +1000a3ac: 6810 ldr r0, [r2, #0] +1000a3ae: 4921 ldr r1, [pc, #132] @ (1000a434 ) +1000a3b0: f844 0008 str.w r0, [r4, r8] +1000a3b4: 6b2a ldr r2, [r5, #48] @ 0x30 +1000a3b6: 4668 mov r0, sp +1000a3b8: f7f8 ffa0 bl 100032fc <__wrap_sprintf> +1000a3bc: 4668 mov r0, sp +1000a3be: f001 fe53 bl 1000c068 +1000a3c2: 4287 cmp r7, r0 +1000a3c4: 4444 add r4, r8 +1000a3c6: 4680 mov r8, r0 +1000a3c8: d92c bls.n 1000a424 +1000a3ca: 4669 mov r1, sp +1000a3cc: 1ce0 adds r0, r4, #3 +1000a3ce: f108 0201 add.w r2, r8, #1 +1000a3d2: f001 fdd3 bl 1000bf7c +1000a3d6: eba7 0108 sub.w r1, r7, r8 +1000a3da: 2901 cmp r1, #1 +1000a3dc: d022 beq.n 1000a424 +1000a3de: 4a13 ldr r2, [pc, #76] @ (1000a42c ) +1000a3e0: eb00 0308 add.w r3, r0, r8 +1000a3e4: 8817 ldrh r7, [r2, #0] +1000a3e6: 1c5c adds r4, r3, #1 +1000a3e8: f820 7008 strh.w r7, [r0, r8] +1000a3ec: f101 39ff add.w r9, r1, #4294967295 @ 0xffffffff +1000a3f0: e9d5 2304 ldrd r2, r3, [r5, #16] +1000a3f4: 4649 mov r1, r9 +1000a3f6: 4620 mov r0, r4 +1000a3f8: f7ff fd3a bl 10009e70 +1000a3fc: 1c43 adds r3, r0, #1 +1000a3fe: d011 beq.n 1000a424 +1000a400: eba9 0100 sub.w r1, r9, r0 +1000a404: 2901 cmp r1, #1 +1000a406: d90d bls.n 1000a424 +1000a408: 5227 strh r7, [r4, r0] +1000a40a: 4420 add r0, r4 +1000a40c: 3901 subs r1, #1 +1000a40e: 3001 adds r0, #1 +1000a410: e9d5 2300 ldrd r2, r3, [r5] +1000a414: f7ff fd2c bl 10009e70 +1000a418: 3001 adds r0, #1 +1000a41a: d003 beq.n 1000a424 +1000a41c: 4630 mov r0, r6 +1000a41e: b009 add sp, #36 @ 0x24 +1000a420: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +1000a424: f06f 061e mvn.w r6, #30 +1000a428: e7f8 b.n 1000a41c +1000a42a: bf00 nop +1000a42c: 1000cc3c .word 0x1000cc3c +1000a430: 1000cc40 .word 0x1000cc40 +1000a434: 1000cc44 .word 0x1000cc44 +1000a438: 1000cc48 .word 0x1000cc48 +1000a43c: 1000cc4c .word 0x1000cc4c +1000a440: 1000cc50 .word 0x1000cc50 + +1000a444 : +1000a444: 4b08 ldr r3, [pc, #32] @ (1000a468 ) +1000a446: fba3 2300 umull r2, r3, r3, r0 +1000a44a: 085b lsrs r3, r3, #1 +1000a44c: eb03 0243 add.w r2, r3, r3, lsl #1 +1000a450: 1a82 subs r2, r0, r2 +1000a452: 2a01 cmp r2, #1 +1000a454: ea4f 0083 mov.w r0, r3, lsl #2 +1000a458: d003 beq.n 1000a462 +1000a45a: 2a02 cmp r2, #2 +1000a45c: d000 beq.n 1000a460 +1000a45e: 4770 bx lr +1000a460: 3001 adds r0, #1 +1000a462: 3002 adds r0, #2 +1000a464: 4770 bx lr +1000a466: bf00 nop +1000a468: aaaaaaab .word 0xaaaaaaab + +1000a46c : +1000a46c: 4603 mov r3, r0 +1000a46e: 2b09 cmp r3, #9 +1000a470: f04f 0001 mov.w r0, #1 +1000a474: d90a bls.n 1000a48c +1000a476: 4906 ldr r1, [pc, #24] @ (1000a490 ) +1000a478: 461a mov r2, r3 +1000a47a: fba1 c303 umull ip, r3, r1, r3 +1000a47e: 2a63 cmp r2, #99 @ 0x63 +1000a480: f100 0001 add.w r0, r0, #1 +1000a484: ea4f 03d3 mov.w r3, r3, lsr #3 +1000a488: d8f6 bhi.n 1000a478 +1000a48a: 4770 bx lr +1000a48c: 4770 bx lr +1000a48e: bf00 nop +1000a490: cccccccd .word 0xcccccccd + +1000a494 : +1000a494: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000a498: 4604 mov r4, r0 +1000a49a: 4625 mov r5, r4 +1000a49c: b0e7 sub sp, #412 @ 0x19c +1000a49e: f10d 0a98 add.w sl, sp, #152 @ 0x98 +1000a4a2: 2280 movs r2, #128 @ 0x80 +1000a4a4: 4650 mov r0, sl +1000a4a6: f001 fd69 bl 1000bf7c +1000a4aa: af46 add r7, sp, #280 @ 0x118 +1000a4ac: f104 0c40 add.w ip, r4, #64 @ 0x40 +1000a4b0: 463e mov r6, r7 +1000a4b2: 6828 ldr r0, [r5, #0] +1000a4b4: 6869 ldr r1, [r5, #4] +1000a4b6: 68aa ldr r2, [r5, #8] +1000a4b8: 68eb ldr r3, [r5, #12] +1000a4ba: 3510 adds r5, #16 +1000a4bc: 4565 cmp r5, ip +1000a4be: c60f stmia r6!, {r0, r1, r2, r3} +1000a4c0: f107 0710 add.w r7, r7, #16 +1000a4c4: d1f4 bne.n 1000a4b0 +1000a4c6: e9d4 2310 ldrd r2, r3, [r4, #64] @ 0x40 +1000a4ca: f082 422d eor.w r2, r2, #2902458368 @ 0xad000000 +1000a4ce: f083 43a2 eor.w r3, r3, #1358954496 @ 0x51000000 +1000a4d2: f482 0266 eor.w r2, r2, #15073280 @ 0xe60000 +1000a4d6: f483 2365 eor.w r3, r3, #937984 @ 0xe5000 +1000a4da: f482 4202 eor.w r2, r2, #33280 @ 0x8200 +1000a4de: f483 731f eor.w r3, r3, #636 @ 0x27c +1000a4e2: f082 02d1 eor.w r2, r2, #209 @ 0xd1 +1000a4e6: f083 0303 eor.w r3, r3, #3 +1000a4ea: 9206 str r2, [sp, #24] +1000a4ec: 9307 str r3, [sp, #28] +1000a4ee: e9d4 2312 ldrd r2, r3, [r4, #72] @ 0x48 +1000a4f2: f082 522c eor.w r2, r2, #721420288 @ 0x2b000000 +1000a4f6: f482 1279 eor.w r2, r2, #4079616 @ 0x3e4000 +1000a4fa: f083 431b eor.w r3, r3, #2600468480 @ 0x9b000000 +1000a4fe: f482 5230 eor.w r2, r2, #11264 @ 0x2c00 +1000a502: f483 23ad eor.w r3, r3, #354304 @ 0x56800 +1000a506: f082 021f eor.w r2, r2, #31 +1000a50a: f083 038c eor.w r3, r3, #140 @ 0x8c +1000a50e: 920a str r2, [sp, #40] @ 0x28 +1000a510: 930b str r3, [sp, #44] @ 0x2c +1000a512: e9d4 2314 ldrd r2, r3, [r4, #80] @ 0x50 +1000a516: f082 427b eor.w r2, r2, #4211081216 @ 0xfb000000 +1000a51a: f083 53fc eor.w r3, r3, #528482304 @ 0x1f800000 +1000a51e: f482 0283 eor.w r2, r2, #4292608 @ 0x418000 +1000a522: f483 3376 eor.w r3, r3, #251904 @ 0x3d800 +1000a526: f482 5275 eor.w r2, r2, #15680 @ 0x3d40 +1000a52a: f483 73d5 eor.w r3, r3, #426 @ 0x1aa +1000a52e: f082 022b eor.w r2, r2, #43 @ 0x2b +1000a532: f083 0301 eor.w r3, r3, #1 +1000a536: 921b str r2, [sp, #108] @ 0x6c +1000a538: 931c str r3, [sp, #112] @ 0x70 +1000a53a: e9d4 2316 ldrd r2, r3, [r4, #88] @ 0x58 +1000a53e: f082 529b eor.w r2, r2, #325058560 @ 0x13600000 +1000a542: f482 12f1 eor.w r2, r2, #1974272 @ 0x1e2000 +1000a546: f482 72bc eor.w r2, r2, #376 @ 0x178 +1000a54a: f082 0201 eor.w r2, r2, #1 +1000a54e: 921f str r2, [sp, #124] @ 0x7c +1000a550: 9a48 ldr r2, [sp, #288] @ 0x120 +1000a552: f083 43b7 eor.w r3, r3, #1535115264 @ 0x5b800000 +1000a556: 920d str r2, [sp, #52] @ 0x34 +1000a558: 9a49 ldr r2, [sp, #292] @ 0x124 +1000a55a: f483 03c1 eor.w r3, r3, #6324224 @ 0x608000 +1000a55e: 9214 str r2, [sp, #80] @ 0x50 +1000a560: f483 439a eor.w r3, r3, #19712 @ 0x4d00 +1000a564: 9a50 ldr r2, [sp, #320] @ 0x140 +1000a566: f083 0319 eor.w r3, r3, #25 +1000a56a: 9320 str r3, [sp, #128] @ 0x80 +1000a56c: 9208 str r2, [sp, #32] +1000a56e: 9b46 ldr r3, [sp, #280] @ 0x118 +1000a570: 9a4a ldr r2, [sp, #296] @ 0x128 +1000a572: 9302 str r3, [sp, #8] +1000a574: 9219 str r2, [sp, #100] @ 0x64 +1000a576: 9b47 ldr r3, [sp, #284] @ 0x11c +1000a578: 9a4b ldr r2, [sp, #300] @ 0x12c +1000a57a: 9303 str r3, [sp, #12] +1000a57c: 984e ldr r0, [sp, #312] @ 0x138 +1000a57e: 9b4f ldr r3, [sp, #316] @ 0x13c +1000a580: 9951 ldr r1, [sp, #324] @ 0x144 +1000a582: 921a str r2, [sp, #104] @ 0x68 +1000a584: 9a52 ldr r2, [sp, #328] @ 0x148 +1000a586: 4d12 ldr r5, [pc, #72] @ (1000a5d0 ) +1000a588: 9212 str r2, [sp, #72] @ 0x48 +1000a58a: 9a53 ldr r2, [sp, #332] @ 0x14c +1000a58c: 4e11 ldr r6, [pc, #68] @ (1000a5d4 ) +1000a58e: 9213 str r2, [sp, #76] @ 0x4c +1000a590: 9a4c ldr r2, [sp, #304] @ 0x130 +1000a592: f8df 9054 ldr.w r9, [pc, #84] @ 1000a5e8 +1000a596: 921d str r2, [sp, #116] @ 0x74 +1000a598: 9a4d ldr r2, [sp, #308] @ 0x134 +1000a59a: f8df 8050 ldr.w r8, [pc, #80] @ 1000a5ec +1000a59e: 921e str r2, [sp, #120] @ 0x78 +1000a5a0: 9a54 ldr r2, [sp, #336] @ 0x150 +1000a5a2: 9425 str r4, [sp, #148] @ 0x94 +1000a5a4: 9221 str r2, [sp, #132] @ 0x84 +1000a5a6: 9a55 ldr r2, [sp, #340] @ 0x154 +1000a5a8: 9201 str r2, [sp, #4] +1000a5aa: 4a0b ldr r2, [pc, #44] @ (1000a5d8 ) +1000a5ac: e9cd 5217 strd r5, r2, [sp, #92] @ 0x5c +1000a5b0: 4a0a ldr r2, [pc, #40] @ (1000a5dc ) +1000a5b2: e9cd 6215 strd r6, r2, [sp, #84] @ 0x54 +1000a5b6: 4a0a ldr r2, [pc, #40] @ (1000a5e0 ) +1000a5b8: 9209 str r2, [sp, #36] @ 0x24 +1000a5ba: f102 525a add.w r2, r2, #914358272 @ 0x36800000 +1000a5be: f502 12e8 add.w r2, r2, #1900544 @ 0x1d0000 +1000a5c2: f202 724a addw r2, r2, #1866 @ 0x74a +1000a5c6: 920c str r2, [sp, #48] @ 0x30 +1000a5c8: 4a06 ldr r2, [pc, #24] @ (1000a5e4 ) +1000a5ca: 9204 str r2, [sp, #16] +1000a5cc: e010 b.n 1000a5f0 +1000a5ce: bf00 nop +1000a5d0: 5f1d36f1 .word 0x5f1d36f1 +1000a5d4: fe94f82b .word 0xfe94f82b +1000a5d8: a54ff53a .word 0xa54ff53a +1000a5dc: 3c6ef372 .word 0x3c6ef372 +1000a5e0: 84caa73b .word 0x84caa73b +1000a5e4: f3bcc908 .word 0xf3bcc908 +1000a5e8: 1000d880 .word 0x1000d880 +1000a5ec: 6a09e667 .word 0x6a09e667 +1000a5f0: e9d9 4500 ldrd r4, r5, [r9] +1000a5f4: f85a 2034 ldr.w r2, [sl, r4, lsl #3] +1000a5f8: eb0a 04c4 add.w r4, sl, r4, lsl #3 +1000a5fc: 6867 ldr r7, [r4, #4] +1000a5fe: 9c02 ldr r4, [sp, #8] +1000a600: 1882 adds r2, r0, r2 +1000a602: eb43 0707 adc.w r7, r3, r7 +1000a606: 1912 adds r2, r2, r4 +1000a608: 9c03 ldr r4, [sp, #12] +1000a60a: 9e07 ldr r6, [sp, #28] +1000a60c: eb44 0707 adc.w r7, r4, r7 +1000a610: 9c04 ldr r4, [sp, #16] +1000a612: 407e eors r6, r7 +1000a614: eb14 0e06 adds.w lr, r4, r6 +1000a618: 9c06 ldr r4, [sp, #24] +1000a61a: ea8e 0000 eor.w r0, lr, r0 +1000a61e: ea84 0402 eor.w r4, r4, r2 +1000a622: eb48 0b04 adc.w fp, r8, r4 +1000a626: f85a c035 ldr.w ip, [sl, r5, lsl #3] +1000a62a: eb0a 05c5 add.w r5, sl, r5, lsl #3 +1000a62e: f8d5 8004 ldr.w r8, [r5, #4] +1000a632: ea8b 0303 eor.w r3, fp, r3 +1000a636: 0e05 lsrs r5, r0, #24 +1000a638: eb05 2503 add.w r5, r5, r3, lsl #8 +1000a63c: 0e1b lsrs r3, r3, #24 +1000a63e: eb15 0c0c adds.w ip, r5, ip +1000a642: eb03 2300 add.w r3, r3, r0, lsl #8 +1000a646: eb43 0808 adc.w r8, r3, r8 +1000a64a: eb1c 0202 adds.w r2, ip, r2 +1000a64e: eb47 0008 adc.w r0, r7, r8 +1000a652: 4056 eors r6, r2 +1000a654: 4044 eors r4, r0 +1000a656: 9003 str r0, [sp, #12] +1000a658: 0c30 lsrs r0, r6, #16 +1000a65a: eb00 4704 add.w r7, r0, r4, lsl #16 +1000a65e: 0c24 lsrs r4, r4, #16 +1000a660: eb1e 0007 adds.w r0, lr, r7 +1000a664: eb04 4606 add.w r6, r4, r6, lsl #16 +1000a668: 9202 str r2, [sp, #8] +1000a66a: 970e str r7, [sp, #56] @ 0x38 +1000a66c: f8d9 2008 ldr.w r2, [r9, #8] +1000a670: eb4b 0706 adc.w r7, fp, r6 +1000a674: 407b eors r3, r7 +1000a676: 4045 eors r5, r0 +1000a678: 9004 str r0, [sp, #16] +1000a67a: 9323 str r3, [sp, #140] @ 0x8c +1000a67c: 9808 ldr r0, [sp, #32] +1000a67e: f85a 3032 ldr.w r3, [sl, r2, lsl #3] +1000a682: eb0a 02c2 add.w r2, sl, r2, lsl #3 +1000a686: 9522 str r5, [sp, #136] @ 0x88 +1000a688: 6855 ldr r5, [r2, #4] +1000a68a: 9a0d ldr r2, [sp, #52] @ 0x34 +1000a68c: 18c3 adds r3, r0, r3 +1000a68e: eb41 0505 adc.w r5, r1, r5 +1000a692: 189b adds r3, r3, r2 +1000a694: 9a14 ldr r2, [sp, #80] @ 0x50 +1000a696: 960f str r6, [sp, #60] @ 0x3c +1000a698: eb42 0505 adc.w r5, r2, r5 +1000a69c: 9a0b ldr r2, [sp, #44] @ 0x2c +1000a69e: 9705 str r7, [sp, #20] +1000a6a0: ea82 0405 eor.w r4, r2, r5 +1000a6a4: 9a09 ldr r2, [sp, #36] @ 0x24 +1000a6a6: 9f0c ldr r7, [sp, #48] @ 0x30 +1000a6a8: 1916 adds r6, r2, r4 +1000a6aa: 9a0a ldr r2, [sp, #40] @ 0x28 +1000a6ac: ea86 0c00 eor.w ip, r6, r0 +1000a6b0: ea82 0203 eor.w r2, r2, r3 +1000a6b4: eb47 0702 adc.w r7, r7, r2 +1000a6b8: f8d9 e00c ldr.w lr, [r9, #12] +1000a6bc: 4079 eors r1, r7 +1000a6be: ea4f 601c mov.w r0, ip, lsr #24 +1000a6c2: eb00 2001 add.w r0, r0, r1, lsl #8 +1000a6c6: 0e09 lsrs r1, r1, #24 +1000a6c8: eb01 210c add.w r1, r1, ip, lsl #8 +1000a6cc: f85a c03e ldr.w ip, [sl, lr, lsl #3] +1000a6d0: eb0a 0ece add.w lr, sl, lr, lsl #3 +1000a6d4: f8de e004 ldr.w lr, [lr, #4] +1000a6d8: eb10 0c0c adds.w ip, r0, ip +1000a6dc: eb41 0e0e adc.w lr, r1, lr +1000a6e0: eb1c 0303 adds.w r3, ip, r3 +1000a6e4: eb45 050e adc.w r5, r5, lr +1000a6e8: 405c eors r4, r3 +1000a6ea: 9306 str r3, [sp, #24] +1000a6ec: 406a eors r2, r5 +1000a6ee: 0c23 lsrs r3, r4, #16 +1000a6f0: eb03 4302 add.w r3, r3, r2, lsl #16 +1000a6f4: 0c12 lsrs r2, r2, #16 +1000a6f6: 18f6 adds r6, r6, r3 +1000a6f8: eb02 4404 add.w r4, r2, r4, lsl #16 +1000a6fc: 9507 str r5, [sp, #28] +1000a6fe: f8d9 5010 ldr.w r5, [r9, #16] +1000a702: eb44 0207 adc.w r2, r4, r7 +1000a706: 4051 eors r1, r2 +1000a708: ea86 0700 eor.w r7, r6, r0 +1000a70c: 9310 str r3, [sp, #64] @ 0x40 +1000a70e: 9209 str r2, [sp, #36] @ 0x24 +1000a710: f85a 3035 ldr.w r3, [sl, r5, lsl #3] +1000a714: 9a12 ldr r2, [sp, #72] @ 0x48 +1000a716: eb0a 05c5 add.w r5, sl, r5, lsl #3 +1000a71a: 9608 str r6, [sp, #32] +1000a71c: 9714 str r7, [sp, #80] @ 0x50 +1000a71e: 686e ldr r6, [r5, #4] +1000a720: 9f13 ldr r7, [sp, #76] @ 0x4c +1000a722: 9124 str r1, [sp, #144] @ 0x90 +1000a724: 9919 ldr r1, [sp, #100] @ 0x64 +1000a726: 18d3 adds r3, r2, r3 +1000a728: eb46 0607 adc.w r6, r6, r7 +1000a72c: 185b adds r3, r3, r1 +1000a72e: 991a ldr r1, [sp, #104] @ 0x68 +1000a730: 981b ldr r0, [sp, #108] @ 0x6c +1000a732: eb41 0606 adc.w r6, r1, r6 +1000a736: 991c ldr r1, [sp, #112] @ 0x70 +1000a738: 9411 str r4, [sp, #68] @ 0x44 +1000a73a: ea81 0406 eor.w r4, r1, r6 +1000a73e: 9915 ldr r1, [sp, #84] @ 0x54 +1000a740: 9d16 ldr r5, [sp, #88] @ 0x58 +1000a742: 1909 adds r1, r1, r4 +1000a744: ea80 0003 eor.w r0, r0, r3 +1000a748: ea81 0c02 eor.w ip, r1, r2 +1000a74c: eb45 0500 adc.w r5, r5, r0 +1000a750: f8d9 e014 ldr.w lr, [r9, #20] +1000a754: ea85 0207 eor.w r2, r5, r7 +1000a758: ea4f 671c mov.w r7, ip, lsr #24 +1000a75c: eb07 2702 add.w r7, r7, r2, lsl #8 +1000a760: 0e12 lsrs r2, r2, #24 +1000a762: eb02 220c add.w r2, r2, ip, lsl #8 +1000a766: f85a c03e ldr.w ip, [sl, lr, lsl #3] +1000a76a: eb0a 0ece add.w lr, sl, lr, lsl #3 +1000a76e: f8de e004 ldr.w lr, [lr, #4] +1000a772: eb17 0c0c adds.w ip, r7, ip +1000a776: eb42 0e0e adc.w lr, r2, lr +1000a77a: eb1c 0303 adds.w r3, ip, r3 +1000a77e: eb46 060e adc.w r6, r6, lr +1000a782: 405c eors r4, r3 +1000a784: 4070 eors r0, r6 +1000a786: 960b str r6, [sp, #44] @ 0x2c +1000a788: 0c26 lsrs r6, r4, #16 +1000a78a: eb06 4600 add.w r6, r6, r0, lsl #16 +1000a78e: 0c00 lsrs r0, r0, #16 +1000a790: 1989 adds r1, r1, r6 +1000a792: eb00 4404 add.w r4, r0, r4, lsl #16 +1000a796: 930a str r3, [sp, #40] @ 0x28 +1000a798: f8d9 3018 ldr.w r3, [r9, #24] +1000a79c: eb45 0504 adc.w r5, r5, r4 +1000a7a0: f85a 0033 ldr.w r0, [sl, r3, lsl #3] +1000a7a4: 406a eors r2, r5 +1000a7a6: 9612 str r6, [sp, #72] @ 0x48 +1000a7a8: eb0a 03c3 add.w r3, sl, r3, lsl #3 +1000a7ac: 9e21 ldr r6, [sp, #132] @ 0x84 +1000a7ae: 685b ldr r3, [r3, #4] +1000a7b0: 921a str r2, [sp, #104] @ 0x68 +1000a7b2: 9a01 ldr r2, [sp, #4] +1000a7b4: 404f eors r7, r1 +1000a7b6: 1830 adds r0, r6, r0 +1000a7b8: eb42 0e03 adc.w lr, r2, r3 +1000a7bc: 9413 str r4, [sp, #76] @ 0x4c +1000a7be: 9719 str r7, [sp, #100] @ 0x64 +1000a7c0: 9b1d ldr r3, [sp, #116] @ 0x74 +1000a7c2: 9c18 ldr r4, [sp, #96] @ 0x60 +1000a7c4: 18c0 adds r0, r0, r3 +1000a7c6: 9b1e ldr r3, [sp, #120] @ 0x78 +1000a7c8: f8d9 b01c ldr.w fp, [r9, #28] +1000a7cc: eb43 0e0e adc.w lr, r3, lr +1000a7d0: 9b20 ldr r3, [sp, #128] @ 0x80 +1000a7d2: f109 0940 add.w r9, r9, #64 @ 0x40 +1000a7d6: ea8e 0703 eor.w r7, lr, r3 +1000a7da: 9b17 ldr r3, [sp, #92] @ 0x5c +1000a7dc: 18fa adds r2, r7, r3 +1000a7de: 9b1f ldr r3, [sp, #124] @ 0x7c +1000a7e0: ea82 0806 eor.w r8, r2, r6 +1000a7e4: ea83 0300 eor.w r3, r3, r0 +1000a7e8: 9e01 ldr r6, [sp, #4] +1000a7ea: eb44 0403 adc.w r4, r4, r3 +1000a7ee: 4066 eors r6, r4 +1000a7f0: ea4f 6c18 mov.w ip, r8, lsr #24 +1000a7f4: eb0c 2c06 add.w ip, ip, r6, lsl #8 +1000a7f8: 0e36 lsrs r6, r6, #24 +1000a7fa: eb06 2608 add.w r6, r6, r8, lsl #8 +1000a7fe: f85a 803b ldr.w r8, [sl, fp, lsl #3] +1000a802: eb0a 0bcb add.w fp, sl, fp, lsl #3 +1000a806: f8db b004 ldr.w fp, [fp, #4] +1000a80a: eb1c 0808 adds.w r8, ip, r8 +1000a80e: eb46 0b0b adc.w fp, r6, fp +1000a812: eb18 0000 adds.w r0, r8, r0 +1000a816: 9001 str r0, [sp, #4] +1000a818: eb4e 000b adc.w r0, lr, fp +1000a81c: 900c str r0, [sp, #48] @ 0x30 +1000a81e: 9801 ldr r0, [sp, #4] +1000a820: f859 bc1c ldr.w fp, [r9, #-28] +1000a824: ea80 0e07 eor.w lr, r0, r7 +1000a828: 9f0c ldr r7, [sp, #48] @ 0x30 +1000a82a: ea4f 401e mov.w r0, lr, lsr #16 +1000a82e: 407b eors r3, r7 +1000a830: eb00 4003 add.w r0, r0, r3, lsl #16 +1000a834: 0c1b lsrs r3, r3, #16 +1000a836: 1812 adds r2, r2, r0 +1000a838: eb03 430e add.w r3, r3, lr, lsl #16 +1000a83c: eb44 0403 adc.w r4, r4, r3 +1000a840: 940d str r4, [sp, #52] @ 0x34 +1000a842: ea82 040c eor.w r4, r2, ip +1000a846: 941b str r4, [sp, #108] @ 0x6c +1000a848: 9c0d ldr r4, [sp, #52] @ 0x34 +1000a84a: f859 7c20 ldr.w r7, [r9, #-32] +1000a84e: 4066 eors r6, r4 +1000a850: 961c str r6, [sp, #112] @ 0x70 +1000a852: 9c02 ldr r4, [sp, #8] +1000a854: f85a 6037 ldr.w r6, [sl, r7, lsl #3] +1000a858: eb0a 07c7 add.w r7, sl, r7, lsl #3 +1000a85c: 687f ldr r7, [r7, #4] +1000a85e: 19a6 adds r6, r4, r6 +1000a860: 9c03 ldr r4, [sp, #12] +1000a862: eb44 0c07 adc.w ip, r4, r7 +1000a866: 9c14 ldr r4, [sp, #80] @ 0x50 +1000a868: 9f24 ldr r7, [sp, #144] @ 0x90 +1000a86a: ea4f 0e44 mov.w lr, r4, lsl #1 +1000a86e: eb0e 7ed7 add.w lr, lr, r7, lsr #31 +1000a872: 007f lsls r7, r7, #1 +1000a874: eb16 060e adds.w r6, r6, lr +1000a878: eb07 77d4 add.w r7, r7, r4, lsr #31 +1000a87c: eb47 0c0c adc.w ip, r7, ip +1000a880: ea8c 0303 eor.w r3, ip, r3 +1000a884: 18c9 adds r1, r1, r3 +1000a886: ea80 0006 eor.w r0, r0, r6 +1000a88a: eb45 0500 adc.w r5, r5, r0 +1000a88e: ea81 0e0e eor.w lr, r1, lr +1000a892: 406f eors r7, r5 +1000a894: ea4f 681e mov.w r8, lr, lsr #24 +1000a898: f85a 403b ldr.w r4, [sl, fp, lsl #3] +1000a89c: eb08 2807 add.w r8, r8, r7, lsl #8 +1000a8a0: eb0a 0bcb add.w fp, sl, fp, lsl #3 +1000a8a4: 0e3f lsrs r7, r7, #24 +1000a8a6: eb07 270e add.w r7, r7, lr, lsl #8 +1000a8aa: f8db e004 ldr.w lr, [fp, #4] +1000a8ae: 1936 adds r6, r6, r4 +1000a8b0: eb4c 0c0e adc.w ip, ip, lr +1000a8b4: eb16 0408 adds.w r4, r6, r8 +1000a8b8: eb47 060c adc.w r6, r7, ip +1000a8bc: 4063 eors r3, r4 +1000a8be: 4070 eors r0, r6 +1000a8c0: ea4f 4c13 mov.w ip, r3, lsr #16 +1000a8c4: 9402 str r4, [sp, #8] +1000a8c6: eb0c 4400 add.w r4, ip, r0, lsl #16 +1000a8ca: 0c00 lsrs r0, r0, #16 +1000a8cc: 1909 adds r1, r1, r4 +1000a8ce: eb00 4003 add.w r0, r0, r3, lsl #16 +1000a8d2: eb40 0505 adc.w r5, r0, r5 +1000a8d6: 9603 str r6, [sp, #12] +1000a8d8: 941f str r4, [sp, #124] @ 0x7c +1000a8da: f859 6c18 ldr.w r6, [r9, #-24] +1000a8de: 9020 str r0, [sp, #128] @ 0x80 +1000a8e0: 9115 str r1, [sp, #84] @ 0x54 +1000a8e2: ea81 0108 eor.w r1, r1, r8 +1000a8e6: 9121 str r1, [sp, #132] @ 0x84 +1000a8e8: ea85 0107 eor.w r1, r5, r7 +1000a8ec: f85a 3036 ldr.w r3, [sl, r6, lsl #3] +1000a8f0: 9124 str r1, [sp, #144] @ 0x90 +1000a8f2: 9906 ldr r1, [sp, #24] +1000a8f4: eb0a 06c6 add.w r6, sl, r6, lsl #3 +1000a8f8: 6870 ldr r0, [r6, #4] +1000a8fa: 18cb adds r3, r1, r3 +1000a8fc: 9907 ldr r1, [sp, #28] +1000a8fe: 9f19 ldr r7, [sp, #100] @ 0x64 +1000a900: eb41 0000 adc.w r0, r1, r0 +1000a904: 991a ldr r1, [sp, #104] @ 0x68 +1000a906: 9516 str r5, [sp, #88] @ 0x58 +1000a908: 007d lsls r5, r7, #1 +1000a90a: eb05 75d1 add.w r5, r5, r1, lsr #31 +1000a90e: 0049 lsls r1, r1, #1 +1000a910: 195b adds r3, r3, r5 +1000a912: 9e0f ldr r6, [sp, #60] @ 0x3c +1000a914: 9c0e ldr r4, [sp, #56] @ 0x38 +1000a916: eb01 71d7 add.w r1, r1, r7, lsr #31 +1000a91a: eb41 0000 adc.w r0, r1, r0 +1000a91e: ea80 0706 eor.w r7, r0, r6 +1000a922: ea83 0604 eor.w r6, r3, r4 +1000a926: 9c0d ldr r4, [sp, #52] @ 0x34 +1000a928: 19d2 adds r2, r2, r7 +1000a92a: eb44 0406 adc.w r4, r4, r6 +1000a92e: 4055 eors r5, r2 +1000a930: f859 ec14 ldr.w lr, [r9, #-20] +1000a934: 4061 eors r1, r4 +1000a936: ea4f 6c15 mov.w ip, r5, lsr #24 +1000a93a: eb0c 2c01 add.w ip, ip, r1, lsl #8 +1000a93e: 0e09 lsrs r1, r1, #24 +1000a940: eb01 2105 add.w r1, r1, r5, lsl #8 +1000a944: f85a 503e ldr.w r5, [sl, lr, lsl #3] +1000a948: eb0a 0ece add.w lr, sl, lr, lsl #3 +1000a94c: 195b adds r3, r3, r5 +1000a94e: f8de 5004 ldr.w r5, [lr, #4] +1000a952: eb40 0005 adc.w r0, r0, r5 +1000a956: eb13 050c adds.w r5, r3, ip +1000a95a: eb41 0300 adc.w r3, r1, r0 +1000a95e: 406f eors r7, r5 +1000a960: 405e eors r6, r3 +1000a962: 9314 str r3, [sp, #80] @ 0x50 +1000a964: 0c3b lsrs r3, r7, #16 +1000a966: 950d str r5, [sp, #52] @ 0x34 +1000a968: eb03 4506 add.w r5, r3, r6, lsl #16 +1000a96c: 0c36 lsrs r6, r6, #16 +1000a96e: eb06 4707 add.w r7, r6, r7, lsl #16 +1000a972: 9506 str r5, [sp, #24] +1000a974: 1955 adds r5, r2, r5 +1000a976: f859 0c10 ldr.w r0, [r9, #-16] +1000a97a: 9707 str r7, [sp, #28] +1000a97c: eb47 0704 adc.w r7, r7, r4 +1000a980: 4079 eors r1, r7 +1000a982: f85a 3030 ldr.w r3, [sl, r0, lsl #3] +1000a986: 9718 str r7, [sp, #96] @ 0x60 +1000a988: 910f str r1, [sp, #60] @ 0x3c +1000a98a: 9f1b ldr r7, [sp, #108] @ 0x6c +1000a98c: 990a ldr r1, [sp, #40] @ 0x28 +1000a98e: 9a1c ldr r2, [sp, #112] @ 0x70 +1000a990: eb0a 00c0 add.w r0, sl, r0, lsl #3 +1000a994: 18cb adds r3, r1, r3 +1000a996: 9c0b ldr r4, [sp, #44] @ 0x2c +1000a998: 6841 ldr r1, [r0, #4] +1000a99a: ea4f 0047 mov.w r0, r7, lsl #1 +1000a99e: eb00 70d2 add.w r0, r0, r2, lsr #31 +1000a9a2: ea4f 0242 mov.w r2, r2, lsl #1 +1000a9a6: 9e11 ldr r6, [sp, #68] @ 0x44 +1000a9a8: eb44 0101 adc.w r1, r4, r1 +1000a9ac: eb02 72d7 add.w r2, r2, r7, lsr #31 +1000a9b0: 181b adds r3, r3, r0 +1000a9b2: 9517 str r5, [sp, #92] @ 0x5c +1000a9b4: ea85 050c eor.w r5, r5, ip +1000a9b8: eb42 0101 adc.w r1, r2, r1 +1000a9bc: 950e str r5, [sp, #56] @ 0x38 +1000a9be: 9c04 ldr r4, [sp, #16] +1000a9c0: ea81 0c06 eor.w ip, r1, r6 +1000a9c4: eb14 050c adds.w r5, r4, ip +1000a9c8: 9c10 ldr r4, [sp, #64] @ 0x40 +1000a9ca: 9f05 ldr r7, [sp, #20] +1000a9cc: ea83 0604 eor.w r6, r3, r4 +1000a9d0: eb47 0406 adc.w r4, r7, r6 +1000a9d4: 4068 eors r0, r5 +1000a9d6: f859 ec0c ldr.w lr, [r9, #-12] +1000a9da: 4062 eors r2, r4 +1000a9dc: 0e07 lsrs r7, r0, #24 +1000a9de: eb07 2702 add.w r7, r7, r2, lsl #8 +1000a9e2: 0e12 lsrs r2, r2, #24 +1000a9e4: eb02 2200 add.w r2, r2, r0, lsl #8 +1000a9e8: f85a 003e ldr.w r0, [sl, lr, lsl #3] +1000a9ec: eb0a 0ece add.w lr, sl, lr, lsl #3 +1000a9f0: 181b adds r3, r3, r0 +1000a9f2: f8de 0004 ldr.w r0, [lr, #4] +1000a9f6: eb41 0100 adc.w r1, r1, r0 +1000a9fa: 19db adds r3, r3, r7 +1000a9fc: eb42 0101 adc.w r1, r2, r1 +1000aa00: ea83 0c0c eor.w ip, r3, ip +1000aa04: 404e eors r6, r1 +1000aa06: 911a str r1, [sp, #104] @ 0x68 +1000aa08: ea4f 411c mov.w r1, ip, lsr #16 +1000aa0c: eb01 4106 add.w r1, r1, r6, lsl #16 +1000aa10: 9319 str r3, [sp, #100] @ 0x64 +1000aa12: f859 3c08 ldr.w r3, [r9, #-8] +1000aa16: 910a str r1, [sp, #40] @ 0x28 +1000aa18: 1869 adds r1, r5, r1 +1000aa1a: ea87 0701 eor.w r7, r7, r1 +1000aa1e: 9d01 ldr r5, [sp, #4] +1000aa20: 9104 str r1, [sp, #16] +1000aa22: ea4f 4616 mov.w r6, r6, lsr #16 +1000aa26: f85a 1033 ldr.w r1, [sl, r3, lsl #3] +1000aa2a: eb06 460c add.w r6, r6, ip, lsl #16 +1000aa2e: eb0a 03c3 add.w r3, sl, r3, lsl #3 +1000aa32: 685b ldr r3, [r3, #4] +1000aa34: eb44 0806 adc.w r8, r4, r6 +1000aa38: 1869 adds r1, r5, r1 +1000aa3a: 9d0c ldr r5, [sp, #48] @ 0x30 +1000aa3c: 9822 ldr r0, [sp, #136] @ 0x88 +1000aa3e: eb45 0e03 adc.w lr, r5, r3 +1000aa42: 9b23 ldr r3, [sp, #140] @ 0x8c +1000aa44: ea4f 0c40 mov.w ip, r0, lsl #1 +1000aa48: ea88 0402 eor.w r4, r8, r2 +1000aa4c: eb0c 7cd3 add.w ip, ip, r3, lsr #31 +1000aa50: 005b lsls r3, r3, #1 +1000aa52: eb11 010c adds.w r1, r1, ip +1000aa56: eb03 73d0 add.w r3, r3, r0, lsr #31 +1000aa5a: 9405 str r4, [sp, #20] +1000aa5c: 9c13 ldr r4, [sp, #76] @ 0x4c +1000aa5e: eb43 0e0e adc.w lr, r3, lr +1000aa62: 960b str r6, [sp, #44] @ 0x2c +1000aa64: 9e08 ldr r6, [sp, #32] +1000aa66: ea8e 0504 eor.w r5, lr, r4 +1000aa6a: 9812 ldr r0, [sp, #72] @ 0x48 +1000aa6c: 1974 adds r4, r6, r5 +1000aa6e: 9e09 ldr r6, [sp, #36] @ 0x24 +1000aa70: ea81 0000 eor.w r0, r1, r0 +1000aa74: eb46 0600 adc.w r6, r6, r0 +1000aa78: 4073 eors r3, r6 +1000aa7a: 9601 str r6, [sp, #4] +1000aa7c: f859 6c04 ldr.w r6, [r9, #-4] +1000aa80: ea84 0c0c eor.w ip, r4, ip +1000aa84: f85a 2036 ldr.w r2, [sl, r6, lsl #3] +1000aa88: eb0a 0bc6 add.w fp, sl, r6, lsl #3 +1000aa8c: f8db 6004 ldr.w r6, [fp, #4] +1000aa90: 1889 adds r1, r1, r2 +1000aa92: eb4e 0e06 adc.w lr, lr, r6 +1000aa96: ea4f 661c mov.w r6, ip, lsr #24 +1000aa9a: eb06 2603 add.w r6, r6, r3, lsl #8 +1000aa9e: 0e1b lsrs r3, r3, #24 +1000aaa0: 1989 adds r1, r1, r6 +1000aaa2: eb03 230c add.w r3, r3, ip, lsl #8 +1000aaa6: eb43 020e adc.w r2, r3, lr +1000aaaa: 404d eors r5, r1 +1000aaac: 911d str r1, [sp, #116] @ 0x74 +1000aaae: 4050 eors r0, r2 +1000aab0: 0c29 lsrs r1, r5, #16 +1000aab2: 921e str r2, [sp, #120] @ 0x78 +1000aab4: eb01 4200 add.w r2, r1, r0, lsl #16 +1000aab8: 0c00 lsrs r0, r0, #16 +1000aaba: eb00 4005 add.w r0, r0, r5, lsl #16 +1000aabe: 921b str r2, [sp, #108] @ 0x6c +1000aac0: 18a2 adds r2, r4, r2 +1000aac2: 4614 mov r4, r2 +1000aac4: 9209 str r2, [sp, #36] @ 0x24 +1000aac6: 4602 mov r2, r0 +1000aac8: 901c str r0, [sp, #112] @ 0x70 +1000aaca: 9801 ldr r0, [sp, #4] +1000aacc: ea86 0604 eor.w r6, r6, r4 +1000aad0: eb42 0000 adc.w r0, r2, r0 +1000aad4: 4043 eors r3, r0 +1000aad6: 900c str r0, [sp, #48] @ 0x30 +1000aad8: 9821 ldr r0, [sp, #132] @ 0x84 +1000aada: 9c24 ldr r4, [sp, #144] @ 0x90 +1000aadc: 0041 lsls r1, r0, #1 +1000aade: eb01 72d4 add.w r2, r1, r4, lsr #31 +1000aae2: 0061 lsls r1, r4, #1 +1000aae4: 9c0e ldr r4, [sp, #56] @ 0x38 +1000aae6: 9d0f ldr r5, [sp, #60] @ 0x3c +1000aae8: eb01 71d0 add.w r1, r1, r0, lsr #31 +1000aaec: 0060 lsls r0, r4, #1 +1000aaee: 9208 str r2, [sp, #32] +1000aaf0: eb00 72d5 add.w r2, r0, r5, lsr #31 +1000aaf4: 0068 lsls r0, r5, #1 +1000aaf6: 9212 str r2, [sp, #72] @ 0x48 +1000aaf8: eb00 72d4 add.w r2, r0, r4, lsr #31 +1000aafc: 9c05 ldr r4, [sp, #20] +1000aafe: 0078 lsls r0, r7, #1 +1000ab00: 9213 str r2, [sp, #76] @ 0x4c +1000ab02: eb00 72d4 add.w r2, r0, r4, lsr #31 +1000ab06: 9221 str r2, [sp, #132] @ 0x84 +1000ab08: 0062 lsls r2, r4, #1 +1000ab0a: eb02 72d7 add.w r2, r2, r7, lsr #31 +1000ab0e: 9201 str r2, [sp, #4] +1000ab10: 4a36 ldr r2, [pc, #216] @ (1000abec ) +1000ab12: 0070 lsls r0, r6, #1 +1000ab14: eb00 70d3 add.w r0, r0, r3, lsr #31 +1000ab18: 454a cmp r2, r9 +1000ab1a: ea4f 0343 mov.w r3, r3, lsl #1 +1000ab1e: eb03 73d6 add.w r3, r3, r6, lsr #31 +1000ab22: f47f ad65 bne.w 1000a5f0 +1000ab26: 9c25 ldr r4, [sp, #148] @ 0x94 +1000ab28: 4684 mov ip, r0 +1000ab2a: 6822 ldr r2, [r4, #0] +1000ab2c: 9802 ldr r0, [sp, #8] +1000ab2e: 4042 eors r2, r0 +1000ab30: 9804 ldr r0, [sp, #16] +1000ab32: 4042 eors r2, r0 +1000ab34: 6022 str r2, [r4, #0] +1000ab36: 9803 ldr r0, [sp, #12] +1000ab38: 6862 ldr r2, [r4, #4] +1000ab3a: 4042 eors r2, r0 +1000ab3c: ea82 0208 eor.w r2, r2, r8 +1000ab40: 980d ldr r0, [sp, #52] @ 0x34 +1000ab42: 6062 str r2, [r4, #4] +1000ab44: 68a2 ldr r2, [r4, #8] +1000ab46: 4042 eors r2, r0 +1000ab48: 9809 ldr r0, [sp, #36] @ 0x24 +1000ab4a: 4042 eors r2, r0 +1000ab4c: 60a2 str r2, [r4, #8] +1000ab4e: 9814 ldr r0, [sp, #80] @ 0x50 +1000ab50: 68e2 ldr r2, [r4, #12] +1000ab52: 4042 eors r2, r0 +1000ab54: 980c ldr r0, [sp, #48] @ 0x30 +1000ab56: 4042 eors r2, r0 +1000ab58: 60e2 str r2, [r4, #12] +1000ab5a: 9819 ldr r0, [sp, #100] @ 0x64 +1000ab5c: 6922 ldr r2, [r4, #16] +1000ab5e: 4042 eors r2, r0 +1000ab60: 9815 ldr r0, [sp, #84] @ 0x54 +1000ab62: 4042 eors r2, r0 +1000ab64: 6122 str r2, [r4, #16] +1000ab66: 981a ldr r0, [sp, #104] @ 0x68 +1000ab68: 6962 ldr r2, [r4, #20] +1000ab6a: 4042 eors r2, r0 +1000ab6c: 9816 ldr r0, [sp, #88] @ 0x58 +1000ab6e: 4042 eors r2, r0 +1000ab70: 6162 str r2, [r4, #20] +1000ab72: 981d ldr r0, [sp, #116] @ 0x74 +1000ab74: 69a2 ldr r2, [r4, #24] +1000ab76: 4042 eors r2, r0 +1000ab78: 9817 ldr r0, [sp, #92] @ 0x5c +1000ab7a: 4042 eors r2, r0 +1000ab7c: 61a2 str r2, [r4, #24] +1000ab7e: 981e ldr r0, [sp, #120] @ 0x78 +1000ab80: 69e2 ldr r2, [r4, #28] +1000ab82: 4042 eors r2, r0 +1000ab84: 9818 ldr r0, [sp, #96] @ 0x60 +1000ab86: 4042 eors r2, r0 +1000ab88: 61e2 str r2, [r4, #28] +1000ab8a: 6a22 ldr r2, [r4, #32] +1000ab8c: 9806 ldr r0, [sp, #24] +1000ab8e: 4042 eors r2, r0 +1000ab90: ea82 020c eor.w r2, r2, ip +1000ab94: 9807 ldr r0, [sp, #28] +1000ab96: 6222 str r2, [r4, #32] +1000ab98: 6a62 ldr r2, [r4, #36] @ 0x24 +1000ab9a: 4042 eors r2, r0 +1000ab9c: 405a eors r2, r3 +1000ab9e: 6262 str r2, [r4, #36] @ 0x24 +1000aba0: 6aa3 ldr r3, [r4, #40] @ 0x28 +1000aba2: 9a0a ldr r2, [sp, #40] @ 0x28 +1000aba4: 4053 eors r3, r2 +1000aba6: 9a08 ldr r2, [sp, #32] +1000aba8: 4053 eors r3, r2 +1000abaa: 62a3 str r3, [r4, #40] @ 0x28 +1000abac: 9a0b ldr r2, [sp, #44] @ 0x2c +1000abae: 6ae3 ldr r3, [r4, #44] @ 0x2c +1000abb0: 4053 eors r3, r2 +1000abb2: 404b eors r3, r1 +1000abb4: 9a1b ldr r2, [sp, #108] @ 0x6c +1000abb6: 62e3 str r3, [r4, #44] @ 0x2c +1000abb8: 6b23 ldr r3, [r4, #48] @ 0x30 +1000abba: 4053 eors r3, r2 +1000abbc: 9a12 ldr r2, [sp, #72] @ 0x48 +1000abbe: 4053 eors r3, r2 +1000abc0: 6323 str r3, [r4, #48] @ 0x30 +1000abc2: 9a1c ldr r2, [sp, #112] @ 0x70 +1000abc4: 6b63 ldr r3, [r4, #52] @ 0x34 +1000abc6: 4053 eors r3, r2 +1000abc8: 9a13 ldr r2, [sp, #76] @ 0x4c +1000abca: 4053 eors r3, r2 +1000abcc: 6363 str r3, [r4, #52] @ 0x34 +1000abce: 9a1f ldr r2, [sp, #124] @ 0x7c +1000abd0: 6ba3 ldr r3, [r4, #56] @ 0x38 +1000abd2: 4053 eors r3, r2 +1000abd4: 9a21 ldr r2, [sp, #132] @ 0x84 +1000abd6: 4053 eors r3, r2 +1000abd8: 63a3 str r3, [r4, #56] @ 0x38 +1000abda: 9a20 ldr r2, [sp, #128] @ 0x80 +1000abdc: 6be3 ldr r3, [r4, #60] @ 0x3c +1000abde: 4053 eors r3, r2 +1000abe0: 9a01 ldr r2, [sp, #4] +1000abe2: 4053 eors r3, r2 +1000abe4: 63e3 str r3, [r4, #60] @ 0x3c +1000abe6: b067 add sp, #412 @ 0x19c +1000abe8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000abec: 1000db80 .word 0x1000db80 + +1000abf0 : +1000abf0: 2900 cmp r1, #0 +1000abf2: d063 beq.n 1000acbc +1000abf4: 2800 cmp r0, #0 +1000abf6: d061 beq.n 1000acbc +1000abf8: b5f8 push {r3, r4, r5, r6, r7, lr} +1000abfa: 4604 mov r4, r0 +1000abfc: 460d mov r5, r1 +1000abfe: 22b0 movs r2, #176 @ 0xb0 +1000ac00: 2100 movs r1, #0 +1000ac02: 3040 adds r0, #64 @ 0x40 +1000ac04: f001 f912 bl 1000be2c +1000ac08: 46a6 mov lr, r4 +1000ac0a: 4e2e ldr r6, [pc, #184] @ (1000acc4 ) +1000ac0c: f106 0740 add.w r7, r6, #64 @ 0x40 +1000ac10: 46b4 mov ip, r6 +1000ac12: f10e 0e10 add.w lr, lr, #16 +1000ac16: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} +1000ac1a: 45bc cmp ip, r7 +1000ac1c: f106 0610 add.w r6, r6, #16 +1000ac20: f84e 0c10 str.w r0, [lr, #-16] +1000ac24: f84e 1c0c str.w r1, [lr, #-12] +1000ac28: f84e 2c08 str.w r2, [lr, #-8] +1000ac2c: f84e 3c04 str.w r3, [lr, #-4] +1000ac30: d1ee bne.n 1000ac10 +1000ac32: 682b ldr r3, [r5, #0] +1000ac34: 4a24 ldr r2, [pc, #144] @ (1000acc8 ) +1000ac36: 6869 ldr r1, [r5, #4] +1000ac38: 405a eors r2, r3 +1000ac3a: 4b24 ldr r3, [pc, #144] @ (1000accc ) +1000ac3c: 6022 str r2, [r4, #0] +1000ac3e: 404b eors r3, r1 +1000ac40: 6063 str r3, [r4, #4] +1000ac42: 68ab ldr r3, [r5, #8] +1000ac44: 4a22 ldr r2, [pc, #136] @ (1000acd0 ) +1000ac46: 68e9 ldr r1, [r5, #12] +1000ac48: 405a eors r2, r3 +1000ac4a: 4b22 ldr r3, [pc, #136] @ (1000acd4 ) +1000ac4c: 60a2 str r2, [r4, #8] +1000ac4e: 404b eors r3, r1 +1000ac50: 60e3 str r3, [r4, #12] +1000ac52: 692b ldr r3, [r5, #16] +1000ac54: 4a20 ldr r2, [pc, #128] @ (1000acd8 ) +1000ac56: 6969 ldr r1, [r5, #20] +1000ac58: 405a eors r2, r3 +1000ac5a: 4b20 ldr r3, [pc, #128] @ (1000acdc ) +1000ac5c: 6122 str r2, [r4, #16] +1000ac5e: 404b eors r3, r1 +1000ac60: 6163 str r3, [r4, #20] +1000ac62: 69ab ldr r3, [r5, #24] +1000ac64: 4a1e ldr r2, [pc, #120] @ (1000ace0 ) +1000ac66: 69e9 ldr r1, [r5, #28] +1000ac68: 405a eors r2, r3 +1000ac6a: 4b1e ldr r3, [pc, #120] @ (1000ace4 ) +1000ac6c: 61a2 str r2, [r4, #24] +1000ac6e: 404b eors r3, r1 +1000ac70: 61e3 str r3, [r4, #28] +1000ac72: 6a2b ldr r3, [r5, #32] +1000ac74: 4a1c ldr r2, [pc, #112] @ (1000ace8 ) +1000ac76: 6a69 ldr r1, [r5, #36] @ 0x24 +1000ac78: 405a eors r2, r3 +1000ac7a: 4b1c ldr r3, [pc, #112] @ (1000acec ) +1000ac7c: 6222 str r2, [r4, #32] +1000ac7e: 404b eors r3, r1 +1000ac80: 6263 str r3, [r4, #36] @ 0x24 +1000ac82: 6aab ldr r3, [r5, #40] @ 0x28 +1000ac84: 4a1a ldr r2, [pc, #104] @ (1000acf0 ) +1000ac86: 6ae9 ldr r1, [r5, #44] @ 0x2c +1000ac88: 405a eors r2, r3 +1000ac8a: 4b1a ldr r3, [pc, #104] @ (1000acf4 ) +1000ac8c: 62a2 str r2, [r4, #40] @ 0x28 +1000ac8e: 404b eors r3, r1 +1000ac90: 62e3 str r3, [r4, #44] @ 0x2c +1000ac92: 6b2b ldr r3, [r5, #48] @ 0x30 +1000ac94: 4a18 ldr r2, [pc, #96] @ (1000acf8 ) +1000ac96: 6b69 ldr r1, [r5, #52] @ 0x34 +1000ac98: 405a eors r2, r3 +1000ac9a: 4b18 ldr r3, [pc, #96] @ (1000acfc ) +1000ac9c: 6322 str r2, [r4, #48] @ 0x30 +1000ac9e: 404b eors r3, r1 +1000aca0: 6363 str r3, [r4, #52] @ 0x34 +1000aca2: 6bab ldr r3, [r5, #56] @ 0x38 +1000aca4: 4a16 ldr r2, [pc, #88] @ (1000ad00 ) +1000aca6: 6be9 ldr r1, [r5, #60] @ 0x3c +1000aca8: 405a eors r2, r3 +1000acaa: 4b16 ldr r3, [pc, #88] @ (1000ad04 ) +1000acac: 63a2 str r2, [r4, #56] @ 0x38 +1000acae: 404b eors r3, r1 +1000acb0: 63e3 str r3, [r4, #60] @ 0x3c +1000acb2: 782b ldrb r3, [r5, #0] +1000acb4: 2000 movs r0, #0 +1000acb6: f8c4 30e4 str.w r3, [r4, #228] @ 0xe4 +1000acba: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000acbc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000acc0: 4770 bx lr +1000acc2: bf00 nop +1000acc4: 1000db80 .word 0x1000db80 +1000acc8: f3bcc908 .word 0xf3bcc908 +1000accc: 6a09e667 .word 0x6a09e667 +1000acd0: 84caa73b .word 0x84caa73b +1000acd4: bb67ae85 .word 0xbb67ae85 +1000acd8: fe94f82b .word 0xfe94f82b +1000acdc: 3c6ef372 .word 0x3c6ef372 +1000ace0: 5f1d36f1 .word 0x5f1d36f1 +1000ace4: a54ff53a .word 0xa54ff53a +1000ace8: ade682d1 .word 0xade682d1 +1000acec: 510e527f .word 0x510e527f +1000acf0: 2b3e6c1f .word 0x2b3e6c1f +1000acf4: 9b05688c .word 0x9b05688c +1000acf8: fb41bd6b .word 0xfb41bd6b +1000acfc: 1f83d9ab .word 0x1f83d9ab +1000ad00: 137e2179 .word 0x137e2179 +1000ad04: 5be0cd19 .word 0x5be0cd19 + +1000ad08 : +1000ad08: 2800 cmp r0, #0 +1000ad0a: d052 beq.n 1000adb2 +1000ad0c: b5f0 push {r4, r5, r6, r7, lr} +1000ad0e: 1e4b subs r3, r1, #1 +1000ad10: 2b3f cmp r3, #63 @ 0x3f +1000ad12: 4604 mov r4, r0 +1000ad14: 460e mov r6, r1 +1000ad16: b091 sub sp, #68 @ 0x44 +1000ad18: d836 bhi.n 1000ad88 +1000ad1a: 2100 movs r1, #0 +1000ad1c: f240 1301 movw r3, #257 @ 0x101 +1000ad20: 4d26 ldr r5, [pc, #152] @ (1000adbc ) +1000ad22: 22b0 movs r2, #176 @ 0xb0 +1000ad24: 3040 adds r0, #64 @ 0x40 +1000ad26: f88d 6000 strb.w r6, [sp] +1000ad2a: f88d 1001 strb.w r1, [sp, #1] +1000ad2e: f8ad 3002 strh.w r3, [sp, #2] +1000ad32: 9101 str r1, [sp, #4] +1000ad34: f105 0730 add.w r7, r5, #48 @ 0x30 +1000ad38: f001 f878 bl 1000be2c +1000ad3c: f104 0e08 add.w lr, r4, #8 +1000ad40: 46ac mov ip, r5 +1000ad42: f10e 0e10 add.w lr, lr, #16 +1000ad46: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} +1000ad4a: 45bc cmp ip, r7 +1000ad4c: f105 0510 add.w r5, r5, #16 +1000ad50: f84e 0c10 str.w r0, [lr, #-16] +1000ad54: f84e 1c0c str.w r1, [lr, #-12] +1000ad58: f84e 2c08 str.w r2, [lr, #-8] +1000ad5c: f84e 3c04 str.w r3, [lr, #-4] +1000ad60: d1ee bne.n 1000ad40 +1000ad62: e9dd 2100 ldrd r2, r1, [sp] +1000ad66: 2300 movs r3, #0 +1000ad68: 4f15 ldr r7, [pc, #84] @ (1000adc0 ) +1000ad6a: 4057 eors r7, r2 +1000ad6c: 4a15 ldr r2, [pc, #84] @ (1000adc4 ) +1000ad6e: 404a eors r2, r1 +1000ad70: cd03 ldmia r5!, {r0, r1} +1000ad72: f8ce 0000 str.w r0, [lr] +1000ad76: f8ce 1004 str.w r1, [lr, #4] +1000ad7a: e9c4 7200 strd r7, r2, [r4] +1000ad7e: f8c4 60e4 str.w r6, [r4, #228] @ 0xe4 +1000ad82: 4618 mov r0, r3 +1000ad84: b011 add sp, #68 @ 0x44 +1000ad86: bdf0 pop {r4, r5, r6, r7, pc} +1000ad88: 21f0 movs r1, #240 @ 0xf0 +1000ad8a: f7fd fd47 bl 1000881c +1000ad8e: f894 30e8 ldrb.w r3, [r4, #232] @ 0xe8 +1000ad92: b12b cbz r3, 1000ada0 +1000ad94: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000ad98: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000ad9c: e9c4 2316 strd r2, r3, [r4, #88] @ 0x58 +1000ada0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000ada4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000ada8: e9c4 2314 strd r2, r3, [r4, #80] @ 0x50 +1000adac: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000adb0: e7e7 b.n 1000ad82 +1000adb2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000adb6: 4618 mov r0, r3 +1000adb8: 4770 bx lr +1000adba: bf00 nop +1000adbc: 1000db88 .word 0x1000db88 +1000adc0: f3bcc908 .word 0xf3bcc908 +1000adc4: 6a09e667 .word 0x6a09e667 + +1000adc8 : +1000adc8: 2a00 cmp r2, #0 +1000adca: f000 809f beq.w 1000af0c +1000adce: 2800 cmp r0, #0 +1000add0: f000 8099 beq.w 1000af06 +1000add4: 460b mov r3, r1 +1000add6: 2900 cmp r1, #0 +1000add8: f000 8095 beq.w 1000af06 +1000addc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000ade0: 4615 mov r5, r2 +1000ade2: e9d0 2414 ldrd r2, r4, [r0, #80] @ 0x50 +1000ade6: 4322 orrs r2, r4 +1000ade8: b085 sub sp, #20 +1000adea: f040 8089 bne.w 1000af00 +1000adee: 4606 mov r6, r0 +1000adf0: f8d0 20e0 ldr.w r2, [r0, #224] @ 0xe0 +1000adf4: f102 0060 add.w r0, r2, #96 @ 0x60 +1000adf8: 1830 adds r0, r6, r0 +1000adfa: 9000 str r0, [sp, #0] +1000adfc: 1950 adds r0, r2, r5 +1000adfe: 2880 cmp r0, #128 @ 0x80 +1000ae00: 9001 str r0, [sp, #4] +1000ae02: d80d bhi.n 1000ae20 +1000ae04: 4619 mov r1, r3 +1000ae06: 462a mov r2, r5 +1000ae08: 9800 ldr r0, [sp, #0] +1000ae0a: f001 f8b7 bl 1000bf7c +1000ae0e: 2000 movs r0, #0 +1000ae10: f8d6 30e0 ldr.w r3, [r6, #224] @ 0xe0 +1000ae14: 442b add r3, r5 +1000ae16: f8c6 30e0 str.w r3, [r6, #224] @ 0xe0 +1000ae1a: b005 add sp, #20 +1000ae1c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000ae20: 2700 movs r7, #0 +1000ae22: f1c2 0580 rsb r5, r2, #128 @ 0x80 +1000ae26: 462a mov r2, r5 +1000ae28: 9800 ldr r0, [sp, #0] +1000ae2a: 9102 str r1, [sp, #8] +1000ae2c: f001 f8a6 bl 1000bf7c +1000ae30: e9d6 8910 ldrd r8, r9, [r6, #64] @ 0x40 +1000ae34: f118 0280 adds.w r2, r8, #128 @ 0x80 +1000ae38: 6432 str r2, [r6, #64] @ 0x40 +1000ae3a: f149 0200 adc.w r2, r9, #0 +1000ae3e: f118 0f80 cmn.w r8, #128 @ 0x80 +1000ae42: 6472 str r2, [r6, #68] @ 0x44 +1000ae44: f179 32ff sbcs.w r2, r9, #4294967295 @ 0xffffffff +1000ae48: bf2c ite cs +1000ae4a: 2401 movcs r4, #1 +1000ae4c: 463c movcc r4, r7 +1000ae4e: 6cb2 ldr r2, [r6, #72] @ 0x48 +1000ae50: f106 0360 add.w r3, r6, #96 @ 0x60 +1000ae54: 18a4 adds r4, r4, r2 +1000ae56: 6cf2 ldr r2, [r6, #76] @ 0x4c +1000ae58: 4619 mov r1, r3 +1000ae5a: f142 0b00 adc.w fp, r2, #0 +1000ae5e: 4630 mov r0, r6 +1000ae60: 64b4 str r4, [r6, #72] @ 0x48 +1000ae62: f8c6 b04c str.w fp, [r6, #76] @ 0x4c +1000ae66: 9300 str r3, [sp, #0] +1000ae68: f7ff fb14 bl 1000a494 +1000ae6c: 9b02 ldr r3, [sp, #8] +1000ae6e: 9a01 ldr r2, [sp, #4] +1000ae70: 442b add r3, r5 +1000ae72: f1a2 0580 sub.w r5, r2, #128 @ 0x80 +1000ae76: 2d80 cmp r5, #128 @ 0x80 +1000ae78: f8c6 70e0 str.w r7, [r6, #224] @ 0xe0 +1000ae7c: d9c2 bls.n 1000ae04 +1000ae7e: f46f 7080 mvn.w r0, #256 @ 0x100 +1000ae82: 4402 add r2, r0 +1000ae84: f518 7580 adds.w r5, r8, #256 @ 0x100 +1000ae88: ea4f 12d2 mov.w r2, r2, lsr #7 +1000ae8c: e9cd 2302 strd r2, r3, [sp, #8] +1000ae90: eba3 0a05 sub.w sl, r3, r5 +1000ae94: 4633 mov r3, r6 +1000ae96: f04f 0180 mov.w r1, #128 @ 0x80 +1000ae9a: 4626 mov r6, r4 +1000ae9c: 465c mov r4, fp +1000ae9e: 469b mov fp, r3 +1000aea0: f149 0700 adc.w r7, r9, #0 +1000aea4: f518 78c0 adds.w r8, r8, #384 @ 0x180 +1000aea8: f149 0900 adc.w r9, r9, #0 +1000aeac: fbe2 8901 umlal r8, r9, r2, r1 +1000aeb0: 2d80 cmp r5, #128 @ 0x80 +1000aeb2: f177 0300 sbcs.w r3, r7, #0 +1000aeb6: bf34 ite cc +1000aeb8: 2301 movcc r3, #1 +1000aeba: 2300 movcs r3, #0 +1000aebc: 199b adds r3, r3, r6 +1000aebe: f144 0400 adc.w r4, r4, #0 +1000aec2: e9cb 5710 strd r5, r7, [fp, #64] @ 0x40 +1000aec6: eb0a 0105 add.w r1, sl, r5 +1000aeca: 4658 mov r0, fp +1000aecc: f8cb 404c str.w r4, [fp, #76] @ 0x4c +1000aed0: f8cb 3048 str.w r3, [fp, #72] @ 0x48 +1000aed4: 461e mov r6, r3 +1000aed6: f7ff fadd bl 1000a494 +1000aeda: 3580 adds r5, #128 @ 0x80 +1000aedc: f147 0700 adc.w r7, r7, #0 +1000aee0: 454f cmp r7, r9 +1000aee2: bf08 it eq +1000aee4: 4545 cmpeq r5, r8 +1000aee6: d1e3 bne.n 1000aeb0 +1000aee8: e9dd 2302 ldrd r2, r3, [sp, #8] +1000aeec: 9901 ldr r1, [sp, #4] +1000aeee: 3380 adds r3, #128 @ 0x80 +1000aef0: f5a1 7180 sub.w r1, r1, #256 @ 0x100 +1000aef4: 465e mov r6, fp +1000aef6: eb03 13c2 add.w r3, r3, r2, lsl #7 +1000aefa: eba1 15c2 sub.w r5, r1, r2, lsl #7 +1000aefe: e781 b.n 1000ae04 +1000af00: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000af04: e789 b.n 1000ae1a +1000af06: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000af0a: 4770 bx lr +1000af0c: 2000 movs r0, #0 +1000af0e: 4770 bx lr + +1000af10 : +1000af10: 2800 cmp r0, #0 +1000af12: d078 beq.n 1000b006 +1000af14: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +1000af18: 461f mov r7, r3 +1000af1a: 1e4b subs r3, r1, #1 +1000af1c: 2b3f cmp r3, #63 @ 0x3f +1000af1e: 4604 mov r4, r0 +1000af20: 4690 mov r8, r2 +1000af22: 460e mov r6, r1 +1000af24: b0b1 sub sp, #196 @ 0xc4 +1000af26: d866 bhi.n 1000aff6 +1000af28: 2a00 cmp r2, #0 +1000af2a: d04e beq.n 1000afca +1000af2c: 1e7b subs r3, r7, #1 +1000af2e: 2b3f cmp r3, #63 @ 0x3f +1000af30: d84b bhi.n 1000afca +1000af32: f240 1301 movw r3, #257 @ 0x101 +1000af36: f88d 1000 strb.w r1, [sp] +1000af3a: 2100 movs r1, #0 +1000af3c: 4d33 ldr r5, [pc, #204] @ (1000b00c ) +1000af3e: 22b0 movs r2, #176 @ 0xb0 +1000af40: 3040 adds r0, #64 @ 0x40 +1000af42: f88d 7001 strb.w r7, [sp, #1] +1000af46: f8ad 3002 strh.w r3, [sp, #2] +1000af4a: 9101 str r1, [sp, #4] +1000af4c: f105 0930 add.w r9, r5, #48 @ 0x30 +1000af50: f000 ff6c bl 1000be2c +1000af54: f104 0e08 add.w lr, r4, #8 +1000af58: 46ac mov ip, r5 +1000af5a: f10e 0e10 add.w lr, lr, #16 +1000af5e: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} +1000af62: 45cc cmp ip, r9 +1000af64: f105 0510 add.w r5, r5, #16 +1000af68: f84e 0c10 str.w r0, [lr, #-16] +1000af6c: f84e 1c0c str.w r1, [lr, #-12] +1000af70: f84e 2c08 str.w r2, [lr, #-8] +1000af74: f84e 3c04 str.w r3, [lr, #-4] +1000af78: d1ee bne.n 1000af58 +1000af7a: e9dd 3200 ldrd r3, r2, [sp] +1000af7e: cd03 ldmia r5!, {r0, r1} +1000af80: f8df c090 ldr.w ip, [pc, #144] @ 1000b014 +1000af84: f8ce 0000 str.w r0, [lr] +1000af88: ea83 0c0c eor.w ip, r3, ip +1000af8c: 4b20 ldr r3, [pc, #128] @ (1000b010 ) +1000af8e: f8ce 1004 str.w r1, [lr, #4] +1000af92: 4053 eors r3, r2 +1000af94: e9c4 c300 strd ip, r3, [r4] +1000af98: 2280 movs r2, #128 @ 0x80 +1000af9a: 2100 movs r1, #0 +1000af9c: f8c4 60e4 str.w r6, [r4, #228] @ 0xe4 +1000afa0: a810 add r0, sp, #64 @ 0x40 +1000afa2: f000 ff43 bl 1000be2c +1000afa6: 463a mov r2, r7 +1000afa8: 4641 mov r1, r8 +1000afaa: a810 add r0, sp, #64 @ 0x40 +1000afac: f000 ffe6 bl 1000bf7c +1000afb0: 2280 movs r2, #128 @ 0x80 +1000afb2: a910 add r1, sp, #64 @ 0x40 +1000afb4: 4620 mov r0, r4 +1000afb6: f7ff ff07 bl 1000adc8 +1000afba: a810 add r0, sp, #64 @ 0x40 +1000afbc: 2180 movs r1, #128 @ 0x80 +1000afbe: f7fd fc2d bl 1000881c +1000afc2: 2000 movs r0, #0 +1000afc4: b031 add sp, #196 @ 0xc4 +1000afc6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +1000afca: 21f0 movs r1, #240 @ 0xf0 +1000afcc: 4620 mov r0, r4 +1000afce: f7fd fc25 bl 1000881c +1000afd2: f894 30e8 ldrb.w r3, [r4, #232] @ 0xe8 +1000afd6: b12b cbz r3, 1000afe4 +1000afd8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000afdc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000afe0: e9c4 2316 strd r2, r3, [r4, #88] @ 0x58 +1000afe4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000afe8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000afec: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000aff0: e9c4 2314 strd r2, r3, [r4, #80] @ 0x50 +1000aff4: e7e6 b.n 1000afc4 +1000aff6: 21f0 movs r1, #240 @ 0xf0 +1000aff8: f7fd fc10 bl 1000881c +1000affc: f894 30e8 ldrb.w r3, [r4, #232] @ 0xe8 +1000b000: 2b00 cmp r3, #0 +1000b002: d0ef beq.n 1000afe4 +1000b004: e7e8 b.n 1000afd8 +1000b006: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b00a: 4770 bx lr +1000b00c: 1000db88 .word 0x1000db88 +1000b010: 6a09e667 .word 0x6a09e667 +1000b014: f3bcc908 .word 0xf3bcc908 + +1000b018 : +1000b018: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000b01c: 4604 mov r4, r0 +1000b01e: b090 sub sp, #64 @ 0x40 +1000b020: 460d mov r5, r1 +1000b022: 4616 mov r6, r2 +1000b024: 2100 movs r1, #0 +1000b026: 2240 movs r2, #64 @ 0x40 +1000b028: 4668 mov r0, sp +1000b02a: f000 feff bl 1000be2c +1000b02e: 2c00 cmp r4, #0 +1000b030: d065 beq.n 1000b0fe +1000b032: 2d00 cmp r5, #0 +1000b034: d063 beq.n 1000b0fe +1000b036: f8d4 30e4 ldr.w r3, [r4, #228] @ 0xe4 +1000b03a: 42b3 cmp r3, r6 +1000b03c: d85f bhi.n 1000b0fe +1000b03e: e9d4 3214 ldrd r3, r2, [r4, #80] @ 0x50 +1000b042: 4313 orrs r3, r2 +1000b044: d15b bne.n 1000b0fe +1000b046: e9d4 1310 ldrd r1, r3, [r4, #64] @ 0x40 +1000b04a: f8d4 20e0 ldr.w r2, [r4, #224] @ 0xe0 +1000b04e: 2000 movs r0, #0 +1000b050: 1851 adds r1, r2, r1 +1000b052: f153 0300 adcs.w r3, r3, #0 +1000b056: bf28 it cs +1000b058: 2001 movcs r0, #1 +1000b05a: e9c4 1310 strd r1, r3, [r4, #64] @ 0x40 +1000b05e: 6ca3 ldr r3, [r4, #72] @ 0x48 +1000b060: f894 10e8 ldrb.w r1, [r4, #232] @ 0xe8 +1000b064: 181b adds r3, r3, r0 +1000b066: 64a3 str r3, [r4, #72] @ 0x48 +1000b068: 6ce3 ldr r3, [r4, #76] @ 0x4c +1000b06a: f143 0300 adc.w r3, r3, #0 +1000b06e: 64e3 str r3, [r4, #76] @ 0x4c +1000b070: bbf1 cbnz r1, 1000b0f0 +1000b072: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b076: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000b07a: e9c4 0114 strd r0, r1, [r4, #80] @ 0x50 +1000b07e: f102 0060 add.w r0, r2, #96 @ 0x60 +1000b082: 2100 movs r1, #0 +1000b084: f1c2 0280 rsb r2, r2, #128 @ 0x80 +1000b088: 4420 add r0, r4 +1000b08a: f104 0760 add.w r7, r4, #96 @ 0x60 +1000b08e: f000 fecd bl 1000be2c +1000b092: 4639 mov r1, r7 +1000b094: 4620 mov r0, r4 +1000b096: f7ff f9fd bl 1000a494 +1000b09a: 466e mov r6, sp +1000b09c: 46a4 mov ip, r4 +1000b09e: f104 0840 add.w r8, r4, #64 @ 0x40 +1000b0a2: 46b6 mov lr, r6 +1000b0a4: f8dc 0000 ldr.w r0, [ip] +1000b0a8: f8dc 1004 ldr.w r1, [ip, #4] +1000b0ac: f8dc 2008 ldr.w r2, [ip, #8] +1000b0b0: f8dc 300c ldr.w r3, [ip, #12] +1000b0b4: f10c 0c10 add.w ip, ip, #16 +1000b0b8: 45c4 cmp ip, r8 +1000b0ba: e8ae 000f stmia.w lr!, {r0, r1, r2, r3} +1000b0be: f106 0610 add.w r6, r6, #16 +1000b0c2: d1ee bne.n 1000b0a2 +1000b0c4: f8d4 20e4 ldr.w r2, [r4, #228] @ 0xe4 +1000b0c8: 4669 mov r1, sp +1000b0ca: 4628 mov r0, r5 +1000b0cc: f000 ff56 bl 1000bf7c +1000b0d0: 2140 movs r1, #64 @ 0x40 +1000b0d2: 4668 mov r0, sp +1000b0d4: f7fd fba2 bl 1000881c +1000b0d8: 2180 movs r1, #128 @ 0x80 +1000b0da: 4638 mov r0, r7 +1000b0dc: f7fd fb9e bl 1000881c +1000b0e0: 4620 mov r0, r4 +1000b0e2: 2140 movs r1, #64 @ 0x40 +1000b0e4: f7fd fb9a bl 1000881c +1000b0e8: 2000 movs r0, #0 +1000b0ea: b010 add sp, #64 @ 0x40 +1000b0ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000b0f0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b0f4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000b0f8: e9c4 0116 strd r0, r1, [r4, #88] @ 0x58 +1000b0fc: e7b9 b.n 1000b072 +1000b0fe: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b102: e7f2 b.n 1000b0ea + +1000b104 : +1000b104: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000b108: 4617 mov r7, r2 +1000b10a: b0cc sub sp, #304 @ 0x130 +1000b10c: 4698 mov r8, r3 +1000b10e: e9dd 2352 ldrd r2, r3, [sp, #328] @ 0x148 +1000b112: 4605 mov r5, r0 +1000b114: 460e mov r6, r1 +1000b116: 2f00 cmp r7, #0 +1000b118: d07d beq.n 1000b216 +1000b11a: 2d00 cmp r5, #0 +1000b11c: d07f beq.n 1000b21e +1000b11e: 1e71 subs r1, r6, #1 +1000b120: 293f cmp r1, #63 @ 0x3f +1000b122: d87c bhi.n 1000b21e +1000b124: 2a00 cmp r2, #0 +1000b126: d07e beq.n 1000b226 +1000b128: 2b40 cmp r3, #64 @ 0x40 +1000b12a: d878 bhi.n 1000b21e +1000b12c: 2b00 cmp r3, #0 +1000b12e: d07c beq.n 1000b22a +1000b130: ac10 add r4, sp, #64 @ 0x40 +1000b132: 4631 mov r1, r6 +1000b134: 4620 mov r0, r4 +1000b136: f7ff feeb bl 1000af10 +1000b13a: 3001 adds r0, #1 +1000b13c: d070 beq.n 1000b220 +1000b13e: 4642 mov r2, r8 +1000b140: 4639 mov r1, r7 +1000b142: 4620 mov r0, r4 +1000b144: f7ff fe40 bl 1000adc8 +1000b148: 3001 adds r0, #1 +1000b14a: d069 beq.n 1000b220 +1000b14c: 2240 movs r2, #64 @ 0x40 +1000b14e: 2100 movs r1, #0 +1000b150: 4668 mov r0, sp +1000b152: f000 fe6b bl 1000be2c +1000b156: 9b49 ldr r3, [sp, #292] @ 0x124 +1000b158: 429e cmp r6, r3 +1000b15a: d361 bcc.n 1000b220 +1000b15c: e9dd 3224 ldrd r3, r2, [sp, #144] @ 0x90 +1000b160: 4313 orrs r3, r2 +1000b162: d15d bne.n 1000b220 +1000b164: e9dd 1320 ldrd r1, r3, [sp, #128] @ 0x80 +1000b168: 9a48 ldr r2, [sp, #288] @ 0x120 +1000b16a: 2000 movs r0, #0 +1000b16c: 1851 adds r1, r2, r1 +1000b16e: f153 0300 adcs.w r3, r3, #0 +1000b172: bf28 it cs +1000b174: 2001 movcs r0, #1 +1000b176: e9cd 1320 strd r1, r3, [sp, #128] @ 0x80 +1000b17a: 9b22 ldr r3, [sp, #136] @ 0x88 +1000b17c: f89d 1128 ldrb.w r1, [sp, #296] @ 0x128 +1000b180: 181b adds r3, r3, r0 +1000b182: 9322 str r3, [sp, #136] @ 0x88 +1000b184: 9b23 ldr r3, [sp, #140] @ 0x8c +1000b186: f143 0300 adc.w r3, r3, #0 +1000b18a: 9323 str r3, [sp, #140] @ 0x8c +1000b18c: b129 cbz r1, 1000b19a +1000b18e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b192: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000b196: e9cd 0126 strd r0, r1, [sp, #152] @ 0x98 +1000b19a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000b19e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000b1a2: e9cd 0124 strd r0, r1, [sp, #144] @ 0x90 +1000b1a6: f102 0060 add.w r0, r2, #96 @ 0x60 +1000b1aa: 2100 movs r1, #0 +1000b1ac: f1c2 0280 rsb r2, r2, #128 @ 0x80 +1000b1b0: 4420 add r0, r4 +1000b1b2: f000 fe3b bl 1000be2c +1000b1b6: 4620 mov r0, r4 +1000b1b8: a928 add r1, sp, #160 @ 0xa0 +1000b1ba: f7ff f96b bl 1000a494 +1000b1be: 46ec mov ip, sp +1000b1c0: 46a6 mov lr, r4 +1000b1c2: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b1c6: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +1000b1ca: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b1ce: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +1000b1d2: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b1d6: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +1000b1da: e89e 000f ldmia.w lr, {r0, r1, r2, r3} +1000b1de: e88c 000f stmia.w ip, {r0, r1, r2, r3} +1000b1e2: 9a49 ldr r2, [sp, #292] @ 0x124 +1000b1e4: 4628 mov r0, r5 +1000b1e6: 4669 mov r1, sp +1000b1e8: f000 fec8 bl 1000bf7c +1000b1ec: 2140 movs r1, #64 @ 0x40 +1000b1ee: 4668 mov r0, sp +1000b1f0: f7fd fb14 bl 1000881c +1000b1f4: 2180 movs r1, #128 @ 0x80 +1000b1f6: a828 add r0, sp, #160 @ 0xa0 +1000b1f8: f7fd fb10 bl 1000881c +1000b1fc: 2140 movs r1, #64 @ 0x40 +1000b1fe: 4620 mov r0, r4 +1000b200: f7fd fb0c bl 1000881c +1000b204: 2500 movs r5, #0 +1000b206: 4620 mov r0, r4 +1000b208: 21f0 movs r1, #240 @ 0xf0 +1000b20a: f7fd fb07 bl 1000881c +1000b20e: 4628 mov r0, r5 +1000b210: b04c add sp, #304 @ 0x130 +1000b212: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000b216: f1b8 0f00 cmp.w r8, #0 +1000b21a: f43f af7e beq.w 1000b11a +1000b21e: ac10 add r4, sp, #64 @ 0x40 +1000b220: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000b224: e7ef b.n 1000b206 +1000b226: 2b00 cmp r3, #0 +1000b228: d1f9 bne.n 1000b21e +1000b22a: ac10 add r4, sp, #64 @ 0x40 +1000b22c: 4631 mov r1, r6 +1000b22e: 4620 mov r0, r4 +1000b230: f7ff fd6a bl 1000ad08 +1000b234: 3001 adds r0, #1 +1000b236: d182 bne.n 1000b13e +1000b238: e7f2 b.n 1000b220 +1000b23a: bf00 nop + +1000b23c : +1000b23c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000b240: f5ad 7d35 sub.w sp, sp, #724 @ 0x2d4 +1000b244: 2940 cmp r1, #64 @ 0x40 +1000b246: af0b add r7, sp, #44 @ 0x2c +1000b248: 460e mov r6, r1 +1000b24a: e9cd 2303 strd r2, r3, [sp, #12] +1000b24e: 9005 str r0, [sp, #20] +1000b250: ac3c add r4, sp, #240 @ 0xf0 +1000b252: 6039 str r1, [r7, #0] +1000b254: d831 bhi.n 1000b2ba +1000b256: 4620 mov r0, r4 +1000b258: f7ff fd56 bl 1000ad08 +1000b25c: 3001 adds r0, #1 +1000b25e: f000 8198 beq.w 1000b592 +1000b262: e9d4 3214 ldrd r3, r2, [r4, #80] @ 0x50 +1000b266: 4313 orrs r3, r2 +1000b268: f040 8193 bne.w 1000b592 +1000b26c: f8d4 90e0 ldr.w r9, [r4, #224] @ 0xe0 +1000b270: f109 0304 add.w r3, r9, #4 +1000b274: 2b80 cmp r3, #128 @ 0x80 +1000b276: f109 0060 add.w r0, r9, #96 @ 0x60 +1000b27a: f200 8195 bhi.w 1000b5a8 +1000b27e: 4639 mov r1, r7 +1000b280: 2704 movs r7, #4 +1000b282: 463a mov r2, r7 +1000b284: 4420 add r0, r4 +1000b286: f000 fe79 bl 1000bf7c +1000b28a: e9dd 1203 ldrd r1, r2, [sp, #12] +1000b28e: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 +1000b292: 4620 mov r0, r4 +1000b294: 443b add r3, r7 +1000b296: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +1000b29a: f7ff fd95 bl 1000adc8 +1000b29e: 3001 adds r0, #1 +1000b2a0: f000 8177 beq.w 1000b592 +1000b2a4: 4632 mov r2, r6 +1000b2a6: 4620 mov r0, r4 +1000b2a8: 9905 ldr r1, [sp, #20] +1000b2aa: f7ff feb5 bl 1000b018 +1000b2ae: 3001 adds r0, #1 +1000b2b0: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000b2b4: bf18 it ne +1000b2b6: 2500 movne r5, #0 +1000b2b8: e16d b.n 1000b596 +1000b2ba: 2140 movs r1, #64 @ 0x40 +1000b2bc: 4620 mov r0, r4 +1000b2be: f7ff fd23 bl 1000ad08 +1000b2c2: 3001 adds r0, #1 +1000b2c4: f000 8165 beq.w 1000b592 +1000b2c8: e9d4 3214 ldrd r3, r2, [r4, #80] @ 0x50 +1000b2cc: 4313 orrs r3, r2 +1000b2ce: f040 8160 bne.w 1000b592 +1000b2d2: f8d4 90e0 ldr.w r9, [r4, #224] @ 0xe0 +1000b2d6: f109 0304 add.w r3, r9, #4 +1000b2da: 2b80 cmp r3, #128 @ 0x80 +1000b2dc: f109 0060 add.w r0, r9, #96 @ 0x60 +1000b2e0: f200 81d6 bhi.w 1000b690 +1000b2e4: 4639 mov r1, r7 +1000b2e6: 2704 movs r7, #4 +1000b2e8: 463a mov r2, r7 +1000b2ea: 4420 add r0, r4 +1000b2ec: f000 fe46 bl 1000bf7c +1000b2f0: e9dd 1203 ldrd r1, r2, [sp, #12] +1000b2f4: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 +1000b2f8: 4620 mov r0, r4 +1000b2fa: 443b add r3, r7 +1000b2fc: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 +1000b300: f7ff fd62 bl 1000adc8 +1000b304: 3001 adds r0, #1 +1000b306: f000 8144 beq.w 1000b592 +1000b30a: 2240 movs r2, #64 @ 0x40 +1000b30c: 4620 mov r0, r4 +1000b30e: a91c add r1, sp, #112 @ 0x70 +1000b310: f7ff fe82 bl 1000b018 +1000b314: 3001 adds r0, #1 +1000b316: f000 813c beq.w 1000b592 +1000b31a: f1a6 0320 sub.w r3, r6, #32 +1000b31e: 9e05 ldr r6, [sp, #20] +1000b320: 9304 str r3, [sp, #16] +1000b322: ad1c add r5, sp, #112 @ 0x70 +1000b324: cd0f ldmia r5!, {r0, r1, r2, r3} +1000b326: 6030 str r0, [r6, #0] +1000b328: 6071 str r1, [r6, #4] +1000b32a: 60b2 str r2, [r6, #8] +1000b32c: 60f3 str r3, [r6, #12] +1000b32e: cd0f ldmia r5!, {r0, r1, r2, r3} +1000b330: 61f3 str r3, [r6, #28] +1000b332: 9b04 ldr r3, [sp, #16] +1000b334: f106 0720 add.w r7, r6, #32 +1000b338: 2b40 cmp r3, #64 @ 0x40 +1000b33a: 6130 str r0, [r6, #16] +1000b33c: 6171 str r1, [r6, #20] +1000b33e: 61b2 str r2, [r6, #24] +1000b340: f10d 0cb0 add.w ip, sp, #176 @ 0xb0 +1000b344: f240 8219 bls.w 1000b77a +1000b348: f50d 7af0 add.w sl, sp, #480 @ 0x1e0 +1000b34c: f8cd c00c str.w ip, [sp, #12] +1000b350: 9409 str r4, [sp, #36] @ 0x24 +1000b352: e093 b.n 1000b47c +1000b354: 2540 movs r5, #64 @ 0x40 +1000b356: 9903 ldr r1, [sp, #12] +1000b358: 462a mov r2, r5 +1000b35a: 4450 add r0, sl +1000b35c: f000 fe0e bl 1000bf7c +1000b360: 9cb0 ldr r4, [sp, #704] @ 0x2c0 +1000b362: 2240 movs r2, #64 @ 0x40 +1000b364: 2100 movs r1, #0 +1000b366: 442c add r4, r5 +1000b368: a80c add r0, sp, #48 @ 0x30 +1000b36a: 94b0 str r4, [sp, #704] @ 0x2c0 +1000b36c: f000 fd5e bl 1000be2c +1000b370: 9bb1 ldr r3, [sp, #708] @ 0x2c4 +1000b372: 2b40 cmp r3, #64 @ 0x40 +1000b374: f200 8108 bhi.w 1000b588 +1000b378: e9dd 328c ldrd r3, r2, [sp, #560] @ 0x230 +1000b37c: 4313 orrs r3, r2 +1000b37e: f040 8103 bne.w 1000b588 +1000b382: e9dd 2388 ldrd r2, r3, [sp, #544] @ 0x220 +1000b386: 18a2 adds r2, r4, r2 +1000b388: f153 0300 adcs.w r3, r3, #0 +1000b38c: f04f 0100 mov.w r1, #0 +1000b390: bf28 it cs +1000b392: 2101 movcs r1, #1 +1000b394: e9cd 2388 strd r2, r3, [sp, #544] @ 0x220 +1000b398: 9b8a ldr r3, [sp, #552] @ 0x228 +1000b39a: 185b adds r3, r3, r1 +1000b39c: 938a str r3, [sp, #552] @ 0x228 +1000b39e: 9b8b ldr r3, [sp, #556] @ 0x22c +1000b3a0: f143 0300 adc.w r3, r3, #0 +1000b3a4: 938b str r3, [sp, #556] @ 0x22c +1000b3a6: f89d 32c8 ldrb.w r3, [sp, #712] @ 0x2c8 +1000b3aa: b12b cbz r3, 1000b3b8 +1000b3ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000b3b0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000b3b4: e9cd 238e strd r2, r3, [sp, #568] @ 0x238 +1000b3b8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +1000b3bc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000b3c0: f104 0060 add.w r0, r4, #96 @ 0x60 +1000b3c4: e9cd 238c strd r2, r3, [sp, #560] @ 0x230 +1000b3c8: 2100 movs r1, #0 +1000b3ca: f1c4 0280 rsb r2, r4, #128 @ 0x80 +1000b3ce: 4450 add r0, sl +1000b3d0: f000 fd2c bl 1000be2c +1000b3d4: 4650 mov r0, sl +1000b3d6: a990 add r1, sp, #576 @ 0x240 +1000b3d8: f7ff f85c bl 1000a494 +1000b3dc: e9dd 457a ldrd r4, r5, [sp, #488] @ 0x1e8 +1000b3e0: 9ab1 ldr r2, [sp, #708] @ 0x2c4 +1000b3e2: a90c add r1, sp, #48 @ 0x30 +1000b3e4: a81c add r0, sp, #112 @ 0x70 +1000b3e6: e9cd 450e strd r4, r5, [sp, #56] @ 0x38 +1000b3ea: e9dd 457c ldrd r4, r5, [sp, #496] @ 0x1f0 +1000b3ee: e9cd 4510 strd r4, r5, [sp, #64] @ 0x40 +1000b3f2: e9dd 457e ldrd r4, r5, [sp, #504] @ 0x1f8 +1000b3f6: e9cd 4512 strd r4, r5, [sp, #72] @ 0x48 +1000b3fa: e9dd 4580 ldrd r4, r5, [sp, #512] @ 0x200 +1000b3fe: e9cd 4514 strd r4, r5, [sp, #80] @ 0x50 +1000b402: e9dd 4582 ldrd r4, r5, [sp, #520] @ 0x208 +1000b406: e9cd 4516 strd r4, r5, [sp, #88] @ 0x58 +1000b40a: e9dd 4584 ldrd r4, r5, [sp, #528] @ 0x210 +1000b40e: e9cd 4518 strd r4, r5, [sp, #96] @ 0x60 +1000b412: e9dd 4586 ldrd r4, r5, [sp, #536] @ 0x218 +1000b416: e9cd 451a strd r4, r5, [sp, #104] @ 0x68 +1000b41a: e9dd 4578 ldrd r4, r5, [sp, #480] @ 0x1e0 +1000b41e: e9cd 450c strd r4, r5, [sp, #48] @ 0x30 +1000b422: f000 fdab bl 1000bf7c +1000b426: 2140 movs r1, #64 @ 0x40 +1000b428: a80c add r0, sp, #48 @ 0x30 +1000b42a: f7fd f9f7 bl 1000881c +1000b42e: 2180 movs r1, #128 @ 0x80 +1000b430: a890 add r0, sp, #576 @ 0x240 +1000b432: f7fd f9f3 bl 1000881c +1000b436: 2140 movs r1, #64 @ 0x40 +1000b438: 4650 mov r0, sl +1000b43a: f7fd f9ef bl 1000881c +1000b43e: 21f0 movs r1, #240 @ 0xf0 +1000b440: 4650 mov r0, sl +1000b442: f7fd f9eb bl 1000881c +1000b446: 9b04 ldr r3, [sp, #16] +1000b448: 3720 adds r7, #32 +1000b44a: f1a3 0520 sub.w r5, r3, #32 +1000b44e: ac1c add r4, sp, #112 @ 0x70 +1000b450: 2d40 cmp r5, #64 @ 0x40 +1000b452: cc0f ldmia r4!, {r0, r1, r2, r3} +1000b454: 9504 str r5, [sp, #16] +1000b456: f847 0c20 str.w r0, [r7, #-32] +1000b45a: f847 1c1c str.w r1, [r7, #-28] +1000b45e: f847 2c18 str.w r2, [r7, #-24] +1000b462: f847 3c14 str.w r3, [r7, #-20] +1000b466: cc0f ldmia r4!, {r0, r1, r2, r3} +1000b468: f847 0c10 str.w r0, [r7, #-16] +1000b46c: f847 1c0c str.w r1, [r7, #-12] +1000b470: f847 2c08 str.w r2, [r7, #-8] +1000b474: f847 3c04 str.w r3, [r7, #-4] +1000b478: f240 817c bls.w 1000b774 +1000b47c: 9c03 ldr r4, [sp, #12] +1000b47e: ad1c add r5, sp, #112 @ 0x70 +1000b480: cd0f ldmia r5!, {r0, r1, r2, r3} +1000b482: c40f stmia r4!, {r0, r1, r2, r3} +1000b484: cd0f ldmia r5!, {r0, r1, r2, r3} +1000b486: c40f stmia r4!, {r0, r1, r2, r3} +1000b488: cd0f ldmia r5!, {r0, r1, r2, r3} +1000b48a: c40f stmia r4!, {r0, r1, r2, r3} +1000b48c: e895 000f ldmia.w r5, {r0, r1, r2, r3} +1000b490: e884 000f stmia.w r4, {r0, r1, r2, r3} +1000b494: 2140 movs r1, #64 @ 0x40 +1000b496: 4650 mov r0, sl +1000b498: f7ff fc36 bl 1000ad08 +1000b49c: 3001 adds r0, #1 +1000b49e: d073 beq.n 1000b588 +1000b4a0: e9dd 328c ldrd r3, r2, [sp, #560] @ 0x230 +1000b4a4: 4313 orrs r3, r2 +1000b4a6: d16f bne.n 1000b588 +1000b4a8: 9bb0 ldr r3, [sp, #704] @ 0x2c0 +1000b4aa: f103 0240 add.w r2, r3, #64 @ 0x40 +1000b4ae: 2a80 cmp r2, #128 @ 0x80 +1000b4b0: f103 0060 add.w r0, r3, #96 @ 0x60 +1000b4b4: f67f af4e bls.w 1000b354 +1000b4b8: 2600 movs r6, #0 +1000b4ba: f1c3 0580 rsb r5, r3, #128 @ 0x80 +1000b4be: 462a mov r2, r5 +1000b4c0: 9903 ldr r1, [sp, #12] +1000b4c2: 4450 add r0, sl +1000b4c4: 9305 str r3, [sp, #20] +1000b4c6: f000 fd59 bl 1000bf7c +1000b4ca: e9dd 8988 ldrd r8, r9, [sp, #544] @ 0x220 +1000b4ce: f118 0280 adds.w r2, r8, #128 @ 0x80 +1000b4d2: 9288 str r2, [sp, #544] @ 0x220 +1000b4d4: f149 0200 adc.w r2, r9, #0 +1000b4d8: f118 0f80 cmn.w r8, #128 @ 0x80 +1000b4dc: 9289 str r2, [sp, #548] @ 0x224 +1000b4de: f179 32ff sbcs.w r2, r9, #4294967295 @ 0xffffffff +1000b4e2: bf2c ite cs +1000b4e4: 2401 movcs r4, #1 +1000b4e6: 4634 movcc r4, r6 +1000b4e8: 9a8a ldr r2, [sp, #552] @ 0x228 +1000b4ea: a990 add r1, sp, #576 @ 0x240 +1000b4ec: 18a4 adds r4, r4, r2 +1000b4ee: 9a8b ldr r2, [sp, #556] @ 0x22c +1000b4f0: 4650 mov r0, sl +1000b4f2: f142 0b00 adc.w fp, r2, #0 +1000b4f6: 948a str r4, [sp, #552] @ 0x228 +1000b4f8: f8cd b22c str.w fp, [sp, #556] @ 0x22c +1000b4fc: f7fe ffca bl 1000a494 +1000b500: 9b03 ldr r3, [sp, #12] +1000b502: 96b0 str r6, [sp, #704] @ 0x2c0 +1000b504: 1959 adds r1, r3, r5 +1000b506: 9b05 ldr r3, [sp, #20] +1000b508: f1a3 0540 sub.w r5, r3, #64 @ 0x40 +1000b50c: 2d80 cmp r5, #128 @ 0x80 +1000b50e: f240 8157 bls.w 1000b7c0 +1000b512: f04f 0c80 mov.w ip, #128 @ 0x80 +1000b516: f518 7580 adds.w r5, r8, #256 @ 0x100 +1000b51a: f149 0600 adc.w r6, r9, #0 +1000b51e: f1a3 00c1 sub.w r0, r3, #193 @ 0xc1 +1000b522: f518 78c0 adds.w r8, r8, #384 @ 0x180 +1000b526: ea4f 10d0 mov.w r0, r0, lsr #7 +1000b52a: f149 0900 adc.w r9, r9, #0 +1000b52e: fbe0 890c umlal r8, r9, r0, ip +1000b532: e9cd 3007 strd r3, r0, [sp, #28] +1000b536: e9cd 7105 strd r7, r1, [sp, #20] +1000b53a: 1b4f subs r7, r1, r5 +1000b53c: 2d80 cmp r5, #128 @ 0x80 +1000b53e: f176 0100 sbcs.w r1, r6, #0 +1000b542: bf34 ite cc +1000b544: 2101 movcc r1, #1 +1000b546: 2100 movcs r1, #0 +1000b548: 1909 adds r1, r1, r4 +1000b54a: 460c mov r4, r1 +1000b54c: f14b 0b00 adc.w fp, fp, #0 +1000b550: 1979 adds r1, r7, r5 +1000b552: 4650 mov r0, sl +1000b554: e9cd 5688 strd r5, r6, [sp, #544] @ 0x220 +1000b558: f8cd b22c str.w fp, [sp, #556] @ 0x22c +1000b55c: 948a str r4, [sp, #552] @ 0x228 +1000b55e: f7fe ff99 bl 1000a494 +1000b562: 3580 adds r5, #128 @ 0x80 +1000b564: f146 0600 adc.w r6, r6, #0 +1000b568: 454e cmp r6, r9 +1000b56a: bf08 it eq +1000b56c: 4545 cmpeq r5, r8 +1000b56e: d1e5 bne.n 1000b53c +1000b570: e9dd 3007 ldrd r3, r0, [sp, #28] +1000b574: e9dd 7105 ldrd r7, r1, [sp, #20] +1000b578: 3bc0 subs r3, #192 @ 0xc0 +1000b57a: eb01 11c0 add.w r1, r1, r0, lsl #7 +1000b57e: eba3 15c0 sub.w r5, r3, r0, lsl #7 +1000b582: 3180 adds r1, #128 @ 0x80 +1000b584: 2060 movs r0, #96 @ 0x60 +1000b586: e6e7 b.n 1000b358 +1000b588: 21f0 movs r1, #240 @ 0xf0 +1000b58a: 4650 mov r0, sl +1000b58c: 9c09 ldr r4, [sp, #36] @ 0x24 +1000b58e: f7fd f945 bl 1000881c +1000b592: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000b596: 4620 mov r0, r4 +1000b598: 21f0 movs r1, #240 @ 0xf0 +1000b59a: f7fd f93f bl 1000881c +1000b59e: 4628 mov r0, r5 +1000b5a0: f50d 7d35 add.w sp, sp, #724 @ 0x2d4 +1000b5a4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000b5a8: f1c9 0a80 rsb sl, r9, #128 @ 0x80 +1000b5ac: 4652 mov r2, sl +1000b5ae: 4639 mov r1, r7 +1000b5b0: 4420 add r0, r4 +1000b5b2: f000 fce3 bl 1000bf7c +1000b5b6: e9d4 b310 ldrd fp, r3, [r4, #64] @ 0x40 +1000b5ba: f11b 0180 adds.w r1, fp, #128 @ 0x80 +1000b5be: 6421 str r1, [r4, #64] @ 0x40 +1000b5c0: f143 0100 adc.w r1, r3, #0 +1000b5c4: f11b 0f80 cmn.w fp, #128 @ 0x80 +1000b5c8: 6461 str r1, [r4, #68] @ 0x44 +1000b5ca: f173 31ff sbcs.w r1, r3, #4294967295 @ 0xffffffff +1000b5ce: bf2c ite cs +1000b5d0: 2501 movcs r5, #1 +1000b5d2: 2500 movcc r5, #0 +1000b5d4: 6ca1 ldr r1, [r4, #72] @ 0x48 +1000b5d6: 4620 mov r0, r4 +1000b5d8: 186d adds r5, r5, r1 +1000b5da: 6ce1 ldr r1, [r4, #76] @ 0x4c +1000b5dc: 9306 str r3, [sp, #24] +1000b5de: f141 0800 adc.w r8, r1, #0 +1000b5e2: a954 add r1, sp, #336 @ 0x150 +1000b5e4: 64a5 str r5, [r4, #72] @ 0x48 +1000b5e6: f8c4 804c str.w r8, [r4, #76] @ 0x4c +1000b5ea: f7fe ff53 bl 1000a494 +1000b5ee: 2200 movs r2, #0 +1000b5f0: eb07 010a add.w r1, r7, sl +1000b5f4: f1a9 077c sub.w r7, r9, #124 @ 0x7c +1000b5f8: 2f80 cmp r7, #128 @ 0x80 +1000b5fa: f8c4 20e0 str.w r2, [r4, #224] @ 0xe0 +1000b5fe: f240 80e3 bls.w 1000b7c8 +1000b602: 2280 movs r2, #128 @ 0x80 +1000b604: 9b06 ldr r3, [sp, #24] +1000b606: f51b 7780 adds.w r7, fp, #256 @ 0x100 +1000b60a: f143 0a00 adc.w sl, r3, #0 +1000b60e: f1a9 00fd sub.w r0, r9, #253 @ 0xfd +1000b612: f51b 7bc0 adds.w fp, fp, #384 @ 0x180 +1000b616: ea4f 10d0 mov.w r0, r0, lsr #7 +1000b61a: f143 0300 adc.w r3, r3, #0 +1000b61e: fbe0 b302 umlal fp, r3, r0, r2 +1000b622: e9cd 0906 strd r0, r9, [sp, #24] +1000b626: 46a1 mov r9, r4 +1000b628: 462c mov r4, r5 +1000b62a: 4655 mov r5, sl +1000b62c: 469a mov sl, r3 +1000b62e: 9609 str r6, [sp, #36] @ 0x24 +1000b630: 9108 str r1, [sp, #32] +1000b632: 4646 mov r6, r8 +1000b634: eba1 0807 sub.w r8, r1, r7 +1000b638: 2f80 cmp r7, #128 @ 0x80 +1000b63a: f175 0100 sbcs.w r1, r5, #0 +1000b63e: bf34 ite cc +1000b640: 2101 movcc r1, #1 +1000b642: 2100 movcs r1, #0 +1000b644: 1909 adds r1, r1, r4 +1000b646: 460c mov r4, r1 +1000b648: f146 0600 adc.w r6, r6, #0 +1000b64c: eb08 0107 add.w r1, r8, r7 +1000b650: 4648 mov r0, r9 +1000b652: e9c9 7510 strd r7, r5, [r9, #64] @ 0x40 +1000b656: f8c9 604c str.w r6, [r9, #76] @ 0x4c +1000b65a: f8c9 4048 str.w r4, [r9, #72] @ 0x48 +1000b65e: f7fe ff19 bl 1000a494 +1000b662: 3780 adds r7, #128 @ 0x80 +1000b664: f145 0500 adc.w r5, r5, #0 +1000b668: 45aa cmp sl, r5 +1000b66a: bf08 it eq +1000b66c: 45bb cmpeq fp, r7 +1000b66e: d1e3 bne.n 1000b638 +1000b670: 9806 ldr r0, [sp, #24] +1000b672: 9908 ldr r1, [sp, #32] +1000b674: 464c mov r4, r9 +1000b676: f8dd 901c ldr.w r9, [sp, #28] +1000b67a: eb01 1ac0 add.w sl, r1, r0, lsl #7 +1000b67e: f1a9 09fc sub.w r9, r9, #252 @ 0xfc +1000b682: eba9 17c0 sub.w r7, r9, r0, lsl #7 +1000b686: 9e09 ldr r6, [sp, #36] @ 0x24 +1000b688: 2060 movs r0, #96 @ 0x60 +1000b68a: f10a 0180 add.w r1, sl, #128 @ 0x80 +1000b68e: e5f8 b.n 1000b282 +1000b690: f1c9 0a80 rsb sl, r9, #128 @ 0x80 +1000b694: 4652 mov r2, sl +1000b696: 4639 mov r1, r7 +1000b698: 4420 add r0, r4 +1000b69a: f000 fc6f bl 1000bf7c +1000b69e: e9d4 b310 ldrd fp, r3, [r4, #64] @ 0x40 +1000b6a2: f11b 0180 adds.w r1, fp, #128 @ 0x80 +1000b6a6: 6421 str r1, [r4, #64] @ 0x40 +1000b6a8: f143 0100 adc.w r1, r3, #0 +1000b6ac: f11b 0f80 cmn.w fp, #128 @ 0x80 +1000b6b0: 6461 str r1, [r4, #68] @ 0x44 +1000b6b2: f173 31ff sbcs.w r1, r3, #4294967295 @ 0xffffffff +1000b6b6: bf2c ite cs +1000b6b8: 2501 movcs r5, #1 +1000b6ba: 2500 movcc r5, #0 +1000b6bc: 6ca1 ldr r1, [r4, #72] @ 0x48 +1000b6be: 4620 mov r0, r4 +1000b6c0: 186d adds r5, r5, r1 +1000b6c2: 6ce1 ldr r1, [r4, #76] @ 0x4c +1000b6c4: 9306 str r3, [sp, #24] +1000b6c6: f141 0800 adc.w r8, r1, #0 +1000b6ca: a954 add r1, sp, #336 @ 0x150 +1000b6cc: 64a5 str r5, [r4, #72] @ 0x48 +1000b6ce: f8c4 804c str.w r8, [r4, #76] @ 0x4c +1000b6d2: f7fe fedf bl 1000a494 +1000b6d6: 2200 movs r2, #0 +1000b6d8: eb07 010a add.w r1, r7, sl +1000b6dc: f1a9 077c sub.w r7, r9, #124 @ 0x7c +1000b6e0: 2f80 cmp r7, #128 @ 0x80 +1000b6e2: f8c4 20e0 str.w r2, [r4, #224] @ 0xe0 +1000b6e6: d96d bls.n 1000b7c4 +1000b6e8: 2280 movs r2, #128 @ 0x80 +1000b6ea: 9b06 ldr r3, [sp, #24] +1000b6ec: f51b 7780 adds.w r7, fp, #256 @ 0x100 +1000b6f0: f143 0a00 adc.w sl, r3, #0 +1000b6f4: f1a9 00fd sub.w r0, r9, #253 @ 0xfd +1000b6f8: f51b 7bc0 adds.w fp, fp, #384 @ 0x180 +1000b6fc: ea4f 10d0 mov.w r0, r0, lsr #7 +1000b700: f143 0300 adc.w r3, r3, #0 +1000b704: fbe0 b302 umlal fp, r3, r0, r2 +1000b708: e9cd 9106 strd r9, r1, [sp, #24] +1000b70c: 4699 mov r9, r3 +1000b70e: 9609 str r6, [sp, #36] @ 0x24 +1000b710: 9008 str r0, [sp, #32] +1000b712: 4646 mov r6, r8 +1000b714: 46a0 mov r8, r4 +1000b716: 462c mov r4, r5 +1000b718: 4655 mov r5, sl +1000b71a: eba1 0a07 sub.w sl, r1, r7 +1000b71e: 2f80 cmp r7, #128 @ 0x80 +1000b720: f175 0100 sbcs.w r1, r5, #0 +1000b724: bf34 ite cc +1000b726: 2101 movcc r1, #1 +1000b728: 2100 movcs r1, #0 +1000b72a: 1909 adds r1, r1, r4 +1000b72c: 460c mov r4, r1 +1000b72e: f146 0600 adc.w r6, r6, #0 +1000b732: eb0a 0107 add.w r1, sl, r7 +1000b736: 4640 mov r0, r8 +1000b738: e9c8 7510 strd r7, r5, [r8, #64] @ 0x40 +1000b73c: f8c8 604c str.w r6, [r8, #76] @ 0x4c +1000b740: f8c8 4048 str.w r4, [r8, #72] @ 0x48 +1000b744: f7fe fea6 bl 1000a494 +1000b748: 3780 adds r7, #128 @ 0x80 +1000b74a: f145 0500 adc.w r5, r5, #0 +1000b74e: 454d cmp r5, r9 +1000b750: bf08 it eq +1000b752: 455f cmpeq r7, fp +1000b754: d1e3 bne.n 1000b71e +1000b756: e9dd 9106 ldrd r9, r1, [sp, #24] +1000b75a: 9808 ldr r0, [sp, #32] +1000b75c: f1a9 09fc sub.w r9, r9, #252 @ 0xfc +1000b760: eb01 1ac0 add.w sl, r1, r0, lsl #7 +1000b764: eba9 17c0 sub.w r7, r9, r0, lsl #7 +1000b768: 4644 mov r4, r8 +1000b76a: 2060 movs r0, #96 @ 0x60 +1000b76c: 9e09 ldr r6, [sp, #36] @ 0x24 +1000b76e: f10a 0180 add.w r1, sl, #128 @ 0x80 +1000b772: e5b9 b.n 1000b2e8 +1000b774: f8dd c00c ldr.w ip, [sp, #12] +1000b778: 9c09 ldr r4, [sp, #36] @ 0x24 +1000b77a: 4666 mov r6, ip +1000b77c: 2500 movs r5, #0 +1000b77e: f10d 0e70 add.w lr, sp, #112 @ 0x70 +1000b782: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b786: c60f stmia r6!, {r0, r1, r2, r3} +1000b788: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b78c: c60f stmia r6!, {r0, r1, r2, r3} +1000b78e: e8be 000f ldmia.w lr!, {r0, r1, r2, r3} +1000b792: c60f stmia r6!, {r0, r1, r2, r3} +1000b794: e89e 000f ldmia.w lr, {r0, r1, r2, r3} +1000b798: e886 000f stmia.w r6, {r0, r1, r2, r3} +1000b79c: 9501 str r5, [sp, #4] +1000b79e: 9e04 ldr r6, [sp, #16] +1000b7a0: 4662 mov r2, ip +1000b7a2: 2340 movs r3, #64 @ 0x40 +1000b7a4: 4631 mov r1, r6 +1000b7a6: 9500 str r5, [sp, #0] +1000b7a8: a81c add r0, sp, #112 @ 0x70 +1000b7aa: f7ff fcab bl 1000b104 +1000b7ae: 3001 adds r0, #1 +1000b7b0: f43f aeef beq.w 1000b592 +1000b7b4: 4632 mov r2, r6 +1000b7b6: 4638 mov r0, r7 +1000b7b8: a91c add r1, sp, #112 @ 0x70 +1000b7ba: f000 fbdf bl 1000bf7c +1000b7be: e6ea b.n 1000b596 +1000b7c0: 2060 movs r0, #96 @ 0x60 +1000b7c2: e5c9 b.n 1000b358 +1000b7c4: 2060 movs r0, #96 @ 0x60 +1000b7c6: e58f b.n 1000b2e8 +1000b7c8: 2060 movs r0, #96 @ 0x60 +1000b7ca: e55a b.n 1000b282 + +1000b7cc : +1000b7cc: 4b02 ldr r3, [pc, #8] @ (1000b7d8 ) +1000b7ce: 4601 mov r1, r0 +1000b7d0: 6818 ldr r0, [r3, #0] +1000b7d2: f000 b80b b.w 1000b7ec <_malloc_r> +1000b7d6: bf00 nop +1000b7d8: 20001668 .word 0x20001668 + +1000b7dc : +1000b7dc: 4b02 ldr r3, [pc, #8] @ (1000b7e8 ) +1000b7de: 4601 mov r1, r0 +1000b7e0: 6818 ldr r0, [r3, #0] +1000b7e2: f000 bcc5 b.w 1000c170 <_free_r> +1000b7e6: bf00 nop +1000b7e8: 20001668 .word 0x20001668 + +1000b7ec <_malloc_r>: +1000b7ec: f101 030b add.w r3, r1, #11 +1000b7f0: 2b16 cmp r3, #22 +1000b7f2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000b7f6: 4680 mov r8, r0 +1000b7f8: b085 sub sp, #20 +1000b7fa: d82c bhi.n 1000b856 <_malloc_r+0x6a> +1000b7fc: 2910 cmp r1, #16 +1000b7fe: d822 bhi.n 1000b846 <_malloc_r+0x5a> +1000b800: f000 fac8 bl 1000bd94 <__malloc_lock> +1000b804: 2118 movs r1, #24 +1000b806: f04f 0e02 mov.w lr, #2 +1000b80a: 2210 movs r2, #16 +1000b80c: 4cb6 ldr r4, [pc, #728] @ (1000bae8 <_malloc_r+0x2fc>) +1000b80e: 4421 add r1, r4 +1000b810: 684d ldr r5, [r1, #4] +1000b812: f1a1 0008 sub.w r0, r1, #8 +1000b816: 4285 cmp r5, r0 +1000b818: f000 815f beq.w 1000bada <_malloc_r+0x2ee> +1000b81c: 686a ldr r2, [r5, #4] +1000b81e: 4640 mov r0, r8 +1000b820: f022 0203 bic.w r2, r2, #3 +1000b824: e9d5 4102 ldrd r4, r1, [r5, #8] +1000b828: 442a add r2, r5 +1000b82a: 60e1 str r1, [r4, #12] +1000b82c: 608c str r4, [r1, #8] +1000b82e: f105 0408 add.w r4, r5, #8 +1000b832: 6851 ldr r1, [r2, #4] +1000b834: f041 0101 orr.w r1, r1, #1 +1000b838: 6051 str r1, [r2, #4] +1000b83a: f000 fab1 bl 1000bda0 <__malloc_unlock> +1000b83e: 4620 mov r0, r4 +1000b840: b005 add sp, #20 +1000b842: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000b846: 230c movs r3, #12 +1000b848: f8c8 3000 str.w r3, [r8] +1000b84c: 2400 movs r4, #0 +1000b84e: 4620 mov r0, r4 +1000b850: b005 add sp, #20 +1000b852: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000b856: 2b00 cmp r3, #0 +1000b858: f023 0207 bic.w r2, r3, #7 +1000b85c: dbf3 blt.n 1000b846 <_malloc_r+0x5a> +1000b85e: 4291 cmp r1, r2 +1000b860: d8f1 bhi.n 1000b846 <_malloc_r+0x5a> +1000b862: 9200 str r2, [sp, #0] +1000b864: f000 fa96 bl 1000bd94 <__malloc_lock> +1000b868: 9a00 ldr r2, [sp, #0] +1000b86a: f5b2 7ffc cmp.w r2, #504 @ 0x1f8 +1000b86e: f0c0 819f bcc.w 1000bbb0 <_malloc_r+0x3c4> +1000b872: 0a53 lsrs r3, r2, #9 +1000b874: d073 beq.n 1000b95e <_malloc_r+0x172> +1000b876: 2b04 cmp r3, #4 +1000b878: f200 8164 bhi.w 1000bb44 <_malloc_r+0x358> +1000b87c: 0993 lsrs r3, r2, #6 +1000b87e: f103 0e39 add.w lr, r3, #57 @ 0x39 +1000b882: f103 0638 add.w r6, r3, #56 @ 0x38 +1000b886: ea4f 03ce mov.w r3, lr, lsl #3 +1000b88a: 4c97 ldr r4, [pc, #604] @ (1000bae8 <_malloc_r+0x2fc>) +1000b88c: 4423 add r3, r4 +1000b88e: f1a3 0508 sub.w r5, r3, #8 +1000b892: 685f ldr r7, [r3, #4] +1000b894: 42bd cmp r5, r7 +1000b896: d107 bne.n 1000b8a8 <_malloc_r+0xbc> +1000b898: e00d b.n 1000b8b6 <_malloc_r+0xca> +1000b89a: 2800 cmp r0, #0 +1000b89c: 68fb ldr r3, [r7, #12] +1000b89e: f280 810b bge.w 1000bab8 <_malloc_r+0x2cc> +1000b8a2: 429d cmp r5, r3 +1000b8a4: 461f mov r7, r3 +1000b8a6: d006 beq.n 1000b8b6 <_malloc_r+0xca> +1000b8a8: 6879 ldr r1, [r7, #4] +1000b8aa: f021 0103 bic.w r1, r1, #3 +1000b8ae: 1a88 subs r0, r1, r2 +1000b8b0: 280f cmp r0, #15 +1000b8b2: ddf2 ble.n 1000b89a <_malloc_r+0xae> +1000b8b4: 46b6 mov lr, r6 +1000b8b6: 6923 ldr r3, [r4, #16] +1000b8b8: 498c ldr r1, [pc, #560] @ (1000baec <_malloc_r+0x300>) +1000b8ba: 428b cmp r3, r1 +1000b8bc: f000 80e9 beq.w 1000ba92 <_malloc_r+0x2a6> +1000b8c0: 685e ldr r6, [r3, #4] +1000b8c2: f026 0603 bic.w r6, r6, #3 +1000b8c6: 1ab1 subs r1, r6, r2 +1000b8c8: 290f cmp r1, #15 +1000b8ca: f300 8183 bgt.w 1000bbd4 <_malloc_r+0x3e8> +1000b8ce: 4887 ldr r0, [pc, #540] @ (1000baec <_malloc_r+0x300>) +1000b8d0: 2900 cmp r1, #0 +1000b8d2: e9c4 0004 strd r0, r0, [r4, #16] +1000b8d6: f280 8170 bge.w 1000bbba <_malloc_r+0x3ce> +1000b8da: f5b6 7f00 cmp.w r6, #512 @ 0x200 +1000b8de: 6867 ldr r7, [r4, #4] +1000b8e0: f080 8110 bcs.w 1000bb04 <_malloc_r+0x318> +1000b8e4: 08f1 lsrs r1, r6, #3 +1000b8e6: 2001 movs r0, #1 +1000b8e8: 0976 lsrs r6, r6, #5 +1000b8ea: 3101 adds r1, #1 +1000b8ec: 40b0 lsls r0, r6 +1000b8ee: f854 5031 ldr.w r5, [r4, r1, lsl #3] +1000b8f2: 4307 orrs r7, r0 +1000b8f4: eb04 00c1 add.w r0, r4, r1, lsl #3 +1000b8f8: 3808 subs r0, #8 +1000b8fa: 6067 str r7, [r4, #4] +1000b8fc: e9c3 5002 strd r5, r0, [r3, #8] +1000b900: f844 3031 str.w r3, [r4, r1, lsl #3] +1000b904: 60eb str r3, [r5, #12] +1000b906: ea4f 03ae mov.w r3, lr, asr #2 +1000b90a: 2601 movs r6, #1 +1000b90c: 409e lsls r6, r3 +1000b90e: 42be cmp r6, r7 +1000b910: d82b bhi.n 1000b96a <_malloc_r+0x17e> +1000b912: 423e tst r6, r7 +1000b914: d106 bne.n 1000b924 <_malloc_r+0x138> +1000b916: f02e 0e03 bic.w lr, lr, #3 +1000b91a: 0076 lsls r6, r6, #1 +1000b91c: f10e 0e04 add.w lr, lr, #4 +1000b920: 423e tst r6, r7 +1000b922: d0fa beq.n 1000b91a <_malloc_r+0x12e> +1000b924: eb04 0ace add.w sl, r4, lr, lsl #3 +1000b928: 46f1 mov r9, lr +1000b92a: eb04 07ce add.w r7, r4, lr, lsl #3 +1000b92e: 68f9 ldr r1, [r7, #12] +1000b930: e00c b.n 1000b94c <_malloc_r+0x160> +1000b932: 6848 ldr r0, [r1, #4] +1000b934: 460b mov r3, r1 +1000b936: 68c9 ldr r1, [r1, #12] +1000b938: f020 0c03 bic.w ip, r0, #3 +1000b93c: ebac 0502 sub.w r5, ip, r2 +1000b940: 2d0f cmp r5, #15 +1000b942: f300 810c bgt.w 1000bb5e <_malloc_r+0x372> +1000b946: 2d00 cmp r5, #0 +1000b948: f280 8122 bge.w 1000bb90 <_malloc_r+0x3a4> +1000b94c: 428f cmp r7, r1 +1000b94e: d1f0 bne.n 1000b932 <_malloc_r+0x146> +1000b950: f109 0301 add.w r3, r9, #1 +1000b954: 3708 adds r7, #8 +1000b956: 0798 lsls r0, r3, #30 +1000b958: 4699 mov r9, r3 +1000b95a: d1e8 bne.n 1000b92e <_malloc_r+0x142> +1000b95c: e174 b.n 1000bc48 <_malloc_r+0x45c> +1000b95e: f44f 7300 mov.w r3, #512 @ 0x200 +1000b962: f04f 0e40 mov.w lr, #64 @ 0x40 +1000b966: 263f movs r6, #63 @ 0x3f +1000b968: e78f b.n 1000b88a <_malloc_r+0x9e> +1000b96a: 68a7 ldr r7, [r4, #8] +1000b96c: 6879 ldr r1, [r7, #4] +1000b96e: f021 0603 bic.w r6, r1, #3 +1000b972: 4296 cmp r6, r2 +1000b974: eba6 0002 sub.w r0, r6, r2 +1000b978: d302 bcc.n 1000b980 <_malloc_r+0x194> +1000b97a: 280f cmp r0, #15 +1000b97c: f300 808b bgt.w 1000ba96 <_malloc_r+0x2aa> +1000b980: 495b ldr r1, [pc, #364] @ (1000baf0 <_malloc_r+0x304>) +1000b982: 2008 movs r0, #8 +1000b984: 6809 ldr r1, [r1, #0] +1000b986: 3110 adds r1, #16 +1000b988: 4411 add r1, r2 +1000b98a: e9cd 1200 strd r1, r2, [sp] +1000b98e: f000 fae3 bl 1000bf58 +1000b992: 9900 ldr r1, [sp, #0] +1000b994: 4603 mov r3, r0 +1000b996: 4682 mov sl, r0 +1000b998: 1e48 subs r0, r1, #1 +1000b99a: 425d negs r5, r3 +1000b99c: 4418 add r0, r3 +1000b99e: 4b55 ldr r3, [pc, #340] @ (1000baf4 <_malloc_r+0x308>) +1000b9a0: 4005 ands r5, r0 +1000b9a2: 6818 ldr r0, [r3, #0] +1000b9a4: f1b0 3fff cmp.w r0, #4294967295 @ 0xffffffff +1000b9a8: bf18 it ne +1000b9aa: 4629 movne r1, r5 +1000b9ac: 4640 mov r0, r8 +1000b9ae: 9100 str r1, [sp, #0] +1000b9b0: f000 faba bl 1000bf28 <_sbrk_r> +1000b9b4: 1c41 adds r1, r0, #1 +1000b9b6: 4605 mov r5, r0 +1000b9b8: e9dd 1200 ldrd r1, r2, [sp] +1000b9bc: f000 8127 beq.w 1000bc0e <_malloc_r+0x422> +1000b9c0: eb07 0c06 add.w ip, r7, r6 +1000b9c4: 4584 cmp ip, r0 +1000b9c6: f200 8120 bhi.w 1000bc0a <_malloc_r+0x41e> +1000b9ca: f8df 9134 ldr.w r9, [pc, #308] @ 1000bb00 <_malloc_r+0x314> +1000b9ce: f10a 3eff add.w lr, sl, #4294967295 @ 0xffffffff +1000b9d2: f8d9 0000 ldr.w r0, [r9] +1000b9d6: 4408 add r0, r1 +1000b9d8: f8c9 0000 str.w r0, [r9] +1000b9dc: f000 8183 beq.w 1000bce6 <_malloc_r+0x4fa> +1000b9e0: 4b44 ldr r3, [pc, #272] @ (1000baf4 <_malloc_r+0x308>) +1000b9e2: 681b ldr r3, [r3, #0] +1000b9e4: 3301 adds r3, #1 +1000b9e6: f000 8188 beq.w 1000bcfa <_malloc_r+0x50e> +1000b9ea: eba5 0c0c sub.w ip, r5, ip +1000b9ee: 4460 add r0, ip +1000b9f0: f8c9 0000 str.w r0, [r9] +1000b9f4: f015 0307 ands.w r3, r5, #7 +1000b9f8: e9cd 2901 strd r2, r9, [sp, #4] +1000b9fc: 469b mov fp, r3 +1000b9fe: f000 813f beq.w 1000bc80 <_malloc_r+0x494> +1000ba02: f1c3 0008 rsb r0, r3, #8 +1000ba06: 4405 add r5, r0 +1000ba08: eb0a 0c00 add.w ip, sl, r0 +1000ba0c: 4640 mov r0, r8 +1000ba0e: 186b adds r3, r5, r1 +1000ba10: ea03 010e and.w r1, r3, lr +1000ba14: 469a mov sl, r3 +1000ba16: ebac 0101 sub.w r1, ip, r1 +1000ba1a: ea01 030e and.w r3, r1, lr +1000ba1e: 4619 mov r1, r3 +1000ba20: 9300 str r3, [sp, #0] +1000ba22: f000 fa81 bl 1000bf28 <_sbrk_r> +1000ba26: 1c42 adds r2, r0, #1 +1000ba28: e9dd 2901 ldrd r2, r9, [sp, #4] +1000ba2c: f000 8180 beq.w 1000bd30 <_malloc_r+0x544> +1000ba30: 1b41 subs r1, r0, r5 +1000ba32: 9b00 ldr r3, [sp, #0] +1000ba34: f8d9 0000 ldr.w r0, [r9] +1000ba38: 42a7 cmp r7, r4 +1000ba3a: 4419 add r1, r3 +1000ba3c: 60a5 str r5, [r4, #8] +1000ba3e: 4418 add r0, r3 +1000ba40: f041 0101 orr.w r1, r1, #1 +1000ba44: f8c9 0000 str.w r0, [r9] +1000ba48: 6069 str r1, [r5, #4] +1000ba4a: d016 beq.n 1000ba7a <_malloc_r+0x28e> +1000ba4c: 2e0f cmp r6, #15 +1000ba4e: f240 8157 bls.w 1000bd00 <_malloc_r+0x514> +1000ba52: f1a6 010c sub.w r1, r6, #12 +1000ba56: 2605 movs r6, #5 +1000ba58: f021 0c07 bic.w ip, r1, #7 +1000ba5c: 6879 ldr r1, [r7, #4] +1000ba5e: f001 0101 and.w r1, r1, #1 +1000ba62: f1bc 0f0f cmp.w ip, #15 +1000ba66: ea41 010c orr.w r1, r1, ip +1000ba6a: 6079 str r1, [r7, #4] +1000ba6c: eb07 010c add.w r1, r7, ip +1000ba70: e9c1 6601 strd r6, r6, [r1, #4] +1000ba74: f200 8163 bhi.w 1000bd3e <_malloc_r+0x552> +1000ba78: 6869 ldr r1, [r5, #4] +1000ba7a: 4b1f ldr r3, [pc, #124] @ (1000baf8 <_malloc_r+0x30c>) +1000ba7c: 681e ldr r6, [r3, #0] +1000ba7e: 4286 cmp r6, r0 +1000ba80: bf38 it cc +1000ba82: 6018 strcc r0, [r3, #0] +1000ba84: 4b1d ldr r3, [pc, #116] @ (1000bafc <_malloc_r+0x310>) +1000ba86: 681e ldr r6, [r3, #0] +1000ba88: 4286 cmp r6, r0 +1000ba8a: d200 bcs.n 1000ba8e <_malloc_r+0x2a2> +1000ba8c: 6018 str r0, [r3, #0] +1000ba8e: 462f mov r7, r5 +1000ba90: e0bf b.n 1000bc12 <_malloc_r+0x426> +1000ba92: 6867 ldr r7, [r4, #4] +1000ba94: e737 b.n 1000b906 <_malloc_r+0x11a> +1000ba96: 18bd adds r5, r7, r2 +1000ba98: f042 0201 orr.w r2, r2, #1 +1000ba9c: f040 0101 orr.w r1, r0, #1 +1000baa0: 4640 mov r0, r8 +1000baa2: 607a str r2, [r7, #4] +1000baa4: 60a5 str r5, [r4, #8] +1000baa6: f107 0408 add.w r4, r7, #8 +1000baaa: 6069 str r1, [r5, #4] +1000baac: f000 f978 bl 1000bda0 <__malloc_unlock> +1000bab0: 4620 mov r0, r4 +1000bab2: b005 add sp, #20 +1000bab4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000bab8: 68ba ldr r2, [r7, #8] +1000baba: 4439 add r1, r7 +1000babc: f107 0408 add.w r4, r7, #8 +1000bac0: 4640 mov r0, r8 +1000bac2: 60d3 str r3, [r2, #12] +1000bac4: 609a str r2, [r3, #8] +1000bac6: 684a ldr r2, [r1, #4] +1000bac8: f042 0201 orr.w r2, r2, #1 +1000bacc: 604a str r2, [r1, #4] +1000bace: f000 f967 bl 1000bda0 <__malloc_unlock> +1000bad2: 4620 mov r0, r4 +1000bad4: b005 add sp, #20 +1000bad6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000bada: 68cd ldr r5, [r1, #12] +1000badc: 42a9 cmp r1, r5 +1000bade: f47f ae9d bne.w 1000b81c <_malloc_r+0x30> +1000bae2: f10e 0e02 add.w lr, lr, #2 +1000bae6: e6e6 b.n 1000b8b6 <_malloc_r+0xca> +1000bae8: 20001260 .word 0x20001260 +1000baec: 20001268 .word 0x20001268 +1000baf0: 20001afc .word 0x20001afc +1000baf4: 20001258 .word 0x20001258 +1000baf8: 20001af4 .word 0x20001af4 +1000bafc: 20001af8 .word 0x20001af8 +1000bb00: 20001acc .word 0x20001acc +1000bb04: f5b6 6f20 cmp.w r6, #2560 @ 0xa00 +1000bb08: ea4f 2056 mov.w r0, r6, lsr #9 +1000bb0c: d377 bcc.n 1000bbfe <_malloc_r+0x412> +1000bb0e: 2814 cmp r0, #20 +1000bb10: f200 80cc bhi.w 1000bcac <_malloc_r+0x4c0> +1000bb14: f100 015c add.w r1, r0, #92 @ 0x5c +1000bb18: 305b adds r0, #91 @ 0x5b +1000bb1a: 00c9 lsls r1, r1, #3 +1000bb1c: 1865 adds r5, r4, r1 +1000bb1e: 5861 ldr r1, [r4, r1] +1000bb20: 3d08 subs r5, #8 +1000bb22: 428d cmp r5, r1 +1000bb24: d103 bne.n 1000bb2e <_malloc_r+0x342> +1000bb26: e0a4 b.n 1000bc72 <_malloc_r+0x486> +1000bb28: 6889 ldr r1, [r1, #8] +1000bb2a: 428d cmp r5, r1 +1000bb2c: d004 beq.n 1000bb38 <_malloc_r+0x34c> +1000bb2e: 6848 ldr r0, [r1, #4] +1000bb30: f020 0003 bic.w r0, r0, #3 +1000bb34: 42b0 cmp r0, r6 +1000bb36: d8f7 bhi.n 1000bb28 <_malloc_r+0x33c> +1000bb38: 68cd ldr r5, [r1, #12] +1000bb3a: e9c3 1502 strd r1, r5, [r3, #8] +1000bb3e: 60ab str r3, [r5, #8] +1000bb40: 60cb str r3, [r1, #12] +1000bb42: e6e0 b.n 1000b906 <_malloc_r+0x11a> +1000bb44: 2b14 cmp r3, #20 +1000bb46: d971 bls.n 1000bc2c <_malloc_r+0x440> +1000bb48: 2b54 cmp r3, #84 @ 0x54 +1000bb4a: f200 80b7 bhi.w 1000bcbc <_malloc_r+0x4d0> +1000bb4e: 0b13 lsrs r3, r2, #12 +1000bb50: f103 0e6f add.w lr, r3, #111 @ 0x6f +1000bb54: f103 066e add.w r6, r3, #110 @ 0x6e +1000bb58: ea4f 03ce mov.w r3, lr, lsl #3 +1000bb5c: e695 b.n 1000b88a <_malloc_r+0x9e> +1000bb5e: 189e adds r6, r3, r2 +1000bb60: f042 0201 orr.w r2, r2, #1 +1000bb64: 689f ldr r7, [r3, #8] +1000bb66: 4640 mov r0, r8 +1000bb68: 605a str r2, [r3, #4] +1000bb6a: 4a87 ldr r2, [pc, #540] @ (1000bd88 <_malloc_r+0x59c>) +1000bb6c: 60f9 str r1, [r7, #12] +1000bb6e: 608f str r7, [r1, #8] +1000bb70: 9300 str r3, [sp, #0] +1000bb72: e9c4 6604 strd r6, r6, [r4, #16] +1000bb76: e9c6 2202 strd r2, r2, [r6, #8] +1000bb7a: f045 0201 orr.w r2, r5, #1 +1000bb7e: 6072 str r2, [r6, #4] +1000bb80: f843 500c str.w r5, [r3, ip] +1000bb84: f000 f90c bl 1000bda0 <__malloc_unlock> +1000bb88: 9b00 ldr r3, [sp, #0] +1000bb8a: f103 0408 add.w r4, r3, #8 +1000bb8e: e65e b.n 1000b84e <_malloc_r+0x62> +1000bb90: 449c add ip, r3 +1000bb92: 461c mov r4, r3 +1000bb94: 4640 mov r0, r8 +1000bb96: f8dc 3004 ldr.w r3, [ip, #4] +1000bb9a: f043 0301 orr.w r3, r3, #1 +1000bb9e: f8cc 3004 str.w r3, [ip, #4] +1000bba2: f854 3f08 ldr.w r3, [r4, #8]! +1000bba6: 60d9 str r1, [r3, #12] +1000bba8: 608b str r3, [r1, #8] +1000bbaa: f000 f8f9 bl 1000bda0 <__malloc_unlock> +1000bbae: e64e b.n 1000b84e <_malloc_r+0x62> +1000bbb0: ea4f 0ed2 mov.w lr, r2, lsr #3 +1000bbb4: f102 0108 add.w r1, r2, #8 +1000bbb8: e628 b.n 1000b80c <_malloc_r+0x20> +1000bbba: 441e add r6, r3 +1000bbbc: 4640 mov r0, r8 +1000bbbe: 9300 str r3, [sp, #0] +1000bbc0: 6872 ldr r2, [r6, #4] +1000bbc2: f042 0201 orr.w r2, r2, #1 +1000bbc6: 6072 str r2, [r6, #4] +1000bbc8: f000 f8ea bl 1000bda0 <__malloc_unlock> +1000bbcc: 9b00 ldr r3, [sp, #0] +1000bbce: f103 0408 add.w r4, r3, #8 +1000bbd2: e63c b.n 1000b84e <_malloc_r+0x62> +1000bbd4: 189d adds r5, r3, r2 +1000bbd6: f042 0201 orr.w r2, r2, #1 +1000bbda: 4640 mov r0, r8 +1000bbdc: 9300 str r3, [sp, #0] +1000bbde: 605a str r2, [r3, #4] +1000bbe0: 4a69 ldr r2, [pc, #420] @ (1000bd88 <_malloc_r+0x59c>) +1000bbe2: e9c4 5504 strd r5, r5, [r4, #16] +1000bbe6: e9c5 2202 strd r2, r2, [r5, #8] +1000bbea: f041 0201 orr.w r2, r1, #1 +1000bbee: 606a str r2, [r5, #4] +1000bbf0: 5199 str r1, [r3, r6] +1000bbf2: f000 f8d5 bl 1000bda0 <__malloc_unlock> +1000bbf6: 9b00 ldr r3, [sp, #0] +1000bbf8: f103 0408 add.w r4, r3, #8 +1000bbfc: e627 b.n 1000b84e <_malloc_r+0x62> +1000bbfe: 09b0 lsrs r0, r6, #6 +1000bc00: f100 0139 add.w r1, r0, #57 @ 0x39 +1000bc04: 3038 adds r0, #56 @ 0x38 +1000bc06: 00c9 lsls r1, r1, #3 +1000bc08: e788 b.n 1000bb1c <_malloc_r+0x330> +1000bc0a: 42a7 cmp r7, r4 +1000bc0c: d061 beq.n 1000bcd2 <_malloc_r+0x4e6> +1000bc0e: 68a7 ldr r7, [r4, #8] +1000bc10: 6879 ldr r1, [r7, #4] +1000bc12: f021 0103 bic.w r1, r1, #3 +1000bc16: 4291 cmp r1, r2 +1000bc18: eba1 0002 sub.w r0, r1, r2 +1000bc1c: d302 bcc.n 1000bc24 <_malloc_r+0x438> +1000bc1e: 280f cmp r0, #15 +1000bc20: f73f af39 bgt.w 1000ba96 <_malloc_r+0x2aa> +1000bc24: 4640 mov r0, r8 +1000bc26: f000 f8bb bl 1000bda0 <__malloc_unlock> +1000bc2a: e60f b.n 1000b84c <_malloc_r+0x60> +1000bc2c: f103 0e5c add.w lr, r3, #92 @ 0x5c +1000bc30: f103 065b add.w r6, r3, #91 @ 0x5b +1000bc34: ea4f 03ce mov.w r3, lr, lsl #3 +1000bc38: e627 b.n 1000b88a <_malloc_r+0x9e> +1000bc3a: 4651 mov r1, sl +1000bc3c: f851 3908 ldr.w r3, [r1], #-8 +1000bc40: 428b cmp r3, r1 +1000bc42: 468a mov sl, r1 +1000bc44: f040 809e bne.w 1000bd84 <_malloc_r+0x598> +1000bc48: f01e 0f03 tst.w lr, #3 +1000bc4c: f10e 3eff add.w lr, lr, #4294967295 @ 0xffffffff +1000bc50: d1f3 bne.n 1000bc3a <_malloc_r+0x44e> +1000bc52: 6863 ldr r3, [r4, #4] +1000bc54: ea23 0306 bic.w r3, r3, r6 +1000bc58: 6063 str r3, [r4, #4] +1000bc5a: 0076 lsls r6, r6, #1 +1000bc5c: 1e71 subs r1, r6, #1 +1000bc5e: 4299 cmp r1, r3 +1000bc60: d303 bcc.n 1000bc6a <_malloc_r+0x47e> +1000bc62: e682 b.n 1000b96a <_malloc_r+0x17e> +1000bc64: 0076 lsls r6, r6, #1 +1000bc66: f109 0904 add.w r9, r9, #4 +1000bc6a: 421e tst r6, r3 +1000bc6c: d0fa beq.n 1000bc64 <_malloc_r+0x478> +1000bc6e: 46ce mov lr, r9 +1000bc70: e658 b.n 1000b924 <_malloc_r+0x138> +1000bc72: 1080 asrs r0, r0, #2 +1000bc74: 2601 movs r6, #1 +1000bc76: fa06 f000 lsl.w r0, r6, r0 +1000bc7a: 4307 orrs r7, r0 +1000bc7c: 6067 str r7, [r4, #4] +1000bc7e: e75c b.n 1000bb3a <_malloc_r+0x34e> +1000bc80: 186b adds r3, r5, r1 +1000bc82: 4640 mov r0, r8 +1000bc84: ea03 010e and.w r1, r3, lr +1000bc88: 9303 str r3, [sp, #12] +1000bc8a: ebaa 0101 sub.w r1, sl, r1 +1000bc8e: ea01 030e and.w r3, r1, lr +1000bc92: 4619 mov r1, r3 +1000bc94: 9300 str r3, [sp, #0] +1000bc96: f000 f947 bl 1000bf28 <_sbrk_r> +1000bc9a: 1c43 adds r3, r0, #1 +1000bc9c: e9dd 2901 ldrd r2, r9, [sp, #4] +1000bca0: f47f aec6 bne.w 1000ba30 <_malloc_r+0x244> +1000bca4: 9803 ldr r0, [sp, #12] +1000bca6: f8cd b000 str.w fp, [sp] +1000bcaa: e6c1 b.n 1000ba30 <_malloc_r+0x244> +1000bcac: 2854 cmp r0, #84 @ 0x54 +1000bcae: d82a bhi.n 1000bd06 <_malloc_r+0x51a> +1000bcb0: 0b30 lsrs r0, r6, #12 +1000bcb2: f100 016f add.w r1, r0, #111 @ 0x6f +1000bcb6: 306e adds r0, #110 @ 0x6e +1000bcb8: 00c9 lsls r1, r1, #3 +1000bcba: e72f b.n 1000bb1c <_malloc_r+0x330> +1000bcbc: f5b3 7faa cmp.w r3, #340 @ 0x154 +1000bcc0: d82a bhi.n 1000bd18 <_malloc_r+0x52c> +1000bcc2: 0bd3 lsrs r3, r2, #15 +1000bcc4: f103 0e78 add.w lr, r3, #120 @ 0x78 +1000bcc8: f103 0677 add.w r6, r3, #119 @ 0x77 +1000bccc: ea4f 03ce mov.w r3, lr, lsl #3 +1000bcd0: e5db b.n 1000b88a <_malloc_r+0x9e> +1000bcd2: f8df 90bc ldr.w r9, [pc, #188] @ 1000bd90 <_malloc_r+0x5a4> +1000bcd6: f10a 3eff add.w lr, sl, #4294967295 @ 0xffffffff +1000bcda: f8d9 0000 ldr.w r0, [r9] +1000bcde: 4408 add r0, r1 +1000bce0: f8c9 0000 str.w r0, [r9] +1000bce4: e67c b.n 1000b9e0 <_malloc_r+0x1f4> +1000bce6: ea15 0f0e tst.w r5, lr +1000bcea: f47f ae79 bne.w 1000b9e0 <_malloc_r+0x1f4> +1000bcee: 4431 add r1, r6 +1000bcf0: 68a5 ldr r5, [r4, #8] +1000bcf2: f041 0101 orr.w r1, r1, #1 +1000bcf6: 6069 str r1, [r5, #4] +1000bcf8: e6bf b.n 1000ba7a <_malloc_r+0x28e> +1000bcfa: 4b24 ldr r3, [pc, #144] @ (1000bd8c <_malloc_r+0x5a0>) +1000bcfc: 601d str r5, [r3, #0] +1000bcfe: e679 b.n 1000b9f4 <_malloc_r+0x208> +1000bd00: 2301 movs r3, #1 +1000bd02: 606b str r3, [r5, #4] +1000bd04: e78e b.n 1000bc24 <_malloc_r+0x438> +1000bd06: f5b0 7faa cmp.w r0, #340 @ 0x154 +1000bd0a: d827 bhi.n 1000bd5c <_malloc_r+0x570> +1000bd0c: 0bf0 lsrs r0, r6, #15 +1000bd0e: f100 0178 add.w r1, r0, #120 @ 0x78 +1000bd12: 3077 adds r0, #119 @ 0x77 +1000bd14: 00c9 lsls r1, r1, #3 +1000bd16: e701 b.n 1000bb1c <_malloc_r+0x330> +1000bd18: f240 5154 movw r1, #1364 @ 0x554 +1000bd1c: 428b cmp r3, r1 +1000bd1e: d827 bhi.n 1000bd70 <_malloc_r+0x584> +1000bd20: 0c93 lsrs r3, r2, #18 +1000bd22: f103 0e7d add.w lr, r3, #125 @ 0x7d +1000bd26: f103 067c add.w r6, r3, #124 @ 0x7c +1000bd2a: ea4f 03ce mov.w r3, lr, lsl #3 +1000bd2e: e5ac b.n 1000b88a <_malloc_r+0x9e> +1000bd30: f1ab 0108 sub.w r1, fp, #8 +1000bd34: 2300 movs r3, #0 +1000bd36: eb0a 0001 add.w r0, sl, r1 +1000bd3a: 9300 str r3, [sp, #0] +1000bd3c: e678 b.n 1000ba30 <_malloc_r+0x244> +1000bd3e: f107 0108 add.w r1, r7, #8 +1000bd42: 4640 mov r0, r8 +1000bd44: e9cd 2900 strd r2, r9, [sp] +1000bd48: f000 fa12 bl 1000c170 <_free_r> +1000bd4c: 68a5 ldr r5, [r4, #8] +1000bd4e: f8dd 9004 ldr.w r9, [sp, #4] +1000bd52: 6869 ldr r1, [r5, #4] +1000bd54: f8d9 0000 ldr.w r0, [r9] +1000bd58: 9a00 ldr r2, [sp, #0] +1000bd5a: e68e b.n 1000ba7a <_malloc_r+0x28e> +1000bd5c: f240 5154 movw r1, #1364 @ 0x554 +1000bd60: 4288 cmp r0, r1 +1000bd62: d80b bhi.n 1000bd7c <_malloc_r+0x590> +1000bd64: 0cb0 lsrs r0, r6, #18 +1000bd66: f100 017d add.w r1, r0, #125 @ 0x7d +1000bd6a: 307c adds r0, #124 @ 0x7c +1000bd6c: 00c9 lsls r1, r1, #3 +1000bd6e: e6d5 b.n 1000bb1c <_malloc_r+0x330> +1000bd70: f44f 737e mov.w r3, #1016 @ 0x3f8 +1000bd74: f04f 0e7f mov.w lr, #127 @ 0x7f +1000bd78: 267e movs r6, #126 @ 0x7e +1000bd7a: e586 b.n 1000b88a <_malloc_r+0x9e> +1000bd7c: f44f 717e mov.w r1, #1016 @ 0x3f8 +1000bd80: 207e movs r0, #126 @ 0x7e +1000bd82: e6cb b.n 1000bb1c <_malloc_r+0x330> +1000bd84: 6863 ldr r3, [r4, #4] +1000bd86: e768 b.n 1000bc5a <_malloc_r+0x46e> +1000bd88: 20001268 .word 0x20001268 +1000bd8c: 20001258 .word 0x20001258 +1000bd90: 20001acc .word 0x20001acc + +1000bd94 <__malloc_lock>: +1000bd94: 4801 ldr r0, [pc, #4] @ (1000bd9c <__malloc_lock+0x8>) +1000bd96: f000 b8ed b.w 1000bf74 <__retarget_lock_acquire_recursive> +1000bd9a: bf00 nop +1000bd9c: 20001ac8 .word 0x20001ac8 + +1000bda0 <__malloc_unlock>: +1000bda0: 4801 ldr r0, [pc, #4] @ (1000bda8 <__malloc_unlock+0x8>) +1000bda2: f000 b8e9 b.w 1000bf78 <__retarget_lock_release_recursive> +1000bda6: bf00 nop +1000bda8: 20001ac8 .word 0x20001ac8 + +1000bdac : +1000bdac: 2a03 cmp r2, #3 +1000bdae: d810 bhi.n 1000bdd2 +1000bdb0: b3d2 cbz r2, 1000be28 +1000bdb2: 3a01 subs r2, #1 +1000bdb4: 1e43 subs r3, r0, #1 +1000bdb6: 3901 subs r1, #1 +1000bdb8: 4402 add r2, r0 +1000bdba: e001 b.n 1000bdc0 +1000bdbc: 429a cmp r2, r3 +1000bdbe: d033 beq.n 1000be28 +1000bdc0: f813 0f01 ldrb.w r0, [r3, #1]! +1000bdc4: f811 cf01 ldrb.w ip, [r1, #1]! +1000bdc8: 4560 cmp r0, ip +1000bdca: d0f7 beq.n 1000bdbc +1000bdcc: eba0 000c sub.w r0, r0, ip +1000bdd0: 4770 bx lr +1000bdd2: b510 push {r4, lr} +1000bdd4: ea41 0400 orr.w r4, r1, r0 +1000bdd8: 4684 mov ip, r0 +1000bdda: 460b mov r3, r1 +1000bddc: 07a4 lsls r4, r4, #30 +1000bdde: d00f beq.n 1000be00 +1000bde0: 3a01 subs r2, #1 +1000bde2: 1e43 subs r3, r0, #1 +1000bde4: 3901 subs r1, #1 +1000bde6: 4402 add r2, r0 +1000bde8: e001 b.n 1000bdee +1000bdea: 429a cmp r2, r3 +1000bdec: d01a beq.n 1000be24 +1000bdee: f813 0f01 ldrb.w r0, [r3, #1]! +1000bdf2: f811 cf01 ldrb.w ip, [r1, #1]! +1000bdf6: 4560 cmp r0, ip +1000bdf8: d0f7 beq.n 1000bdea +1000bdfa: eba0 000c sub.w r0, r0, ip +1000bdfe: bd10 pop {r4, pc} +1000be00: f8dc 4000 ldr.w r4, [ip] +1000be04: 4619 mov r1, r3 +1000be06: f8d3 e000 ldr.w lr, [r3] +1000be0a: 4660 mov r0, ip +1000be0c: 3304 adds r3, #4 +1000be0e: f10c 0c04 add.w ip, ip, #4 +1000be12: 4574 cmp r4, lr +1000be14: d1e4 bne.n 1000bde0 +1000be16: 3a04 subs r2, #4 +1000be18: 2a03 cmp r2, #3 +1000be1a: d8f1 bhi.n 1000be00 +1000be1c: 4660 mov r0, ip +1000be1e: 4619 mov r1, r3 +1000be20: 2a00 cmp r2, #0 +1000be22: d1dd bne.n 1000bde0 +1000be24: 2000 movs r0, #0 +1000be26: bd10 pop {r4, pc} +1000be28: 2000 movs r0, #0 +1000be2a: 4770 bx lr + +1000be2c : +1000be2c: b530 push {r4, r5, lr} +1000be2e: 0784 lsls r4, r0, #30 +1000be30: 4686 mov lr, r0 +1000be32: 4603 mov r3, r0 +1000be34: d006 beq.n 1000be44 +1000be36: b3a2 cbz r2, 1000bea2 +1000be38: f803 1b01 strb.w r1, [r3], #1 +1000be3c: 0798 lsls r0, r3, #30 +1000be3e: f102 32ff add.w r2, r2, #4294967295 @ 0xffffffff +1000be42: d1f8 bne.n 1000be36 +1000be44: 2a03 cmp r2, #3 +1000be46: d926 bls.n 1000be96 +1000be48: fa5f fc81 uxtb.w ip, r1 +1000be4c: 2a0f cmp r2, #15 +1000be4e: eb0c 2c0c add.w ip, ip, ip, lsl #8 +1000be52: eb0c 400c add.w r0, ip, ip, lsl #16 +1000be56: d92a bls.n 1000beae +1000be58: f022 0c0f bic.w ip, r2, #15 +1000be5c: 449c add ip, r3 +1000be5e: e9c3 0000 strd r0, r0, [r3] +1000be62: e9c3 0002 strd r0, r0, [r3, #8] +1000be66: 3310 adds r3, #16 +1000be68: 4563 cmp r3, ip +1000be6a: d1f8 bne.n 1000be5e +1000be6c: f012 0f0c tst.w r2, #12 +1000be70: f002 050f and.w r5, r2, #15 +1000be74: d017 beq.n 1000bea6 +1000be76: ea4f 0c95 mov.w ip, r5, lsr #2 +1000be7a: 461a mov r2, r3 +1000be7c: f10c 34ff add.w r4, ip, #4294967295 @ 0xffffffff +1000be80: eb03 0c8c add.w ip, r3, ip, lsl #2 +1000be84: f842 0b04 str.w r0, [r2], #4 +1000be88: 4562 cmp r2, ip +1000be8a: d1fb bne.n 1000be84 +1000be8c: 3304 adds r3, #4 +1000be8e: f005 0203 and.w r2, r5, #3 +1000be92: eb03 0384 add.w r3, r3, r4, lsl #2 +1000be96: b122 cbz r2, 1000bea2 +1000be98: 441a add r2, r3 +1000be9a: f803 1b01 strb.w r1, [r3], #1 +1000be9e: 429a cmp r2, r3 +1000bea0: d1fb bne.n 1000be9a +1000bea2: 4670 mov r0, lr +1000bea4: bd30 pop {r4, r5, pc} +1000bea6: 462a mov r2, r5 +1000bea8: 2a00 cmp r2, #0 +1000beaa: d1f5 bne.n 1000be98 +1000beac: e7f9 b.n 1000bea2 +1000beae: 4615 mov r5, r2 +1000beb0: e7e1 b.n 1000be76 +1000beb2: bf00 nop + +1000beb4 : +1000beb4: b382 cbz r2, 1000bf18 +1000beb6: ea40 0301 orr.w r3, r0, r1 +1000beba: 079b lsls r3, r3, #30 +1000bebc: b530 push {r4, r5, lr} +1000bebe: 4604 mov r4, r0 +1000bec0: 468e mov lr, r1 +1000bec2: d117 bne.n 1000bef4 +1000bec4: 2a03 cmp r2, #3 +1000bec6: d807 bhi.n 1000bed8 +1000bec8: e014 b.n 1000bef4 +1000beca: 3a04 subs r2, #4 +1000becc: d022 beq.n 1000bf14 +1000bece: f01c 3f80 tst.w ip, #2155905152 @ 0x80808080 +1000bed2: d11f bne.n 1000bf14 +1000bed4: 2a03 cmp r2, #3 +1000bed6: d923 bls.n 1000bf20 +1000bed8: 6823 ldr r3, [r4, #0] +1000beda: 4671 mov r1, lr +1000bedc: f8de 5000 ldr.w r5, [lr] +1000bee0: 4620 mov r0, r4 +1000bee2: f1a3 3c01 sub.w ip, r3, #16843009 @ 0x1010101 +1000bee6: 3404 adds r4, #4 +1000bee8: 42ab cmp r3, r5 +1000beea: f10e 0e04 add.w lr, lr, #4 +1000beee: ea2c 0c03 bic.w ip, ip, r3 +1000bef2: d0ea beq.n 1000beca +1000bef4: 7803 ldrb r3, [r0, #0] +1000bef6: 780c ldrb r4, [r1, #0] +1000bef8: 42a3 cmp r3, r4 +1000befa: d10f bne.n 1000bf1c +1000befc: 3a01 subs r2, #1 +1000befe: 4402 add r2, r0 +1000bf00: e006 b.n 1000bf10 +1000bf02: b13b cbz r3, 1000bf14 +1000bf04: f810 3f01 ldrb.w r3, [r0, #1]! +1000bf08: f811 4f01 ldrb.w r4, [r1, #1]! +1000bf0c: 42a3 cmp r3, r4 +1000bf0e: d105 bne.n 1000bf1c +1000bf10: 4290 cmp r0, r2 +1000bf12: d1f6 bne.n 1000bf02 +1000bf14: 2000 movs r0, #0 +1000bf16: bd30 pop {r4, r5, pc} +1000bf18: 4610 mov r0, r2 +1000bf1a: 4770 bx lr +1000bf1c: 1b18 subs r0, r3, r4 +1000bf1e: bd30 pop {r4, r5, pc} +1000bf20: 4620 mov r0, r4 +1000bf22: 4671 mov r1, lr +1000bf24: e7e6 b.n 1000bef4 +1000bf26: bf00 nop + +1000bf28 <_sbrk_r>: +1000bf28: b538 push {r3, r4, r5, lr} +1000bf2a: 2300 movs r3, #0 +1000bf2c: 4c06 ldr r4, [pc, #24] @ (1000bf48 <_sbrk_r+0x20>) +1000bf2e: 4605 mov r5, r0 +1000bf30: 4608 mov r0, r1 +1000bf32: 6023 str r3, [r4, #0] +1000bf34: f7f7 fa28 bl 10003388 <_sbrk> +1000bf38: 1c43 adds r3, r0, #1 +1000bf3a: d000 beq.n 1000bf3e <_sbrk_r+0x16> +1000bf3c: bd38 pop {r3, r4, r5, pc} +1000bf3e: 6823 ldr r3, [r4, #0] +1000bf40: 2b00 cmp r3, #0 +1000bf42: d0fb beq.n 1000bf3c <_sbrk_r+0x14> +1000bf44: 602b str r3, [r5, #0] +1000bf46: bd38 pop {r3, r4, r5, pc} +1000bf48: 20001ec4 .word 0x20001ec4 + +1000bf4c <__errno>: +1000bf4c: 4b01 ldr r3, [pc, #4] @ (1000bf54 <__errno+0x8>) +1000bf4e: 6818 ldr r0, [r3, #0] +1000bf50: 4770 bx lr +1000bf52: bf00 nop +1000bf54: 20001668 .word 0x20001668 + +1000bf58 : +1000bf58: 2808 cmp r0, #8 +1000bf5a: d102 bne.n 1000bf62 +1000bf5c: f44f 5080 mov.w r0, #4096 @ 0x1000 +1000bf60: 4770 bx lr +1000bf62: b508 push {r3, lr} +1000bf64: f7ff fff2 bl 1000bf4c <__errno> +1000bf68: 2216 movs r2, #22 +1000bf6a: 4603 mov r3, r0 +1000bf6c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000bf70: 601a str r2, [r3, #0] +1000bf72: bd08 pop {r3, pc} + +1000bf74 <__retarget_lock_acquire_recursive>: +1000bf74: 4770 bx lr +1000bf76: bf00 nop + +1000bf78 <__retarget_lock_release_recursive>: +1000bf78: 4770 bx lr +1000bf7a: bf00 nop + +1000bf7c : +1000bf7c: 4684 mov ip, r0 +1000bf7e: ea41 0300 orr.w r3, r1, r0 +1000bf82: f013 0303 ands.w r3, r3, #3 +1000bf86: d149 bne.n 1000c01c +1000bf88: 3a40 subs r2, #64 @ 0x40 +1000bf8a: d323 bcc.n 1000bfd4 +1000bf8c: 680b ldr r3, [r1, #0] +1000bf8e: 6003 str r3, [r0, #0] +1000bf90: 684b ldr r3, [r1, #4] +1000bf92: 6043 str r3, [r0, #4] +1000bf94: 688b ldr r3, [r1, #8] +1000bf96: 6083 str r3, [r0, #8] +1000bf98: 68cb ldr r3, [r1, #12] +1000bf9a: 60c3 str r3, [r0, #12] +1000bf9c: 690b ldr r3, [r1, #16] +1000bf9e: 6103 str r3, [r0, #16] +1000bfa0: 694b ldr r3, [r1, #20] +1000bfa2: 6143 str r3, [r0, #20] +1000bfa4: 698b ldr r3, [r1, #24] +1000bfa6: 6183 str r3, [r0, #24] +1000bfa8: 69cb ldr r3, [r1, #28] +1000bfaa: 61c3 str r3, [r0, #28] +1000bfac: 6a0b ldr r3, [r1, #32] +1000bfae: 6203 str r3, [r0, #32] +1000bfb0: 6a4b ldr r3, [r1, #36] @ 0x24 +1000bfb2: 6243 str r3, [r0, #36] @ 0x24 +1000bfb4: 6a8b ldr r3, [r1, #40] @ 0x28 +1000bfb6: 6283 str r3, [r0, #40] @ 0x28 +1000bfb8: 6acb ldr r3, [r1, #44] @ 0x2c +1000bfba: 62c3 str r3, [r0, #44] @ 0x2c +1000bfbc: 6b0b ldr r3, [r1, #48] @ 0x30 +1000bfbe: 6303 str r3, [r0, #48] @ 0x30 +1000bfc0: 6b4b ldr r3, [r1, #52] @ 0x34 +1000bfc2: 6343 str r3, [r0, #52] @ 0x34 +1000bfc4: 6b8b ldr r3, [r1, #56] @ 0x38 +1000bfc6: 6383 str r3, [r0, #56] @ 0x38 +1000bfc8: 6bcb ldr r3, [r1, #60] @ 0x3c +1000bfca: 63c3 str r3, [r0, #60] @ 0x3c +1000bfcc: 3040 adds r0, #64 @ 0x40 +1000bfce: 3140 adds r1, #64 @ 0x40 +1000bfd0: 3a40 subs r2, #64 @ 0x40 +1000bfd2: d2db bcs.n 1000bf8c +1000bfd4: 3230 adds r2, #48 @ 0x30 +1000bfd6: d30b bcc.n 1000bff0 +1000bfd8: 680b ldr r3, [r1, #0] +1000bfda: 6003 str r3, [r0, #0] +1000bfdc: 684b ldr r3, [r1, #4] +1000bfde: 6043 str r3, [r0, #4] +1000bfe0: 688b ldr r3, [r1, #8] +1000bfe2: 6083 str r3, [r0, #8] +1000bfe4: 68cb ldr r3, [r1, #12] +1000bfe6: 60c3 str r3, [r0, #12] +1000bfe8: 3010 adds r0, #16 +1000bfea: 3110 adds r1, #16 +1000bfec: 3a10 subs r2, #16 +1000bfee: d2f3 bcs.n 1000bfd8 +1000bff0: 320c adds r2, #12 +1000bff2: d305 bcc.n 1000c000 +1000bff4: f851 3b04 ldr.w r3, [r1], #4 +1000bff8: f840 3b04 str.w r3, [r0], #4 +1000bffc: 3a04 subs r2, #4 +1000bffe: d2f9 bcs.n 1000bff4 +1000c000: 3204 adds r2, #4 +1000c002: d008 beq.n 1000c016 +1000c004: 07d2 lsls r2, r2, #31 +1000c006: bf1c itt ne +1000c008: f811 3b01 ldrbne.w r3, [r1], #1 +1000c00c: f800 3b01 strbne.w r3, [r0], #1 +1000c010: d301 bcc.n 1000c016 +1000c012: 880b ldrh r3, [r1, #0] +1000c014: 8003 strh r3, [r0, #0] +1000c016: 4660 mov r0, ip +1000c018: 4770 bx lr +1000c01a: bf00 nop +1000c01c: 2a08 cmp r2, #8 +1000c01e: d313 bcc.n 1000c048 +1000c020: 078b lsls r3, r1, #30 +1000c022: d0b1 beq.n 1000bf88 +1000c024: f010 0303 ands.w r3, r0, #3 +1000c028: d0ae beq.n 1000bf88 +1000c02a: f1c3 0304 rsb r3, r3, #4 +1000c02e: 1ad2 subs r2, r2, r3 +1000c030: 07db lsls r3, r3, #31 +1000c032: bf1c itt ne +1000c034: f811 3b01 ldrbne.w r3, [r1], #1 +1000c038: f800 3b01 strbne.w r3, [r0], #1 +1000c03c: d3a4 bcc.n 1000bf88 +1000c03e: f831 3b02 ldrh.w r3, [r1], #2 +1000c042: f820 3b02 strh.w r3, [r0], #2 +1000c046: e79f b.n 1000bf88 +1000c048: 3a04 subs r2, #4 +1000c04a: d3d9 bcc.n 1000c000 +1000c04c: 3a01 subs r2, #1 +1000c04e: f811 3b01 ldrb.w r3, [r1], #1 +1000c052: f800 3b01 strb.w r3, [r0], #1 +1000c056: d2f9 bcs.n 1000c04c +1000c058: 780b ldrb r3, [r1, #0] +1000c05a: 7003 strb r3, [r0, #0] +1000c05c: 784b ldrb r3, [r1, #1] +1000c05e: 7043 strb r3, [r0, #1] +1000c060: 788b ldrb r3, [r1, #2] +1000c062: 7083 strb r3, [r0, #2] +1000c064: 4660 mov r0, ip +1000c066: 4770 bx lr + +1000c068 : +1000c068: f020 0103 bic.w r1, r0, #3 +1000c06c: f010 0003 ands.w r0, r0, #3 +1000c070: f1c0 0000 rsb r0, r0, #0 +1000c074: f851 3b04 ldr.w r3, [r1], #4 +1000c078: f100 0c04 add.w ip, r0, #4 +1000c07c: ea4f 0ccc mov.w ip, ip, lsl #3 +1000c080: f06f 0200 mvn.w r2, #0 +1000c084: bf1c itt ne +1000c086: fa22 f20c lsrne.w r2, r2, ip +1000c08a: 4313 orrne r3, r2 +1000c08c: f04f 0c01 mov.w ip, #1 +1000c090: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000c094: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +1000c098: eba3 020c sub.w r2, r3, ip +1000c09c: ea22 0203 bic.w r2, r2, r3 +1000c0a0: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000c0a4: bf04 itt eq +1000c0a6: f851 3b04 ldreq.w r3, [r1], #4 +1000c0aa: 3004 addeq r0, #4 +1000c0ac: d0f4 beq.n 1000c098 +1000c0ae: f1c2 0100 rsb r1, r2, #0 +1000c0b2: ea02 0201 and.w r2, r2, r1 +1000c0b6: fab2 f282 clz r2, r2 +1000c0ba: f1c2 021f rsb r2, r2, #31 +1000c0be: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000c0c2: 4770 bx lr + +1000c0c4 <_malloc_trim_r>: +1000c0c4: b5f8 push {r3, r4, r5, r6, r7, lr} +1000c0c6: 4606 mov r6, r0 +1000c0c8: 2008 movs r0, #8 +1000c0ca: 460c mov r4, r1 +1000c0cc: f7ff ff44 bl 1000bf58 +1000c0d0: 4607 mov r7, r0 +1000c0d2: 4630 mov r0, r6 +1000c0d4: f7ff fe5e bl 1000bd94 <__malloc_lock> +1000c0d8: 4a22 ldr r2, [pc, #136] @ (1000c164 <_malloc_trim_r+0xa0>) +1000c0da: 6893 ldr r3, [r2, #8] +1000c0dc: 685d ldr r5, [r3, #4] +1000c0de: f025 0503 bic.w r5, r5, #3 +1000c0e2: f1a5 0311 sub.w r3, r5, #17 +1000c0e6: 1b1c subs r4, r3, r4 +1000c0e8: 443c add r4, r7 +1000c0ea: fbb4 f4f7 udiv r4, r4, r7 +1000c0ee: 3c01 subs r4, #1 +1000c0f0: fb07 f404 mul.w r4, r7, r4 +1000c0f4: 42a7 cmp r7, r4 +1000c0f6: dc08 bgt.n 1000c10a <_malloc_trim_r+0x46> +1000c0f8: 2100 movs r1, #0 +1000c0fa: 4630 mov r0, r6 +1000c0fc: f7ff ff14 bl 1000bf28 <_sbrk_r> +1000c100: 4a18 ldr r2, [pc, #96] @ (1000c164 <_malloc_trim_r+0xa0>) +1000c102: 6893 ldr r3, [r2, #8] +1000c104: 442b add r3, r5 +1000c106: 4298 cmp r0, r3 +1000c108: d004 beq.n 1000c114 <_malloc_trim_r+0x50> +1000c10a: 4630 mov r0, r6 +1000c10c: f7ff fe48 bl 1000bda0 <__malloc_unlock> +1000c110: 2000 movs r0, #0 +1000c112: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000c114: 4261 negs r1, r4 +1000c116: 4630 mov r0, r6 +1000c118: f7ff ff06 bl 1000bf28 <_sbrk_r> +1000c11c: 3001 adds r0, #1 +1000c11e: 4a11 ldr r2, [pc, #68] @ (1000c164 <_malloc_trim_r+0xa0>) +1000c120: d00d beq.n 1000c13e <_malloc_trim_r+0x7a> +1000c122: 1b2d subs r5, r5, r4 +1000c124: 4910 ldr r1, [pc, #64] @ (1000c168 <_malloc_trim_r+0xa4>) +1000c126: 6893 ldr r3, [r2, #8] +1000c128: 4630 mov r0, r6 +1000c12a: f045 0501 orr.w r5, r5, #1 +1000c12e: 605d str r5, [r3, #4] +1000c130: 680b ldr r3, [r1, #0] +1000c132: 1b1b subs r3, r3, r4 +1000c134: 600b str r3, [r1, #0] +1000c136: f7ff fe33 bl 1000bda0 <__malloc_unlock> +1000c13a: 2001 movs r0, #1 +1000c13c: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000c13e: 2100 movs r1, #0 +1000c140: 4630 mov r0, r6 +1000c142: f7ff fef1 bl 1000bf28 <_sbrk_r> +1000c146: 4a07 ldr r2, [pc, #28] @ (1000c164 <_malloc_trim_r+0xa0>) +1000c148: 6892 ldr r2, [r2, #8] +1000c14a: 1a83 subs r3, r0, r2 +1000c14c: 2b0f cmp r3, #15 +1000c14e: dddc ble.n 1000c10a <_malloc_trim_r+0x46> +1000c150: f043 0301 orr.w r3, r3, #1 +1000c154: 4904 ldr r1, [pc, #16] @ (1000c168 <_malloc_trim_r+0xa4>) +1000c156: 6053 str r3, [r2, #4] +1000c158: 4b04 ldr r3, [pc, #16] @ (1000c16c <_malloc_trim_r+0xa8>) +1000c15a: 681b ldr r3, [r3, #0] +1000c15c: 1ac0 subs r0, r0, r3 +1000c15e: 6008 str r0, [r1, #0] +1000c160: e7d3 b.n 1000c10a <_malloc_trim_r+0x46> +1000c162: bf00 nop +1000c164: 20001260 .word 0x20001260 +1000c168: 20001acc .word 0x20001acc +1000c16c: 20001258 .word 0x20001258 + +1000c170 <_free_r>: +1000c170: 2900 cmp r1, #0 +1000c172: d062 beq.n 1000c23a <_free_r+0xca> +1000c174: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000c178: 460c mov r4, r1 +1000c17a: 4607 mov r7, r0 +1000c17c: f7ff fe0a bl 1000bd94 <__malloc_lock> +1000c180: 497a ldr r1, [pc, #488] @ (1000c36c <_free_r+0x1fc>) +1000c182: f854 ec04 ldr.w lr, [r4, #-4] +1000c186: f1a4 0c08 sub.w ip, r4, #8 +1000c18a: 688d ldr r5, [r1, #8] +1000c18c: f02e 0301 bic.w r3, lr, #1 +1000c190: f00e 0601 and.w r6, lr, #1 +1000c194: eb0c 0203 add.w r2, ip, r3 +1000c198: 6850 ldr r0, [r2, #4] +1000c19a: 4295 cmp r5, r2 +1000c19c: f020 0003 bic.w r0, r0, #3 +1000c1a0: f000 8087 beq.w 1000c2b2 <_free_r+0x142> +1000c1a4: 1815 adds r5, r2, r0 +1000c1a6: 6050 str r0, [r2, #4] +1000c1a8: 686d ldr r5, [r5, #4] +1000c1aa: f005 0501 and.w r5, r5, #1 +1000c1ae: 46a8 mov r8, r5 +1000c1b0: bb96 cbnz r6, 1000c218 <_free_r+0xa8> +1000c1b2: f854 4c08 ldr.w r4, [r4, #-8] +1000c1b6: f101 0e08 add.w lr, r1, #8 +1000c1ba: ebac 0c04 sub.w ip, ip, r4 +1000c1be: 4423 add r3, r4 +1000c1c0: f8dc 4008 ldr.w r4, [ip, #8] +1000c1c4: 4574 cmp r4, lr +1000c1c6: d067 beq.n 1000c298 <_free_r+0x128> +1000c1c8: f8dc 500c ldr.w r5, [ip, #12] +1000c1cc: 60e5 str r5, [r4, #12] +1000c1ce: 60ac str r4, [r5, #8] +1000c1d0: f1b8 0f00 cmp.w r8, #0 +1000c1d4: f000 8088 beq.w 1000c2e8 <_free_r+0x178> +1000c1d8: f043 0001 orr.w r0, r3, #1 +1000c1dc: f8cc 0004 str.w r0, [ip, #4] +1000c1e0: 6013 str r3, [r2, #0] +1000c1e2: f5b3 7f00 cmp.w r3, #512 @ 0x200 +1000c1e6: d232 bcs.n 1000c24e <_free_r+0xde> +1000c1e8: 0958 lsrs r0, r3, #5 +1000c1ea: 08da lsrs r2, r3, #3 +1000c1ec: 2301 movs r3, #1 +1000c1ee: 4083 lsls r3, r0 +1000c1f0: 6848 ldr r0, [r1, #4] +1000c1f2: 3201 adds r2, #1 +1000c1f4: 4303 orrs r3, r0 +1000c1f6: f851 0032 ldr.w r0, [r1, r2, lsl #3] +1000c1fa: 604b str r3, [r1, #4] +1000c1fc: eb01 03c2 add.w r3, r1, r2, lsl #3 +1000c200: 3b08 subs r3, #8 +1000c202: e9cc 0302 strd r0, r3, [ip, #8] +1000c206: f841 c032 str.w ip, [r1, r2, lsl #3] +1000c20a: f8c0 c00c str.w ip, [r0, #12] +1000c20e: 4638 mov r0, r7 +1000c210: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +1000c214: f7ff bdc4 b.w 1000bda0 <__malloc_unlock> +1000c218: b985 cbnz r5, 1000c23c <_free_r+0xcc> +1000c21a: 4403 add r3, r0 +1000c21c: f101 0e08 add.w lr, r1, #8 +1000c220: 6890 ldr r0, [r2, #8] +1000c222: f043 0401 orr.w r4, r3, #1 +1000c226: 4570 cmp r0, lr +1000c228: d077 beq.n 1000c31a <_free_r+0x1aa> +1000c22a: 68d2 ldr r2, [r2, #12] +1000c22c: 60c2 str r2, [r0, #12] +1000c22e: 6090 str r0, [r2, #8] +1000c230: f8cc 4004 str.w r4, [ip, #4] +1000c234: f84c 3003 str.w r3, [ip, r3] +1000c238: e7d3 b.n 1000c1e2 <_free_r+0x72> +1000c23a: 4770 bx lr +1000c23c: f04e 0201 orr.w r2, lr, #1 +1000c240: f5b3 7f00 cmp.w r3, #512 @ 0x200 +1000c244: f844 2c04 str.w r2, [r4, #-4] +1000c248: f84c 3003 str.w r3, [ip, r3] +1000c24c: d3cc bcc.n 1000c1e8 <_free_r+0x78> +1000c24e: f5b3 6f20 cmp.w r3, #2560 @ 0xa00 +1000c252: ea4f 2253 mov.w r2, r3, lsr #9 +1000c256: d249 bcs.n 1000c2ec <_free_r+0x17c> +1000c258: 099a lsrs r2, r3, #6 +1000c25a: f102 0039 add.w r0, r2, #57 @ 0x39 +1000c25e: f102 0438 add.w r4, r2, #56 @ 0x38 +1000c262: 00c2 lsls r2, r0, #3 +1000c264: 1888 adds r0, r1, r2 +1000c266: 588a ldr r2, [r1, r2] +1000c268: 3808 subs r0, #8 +1000c26a: 4290 cmp r0, r2 +1000c26c: d103 bne.n 1000c276 <_free_r+0x106> +1000c26e: e05d b.n 1000c32c <_free_r+0x1bc> +1000c270: 6892 ldr r2, [r2, #8] +1000c272: 4290 cmp r0, r2 +1000c274: d004 beq.n 1000c280 <_free_r+0x110> +1000c276: 6851 ldr r1, [r2, #4] +1000c278: f021 0103 bic.w r1, r1, #3 +1000c27c: 4299 cmp r1, r3 +1000c27e: d8f7 bhi.n 1000c270 <_free_r+0x100> +1000c280: 68d0 ldr r0, [r2, #12] +1000c282: e9cc 2002 strd r2, r0, [ip, #8] +1000c286: f8c0 c008 str.w ip, [r0, #8] +1000c28a: 4638 mov r0, r7 +1000c28c: f8c2 c00c str.w ip, [r2, #12] +1000c290: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +1000c294: f7ff bd84 b.w 1000bda0 <__malloc_unlock> +1000c298: bb9d cbnz r5, 1000c302 <_free_r+0x192> +1000c29a: 4418 add r0, r3 +1000c29c: e9d2 2302 ldrd r2, r3, [r2, #8] +1000c2a0: 60d3 str r3, [r2, #12] +1000c2a2: 609a str r2, [r3, #8] +1000c2a4: f040 0301 orr.w r3, r0, #1 +1000c2a8: f8cc 3004 str.w r3, [ip, #4] +1000c2ac: f84c 0000 str.w r0, [ip, r0] +1000c2b0: e7ad b.n 1000c20e <_free_r+0x9e> +1000c2b2: 4418 add r0, r3 +1000c2b4: b946 cbnz r6, 1000c2c8 <_free_r+0x158> +1000c2b6: f854 3c08 ldr.w r3, [r4, #-8] +1000c2ba: ebac 0c03 sub.w ip, ip, r3 +1000c2be: 4418 add r0, r3 +1000c2c0: e9dc 2302 ldrd r2, r3, [ip, #8] +1000c2c4: 60d3 str r3, [r2, #12] +1000c2c6: 609a str r2, [r3, #8] +1000c2c8: f040 0301 orr.w r3, r0, #1 +1000c2cc: f8cc 3004 str.w r3, [ip, #4] +1000c2d0: 4b27 ldr r3, [pc, #156] @ (1000c370 <_free_r+0x200>) +1000c2d2: f8c1 c008 str.w ip, [r1, #8] +1000c2d6: 681b ldr r3, [r3, #0] +1000c2d8: 4283 cmp r3, r0 +1000c2da: d898 bhi.n 1000c20e <_free_r+0x9e> +1000c2dc: 4b25 ldr r3, [pc, #148] @ (1000c374 <_free_r+0x204>) +1000c2de: 4638 mov r0, r7 +1000c2e0: 6819 ldr r1, [r3, #0] +1000c2e2: f7ff feef bl 1000c0c4 <_malloc_trim_r> +1000c2e6: e792 b.n 1000c20e <_free_r+0x9e> +1000c2e8: 4403 add r3, r0 +1000c2ea: e799 b.n 1000c220 <_free_r+0xb0> +1000c2ec: 2a14 cmp r2, #20 +1000c2ee: d90e bls.n 1000c30e <_free_r+0x19e> +1000c2f0: 2a54 cmp r2, #84 @ 0x54 +1000c2f2: d822 bhi.n 1000c33a <_free_r+0x1ca> +1000c2f4: 0b1a lsrs r2, r3, #12 +1000c2f6: f102 006f add.w r0, r2, #111 @ 0x6f +1000c2fa: f102 046e add.w r4, r2, #110 @ 0x6e +1000c2fe: 00c2 lsls r2, r0, #3 +1000c300: e7b0 b.n 1000c264 <_free_r+0xf4> +1000c302: f043 0101 orr.w r1, r3, #1 +1000c306: f8cc 1004 str.w r1, [ip, #4] +1000c30a: 6013 str r3, [r2, #0] +1000c30c: e77f b.n 1000c20e <_free_r+0x9e> +1000c30e: f102 005c add.w r0, r2, #92 @ 0x5c +1000c312: f102 045b add.w r4, r2, #91 @ 0x5b +1000c316: 00c2 lsls r2, r0, #3 +1000c318: e7a4 b.n 1000c264 <_free_r+0xf4> +1000c31a: e9c1 cc04 strd ip, ip, [r1, #16] +1000c31e: e9cc ee02 strd lr, lr, [ip, #8] +1000c322: f8cc 4004 str.w r4, [ip, #4] +1000c326: f84c 3003 str.w r3, [ip, r3] +1000c32a: e770 b.n 1000c20e <_free_r+0x9e> +1000c32c: 10a4 asrs r4, r4, #2 +1000c32e: 2301 movs r3, #1 +1000c330: 40a3 lsls r3, r4 +1000c332: 684c ldr r4, [r1, #4] +1000c334: 4323 orrs r3, r4 +1000c336: 604b str r3, [r1, #4] +1000c338: e7a3 b.n 1000c282 <_free_r+0x112> +1000c33a: f5b2 7faa cmp.w r2, #340 @ 0x154 +1000c33e: d806 bhi.n 1000c34e <_free_r+0x1de> +1000c340: 0bda lsrs r2, r3, #15 +1000c342: f102 0078 add.w r0, r2, #120 @ 0x78 +1000c346: f102 0477 add.w r4, r2, #119 @ 0x77 +1000c34a: 00c2 lsls r2, r0, #3 +1000c34c: e78a b.n 1000c264 <_free_r+0xf4> +1000c34e: f240 5054 movw r0, #1364 @ 0x554 +1000c352: 4282 cmp r2, r0 +1000c354: d806 bhi.n 1000c364 <_free_r+0x1f4> +1000c356: 0c9a lsrs r2, r3, #18 +1000c358: f102 007d add.w r0, r2, #125 @ 0x7d +1000c35c: f102 047c add.w r4, r2, #124 @ 0x7c +1000c360: 00c2 lsls r2, r0, #3 +1000c362: e77f b.n 1000c264 <_free_r+0xf4> +1000c364: f44f 727e mov.w r2, #1016 @ 0x3f8 +1000c368: 247e movs r4, #126 @ 0x7e +1000c36a: e77b b.n 1000c264 <_free_r+0xf4> +1000c36c: 20001260 .word 0x20001260 +1000c370: 2000125c .word 0x2000125c +1000c374: 20001afc .word 0x20001afc + +1000c378 <__mutex_exit_veneer>: +1000c378: f85f f000 ldr.w pc, [pc] @ 1000c37c <__mutex_exit_veneer+0x4> +1000c37c: 20000299 .word 0x20000299 + +1000c380 <__mutex_try_enter_veneer>: +1000c380: f85f f000 ldr.w pc, [pc] @ 1000c384 <__mutex_try_enter_veneer+0x4> +1000c384: 20000111 .word 0x20000111 + +1000c388 <__reset_non_control_endpoints_veneer>: +1000c388: f85f f000 ldr.w pc, [pc] @ 1000c38c <__reset_non_control_endpoints_veneer+0x4> +1000c38c: 200002e1 .word 0x200002e1 + +1000c390 <__mutex_enter_timeout_ms_veneer>: +1000c390: f85f f000 ldr.w pc, [pc] @ 1000c394 <__mutex_enter_timeout_ms_veneer+0x4> +1000c394: 20000261 .word 0x20000261 + +1000c398 <____aeabi_uldivmod_veneer>: +1000c398: f85f f000 ldr.w pc, [pc] @ 1000c39c <____aeabi_uldivmod_veneer+0x4> +1000c39c: 20000de5 .word 0x20000de5 + +1000c3a0 <__hw_endpoint_start_next_buffer_veneer>: +1000c3a0: f85f f000 ldr.w pc, [pc] @ 1000c3a4 <__hw_endpoint_start_next_buffer_veneer+0x4> +1000c3a4: 20000b31 .word 0x20000b31 + +1000c3a8 <__e15_is_bulkin_ep_veneer>: +1000c3a8: f85f f000 ldr.w pc, [pc] @ 1000c3ac <__e15_is_bulkin_ep_veneer+0x4> +1000c3ac: 20000a8d .word 0x20000a8d + +1000c3b0 <__mutex_try_enter_block_until_veneer>: +1000c3b0: f85f f000 ldr.w pc, [pc] @ 1000c3b4 <__mutex_try_enter_block_until_veneer+0x4> +1000c3b4: 200001f9 .word 0x200001f9 + +1000c3b8 <___hw_endpoint_buffer_control_update32_veneer>: +1000c3b8: f85f f000 ldr.w pc, [pc] @ 1000c3bc <___hw_endpoint_buffer_control_update32_veneer+0x4> +1000c3bc: 20000ae9 .word 0x20000ae9 + +1000c3c0 <__e15_is_critical_frame_period_veneer>: +1000c3c0: f85f f000 ldr.w pc, [pc] @ 1000c3c4 <__e15_is_critical_frame_period_veneer+0x4> +1000c3c4: 20000ab5 .word 0x20000ab5 + +1000c3c8 <__pre_init_runtime_init_bootrom_reset>: +1000c3c8: 10001809 .... + +1000c3cc <__pre_init_runtime_init_early_resets>: +1000c3cc: 10001781 .... + +1000c3d0 <__pre_init_runtime_init_usb_power_down>: +1000c3d0: 100017b1 .... + +1000c3d4 <__pre_init_runtime_init_clocks>: +1000c3d4: 10001899 .... + +1000c3d8 <__pre_init_runtime_init_post_clock_resets>: +1000c3d8: 100017e9 .... + +1000c3dc <__pre_init_runtime_init_boot_locks_reset>: +1000c3dc: 10001709 .... + +1000c3e0 <__pre_init_runtime_init_spin_locks_reset>: +1000c3e0: 10001831 1... + +1000c3e4 <__pre_init_runtime_init_bootrom_locking_enable>: +1000c3e4: 100016f5 .... + +1000c3e8 <__pre_init_runtime_init_mutex>: +1000c3e8: 10000ac5 .... + +1000c3ec <__pre_init_runtime_init_install_ram_vector_table>: +1000c3ec: 10001835 5... + +1000c3f0 <__pre_init_runtime_init_default_alarm_pool>: +1000c3f0: 10000e81 .... + +1000c3f4 <__pre_init_first_per_core_initializer>: +1000c3f4: 10001751 Q... + +1000c3f8 <__pre_init_runtime_init_per_core_bootrom_reset>: +1000c3f8: 1000181d .... + +1000c3fc <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000c3fc: 100017cd .... + +1000c400 <__pre_init_spinlock_set_extexclall>: +1000c400: 10000695 .... + +1000c404 <__pre_init_runtime_init_per_core_irq_priorities>: +1000c404: 100006bd .... + +1000c408 <__init_array_start>: +1000c408: 10003d85 .word 0x10003d85 + +Disassembly of section .data: + +20000110 : +20000110: 4603 mov r3, r0 +20000112: b500 push {lr} +20000114: 6802 ldr r2, [r0, #0] +20000116: f3ef 8c10 mrs ip, PRIMASK +2000011a: b672 cpsid i +2000011c: e8d2 efcf ldaexb lr, [r2] +20000120: 2001 movs r0, #1 +20000122: f1be 0f00 cmp.w lr, #0 +20000126: d1f9 bne.n 2000011c +20000128: e8c2 0f4e strexb lr, r0, [r2] +2000012c: f1be 0f00 cmp.w lr, #0 +20000130: d1f4 bne.n 2000011c +20000132: f3bf 8f5f dmb sy +20000136: f993 2004 ldrsb.w r2, [r3, #4] +2000013a: 2a00 cmp r2, #0 +2000013c: db09 blt.n 20000152 +2000013e: b101 cbz r1, 20000142 +20000140: 600a str r2, [r1, #0] +20000142: 2000 movs r0, #0 +20000144: 2200 movs r2, #0 +20000146: 681b ldr r3, [r3, #0] +20000148: e8c3 2f8f stlb r2, [r3] +2000014c: f38c 8810 msr PRIMASK, ip +20000150: bd00 pop {pc} +20000152: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +20000156: 6812 ldr r2, [r2, #0] +20000158: 2001 movs r0, #1 +2000015a: 711a strb r2, [r3, #4] +2000015c: e7f2 b.n 20000144 +2000015e: bf00 nop + +20000160 : +20000160: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000164: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +20000168: 4699 mov r9, r3 +2000016a: 680b ldr r3, [r1, #0] +2000016c: 4604 mov r4, r0 +2000016e: 4617 mov r7, r2 +20000170: f04f 0800 mov.w r8, #0 +20000174: 469a mov sl, r3 +20000176: 4d1e ldr r5, [pc, #120] @ (200001f0 ) +20000178: 4e1e ldr r6, [pc, #120] @ (200001f4 ) +2000017a: 6820 ldr r0, [r4, #0] +2000017c: f3ef 8c10 mrs ip, PRIMASK +20000180: b672 cpsid i +20000182: e8d0 2fcf ldaexb r2, [r0] +20000186: 2301 movs r3, #1 +20000188: 2a00 cmp r2, #0 +2000018a: d1fa bne.n 20000182 +2000018c: e8c0 3f42 strexb r2, r3, [r0] +20000190: 2a00 cmp r2, #0 +20000192: d1f6 bne.n 20000182 +20000194: f3bf 8f5f dmb sy +20000198: f994 2004 ldrsb.w r2, [r4, #4] +2000019c: 6823 ldr r3, [r4, #0] +2000019e: 2a00 cmp r2, #0 +200001a0: db1b blt.n 200001da +200001a2: 7828 ldrb r0, [r5, #0] +200001a4: b2c0 uxtb r0, r0 +200001a6: e8c3 8f8f stlb r8, [r3] +200001aa: bf20 wfe +200001ac: f38c 8810 msr PRIMASK, ip +200001b0: 782b ldrb r3, [r5, #0] +200001b2: 4283 cmp r3, r0 +200001b4: d00a beq.n 200001cc +200001b6: 6a73 ldr r3, [r6, #36] @ 0x24 +200001b8: 4599 cmp r9, r3 +200001ba: d8de bhi.n 2000017a +200001bc: 6ab2 ldr r2, [r6, #40] @ 0x28 +200001be: 42ba cmp r2, r7 +200001c0: d201 bcs.n 200001c6 +200001c2: 4599 cmp r9, r3 +200001c4: d0d9 beq.n 2000017a +200001c6: 2000 movs r0, #0 +200001c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +200001cc: 4638 mov r0, r7 +200001ce: 4649 mov r1, r9 +200001d0: f000 ffc6 bl 20001160 <__best_effort_wfe_or_timeout_veneer> +200001d4: 2800 cmp r0, #0 +200001d6: d0d0 beq.n 2000017a +200001d8: e7f5 b.n 200001c6 +200001da: 2200 movs r2, #0 +200001dc: f884 a004 strb.w sl, [r4, #4] +200001e0: e8c3 2f8f stlb r2, [r3] +200001e4: f38c 8810 msr PRIMASK, ip +200001e8: 2001 movs r0, #1 +200001ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +200001ee: bf00 nop +200001f0: 2000253f .word 0x2000253f +200001f4: 400b0000 .word 0x400b0000 + +200001f8 : +200001f8: b510 push {r4, lr} +200001fa: 6801 ldr r1, [r0, #0] +200001fc: f3ef 8e10 mrs lr, PRIMASK +20000200: b672 cpsid i +20000202: e8d1 cfcf ldaexb ip, [r1] +20000206: 2401 movs r4, #1 +20000208: f1bc 0f00 cmp.w ip, #0 +2000020c: d1f9 bne.n 20000202 +2000020e: e8c1 4f4c strexb ip, r4, [r1] +20000212: f1bc 0f00 cmp.w ip, #0 +20000216: d1f4 bne.n 20000202 +20000218: f3bf 8f5f dmb sy +2000021c: f990 c004 ldrsb.w ip, [r0, #4] +20000220: 6804 ldr r4, [r0, #0] +20000222: f1bc 0f00 cmp.w ip, #0 +20000226: db10 blt.n 2000024a +20000228: 2100 movs r1, #0 +2000022a: e8c4 1f8f stlb r1, [r4] +2000022e: f38e 8810 msr PRIMASK, lr +20000232: f04f 4450 mov.w r4, #3489660928 @ 0xd0000000 +20000236: f994 4000 ldrsb.w r4, [r4] +2000023a: 4564 cmp r4, ip +2000023c: d101 bne.n 20000242 +2000023e: 4608 mov r0, r1 +20000240: bd10 pop {r4, pc} +20000242: e8bd 4010 ldmia.w sp!, {r4, lr} +20000246: f7ff bf8b b.w 20000160 +2000024a: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +2000024e: 6812 ldr r2, [r2, #0] +20000250: 2300 movs r3, #0 +20000252: 7102 strb r2, [r0, #4] +20000254: e8c4 3f8f stlb r3, [r4] +20000258: f38e 8810 msr PRIMASK, lr +2000025c: 2001 movs r0, #1 +2000025e: bd10 pop {r4, pc} + +20000260 : +20000260: b570 push {r4, r5, r6, lr} +20000262: 4605 mov r5, r0 +20000264: 460c mov r4, r1 +20000266: f000 ff77 bl 20001158 <__time_us_64_veneer> +2000026a: 4602 mov r2, r0 +2000026c: 460b mov r3, r1 +2000026e: f44f 707a mov.w r0, #1000 @ 0x3e8 +20000272: f04f 3eff mov.w lr, #4294967295 @ 0xffffffff +20000276: f06f 4c00 mvn.w ip, #2147483648 @ 0x80000000 +2000027a: fbe4 2300 umlal r2, r3, r4, r0 +2000027e: 4596 cmp lr, r2 +20000280: eb7c 0103 sbcs.w r1, ip, r3 +20000284: bf38 it cc +20000286: 4672 movcc r2, lr +20000288: 4628 mov r0, r5 +2000028a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} +2000028e: bf38 it cc +20000290: 4663 movcc r3, ip +20000292: f7ff bf65 b.w 20000160 +20000296: bf00 nop + +20000298 : +20000298: 6803 ldr r3, [r0, #0] +2000029a: f3ef 8110 mrs r1, PRIMASK +2000029e: b672 cpsid i +200002a0: e8d3 cfcf ldaexb ip, [r3] +200002a4: 2201 movs r2, #1 +200002a6: f1bc 0f00 cmp.w ip, #0 +200002aa: d1f9 bne.n 200002a0 +200002ac: e8c3 2f4c strexb ip, r2, [r3] +200002b0: f1bc 0f00 cmp.w ip, #0 +200002b4: d1f4 bne.n 200002a0 +200002b6: f3bf 8f5f dmb sy +200002ba: f04f 0cff mov.w ip, #255 @ 0xff +200002be: 4a07 ldr r2, [pc, #28] @ (200002dc ) +200002c0: f880 c004 strb.w ip, [r0, #4] +200002c4: 7813 ldrb r3, [r2, #0] +200002c6: 3301 adds r3, #1 +200002c8: 7013 strb r3, [r2, #0] +200002ca: 2300 movs r3, #0 +200002cc: 6802 ldr r2, [r0, #0] +200002ce: e8c2 3f8f stlb r3, [r2] +200002d2: f381 8810 msr PRIMASK, r1 +200002d6: bf40 sev +200002d8: 4770 bx lr +200002da: bf00 nop +200002dc: 2000253f .word 0x2000253f + +200002e0 : +200002e0: 2100 movs r1, #0 +200002e2: b508 push {r3, lr} +200002e4: 4b13 ldr r3, [pc, #76] @ (20000334 ) +200002e6: f44f 7270 mov.w r2, #960 @ 0x3c0 +200002ea: 6099 str r1, [r3, #8] +200002ec: 4812 ldr r0, [pc, #72] @ (20000338 ) +200002ee: 60d9 str r1, [r3, #12] +200002f0: 6119 str r1, [r3, #16] +200002f2: 6159 str r1, [r3, #20] +200002f4: 6199 str r1, [r3, #24] +200002f6: 61d9 str r1, [r3, #28] +200002f8: 6219 str r1, [r3, #32] +200002fa: 6259 str r1, [r3, #36] @ 0x24 +200002fc: 6299 str r1, [r3, #40] @ 0x28 +200002fe: 62d9 str r1, [r3, #44] @ 0x2c +20000300: 6319 str r1, [r3, #48] @ 0x30 +20000302: 6359 str r1, [r3, #52] @ 0x34 +20000304: 6399 str r1, [r3, #56] @ 0x38 +20000306: 63d9 str r1, [r3, #60] @ 0x3c +20000308: 6419 str r1, [r3, #64] @ 0x40 +2000030a: 6459 str r1, [r3, #68] @ 0x44 +2000030c: 6499 str r1, [r3, #72] @ 0x48 +2000030e: 64d9 str r1, [r3, #76] @ 0x4c +20000310: 6519 str r1, [r3, #80] @ 0x50 +20000312: 6559 str r1, [r3, #84] @ 0x54 +20000314: 6599 str r1, [r3, #88] @ 0x58 +20000316: 65d9 str r1, [r3, #92] @ 0x5c +20000318: 6619 str r1, [r3, #96] @ 0x60 +2000031a: 6659 str r1, [r3, #100] @ 0x64 +2000031c: 6699 str r1, [r3, #104] @ 0x68 +2000031e: 66d9 str r1, [r3, #108] @ 0x6c +20000320: 6719 str r1, [r3, #112] @ 0x70 +20000322: 6759 str r1, [r3, #116] @ 0x74 +20000324: 6799 str r1, [r3, #120] @ 0x78 +20000326: 67d9 str r1, [r3, #124] @ 0x7c +20000328: f000 ff26 bl 20001178 <__memset_veneer> +2000032c: 4b03 ldr r3, [pc, #12] @ (2000033c ) +2000032e: 4a04 ldr r2, [pc, #16] @ (20000340 ) +20000330: 601a str r2, [r3, #0] +20000332: bd08 pop {r3, pc} +20000334: 50100000 .word 0x50100000 +20000338: 20002124 .word 0x20002124 +2000033c: 200024ec .word 0x200024ec +20000340: 50100180 .word 0x50100180 + +20000344 : +20000344: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +20000348: 4b1e ldr r3, [pc, #120] @ (200003c4 ) +2000034a: b084 sub sp, #16 +2000034c: f8d3 a058 ldr.w sl, [r3, #88] @ 0x58 +20000350: f1ba 0f00 cmp.w sl, #0 +20000354: d021 beq.n 2000039a +20000356: 2400 movs r4, #0 +20000358: 2501 movs r5, #1 +2000035a: f44f 69e0 mov.w r9, #1792 @ 0x700 +2000035e: f8df 806c ldr.w r8, [pc, #108] @ 200003cc +20000362: 4f19 ldr r7, [pc, #100] @ (200003c8 ) +20000364: e005 b.n 20000372 +20000366: 3401 adds r4, #1 +20000368: b2e4 uxtb r4, r4 +2000036a: 2c20 cmp r4, #32 +2000036c: ea4f 0545 mov.w r5, r5, lsl #1 +20000370: d013 beq.n 2000039a +20000372: ea1a 0f05 tst.w sl, r5 +20000376: d0f6 beq.n 20000366 +20000378: 43e3 mvns r3, r4 +2000037a: f004 06fe and.w r6, r4, #254 @ 0xfe +2000037e: f003 0301 and.w r3, r3, #1 +20000382: 441e add r6, r3 +20000384: eb07 1646 add.w r6, r7, r6, lsl #5 +20000388: 4630 mov r0, r6 +2000038a: f8c8 5058 str.w r5, [r8, #88] @ 0x58 +2000038e: f000 fc01 bl 20000b94 +20000392: b928 cbnz r0, 200003a0 +20000394: ea3a 0a05 bics.w sl, sl, r5 +20000398: d1e5 bne.n 20000366 +2000039a: b004 add sp, #16 +2000039c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +200003a0: 78b3 ldrb r3, [r6, #2] +200003a2: 8af2 ldrh r2, [r6, #22] +200003a4: f88d 3008 strb.w r3, [sp, #8] +200003a8: 2300 movs r3, #0 +200003aa: a801 add r0, sp, #4 +200003ac: 2101 movs r1, #1 +200003ae: f8ad 9004 strh.w r9, [sp, #4] +200003b2: 9203 str r2, [sp, #12] +200003b4: f88d 3009 strb.w r3, [sp, #9] +200003b8: f000 fc0a bl 20000bd0 +200003bc: 4630 mov r0, r6 +200003be: f000 fb8d bl 20000adc +200003c2: e7e7 b.n 20000394 +200003c4: 50110000 .word 0x50110000 +200003c8: 200020e4 .word 0x200020e4 +200003cc: 50113000 .word 0x50113000 + +200003d0 : +200003d0: b570 push {r4, r5, r6, lr} +200003d2: 4bb2 ldr r3, [pc, #712] @ (2000069c ) +200003d4: b086 sub sp, #24 +200003d6: f8d3 4098 ldr.w r4, [r3, #152] @ 0x98 +200003da: f414 3500 ands.w r5, r4, #131072 @ 0x20000 +200003de: d074 beq.n 200004ca +200003e0: 4aaf ldr r2, [pc, #700] @ (200006a0 ) +200003e2: 4bb0 ldr r3, [pc, #704] @ (200006a4 ) +200003e4: 6a90 ldr r0, [r2, #40] @ 0x28 +200003e6: f893 203b ldrb.w r2, [r3, #59] @ 0x3b +200003ea: 49af ldr r1, [pc, #700] @ (200006a8 ) +200003ec: 2a02 cmp r2, #2 +200003ee: 6008 str r0, [r1, #0] +200003f0: f000 80e6 beq.w 200005c0 +200003f4: 2500 movs r5, #0 +200003f6: f893 207b ldrb.w r2, [r3, #123] @ 0x7b +200003fa: 2a02 cmp r2, #2 +200003fc: f000 81b2 beq.w 20000764 +20000400: f893 20bb ldrb.w r2, [r3, #187] @ 0xbb +20000404: 2a02 cmp r2, #2 +20000406: f000 81a2 beq.w 2000074e +2000040a: f893 20fb ldrb.w r2, [r3, #251] @ 0xfb +2000040e: 2a02 cmp r2, #2 +20000410: f000 8192 beq.w 20000738 +20000414: f893 213b ldrb.w r2, [r3, #315] @ 0x13b +20000418: 2a02 cmp r2, #2 +2000041a: f000 8181 beq.w 20000720 +2000041e: f893 217b ldrb.w r2, [r3, #379] @ 0x17b +20000422: 2a02 cmp r2, #2 +20000424: f000 8171 beq.w 2000070a +20000428: f893 21bb ldrb.w r2, [r3, #443] @ 0x1bb +2000042c: 2a02 cmp r2, #2 +2000042e: f000 8161 beq.w 200006f4 +20000432: f893 21fb ldrb.w r2, [r3, #507] @ 0x1fb +20000436: 2a02 cmp r2, #2 +20000438: f000 8150 beq.w 200006dc +2000043c: f893 223b ldrb.w r2, [r3, #571] @ 0x23b +20000440: 2a02 cmp r2, #2 +20000442: f000 813f beq.w 200006c4 +20000446: f893 227b ldrb.w r2, [r3, #635] @ 0x27b +2000044a: 2a02 cmp r2, #2 +2000044c: f000 811a beq.w 20000684 +20000450: f893 22bb ldrb.w r2, [r3, #699] @ 0x2bb +20000454: 2a02 cmp r2, #2 +20000456: f000 8109 beq.w 2000066c +2000045a: f893 22fb ldrb.w r2, [r3, #763] @ 0x2fb +2000045e: 2a02 cmp r2, #2 +20000460: f000 80f8 beq.w 20000654 +20000464: f893 233b ldrb.w r2, [r3, #827] @ 0x33b +20000468: 2a02 cmp r2, #2 +2000046a: f000 80e7 beq.w 2000063c +2000046e: f893 237b ldrb.w r2, [r3, #891] @ 0x37b +20000472: 2a02 cmp r2, #2 +20000474: f000 80b7 beq.w 200005e6 +20000478: f893 23bb ldrb.w r2, [r3, #955] @ 0x3bb +2000047c: 2a02 cmp r2, #2 +2000047e: f000 817c beq.w 2000077a +20000482: f893 23fb ldrb.w r2, [r3, #1019] @ 0x3fb +20000486: 2a02 cmp r2, #2 +20000488: f000 80c7 beq.w 2000061a +2000048c: b93d cbnz r5, 2000049e +2000048e: 4b87 ldr r3, [pc, #540] @ (200006ac ) +20000490: 781b ldrb r3, [r3, #0] +20000492: b923 cbnz r3, 2000049e +20000494: f44f 3200 mov.w r2, #131072 @ 0x20000 +20000498: 4b85 ldr r3, [pc, #532] @ (200006b0 ) +2000049a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 +2000049e: f44f 7240 mov.w r2, #768 @ 0x300 +200004a2: 4b7e ldr r3, [pc, #504] @ (2000069c ) +200004a4: 2101 movs r1, #1 +200004a6: 6c9b ldr r3, [r3, #72] @ 0x48 +200004a8: a803 add r0, sp, #12 +200004aa: f3c3 030a ubfx r3, r3, #0, #11 +200004ae: 9304 str r3, [sp, #16] +200004b0: f8ad 200c strh.w r2, [sp, #12] +200004b4: f000 fb8c bl 20000bd0 +200004b8: 06e3 lsls r3, r4, #27 +200004ba: f44f 3500 mov.w r5, #131072 @ 0x20000 +200004be: 4e7d ldr r6, [pc, #500] @ (200006b4 ) +200004c0: d507 bpl.n 200004d2 +200004c2: f7ff ff3f bl 20000344 +200004c6: 4635 mov r5, r6 +200004c8: e003 b.n 200004d2 +200004ca: 06e3 lsls r3, r4, #27 +200004cc: f04f 0610 mov.w r6, #16 +200004d0: d4f7 bmi.n 200004c2 +200004d2: 03e0 lsls r0, r4, #15 +200004d4: d51d bpl.n 20000512 +200004d6: 4873 ldr r0, [pc, #460] @ (200006a4 ) +200004d8: 2602 movs r6, #2 +200004da: 7e83 ldrb r3, [r0, #26] +200004dc: f445 3580 orr.w r5, r5, #65536 @ 0x10000 +200004e0: bb33 cbnz r3, 20000530 +200004e2: f04f 0301 mov.w r3, #1 +200004e6: 2e01 cmp r6, #1 +200004e8: 70c3 strb r3, [r0, #3] +200004ea: f100 0020 add.w r0, r0, #32 +200004ee: d11b bne.n 20000528 +200004f0: f44f 62c0 mov.w r2, #1536 @ 0x600 +200004f4: 4b70 ldr r3, [pc, #448] @ (200006b8 ) +200004f6: f8ad 200c strh.w r2, [sp, #12] +200004fa: e893 0003 ldmia.w r3, {r0, r1} +200004fe: e9cd 0104 strd r0, r1, [sp, #16] +20000502: 4631 mov r1, r6 +20000504: a803 add r0, sp, #12 +20000506: f000 fb63 bl 20000bd0 +2000050a: f44f 3200 mov.w r2, #131072 @ 0x20000 +2000050e: 4b68 ldr r3, [pc, #416] @ (200006b0 ) +20000510: 651a str r2, [r3, #80] @ 0x50 +20000512: 04e1 lsls r1, r4, #19 +20000514: d43e bmi.n 20000594 +20000516: 0462 lsls r2, r4, #17 +20000518: d42e bmi.n 20000578 +2000051a: 0423 lsls r3, r4, #16 +2000051c: d41d bmi.n 2000055a +2000051e: 42a5 cmp r5, r4 +20000520: f040 81bb bne.w 2000089a +20000524: b006 add sp, #24 +20000526: bd70 pop {r4, r5, r6, pc} +20000528: 7e83 ldrb r3, [r0, #26] +2000052a: 2601 movs r6, #1 +2000052c: 2b00 cmp r3, #0 +2000052e: d0d8 beq.n 200004e2 +20000530: 4b62 ldr r3, [pc, #392] @ (200006bc ) +20000532: 4a5a ldr r2, [pc, #360] @ (2000069c ) +20000534: 661e str r6, [r3, #96] @ 0x60 +20000536: 6e53 ldr r3, [r2, #100] @ 0x64 +20000538: ea36 0303 bics.w r3, r6, r3 +2000053c: d1fb bne.n 20000536 +2000053e: f44f 5240 mov.w r2, #12288 @ 0x3000 +20000542: 2100 movs r1, #0 +20000544: 9001 str r0, [sp, #4] +20000546: f000 facf bl 20000ae8 <_hw_endpoint_buffer_control_update32> +2000054a: 9801 ldr r0, [sp, #4] +2000054c: f000 fac6 bl 20000adc +20000550: 4b57 ldr r3, [pc, #348] @ (200006b0 ) +20000552: 9801 ldr r0, [sp, #4] +20000554: 665e str r6, [r3, #100] @ 0x64 +20000556: 661e str r6, [r3, #96] @ 0x60 +20000558: e7c3 b.n 200004e2 +2000055a: f44f 63a0 mov.w r3, #1280 @ 0x500 +2000055e: 2101 movs r1, #1 +20000560: a803 add r0, sp, #12 +20000562: f8ad 300c strh.w r3, [sp, #12] +20000566: f000 fb33 bl 20000bd0 +2000056a: f44f 6200 mov.w r2, #2048 @ 0x800 +2000056e: 4b50 ldr r3, [pc, #320] @ (200006b0 ) +20000570: f445 4500 orr.w r5, r5, #32768 @ 0x8000 +20000574: 651a str r2, [r3, #80] @ 0x50 +20000576: e7d2 b.n 2000051e +20000578: f44f 6380 mov.w r3, #1024 @ 0x400 +2000057c: 2101 movs r1, #1 +2000057e: a803 add r0, sp, #12 +20000580: f8ad 300c strh.w r3, [sp, #12] +20000584: f000 fb24 bl 20000bd0 +20000588: 2210 movs r2, #16 +2000058a: 4b49 ldr r3, [pc, #292] @ (200006b0 ) +2000058c: f445 4580 orr.w r5, r5, #16384 @ 0x4000 +20000590: 651a str r2, [r3, #80] @ 0x50 +20000592: e7c2 b.n 2000051a +20000594: 2600 movs r6, #0 +20000596: 4b41 ldr r3, [pc, #260] @ (2000069c ) +20000598: f445 5580 orr.w r5, r5, #4096 @ 0x1000 +2000059c: 601e str r6, [r3, #0] +2000059e: f7ff fe9f bl 200002e0 +200005a2: f44f 7380 mov.w r3, #256 @ 0x100 +200005a6: 2101 movs r1, #1 +200005a8: a803 add r0, sp, #12 +200005aa: f8ad 300c strh.w r3, [sp, #12] +200005ae: f88d 6010 strb.w r6, [sp, #16] +200005b2: f000 fb0d bl 20000bd0 +200005b6: f44f 2200 mov.w r2, #524288 @ 0x80000 +200005ba: 4b3d ldr r3, [pc, #244] @ (200006b0 ) +200005bc: 651a str r2, [r3, #80] @ 0x50 +200005be: e7aa b.n 20000516 +200005c0: f893 503a ldrb.w r5, [r3, #58] @ 0x3a +200005c4: 2d00 cmp r5, #0 +200005c6: f43f af16 beq.w 200003f6 +200005ca: f893 203c ldrb.w r2, [r3, #60] @ 0x3c +200005ce: 2a00 cmp r2, #0 +200005d0: f43f af11 beq.w 200003f6 +200005d4: 2200 movs r2, #0 +200005d6: f103 0020 add.w r0, r3, #32 +200005da: f883 203c strb.w r2, [r3, #60] @ 0x3c +200005de: f000 faa7 bl 20000b30 +200005e2: 4b30 ldr r3, [pc, #192] @ (200006a4 ) +200005e4: e707 b.n 200003f6 +200005e6: f893 637a ldrb.w r6, [r3, #890] @ 0x37a +200005ea: 2e00 cmp r6, #0 +200005ec: f43f af44 beq.w 20000478 +200005f0: f893 237c ldrb.w r2, [r3, #892] @ 0x37c +200005f4: 2a00 cmp r2, #0 +200005f6: f040 8140 bne.w 2000087a +200005fa: f893 23bb ldrb.w r2, [r3, #955] @ 0x3bb +200005fe: 2a02 cmp r2, #2 +20000600: f040 80c4 bne.w 2000078c +20000604: f893 23ba ldrb.w r2, [r3, #954] @ 0x3ba +20000608: 2a00 cmp r2, #0 +2000060a: f040 80bb bne.w 20000784 +2000060e: f893 23fb ldrb.w r2, [r3, #1019] @ 0x3fb +20000612: 2a02 cmp r2, #2 +20000614: f47f af43 bne.w 2000049e +20000618: 4635 mov r5, r6 +2000061a: f893 23fa ldrb.w r2, [r3, #1018] @ 0x3fa +2000061e: 2a00 cmp r2, #0 +20000620: f43f af34 beq.w 2000048c +20000624: f893 23fc ldrb.w r2, [r3, #1020] @ 0x3fc +20000628: 2a00 cmp r2, #0 +2000062a: f43f af38 beq.w 2000049e +2000062e: 2200 movs r2, #0 +20000630: 4823 ldr r0, [pc, #140] @ (200006c0 ) +20000632: f883 23fc strb.w r2, [r3, #1020] @ 0x3fc +20000636: f000 fa7b bl 20000b30 +2000063a: e730 b.n 2000049e +2000063c: f893 633a ldrb.w r6, [r3, #826] @ 0x33a +20000640: 2e00 cmp r6, #0 +20000642: f43f af14 beq.w 2000046e +20000646: f893 233c ldrb.w r2, [r3, #828] @ 0x33c +2000064a: 2a00 cmp r2, #0 +2000064c: f040 80a9 bne.w 200007a2 +20000650: 4635 mov r5, r6 +20000652: e70c b.n 2000046e +20000654: f893 62fa ldrb.w r6, [r3, #762] @ 0x2fa +20000658: 2e00 cmp r6, #0 +2000065a: f43f af03 beq.w 20000464 +2000065e: f893 22fc ldrb.w r2, [r3, #764] @ 0x2fc +20000662: 2a00 cmp r2, #0 +20000664: f040 80af bne.w 200007c6 +20000668: 4635 mov r5, r6 +2000066a: e6fb b.n 20000464 +2000066c: f893 62ba ldrb.w r6, [r3, #698] @ 0x2ba +20000670: 2e00 cmp r6, #0 +20000672: f43f aef2 beq.w 2000045a +20000676: f893 22bc ldrb.w r2, [r3, #700] @ 0x2bc +2000067a: 2a00 cmp r2, #0 +2000067c: f040 809a bne.w 200007b4 +20000680: 4635 mov r5, r6 +20000682: e6ea b.n 2000045a +20000684: f893 627a ldrb.w r6, [r3, #634] @ 0x27a +20000688: 2e00 cmp r6, #0 +2000068a: f43f aee1 beq.w 20000450 +2000068e: f893 227c ldrb.w r2, [r3, #636] @ 0x27c +20000692: 2a00 cmp r2, #0 +20000694: f040 80cd bne.w 20000832 +20000698: 4635 mov r5, r6 +2000069a: e6d9 b.n 20000450 +2000069c: 50110000 .word 0x50110000 +200006a0: 400b0000 .word 0x400b0000 +200006a4: 200020e4 .word 0x200020e4 +200006a8: 20001ec0 .word 0x20001ec0 +200006ac: 2000253a .word 0x2000253a +200006b0: 50113000 .word 0x50113000 +200006b4: 00020010 .word 0x00020010 +200006b8: 50100000 .word 0x50100000 +200006bc: 50112000 .word 0x50112000 +200006c0: 200024c4 .word 0x200024c4 +200006c4: f893 623a ldrb.w r6, [r3, #570] @ 0x23a +200006c8: 2e00 cmp r6, #0 +200006ca: f43f aebc beq.w 20000446 +200006ce: f893 223c ldrb.w r2, [r3, #572] @ 0x23c +200006d2: 2a00 cmp r2, #0 +200006d4: f040 80a4 bne.w 20000820 +200006d8: 4635 mov r5, r6 +200006da: e6b4 b.n 20000446 +200006dc: f893 61fa ldrb.w r6, [r3, #506] @ 0x1fa +200006e0: 2e00 cmp r6, #0 +200006e2: f43f aeab beq.w 2000043c +200006e6: f893 21fc ldrb.w r2, [r3, #508] @ 0x1fc +200006ea: 2a00 cmp r2, #0 +200006ec: f040 808f bne.w 2000080e +200006f0: 4635 mov r5, r6 +200006f2: e6a3 b.n 2000043c +200006f4: f893 61ba ldrb.w r6, [r3, #442] @ 0x1ba +200006f8: 2e00 cmp r6, #0 +200006fa: f43f ae9a beq.w 20000432 +200006fe: f893 21bc ldrb.w r2, [r3, #444] @ 0x1bc +20000702: 2a00 cmp r2, #0 +20000704: d17a bne.n 200007fc +20000706: 4635 mov r5, r6 +20000708: e693 b.n 20000432 +2000070a: f893 617a ldrb.w r6, [r3, #378] @ 0x17a +2000070e: 2e00 cmp r6, #0 +20000710: f43f ae8a beq.w 20000428 +20000714: f893 217c ldrb.w r2, [r3, #380] @ 0x17c +20000718: 2a00 cmp r2, #0 +2000071a: d166 bne.n 200007ea +2000071c: 4635 mov r5, r6 +2000071e: e683 b.n 20000428 +20000720: f893 613a ldrb.w r6, [r3, #314] @ 0x13a +20000724: 2e00 cmp r6, #0 +20000726: f43f ae7a beq.w 2000041e +2000072a: f893 213c ldrb.w r2, [r3, #316] @ 0x13c +2000072e: 2a00 cmp r2, #0 +20000730: f040 8091 bne.w 20000856 +20000734: 4635 mov r5, r6 +20000736: e672 b.n 2000041e +20000738: f893 60fa ldrb.w r6, [r3, #250] @ 0xfa +2000073c: 2e00 cmp r6, #0 +2000073e: f43f ae69 beq.w 20000414 +20000742: f893 20fc ldrb.w r2, [r3, #252] @ 0xfc +20000746: 2a00 cmp r2, #0 +20000748: d17c bne.n 20000844 +2000074a: 4635 mov r5, r6 +2000074c: e662 b.n 20000414 +2000074e: f893 60ba ldrb.w r6, [r3, #186] @ 0xba +20000752: 2e00 cmp r6, #0 +20000754: f43f ae59 beq.w 2000040a +20000758: f893 20bc ldrb.w r2, [r3, #188] @ 0xbc +2000075c: 2a00 cmp r2, #0 +2000075e: d13b bne.n 200007d8 +20000760: 4635 mov r5, r6 +20000762: e652 b.n 2000040a +20000764: f893 607a ldrb.w r6, [r3, #122] @ 0x7a +20000768: 2e00 cmp r6, #0 +2000076a: f43f ae49 beq.w 20000400 +2000076e: f893 207c ldrb.w r2, [r3, #124] @ 0x7c +20000772: 2a00 cmp r2, #0 +20000774: d178 bne.n 20000868 +20000776: 4635 mov r5, r6 +20000778: e642 b.n 20000400 +2000077a: f893 23ba ldrb.w r2, [r3, #954] @ 0x3ba +2000077e: 2a00 cmp r2, #0 +20000780: f43f ae7f beq.w 20000482 +20000784: f893 23bc ldrb.w r2, [r3, #956] @ 0x3bc +20000788: 2a00 cmp r2, #0 +2000078a: d17e bne.n 2000088a +2000078c: f893 23fb ldrb.w r2, [r3, #1019] @ 0x3fb +20000790: 2a02 cmp r2, #2 +20000792: f47f ae84 bne.w 2000049e +20000796: f893 23fa ldrb.w r2, [r3, #1018] @ 0x3fa +2000079a: 2a00 cmp r2, #0 +2000079c: f43f ae7f beq.w 2000049e +200007a0: e740 b.n 20000624 +200007a2: 2200 movs r2, #0 +200007a4: 483f ldr r0, [pc, #252] @ (200008a4 ) +200007a6: f883 233c strb.w r2, [r3, #828] @ 0x33c +200007aa: 4635 mov r5, r6 +200007ac: f000 f9c0 bl 20000b30 +200007b0: 4b3d ldr r3, [pc, #244] @ (200008a8 ) +200007b2: e65c b.n 2000046e +200007b4: 2200 movs r2, #0 +200007b6: 483d ldr r0, [pc, #244] @ (200008ac ) +200007b8: f883 22bc strb.w r2, [r3, #700] @ 0x2bc +200007bc: 4635 mov r5, r6 +200007be: f000 f9b7 bl 20000b30 +200007c2: 4b39 ldr r3, [pc, #228] @ (200008a8 ) +200007c4: e649 b.n 2000045a +200007c6: 2200 movs r2, #0 +200007c8: 4839 ldr r0, [pc, #228] @ (200008b0 ) +200007ca: f883 22fc strb.w r2, [r3, #764] @ 0x2fc +200007ce: 4635 mov r5, r6 +200007d0: f000 f9ae bl 20000b30 +200007d4: 4b34 ldr r3, [pc, #208] @ (200008a8 ) +200007d6: e645 b.n 20000464 +200007d8: 2200 movs r2, #0 +200007da: 4836 ldr r0, [pc, #216] @ (200008b4 ) +200007dc: f883 20bc strb.w r2, [r3, #188] @ 0xbc +200007e0: 4635 mov r5, r6 +200007e2: f000 f9a5 bl 20000b30 +200007e6: 4b30 ldr r3, [pc, #192] @ (200008a8 ) +200007e8: e60f b.n 2000040a +200007ea: 2200 movs r2, #0 +200007ec: 4832 ldr r0, [pc, #200] @ (200008b8 ) +200007ee: f883 217c strb.w r2, [r3, #380] @ 0x17c +200007f2: 4635 mov r5, r6 +200007f4: f000 f99c bl 20000b30 +200007f8: 4b2b ldr r3, [pc, #172] @ (200008a8 ) +200007fa: e615 b.n 20000428 +200007fc: 2200 movs r2, #0 +200007fe: 482f ldr r0, [pc, #188] @ (200008bc ) +20000800: f883 21bc strb.w r2, [r3, #444] @ 0x1bc +20000804: 4635 mov r5, r6 +20000806: f000 f993 bl 20000b30 +2000080a: 4b27 ldr r3, [pc, #156] @ (200008a8 ) +2000080c: e611 b.n 20000432 +2000080e: 2200 movs r2, #0 +20000810: 482b ldr r0, [pc, #172] @ (200008c0 ) +20000812: f883 21fc strb.w r2, [r3, #508] @ 0x1fc +20000816: 4635 mov r5, r6 +20000818: f000 f98a bl 20000b30 +2000081c: 4b22 ldr r3, [pc, #136] @ (200008a8 ) +2000081e: e60d b.n 2000043c +20000820: 2200 movs r2, #0 +20000822: 4828 ldr r0, [pc, #160] @ (200008c4 ) +20000824: f883 223c strb.w r2, [r3, #572] @ 0x23c +20000828: 4635 mov r5, r6 +2000082a: f000 f981 bl 20000b30 +2000082e: 4b1e ldr r3, [pc, #120] @ (200008a8 ) +20000830: e609 b.n 20000446 +20000832: 2200 movs r2, #0 +20000834: 4824 ldr r0, [pc, #144] @ (200008c8 ) +20000836: f883 227c strb.w r2, [r3, #636] @ 0x27c +2000083a: 4635 mov r5, r6 +2000083c: f000 f978 bl 20000b30 +20000840: 4b19 ldr r3, [pc, #100] @ (200008a8 ) +20000842: e605 b.n 20000450 +20000844: 2200 movs r2, #0 +20000846: 4821 ldr r0, [pc, #132] @ (200008cc ) +20000848: f883 20fc strb.w r2, [r3, #252] @ 0xfc +2000084c: 4635 mov r5, r6 +2000084e: f000 f96f bl 20000b30 +20000852: 4b15 ldr r3, [pc, #84] @ (200008a8 ) +20000854: e5de b.n 20000414 +20000856: 2200 movs r2, #0 +20000858: 481d ldr r0, [pc, #116] @ (200008d0 ) +2000085a: f883 213c strb.w r2, [r3, #316] @ 0x13c +2000085e: 4635 mov r5, r6 +20000860: f000 f966 bl 20000b30 +20000864: 4b10 ldr r3, [pc, #64] @ (200008a8 ) +20000866: e5da b.n 2000041e +20000868: 2200 movs r2, #0 +2000086a: 481a ldr r0, [pc, #104] @ (200008d4 ) +2000086c: f883 207c strb.w r2, [r3, #124] @ 0x7c +20000870: 4635 mov r5, r6 +20000872: f000 f95d bl 20000b30 +20000876: 4b0c ldr r3, [pc, #48] @ (200008a8 ) +20000878: e5c2 b.n 20000400 +2000087a: 2200 movs r2, #0 +2000087c: 4816 ldr r0, [pc, #88] @ (200008d8 ) +2000087e: f883 237c strb.w r2, [r3, #892] @ 0x37c +20000882: f000 f955 bl 20000b30 +20000886: 4b08 ldr r3, [pc, #32] @ (200008a8 ) +20000888: e6b7 b.n 200005fa +2000088a: 2200 movs r2, #0 +2000088c: 4813 ldr r0, [pc, #76] @ (200008dc ) +2000088e: f883 23bc strb.w r2, [r3, #956] @ 0x3bc +20000892: f000 f94d bl 20000b30 +20000896: 4b04 ldr r3, [pc, #16] @ (200008a8 ) +20000898: e778 b.n 2000078c +2000089a: 4811 ldr r0, [pc, #68] @ (200008e0 ) +2000089c: ea85 0104 eor.w r1, r5, r4 +200008a0: f000 fc62 bl 20001168 <__panic_veneer> +200008a4: 20002404 .word 0x20002404 +200008a8: 200020e4 .word 0x200020e4 +200008ac: 20002384 .word 0x20002384 +200008b0: 200023c4 .word 0x200023c4 +200008b4: 20002184 .word 0x20002184 +200008b8: 20002244 .word 0x20002244 +200008bc: 20002284 .word 0x20002284 +200008c0: 200022c4 .word 0x200022c4 +200008c4: 20002304 .word 0x20002304 +200008c8: 20002344 .word 0x20002344 +200008cc: 200021c4 .word 0x200021c4 +200008d0: 20002204 .word 0x20002204 +200008d4: 20002144 .word 0x20002144 +200008d8: 20002444 .word 0x20002444 +200008dc: 20002484 .word 0x20002484 +200008e0: 1000c6cc .word 0x1000c6cc + +200008e4 : +200008e4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +200008e8: 8a82 ldrh r2, [r0, #20] +200008ea: f8b0 e018 ldrh.w lr, [r0, #24] +200008ee: 4603 mov r3, r0 +200008f0: 4596 cmp lr, r2 +200008f2: 78c0 ldrb r0, [r0, #3] +200008f4: bf28 it cs +200008f6: 4696 movcs lr, r2 +200008f8: 1e04 subs r4, r0, #0 +200008fa: bf18 it ne +200008fc: 2401 movne r4, #1 +200008fe: f080 0001 eor.w r0, r0, #1 +20000902: 460d mov r5, r1 +20000904: eba2 020e sub.w r2, r2, lr +20000908: 7859 ldrb r1, [r3, #1] +2000090a: 70d8 strb r0, [r3, #3] +2000090c: b292 uxth r2, r2 +2000090e: f44e 6080 orr.w r0, lr, #1024 @ 0x400 +20000912: 829a strh r2, [r3, #20] +20000914: ea40 3044 orr.w r0, r0, r4, lsl #13 +20000918: bba1 cbnz r1, 20000984 +2000091a: 6919 ldr r1, [r3, #16] +2000091c: f1be 0f00 cmp.w lr, #0 +20000920: d02c beq.n 2000097c +20000922: f10e 34ff add.w r4, lr, #4294967295 @ 0xffffffff +20000926: 68da ldr r2, [r3, #12] +20000928: 2c05 cmp r4, #5 +2000092a: 46a1 mov r9, r4 +2000092c: eb02 1885 add.w r8, r2, r5, lsl #6 +20000930: d92f bls.n 20000992 +20000932: eba8 0401 sub.w r4, r8, r1 +20000936: 3c01 subs r4, #1 +20000938: 2c02 cmp r4, #2 +2000093a: 46c4 mov ip, r8 +2000093c: 460a mov r2, r1 +2000093e: d928 bls.n 20000992 +20000940: ea4f 079e mov.w r7, lr, lsr #2 +20000944: eb01 0687 add.w r6, r1, r7, lsl #2 +20000948: f852 4b04 ldr.w r4, [r2], #4 +2000094c: 4296 cmp r6, r2 +2000094e: f84c 4b04 str.w r4, [ip], #4 +20000952: d1f9 bne.n 20000948 +20000954: ebbe 0f87 cmp.w lr, r7, lsl #2 +20000958: d00e beq.n 20000978 +2000095a: f811 2027 ldrb.w r2, [r1, r7, lsl #2] +2000095e: ebb9 0187 subs.w r1, r9, r7, lsl #2 +20000962: f808 2027 strb.w r2, [r8, r7, lsl #2] +20000966: eb08 0287 add.w r2, r8, r7, lsl #2 +2000096a: d005 beq.n 20000978 +2000096c: 7874 ldrb r4, [r6, #1] +2000096e: 2901 cmp r1, #1 +20000970: 7054 strb r4, [r2, #1] +20000972: d001 beq.n 20000978 +20000974: 78b1 ldrb r1, [r6, #2] +20000976: 7091 strb r1, [r2, #2] +20000978: 6919 ldr r1, [r3, #16] +2000097a: 8a9a ldrh r2, [r3, #20] +2000097c: 4471 add r1, lr +2000097e: 6119 str r1, [r3, #16] +20000980: f440 4000 orr.w r0, r0, #32768 @ 0x8000 +20000984: b90a cbnz r2, 2000098a +20000986: f440 4080 orr.w r0, r0, #16384 @ 0x4000 +2000098a: b105 cbz r5, 2000098e +2000098c: 0400 lsls r0, r0, #16 +2000098e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +20000992: f108 32ff add.w r2, r8, #4294967295 @ 0xffffffff +20000996: eb01 060e add.w r6, r1, lr +2000099a: f811 4b01 ldrb.w r4, [r1], #1 +2000099e: 42b1 cmp r1, r6 +200009a0: f802 4f01 strb.w r4, [r2, #1]! +200009a4: d1f9 bne.n 2000099a +200009a6: e7e7 b.n 20000978 + +200009a8 : +200009a8: 6883 ldr r3, [r0, #8] +200009aa: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +200009ae: 4605 mov r5, r0 +200009b0: 6818 ldr r0, [r3, #0] +200009b2: b101 cbz r1, 200009b6 +200009b4: 0c00 lsrs r0, r0, #16 +200009b6: 786a ldrb r2, [r5, #1] +200009b8: f3c0 0009 ubfx r0, r0, #0, #10 +200009bc: b94a cbnz r2, 200009d2 +200009be: 8aeb ldrh r3, [r5, #22] +200009c0: 4403 add r3, r0 +200009c2: 82eb strh r3, [r5, #22] +200009c4: 8b2b ldrh r3, [r5, #24] +200009c6: 4283 cmp r3, r0 +200009c8: bf84 itt hi +200009ca: 2300 movhi r3, #0 +200009cc: 82ab strhhi r3, [r5, #20] +200009ce: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +200009d2: f8d5 c010 ldr.w ip, [r5, #16] +200009d6: b388 cbz r0, 20000a3c +200009d8: 1e42 subs r2, r0, #1 +200009da: 68eb ldr r3, [r5, #12] +200009dc: 2a05 cmp r2, #5 +200009de: 4616 mov r6, r2 +200009e0: eb03 1e81 add.w lr, r3, r1, lsl #6 +200009e4: d931 bls.n 20000a4a +200009e6: 0189 lsls r1, r1, #6 +200009e8: 1c4c adds r4, r1, #1 +200009ea: 441c add r4, r3 +200009ec: ebac 0404 sub.w r4, ip, r4 +200009f0: 2c02 cmp r4, #2 +200009f2: 4662 mov r2, ip +200009f4: d929 bls.n 20000a4a +200009f6: f400 717f and.w r1, r0, #1020 @ 0x3fc +200009fa: 4673 mov r3, lr +200009fc: 460f mov r7, r1 +200009fe: ea4f 0890 mov.w r8, r0, lsr #2 +20000a02: 185c adds r4, r3, r1 +20000a04: f853 1b04 ldr.w r1, [r3], #4 +20000a08: 42a3 cmp r3, r4 +20000a0a: f842 1b04 str.w r1, [r2], #4 +20000a0e: d1f9 bne.n 20000a04 +20000a10: 42b8 cmp r0, r7 +20000a12: d011 beq.n 20000a38 +20000a14: f81e 3028 ldrb.w r3, [lr, r8, lsl #2] +20000a18: 44be add lr, r7 +20000a1a: f80c 3028 strb.w r3, [ip, r8, lsl #2] +20000a1e: 1bf3 subs r3, r6, r7 +20000a20: 44bc add ip, r7 +20000a22: d009 beq.n 20000a38 +20000a24: f89e 2001 ldrb.w r2, [lr, #1] +20000a28: 2b01 cmp r3, #1 +20000a2a: f88c 2001 strb.w r2, [ip, #1] +20000a2e: d003 beq.n 20000a38 +20000a30: f89e 3002 ldrb.w r3, [lr, #2] +20000a34: f88c 3002 strb.w r3, [ip, #2] +20000a38: f8d5 c010 ldr.w ip, [r5, #16] +20000a3c: 8aea ldrh r2, [r5, #22] +20000a3e: eb0c 0300 add.w r3, ip, r0 +20000a42: 4402 add r2, r0 +20000a44: 82ea strh r2, [r5, #22] +20000a46: 612b str r3, [r5, #16] +20000a48: e7bc b.n 200009c4 +20000a4a: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff +20000a4e: eb0e 0200 add.w r2, lr, r0 +20000a52: f81e 3b01 ldrb.w r3, [lr], #1 +20000a56: 4572 cmp r2, lr +20000a58: f80c 3f01 strb.w r3, [ip, #1]! +20000a5c: d1f9 bne.n 20000a52 +20000a5e: e7eb b.n 20000a38 + +20000a60 <_hw_endpoint_xfer_sync>: +20000a60: b510 push {r4, lr} +20000a62: 4604 mov r4, r0 +20000a64: 6883 ldr r3, [r0, #8] +20000a66: 2100 movs r1, #0 +20000a68: 681b ldr r3, [r3, #0] +20000a6a: f7ff ff9d bl 200009a8 +20000a6e: 6863 ldr r3, [r4, #4] +20000a70: 681b ldr r3, [r3, #0] +20000a72: 005b lsls r3, r3, #1 +20000a74: d502 bpl.n 20000a7c <_hw_endpoint_xfer_sync+0x1c> +20000a76: 8b23 ldrh r3, [r4, #24] +20000a78: 4283 cmp r3, r0 +20000a7a: d000 beq.n 20000a7e <_hw_endpoint_xfer_sync+0x1e> +20000a7c: bd10 pop {r4, pc} +20000a7e: 4620 mov r0, r4 +20000a80: e8bd 4010 ldmia.w sp!, {r4, lr} +20000a84: 2101 movs r1, #1 +20000a86: f7ff bf8f b.w 200009a8 +20000a8a: bf00 nop + +20000a8c : +20000a8c: 4b08 ldr r3, [pc, #32] @ (20000ab0 ) +20000a8e: 6c1b ldr r3, [r3, #64] @ 0x40 +20000a90: f013 0302 ands.w r3, r3, #2 +20000a94: d102 bne.n 20000a9c +20000a96: 7882 ldrb r2, [r0, #2] +20000a98: 09d2 lsrs r2, r2, #7 +20000a9a: d101 bne.n 20000aa0 +20000a9c: 2000 movs r0, #0 +20000a9e: 4770 bx lr +20000aa0: 7ec0 ldrb r0, [r0, #27] +20000aa2: f1a0 0002 sub.w r0, r0, #2 +20000aa6: fab0 f080 clz r0, r0 +20000aaa: 0940 lsrs r0, r0, #5 +20000aac: 4770 bx lr +20000aae: bf00 nop +20000ab0: 50110000 .word 0x50110000 + +20000ab4 : +20000ab4: b508 push {r3, lr} +20000ab6: f7ff ffe9 bl 20000a8c +20000aba: b150 cbz r0, 20000ad2 +20000abc: 4a05 ldr r2, [pc, #20] @ (20000ad4 ) +20000abe: 4b06 ldr r3, [pc, #24] @ (20000ad8 ) +20000ac0: 6a90 ldr r0, [r2, #40] @ 0x28 +20000ac2: 681b ldr r3, [r3, #0] +20000ac4: f5a0 7048 sub.w r0, r0, #800 @ 0x320 +20000ac8: 1ac0 subs r0, r0, r3 +20000aca: 28c6 cmp r0, #198 @ 0xc6 +20000acc: bf8c ite hi +20000ace: 2000 movhi r0, #0 +20000ad0: 2001 movls r0, #1 +20000ad2: bd08 pop {r3, pc} +20000ad4: 400b0000 .word 0x400b0000 +20000ad8: 20001ec0 .word 0x20001ec0 + +20000adc : +20000adc: 2300 movs r3, #0 +20000ade: e9c0 3304 strd r3, r3, [r0, #16] +20000ae2: 7683 strb r3, [r0, #26] +20000ae4: 4770 bx lr +20000ae6: bf00 nop + +20000ae8 <_hw_endpoint_buffer_control_update32>: +20000ae8: b508 push {r3, lr} +20000aea: 6883 ldr r3, [r0, #8] +20000aec: b119 cbz r1, 20000af6 <_hw_endpoint_buffer_control_update32+0xe> +20000aee: f8d3 c000 ldr.w ip, [r3] +20000af2: ea01 010c and.w r1, r1, ip +20000af6: b18a cbz r2, 20000b1c <_hw_endpoint_buffer_control_update32+0x34> +20000af8: 4311 orrs r1, r2 +20000afa: 0552 lsls r2, r2, #21 +20000afc: d50e bpl.n 20000b1c <_hw_endpoint_buffer_control_update32+0x34> +20000afe: 681a ldr r2, [r3, #0] +20000b00: 0552 lsls r2, r2, #21 +20000b02: d40d bmi.n 20000b20 <_hw_endpoint_buffer_control_update32+0x38> +20000b04: 4a08 ldr r2, [pc, #32] @ (20000b28 <_hw_endpoint_buffer_control_update32+0x40>) +20000b06: f421 6c80 bic.w ip, r1, #1024 @ 0x400 +20000b0a: f8c3 c000 str.w ip, [r3] +20000b0e: 6c12 ldr r2, [r2, #64] @ 0x40 +20000b10: 0792 lsls r2, r2, #30 +20000b12: d403 bmi.n 20000b1c <_hw_endpoint_buffer_control_update32+0x34> +20000b14: 230c movs r3, #12 +20000b16: 3b03 subs r3, #3 +20000b18: d2fd bcs.n 20000b16 <_hw_endpoint_buffer_control_update32+0x2e> +20000b1a: 6883 ldr r3, [r0, #8] +20000b1c: 6019 str r1, [r3, #0] +20000b1e: bd08 pop {r3, pc} +20000b20: 7881 ldrb r1, [r0, #2] +20000b22: 4802 ldr r0, [pc, #8] @ (20000b2c <_hw_endpoint_buffer_control_update32+0x44>) +20000b24: f000 fb20 bl 20001168 <__panic_veneer> +20000b28: 50110000 .word 0x50110000 +20000b2c: 1000c6e0 .word 0x1000c6e0 + +20000b30 : +20000b30: b530 push {r4, r5, lr} +20000b32: 6843 ldr r3, [r0, #4] +20000b34: 2100 movs r1, #0 +20000b36: b083 sub sp, #12 +20000b38: 4605 mov r5, r0 +20000b3a: 681c ldr r4, [r3, #0] +20000b3c: f7ff fed2 bl 200008e4 +20000b40: 4b13 ldr r3, [pc, #76] @ (20000b90 ) +20000b42: f440 5280 orr.w r2, r0, #4096 @ 0x1000 +20000b46: 6c19 ldr r1, [r3, #64] @ 0x40 +20000b48: 78ab ldrb r3, [r5, #2] +20000b4a: 0789 lsls r1, r1, #30 +20000b4c: d50e bpl.n 20000b6c +20000b4e: 065b lsls r3, r3, #25 +20000b50: d00e beq.n 20000b70 +20000b52: f024 44a0 bic.w r4, r4, #1342177280 @ 0x50000000 +20000b56: f044 5400 orr.w r4, r4, #536870912 @ 0x20000000 +20000b5a: 2100 movs r1, #0 +20000b5c: 4628 mov r0, r5 +20000b5e: 686b ldr r3, [r5, #4] +20000b60: 601c str r4, [r3, #0] +20000b62: b003 add sp, #12 +20000b64: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +20000b68: f7ff bfbe b.w 20000ae8 <_hw_endpoint_buffer_control_update32> +20000b6c: 09db lsrs r3, r3, #7 +20000b6e: d0f0 beq.n 20000b52 +20000b70: 8aab ldrh r3, [r5, #20] +20000b72: 2b00 cmp r3, #0 +20000b74: d0ed beq.n 20000b52 +20000b76: 2101 movs r1, #1 +20000b78: 4628 mov r0, r5 +20000b7a: 9201 str r2, [sp, #4] +20000b7c: f7ff feb2 bl 200008e4 +20000b80: 9a01 ldr r2, [sp, #4] +20000b82: f024 5400 bic.w r4, r4, #536870912 @ 0x20000000 +20000b86: 4302 orrs r2, r0 +20000b88: f044 44a0 orr.w r4, r4, #1342177280 @ 0x50000000 +20000b8c: e7e5 b.n 20000b5a +20000b8e: bf00 nop +20000b90: 50110000 .word 0x50110000 + +20000b94 : +20000b94: b538 push {r3, r4, r5, lr} +20000b96: 7e85 ldrb r5, [r0, #26] +20000b98: 4604 mov r4, r0 +20000b9a: b195 cbz r5, 20000bc2 +20000b9c: f7ff ff60 bl 20000a60 <_hw_endpoint_xfer_sync> +20000ba0: 8aa3 ldrh r3, [r4, #20] +20000ba2: b90b cbnz r3, 20000ba8 +20000ba4: 4628 mov r0, r5 +20000ba6: bd38 pop {r3, r4, r5, pc} +20000ba8: 4620 mov r0, r4 +20000baa: f7ff ff83 bl 20000ab4 +20000bae: b120 cbz r0, 20000bba +20000bb0: 2301 movs r3, #1 +20000bb2: 7723 strb r3, [r4, #28] +20000bb4: 2500 movs r5, #0 +20000bb6: 4628 mov r0, r5 +20000bb8: bd38 pop {r3, r4, r5, pc} +20000bba: 4620 mov r0, r4 +20000bbc: f7ff ffb8 bl 20000b30 +20000bc0: e7f8 b.n 20000bb4 +20000bc2: 7881 ldrb r1, [r0, #2] +20000bc4: 4801 ldr r0, [pc, #4] @ (20000bcc ) +20000bc6: f000 facf bl 20001168 <__panic_veneer> +20000bca: bf00 nop +20000bcc: 1000c700 .word 0x1000c700 + +20000bd0 : +20000bd0: b570 push {r4, r5, r6, lr} +20000bd2: 7843 ldrb r3, [r0, #1] +20000bd4: 4604 mov r4, r0 +20000bd6: 3b02 subs r3, #2 +20000bd8: 460e mov r6, r1 +20000bda: b086 sub sp, #24 +20000bdc: 2b04 cmp r3, #4 +20000bde: d813 bhi.n 20000c08 +20000be0: e8df f003 tbb [pc, r3] +20000be4: 70674903 .word 0x70674903 +20000be8: 44 .byte 0x44 +20000be9: 00 .byte 0x00 +20000bea: 2100 movs r1, #0 +20000bec: 4b77 ldr r3, [pc, #476] @ (20000dcc ) +20000bee: 781a ldrb r2, [r3, #0] +20000bf0: f022 0201 bic.w r2, r2, #1 +20000bf4: 701a strb r2, [r3, #0] +20000bf6: 781a ldrb r2, [r3, #0] +20000bf8: f022 0202 bic.w r2, r2, #2 +20000bfc: 701a strb r2, [r3, #0] +20000bfe: 7059 strb r1, [r3, #1] +20000c00: 781a ldrb r2, [r3, #0] +20000c02: f361 0282 bfi r2, r1, #2, #1 +20000c06: 701a strb r2, [r3, #0] +20000c08: 4b71 ldr r3, [pc, #452] @ (20000dd0 ) +20000c0a: 681b ldr r3, [r3, #0] +20000c0c: 695a ldr r2, [r3, #20] +20000c0e: f3ef 8010 mrs r0, PRIMASK +20000c12: b672 cpsid i +20000c14: e8d2 cfcf ldaexb ip, [r2] +20000c18: 2101 movs r1, #1 +20000c1a: f1bc 0f00 cmp.w ip, #0 +20000c1e: d1f9 bne.n 20000c14 +20000c20: e8c2 1f4c strexb ip, r1, [r2] +20000c24: f1bc 0f00 cmp.w ip, #0 +20000c28: d1f4 bne.n 20000c14 +20000c2a: f3bf 8f5f dmb sy +20000c2e: 4621 mov r1, r4 +20000c30: 6198 str r0, [r3, #24] +20000c32: 4618 mov r0, r3 +20000c34: 9301 str r3, [sp, #4] +20000c36: f000 fa9b bl 20001170 <__tu_fifo_write_veneer> +20000c3a: 9b01 ldr r3, [sp, #4] +20000c3c: 2200 movs r2, #0 +20000c3e: 6959 ldr r1, [r3, #20] +20000c40: e8c1 2f8f stlb r2, [r1] +20000c44: 699b ldr r3, [r3, #24] +20000c46: f383 8810 msr PRIMASK, r3 +20000c4a: b940 cbnz r0, 20000c5e +20000c4c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +20000c50: f8d3 3df0 ldr.w r3, [r3, #3568] @ 0xdf0 +20000c54: 07db lsls r3, r3, #31 +20000c56: d507 bpl.n 20000c68 +20000c58: be00 bkpt 0x0000 +20000c5a: b006 add sp, #24 +20000c5c: bd70 pop {r4, r5, r6, pc} +20000c5e: 4632 mov r2, r6 +20000c60: 7861 ldrb r1, [r4, #1] +20000c62: 7820 ldrb r0, [r4, #0] +20000c64: f000 fa8c bl 20001180 <__tud_event_hook_cb_veneer> +20000c68: b006 add sp, #24 +20000c6a: bd70 pop {r4, r5, r6, pc} +20000c6c: 4a59 ldr r2, [pc, #356] @ (20000dd4 ) +20000c6e: 7813 ldrb r3, [r2, #0] +20000c70: 3301 adds r3, #1 +20000c72: 7013 strb r3, [r2, #0] +20000c74: e7c8 b.n 20000c08 +20000c76: 2200 movs r2, #0 +20000c78: 4b57 ldr r3, [pc, #348] @ (20000dd8 ) +20000c7a: 7818 ldrb r0, [r3, #0] +20000c7c: 4613 mov r3, r2 +20000c7e: e011 b.n 20000ca4 +20000c80: 4956 ldr r1, [pc, #344] @ (20000ddc ) +20000c82: 6809 ldr r1, [r1, #0] +20000c84: eb11 1343 adds.w r3, r1, r3, lsl #5 +20000c88: d008 beq.n 20000c9c +20000c8a: 69db ldr r3, [r3, #28] +20000c8c: b133 cbz r3, 20000c9c +20000c8e: 7820 ldrb r0, [r4, #0] +20000c90: 6861 ldr r1, [r4, #4] +20000c92: 9201 str r2, [sp, #4] +20000c94: 4798 blx r3 +20000c96: 4b50 ldr r3, [pc, #320] @ (20000dd8 ) +20000c98: 9a01 ldr r2, [sp, #4] +20000c9a: 7818 ldrb r0, [r3, #0] +20000c9c: 3201 adds r2, #1 +20000c9e: b2d3 uxtb r3, r2 +20000ca0: 4283 cmp r3, r0 +20000ca2: d818 bhi.n 20000cd6 +20000ca4: 4298 cmp r0, r3 +20000ca6: d8eb bhi.n 20000c80 +20000ca8: 494d ldr r1, [pc, #308] @ (20000de0 ) +20000caa: 1a1b subs r3, r3, r0 +20000cac: eb01 1343 add.w r3, r1, r3, lsl #5 +20000cb0: e7eb b.n 20000c8a +20000cb2: 4b46 ldr r3, [pc, #280] @ (20000dcc ) +20000cb4: 781a ldrb r2, [r3, #0] +20000cb6: 07d2 lsls r2, r2, #31 +20000cb8: d5d6 bpl.n 20000c68 +20000cba: 781a ldrb r2, [r3, #0] +20000cbc: f042 0204 orr.w r2, r2, #4 +20000cc0: 701a strb r2, [r3, #0] +20000cc2: e7a1 b.n 20000c08 +20000cc4: 4b41 ldr r3, [pc, #260] @ (20000dcc ) +20000cc6: 781a ldrb r2, [r3, #0] +20000cc8: 07d5 lsls r5, r2, #31 +20000cca: d5cd bpl.n 20000c68 +20000ccc: 781a ldrb r2, [r3, #0] +20000cce: f022 0204 bic.w r2, r2, #4 +20000cd2: 701a strb r2, [r3, #0] +20000cd4: e798 b.n 20000c08 +20000cd6: 4b3d ldr r3, [pc, #244] @ (20000dcc ) +20000cd8: 781a ldrb r2, [r3, #0] +20000cda: 0750 lsls r0, r2, #29 +20000cdc: d433 bmi.n 20000d46 +20000cde: 78db ldrb r3, [r3, #3] +20000ce0: 07da lsls r2, r3, #31 +20000ce2: d5c1 bpl.n 20000c68 +20000ce4: 2203 movs r2, #3 +20000ce6: 4b3a ldr r3, [pc, #232] @ (20000dd0 ) +20000ce8: 7820 ldrb r0, [r4, #0] +20000cea: 6861 ldr r1, [r4, #4] +20000cec: 681b ldr r3, [r3, #0] +20000cee: f88d 000c strb.w r0, [sp, #12] +20000cf2: f88d 200d strb.w r2, [sp, #13] +20000cf6: 695a ldr r2, [r3, #20] +20000cf8: 9104 str r1, [sp, #16] +20000cfa: f3ef 8110 mrs r1, PRIMASK +20000cfe: b672 cpsid i +20000d00: e8d2 4fcf ldaexb r4, [r2] +20000d04: 2001 movs r0, #1 +20000d06: 2c00 cmp r4, #0 +20000d08: d1fa bne.n 20000d00 +20000d0a: e8c2 0f44 strexb r4, r0, [r2] +20000d0e: 2c00 cmp r4, #0 +20000d10: d1f6 bne.n 20000d00 +20000d12: f3bf 8f5f dmb sy +20000d16: 6199 str r1, [r3, #24] +20000d18: 4618 mov r0, r3 +20000d1a: a903 add r1, sp, #12 +20000d1c: 9301 str r3, [sp, #4] +20000d1e: f000 fa27 bl 20001170 <__tu_fifo_write_veneer> +20000d22: 9b01 ldr r3, [sp, #4] +20000d24: 2200 movs r2, #0 +20000d26: 6959 ldr r1, [r3, #20] +20000d28: e8c1 2f8f stlb r2, [r1] +20000d2c: 699b ldr r3, [r3, #24] +20000d2e: f383 8810 msr PRIMASK, r3 +20000d32: 2800 cmp r0, #0 +20000d34: d08a beq.n 20000c4c +20000d36: 4632 mov r2, r6 +20000d38: f89d 100d ldrb.w r1, [sp, #13] +20000d3c: f89d 000c ldrb.w r0, [sp, #12] +20000d40: f000 fa1e bl 20001180 <__tud_event_hook_cb_veneer> +20000d44: e790 b.n 20000c68 +20000d46: 2500 movs r5, #0 +20000d48: 2005 movs r0, #5 +20000d4a: 7819 ldrb r1, [r3, #0] +20000d4c: e9cd 5504 strd r5, r5, [sp, #16] +20000d50: f021 0104 bic.w r1, r1, #4 +20000d54: 9503 str r5, [sp, #12] +20000d56: 7019 strb r1, [r3, #0] +20000d58: f88d 000d strb.w r0, [sp, #13] +20000d5c: 4a1c ldr r2, [pc, #112] @ (20000dd0 ) +20000d5e: 7821 ldrb r1, [r4, #0] +20000d60: 6812 ldr r2, [r2, #0] +20000d62: f88d 100c strb.w r1, [sp, #12] +20000d66: 6951 ldr r1, [r2, #20] +20000d68: f3ef 8010 mrs r0, PRIMASK +20000d6c: b672 cpsid i +20000d6e: e8d1 efcf ldaexb lr, [r1] +20000d72: f05f 0c01 movs.w ip, #1 +20000d76: f1be 0f00 cmp.w lr, #0 +20000d7a: d1f8 bne.n 20000d6e +20000d7c: e8c1 cf4e strexb lr, ip, [r1] +20000d80: f1be 0f00 cmp.w lr, #0 +20000d84: d1f3 bne.n 20000d6e +20000d86: f3bf 8f5f dmb sy +20000d8a: 6190 str r0, [r2, #24] +20000d8c: a903 add r1, sp, #12 +20000d8e: 4610 mov r0, r2 +20000d90: 9201 str r2, [sp, #4] +20000d92: f000 f9ed bl 20001170 <__tu_fifo_write_veneer> +20000d96: 9a01 ldr r2, [sp, #4] +20000d98: 6951 ldr r1, [r2, #20] +20000d9a: e8c1 5f8f stlb r5, [r1] +20000d9e: 6992 ldr r2, [r2, #24] +20000da0: f382 8810 msr PRIMASK, r2 +20000da4: 4b09 ldr r3, [pc, #36] @ (20000dcc ) +20000da6: b938 cbnz r0, 20000db8 +20000da8: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +20000dac: f8d2 2df0 ldr.w r2, [r2, #3568] @ 0xdf0 +20000db0: 07d1 lsls r1, r2, #31 +20000db2: d594 bpl.n 20000cde +20000db4: be00 bkpt 0x0000 +20000db6: e792 b.n 20000cde +20000db8: 4632 mov r2, r6 +20000dba: f89d 100d ldrb.w r1, [sp, #13] +20000dbe: f89d 000c ldrb.w r0, [sp, #12] +20000dc2: f000 f9dd bl 20001180 <__tud_event_hook_cb_veneer> +20000dc6: 4b01 ldr r3, [pc, #4] @ (20000dcc ) +20000dc8: e789 b.n 20000cde +20000dca: bf00 nop +20000dcc: 20001d40 .word 0x20001d40 +20000dd0: 20001d98 .word 0x20001d98 +20000dd4: 2000253b .word 0x2000253b +20000dd8: 20002539 .word 0x20002539 +20000ddc: 20001c38 .word 0x20001c38 +20000de0: 1000ce74 .word 0x1000ce74 + +20000de4 <__aeabi_uldivmod>: +20000de4: b953 cbnz r3, 20000dfc <__aeabi_uldivmod+0x18> +20000de6: b94a cbnz r2, 20000dfc <__aeabi_uldivmod+0x18> +20000de8: 2900 cmp r1, #0 +20000dea: bf08 it eq +20000dec: 2800 cmpeq r0, #0 +20000dee: bf1c itt ne +20000df0: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000df4: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000df8: f000 b9ac b.w 20001154 <__aeabi_idiv0> +20000dfc: f1ad 0c08 sub.w ip, sp, #8 +20000e00: e96d ce04 strd ip, lr, [sp, #-16]! +20000e04: f000 f806 bl 20000e14 <__udivmoddi4> +20000e08: f8dd e004 ldr.w lr, [sp, #4] +20000e0c: e9dd 2302 ldrd r2, r3, [sp, #8] +20000e10: b004 add sp, #16 +20000e12: 4770 bx lr + +20000e14 <__udivmoddi4>: +20000e14: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +20000e18: 4606 mov r6, r0 +20000e1a: b082 sub sp, #8 +20000e1c: 4617 mov r7, r2 +20000e1e: 4608 mov r0, r1 +20000e20: 9a0a ldr r2, [sp, #40] @ 0x28 +20000e22: 46b4 mov ip, r6 +20000e24: 460d mov r5, r1 +20000e26: 2b00 cmp r3, #0 +20000e28: d14d bne.n 20000ec6 <__udivmoddi4+0xb2> +20000e2a: 428f cmp r7, r1 +20000e2c: 46be mov lr, r7 +20000e2e: d965 bls.n 20000efc <__udivmoddi4+0xe8> +20000e30: fab7 f187 clz r1, r7 +20000e34: b149 cbz r1, 20000e4a <__udivmoddi4+0x36> +20000e36: f1c1 0320 rsb r3, r1, #32 +20000e3a: 408d lsls r5, r1 +20000e3c: fa07 fe01 lsl.w lr, r7, r1 +20000e40: fa06 fc01 lsl.w ip, r6, r1 +20000e44: fa26 f303 lsr.w r3, r6, r3 +20000e48: 431d orrs r5, r3 +20000e4a: ea4f 461e mov.w r6, lr, lsr #16 +20000e4e: fa1f f08e uxth.w r0, lr +20000e52: ea4f 431c mov.w r3, ip, lsr #16 +20000e56: fbb5 f4f6 udiv r4, r5, r6 +20000e5a: fb06 5514 mls r5, r6, r4, r5 +20000e5e: ea43 4305 orr.w r3, r3, r5, lsl #16 +20000e62: fb04 f500 mul.w r5, r4, r0 +20000e66: 429d cmp r5, r3 +20000e68: d906 bls.n 20000e78 <__udivmoddi4+0x64> +20000e6a: eb1e 0303 adds.w r3, lr, r3 +20000e6e: d202 bcs.n 20000e76 <__udivmoddi4+0x62> +20000e70: 429d cmp r5, r3 +20000e72: f200 814c bhi.w 2000110e <__udivmoddi4+0x2fa> +20000e76: 3c01 subs r4, #1 +20000e78: 1b5b subs r3, r3, r5 +20000e7a: fa1f fc8c uxth.w ip, ip +20000e7e: fbb3 f5f6 udiv r5, r3, r6 +20000e82: fb06 3315 mls r3, r6, r5, r3 +20000e86: fb05 f000 mul.w r0, r5, r0 +20000e8a: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +20000e8e: 4560 cmp r0, ip +20000e90: d90a bls.n 20000ea8 <__udivmoddi4+0x94> +20000e92: eb1e 0c0c adds.w ip, lr, ip +20000e96: bf2c ite cs +20000e98: 2301 movcs r3, #1 +20000e9a: 2300 movcc r3, #0 +20000e9c: 4560 cmp r0, ip +20000e9e: d902 bls.n 20000ea6 <__udivmoddi4+0x92> +20000ea0: 2b00 cmp r3, #0 +20000ea2: f000 8137 beq.w 20001114 <__udivmoddi4+0x300> +20000ea6: 3d01 subs r5, #1 +20000ea8: ebac 0c00 sub.w ip, ip, r0 +20000eac: ea45 4004 orr.w r0, r5, r4, lsl #16 +20000eb0: 2400 movs r4, #0 +20000eb2: b122 cbz r2, 20000ebe <__udivmoddi4+0xaa> +20000eb4: fa2c f301 lsr.w r3, ip, r1 +20000eb8: 2100 movs r1, #0 +20000eba: e9c2 3100 strd r3, r1, [r2] +20000ebe: 4621 mov r1, r4 +20000ec0: b002 add sp, #8 +20000ec2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +20000ec6: 428b cmp r3, r1 +20000ec8: d908 bls.n 20000edc <__udivmoddi4+0xc8> +20000eca: b10a cbz r2, 20000ed0 <__udivmoddi4+0xbc> +20000ecc: e9c2 6100 strd r6, r1, [r2] +20000ed0: 2400 movs r4, #0 +20000ed2: 4620 mov r0, r4 +20000ed4: 4621 mov r1, r4 +20000ed6: b002 add sp, #8 +20000ed8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +20000edc: fab3 f483 clz r4, r3 +20000ee0: 2c00 cmp r4, #0 +20000ee2: d14d bne.n 20000f80 <__udivmoddi4+0x16c> +20000ee4: 428b cmp r3, r1 +20000ee6: f0c0 8105 bcc.w 200010f4 <__udivmoddi4+0x2e0> +20000eea: 42b7 cmp r7, r6 +20000eec: f240 8102 bls.w 200010f4 <__udivmoddi4+0x2e0> +20000ef0: 4620 mov r0, r4 +20000ef2: 2a00 cmp r2, #0 +20000ef4: d0e3 beq.n 20000ebe <__udivmoddi4+0xaa> +20000ef6: e9c2 c500 strd ip, r5, [r2] +20000efa: e7e0 b.n 20000ebe <__udivmoddi4+0xaa> +20000efc: 2f00 cmp r7, #0 +20000efe: f000 80a2 beq.w 20001046 <__udivmoddi4+0x232> +20000f02: 4619 mov r1, r3 +20000f04: fab7 f387 clz r3, r7 +20000f08: 2b00 cmp r3, #0 +20000f0a: f040 80b4 bne.w 20001076 <__udivmoddi4+0x262> +20000f0e: 1bc3 subs r3, r0, r7 +20000f10: fa1f f88e uxth.w r8, lr +20000f14: 0c3f lsrs r7, r7, #16 +20000f16: 2401 movs r4, #1 +20000f18: ea4f 401c mov.w r0, ip, lsr #16 +20000f1c: fbb3 f5f7 udiv r5, r3, r7 +20000f20: fb07 3315 mls r3, r7, r5, r3 +20000f24: ea40 4303 orr.w r3, r0, r3, lsl #16 +20000f28: fb08 f005 mul.w r0, r8, r5 +20000f2c: 4298 cmp r0, r3 +20000f2e: d90a bls.n 20000f46 <__udivmoddi4+0x132> +20000f30: eb1e 0303 adds.w r3, lr, r3 +20000f34: bf2c ite cs +20000f36: 2601 movcs r6, #1 +20000f38: 2600 movcc r6, #0 +20000f3a: 4298 cmp r0, r3 +20000f3c: d902 bls.n 20000f44 <__udivmoddi4+0x130> +20000f3e: 2e00 cmp r6, #0 +20000f40: f000 80e2 beq.w 20001108 <__udivmoddi4+0x2f4> +20000f44: 3d01 subs r5, #1 +20000f46: 1a1b subs r3, r3, r0 +20000f48: fa1f fc8c uxth.w ip, ip +20000f4c: fbb3 f0f7 udiv r0, r3, r7 +20000f50: fb07 3310 mls r3, r7, r0, r3 +20000f54: ea4c 4c03 orr.w ip, ip, r3, lsl #16 +20000f58: fb08 f300 mul.w r3, r8, r0 +20000f5c: 4563 cmp r3, ip +20000f5e: d90a bls.n 20000f76 <__udivmoddi4+0x162> +20000f60: eb1e 0c0c adds.w ip, lr, ip +20000f64: bf2c ite cs +20000f66: 2601 movcs r6, #1 +20000f68: 2600 movcc r6, #0 +20000f6a: 4563 cmp r3, ip +20000f6c: d902 bls.n 20000f74 <__udivmoddi4+0x160> +20000f6e: 2e00 cmp r6, #0 +20000f70: f000 80c7 beq.w 20001102 <__udivmoddi4+0x2ee> +20000f74: 3801 subs r0, #1 +20000f76: ebac 0c03 sub.w ip, ip, r3 +20000f7a: ea40 4005 orr.w r0, r0, r5, lsl #16 +20000f7e: e798 b.n 20000eb2 <__udivmoddi4+0x9e> +20000f80: f1c4 0820 rsb r8, r4, #32 +20000f84: 40a3 lsls r3, r4 +20000f86: fa06 fa04 lsl.w sl, r6, r4 +20000f8a: 40a1 lsls r1, r4 +20000f8c: fa27 fc08 lsr.w ip, r7, r8 +20000f90: fa20 f008 lsr.w r0, r0, r8 +20000f94: fa07 f904 lsl.w r9, r7, r4 +20000f98: ea4c 0c03 orr.w ip, ip, r3 +20000f9c: fa26 f308 lsr.w r3, r6, r8 +20000fa0: ea4f 461c mov.w r6, ip, lsr #16 +20000fa4: 430b orrs r3, r1 +20000fa6: fa1f fe8c uxth.w lr, ip +20000faa: 0c19 lsrs r1, r3, #16 +20000fac: fbb0 f7f6 udiv r7, r0, r6 +20000fb0: fb06 0017 mls r0, r6, r7, r0 +20000fb4: ea41 4100 orr.w r1, r1, r0, lsl #16 +20000fb8: fb07 f00e mul.w r0, r7, lr +20000fbc: 4288 cmp r0, r1 +20000fbe: d90a bls.n 20000fd6 <__udivmoddi4+0x1c2> +20000fc0: eb1c 0101 adds.w r1, ip, r1 +20000fc4: bf2c ite cs +20000fc6: 2501 movcs r5, #1 +20000fc8: 2500 movcc r5, #0 +20000fca: 4288 cmp r0, r1 +20000fcc: d902 bls.n 20000fd4 <__udivmoddi4+0x1c0> +20000fce: 2d00 cmp r5, #0 +20000fd0: f000 80b2 beq.w 20001138 <__udivmoddi4+0x324> +20000fd4: 3f01 subs r7, #1 +20000fd6: 1a09 subs r1, r1, r0 +20000fd8: b29b uxth r3, r3 +20000fda: fbb1 f0f6 udiv r0, r1, r6 +20000fde: fb06 1110 mls r1, r6, r0, r1 +20000fe2: fb00 fe0e mul.w lr, r0, lr +20000fe6: ea43 4301 orr.w r3, r3, r1, lsl #16 +20000fea: 459e cmp lr, r3 +20000fec: d90a bls.n 20001004 <__udivmoddi4+0x1f0> +20000fee: eb1c 0303 adds.w r3, ip, r3 +20000ff2: bf2c ite cs +20000ff4: 2101 movcs r1, #1 +20000ff6: 2100 movcc r1, #0 +20000ff8: 459e cmp lr, r3 +20000ffa: d902 bls.n 20001002 <__udivmoddi4+0x1ee> +20000ffc: 2900 cmp r1, #0 +20000ffe: f000 809e beq.w 2000113e <__udivmoddi4+0x32a> +20001002: 3801 subs r0, #1 +20001004: ea40 4007 orr.w r0, r0, r7, lsl #16 +20001008: eba3 030e sub.w r3, r3, lr +2000100c: fba0 e109 umull lr, r1, r0, r9 +20001010: 428b cmp r3, r1 +20001012: 4676 mov r6, lr +20001014: 460f mov r7, r1 +20001016: d302 bcc.n 2000101e <__udivmoddi4+0x20a> +20001018: d107 bne.n 2000102a <__udivmoddi4+0x216> +2000101a: 45f2 cmp sl, lr +2000101c: d205 bcs.n 2000102a <__udivmoddi4+0x216> +2000101e: ebbe 0609 subs.w r6, lr, r9 +20001022: eb61 010c sbc.w r1, r1, ip +20001026: 3801 subs r0, #1 +20001028: 460f mov r7, r1 +2000102a: b152 cbz r2, 20001042 <__udivmoddi4+0x22e> +2000102c: ebba 0106 subs.w r1, sl, r6 +20001030: eb63 0307 sbc.w r3, r3, r7 +20001034: fa03 f508 lsl.w r5, r3, r8 +20001038: 40e1 lsrs r1, r4 +2000103a: 40e3 lsrs r3, r4 +2000103c: 430d orrs r5, r1 +2000103e: e9c2 5300 strd r5, r3, [r2] +20001042: 2400 movs r4, #0 +20001044: e73b b.n 20000ebe <__udivmoddi4+0xaa> +20001046: 0873 lsrs r3, r6, #1 +20001048: 46b8 mov r8, r7 +2000104a: 0849 lsrs r1, r1, #1 +2000104c: 9701 str r7, [sp, #4] +2000104e: ea43 73c0 orr.w r3, r3, r0, lsl #31 +20001052: ea4f 7cc6 mov.w ip, r6, lsl #31 +20001056: 0c1c lsrs r4, r3, #16 +20001058: b29b uxth r3, r3 +2000105a: ea44 4401 orr.w r4, r4, r1, lsl #16 +2000105e: ea43 4304 orr.w r3, r3, r4, lsl #16 +20001062: fbb4 f4f7 udiv r4, r4, r7 +20001066: fbb1 f5f7 udiv r5, r1, r7 +2000106a: 211f movs r1, #31 +2000106c: 9801 ldr r0, [sp, #4] +2000106e: ea44 4405 orr.w r4, r4, r5, lsl #16 +20001072: 1a1b subs r3, r3, r0 +20001074: e750 b.n 20000f18 <__udivmoddi4+0x104> +20001076: 4619 mov r1, r3 +20001078: fa07 fe03 lsl.w lr, r7, r3 +2000107c: f1c3 0320 rsb r3, r3, #32 +20001080: fa00 f401 lsl.w r4, r0, r1 +20001084: ea4f 471e mov.w r7, lr, lsr #16 +20001088: 40d8 lsrs r0, r3 +2000108a: fa26 f303 lsr.w r3, r6, r3 +2000108e: fa1f f88e uxth.w r8, lr +20001092: fa06 fc01 lsl.w ip, r6, r1 +20001096: 4323 orrs r3, r4 +20001098: fbb0 f5f7 udiv r5, r0, r7 +2000109c: 0c1c lsrs r4, r3, #16 +2000109e: fb07 0015 mls r0, r7, r5, r0 +200010a2: ea44 4000 orr.w r0, r4, r0, lsl #16 +200010a6: fb05 f408 mul.w r4, r5, r8 +200010aa: 4284 cmp r4, r0 +200010ac: d94a bls.n 20001144 <__udivmoddi4+0x330> +200010ae: eb1e 0000 adds.w r0, lr, r0 +200010b2: bf2c ite cs +200010b4: 2601 movcs r6, #1 +200010b6: 2600 movcc r6, #0 +200010b8: 4284 cmp r4, r0 +200010ba: d900 bls.n 200010be <__udivmoddi4+0x2aa> +200010bc: b38e cbz r6, 20001122 <__udivmoddi4+0x30e> +200010be: 1b00 subs r0, r0, r4 +200010c0: 3d01 subs r5, #1 +200010c2: fbb0 f4f7 udiv r4, r0, r7 +200010c6: fb04 f608 mul.w r6, r4, r8 +200010ca: 46a1 mov r9, r4 +200010cc: 9601 str r6, [sp, #4] +200010ce: fb07 0019 mls r0, r7, r9, r0 +200010d2: b29b uxth r3, r3 +200010d4: 9e01 ldr r6, [sp, #4] +200010d6: ea43 4300 orr.w r3, r3, r0, lsl #16 +200010da: 42b3 cmp r3, r6 +200010dc: d2c6 bcs.n 2000106c <__udivmoddi4+0x258> +200010de: eb1e 0303 adds.w r3, lr, r3 +200010e2: bf2c ite cs +200010e4: 2001 movcs r0, #1 +200010e6: 2000 movcc r0, #0 +200010e8: 42b3 cmp r3, r6 +200010ea: d200 bcs.n 200010ee <__udivmoddi4+0x2da> +200010ec: b1a8 cbz r0, 2000111a <__udivmoddi4+0x306> +200010ee: f109 34ff add.w r4, r9, #4294967295 @ 0xffffffff +200010f2: e7bb b.n 2000106c <__udivmoddi4+0x258> +200010f4: ebb6 0c07 subs.w ip, r6, r7 +200010f8: eb60 0303 sbc.w r3, r0, r3 +200010fc: 2001 movs r0, #1 +200010fe: 461d mov r5, r3 +20001100: e6f7 b.n 20000ef2 <__udivmoddi4+0xde> +20001102: 44f4 add ip, lr +20001104: 3802 subs r0, #2 +20001106: e736 b.n 20000f76 <__udivmoddi4+0x162> +20001108: 3d02 subs r5, #2 +2000110a: 4473 add r3, lr +2000110c: e71b b.n 20000f46 <__udivmoddi4+0x132> +2000110e: 3c02 subs r4, #2 +20001110: 4473 add r3, lr +20001112: e6b1 b.n 20000e78 <__udivmoddi4+0x64> +20001114: 44f4 add ip, lr +20001116: 3d02 subs r5, #2 +20001118: e6c6 b.n 20000ea8 <__udivmoddi4+0x94> +2000111a: f1a9 0402 sub.w r4, r9, #2 +2000111e: 4473 add r3, lr +20001120: e7a4 b.n 2000106c <__udivmoddi4+0x258> +20001122: ebae 0404 sub.w r4, lr, r4 +20001126: 3d02 subs r5, #2 +20001128: 4420 add r0, r4 +2000112a: fbb0 f4f7 udiv r4, r0, r7 +2000112e: fb04 f608 mul.w r6, r4, r8 +20001132: 46a1 mov r9, r4 +20001134: 9601 str r6, [sp, #4] +20001136: e7ca b.n 200010ce <__udivmoddi4+0x2ba> +20001138: 3f02 subs r7, #2 +2000113a: 4461 add r1, ip +2000113c: e74b b.n 20000fd6 <__udivmoddi4+0x1c2> +2000113e: 3802 subs r0, #2 +20001140: 4463 add r3, ip +20001142: e75f b.n 20001004 <__udivmoddi4+0x1f0> +20001144: 1b00 subs r0, r0, r4 +20001146: fbb0 f4f7 udiv r4, r0, r7 +2000114a: fb04 f608 mul.w r6, r4, r8 +2000114e: 46a1 mov r9, r4 +20001150: 9601 str r6, [sp, #4] +20001152: e7bc b.n 200010ce <__udivmoddi4+0x2ba> + +20001154 <__aeabi_idiv0>: +20001154: 4770 bx lr +20001156: bf00 nop + +20001158 <__time_us_64_veneer>: +20001158: f85f f000 ldr.w pc, [pc] @ 2000115c <__time_us_64_veneer+0x4> +2000115c: 10001399 .word 0x10001399 + +20001160 <__best_effort_wfe_or_timeout_veneer>: +20001160: f85f f000 ldr.w pc, [pc] @ 20001164 <__best_effort_wfe_or_timeout_veneer+0x4> +20001164: 10001251 .word 0x10001251 + +20001168 <__panic_veneer>: +20001168: f85f f000 ldr.w pc, [pc] @ 2000116c <__panic_veneer+0x4> +2000116c: 1000054d .word 0x1000054d + +20001170 <__tu_fifo_write_veneer>: +20001170: f85f f000 ldr.w pc, [pc] @ 20001174 <__tu_fifo_write_veneer+0x4> +20001174: 100059d1 .word 0x100059d1 + +20001178 <__memset_veneer>: +20001178: f85f f000 ldr.w pc, [pc] @ 2000117c <__memset_veneer+0x4> +2000117c: 1000be2d .word 0x1000be2d + +20001180 <__tud_event_hook_cb_veneer>: +20001180: f85f f000 ldr.w pc, [pc] @ 20001184 <__tud_event_hook_cb_veneer+0x4> +20001184: 10004391 .word 0x10004391 + +20001188 : +20001188: 9999999a 40099999 00000003 00000007 .......@........ + +20001198 : +20001198: 0a0a0a0a .... + +2000119c : +2000119c: 00000057 W... + +200011a0 : +200011a0: 00000010 .... + +200011a4 : +200011a4: 00000000 .word 0x00000000 +200011a8: 00010000 .word 0x00010000 + ... +200011b4: 00020000 .word 0x00020000 + ... +200011c0: 00030000 .word 0x00030000 + ... +200011cc: 00040000 .word 0x00040000 + ... +200011d8: 00050000 .word 0x00050000 + ... +200011e4: 00ff0000 .word 0x00ff0000 +200011e8: 00000000 .word 0x00000000 + +200011ec : +200011ec: b501 push {r0, lr} +200011ee: 6848 ldr r0, [r1, #4] +200011f0: 3101 adds r1, #1 +200011f2: 468e mov lr, r1 +200011f4: 4700 bx r0 + +200011f6 : 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b/WEEK07/0x0017a_ctf/build/libargon2_ref.a new file mode 100644 index 0000000..8b50295 Binary files /dev/null and b/WEEK07/0x0017a_ctf/build/libargon2_ref.a differ diff --git a/WEEK07/0x0017a_ctf/build/libauth.a b/WEEK07/0x0017a_ctf/build/libauth.a new file mode 100644 index 0000000..fcb24b1 Binary files /dev/null and b/WEEK07/0x0017a_ctf/build/libauth.a differ diff --git a/WEEK07/0x0017a_ctf/build/libmbedtls_subset.a b/WEEK07/0x0017a_ctf/build/libmbedtls_subset.a new file mode 100644 index 0000000..38d39fd Binary files /dev/null and b/WEEK07/0x0017a_ctf/build/libmbedtls_subset.a differ diff --git a/WEEK07/0x0017a_ctf/include/auth.h b/WEEK07/0x0017a_ctf/include/auth.h new file mode 100644 index 0000000..e8ddc9e --- /dev/null +++ b/WEEK07/0x0017a_ctf/include/auth.h @@ -0,0 +1,143 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent/encryption-c-rp2350 +// File: auth.h +// Desc: Declares the Ouroboros authentication engine API for RP2350 firmware. +// Created: 2026 + +#ifndef AUTH_H +#define AUTH_H + +#include +#include +#include + +/** + * @brief Onboard LED GPIO pin number. + * + * The RP2350 Pico 2 onboard LED is connected to GPIO 25. Driven high + * on successful authentication and low on failure or idle. + */ +#define AUTH_LED_PIN 25u + +/** + * @brief Maximum accepted terminal passphrase length in bytes. + * + * The CLI accepts interactive human-entered passphrases up to 512 bytes, + * matching the hardened host demo boundary before policy validation. + */ +#define AUTH_PASSPHRASE_MAX_LEN 512u + +/** + * @brief Required number of lowercase words in the hardened passphrase. + * + * The embedded hardened workflow matches the host-side policy exactly: + * twelve lowercase ASCII words separated by whitespace. + */ +#define AUTH_REQUIRED_WORDS 12u + +/** + * @brief Hardened Argon2id salt size in bytes. + * + * Every demo artifact carries a per-ciphertext random 128-bit salt. + */ +#define AUTH_SALT_SIZE 16u + +/** + * @brief Hardened XChaCha20 nonce size in bytes. + * + * XChaCha20-Poly1305 consumes a 192-bit nonce in the outer construction. + */ +#define AUTH_NONCE_SIZE 24u + +/** + * @brief Subkey size in bytes derived from Argon2id. + * + * The AEAD key size is 256 bits. + */ +#define AUTH_KEY_SIZE 32u + +/** + * @brief AEAD authentication tag size in bytes. + * + * XChaCha20-Poly1305 appends a 128-bit authentication tag. + */ +#define AUTH_TAG_SIZE 16u + +/** + * @brief Plaintext payload size in bytes. + * + * The fixed dispatch payload is 48 bytes: LED state, UART bytes, + * and trailing reserved bytes matching the Rust hardened demo layout. + */ +#define AUTH_PAYLOAD_SIZE 48u + +/** + * @brief Full ciphertext-plus-tag artifact size in bytes. + * + * The encrypted payload is 48 bytes followed by a 16-byte tag. + */ +#define AUTH_CIPHERTEXT_SIZE (AUTH_PAYLOAD_SIZE + AUTH_TAG_SIZE) + +/** + * @brief Authentication result codes returned by the hardened engine. + * + * These values let the CLI distinguish policy failures from + * cryptographic authentication failures without guessing. + */ +typedef enum auth_result { + AUTH_RESULT_SUCCESS = 0, + AUTH_RESULT_POLICY_VIOLATION = 1, + AUTH_RESULT_AUTHENTICATION_FAILED = 2, + AUTH_RESULT_INTERNAL_ERROR = 3, +} auth_result_t; + +/** + * @brief Initialize the Ouroboros authentication module. + * + * Configures the onboard LED GPIO and marks the hardened engine as ready + * for passphrase authentication. + * + * @param None. + * @return bool true when initialization is successful, else false. + */ +bool auth_init(void); + +/** + * @brief Execute the hardened Ouroboros authentication pipeline. + * + * Validates the strict 12-word lowercase passphrase policy, derives the + * 256-bit AEAD key with Argon2id using artifact parameters, decrypts the + * embedded XChaCha20-Poly1305 ciphertext, and dispatches GPIO25/UART + * payload bytes on success. + * + * @param passphrase Pointer to passphrase bytes. + * @param passphrase_len Number of passphrase bytes. + * @return auth_result_t Detailed authentication outcome for the caller. + */ +auth_result_t auth_execute(const uint8_t *passphrase, + size_t passphrase_len); + +#endif // AUTH_H diff --git a/WEEK07/0x0017a_ctf/include/cli.h b/WEEK07/0x0017a_ctf/include/cli.h new file mode 100644 index 0000000..f14d375 --- /dev/null +++ b/WEEK07/0x0017a_ctf/include/cli.h @@ -0,0 +1,59 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: cli.h +// Desc: Declares the CLI UART passphrase input interface for Ouroboros. +// Created: 2026 + +#ifndef CLI_H +#define CLI_H + +#include + +/** + * @brief Print the UART passphrase prompt. + * + * Emits a minimal shell-style prompt followed by a space so the + * terminal clearly indicates that hardened passphrase input is expected. + * + * @param None. + * @return None. + */ +void print_prompt(void); + +/** + * @brief Service one UART polling step for passphrase input. + * + * Polls stdio for a character, dispatches backspace or newline + * handling, and appends printable characters to the passphrase + * buffer. Call repeatedly from the main loop. + * + * @param buf Pointer to mutable passphrase buffer. + * @param idx Pointer to current buffer length. + * @return None. + */ +void service_uart(char *buf, size_t *idx); + +#endif // CLI_H diff --git a/WEEK07/0x0017a_ctf/include/demo_artifact.h b/WEEK07/0x0017a_ctf/include/demo_artifact.h new file mode 100644 index 0000000..b7857a0 --- /dev/null +++ b/WEEK07/0x0017a_ctf/include/demo_artifact.h @@ -0,0 +1,60 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person +// obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without +// restriction, including without limitation the rights to use, +// copy, modify, merge, publish, distribute, sublicense, and/or +// sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following +// conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +// This file is generated by scripts/dec.py. Do not edit by hand. + +#ifndef DEMO_ARTIFACT_H +#define DEMO_ARTIFACT_H + +#include + +#define DEMO_ARTIFACT_FORMAT "ouroboros-hardened-demo-v1" +#define DEMO_MEMORY_KIB 64u +#define DEMO_ITERATIONS 3u +#define DEMO_PARALLELISM 1u + +static const uint8_t DEMO_SALT[16] = { + 0xF2u, 0xD5u, 0x18u, 0x63u, 0x9Au, 0x82u, 0x01u, 0x9Du, + 0xC2u, 0xD7u, 0xAFu, 0xA5u, 0xCDu, 0xB6u, 0xD8u, 0x71u +}; + +static const uint8_t DEMO_NONCE[24] = { + 0x1Cu, 0xEFu, 0x79u, 0x0Du, 0x77u, 0x9Eu, 0x7Cu, 0x04u, + 0xE7u, 0xF0u, 0x66u, 0xDDu, 0x90u, 0xD0u, 0x80u, 0x70u, + 0x87u, 0x97u, 0x67u, 0x1Fu, 0x79u, 0xEFu, 0xC4u, 0xE4u +}; + +static const uint8_t DEMO_CIPHERTEXT_AND_TAG[64] = { + 0x2Cu, 0x23u, 0xB2u, 0x7Eu, 0x95u, 0x62u, 0xB8u, 0xEDu, + 0x9Eu, 0x08u, 0xE0u, 0x6Du, 0xD9u, 0x9Du, 0xB4u, 0x91u, + 0x3Eu, 0x81u, 0x9Au, 0x77u, 0x8Bu, 0xB4u, 0x7Bu, 0x71u, + 0xBCu, 0x66u, 0x1Eu, 0x6Eu, 0x73u, 0x1Au, 0x81u, 0x54u, + 0xCDu, 0xB5u, 0x36u, 0xA4u, 0x76u, 0x7Eu, 0x9Bu, 0xF8u, + 0x53u, 0x3Eu, 0x03u, 0x1Du, 0xB8u, 0xE5u, 0xAEu, 0x7Au, + 0xADu, 0xB4u, 0x31u, 0xCFu, 0x12u, 0xD9u, 0xF9u, 0xC4u, + 0x5Fu, 0xA9u, 0xB9u, 0x4Bu, 0x80u, 0xDCu, 0xBBu, 0xDEu +}; + +#endif // DEMO_ARTIFACT_H diff --git a/WEEK07/0x0017a_ctf/include/mbedtls_config.h b/WEEK07/0x0017a_ctf/include/mbedtls_config.h new file mode 100644 index 0000000..b27211e --- /dev/null +++ b/WEEK07/0x0017a_ctf/include/mbedtls_config.h @@ -0,0 +1,39 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: mbedtls_config.h +// Desc: Configures the minimal mbedTLS cryptographic features required by +// the Ouroboros AEAD engine on RP2350. +// Created: 2026 + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +#define MBEDTLS_CHACHA20_C +#define MBEDTLS_CHACHAPOLY_C +#define MBEDTLS_POLY1305_C +#define MBEDTLS_PLATFORM_C + +#endif // MBEDTLS_CONFIG_H diff --git a/WEEK07/0x0017a_ctf/pico_sdk_import.cmake b/WEEK07/0x0017a_ctf/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK07/0x0017a_ctf/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK07/0x0017a_ctf/scripts/dec.py b/WEEK07/0x0017a_ctf/scripts/dec.py new file mode 100644 index 0000000..389efaf --- /dev/null +++ b/WEEK07/0x0017a_ctf/scripts/dec.py @@ -0,0 +1,944 @@ +"""Generate hardened demo artifacts for the RP2350 Ouroboros firmware. + +This script writes the same JSON schema used by the Rust demo and also emits +the generated C header consumed by the embedded firmware. +""" + +import argparse +import json +import platform +import secrets +import sys +from pathlib import Path +from typing import Optional + + +DEFAULT_PASSPHRASE = ( + "orbit olive ladder marble quartz canyon " + "ripple saddle violet ember walnut falcon" +) +DEFAULT_TEXT = "hello" +DEFAULT_OUTPUT_JSON = "scripts/demo_artifact.json" +DEFAULT_OUTPUT_HEADER = "include/demo_artifact.h" +DEFAULT_MEMORY_KIB = 64 +DEFAULT_ITERATIONS = 3 +DEFAULT_PARALLELISM = 1 +ARTIFACT_FORMAT = "ouroboros-hardened-demo-v1" + +_KEY_HELP = "12-word lowercase passphrase" +_TEXT_HELP = "Text to place in payload bytes 1..7" +_OUT_HELP = "Output JSON artifact path" +_HEADER_OUT_HELP = "Output generated C header path" +_FROM_JSON_HELP = ( + "Load existing JSON artifact and emit header without re-encrypting" +) +_CHECK_HEADER_HELP = ( + "Optional path to compare against generated header and fail if stale" +) +_SALT_HEX_HELP = "Optional fixed 16-byte salt as hex" +_NONCE_HEX_HELP = "Optional fixed 24-byte nonce as hex" +_NO_CRLF_HELP = "Do not append CRLF to payload text" +_LED_OFF_HELP = "Encode LED off instead of on" +_MEMORY_HELP = "Argon2 memory cost in KiB" +_ITERATIONS_HELP = "Argon2 time cost" +_PARALLELISM_HELP = "Argon2 parallel lanes" + +_POLICY_ERROR = ( + "Hardened mode requires exactly 12 lowercase ASCII words in --key." +) +_PAYLOAD_TOO_LONG = ( + "Output text is too long for fixed dispatch " + "(max 7 bytes after CRLF handling)." +) +_INVALID_JSON = "Artifact JSON at {0} is invalid JSON." +_MISMATCH_PREFIX = "Detected a Python native-extension architecture mismatch. " +_REINSTALL_DEPS = ("Recreate this virtual environment with a native Python " + "and reinstall deps:") +_REINSTALL_LINES = ( + "rm -rf .venv", + "python3 -m venv .venv", + "source .venv/bin/activate", + "python3 -m pip install -U pip setuptools wheel", + "python3 -m pip install argon2-cffi pynacl", +) +_HEADER_TEMPLATE = """// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person +// obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without +// restriction, including without limitation the rights to use, +// copy, modify, merge, publish, distribute, sublicense, and/or +// sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following +// conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +// DEALINGS IN THE SOFTWARE. +// +// This file is generated by scripts/dec.py. Do not edit by hand. + +#ifndef DEMO_ARTIFACT_H +#define DEMO_ARTIFACT_H + +#include + +#define DEMO_ARTIFACT_FORMAT "{artifact_format}" +#define DEMO_MEMORY_KIB {memory_kib}u +#define DEMO_ITERATIONS {iterations}u +#define DEMO_PARALLELISM {parallelism}u + +static const uint8_t DEMO_SALT[16] = {{ +{salt_body} +}}; + +static const uint8_t DEMO_NONCE[24] = {{ +{nonce_body} +}}; + +static const uint8_t DEMO_CIPHERTEXT_AND_TAG[64] = {{ +{cipher_body} +}}; + +#endif // DEMO_ARTIFACT_H +""" + + +def _raise_dependency_error(package_name, install_hint, exc): + """Raise a RuntimeError with environment-aware dependency diagnostics. + + Parameters + ---------- + package_name : str + Package common name for the error message. + install_hint : str + Pip install command in the error message. + exc : Exception + Import error observed while loading the native module. + + Returns + ------- + None + """ + message = "Hardened mode requires {0}. Install with: {1}".format( + package_name, install_hint) + message += _reinstall_message() if _is_arch_mismatch(exc) else "" + raise RuntimeError(message) from exc + + +def _is_arch_mismatch(exc): + """Report whether the interpreter likely has a native-extension mismatch. + + Parameters + ---------- + exc : Exception + Import error observed while loading the native module. + + Returns + ------- + bool + True when the error text matches a native architecture mismatch. + """ + detail = str(exc) + return ( + "incompatible architecture" in detail + or "_cffi_backend" in detail + or "mach-o file, but is an incompatible architecture" in detail + ) + + +def _reinstall_message(): + """Build the native-interpreter reinstall diagnostic text. + + Parameters + ---------- + None + + Returns + ------- + str + Newline-delimited machine and reinstall details, or an empty string. + """ + machine = platform.machine() + head = (_MISMATCH_PREFIX + + "Current interpreter reports machine=" + machine + + ", executable=" + sys.executable + ".") + lines = [" {0}".format(item) for item in _REINSTALL_LINES] + return ("\n" + head + "\n" + _REINSTALL_DEPS + "\n" + + "\n".join(lines)) + + +def _is_policy_compliant(passphrase): + """Return True when passphrase is exactly 12 lowercase ASCII words. + + Parameters + ---------- + passphrase : str + Candidate operator passphrase. + + Returns + ------- + bool + True when the passphrase satisfies the gate policy. + """ + words = passphrase.split() + if len(words) != 12: + return False + return all( + word and all(ch.isascii() and ch.islower() for ch in word) + for word in words + ) + + +def _build_payload(text_str, led_on=True, append_crlf=True): + """Build the fixed 48-byte payload dispatched by the firmware. + + Parameters + ---------- + text_str : str + Console text placed in payload bytes 1..7. + led_on : bool + True turns the LED byte on, False leaves it off. + append_crlf : bool + True appends CRLF to the console text. + + Returns + ------- + bytes + Fixed 48-byte dispatch payload. + """ + tx_bytes = text_str.encode() + (b"\r\n" if append_crlf else b"") + if len(tx_bytes) > 7: + raise ValueError(_PAYLOAD_TOO_LONG) + payload = bytearray(48) + payload[0] = 1 if led_on else 0 + payload[1:1 + len(tx_bytes)] = tx_bytes + return bytes(payload) + + +def _resolve_salt_nonce(salt, nonce): + """Confirm or generate the 16-byte salt and 24-byte nonce. + + Parameters + ---------- + salt : bytes or None + Optional fixed salt value. + nonce : bytes or None + Optional fixed nonce value. + + Returns + ------- + tuple + Confirmed (salt, nonce) byte values. + """ + salt_word = secrets.token_bytes(16) if salt is None else salt + nonce_word = secrets.token_bytes(24) if nonce is None else nonce + if len(salt_word) != 16: + raise ValueError("Hardened salt must be exactly 16 bytes.") + if len(nonce_word) != 24: + raise ValueError("Hardened nonce must be exactly 24 bytes.") + return salt_word, nonce_word + + +def _optional_hex(value, length, label): + """Decode an optional hex argument, leaving absent values as None. + + Parameters + ---------- + value : str or None + Hex string supplied on the command line. + length : int + Expected decoded byte length. + label : str + Field name used in validation errors. + + Returns + ------- + bytes or None + Decoded bytes, or None when value is absent. + """ + return _hex_decode(value, length, label) if value else None + + +def _load_argon2(): + """Load the Argon2 low-level binding with dependency diagnostics. + + Parameters + ---------- + None + + Returns + ------- + tuple + Argon2 Type enum and hash_secret_raw callable. + """ + try: + from argon2.low_level import Type, hash_secret_raw + except ImportError as exc: + install_hint = "python3 -m pip install argon2-cffi" + _raise_dependency_error("argon2-cffi", install_hint, exc) + return Type, hash_secret_raw + + +def _load_nacl_encrypt(): + """Load the XChaCha20-Poly1305 encrypt binding with diagnostics. + + Parameters + ---------- + None + + Returns + ------- + callable + PyNaCl crypto_aead_xchacha20poly1305_ietf_encrypt function. + """ + try: + from nacl.bindings import ( + crypto_aead_xchacha20poly1305_ietf_encrypt as encrypt, + ) + except ImportError as exc: + install_hint = "python3 -m pip install pynacl" + _raise_dependency_error("PyNaCl", install_hint, exc) + return encrypt + + +def _derive_hardened_key(passphrase, salt, memory_kib, iterations, + parallelism): + """Derive a 32-byte key with Argon2id. + + Parameters + ---------- + passphrase : str + Policy-compliant operator passphrase. + salt : bytes + 16-byte Argon2 salt. + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + + Returns + ------- + bytes + Derived 32-byte key. + """ + arg2_type, hash_secret_raw = _load_argon2() + args = ( + passphrase.encode(), salt, iterations, memory_kib, + parallelism, 32, arg2_type, + ) + return hash_secret_raw(*args) + + +def _entry_key(phrase, seed, memory_kib, iterations, parallelism): + """Derive the entry key word for the hardened artifact. + + Parameters + ---------- + phrase : str + Policy-compliant operator passphrase. + seed : bytes + 16-byte Argon2 salt. + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + + Returns + ------- + bytes + Derived 32-byte entry key. + """ + return _derive_hardened_key( + phrase, seed, memory_kib, iterations, parallelism + ) + + +def _build_key_material(phrase, salt, nonce, memory_kib, iterations, + parallelism): + """Resolve salt, nonce, and the entry key. + + Parameters + ---------- + phrase : str + Policy-compliant operator passphrase. + salt : bytes or None + Optional fixed salt value. + nonce : bytes or None + Optional fixed nonce value. + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + + Returns + ------- + tuple + Resolved (salt, nonce, key) values. + """ + seed, nonce_word = _resolve_salt_nonce(salt, nonce) + key = _entry_key(phrase, seed, memory_kib, iterations, parallelism) + return seed, nonce_word, key + + +def build_hardened_entry( + key_str, + text_str, + led_on=True, + append_crlf=True, + salt: Optional[bytes] = None, + nonce: Optional[bytes] = None, + memory_kib=DEFAULT_MEMORY_KIB, + iterations=DEFAULT_ITERATIONS, + parallelism=DEFAULT_PARALLELISM, +): + """Build a hardened encrypted entry with Argon2id + XChaCha20-Poly1305. + + Parameters + ---------- + key_str : str + Policy-compliant 12-word operator passphrase. + text_str : str + Console text placed in payload bytes 1..7. + led_on : bool + True turns the LED byte on, False leaves it off. + append_crlf : bool + True appends CRLF to the console text. + salt : bytes or None + Optional fixed 16-byte salt. + nonce : bytes or None + Optional fixed 24-byte nonce. + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + + Returns + ------- + tuple + Resulting (salt, nonce, ciphertext_and_tag) values. + """ + if not _is_policy_compliant(key_str): + raise ValueError(_POLICY_ERROR) + salt_word, nonce_word, key = _build_key_material( + key_str, salt, nonce, memory_kib, iterations, parallelism) + payload = _build_payload(text_str, led_on, append_crlf) + encrypt = _load_nacl_encrypt() + ciphertext_and_tag = encrypt(payload, b"", nonce_word, key) + return salt_word, nonce_word, ciphertext_and_tag + + +def _hex_decode(value, expected_len, label): + """Decode a hex string and validate the expected byte length. + + Parameters + ---------- + value : str + Hex string to decode. + expected_len : int + Required decoded byte length. + label : str + Field name used in validation errors. + + Returns + ------- + bytes + Decoded bytes of the expected length. + """ + try: + decoded = bytes.fromhex(value) + except ValueError as exc: + raise ValueError("{0} must be valid hex.".format(label)) from exc + if len(decoded) != expected_len: + message = "{0} must decode to exactly {1} bytes.".format( + label, expected_len) + raise ValueError(message) + return decoded + + +def _artifact_dict(memory_kib, iterations, parallelism, salt, nonce, cipher): + """Compose the canonical artifact dictionary. + + Parameters + ---------- + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + salt : bytes + 16-byte salt. + nonce : bytes + 24-byte nonce. + cipher : bytes + 64-byte ciphertext and tag. + + Returns + ------- + dict + Canonical artifact fields with hex-encoded byte values. + """ + return { + "format": ARTIFACT_FORMAT, "memory_kib": memory_kib, + "iterations": iterations, "parallelism": parallelism, + "salt_hex": salt.hex(), "nonce_hex": nonce.hex(), + "ciphertext_and_tag_hex": cipher.hex(), + } + + +def _format_c_array(data, width=8): + """Format bytes as an indented C array literal body. + + Parameters + ---------- + data : bytes + Bytes to serialize as a C array. + width : int + Byte values emitted per source line. + + Returns + ------- + str + Indented, comma-joined C array body. + """ + items = [f"0x{value:02X}u" for value in data] + rows = [", ".join(items[offset:offset + width]) + for offset in range(0, len(items), width)] + return ",\n".join(" " + row for row in rows) + + +def _render_header(artifact): + """Render the generated firmware header text from the artifact. + + Parameters + ---------- + artifact : dict + Canonical artifact dictionary. + + Returns + ------- + str + Complete generated C header text. + """ + cipher = bytes.fromhex(artifact["ciphertext_and_tag_hex"]) + return _HEADER_TEMPLATE.format( + artifact_format=ARTIFACT_FORMAT, memory_kib=artifact["memory_kib"], + iterations=artifact["iterations"], parallelism=artifact["parallelism"], + salt_body=_format_c_array(bytes.fromhex(artifact["salt_hex"])), + nonce_body=_format_c_array(bytes.fromhex(artifact["nonce_hex"])), + cipher_body=_format_c_array(cipher), + ) + + +def _write_header(path, artifact): + """Write the generated firmware header from the hardened artifact. + + Parameters + ---------- + path : str + Destination header file path. + artifact : dict + Canonical artifact dictionary. + + Returns + ------- + Path + Resolved destination header path. + """ + output_path = Path(path) + output_path.parent.mkdir(parents=True, exist_ok=True) + output_path.write_text(_render_header(artifact), encoding="utf-8") + return output_path.resolve() + + +def _parse_json_file(path): + """Load and parse the artifact JSON file. + + Parameters + ---------- + path : str + Artifact JSON file path. + + Returns + ------- + dict + Parsed JSON document. + """ + raw = Path(path).read_text(encoding="utf-8") + try: + parsed = json.loads(raw) + except json.JSONDecodeError as exc: + raise ValueError(_INVALID_JSON.format(path)) from exc + return parsed + + +def _validate_artifact_format(parsed): + """Reject artifact JSON with an unexpected format marker. + + Parameters + ---------- + parsed : dict + Parsed JSON document. + + Returns + ------- + None + """ + actual = parsed.get("format") + if actual != ARTIFACT_FORMAT: + raise ValueError( + "Artifact format must be '{0}', got '{1}'.".format( + ARTIFACT_FORMAT, actual)) + + +def _parsed_ints(parsed): + """Parse the integer cost fields from artifact JSON. + + Parameters + ---------- + parsed : dict + Parsed JSON document. + + Returns + ------- + list + Parsed memory_kib, iterations, and parallelism integer values. + """ + try: + int_names = ("memory_kib", "iterations", "parallelism") + return [int(parsed[name]) for name in int_names] + except (KeyError, TypeError, ValueError) as exc: + raise ValueError( + "Artifact must include integer memory_kib, " + "iterations, and parallelism fields.") from exc + + +def _artifact_ints(parsed): + """Unpack the three integer cost fields from artifact JSON. + + Parameters + ---------- + parsed : dict + Parsed JSON document. + + Returns + ------- + tuple + (memory_kib, iterations, parallelism) integer values. + """ + values = _parsed_ints(parsed) + return values[0], values[1], values[2] + + +def _artifact_from_parsed(parsed): + """Reconstruct a canonical artifact dict from parsed JSON. + + Parameters + ---------- + parsed : dict + Parsed JSON document. + + Returns + ------- + dict + Canonical artifact dictionary. + """ + _validate_artifact_format(parsed) + memory_kib, iterations, parallelism = _artifact_ints(parsed) + cipher_field = "ciphertext_and_tag_hex" + salt = _hex_decode(parsed.get("salt_hex", ""), 16, "salt_hex") + nonce = _hex_decode(parsed.get("nonce_hex", ""), 24, "nonce_hex") + cipher = _hex_decode(parsed.get(cipher_field, ""), 64, cipher_field) + return _artifact_dict( + memory_kib, iterations, parallelism, salt, nonce, cipher) + + +def _load_artifact_json(path): + """Load and validate a hardened artifact JSON for header generation. + + Parameters + ---------- + path : str + Artifact JSON file path. + + Returns + ------- + dict + Canonical artifact dictionary. + """ + parsed = _parse_json_file(path) + return _artifact_from_parsed(parsed) + + +def _check_header_match(generated_path, expected_path): + """Fail when the generated header does not match an expected file. + + Parameters + ---------- + generated_path : str + Generated header file path. + expected_path : str + Expected committed header file path. + + Returns + ------- + None + """ + generated = Path(generated_path).read_text(encoding="utf-8") + expected = Path(expected_path).read_text(encoding="utf-8") + if generated != expected: + raise RuntimeError( + "Generated header does not match committed " + "include/demo_artifact.h. Regenerate and commit " + "updated artifacts with scripts/dec.py.") + + +def _print_header_check(header_path, expected_path): + """Print the verified header match result. + + Parameters + ---------- + header_path : str + Generated header file path. + expected_path : str + Expected committed header file path. + + Returns + ------- + None + """ + _check_header_match(header_path, expected_path) + print("Verified header matches: {0}".format(Path(expected_path).resolve())) + + +def _parse_args(): + """Parse command-line arguments. + + Parameters + ---------- + None + + Returns + ------- + argparse.Namespace + Parsed command-line arguments. + """ + parser = argparse.ArgumentParser(description=__doc__) + for argument_group in _ARGUMENT_GROUPS: + for name, kwargs in argument_group: + parser.add_argument(name, **kwargs) + return parser.parse_args() + + +def _build_from_args(args, salt, nonce): + """Build the hardened entry from parsed arguments. + + Parameters + ---------- + args : argparse.Namespace + Parsed command-line arguments. + salt : bytes or None + Optional fixed salt value. + nonce : bytes or None + Optional fixed nonce value. + + Returns + ------- + tuple + Resulting (salt, nonce, ciphertext_and_tag) values. + """ + return build_hardened_entry( + key_str=args.key, text_str=args.text, led_on=not args.led_off, + append_crlf=not args.no_crlf, salt=salt, nonce=nonce, + memory_kib=args.memory_kib, iterations=args.iterations, + parallelism=args.parallelism, + ) + + +def _flush_outputs(args, salt, nonce, cipher): + """Write the artifact JSON and header, then return the header path. + + Parameters + ---------- + args : argparse.Namespace + Parsed command-line arguments. + salt : bytes + 16-byte salt. + nonce : bytes + 24-byte nonce. + cipher : bytes + 64-byte ciphertext and tag. + + Returns + ------- + Path + Resolved generated header path. + """ + json_path, artifact = _write_demo_json( + args.out, args.memory_kib, args.iterations, args.parallelism, + salt, nonce, cipher) + header_path = _write_header(args.header_out, artifact) + print("Wrote hardened demo artifact JSON: {0}".format(json_path)) + print("Wrote generated firmware header: {0}".format(header_path)) + return header_path + + +def _write_demo_json(path, memory_kib, iterations, parallelism, salt, + nonce, ciphertext_and_tag): + """Write the hardened JSON artifact consumed by docs and validation. + + Parameters + ---------- + path : str + Destination JSON file path. + memory_kib : int + Argon2 memory cost in KiB. + iterations : int + Argon2 time cost. + parallelism : int + Argon2 parallel lane count. + salt : bytes + 16-byte salt. + nonce : bytes + 24-byte nonce. + ciphertext_and_tag : bytes + 64-byte ciphertext and tag. + + Returns + ------- + tuple + Resolved (path, artifact) values. + """ + output_path = Path(path) + output_path.parent.mkdir(parents=True, exist_ok=True) + artifact = _artifact_dict( + memory_kib, iterations, parallelism, salt, nonce, ciphertext_and_tag) + text = json.dumps(artifact, indent=2) + "\n" + output_path.write_text(text, encoding="utf-8") + return output_path.resolve(), artifact + + +def _flush_from_json(args): + """Write the header from an existing artifact JSON. + + Parameters + ---------- + args : argparse.Namespace + Parsed command-line arguments. + + Returns + ------- + Path + Resolved generated header path. + """ + artifact = _load_artifact_json(args.from_json) + header_path = _write_header(args.header_out, artifact) + print("Wrote generated firmware header: {0}".format(header_path)) + return header_path + + +def _run_from_json(args): + """Generate the header only from committed artifact JSON. + + Parameters + ---------- + args : argparse.Namespace + Parsed command-line arguments. + + Returns + ------- + None + """ + header_path = _flush_from_json(args) + if args.check_header_path: + _print_header_check(header_path, args.check_header_path) + + +def _run_from_generate(args): + """Encrypt fresh artifact material, then emit JSON and the header. + + Parameters + ---------- + args : argparse.Namespace + Parsed command-line arguments. + + Returns + ------- + None + """ + salt = _optional_hex(args.salt_hex, 16, "salt_hex") + nonce = _optional_hex(args.nonce_hex, 24, "nonce_hex") + header_path = _flush_outputs( + args, *_build_from_args(args, salt, nonce), + ) + if args.check_header_path: + _print_header_check(header_path, args.check_header_path) + + +def main(): + """Generate the hardened artifact JSON and C header. + + Parameters + ---------- + None + + Returns + ------- + None + """ + args = _parse_args() + if args.from_json: + _run_from_json(args) + else: + _run_from_generate(args) + + +_ARGUMENT_GROUPS = ( + ( + ("--key", dict(default=DEFAULT_PASSPHRASE, help=_KEY_HELP)), + ("--salt-hex", dict(help=_SALT_HEX_HELP)), + ("--nonce-hex", dict(help=_NONCE_HEX_HELP)), + ), + ( + ("--text", dict(default=DEFAULT_TEXT, help=_TEXT_HELP)), + ("--out", dict(default=DEFAULT_OUTPUT_JSON, help=_OUT_HELP)), + ("--header-out", + dict(default=DEFAULT_OUTPUT_HEADER, help=_HEADER_OUT_HELP)), + ("--from-json", dict(help=_FROM_JSON_HELP)), + ("--no-crlf", dict(action="store_true", help=_NO_CRLF_HELP)), + ("--led-off", dict(action="store_true", help=_LED_OFF_HELP)), + ), + ( + ("--memory-kib", + dict(type=int, default=DEFAULT_MEMORY_KIB, help=_MEMORY_HELP)), + ("--iterations", + dict(type=int, default=DEFAULT_ITERATIONS, help=_ITERATIONS_HELP)), + ("--parallelism", + dict(type=int, default=DEFAULT_PARALLELISM, + help=_PARALLELISM_HELP)), + ("--check-header-path", dict(help=_CHECK_HEADER_HELP)), + ), +) + + +if __name__ == "__main__": + main() diff --git a/WEEK07/0x0017a_ctf/scripts/demo_artifact.json b/WEEK07/0x0017a_ctf/scripts/demo_artifact.json new file mode 100644 index 0000000..5c61254 --- /dev/null +++ b/WEEK07/0x0017a_ctf/scripts/demo_artifact.json @@ -0,0 +1,9 @@ +{ + "format": "ouroboros-hardened-demo-v1", + "memory_kib": 64, + "iterations": 3, + "parallelism": 1, + "salt_hex": "f2d518639a82019dc2d7afa5cdb6d871", + "nonce_hex": "1cef790d779e7c04e7f066dd90d080708797671f79efc4e4", + "ciphertext_and_tag_hex": "2c23b27e9562b8ed9e08e06dd99db4913e819a778bb47b71bc661e6e731a8154cdb536a4767e9bf8533e031db8e5ae7aadb431cf12d9f9c45fa9b94b80dcbbde" +} diff --git a/WEEK07/0x0017a_ctf/scripts/verify_ctf.py b/WEEK07/0x0017a_ctf/scripts/verify_ctf.py new file mode 100644 index 0000000..a5de5b1 --- /dev/null +++ b/WEEK07/0x0017a_ctf/scripts/verify_ctf.py @@ -0,0 +1,149 @@ +#!/usr/bin/env python3 +"""Verify every technical claim of Operation Copperhead against CTF-02.bin. + +Exits 0 only when every address, byte, hash, and derived value in CTF-R.md and +CTF-S.md matches the shipped image and the compiled ELF. +""" +import hashlib +import struct +import sys +from pathlib import Path + +BASE = 0x10000000 +ROOT = Path(__file__).resolve().parent.parent +BIN = ROOT / "CTF-02.bin" +UF2 = ROOT / "CTF-02.uf2" + +EXPECTED_BIN_SHA = "85330c37cd0897746b1af447e4bac371dde2042abd2d61d58a61fe2a8eef3537" +EXPECTED_UF2_SHA = "f3cd4840260db820d792758cecacc5297bef1971b9eacf7601279256d8af1eab" + +FRAME_THRESHOLD_A = 0x10000302 +FRAME_THRESHOLD_B = 0x10000312 +FRAME_TRACK = 0x1000C4B8 +FRAME_BLOCKLEN = 0x1000C4F0 +FRAME_SIGNALKEY = 0x1000C51C +FRAME_GATE = 0x1000C544 +FRAME_AUTH = 0x1000C57C +FRAME_OK = 0x1000C438 +FRAME_MISMATCH = 0x1000C43C +FRAME_SPEC_LITERAL = 0x100004FC +FRAME_DOUBLE = 0x1000EC60 +FRAME_SEED = 0x1000EC70 +FRAME_SALT = 0x1000CEEC +FRAME_NONCE = 0x1000CED4 +FRAME_CT = 0x1000CE94 + +DOUBLE_3_2 = bytes.fromhex("9A99999999990940") +DOUBLE_0_32 = bytes.fromhex("7B14AE47E17AD43F") +SEED_BAD = bytes.fromhex("0A0A0A0A") +SEED_GOOD = bytes.fromhex("7465206B") +SPEC_VALUE = 0x2D879291 +BUG_KEY = 0x915DCFF8 + +RESULTS = [] + + +def check(label, ok, detail=""): + """Record one verification result. + + Parameters + ---------- + label : str + Human-readable check name. + ok : bool + Whether the check passed. + detail : str + Extra context printed with the result. + + Returns + ------- + None + """ + RESULTS.append(ok) + print(f"[{'PASS' if ok else 'FAIL'}] {label} {detail}") + + +def rotl(v, s): + """Rotate a 32-bit value left.""" + return ((v << s) & 0xFFFFFFFF) | (v >> (32 - s)) + + +def qr_phase(a, b, c, d, s): + """Apply one ARX phase of a ChaCha quarter round.""" + a = (a + b) & 0xFFFFFFFF + d ^= a + d = rotl(d, s) + c = (c + d) & 0xFFFFFFFF + b ^= c + b = rotl(b, s) + return a, b, c, d + + +def derive(seed, iv): + """Derive the firmware signal key from a seed and IV.""" + a, b, c, d = seed, iv, 0x61707865, 0x3320646E + for _ in range(4): + for s in (16, 12, 8, 7): + a, b, c, d = qr_phase(a, b, c, d, s) + return (a ^ d) & 0xFFFFFFFF + + +def main(): + """Run all verification checks. + + Returns + ------- + int + Zero when every check passes, else one. + """ + data = BIN.read_bytes() + check("CTF-02.bin SHA-256", hashlib.sha256(data).hexdigest() == EXPECTED_BIN_SHA) + check("CTF-02.uf2 SHA-256", + hashlib.sha256(UF2.read_bytes()).hexdigest() == EXPECTED_UF2_SHA) + check("CTF-02.bin size", len(data) == 62308, f"({len(data)})") + check("vector table", data[0:32].hex() == + "002008205b0100101b0100101d01001011010010110100101101001011010010") + check("initial SP", struct.unpack(" + +// Non-zero once auth_init() has prepared the onboard LED GPIO. auth_execute() +// reports an internal error whenever this flag is not yet set, mirroring the +// reference construction from the encryption-c-rp2350 repository. +static bool g_auth_ready; + +/** + * @brief Clear a byte buffer. + * + * Writes zero to each byte in the caller-supplied buffer so derived keys + * and plaintext are not left resident in memory longer than needed. + * + * @param buf Pointer to mutable byte buffer. + * @param len Number of bytes to clear. + * @return None. + */ +static void clear_bytes(uint8_t *buf, size_t len) +{ + size_t i; + for (i = 0u; i < len; ++i) { + buf[i] = 0u; + } +} + +/** + * @brief Rotate a 32-bit value left. + * + * The HChaCha20 core uses 32-bit modular additions and left rotations in + * its quarter-round primitive. + * + * @param value Input 32-bit word. + * @param shift Rotation distance in bits. + * @return uint32_t Rotated result. + */ +static uint32_t rotl32(uint32_t value, uint8_t shift) +{ + return (value << shift) | (value >> (32u - shift)); +} + +/** + * @brief Load a 32-bit little-endian word from bytes. + * + * Converts four little-endian bytes into the word representation used by + * the HChaCha20 state machine. + * + * @param src Pointer to four readable bytes. + * @return uint32_t Parsed 32-bit word. + */ +static uint32_t load32_le(const uint8_t *src) +{ + return (uint32_t)src[0] | ((uint32_t)src[1] << 8u) | + ((uint32_t)src[2] << 16u) | ((uint32_t)src[3] << 24u); +} + +/** + * @brief Store a 32-bit word in little-endian byte order. + * + * Serializes one HChaCha20 state word into the caller-supplied output + * buffer. + * + * @param dst Pointer to four writable bytes. + * @param value 32-bit word to serialize. + * @return None. + */ +static void store32_le(uint8_t *dst, uint32_t value) +{ + dst[0] = (uint8_t)(value & 0xFFu); + dst[1] = (uint8_t)((value >> 8u) & 0xFFu); + dst[2] = (uint8_t)((value >> 16u) & 0xFFu); + dst[3] = (uint8_t)((value >> 24u) & 0xFFu); +} + +/** + * @brief Execute one ChaCha quarter-round. + * + * Mutates four state words in place according to the standard ChaCha20 + * ARX quarter-round used by the HChaCha20 subkey derivation. + * + * @param a Pointer to state word a. + * @param b Pointer to state word b. + * @param c Pointer to state word c. + * @param d Pointer to state word d. + * @return None. + */ +static void quarter_round(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d) +{ + *a += *b; *d ^= *a; *d = rotl32(*d, 16u); + *c += *d; *b ^= *c; *b = rotl32(*b, 12u); + *a += *b; *d ^= *a; *d = rotl32(*d, 8u); + *c += *d; *b ^= *c; *b = rotl32(*b, 7u); +} + +/** + * @brief Derive a 256-bit XChaCha20 subkey from key and nonce prefix. + * + * Runs the HChaCha20 core over the first 16 bytes of the 24-byte XChaCha + * nonce and emits the derived 32-byte subkey. + * + * @param key Pointer to 32-byte AEAD key. + * @param nonce Pointer to 24-byte XChaCha20 nonce. + * @param subkey Output 32-byte subkey buffer. + * @return None. + */ +static void hchacha20(const uint8_t key[32], const uint8_t nonce[24], uint8_t subkey[32]) +{ + uint32_t state[16] = { + 0x61707865u, 0x3320646Eu, 0x79622D32u, 0x6B206574u, + load32_le(&key[0]), load32_le(&key[4]), load32_le(&key[8]), load32_le(&key[12]), + load32_le(&key[16]), load32_le(&key[20]), load32_le(&key[24]), load32_le(&key[28]), + load32_le(&nonce[0]), load32_le(&nonce[4]), load32_le(&nonce[8]), load32_le(&nonce[12]), + }; + uint8_t round; + for (round = 0u; round < 10u; ++round) { + quarter_round(&state[0], &state[4], &state[8], &state[12]); + quarter_round(&state[1], &state[5], &state[9], &state[13]); + quarter_round(&state[2], &state[6], &state[10], &state[14]); + quarter_round(&state[3], &state[7], &state[11], &state[15]); + quarter_round(&state[0], &state[5], &state[10], &state[15]); + quarter_round(&state[1], &state[6], &state[11], &state[12]); + quarter_round(&state[2], &state[7], &state[8], &state[13]); + quarter_round(&state[3], &state[4], &state[9], &state[14]); + } + store32_le(&subkey[0], state[0]); + store32_le(&subkey[4], state[1]); + store32_le(&subkey[8], state[2]); + store32_le(&subkey[12], state[3]); + store32_le(&subkey[16], state[12]); + store32_le(&subkey[20], state[13]); + store32_le(&subkey[24], state[14]); + store32_le(&subkey[28], state[15]); +} + +/** + * @brief Build the inner 96-bit nonce used by ChaCha20-Poly1305. + * + * XChaCha20 converts the last 8 bytes of the 24-byte outer nonce into the + * final 12-byte IETF ChaCha nonce by prefixing four zero bytes. + * + * @param nonce Pointer to 24-byte XChaCha20 nonce. + * @param out Output 12-byte nonce buffer. + * @return None. + */ +static void build_inner_nonce(const uint8_t nonce[24], uint8_t out[12]) +{ + memset(out, 0, 4u); + memcpy(&out[4], &nonce[16], 8u); +} + +/** + * @brief Return true when a byte is ASCII whitespace used by the CLI. + * + * The firmware normalizes spaces, carriage returns, tabs, and newlines in + * the same broad spirit as split-whitespace host parsing. + * + * @param ch Input byte. + * @return bool true when byte is treated as whitespace. + */ +static bool is_space(uint8_t ch) +{ + return (ch == ' ') || (ch == '\t') || (ch == '\r') || (ch == '\n'); +} + +/** + * @brief Return true when a byte is lowercase ASCII. + * + * Hardened passphrases accept only lowercase a-z characters in each word. + * + * @param ch Input byte. + * @return bool true when byte is in the lowercase ASCII range. + */ +static bool is_lowercase_ascii(uint8_t ch) +{ + return (ch >= 'a') && (ch <= 'z'); +} + +/** + * @brief Validate the strict hardened passphrase policy. + * + * Accepts only passphrases containing exactly 12 lowercase ASCII words + * separated by whitespace. + * + * @param passphrase Pointer to passphrase bytes. + * @param passphrase_len Number of passphrase bytes. + * @return bool true when the passphrase satisfies the policy. + */ +static bool validate_hardened_passphrase(const uint8_t *passphrase, size_t passphrase_len) +{ + size_t i = 0u; + uint8_t words = 0u; + if ((passphrase == NULL) || (passphrase_len == 0u) || (passphrase_len > AUTH_PASSPHRASE_MAX_LEN)) { + return false; + } + while (i < passphrase_len) { + while ((i < passphrase_len) && is_space(passphrase[i])) { + ++i; + } + if (i == passphrase_len) { + break; + } + ++words; + while ((i < passphrase_len) && !is_space(passphrase[i])) { + if (!is_lowercase_ascii(passphrase[i])) { + return false; + } + ++i; + } + } + return words == AUTH_REQUIRED_WORDS; +} + +/** + * @brief Derive the 32-byte hardened key with Argon2id. + * + * Uses the generated artifact parameters and salt to derive the AEAD key + * that protects the embedded ciphertext. + * + * @param passphrase Pointer to passphrase bytes. + * @param passphrase_len Number of passphrase bytes. + * @param key_out Output 32-byte key buffer. + * @return bool true when derivation succeeds. + */ +static bool derive_hardened_key(const uint8_t *passphrase, size_t passphrase_len, uint8_t key_out[32]) +{ + return argon2id_hash_raw( + DEMO_ITERATIONS, + DEMO_MEMORY_KIB, + DEMO_PARALLELISM, + passphrase, + passphrase_len, + DEMO_SALT, + AUTH_SALT_SIZE, + key_out, + AUTH_KEY_SIZE) == ARGON2_OK; +} + +/** + * @brief Decrypt the embedded artifact with XChaCha20-Poly1305. + * + * Derives the XChaCha20 subkey with HChaCha20, converts the outer nonce to + * the inner 96-bit nonce, and verifies/decrypts the payload in one shot. + * + * @param key Pointer to 32-byte Argon2id-derived key. + * @param payload_out Output 48-byte plaintext payload buffer. + * @return bool true when tag verification and decryption succeed. + */ +static bool decrypt_artifact(const uint8_t key[32], uint8_t payload_out[AUTH_PAYLOAD_SIZE]) +{ + bool ok; + int rc; + uint8_t subkey[32]; + uint8_t inner_nonce[12]; + mbedtls_chachapoly_context ctx; + hchacha20(key, DEMO_NONCE, subkey); + build_inner_nonce(DEMO_NONCE, inner_nonce); + mbedtls_chachapoly_init(&ctx); + rc = mbedtls_chachapoly_setkey(&ctx, subkey); + if (rc == 0) { + rc = mbedtls_chachapoly_auth_decrypt( + &ctx, + AUTH_PAYLOAD_SIZE, + inner_nonce, + NULL, + 0u, + &DEMO_CIPHERTEXT_AND_TAG[AUTH_PAYLOAD_SIZE], + DEMO_CIPHERTEXT_AND_TAG, + payload_out); + } + mbedtls_chachapoly_free(&ctx); + clear_bytes(subkey, sizeof(subkey)); + clear_bytes(inner_nonce, sizeof(inner_nonce)); + ok = (rc == 0); + if (!ok) { + clear_bytes(payload_out, AUTH_PAYLOAD_SIZE); + } + return ok; +} + +/** + * @brief Dispatch the decrypted payload to GPIO25 and UART. + * + * Mirrors the Rust demo payload contract: byte 0 controls the LED, and + * bytes 1..7 are transmitted verbatim over UART. + * + * @param payload Pointer to decrypted 48-byte payload. + * @return None. + */ +static void dispatch_payload(const uint8_t payload[AUTH_PAYLOAD_SIZE]) +{ + uint8_t i; + gpio_put(AUTH_LED_PIN, payload[0] ? 1 : 0); + for (i = 1u; i < 8u; ++i) { + putchar_raw((char)payload[i]); + } +} + +bool auth_init(void) +{ + g_auth_ready = true; + gpio_init(AUTH_LED_PIN); + gpio_set_dir(AUTH_LED_PIN, GPIO_OUT); + gpio_put(AUTH_LED_PIN, 0); + return true; +} + +auth_result_t auth_execute(const uint8_t *passphrase, size_t passphrase_len) +{ + uint8_t key[AUTH_KEY_SIZE]; + uint8_t payload[AUTH_PAYLOAD_SIZE]; + if (!g_auth_ready) { + return AUTH_RESULT_INTERNAL_ERROR; + } + if (!validate_hardened_passphrase(passphrase, passphrase_len)) { + return AUTH_RESULT_POLICY_VIOLATION; + } + if (!derive_hardened_key(passphrase, passphrase_len, key)) { + return AUTH_RESULT_INTERNAL_ERROR; + } + if (!decrypt_artifact(key, payload)) { + clear_bytes(key, sizeof(key)); + return AUTH_RESULT_AUTHENTICATION_FAILED; + } + dispatch_payload(payload); + clear_bytes(payload, sizeof(payload)); + clear_bytes(key, sizeof(key)); + return AUTH_RESULT_SUCCESS; +} \ No newline at end of file diff --git a/WEEK07/0x0017a_ctf/src/cli.c b/WEEK07/0x0017a_ctf/src/cli.c new file mode 100644 index 0000000..cb6fc6c --- /dev/null +++ b/WEEK07/0x0017a_ctf/src/cli.c @@ -0,0 +1,149 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent/encryption-c-rp2350 +// File: cli.c +// Desc: Implements the CLI UART passphrase input interface for Ouroboros. +// Created: 2026 + +#include "cli.h" +#include "auth.h" +#include "pico/stdlib.h" +#include + +/** + * @brief Maximum number of passphrase characters accepted from UART. + * + * Limits the input buffer to the hardened engine boundary. A null + * terminator is written after the last character so the buffer must be + * declared with at least this many bytes. + */ +#define PASS_BUF_LEN AUTH_PASSPHRASE_MAX_LEN + +/** + * @brief Print the hardened passphrase policy hint. + * + * The firmware uses the same interactive policy as the host demo: + * exactly 12 lowercase words separated by spaces. + * + * @param None. + * @return None. + */ +static void print_policy_hint(void) +{ + printf("Enter exactly 12 lowercase words separated by spaces.\r\n"); +} + +/** + * @brief Append one received character to the passphrase buffer. + * + * Stores printable characters up to the buffer limit minus one to + * reserve room for a null terminator. Echoes the character back + * over UART for interactive typing feedback. + * + * @param ch Input character value. + * @param buf Pointer to mutable passphrase buffer. + * @param idx Pointer to current buffer length. + * @return None. + */ +static void append_char(int ch, char *buf, size_t *idx) +{ + if (*idx + 1u >= PASS_BUF_LEN) { + return; + } + buf[*idx] = (char)ch; + *idx += 1u; + putchar_raw((char)ch); +} + +/** + * @brief Remove one character from the passphrase buffer. + * + * Moves the index back by one and emits the backspace-escape + * sequence to erase the last echoed character on the terminal. + * + * @param idx Pointer to current buffer length. + * @return None. + */ +static void handle_backspace(size_t *idx) +{ + if (*idx == 0u) { + return; + } + *idx -= 1u; + printf("\b \b"); +} + +/** + * @brief Finalise and authenticate the current passphrase buffer. + * + * Null-terminates the input, runs the full Ouroboros authentication + * pipeline via auth_execute, prints policy guidance or authentication + * failure text as needed, and resets the buffer index for the next + * prompt cycle. + * + * @param buf Pointer to mutable passphrase buffer. + * @param idx Pointer to current buffer length. + * @return None. + */ +static void finish_passphrase(char *buf, size_t *idx) +{ + auth_result_t result; + putchar_raw('\r'); + putchar_raw('\n'); + buf[*idx] = '\0'; + result = auth_execute((const uint8_t *)buf, *idx); + if (result == AUTH_RESULT_POLICY_VIOLATION) { + gpio_put(AUTH_LED_PIN, 0); + print_policy_hint(); + } else if (result != AUTH_RESULT_SUCCESS) { + gpio_put(AUTH_LED_PIN, 0); + printf("Authentication failed.\r\n"); + } + *idx = 0u; + print_prompt(); +} + +void print_prompt(void) +{ + printf("\r\n> "); +} + +void service_uart(char *buf, size_t *idx) +{ + int ch = getchar_timeout_us(0); + if (ch == PICO_ERROR_TIMEOUT) { + tight_loop_contents(); + return; + } + if ((ch == '\b') || (ch == 127)) { + handle_backspace(idx); + return; + } + if ((ch == '\r') || (ch == '\n')) { + finish_passphrase(buf, idx); + return; + } + append_char(ch, buf, idx); +} diff --git a/WEEK07/0x0017a_ctf/src/main.c b/WEEK07/0x0017a_ctf/src/main.c new file mode 100644 index 0000000..d672f92 --- /dev/null +++ b/WEEK07/0x0017a_ctf/src/main.c @@ -0,0 +1,404 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: main.c +// Desc: DEEPLINE Metro interlocking host for the FINAL-PRACTICE exercise. +// Chains the strict Ouroboros operator gate (Argon2id plus +// XChaCha20-Poly1305) around the frozen relay telemetry puzzles. +// Created: 2026 + +#include +#include +#include +#include +#include "auth.h" +#include "pico/stdlib.h" + +// Block deviation classification ceiling below which an automated train +// release is permitted. BUG: PALLAS compiled in 95; the engineering limit +// is 60 (two redundant cmp sites in the ship image). +#define SAFE_THRESHOLD 95u + +// Number of 32-bit ARX state words used by the signal-key machinery. +#define ARX_WORDS 4u + +// Spec value of the derived signal key minted in the incident report. This is +// the key the honest build derives from GATE_SEED_GOOD and the derived IV. +#define SIGNAL_SPEC 0x2D879291u + +// ChaCha expand word used by the console-side derivation path. +#define GATE_SEED_GOOD 0x6B206574u + +// Track-circuit current deviation frozen by the dead pilot wire (amperes). +// A live reading is recalculated in the field; this image holds a wrong +// snapshot that engineers must decode from registers and SRAM. +static volatile uint32_t g_block_current = 87u; + +// Operator-facing block classification (drives the BLOCK STATE line). +static volatile uint32_t g_operator_state = 0u; + +// Automatic train release decision (drives the AUTO TRAIN line). +static volatile uint32_t g_dispatch_state = 0u; + +// Static per-cycle poll counter retained in .bss. Watch this from GDB. +static volatile uint32_t g_fault_polls = 0u; + +// ARX seed substituted by the poisoned build up to the signal derivation. +// BUG: 0x0A0A0A0A was fused in place of the "te k" expand word 0x6B206574. +static volatile uint32_t g_auth_seed = 0x0A0A0A0Au; + +// Derived signal key printed each cycle and checked against SIGNAL_SPEC. +static uint32_t g_signal_key = 0u; + +/** + * @brief Hold one track-block telemetry record for the interlocking. + * + * Stores the measured block length, the condition flag word, and the + * crossing identifier used by the automatic train protection logic. + */ +typedef struct telemetry_t { + double block_length_km; + uint32_t block_flags; + uint16_t crossing; +} telemetry_t; + +// Live telemetry record. BUG: block_length_km shipped as 3.2 km; the real +// BRIDGE-4 block is 0.32 km, far below the minimum release spacing. +static volatile telemetry_t g_telemetry = { 3.2, 0x3u, 7u }; + +// Interactive passphrase buffer and parser cursor for the operator gate. +static char g_linebuf[AUTH_PASSPHRASE_MAX_LEN]; +static size_t g_lineidx = 0u; + +/** + * @brief Rotate a 32-bit value left. + * + * @param value Input 32-bit word. + * @param shift Rotation distance in bits. + * @return uint32_t Rotated result. + */ +static uint32_t rotl32(uint32_t value, uint8_t shift) +{ + return (value << shift) | (value >> (32u - shift)); +} + +/** + * @brief Load a 32-bit little-endian word from bytes. + * + * @param src Pointer to four readable bytes. + * @return uint32_t Parsed 32-bit word. + */ +static uint32_t load32_le(const uint8_t *src) +{ + return (uint32_t)src[0] | ((uint32_t)src[1] << 8u) | + ((uint32_t)src[2] << 16u) | ((uint32_t)src[3] << 24u); +} + +/** + * @brief Store a 32-bit word in little-endian byte order. + * + * @param dst Pointer to four writable bytes. + * @param value 32-bit word to serialize. + * @return None. + */ +static void store32_le(uint8_t *dst, uint32_t value) +{ + dst[0] = (uint8_t)(value & 0xFFu); + dst[1] = (uint8_t)((value >> 8u) & 0xFFu); + dst[2] = (uint8_t)((value >> 16u) & 0xFFu); + dst[3] = (uint8_t)((value >> 24u) & 0xFFu); +} + +/** + * @brief Apply one additive-rotate-xor phase of a ChaCha quarter-round. + * + * @param a Pointer to state word A. + * @param b Pointer to state word B. + * @param c Pointer to state word C. + * @param d Pointer to state word D. + * @param shift Rotation distance in bits. + * @return None. + */ +static void qr_phase(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d, uint8_t shift) +{ + *a += *b; + *d ^= *a; + *d = rotl32(*d, shift); + *c += *d; + *b ^= *c; + *b = rotl32(*b, shift); +} + +/** + * @brief Execute one full ChaCha ARX quarter-round. + * + * @param a Pointer to state word A. + * @param b Pointer to state word B. + * @param c Pointer to state word C. + * @param d Pointer to state word D. + * @return None. + */ +static void quarter_round(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d) +{ + qr_phase(a, b, c, d, 16u); + qr_phase(a, b, c, d, 12u); + qr_phase(a, b, c, d, 8u); + qr_phase(a, b, c, d, 7u); +} + +/** + * @brief Run r full quarter-rounds over a four-word ARX state. + * + * @param a Pointer to state word A. + * @param b Pointer to state word B. + * @param c Pointer to state word C. + * @param d Pointer to state word D. + * @param rounds Number of full quarter-rounds to run. + * @return None. + */ +static void run_rounds(uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d, uint8_t rounds) +{ + uint8_t r; + for (r = 0u; r < rounds; ++r) { + quarter_round(a, b, c, d); + } +} + +/** + * @brief Derive a 32-bit ARX session key from a seed and IV. + * + * Runs four ChaCha quarter-rounds over the seed, the IV, and the ChaCha + * expand constants; returns state word A exclusive-or state word D. + * + * @param seed 32-bit seed word. + * @param iv 32-bit IV word. + * @return uint32_t Derived session key word. + */ +static uint32_t derive_session_key(uint32_t seed, uint32_t iv) +{ + uint32_t a = seed; + uint32_t b = iv; + uint32_t c = 0x61707865u; + uint32_t d = 0x3320646Eu; + run_rounds(&a, &b, &c, &d, 4u); + return a ^ d; +} + +/** + * @brief Derive the runtime IV from the good console seed word. + * + * @param None. + * @return uint32_t Derived IV word (0xC0F89829 in an honest image). + */ +static uint32_t derive_state_iv(void) +{ + return derive_session_key(GATE_SEED_GOOD, 0u); +} + +/** + * @brief Refresh the runtime signal key from the live seed and IV. + * + * Captures the freshly derived IV, then derives the final key word from + * the substituted seed. Break after each derivation to read the register. + * + * @param None. + * @return None. + */ +static void set_signal_state(void) +{ + uint32_t iv = derive_state_iv(); + g_signal_key = derive_session_key(g_auth_seed, iv); +} + +/** + * @brief Classify the frozen current reading against the compiled limit. + * + * Compares the frozen track-circuit current reading against SAFE_THRESHOLD + * and assigns the resulting boolean status to both g_operator_state and + * g_dispatch_state. + * + * @param None. + * @return None. + */ +static void classify_blocks(void) +{ + g_operator_state = (g_block_current < SAFE_THRESHOLD) ? 1u : 0u; + g_dispatch_state = (g_block_current < SAFE_THRESHOLD) ? 1u : 0u; +} + +/** + * @brief Print the relay boot identity and unconditional signal line. + * + * Emits the DEEPLINE authority banner, adaptive signal window, serial console + * configuration string, and nominal track status prompt over the console. + * + * @param None. + * @return None. + */ +static void print_identity(void) +{ + printf("DEEPLINE METRO AUTHORITY\r\n"); + printf("ADAPTIVE SIGNAL WINDOW: 38 MINUTES\r\n"); + printf("USB-CDC 115200 8N1 | AUTHORIZED LAB CONSOLE\r\n"); + printf("TRACK: NORMAL\r\n"); +} + +/** + * @brief Print the recurring interlocking status report once per cycle. + * + * Computes block length in meters, increments the fault poll counter, prints + * block state, train authorization status, fault poll tally, and signal key + * validation report, and re-emits the command prompt. + * + * @param None. + * @return None. + */ +static void print_status(void) +{ + uint32_t metres = (uint32_t)(g_telemetry.block_length_km * 1000.0); + g_fault_polls += 1u; + printf("BLOCK STATE: %s\r\n", g_operator_state ? "STABLE" : "CRITICAL"); + printf("AUTO TRAIN: %s\r\n", g_dispatch_state ? "AUTHORIZED" : "HELD"); + printf("BLOCK LENGTH: %u M\r\n", metres); + printf("FAULT POLLS: %u\r\n", g_fault_polls); + printf("SIGNAL KEY: 0x%08X %s\r\n", g_signal_key, + (g_signal_key == SIGNAL_SPEC) ? "OK" : "MISMATCH"); + printf("RESPONSE> "); +} + +/** + * @brief Append one received character to the passphrase buffer. + * + * Stores printable characters up to the maximum passphrase length boundary + * and echoes the character back to the console for interactive typing feedback. + * + * @param ch Input character value. + * @return None. + */ +static void append_char(int ch) +{ + if (g_lineidx + 1u >= AUTH_PASSPHRASE_MAX_LEN) { + return; + } + g_linebuf[g_lineidx] = (char)ch; + g_lineidx += 1u; + putchar_raw((char)ch); +} + +/** + * @brief Remove one character from the passphrase buffer. + * + * Decrements the buffer index and emits a backspace-space-backspace escape + * sequence to erase the character on the user's terminal. + * + * @param None. + * @return None. + */ +static void drop_char(void) +{ + if (g_lineidx == 0u) { + return; + } + g_lineidx -= 1u; + printf("\b \b"); +} + +/** + * @brief Authenticate the completed passphrase against the Ouroboros gate. + * + * Terminates the string buffer, invokes auth_execute, handles policy violation + * or authentication failure outputs, and resets the line buffer for the next input. + * + * @param None. + * @return None. + */ +static void submit_gate(void) +{ + auth_result_t result; + putchar_raw('\r'); + putchar_raw('\n'); + g_linebuf[g_lineidx] = '\0'; + result = auth_execute((const uint8_t *)g_linebuf, g_lineidx); + if (result == AUTH_RESULT_POLICY_VIOLATION) { + gpio_put(AUTH_LED_PIN, 0); + printf("Enter exactly 12 lowercase words separated by spaces.\r\n"); + } else if (result == AUTH_RESULT_SUCCESS) { + printf("AUTHORITY FRAME: VERIFIED\r\n"); + } else { + gpio_put(AUTH_LED_PIN, 0); + printf("Authentication failed.\r\n"); + } + g_lineidx = 0u; + printf("RESPONSE> "); +} + +/** + * @brief Poll the console for one passphrase input event. + * + * Reads a single character from standard input with zero timeout and routes + * backspace, newline/carriage return, or printable characters to their respective + * handlers. + * + * @param None. + * @return None. + */ +static void poll_console(void) +{ + int ch = getchar_timeout_us(0); + while (ch != PICO_ERROR_TIMEOUT) { + if ((ch == '\b') || (ch == 127)) { + drop_char(); + } else if ((ch == '\r') || (ch == '\n')) { + submit_gate(); + } else { + append_char(ch); + } + ch = getchar_timeout_us(0); + } +} + +/** + * @brief Drive the DEEPLINE relay console and operator gate forever. + * + * Initializes standard I/O and the authentication engine, classifies the track + * blocks, emits the initial system banner, and enters an infinite loop refreshing + * the signal state, reporting status, and servicing the console every two seconds. + * + * @param None. + * @return int Process exit code (never returns during normal operation). + */ +int main(void) +{ + stdio_init_all(); + auth_init(); + classify_blocks(); + print_identity(); + while (true) { + set_signal_state(); + print_status(); + poll_console(); + sleep_ms(2000u); + } +} \ No newline at end of file diff --git a/WEEK07/0x0017a_ctf/src/mbedtls_shims.c b/WEEK07/0x0017a_ctf/src/mbedtls_shims.c new file mode 100644 index 0000000..7c06a9d --- /dev/null +++ b/WEEK07/0x0017a_ctf/src/mbedtls_shims.c @@ -0,0 +1,49 @@ +// MIT License +// +// Copyright (c) 2026 Kevin Thomas +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +// Author: Kevin Thomas +// Email: kevin@mytechnotalent.com +// GitHub: https://github.com/mytechnotalent +// File: mbedtls_shims.c +// Desc: Implements platform zeroization shims required by mbedTLS on RP2350. +// Created: 2026 + +#include "mbedtls/platform_util.h" + +/** + * @brief Securely clear a memory region. + * + * Provides the mbedTLS platform zeroization hook for this firmware build. + * The volatile pointer prevents the compiler from optimizing away the + * clearing loop. + * + * @param buf Pointer to mutable memory region to clear. + * @param len Number of bytes to clear. + * @return None. + */ +void mbedtls_platform_zeroize(void *buf, size_t len) +{ + volatile unsigned char *ptr = (volatile unsigned char *)buf; + while (len-- > 0u) { + *ptr++ = 0u; + } +} diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/include/argon2.h b/WEEK07/0x0017a_ctf/third_party/argon2/include/argon2.h new file mode 100644 index 0000000..3980bb3 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/include/argon2.h @@ -0,0 +1,437 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef ARGON2_H +#define ARGON2_H + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/* Symbols visibility control */ +#ifdef A2_VISCTL +#define ARGON2_PUBLIC __attribute__((visibility("default"))) +#define ARGON2_LOCAL __attribute__ ((visibility ("hidden"))) +#elif defined(_MSC_VER) +#define ARGON2_PUBLIC __declspec(dllexport) +#define ARGON2_LOCAL +#else +#define ARGON2_PUBLIC +#define ARGON2_LOCAL +#endif + +/* + * Argon2 input parameter restrictions + */ + +/* Minimum and maximum number of lanes (degree of parallelism) */ +#define ARGON2_MIN_LANES UINT32_C(1) +#define ARGON2_MAX_LANES UINT32_C(0xFFFFFF) + +/* Minimum and maximum number of threads */ +#define ARGON2_MIN_THREADS UINT32_C(1) +#define ARGON2_MAX_THREADS UINT32_C(0xFFFFFF) + +/* Number of synchronization points between lanes per pass */ +#define ARGON2_SYNC_POINTS UINT32_C(4) + +/* Minimum and maximum digest size in bytes */ +#define ARGON2_MIN_OUTLEN UINT32_C(4) +#define ARGON2_MAX_OUTLEN UINT32_C(0xFFFFFFFF) + +/* Minimum and maximum number of memory blocks (each of BLOCK_SIZE bytes) */ +#define ARGON2_MIN_MEMORY (2 * ARGON2_SYNC_POINTS) /* 2 blocks per slice */ + +#define ARGON2_MIN(a, b) ((a) < (b) ? (a) : (b)) +/* Max memory size is addressing-space/2, topping at 2^32 blocks (4 TB) */ +#define ARGON2_MAX_MEMORY_BITS \ + ARGON2_MIN(UINT32_C(32), (sizeof(void *) * CHAR_BIT - 10 - 1)) +#define ARGON2_MAX_MEMORY \ + ARGON2_MIN(UINT32_C(0xFFFFFFFF), UINT64_C(1) << ARGON2_MAX_MEMORY_BITS) + +/* Minimum and maximum number of passes */ +#define ARGON2_MIN_TIME UINT32_C(1) +#define ARGON2_MAX_TIME UINT32_C(0xFFFFFFFF) + +/* Minimum and maximum password length in bytes */ +#define ARGON2_MIN_PWD_LENGTH UINT32_C(0) +#define ARGON2_MAX_PWD_LENGTH UINT32_C(0xFFFFFFFF) + +/* Minimum and maximum associated data length in bytes */ +#define ARGON2_MIN_AD_LENGTH UINT32_C(0) +#define ARGON2_MAX_AD_LENGTH UINT32_C(0xFFFFFFFF) + +/* Minimum and maximum salt length in bytes */ +#define ARGON2_MIN_SALT_LENGTH UINT32_C(8) +#define ARGON2_MAX_SALT_LENGTH UINT32_C(0xFFFFFFFF) + +/* Minimum and maximum key length in bytes */ +#define ARGON2_MIN_SECRET UINT32_C(0) +#define ARGON2_MAX_SECRET UINT32_C(0xFFFFFFFF) + +/* Flags to determine which fields are securely wiped (default = no wipe). */ +#define ARGON2_DEFAULT_FLAGS UINT32_C(0) +#define ARGON2_FLAG_CLEAR_PASSWORD (UINT32_C(1) << 0) +#define ARGON2_FLAG_CLEAR_SECRET (UINT32_C(1) << 1) + +/* Global flag to determine if we are wiping internal memory buffers. This flag + * is defined in core.c and defaults to 1 (wipe internal memory). */ +extern int FLAG_clear_internal_memory; + +/* Error codes */ +typedef enum Argon2_ErrorCodes { + ARGON2_OK = 0, + + ARGON2_OUTPUT_PTR_NULL = -1, + + ARGON2_OUTPUT_TOO_SHORT = -2, + ARGON2_OUTPUT_TOO_LONG = -3, + + ARGON2_PWD_TOO_SHORT = -4, + ARGON2_PWD_TOO_LONG = -5, + + ARGON2_SALT_TOO_SHORT = -6, + ARGON2_SALT_TOO_LONG = -7, + + ARGON2_AD_TOO_SHORT = -8, + ARGON2_AD_TOO_LONG = -9, + + ARGON2_SECRET_TOO_SHORT = -10, + ARGON2_SECRET_TOO_LONG = -11, + + ARGON2_TIME_TOO_SMALL = -12, + ARGON2_TIME_TOO_LARGE = -13, + + ARGON2_MEMORY_TOO_LITTLE = -14, + ARGON2_MEMORY_TOO_MUCH = -15, + + ARGON2_LANES_TOO_FEW = -16, + ARGON2_LANES_TOO_MANY = -17, + + ARGON2_PWD_PTR_MISMATCH = -18, /* NULL ptr with non-zero length */ + ARGON2_SALT_PTR_MISMATCH = -19, /* NULL ptr with non-zero length */ + ARGON2_SECRET_PTR_MISMATCH = -20, /* NULL ptr with non-zero length */ + ARGON2_AD_PTR_MISMATCH = -21, /* NULL ptr with non-zero length */ + + ARGON2_MEMORY_ALLOCATION_ERROR = -22, + + ARGON2_FREE_MEMORY_CBK_NULL = -23, + ARGON2_ALLOCATE_MEMORY_CBK_NULL = -24, + + ARGON2_INCORRECT_PARAMETER = -25, + ARGON2_INCORRECT_TYPE = -26, + + ARGON2_OUT_PTR_MISMATCH = -27, + + ARGON2_THREADS_TOO_FEW = -28, + ARGON2_THREADS_TOO_MANY = -29, + + ARGON2_MISSING_ARGS = -30, + + ARGON2_ENCODING_FAIL = -31, + + ARGON2_DECODING_FAIL = -32, + + ARGON2_THREAD_FAIL = -33, + + ARGON2_DECODING_LENGTH_FAIL = -34, + + ARGON2_VERIFY_MISMATCH = -35 +} argon2_error_codes; + +/* Memory allocator types --- for external allocation */ +typedef int (*allocate_fptr)(uint8_t **memory, size_t bytes_to_allocate); +typedef void (*deallocate_fptr)(uint8_t *memory, size_t bytes_to_allocate); + +/* Argon2 external data structures */ + +/* + ***** + * Context: structure to hold Argon2 inputs: + * output array and its length, + * password and its length, + * salt and its length, + * secret and its length, + * associated data and its length, + * number of passes, amount of used memory (in KBytes, can be rounded up a bit) + * number of parallel threads that will be run. + * All the parameters above affect the output hash value. + * Additionally, two function pointers can be provided to allocate and + * deallocate the memory (if NULL, memory will be allocated internally). + * Also, three flags indicate whether to erase password, secret as soon as they + * are pre-hashed (and thus not needed anymore), and the entire memory + ***** + * Simplest situation: you have output array out[8], password is stored in + * pwd[32], salt is stored in salt[16], you do not have keys nor associated + * data. You need to spend 1 GB of RAM and you run 5 passes of Argon2d with + * 4 parallel lanes. + * You want to erase the password, but you're OK with last pass not being + * erased. You want to use the default memory allocator. + * Then you initialize: + Argon2_Context(out,8,pwd,32,salt,16,NULL,0,NULL,0,5,1<<20,4,4,NULL,NULL,true,false,false,false) + */ +typedef struct Argon2_Context { + uint8_t *out; /* output array */ + uint32_t outlen; /* digest length */ + + uint8_t *pwd; /* password array */ + uint32_t pwdlen; /* password length */ + + uint8_t *salt; /* salt array */ + uint32_t saltlen; /* salt length */ + + uint8_t *secret; /* key array */ + uint32_t secretlen; /* key length */ + + uint8_t *ad; /* associated data array */ + uint32_t adlen; /* associated data length */ + + uint32_t t_cost; /* number of passes */ + uint32_t m_cost; /* amount of memory requested (KB) */ + uint32_t lanes; /* number of lanes */ + uint32_t threads; /* maximum number of threads */ + + uint32_t version; /* version number */ + + allocate_fptr allocate_cbk; /* pointer to memory allocator */ + deallocate_fptr free_cbk; /* pointer to memory deallocator */ + + uint32_t flags; /* array of bool options */ +} argon2_context; + +/* Argon2 primitive type */ +typedef enum Argon2_type { + Argon2_d = 0, + Argon2_i = 1, + Argon2_id = 2 +} argon2_type; + +/* Version of the algorithm */ +typedef enum Argon2_version { + ARGON2_VERSION_10 = 0x10, + ARGON2_VERSION_13 = 0x13, + ARGON2_VERSION_NUMBER = ARGON2_VERSION_13 +} argon2_version; + +/* + * Function that gives the string representation of an argon2_type. + * @param type The argon2_type that we want the string for + * @param uppercase Whether the string should have the first letter uppercase + * @return NULL if invalid type, otherwise the string representation. + */ +ARGON2_PUBLIC const char *argon2_type2string(argon2_type type, int uppercase); + +/* + * Function that performs memory-hard hashing with certain degree of parallelism + * @param context Pointer to the Argon2 internal structure + * @return Error code if smth is wrong, ARGON2_OK otherwise + */ +ARGON2_PUBLIC int argon2_ctx(argon2_context *context, argon2_type type); + +/** + * Hashes a password with Argon2i, producing an encoded hash + * @param t_cost Number of iterations + * @param m_cost Sets memory usage to m_cost kibibytes + * @param parallelism Number of threads and compute lanes + * @param pwd Pointer to password + * @param pwdlen Password size in bytes + * @param salt Pointer to salt + * @param saltlen Salt size in bytes + * @param hashlen Desired length of the hash in bytes + * @param encoded Buffer where to write the encoded hash + * @param encodedlen Size of the buffer (thus max size of the encoded hash) + * @pre Different parallelism levels will give different results + * @pre Returns ARGON2_OK if successful + */ +ARGON2_PUBLIC int argon2i_hash_encoded(const uint32_t t_cost, + const uint32_t m_cost, + const uint32_t parallelism, + const void *pwd, const size_t pwdlen, + const void *salt, const size_t saltlen, + const size_t hashlen, char *encoded, + const size_t encodedlen); + +/** + * Hashes a password with Argon2i, producing a raw hash at @hash + * @param t_cost Number of iterations + * @param m_cost Sets memory usage to m_cost kibibytes + * @param parallelism Number of threads and compute lanes + * @param pwd Pointer to password + * @param pwdlen Password size in bytes + * @param salt Pointer to salt + * @param saltlen Salt size in bytes + * @param hash Buffer where to write the raw hash - updated by the function + * @param hashlen Desired length of the hash in bytes + * @pre Different parallelism levels will give different results + * @pre Returns ARGON2_OK if successful + */ +ARGON2_PUBLIC int argon2i_hash_raw(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, + const size_t hashlen); + +ARGON2_PUBLIC int argon2d_hash_encoded(const uint32_t t_cost, + const uint32_t m_cost, + const uint32_t parallelism, + const void *pwd, const size_t pwdlen, + const void *salt, const size_t saltlen, + const size_t hashlen, char *encoded, + const size_t encodedlen); + +ARGON2_PUBLIC int argon2d_hash_raw(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, + const size_t hashlen); + +ARGON2_PUBLIC int argon2id_hash_encoded(const uint32_t t_cost, + const uint32_t m_cost, + const uint32_t parallelism, + const void *pwd, const size_t pwdlen, + const void *salt, const size_t saltlen, + const size_t hashlen, char *encoded, + const size_t encodedlen); + +ARGON2_PUBLIC int argon2id_hash_raw(const uint32_t t_cost, + const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, + const size_t hashlen); + +/* generic function underlying the above ones */ +ARGON2_PUBLIC int argon2_hash(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, + const size_t hashlen, char *encoded, + const size_t encodedlen, argon2_type type, + const uint32_t version); + +/** + * Verifies a password against an encoded string + * Encoded string is restricted as in validate_inputs() + * @param encoded String encoding parameters, salt, hash + * @param pwd Pointer to password + * @pre Returns ARGON2_OK if successful + */ +ARGON2_PUBLIC int argon2i_verify(const char *encoded, const void *pwd, + const size_t pwdlen); + +ARGON2_PUBLIC int argon2d_verify(const char *encoded, const void *pwd, + const size_t pwdlen); + +ARGON2_PUBLIC int argon2id_verify(const char *encoded, const void *pwd, + const size_t pwdlen); + +/* generic function underlying the above ones */ +ARGON2_PUBLIC int argon2_verify(const char *encoded, const void *pwd, + const size_t pwdlen, argon2_type type); + +/** + * Argon2d: Version of Argon2 that picks memory blocks depending + * on the password and salt. Only for side-channel-free + * environment!! + ***** + * @param context Pointer to current Argon2 context + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2d_ctx(argon2_context *context); + +/** + * Argon2i: Version of Argon2 that picks memory blocks + * independent on the password and salt. Good for side-channels, + * but worse w.r.t. tradeoff attacks if only one pass is used. + ***** + * @param context Pointer to current Argon2 context + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2i_ctx(argon2_context *context); + +/** + * Argon2id: Version of Argon2 where the first half-pass over memory is + * password-independent, the rest are password-dependent (on the password and + * salt). OK against side channels (they reduce to 1/2-pass Argon2i), and + * better with w.r.t. tradeoff attacks (similar to Argon2d). + ***** + * @param context Pointer to current Argon2 context + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2id_ctx(argon2_context *context); + +/** + * Verify if a given password is correct for Argon2d hashing + * @param context Pointer to current Argon2 context + * @param hash The password hash to verify. The length of the hash is + * specified by the context outlen member + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2d_verify_ctx(argon2_context *context, const char *hash); + +/** + * Verify if a given password is correct for Argon2i hashing + * @param context Pointer to current Argon2 context + * @param hash The password hash to verify. The length of the hash is + * specified by the context outlen member + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2i_verify_ctx(argon2_context *context, const char *hash); + +/** + * Verify if a given password is correct for Argon2id hashing + * @param context Pointer to current Argon2 context + * @param hash The password hash to verify. The length of the hash is + * specified by the context outlen member + * @return Zero if successful, a non zero error code otherwise + */ +ARGON2_PUBLIC int argon2id_verify_ctx(argon2_context *context, + const char *hash); + +/* generic function underlying the above ones */ +ARGON2_PUBLIC int argon2_verify_ctx(argon2_context *context, const char *hash, + argon2_type type); + +/** + * Get the associated error message for given error code + * @return The error message associated with the given error code + */ +ARGON2_PUBLIC const char *argon2_error_message(int error_code); + +/** + * Returns the encoded hash length for the given input parameters + * @param t_cost Number of iterations + * @param m_cost Memory usage in kibibytes + * @param parallelism Number of threads; used to compute lanes + * @param saltlen Salt size in bytes + * @param hashlen Hash size in bytes + * @param type The argon2_type that we want the encoded length for + * @return The encoded hash length in bytes + */ +ARGON2_PUBLIC size_t argon2_encodedlen(uint32_t t_cost, uint32_t m_cost, + uint32_t parallelism, uint32_t saltlen, + uint32_t hashlen, argon2_type type); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/argon2.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/argon2.c new file mode 100644 index 0000000..34da3d6 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/argon2.c @@ -0,0 +1,452 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#include +#include +#include + +#include "argon2.h" +#include "encoding.h" +#include "core.h" + +const char *argon2_type2string(argon2_type type, int uppercase) { + switch (type) { + case Argon2_d: + return uppercase ? "Argon2d" : "argon2d"; + case Argon2_i: + return uppercase ? "Argon2i" : "argon2i"; + case Argon2_id: + return uppercase ? "Argon2id" : "argon2id"; + } + + return NULL; +} + +int argon2_ctx(argon2_context *context, argon2_type type) { + /* 1. Validate all inputs */ + int result = validate_inputs(context); + uint32_t memory_blocks, segment_length; + argon2_instance_t instance; + + if (ARGON2_OK != result) { + return result; + } + + if (Argon2_d != type && Argon2_i != type && Argon2_id != type) { + return ARGON2_INCORRECT_TYPE; + } + + /* 2. Align memory size */ + /* Minimum memory_blocks = 8L blocks, where L is the number of lanes */ + memory_blocks = context->m_cost; + + if (memory_blocks < 2 * ARGON2_SYNC_POINTS * context->lanes) { + memory_blocks = 2 * ARGON2_SYNC_POINTS * context->lanes; + } + + segment_length = memory_blocks / (context->lanes * ARGON2_SYNC_POINTS); + /* Ensure that all segments have equal length */ + memory_blocks = segment_length * (context->lanes * ARGON2_SYNC_POINTS); + + instance.version = context->version; + instance.memory = NULL; + instance.passes = context->t_cost; + instance.memory_blocks = memory_blocks; + instance.segment_length = segment_length; + instance.lane_length = segment_length * ARGON2_SYNC_POINTS; + instance.lanes = context->lanes; + instance.threads = context->threads; + instance.type = type; + + if (instance.threads > instance.lanes) { + instance.threads = instance.lanes; + } + + /* 3. Initialization: Hashing inputs, allocating memory, filling first + * blocks + */ + result = initialize(&instance, context); + + if (ARGON2_OK != result) { + return result; + } + + /* 4. Filling memory */ + result = fill_memory_blocks(&instance); + + if (ARGON2_OK != result) { + return result; + } + /* 5. Finalization */ + finalize(context, &instance); + + return ARGON2_OK; +} + +int argon2_hash(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, const size_t saltlen, + void *hash, const size_t hashlen, char *encoded, + const size_t encodedlen, argon2_type type, + const uint32_t version){ + + argon2_context context; + int result; + uint8_t *out; + + if (pwdlen > ARGON2_MAX_PWD_LENGTH) { + return ARGON2_PWD_TOO_LONG; + } + + if (saltlen > ARGON2_MAX_SALT_LENGTH) { + return ARGON2_SALT_TOO_LONG; + } + + if (hashlen > ARGON2_MAX_OUTLEN) { + return ARGON2_OUTPUT_TOO_LONG; + } + + if (hashlen < ARGON2_MIN_OUTLEN) { + return ARGON2_OUTPUT_TOO_SHORT; + } + + out = malloc(hashlen); + if (!out) { + return ARGON2_MEMORY_ALLOCATION_ERROR; + } + + context.out = (uint8_t *)out; + context.outlen = (uint32_t)hashlen; + context.pwd = CONST_CAST(uint8_t *)pwd; + context.pwdlen = (uint32_t)pwdlen; + context.salt = CONST_CAST(uint8_t *)salt; + context.saltlen = (uint32_t)saltlen; + context.secret = NULL; + context.secretlen = 0; + context.ad = NULL; + context.adlen = 0; + context.t_cost = t_cost; + context.m_cost = m_cost; + context.lanes = parallelism; + context.threads = parallelism; + context.allocate_cbk = NULL; + context.free_cbk = NULL; + context.flags = ARGON2_DEFAULT_FLAGS; + context.version = version; + + result = argon2_ctx(&context, type); + + if (result != ARGON2_OK) { + clear_internal_memory(out, hashlen); + free(out); + return result; + } + + /* if raw hash requested, write it */ + if (hash) { + memcpy(hash, out, hashlen); + } + + /* if encoding requested, write it */ + if (encoded && encodedlen) { + if (encode_string(encoded, encodedlen, &context, type) != ARGON2_OK) { + clear_internal_memory(out, hashlen); /* wipe buffers if error */ + clear_internal_memory(encoded, encodedlen); + free(out); + return ARGON2_ENCODING_FAIL; + } + } + clear_internal_memory(out, hashlen); + free(out); + + return ARGON2_OK; +} + +int argon2i_hash_encoded(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, const size_t hashlen, + char *encoded, const size_t encodedlen) { + + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + NULL, hashlen, encoded, encodedlen, Argon2_i, + ARGON2_VERSION_NUMBER); +} + +int argon2i_hash_raw(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, const size_t hashlen) { + + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + hash, hashlen, NULL, 0, Argon2_i, ARGON2_VERSION_NUMBER); +} + +int argon2d_hash_encoded(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, const size_t hashlen, + char *encoded, const size_t encodedlen) { + + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + NULL, hashlen, encoded, encodedlen, Argon2_d, + ARGON2_VERSION_NUMBER); +} + +int argon2d_hash_raw(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, const size_t hashlen) { + + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + hash, hashlen, NULL, 0, Argon2_d, ARGON2_VERSION_NUMBER); +} + +int argon2id_hash_encoded(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, const size_t hashlen, + char *encoded, const size_t encodedlen) { + + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + NULL, hashlen, encoded, encodedlen, Argon2_id, + ARGON2_VERSION_NUMBER); +} + +int argon2id_hash_raw(const uint32_t t_cost, const uint32_t m_cost, + const uint32_t parallelism, const void *pwd, + const size_t pwdlen, const void *salt, + const size_t saltlen, void *hash, const size_t hashlen) { + return argon2_hash(t_cost, m_cost, parallelism, pwd, pwdlen, salt, saltlen, + hash, hashlen, NULL, 0, Argon2_id, + ARGON2_VERSION_NUMBER); +} + +static int argon2_compare(const uint8_t *b1, const uint8_t *b2, size_t len) { + size_t i; + uint8_t d = 0U; + + for (i = 0U; i < len; i++) { + d |= b1[i] ^ b2[i]; + } + return (int)((1 & ((d - 1) >> 8)) - 1); +} + +int argon2_verify(const char *encoded, const void *pwd, const size_t pwdlen, + argon2_type type) { + + argon2_context ctx; + uint8_t *desired_result = NULL; + + int ret = ARGON2_OK; + + size_t encoded_len; + uint32_t max_field_len; + + if (pwdlen > ARGON2_MAX_PWD_LENGTH) { + return ARGON2_PWD_TOO_LONG; + } + + if (encoded == NULL) { + return ARGON2_DECODING_FAIL; + } + + encoded_len = strlen(encoded); + if (encoded_len > UINT32_MAX) { + return ARGON2_DECODING_FAIL; + } + + /* No field can be longer than the encoded length */ + max_field_len = (uint32_t)encoded_len; + + ctx.saltlen = max_field_len; + ctx.outlen = max_field_len; + + ctx.salt = malloc(ctx.saltlen); + ctx.out = malloc(ctx.outlen); + if (!ctx.salt || !ctx.out) { + ret = ARGON2_MEMORY_ALLOCATION_ERROR; + goto fail; + } + + ctx.pwd = (uint8_t *)pwd; + ctx.pwdlen = (uint32_t)pwdlen; + + ret = decode_string(&ctx, encoded, type); + if (ret != ARGON2_OK) { + goto fail; + } + + /* Set aside the desired result, and get a new buffer. */ + desired_result = ctx.out; + ctx.out = malloc(ctx.outlen); + if (!ctx.out) { + ret = ARGON2_MEMORY_ALLOCATION_ERROR; + goto fail; + } + + ret = argon2_verify_ctx(&ctx, (char *)desired_result, type); + if (ret != ARGON2_OK) { + goto fail; + } + +fail: + free(ctx.salt); + free(ctx.out); + free(desired_result); + + return ret; +} + +int argon2i_verify(const char *encoded, const void *pwd, const size_t pwdlen) { + + return argon2_verify(encoded, pwd, pwdlen, Argon2_i); +} + +int argon2d_verify(const char *encoded, const void *pwd, const size_t pwdlen) { + + return argon2_verify(encoded, pwd, pwdlen, Argon2_d); +} + +int argon2id_verify(const char *encoded, const void *pwd, const size_t pwdlen) { + + return argon2_verify(encoded, pwd, pwdlen, Argon2_id); +} + +int argon2d_ctx(argon2_context *context) { + return argon2_ctx(context, Argon2_d); +} + +int argon2i_ctx(argon2_context *context) { + return argon2_ctx(context, Argon2_i); +} + +int argon2id_ctx(argon2_context *context) { + return argon2_ctx(context, Argon2_id); +} + +int argon2_verify_ctx(argon2_context *context, const char *hash, + argon2_type type) { + int ret = argon2_ctx(context, type); + if (ret != ARGON2_OK) { + return ret; + } + + if (argon2_compare((uint8_t *)hash, context->out, context->outlen)) { + return ARGON2_VERIFY_MISMATCH; + } + + return ARGON2_OK; +} + +int argon2d_verify_ctx(argon2_context *context, const char *hash) { + return argon2_verify_ctx(context, hash, Argon2_d); +} + +int argon2i_verify_ctx(argon2_context *context, const char *hash) { + return argon2_verify_ctx(context, hash, Argon2_i); +} + +int argon2id_verify_ctx(argon2_context *context, const char *hash) { + return argon2_verify_ctx(context, hash, Argon2_id); +} + +const char *argon2_error_message(int error_code) { + switch (error_code) { + case ARGON2_OK: + return "OK"; + case ARGON2_OUTPUT_PTR_NULL: + return "Output pointer is NULL"; + case ARGON2_OUTPUT_TOO_SHORT: + return "Output is too short"; + case ARGON2_OUTPUT_TOO_LONG: + return "Output is too long"; + case ARGON2_PWD_TOO_SHORT: + return "Password is too short"; + case ARGON2_PWD_TOO_LONG: + return "Password is too long"; + case ARGON2_SALT_TOO_SHORT: + return "Salt is too short"; + case ARGON2_SALT_TOO_LONG: + return "Salt is too long"; + case ARGON2_AD_TOO_SHORT: + return "Associated data is too short"; + case ARGON2_AD_TOO_LONG: + return "Associated data is too long"; + case ARGON2_SECRET_TOO_SHORT: + return "Secret is too short"; + case ARGON2_SECRET_TOO_LONG: + return "Secret is too long"; + case ARGON2_TIME_TOO_SMALL: + return "Time cost is too small"; + case ARGON2_TIME_TOO_LARGE: + return "Time cost is too large"; + case ARGON2_MEMORY_TOO_LITTLE: + return "Memory cost is too small"; + case ARGON2_MEMORY_TOO_MUCH: + return "Memory cost is too large"; + case ARGON2_LANES_TOO_FEW: + return "Too few lanes"; + case ARGON2_LANES_TOO_MANY: + return "Too many lanes"; + case ARGON2_PWD_PTR_MISMATCH: + return "Password pointer is NULL, but password length is not 0"; + case ARGON2_SALT_PTR_MISMATCH: + return "Salt pointer is NULL, but salt length is not 0"; + case ARGON2_SECRET_PTR_MISMATCH: + return "Secret pointer is NULL, but secret length is not 0"; + case ARGON2_AD_PTR_MISMATCH: + return "Associated data pointer is NULL, but ad length is not 0"; + case ARGON2_MEMORY_ALLOCATION_ERROR: + return "Memory allocation error"; + case ARGON2_FREE_MEMORY_CBK_NULL: + return "The free memory callback is NULL"; + case ARGON2_ALLOCATE_MEMORY_CBK_NULL: + return "The allocate memory callback is NULL"; + case ARGON2_INCORRECT_PARAMETER: + return "Argon2_Context context is NULL"; + case ARGON2_INCORRECT_TYPE: + return "There is no such version of Argon2"; + case ARGON2_OUT_PTR_MISMATCH: + return "Output pointer mismatch"; + case ARGON2_THREADS_TOO_FEW: + return "Not enough threads"; + case ARGON2_THREADS_TOO_MANY: + return "Too many threads"; + case ARGON2_MISSING_ARGS: + return "Missing arguments"; + case ARGON2_ENCODING_FAIL: + return "Encoding failed"; + case ARGON2_DECODING_FAIL: + return "Decoding failed"; + case ARGON2_THREAD_FAIL: + return "Threading failure"; + case ARGON2_DECODING_LENGTH_FAIL: + return "Some of encoded parameters are too long or too short"; + case ARGON2_VERIFY_MISMATCH: + return "The password does not match the supplied hash"; + default: + return "Unknown error code"; + } +} + +size_t argon2_encodedlen(uint32_t t_cost, uint32_t m_cost, uint32_t parallelism, + uint32_t saltlen, uint32_t hashlen, argon2_type type) { + return strlen("$$v=$m=,t=,p=$$") + strlen(argon2_type2string(type, 0)) + + numlen(t_cost) + numlen(m_cost) + numlen(parallelism) + + b64len(saltlen) + b64len(hashlen) + numlen(ARGON2_VERSION_NUMBER) + 1; +} diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2-impl.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2-impl.h new file mode 100644 index 0000000..86d0d5c --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2-impl.h @@ -0,0 +1,156 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef PORTABLE_BLAKE2_IMPL_H +#define PORTABLE_BLAKE2_IMPL_H + +#include +#include + +#ifdef _WIN32 +#define BLAKE2_INLINE __inline +#elif defined(__GNUC__) || defined(__clang__) +#define BLAKE2_INLINE __inline__ +#else +#define BLAKE2_INLINE +#endif + +/* Argon2 Team - Begin Code */ +/* + Not an exhaustive list, but should cover the majority of modern platforms + Additionally, the code will always be correct---this is only a performance + tweak. +*/ +#if (defined(__BYTE_ORDER__) && \ + (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)) || \ + defined(__LITTLE_ENDIAN__) || defined(__ARMEL__) || defined(__MIPSEL__) || \ + defined(__AARCH64EL__) || defined(__amd64__) || defined(__i386__) || \ + defined(_M_IX86) || defined(_M_X64) || defined(_M_AMD64) || \ + defined(_M_ARM) +#define NATIVE_LITTLE_ENDIAN +#endif +/* Argon2 Team - End Code */ + +static BLAKE2_INLINE uint32_t load32(const void *src) { +#if defined(NATIVE_LITTLE_ENDIAN) + uint32_t w; + memcpy(&w, src, sizeof w); + return w; +#else + const uint8_t *p = (const uint8_t *)src; + uint32_t w = *p++; + w |= (uint32_t)(*p++) << 8; + w |= (uint32_t)(*p++) << 16; + w |= (uint32_t)(*p++) << 24; + return w; +#endif +} + +static BLAKE2_INLINE uint64_t load64(const void *src) { +#if defined(NATIVE_LITTLE_ENDIAN) + uint64_t w; + memcpy(&w, src, sizeof w); + return w; +#else + const uint8_t *p = (const uint8_t *)src; + uint64_t w = *p++; + w |= (uint64_t)(*p++) << 8; + w |= (uint64_t)(*p++) << 16; + w |= (uint64_t)(*p++) << 24; + w |= (uint64_t)(*p++) << 32; + w |= (uint64_t)(*p++) << 40; + w |= (uint64_t)(*p++) << 48; + w |= (uint64_t)(*p++) << 56; + return w; +#endif +} + +static BLAKE2_INLINE void store32(void *dst, uint32_t w) { +#if defined(NATIVE_LITTLE_ENDIAN) + memcpy(dst, &w, sizeof w); +#else + uint8_t *p = (uint8_t *)dst; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; +#endif +} + +static BLAKE2_INLINE void store64(void *dst, uint64_t w) { +#if defined(NATIVE_LITTLE_ENDIAN) + memcpy(dst, &w, sizeof w); +#else + uint8_t *p = (uint8_t *)dst; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; +#endif +} + +static BLAKE2_INLINE uint64_t load48(const void *src) { + const uint8_t *p = (const uint8_t *)src; + uint64_t w = *p++; + w |= (uint64_t)(*p++) << 8; + w |= (uint64_t)(*p++) << 16; + w |= (uint64_t)(*p++) << 24; + w |= (uint64_t)(*p++) << 32; + w |= (uint64_t)(*p++) << 40; + return w; +} + +static BLAKE2_INLINE void store48(void *dst, uint64_t w) { + uint8_t *p = (uint8_t *)dst; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; + w >>= 8; + *p++ = (uint8_t)w; +} + +static BLAKE2_INLINE uint32_t rotr32(const uint32_t w, const unsigned c) { + return (w >> c) | (w << (32 - c)); +} + +static BLAKE2_INLINE uint64_t rotr64(const uint64_t w, const unsigned c) { + return (w >> c) | (w << (64 - c)); +} + +void clear_internal_memory(void *v, size_t n); + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2.h new file mode 100644 index 0000000..501c6a3 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2.h @@ -0,0 +1,89 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef PORTABLE_BLAKE2_H +#define PORTABLE_BLAKE2_H + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +enum blake2b_constant { + BLAKE2B_BLOCKBYTES = 128, + BLAKE2B_OUTBYTES = 64, + BLAKE2B_KEYBYTES = 64, + BLAKE2B_SALTBYTES = 16, + BLAKE2B_PERSONALBYTES = 16 +}; + +#pragma pack(push, 1) +typedef struct __blake2b_param { + uint8_t digest_length; /* 1 */ + uint8_t key_length; /* 2 */ + uint8_t fanout; /* 3 */ + uint8_t depth; /* 4 */ + uint32_t leaf_length; /* 8 */ + uint64_t node_offset; /* 16 */ + uint8_t node_depth; /* 17 */ + uint8_t inner_length; /* 18 */ + uint8_t reserved[14]; /* 32 */ + uint8_t salt[BLAKE2B_SALTBYTES]; /* 48 */ + uint8_t personal[BLAKE2B_PERSONALBYTES]; /* 64 */ +} blake2b_param; +#pragma pack(pop) + +typedef struct __blake2b_state { + uint64_t h[8]; + uint64_t t[2]; + uint64_t f[2]; + uint8_t buf[BLAKE2B_BLOCKBYTES]; + unsigned buflen; + unsigned outlen; + uint8_t last_node; +} blake2b_state; + +/* Ensure param structs have not been wrongly padded */ +/* Poor man's static_assert */ +enum { + blake2_size_check_0 = 1 / !!(CHAR_BIT == 8), + blake2_size_check_2 = + 1 / !!(sizeof(blake2b_param) == sizeof(uint64_t) * CHAR_BIT) +}; + +/* Streaming API */ +ARGON2_LOCAL int blake2b_init(blake2b_state *S, size_t outlen); +ARGON2_LOCAL int blake2b_init_key(blake2b_state *S, size_t outlen, const void *key, + size_t keylen); +ARGON2_LOCAL int blake2b_init_param(blake2b_state *S, const blake2b_param *P); +ARGON2_LOCAL int blake2b_update(blake2b_state *S, const void *in, size_t inlen); +ARGON2_LOCAL int blake2b_final(blake2b_state *S, void *out, size_t outlen); + +/* Simple API */ +ARGON2_LOCAL int blake2b(void *out, size_t outlen, const void *in, size_t inlen, + const void *key, size_t keylen); + +/* Argon2 Team - Begin Code */ +ARGON2_LOCAL int blake2b_long(void *out, size_t outlen, const void *in, size_t inlen); +/* Argon2 Team - End Code */ + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2b.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2b.c new file mode 100644 index 0000000..3b519dd --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blake2b.c @@ -0,0 +1,390 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#include +#include +#include + +#include "blake2.h" +#include "blake2-impl.h" + +static const uint64_t blake2b_IV[8] = { + UINT64_C(0x6a09e667f3bcc908), UINT64_C(0xbb67ae8584caa73b), + UINT64_C(0x3c6ef372fe94f82b), UINT64_C(0xa54ff53a5f1d36f1), + UINT64_C(0x510e527fade682d1), UINT64_C(0x9b05688c2b3e6c1f), + UINT64_C(0x1f83d9abfb41bd6b), UINT64_C(0x5be0cd19137e2179)}; + +static const unsigned int blake2b_sigma[12][16] = { + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, + {14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3}, + {11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4}, + {7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8}, + {9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13}, + {2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9}, + {12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11}, + {13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10}, + {6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5}, + {10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, + {14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3}, +}; + +static BLAKE2_INLINE void blake2b_set_lastnode(blake2b_state *S) { + S->f[1] = (uint64_t)-1; +} + +static BLAKE2_INLINE void blake2b_set_lastblock(blake2b_state *S) { + if (S->last_node) { + blake2b_set_lastnode(S); + } + S->f[0] = (uint64_t)-1; +} + +static BLAKE2_INLINE void blake2b_increment_counter(blake2b_state *S, + uint64_t inc) { + S->t[0] += inc; + S->t[1] += (S->t[0] < inc); +} + +static BLAKE2_INLINE void blake2b_invalidate_state(blake2b_state *S) { + clear_internal_memory(S, sizeof(*S)); /* wipe */ + blake2b_set_lastblock(S); /* invalidate for further use */ +} + +static BLAKE2_INLINE void blake2b_init0(blake2b_state *S) { + memset(S, 0, sizeof(*S)); + memcpy(S->h, blake2b_IV, sizeof(S->h)); +} + +int blake2b_init_param(blake2b_state *S, const blake2b_param *P) { + const unsigned char *p = (const unsigned char *)P; + unsigned int i; + + if (NULL == P || NULL == S) { + return -1; + } + + blake2b_init0(S); + /* IV XOR Parameter Block */ + for (i = 0; i < 8; ++i) { + S->h[i] ^= load64(&p[i * sizeof(S->h[i])]); + } + S->outlen = P->digest_length; + return 0; +} + +/* Sequential blake2b initialization */ +int blake2b_init(blake2b_state *S, size_t outlen) { + blake2b_param P; + + if (S == NULL) { + return -1; + } + + if ((outlen == 0) || (outlen > BLAKE2B_OUTBYTES)) { + blake2b_invalidate_state(S); + return -1; + } + + /* Setup Parameter Block for unkeyed BLAKE2 */ + P.digest_length = (uint8_t)outlen; + P.key_length = 0; + P.fanout = 1; + P.depth = 1; + P.leaf_length = 0; + P.node_offset = 0; + P.node_depth = 0; + P.inner_length = 0; + memset(P.reserved, 0, sizeof(P.reserved)); + memset(P.salt, 0, sizeof(P.salt)); + memset(P.personal, 0, sizeof(P.personal)); + + return blake2b_init_param(S, &P); +} + +int blake2b_init_key(blake2b_state *S, size_t outlen, const void *key, + size_t keylen) { + blake2b_param P; + + if (S == NULL) { + return -1; + } + + if ((outlen == 0) || (outlen > BLAKE2B_OUTBYTES)) { + blake2b_invalidate_state(S); + return -1; + } + + if ((key == 0) || (keylen == 0) || (keylen > BLAKE2B_KEYBYTES)) { + blake2b_invalidate_state(S); + return -1; + } + + /* Setup Parameter Block for keyed BLAKE2 */ + P.digest_length = (uint8_t)outlen; + P.key_length = (uint8_t)keylen; + P.fanout = 1; + P.depth = 1; + P.leaf_length = 0; + P.node_offset = 0; + P.node_depth = 0; + P.inner_length = 0; + memset(P.reserved, 0, sizeof(P.reserved)); + memset(P.salt, 0, sizeof(P.salt)); + memset(P.personal, 0, sizeof(P.personal)); + + if (blake2b_init_param(S, &P) < 0) { + blake2b_invalidate_state(S); + return -1; + } + + { + uint8_t block[BLAKE2B_BLOCKBYTES]; + memset(block, 0, BLAKE2B_BLOCKBYTES); + memcpy(block, key, keylen); + blake2b_update(S, block, BLAKE2B_BLOCKBYTES); + /* Burn the key from stack */ + clear_internal_memory(block, BLAKE2B_BLOCKBYTES); + } + return 0; +} + +static void blake2b_compress(blake2b_state *S, const uint8_t *block) { + uint64_t m[16]; + uint64_t v[16]; + unsigned int i, r; + + for (i = 0; i < 16; ++i) { + m[i] = load64(block + i * sizeof(m[i])); + } + + for (i = 0; i < 8; ++i) { + v[i] = S->h[i]; + } + + v[8] = blake2b_IV[0]; + v[9] = blake2b_IV[1]; + v[10] = blake2b_IV[2]; + v[11] = blake2b_IV[3]; + v[12] = blake2b_IV[4] ^ S->t[0]; + v[13] = blake2b_IV[5] ^ S->t[1]; + v[14] = blake2b_IV[6] ^ S->f[0]; + v[15] = blake2b_IV[7] ^ S->f[1]; + +#define G(r, i, a, b, c, d) \ + do { \ + a = a + b + m[blake2b_sigma[r][2 * i + 0]]; \ + d = rotr64(d ^ a, 32); \ + c = c + d; \ + b = rotr64(b ^ c, 24); \ + a = a + b + m[blake2b_sigma[r][2 * i + 1]]; \ + d = rotr64(d ^ a, 16); \ + c = c + d; \ + b = rotr64(b ^ c, 63); \ + } while ((void)0, 0) + +#define ROUND(r) \ + do { \ + G(r, 0, v[0], v[4], v[8], v[12]); \ + G(r, 1, v[1], v[5], v[9], v[13]); \ + G(r, 2, v[2], v[6], v[10], v[14]); \ + G(r, 3, v[3], v[7], v[11], v[15]); \ + G(r, 4, v[0], v[5], v[10], v[15]); \ + G(r, 5, v[1], v[6], v[11], v[12]); \ + G(r, 6, v[2], v[7], v[8], v[13]); \ + G(r, 7, v[3], v[4], v[9], v[14]); \ + } while ((void)0, 0) + + for (r = 0; r < 12; ++r) { + ROUND(r); + } + + for (i = 0; i < 8; ++i) { + S->h[i] = S->h[i] ^ v[i] ^ v[i + 8]; + } + +#undef G +#undef ROUND +} + +int blake2b_update(blake2b_state *S, const void *in, size_t inlen) { + const uint8_t *pin = (const uint8_t *)in; + + if (inlen == 0) { + return 0; + } + + /* Sanity check */ + if (S == NULL || in == NULL) { + return -1; + } + + /* Is this a reused state? */ + if (S->f[0] != 0) { + return -1; + } + + if (S->buflen + inlen > BLAKE2B_BLOCKBYTES) { + /* Complete current block */ + size_t left = S->buflen; + size_t fill = BLAKE2B_BLOCKBYTES - left; + memcpy(&S->buf[left], pin, fill); + blake2b_increment_counter(S, BLAKE2B_BLOCKBYTES); + blake2b_compress(S, S->buf); + S->buflen = 0; + inlen -= fill; + pin += fill; + /* Avoid buffer copies when possible */ + while (inlen > BLAKE2B_BLOCKBYTES) { + blake2b_increment_counter(S, BLAKE2B_BLOCKBYTES); + blake2b_compress(S, pin); + inlen -= BLAKE2B_BLOCKBYTES; + pin += BLAKE2B_BLOCKBYTES; + } + } + memcpy(&S->buf[S->buflen], pin, inlen); + S->buflen += (unsigned int)inlen; + return 0; +} + +int blake2b_final(blake2b_state *S, void *out, size_t outlen) { + uint8_t buffer[BLAKE2B_OUTBYTES] = {0}; + unsigned int i; + + /* Sanity checks */ + if (S == NULL || out == NULL || outlen < S->outlen) { + return -1; + } + + /* Is this a reused state? */ + if (S->f[0] != 0) { + return -1; + } + + blake2b_increment_counter(S, S->buflen); + blake2b_set_lastblock(S); + memset(&S->buf[S->buflen], 0, BLAKE2B_BLOCKBYTES - S->buflen); /* Padding */ + blake2b_compress(S, S->buf); + + for (i = 0; i < 8; ++i) { /* Output full hash to temp buffer */ + store64(buffer + sizeof(S->h[i]) * i, S->h[i]); + } + + memcpy(out, buffer, S->outlen); + clear_internal_memory(buffer, sizeof(buffer)); + clear_internal_memory(S->buf, sizeof(S->buf)); + clear_internal_memory(S->h, sizeof(S->h)); + return 0; +} + +int blake2b(void *out, size_t outlen, const void *in, size_t inlen, + const void *key, size_t keylen) { + blake2b_state S; + int ret = -1; + + /* Verify parameters */ + if (NULL == in && inlen > 0) { + goto fail; + } + + if (NULL == out || outlen == 0 || outlen > BLAKE2B_OUTBYTES) { + goto fail; + } + + if ((NULL == key && keylen > 0) || keylen > BLAKE2B_KEYBYTES) { + goto fail; + } + + if (keylen > 0) { + if (blake2b_init_key(&S, outlen, key, keylen) < 0) { + goto fail; + } + } else { + if (blake2b_init(&S, outlen) < 0) { + goto fail; + } + } + + if (blake2b_update(&S, in, inlen) < 0) { + goto fail; + } + ret = blake2b_final(&S, out, outlen); + +fail: + clear_internal_memory(&S, sizeof(S)); + return ret; +} + +/* Argon2 Team - Begin Code */ +int blake2b_long(void *pout, size_t outlen, const void *in, size_t inlen) { + uint8_t *out = (uint8_t *)pout; + blake2b_state blake_state; + uint8_t outlen_bytes[sizeof(uint32_t)] = {0}; + int ret = -1; + + if (outlen > UINT32_MAX) { + goto fail; + } + + /* Ensure little-endian byte order! */ + store32(outlen_bytes, (uint32_t)outlen); + +#define TRY(statement) \ + do { \ + ret = statement; \ + if (ret < 0) { \ + goto fail; \ + } \ + } while ((void)0, 0) + + if (outlen <= BLAKE2B_OUTBYTES) { + TRY(blake2b_init(&blake_state, outlen)); + TRY(blake2b_update(&blake_state, outlen_bytes, sizeof(outlen_bytes))); + TRY(blake2b_update(&blake_state, in, inlen)); + TRY(blake2b_final(&blake_state, out, outlen)); + } else { + uint32_t toproduce; + uint8_t out_buffer[BLAKE2B_OUTBYTES]; + uint8_t in_buffer[BLAKE2B_OUTBYTES]; + TRY(blake2b_init(&blake_state, BLAKE2B_OUTBYTES)); + TRY(blake2b_update(&blake_state, outlen_bytes, sizeof(outlen_bytes))); + TRY(blake2b_update(&blake_state, in, inlen)); + TRY(blake2b_final(&blake_state, out_buffer, BLAKE2B_OUTBYTES)); + memcpy(out, out_buffer, BLAKE2B_OUTBYTES / 2); + out += BLAKE2B_OUTBYTES / 2; + toproduce = (uint32_t)outlen - BLAKE2B_OUTBYTES / 2; + + while (toproduce > BLAKE2B_OUTBYTES) { + memcpy(in_buffer, out_buffer, BLAKE2B_OUTBYTES); + TRY(blake2b(out_buffer, BLAKE2B_OUTBYTES, in_buffer, + BLAKE2B_OUTBYTES, NULL, 0)); + memcpy(out, out_buffer, BLAKE2B_OUTBYTES / 2); + out += BLAKE2B_OUTBYTES / 2; + toproduce -= BLAKE2B_OUTBYTES / 2; + } + + memcpy(in_buffer, out_buffer, BLAKE2B_OUTBYTES); + TRY(blake2b(out_buffer, toproduce, in_buffer, BLAKE2B_OUTBYTES, NULL, + 0)); + memcpy(out, out_buffer, toproduce); + } +fail: + clear_internal_memory(&blake_state, sizeof(blake_state)); + return ret; +#undef TRY +} +/* Argon2 Team - End Code */ diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-opt.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-opt.h new file mode 100644 index 0000000..3127f2a --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-opt.h @@ -0,0 +1,471 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef BLAKE_ROUND_MKA_OPT_H +#define BLAKE_ROUND_MKA_OPT_H + +#include "blake2-impl.h" + +#include +#if defined(__SSSE3__) +#include /* for _mm_shuffle_epi8 and _mm_alignr_epi8 */ +#endif + +#if defined(__XOP__) && (defined(__GNUC__) || defined(__clang__)) +#include +#endif + +#if !defined(__AVX512F__) +#if !defined(__AVX2__) +#if !defined(__XOP__) +#if defined(__SSSE3__) +#define r16 \ + (_mm_setr_epi8(2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9)) +#define r24 \ + (_mm_setr_epi8(3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10)) +#define _mm_roti_epi64(x, c) \ + (-(c) == 32) \ + ? _mm_shuffle_epi32((x), _MM_SHUFFLE(2, 3, 0, 1)) \ + : (-(c) == 24) \ + ? _mm_shuffle_epi8((x), r24) \ + : (-(c) == 16) \ + ? _mm_shuffle_epi8((x), r16) \ + : (-(c) == 63) \ + ? _mm_xor_si128(_mm_srli_epi64((x), -(c)), \ + _mm_add_epi64((x), (x))) \ + : _mm_xor_si128(_mm_srli_epi64((x), -(c)), \ + _mm_slli_epi64((x), 64 - (-(c)))) +#else /* defined(__SSE2__) */ +#define _mm_roti_epi64(r, c) \ + _mm_xor_si128(_mm_srli_epi64((r), -(c)), _mm_slli_epi64((r), 64 - (-(c)))) +#endif +#else +#endif + +static BLAKE2_INLINE __m128i fBlaMka(__m128i x, __m128i y) { + const __m128i z = _mm_mul_epu32(x, y); + return _mm_add_epi64(_mm_add_epi64(x, y), _mm_add_epi64(z, z)); +} + +#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + A0 = fBlaMka(A0, B0); \ + A1 = fBlaMka(A1, B1); \ + \ + D0 = _mm_xor_si128(D0, A0); \ + D1 = _mm_xor_si128(D1, A1); \ + \ + D0 = _mm_roti_epi64(D0, -32); \ + D1 = _mm_roti_epi64(D1, -32); \ + \ + C0 = fBlaMka(C0, D0); \ + C1 = fBlaMka(C1, D1); \ + \ + B0 = _mm_xor_si128(B0, C0); \ + B1 = _mm_xor_si128(B1, C1); \ + \ + B0 = _mm_roti_epi64(B0, -24); \ + B1 = _mm_roti_epi64(B1, -24); \ + } while ((void)0, 0) + +#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + A0 = fBlaMka(A0, B0); \ + A1 = fBlaMka(A1, B1); \ + \ + D0 = _mm_xor_si128(D0, A0); \ + D1 = _mm_xor_si128(D1, A1); \ + \ + D0 = _mm_roti_epi64(D0, -16); \ + D1 = _mm_roti_epi64(D1, -16); \ + \ + C0 = fBlaMka(C0, D0); \ + C1 = fBlaMka(C1, D1); \ + \ + B0 = _mm_xor_si128(B0, C0); \ + B1 = _mm_xor_si128(B1, C1); \ + \ + B0 = _mm_roti_epi64(B0, -63); \ + B1 = _mm_roti_epi64(B1, -63); \ + } while ((void)0, 0) + +#if defined(__SSSE3__) +#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + __m128i t0 = _mm_alignr_epi8(B1, B0, 8); \ + __m128i t1 = _mm_alignr_epi8(B0, B1, 8); \ + B0 = t0; \ + B1 = t1; \ + \ + t0 = C0; \ + C0 = C1; \ + C1 = t0; \ + \ + t0 = _mm_alignr_epi8(D1, D0, 8); \ + t1 = _mm_alignr_epi8(D0, D1, 8); \ + D0 = t1; \ + D1 = t0; \ + } while ((void)0, 0) + +#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + __m128i t0 = _mm_alignr_epi8(B0, B1, 8); \ + __m128i t1 = _mm_alignr_epi8(B1, B0, 8); \ + B0 = t0; \ + B1 = t1; \ + \ + t0 = C0; \ + C0 = C1; \ + C1 = t0; \ + \ + t0 = _mm_alignr_epi8(D0, D1, 8); \ + t1 = _mm_alignr_epi8(D1, D0, 8); \ + D0 = t1; \ + D1 = t0; \ + } while ((void)0, 0) +#else /* SSE2 */ +#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + __m128i t0 = D0; \ + __m128i t1 = B0; \ + D0 = C0; \ + C0 = C1; \ + C1 = D0; \ + D0 = _mm_unpackhi_epi64(D1, _mm_unpacklo_epi64(t0, t0)); \ + D1 = _mm_unpackhi_epi64(t0, _mm_unpacklo_epi64(D1, D1)); \ + B0 = _mm_unpackhi_epi64(B0, _mm_unpacklo_epi64(B1, B1)); \ + B1 = _mm_unpackhi_epi64(B1, _mm_unpacklo_epi64(t1, t1)); \ + } while ((void)0, 0) + +#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + __m128i t0, t1; \ + t0 = C0; \ + C0 = C1; \ + C1 = t0; \ + t0 = B0; \ + t1 = D0; \ + B0 = _mm_unpackhi_epi64(B1, _mm_unpacklo_epi64(B0, B0)); \ + B1 = _mm_unpackhi_epi64(t0, _mm_unpacklo_epi64(B1, B1)); \ + D0 = _mm_unpackhi_epi64(D0, _mm_unpacklo_epi64(D1, D1)); \ + D1 = _mm_unpackhi_epi64(D1, _mm_unpacklo_epi64(t1, t1)); \ + } while ((void)0, 0) +#endif + +#define BLAKE2_ROUND(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + G1(A0, B0, C0, D0, A1, B1, C1, D1); \ + G2(A0, B0, C0, D0, A1, B1, C1, D1); \ + \ + DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ + \ + G1(A0, B0, C0, D0, A1, B1, C1, D1); \ + G2(A0, B0, C0, D0, A1, B1, C1, D1); \ + \ + UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ + } while ((void)0, 0) +#else /* __AVX2__ */ + +#include + +#define rotr32(x) _mm256_shuffle_epi32(x, _MM_SHUFFLE(2, 3, 0, 1)) +#define rotr24(x) _mm256_shuffle_epi8(x, _mm256_setr_epi8(3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10, 3, 4, 5, 6, 7, 0, 1, 2, 11, 12, 13, 14, 15, 8, 9, 10)) +#define rotr16(x) _mm256_shuffle_epi8(x, _mm256_setr_epi8(2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9, 2, 3, 4, 5, 6, 7, 0, 1, 10, 11, 12, 13, 14, 15, 8, 9)) +#define rotr63(x) _mm256_xor_si256(_mm256_srli_epi64((x), 63), _mm256_add_epi64((x), (x))) + +#define G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + __m256i ml = _mm256_mul_epu32(A0, B0); \ + ml = _mm256_add_epi64(ml, ml); \ + A0 = _mm256_add_epi64(A0, _mm256_add_epi64(B0, ml)); \ + D0 = _mm256_xor_si256(D0, A0); \ + D0 = rotr32(D0); \ + \ + ml = _mm256_mul_epu32(C0, D0); \ + ml = _mm256_add_epi64(ml, ml); \ + C0 = _mm256_add_epi64(C0, _mm256_add_epi64(D0, ml)); \ + \ + B0 = _mm256_xor_si256(B0, C0); \ + B0 = rotr24(B0); \ + \ + ml = _mm256_mul_epu32(A1, B1); \ + ml = _mm256_add_epi64(ml, ml); \ + A1 = _mm256_add_epi64(A1, _mm256_add_epi64(B1, ml)); \ + D1 = _mm256_xor_si256(D1, A1); \ + D1 = rotr32(D1); \ + \ + ml = _mm256_mul_epu32(C1, D1); \ + ml = _mm256_add_epi64(ml, ml); \ + C1 = _mm256_add_epi64(C1, _mm256_add_epi64(D1, ml)); \ + \ + B1 = _mm256_xor_si256(B1, C1); \ + B1 = rotr24(B1); \ + } while((void)0, 0); + +#define G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + __m256i ml = _mm256_mul_epu32(A0, B0); \ + ml = _mm256_add_epi64(ml, ml); \ + A0 = _mm256_add_epi64(A0, _mm256_add_epi64(B0, ml)); \ + D0 = _mm256_xor_si256(D0, A0); \ + D0 = rotr16(D0); \ + \ + ml = _mm256_mul_epu32(C0, D0); \ + ml = _mm256_add_epi64(ml, ml); \ + C0 = _mm256_add_epi64(C0, _mm256_add_epi64(D0, ml)); \ + B0 = _mm256_xor_si256(B0, C0); \ + B0 = rotr63(B0); \ + \ + ml = _mm256_mul_epu32(A1, B1); \ + ml = _mm256_add_epi64(ml, ml); \ + A1 = _mm256_add_epi64(A1, _mm256_add_epi64(B1, ml)); \ + D1 = _mm256_xor_si256(D1, A1); \ + D1 = rotr16(D1); \ + \ + ml = _mm256_mul_epu32(C1, D1); \ + ml = _mm256_add_epi64(ml, ml); \ + C1 = _mm256_add_epi64(C1, _mm256_add_epi64(D1, ml)); \ + B1 = _mm256_xor_si256(B1, C1); \ + B1 = rotr63(B1); \ + } while((void)0, 0); + +#define DIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(0, 3, 2, 1)); \ + C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ + D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(2, 1, 0, 3)); \ + \ + B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(0, 3, 2, 1)); \ + C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ + D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(2, 1, 0, 3)); \ + } while((void)0, 0); + +#define DIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + __m256i tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \ + __m256i tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \ + B1 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ + B0 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ + \ + tmp1 = C0; \ + C0 = C1; \ + C1 = tmp1; \ + \ + tmp1 = _mm256_blend_epi32(D0, D1, 0xCC); \ + tmp2 = _mm256_blend_epi32(D0, D1, 0x33); \ + D0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ + D1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ + } while(0); + +#define UNDIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(2, 1, 0, 3)); \ + C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ + D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(0, 3, 2, 1)); \ + \ + B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(2, 1, 0, 3)); \ + C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ + D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(0, 3, 2, 1)); \ + } while((void)0, 0); + +#define UNDIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + __m256i tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \ + __m256i tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \ + B0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ + B1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ + \ + tmp1 = C0; \ + C0 = C1; \ + C1 = tmp1; \ + \ + tmp1 = _mm256_blend_epi32(D0, D1, 0x33); \ + tmp2 = _mm256_blend_epi32(D0, D1, 0xCC); \ + D0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \ + D1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \ + } while((void)0, 0); + +#define BLAKE2_ROUND_1(A0, A1, B0, B1, C0, C1, D0, D1) \ + do{ \ + G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + \ + DIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ + \ + G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + \ + UNDIAGONALIZE_1(A0, B0, C0, D0, A1, B1, C1, D1) \ + } while((void)0, 0); + +#define BLAKE2_ROUND_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do{ \ + G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + \ + DIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + \ + G1_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + G2_AVX2(A0, A1, B0, B1, C0, C1, D0, D1) \ + \ + UNDIAGONALIZE_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + } while((void)0, 0); + +#endif /* __AVX2__ */ + +#else /* __AVX512F__ */ + +#include + +#define ror64(x, n) _mm512_ror_epi64((x), (n)) + +static __m512i muladd(__m512i x, __m512i y) +{ + __m512i z = _mm512_mul_epu32(x, y); + return _mm512_add_epi64(_mm512_add_epi64(x, y), _mm512_add_epi64(z, z)); +} + +#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + A0 = muladd(A0, B0); \ + A1 = muladd(A1, B1); \ +\ + D0 = _mm512_xor_si512(D0, A0); \ + D1 = _mm512_xor_si512(D1, A1); \ +\ + D0 = ror64(D0, 32); \ + D1 = ror64(D1, 32); \ +\ + C0 = muladd(C0, D0); \ + C1 = muladd(C1, D1); \ +\ + B0 = _mm512_xor_si512(B0, C0); \ + B1 = _mm512_xor_si512(B1, C1); \ +\ + B0 = ror64(B0, 24); \ + B1 = ror64(B1, 24); \ + } while ((void)0, 0) + +#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + A0 = muladd(A0, B0); \ + A1 = muladd(A1, B1); \ +\ + D0 = _mm512_xor_si512(D0, A0); \ + D1 = _mm512_xor_si512(D1, A1); \ +\ + D0 = ror64(D0, 16); \ + D1 = ror64(D1, 16); \ +\ + C0 = muladd(C0, D0); \ + C1 = muladd(C1, D1); \ +\ + B0 = _mm512_xor_si512(B0, C0); \ + B1 = _mm512_xor_si512(B1, C1); \ +\ + B0 = ror64(B0, 63); \ + B1 = ror64(B1, 63); \ + } while ((void)0, 0) + +#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + B0 = _mm512_permutex_epi64(B0, _MM_SHUFFLE(0, 3, 2, 1)); \ + B1 = _mm512_permutex_epi64(B1, _MM_SHUFFLE(0, 3, 2, 1)); \ +\ + C0 = _mm512_permutex_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ + C1 = _mm512_permutex_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ +\ + D0 = _mm512_permutex_epi64(D0, _MM_SHUFFLE(2, 1, 0, 3)); \ + D1 = _mm512_permutex_epi64(D1, _MM_SHUFFLE(2, 1, 0, 3)); \ + } while ((void)0, 0) + +#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + B0 = _mm512_permutex_epi64(B0, _MM_SHUFFLE(2, 1, 0, 3)); \ + B1 = _mm512_permutex_epi64(B1, _MM_SHUFFLE(2, 1, 0, 3)); \ +\ + C0 = _mm512_permutex_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \ + C1 = _mm512_permutex_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \ +\ + D0 = _mm512_permutex_epi64(D0, _MM_SHUFFLE(0, 3, 2, 1)); \ + D1 = _mm512_permutex_epi64(D1, _MM_SHUFFLE(0, 3, 2, 1)); \ + } while ((void)0, 0) + +#define BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1) \ + do { \ + G1(A0, B0, C0, D0, A1, B1, C1, D1); \ + G2(A0, B0, C0, D0, A1, B1, C1, D1); \ +\ + DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ +\ + G1(A0, B0, C0, D0, A1, B1, C1, D1); \ + G2(A0, B0, C0, D0, A1, B1, C1, D1); \ +\ + UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \ + } while ((void)0, 0) + +#define SWAP_HALVES(A0, A1) \ + do { \ + __m512i t0, t1; \ + t0 = _mm512_shuffle_i64x2(A0, A1, _MM_SHUFFLE(1, 0, 1, 0)); \ + t1 = _mm512_shuffle_i64x2(A0, A1, _MM_SHUFFLE(3, 2, 3, 2)); \ + A0 = t0; \ + A1 = t1; \ + } while((void)0, 0) + +#define SWAP_QUARTERS(A0, A1) \ + do { \ + SWAP_HALVES(A0, A1); \ + A0 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A0); \ + A1 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A1); \ + } while((void)0, 0) + +#define UNSWAP_QUARTERS(A0, A1) \ + do { \ + A0 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A0); \ + A1 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A1); \ + SWAP_HALVES(A0, A1); \ + } while((void)0, 0) + +#define BLAKE2_ROUND_1(A0, C0, B0, D0, A1, C1, B1, D1) \ + do { \ + SWAP_HALVES(A0, B0); \ + SWAP_HALVES(C0, D0); \ + SWAP_HALVES(A1, B1); \ + SWAP_HALVES(C1, D1); \ + BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1); \ + SWAP_HALVES(A0, B0); \ + SWAP_HALVES(C0, D0); \ + SWAP_HALVES(A1, B1); \ + SWAP_HALVES(C1, D1); \ + } while ((void)0, 0) + +#define BLAKE2_ROUND_2(A0, A1, B0, B1, C0, C1, D0, D1) \ + do { \ + SWAP_QUARTERS(A0, A1); \ + SWAP_QUARTERS(B0, B1); \ + SWAP_QUARTERS(C0, C1); \ + SWAP_QUARTERS(D0, D1); \ + BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1); \ + UNSWAP_QUARTERS(A0, A1); \ + UNSWAP_QUARTERS(B0, B1); \ + UNSWAP_QUARTERS(C0, C1); \ + UNSWAP_QUARTERS(D0, D1); \ + } while ((void)0, 0) + +#endif /* __AVX512F__ */ +#endif /* BLAKE_ROUND_MKA_OPT_H */ diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-ref.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-ref.h new file mode 100644 index 0000000..16cfc1c --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/blake2/blamka-round-ref.h @@ -0,0 +1,56 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef BLAKE_ROUND_MKA_H +#define BLAKE_ROUND_MKA_H + +#include "blake2.h" +#include "blake2-impl.h" + +/* designed by the Lyra PHC team */ +static BLAKE2_INLINE uint64_t fBlaMka(uint64_t x, uint64_t y) { + const uint64_t m = UINT64_C(0xFFFFFFFF); + const uint64_t xy = (x & m) * (y & m); + return x + y + 2 * xy; +} + +#define G(a, b, c, d) \ + do { \ + a = fBlaMka(a, b); \ + d = rotr64(d ^ a, 32); \ + c = fBlaMka(c, d); \ + b = rotr64(b ^ c, 24); \ + a = fBlaMka(a, b); \ + d = rotr64(d ^ a, 16); \ + c = fBlaMka(c, d); \ + b = rotr64(b ^ c, 63); \ + } while ((void)0, 0) + +#define BLAKE2_ROUND_NOMSG(v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, \ + v12, v13, v14, v15) \ + do { \ + G(v0, v4, v8, v12); \ + G(v1, v5, v9, v13); \ + G(v2, v6, v10, v14); \ + G(v3, v7, v11, v15); \ + G(v0, v5, v10, v15); \ + G(v1, v6, v11, v12); \ + G(v2, v7, v8, v13); \ + G(v3, v4, v9, v14); \ + } while ((void)0, 0) + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/core.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/core.c new file mode 100644 index 0000000..e697882 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/core.c @@ -0,0 +1,648 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +/*For memory wiping*/ +#ifdef _WIN32 +#include +#include /* For SecureZeroMemory */ +#endif +#if defined __STDC_LIB_EXT1__ +#define __STDC_WANT_LIB_EXT1__ 1 +#endif +#define VC_GE_2005(version) (version >= 1400) + +/* for explicit_bzero() on glibc */ +#define _DEFAULT_SOURCE + +#include +#include +#include + +#include "core.h" +#include "thread.h" +#include "blake2/blake2.h" +#include "blake2/blake2-impl.h" + +#ifdef GENKAT +#include "genkat.h" +#endif + +#if defined(__clang__) +#if __has_attribute(optnone) +#define NOT_OPTIMIZED __attribute__((optnone)) +#endif +#elif defined(__GNUC__) +#define GCC_VERSION \ + (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) +#if GCC_VERSION >= 40400 +#define NOT_OPTIMIZED __attribute__((optimize("O0"))) +#endif +#endif +#ifndef NOT_OPTIMIZED +#define NOT_OPTIMIZED +#endif + +/***************Instance and Position constructors**********/ +void init_block_value(block *b, uint8_t in) { memset(b->v, in, sizeof(b->v)); } + +void copy_block(block *dst, const block *src) { + memcpy(dst->v, src->v, sizeof(uint64_t) * ARGON2_QWORDS_IN_BLOCK); +} + +void xor_block(block *dst, const block *src) { + int i; + for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { + dst->v[i] ^= src->v[i]; + } +} + +static void load_block(block *dst, const void *input) { + unsigned i; + for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { + dst->v[i] = load64((const uint8_t *)input + i * sizeof(dst->v[i])); + } +} + +static void store_block(void *output, const block *src) { + unsigned i; + for (i = 0; i < ARGON2_QWORDS_IN_BLOCK; ++i) { + store64((uint8_t *)output + i * sizeof(src->v[i]), src->v[i]); + } +} + +/***************Memory functions*****************/ + +int allocate_memory(const argon2_context *context, uint8_t **memory, + size_t num, size_t size) { + size_t memory_size = num*size; + if (memory == NULL) { + return ARGON2_MEMORY_ALLOCATION_ERROR; + } + + /* 1. Check for multiplication overflow */ + if (size != 0 && memory_size / size != num) { + return ARGON2_MEMORY_ALLOCATION_ERROR; + } + + /* 2. Try to allocate with appropriate allocator */ + if (context->allocate_cbk) { + (context->allocate_cbk)(memory, memory_size); + } else { + *memory = malloc(memory_size); + } + + if (*memory == NULL) { + return ARGON2_MEMORY_ALLOCATION_ERROR; + } + + return ARGON2_OK; +} + +void free_memory(const argon2_context *context, uint8_t *memory, + size_t num, size_t size) { + size_t memory_size = num*size; + clear_internal_memory(memory, memory_size); + if (context->free_cbk) { + (context->free_cbk)(memory, memory_size); + } else { + free(memory); + } +} + +#if defined(__OpenBSD__) +#define HAVE_EXPLICIT_BZERO 1 +#elif defined(__GLIBC__) && defined(__GLIBC_PREREQ) +#if __GLIBC_PREREQ(2,25) +#define HAVE_EXPLICIT_BZERO 1 +#endif +#endif + +void NOT_OPTIMIZED secure_wipe_memory(void *v, size_t n) { +#if defined(_MSC_VER) && VC_GE_2005(_MSC_VER) || defined(__MINGW32__) + SecureZeroMemory(v, n); +#elif defined memset_s + memset_s(v, n, 0, n); +#elif defined(HAVE_EXPLICIT_BZERO) + explicit_bzero(v, n); +#else + static void *(*const volatile memset_sec)(void *, int, size_t) = &memset; + memset_sec(v, 0, n); +#endif +} + +/* Memory clear flag defaults to true. */ +int FLAG_clear_internal_memory = 1; +void clear_internal_memory(void *v, size_t n) { + if (FLAG_clear_internal_memory && v) { + secure_wipe_memory(v, n); + } +} + +void finalize(const argon2_context *context, argon2_instance_t *instance) { + if (context != NULL && instance != NULL) { + block blockhash; + uint32_t l; + + copy_block(&blockhash, instance->memory + instance->lane_length - 1); + + /* XOR the last blocks */ + for (l = 1; l < instance->lanes; ++l) { + uint32_t last_block_in_lane = + l * instance->lane_length + (instance->lane_length - 1); + xor_block(&blockhash, instance->memory + last_block_in_lane); + } + + /* Hash the result */ + { + uint8_t blockhash_bytes[ARGON2_BLOCK_SIZE]; + store_block(blockhash_bytes, &blockhash); + blake2b_long(context->out, context->outlen, blockhash_bytes, + ARGON2_BLOCK_SIZE); + /* clear blockhash and blockhash_bytes */ + clear_internal_memory(blockhash.v, ARGON2_BLOCK_SIZE); + clear_internal_memory(blockhash_bytes, ARGON2_BLOCK_SIZE); + } + +#ifdef GENKAT + print_tag(context->out, context->outlen); +#endif + + free_memory(context, (uint8_t *)instance->memory, + instance->memory_blocks, sizeof(block)); + } +} + +uint32_t index_alpha(const argon2_instance_t *instance, + const argon2_position_t *position, uint32_t pseudo_rand, + int same_lane) { + /* + * Pass 0: + * This lane : all already finished segments plus already constructed + * blocks in this segment + * Other lanes : all already finished segments + * Pass 1+: + * This lane : (SYNC_POINTS - 1) last segments plus already constructed + * blocks in this segment + * Other lanes : (SYNC_POINTS - 1) last segments + */ + uint32_t reference_area_size; + uint64_t relative_position; + uint32_t start_position, absolute_position; + + if (0 == position->pass) { + /* First pass */ + if (0 == position->slice) { + /* First slice */ + reference_area_size = + position->index - 1; /* all but the previous */ + } else { + if (same_lane) { + /* The same lane => add current segment */ + reference_area_size = + position->slice * instance->segment_length + + position->index - 1; + } else { + reference_area_size = + position->slice * instance->segment_length + + ((position->index == 0) ? (-1) : 0); + } + } + } else { + /* Second pass */ + if (same_lane) { + reference_area_size = instance->lane_length - + instance->segment_length + position->index - + 1; + } else { + reference_area_size = instance->lane_length - + instance->segment_length + + ((position->index == 0) ? (-1) : 0); + } + } + + /* 1.2.4. Mapping pseudo_rand to 0.. and produce + * relative position */ + relative_position = pseudo_rand; + relative_position = relative_position * relative_position >> 32; + relative_position = reference_area_size - 1 - + (reference_area_size * relative_position >> 32); + + /* 1.2.5 Computing starting position */ + start_position = 0; + + if (0 != position->pass) { + start_position = (position->slice == ARGON2_SYNC_POINTS - 1) + ? 0 + : (position->slice + 1) * instance->segment_length; + } + + /* 1.2.6. Computing absolute position */ + absolute_position = (start_position + relative_position) % + instance->lane_length; /* absolute position */ + return absolute_position; +} + +/* Single-threaded version for p=1 case */ +static int fill_memory_blocks_st(argon2_instance_t *instance) { + uint32_t r, s, l; + + for (r = 0; r < instance->passes; ++r) { + for (s = 0; s < ARGON2_SYNC_POINTS; ++s) { + for (l = 0; l < instance->lanes; ++l) { + argon2_position_t position = {r, l, (uint8_t)s, 0}; + fill_segment(instance, position); + } + } +#ifdef GENKAT + internal_kat(instance, r); /* Print all memory blocks */ +#endif + } + return ARGON2_OK; +} + +#if !defined(ARGON2_NO_THREADS) + +#ifdef _WIN32 +static unsigned __stdcall fill_segment_thr(void *thread_data) +#else +static void *fill_segment_thr(void *thread_data) +#endif +{ + argon2_thread_data *my_data = thread_data; + fill_segment(my_data->instance_ptr, my_data->pos); + argon2_thread_exit(); + return 0; +} + +/* Multi-threaded version for p > 1 case */ +static int fill_memory_blocks_mt(argon2_instance_t *instance) { + uint32_t r, s; + argon2_thread_handle_t *thread = NULL; + argon2_thread_data *thr_data = NULL; + int rc = ARGON2_OK; + + /* 1. Allocating space for threads */ + thread = calloc(instance->lanes, sizeof(argon2_thread_handle_t)); + if (thread == NULL) { + rc = ARGON2_MEMORY_ALLOCATION_ERROR; + goto fail; + } + + thr_data = calloc(instance->lanes, sizeof(argon2_thread_data)); + if (thr_data == NULL) { + rc = ARGON2_MEMORY_ALLOCATION_ERROR; + goto fail; + } + + for (r = 0; r < instance->passes; ++r) { + for (s = 0; s < ARGON2_SYNC_POINTS; ++s) { + uint32_t l, ll; + + /* 2. Calling threads */ + for (l = 0; l < instance->lanes; ++l) { + argon2_position_t position; + + /* 2.1 Join a thread if limit is exceeded */ + if (l >= instance->threads) { + if (argon2_thread_join(thread[l - instance->threads])) { + rc = ARGON2_THREAD_FAIL; + goto fail; + } + } + + /* 2.2 Create thread */ + position.pass = r; + position.lane = l; + position.slice = (uint8_t)s; + position.index = 0; + thr_data[l].instance_ptr = + instance; /* preparing the thread input */ + memcpy(&(thr_data[l].pos), &position, + sizeof(argon2_position_t)); + if (argon2_thread_create(&thread[l], &fill_segment_thr, + (void *)&thr_data[l])) { + /* Wait for already running threads */ + for (ll = 0; ll < l; ++ll) + argon2_thread_join(thread[ll]); + rc = ARGON2_THREAD_FAIL; + goto fail; + } + + /* fill_segment(instance, position); */ + /*Non-thread equivalent of the lines above */ + } + + /* 3. Joining remaining threads */ + for (l = instance->lanes - instance->threads; l < instance->lanes; + ++l) { + if (argon2_thread_join(thread[l])) { + rc = ARGON2_THREAD_FAIL; + goto fail; + } + } + } + +#ifdef GENKAT + internal_kat(instance, r); /* Print all memory blocks */ +#endif + } + +fail: + if (thread != NULL) { + free(thread); + } + if (thr_data != NULL) { + free(thr_data); + } + return rc; +} + +#endif /* ARGON2_NO_THREADS */ + +int fill_memory_blocks(argon2_instance_t *instance) { + if (instance == NULL || instance->lanes == 0) { + return ARGON2_INCORRECT_PARAMETER; + } +#if defined(ARGON2_NO_THREADS) + return fill_memory_blocks_st(instance); +#else + return instance->threads == 1 ? + fill_memory_blocks_st(instance) : fill_memory_blocks_mt(instance); +#endif +} + +int validate_inputs(const argon2_context *context) { + if (NULL == context) { + return ARGON2_INCORRECT_PARAMETER; + } + + if (NULL == context->out) { + return ARGON2_OUTPUT_PTR_NULL; + } + + /* Validate output length */ + if (ARGON2_MIN_OUTLEN > context->outlen) { + return ARGON2_OUTPUT_TOO_SHORT; + } + + if (ARGON2_MAX_OUTLEN < context->outlen) { + return ARGON2_OUTPUT_TOO_LONG; + } + + /* Validate password (required param) */ + if (NULL == context->pwd) { + if (0 != context->pwdlen) { + return ARGON2_PWD_PTR_MISMATCH; + } + } + + if (ARGON2_MIN_PWD_LENGTH > context->pwdlen) { + return ARGON2_PWD_TOO_SHORT; + } + + if (ARGON2_MAX_PWD_LENGTH < context->pwdlen) { + return ARGON2_PWD_TOO_LONG; + } + + /* Validate salt (required param) */ + if (NULL == context->salt) { + if (0 != context->saltlen) { + return ARGON2_SALT_PTR_MISMATCH; + } + } + + if (ARGON2_MIN_SALT_LENGTH > context->saltlen) { + return ARGON2_SALT_TOO_SHORT; + } + + if (ARGON2_MAX_SALT_LENGTH < context->saltlen) { + return ARGON2_SALT_TOO_LONG; + } + + /* Validate secret (optional param) */ + if (NULL == context->secret) { + if (0 != context->secretlen) { + return ARGON2_SECRET_PTR_MISMATCH; + } + } else { + if (ARGON2_MIN_SECRET > context->secretlen) { + return ARGON2_SECRET_TOO_SHORT; + } + if (ARGON2_MAX_SECRET < context->secretlen) { + return ARGON2_SECRET_TOO_LONG; + } + } + + /* Validate associated data (optional param) */ + if (NULL == context->ad) { + if (0 != context->adlen) { + return ARGON2_AD_PTR_MISMATCH; + } + } else { + if (ARGON2_MIN_AD_LENGTH > context->adlen) { + return ARGON2_AD_TOO_SHORT; + } + if (ARGON2_MAX_AD_LENGTH < context->adlen) { + return ARGON2_AD_TOO_LONG; + } + } + + /* Validate memory cost */ + if (ARGON2_MIN_MEMORY > context->m_cost) { + return ARGON2_MEMORY_TOO_LITTLE; + } + + if (ARGON2_MAX_MEMORY < context->m_cost) { + return ARGON2_MEMORY_TOO_MUCH; + } + + if (context->m_cost < 8 * context->lanes) { + return ARGON2_MEMORY_TOO_LITTLE; + } + + /* Validate time cost */ + if (ARGON2_MIN_TIME > context->t_cost) { + return ARGON2_TIME_TOO_SMALL; + } + + if (ARGON2_MAX_TIME < context->t_cost) { + return ARGON2_TIME_TOO_LARGE; + } + + /* Validate lanes */ + if (ARGON2_MIN_LANES > context->lanes) { + return ARGON2_LANES_TOO_FEW; + } + + if (ARGON2_MAX_LANES < context->lanes) { + return ARGON2_LANES_TOO_MANY; + } + + /* Validate threads */ + if (ARGON2_MIN_THREADS > context->threads) { + return ARGON2_THREADS_TOO_FEW; + } + + if (ARGON2_MAX_THREADS < context->threads) { + return ARGON2_THREADS_TOO_MANY; + } + + if (NULL != context->allocate_cbk && NULL == context->free_cbk) { + return ARGON2_FREE_MEMORY_CBK_NULL; + } + + if (NULL == context->allocate_cbk && NULL != context->free_cbk) { + return ARGON2_ALLOCATE_MEMORY_CBK_NULL; + } + + return ARGON2_OK; +} + +void fill_first_blocks(uint8_t *blockhash, const argon2_instance_t *instance) { + uint32_t l; + /* Make the first and second block in each lane as G(H0||0||i) or + G(H0||1||i) */ + uint8_t blockhash_bytes[ARGON2_BLOCK_SIZE]; + for (l = 0; l < instance->lanes; ++l) { + + store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, 0); + store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH + 4, l); + blake2b_long(blockhash_bytes, ARGON2_BLOCK_SIZE, blockhash, + ARGON2_PREHASH_SEED_LENGTH); + load_block(&instance->memory[l * instance->lane_length + 0], + blockhash_bytes); + + store32(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, 1); + blake2b_long(blockhash_bytes, ARGON2_BLOCK_SIZE, blockhash, + ARGON2_PREHASH_SEED_LENGTH); + load_block(&instance->memory[l * instance->lane_length + 1], + blockhash_bytes); + } + clear_internal_memory(blockhash_bytes, ARGON2_BLOCK_SIZE); +} + +void initial_hash(uint8_t *blockhash, argon2_context *context, + argon2_type type) { + blake2b_state BlakeHash; + uint8_t value[sizeof(uint32_t)]; + + if (NULL == context || NULL == blockhash) { + return; + } + + blake2b_init(&BlakeHash, ARGON2_PREHASH_DIGEST_LENGTH); + + store32(&value, context->lanes); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, context->outlen); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, context->m_cost); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, context->t_cost); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, context->version); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, (uint32_t)type); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + store32(&value, context->pwdlen); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + if (context->pwd != NULL) { + blake2b_update(&BlakeHash, (const uint8_t *)context->pwd, + context->pwdlen); + + if (context->flags & ARGON2_FLAG_CLEAR_PASSWORD) { + secure_wipe_memory(context->pwd, context->pwdlen); + context->pwdlen = 0; + } + } + + store32(&value, context->saltlen); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + if (context->salt != NULL) { + blake2b_update(&BlakeHash, (const uint8_t *)context->salt, + context->saltlen); + } + + store32(&value, context->secretlen); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + if (context->secret != NULL) { + blake2b_update(&BlakeHash, (const uint8_t *)context->secret, + context->secretlen); + + if (context->flags & ARGON2_FLAG_CLEAR_SECRET) { + secure_wipe_memory(context->secret, context->secretlen); + context->secretlen = 0; + } + } + + store32(&value, context->adlen); + blake2b_update(&BlakeHash, (const uint8_t *)&value, sizeof(value)); + + if (context->ad != NULL) { + blake2b_update(&BlakeHash, (const uint8_t *)context->ad, + context->adlen); + } + + blake2b_final(&BlakeHash, blockhash, ARGON2_PREHASH_DIGEST_LENGTH); +} + +int initialize(argon2_instance_t *instance, argon2_context *context) { + uint8_t blockhash[ARGON2_PREHASH_SEED_LENGTH]; + int result = ARGON2_OK; + + if (instance == NULL || context == NULL) + return ARGON2_INCORRECT_PARAMETER; + instance->context_ptr = context; + + /* 1. Memory allocation */ + result = allocate_memory(context, (uint8_t **)&(instance->memory), + instance->memory_blocks, sizeof(block)); + if (result != ARGON2_OK) { + return result; + } + + /* 2. Initial hashing */ + /* H_0 + 8 extra bytes to produce the first blocks */ + /* uint8_t blockhash[ARGON2_PREHASH_SEED_LENGTH]; */ + /* Hashing all inputs */ + initial_hash(blockhash, context, instance->type); + /* Zeroing 8 extra bytes */ + clear_internal_memory(blockhash + ARGON2_PREHASH_DIGEST_LENGTH, + ARGON2_PREHASH_SEED_LENGTH - + ARGON2_PREHASH_DIGEST_LENGTH); + +#ifdef GENKAT + initial_kat(blockhash, context, instance->type); +#endif + + /* 3. Creating first blocks, we always have at least two blocks in a slice + */ + fill_first_blocks(blockhash, instance); + /* Clearing the hash */ + clear_internal_memory(blockhash, ARGON2_PREHASH_SEED_LENGTH); + + return ARGON2_OK; +} diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/core.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/core.h new file mode 100644 index 0000000..59e2564 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/core.h @@ -0,0 +1,228 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef ARGON2_CORE_H +#define ARGON2_CORE_H + +#include "argon2.h" + +#define CONST_CAST(x) (x)(uintptr_t) + +/**********************Argon2 internal constants*******************************/ + +enum argon2_core_constants { + /* Memory block size in bytes */ + ARGON2_BLOCK_SIZE = 1024, + ARGON2_QWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 8, + ARGON2_OWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 16, + ARGON2_HWORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 32, + ARGON2_512BIT_WORDS_IN_BLOCK = ARGON2_BLOCK_SIZE / 64, + + /* Number of pseudo-random values generated by one call to Blake in Argon2i + to + generate reference block positions */ + ARGON2_ADDRESSES_IN_BLOCK = 128, + + /* Pre-hashing digest length and its extension*/ + ARGON2_PREHASH_DIGEST_LENGTH = 64, + ARGON2_PREHASH_SEED_LENGTH = 72 +}; + +/*************************Argon2 internal data types***********************/ + +/* + * Structure for the (1KB) memory block implemented as 128 64-bit words. + * Memory blocks can be copied, XORed. Internal words can be accessed by [] (no + * bounds checking). + */ +typedef struct block_ { uint64_t v[ARGON2_QWORDS_IN_BLOCK]; } block; + +/*****************Functions that work with the block******************/ + +/* Initialize each byte of the block with @in */ +void init_block_value(block *b, uint8_t in); + +/* Copy block @src to block @dst */ +void copy_block(block *dst, const block *src); + +/* XOR @src onto @dst bytewise */ +void xor_block(block *dst, const block *src); + +/* + * Argon2 instance: memory pointer, number of passes, amount of memory, type, + * and derived values. + * Used to evaluate the number and location of blocks to construct in each + * thread + */ +typedef struct Argon2_instance_t { + block *memory; /* Memory pointer */ + uint32_t version; + uint32_t passes; /* Number of passes */ + uint32_t memory_blocks; /* Number of blocks in memory */ + uint32_t segment_length; + uint32_t lane_length; + uint32_t lanes; + uint32_t threads; + argon2_type type; + int print_internals; /* whether to print the memory blocks */ + argon2_context *context_ptr; /* points back to original context */ +} argon2_instance_t; + +/* + * Argon2 position: where we construct the block right now. Used to distribute + * work between threads. + */ +typedef struct Argon2_position_t { + uint32_t pass; + uint32_t lane; + uint8_t slice; + uint32_t index; +} argon2_position_t; + +/*Struct that holds the inputs for thread handling FillSegment*/ +typedef struct Argon2_thread_data { + argon2_instance_t *instance_ptr; + argon2_position_t pos; +} argon2_thread_data; + +/*************************Argon2 core functions********************************/ + +/* Allocates memory to the given pointer, uses the appropriate allocator as + * specified in the context. Total allocated memory is num*size. + * @param context argon2_context which specifies the allocator + * @param memory pointer to the pointer to the memory + * @param size the size in bytes for each element to be allocated + * @param num the number of elements to be allocated + * @return ARGON2_OK if @memory is a valid pointer and memory is allocated + */ +int allocate_memory(const argon2_context *context, uint8_t **memory, + size_t num, size_t size); + +/* + * Frees memory at the given pointer, uses the appropriate deallocator as + * specified in the context. Also cleans the memory using clear_internal_memory. + * @param context argon2_context which specifies the deallocator + * @param memory pointer to buffer to be freed + * @param size the size in bytes for each element to be deallocated + * @param num the number of elements to be deallocated + */ +void free_memory(const argon2_context *context, uint8_t *memory, + size_t num, size_t size); + +/* Function that securely cleans the memory. This ignores any flags set + * regarding clearing memory. Usually one just calls clear_internal_memory. + * @param mem Pointer to the memory + * @param s Memory size in bytes + */ +void secure_wipe_memory(void *v, size_t n); + +/* Function that securely clears the memory if FLAG_clear_internal_memory is + * set. If the flag isn't set, this function does nothing. + * @param mem Pointer to the memory + * @param s Memory size in bytes + */ +void clear_internal_memory(void *v, size_t n); + +/* + * Computes absolute position of reference block in the lane following a skewed + * distribution and using a pseudo-random value as input + * @param instance Pointer to the current instance + * @param position Pointer to the current position + * @param pseudo_rand 32-bit pseudo-random value used to determine the position + * @param same_lane Indicates if the block will be taken from the current lane. + * If so we can reference the current segment + * @pre All pointers must be valid + */ +uint32_t index_alpha(const argon2_instance_t *instance, + const argon2_position_t *position, uint32_t pseudo_rand, + int same_lane); + +/* + * Function that validates all inputs against predefined restrictions and return + * an error code + * @param context Pointer to current Argon2 context + * @return ARGON2_OK if everything is all right, otherwise one of error codes + * (all defined in + */ +int validate_inputs(const argon2_context *context); + +/* + * Hashes all the inputs into @a blockhash[PREHASH_DIGEST_LENGTH], clears + * password and secret if needed + * @param context Pointer to the Argon2 internal structure containing memory + * pointer, and parameters for time and space requirements. + * @param blockhash Buffer for pre-hashing digest + * @param type Argon2 type + * @pre @a blockhash must have at least @a PREHASH_DIGEST_LENGTH bytes + * allocated + */ +void initial_hash(uint8_t *blockhash, argon2_context *context, + argon2_type type); + +/* + * Function creates first 2 blocks per lane + * @param instance Pointer to the current instance + * @param blockhash Pointer to the pre-hashing digest + * @pre blockhash must point to @a PREHASH_SEED_LENGTH allocated values + */ +void fill_first_blocks(uint8_t *blockhash, const argon2_instance_t *instance); + +/* + * Function allocates memory, hashes the inputs with Blake, and creates first + * two blocks. Returns the pointer to the main memory with 2 blocks per lane + * initialized + * @param context Pointer to the Argon2 internal structure containing memory + * pointer, and parameters for time and space requirements. + * @param instance Current Argon2 instance + * @return Zero if successful, -1 if memory failed to allocate. @context->state + * will be modified if successful. + */ +int initialize(argon2_instance_t *instance, argon2_context *context); + +/* + * XORing the last block of each lane, hashing it, making the tag. Deallocates + * the memory. + * @param context Pointer to current Argon2 context (use only the out parameters + * from it) + * @param instance Pointer to current instance of Argon2 + * @pre instance->state must point to necessary amount of memory + * @pre context->out must point to outlen bytes of memory + * @pre if context->free_cbk is not NULL, it should point to a function that + * deallocates memory + */ +void finalize(const argon2_context *context, argon2_instance_t *instance); + +/* + * Function that fills the segment using previous segments also from other + * threads + * @param context current context + * @param instance Pointer to the current instance + * @param position Current position + * @pre all block pointers must be valid + */ +void fill_segment(const argon2_instance_t *instance, + argon2_position_t position); + +/* + * Function that fills the entire memory t_cost times based on the first two + * blocks in each lane + * @param instance Pointer to the current instance + * @return ARGON2_OK if successful, @context->state + */ +int fill_memory_blocks(argon2_instance_t *instance); + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.c new file mode 100644 index 0000000..771a440 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.c @@ -0,0 +1,463 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#include +#include +#include +#include +#include "encoding.h" +#include "core.h" + +/* + * Example code for a decoder and encoder of "hash strings", with Argon2 + * parameters. + * + * This code comprises three sections: + * + * -- The first section contains generic Base64 encoding and decoding + * functions. It is conceptually applicable to any hash function + * implementation that uses Base64 to encode and decode parameters, + * salts and outputs. It could be made into a library, provided that + * the relevant functions are made public (non-static) and be given + * reasonable names to avoid collisions with other functions. + * + * -- The second section is specific to Argon2. It encodes and decodes + * the parameters, salts and outputs. It does not compute the hash + * itself. + * + * The code was originally written by Thomas Pornin , + * to whom comments and remarks may be sent. It is released under what + * should amount to Public Domain or its closest equivalent; the + * following mantra is supposed to incarnate that fact with all the + * proper legal rituals: + * + * --------------------------------------------------------------------- + * This file is provided under the terms of Creative Commons CC0 1.0 + * Public Domain Dedication. To the extent possible under law, the + * author (Thomas Pornin) has waived all copyright and related or + * neighboring rights to this file. This work is published from: Canada. + * --------------------------------------------------------------------- + * + * Copyright (c) 2015 Thomas Pornin + */ + +/* ==================================================================== */ +/* + * Common code; could be shared between different hash functions. + * + * Note: the Base64 functions below assume that uppercase letters (resp. + * lowercase letters) have consecutive numerical codes, that fit on 8 + * bits. All modern systems use ASCII-compatible charsets, where these + * properties are true. If you are stuck with a dinosaur of a system + * that still defaults to EBCDIC then you already have much bigger + * interoperability issues to deal with. + */ + +/* + * Some macros for constant-time comparisons. These work over values in + * the 0..255 range. Returned value is 0x00 on "false", 0xFF on "true". + */ +#define EQ(x, y) ((((0U - ((unsigned)(x) ^ (unsigned)(y))) >> 8) & 0xFF) ^ 0xFF) +#define GT(x, y) ((((unsigned)(y) - (unsigned)(x)) >> 8) & 0xFF) +#define GE(x, y) (GT(y, x) ^ 0xFF) +#define LT(x, y) GT(y, x) +#define LE(x, y) GE(y, x) + +/* + * Convert value x (0..63) to corresponding Base64 character. + */ +static int b64_byte_to_char(unsigned x) { + return (LT(x, 26) & (x + 'A')) | + (GE(x, 26) & LT(x, 52) & (x + ('a' - 26))) | + (GE(x, 52) & LT(x, 62) & (x + ('0' - 52))) | (EQ(x, 62) & '+') | + (EQ(x, 63) & '/'); +} + +/* + * Convert character c to the corresponding 6-bit value. If character c + * is not a Base64 character, then 0xFF (255) is returned. + */ +static unsigned b64_char_to_byte(int c) { + unsigned x; + + x = (GE(c, 'A') & LE(c, 'Z') & (c - 'A')) | + (GE(c, 'a') & LE(c, 'z') & (c - ('a' - 26))) | + (GE(c, '0') & LE(c, '9') & (c - ('0' - 52))) | (EQ(c, '+') & 62) | + (EQ(c, '/') & 63); + return x | (EQ(x, 0) & (EQ(c, 'A') ^ 0xFF)); +} + +/* + * Convert some bytes to Base64. 'dst_len' is the length (in characters) + * of the output buffer 'dst'; if that buffer is not large enough to + * receive the result (including the terminating 0), then (size_t)-1 + * is returned. Otherwise, the zero-terminated Base64 string is written + * in the buffer, and the output length (counted WITHOUT the terminating + * zero) is returned. + */ +static size_t to_base64(char *dst, size_t dst_len, const void *src, + size_t src_len) { + size_t olen; + const unsigned char *buf; + unsigned acc, acc_len; + + olen = (src_len / 3) << 2; + switch (src_len % 3) { + case 2: + olen++; + /* fall through */ + case 1: + olen += 2; + break; + } + if (dst_len <= olen) { + return (size_t)-1; + } + acc = 0; + acc_len = 0; + buf = (const unsigned char *)src; + while (src_len-- > 0) { + acc = (acc << 8) + (*buf++); + acc_len += 8; + while (acc_len >= 6) { + acc_len -= 6; + *dst++ = (char)b64_byte_to_char((acc >> acc_len) & 0x3F); + } + } + if (acc_len > 0) { + *dst++ = (char)b64_byte_to_char((acc << (6 - acc_len)) & 0x3F); + } + *dst++ = 0; + return olen; +} + +/* + * Decode Base64 chars into bytes. The '*dst_len' value must initially + * contain the length of the output buffer '*dst'; when the decoding + * ends, the actual number of decoded bytes is written back in + * '*dst_len'. + * + * Decoding stops when a non-Base64 character is encountered, or when + * the output buffer capacity is exceeded. If an error occurred (output + * buffer is too small, invalid last characters leading to unprocessed + * buffered bits), then NULL is returned; otherwise, the returned value + * points to the first non-Base64 character in the source stream, which + * may be the terminating zero. + */ +static const char *from_base64(void *dst, size_t *dst_len, const char *src) { + size_t len; + unsigned char *buf; + unsigned acc, acc_len; + + buf = (unsigned char *)dst; + len = 0; + acc = 0; + acc_len = 0; + for (;;) { + unsigned d; + + d = b64_char_to_byte(*src); + if (d == 0xFF) { + break; + } + src++; + acc = (acc << 6) + d; + acc_len += 6; + if (acc_len >= 8) { + acc_len -= 8; + if ((len++) >= *dst_len) { + return NULL; + } + *buf++ = (acc >> acc_len) & 0xFF; + } + } + + /* + * If the input length is equal to 1 modulo 4 (which is + * invalid), then there will remain 6 unprocessed bits; + * otherwise, only 0, 2 or 4 bits are buffered. The buffered + * bits must also all be zero. + */ + if (acc_len > 4 || (acc & (((unsigned)1 << acc_len) - 1)) != 0) { + return NULL; + } + *dst_len = len; + return src; +} + +/* + * Decode decimal integer from 'str'; the value is written in '*v'. + * Returned value is a pointer to the next non-decimal character in the + * string. If there is no digit at all, or the value encoding is not + * minimal (extra leading zeros), or the value does not fit in an + * 'unsigned long', then NULL is returned. + */ +static const char *decode_decimal(const char *str, unsigned long *v) { + const char *orig; + unsigned long acc; + + acc = 0; + for (orig = str;; str++) { + int c; + + c = *str; + if (c < '0' || c > '9') { + break; + } + c -= '0'; + if (acc > (ULONG_MAX / 10)) { + return NULL; + } + acc *= 10; + if ((unsigned long)c > (ULONG_MAX - acc)) { + return NULL; + } + acc += (unsigned long)c; + } + if (str == orig || (*orig == '0' && str != (orig + 1))) { + return NULL; + } + *v = acc; + return str; +} + +/* ==================================================================== */ +/* + * Code specific to Argon2. + * + * The code below applies the following format: + * + * $argon2[$v=]$m=,t=,p=$$ + * + * where is either 'd', 'id', or 'i', is a decimal integer (positive, + * fits in an 'unsigned long'), and is Base64-encoded data (no '=' padding + * characters, no newline or whitespace). + * + * The last two binary chunks (encoded in Base64) are, in that order, + * the salt and the output. Both are required. The binary salt length and the + * output length must be in the allowed ranges defined in argon2.h. + * + * The ctx struct must contain buffers large enough to hold the salt and pwd + * when it is fed into decode_string. + */ + +int decode_string(argon2_context *ctx, const char *str, argon2_type type) { + +/* check for prefix */ +#define CC(prefix) \ + do { \ + size_t cc_len = strlen(prefix); \ + if (strncmp(str, prefix, cc_len) != 0) { \ + return ARGON2_DECODING_FAIL; \ + } \ + str += cc_len; \ + } while ((void)0, 0) + +/* optional prefix checking with supplied code */ +#define CC_opt(prefix, code) \ + do { \ + size_t cc_len = strlen(prefix); \ + if (strncmp(str, prefix, cc_len) == 0) { \ + str += cc_len; \ + { code; } \ + } \ + } while ((void)0, 0) + +/* Decoding prefix into decimal */ +#define DECIMAL(x) \ + do { \ + unsigned long dec_x; \ + str = decode_decimal(str, &dec_x); \ + if (str == NULL) { \ + return ARGON2_DECODING_FAIL; \ + } \ + (x) = dec_x; \ + } while ((void)0, 0) + + +/* Decoding prefix into uint32_t decimal */ +#define DECIMAL_U32(x) \ + do { \ + unsigned long dec_x; \ + str = decode_decimal(str, &dec_x); \ + if (str == NULL || dec_x > UINT32_MAX) { \ + return ARGON2_DECODING_FAIL; \ + } \ + (x) = (uint32_t)dec_x; \ + } while ((void)0, 0) + + +/* Decoding base64 into a binary buffer */ +#define BIN(buf, max_len, len) \ + do { \ + size_t bin_len = (max_len); \ + str = from_base64(buf, &bin_len, str); \ + if (str == NULL || bin_len > UINT32_MAX) { \ + return ARGON2_DECODING_FAIL; \ + } \ + (len) = (uint32_t)bin_len; \ + } while ((void)0, 0) + + size_t maxsaltlen = ctx->saltlen; + size_t maxoutlen = ctx->outlen; + int validation_result; + const char* type_string; + + /* We should start with the argon2_type we are using */ + type_string = argon2_type2string(type, 0); + if (!type_string) { + return ARGON2_INCORRECT_TYPE; + } + + CC("$"); + CC(type_string); + + /* Reading the version number if the default is suppressed */ + ctx->version = ARGON2_VERSION_10; + CC_opt("$v=", DECIMAL_U32(ctx->version)); + + CC("$m="); + DECIMAL_U32(ctx->m_cost); + CC(",t="); + DECIMAL_U32(ctx->t_cost); + CC(",p="); + DECIMAL_U32(ctx->lanes); + ctx->threads = ctx->lanes; + + CC("$"); + BIN(ctx->salt, maxsaltlen, ctx->saltlen); + CC("$"); + BIN(ctx->out, maxoutlen, ctx->outlen); + + /* The rest of the fields get the default values */ + ctx->secret = NULL; + ctx->secretlen = 0; + ctx->ad = NULL; + ctx->adlen = 0; + ctx->allocate_cbk = NULL; + ctx->free_cbk = NULL; + ctx->flags = ARGON2_DEFAULT_FLAGS; + + /* On return, must have valid context */ + validation_result = validate_inputs(ctx); + if (validation_result != ARGON2_OK) { + return validation_result; + } + + /* Can't have any additional characters */ + if (*str == 0) { + return ARGON2_OK; + } else { + return ARGON2_DECODING_FAIL; + } +#undef CC +#undef CC_opt +#undef DECIMAL +#undef BIN +} + +int encode_string(char *dst, size_t dst_len, argon2_context *ctx, + argon2_type type) { +#define SS(str) \ + do { \ + size_t pp_len = strlen(str); \ + if (pp_len >= dst_len) { \ + return ARGON2_ENCODING_FAIL; \ + } \ + memcpy(dst, str, pp_len + 1); \ + dst += pp_len; \ + dst_len -= pp_len; \ + } while ((void)0, 0) + +#define SX(x) \ + do { \ + char tmp[30]; \ + sprintf(tmp, "%lu", (unsigned long)(x)); \ + SS(tmp); \ + } while ((void)0, 0) + +#define SB(buf, len) \ + do { \ + size_t sb_len = to_base64(dst, dst_len, buf, len); \ + if (sb_len == (size_t)-1) { \ + return ARGON2_ENCODING_FAIL; \ + } \ + dst += sb_len; \ + dst_len -= sb_len; \ + } while ((void)0, 0) + + const char* type_string = argon2_type2string(type, 0); + int validation_result = validate_inputs(ctx); + + if (!type_string) { + return ARGON2_ENCODING_FAIL; + } + + if (validation_result != ARGON2_OK) { + return validation_result; + } + + + SS("$"); + SS(type_string); + + SS("$v="); + SX(ctx->version); + + SS("$m="); + SX(ctx->m_cost); + SS(",t="); + SX(ctx->t_cost); + SS(",p="); + SX(ctx->lanes); + + SS("$"); + SB(ctx->salt, ctx->saltlen); + + SS("$"); + SB(ctx->out, ctx->outlen); + return ARGON2_OK; + +#undef SS +#undef SX +#undef SB +} + +size_t b64len(uint32_t len) { + size_t olen = ((size_t)len / 3) << 2; + + switch (len % 3) { + case 2: + olen++; + /* fall through */ + case 1: + olen += 2; + break; + } + + return olen; +} + +size_t numlen(uint32_t num) { + size_t len = 1; + while (num >= 10) { + ++len; + num = num / 10; + } + return len; +} + diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.h new file mode 100644 index 0000000..5b8b2dd --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/encoding.h @@ -0,0 +1,57 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef ENCODING_H +#define ENCODING_H +#include "argon2.h" + +#define ARGON2_MAX_DECODED_LANES UINT32_C(255) +#define ARGON2_MIN_DECODED_SALT_LEN UINT32_C(8) +#define ARGON2_MIN_DECODED_OUT_LEN UINT32_C(12) + +/* +* encode an Argon2 hash string into the provided buffer. 'dst_len' +* contains the size, in characters, of the 'dst' buffer; if 'dst_len' +* is less than the number of required characters (including the +* terminating 0), then this function returns ARGON2_ENCODING_ERROR. +* +* on success, ARGON2_OK is returned. +*/ +int encode_string(char *dst, size_t dst_len, argon2_context *ctx, + argon2_type type); + +/* +* Decodes an Argon2 hash string into the provided structure 'ctx'. +* The only fields that must be set prior to this call are ctx.saltlen and +* ctx.outlen (which must be the maximal salt and out length values that are +* allowed), ctx.salt and ctx.out (which must be buffers of the specified +* length), and ctx.pwd and ctx.pwdlen which must hold a valid password. +* +* Invalid input string causes an error. On success, the ctx is valid and all +* fields have been initialized. +* +* Returned value is ARGON2_OK on success, other ARGON2_ codes on error. +*/ +int decode_string(argon2_context *ctx, const char *str, argon2_type type); + +/* Returns the length of the encoded byte stream with length len */ +size_t b64len(uint32_t len); + +/* Returns the length of the encoded number num */ +size_t numlen(uint32_t num); + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/genkat.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/genkat.h new file mode 100644 index 0000000..3a7162a --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/genkat.h @@ -0,0 +1,51 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef ARGON2_KAT_H +#define ARGON2_KAT_H + +#include "core.h" + +/* + * Initial KAT function that prints the inputs to the file + * @param blockhash Array that contains pre-hashing digest + * @param context Holds inputs + * @param type Argon2 type + * @pre blockhash must point to INPUT_INITIAL_HASH_LENGTH bytes + * @pre context member pointers must point to allocated memory of size according + * to the length values + */ +void initial_kat(const uint8_t *blockhash, const argon2_context *context, + argon2_type type); + +/* + * Function that prints the output tag + * @param out output array pointer + * @param outlen digest length + * @pre out must point to @a outlen bytes + **/ +void print_tag(const void *out, uint32_t outlen); + +/* + * Function that prints the internal state at given moment + * @param instance pointer to the current instance + * @param pass current pass number + * @pre instance must have necessary memory allocated + **/ +void internal_kat(const argon2_instance_t *instance, uint32_t pass); + +#endif diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/ref.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/ref.c new file mode 100644 index 0000000..10e45eb --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/ref.c @@ -0,0 +1,194 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#include +#include +#include + +#include "argon2.h" +#include "core.h" + +#include "blake2/blamka-round-ref.h" +#include "blake2/blake2-impl.h" +#include "blake2/blake2.h" + + +/* + * Function fills a new memory block and optionally XORs the old block over the new one. + * @next_block must be initialized. + * @param prev_block Pointer to the previous block + * @param ref_block Pointer to the reference block + * @param next_block Pointer to the block to be constructed + * @param with_xor Whether to XOR into the new block (1) or just overwrite (0) + * @pre all block pointers must be valid + */ +static void fill_block(const block *prev_block, const block *ref_block, + block *next_block, int with_xor) { + block blockR, block_tmp; + unsigned i; + + copy_block(&blockR, ref_block); + xor_block(&blockR, prev_block); + copy_block(&block_tmp, &blockR); + /* Now blockR = ref_block + prev_block and block_tmp = ref_block + prev_block */ + if (with_xor) { + /* Saving the next block contents for XOR over: */ + xor_block(&block_tmp, next_block); + /* Now blockR = ref_block + prev_block and + block_tmp = ref_block + prev_block + next_block */ + } + + /* Apply Blake2 on columns of 64-bit words: (0,1,...,15) , then + (16,17,..31)... finally (112,113,...127) */ + for (i = 0; i < 8; ++i) { + BLAKE2_ROUND_NOMSG( + blockR.v[16 * i], blockR.v[16 * i + 1], blockR.v[16 * i + 2], + blockR.v[16 * i + 3], blockR.v[16 * i + 4], blockR.v[16 * i + 5], + blockR.v[16 * i + 6], blockR.v[16 * i + 7], blockR.v[16 * i + 8], + blockR.v[16 * i + 9], blockR.v[16 * i + 10], blockR.v[16 * i + 11], + blockR.v[16 * i + 12], blockR.v[16 * i + 13], blockR.v[16 * i + 14], + blockR.v[16 * i + 15]); + } + + /* Apply Blake2 on rows of 64-bit words: (0,1,16,17,...112,113), then + (2,3,18,19,...,114,115).. finally (14,15,30,31,...,126,127) */ + for (i = 0; i < 8; i++) { + BLAKE2_ROUND_NOMSG( + blockR.v[2 * i], blockR.v[2 * i + 1], blockR.v[2 * i + 16], + blockR.v[2 * i + 17], blockR.v[2 * i + 32], blockR.v[2 * i + 33], + blockR.v[2 * i + 48], blockR.v[2 * i + 49], blockR.v[2 * i + 64], + blockR.v[2 * i + 65], blockR.v[2 * i + 80], blockR.v[2 * i + 81], + blockR.v[2 * i + 96], blockR.v[2 * i + 97], blockR.v[2 * i + 112], + blockR.v[2 * i + 113]); + } + + copy_block(next_block, &block_tmp); + xor_block(next_block, &blockR); +} + +static void next_addresses(block *address_block, block *input_block, + const block *zero_block) { + input_block->v[6]++; + fill_block(zero_block, input_block, address_block, 0); + fill_block(zero_block, address_block, address_block, 0); +} + +void fill_segment(const argon2_instance_t *instance, + argon2_position_t position) { + block *ref_block = NULL, *curr_block = NULL; + block address_block, input_block, zero_block; + uint64_t pseudo_rand, ref_index, ref_lane; + uint32_t prev_offset, curr_offset; + uint32_t starting_index; + uint32_t i; + int data_independent_addressing; + + if (instance == NULL) { + return; + } + + data_independent_addressing = + (instance->type == Argon2_i) || + (instance->type == Argon2_id && (position.pass == 0) && + (position.slice < ARGON2_SYNC_POINTS / 2)); + + if (data_independent_addressing) { + init_block_value(&zero_block, 0); + init_block_value(&input_block, 0); + + input_block.v[0] = position.pass; + input_block.v[1] = position.lane; + input_block.v[2] = position.slice; + input_block.v[3] = instance->memory_blocks; + input_block.v[4] = instance->passes; + input_block.v[5] = instance->type; + } + + starting_index = 0; + + if ((0 == position.pass) && (0 == position.slice)) { + starting_index = 2; /* we have already generated the first two blocks */ + + /* Don't forget to generate the first block of addresses: */ + if (data_independent_addressing) { + next_addresses(&address_block, &input_block, &zero_block); + } + } + + /* Offset of the current block */ + curr_offset = position.lane * instance->lane_length + + position.slice * instance->segment_length + starting_index; + + if (0 == curr_offset % instance->lane_length) { + /* Last block in this lane */ + prev_offset = curr_offset + instance->lane_length - 1; + } else { + /* Previous block */ + prev_offset = curr_offset - 1; + } + + for (i = starting_index; i < instance->segment_length; + ++i, ++curr_offset, ++prev_offset) { + /*1.1 Rotating prev_offset if needed */ + if (curr_offset % instance->lane_length == 1) { + prev_offset = curr_offset - 1; + } + + /* 1.2 Computing the index of the reference block */ + /* 1.2.1 Taking pseudo-random value from the previous block */ + if (data_independent_addressing) { + if (i % ARGON2_ADDRESSES_IN_BLOCK == 0) { + next_addresses(&address_block, &input_block, &zero_block); + } + pseudo_rand = address_block.v[i % ARGON2_ADDRESSES_IN_BLOCK]; + } else { + pseudo_rand = instance->memory[prev_offset].v[0]; + } + + /* 1.2.2 Computing the lane of the reference block */ + ref_lane = ((pseudo_rand >> 32)) % instance->lanes; + + if ((position.pass == 0) && (position.slice == 0)) { + /* Can not reference other lanes yet */ + ref_lane = position.lane; + } + + /* 1.2.3 Computing the number of possible reference block within the + * lane. + */ + position.index = i; + ref_index = index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, + ref_lane == position.lane); + + /* 2 Creating a new block */ + ref_block = + instance->memory + instance->lane_length * ref_lane + ref_index; + curr_block = instance->memory + curr_offset; + if (ARGON2_VERSION_10 == instance->version) { + /* version 1.2.1 and earlier: overwrite, not XOR */ + fill_block(instance->memory + prev_offset, ref_block, curr_block, 0); + } else { + if(0 == position.pass) { + fill_block(instance->memory + prev_offset, ref_block, + curr_block, 0); + } else { + fill_block(instance->memory + prev_offset, ref_block, + curr_block, 1); + } + } + } +} diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.c b/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.c new file mode 100644 index 0000000..3ae2fb2 --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.c @@ -0,0 +1,57 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#if !defined(ARGON2_NO_THREADS) + +#include "thread.h" +#if defined(_WIN32) +#include +#endif + +int argon2_thread_create(argon2_thread_handle_t *handle, + argon2_thread_func_t func, void *args) { + if (NULL == handle || func == NULL) { + return -1; + } +#if defined(_WIN32) + *handle = _beginthreadex(NULL, 0, func, args, 0, NULL); + return *handle != 0 ? 0 : -1; +#else + return pthread_create(handle, NULL, func, args); +#endif +} + +int argon2_thread_join(argon2_thread_handle_t handle) { +#if defined(_WIN32) + if (WaitForSingleObject((HANDLE)handle, INFINITE) == WAIT_OBJECT_0) { + return CloseHandle((HANDLE)handle) != 0 ? 0 : -1; + } + return -1; +#else + return pthread_join(handle, NULL); +#endif +} + +void argon2_thread_exit(void) { +#if defined(_WIN32) + _endthreadex(0); +#else + pthread_exit(NULL); +#endif +} + +#endif /* ARGON2_NO_THREADS */ diff --git a/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.h b/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.h new file mode 100644 index 0000000..d4ca10c --- /dev/null +++ b/WEEK07/0x0017a_ctf/third_party/argon2/src/thread.h @@ -0,0 +1,67 @@ +/* + * Argon2 reference source code package - reference C implementations + * + * Copyright 2015 + * Daniel Dinu, Dmitry Khovratovich, Jean-Philippe Aumasson, and Samuel Neves + * + * You may use this work under the terms of a Creative Commons CC0 1.0 + * License/Waiver or the Apache Public License 2.0, at your option. The terms of + * these licenses can be found at: + * + * - CC0 1.0 Universal : https://creativecommons.org/publicdomain/zero/1.0 + * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0 + * + * You should have received a copy of both of these licenses along with this + * software. If not, they may be obtained at the above URLs. + */ + +#ifndef ARGON2_THREAD_H +#define ARGON2_THREAD_H + +#if !defined(ARGON2_NO_THREADS) + +/* + Here we implement an abstraction layer for the simpĺe requirements + of the Argon2 code. We only require 3 primitives---thread creation, + joining, and termination---so full emulation of the pthreads API + is unwarranted. Currently we wrap pthreads and Win32 threads. + + The API defines 2 types: the function pointer type, + argon2_thread_func_t, + and the type of the thread handle---argon2_thread_handle_t. +*/ +#if defined(_WIN32) +#include +typedef unsigned(__stdcall *argon2_thread_func_t)(void *); +typedef uintptr_t argon2_thread_handle_t; +#else +#include +typedef void *(*argon2_thread_func_t)(void *); +typedef pthread_t argon2_thread_handle_t; +#endif + +/* Creates a thread + * @param handle pointer to a thread handle, which is the output of this + * function. Must not be NULL. + * @param func A function pointer for the thread's entry point. Must not be + * NULL. + * @param args Pointer that is passed as an argument to @func. May be NULL. + * @return 0 if @handle and @func are valid pointers and a thread is successfully + * created. + */ +int argon2_thread_create(argon2_thread_handle_t *handle, + argon2_thread_func_t func, void *args); + +/* Waits for a thread to terminate + * @param handle Handle to a thread created with argon2_thread_create. + * @return 0 if @handle is a valid handle, and joining completed successfully. +*/ +int argon2_thread_join(argon2_thread_handle_t handle); + +/* Terminate the current thread. Must be run inside a thread created by + * argon2_thread_create. +*/ +void argon2_thread_exit(void); + +#endif /* ARGON2_NO_THREADS */ +#endif diff --git a/WEEK07/0x0017a_ctf/uf2families.json b/WEEK07/0x0017a_ctf/uf2families.json new file mode 100644 index 0000000..91d99ad --- /dev/null +++ b/WEEK07/0x0017a_ctf/uf2families.json @@ -0,0 +1,22 @@ +[ + { + "short_name": "RP2040", + "id": "0xe48bff56", + "description": "Raspberry Pi RP2040" + }, + { + "short_name": "RP2350-ARM-S", + "id": "0xe48bff59", + "description": "Raspberry Pi RP2350, ARM, Secure" + }, + { + "short_name": "RP2350-ARM-NS", + "id": "0xe48bff5a", + "description": "Raspberry Pi RP2350, ARM, Non-Secure" + }, + { + "short_name": "RP2350-RISCV", + "id": "0xe48bff5b", + "description": "Raspberry Pi RP2350, RISC-V" + } +] diff --git a/WEEK07/WEEK07-BN.md b/WEEK07/WEEK07-BN.md new file mode 100644 index 0000000..5255385 --- /dev/null +++ b/WEEK07/WEEK07-BN.md @@ -0,0 +1,1509 @@ +# Week 7-BN: Binary Ninja Personal — Read, Hack, and Patch Constants and a 1602 LCD String (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into Binary Ninja at `0x10000000` +- Read how a `#define` macro **and** a `const` variable both fold to bare instruction immediates +- Tell a 16-bit `movs r1, #42` from a 32-bit `movw r1, #1337` in the disassembly +- Follow the I2C path through the `i2c_inst_t` struct: `I2C_PORT` -> `i2c1` -> `&i2c1_inst` -> `hw` -> `0x40098000` +- **Break at the `printf` call** on live silicon and hack the printed constant live +- Optionally **hack the LCD string live** by pointing `r0` at a RAM replacement +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map, including the `lcd_1602.c` driver symbols +- **Patch** both constants (`42 -> 43`, `1337 -> 1344`) and the LCD string (`"Reverse" -> "Exploit"`) +- **Export** the patched image, convert it to UF2, and flash it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in Binary Ninja, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 7 lesson, and the Week 7 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helpers `init_i2c_and_lcd` and `write_lcd_greeting` (and the whole `lcd_1602.c` static helper chain) straight into `main` or into the public `lcd_*` functions, and it folds both `FAV_NUM` and `OTHER_FAV_NUM` down to immediate values. If you build `Debug`, the SDK function addresses move and the helpers stay separate calls, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the output change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Serial output | Also does | The hacks | +| ------- | ------------- | --------- | --------- | +| `0x0017_constants` | `FAV_NUM: 42`, `OTHER_FAV_NUM: 1337` | I2C1 (SDA GP2, SCL GP3) drives a 1602 LCD, writing `Reverse` / `Engineering` | `42 -> 43`, `1337 -> 1344`, and `"Reverse" -> "Exploit"` | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **The surprise of this week is that `const` is not in memory.** `#define FAV_NUM 42` becomes the 16-bit `movs r1, #42`; `const int OTHER_FAV_NUM = 1337` *also* becomes an immediate, the 32-bit `movw r1, #1337`. The compiler only keeps a `const` in `.rodata` if the program **takes its address** (`&OTHER_FAV_NUM`); this program never does, so the `const` is inlined exactly like the macro. You patch an instruction operand, not a data word. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +file "$(which telnet)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**`telnet` is special — and optional.** The GDB MI workflow does not need it; it is only used by the command-port fallback. macOS no longer ships `telnet`, and the Homebrew build is often the Intel one, so `telnet 127.0.0.1 4444` fails with `bad CPU type in executable`. Call the Apple Silicon Homebrew explicitly: + +```bash +/opt/homebrew/bin/brew install telnet +``` + +If you would rather not install anything, macOS ships an arm64 `nc`, which can connect to the same OpenOCD port: + +```bash +nc 127.0.0.1 4444 +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x0017_constants/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x0017_constants/build/0x0017_constants.elf` and `.bin` — the `.bin` is **17980** bytes (`0x463c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0017_constants.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0017_constants.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (`init_i2c_and_lcd` and `write_lcd_greeting` inlined) | + +**Our I2C/LCD driver (`lcd_1602.c`) and the SDK I2C functions `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100002bc` | `lcd_i2c_init` | `void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)` | store config + HD44780 reset/configure | +| `0x100006f4` | `lcd_set_cursor` | `void lcd_set_cursor(int, int)` | move the HD44780 cursor | +| `0x100007f0` | `lcd_puts` | `void lcd_puts(const char*)` | write a string to the LCD | +| `0x10003cdc` | `i2c_init` | `uint i2c_init(i2c_inst_t*, uint)` | SDK I2C init (100 kHz) | +| `0x10003d28` | `i2c_write_blocking` | `int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)` | one blocking I2C transfer | +| `0x100008f0` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (I2C pins) | +| `0x1000092c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | + +> The `lcd_1602.c` static helpers — `pcf_write_byte`, `pcf_pulse_enable`, `lcd_write4`, `lcd_send`, `lcd_store_config`, `lcd_hd44780_reset`, `lcd_hd44780_configure` — have **no symbol of their own** in the `Release` build. They are inlined into `lcd_i2c_init`, `lcd_set_cursor`, and `lcd_puts`, which is why those three functions are large and call `i2c_write_blocking` and the `sleep_*` helpers directly. + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10001368` | `sleep_us` | `void sleep_us(uint64_t)` | SDK microsecond delay | +| `0x10001440` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x10001624` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001638` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100016b8` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x1000188c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x100035a4` | `exit` | `void exit(int)` | C runtime exit | +| `0x100035ac` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x100035d8` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x100036e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x100037d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100037fc` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100038c8` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x1000398c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x10003b48` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003e24` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` path reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10003548` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002b64` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10001f48` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x10001eac` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x1000211c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | + +Two things in this project have **no symbol of their own**, because the compiler inlined them into `main`: + +- `init_i2c_and_lcd` and `write_lcd_greeting` — the two `static` helpers in our own source are inlined, so there is no address to rename. You see their bodies directly inside `main`. +- `gpio_pull_up` — `static inline` in the SDK, so `gpio_pull_up(2)` and `gpio_pull_up(3)` compile to direct calls to `gpio_set_pulls` at `0x10000258` and `0x10000262`. + +### Step 5: Flash and confirm the output + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x0017_constants/build/0x0017_constants.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x0017_constants\build\0x0017_constants.bin +``` + +**Or flash from the Binary Ninja console** (the console reads the repo root from the marker file, so it works with no database open): + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0017_constants", "build", "0x0017_constants.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0017_constants", "build", "0x0017_constants.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 17980 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +... +``` + +The 1602 LCD shows `Reverse` on line 1 and `Engineering` on line 2. Both numbers print forever, because both constants are baked into the loop as immediates. That is the behavior we will change. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 6: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x0017_constants/build/0x0017_constants.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> import os +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +> load(os.path.join(root, "0x0017_constants", "build", "0x0017_constants.bin"), +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 7: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x0017_constants.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +The two files have different roles: + +| File | Role | +| ---- | ---- | +| `0x0017_constants.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x0017_constants.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. If a database gets messy, delete the `.bndb` and re-import the `.bin` from Step 6 — the firmware is never at risk. You export the patched image out of this view later, in Step 19. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 12. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at the `printf` Call and Hack Live + +### Step 9: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 10. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. This is the whole reason the lab works cleanly — you never have to drive a reset from outside the GUI. +> +> Use the address you actually want to stop at: +> +> | What you want to stop at | Address | Command | +> | --- | --- | --- | +> | `main` (once per reset) | `0x10000234` | `BP_ADDR=0x10000234 ./debug-server.sh` | +> | The **loop** — the `FAV_NUM` `printf` call, hit every iteration | `0x10000292` | `BP_ADDR=0x10000292 ./debug-server.sh` | +> +> ```bash +> BP_ADDR=0x10000234 ./debug-server.sh # park at main +> BP_ADDR=0x10000292 ./debug-server.sh # park in the loop instead +> ``` +> +> ```powershell +> $env:BP_ADDR="0x10000234"; .\debug-server.ps1 # park at main +> $env:BP_ADDR="0x10000292"; .\debug-server.ps1 # park in the loop +> ``` +> +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 12) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 10: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 9 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length and handles step-over itself. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. Stops are reported as `Breakpoint` (not `SingleStep`). +> +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 9), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. +> +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. +> +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. It is not the adapter for this lab. The dropdown is a combo box, so an accidental arrow-key press can land on it — always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +> **Watch for an off-screen error dialog.** When a connection fails, Binary Ninja pops a `Binary Ninja critical alert` window that can be positioned mostly outside the main window, which makes it look like nothing happened. If the connect seems to do nothing, check your other display. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 11: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186: ldr r1, [pc, #80] @ (100001d8 ) +10000188: blx r1 +1000018a: ldr r1, [pc, #80] @ (100001dc ) +1000018c: blx r1 +1000018e: ldr r1, [pc, #80] @ (100001e0 ) +10000190: blx r1 +10000192: bkpt 0x0000 +10000194: b.n 10000192 @ +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in every project, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234`. + +### Step 12: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +> **Why older drafts used the command port.** Binary Ninja's **GDB RSP** adapter is its own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 FPB comparators need 2 bytes, so OpenOCD rejected it with `only breakpoints of two bytes length supported`. The old workaround was to arm breakpoints by hand over telnet. **The GDB MI adapter does not have this problem** — it drives real `arm-none-eabi-gdb`, which sends the right length. So everything below is done in the GUI. The command port still exists as a fallback (see the end of this step), but you do not need it. + +#### Where you can stop + +| You want to stop at | Address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 9), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **The `FAV_NUM` `printf` call** | `0x10000292` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | +| **The `OTHER_FAV_NUM` `printf` call** | `0x1000029c` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | +| **The `lcd_puts("Reverse")` call** | `0x1000027c` | Set a hardware breakpoint while stopped at `main`, then click **Resume**. | No — the LCD is written once at init. | + +#### Set the loop breakpoint in the GUI + +1. Press `G`, type the loop address (`0x10000292`), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the loop address and reports it as a **Breakpoint** — verified: `Stopped (Breakpoint) at 0x10000292`. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 10). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +#### Stepping + +With the target halted at the breakpoint, **Step Into** (`F7`) and **Step Over** (`F8`) run through real GDB and move the PC. Verified: `0x10000292 -> 0x1000398c -> 0x1000398e -> ...`. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, so **Step Over** at the `printf` call behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 13 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +> **If you ever need the command port.** It is still there — `nc 127.0.0.1 4444`, and `bp 2 hw` still arms a breakpoint, `rbp ` / `rbp all` still remove them. It is the fallback if you switch back to the **GDB RSP** adapter, whose 1-byte breakpoints the GUI cannot set. With GDB MI you do not need it for this lab. + +### Step 13: HACK IT LIVE — change the printed `FAV_NUM` + +`main` loads the `#define` `0x2a` (42) into `r1` and calls `printf` on every iteration. We break on that call and change it live: + +```asm +1000028e: movs r1, #42 @ 0x2a +10000290: ldr r0, [pc, #32] @ (100002b4 ) +10000292: bl 1000398c @ <__wrap_printf> +10000296: movw r1, #1337 @ 0x539 +1000029a: ldr r0, [pc, #28] @ (100002b8 ) +1000029c: bl 1000398c @ <__wrap_printf> +100002a0: b.n 1000028e @ +``` + +1. Press `G`, go to `0x10000292` (the `bl __wrap_printf` for `FAV_NUM`). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the program counter at `0x10000292` and `r1 = 0x2a`. +4. Open the **Registers** widget (bug icon -> **Registers**). +5. Find `r1`. Its value is `0x2a` (42), loaded by the `movs r1, #42` at `0x1000028e`. +6. **Set `r1` to `0x2b` (43).** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r1", 0x2b) + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r1` in the **Registers** widget, press `E` (edit), type `2b`, and press Enter. The widget may not repaint the value, but the write reaches the target — you confirm it by the printed output in the next steps. +7. **Move the breakpoint past the call.** You want `printf` to run once and then stop, so move the breakpoint from `0x10000292` to the instruction *after* the call, `0x10000296` (the `movw r1, #1337` that begins the `OTHER_FAV_NUM` half of the loop): remove the breakpoint at `0x10000292` and set a hardware breakpoint at `0x10000296`. Two reasons not to just click **Step Over** here: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `__wrap_printf` on this raw `.bin` because the image carries no symbol for the call. Moving the breakpoint to the return site is deterministic. +8. Click **Resume** in Binary Ninja. The core executes `bl __wrap_printf` with `r1 = 0x2b`, so this iteration prints `FAV_NUM: 43`, then stops at `0x10000296`. +9. Look at your serial monitor — the `screen` session on the Pico's USB serial port — and at the **Target** tab in Binary Ninja: + + ``` + FAV_NUM: 43 + ``` + +You changed a running program's output without touching the binary. + +### Step 13b: HACK THE LCD STRING LIVE — change `"Reverse"` to `"Exploit"` (optional) + +The LCD text `"Reverse"` lives in flash (`.rodata`) at `0x10003ee8`, and flash is **read-only at runtime** — a debugger write there does not stick. So instead of overwriting the text in place, redirect the pointer: at the `lcd_puts` call for `"Reverse"`, `r0` holds the string address, so point `r0` at a replacement string you place in RAM. + +> **Do this one while stopped at `main`, before `Resume`.** The LCD is written once during init, at `0x1000027c`. If you have already resumed into the loop, restart the server parked at `0x10000234` (Step 9) and reconnect, or the breakpoint at `0x1000027c` never fires again. + +1. With Binary Ninja stopped at `main` (`0x10000234`), press `G` and go to `0x1000027c` (the `bl lcd_puts` that writes `"Reverse"`, loaded from the literal pool word at `0x100002ac`). +2. Set a **hardware execute** breakpoint at `0x1000027c` and click **Resume**. It fires once, with `r0 = 0x10003ee8`. +3. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console** (`Plugins -> Python Console`) — no command port needed: + ```python + dbg.write_memory(0x20080000, b"Exploit\x00") + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. That writes `Exploit\0`. +4. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +5. Move the breakpoint off the current PC (remove it at `0x1000027c`, set one at `0x10000280`, the `movs r0, #1` after the call) and click **Resume**. `lcd_puts` walks your RAM string and pushes `E x p l o i t` to the PCF8574 over I2C, so line 1 of the LCD now reads: + + ``` + Exploit + ``` + +Like the value hack, this is **one boot only**: the next `lcd_puts` for `"Engineering"` is unaffected, but a reset reloads `r0` from flash. The permanent version is the static patch in Step 18c. + +### Step 14: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x1000028e`, which reloads `movs r1, #42`, so the next line is `FAV_NUM: 42`. The live edit changed one iteration only. There is no memory variable to change; the value is baked into the instruction. To make `FAV_NUM: 43` permanent we must patch the instruction. That is the static pass. + +Press **Pause** to stop the output flood. + +### Step 15: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | ------------------- | ---------- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_100037fc()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `i2c_init` + +1. `G` -> `0x10003cdc`. +2. `Y` -> `uint i2c_init(i2c_inst_t* i2c, uint baudrate)`. + +> **`i2c_init` returns `uint`, not `void`.** The SDK's `i2c_init` returns the actual configured baud rate; the ELF says `unsigned int (i2c_inst_t *, uint)`. Keep the return type. + +#### Worked example: `lcd_i2c_init` + +1. `G` -> `0x100002bc`. +2. `Y` -> `void lcd_i2c_init(i2c_inst_t* i2c, uint8_t pcf_addr, int nibble_shift, uint8_t backlight_mask)`. + +This is our own `lcd_1602.c` code. In this build it is one big function: the compiler inlined `lcd_store_config`, `lcd_hd44780_reset`, and `lcd_hd44780_configure` into it. + +#### Worked example: `lcd_set_cursor` + +1. `G` -> `0x100006f4`. +2. `Y` -> `void lcd_set_cursor(int line, int position)`. + +#### Worked example: `lcd_puts` + +1. `G` -> `0x100007f0`. +2. `Y` -> `void lcd_puts(const char* s)`. + +#### Worked example: `gpio_set_function` + +1. `G` -> `0x100008f0`. +2. `Y` -> `void gpio_set_function(uint gpio, gpio_function_t fn)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x1000092c`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(2)` in our source compiles to: the SDK's `static inline` `gpio_pull_up` disappears, and `main` calls `gpio_set_pulls(2, true, false)` directly at `0x10000258`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x1000398c`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x100037fc`. +2. `Y` -> `bool stdio_init_all(void)`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `i2c_init`, `gpio_set_function`, `gpio_set_pulls`, `lcd_i2c_init`, `lcd_set_cursor`, `lcd_puts`, and `printf`, so we follow that chain down. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── i2c_init +├── gpio_set_function +├── gpio_set_pulls (gpio_pull_up inlined) +├── lcd_i2c_init ── i2c_write_blocking, sleep_us, sleep_ms +│ └── pcf_write_byte / pcf_pulse_enable / lcd_write4 / lcd_send / lcd_store_config / +│ lcd_hd44780_reset / lcd_hd44780_configure (all inlined; no calls) +├── lcd_set_cursor ── i2c_write_blocking, sleep_us +├── lcd_puts ── i2c_write_blocking, sleep_us +└── __wrap_printf ── __wrap_vprintf ── vfctprintf ── _vsnprintf + │ └── _ntoa_format / _out_rev / _out_char + ├── time_us_64 + └── stdio_out_chars_crlf +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002bc` | `lcd_i2c_init` | `void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)` | +| `0x100006f4` | `lcd_set_cursor` | `void lcd_set_cursor(int, int)` | +| `0x100007f0` | `lcd_puts` | `void lcd_puts(const char*)` | +| `0x100008f0` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x1000092c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10001368` | `sleep_us` | `void sleep_us(uint64_t)` | +| `0x10001440` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x10001624` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001638` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100016b8` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x1000188c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x100035a4` | `exit` | `void exit(int)` | +| `0x100035ac` | `runtime_init` | `void runtime_init(void)` | +| `0x100035d8` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x100036e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x100037d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100037fc` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100038c8` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x1000398c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003b48` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003cdc` | `i2c_init` | `uint i2c_init(i2c_inst_t*, uint)` | +| `0x10003d28` | `i2c_write_blocking` | `int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)` | +| `0x10003e24` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` path reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10003548` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002b64` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10001f48` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x10001eac` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x1000211c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`i2c1_inst` is data, not a function.** `arm-none-eabi-nm -n` lists `2000062c T i2c1_inst`. The `T` is a **global data** symbol: the linker parks the `i2c1_inst` struct at RAM address `0x2000062c`. Its first word is the hardware pointer `0x40098000`, the I2C1 register base. There is no function there; do not `Y` it with a prototype. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> struct i2c_inst; +> typedef struct i2c_inst i2c_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002bc: ("lcd_i2c_init", "void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)"), +> 0x100006f4: ("lcd_set_cursor", "void lcd_set_cursor(int, int)"), +> 0x100007f0: ("lcd_puts", "void lcd_puts(const char*)"), +> 0x100008f0: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x1000092c: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10001368: ("sleep_us", "void sleep_us(uint64_t)"), +> 0x10001440: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x10001624: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001638: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100016b8: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x1000188c: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x100035a4: ("exit", "void exit(int)"), +> 0x100035ac: ("runtime_init", "void runtime_init(void)"), +> 0x100035d8: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x100036e8: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x100037d4: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100037fc: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100038c8: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x1000398c: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003b48: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003cdc: ("i2c_init", "uint i2c_init(i2c_inst_t*, uint)"), +> 0x10003d28: ("i2c_write_blocking", "int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)"), +> 0x10003e24: ("strlen", "size_t strlen(const char*)"), +> 0x10003548: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x10002b64: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x10001f48: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x10001eac: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x1000211c: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`i2c_inst_t`, `uart_inst_t`, `stdio_driver_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`, and `out_fct_type`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + i2c_init(&i2c1_inst, 0x186a0); // i2c_init(i2c1, 100000) + gpio_set_function(2, GPIO_FUNC_I2C); + gpio_set_function(3, GPIO_FUNC_I2C); + gpio_set_pulls(2, true, false); // gpio_pull_up(2) + gpio_set_pulls(3, true, false); // gpio_pull_up(3) + lcd_i2c_init(&i2c1_inst, 0x27, 4, 8); // lcd_i2c_init(i2c1, 0x27, 4, 0x08) + lcd_set_cursor(0, 0); + lcd_puts("Reverse"); + lcd_set_cursor(1, 0); + lcd_puts("Engineering"); + while (true) { + __wrap_printf("FAV_NUM: %d\r\n", 0x2a); // FAV_NUM = 42 + __wrap_printf("OTHER_FAV_NUM: %d\r\n", 0x539); // OTHER_FAV_NUM = 1337 + } +} +``` + +The `0x2a` and `0x539` are the constants we will patch. Both are **immediates in the instruction stream** — there is no `.rodata` word to change, which is why the patch edits the instruction operand. Now make the hacks permanent. + +### Step 18: Patch 1 — change `FAV_NUM` from 42 to 43 + +Go to `0x1000028e`: + +```asm +1000028e: 2a 21 movs r1, #42 @ 0x2a +``` + +The halfword is `0x212a`, stored little-endian as `2a 21`. The immediate is the low byte, so the byte at the instruction's own address is `0x2a`. Change it to `0x2b` (43). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x1000028e` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `FAV_NUM: 43` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000028e` and change the byte `2A` to `2B`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000028e, b"\x2b") +print(hex(bv.read(0x1000028e, 1)[0])) # -> 0x2b +``` + +After reanalysis the instruction reads `movs r1, #43`. + +### Step 18b: Patch 2 — change `OTHER_FAV_NUM` from 1337 to 1344 + +Go to `0x10000296`: + +```asm +10000296: 40 f2 39 51 movw r1, #1337 @ 0x539 +``` + +This is the 32-bit Thumb-2 encoding of `movw r1, #0x539`. The four bytes and their roles: + +``` ++-----------------------------------------------------------------+ +| movw r1, #0x539 -> bytes: 40 F2 39 51 | +| | +| Byte 0: 0x40 -+ | +| Byte 1: 0xF2 -+ First halfword (opcode + upper imm bits) | +| Byte 2: 0x39 ---- Lower 8 bits of immediate (imm8) <- CHANGE | +| Byte 3: 0x51 ---- Destination register (r1) + upper imm bits | +| | +| imm16 = 0x0539 = 1337 decimal | +| imm8 field = 0x39 (lower 8 bits of the value) | +| | ++-----------------------------------------------------------------+ +``` + +The imm8 byte is the **third** byte of the 4-byte instruction: the instruction starts at `0x10000296`, so the byte to change is `0x10000296 + 2 = 0x10000298`. Change `0x39` to `0x40`, which changes the value from `0x539` (1337) to `0x540` (1344). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x10000298` | `39` | `40` | `movw r1, #1337` -> `#1344`, prints `OTHER_FAV_NUM: 1344` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000298` and change the byte `39` to `40`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000298, b"\x40") +print(bv.read(0x10000296, 4).hex()) # -> 40f24051 +``` + +> **Do not patch `0x10000296` itself.** That is the instruction's first byte (the opcode), not the immediate. The immediate's low 8 bits are at `0x10000298`; patching the opcode corrupts the instruction. + +### Step 18c: Patch 3 — change the LCD text from `"Reverse"` to `"Exploit"` + +The string `"Reverse"` starts at `0x10003ee8`. Its eight bytes are `52 65 76 65 72 73 65 00` (`Reverse\0`). Change them to `45 78 70 6c 6f 69 74 00` (`Exploit\0`). **Both strings are exactly seven characters**, so the replacement fits without touching `"Engineering"` at `0x10003ef0`. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x10003ee8` | `52 65 76 65 72 73 65 00` | `45 78 70 6c 6f 69 74 00` | LCD line 1 prints `Exploit` instead of `Reverse` | + +**ASCII reference:** + +| Character | Hex | +| --------- | --- | +| E | `0x45` | +| x | `0x78` | +| p | `0x70` | +| l | `0x6c` | +| o | `0x6f` | +| i | `0x69` | +| t | `0x74` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10003ee8` and change the eight bytes `52 65 76 65 72 73 65 00` to `45 78 70 6c 6f 69 74 00`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10003ee8, b"Exploit\x00") +print(bv.read(0x10003ee8, 8)) # -> b'Exploit\x00' +``` + +Keep the replacement exactly eight bytes. If you use a shorter string you must pad it and keep the terminating `\0`, or `lcd_puts` will run into the `"Engineering"` string that follows at `0x10003ef0`. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0017_constants", "build"), "0x0017_constants-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 17980 /.../build/0x0017_constants-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x463c` = 17980). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so `open("0x0017_constants-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0017_constants-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0017_constants-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0017_constants", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0017_constants-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +### Step 21: Flash and verify + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Open the serial monitor: + +``` +FAV_NUM: 43 +OTHER_FAV_NUM: 1344 +FAV_NUM: 43 +OTHER_FAV_NUM: 1344 +... +``` + +and the **LCD line 1 reads `Exploit`** while line 2 still reads `Engineering`. + +**Both constants changed and the LCD string changed — with nine operand bytes patched and no source code.** (`0x2a -> 0x2b`, `0x39 -> 0x40`, and the eight-byte string.) + +> **Faster: flash over the Debug Probe (no BOOTSEL).** The repo's `flash.sh` writes the raw `.bin` straight into XIP flash over SWD (`program 0x10000000 verify reset exit`), so you never touch BOOTSEL or a UF2. Run it from a terminal (`./flash.sh `), or from the Binary Ninja console **without freezing it** — use `subprocess.Popen`, which returns immediately, and send OpenOCD's output to a log file. (`subprocess.run` blocks the console until the flash finishes; do not use it here.) +> +> ```python +> import os, subprocess +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +> bin_path = os.path.join(os.path.join(root, "0x0017_constants", "build"), "0x0017_constants-h.bin") +> log = os.path.join(os.path.join(root, "0x0017_constants", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> The `pkill` frees the probe first; on Windows use `subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"])`. +> +> The console is free the moment this returns. Check it with `print(p.poll())` (`None` = still running, `0` = done) or read `flash.log` — success ends with `** Verified OK **`. +> +> The same non-blocking form without the script: +> +> ```python +> import os, subprocess +> ocd = os.path.expanduser("~/.pico-sdk/openocd/0.12.0+dev") +> bin_path = os.path.join(os.path.join(root, "0x0017_constants", "build"), "0x0017_constants-h.bin") +> log = os.path.join(os.path.join(root, "0x0017_constants", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([f"{ocd}/openocd", "-s", f"{ocd}/scripts", +> "-f", "interface/cmsis-dap.cfg", "-f", "target/rp2350.cfg", +> "-c", "adapter speed 5000", +> "-c", f"program {bin_path} 0x10000000 verify reset exit"], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> **The Debug Probe is single-owner.** If Binary Ninja is still attached (the `debug-server.sh` OpenOCD is running), the flash cannot grab the probe. Detach in Binary Ninja and stop that OpenOCD first: +> +> ```bash +> # macOS / Linux +> pkill -TERM -f openocd +> ``` +> ```powershell +> # Windows +> Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +> ``` +> +> Success looks like `Programming Finished` -> `Verified OK` -> `Resetting Target`. On Windows use `flash.ps1` (`.\flash.ps1 -Bin `) the same way. + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r1", 0x2b)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write a RAM string live | `dbg.write_memory(0x20080000, b"Exploit\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 12). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Start the server parked in the loop | macOS/Linux: `BP_ADDR=0x10000292 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000292"; .\debug-server.ps1` | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x1000028e` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `FAV_NUM: 43` | +| `0x0017` | `0x10000298` | `39` | `40` | `movw r1, #1337` -> `#1344`, prints `OTHER_FAV_NUM: 1344` | +| `0x0017` | `0x10003ee8` | `52 65 76 65 72 73 65 00` | `45 78 70 6c 6f 69 74 00` | LCD line 1 prints `Exploit` instead of `Reverse` | + +### The I2C/LCD memory map + +| Item | Address | Notes | +| ---- | ------- | ----- | +| `i2c1_inst` | `0x2000062c` | RAM `.data`, fixed for the life of the program | +| `i2c1_inst.hw` | `0x40098000` | I2C1 hardware register base (first word of the struct) | +| `i2c1_inst.restart_on_next` | `0x20000630` | second word of the struct, `0` (false) | +| Literal-pool word 1 | `0x100002a4` | `0x000186a0` — I2C baud rate, 100000 | +| Literal-pool word 2 | `0x100002a8` | `0x2000062c` — `&i2c1_inst` | +| Literal-pool word 3 | `0x100002ac` | `0x10003ee8` — pointer to `"Reverse"` | +| Literal-pool word 4 | `0x100002b0` | `0x10003ef0` — pointer to `"Engineering"` | +| Literal-pool word 5 | `0x100002b4` | `0x10003efc` — pointer to `"FAV_NUM: %d\r\n"` | +| Literal-pool word 6 | `0x100002b8` | `0x10003f0c` — pointer to `"OTHER_FAV_NUM: %d\r\n"` | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project size | `17980` bytes (`0x463c`) | +| Fixed `main` anchor | `0x1000018c` (reset handler middle `blx`) | +| `main` | `0x10000234` | +| `printf` call / return, `FAV_NUM` | `0x10000292` / `0x10000296` | +| `printf` call, `OTHER_FAV_NUM` | `0x1000029c` | +| `i2c1_inst` RAM address | `0x2000062c` | +| I2C1 hardware registers | `0x40098000` | +| `FAV_NUM` format string | `0x10003efc` | +| `OTHER_FAV_NUM` format string | `0x10003f0c` | +| `"Reverse"` string | `0x10003ee8` | +| `"Engineering"` string | `0x10003ef0` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints (see the next entry). +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 10). The 13.3.rel1 build did **not** connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +**Use GDB MI**, with the 14.2.rel1 path above. If it still fails, fall back to plain `arm-none-eabi-gdb` against the same server — the addresses and register values are identical to the GUI steps. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### The GUI refuses to set a breakpoint (GDB RSP adapter only) + +If you are on the **GDB RSP** adapter, the GUI cannot set breakpoints on this target. That adapter is Binary Ninja's own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 comparators need 2 bytes, so OpenOCD answers `only breakpoints of two bytes length supported`. It affects every address, both `Toggle Breakpoint` and `Add Hardware Breakpoint`, and the dialog's **Size** field is disabled. `gdb_breakpoint_override` makes no difference. + +**Fix: use the GDB MI adapter** (Step 10). It drives real GDB, which sends the correct length, so GUI breakpoints just work. If you must stay on GDB RSP, arm breakpoints from the command port after connecting (`bp 2 hw`) — but the lab uses GDB MI and does not need that. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. This is a Binary Ninja bug. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +Never have a breakpoint in the binary view before the GDB MI connection. If it hangs, quit Binary Ninja, restart the server with `BP_ADDR`, and connect again before adding any breakpoints. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping, because the RP2350 config's `-rtos hwthread` makes the current thread id 1 while Binary Ninja sends thread id 0. Fix: `rp2350.dap.core0 configure -rtos none` (the launcher scripts already pass this). **GDB MI does not hit this.** + +To tell them apart, turn on OpenOCD logging (`log_output /tmp/ocd.log`, then `debug_level 3` on the command port) and look for `fake step` versus `Duplicate Breakpoint`. + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps `init_i2c_and_lcd` / `write_lcd_greeting` as separate calls, so `main` is not at `0x10000234`. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. With the **GDB MI** adapter, `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — that is a software breakpoint and cannot be written to read-only flash, so it never installs. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Verify it is armed:** `mdw 0xE0002000 8`. You should see your address with the low bit set (`0x10000292` -> `0x10000293`). All zeros means nothing is armed — re-read this first, because it distinguishes "not armed" from "armed but never reached". +- **Is the core running?** `poll` on the command port should not report a halt. If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup (Step 9) rather than `reset run` while attached. Loop addresses such as `0x10000292` fire on the next pass with no reset — arm them and click **Resume** in Binary Ninja. +- **With GDB MI the stop is reported as `Breakpoint`** and appears in the **Breakpoints** widget, because GDB really did set it. + +### I edit `r1` (or another register) and it reverts + +`main` reloads the value at the top of every loop iteration — `movs r1, #42` at `0x1000028e` runs right before the `printf` at `0x10000292`. So `r1` is only `0x2b` for the instant between your edit and the next pass; then it is `0x2a` again. The edit sticks only if the core is **genuinely stopped** at the breakpoint and stays stopped. + +If it keeps reverting, the core is running, which almost always means the breakpoint is not installed — usually because it is a **software** breakpoint (`F2`) that cannot be written to read-only flash. Use `Debugger -> Add Hardware Breakpoint...` (hardware execute). + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target, and there is no "refresh registers" command. So a value changed outside Binary Ninja will not appear until the next stop. + +### The LCD string hack does nothing + +The LCD is written **once**, during `lcd_i2c_init` / `write_lcd_greeting`, before the loop starts. You must break at `0x1000027c` and redirect `r0` **before** that call runs. If you already let the target run into the loop, the LCD already shows the old strings. Restart the server parked at `main` (`BP_ADDR=0x10000234`) and reconnect, then set the breakpoint at `0x1000027c` while stopped. + +Also confirm you wrote a NUL-terminated string. `lcd_puts` walks bytes until `*s == 0`; without the trailing `\x00`, it keeps sending RAM garbage to the PCF8574. + +### The compiler did not keep `const` in `.rodata` + +It is not supposed to in this build. `const int OTHER_FAV_NUM = 1337` becomes `movw r1, #1337` because the program never takes its address (`&OTHER_FAV_NUM`) and the value fits in a 16-bit immediate. A `const` only stays in `.rodata` when something forces it there — an address-taken `const`, an array, a pointer, or `volatile`. When you reverse a real binary, never assume a `const` is a memory load; check the instruction. + +### The `movw` patch did not take + +You patched the wrong byte. `movw` is a 32-bit instruction and its low immediate byte (`imm8`) is the **third** byte. The instruction starts at `0x10000296`, so the byte to change is `0x10000298` (`0x39 -> 0x40`). Patching `0x10000296` (the opcode) corrupts the instruction and the core will fault. + +### The LCD shows garbage after patching + +The replacement string is the wrong length or is missing its NUL. `"Reverse"` and `"Exploit"` are both seven characters, and the original eight-byte block is `52 65 76 65 72 73 65 00`. Write exactly `45 78 70 6c 6f 69 74 00`. A shorter string without padding runs into `"Engineering"` at `0x10003ef0`; a longer one overwrites it. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first: clear canonical/echo flags, set `CLOCAL|CREAD`, and `B115200` on input and output. `screen /dev/cu.usbmodem* 115200` does all of this for you; a script must call `tcsetattr` itself. Once set, the capture reads clean `FAV_NUM: 42` lines. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +This is the most common failure, and it has one main cause: **driving the core from the OpenOCD command port while Binary Ninja is connected.** + +- If you send `reset run` from the port while attached, the core resets, runs, and halts at your breakpoint — but Binary Ninja never receives the stop event. Its sidebar keeps showing the *previous* location, so **Step** and **Resume** act on a stale PC and appear to do nothing. +- If the OpenOCD process dies (or you restart it) while attached, Binary Ninja keeps believing it is connected: the sidebar stays, but the menu shows **Pause** enabled and **Resume**/**Step** disabled because Binary Ninja last saw the target *running*. + +Recovery: **Detach, then reconnect.** If Detach does nothing (the connection is already dead), restart Binary Ninja — its menu still shows a session that no longer exists. + +Prevention: + +- Stop at `main` with `BP_ADDR` on a fresh server start, not with `reset run` while attached. +- For loop addresses, set the breakpoint in the GUI and click **Resume**. Let Binary Ninja be the thing that starts the core. +- If you must reset, **Detach first**, `reset run`, then reconnect. +- Never leave a breakpoint on the PC you are about to step or resume from. + +### The target "blows past" `main` and stops at `0x10003ab4` instead + +`0x10003ab4` is inside `stdio_uart_out_flush`: + +```asm +10003ab0: 4b02 ldr r3, [pc, #8] @ (10003abc ) +10003ab2: 681a ldr r2, [r3] +10003ab4: 6993 ldr r3, [r2, #24] @ the core sits here while the UART drains +10003ab6: 071b lsls r3, r3, #28 +10003ab8: d4fc bmi.n 10003ab4 +10003aba: 4770 bx lr +10003abc: 2000086c .word 0x2000086c +``` + +That is the UART transmit-FIFO drain loop inside `printf`, so the core is running `main`'s loop and simply spends nearly all its time there. The breakpoint at `main` did not fire because `main`'s entry runs exactly **once per reset**. If you arm the breakpoint after the reset, or set it while the target is already running and just resume, the core is already past `main` and will never re-execute it. Either arm the breakpoint **before** resetting, or break inside the loop at `0x10000292`, which fires every iteration. + +**`0x10003ab4` is not a function.** It is one instruction inside `stdio_uart_out_flush`, which starts at `0x10003ab0`. If Binary Ninja has created a function at `0x10003ab4` (for example because the debugger stopped at that PC), the decompiler shows garbage. Delete that bogus function (right-click it -> `Delete Function`, or put the cursor on it and press `U` to undefine) and reanalyze. The real function is `stdio_uart_out_flush` at `0x10003ab0`. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### `Connect to Remote Process` is greyed out and Pause does nothing + +Binary Ninja is in a stale session, usually because the debug server restarted while attached. Quit and reopen Binary Ninja (or the `.bndb`) and connect again. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27 (see Troubleshooting), you can still do the live hack with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 9), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x10000292 +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x10000292` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. If you reset first, the core runs `main` and you will not catch it. + +GDB stops at the `printf` call. Confirm the value, change it, and let it run: + +``` +info registers pc r1 # pc = 0x10000292, r1 = 0x2a +set $r1 = 0x2b +stepi +continue +``` + +The serial monitor prints `FAV_NUM: 43` for the iteration you changed — the same temporary live hack as editing `r1` in the Binary Ninja Registers widget. When you are done, press `Ctrl-C`, then `detach` and `quit`. + +**If you specifically want to stop at `main` (`0x10000234`),** remember its entry runs only once per reset, so the breakpoint must be armed *before* the reset: + +``` +monitor reset halt +hbreak *0x10000234 +continue +``` + +If you instead set it while the target is running and just `continue`, you will "blow past" `main` and catch the core inside `printf` — in this build at `0x10003ab4`, the `stdio_uart_out_flush` UART-drain loop. + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too; the old **GDB RSP** adapter was the one that sent a 1-byte length and could not set breakpoints here. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **AAPCS** | ARM Architecture Procedure Call Standard — `r0`-`r3` for the first four arguments, `r0` for the return value | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; zeroed by startup code | +| **`const`** | A source-level "read-only" qualifier; the compiler may still inline it as an immediate | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **`#define`** | Preprocessor text replacement performed before compilation; consumed by the compiler as a literal | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`imm8`** | The low 8 bits of a `movw` immediate, stored in the third byte of the 32-bit instruction | +| **Immediate value** | A constant embedded directly in an instruction, not fetched from memory | +| **I2C** | Inter-Integrated Circuit — a two-wire (SDA/SCL) serial bus; open-drain, needs pull-ups | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **`movs`** | 16-bit Thumb move that loads an 8-bit immediate (0-255) | +| **`movw`** | 32-bit Thumb-2 "move wide" that loads any 16-bit immediate (0-65535) | +| **Open-drain** | An output that can only pull a line LOW, not drive it HIGH; pull-ups restore HIGH | +| **PCF8574** | The I2C I/O expander on a typical 1602 LCD backpack; commonly at `0x27` | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SCL / SDA** | I2C Serial Clock and Serial Data lines | +| **Struct** | A user-defined type that groups related variables; the SDK uses one per I2C controller | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **`typedef`** | Creates an alias for a type (for example `typedef struct i2c_inst i2c_inst_t`) | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, read `r1` at the `printf` call, resolve the names from the ELF (including the `lcd_1602.c` symbols), then patch the bytes — `0x2a -> 0x2b`, `0x39 -> 0x40`, and the eight-byte LCD string — and flash. diff --git a/WEEK07/WEEK07-BN.pdf b/WEEK07/WEEK07-BN.pdf new file mode 100644 index 0000000..ac65051 Binary files /dev/null and b/WEEK07/WEEK07-BN.pdf differ diff --git a/WEEK07/WEEK07-IDA.md b/WEEK07/WEEK07-IDA.md new file mode 100644 index 0000000..ec8848d --- /dev/null +++ b/WEEK07/WEEK07-IDA.md @@ -0,0 +1,765 @@ +# Week 7-IDA: IDA Pro — Read, Hack, and Patch Constants and a 1602 LCD String (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into IDA at `0x10000000` +- Read how a `#define` macro **and** a `const` variable both fold to bare instruction immediates +- Tell a 16-bit `movs r1, #42` from a 32-bit `movw r1, #1337` in the disassembly +- Follow the I2C path through the `i2c_inst_t` struct: `I2C_PORT` -> `i2c1` -> `&i2c1_inst` -> `hw` -> `0x40098000` +- Optionally **hack the LCD string live** by pointing `r0` at a RAM replacement +- **Resolve the functions in the IDA GUI** using the ELF symbol map, including the `lcd_1602.c` driver symbols +- **Patch** both constants (`42 -> 43`, `1337 -> 1344`) and the LCD string (`"Reverse" -> "Exploit"`) +- **Export** the patched image, convert it to UF2, and export it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in IDA, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 7 lesson, and the Week 7 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helpers `init_i2c_and_lcd` and `write_lcd_greeting` (and the whole `lcd_1602.c` static helper chain) straight into `main` or into the public `lcd_*` functions, and it folds both `FAV_NUM` and `OTHER_FAV_NUM` down to immediate values. If you build `Debug`, the SDK function addresses move and the helpers stay separate calls, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Serial output | Also does | The hacks | +| ------- | ------------- | --------- | --------- | +| `0x0017_constants` | `FAV_NUM: 42`, `OTHER_FAV_NUM: 1337` | I2C1 (SDA GP2, SCL GP3) drives a 1602 LCD, writing `Reverse` / `Engineering` | `42 -> 43`, `1337 -> 1344`, and `"Reverse" -> "Exploit"` | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **The surprise of this week is that `const` is not in memory.** `#define FAV_NUM 42` becomes the 16-bit `movs r1, #42`; `const int OTHER_FAV_NUM = 1337` *also* becomes an immediate, the 32-bit `movw r1, #1337`. The compiler only keeps a `const` in `.rodata` if the program **takes its address** (`&OTHER_FAV_NUM`); this program never does, so the `const` is inlined exactly like the macro. You patch an instruction operand, not a data word. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +bash +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x0017_constants/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point IDA at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so IDA never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the IDA console**, so the whole build -> patch -> flash loop stays inside IDA. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x0017_constants") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x0017_constants/build/0x0017_constants.elf` and `.bin` — the `.bin` is **17980** bytes (`0x463c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0017_constants.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0017_constants.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (`init_i2c_and_lcd` and `write_lcd_greeting` inlined) | + +**Our I2C/LCD driver (`lcd_1602.c`) and the SDK I2C functions `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100002bc` | `lcd_i2c_init` | `void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)` | store config + HD44780 reset/configure | +| `0x100006f4` | `lcd_set_cursor` | `void lcd_set_cursor(int, int)` | move the HD44780 cursor | +| `0x100007f0` | `lcd_puts` | `void lcd_puts(const char*)` | write a string to the LCD | +| `0x10003cdc` | `i2c_init` | `uint i2c_init(i2c_inst_t*, uint)` | SDK I2C init (100 kHz) | +| `0x10003d28` | `i2c_write_blocking` | `int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)` | one blocking I2C transfer | +| `0x100008f0` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (I2C pins) | +| `0x1000092c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | + +> The `lcd_1602.c` static helpers — `pcf_write_byte`, `pcf_pulse_enable`, `lcd_write4`, `lcd_send`, `lcd_store_config`, `lcd_hd44780_reset`, `lcd_hd44780_configure` — have **no symbol of their own** in the `Release` build. They are inlined into `lcd_i2c_init`, `lcd_set_cursor`, and `lcd_puts`, which is why those three functions are large and call `i2c_write_blocking` and the `sleep_*` helpers directly. + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10001368` | `sleep_us` | `void sleep_us(uint64_t)` | SDK microsecond delay | +| `0x10001440` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x10001624` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001638` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100016b8` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x1000188c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x100035a4` | `exit` | `void exit(int)` | C runtime exit | +| `0x100035ac` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x100035d8` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x100036e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x100037d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100037fc` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100038c8` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x1000398c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper | +| `0x10003b48` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003e24` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` path reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10003548` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002b64` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x10001f48` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x10001eac` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x1000211c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | + +Two things in this project have **no symbol of their own**, because the compiler inlined them into `main`: + +- `init_i2c_and_lcd` and `write_lcd_greeting` — the two `static` helpers in our own source are inlined, so there is no address to rename. You see their bodies directly inside `main`. +- `gpio_pull_up` — `static inline` in the SDK, so `gpio_pull_up(2)` and `gpio_pull_up(3)` compile to direct calls to `gpio_set_pulls` at `0x10000258` and `0x10000262`. + +## Part 2: Load the Raw `.bin` into IDA + +Start from a fresh IDA state. If you already have a database for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into IDA + +A raw `.bin` has no headers, so IDA cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, IDA may load it with a guessed architecture, and every address in this lesson will be wrong. + +#### 1.1 Open the file +1. **File ▸ Open…** (Ctrl/Cmd+O). +2. Select the `.bin` file and click **Open**. + +IDA opens the **"Load a new file"** dialog because a raw `.bin` has no header. + +#### 1.2 Set the format and processor +In the *Load a new file* dialog: +1. **Format**: leave it as **Binary file** (IDA auto-detects a headerless image). +2. **Processor type**: click the **…** button next to the processor field. In the *Processor type* dialog: + - Family: **ARM** + - Type: **ARM Little-endian** (the 32-bit ARM module). + - Click **OK**. + +> If IDA asks **"Do you want to disassemble it as 64-bit code?"** — click **No**. +> The RP2350 is 32-bit; answering *Yes* loads AArch64 and you get `X` registers / data. (This is the single most common cause of the `DCB` wall.) + +#### 1.3 Configure the ARM architecture and Thumb mode +Still in the *Load a new file* dialog, open the processor options (the **Processor options** / **Set…** button, which opens the dialog titled **ARM architecture options**): +- **ARM architecture**: choose **ARMv8-M** (this is the Cortex-M33 / RP2350 core). +- **Thumb instructions**: select **Thumb-2** (ARMv8-M is Thumb-only, so this is the correct mode). +- Leave **automatic ARM-THUMB switch** off; we want Thumb throughout. + +#### 1.4 Set the loading address +- **Loading address**: enter **`10000000`** (hex; the RP2350 XIP flash base). + IDA rejects addresses that don't look like ROM/RAM with *"The loading address should belong to RAM or ROM"* — `0x10000000` is the correct flash window. + +Leave **Manual load** and **Create segments** at their defaults. Click **OK**. + +#### 1.5 Force Thumb, then seed the code from the vector table +A raw `.bin` has no header, so IDA's loader has **no entry point** and defaults the segment to **ARM mode** (which cannot decode Thumb). Two required steps — in this order: + +**A. Set the segment to Thumb (do this first).** +- **Edit ▸ Segments ▸ Set default segment register value…** → register **`T`** = **`1`** (or press **`Alt+G`**). IDA reanalyzes the segment as Thumb automatically. + +**B. Seed the code from the vector table.** +1. **G** → `10000000`. The first two words are the initial stack pointer and the **reset vector**. +2. **Read the 4-byte word at `0x10000004`** (do **not** assume its value — it differs per build). +3. **Clear bit 0** (the ARM **Thumb** flag) → the reset handler address. +4. **G** to that address → press **C** (**MakeCode**). IDA disassembles the reset handler and follows its `bl`s into `main`. + +Once `main` shows code, the import is correct. + +**Why IDA needs this and others don't:** IDA's generic raw-binary ARM loader treats the image as flat data and waits for you to set Thumb and mark the entry point. It's an IDA quirk, not a mistake on your part. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Static — Resolve the Functions in IDA and Patch + +### Step 16: Resolve the functions in the IDA GUI + +We now name the functions in IDA using the ELF symbol map from Step 4. IDA loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | IDA action | Use it for | +| --- | ------------------- | ---------- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in IDA (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_100037fc()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. IDA parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **IDA shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and IDA's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `i2c_init` + +1. `G` -> `0x10003cdc`. +2. `Y` -> `uint i2c_init(i2c_inst_t* i2c, uint baudrate)`. + +> **`i2c_init` returns `uint`, not `void`.** The SDK's `i2c_init` returns the actual configured baud rate; the ELF says `unsigned int (i2c_inst_t *, uint)`. Keep the return type. + +#### Worked example: `lcd_i2c_init` + +1. `G` -> `0x100002bc`. +2. `Y` -> `void lcd_i2c_init(i2c_inst_t* i2c, uint8_t pcf_addr, int nibble_shift, uint8_t backlight_mask)`. + +This is our own `lcd_1602.c` code. In this build it is one big function: the compiler inlined `lcd_store_config`, `lcd_hd44780_reset`, and `lcd_hd44780_configure` into it. + +#### Worked example: `lcd_set_cursor` + +1. `G` -> `0x100006f4`. +2. `Y` -> `void lcd_set_cursor(int line, int position)`. + +#### Worked example: `lcd_puts` + +1. `G` -> `0x100007f0`. +2. `Y` -> `void lcd_puts(const char* s)`. + +#### Worked example: `gpio_set_function` + +1. `G` -> `0x100008f0`. +2. `Y` -> `void gpio_set_function(uint gpio, gpio_function_t fn)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x1000092c`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(2)` in our source compiles to: the SDK's `static inline` `gpio_pull_up` disappears, and `main` calls `gpio_set_pulls(2, true, false)` directly at `0x10000258`. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x1000398c`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x100037fc`. +2. `Y` -> `bool stdio_init_all(void)`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `i2c_init`, `gpio_set_function`, `gpio_set_pulls`, `lcd_i2c_init`, `lcd_set_cursor`, `lcd_puts`, and `printf`, so we follow that chain down. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── i2c_init +├── gpio_set_function +├── gpio_set_pulls (gpio_pull_up inlined) +├── lcd_i2c_init ── i2c_write_blocking, sleep_us, sleep_ms +│ └── pcf_write_byte / pcf_pulse_enable / lcd_write4 / lcd_send / lcd_store_config / +│ lcd_hd44780_reset / lcd_hd44780_configure (all inlined; no calls) +├── lcd_set_cursor ── i2c_write_blocking, sleep_us +├── lcd_puts ── i2c_write_blocking, sleep_us +└── __wrap_printf ── __wrap_vprintf ── vfctprintf ── _vsnprintf + │ └── _ntoa_format / _out_rev / _out_char + ├── time_us_64 + └── stdio_out_chars_crlf +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002bc` | `lcd_i2c_init` | `void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)` | +| `0x100006f4` | `lcd_set_cursor` | `void lcd_set_cursor(int, int)` | +| `0x100007f0` | `lcd_puts` | `void lcd_puts(const char*)` | +| `0x100008f0` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x1000092c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10001368` | `sleep_us` | `void sleep_us(uint64_t)` | +| `0x10001440` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x10001624` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001638` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100016b8` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x1000188c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x100035a4` | `exit` | `void exit(int)` | +| `0x100035ac` | `runtime_init` | `void runtime_init(void)` | +| `0x100035d8` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x100036e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x100037d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100037fc` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100038c8` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x1000398c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003b48` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003cdc` | `i2c_init` | `uint i2c_init(i2c_inst_t*, uint)` | +| `0x10003d28` | `i2c_write_blocking` | `int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)` | +| `0x10003e24` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` path reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10003548` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002b64` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x10001f48` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x10001eac` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x1000211c` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | + +> **A `void` return type may not stick — here is the fix.** IDA treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type IDA thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`i2c1_inst` is data, not a function.** `arm-none-eabi-nm -n` lists `2000062c T i2c1_inst`. The `T` is a **global data** symbol: the linker parks the `i2c1_inst` struct at RAM address `0x2000062c`. Its first word is the hardware pointer `0x40098000`, the I2C1 register base. There is no function there; do not `Y` it with a prototype. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into IDA's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> struct i2c_inst; +> typedef struct i2c_inst i2c_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002bc: ("lcd_i2c_init", "void lcd_i2c_init(i2c_inst_t*, uint8_t, int, uint8_t)"), +> 0x100006f4: ("lcd_set_cursor", "void lcd_set_cursor(int, int)"), +> 0x100007f0: ("lcd_puts", "void lcd_puts(const char*)"), +> 0x100008f0: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x1000092c: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10001368: ("sleep_us", "void sleep_us(uint64_t)"), +> 0x10001440: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x10001624: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001638: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100016b8: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x1000188c: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x100035a4: ("exit", "void exit(int)"), +> 0x100035ac: ("runtime_init", "void runtime_init(void)"), +> 0x100035d8: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x100036e8: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x100037d4: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100037fc: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100038c8: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x1000398c: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003b48: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003cdc: ("i2c_init", "uint i2c_init(i2c_inst_t*, uint)"), +> 0x10003d28: ("i2c_write_blocking", "int i2c_write_blocking(i2c_inst_t*, uint8_t, const uint8_t*, size_t, bool)"), +> 0x10003e24: ("strlen", "size_t strlen(const char*)"), +> 0x10003548: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x10002b64: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x10001f48: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x10001eac: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x1000211c: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`i2c_inst_t`, `uart_inst_t`, `stdio_driver_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`, and `out_fct_type`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + i2c_init(&i2c1_inst, 0x186a0); // i2c_init(i2c1, 100000) + gpio_set_function(2, GPIO_FUNC_I2C); + gpio_set_function(3, GPIO_FUNC_I2C); + gpio_set_pulls(2, true, false); // gpio_pull_up(2) + gpio_set_pulls(3, true, false); // gpio_pull_up(3) + lcd_i2c_init(&i2c1_inst, 0x27, 4, 8); // lcd_i2c_init(i2c1, 0x27, 4, 0x08) + lcd_set_cursor(0, 0); + lcd_puts("Reverse"); + lcd_set_cursor(1, 0); + lcd_puts("Engineering"); + while (true) { + __wrap_printf("FAV_NUM: %d\r\n", 0x2a); // FAV_NUM = 42 + __wrap_printf("OTHER_FAV_NUM: %d\r\n", 0x539); // OTHER_FAV_NUM = 1337 + } +} +``` + +The `0x2a` and `0x539` are the constants we will patch. Both are **immediates in the instruction stream** — there is no `.rodata` word to change, which is why the patch edits the instruction operand. Now make the hacks permanent. + +### Step 18: Patch 1 — change `FAV_NUM` from 42 to 43 + +Go to `0x1000028e`: + +```asm +1000028e: 2a 21 movs r1, #42 @ 0x2a +``` + +The halfword is `0x212a`, stored little-endian as `2a 21`. The immediate is the low byte, so the byte at the instruction's own address is `0x2a`. Change it to `0x2b` (43). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x1000028e` | `2a` | `2b` | `movs r1, #42` -> `#43`, prints `FAV_NUM: 43` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000028e` and change the byte `2A` to `2B`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000028e, b"\x2b") +print(hex(bv.read(0x1000028e, 1)[0])) # -> 0x2b +``` + +After reanalysis the instruction reads `movs r1, #43`. + +### Step 18b: Patch 2 — change `OTHER_FAV_NUM` from 1337 to 1344 + +Go to `0x10000296`: + +```asm +10000296: 40 f2 39 51 movw r1, #1337 @ 0x539 +``` + +This is the 32-bit Thumb-2 encoding of `movw r1, #0x539`. The four bytes and their roles: + +``` ++-----------------------------------------------------------------+ +| movw r1, #0x539 -> bytes: 40 F2 39 51 | +| | +| Byte 0: 0x40 -+ | +| Byte 1: 0xF2 -+ First halfword (opcode + upper imm bits) | +| Byte 2: 0x39 ---- Lower 8 bits of immediate (imm8) <- CHANGE | +| Byte 3: 0x51 ---- Destination register (r1) + upper imm bits | +| | +| imm16 = 0x0539 = 1337 decimal | +| imm8 field = 0x39 (lower 8 bits of the value) | +| | ++-----------------------------------------------------------------+ +``` + +The imm8 byte is the **third** byte of the 4-byte instruction: the instruction starts at `0x10000296`, so the byte to change is `0x10000296 + 2 = 0x10000298`. Change `0x39` to `0x40`, which changes the value from `0x539` (1337) to `0x540` (1344). + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x10000298` | `39` | `40` | `movw r1, #1337` -> `#1344`, prints `OTHER_FAV_NUM: 1344` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000298` and change the byte `39` to `40`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000298, b"\x40") +print(bv.read(0x10000296, 4).hex()) # -> 40f24051 +``` + +> **Do not patch `0x10000296` itself.** That is the instruction's first byte (the opcode), not the immediate. The immediate's low 8 bits are at `0x10000298`; patching the opcode corrupts the instruction. + +### Step 18c: Patch 3 — change the LCD text from `"Reverse"` to `"Exploit"` + +The string `"Reverse"` starts at `0x10003ee8`. Its eight bytes are `52 65 76 65 72 73 65 00` (`Reverse\0`). Change them to `45 78 70 6c 6f 69 74 00` (`Exploit\0`). **Both strings are exactly seven characters**, so the replacement fits without touching `"Engineering"` at `0x10003ef0`. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0017` | `0x10003ee8` | `52 65 76 65 72 73 65 00` | `45 78 70 6c 6f 69 74 00` | LCD line 1 prints `Exploit` instead of `Reverse` | + +**ASCII reference:** + +| Character | Hex | +| --------- | --- | +| E | `0x45` | +| x | `0x78` | +| p | `0x70` | +| l | `0x6c` | +| o | `0x6f` | +| i | `0x69` | +| t | `0x74` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10003ee8` and change the eight bytes `52 65 76 65 72 73 65 00` to `45 78 70 6c 6f 69 74 00`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10003ee8, b"Exploit\x00") +print(bv.read(0x10003ee8, 8)) # -> b'Exploit\x00' +``` + +Keep the replacement exactly eight bytes. If you use a shorter string you must pad it and keep the terminating `\0`, or `lcd_puts` will run into the `"Engineering"` string that follows at `0x10003ef0`. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0017_constants", "build"), "0x0017_constants-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 17980 /.../build/0x0017_constants-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base IDA loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x463c` = 17980). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** IDA's Python console runs with a read-only working directory (inside the app bundle), so `open("0x0017_constants-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0017_constants-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0017_constants-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the IDA console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0017_constants", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0017_constants-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +## Static stopping point + +The patched image has been exported and converted to UF2. This IDA guide ends at static verification; it does not connect to, flash, or debug a live target. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **AAPCS** | ARM Architecture Procedure Call Standard — `r0`-`r3` for the first four arguments, `r0` for the return value | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; zeroed by startup code | +| **`const`** | A source-level "read-only" qualifier; the compiler may still inline it as an immediate | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **`#define`** | Preprocessor text replacement performed before compilation; consumed by the compiler as a literal | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **`imm8`** | The low 8 bits of a `movw` immediate, stored in the third byte of the 32-bit instruction | +| **Immediate value** | A constant embedded directly in an instruction, not fetched from memory | +| **I2C** | Inter-Integrated Circuit — a two-wire (SDA/SCL) serial bus; open-drain, needs pull-ups | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **`movs`** | 16-bit Thumb move that loads an 8-bit immediate (0-255) | +| **`movw`** | 32-bit Thumb-2 "move wide" that loads any 16-bit immediate (0-65535) | +| **Open-drain** | An output that can only pull a line LOW, not drive it HIGH; pull-ups restore HIGH | +| **PCF8574** | The I2C I/O expander on a typical 1602 LCD backpack; commonly at `0x27` | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SCL / SDA** | I2C Serial Clock and Serial Data lines | +| **Struct** | A user-defined type that groups related variables; the SDK uses one per I2C controller | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **`typedef`** | Creates an alias for a type (for example `typedef struct i2c_inst i2c_inst_t`) | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions.c` symbols), then patch the bytes — `0x2a -> 0x2b`, `0x39 -> 0x40`, and the eight-byte LCD string — and export the patched artifact. diff --git a/WEEK07/WEEK07-IDA.pdf b/WEEK07/WEEK07-IDA.pdf new file mode 100644 index 0000000..41ca2a5 Binary files /dev/null and b/WEEK07/WEEK07-IDA.pdf differ diff --git a/WEEK07/WEEK07-SLIDES.pdf b/WEEK07/WEEK07-SLIDES.pdf new file mode 100644 index 0000000..7ffc94a Binary files /dev/null and b/WEEK07/WEEK07-SLIDES.pdf differ diff --git a/WEEK07/WEEK07.md b/WEEK07/WEEK07.md new file mode 100644 index 0000000..58c2f87 --- /dev/null +++ b/WEEK07/WEEK07.md @@ -0,0 +1,1097 @@ +# Week 7: Constants in Embedded Systems: Debugging and Hacking Constants w/ 1602 LCD I2C Basics + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand the difference between `#define` macros and `const` variables +- Know how constants are stored differently in memory (compile-time vs runtime) +- Understand the I2C (Inter-Integrated Circuit) communication protocol +- Configure I2C peripherals and communicate with LCD displays +- Understand C structs and how the Pico SDK uses them for hardware abstraction +- Use GDB to examine constants, structs, and string literals in memory +- Hack constant values and string literals using a hex editor +- Patch LCD display text without access to source code + +--- + +## Part 1: Understanding Constants in C + +### Two Types of Constants + +In C, there are two ways to create values that shouldn't change: + +| Type | Syntax | Where It Lives | When Resolved | +| ----------- | ----------------------- | ------------------ | ------------- | +| **#define** | `#define FAV_NUM 42` | Nowhere (replaced) | Compile time | +| **const** | `const int NUM = 1337;` | Flash (.rodata) | Runtime | + +### Preprocessor Macros (#define) + +A **preprocessor macro** is a text replacement that happens BEFORE your code is compiled: + +```c +#define FAV_NUM 42 + +printf("Value: %d", FAV_NUM); +// Becomes: printf("Value: %d", 42); +``` + +Think of it like a "find and replace" in a text editor. The compiler never sees `FAV_NUM` - it only sees `42`! + +``` ++-----------------------------------------------------------------+ +| Preprocessor Macro Flow | +| | +| Source Code Preprocessor Compiler | +| +----------+ +----------+ +----------+ | +| | #define | | Replace | | Compile | | +| | FAV_NUM | -----> | FAV_NUM | -----> | binary | | +| | 42 | | with 42 | | code | | +| +----------+ +----------+ +----------+ | +| | +| FAV_NUM doesn't exist in the final binary! | +| The value 42 is embedded directly in instructions. | +| | ++-----------------------------------------------------------------+ +``` + +### Const Variables + +A **const variable** is an actual variable stored in memory, but marked as read-only: + +```c +const int OTHER_FAV_NUM = 1337; +``` + +Unlike `#define`, this creates a real memory location in the `.rodata` (read-only data) section of flash: + +``` ++-----------------------------------------------------------------+ +| Const Variable in Memory | +| | +| Flash Memory (.rodata section) | +| +------------------------------------------------------------+ | +| | Address: 0x10001234 | | +| | Value: 0x00000539 (1337 in hex) | | +| | Name: OTHER_FAV_NUM (in debug symbols only) | | +| +------------------------------------------------------------+ | +| | +| The variable EXISTS in memory and can be read at runtime. | +| | ++-----------------------------------------------------------------+ +``` + +### Comparison: #define vs const + +| Feature | #define | const | +| -------------------- | ------------------------ | ---------------------------- | +| **Type checking** | None (just text) | Yes (compiler enforced) | +| **Memory usage** | None (inlined) | Uses flash space | +| **Debugger visible** | No | Yes (with symbols) | +| **Can take address** | No (`&FAV_NUM` fails) | Yes (`&OTHER_FAV_NUM` works) | +| **Scope** | Global (from definition) | Normal C scoping rules | + +--- + +## Part 2: Understanding I2C Communication + +### What is I2C? + +**I2C** (pronounced "I-squared-C" or "I-two-C") stands for **Inter-Integrated Circuit**. It's a way for chips to talk to each other using just TWO wires! + +``` ++-----------------------------------------------------------------+ +| I2C Bus - Two Wires, Many Devices | +| | +| 3.3V | +| | | +| + Pull-up + Pull-up | +| | | | +| SDA -+------------+--------------------------------------- | +| | | | +| SCL -+------------+--------------------------------------- | +| | | | | | +| +---+----+ +--+---+ +----+--+ +-----+---+ | +| | Pico | | LCD | |Sensor | | EEPROM | | +| |(Master)| | 0x27 | | 0x48 | | 0x50 | | +| +--------+ +------+ +-------+ +---------+ | +| | +| Each device has a unique address (0x27, 0x48, 0x50...) | +| | ++-----------------------------------------------------------------+ +``` + +### The Two I2C Wires + +| Wire | Name | Purpose | +| ------- | ------------ | ------------------------------------ | +| **SDA** | Serial Data | Carries the actual data bits | +| **SCL** | Serial Clock | Timing signal that synchronizes data | + +### Why Pull-Up Resistors? + +I2C uses **open-drain** signals, meaning devices can only pull the line LOW. They can't drive it HIGH! Pull-up resistors are needed to bring the lines back to HIGH when no device is pulling them down. + +The Pico 2 has internal pull-ups that we can enable with `gpio_pull_up()`. + +### I2C Addresses + +Every I2C device has a unique **7-bit address**. Common addresses: + +| Device Type | Typical Address | +| --------------------- | ---------------- | +| 1602 LCD with PCF8574 | `0x27` or `0x3F` | +| Temperature sensor | `0x48` | +| EEPROM | `0x50` | +| Real-time clock | `0x68` | + +### I2C Communication Flow + +``` ++-----------------------------------------------------------------+ +| I2C Transaction | +| | +| 1. Master sends START condition | +| 2. Master sends device address (7 bits) + R/W bit | +| 3. Addressed device sends ACK (acknowledge) | +| 4. Data is transferred (8 bits at a time) | +| 5. Receiver sends ACK after each byte | +| 6. Master sends STOP condition | +| | +| START --> Address --> ACK --> Data --> ACK --> STOP | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 3: Understanding C Structs + +### What is a Struct? + +A **struct** (short for "structure") is a way to group related variables together under one name. Think of it like a form with multiple fields: + +```c +// A struct definition - like a template +struct student { + char name[50]; + int age; + float gpa; +}; + +// Creating a variable of this struct type +struct student alice = {"Alice", 16, 3.8}; +``` + +### Why Use Structs? + +Instead of passing many separate variables: +```c +void print_student(char *name, int age, float gpa); // Messy! +``` + +You pass one struct: +```c +void print_student(struct student s); // Clean! +``` + +### The typedef Keyword + +Writing `struct student` everywhere is tedious. The `typedef` keyword creates an alias: + +```c +typedef struct student student_t; + +// Now you can write: +student_t alice; // Instead of: struct student alice; +``` + +### Forward Declaration + +Sometimes you need to tell the compiler "this struct exists" before defining it: + +```c +typedef struct i2c_inst i2c_inst_t; // Forward declaration + alias + +// Later, the full definition: +struct i2c_inst { + i2c_hw_t *hw; + bool restart_on_next; +}; +``` + +--- + +## Part 4: Understanding the Pico SDK's I2C Structs + +### The i2c_inst_t Struct + +The Pico SDK uses a struct to represent each I2C controller: + +```c +struct i2c_inst { + i2c_hw_t *hw; // Pointer to hardware registers + bool restart_on_next; // SDK internal flag +}; +``` + +**What each member means:** + +| Member | Type | Purpose | +| ----------------- | ------------ | ---------------------------------------- | +| `hw` | `i2c_hw_t *` | Pointer to the actual hardware registers | +| `restart_on_next` | `bool` | Tracks if next transfer needs a restart | + +### The Macro Chain + +When you write `I2C_PORT` in your code, here's what happens: + +``` ++-----------------------------------------------------------------+ +| Macro Expansion Chain | +| | +| In your code: #define I2C_PORT i2c1 | +| | | +| ↓ | +| In i2c.h: #define i2c1 (&i2c1_inst) | +| | | +| ↓ | +| In i2c.c: i2c_inst_t i2c1_inst = {i2c1_hw, false}; | +| | | +| ↓ | +| In i2c.h: #define i2c1_hw ((i2c_hw_t *)I2C1_BASE) | +| | | +| ↓ | +| In addressmap.h: #define I2C1_BASE 0x40098000 | +| | ++-----------------------------------------------------------------+ +``` + +So `I2C_PORT` eventually becomes a pointer to a struct that contains a pointer to hardware registers at address `0x40098000`! + +### The Hardware Register Pointer + +The `i2c_hw_t *hw` member points to the actual silicon: + +``` ++-----------------------------------------------------------------+ +| Memory Map | +| | +| Address 0x40098000: I2C1 Hardware Registers | +| +------------------------------------------------------------+ | +| | Offset 0x00: IC_CON (Control register) | | +| | Offset 0x04: IC_TAR (Target address register) | | +| | Offset 0x10: IC_DATA_CMD (Data command register) | | +| | ... | | +| +------------------------------------------------------------+ | +| | +| The i2c_hw_t struct maps directly to these registers! | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 5: The ARM Calling Convention (AAPCS) + +### How Arguments Are Passed + +On ARM Cortex-M, the **ARM Architecture Procedure Call Standard (AAPCS)** defines how functions receive arguments: + +| Register | Purpose | +| -------- | ---------------- | +| `r0` | First argument | +| `r1` | Second argument | +| `r2` | Third argument | +| `r3` | Fourth argument | +| Stack | Fifth+ arguments | +| `r0` | Return value | + +### Example: i2c_init(i2c1, 100000) + +```c +i2c_init(I2C_PORT, 100000); +``` + +In assembly: +```assembly +ldr r0, [address of i2c1_inst] ; r0 = pointer to struct (first arg) +ldr r1, =0x186A0 ; r1 = 100000 (second arg) +bl i2c_init ; Call the function +``` + +--- + +## Part 6: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. A Raspberry Pi Pico Debug Probe +3. OpenOCD installed and configured +4. GDB (`arm-none-eabi-gdb`) installed +5. Python installed (for UF2 conversion) +6. A serial monitor (PuTTY, minicom, or screen) +7. A 1602 LCD display with I2C backpack (PCF8574) +8. A hex editor (HxD, ImHex, or similar) +9. The sample project: `0x0017_constants` + +### Hardware Setup + +Connect your LCD like this: + +| LCD Pin | Pico 2 Pin | +| ------- | ---------- | +| VCC | 3.3V or 5V | +| GND | GND | +| SDA | GPIO 2 | +| SCL | GPIO 3 | + +``` ++-----------------------------------------------------------------+ +| I2C LCD Wiring | +| | +| Pico 2 1602 LCD + I2C Backpack | +| +----------+ +----------------------+ | +| | | | | | +| | GPIO 2 |------- SDA ----->| SDA | | +| | (SDA) | | | | +| | | | +------------+ | | +| | GPIO 3 |------- SCL ----->| SCL| Reverse | | | +| | (SCL) | | |Engineering | | | +| | | | +------------+ | | +| | 3.3V |------- VCC ----->| VCC | | +| | | | | | +| | GND |------- GND ----->| GND | | +| | | | | | +| +----------+ +----------------------+ | +| | ++-----------------------------------------------------------------+ +``` + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x0017_constants/ +| +-- build/ +| | +-- 0x0017_constants.uf2 +| | +-- 0x0017_constants.bin +| +-- 0x0017_constants.c +| +-- lcd_1602.h ++-- uf2conv.py +``` + +--- + +## Part 7: Hands-On Tutorial - Constants and I2C LCD + +### Step 1: Review the Source Code + +Let's examine the constants code: + +**File: `0x0017_constants.c`** + +```c +#include +#include +#include "pico/stdlib.h" +#include "hardware/i2c.h" +#include "lcd_1602.h" + +#define FAV_NUM 42 +#define I2C_PORT i2c1 +#define I2C_SDA_PIN 2 +#define I2C_SCL_PIN 3 + +const int OTHER_FAV_NUM = 1337; + +int main(void) { + stdio_init_all(); + + i2c_init(I2C_PORT, 100000); + gpio_set_function(I2C_SDA_PIN, GPIO_FUNC_I2C); + gpio_set_function(I2C_SCL_PIN, GPIO_FUNC_I2C); + gpio_pull_up(I2C_SDA_PIN); + gpio_pull_up(I2C_SCL_PIN); + + lcd_i2c_init(I2C_PORT, 0x27, 4, 0x08); + lcd_set_cursor(0, 0); + lcd_puts("Reverse"); + lcd_set_cursor(1, 0); + lcd_puts("Engineering"); + + while (true) { + printf("FAV_NUM: %d\r\n", FAV_NUM); + printf("OTHER_FAV_NUM: %d\r\n", OTHER_FAV_NUM); + } +} +``` + +**What this code does:** + +1. **Lines 7-10:** Define preprocessor macros for constants and I2C configuration +2. **Line 12:** Define a `const` variable stored in flash +3. **Line 15:** Initialize UART for serial output +4. **Lines 17-21:** Initialize I2C1 at 100kHz, configure GPIO pins, enable pull-ups +5. **Lines 23-27:** Initialize LCD and display "Reverse" on line 0, "Engineering" on line 1 +6. **Lines 29-32:** Infinite loop printing both constant values to serial terminal + +### Step 2: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x0017_constants.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 3: Verify It's Working + +**Check the LCD:** + +- Line 1 should show: `Reverse` +- Line 2 should show: `Engineering` + +**Check the serial monitor (PuTTY/screen):** +``` +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +... +``` + +--- + +## Part 8: Debugging with GDB (Dynamic Analysis) + +> **REVIEW:** This setup is identical to previous weeks. If you need a refresher on OpenOCD and GDB connection, refer back to Week 3 Part 6. + +### Starting the Debug Session + +**Terminal 1 - Start OpenOCD:** + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +**Terminal 2 - Start GDB:** + +```cmd +arm-none-eabi-gdb build\0x0017_constants.elf +``` + +**Connect to target:** + +```gdb +(gdb) target extended-remote :3333 +(gdb) monitor reset halt +``` + +### Step 4: Examine Main Function + +Let's examine the main function. Disassemble from the entry point: + +``` +x/54i 0x10000234 +``` + +You should see output like: + +``` +(gdb) x/54i 0x10000234 + 0x10000234
: push {r3, lr} + 0x10000236 : bl 0x100037fc + 0x1000023a : ldr r1, [pc, #104] @ (0x100002a4 ) + 0x1000023c : ldr r0, [pc, #104] @ (0x100002a8 ) + 0x1000023e : bl 0x10003cdc + 0x10000242 : movs r1, #3 + 0x10000244 : movs r0, #2 + 0x10000246 : bl 0x100008f0 + 0x1000024a : movs r1, #3 + 0x1000024c : mov r0, r1 + 0x1000024e : bl 0x100008f0 + 0x10000252 : movs r2, #0 + 0x10000254 : movs r1, #1 + 0x10000256 : movs r0, #2 + 0x10000258 : bl 0x1000092c + 0x1000025c : movs r2, #0 + 0x1000025e : movs r1, #1 + 0x10000260 : movs r0, #3 + 0x10000262 : bl 0x1000092c + 0x10000266 : movs r3, #8 + 0x10000268 : movs r2, #4 + 0x1000026a : movs r1, #39 @ 0x27 + 0x1000026c : ldr r0, [pc, #56] @ (0x100002a8 ) + 0x1000026e : bl 0x100002bc + 0x10000272 : movs r1, #0 + 0x10000274 : mov r0, r1 + 0x10000276 : bl 0x100006f4 + 0x1000027a : ldr r0, [pc, #48] @ (0x100002ac ) + 0x1000027c : bl 0x100007f0 + 0x10000280 : movs r0, #1 + 0x10000282 : movs r1, #0 + 0x10000284 : bl 0x100006f4 + 0x10000288 : ldr r0, [pc, #36] @ (0x100002b0 ) + 0x1000028a : bl 0x100007f0 + 0x1000028e : movs r1, #42 @ 0x2a + 0x10000290 : ldr r0, [pc, #32] @ (0x100002b4 ) + 0x10000292 : bl 0x1000398c <__wrap_printf> + 0x10000296 : movw r1, #1337 @ 0x539 + 0x1000029a : ldr r0, [pc, #28] @ (0x100002b8 ) + 0x1000029c : bl 0x1000398c <__wrap_printf> + 0x100002a0 : b.n 0x1000028e + 0x100002a2 : nop + 0x100002a4 : strh r0, [r4, #52] @ 0x34 + 0x100002a6 : movs r1, r0 + 0x100002a8 : lsls r4, r5, #24 + 0x100002aa : movs r0, #0 + 0x100002ac : subs r6, #232 @ 0xe8 + 0x100002ae : asrs r0, r0, #32 + 0x100002b0 : subs r6, #240 @ 0xf0 + 0x100002b2 : asrs r0, r0, #32 + 0x100002b4 : subs r6, #252 @ 0xfc + 0x100002b6 : asrs r0, r0, #32 + 0x100002b8 : subs r7, #12 + 0x100002ba : asrs r0, r0, #32 +``` + +### Step 5: Set a Breakpoint at Main + +``` +b *0x10000234 +c +``` + +### Step 6: Find the #define Constant (FAV_NUM) + +Step through to the printf call and examine the registers: + +``` +x/20i 0x1000028e +``` + +Look for: +``` +... + 0x1000028e : movs r1, #42 @ 0x2a +... +``` + +The `#define` constant is embedded directly as an immediate value in the instruction! + +### Step 7: Find the const Variable (OTHER_FAV_NUM) + +Continue examining the loop body: + +```gdb +(gdb) x/5i 0x10000296 +``` + +Look for this instruction: + +``` +... + 0x10000296 : movw r1, #1337 @ 0x539 +... +``` + +**Surprise!** The `const` variable is ALSO embedded as an immediate value - not loaded from memory! The compiler saw that `OTHER_FAV_NUM` is never address-taken (`&OTHER_FAV_NUM` is never used), so it optimized the `const` the same way as `#define` - as a constant embedded directly in the instruction. + +The difference is the instruction encoding: + +- `FAV_NUM` (42): `movs r1, #0x2a` - 16-bit Thumb instruction (values 0-255) +- `OTHER_FAV_NUM` (1337): `movw r1, #0x539` - 32-bit Thumb-2 instruction (values 0-65535) + +> Tip: **Why `movw` instead of `movs`?** The value 1337 doesn't fit in 8 bits (max 255), so the compiler uses `movw` (Move Wide) which can encode any 16-bit immediate (0-65535) in a 32-bit instruction. + +### Step 8: Examine the Literal Pool + +The literal pool after the loop contains addresses and constants that are too large for regular instruction immediates. Let's examine it: + +```gdb +(gdb) x/6wx 0x100002a4 +0x100002a4 : 0x000186a0 0x2000062c 0x10003ee8 0x10003ef0 +0x100002b4 : 0x10003efc 0x10003f0c +``` + +These are the values that `ldr rN, [pc, #offset]` instructions load: + +| Literal Pool Addr | Value | Used By | +| ----------------- | -------------- | ------------------------------ | +| `0x100002a4` | `0x000186A0` | I2C baudrate (100000) | +| `0x100002a8` | `0x2000062C` | &i2c1_inst (I2C struct in RAM) | +| `0x100002ac` | `0x10003EE8` | "Reverse" string address | +| `0x100002b0` | `0x10003EF0` | "Engineering" string address | +| `0x100002b4` | `0x10003EFC` | `"FAV_NUM: %d\r\n"` format str | +| `0x100002b8` | `0x10003F0C` | `"OTHER_FAV_NUM: %d\r\n"` fmt | + +> Tip: **Why does the disassembly at `0x100002a4` show `strh r0, [r4, #52]` instead of data?** Same reason as Week 6 - GDB's `x/i` tries to decode raw data as instructions. Use `x/wx` to see the actual word values or we can also use `x/x`. + +```gdb +(gdb) x/x 0x100002a4 +0x100002a4 : 0x000186a0 +(gdb) x/x 0x100002a8 +0x100002a8 : 0x2000062c +(gdb) x/x 0x100002ac +0x100002ac : 0x10003ee8 +(gdb) x/x 0x100002b0 +0x100002b0 : 0x10003ef0 +(gdb) x/x 0x100002b4 +0x100002b4 : 0x10003efc +(gdb) x/x 0x100002b8 +0x100002b8 : 0x10003f0c +``` + +### Step 9: Examine the I2C Struct + +Find the i2c1_inst struct address loaded into r0 before i2c_init: + +``` +x/2wx 0x2000062c +``` + +You should see: +``` +0x2000062c : 0x40098000 0x00000000 +``` + +### Step 10: Examine the LCD String Literals + +Find the strings passed to lcd_puts: + +``` +x/s 0x10003ee8 +``` + +Output: +``` +0x10003ee8: "Reverse" +``` + +``` +x/s 0x10003ef0 +``` + +Output: +``` +0x10003ef0: "Engineering" +``` + +### Step 11: Step Through I2C Initialization + +Step through instructions and watch the I2C setup: + +```gdb +(gdb) b *0x1000023e +(gdb) c +(gdb) i r r0 r1 +r0 0x2000062c 536872492 +r1 0x186a0 100000 +``` + +--- + +## Part 9: Understanding the Assembly + +Now that we've explored the binary in GDB, let's make sense of the key patterns we found. + +### Step 12: Analyze #define vs const in Assembly + +From GDB, we discovered something interesting - **both constants ended up as instruction immediates!** + +**For FAV_NUM (42) - a `#define` macro:** +``` +0x1000028e <+90>: movs r1, #42 @ 0x2a +``` + +The value 42 is embedded directly in a 16-bit Thumb instruction. This is expected - `#define` is text replacement, so the compiler never sees `FAV_NUM`, only `42`. + +**For OTHER_FAV_NUM (1337) - a `const` variable:** +``` +0x10000296 <+98>: movw r1, #1337 @ 0x539 +``` + +The value 1337 is ALSO embedded directly in an instruction - but this time a 32-bit Thumb-2 `movw` because the value doesn't fit in 8 bits. + +**Why wasn't `const` stored in memory?** In theory, `const int OTHER_FAV_NUM = 1337` creates a variable in the `.rodata` section. But the compiler optimized it away because: + +1. We never take the address of `OTHER_FAV_NUM` (no `&OTHER_FAV_NUM`) +2. The value fits in a 16-bit `movw` immediate +3. Loading from an immediate is faster than loading from memory + +> Tip: **Key takeaway for reverse engineering:** Don't assume `const` variables will appear as memory loads. Modern compilers aggressively inline constant values. The C keyword `const` is a **source-level** concept - the compiler may or may not honor it in the final binary. + +### Step 13: Analyze the I2C Struct Layout + +In GDB, we examined the `i2c1_inst` struct at `0x2000062c`: + +```gdb +(gdb) x/2wx 0x2000062c +0x2000062c : 0x40098000 0x00000000 +``` + +This maps to the `i2c_inst_t` struct: + +``` ++-----------------------------------------------------------------+ +| i2c_inst_t at 0x2000062c | +| | +| +------------------------------------------------------------+ | +| | Offset Type Name Value | | +| | 0x00 i2c_hw_t * hw 0x40098000 | | +| | 0x04 bool restart_on_next 0x00 (false) | | +| +------------------------------------------------------------+ | +| | ++-----------------------------------------------------------------+ +``` + +The first member (`hw`) points to `0x40098000` - the I2C1 hardware register base. This is the end of the macro chain: `I2C_PORT` -> `i2c1` -> `&i2c1_inst` -> `hw` -> `0x40098000`. + +### Step 14: Locate the String Literals + +We found the LCD strings in flash memory: + +```gdb +(gdb) x/s 0x10003ee8 +0x10003ee8: "Reverse" + +(gdb) x/s 0x10003ef0 +0x10003ef0: "Engineering" +``` + +These are stored consecutively in the `.rodata` section. Note the addresses - we'll need them for patching. + +--- + +## Part 10: Hacking the Binary with a Hex Editor + +Now for the fun part - we'll patch the `.bin` file directly using a hex editor! + +> Tip: **Why a hex editor?** GDB **cannot write to flash memory** - the `0x10000000+` address range where program instructions and read-only data live. Trying `set *(char *)0x1000028e = 0x2b` in GDB gives `Writing to flash memory forbidden in this context`. To make **permanent** patches that survive a power cycle, we edit the `.bin` file directly with a hex editor and re-flash it. + +### Step 15: Open the Binary in a Hex Editor + +1. Open **HxD** (or your preferred hex editor: ImHex, 010 Editor, etc.) +2. Click **File** -> **Open** +3. Navigate to `C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0017_constants\build\` +4. Open `0x0017_constants.bin` + +### Step 16: Calculate the File Offset + +The binary is loaded at base address `0x10000000`. To find the file offset of any address: + +``` +file_offset = address - 0x10000000 +``` + +For example: + +- Address `0x1000028e` -> file offset `0x28E` (654 in decimal) +- Address `0x10003ee8` -> file offset `0x3EE8` (16104 in decimal) + +### Step 17: Understand FAV_NUM Encoding (movs - 16-bit Thumb) + +From our GDB analysis, we know the instruction at `0x1000028e` is: + +``` +movs r1, #0x2a -> bytes: 2a 21 +``` + +In HxD, use **Ctrl+G** to navigate to file offset `28E` and verify you see the byte `2A` followed by `21`. + +> **How Thumb encoding works:** In `movs r1, #imm8`, the immediate value is the first byte, and the opcode `21` is the second byte. So the bytes `2a 21` encode `movs r1, #0x2a` (42). If you wanted to change this to 43, you'd change `2A` to `2B`. + +### Step 18: Understand OTHER_FAV_NUM Encoding (movw - 32-bit Thumb-2) + +From GDB, we found the `movw r1, #1337` instruction at `0x10000296`. Examine the exact bytes: + +```gdb +(gdb) x/4bx 0x10000296 +0x10000296 : 0x40 0xf2 0x39 0x51 +``` + +This is the 32-bit Thumb-2 encoding of `movw r1, #0x539` (1337). The bytes break down as: + +``` ++-----------------------------------------------------------------+ +| movw r1, #0x539 -> bytes: 40 F2 39 51 | +| | +| Byte 0: 0x40 -+ | +| Byte 1: 0xF2 -+ First halfword (opcode + upper imm bits) | +| Byte 2: 0x39 ---- Lower 8 bits of immediate (imm8) <- CHANGE | +| Byte 3: 0x51 ---- Destination register (r1) + upper imm bits | +| | +| imm16 = 0x0539 = 1337 decimal | +| imm8 field = 0x39 (lower 8 bits of the value) | +| | ++-----------------------------------------------------------------+ +``` + +The file offset is `0x10000296 - 0x10000000 = 0x296`. The imm8 byte is the 3rd byte of the instruction: `0x296 + 2 = 0x298`. + +To change `movw r1, #1337` to `movw r1, #1344`: + +1. In HxD, press **Ctrl+G** (Go to offset) +2. Enter offset: `298` (the third byte of the 4-byte instruction) +3. You should see the byte `39` at this position +4. Change `39` to `40` + +> **Why offset `0x298` and not `0x296`?** The lower 8 bits of the immediate (`imm8`) are in the **third byte** of the 4-byte `movw` instruction. The instruction starts at file offset `0x296`, so imm8 is at `0x296 + 2 = 0x298`. Changing `0x39` to `0x40` changes the value from `0x539` (1337) to `0x540` (1344). + +### Step 19: Hack - Change LCD Text from "Reverse" to "Exploit" + +**IMPORTANT:** The new string must be the **same length** as the original! "Reverse" and "Exploit" are both 7 characters - perfect! + +From our GDB analysis in Step 10, we found the string at `0x10003ee8`. File offset = `0x10003ee8 - 0x10000000 = 0x3EE8`. + +1. In HxD, press **Ctrl+G** and enter offset: `3EE8` +2. You should see the bytes for "Reverse": `52 65 76 65 72 73 65 00` +3. Change the bytes to spell "Exploit": `45 78 70 6c 6f 69 74 00` + +**ASCII Reference:** + +| Character | Hex | +| --------- | ------ | +| E | `0x45` | +| x | `0x78` | +| p | `0x70` | +| l | `0x6c` | +| o | `0x6f` | +| i | `0x69` | +| t | `0x74` | + +### Step 20: Save the Patched Binary + +1. Click **File** -> **Save As** +2. Save as `0x0017_constants-h.bin` in the build directory +3. Close the hex editor + +--- + +## Part 11: Converting and Flashing the Hacked Binary + +### Step 21: Convert to UF2 Format + +Open a terminal and navigate to your project directory: + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0017_constants +``` + +Run the conversion command: + +```cmd +python ..\uf2conv.py build\0x0017_constants-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 22: Flash the Hacked Binary + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Check your LCD and serial monitor + +### Step 23: Verify the Hack + +**Check the LCD:** + +- Line 1 should now show: `Exploit` (instead of "Reverse") +- Line 2 should still show: `Engineering` + +**Check the serial monitor:** +``` +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 +... +``` + +The numbers are unchanged - we only patched the LCD string! + + **BOOM! We successfully changed the LCD text from "Reverse" to "Exploit" without access to the source code!** + +--- + +## Part 12: Summary and Review + +### What We Accomplished + +1. **Learned about constants** - `#define` macros vs `const` variables +2. **Understood I2C communication** - Two-wire protocol for peripheral communication +3. **Explored C structs** - How the Pico SDK abstracts hardware +4. **Mastered the macro chain** - From `I2C_PORT` to `0x40098000` +5. **Examined structs in GDB** - Inspected memory layout of `i2c_inst_t` +6. **Analyzed instruction encodings** - Both `movs` (8-bit) and `movw` (16-bit) immediates in the hex editor +7. **Patched a string literal** - Changed LCD display text from "Reverse" to "Exploit" + +### #define vs const Summary + +``` ++-----------------------------------------------------------------+ +| #define FAV_NUM 42 | +| ------------------- | +| - Text replacement at compile time | +| - No memory allocated | +| - Cannot take address (&FAV_NUM is invalid) | +| - In binary: value appears as immediate (movs r1, #0x2a) | +| - To hack: patch the instruction operand | ++-----------------------------------------------------------------+ +| const int OTHER_FAV_NUM = 1337 | +| ------------------------------ | +| - Theoretically in .rodata, but compiler optimized it away | +| - Value embedded as immediate: movw r1, #0x539 (32-bit instr) | +| - Optimization: compiler saw &OTHER_FAV_NUM is never used | +| - In binary: immediate in instruction, same as #define! | +| - To hack: patch instruction operand (imm8 byte at offset +2) | ++-----------------------------------------------------------------+ +``` + +### I2C Configuration Summary + +``` ++-----------------------------------------------------------------+ +| I2C Setup Steps | +| | +| 1. i2c_init(i2c1, 100000) - Initialize at 100kHz | +| 2. gpio_set_function(pin, I2C) - Assign pins to I2C | +| 3. gpio_pull_up(sda_pin) - Enable SDA pull-up | +| 4. gpio_pull_up(scl_pin) - Enable SCL pull-up | +| 5. lcd_i2c_init(...) - Initialize the device | +| | ++-----------------------------------------------------------------+ +``` + +### The Struct Chain + +``` ++-----------------------------------------------------------------+ +| I2C_PORT -> i2c1 -> &i2c1_inst -> i2c_inst_t | +| | | +| +-- hw -> i2c_hw_t * | +| | +-- 0x40098000 | +| | | +| +-- restart_on_next (bool) | +| | ++-----------------------------------------------------------------+ +``` + +### Key Memory Addresses + +| Address | Description | +| ------------ | ---------------------------------- | +| `0x10000234` | main() entry point | +| `0x1000028e` | FAV_NUM value in instruction | +| `0x10000296` | OTHER_FAV_NUM value in instruction | +| `0x10003ee8` | "Reverse" string literal (example) | +| `0x40098000` | I2C1 hardware registers base | +| `0x2000062C` | i2c1_inst struct in SRAM | + +--- + +--- + +## Key Takeaways + +1. **#define is text replacement** - It happens before compilation, no memory used. + +2. **const creates real variables** - Stored in .rodata, takes memory, has an address. + +3. **I2C uses two wires** - SDA for data, SCL for clock, pull-ups required. + +4. **Structs group related data** - The SDK uses them to abstract hardware. + +5. **Macros can chain** - `I2C_PORT` -> `i2c1` -> `&i2c1_inst` -> hardware pointer. + +6. **ARM passes args in registers** - r0-r3 for first four arguments. + +7. **GDB reveals struct layouts** - Examine memory to understand data organization. + +8. **String hacking requires same length** - Or you'll corrupt adjacent data! + +9. **Constants aren't constant** - With binary patching, everything can change! + +10. **Compiler optimization changes code** - `gpio_pull_up` becomes `gpio_set_pulls`. + +--- + +## Glossary + +| Term | Definition | +| ----------------------- | --------------------------------------------------- | +| **#define** | Preprocessor directive for text replacement | +| **AAPCS** | ARM Architecture Procedure Call Standard | +| **const** | Keyword marking a variable as read-only | +| **Forward Declaration** | Telling compiler a type exists before defining it | +| **I2C** | Inter-Integrated Circuit - two-wire serial protocol | +| **Immediate Value** | A constant embedded directly in an instruction | +| **Open-Drain** | Output that can only pull low, not drive high | +| **PCF8574** | Common I2C I/O expander chip used in LCD backpacks | +| **Preprocessor** | Tool that processes code before compilation | +| **Pull-Up Resistor** | Resistor that holds a line HIGH by default | +| **SCL** | Serial Clock - I2C timing signal | +| **SDA** | Serial Data - I2C data line | +| **Struct** | User-defined type grouping related variables | +| **typedef** | Creates an alias for a type | + +--- + +## Additional Resources + +### I2C Timing Reference + +| Speed Mode | Maximum Frequency | +| ---------- | ----------------- | +| Standard | 100 kHz | +| Fast | 400 kHz | +| Fast Plus | 1 MHz | + +### Common I2C Addresses + +| Device | Address | +| --------------------- | ------------- | +| PCF8574 LCD (default) | `0x27` | +| PCF8574A LCD | `0x3F` | +| DS3231 RTC | `0x68` | +| BMP280 Sensor | `0x76`/`0x77` | +| SSD1306 OLED | `0x3C`/`0x3D` | + +### Key ARM Instructions for Constants + +| Instruction | Description | +| -------------------- | ------------------------------------------- | +| `movs rN, #imm` | Load small immediate (0-255) directly | +| `ldr rN, [pc, #off]` | Load larger value from literal pool | +| `ldr rN, =value` | Pseudo-instruction for loading any constant | + +### RP2350 I2C Memory Map + +| Address | Description | +| ------------ | ----------------------- | +| `0x40090000` | I2C0 hardware registers | +| `0x40098000` | I2C1 hardware registers | + +--- + +**Remember:** When you see complex nested structures in a binary, take your time to understand the hierarchy. Use GDB to examine struct layouts in memory and trace pointer chains. And always remember - even "constants" can be hacked! + +Happy hacking! \ No newline at end of file diff --git a/WEEK07/WEEK07.pdf b/WEEK07/WEEK07.pdf new file mode 100644 index 0000000..20f5df3 Binary files /dev/null and b/WEEK07/WEEK07.pdf differ diff --git a/WEEK07/slides/WEEK07-IMG00.svg b/WEEK07/slides/WEEK07-IMG00.svg new file mode 100644 index 0000000..427c6f7 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 07 + + +Constants in Embedded Systems: +Debugging and Hacking Constants +w/ 1602 LCD I2C Basics + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK07/slides/WEEK07-IMG01.svg b/WEEK07/slides/WEEK07-IMG01.svg new file mode 100644 index 0000000..bbe54c4 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG01.svg @@ -0,0 +1,63 @@ + + + + +#define vs const +Preprocessor Macros vs Constant Variables + + + +#define FAV_NUM 42 + +Preprocessor text replacement +Happens BEFORE compilation +No memory allocated +Cannot take address (&) + +In Binary: + +movs r1, #42 @ 0x2a + +16-bit Thumb instruction +Value embedded as immediate +Compiler sees only "42" + + + +const int OTHER_FAV_NUM=1337 + +Creates real variable +Theoretically in .rodata +Has an address (if needed) +Type-checked by compiler + +In Binary: + +movw r1, #1337 @ 0x539 + +32-bit Thumb-2 instruction +Also embedded as immediate! +Compiler optimized it away + + + +KEY INSIGHT: +Both ended up as instruction immediates! +The compiler saw &OTHER_FAV_NUM is never used, so it +optimized const the same way as #define -- no memory load needed. +Lesson: const is a source-level concept -- not guaranteed in binary + + + + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG02.svg b/WEEK07/slides/WEEK07-IMG02.svg new file mode 100644 index 0000000..d798cd5 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG02.svg @@ -0,0 +1,85 @@ + + + + +I2C Protocol +Two-Wire Serial Communication + + + +What is I2C? +Two-wire serial protocol +SDA += Serial Data +SCL += Serial Clock +Open-drain with pull-up resistors + + + +I2C Bus + +Pico + + +SDA +SCL + +LCD +GPIO 2 = SDA, GPIO 3 = SCL +Pull-ups hold lines HIGH + + + +Common I2C Addresses (7-bit) + +0x27 +LCD + +0x3F +LCD Alt + +0x48 +Sensor + +0x50 +EEPROM + + + +I2C Transaction Flow + +START +--> + +Address +--> + +ACK +--> + +Data +--> + +ACK +--> + +STOP + +Master sends START, then 7-bit address + R/W bit +Slave responds with ACK, then data bytes follow + + + + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG03.svg b/WEEK07/slides/WEEK07-IMG03.svg new file mode 100644 index 0000000..d69b142 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG03.svg @@ -0,0 +1,66 @@ + + + + +C Structs & typedef +Grouping Related Data in C + + + +Struct Definition + +typedef struct { +i2c_hw_t *hw; +bool restart_on_next; +} i2c_inst_t; +typedef creates an alias +so we can write: i2c_inst_t var; +instead of: struct { ... } var; + + + +Memory Layout +i2c_inst_t at 0x2000062C + + +Offset 0x00 +hw += 0x40098000 +i2c_hw_t* (4 bytes) + + +Offset 0x04 +restart_on_next += 0x00 (false) +bool (1 byte) + +Total struct size: 8 bytes +hw points to I2C1 registers + + + +Forward Declaration + +struct i2c_inst; +// tells compiler: this type exists, define later + + + +Why Structs Matter in RE +GDB shows raw memory -- you must recognize struct layouts +x/2wx 0x2000062c shows: 0x40098000 0x00000000 + + + + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG04.svg b/WEEK07/slides/WEEK07-IMG04.svg new file mode 100644 index 0000000..927fd8c --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG04.svg @@ -0,0 +1,80 @@ + + + + +Pico SDK Macro Chain +From I2C_PORT to Hardware Registers + + + +Macro Expansion Chain + + + +I2C_PORT +#define I2C_PORT i2c1 + + +--> + + + +i2c1 +#define i2c1 (&i2c1_inst) + + +--> + + + +&i2c1_inst +Address of global struct + + +Struct Contents at 0x2000062C + +i2c_inst_t i2c1_inst = { +.hw = (i2c_hw_t *)0x40098000, +.restart_on_next = false +}; + + +Hardware Register Access + + +i2c1_inst.hw +--> +i2c1_hw +--> +(i2c_hw_t*)0x40098000 + +I2C1_BASE = 0x40098000 +I2C0_BASE = 0x40090000 +Direct memory-mapped I/O to RP2350 peripheral + + + +FULL CHAIN: +I2C_PORT +--> +i2c1 +--> +&i2c1_inst +--> +0x40098000 +Macro --> Macro --> Struct pointer --> HW register base + + + + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG05.svg b/WEEK07/slides/WEEK07-IMG05.svg new file mode 100644 index 0000000..de2e153 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG05.svg @@ -0,0 +1,53 @@ + + + + +Source Code +0x0017_constants.c + + + + + +//--- Defines and Constants --- +#define FAV_NUM 42 +#define I2C_PORT i2c1 +#define I2C_SDA_PIN 2 +#define I2C_SCL_PIN 3 +const int OTHER_FAV_NUM = 1337; + +//--- Main Loop --- +lcd_set_cursor(0, 0); +lcd_puts("Reverse"); +lcd_set_cursor(1, 0); +lcd_puts("Engineering"); + +//--- Serial Output Loop --- +printf("FAV_NUM: %d\r\n", FAV_NUM); +printf("OTHER_FAV_NUM: %d\r\n", OTHER_FAV_NUM); + + + +LCD Output +Line 0: "Reverse" +Line 1: "Engineering" + + +Serial Output +FAV_NUM: 42 +OTHER_FAV_NUM: 1337 + + + + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG06.svg b/WEEK07/slides/WEEK07-IMG06.svg new file mode 100644 index 0000000..738b366 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG06.svg @@ -0,0 +1,65 @@ + + + + +GDB Analysis +Disassembly of main() at 0x10000234 + + + +Key Instructions from x/54i 0x10000234 + + +push {r3, lr} +// save return addr +bl stdio_init_all +// init serial +ldr r1, [pc, #104] +// r1 = 100000 (baud) +ldr r0, [pc, #104] +// r0 = &i2c1_inst +bl i2c_init +// init I2C at 100kHz +movs r0, #2 +// GPIO 2 (SDA) +bl gpio_set_function +// set pin to I2C +movs r1, #39 +// 0x27 = LCD addr +bl lcd_i2c_init +// init LCD device + +b.n 0x1000028e +// infinite loop start +... +AAPCS: r0-r3 = first 4 args, r0 = return value + + + +Literal Pool at 0x100002A4 + + +0x000186A0 +I2C baudrate (100000) +0x2000062C +&i2c1_inst struct in RAM +0x10003EE8 +"Reverse" string in flash +0x10003EF0 +"Engineering" string in flash +0x10003EFC +"FAV_NUM: %d\r\n" +0x10003F0C +"OTHER_FAV_NUM: %d\r\n" + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG07.svg b/WEEK07/slides/WEEK07-IMG07.svg new file mode 100644 index 0000000..15a1e54 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG07.svg @@ -0,0 +1,71 @@ + + + + +Instruction Encoding +movs (16-bit Thumb) vs movw (32-bit Thumb-2) + + + +movs r1, #42 (FAV_NUM) +At address 0x1000028E + + +Bytes: 2A 21 + +2A = immediate value (42) +21 = opcode (movs r1) +16-bit Thumb instruction +Fits values 0-255 in 8 bits +File offset: 0x28E + + + +movw r1, #1337 (OTHER_FAV) +At address 0x10000296 + + +Bytes: 40 F2 39 51 + +40 F2 = opcode (first halfword) +39 = imm8 (lower 8 bits) +51 = dest reg + upper imm +32-bit Thumb-2 instruction +File offset: 0x296 + + + +movw Byte Layout (40 F2 39 51) + + +40 F2 +Opcode + upper imm + + +39 +imm8 (lower 8 bits) + + +51 +Dest reg (r1) + bits + +imm16 = 0x539 += 1337 decimal + + + +Why movw instead of movs? +1337 > 255 -- does not fit in 8-bit movs immediate +movw encodes 0-65535 in 32-bit instruction + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG08.svg b/WEEK07/slides/WEEK07-IMG08.svg new file mode 100644 index 0000000..9f8ea92 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG08.svg @@ -0,0 +1,68 @@ + + + + +I2C Struct in Memory +Examining i2c1_inst at 0x2000062C + + + +GDB Memory Dump + +x/2wx 0x2000062c: +0x40098000 +0x00000000 + + + +i2c_inst_t Struct Layout + + + +Offset 0x00 | 4 bytes +i2c_hw_t *hw += 0x40098000 + + +--> + + + +I2C1 HW Registers +Base: 0x40098000 (MMIO) + + + +Offset 0x04 | 1 byte +bool restart_on_next += false + +I2C0 base = 0x40090000 +I2C1 base = 0x40098000 + + + +String Literals in Flash (.rodata) + + +x/s 0x10003ee8: +"Reverse" + + +x/s 0x10003ef0: +"Engineering" + +Stored consecutively in .rodata (flash) +These addresses are targets for patching + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG09.svg b/WEEK07/slides/WEEK07-IMG09.svg new file mode 100644 index 0000000..5934306 --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG09.svg @@ -0,0 +1,63 @@ + + + + +Hacking the Binary +Patching LCD Text: "Reverse" --> "Exploit" + + + +File Offset Formula +file_offset = address - 0x10000000 +Binary loaded at 0x10000000 + + + +Hack: Change LCD String +Address 0x10003EE8 --> File offset 0x3EE8 + +Original: + +52 65 76 65 72 73 65 00 +"Reverse" + +Patched: + +45 78 70 6C 6F 69 74 00 +"Exploit" + +Same length (7 chars) -- null terminator stays + + + +Flash the Hacked Binary + + +python uf2conv.py build\patched.bin + +1. +Save patched .bin file +2. +Convert to .uf2 format +3. +Hold BOOTSEL, plug in Pico +4. +Drag hacked.uf2 to drive + + + +LCD now shows: "Exploit" +instead of "Reverse" +No source code needed! + \ No newline at end of file diff --git a/WEEK07/slides/WEEK07-IMG10.svg b/WEEK07/slides/WEEK07-IMG10.svg new file mode 100644 index 0000000..3fda6dc --- /dev/null +++ b/WEEK07/slides/WEEK07-IMG10.svg @@ -0,0 +1,88 @@ + + + + +I2C & Macro Exploitation +Constants, I2C, Structs, and Hacking + + + +Key Concepts + +#define +Text replacement, no memory +const +Variable in .rodata (maybe) +I2C +Two-wire: SDA + SCL +struct +Groups related data fields +typedef +Creates type alias +AAPCS +r0-r3 args, r0 return +movs +16-bit, imm 0-255 +movw +32-bit, imm 0-65535 +Literal Pool +Large consts after code + + + +Key Addresses + +0x10000234 +main() entry +0x1000028E +FAV_NUM (movs) +0x10000296 +OTHER_FAV_NUM (movw) +0x10003EE8 +"Reverse" string +0x10003EF0 +"Engineering" string +0x40098000 +I2C1 HW base +0x2000062C +i2c1_inst struct + +file_offset = addr - 0x10000000 +String patches must be same length + + + +Macro Chain +I2C_PORT +--> +i2c1 +--> +&i2c1_inst +--> +0x40098000 + + + +Binary Hack Result +LCD: "Reverse" --> +"Exploit" +Patched at 0x3EE8 +Compiler may optimize const same as #define + + + +TAKEAWAY: +const is a source-level concept. +In binary, everything can change! + \ No newline at end of file diff --git a/WEEK09/0x001a_operators/.gitignore b/WEEK09/0x001a_operators/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK09/0x001a_operators/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK09/0x001a_operators/.vscode/c_cpp_properties.json b/WEEK09/0x001a_operators/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK09/0x001a_operators/.vscode/cmake-kits.json b/WEEK09/0x001a_operators/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK09/0x001a_operators/.vscode/extensions.json b/WEEK09/0x001a_operators/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK09/0x001a_operators/.vscode/launch.json b/WEEK09/0x001a_operators/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK09/0x001a_operators/.vscode/settings.json b/WEEK09/0x001a_operators/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK09/0x001a_operators/.vscode/tasks.json b/WEEK09/0x001a_operators/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK09/0x001a_operators/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK09/0x001a_operators/0x001a_operators.c b/WEEK09/0x001a_operators/0x001a_operators.c new file mode 100644 index 0000000..d9ddccf --- /dev/null +++ b/WEEK09/0x001a_operators/0x001a_operators.c @@ -0,0 +1,36 @@ +#include +#include "pico/stdlib.h" +#include "dht11.h" + +int main(void) { + stdio_init_all(); + + dht11_init(4); + + int x = 5; + int y = 10; + int arithmetic_operator = (x * y); + int increment_operator = x++; + bool relational_operator = (x > y); + bool logical_operator = (x > y) && (y > x); + int bitwise_operator = (x<<1); // x is now 6 because of x++ or 0b00000110 and (x<<1) is 0b00001100 or 12 + int assignment_operator = (x += 5); + + while (true) { + printf("arithmetic_operator: %d\r\n", arithmetic_operator); + printf("increment_operator: %d\r\n", increment_operator); + printf("relational_operator: %d\r\n", relational_operator); + printf("logical_operator: %d\r\n", logical_operator); + printf("bitwise_operator: %d\r\n", bitwise_operator); + printf("assignment_operator: %d\r\n", assignment_operator); + + float hum, temp; + if (dht11_read(&hum, &temp)) { + printf("Humidity: %.1f%%, Temperature: %.1f°C\r\n", hum, temp); + } else { + printf("DHT11 read failed\r\n"); + } + + sleep_ms(2000); + } +} \ No newline at end of file diff --git a/WEEK09/0x001a_operators/CMakeLists.txt b/WEEK09/0x001a_operators/CMakeLists.txt new file mode 100644 index 0000000..f6ef427 --- /dev/null +++ b/WEEK09/0x001a_operators/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x001a_operators C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x001a_operators 0x001a_operators.c dht11.c ) + +pico_set_program_name(0x001a_operators "0x001a_operators") +pico_set_program_version(0x001a_operators "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x001a_operators 1) +pico_enable_stdio_usb(0x001a_operators 0) + +# Add the standard library to the build +target_link_libraries(0x001a_operators + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x001a_operators PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x001a_operators) + diff --git a/WEEK09/0x001a_operators/build/0x001a_operators.bin b/WEEK09/0x001a_operators/build/0x001a_operators.bin new file mode 100755 index 0000000..6e3ca84 Binary files /dev/null and b/WEEK09/0x001a_operators/build/0x001a_operators.bin differ diff --git a/WEEK09/0x001a_operators/build/0x001a_operators.dis b/WEEK09/0x001a_operators/build/0x001a_operators.dis new file mode 100644 index 0000000..566a2b3 --- /dev/null +++ b/WEEK09/0x001a_operators/build/0x001a_operators.dis @@ -0,0 +1,6441 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x001a_operators/build/0x001a_operators.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000038e4 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000288 100038e8 100038e8 000048e8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003b70 10003b70 00004b70 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003b78 10003b78 00004b78 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00007000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 0000644c 2**0 + CONTENTS + 6 .data 00000894 20000110 10003ba4 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 200009a4 200009a4 0000644c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 200009a4 200009a4 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 0000022c 200009a8 10004438 000069a8 2**3 + ALLOC + 10 .heap 00000800 20000bd4 10004438 00006bd4 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 0000644c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 0000644c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00007000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10004438 10004438 00006438 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 0000644c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00006480 2**0 + CONTENTS, READONLY + 17 .debug_info 000218be 00000000 00000000 000064c5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005a04 00000000 00000000 00027d83 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 00010317 00000000 00000000 0002d787 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000c10 00000000 00000000 0003daa0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 0000312b 00000000 00000000 0003e6b0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000161c2 00000000 00000000 000417db 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005ade 00000000 00000000 0005799d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00002048 00000000 00000000 0005d47c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c4 00000000 00000000 0005f4c4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x001a_operators/build/0x001a_operators.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003b78 .word 0x10003b78 +1000012c: 10003ba4 .word 0x10003ba4 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00004300 .word 0x00004300 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10003ba4 .word 0x10003ba4 +100001a4: 20000110 .word 0x20000110 +100001a8: 200009a4 .word 0x200009a4 +100001ac: 10004438 .word 0x10004438 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10004438 .word 0x10004438 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 200009a4 .word 0x200009a4 +100001d4: 20000bd4 .word 0x20000bd4 +100001d8: 10003145 .word 0x10003145 +100001dc: 10000235 .word 0x10000235 +100001e0: 1000313d .word 0x1000313d + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 200009a4 .word 0x200009a4 +10000208: 200009a4 .word 0x200009a4 +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000b8c .word 0x20000b8c +10000230: 100038e4 .word 0x100038e4 + +10000234
: +10000234: b580 push {r7, lr} +10000236: b084 sub sp, #16 +10000238: f003 f8ac bl 10003394 +1000023c: 2004 movs r0, #4 +1000023e: f000 f849 bl 100002d4 +10000242: e014 b.n 1000026e +10000244: 9802 ldr r0, [sp, #8] +10000246: f003 fb1b bl 10003880 <____aeabi_f2d_veneer> +1000024a: 4604 mov r4, r0 +1000024c: 9803 ldr r0, [sp, #12] +1000024e: 460d mov r5, r1 +10000250: f003 fb16 bl 10003880 <____aeabi_f2d_veneer> +10000254: 4606 mov r6, r0 +10000256: 460f mov r7, r1 +10000258: 4622 mov r2, r4 +1000025a: 462b mov r3, r5 +1000025c: e9cd 6700 strd r6, r7, [sp] +10000260: 4814 ldr r0, [pc, #80] @ (100002b4 ) +10000262: f003 f95f bl 10003524 <__wrap_printf> +10000266: f44f 60fa mov.w r0, #2000 @ 0x7d0 +1000026a: f000 feb5 bl 10000fd8 +1000026e: 2132 movs r1, #50 @ 0x32 +10000270: 4811 ldr r0, [pc, #68] @ (100002b8 ) +10000272: f003 f957 bl 10003524 <__wrap_printf> +10000276: 2105 movs r1, #5 +10000278: 4810 ldr r0, [pc, #64] @ (100002bc ) +1000027a: f003 f953 bl 10003524 <__wrap_printf> +1000027e: 2100 movs r1, #0 +10000280: 480f ldr r0, [pc, #60] @ (100002c0 ) +10000282: f003 f94f bl 10003524 <__wrap_printf> +10000286: 2100 movs r1, #0 +10000288: 480e ldr r0, [pc, #56] @ (100002c4 ) +1000028a: f003 f94b bl 10003524 <__wrap_printf> +1000028e: 210a movs r1, #10 +10000290: 480d ldr r0, [pc, #52] @ (100002c8 ) +10000292: f003 f947 bl 10003524 <__wrap_printf> +10000296: 210a movs r1, #10 +10000298: 480c ldr r0, [pc, #48] @ (100002cc ) +1000029a: f003 f943 bl 10003524 <__wrap_printf> +1000029e: a903 add r1, sp, #12 +100002a0: a802 add r0, sp, #8 +100002a2: f000 f827 bl 100002f4 +100002a6: 4603 mov r3, r0 +100002a8: 4809 ldr r0, [pc, #36] @ (100002d0 ) +100002aa: 2b00 cmp r3, #0 +100002ac: d1ca bne.n 10000244 +100002ae: f003 f8b9 bl 10003424 <__wrap_puts> +100002b2: e7d8 b.n 10000266 +100002b4: 10003988 .word 0x10003988 +100002b8: 100038e8 .word 0x100038e8 +100002bc: 10003904 .word 0x10003904 +100002c0: 10003920 .word 0x10003920 +100002c4: 1000393c .word 0x1000393c +100002c8: 10003954 .word 0x10003954 +100002cc: 1000396c .word 0x1000396c +100002d0: 100039b4 .word 0x100039b4 + +100002d4 : +100002d4: b510 push {r4, lr} +100002d6: 4604 mov r4, r0 +100002d8: 4b05 ldr r3, [pc, #20] @ (100002f0 ) +100002da: 6018 str r0, [r3, #0] +100002dc: f000 f8e2 bl 100004a4 +100002e0: 4620 mov r0, r4 +100002e2: e8bd 4010 ldmia.w sp!, {r4, lr} +100002e6: 2200 movs r2, #0 +100002e8: 2101 movs r1, #1 +100002ea: f000 b8c7 b.w 1000047c +100002ee: bf00 nop +100002f0: 20000b7c .word 0x20000b7c + +100002f4 : +100002f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100002f8: 2700 movs r7, #0 +100002fa: f8df 8140 ldr.w r8, [pc, #320] @ 1000043c +100002fe: b083 sub sp, #12 +10000300: 466e mov r6, sp +10000302: f04f 0901 mov.w r9, #1 +10000306: 4605 mov r5, r0 +10000308: 468b mov fp, r1 +1000030a: f8d8 2000 ldr.w r2, [r8] +1000030e: 9700 str r7, [sp, #0] +10000310: f88d 7004 strb.w r7, [sp, #4] +10000314: ec49 2044 gpioc_bit_oe_put r2, r9 +10000318: ec47 2040 gpioc_bit_out_put r2, r7 +1000031c: 2012 movs r0, #18 +1000031e: f000 fe5b bl 10000fd8 +10000322: f8d8 3000 ldr.w r3, [r8] +10000326: ec49 3040 gpioc_bit_out_put r3, r9 +1000032a: 2028 movs r0, #40 @ 0x28 +1000032c: 2100 movs r1, #0 +1000032e: f000 fde7 bl 10000f00 +10000332: f8d8 3000 ldr.w r3, [r8] +10000336: ec47 3044 gpioc_bit_oe_put r3, r7 +1000033a: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +1000033e: fa09 fc03 lsl.w ip, r9, r3 +10000342: f242 7310 movw r3, #10000 @ 0x2710 +10000346: e001 b.n 1000034c +10000348: 3b01 subs r3, #1 +1000034a: d06e beq.n 1000042a +1000034c: 684a ldr r2, [r1, #4] +1000034e: ea12 0f0c tst.w r2, ip +10000352: d1f9 bne.n 10000348 +10000354: f242 7310 movw r3, #10000 @ 0x2710 +10000358: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +1000035c: e001 b.n 10000362 +1000035e: 3b01 subs r3, #1 +10000360: d063 beq.n 1000042a +10000362: 684a ldr r2, [r1, #4] +10000364: ea1c 0f02 tst.w ip, r2 +10000368: d0f9 beq.n 1000035e +1000036a: f242 7310 movw r3, #10000 @ 0x2710 +1000036e: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +10000372: e001 b.n 10000378 +10000374: 3b01 subs r3, #1 +10000376: d058 beq.n 1000042a +10000378: 6851 ldr r1, [r2, #4] +1000037a: ea1c 0101 ands.w r1, ip, r1 +1000037e: d1f9 bne.n 10000374 +10000380: f04f 4e50 mov.w lr, #3489660928 @ 0xd0000000 +10000384: 482b ldr r0, [pc, #172] @ (10000434 ) +10000386: f242 7310 movw r3, #10000 @ 0x2710 +1000038a: e001 b.n 10000390 +1000038c: 3b01 subs r3, #1 +1000038e: d04c beq.n 1000042a +10000390: f8de 2004 ldr.w r2, [lr, #4] +10000394: ea1c 0f02 tst.w ip, r2 +10000398: d0f8 beq.n 1000038c +1000039a: f242 7310 movw r3, #10000 @ 0x2710 +1000039e: 6a84 ldr r4, [r0, #40] @ 0x28 +100003a0: e001 b.n 100003a6 +100003a2: 3b01 subs r3, #1 +100003a4: d041 beq.n 1000042a +100003a6: f8de 2004 ldr.w r2, [lr, #4] +100003aa: ea1c 0f02 tst.w ip, r2 +100003ae: d1f8 bne.n 100003a2 +100003b0: 10ca asrs r2, r1, #3 +100003b2: 6a87 ldr r7, [r0, #40] @ 0x28 +100003b4: 5cb3 ldrb r3, [r6, r2] +100003b6: 1b3f subs r7, r7, r4 +100003b8: 005b lsls r3, r3, #1 +100003ba: b2db uxtb r3, r3 +100003bc: 2f28 cmp r7, #40 @ 0x28 +100003be: f101 0101 add.w r1, r1, #1 +100003c2: bf88 it hi +100003c4: f043 0301 orrhi.w r3, r3, #1 +100003c8: 2928 cmp r1, #40 @ 0x28 +100003ca: 54b3 strb r3, [r6, r2] +100003cc: d1db bne.n 10000386 +100003ce: f89d 1000 ldrb.w r1, [sp] +100003d2: f89d 6001 ldrb.w r6, [sp, #1] +100003d6: f89d 2002 ldrb.w r2, [sp, #2] +100003da: f89d 0003 ldrb.w r0, [sp, #3] +100003de: 198b adds r3, r1, r6 +100003e0: 4413 add r3, r2 +100003e2: f89d 7004 ldrb.w r7, [sp, #4] +100003e6: 4403 add r3, r0 +100003e8: b2db uxtb r3, r3 +100003ea: 429f cmp r7, r3 +100003ec: d11d bne.n 1000042a +100003ee: ee07 6a90 vmov s15, r6 +100003f2: eeb8 6ae7 vcvt.f32.s32 s12, s15 +100003f6: ee07 1a90 vmov s15, r1 +100003fa: eeb8 7ae7 vcvt.f32.s32 s14, s15 +100003fe: ee07 0a90 vmov s15, r0 +10000402: eef8 6ae7 vcvt.f32.s32 s13, s15 +10000406: ee07 2a90 vmov s15, r2 +1000040a: eddf 5a0b vldr s11, [pc, #44] @ 10000438 +1000040e: eef8 7ae7 vcvt.f32.s32 s15, s15 +10000412: 2001 movs r0, #1 +10000414: eea6 7a25 vfma.f32 s14, s12, s11 +10000418: eee6 7aa5 vfma.f32 s15, s13, s11 +1000041c: ed85 7a00 vstr s14, [r5] +10000420: edcb 7a00 vstr s15, [fp] +10000424: b003 add sp, #12 +10000426: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000042a: 2000 movs r0, #0 +1000042c: b003 add sp, #12 +1000042e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000432: bf00 nop +10000434: 400b0000 .word 0x400b0000 +10000438: 3dcccccd .word 0x3dcccccd +1000043c: 20000b7c .word 0x20000b7c + +10000440 : +10000440: b410 push {r4} +10000442: f44f 7480 mov.w r4, #256 @ 0x100 +10000446: 4b0c ldr r3, [pc, #48] @ (10000478 ) +10000448: f853 2020 ldr.w r2, [r3, r0, lsl #2] +1000044c: eb03 0380 add.w r3, r3, r0, lsl #2 +10000450: 00c0 lsls r0, r0, #3 +10000452: f082 0240 eor.w r2, r2, #64 @ 0x40 +10000456: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +1000045a: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +1000045e: f002 02c0 and.w r2, r2, #192 @ 0xc0 +10000462: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000466: f503 5340 add.w r3, r3, #12288 @ 0x3000 +1000046a: f8cc 2000 str.w r2, [ip] +1000046e: 6041 str r1, [r0, #4] +10000470: 601c str r4, [r3, #0] +10000472: f85d 4b04 ldr.w r4, [sp], #4 +10000476: 4770 bx lr +10000478: 40038004 .word 0x40038004 + +1000047c : +1000047c: b410 push {r4} +1000047e: 4c08 ldr r4, [pc, #32] @ (100004a0 ) +10000480: 00c9 lsls r1, r1, #3 +10000482: ea41 0182 orr.w r1, r1, r2, lsl #2 +10000486: f854 2020 ldr.w r2, [r4, r0, lsl #2] +1000048a: eb04 0380 add.w r3, r4, r0, lsl #2 +1000048e: 4051 eors r1, r2 +10000490: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000494: f001 010c and.w r1, r1, #12 +10000498: f85d 4b04 ldr.w r4, [sp], #4 +1000049c: 6019 str r1, [r3, #0] +1000049e: 4770 bx lr +100004a0: 40038004 .word 0x40038004 + +100004a4 : +100004a4: b430 push {r4, r5} +100004a6: f04f 0300 mov.w r3, #0 +100004aa: ec43 0044 gpioc_bit_oe_put r0, r3 +100004ae: ec43 0040 gpioc_bit_out_put r0, r3 +100004b2: 2505 movs r5, #5 +100004b4: f44f 7480 mov.w r4, #256 @ 0x100 +100004b8: 4b0b ldr r3, [pc, #44] @ (100004e8 ) +100004ba: 00c2 lsls r2, r0, #3 +100004bc: f853 1020 ldr.w r1, [r3, r0, lsl #2] +100004c0: eb03 0080 add.w r0, r3, r0, lsl #2 +100004c4: f081 0140 eor.w r1, r1, #64 @ 0x40 +100004c8: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +100004cc: f503 3320 add.w r3, r3, #163840 @ 0x28000 +100004d0: f001 02c0 and.w r2, r1, #192 @ 0xc0 +100004d4: f500 5180 add.w r1, r0, #4096 @ 0x1000 +100004d8: f500 5040 add.w r0, r0, #12288 @ 0x3000 +100004dc: 600a str r2, [r1, #0] +100004de: 605d str r5, [r3, #4] +100004e0: 6004 str r4, [r0, #0] +100004e2: bc30 pop {r4, r5} +100004e4: 4770 bx lr +100004e6: bf00 nop +100004e8: 40038004 .word 0x40038004 + +100004ec : +100004ec: b40f push {r0, r1, r2, r3} +100004ee: b500 push {lr} +100004f0: b083 sub sp, #12 +100004f2: 9c04 ldr r4, [sp, #16] +100004f4: 4807 ldr r0, [pc, #28] @ (10000514 ) +100004f6: f002 ff95 bl 10003424 <__wrap_puts> +100004fa: b13c cbz r4, 1000050c +100004fc: a905 add r1, sp, #20 +100004fe: 4620 mov r0, r4 +10000500: 9101 str r1, [sp, #4] +10000502: f002 fe01 bl 10003108 +10000506: 4804 ldr r0, [pc, #16] @ (10000518 ) +10000508: f002 ff8c bl 10003424 <__wrap_puts> +1000050c: 2001 movs r0, #1 +1000050e: f002 fe13 bl 10003138 <_exit> +10000512: bf00 nop +10000514: 100039c8 .word 0x100039c8 +10000518: 100039d8 .word 0x100039d8 + +1000051c : +1000051c: b570 push {r4, r5, r6, lr} +1000051e: 4686 mov lr, r0 +10000520: f3ef 8510 mrs r5, PRIMASK +10000524: b672 cpsid i +10000526: 4c12 ldr r4, [pc, #72] @ (10000570 ) +10000528: e8d4 6fcf ldaexb r6, [r4] +1000052c: 2001 movs r0, #1 +1000052e: 2e00 cmp r6, #0 +10000530: d1fa bne.n 10000528 +10000532: e8c4 0f46 strexb r6, r0, [r4] +10000536: 2e00 cmp r6, #0 +10000538: d1f6 bne.n 10000528 +1000053a: f3bf 8f5f dmb sy +1000053e: f04f 0c01 mov.w ip, #1 +10000542: 08c8 lsrs r0, r1, #3 +10000544: f001 0307 and.w r3, r1, #7 +10000548: fa0c f303 lsl.w r3, ip, r3 +1000054c: f81e c000 ldrb.w ip, [lr, r0] +10000550: ea1c 0603 ands.w r6, ip, r3 +10000554: d108 bne.n 10000568 +10000556: ea4c 0c03 orr.w ip, ip, r3 +1000055a: f80e c000 strb.w ip, [lr, r0] +1000055e: e8c4 6f8f stlb r6, [r4] +10000562: f385 8810 msr PRIMASK, r5 +10000566: bd70 pop {r4, r5, r6, pc} +10000568: 4610 mov r0, r2 +1000056a: f7ff ffbf bl 100004ec +1000056e: bf00 nop +10000570: 20000b33 .word 0x20000b33 + +10000574 : +10000574: 4a04 ldr r2, [pc, #16] @ (10000588 ) +10000576: 7810 ldrb r0, [r2, #0] +10000578: 1c43 adds r3, r0, #1 +1000057a: b2db uxtb r3, r3 +1000057c: 2b18 cmp r3, #24 +1000057e: bf28 it cs +10000580: 2310 movcs r3, #16 +10000582: 7013 strb r3, [r2, #0] +10000584: 4770 bx lr +10000586: bf00 nop +10000588: 20000920 .word 0x20000920 + +1000058c : +1000058c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000590: 6893 ldr r3, [r2, #8] +10000592: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +10000596: 6093 str r3, [r2, #8] +10000598: 4770 bx lr +1000059a: bf00 nop + +1000059c : +1000059c: 2100 movs r1, #0 +1000059e: 4b04 ldr r3, [pc, #16] @ (100005b0 ) +100005a0: f103 0220 add.w r2, r3, #32 +100005a4: e8c3 1f8f stlb r1, [r3] +100005a8: 3301 adds r3, #1 +100005aa: 4293 cmp r3, r2 +100005ac: d1fa bne.n 100005a4 +100005ae: 4770 bx lr +100005b0: 20000b28 .word 0x20000b28 + +100005b4 : +100005b4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100005b8: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100005bc: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100005c0: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100005c4: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100005c8: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100005cc: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100005d0: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100005d4: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +100005d8: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100005dc: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100005e0: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100005e4: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100005e8: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100005ec: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100005f0: b662 cpsie i +100005f2: 4770 bx lr + +100005f4 : +100005f4: 2301 movs r3, #1 +100005f6: f000 021f and.w r2, r0, #31 +100005fa: 4093 lsls r3, r2 +100005fc: 0940 lsrs r0, r0, #5 +100005fe: b141 cbz r1, 10000612 +10000600: 0080 lsls r0, r0, #2 +10000602: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000606: f500 4061 add.w r0, r0, #57600 @ 0xe100 +1000060a: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000060e: 6003 str r3, [r0, #0] +10000610: 4770 bx lr +10000612: 4a02 ldr r2, [pc, #8] @ (1000061c ) +10000614: 3020 adds r0, #32 +10000616: f842 3020 str.w r3, [r2, r0, lsl #2] +1000061a: 4770 bx lr +1000061c: e000e100 .word 0xe000e100 + +10000620 : +10000620: b5f8 push {r3, r4, r5, r6, r7, lr} +10000622: 460d mov r5, r1 +10000624: f3ef 8710 mrs r7, PRIMASK +10000628: b672 cpsid i +1000062a: 4e12 ldr r6, [pc, #72] @ (10000674 ) +1000062c: e8d6 2fcf ldaexb r2, [r6] +10000630: 2301 movs r3, #1 +10000632: 2a00 cmp r2, #0 +10000634: d1fa bne.n 1000062c +10000636: e8c6 3f42 strexb r2, r3, [r6] +1000063a: 2a00 cmp r2, #0 +1000063c: d1f6 bne.n 1000062c +1000063e: f3bf 8f5f dmb sy +10000642: 4b0d ldr r3, [pc, #52] @ (10000678 ) +10000644: f100 0410 add.w r4, r0, #16 +10000648: 689b ldr r3, [r3, #8] +1000064a: 4a0c ldr r2, [pc, #48] @ (1000067c ) +1000064c: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000650: 4293 cmp r3, r2 +10000652: d003 beq.n 1000065c +10000654: 4299 cmp r1, r3 +10000656: d001 beq.n 1000065c +10000658: f000 ff7a bl 10001550 +1000065c: 4b06 ldr r3, [pc, #24] @ (10000678 ) +1000065e: 689b ldr r3, [r3, #8] +10000660: f843 5024 str.w r5, [r3, r4, lsl #2] +10000664: f3bf 8f5f dmb sy +10000668: 2300 movs r3, #0 +1000066a: e8c6 3f8f stlb r3, [r6] +1000066e: f387 8810 msr PRIMASK, r7 +10000672: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000674: 20000b31 .word 0x20000b31 +10000678: e000ed00 .word 0xe000ed00 +1000067c: 10000111 .word 0x10000111 + +10000680 : +10000680: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000684: b083 sub sp, #12 +10000686: f3ef 8a10 mrs sl, PRIMASK +1000068a: b672 cpsid i +1000068c: 4e71 ldr r6, [pc, #452] @ (10000854 ) +1000068e: e8d6 2fcf ldaexb r2, [r6] +10000692: 2301 movs r3, #1 +10000694: 2a00 cmp r2, #0 +10000696: d1fa bne.n 1000068e +10000698: e8c6 3f42 strexb r2, r3, [r6] +1000069c: 2a00 cmp r2, #0 +1000069e: d1f6 bne.n 1000068e +100006a0: f3bf 8f5f dmb sy +100006a4: 4b6c ldr r3, [pc, #432] @ (10000858 ) +100006a6: f100 0810 add.w r8, r0, #16 +100006aa: 689b ldr r3, [r3, #8] +100006ac: 4a6b ldr r2, [pc, #428] @ (1000085c ) +100006ae: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100006b2: 4295 cmp r5, r2 +100006b4: d045 beq.n 10000742 +100006b6: 428d cmp r5, r1 +100006b8: 460c mov r4, r1 +100006ba: d050 beq.n 1000075e +100006bc: 4f68 ldr r7, [pc, #416] @ (10000860 ) +100006be: 1beb subs r3, r5, r7 +100006c0: 2b2f cmp r3, #47 @ 0x2f +100006c2: d83e bhi.n 10000742 +100006c4: 2101 movs r1, #1 +100006c6: ea4f 1950 mov.w r9, r0, lsr #5 +100006ca: ea4f 0989 mov.w r9, r9, lsl #2 +100006ce: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100006d2: f509 4961 add.w r9, r9, #57600 @ 0xe100 +100006d6: f000 031f and.w r3, r0, #31 +100006da: fa01 f003 lsl.w r0, r1, r3 +100006de: f8d9 3000 ldr.w r3, [r9] +100006e2: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100006e6: ea00 0b03 and.w fp, r0, r3 +100006ea: f3bf 8f5f dmb sy +100006ee: f3ef 8105 mrs r1, IPSR +100006f2: b2c9 uxtb r1, r1 +100006f4: 2900 cmp r1, #0 +100006f6: d034 beq.n 10000762 +100006f8: 4588 cmp r8, r1 +100006fa: d005 beq.n 10000708 +100006fc: e9cd 1000 strd r1, r0, [sp] +10000700: f000 ff26 bl 10001550 +10000704: e9dd 1000 ldrd r1, r0, [sp] +10000708: f025 0e01 bic.w lr, r5, #1 +1000070c: f8de c008 ldr.w ip, [lr, #8] +10000710: 4564 cmp r4, ip +10000712: d105 bne.n 10000720 +10000714: e089 b.n 1000082a +10000716: f8d3 c008 ldr.w ip, [r3, #8] +1000071a: 4564 cmp r4, ip +1000071c: d031 beq.n 10000782 +1000071e: 469e mov lr, r3 +10000720: f99e 2006 ldrsb.w r2, [lr, #6] +10000724: eb02 0342 add.w r3, r2, r2, lsl #1 +10000728: 2a00 cmp r2, #0 +1000072a: eb07 0383 add.w r3, r7, r3, lsl #2 +1000072e: daf2 bge.n 10000716 +10000730: 4564 cmp r4, ip +10000732: d061 beq.n 100007f8 +10000734: f1bb 0f00 cmp.w fp, #0 +10000738: d020 beq.n 1000077c +1000073a: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +1000073e: f8c9 0000 str.w r0, [r9] +10000742: 4b45 ldr r3, [pc, #276] @ (10000858 ) +10000744: 689b ldr r3, [r3, #8] +10000746: f843 5028 str.w r5, [r3, r8, lsl #2] +1000074a: f3bf 8f5f dmb sy +1000074e: 2300 movs r3, #0 +10000750: e8c6 3f8f stlb r3, [r6] +10000754: f38a 8810 msr PRIMASK, sl +10000758: b003 add sp, #12 +1000075a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000075e: 4615 mov r5, r2 +10000760: e7ef b.n 10000742 +10000762: f025 0e01 bic.w lr, r5, #1 +10000766: f8de c008 ldr.w ip, [lr, #8] +1000076a: 4564 cmp r4, ip +1000076c: d1d8 bne.n 10000720 +1000076e: f99e 4006 ldrsb.w r4, [lr, #6] +10000772: 4673 mov r3, lr +10000774: 2c00 cmp r4, #0 +10000776: da08 bge.n 1000078a +10000778: 4615 mov r5, r2 +1000077a: e046 b.n 1000080a +1000077c: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000780: e7df b.n 10000742 +10000782: f993 4006 ldrsb.w r4, [r3, #6] +10000786: 2c00 cmp r4, #0 +10000788: db37 blt.n 100007fa +1000078a: eb04 0c44 add.w ip, r4, r4, lsl #1 +1000078e: eb07 0c8c add.w ip, r7, ip, lsl #2 +10000792: f89c 1007 ldrb.w r1, [ip, #7] +10000796: f8dc 2008 ldr.w r2, [ip, #8] +1000079a: 71d9 strb r1, [r3, #7] +1000079c: 609a str r2, [r3, #8] +1000079e: f99c 2006 ldrsb.w r2, [ip, #6] +100007a2: 0061 lsls r1, r4, #1 +100007a4: 2a00 cmp r2, #0 +100007a6: 719a strb r2, [r3, #6] +100007a8: db3d blt.n 10000826 +100007aa: f8bc e004 ldrh.w lr, [ip, #4] +100007ae: ea5f 5e4e movs.w lr, lr, lsl #21 +100007b2: d505 bpl.n 100007c0 +100007b4: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100007b8: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100007bc: f10e 0e1f add.w lr, lr, #31 +100007c0: f06f 0c07 mvn.w ip, #7 +100007c4: 190a adds r2, r1, r4 +100007c6: ea4f 5e6e mov.w lr, lr, asr #21 +100007ca: 0092 lsls r2, r2, #2 +100007cc: eb02 024e add.w r2, r2, lr, lsl #1 +100007d0: 3208 adds r2, #8 +100007d2: 443a add r2, r7 +100007d4: ebac 0c03 sub.w ip, ip, r3 +100007d8: 4462 add r2, ip +100007da: f3c2 024a ubfx r2, r2, #1, #11 +100007de: ea6f 42c2 mvn.w r2, r2, lsl #19 +100007e2: ea6f 42d2 mvn.w r2, r2, lsr #19 +100007e6: 809a strh r2, [r3, #4] +100007e8: 4b1e ldr r3, [pc, #120] @ (10000864 ) +100007ea: 4421 add r1, r4 +100007ec: 781a ldrb r2, [r3, #0] +100007ee: eb07 0181 add.w r1, r7, r1, lsl #2 +100007f2: 701c strb r4, [r3, #0] +100007f4: 718a strb r2, [r1, #6] +100007f6: e79d b.n 10000734 +100007f8: 4673 mov r3, lr +100007fa: b9d9 cbnz r1, 10000834 +100007fc: 22ff movs r2, #255 @ 0xff +100007fe: f88e 2006 strb.w r2, [lr, #6] +10000802: f64b 5201 movw r2, #48385 @ 0xbd01 +10000806: f8ae 2004 strh.w r2, [lr, #4] +1000080a: 4c16 ldr r4, [pc, #88] @ (10000864 ) +1000080c: f64a 22aa movw r2, #43690 @ 0xaaaa +10000810: f894 c000 ldrb.w ip, [r4] +10000814: 4619 mov r1, r3 +10000816: 1bc9 subs r1, r1, r7 +10000818: 4149 adcs r1, r1 +1000081a: 434a muls r2, r1 +1000081c: 0d12 lsrs r2, r2, #20 +1000081e: f883 c006 strb.w ip, [r3, #6] +10000822: 7022 strb r2, [r4, #0] +10000824: e786 b.n 10000734 +10000826: 4a10 ldr r2, [pc, #64] @ (10000868 ) +10000828: e7dd b.n 100007e6 +1000082a: f99e 4006 ldrsb.w r4, [lr, #6] +1000082e: 4673 mov r3, lr +10000830: 2c00 cmp r4, #0 +10000832: daaa bge.n 1000078a +10000834: 4a0d ldr r2, [pc, #52] @ (1000086c ) +10000836: 4c0e ldr r4, [pc, #56] @ (10000870 ) +10000838: 1ad2 subs r2, r2, r3 +1000083a: 3a08 subs r2, #8 +1000083c: f3c2 310a ubfx r1, r2, #12, #11 +10000840: ea6f 5101 mvn.w r1, r1, lsl #20 +10000844: ea6f 5111 mvn.w r1, r1, lsr #20 +10000848: ea44 0252 orr.w r2, r4, r2, lsr #1 +1000084c: 80da strh r2, [r3, #6] +1000084e: 8099 strh r1, [r3, #4] +10000850: e770 b.n 10000734 +10000852: bf00 nop +10000854: 20000b31 .word 0x20000b31 +10000858: e000ed00 .word 0xe000ed00 +1000085c: 10000111 .word 0x10000111 +10000860: 20000924 .word 0x20000924 +10000864: 20000bd0 .word 0x20000bd0 +10000868: ffffbd01 .word 0xffffbd01 +1000086c: 2000095e .word 0x2000095e +10000870: fffff800 .word 0xfffff800 + +10000874 : +10000874: b5f0 push {r4, r5, r6, r7, lr} +10000876: f3ef 8505 mrs r5, IPSR +1000087a: b2ed uxtb r5, r5 +1000087c: f3ef 8c10 mrs ip, PRIMASK +10000880: b672 cpsid i +10000882: 4926 ldr r1, [pc, #152] @ (1000091c ) +10000884: e8d1 2fcf ldaexb r2, [r1] +10000888: 2301 movs r3, #1 +1000088a: 2a00 cmp r2, #0 +1000088c: d1fa bne.n 10000884 +1000088e: e8c1 3f42 strexb r2, r3, [r1] +10000892: 2a00 cmp r2, #0 +10000894: d1f6 bne.n 10000884 +10000896: f3bf 8f5f dmb sy +1000089a: 4e21 ldr r6, [pc, #132] @ (10000920 ) +1000089c: f040 0e01 orr.w lr, r0, #1 +100008a0: 68b4 ldr r4, [r6, #8] +100008a2: f64a 23aa movw r3, #43690 @ 0xaaaa +100008a6: f854 7025 ldr.w r7, [r4, r5, lsl #2] +100008aa: 4a1e ldr r2, [pc, #120] @ (10000924 ) +100008ac: 4604 mov r4, r0 +100008ae: 1aa4 subs r4, r4, r2 +100008b0: 4164 adcs r4, r4 +100008b2: 4363 muls r3, r4 +100008b4: 0d1b lsrs r3, r3, #20 +100008b6: 4577 cmp r7, lr +100008b8: b25b sxtb r3, r3 +100008ba: d01b beq.n 100008f4 +100008bc: f992 4006 ldrsb.w r4, [r2, #6] +100008c0: 429c cmp r4, r3 +100008c2: d01c beq.n 100008fe +100008c4: f992 4012 ldrsb.w r4, [r2, #18] +100008c8: 429c cmp r4, r3 +100008ca: d023 beq.n 10000914 +100008cc: f992 401e ldrsb.w r4, [r2, #30] +100008d0: 429c cmp r4, r3 +100008d2: d021 beq.n 10000918 +100008d4: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100008d8: 429c cmp r4, r3 +100008da: bf08 it eq +100008dc: 2403 moveq r4, #3 +100008de: d00f beq.n 10000900 +100008e0: 4a11 ldr r2, [pc, #68] @ (10000928 ) +100008e2: 2400 movs r4, #0 +100008e4: 7815 ldrb r5, [r2, #0] +100008e6: 7013 strb r3, [r2, #0] +100008e8: 7185 strb r5, [r0, #6] +100008ea: e8c1 4f8f stlb r4, [r1] +100008ee: f38c 8810 msr PRIMASK, ip +100008f2: bdf0 pop {r4, r5, r6, r7, pc} +100008f4: 68b2 ldr r2, [r6, #8] +100008f6: 4c0d ldr r4, [pc, #52] @ (1000092c ) +100008f8: f842 4025 str.w r4, [r2, r5, lsl #2] +100008fc: e7f0 b.n 100008e0 +100008fe: 2400 movs r4, #0 +10000900: eb04 0444 add.w r4, r4, r4, lsl #1 +10000904: eb02 0284 add.w r2, r2, r4, lsl #2 +10000908: 24ff movs r4, #255 @ 0xff +1000090a: 7194 strb r4, [r2, #6] +1000090c: f64b 5401 movw r4, #48385 @ 0xbd01 +10000910: 8094 strh r4, [r2, #4] +10000912: e7e5 b.n 100008e0 +10000914: 2401 movs r4, #1 +10000916: e7f3 b.n 10000900 +10000918: 2402 movs r4, #2 +1000091a: e7f1 b.n 10000900 +1000091c: 20000b31 .word 0x20000b31 +10000920: e000ed00 .word 0xe000ed00 +10000924: 20000924 .word 0x20000924 +10000928: 20000bd0 .word 0x20000bd0 +1000092c: 10000111 .word 0x10000111 + +10000930 : +10000930: 4b01 ldr r3, [pc, #4] @ (10000938 ) +10000932: 440b add r3, r1 +10000934: 6003 str r3, [r0, #0] +10000936: 4770 bx lr +10000938: 20000b28 .word 0x20000b28 + +1000093c : +1000093c: b570 push {r4, r5, r6, lr} +1000093e: 4c10 ldr r4, [pc, #64] @ (10000980 ) +10000940: 4d10 ldr r5, [pc, #64] @ (10000984 ) +10000942: 42ac cmp r4, r5 +10000944: d20e bcs.n 10000964 +10000946: 26ff movs r6, #255 @ 0xff +10000948: 6823 ldr r3, [r4, #0] +1000094a: b163 cbz r3, 10000966 +1000094c: f7ff fe12 bl 10000574 +10000950: 4601 mov r1, r0 +10000952: 4620 mov r0, r4 +10000954: f7ff ffec bl 10000930 +10000958: 80a6 strh r6, [r4, #4] +1000095a: f3bf 8f5f dmb sy +1000095e: 3408 adds r4, #8 +10000960: 42ac cmp r4, r5 +10000962: d3f1 bcc.n 10000948 +10000964: bd70 pop {r4, r5, r6, pc} +10000966: f7ff fe05 bl 10000574 +1000096a: 4601 mov r1, r0 +1000096c: 4620 mov r0, r4 +1000096e: f7ff ffdf bl 10000930 +10000972: 7126 strb r6, [r4, #4] +10000974: f3bf 8f5f dmb sy +10000978: 3408 adds r4, #8 +1000097a: 42ac cmp r4, r5 +1000097c: d3e4 bcc.n 10000948 +1000097e: bd70 pop {r4, r5, r6, pc} +10000980: 2000099c .word 0x2000099c +10000984: 200009a4 .word 0x200009a4 + +10000988 : +10000988: 4b0d ldr r3, [pc, #52] @ (100009c0 ) +1000098a: 681a ldr r2, [r3, #0] +1000098c: f3ef 8110 mrs r1, PRIMASK +10000990: b672 cpsid i +10000992: e8d2 cfcf ldaexb ip, [r2] +10000996: 2001 movs r0, #1 +10000998: f1bc 0f00 cmp.w ip, #0 +1000099c: d1f9 bne.n 10000992 +1000099e: e8c2 0f4c strexb ip, r0, [r2] +100009a2: f1bc 0f00 cmp.w ip, #0 +100009a6: d1f4 bne.n 10000992 +100009a8: f3bf 8f5f dmb sy +100009ac: 2200 movs r2, #0 +100009ae: 681b ldr r3, [r3, #0] +100009b0: e8c3 2f8f stlb r2, [r3] +100009b4: f381 8810 msr PRIMASK, r1 +100009b8: bf40 sev +100009ba: 2000 movs r0, #0 +100009bc: 2100 movs r1, #0 +100009be: 4770 bx lr +100009c0: 20000bc4 .word 0x20000bc4 +100009c4: 00000000 .word 0x00000000 + +100009c8 : +100009c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100009cc: ed2d 8b02 vpush {d8} +100009d0: b085 sub sp, #20 +100009d2: f3ef 8305 mrs r3, IPSR +100009d6: b2db uxtb r3, r3 +100009d8: 3b10 subs r3, #16 +100009da: 089a lsrs r2, r3, #2 +100009dc: bf18 it ne +100009de: 2201 movne r2, #1 +100009e0: f04f 0101 mov.w r1, #1 +100009e4: f003 0b03 and.w fp, r3, #3 +100009e8: bf18 it ne +100009ea: 4daf ldrne r5, [pc, #700] @ (10000ca8 ) +100009ec: 4baf ldr r3, [pc, #700] @ (10000cac ) +100009ee: bf08 it eq +100009f0: 4daf ldreq r5, [pc, #700] @ (10000cb0 ) +100009f2: eb0b 0282 add.w r2, fp, r2, lsl #2 +100009f6: f853 6022 ldr.w r6, [r3, r2, lsl #2] +100009fa: fa01 f20b lsl.w r2, r1, fp +100009fe: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000a02: ed9f 8ba7 vldr d8, [pc, #668] @ 10000ca0 +10000a06: 9201 str r2, [sp, #4] +10000a08: 605a str r2, [r3, #4] +10000a0a: e02f b.n 10000a6c +10000a0c: 88b3 ldrh r3, [r6, #4] +10000a0e: 041c lsls r4, r3, #16 +10000a10: f140 8093 bpl.w 10000b3a +10000a14: 79b3 ldrb r3, [r6, #6] +10000a16: 2b00 cmp r3, #0 +10000a18: f040 80dd bne.w 10000bd6 +10000a1c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000a20: 2a00 cmp r2, #0 +10000a22: f2c0 811e blt.w 10000c62 +10000a26: 6973 ldr r3, [r6, #20] +10000a28: eb02 0242 add.w r2, r2, r2, lsl #1 +10000a2c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000a30: e9d3 4702 ldrd r4, r7, [r3, #8] +10000a34: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000a38: bf08 it eq +10000a3a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000a3e: d00e beq.n 10000a5e +10000a40: eb05 018b add.w r1, r5, fp, lsl #2 +10000a44: 6aab ldr r3, [r5, #40] @ 0x28 +10000a46: 690a ldr r2, [r1, #16] +10000a48: 1ad2 subs r2, r2, r3 +10000a4a: 1ae3 subs r3, r4, r3 +10000a4c: 4293 cmp r3, r2 +10000a4e: d305 bcc.n 10000a5c +10000a50: 2301 movs r3, #1 +10000a52: 6a2a ldr r2, [r5, #32] +10000a54: fa03 f30b lsl.w r3, r3, fp +10000a58: 4213 tst r3, r2 +10000a5a: d100 bne.n 10000a5e +10000a5c: 610c str r4, [r1, #16] +10000a5e: 4628 mov r0, r5 +10000a60: f000 fba4 bl 100011ac +10000a64: 42a0 cmp r0, r4 +10000a66: 41b9 sbcs r1, r7 +10000a68: f2c0 80fb blt.w 10000c62 +10000a6c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000a70: 9a01 ldr r2, [sp, #4] +10000a72: 2b00 cmp r3, #0 +10000a74: 9300 str r3, [sp, #0] +10000a76: 63ea str r2, [r5, #60] @ 0x3c +10000a78: dbc8 blt.n 10000a0c +10000a7a: f8d6 8014 ldr.w r8, [r6, #20] +10000a7e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000a82: 4628 mov r0, r5 +10000a84: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000a88: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000a8c: f000 fb8e bl 100011ac +10000a90: 42a0 cmp r0, r4 +10000a92: eb71 010a sbcs.w r1, r1, sl +10000a96: dbb9 blt.n 10000a0c +10000a98: f1ba 0f00 cmp.w sl, #0 +10000a9c: f2c0 80c3 blt.w 10000c26 +10000aa0: e9d7 3104 ldrd r3, r1, [r7, #16] +10000aa4: 4a83 ldr r2, [pc, #524] @ (10000cb4 ) +10000aa6: 4293 cmp r3, r2 +10000aa8: f000 80ed beq.w 10000c86 +10000aac: 887a ldrh r2, [r7, #2] +10000aae: f9b6 0008 ldrsh.w r0, [r6, #8] +10000ab2: b292 uxth r2, r2 +10000ab4: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000ab8: 4798 blx r3 +10000aba: 4602 mov r2, r0 +10000abc: 460b mov r3, r1 +10000abe: ea52 0103 orrs.w r1, r2, r3 +10000ac2: f000 80b0 beq.w 10000c26 +10000ac6: 2b00 cmp r3, #0 +10000ac8: f280 80d1 bge.w 10000c6e +10000acc: ebb4 0e02 subs.w lr, r4, r2 +10000ad0: eb6a 0a03 sbc.w sl, sl, r3 +10000ad4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000ad8: e9c7 ea02 strd lr, sl, [r7, #8] +10000adc: 2b00 cmp r3, #0 +10000ade: db95 blt.n 10000a0c +10000ae0: 6971 ldr r1, [r6, #20] +10000ae2: eb03 0243 add.w r2, r3, r3, lsl #1 +10000ae6: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000aea: e9d2 7002 ldrd r7, r0, [r2, #8] +10000aee: 45be cmp lr, r7 +10000af0: eb7a 0c00 sbcs.w ip, sl, r0 +10000af4: ea4f 0243 mov.w r2, r3, lsl #1 +10000af8: db88 blt.n 10000a0c +10000afa: 46b4 mov ip, r6 +10000afc: f82c 3f08 strh.w r3, [ip, #8]! +10000b00: e006 b.n 10000b10 +10000b02: eb03 0043 add.w r0, r3, r3, lsl #1 +10000b06: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000b0a: 005a lsls r2, r3, #1 +10000b0c: e9d0 7002 ldrd r7, r0, [r0, #8] +10000b10: 45be cmp lr, r7 +10000b12: 441a add r2, r3 +10000b14: eb7a 0000 sbcs.w r0, sl, r0 +10000b18: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000b1c: db04 blt.n 10000b28 +10000b1e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000b22: 46a4 mov ip, r4 +10000b24: 2b00 cmp r3, #0 +10000b26: daec bge.n 10000b02 +10000b28: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000b2c: 9b00 ldr r3, [sp, #0] +10000b2e: f8ac 3000 strh.w r3, [ip] +10000b32: 88b3 ldrh r3, [r6, #4] +10000b34: 041c lsls r4, r3, #16 +10000b36: f53f af6d bmi.w 10000a14 +10000b3a: 6933 ldr r3, [r6, #16] +10000b3c: f3ef 8210 mrs r2, PRIMASK +10000b40: b672 cpsid i +10000b42: e8d3 0fcf ldaexb r0, [r3] +10000b46: 2101 movs r1, #1 +10000b48: 2800 cmp r0, #0 +10000b4a: d1fa bne.n 10000b42 +10000b4c: e8c3 1f40 strexb r0, r1, [r3] +10000b50: 2800 cmp r0, #0 +10000b52: d1f6 bne.n 10000b42 +10000b54: f3bf 8f5f dmb sy +10000b58: f64f 74ff movw r4, #65535 @ 0xffff +10000b5c: 88b0 ldrh r0, [r6, #4] +10000b5e: 2300 movs r3, #0 +10000b60: 6931 ldr r1, [r6, #16] +10000b62: b200 sxth r0, r0 +10000b64: 80b4 strh r4, [r6, #4] +10000b66: e8c1 3f8f stlb r3, [r1] +10000b6a: f382 8810 msr PRIMASK, r2 +10000b6e: 4298 cmp r0, r3 +10000b70: f6ff af50 blt.w 10000a14 +10000b74: 4607 mov r7, r0 +10000b76: 46a9 mov r9, r5 +10000b78: 6974 ldr r4, [r6, #20] +10000b7a: f106 0808 add.w r8, r6, #8 +10000b7e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000b82: eb04 03ce add.w r3, r4, lr, lsl #3 +10000b86: e9d3 5002 ldrd r5, r0, [r3, #8] +10000b8a: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b8e: 46c4 mov ip, r8 +10000b90: 2b00 cmp r3, #0 +10000b92: db13 blt.n 10000bbc +10000b94: 46b2 mov sl, r6 +10000b96: 9700 str r7, [sp, #0] +10000b98: e004 b.n 10000ba4 +10000b9a: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000b9e: 4694 mov ip, r2 +10000ba0: 2b00 cmp r3, #0 +10000ba2: db09 blt.n 10000bb8 +10000ba4: eb03 0643 add.w r6, r3, r3, lsl #1 +10000ba8: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000bac: e9d2 7102 ldrd r7, r1, [r2, #8] +10000bb0: 42bd cmp r5, r7 +10000bb2: eb70 0101 sbcs.w r1, r0, r1 +10000bb6: daf0 bge.n 10000b9a +10000bb8: 4656 mov r6, sl +10000bba: 9f00 ldr r7, [sp, #0] +10000bbc: f8ac 7000 strh.w r7, [ip] +10000bc0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000bc4: f824 303e strh.w r3, [r4, lr, lsl #3] +10000bc8: 2f00 cmp r7, #0 +10000bca: dad8 bge.n 10000b7e +10000bcc: 79b3 ldrb r3, [r6, #6] +10000bce: 464d mov r5, r9 +10000bd0: 2b00 cmp r3, #0 +10000bd2: f43f af23 beq.w 10000a1c +10000bd6: 2300 movs r3, #0 +10000bd8: 71b3 strb r3, [r6, #6] +10000bda: f9b6 3008 ldrsh.w r3, [r6, #8] +10000bde: f106 0808 add.w r8, r6, #8 +10000be2: 1c58 adds r0, r3, #1 +10000be4: d03d beq.n 10000c62 +10000be6: 461a mov r2, r3 +10000be8: 6977 ldr r7, [r6, #20] +10000bea: e003 b.n 10000bf4 +10000bec: 4680 mov r8, r0 +10000bee: 1c59 adds r1, r3, #1 +10000bf0: f43f af16 beq.w 10000a20 +10000bf4: eb03 0143 add.w r1, r3, r3, lsl #1 +10000bf8: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000bfc: f8b0 c002 ldrh.w ip, [r0, #2] +10000c00: 461c mov r4, r3 +10000c02: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000c06: 469e mov lr, r3 +10000c08: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000c0c: d0ee beq.n 10000bec +10000c0e: 4294 cmp r4, r2 +10000c10: ed80 8b02 vstr d8, [r0, #8] +10000c14: d005 beq.n 10000c22 +10000c16: f8a8 3000 strh.w r3, [r8] +10000c1a: 8932 ldrh r2, [r6, #8] +10000c1c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000c20: 8134 strh r4, [r6, #8] +10000c22: 4672 mov r2, lr +10000c24: e7e3 b.n 10000bee +10000c26: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000c2a: 8133 strh r3, [r6, #8] +10000c2c: 6933 ldr r3, [r6, #16] +10000c2e: f3ef 8210 mrs r2, PRIMASK +10000c32: b672 cpsid i +10000c34: e8d3 0fcf ldaexb r0, [r3] +10000c38: 2101 movs r1, #1 +10000c3a: 2800 cmp r0, #0 +10000c3c: d1fa bne.n 10000c34 +10000c3e: e8c3 1f40 strexb r0, r1, [r3] +10000c42: 2800 cmp r0, #0 +10000c44: d1f6 bne.n 10000c34 +10000c46: f3bf 8f5f dmb sy +10000c4a: 8873 ldrh r3, [r6, #2] +10000c4c: 6931 ldr r1, [r6, #16] +10000c4e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000c52: 9b00 ldr r3, [sp, #0] +10000c54: 8073 strh r3, [r6, #2] +10000c56: 2300 movs r3, #0 +10000c58: e8c1 3f8f stlb r3, [r1] +10000c5c: f382 8810 msr PRIMASK, r2 +10000c60: e6d4 b.n 10000a0c +10000c62: bf40 sev +10000c64: b005 add sp, #20 +10000c66: ecbd 8b02 vpop {d8} +10000c6a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000c6e: 4628 mov r0, r5 +10000c70: e9cd 2302 strd r2, r3, [sp, #8] +10000c74: f000 fa9a bl 100011ac +10000c78: 9a02 ldr r2, [sp, #8] +10000c7a: 9b03 ldr r3, [sp, #12] +10000c7c: eb10 0e02 adds.w lr, r0, r2 +10000c80: eb43 0a01 adc.w sl, r3, r1 +10000c84: e726 b.n 10000ad4 +10000c86: 4608 mov r0, r1 +10000c88: 690b ldr r3, [r1, #16] +10000c8a: 9102 str r1, [sp, #8] +10000c8c: 4798 blx r3 +10000c8e: 2800 cmp r0, #0 +10000c90: d0c9 beq.n 10000c26 +10000c92: 9902 ldr r1, [sp, #8] +10000c94: e9d1 2300 ldrd r2, r3, [r1] +10000c98: e711 b.n 10000abe +10000c9a: bf00 nop +10000c9c: f3af 8000 nop.w +10000ca0: ffffffff .word 0xffffffff +10000ca4: ffffffff .word 0xffffffff +10000ca8: 400b8000 .word 0x400b8000 +10000cac: 20000ba4 .word 0x20000ba4 +10000cb0: 400b0000 .word 0x400b0000 +10000cb4: 100009c9 .word 0x100009c9 + +10000cb8 : +10000cb8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000cbc: 4c36 ldr r4, [pc, #216] @ (10000d98 ) +10000cbe: 6925 ldr r5, [r4, #16] +10000cc0: b12d cbz r5, 10000cce +10000cc2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000cc6: 210a movs r1, #10 +10000cc8: 4834 ldr r0, [pc, #208] @ (10000d9c ) +10000cca: f7ff be31 b.w 10000930 +10000cce: f8df 80e4 ldr.w r8, [pc, #228] @ 10000db4 +10000cd2: 2103 movs r1, #3 +10000cd4: 4640 mov r0, r8 +10000cd6: f000 fa57 bl 10001188 +10000cda: 2603 movs r6, #3 +10000cdc: f8c4 800c str.w r8, [r4, #12] +10000ce0: f7ff fc48 bl 10000574 +10000ce4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000ce8: 4b2d ldr r3, [pc, #180] @ (10000da0 ) +10000cea: 7026 strb r6, [r4, #0] +10000cec: 4403 add r3, r0 +10000cee: 6123 str r3, [r4, #16] +10000cf0: f8dc 3000 ldr.w r3, [ip] +10000cf4: 210f movs r1, #15 +10000cf6: 7063 strb r3, [r4, #1] +10000cf8: 6963 ldr r3, [r4, #20] +10000cfa: 8061 strh r1, [r4, #2] +10000cfc: 831d strh r5, [r3, #24] +10000cfe: f04f 0504 mov.w r5, #4 +10000d02: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000d06: f04f 0505 mov.w r5, #5 +10000d0a: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000d0e: f04f 0506 mov.w r5, #6 +10000d12: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000d16: f04f 0507 mov.w r5, #7 +10000d1a: 210e movs r1, #14 +10000d1c: f64f 72ff movw r2, #65535 @ 0xffff +10000d20: 2708 movs r7, #8 +10000d22: f04f 0e0a mov.w lr, #10 +10000d26: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000d2a: f04f 0901 mov.w r9, #1 +10000d2e: f04f 0c0c mov.w ip, #12 +10000d32: f04f 0b02 mov.w fp, #2 +10000d36: f04f 0a09 mov.w sl, #9 +10000d3a: 200d movs r0, #13 +10000d3c: f04f 050b mov.w r5, #11 +10000d40: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000d44: 4917 ldr r1, [pc, #92] @ (10000da4 ) +10000d46: 80a2 strh r2, [r4, #4] +10000d48: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000d4c: 60a1 str r1, [r4, #8] +10000d4e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000d52: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000d56: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000d5a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000d5e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000d62: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000d66: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000d6a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000d6e: 801a strh r2, [r3, #0] +10000d70: 4b0d ldr r3, [pc, #52] @ (10000da8 ) +10000d72: 4630 mov r0, r6 +10000d74: f8c8 7020 str.w r7, [r8, #32] +10000d78: 490c ldr r1, [pc, #48] @ (10000dac ) +10000d7a: 60dc str r4, [r3, #12] +10000d7c: f7ff fc50 bl 10000620 +10000d80: 4649 mov r1, r9 +10000d82: 4630 mov r0, r6 +10000d84: f7ff fc36 bl 100005f4 +10000d88: 4b09 ldr r3, [pc, #36] @ (10000db0 ) +10000d8a: 210a movs r1, #10 +10000d8c: 641f str r7, [r3, #64] @ 0x40 +10000d8e: 4803 ldr r0, [pc, #12] @ (10000d9c ) +10000d90: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000d94: f7ff bdcc b.w 10000930 +10000d98: 2000096c .word 0x2000096c +10000d9c: 20000bc4 .word 0x20000bc4 +10000da0: 20000b28 .word 0x20000b28 +10000da4: 0010ffff .word 0x0010ffff +10000da8: 20000ba4 .word 0x20000ba4 +10000dac: 100009c9 .word 0x100009c9 +10000db0: 400b2000 .word 0x400b2000 +10000db4: 400b0000 .word 0x400b0000 + +10000db8 : +10000db8: 4601 mov r1, r0 +10000dba: b5f0 push {r4, r5, r6, r7, lr} +10000dbc: 6900 ldr r0, [r0, #16] +10000dbe: f3ef 8710 mrs r7, PRIMASK +10000dc2: b672 cpsid i +10000dc4: e8d0 5fcf ldaexb r5, [r0] +10000dc8: 2401 movs r4, #1 +10000dca: 2d00 cmp r5, #0 +10000dcc: d1fa bne.n 10000dc4 +10000dce: e8c0 4f45 strexb r5, r4, [r0] +10000dd2: 2d00 cmp r5, #0 +10000dd4: d1f6 bne.n 10000dc4 +10000dd6: f3bf 8f5f dmb sy +10000dda: f9b1 e002 ldrsh.w lr, [r1, #2] +10000dde: 694c ldr r4, [r1, #20] +10000de0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000de4: f1be 0f00 cmp.w lr, #0 +10000de8: ea4f 05cc mov.w r5, ip, lsl #3 +10000dec: 6908 ldr r0, [r1, #16] +10000dee: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000df2: db3c blt.n 10000e6e +10000df4: 5b66 ldrh r6, [r4, r5] +10000df6: 804e strh r6, [r1, #2] +10000df8: 2600 movs r6, #0 +10000dfa: e8c0 6f8f stlb r6, [r0] +10000dfe: f387 8810 msr PRIMASK, r7 +10000e02: f8bc 0002 ldrh.w r0, [ip, #2] +10000e06: e9cc 2302 strd r2, r3, [ip, #8] +10000e0a: 3001 adds r0, #1 +10000e0c: f3c0 000e ubfx r0, r0, #0, #15 +10000e10: 2801 cmp r0, #1 +10000e12: bf38 it cc +10000e14: 2001 movcc r0, #1 +10000e16: 9b05 ldr r3, [sp, #20] +10000e18: f8ac 0002 strh.w r0, [ip, #2] +10000e1c: f8cc 3010 str.w r3, [ip, #16] +10000e20: 9b06 ldr r3, [sp, #24] +10000e22: ea40 400e orr.w r0, r0, lr, lsl #16 +10000e26: f8cc 3014 str.w r3, [ip, #20] +10000e2a: 690b ldr r3, [r1, #16] +10000e2c: f3ef 8210 mrs r2, PRIMASK +10000e30: b672 cpsid i +10000e32: e8d3 cfcf ldaexb ip, [r3] +10000e36: 2701 movs r7, #1 +10000e38: f1bc 0f00 cmp.w ip, #0 +10000e3c: d1f9 bne.n 10000e32 +10000e3e: e8c3 7f4c strexb ip, r7, [r3] +10000e42: f1bc 0f00 cmp.w ip, #0 +10000e46: d1f4 bne.n 10000e32 +10000e48: f3bf 8f5f dmb sy +10000e4c: 888b ldrh r3, [r1, #4] +10000e4e: 5363 strh r3, [r4, r5] +10000e50: f8a1 e004 strh.w lr, [r1, #4] +10000e54: 690b ldr r3, [r1, #16] +10000e56: e8c3 6f8f stlb r6, [r3] +10000e5a: f382 8810 msr PRIMASK, r2 +10000e5e: 2201 movs r2, #1 +10000e60: 68cb ldr r3, [r1, #12] +10000e62: 7809 ldrb r1, [r1, #0] +10000e64: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000e68: 408a lsls r2, r1 +10000e6a: 605a str r2, [r3, #4] +10000e6c: bdf0 pop {r4, r5, r6, r7, pc} +10000e6e: 2300 movs r3, #0 +10000e70: e8c0 3f8f stlb r3, [r0] +10000e74: f387 8810 msr PRIMASK, r7 +10000e78: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000e7c: bdf0 pop {r4, r5, r6, r7, pc} +10000e7e: bf00 nop + +10000e80 : +10000e80: 4603 mov r3, r0 +10000e82: 8940 ldrh r0, [r0, #10] +10000e84: ebb0 4f21 cmp.w r0, r1, asr #16 +10000e88: dd37 ble.n 10000efa +10000e8a: 6958 ldr r0, [r3, #20] +10000e8c: 140a asrs r2, r1, #16 +10000e8e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000e92: b510 push {r4, lr} +10000e94: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000e98: 691c ldr r4, [r3, #16] +10000e9a: f3ef 8c10 mrs ip, PRIMASK +10000e9e: b672 cpsid i +10000ea0: e8d4 efcf ldaexb lr, [r4] +10000ea4: 2201 movs r2, #1 +10000ea6: f1be 0f00 cmp.w lr, #0 +10000eaa: d1f9 bne.n 10000ea0 +10000eac: e8c4 2f4e strexb lr, r2, [r4] +10000eb0: f1be 0f00 cmp.w lr, #0 +10000eb4: d1f4 bne.n 10000ea0 +10000eb6: f3bf 8f5f dmb sy +10000eba: 8842 ldrh r2, [r0, #2] +10000ebc: b289 uxth r1, r1 +10000ebe: b292 uxth r2, r2 +10000ec0: 428a cmp r2, r1 +10000ec2: d007 beq.n 10000ed4 +10000ec4: 2200 movs r2, #0 +10000ec6: 691b ldr r3, [r3, #16] +10000ec8: e8c3 2f8f stlb r2, [r3] +10000ecc: f38c 8810 msr PRIMASK, ip +10000ed0: 2000 movs r0, #0 +10000ed2: bd10 pop {r4, pc} +10000ed4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000ed8: 8042 strh r2, [r0, #2] +10000eda: 2101 movs r1, #1 +10000edc: 2200 movs r2, #0 +10000ede: 6918 ldr r0, [r3, #16] +10000ee0: 7199 strb r1, [r3, #6] +10000ee2: e8c0 2f8f stlb r2, [r0] +10000ee6: f38c 8810 msr PRIMASK, ip +10000eea: 781c ldrb r4, [r3, #0] +10000eec: 68da ldr r2, [r3, #12] +10000eee: 4608 mov r0, r1 +10000ef0: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000ef4: 40a1 lsls r1, r4 +10000ef6: 6059 str r1, [r3, #4] +10000ef8: bd10 pop {r4, pc} +10000efa: 2000 movs r0, #0 +10000efc: 4770 bx lr +10000efe: bf00 nop + +10000f00 : +10000f00: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000f04: b082 sub sp, #8 +10000f06: 4604 mov r4, r0 +10000f08: 460e mov r6, r1 +10000f0a: f000 f957 bl 100011bc +10000f0e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10000f12: f06f 4300 mvn.w r3, #2147483648 @ 0x80000000 +10000f16: 1824 adds r4, r4, r0 +10000f18: eb46 0601 adc.w r6, r6, r1 +10000f1c: 42a2 cmp r2, r4 +10000f1e: eb73 0106 sbcs.w r1, r3, r6 +10000f22: bf3c itt cc +10000f24: 4614 movcc r4, r2 +10000f26: 461e movcc r6, r3 +10000f28: 1fa5 subs r5, r4, #6 +10000f2a: f146 37ff adc.w r7, r6, #4294967295 @ 0xffffffff +10000f2e: 42ac cmp r4, r5 +10000f30: eb76 0307 sbcs.w r3, r6, r7 +10000f34: bf3c itt cc +10000f36: 2500 movcc r5, #0 +10000f38: 462f movcc r7, r5 +10000f3a: f000 f93f bl 100011bc +10000f3e: 1a28 subs r0, r5, r0 +10000f40: eb67 0c01 sbc.w ip, r7, r1 +10000f44: 2801 cmp r0, #1 +10000f46: f17c 0c00 sbcs.w ip, ip, #0 +10000f4a: da06 bge.n 10000f5a +10000f4c: 4620 mov r0, r4 +10000f4e: 4631 mov r1, r6 +10000f50: b002 add sp, #8 +10000f52: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000f56: f000 b969 b.w 1000122c +10000f5a: f000 f92f bl 100011bc +10000f5e: 4285 cmp r5, r0 +10000f60: eb67 0101 sbc.w r1, r7, r1 +10000f64: 2900 cmp r1, #0 +10000f66: db0a blt.n 10000f7e +10000f68: 2100 movs r1, #0 +10000f6a: 4b17 ldr r3, [pc, #92] @ (10000fc8 ) +10000f6c: 462a mov r2, r5 +10000f6e: 9300 str r3, [sp, #0] +10000f70: 4816 ldr r0, [pc, #88] @ (10000fcc ) +10000f72: 463b mov r3, r7 +10000f74: 9101 str r1, [sp, #4] +10000f76: f7ff ff1f bl 10000db8 +10000f7a: 3001 adds r0, #1 +10000f7c: d0e6 beq.n 10000f4c +10000f7e: f04f 0c00 mov.w ip, #0 +10000f82: 4a13 ldr r2, [pc, #76] @ (10000fd0 ) +10000f84: 4913 ldr r1, [pc, #76] @ (10000fd4 ) +10000f86: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f88: 429f cmp r7, r3 +10000f8a: d804 bhi.n 10000f96 +10000f8c: 6a90 ldr r0, [r2, #40] @ 0x28 +10000f8e: 42a8 cmp r0, r5 +10000f90: d2dc bcs.n 10000f4c +10000f92: 429f cmp r7, r3 +10000f94: d1da bne.n 10000f4c +10000f96: 680b ldr r3, [r1, #0] +10000f98: f3ef 8010 mrs r0, PRIMASK +10000f9c: b672 cpsid i +10000f9e: e8d3 8fcf ldaexb r8, [r3] +10000fa2: f05f 0e01 movs.w lr, #1 +10000fa6: f1b8 0f00 cmp.w r8, #0 +10000faa: d1f8 bne.n 10000f9e +10000fac: e8c3 ef48 strexb r8, lr, [r3] +10000fb0: f1b8 0f00 cmp.w r8, #0 +10000fb4: d1f3 bne.n 10000f9e +10000fb6: f3bf 8f5f dmb sy +10000fba: 680b ldr r3, [r1, #0] +10000fbc: e8c3 cf8f stlb ip, [r3] +10000fc0: f380 8810 msr PRIMASK, r0 +10000fc4: bf20 wfe +10000fc6: e7de b.n 10000f86 +10000fc8: 10000989 .word 0x10000989 +10000fcc: 2000096c .word 0x2000096c +10000fd0: 400b0000 .word 0x400b0000 +10000fd4: 20000bc4 .word 0x20000bc4 + +10000fd8 : +10000fd8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000fdc: b082 sub sp, #8 +10000fde: 4606 mov r6, r0 +10000fe0: f000 f8ec bl 100011bc +10000fe4: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000fe8: 4604 mov r4, r0 +10000fea: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000fee: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000ff2: fbe6 4103 umlal r4, r1, r6, r3 +10000ff6: 42a0 cmp r0, r4 +10000ff8: eb72 0301 sbcs.w r3, r2, r1 +10000ffc: bf3a itte cc +10000ffe: 4604 movcc r4, r0 +10001000: 4615 movcc r5, r2 +10001002: 460d movcs r5, r1 +10001004: 1fa6 subs r6, r4, #6 +10001006: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +1000100a: 42b4 cmp r4, r6 +1000100c: eb75 0307 sbcs.w r3, r5, r7 +10001010: bf3c itt cc +10001012: 2600 movcc r6, #0 +10001014: 4637 movcc r7, r6 +10001016: f000 f8d1 bl 100011bc +1000101a: 1a30 subs r0, r6, r0 +1000101c: eb67 0101 sbc.w r1, r7, r1 +10001020: 2801 cmp r0, #1 +10001022: f171 0100 sbcs.w r1, r1, #0 +10001026: da06 bge.n 10001036 +10001028: 4620 mov r0, r4 +1000102a: 4629 mov r1, r5 +1000102c: b002 add sp, #8 +1000102e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001032: f000 b8fb b.w 1000122c +10001036: f000 f8c1 bl 100011bc +1000103a: 4286 cmp r6, r0 +1000103c: eb67 0101 sbc.w r1, r7, r1 +10001040: 2900 cmp r1, #0 +10001042: db0a blt.n 1000105a +10001044: 2100 movs r1, #0 +10001046: 4b17 ldr r3, [pc, #92] @ (100010a4 ) +10001048: 4632 mov r2, r6 +1000104a: 9300 str r3, [sp, #0] +1000104c: 4816 ldr r0, [pc, #88] @ (100010a8 ) +1000104e: 463b mov r3, r7 +10001050: 9101 str r1, [sp, #4] +10001052: f7ff feb1 bl 10000db8 +10001056: 3001 adds r0, #1 +10001058: d0e6 beq.n 10001028 +1000105a: f04f 0c00 mov.w ip, #0 +1000105e: 4a13 ldr r2, [pc, #76] @ (100010ac ) +10001060: 4913 ldr r1, [pc, #76] @ (100010b0 ) +10001062: 6a53 ldr r3, [r2, #36] @ 0x24 +10001064: 429f cmp r7, r3 +10001066: d804 bhi.n 10001072 +10001068: 6a90 ldr r0, [r2, #40] @ 0x28 +1000106a: 42b0 cmp r0, r6 +1000106c: d2dc bcs.n 10001028 +1000106e: 429f cmp r7, r3 +10001070: d1da bne.n 10001028 +10001072: 680b ldr r3, [r1, #0] +10001074: f3ef 8010 mrs r0, PRIMASK +10001078: b672 cpsid i +1000107a: e8d3 8fcf ldaexb r8, [r3] +1000107e: f05f 0e01 movs.w lr, #1 +10001082: f1b8 0f00 cmp.w r8, #0 +10001086: d1f8 bne.n 1000107a +10001088: e8c3 ef48 strexb r8, lr, [r3] +1000108c: f1b8 0f00 cmp.w r8, #0 +10001090: d1f3 bne.n 1000107a +10001092: f3bf 8f5f dmb sy +10001096: 680b ldr r3, [r1, #0] +10001098: e8c3 cf8f stlb ip, [r3] +1000109c: f380 8810 msr PRIMASK, r0 +100010a0: bf20 wfe +100010a2: e7de b.n 10001062 +100010a4: 10000989 .word 0x10000989 +100010a8: 2000096c .word 0x2000096c +100010ac: 400b0000 .word 0x400b0000 +100010b0: 20000bc4 .word 0x20000bc4 + +100010b4 : +100010b4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100010b8: 4606 mov r6, r0 +100010ba: 460d mov r5, r1 +100010bc: b083 sub sp, #12 +100010be: f3ef 8405 mrs r4, IPSR +100010c2: b2e4 uxtb r4, r4 +100010c4: b13c cbz r4, 100010d6 +100010c6: 4b2d ldr r3, [pc, #180] @ (1000117c ) +100010c8: 6a5a ldr r2, [r3, #36] @ 0x24 +100010ca: 42aa cmp r2, r5 +100010cc: d21c bcs.n 10001108 +100010ce: 2000 movs r0, #0 +100010d0: b003 add sp, #12 +100010d2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100010d6: 4f2a ldr r7, [pc, #168] @ (10001180 ) +100010d8: f8d7 900c ldr.w r9, [r7, #12] +100010dc: f897 8000 ldrb.w r8, [r7] +100010e0: 4648 mov r0, r9 +100010e2: f000 f863 bl 100011ac +100010e6: f108 0804 add.w r8, r8, #4 +100010ea: f859 3028 ldr.w r3, [r9, r8, lsl #2] +100010ee: 1a1b subs r3, r3, r0 +100010f0: 1a30 subs r0, r6, r0 +100010f2: eb65 0101 sbc.w r1, r5, r1 +100010f6: 4298 cmp r0, r3 +100010f8: f171 0100 sbcs.w r1, r1, #0 +100010fc: db10 blt.n 10001120 +100010fe: bf20 wfe +10001100: 4b1e ldr r3, [pc, #120] @ (1000117c ) +10001102: 6a5a ldr r2, [r3, #36] @ 0x24 +10001104: 42aa cmp r2, r5 +10001106: d3e2 bcc.n 100010ce +10001108: bf14 ite ne +1000110a: 2401 movne r4, #1 +1000110c: 2400 moveq r4, #0 +1000110e: 6a9b ldr r3, [r3, #40] @ 0x28 +10001110: 42b3 cmp r3, r6 +10001112: bf34 ite cc +10001114: 4620 movcc r0, r4 +10001116: f044 0001 orrcs.w r0, r4, #1 +1000111a: b003 add sp, #12 +1000111c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10001120: f000 f84c bl 100011bc +10001124: 4286 cmp r6, r0 +10001126: eb65 0101 sbc.w r1, r5, r1 +1000112a: 2900 cmp r1, #0 +1000112c: db14 blt.n 10001158 +1000112e: 4b15 ldr r3, [pc, #84] @ (10001184 ) +10001130: 4638 mov r0, r7 +10001132: e9cd 3400 strd r3, r4, [sp] +10001136: 4632 mov r2, r6 +10001138: 462b mov r3, r5 +1000113a: f7ff fe3d bl 10000db8 +1000113e: 1e01 subs r1, r0, #0 +10001140: dd0a ble.n 10001158 +10001142: 4b0e ldr r3, [pc, #56] @ (1000117c ) +10001144: 6a5a ldr r2, [r3, #36] @ 0x24 +10001146: 42aa cmp r2, r5 +10001148: d316 bcc.n 10001178 +1000114a: 6a9b ldr r3, [r3, #40] @ 0x28 +1000114c: 42b3 cmp r3, r6 +1000114e: d311 bcc.n 10001174 +10001150: 480b ldr r0, [pc, #44] @ (10001180 ) +10001152: f7ff fe95 bl 10000e80 +10001156: e7b6 b.n 100010c6 +10001158: 4b08 ldr r3, [pc, #32] @ (1000117c ) +1000115a: 6a5c ldr r4, [r3, #36] @ 0x24 +1000115c: 42ac cmp r4, r5 +1000115e: d3b6 bcc.n 100010ce +10001160: 1b64 subs r4, r4, r5 +10001162: bf18 it ne +10001164: 2401 movne r4, #1 +10001166: 6a9b ldr r3, [r3, #40] @ 0x28 +10001168: 42b3 cmp r3, r6 +1000116a: bf34 ite cc +1000116c: 4620 movcc r0, r4 +1000116e: f044 0001 orrcs.w r0, r4, #1 +10001172: e7ad b.n 100010d0 +10001174: 42aa cmp r2, r5 +10001176: d1eb bne.n 10001150 +10001178: bf20 wfe +1000117a: e7e9 b.n 10001150 +1000117c: 400b0000 .word 0x400b0000 +10001180: 2000096c .word 0x2000096c +10001184: 10000989 .word 0x10000989 + +10001188 : +10001188: b410 push {r4} +1000118a: 4b05 ldr r3, [pc, #20] @ (100011a0 ) +1000118c: 4c05 ldr r4, [pc, #20] @ (100011a4 ) +1000118e: 4a06 ldr r2, [pc, #24] @ (100011a8 ) +10001190: 42a0 cmp r0, r4 +10001192: bf14 ite ne +10001194: 4618 movne r0, r3 +10001196: 1c58 addeq r0, r3, #1 +10001198: f85d 4b04 ldr.w r4, [sp], #4 +1000119c: f7ff b9be b.w 1000051c +100011a0: 20000b50 .word 0x20000b50 +100011a4: 400b8000 .word 0x400b8000 +100011a8: 100039dc .word 0x100039dc + +100011ac : +100011ac: 4603 mov r3, r0 +100011ae: 6a41 ldr r1, [r0, #36] @ 0x24 +100011b0: 460a mov r2, r1 +100011b2: 6a98 ldr r0, [r3, #40] @ 0x28 +100011b4: 6a59 ldr r1, [r3, #36] @ 0x24 +100011b6: 428a cmp r2, r1 +100011b8: d1fa bne.n 100011b0 +100011ba: 4770 bx lr + +100011bc : +100011bc: 4b03 ldr r3, [pc, #12] @ (100011cc ) +100011be: 6a59 ldr r1, [r3, #36] @ 0x24 +100011c0: 460a mov r2, r1 +100011c2: 6a98 ldr r0, [r3, #40] @ 0x28 +100011c4: 6a59 ldr r1, [r3, #36] @ 0x24 +100011c6: 4291 cmp r1, r2 +100011c8: d1fa bne.n 100011c0 +100011ca: 4770 bx lr +100011cc: 400b0000 .word 0x400b0000 + +100011d0 : +100011d0: b430 push {r4, r5} +100011d2: 4a15 ldr r2, [pc, #84] @ (10001228 ) +100011d4: 6a53 ldr r3, [r2, #36] @ 0x24 +100011d6: 469c mov ip, r3 +100011d8: 6a94 ldr r4, [r2, #40] @ 0x28 +100011da: 6a53 ldr r3, [r2, #36] @ 0x24 +100011dc: 4563 cmp r3, ip +100011de: d1fa bne.n 100011d6 +100011e0: 1902 adds r2, r0, r4 +100011e2: 4159 adcs r1, r3 +100011e4: f04f 0500 mov.w r5, #0 +100011e8: bf28 it cs +100011ea: 2501 movcs r5, #1 +100011ec: 4b0e ldr r3, [pc, #56] @ (10001228 ) +100011ee: 6a5b ldr r3, [r3, #36] @ 0x24 +100011f0: b1b5 cbz r5, 10001220 +100011f2: 1c5a adds r2, r3, #1 +100011f4: bf08 it eq +100011f6: 461a moveq r2, r3 +100011f8: d008 beq.n 1000120c +100011fa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100011fe: 460a mov r2, r1 +10001200: 4809 ldr r0, [pc, #36] @ (10001228 ) +10001202: 6a43 ldr r3, [r0, #36] @ 0x24 +10001204: 428b cmp r3, r1 +10001206: d3fc bcc.n 10001202 +10001208: 428b cmp r3, r1 +1000120a: d107 bne.n 1000121c +1000120c: 4906 ldr r1, [pc, #24] @ (10001228 ) +1000120e: e002 b.n 10001216 +10001210: 6a48 ldr r0, [r1, #36] @ 0x24 +10001212: 4298 cmp r0, r3 +10001214: d102 bne.n 1000121c +10001216: 6a88 ldr r0, [r1, #40] @ 0x28 +10001218: 4290 cmp r0, r2 +1000121a: d3f9 bcc.n 10001210 +1000121c: bc30 pop {r4, r5} +1000121e: 4770 bx lr +10001220: 4299 cmp r1, r3 +10001222: d8ed bhi.n 10001200 +10001224: e7f0 b.n 10001208 +10001226: bf00 nop +10001228: 400b0000 .word 0x400b0000 + +1000122c : +1000122c: 4a07 ldr r2, [pc, #28] @ (1000124c ) +1000122e: 6a53 ldr r3, [r2, #36] @ 0x24 +10001230: 4299 cmp r1, r3 +10001232: d8fc bhi.n 1000122e +10001234: 4299 cmp r1, r3 +10001236: d107 bne.n 10001248 +10001238: 4b04 ldr r3, [pc, #16] @ (1000124c ) +1000123a: e002 b.n 10001242 +1000123c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000123e: 4291 cmp r1, r2 +10001240: d102 bne.n 10001248 +10001242: 6a9a ldr r2, [r3, #40] @ 0x28 +10001244: 4290 cmp r0, r2 +10001246: d8f9 bhi.n 1000123c +10001248: 4770 bx lr +1000124a: bf00 nop +1000124c: 400b0000 .word 0x400b0000 + +10001250 : +10001250: b5f8 push {r3, r4, r5, r6, r7, lr} +10001252: 4605 mov r5, r0 +10001254: 2006 movs r0, #6 +10001256: 460e mov r6, r1 +10001258: f000 f8e4 bl 10001424 +1000125c: 2800 cmp r0, #0 +1000125e: d042 beq.n 100012e6 +10001260: 4a35 ldr r2, [pc, #212] @ (10001338 ) +10001262: 4836 ldr r0, [pc, #216] @ (1000133c ) +10001264: 4295 cmp r5, r2 +10001266: bf14 ite ne +10001268: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +1000126c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10001270: 4b33 ldr r3, [pc, #204] @ (10001340 ) +10001272: 4934 ldr r1, [pc, #208] @ (10001344 ) +10001274: 6002 str r2, [r0, #0] +10001276: 601a str r2, [r3, #0] +10001278: 688c ldr r4, [r1, #8] +1000127a: ea32 0404 bics.w r4, r2, r4 +1000127e: d1fb bne.n 10001278 +10001280: 4b2d ldr r3, [pc, #180] @ (10001338 ) +10001282: f44f 7180 mov.w r1, #256 @ 0x100 +10001286: 1aeb subs r3, r5, r3 +10001288: fab3 f383 clz r3, r3 +1000128c: 4a2e ldr r2, [pc, #184] @ (10001348 ) +1000128e: 095b lsrs r3, r3, #5 +10001290: 2006 movs r0, #6 +10001292: f822 1013 strh.w r1, [r2, r3, lsl #1] +10001296: f000 f8c5 bl 10001424 +1000129a: 00c3 lsls r3, r0, #3 +1000129c: fbb3 f3f6 udiv r3, r3, r6 +100012a0: 3301 adds r3, #1 +100012a2: 09da lsrs r2, r3, #7 +100012a4: d120 bne.n 100012e8 +100012a6: 2640 movs r6, #64 @ 0x40 +100012a8: 2101 movs r1, #1 +100012aa: 6269 str r1, [r5, #36] @ 0x24 +100012ac: 62aa str r2, [r5, #40] @ 0x28 +100012ae: 6b2f ldr r7, [r5, #48] @ 0x30 +100012b0: 07fb lsls r3, r7, #31 +100012b2: d422 bmi.n 100012fa +100012b4: 462b mov r3, r5 +100012b6: 2200 movs r2, #0 +100012b8: f853 1f2c ldr.w r1, [r3, #44]! +100012bc: 2006 movs r0, #6 +100012be: f503 5480 add.w r4, r3, #4096 @ 0x1000 +100012c2: 6022 str r2, [r4, #0] +100012c4: 632f str r7, [r5, #48] @ 0x30 +100012c6: f000 f8ad bl 10001424 +100012ca: f240 3101 movw r1, #769 @ 0x301 +100012ce: 2203 movs r2, #3 +100012d0: 0080 lsls r0, r0, #2 +100012d2: fbb0 f0f6 udiv r0, r0, r6 +100012d6: 6aeb ldr r3, [r5, #44] @ 0x2c +100012d8: f083 0370 eor.w r3, r3, #112 @ 0x70 +100012dc: f003 037e and.w r3, r3, #126 @ 0x7e +100012e0: 6023 str r3, [r4, #0] +100012e2: 6329 str r1, [r5, #48] @ 0x30 +100012e4: 64aa str r2, [r5, #72] @ 0x48 +100012e6: bdf8 pop {r3, r4, r5, r6, r7, pc} +100012e8: f64f 71fe movw r1, #65534 @ 0xfffe +100012ec: 428a cmp r2, r1 +100012ee: d91b bls.n 10001328 +100012f0: 4622 mov r2, r4 +100012f2: f64f 71ff movw r1, #65535 @ 0xffff +100012f6: 4e15 ldr r6, [pc, #84] @ (1000134c ) +100012f8: e7d7 b.n 100012aa +100012fa: f240 3201 movw r2, #769 @ 0x301 +100012fe: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10001302: 631a str r2, [r3, #48] @ 0x30 +10001304: 6a6b ldr r3, [r5, #36] @ 0x24 +10001306: 6aac ldr r4, [r5, #40] @ 0x28 +10001308: 2006 movs r0, #6 +1000130a: eb04 1483 add.w r4, r4, r3, lsl #6 +1000130e: f000 f889 bl 10001424 +10001312: 4b0f ldr r3, [pc, #60] @ (10001350 ) +10001314: 02a4 lsls r4, r4, #10 +10001316: fba3 2300 umull r2, r3, r3, r0 +1000131a: 0adb lsrs r3, r3, #11 +1000131c: 2100 movs r1, #0 +1000131e: fbb4 f0f3 udiv r0, r4, r3 +10001322: f7ff ff55 bl 100011d0 +10001326: e7c5 b.n 100012b4 +10001328: f3c3 0345 ubfx r3, r3, #1, #6 +1000132c: 4611 mov r1, r2 +1000132e: eb03 1682 add.w r6, r3, r2, lsl #6 +10001332: 461a mov r2, r3 +10001334: e7b9 b.n 100012aa +10001336: bf00 nop +10001338: 40078000 .word 0x40078000 +1000133c: 40022000 .word 0x40022000 +10001340: 40023000 .word 0x40023000 +10001344: 40020000 .word 0x40020000 +10001348: 20000bc8 .word 0x20000bc8 +1000134c: 003fffc0 .word 0x003fffc0 +10001350: 8f2b7b75 .word 0x8f2b7b75 + +10001354 : +10001354: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001358: ea4f 0c8c mov.w ip, ip, lsl #2 +1000135c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001360: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10001364: b5f0 push {r4, r5, r6, r7, lr} +10001366: 4616 mov r6, r2 +10001368: f8dc 2004 ldr.w r2, [ip, #4] +1000136c: 1f05 subs r5, r0, #4 +1000136e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10001372: bf38 it cc +10001374: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10001378: b2ed uxtb r5, r5 +1000137a: bf38 it cc +1000137c: f8cc 2004 strcc.w r2, [ip, #4] +10001380: 2d01 cmp r5, #1 +10001382: d92a bls.n 100013da +10001384: f44f 6700 mov.w r7, #2048 @ 0x800 +10001388: 4c25 ldr r4, [pc, #148] @ (10001420 ) +1000138a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000138e: 6017 str r7, [r2, #0] +10001390: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10001394: b9b2 cbnz r2, 100013c4 +10001396: f8dc 2000 ldr.w r2, [ip] +1000139a: 2d01 cmp r5, #1 +1000139c: ea82 1246 eor.w r2, r2, r6, lsl #5 +100013a0: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100013a4: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100013a8: 6032 str r2, [r6, #0] +100013aa: d92a bls.n 10001402 +100013ac: f44f 6100 mov.w r1, #2048 @ 0x800 +100013b0: f844 3020 str.w r3, [r4, r0, lsl #2] +100013b4: f44f 3380 mov.w r3, #65536 @ 0x10000 +100013b8: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100013bc: 6011 str r1, [r2, #0] +100013be: f8cc 3004 str.w r3, [ip, #4] +100013c2: bdf0 pop {r4, r5, r6, r7, pc} +100013c4: 6967 ldr r7, [r4, #20] +100013c6: fbb7 fef2 udiv lr, r7, r2 +100013ca: f10e 0e01 add.w lr, lr, #1 +100013ce: eb0e 0e4e add.w lr, lr, lr, lsl #1 +100013d2: f1be 0e03 subs.w lr, lr, #3 +100013d6: d2fc bcs.n 100013d2 +100013d8: e7dd b.n 10001396 +100013da: 2901 cmp r1, #1 +100013dc: d1d2 bne.n 10001384 +100013de: 2403 movs r4, #3 +100013e0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100013e4: 6014 str r4, [r2, #0] +100013e6: f8dc 2008 ldr.w r2, [ip, #8] +100013ea: 07d2 lsls r2, r2, #31 +100013ec: d5fb bpl.n 100013e6 +100013ee: f8dc 2000 ldr.w r2, [ip] +100013f2: 4c0b ldr r4, [pc, #44] @ (10001420 ) +100013f4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100013f8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100013fc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001400: 6032 str r2, [r6, #0] +10001402: 2201 movs r2, #1 +10001404: f8dc 5000 ldr.w r5, [ip] +10001408: 404d eors r5, r1 +1000140a: f005 0503 and.w r5, r5, #3 +1000140e: 6035 str r5, [r6, #0] +10001410: fa02 f101 lsl.w r1, r2, r1 +10001414: f8dc 2008 ldr.w r2, [ip, #8] +10001418: 420a tst r2, r1 +1000141a: d0fb beq.n 10001414 +1000141c: e7c6 b.n 100013ac +1000141e: bf00 nop +10001420: 20000b54 .word 0x20000b54 + +10001424 : +10001424: 4b01 ldr r3, [pc, #4] @ (1000142c ) +10001426: f853 0020 ldr.w r0, [r3, r0, lsl #2] +1000142a: 4770 bx lr +1000142c: 20000b54 .word 0x20000b54 + +10001430 : +10001430: b470 push {r4, r5, r6} +10001432: 9d03 ldr r5, [sp, #12] +10001434: 6804 ldr r4, [r0, #0] +10001436: 032d lsls r5, r5, #12 +10001438: ea45 4503 orr.w r5, r5, r3, lsl #16 +1000143c: 4b1b ldr r3, [pc, #108] @ (100014ac ) +1000143e: 2c00 cmp r4, #0 +10001440: fbb3 f3f1 udiv r3, r3, r1 +10001444: fbb2 f6f3 udiv r6, r2, r3 +10001448: db1f blt.n 1000148a +1000144a: 4a19 ldr r2, [pc, #100] @ (100014b0 ) +1000144c: 4b19 ldr r3, [pc, #100] @ (100014b4 ) +1000144e: 4290 cmp r0, r2 +10001450: bf14 ite ne +10001452: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001456: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000145a: 4c17 ldr r4, [pc, #92] @ (100014b8 ) +1000145c: 601a str r2, [r3, #0] +1000145e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001462: 601a str r2, [r3, #0] +10001464: 68a3 ldr r3, [r4, #8] +10001466: ea32 0303 bics.w r3, r2, r3 +1000146a: d1fb bne.n 10001464 +1000146c: 2221 movs r2, #33 @ 0x21 +1000146e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001472: 3304 adds r3, #4 +10001474: 6001 str r1, [r0, #0] +10001476: 6086 str r6, [r0, #8] +10001478: 601a str r2, [r3, #0] +1000147a: 6802 ldr r2, [r0, #0] +1000147c: 2a00 cmp r2, #0 +1000147e: dafc bge.n 1000147a +10001480: 2208 movs r2, #8 +10001482: 60c5 str r5, [r0, #12] +10001484: 601a str r2, [r3, #0] +10001486: bc70 pop {r4, r5, r6} +10001488: 4770 bx lr +1000148a: 6803 ldr r3, [r0, #0] +1000148c: f003 033f and.w r3, r3, #63 @ 0x3f +10001490: 428b cmp r3, r1 +10001492: d1da bne.n 1000144a +10001494: 6883 ldr r3, [r0, #8] +10001496: f3c3 030b ubfx r3, r3, #0, #12 +1000149a: 42b3 cmp r3, r6 +1000149c: d1d5 bne.n 1000144a +1000149e: 68c3 ldr r3, [r0, #12] +100014a0: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100014a4: 42ab cmp r3, r5 +100014a6: d1d0 bne.n 1000144a +100014a8: e7ed b.n 10001486 +100014aa: bf00 nop +100014ac: 00b71b00 .word 0x00b71b00 +100014b0: 40058000 .word 0x40058000 +100014b4: 40022000 .word 0x40022000 +100014b8: 40020000 .word 0x40020000 + +100014bc : +100014bc: 2301 movs r3, #1 +100014be: eb00 0040 add.w r0, r0, r0, lsl #1 +100014c2: 0080 lsls r0, r0, #2 +100014c4: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100014c8: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +100014cc: 6041 str r1, [r0, #4] +100014ce: 6003 str r3, [r0, #0] +100014d0: 4770 bx lr +100014d2: bf00 nop + +100014d4 : +100014d4: 2300 movs r3, #0 +100014d6: 8adb ldrh r3, [r3, #22] +100014d8: 2200 movs r2, #0 +100014da: e842 f200 tt r2, r2 +100014de: 0252 lsls r2, r2, #9 +100014e0: d401 bmi.n 100014e6 +100014e2: 2110 movs r1, #16 +100014e4: 4718 bx r3 +100014e6: 2104 movs r1, #4 +100014e8: 4718 bx r3 +100014ea: bf00 nop + +100014ec : +100014ec: 4a03 ldr r2, [pc, #12] @ (100014fc ) +100014ee: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100014f2: 2b00 cmp r3, #0 +100014f4: d0fb beq.n 100014ee +100014f6: f3bf 8f5f dmb sy +100014fa: 4770 bx lr +100014fc: 400e0000 .word 0x400e0000 + +10001500 : +10001500: 2100 movs r1, #0 +10001502: 4b04 ldr r3, [pc, #16] @ (10001514 ) +10001504: 4a04 ldr r2, [pc, #16] @ (10001518 ) +10001506: f3bf 8f5f dmb sy +1000150a: f843 1b04 str.w r1, [r3], #4 +1000150e: 4293 cmp r3, r2 +10001510: d1f9 bne.n 10001506 +10001512: 4770 bx lr +10001514: 400e080c .word 0x400e080c +10001518: 400e082c .word 0x400e082c + +1000151c : +1000151c: b410 push {r4} +1000151e: f44f 708d mov.w r0, #282 @ 0x11a +10001522: f44f 642a mov.w r4, #2720 @ 0xaa0 +10001526: 4a06 ldr r2, [pc, #24] @ (10001540 ) +10001528: 4b06 ldr r3, [pc, #24] @ (10001544 ) +1000152a: 4907 ldr r1, [pc, #28] @ (10001548 ) +1000152c: 6014 str r4, [r2, #0] +1000152e: 60d0 str r0, [r2, #12] +10001530: 6019 str r1, [r3, #0] +10001532: 6853 ldr r3, [r2, #4] +10001534: 2b00 cmp r3, #0 +10001536: dafc bge.n 10001532 +10001538: f85d 4b04 ldr.w r4, [sp], #4 +1000153c: 4770 bx lr +1000153e: bf00 nop +10001540: 40048000 .word 0x40048000 +10001544: 4004a000 .word 0x4004a000 +10001548: 00fab000 .word 0x00fab000 + +1000154c : +1000154c: 4770 bx lr +1000154e: bf00 nop + +10001550 : +10001550: b508 push {r3, lr} +10001552: 4801 ldr r0, [pc, #4] @ (10001558 ) +10001554: f7fe ffca bl 100004ec +10001558: 10003a00 .word 0x10003a00 + +1000155c : +1000155c: b538 push {r3, r4, r5, lr} +1000155e: 4c05 ldr r4, [pc, #20] @ (10001574 ) +10001560: 4d05 ldr r5, [pc, #20] @ (10001578 ) +10001562: 42ac cmp r4, r5 +10001564: d204 bcs.n 10001570 +10001566: f854 3b04 ldr.w r3, [r4], #4 +1000156a: 4798 blx r3 +1000156c: 42ac cmp r4, r5 +1000156e: d3fa bcc.n 10001566 +10001570: bd38 pop {r3, r4, r5, pc} +10001572: bf00 nop +10001574: 100038a0 .word 0x100038a0 +10001578: 100038e0 .word 0x100038e0 + +1000157c : +1000157c: b410 push {r4} +1000157e: 4807 ldr r0, [pc, #28] @ (1000159c ) +10001580: 4c07 ldr r4, [pc, #28] @ (100015a0 ) +10001582: 4b08 ldr r3, [pc, #32] @ (100015a4 ) +10001584: 4a08 ldr r2, [pc, #32] @ (100015a8 ) +10001586: 4909 ldr r1, [pc, #36] @ (100015ac ) +10001588: 6004 str r4, [r0, #0] +1000158a: 601a str r2, [r3, #0] +1000158c: 688b ldr r3, [r1, #8] +1000158e: ea32 0303 bics.w r3, r2, r3 +10001592: d1fb bne.n 1000158c +10001594: f85d 4b04 ldr.w r4, [sp], #4 +10001598: 4770 bx lr +1000159a: bf00 nop +1000159c: 40022000 .word 0x40022000 +100015a0: efef3b7f .word 0xefef3b7f +100015a4: 40023000 .word 0x40023000 +100015a8: 03f3fff6 .word 0x03f3fff6 +100015ac: 40020000 .word 0x40020000 + +100015b0 : +100015b0: 4b04 ldr r3, [pc, #16] @ (100015c4 ) +100015b2: 6cdb ldr r3, [r3, #76] @ 0x4c +100015b4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100015b8: d103 bne.n 100015c2 +100015ba: f44f 2280 mov.w r2, #262144 @ 0x40000 +100015be: 4b02 ldr r3, [pc, #8] @ (100015c8 ) +100015c0: 64da str r2, [r3, #76] @ 0x4c +100015c2: 4770 bx lr +100015c4: 50110000 .word 0x50110000 +100015c8: 50112000 .word 0x50112000 + +100015cc : +100015cc: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100015d0: 4b04 ldr r3, [pc, #16] @ (100015e4 ) +100015d2: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100015d6: 430b orrs r3, r1 +100015d8: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100015dc: ee10 0430 dcp_rcmp r0 +100015e0: 4770 bx lr +100015e2: bf00 nop +100015e4: 00300303 .word 0x00300303 + +100015e8 : +100015e8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100015ec: 4b04 ldr r3, [pc, #16] @ (10001600 ) +100015ee: 4a05 ldr r2, [pc, #20] @ (10001604 ) +100015f0: 6019 str r1, [r3, #0] +100015f2: 6893 ldr r3, [r2, #8] +100015f4: 43db mvns r3, r3 +100015f6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100015fa: d1fa bne.n 100015f2 +100015fc: 4770 bx lr +100015fe: bf00 nop +10001600: 40023000 .word 0x40023000 +10001604: 40020000 .word 0x40020000 + +10001608 : +10001608: b510 push {r4, lr} +1000160a: f245 2053 movw r0, #21075 @ 0x5253 +1000160e: f7ff ff61 bl 100014d4 +10001612: e8bd 4010 ldmia.w sp!, {r4, lr} +10001616: 4603 mov r3, r0 +10001618: 2004 movs r0, #4 +1000161a: 4718 bx r3 + +1000161c : +1000161c: b510 push {r4, lr} +1000161e: f245 2053 movw r0, #21075 @ 0x5253 +10001622: f7ff ff57 bl 100014d4 +10001626: e8bd 4010 ldmia.w sp!, {r4, lr} +1000162a: 4603 mov r3, r0 +1000162c: 2001 movs r0, #1 +1000162e: 4718 bx r3 + +10001630 : +10001630: f7fe bfb4 b.w 1000059c + +10001634 : +10001634: 4914 ldr r1, [pc, #80] @ (10001688 ) +10001636: 4b15 ldr r3, [pc, #84] @ (1000168c ) +10001638: b570 push {r4, r5, r6, lr} +1000163a: 1a5c subs r4, r3, r1 +1000163c: 10a6 asrs r6, r4, #2 +1000163e: 2e44 cmp r6, #68 @ 0x44 +10001640: 4632 mov r2, r6 +10001642: bf28 it cs +10001644: 2244 movcs r2, #68 @ 0x44 +10001646: 4d12 ldr r5, [pc, #72] @ (10001690 ) +10001648: 0092 lsls r2, r2, #2 +1000164a: 4628 mov r0, r5 +1000164c: f002 f872 bl 10003734 +10001650: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001654: d813 bhi.n 1000167e +10001656: 4a0f ldr r2, [pc, #60] @ (10001694 ) +10001658: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000165c: d012 beq.n 10001684 +1000165e: 192b adds r3, r5, r4 +10001660: 0841 lsrs r1, r0, #1 +10001662: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001666: e9c3 2200 strd r2, r2, [r3] +1000166a: 3308 adds r3, #8 +1000166c: 428b cmp r3, r1 +1000166e: d1fa bne.n 10001666 +10001670: 07c3 lsls r3, r0, #31 +10001672: d504 bpl.n 1000167e +10001674: f020 0001 bic.w r0, r0, #1 +10001678: 4430 add r0, r6 +1000167a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000167e: 4b06 ldr r3, [pc, #24] @ (10001698 ) +10001680: 609d str r5, [r3, #8] +10001682: bd70 pop {r4, r5, r6, pc} +10001684: 2043 movs r0, #67 @ 0x43 +10001686: e7f8 b.n 1000167a +10001688: 10000000 .word 0x10000000 +1000168c: 10000110 .word 0x10000110 +10001690: 20000000 .word 0x20000000 +10001694: 10000111 .word 0x10000111 +10001698: e000ed00 .word 0xe000ed00 + +1000169c : +1000169c: 2300 movs r3, #0 +1000169e: b570 push {r4, r5, r6, lr} +100016a0: 4c2b ldr r4, [pc, #172] @ (10001750 ) +100016a2: b082 sub sp, #8 +100016a4: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100016a8: f7ff ff38 bl 1000151c +100016ac: 2201 movs r2, #1 +100016ae: 4b29 ldr r3, [pc, #164] @ (10001754 ) +100016b0: 63da str r2, [r3, #60] @ 0x3c +100016b2: 6c63 ldr r3, [r4, #68] @ 0x44 +100016b4: 2b01 cmp r3, #1 +100016b6: d1fc bne.n 100016b2 +100016b8: 2103 movs r1, #3 +100016ba: 4a26 ldr r2, [pc, #152] @ (10001754 ) +100016bc: 4b24 ldr r3, [pc, #144] @ (10001750 ) +100016be: 6311 str r1, [r2, #48] @ 0x30 +100016c0: 6b9c ldr r4, [r3, #56] @ 0x38 +100016c2: 2c01 cmp r4, #1 +100016c4: d1fc bne.n 100016c0 +100016c6: 2602 movs r6, #2 +100016c8: 2505 movs r5, #5 +100016ca: 4621 mov r1, r4 +100016cc: 2305 movs r3, #5 +100016ce: 4a22 ldr r2, [pc, #136] @ (10001758 ) +100016d0: 4822 ldr r0, [pc, #136] @ (1000175c ) +100016d2: 9600 str r6, [sp, #0] +100016d4: f7ff feac bl 10001430 +100016d8: 4621 mov r1, r4 +100016da: 462b mov r3, r5 +100016dc: 4a20 ldr r2, [pc, #128] @ (10001760 ) +100016de: 4821 ldr r0, [pc, #132] @ (10001764 ) +100016e0: 9500 str r5, [sp, #0] +100016e2: f7ff fea5 bl 10001430 +100016e6: 2200 movs r2, #0 +100016e8: 2004 movs r0, #4 +100016ea: 4631 mov r1, r6 +100016ec: 4b1e ldr r3, [pc, #120] @ (10001768 ) +100016ee: f7ff fe31 bl 10001354 +100016f2: 4621 mov r1, r4 +100016f4: 4628 mov r0, r5 +100016f6: 2200 movs r2, #0 +100016f8: 4b1c ldr r3, [pc, #112] @ (1000176c ) +100016fa: f7ff fe2b bl 10001354 +100016fe: 2200 movs r2, #0 +10001700: 2008 movs r0, #8 +10001702: 4611 mov r1, r2 +10001704: 4b1a ldr r3, [pc, #104] @ (10001770 ) +10001706: f7ff fe25 bl 10001354 +1000170a: 2200 movs r2, #0 +1000170c: 2009 movs r0, #9 +1000170e: 4611 mov r1, r2 +10001710: 4b17 ldr r3, [pc, #92] @ (10001770 ) +10001712: f7ff fe1f bl 10001354 +10001716: 2200 movs r2, #0 +10001718: 2006 movs r0, #6 +1000171a: 4611 mov r1, r2 +1000171c: 4b13 ldr r3, [pc, #76] @ (1000176c ) +1000171e: f7ff fe19 bl 10001354 +10001722: 2200 movs r2, #0 +10001724: 4b11 ldr r3, [pc, #68] @ (1000176c ) +10001726: 2007 movs r0, #7 +10001728: 4611 mov r1, r2 +1000172a: f7ff fe13 bl 10001354 +1000172e: 2004 movs r0, #4 +10001730: f7ff fe78 bl 10001424 +10001734: 2400 movs r4, #0 +10001736: 4b0f ldr r3, [pc, #60] @ (10001774 ) +10001738: fba3 3500 umull r3, r5, r3, r0 +1000173c: 0cad lsrs r5, r5, #18 +1000173e: b2e0 uxtb r0, r4 +10001740: 4629 mov r1, r5 +10001742: 3401 adds r4, #1 +10001744: f7ff feba bl 100014bc +10001748: 2c06 cmp r4, #6 +1000174a: d1f8 bne.n 1000173e +1000174c: b002 add sp, #8 +1000174e: bd70 pop {r4, r5, r6, pc} +10001750: 40010000 .word 0x40010000 +10001754: 40013000 .word 0x40013000 +10001758: 59682f00 .word 0x59682f00 +1000175c: 40050000 .word 0x40050000 +10001760: 47868c00 .word 0x47868c00 +10001764: 40058000 .word 0x40058000 +10001768: 00b71b00 .word 0x00b71b00 +1000176c: 08f0d180 .word 0x08f0d180 +10001770: 02dc6c00 .word 0x02dc6c00 +10001774: 431bde83 .word 0x431bde83 + +10001778 : +10001778: b086 sub sp, #24 +1000177a: b403 push {r0, r1} +1000177c: fc51 0408 dcp_pxmd r0, r1 +10001780: e9cd 0102 strd r0, r1, [sp, #8] +10001784: fc51 0409 dcp_pymd r0, r1 +10001788: e9cd 0104 strd r0, r1, [sp, #16] +1000178c: ec51 040a dcp_refd r0, r1 +10001790: e9cd 0106 strd r0, r1, [sp, #24] +10001794: bc03 pop {r0, r1} +10001796: 47f0 blx lr + +10001798 : +10001798: e8bd 5000 ldmia.w sp!, {ip, lr} +1000179c: ec4e c400 dcp_wxmd ip, lr +100017a0: e8bd 5000 ldmia.w sp!, {ip, lr} +100017a4: ec4e c401 dcp_wymd ip, lr +100017a8: e8bd 5000 ldmia.w sp!, {ip, lr} +100017ac: ec4e c402 dcp_wefd ip, lr +100017b0: bd00 pop {pc} +100017b2: 0000 movs r0, r0 +100017b4: b500 push {lr} +100017b6: f7ff ffdf bl 10001778 +100017ba: e002 b.n 100017c2 <__wrap___aeabi_dadd+0x6> + +100017bc <__wrap___aeabi_dadd>: +100017bc: fe10 f430 dcp_pcmp APSR_nzcv +100017c0: d4f8 bmi.n 100017b4 +100017c2: ec41 0410 dcp_wxup r0, r1 +100017c6: ec43 2411 dcp_wyup r2, r3 +100017ca: ee00 0401 dcp_add0 +100017ce: ee10 0401 dcp_add1 +100017d2: ee80 0420 dcp_nrdd +100017d6: ec51 0410 dcp_rdda r0, r1 +100017da: 4770 bx lr +100017dc: b500 push {lr} +100017de: f7ff ffcb bl 10001778 +100017e2: e002 b.n 100017ea <__wrap___aeabi_dsub+0x6> + +100017e4 <__wrap___aeabi_dsub>: +100017e4: fe10 f430 dcp_pcmp APSR_nzcv +100017e8: d4f8 bmi.n 100017dc <__wrap___aeabi_dadd+0x20> +100017ea: ec41 0410 dcp_wxup r0, r1 +100017ee: ec43 2411 dcp_wyup r2, r3 +100017f2: ee00 0401 dcp_add0 +100017f6: ee10 0421 dcp_sub1 +100017fa: ee80 0420 dcp_nrdd +100017fe: ec51 0430 dcp_rdds r0, r1 +10001802: 4770 bx lr +10001804: b500 push {lr} +10001806: f7ff ffb7 bl 10001778 +1000180a: e002 b.n 10001812 <__wrap___aeabi_dmul+0x6> + +1000180c <__wrap___aeabi_dmul>: +1000180c: fe10 f430 dcp_pcmp APSR_nzcv +10001810: d4f8 bmi.n 10001804 <__wrap___aeabi_dsub+0x20> +10001812: b510 push {r4, lr} +10001814: ec41 0410 dcp_wxup r0, r1 +10001818: ec43 2411 dcp_wyup r2, r3 +1000181c: ec51 0404 dcp_rxms r0, r1, #0x0 +10001820: ec53 2405 dcp_ryms r2, r3, #0x0 +10001824: fba0 4c02 umull r4, ip, r0, r2 +10001828: f05f 0e00 movs.w lr, #0 +1000182c: fbe0 ce03 umlal ip, lr, r0, r3 +10001830: fbe1 ce02 umlal ip, lr, r1, r2 +10001834: ec4c 4420 dcp_wxms r4, ip +10001838: 2400 movs r4, #0 +1000183a: fbe1 e403 umlal lr, r4, r1, r3 +1000183e: ec44 e430 dcp_wxmo lr, r4 +10001842: ee80 0420 dcp_nrdd +10001846: ec51 0450 dcp_rddm r0, r1 +1000184a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000184e: 4770 bx lr +10001850: b500 push {lr} +10001852: f7ff ff91 bl 10001778 +10001856: e002 b.n 1000185e <__wrap___aeabi_ddiv+0x6> + +10001858 <__wrap___aeabi_ddiv>: +10001858: fe10 f430 dcp_pcmp APSR_nzcv +1000185c: d4f8 bmi.n 10001850 <__wrap___aeabi_dmul+0x44> +1000185e: ec41 0410 dcp_wxup r0, r1 +10001862: ec43 2411 dcp_wyup r2, r3 +10001866: ec51 0421 dcp_rymr r0, r1 +1000186a: fba0 1201 umull r1, r2, r0, r1 +1000186e: ea6f 0282 mvn.w r2, r2, lsl #2 +10001872: fb52 0010 smmlar r0, r2, r0, r0 +10001876: fb52 f212 smmulr r2, r2, r2 +1000187a: fb52 0010 smmlar r0, r2, r0, r0 +1000187e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001882: ec53 2404 dcp_rxms r2, r3, #0x0 +10001886: fb5c f113 smmulr r1, ip, r3 +1000188a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000188e: fba1 2002 umull r2, r0, r1, r2 +10001892: fb01 0003 mla r0, r1, r3, r0 +10001896: ec53 2444 dcp_rxms r2, r3, #0x4 +1000189a: eba2 0000 sub.w r0, r2, r0 +1000189e: fb50 f21c smmulr r2, r0, ip +100018a2: ea4f 1311 mov.w r3, r1, lsr #4 +100018a6: eb12 7001 adds.w r0, r2, r1, lsl #28 +100018aa: eb43 71e2 adc.w r1, r3, r2, asr #31 +100018ae: ea40 5051 orr.w r0, r0, r1, lsr #21 +100018b2: ea20 5091 bic.w r0, r0, r1, lsr #22 +100018b6: f020 0007 bic.w r0, r0, #7 +100018ba: ec53 2475 dcp_ryms r2, r3, #0x7 +100018be: fba0 3c02 umull r3, ip, r0, r2 +100018c2: ec53 2475 dcp_ryms r2, r3, #0x7 +100018c6: fb00 cc03 mla ip, r0, r3, ip +100018ca: fb01 cc02 mla ip, r1, r2, ip +100018ce: ec53 2404 dcp_rxms r2, r3, #0x0 +100018d2: ebac 4c82 sub.w ip, ip, r2, lsl #18 +100018d6: ea40 705c orr.w r0, r0, ip, lsr #29 +100018da: f1a0 0001 sub.w r0, r0, #1 +100018de: ec41 0440 dcp_wxdd r0, r1 +100018e2: ee80 0420 dcp_nrdd +100018e6: ec51 0470 dcp_rddd r0, r1 +100018ea: 4770 bx lr +100018ec: b500 push {lr} +100018ee: f7ff ff43 bl 10001778 +100018f2: e002 b.n 100018fa <__wrap___aeabi_i2d+0x6> + +100018f4 <__wrap___aeabi_i2d>: +100018f4: fe10 f430 dcp_pcmp APSR_nzcv +100018f8: d4f8 bmi.n 100018ec <__wrap___aeabi_ddiv+0x94> +100018fa: ec40 0470 dcp_wxic r0, r0 +100018fe: ee00 0401 dcp_add0 +10001902: ee10 0421 dcp_sub1 +10001906: ee80 0420 dcp_nrdd +1000190a: ec51 0430 dcp_rdds r0, r1 +1000190e: 4770 bx lr +10001910: b500 push {lr} +10001912: f7ff ff31 bl 10001778 +10001916: e002 b.n 1000191e <__wrap___aeabi_ui2d+0x6> + +10001918 <__wrap___aeabi_ui2d>: +10001918: fe10 f430 dcp_pcmp APSR_nzcv +1000191c: d4f8 bmi.n 10001910 <__wrap___aeabi_i2d+0x1c> +1000191e: ec40 0460 dcp_wxuc r0, r0 +10001922: ee00 0401 dcp_add0 +10001926: ee10 0421 dcp_sub1 +1000192a: ee80 0420 dcp_nrdd +1000192e: ec51 0430 dcp_rdds r0, r1 +10001932: 4770 bx lr +10001934: b500 push {lr} +10001936: f7ff ff1f bl 10001778 +1000193a: e002 b.n 10001942 + +1000193c <__wrap___aeabi_d2iz>: +1000193c: fe10 f430 dcp_pcmp APSR_nzcv +10001940: d4f8 bmi.n 10001934 <__wrap___aeabi_ui2d+0x1c> + +10001942 : +10001942: ec41 0480 dcp_wxdc r0, r1 +10001946: ee00 0401 dcp_add0 +1000194a: ee10 0401 dcp_add1 +1000194e: ee80 0440 dcp_ntdc +10001952: ee10 0413 dcp_rdic r0 +10001956: 4770 bx lr +10001958: b500 push {lr} +1000195a: f7ff ff0d bl 10001778 +1000195e: e002 b.n 10001966 + +10001960 <__wrap___aeabi_d2uiz>: +10001960: fe10 f430 dcp_pcmp APSR_nzcv +10001964: d4f8 bmi.n 10001958 + +10001966 : +10001966: ec41 0480 dcp_wxdc r0, r1 +1000196a: ee00 0401 dcp_add0 +1000196e: ee10 0401 dcp_add1 +10001972: ee80 0440 dcp_ntdc +10001976: ee10 0433 dcp_rduc r0 +1000197a: 4770 bx lr +1000197c: b500 push {lr} +1000197e: f7ff fefb bl 10001778 +10001982: e002 b.n 1000198a <__wrap___aeabi_dcmpun+0x6> + +10001984 <__wrap___aeabi_dcmpun>: +10001984: fe10 f430 dcp_pcmp APSR_nzcv +10001988: d4f8 bmi.n 1000197c +1000198a: ec41 0410 dcp_wxup r0, r1 +1000198e: ec43 2411 dcp_wyup r2, r3 +10001992: ee00 0401 dcp_add0 +10001996: ee10 0430 dcp_rcmp r0 +1000199a: f3c0 7000 ubfx r0, r0, #28, #1 +1000199e: 4770 bx lr +100019a0: b500 push {lr} +100019a2: f7ff fee9 bl 10001778 +100019a6: e002 b.n 100019ae <__wrap___aeabi_dcmplt+0x6> + +100019a8 <__wrap___aeabi_dcmplt>: +100019a8: fe10 f430 dcp_pcmp APSR_nzcv +100019ac: d4f8 bmi.n 100019a0 <__wrap___aeabi_dcmpun+0x1c> +100019ae: ec43 2410 dcp_wxup r2, r3 +100019b2: ec41 0411 dcp_wyup r0, r1 +100019b6: ee00 0401 dcp_add0 +100019ba: ee10 f430 dcp_rcmp APSR_nzcv +100019be: bf8c ite hi +100019c0: 2001 movhi r0, #1 +100019c2: 2000 movls r0, #0 +100019c4: 4770 bx lr +100019c6: bf00 nop +100019c8: b500 push {lr} +100019ca: f7ff fed5 bl 10001778 +100019ce: e002 b.n 100019d6 <__wrap___aeabi_dcmple+0x6> + +100019d0 <__wrap___aeabi_dcmple>: +100019d0: fe10 f430 dcp_pcmp APSR_nzcv +100019d4: d4f8 bmi.n 100019c8 <__wrap___aeabi_dcmplt+0x20> +100019d6: ec43 2410 dcp_wxup r2, r3 +100019da: ec41 0411 dcp_wyup r0, r1 +100019de: ee00 0401 dcp_add0 +100019e2: ee10 f430 dcp_rcmp APSR_nzcv +100019e6: bf2c ite cs +100019e8: 2001 movcs r0, #1 +100019ea: 2000 movcc r0, #0 +100019ec: 4770 bx lr +100019ee: bf00 nop +100019f0: b500 push {lr} +100019f2: f7ff fec1 bl 10001778 +100019f6: e002 b.n 100019fe <__wrap___aeabi_dcmpge+0x6> + +100019f8 <__wrap___aeabi_dcmpge>: +100019f8: fe10 f430 dcp_pcmp APSR_nzcv +100019fc: d4f8 bmi.n 100019f0 <__wrap___aeabi_dcmple+0x20> +100019fe: ec41 0410 dcp_wxup r0, r1 +10001a02: ec43 2411 dcp_wyup r2, r3 +10001a06: ee00 0401 dcp_add0 +10001a0a: ee10 f430 dcp_rcmp APSR_nzcv +10001a0e: bf2c ite cs +10001a10: 2001 movcs r0, #1 +10001a12: 2000 movcc r0, #0 +10001a14: 4770 bx lr +10001a16: bf00 nop +10001a18: b500 push {lr} +10001a1a: f7ff fead bl 10001778 +10001a1e: e002 b.n 10001a26 <__wrap___aeabi_dcmpgt+0x6> + +10001a20 <__wrap___aeabi_dcmpgt>: +10001a20: fe10 f430 dcp_pcmp APSR_nzcv +10001a24: d4f8 bmi.n 10001a18 <__wrap___aeabi_dcmpge+0x20> +10001a26: ec41 0410 dcp_wxup r0, r1 +10001a2a: ec43 2411 dcp_wyup r2, r3 +10001a2e: ee00 0401 dcp_add0 +10001a32: ee10 f430 dcp_rcmp APSR_nzcv +10001a36: bf8c ite hi +10001a38: 2001 movhi r0, #1 +10001a3a: 2000 movls r0, #0 +10001a3c: 4770 bx lr +10001a3e: bf00 nop + +10001a40 <_out_null>: +10001a40: 4770 bx lr +10001a42: bf00 nop + +10001a44 <_out_rev>: +10001a44: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a48: b083 sub sp, #12 +10001a4a: 4699 mov r9, r3 +10001a4c: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001a50: 9b0f ldr r3, [sp, #60] @ 0x3c +10001a52: 4688 mov r8, r1 +10001a54: 4611 mov r1, r2 +10001a56: 079a lsls r2, r3, #30 +10001a58: 4607 mov r7, r0 +10001a5a: d116 bne.n 10001a8a <_out_rev+0x46> +10001a5c: 45da cmp sl, fp +10001a5e: d23a bcs.n 10001ad6 <_out_rev+0x92> +10001a60: 460c mov r4, r1 +10001a62: 460d mov r5, r1 +10001a64: ebab 060a sub.w r6, fp, sl +10001a68: 440e add r6, r1 +10001a6a: 4622 mov r2, r4 +10001a6c: 464b mov r3, r9 +10001a6e: 4641 mov r1, r8 +10001a70: 2020 movs r0, #32 +10001a72: 3401 adds r4, #1 +10001a74: 47b8 blx r7 +10001a76: 42b4 cmp r4, r6 +10001a78: d1f7 bne.n 10001a6a <_out_rev+0x26> +10001a7a: 4629 mov r1, r5 +10001a7c: f1ba 0f00 cmp.w sl, #0 +10001a80: d108 bne.n 10001a94 <_out_rev+0x50> +10001a82: 4620 mov r0, r4 +10001a84: b003 add sp, #12 +10001a86: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001a8a: 460c mov r4, r1 +10001a8c: f1ba 0f00 cmp.w sl, #0 +10001a90: d010 beq.n 10001ab4 <_out_rev+0x70> +10001a92: 460e mov r6, r1 +10001a94: 4655 mov r5, sl +10001a96: 9b0c ldr r3, [sp, #48] @ 0x30 +10001a98: 442e add r6, r5 +10001a9a: 449a add sl, r3 +10001a9c: 9101 str r1, [sp, #4] +10001a9e: 1b72 subs r2, r6, r5 +10001aa0: 464b mov r3, r9 +10001aa2: 3d01 subs r5, #1 +10001aa4: 4641 mov r1, r8 +10001aa6: f81a 0d01 ldrb.w r0, [sl, #-1]! +10001aaa: 4634 mov r4, r6 +10001aac: 47b8 blx r7 +10001aae: 2d00 cmp r5, #0 +10001ab0: d1f5 bne.n 10001a9e <_out_rev+0x5a> +10001ab2: 9901 ldr r1, [sp, #4] +10001ab4: 9b0f ldr r3, [sp, #60] @ 0x3c +10001ab6: 079b lsls r3, r3, #30 +10001ab8: d5e3 bpl.n 10001a82 <_out_rev+0x3e> +10001aba: 1a65 subs r5, r4, r1 +10001abc: 45ab cmp fp, r5 +10001abe: d9e0 bls.n 10001a82 <_out_rev+0x3e> +10001ac0: 4622 mov r2, r4 +10001ac2: 464b mov r3, r9 +10001ac4: 4641 mov r1, r8 +10001ac6: 2020 movs r0, #32 +10001ac8: 3501 adds r5, #1 +10001aca: 47b8 blx r7 +10001acc: 455d cmp r5, fp +10001ace: f104 0401 add.w r4, r4, #1 +10001ad2: d3f5 bcc.n 10001ac0 <_out_rev+0x7c> +10001ad4: e7d5 b.n 10001a82 <_out_rev+0x3e> +10001ad6: 460c mov r4, r1 +10001ad8: f1ba 0f00 cmp.w sl, #0 +10001adc: d1d9 bne.n 10001a92 <_out_rev+0x4e> +10001ade: e7d0 b.n 10001a82 <_out_rev+0x3e> + +10001ae0 <_ntoa_format>: +10001ae0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ae4: 9f0f ldr r7, [sp, #60] @ 0x3c +10001ae6: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001aea: f017 0f02 tst.w r7, #2 +10001aee: 9c0a ldr r4, [sp, #40] @ 0x28 +10001af0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001af4: 9d0e ldr r5, [sp, #56] @ 0x38 +10001af6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001afa: d144 bne.n 10001b86 <_ntoa_format+0xa6> +10001afc: bbf5 cbnz r5, 10001b7c <_ntoa_format+0x9c> +10001afe: 42b4 cmp r4, r6 +10001b00: d241 bcs.n 10001b86 <_ntoa_format+0xa6> +10001b02: f007 0b01 and.w fp, r7, #1 +10001b06: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001b0a: f04f 0e30 mov.w lr, #48 @ 0x30 +10001b0e: 44c4 add ip, r8 +10001b10: e004 b.n 10001b1c <_ntoa_format+0x3c> +10001b12: 3401 adds r4, #1 +10001b14: 42a6 cmp r6, r4 +10001b16: f80c ef01 strb.w lr, [ip, #1]! +10001b1a: d901 bls.n 10001b20 <_ntoa_format+0x40> +10001b1c: 2c20 cmp r4, #32 +10001b1e: d1f8 bne.n 10001b12 <_ntoa_format+0x32> +10001b20: f1bb 0f00 cmp.w fp, #0 +10001b24: f000 8088 beq.w 10001c38 <_ntoa_format+0x158> +10001b28: 42a5 cmp r5, r4 +10001b2a: d92c bls.n 10001b86 <_ntoa_format+0xa6> +10001b2c: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001b30: f04f 0e30 mov.w lr, #48 @ 0x30 +10001b34: 44c4 add ip, r8 +10001b36: e004 b.n 10001b42 <_ntoa_format+0x62> +10001b38: 3401 adds r4, #1 +10001b3a: 42ac cmp r4, r5 +10001b3c: f80c ef01 strb.w lr, [ip, #1]! +10001b40: d021 beq.n 10001b86 <_ntoa_format+0xa6> +10001b42: 2c20 cmp r4, #32 +10001b44: d1f8 bne.n 10001b38 <_ntoa_format+0x58> +10001b46: f017 0f10 tst.w r7, #16 +10001b4a: d00e beq.n 10001b6a <_ntoa_format+0x8a> +10001b4c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001b50: d154 bne.n 10001bfc <_ntoa_format+0x11c> +10001b52: 42a6 cmp r6, r4 +10001b54: d063 beq.n 10001c1e <_ntoa_format+0x13e> +10001b56: 42a5 cmp r5, r4 +10001b58: d061 beq.n 10001c1e <_ntoa_format+0x13e> +10001b5a: f1b9 0f10 cmp.w r9, #16 +10001b5e: d050 beq.n 10001c02 <_ntoa_format+0x122> +10001b60: f1b9 0f02 cmp.w r9, #2 +10001b64: d056 beq.n 10001c14 <_ntoa_format+0x134> +10001b66: 2c20 cmp r4, #32 +10001b68: d129 bne.n 10001bbe <_ntoa_format+0xde> +10001b6a: 2420 movs r4, #32 +10001b6c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001b70: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001b74: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b78: f7ff bf64 b.w 10001a44 <_out_rev> +10001b7c: f017 0b01 ands.w fp, r7, #1 +10001b80: d134 bne.n 10001bec <_ntoa_format+0x10c> +10001b82: 42b4 cmp r4, r6 +10001b84: d3bf bcc.n 10001b06 <_ntoa_format+0x26> +10001b86: f017 0f10 tst.w r7, #16 +10001b8a: d01e beq.n 10001bca <_ntoa_format+0xea> +10001b8c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001b90: d1e3 bne.n 10001b5a <_ntoa_format+0x7a> +10001b92: 2c00 cmp r4, #0 +10001b94: d1dd bne.n 10001b52 <_ntoa_format+0x72> +10001b96: f1b9 0f10 cmp.w r9, #16 +10001b9a: d063 beq.n 10001c64 <_ntoa_format+0x184> +10001b9c: f1b9 0f02 cmp.w r9, #2 +10001ba0: d077 beq.n 10001c92 <_ntoa_format+0x1b2> +10001ba2: 2430 movs r4, #48 @ 0x30 +10001ba4: f888 4000 strb.w r4, [r8] +10001ba8: 2401 movs r4, #1 +10001baa: f1ba 0f00 cmp.w sl, #0 +10001bae: d111 bne.n 10001bd4 <_ntoa_format+0xf4> +10001bb0: 077e lsls r6, r7, #29 +10001bb2: d548 bpl.n 10001c46 <_ntoa_format+0x166> +10001bb4: 262b movs r6, #43 @ 0x2b +10001bb6: f808 6004 strb.w r6, [r8, r4] +10001bba: 3401 adds r4, #1 +10001bbc: e7d6 b.n 10001b6c <_ntoa_format+0x8c> +10001bbe: 4626 mov r6, r4 +10001bc0: 3401 adds r4, #1 +10001bc2: f04f 0c30 mov.w ip, #48 @ 0x30 +10001bc6: f808 c006 strb.w ip, [r8, r6] +10001bca: 2c20 cmp r4, #32 +10001bcc: d0cd beq.n 10001b6a <_ntoa_format+0x8a> +10001bce: f1ba 0f00 cmp.w sl, #0 +10001bd2: d0ed beq.n 10001bb0 <_ntoa_format+0xd0> +10001bd4: 262d movs r6, #45 @ 0x2d +10001bd6: f808 6004 strb.w r6, [r8, r4] +10001bda: 3401 adds r4, #1 +10001bdc: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001be0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001be4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001be8: f7ff bf2c b.w 10001a44 <_out_rev> +10001bec: f1ba 0f00 cmp.w sl, #0 +10001bf0: d030 beq.n 10001c54 <_ntoa_format+0x174> +10001bf2: 42b4 cmp r4, r6 +10001bf4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001bf8: d385 bcc.n 10001b06 <_ntoa_format+0x26> +10001bfa: e795 b.n 10001b28 <_ntoa_format+0x48> +10001bfc: f1b9 0f10 cmp.w r9, #16 +10001c00: d1b3 bne.n 10001b6a <_ntoa_format+0x8a> +10001c02: 06be lsls r6, r7, #26 +10001c04: d53b bpl.n 10001c7e <_ntoa_format+0x19e> +10001c06: 2c20 cmp r4, #32 +10001c08: d0af beq.n 10001b6a <_ntoa_format+0x8a> +10001c0a: 2658 movs r6, #88 @ 0x58 +10001c0c: f808 6004 strb.w r6, [r8, r4] +10001c10: 3401 adds r4, #1 +10001c12: e7a8 b.n 10001b66 <_ntoa_format+0x86> +10001c14: 2c20 cmp r4, #32 +10001c16: d0a8 beq.n 10001b6a <_ntoa_format+0x8a> +10001c18: 4626 mov r6, r4 +10001c1a: 3401 adds r4, #1 +10001c1c: e007 b.n 10001c2e <_ntoa_format+0x14e> +10001c1e: 1e66 subs r6, r4, #1 +10001c20: d0b9 beq.n 10001b96 <_ntoa_format+0xb6> +10001c22: f1b9 0f10 cmp.w r9, #16 +10001c26: d036 beq.n 10001c96 <_ntoa_format+0x1b6> +10001c28: f1b9 0f02 cmp.w r9, #2 +10001c2c: d1c9 bne.n 10001bc2 <_ntoa_format+0xe2> +10001c2e: f04f 0c62 mov.w ip, #98 @ 0x62 +10001c32: f808 c006 strb.w ip, [r8, r6] +10001c36: e796 b.n 10001b66 <_ntoa_format+0x86> +10001c38: f017 0f10 tst.w r7, #16 +10001c3c: d0c5 beq.n 10001bca <_ntoa_format+0xea> +10001c3e: f417 6f80 tst.w r7, #1024 @ 0x400 +10001c42: d086 beq.n 10001b52 <_ntoa_format+0x72> +10001c44: e789 b.n 10001b5a <_ntoa_format+0x7a> +10001c46: 073e lsls r6, r7, #28 +10001c48: d590 bpl.n 10001b6c <_ntoa_format+0x8c> +10001c4a: 2620 movs r6, #32 +10001c4c: f808 6004 strb.w r6, [r8, r4] +10001c50: 3401 adds r4, #1 +10001c52: e78b b.n 10001b6c <_ntoa_format+0x8c> +10001c54: f017 0f0c tst.w r7, #12 +10001c58: d000 beq.n 10001c5c <_ntoa_format+0x17c> +10001c5a: 3d01 subs r5, #1 +10001c5c: 42b4 cmp r4, r6 +10001c5e: f4ff af52 bcc.w 10001b06 <_ntoa_format+0x26> +10001c62: e761 b.n 10001b28 <_ntoa_format+0x48> +10001c64: 06bc lsls r4, r7, #26 +10001c66: d412 bmi.n 10001c8e <_ntoa_format+0x1ae> +10001c68: 2478 movs r4, #120 @ 0x78 +10001c6a: f888 4000 strb.w r4, [r8] +10001c6e: 2430 movs r4, #48 @ 0x30 +10001c70: f888 4001 strb.w r4, [r8, #1] +10001c74: 2402 movs r4, #2 +10001c76: f1ba 0f00 cmp.w sl, #0 +10001c7a: d099 beq.n 10001bb0 <_ntoa_format+0xd0> +10001c7c: e7aa b.n 10001bd4 <_ntoa_format+0xf4> +10001c7e: 2c20 cmp r4, #32 +10001c80: f43f af73 beq.w 10001b6a <_ntoa_format+0x8a> +10001c84: 2678 movs r6, #120 @ 0x78 +10001c86: f808 6004 strb.w r6, [r8, r4] +10001c8a: 3401 adds r4, #1 +10001c8c: e76b b.n 10001b66 <_ntoa_format+0x86> +10001c8e: 2458 movs r4, #88 @ 0x58 +10001c90: e7eb b.n 10001c6a <_ntoa_format+0x18a> +10001c92: 2462 movs r4, #98 @ 0x62 +10001c94: e7e9 b.n 10001c6a <_ntoa_format+0x18a> +10001c96: f017 0f20 tst.w r7, #32 +10001c9a: f1a4 0c02 sub.w ip, r4, #2 +10001c9e: d004 beq.n 10001caa <_ntoa_format+0x1ca> +10001ca0: f04f 0e58 mov.w lr, #88 @ 0x58 +10001ca4: f808 e00c strb.w lr, [r8, ip] +10001ca8: e78b b.n 10001bc2 <_ntoa_format+0xe2> +10001caa: f04f 0e78 mov.w lr, #120 @ 0x78 +10001cae: f808 e00c strb.w lr, [r8, ip] +10001cb2: e786 b.n 10001bc2 <_ntoa_format+0xe2> + +10001cb4 <_out_char>: +10001cb4: b900 cbnz r0, 10001cb8 <_out_char+0x4> +10001cb6: 4770 bx lr +10001cb8: f001 bb72 b.w 100033a0 <__wrap_putchar> + +10001cbc <_out_fct>: +10001cbc: b110 cbz r0, 10001cc4 <_out_fct+0x8> +10001cbe: e9d1 3100 ldrd r3, r1, [r1] +10001cc2: 4718 bx r3 +10001cc4: 4770 bx lr +10001cc6: bf00 nop + +10001cc8 <_ftoa>: +10001cc8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ccc: b097 sub sp, #92 @ 0x5c +10001cce: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001cd2: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001cd6: 4607 mov r7, r0 +10001cd8: 4688 mov r8, r1 +10001cda: ec51 0b17 vmov r0, r1, d7 +10001cde: 9c24 ldr r4, [sp, #144] @ 0x90 +10001ce0: 4699 mov r9, r3 +10001ce2: 920c str r2, [sp, #48] @ 0x30 +10001ce4: 460b mov r3, r1 +10001ce6: 4602 mov r2, r0 +10001ce8: ed8d 7b04 vstr d7, [sp, #16] +10001cec: 9407 str r4, [sp, #28] +10001cee: f7ff fe49 bl 10001984 <__wrap___aeabi_dcmpun> +10001cf2: 2800 cmp r0, #0 +10001cf4: f040 81f4 bne.w 100020e0 <_ftoa+0x418> +10001cf8: e9dd 0104 ldrd r0, r1, [sp, #16] +10001cfc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d00: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001d04: f7ff fe50 bl 100019a8 <__wrap___aeabi_dcmplt> +10001d08: 2800 cmp r0, #0 +10001d0a: f040 811b bne.w 10001f44 <_ftoa+0x27c> +10001d0e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d12: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d16: 4bac ldr r3, [pc, #688] @ (10001fc8 <_ftoa+0x300>) +10001d18: f7ff fe82 bl 10001a20 <__wrap___aeabi_dcmpgt> +10001d1c: 2800 cmp r0, #0 +10001d1e: f040 80ee bne.w 10001efe <_ftoa+0x236> +10001d22: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d26: a3a4 add r3, pc, #656 @ (adr r3, 10001fb8 <_ftoa+0x2f0>) +10001d28: e9d3 2300 ldrd r2, r3, [r3] +10001d2c: f7ff fe78 bl 10001a20 <__wrap___aeabi_dcmpgt> +10001d30: 2800 cmp r0, #0 +10001d32: f040 80d3 bne.w 10001edc <_ftoa+0x214> +10001d36: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d3a: a3a1 add r3, pc, #644 @ (adr r3, 10001fc0 <_ftoa+0x2f8>) +10001d3c: e9d3 2300 ldrd r2, r3, [r3] +10001d40: f7ff fe32 bl 100019a8 <__wrap___aeabi_dcmplt> +10001d44: 2800 cmp r0, #0 +10001d46: f040 80c9 bne.w 10001edc <_ftoa+0x214> +10001d4a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d4e: 2200 movs r2, #0 +10001d50: 2300 movs r3, #0 +10001d52: f7ff fe29 bl 100019a8 <__wrap___aeabi_dcmplt> +10001d56: 2800 cmp r0, #0 +10001d58: f040 80e8 bne.w 10001f2c <_ftoa+0x264> +10001d5c: 4623 mov r3, r4 +10001d5e: 900d str r0, [sp, #52] @ 0x34 +10001d60: f413 6f80 tst.w r3, #1024 @ 0x400 +10001d64: bf08 it eq +10001d66: 2506 moveq r5, #6 +10001d68: 2130 movs r1, #48 @ 0x30 +10001d6a: 462b mov r3, r5 +10001d6c: aa0e add r2, sp, #56 @ 0x38 +10001d6e: f1a5 0620 sub.w r6, r5, #32 +10001d72: e005 b.n 10001d80 <_ftoa+0xb8> +10001d74: 3b01 subs r3, #1 +10001d76: 42b3 cmp r3, r6 +10001d78: f802 1b01 strb.w r1, [r2], #1 +10001d7c: f000 8193 beq.w 100020a6 <_ftoa+0x3de> +10001d80: 2b09 cmp r3, #9 +10001d82: d8f7 bhi.n 10001d74 <_ftoa+0xac> +10001d84: 461e mov r6, r3 +10001d86: 1aed subs r5, r5, r3 +10001d88: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d8c: f7ff fdd6 bl 1000193c <__wrap___aeabi_d2iz> +10001d90: 4b8e ldr r3, [pc, #568] @ (10001fcc <_ftoa+0x304>) +10001d92: 4604 mov r4, r0 +10001d94: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001d98: ed93 7b00 vldr d7, [r3] +10001d9c: ed8d 7b08 vstr d7, [sp, #32] +10001da0: f7ff fda8 bl 100018f4 <__wrap___aeabi_i2d> +10001da4: 4602 mov r2, r0 +10001da6: 460b mov r3, r1 +10001da8: e9dd 0104 ldrd r0, r1, [sp, #16] +10001dac: f7ff fd1a bl 100017e4 <__wrap___aeabi_dsub> +10001db0: e9dd 2308 ldrd r2, r3, [sp, #32] +10001db4: f7ff fd2a bl 1000180c <__wrap___aeabi_dmul> +10001db8: 4602 mov r2, r0 +10001dba: 460b mov r3, r1 +10001dbc: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001dc0: f7ff fdce bl 10001960 <__wrap___aeabi_d2uiz> +10001dc4: 4682 mov sl, r0 +10001dc6: f7ff fda7 bl 10001918 <__wrap___aeabi_ui2d> +10001dca: 4602 mov r2, r0 +10001dcc: 460b mov r3, r1 +10001dce: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001dd2: f7ff fd07 bl 100017e4 <__wrap___aeabi_dsub> +10001dd6: 4602 mov r2, r0 +10001dd8: 460b mov r3, r1 +10001dda: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001dde: 2200 movs r2, #0 +10001de0: 4b7b ldr r3, [pc, #492] @ (10001fd0 <_ftoa+0x308>) +10001de2: f7ff fe1d bl 10001a20 <__wrap___aeabi_dcmpgt> +10001de6: 2800 cmp r0, #0 +10001de8: f000 80fe beq.w 10001fe8 <_ftoa+0x320> +10001dec: f10a 0a01 add.w sl, sl, #1 +10001df0: 4650 mov r0, sl +10001df2: f7ff fd91 bl 10001918 <__wrap___aeabi_ui2d> +10001df6: 4602 mov r2, r0 +10001df8: 460b mov r3, r1 +10001dfa: e9dd 0108 ldrd r0, r1, [sp, #32] +10001dfe: f7ff fde7 bl 100019d0 <__wrap___aeabi_dcmple> +10001e02: b110 cbz r0, 10001e0a <_ftoa+0x142> +10001e04: f04f 0a00 mov.w sl, #0 +10001e08: 3401 adds r4, #1 +10001e0a: 2e00 cmp r6, #0 +10001e0c: f000 80fd beq.w 1000200a <_ftoa+0x342> +10001e10: 1e68 subs r0, r5, #1 +10001e12: ab0e add r3, sp, #56 @ 0x38 +10001e14: f8df c1cc ldr.w ip, [pc, #460] @ 10001fe4 <_ftoa+0x31c> +10001e18: 4418 add r0, r3 +10001e1a: e00f b.n 10001e3c <_ftoa+0x174> +10001e1c: fbac 210a umull r2, r1, ip, sl +10001e20: 08c9 lsrs r1, r1, #3 +10001e22: eb01 0281 add.w r2, r1, r1, lsl #2 +10001e26: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001e2a: 3230 adds r2, #48 @ 0x30 +10001e2c: f1ba 0f09 cmp.w sl, #9 +10001e30: f800 2f01 strb.w r2, [r0, #1]! +10001e34: f240 811c bls.w 10002070 <_ftoa+0x3a8> +10001e38: 468a mov sl, r1 +10001e3a: 461d mov r5, r3 +10001e3c: 2d20 cmp r5, #32 +10001e3e: f105 0301 add.w r3, r5, #1 +10001e42: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001e46: d1e9 bne.n 10001e1c <_ftoa+0x154> +10001e48: 2520 movs r5, #32 +10001e4a: 1e69 subs r1, r5, #1 +10001e4c: ab0e add r3, sp, #56 @ 0x38 +10001e4e: 4861 ldr r0, [pc, #388] @ (10001fd4 <_ftoa+0x30c>) +10001e50: 4419 add r1, r3 +10001e52: e010 b.n 10001e76 <_ftoa+0x1ae> +10001e54: fb80 6204 smull r6, r2, r0, r4 +10001e58: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001e5c: eb03 0283 add.w r2, r3, r3, lsl #2 +10001e60: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001e64: f104 0230 add.w r2, r4, #48 @ 0x30 +10001e68: 3501 adds r5, #1 +10001e6a: 461c mov r4, r3 +10001e6c: f801 2f01 strb.w r2, [r1, #1]! +10001e70: 2b00 cmp r3, #0 +10001e72: f000 80eb beq.w 1000204c <_ftoa+0x384> +10001e76: 2d20 cmp r5, #32 +10001e78: ea4f 73e4 mov.w r3, r4, asr #31 +10001e7c: d1ea bne.n 10001e54 <_ftoa+0x18c> +10001e7e: 9b07 ldr r3, [sp, #28] +10001e80: f003 0303 and.w r3, r3, #3 +10001e84: 2b01 cmp r3, #1 +10001e86: d118 bne.n 10001eba <_ftoa+0x1f2> +10001e88: f1bb 0f00 cmp.w fp, #0 +10001e8c: d015 beq.n 10001eba <_ftoa+0x1f2> +10001e8e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001e90: 2b00 cmp r3, #0 +10001e92: f000 810a beq.w 100020aa <_ftoa+0x3e2> +10001e96: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001e9a: f1bb 0f20 cmp.w fp, #32 +10001e9e: d90c bls.n 10001eba <_ftoa+0x1f2> +10001ea0: 1e6b subs r3, r5, #1 +10001ea2: a90e add r1, sp, #56 @ 0x38 +10001ea4: 2230 movs r2, #48 @ 0x30 +10001ea6: 440b add r3, r1 +10001ea8: e005 b.n 10001eb6 <_ftoa+0x1ee> +10001eaa: 3501 adds r5, #1 +10001eac: 455d cmp r5, fp +10001eae: f803 2f01 strb.w r2, [r3, #1]! +10001eb2: f080 80d1 bcs.w 10002058 <_ftoa+0x390> +10001eb6: 2d20 cmp r5, #32 +10001eb8: d1f7 bne.n 10001eaa <_ftoa+0x1e2> +10001eba: 9b07 ldr r3, [sp, #28] +10001ebc: ac0e add r4, sp, #56 @ 0x38 +10001ebe: e9cd b302 strd fp, r3, [sp, #8] +10001ec2: 4641 mov r1, r8 +10001ec4: 464b mov r3, r9 +10001ec6: 4638 mov r0, r7 +10001ec8: 9a0c ldr r2, [sp, #48] @ 0x30 +10001eca: 9501 str r5, [sp, #4] +10001ecc: 9400 str r4, [sp, #0] +10001ece: f7ff fdb9 bl 10001a44 <_out_rev> +10001ed2: 4682 mov sl, r0 +10001ed4: 4650 mov r0, sl +10001ed6: b017 add sp, #92 @ 0x5c +10001ed8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001edc: 9b07 ldr r3, [sp, #28] +10001ede: ed9d 7b04 vldr d7, [sp, #16] +10001ee2: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001ee6: 4641 mov r1, r8 +10001ee8: 464b mov r3, r9 +10001eea: 4638 mov r0, r7 +10001eec: 9a0c ldr r2, [sp, #48] @ 0x30 +10001eee: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001ef2: 9522 str r5, [sp, #136] @ 0x88 +10001ef4: b017 add sp, #92 @ 0x5c +10001ef6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001efa: f000 b945 b.w 10002188 <_etoa> +10001efe: 0761 lsls r1, r4, #29 +10001f00: 4623 mov r3, r4 +10001f02: bf4c ite mi +10001f04: 2304 movmi r3, #4 +10001f06: 2303 movpl r3, #3 +10001f08: 4641 mov r1, r8 +10001f0a: 9321 str r3, [sp, #132] @ 0x84 +10001f0c: 4638 mov r0, r7 +10001f0e: 464b mov r3, r9 +10001f10: 9a07 ldr r2, [sp, #28] +10001f12: bf48 it mi +10001f14: 4c30 ldrmi r4, [pc, #192] @ (10001fd8 <_ftoa+0x310>) +10001f16: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001f1a: bf58 it pl +10001f1c: 4c2f ldrpl r4, [pc, #188] @ (10001fdc <_ftoa+0x314>) +10001f1e: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f20: 9420 str r4, [sp, #128] @ 0x80 +10001f22: b017 add sp, #92 @ 0x5c +10001f24: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f28: f7ff bd8c b.w 10001a44 <_out_rev> +10001f2c: e9dd 2304 ldrd r2, r3, [sp, #16] +10001f30: 2000 movs r0, #0 +10001f32: 2100 movs r1, #0 +10001f34: f7ff fc56 bl 100017e4 <__wrap___aeabi_dsub> +10001f38: 2301 movs r3, #1 +10001f3a: e9cd 0104 strd r0, r1, [sp, #16] +10001f3e: 930d str r3, [sp, #52] @ 0x34 +10001f40: 4623 mov r3, r4 +10001f42: e70d b.n 10001d60 <_ftoa+0x98> +10001f44: 4623 mov r3, r4 +10001f46: 079c lsls r4, r3, #30 +10001f48: f040 80aa bne.w 100020a0 <_ftoa+0x3d8> +10001f4c: f1bb 0f04 cmp.w fp, #4 +10001f50: f240 80a6 bls.w 100020a0 <_ftoa+0x3d8> +10001f54: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f56: 461d mov r5, r3 +10001f58: 1f1c subs r4, r3, #4 +10001f5a: eb04 0a0b add.w sl, r4, fp +10001f5e: 462a mov r2, r5 +10001f60: 464b mov r3, r9 +10001f62: 4641 mov r1, r8 +10001f64: 2020 movs r0, #32 +10001f66: 3501 adds r5, #1 +10001f68: 47b8 blx r7 +10001f6a: 45aa cmp sl, r5 +10001f6c: d1f7 bne.n 10001f5e <_ftoa+0x296> +10001f6e: 4655 mov r5, sl +10001f70: 4c1b ldr r4, [pc, #108] @ (10001fe0 <_ftoa+0x318>) +10001f72: 1f26 subs r6, r4, #4 +10001f74: f814 0d01 ldrb.w r0, [r4, #-1]! +10001f78: 462a mov r2, r5 +10001f7a: 464b mov r3, r9 +10001f7c: 4641 mov r1, r8 +10001f7e: 47b8 blx r7 +10001f80: 42b4 cmp r4, r6 +10001f82: f105 0501 add.w r5, r5, #1 +10001f86: d1f5 bne.n 10001f74 <_ftoa+0x2ac> +10001f88: 9b07 ldr r3, [sp, #28] +10001f8a: f10a 0a04 add.w sl, sl, #4 +10001f8e: 0798 lsls r0, r3, #30 +10001f90: d5a0 bpl.n 10001ed4 <_ftoa+0x20c> +10001f92: 9c0c ldr r4, [sp, #48] @ 0x30 +10001f94: ebaa 0304 sub.w r3, sl, r4 +10001f98: 459b cmp fp, r3 +10001f9a: d99b bls.n 10001ed4 <_ftoa+0x20c> +10001f9c: 4652 mov r2, sl +10001f9e: 464b mov r3, r9 +10001fa0: 4641 mov r1, r8 +10001fa2: 2020 movs r0, #32 +10001fa4: f10a 0a01 add.w sl, sl, #1 +10001fa8: 47b8 blx r7 +10001faa: ebaa 0304 sub.w r3, sl, r4 +10001fae: 455b cmp r3, fp +10001fb0: d3f4 bcc.n 10001f9c <_ftoa+0x2d4> +10001fb2: e78f b.n 10001ed4 <_ftoa+0x20c> +10001fb4: f3af 8000 nop.w +10001fb8: 00000000 .word 0x00000000 +10001fbc: 41cdcd65 .word 0x41cdcd65 +10001fc0: 00000000 .word 0x00000000 +10001fc4: c1cdcd65 .word 0xc1cdcd65 +10001fc8: 7fefffff .word 0x7fefffff +10001fcc: 10003b00 .word 0x10003b00 +10001fd0: 3fe00000 .word 0x3fe00000 +10001fd4: 66666667 .word 0x66666667 +10001fd8: 10003a58 .word 0x10003a58 +10001fdc: 10003a60 .word 0x10003a60 +10001fe0: 10003a6c .word 0x10003a6c +10001fe4: cccccccd .word 0xcccccccd +10001fe8: 2200 movs r2, #0 +10001fea: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001fee: 4b63 ldr r3, [pc, #396] @ (1000217c <_ftoa+0x4b4>) +10001ff0: f7ff fcda bl 100019a8 <__wrap___aeabi_dcmplt> +10001ff4: 2800 cmp r0, #0 +10001ff6: f47f af08 bne.w 10001e0a <_ftoa+0x142> +10001ffa: f1ba 0f00 cmp.w sl, #0 +10001ffe: d16a bne.n 100020d6 <_ftoa+0x40e> +10002000: f10a 0a01 add.w sl, sl, #1 +10002004: 2e00 cmp r6, #0 +10002006: f47f af03 bne.w 10001e10 <_ftoa+0x148> +1000200a: 4620 mov r0, r4 +1000200c: f7ff fc72 bl 100018f4 <__wrap___aeabi_i2d> +10002010: 4602 mov r2, r0 +10002012: 460b mov r3, r1 +10002014: e9dd 0104 ldrd r0, r1, [sp, #16] +10002018: f7ff fbe4 bl 100017e4 <__wrap___aeabi_dsub> +1000201c: 4602 mov r2, r0 +1000201e: 460b mov r3, r1 +10002020: e9cd 2304 strd r2, r3, [sp, #16] +10002024: 2200 movs r2, #0 +10002026: 4b55 ldr r3, [pc, #340] @ (1000217c <_ftoa+0x4b4>) +10002028: f7ff fcbe bl 100019a8 <__wrap___aeabi_dcmplt> +1000202c: 2800 cmp r0, #0 +1000202e: f47f af0c bne.w 10001e4a <_ftoa+0x182> +10002032: e9dd 0104 ldrd r0, r1, [sp, #16] +10002036: 2200 movs r2, #0 +10002038: 4b50 ldr r3, [pc, #320] @ (1000217c <_ftoa+0x4b4>) +1000203a: f7ff fcf1 bl 10001a20 <__wrap___aeabi_dcmpgt> +1000203e: 2800 cmp r0, #0 +10002040: f47f af03 bne.w 10001e4a <_ftoa+0x182> +10002044: 3401 adds r4, #1 +10002046: f024 0401 bic.w r4, r4, #1 +1000204a: e6fe b.n 10001e4a <_ftoa+0x182> +1000204c: 9b07 ldr r3, [sp, #28] +1000204e: f003 0303 and.w r3, r3, #3 +10002052: 2b01 cmp r3, #1 +10002054: f000 8082 beq.w 1000215c <_ftoa+0x494> +10002058: 2d20 cmp r5, #32 +1000205a: f43f af2e beq.w 10001eba <_ftoa+0x1f2> +1000205e: 9b0d ldr r3, [sp, #52] @ 0x34 +10002060: b37b cbz r3, 100020c2 <_ftoa+0x3fa> +10002062: 222d movs r2, #45 @ 0x2d +10002064: eb0d 0305 add.w r3, sp, r5 +10002068: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1000206c: 3501 adds r5, #1 +1000206e: e724 b.n 10001eba <_ftoa+0x1f2> +10002070: 2b20 cmp r3, #32 +10002072: f43f aee9 beq.w 10001e48 <_ftoa+0x180> +10002076: aa0e add r2, sp, #56 @ 0x38 +10002078: 4415 add r5, r2 +1000207a: 441e add r6, r3 +1000207c: 2230 movs r2, #48 @ 0x30 +1000207e: e004 b.n 1000208a <_ftoa+0x3c2> +10002080: 2b20 cmp r3, #32 +10002082: f805 2f01 strb.w r2, [r5, #1]! +10002086: f43f aedf beq.w 10001e48 <_ftoa+0x180> +1000208a: 429e cmp r6, r3 +1000208c: f103 0301 add.w r3, r3, #1 +10002090: d1f6 bne.n 10002080 <_ftoa+0x3b8> +10002092: 222e movs r2, #46 @ 0x2e +10002094: eb0d 0306 add.w r3, sp, r6 +10002098: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1000209c: 1c75 adds r5, r6, #1 +1000209e: e6d4 b.n 10001e4a <_ftoa+0x182> +100020a0: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +100020a4: e763 b.n 10001f6e <_ftoa+0x2a6> +100020a6: 2520 movs r5, #32 +100020a8: e66e b.n 10001d88 <_ftoa+0xc0> +100020aa: 9b07 ldr r3, [sp, #28] +100020ac: f013 0f0c tst.w r3, #12 +100020b0: d050 beq.n 10002154 <_ftoa+0x48c> +100020b2: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +100020b6: 45ab cmp fp, r5 +100020b8: f63f aef2 bhi.w 10001ea0 <_ftoa+0x1d8> +100020bc: 2d20 cmp r5, #32 +100020be: f43f aefc beq.w 10001eba <_ftoa+0x1f2> +100020c2: 9b07 ldr r3, [sp, #28] +100020c4: 075a lsls r2, r3, #29 +100020c6: d501 bpl.n 100020cc <_ftoa+0x404> +100020c8: 222b movs r2, #43 @ 0x2b +100020ca: e7cb b.n 10002064 <_ftoa+0x39c> +100020cc: 071b lsls r3, r3, #28 +100020ce: f57f aef4 bpl.w 10001eba <_ftoa+0x1f2> +100020d2: 2220 movs r2, #32 +100020d4: e7c6 b.n 10002064 <_ftoa+0x39c> +100020d6: f01a 0f01 tst.w sl, #1 +100020da: f43f ae96 beq.w 10001e0a <_ftoa+0x142> +100020de: e78f b.n 10002000 <_ftoa+0x338> +100020e0: 07a6 lsls r6, r4, #30 +100020e2: d134 bne.n 1000214e <_ftoa+0x486> +100020e4: f1bb 0f03 cmp.w fp, #3 +100020e8: d931 bls.n 1000214e <_ftoa+0x486> +100020ea: 9b0c ldr r3, [sp, #48] @ 0x30 +100020ec: 461d mov r5, r3 +100020ee: 1edc subs r4, r3, #3 +100020f0: eb04 0a0b add.w sl, r4, fp +100020f4: 462a mov r2, r5 +100020f6: 464b mov r3, r9 +100020f8: 4641 mov r1, r8 +100020fa: 2020 movs r0, #32 +100020fc: 3501 adds r5, #1 +100020fe: 47b8 blx r7 +10002100: 4555 cmp r5, sl +10002102: d1f7 bne.n 100020f4 <_ftoa+0x42c> +10002104: 4655 mov r5, sl +10002106: 4c1e ldr r4, [pc, #120] @ (10002180 <_ftoa+0x4b8>) +10002108: 1ee6 subs r6, r4, #3 +1000210a: f814 0d01 ldrb.w r0, [r4, #-1]! +1000210e: 462a mov r2, r5 +10002110: 464b mov r3, r9 +10002112: 4641 mov r1, r8 +10002114: 47b8 blx r7 +10002116: 42a6 cmp r6, r4 +10002118: f105 0501 add.w r5, r5, #1 +1000211c: d1f5 bne.n 1000210a <_ftoa+0x442> +1000211e: 9b07 ldr r3, [sp, #28] +10002120: f10a 0a03 add.w sl, sl, #3 +10002124: 079d lsls r5, r3, #30 +10002126: f57f aed5 bpl.w 10001ed4 <_ftoa+0x20c> +1000212a: 9c0c ldr r4, [sp, #48] @ 0x30 +1000212c: ebaa 0304 sub.w r3, sl, r4 +10002130: 459b cmp fp, r3 +10002132: f67f aecf bls.w 10001ed4 <_ftoa+0x20c> +10002136: 4652 mov r2, sl +10002138: 464b mov r3, r9 +1000213a: 4641 mov r1, r8 +1000213c: 2020 movs r0, #32 +1000213e: f10a 0a01 add.w sl, sl, #1 +10002142: 47b8 blx r7 +10002144: ebaa 0304 sub.w r3, sl, r4 +10002148: 459b cmp fp, r3 +1000214a: d8f4 bhi.n 10002136 <_ftoa+0x46e> +1000214c: e6c2 b.n 10001ed4 <_ftoa+0x20c> +1000214e: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10002152: e7d7 b.n 10002104 <_ftoa+0x43c> +10002154: 45ab cmp fp, r5 +10002156: f63f aea3 bhi.w 10001ea0 <_ftoa+0x1d8> +1000215a: e6ae b.n 10001eba <_ftoa+0x1f2> +1000215c: f1bb 0f00 cmp.w fp, #0 +10002160: f43f af7a beq.w 10002058 <_ftoa+0x390> +10002164: 9b0d ldr r3, [sp, #52] @ 0x34 +10002166: 2b00 cmp r3, #0 +10002168: d09f beq.n 100020aa <_ftoa+0x3e2> +1000216a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000216e: 455d cmp r5, fp +10002170: f4ff ae96 bcc.w 10001ea0 <_ftoa+0x1d8> +10002174: 2d20 cmp r5, #32 +10002176: f47f af74 bne.w 10002062 <_ftoa+0x39a> +1000217a: e69e b.n 10001eba <_ftoa+0x1f2> +1000217c: 3fe00000 .word 0x3fe00000 +10002180: 10003a67 .word 0x10003a67 +10002184: 00000000 .word 0x00000000 + +10002188 <_etoa>: +10002188: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000218c: b09f sub sp, #124 @ 0x7c +1000218e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10002190: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10002194: 4607 mov r7, r0 +10002196: 4693 mov fp, r2 +10002198: 9108 str r1, [sp, #32] +1000219a: 9309 str r3, [sp, #36] @ 0x24 +1000219c: 4622 mov r2, r4 +1000219e: 462b mov r3, r5 +100021a0: 4620 mov r0, r4 +100021a2: 4629 mov r1, r5 +100021a4: 960e str r6, [sp, #56] @ 0x38 +100021a6: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +100021aa: f7ff fbeb bl 10001984 <__wrap___aeabi_dcmpun> +100021ae: 2800 cmp r0, #0 +100021b0: f040 80be bne.w 10002330 <_etoa+0x1a8> +100021b4: 4620 mov r0, r4 +100021b6: 4629 mov r1, r5 +100021b8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100021bc: 4b78 ldr r3, [pc, #480] @ (100023a0 <_etoa+0x218>) +100021be: f7ff fc2f bl 10001a20 <__wrap___aeabi_dcmpgt> +100021c2: 2800 cmp r0, #0 +100021c4: f040 80b4 bne.w 10002330 <_etoa+0x1a8> +100021c8: 4620 mov r0, r4 +100021ca: 4629 mov r1, r5 +100021cc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100021d0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100021d4: f7ff fbe8 bl 100019a8 <__wrap___aeabi_dcmplt> +100021d8: 2800 cmp r0, #0 +100021da: f040 80a9 bne.w 10002330 <_etoa+0x1a8> +100021de: 4620 mov r0, r4 +100021e0: 4629 mov r1, r5 +100021e2: 2200 movs r2, #0 +100021e4: 2300 movs r3, #0 +100021e6: f7ff fbdf bl 100019a8 <__wrap___aeabi_dcmplt> +100021ea: 2800 cmp r0, #0 +100021ec: f040 81d5 bne.w 1000259a <_etoa+0x412> +100021f0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +100021f4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +100021f8: 4690 mov r8, r2 +100021fa: 4699 mov r9, r3 +100021fc: f406 6200 and.w r2, r6, #2048 @ 0x800 +10002200: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10002204: 920f str r2, [sp, #60] @ 0x3c +10002206: 9313 str r3, [sp, #76] @ 0x4c +10002208: f040 80a1 bne.w 1000234e <_etoa+0x1c6> +1000220c: ea58 0309 orrs.w r3, r8, r9 +10002210: f040 80ca bne.w 100023a8 <_etoa+0x220> +10002214: 2a00 cmp r2, #0 +10002216: f040 81e3 bne.w 100025e0 <_etoa+0x458> +1000221a: 2306 movs r3, #6 +1000221c: 930e str r3, [sp, #56] @ 0x38 +1000221e: f016 0202 ands.w r2, r6, #2 +10002222: 9210 str r2, [sp, #64] @ 0x40 +10002224: f040 81d4 bne.w 100025d0 <_etoa+0x448> +10002228: 4653 mov r3, sl +1000222a: 2b04 cmp r3, #4 +1000222c: bf38 it cc +1000222e: 2304 movcc r3, #4 +10002230: 920c str r2, [sp, #48] @ 0x30 +10002232: 2204 movs r2, #4 +10002234: 3b04 subs r3, #4 +10002236: 9212 str r2, [sp, #72] @ 0x48 +10002238: 930f str r3, [sp, #60] @ 0x3c +1000223a: 4620 mov r0, r4 +1000223c: 4629 mov r1, r5 +1000223e: 2200 movs r2, #0 +10002240: 2300 movs r3, #0 +10002242: f7ff fbb1 bl 100019a8 <__wrap___aeabi_dcmplt> +10002246: 2800 cmp r0, #0 +10002248: f040 81f3 bne.w 10002632 <_etoa+0x4aa> +1000224c: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002250: 9b0f ldr r3, [sp, #60] @ 0x3c +10002252: 465a mov r2, fp +10002254: 9303 str r3, [sp, #12] +10002256: 9b0e ldr r3, [sp, #56] @ 0x38 +10002258: ed8d 7b00 vstr d7, [sp] +1000225c: 9302 str r3, [sp, #8] +1000225e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002262: 9304 str r3, [sp, #16] +10002264: 4638 mov r0, r7 +10002266: 9b09 ldr r3, [sp, #36] @ 0x24 +10002268: 9908 ldr r1, [sp, #32] +1000226a: f7ff fd2d bl 10001cc8 <_ftoa> +1000226e: 4602 mov r2, r0 +10002270: f016 0f20 tst.w r6, #32 +10002274: 9b09 ldr r3, [sp, #36] @ 0x24 +10002276: 9908 ldr r1, [sp, #32] +10002278: bf0c ite eq +1000227a: 2065 moveq r0, #101 @ 0x65 +1000227c: 2045 movne r0, #69 @ 0x45 +1000227e: f102 0801 add.w r8, r2, #1 +10002282: 47b8 blx r7 +10002284: 9a0c ldr r2, [sp, #48] @ 0x30 +10002286: 9b12 ldr r3, [sp, #72] @ 0x48 +10002288: ac16 add r4, sp, #88 @ 0x58 +1000228a: 1e5d subs r5, r3, #1 +1000228c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10002290: eba3 73e2 sub.w r3, r3, r2, asr #31 +10002294: 0fd1 lsrs r1, r2, #31 +10002296: 2600 movs r6, #0 +10002298: 4622 mov r2, r4 +1000229a: 4699 mov r9, r3 +1000229c: f8df c104 ldr.w ip, [pc, #260] @ 100023a4 <_etoa+0x21c> +100022a0: e001 b.n 100022a6 <_etoa+0x11e> +100022a2: 2e20 cmp r6, #32 +100022a4: d010 beq.n 100022c8 <_etoa+0x140> +100022a6: 46ce mov lr, r9 +100022a8: fbac 3009 umull r3, r0, ip, r9 +100022ac: 08c0 lsrs r0, r0, #3 +100022ae: eb00 0380 add.w r3, r0, r0, lsl #2 +100022b2: eba9 0343 sub.w r3, r9, r3, lsl #1 +100022b6: 3330 adds r3, #48 @ 0x30 +100022b8: f1be 0f09 cmp.w lr, #9 +100022bc: 4681 mov r9, r0 +100022be: f106 0601 add.w r6, r6, #1 +100022c2: f802 3b01 strb.w r3, [r2], #1 +100022c6: d8ec bhi.n 100022a2 <_etoa+0x11a> +100022c8: 2305 movs r3, #5 +100022ca: 2000 movs r0, #0 +100022cc: 9306 str r3, [sp, #24] +100022ce: 230a movs r3, #10 +100022d0: 9505 str r5, [sp, #20] +100022d2: 9400 str r4, [sp, #0] +100022d4: 9d09 ldr r5, [sp, #36] @ 0x24 +100022d6: 9c08 ldr r4, [sp, #32] +100022d8: 4642 mov r2, r8 +100022da: e9cd 3003 strd r3, r0, [sp, #12] +100022de: e9cd 6101 strd r6, r1, [sp, #4] +100022e2: 462b mov r3, r5 +100022e4: 4621 mov r1, r4 +100022e6: 4638 mov r0, r7 +100022e8: f7ff fbfa bl 10001ae0 <_ntoa_format> +100022ec: 9a10 ldr r2, [sp, #64] @ 0x40 +100022ee: 4680 mov r8, r0 +100022f0: b1d2 cbz r2, 10002328 <_etoa+0x1a0> +100022f2: eba0 060b sub.w r6, r0, fp +100022f6: 45b2 cmp sl, r6 +100022f8: d916 bls.n 10002328 <_etoa+0x1a0> +100022fa: eb0b 0206 add.w r2, fp, r6 +100022fe: 462b mov r3, r5 +10002300: 4621 mov r1, r4 +10002302: 2020 movs r0, #32 +10002304: 3601 adds r6, #1 +10002306: 47b8 blx r7 +10002308: 45b2 cmp sl, r6 +1000230a: d8f6 bhi.n 100022fa <_etoa+0x172> +1000230c: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002310: 4453 add r3, sl +10002312: f1cb 0201 rsb r2, fp, #1 +10002316: eba3 0308 sub.w r3, r3, r8 +1000231a: 4442 add r2, r8 +1000231c: 4592 cmp sl, r2 +1000231e: bf38 it cc +10002320: 2300 movcc r3, #0 +10002322: f108 0801 add.w r8, r8, #1 +10002326: 4498 add r8, r3 +10002328: 4640 mov r0, r8 +1000232a: b01f add sp, #124 @ 0x7c +1000232c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002330: 465a mov r2, fp +10002332: 4638 mov r0, r7 +10002334: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002338: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +1000233c: 9c0e ldr r4, [sp, #56] @ 0x38 +1000233e: 9b09 ldr r3, [sp, #36] @ 0x24 +10002340: 9908 ldr r1, [sp, #32] +10002342: 942a str r4, [sp, #168] @ 0xa8 +10002344: b01f add sp, #124 @ 0x7c +10002346: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000234a: f7ff bcbd b.w 10001cc8 <_ftoa> +1000234e: ea58 0309 orrs.w r3, r8, r9 +10002352: d12b bne.n 100023ac <_etoa+0x224> +10002354: 2a00 cmp r2, #0 +10002356: f43f af62 beq.w 1000221e <_etoa+0x96> +1000235a: 2300 movs r3, #0 +1000235c: 930c str r3, [sp, #48] @ 0x30 +1000235e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002360: 9a0c ldr r2, [sp, #48] @ 0x30 +10002362: 4293 cmp r3, r2 +10002364: f300 81b9 bgt.w 100026da <_etoa+0x552> +10002368: f04f 0800 mov.w r8, #0 +1000236c: 4620 mov r0, r4 +1000236e: 4629 mov r1, r5 +10002370: 2200 movs r2, #0 +10002372: 2300 movs r3, #0 +10002374: f7ff fb18 bl 100019a8 <__wrap___aeabi_dcmplt> +10002378: 2800 cmp r0, #0 +1000237a: f040 8113 bne.w 100025a4 <_etoa+0x41c> +1000237e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002382: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002386: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000238a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1000238e: 465a mov r2, fp +10002390: 4638 mov r0, r7 +10002392: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002396: 9b09 ldr r3, [sp, #36] @ 0x24 +10002398: 9908 ldr r1, [sp, #32] +1000239a: 962c str r6, [sp, #176] @ 0xb0 +1000239c: e7d2 b.n 10002344 <_etoa+0x1bc> +1000239e: bf00 nop +100023a0: 7fefffff .word 0x7fefffff +100023a4: cccccccd .word 0xcccccccd +100023a8: 2306 movs r3, #6 +100023aa: 930e str r3, [sp, #56] @ 0x38 +100023ac: f3c9 500a ubfx r0, r9, #20, #11 +100023b0: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100023b4: f7ff fa9e bl 100018f4 <__wrap___aeabi_i2d> +100023b8: a3c1 add r3, pc, #772 @ (adr r3, 100026c0 <_etoa+0x538>) +100023ba: e9d3 2300 ldrd r2, r3, [r3] +100023be: f7ff fa25 bl 1000180c <__wrap___aeabi_dmul> +100023c2: a3c1 add r3, pc, #772 @ (adr r3, 100026c8 <_etoa+0x540>) +100023c4: e9d3 2300 ldrd r2, r3, [r3] +100023c8: f7ff f9f8 bl 100017bc <__wrap___aeabi_dadd> +100023cc: f3c9 0913 ubfx r9, r9, #0, #20 +100023d0: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +100023d4: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +100023d8: 4640 mov r0, r8 +100023da: 2200 movs r2, #0 +100023dc: 4bb2 ldr r3, [pc, #712] @ (100026a8 <_etoa+0x520>) +100023de: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +100023e2: f7ff f9ff bl 100017e4 <__wrap___aeabi_dsub> +100023e6: a3a4 add r3, pc, #656 @ (adr r3, 10002678 <_etoa+0x4f0>) +100023e8: e9d3 2300 ldrd r2, r3, [r3] +100023ec: f7ff fa0e bl 1000180c <__wrap___aeabi_dmul> +100023f0: 4602 mov r2, r0 +100023f2: 460b mov r3, r1 +100023f4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +100023f8: f7ff f9e0 bl 100017bc <__wrap___aeabi_dadd> +100023fc: f7ff fa9e bl 1000193c <__wrap___aeabi_d2iz> +10002400: 900c str r0, [sp, #48] @ 0x30 +10002402: f7ff fa77 bl 100018f4 <__wrap___aeabi_i2d> +10002406: a39e add r3, pc, #632 @ (adr r3, 10002680 <_etoa+0x4f8>) +10002408: e9d3 2300 ldrd r2, r3, [r3] +1000240c: 4680 mov r8, r0 +1000240e: 4689 mov r9, r1 +10002410: f7ff f9fc bl 1000180c <__wrap___aeabi_dmul> +10002414: 2200 movs r2, #0 +10002416: 4ba5 ldr r3, [pc, #660] @ (100026ac <_etoa+0x524>) +10002418: f7ff f9d0 bl 100017bc <__wrap___aeabi_dadd> +1000241c: f7ff fa8e bl 1000193c <__wrap___aeabi_d2iz> +10002420: 4603 mov r3, r0 +10002422: 4649 mov r1, r9 +10002424: 4640 mov r0, r8 +10002426: 9312 str r3, [sp, #72] @ 0x48 +10002428: a397 add r3, pc, #604 @ (adr r3, 10002688 <_etoa+0x500>) +1000242a: e9d3 2300 ldrd r2, r3, [r3] +1000242e: f7ff f9ed bl 1000180c <__wrap___aeabi_dmul> +10002432: 4680 mov r8, r0 +10002434: 9812 ldr r0, [sp, #72] @ 0x48 +10002436: 4689 mov r9, r1 +10002438: f7ff fa5c bl 100018f4 <__wrap___aeabi_i2d> +1000243c: a394 add r3, pc, #592 @ (adr r3, 10002690 <_etoa+0x508>) +1000243e: e9d3 2300 ldrd r2, r3, [r3] +10002442: f7ff f9e3 bl 1000180c <__wrap___aeabi_dmul> +10002446: 4602 mov r2, r0 +10002448: 460b mov r3, r1 +1000244a: 4640 mov r0, r8 +1000244c: 4649 mov r1, r9 +1000244e: f7ff f9c9 bl 100017e4 <__wrap___aeabi_dsub> +10002452: 4602 mov r2, r0 +10002454: 460b mov r3, r1 +10002456: 4680 mov r8, r0 +10002458: 4689 mov r9, r1 +1000245a: f7ff f9d7 bl 1000180c <__wrap___aeabi_dmul> +1000245e: 4642 mov r2, r8 +10002460: 464b mov r3, r9 +10002462: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002466: 4640 mov r0, r8 +10002468: 4649 mov r1, r9 +1000246a: f7ff f9a7 bl 100017bc <__wrap___aeabi_dadd> +1000246e: 2200 movs r2, #0 +10002470: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10002474: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002478: 4b8d ldr r3, [pc, #564] @ (100026b0 <_etoa+0x528>) +1000247a: f7ff f9ed bl 10001858 <__wrap___aeabi_ddiv> +1000247e: 2200 movs r2, #0 +10002480: 4b8c ldr r3, [pc, #560] @ (100026b4 <_etoa+0x52c>) +10002482: f7ff f99b bl 100017bc <__wrap___aeabi_dadd> +10002486: 4602 mov r2, r0 +10002488: 460b mov r3, r1 +1000248a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000248e: f7ff f9e3 bl 10001858 <__wrap___aeabi_ddiv> +10002492: 2200 movs r2, #0 +10002494: 4b88 ldr r3, [pc, #544] @ (100026b8 <_etoa+0x530>) +10002496: f7ff f991 bl 100017bc <__wrap___aeabi_dadd> +1000249a: 4602 mov r2, r0 +1000249c: 460b mov r3, r1 +1000249e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100024a2: f7ff f9d9 bl 10001858 <__wrap___aeabi_ddiv> +100024a6: 4642 mov r2, r8 +100024a8: 464b mov r3, r9 +100024aa: 4680 mov r8, r0 +100024ac: 4689 mov r9, r1 +100024ae: 2000 movs r0, #0 +100024b0: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100024b4: f7ff f996 bl 100017e4 <__wrap___aeabi_dsub> +100024b8: 4602 mov r2, r0 +100024ba: 460b mov r3, r1 +100024bc: 4640 mov r0, r8 +100024be: 4649 mov r1, r9 +100024c0: f7ff f97c bl 100017bc <__wrap___aeabi_dadd> +100024c4: 4602 mov r2, r0 +100024c6: 460b mov r3, r1 +100024c8: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +100024cc: f7ff f9c4 bl 10001858 <__wrap___aeabi_ddiv> +100024d0: 2200 movs r2, #0 +100024d2: 4b7a ldr r3, [pc, #488] @ (100026bc <_etoa+0x534>) +100024d4: f7ff f972 bl 100017bc <__wrap___aeabi_dadd> +100024d8: 9b12 ldr r3, [sp, #72] @ 0x48 +100024da: 2200 movs r2, #0 +100024dc: f203 3cff addw ip, r3, #1023 @ 0x3ff +100024e0: ea4f 530c mov.w r3, ip, lsl #20 +100024e4: f7ff f992 bl 1000180c <__wrap___aeabi_dmul> +100024e8: 4680 mov r8, r0 +100024ea: 4689 mov r9, r1 +100024ec: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100024f0: 4642 mov r2, r8 +100024f2: 464b mov r3, r9 +100024f4: f7ff fa58 bl 100019a8 <__wrap___aeabi_dcmplt> +100024f8: b150 cbz r0, 10002510 <_etoa+0x388> +100024fa: 9b0c ldr r3, [sp, #48] @ 0x30 +100024fc: 4640 mov r0, r8 +100024fe: 3b01 subs r3, #1 +10002500: 4649 mov r1, r9 +10002502: 930c str r3, [sp, #48] @ 0x30 +10002504: 2200 movs r2, #0 +10002506: 4b6b ldr r3, [pc, #428] @ (100026b4 <_etoa+0x52c>) +10002508: f7ff f9a6 bl 10001858 <__wrap___aeabi_ddiv> +1000250c: 4680 mov r8, r0 +1000250e: 4689 mov r9, r1 +10002510: 9a0c ldr r2, [sp, #48] @ 0x30 +10002512: 4643 mov r3, r8 +10002514: 3263 adds r2, #99 @ 0x63 +10002516: 2ac6 cmp r2, #198 @ 0xc6 +10002518: f006 0202 and.w r2, r6, #2 +1000251c: 9210 str r2, [sp, #64] @ 0x40 +1000251e: 4649 mov r1, r9 +10002520: 9a0f ldr r2, [sp, #60] @ 0x3c +10002522: d82c bhi.n 1000257e <_etoa+0x3f6> +10002524: 2a00 cmp r2, #0 +10002526: d05e beq.n 100025e6 <_etoa+0x45e> +10002528: 2204 movs r2, #4 +1000252a: 9212 str r2, [sp, #72] @ 0x48 +1000252c: 430b orrs r3, r1 +1000252e: f43f af16 beq.w 1000235e <_etoa+0x1d6> +10002532: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002536: a358 add r3, pc, #352 @ (adr r3, 10002698 <_etoa+0x510>) +10002538: e9d3 2300 ldrd r2, r3, [r3] +1000253c: f7ff fa5c bl 100019f8 <__wrap___aeabi_dcmpge> +10002540: b148 cbz r0, 10002556 <_etoa+0x3ce> +10002542: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002546: a356 add r3, pc, #344 @ (adr r3, 100026a0 <_etoa+0x518>) +10002548: e9d3 2300 ldrd r2, r3, [r3] +1000254c: f7ff fa2c bl 100019a8 <__wrap___aeabi_dcmplt> +10002550: 2800 cmp r0, #0 +10002552: f47f af04 bne.w 1000235e <_etoa+0x1d6> +10002556: 9b0e ldr r3, [sp, #56] @ 0x38 +10002558: 2b00 cmp r3, #0 +1000255a: d050 beq.n 100025fe <_etoa+0x476> +1000255c: 9a13 ldr r2, [sp, #76] @ 0x4c +1000255e: 2a00 cmp r2, #0 +10002560: d07d beq.n 1000265e <_etoa+0x4d6> +10002562: 3b01 subs r3, #1 +10002564: 930e str r3, [sp, #56] @ 0x38 +10002566: 9b12 ldr r3, [sp, #72] @ 0x48 +10002568: 459a cmp sl, r3 +1000256a: d905 bls.n 10002578 <_etoa+0x3f0> +1000256c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000256e: 2b00 cmp r3, #0 +10002570: f000 80ae beq.w 100026d0 <_etoa+0x548> +10002574: 2302 movs r3, #2 +10002576: 9310 str r3, [sp, #64] @ 0x40 +10002578: 2300 movs r3, #0 +1000257a: 930f str r3, [sp, #60] @ 0x3c +1000257c: e044 b.n 10002608 <_etoa+0x480> +1000257e: bb22 cbnz r2, 100025ca <_etoa+0x442> +10002580: f1ba 0f05 cmp.w sl, #5 +10002584: d94f bls.n 10002626 <_etoa+0x49e> +10002586: f006 0302 and.w r3, r6, #2 +1000258a: 2b00 cmp r3, #0 +1000258c: d149 bne.n 10002622 <_etoa+0x49a> +1000258e: 2305 movs r3, #5 +10002590: 9312 str r3, [sp, #72] @ 0x48 +10002592: f1aa 0305 sub.w r3, sl, #5 +10002596: 930f str r3, [sp, #60] @ 0x3c +10002598: e03a b.n 10002610 <_etoa+0x488> +1000259a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000259e: 940a str r4, [sp, #40] @ 0x28 +100025a0: 930b str r3, [sp, #44] @ 0x2c +100025a2: e627 b.n 100021f4 <_etoa+0x6c> +100025a4: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100025a8: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100025ac: 4638 mov r0, r7 +100025ae: 962c str r6, [sp, #176] @ 0xb0 +100025b0: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +100025b4: 4634 mov r4, r6 +100025b6: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100025ba: 465a mov r2, fp +100025bc: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100025c0: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100025c4: 9b09 ldr r3, [sp, #36] @ 0x24 +100025c6: 9908 ldr r1, [sp, #32] +100025c8: e6bc b.n 10002344 <_etoa+0x1bc> +100025ca: 2205 movs r2, #5 +100025cc: 9212 str r2, [sp, #72] @ 0x48 +100025ce: e7ad b.n 1000252c <_etoa+0x3a4> +100025d0: 2300 movs r3, #0 +100025d2: 2202 movs r2, #2 +100025d4: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +100025d8: 2204 movs r2, #4 +100025da: 930c str r3, [sp, #48] @ 0x30 +100025dc: 9212 str r2, [sp, #72] @ 0x48 +100025de: e62c b.n 1000223a <_etoa+0xb2> +100025e0: f04f 0805 mov.w r8, #5 +100025e4: e6c2 b.n 1000236c <_etoa+0x1e4> +100025e6: f1ba 0f04 cmp.w sl, #4 +100025ea: d91f bls.n 1000262c <_etoa+0x4a4> +100025ec: 9b10 ldr r3, [sp, #64] @ 0x40 +100025ee: 2b00 cmp r3, #0 +100025f0: d178 bne.n 100026e4 <_etoa+0x55c> +100025f2: 2304 movs r3, #4 +100025f4: 9312 str r3, [sp, #72] @ 0x48 +100025f6: f1aa 0304 sub.w r3, sl, #4 +100025fa: 930f str r3, [sp, #60] @ 0x3c +100025fc: e004 b.n 10002608 <_etoa+0x480> +100025fe: 9b12 ldr r3, [sp, #72] @ 0x48 +10002600: 459a cmp sl, r3 +10002602: d831 bhi.n 10002668 <_etoa+0x4e0> +10002604: 9b0e ldr r3, [sp, #56] @ 0x38 +10002606: 930f str r3, [sp, #60] @ 0x3c +10002608: 9b0c ldr r3, [sp, #48] @ 0x30 +1000260a: 2b00 cmp r3, #0 +1000260c: f43f ae15 beq.w 1000223a <_etoa+0xb2> +10002610: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002614: 4642 mov r2, r8 +10002616: 464b mov r3, r9 +10002618: f7ff f91e bl 10001858 <__wrap___aeabi_ddiv> +1000261c: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10002620: e60b b.n 1000223a <_etoa+0xb2> +10002622: 2302 movs r3, #2 +10002624: 9310 str r3, [sp, #64] @ 0x40 +10002626: 2305 movs r3, #5 +10002628: 9312 str r3, [sp, #72] @ 0x48 +1000262a: e7f1 b.n 10002610 <_etoa+0x488> +1000262c: 2304 movs r3, #4 +1000262e: 9312 str r3, [sp, #72] @ 0x48 +10002630: e7ea b.n 10002608 <_etoa+0x480> +10002632: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +10002636: 46a0 mov r8, r4 +10002638: 9b0f ldr r3, [sp, #60] @ 0x3c +1000263a: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +1000263e: 9303 str r3, [sp, #12] +10002640: 9b0e ldr r3, [sp, #56] @ 0x38 +10002642: 465a mov r2, fp +10002644: 9302 str r3, [sp, #8] +10002646: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1000264a: 9304 str r3, [sp, #16] +1000264c: 4638 mov r0, r7 +1000264e: e9cd 8900 strd r8, r9, [sp] +10002652: 9b09 ldr r3, [sp, #36] @ 0x24 +10002654: 9908 ldr r1, [sp, #32] +10002656: f7ff fb37 bl 10001cc8 <_ftoa> +1000265a: 4602 mov r2, r0 +1000265c: e608 b.n 10002270 <_etoa+0xe8> +1000265e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002660: 459a cmp sl, r3 +10002662: d844 bhi.n 100026ee <_etoa+0x566> +10002664: 920f str r2, [sp, #60] @ 0x3c +10002666: e7cf b.n 10002608 <_etoa+0x480> +10002668: 9b10 ldr r3, [sp, #64] @ 0x40 +1000266a: b38b cbz r3, 100026d0 <_etoa+0x548> +1000266c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000266e: 930f str r3, [sp, #60] @ 0x3c +10002670: 2302 movs r3, #2 +10002672: 9310 str r3, [sp, #64] @ 0x40 +10002674: e7c8 b.n 10002608 <_etoa+0x480> +10002676: bf00 nop +10002678: 636f4361 .word 0x636f4361 +1000267c: 3fd287a7 .word 0x3fd287a7 +10002680: 0979a371 .word 0x0979a371 +10002684: 400a934f .word 0x400a934f +10002688: bbb55516 .word 0xbbb55516 +1000268c: 40026bb1 .word 0x40026bb1 +10002690: fefa39ef .word 0xfefa39ef +10002694: 3fe62e42 .word 0x3fe62e42 +10002698: eb1c432d .word 0xeb1c432d +1000269c: 3f1a36e2 .word 0x3f1a36e2 +100026a0: 00000000 .word 0x00000000 +100026a4: 412e8480 .word 0x412e8480 +100026a8: 3ff80000 .word 0x3ff80000 +100026ac: 3fe00000 .word 0x3fe00000 +100026b0: 402c0000 .word 0x402c0000 +100026b4: 40240000 .word 0x40240000 +100026b8: 40180000 .word 0x40180000 +100026bc: 3ff00000 .word 0x3ff00000 +100026c0: 509f79fb .word 0x509f79fb +100026c4: 3fd34413 .word 0x3fd34413 +100026c8: 8b60c8b3 .word 0x8b60c8b3 +100026cc: 3fc68a28 .word 0x3fc68a28 +100026d0: 9b12 ldr r3, [sp, #72] @ 0x48 +100026d2: ebaa 0303 sub.w r3, sl, r3 +100026d6: 930f str r3, [sp, #60] @ 0x3c +100026d8: e796 b.n 10002608 <_etoa+0x480> +100026da: eba3 0802 sub.w r8, r3, r2 +100026de: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100026e2: e643 b.n 1000236c <_etoa+0x1e4> +100026e4: 2304 movs r3, #4 +100026e6: 9312 str r3, [sp, #72] @ 0x48 +100026e8: 2302 movs r3, #2 +100026ea: 9310 str r3, [sp, #64] @ 0x40 +100026ec: e78c b.n 10002608 <_etoa+0x480> +100026ee: 9b10 ldr r3, [sp, #64] @ 0x40 +100026f0: 2b00 cmp r3, #0 +100026f2: d0ed beq.n 100026d0 <_etoa+0x548> +100026f4: 2302 movs r3, #2 +100026f6: 920f str r2, [sp, #60] @ 0x3c +100026f8: 9310 str r3, [sp, #64] @ 0x40 +100026fa: e785 b.n 10002608 <_etoa+0x480> + +100026fc <_vsnprintf>: +100026fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002700: b09b sub sp, #108 @ 0x6c +10002702: 9c24 ldr r4, [sp, #144] @ 0x90 +10002704: 4d95 ldr r5, [pc, #596] @ (1000295c <_vsnprintf+0x260>) +10002706: 940a str r4, [sp, #40] @ 0x28 +10002708: 4c95 ldr r4, [pc, #596] @ (10002960 <_vsnprintf+0x264>) +1000270a: f1b1 0a00 subs.w sl, r1, #0 +1000270e: bf18 it ne +10002710: 4683 movne fp, r0 +10002712: 6025 str r5, [r4, #0] +10002714: 7818 ldrb r0, [r3, #0] +10002716: 4c93 ldr r4, [pc, #588] @ (10002964 <_vsnprintf+0x268>) +10002718: 4691 mov r9, r2 +1000271a: bf08 it eq +1000271c: 46a3 moveq fp, r4 +1000271e: 9309 str r3, [sp, #36] @ 0x24 +10002720: 2800 cmp r0, #0 +10002722: f000 8293 beq.w 10002c4c <_vsnprintf+0x550> +10002726: f04f 0800 mov.w r8, #0 +1000272a: e00a b.n 10002742 <_vsnprintf+0x46> +1000272c: 4642 mov r2, r8 +1000272e: 464b mov r3, r9 +10002730: 4651 mov r1, sl +10002732: f108 0801 add.w r8, r8, #1 +10002736: 47d8 blx fp +10002738: 9b09 ldr r3, [sp, #36] @ 0x24 +1000273a: 7818 ldrb r0, [r3, #0] +1000273c: 2800 cmp r0, #0 +1000273e: f000 80ce beq.w 100028de <_vsnprintf+0x1e2> +10002742: 9b09 ldr r3, [sp, #36] @ 0x24 +10002744: 2825 cmp r0, #37 @ 0x25 +10002746: f103 0301 add.w r3, r3, #1 +1000274a: 9309 str r3, [sp, #36] @ 0x24 +1000274c: d1ee bne.n 1000272c <_vsnprintf+0x30> +1000274e: 461c mov r4, r3 +10002750: 2300 movs r3, #0 +10002752: 4622 mov r2, r4 +10002754: f812 0b01 ldrb.w r0, [r2], #1 +10002758: f1a0 0120 sub.w r1, r0, #32 +1000275c: 2910 cmp r1, #16 +1000275e: d80a bhi.n 10002776 <_vsnprintf+0x7a> +10002760: e8df f001 tbb [pc, r1] +10002764: 3c090940 .word 0x3c090940 +10002768: 09090909 .word 0x09090909 +1000276c: 38090909 .word 0x38090909 +10002770: 09093409 .word 0x09093409 +10002774: 30 .byte 0x30 +10002775: 00 .byte 0x00 +10002776: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000277a: 2909 cmp r1, #9 +1000277c: 9409 str r4, [sp, #36] @ 0x24 +1000277e: f240 808a bls.w 10002896 <_vsnprintf+0x19a> +10002782: 282a cmp r0, #42 @ 0x2a +10002784: f000 80f0 beq.w 10002968 <_vsnprintf+0x26c> +10002788: 2500 movs r5, #0 +1000278a: 282e cmp r0, #46 @ 0x2e +1000278c: f000 8096 beq.w 100028bc <_vsnprintf+0x1c0> +10002790: 2600 movs r6, #0 +10002792: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002796: 2912 cmp r1, #18 +10002798: d82d bhi.n 100027f6 <_vsnprintf+0xfa> +1000279a: e8df f011 tbh [pc, r1, lsl #1] +1000279e: 0149 .short 0x0149 +100027a0: 0143002c .word 0x0143002c +100027a4: 0138002c .word 0x0138002c +100027a8: 002c002c .word 0x002c002c +100027ac: 002c002c .word 0x002c002c +100027b0: 002c002c .word 0x002c002c +100027b4: 0027002c .word 0x0027002c +100027b8: 002c002c .word 0x002c002c +100027bc: 002c002c .word 0x002c002c +100027c0: 0027002c .word 0x0027002c +100027c4: 4614 mov r4, r2 +100027c6: f043 0301 orr.w r3, r3, #1 +100027ca: e7c2 b.n 10002752 <_vsnprintf+0x56> +100027cc: 4614 mov r4, r2 +100027ce: f043 0302 orr.w r3, r3, #2 +100027d2: e7be b.n 10002752 <_vsnprintf+0x56> +100027d4: 4614 mov r4, r2 +100027d6: f043 0304 orr.w r3, r3, #4 +100027da: e7ba b.n 10002752 <_vsnprintf+0x56> +100027dc: 4614 mov r4, r2 +100027de: f043 0310 orr.w r3, r3, #16 +100027e2: e7b6 b.n 10002752 <_vsnprintf+0x56> +100027e4: 4614 mov r4, r2 +100027e6: f043 0308 orr.w r3, r3, #8 +100027ea: e7b2 b.n 10002752 <_vsnprintf+0x56> +100027ec: 9909 ldr r1, [sp, #36] @ 0x24 +100027ee: 7848 ldrb r0, [r1, #1] +100027f0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100027f4: 3201 adds r2, #1 +100027f6: 2867 cmp r0, #103 @ 0x67 +100027f8: 9209 str r2, [sp, #36] @ 0x24 +100027fa: d87e bhi.n 100028fa <_vsnprintf+0x1fe> +100027fc: 2824 cmp r0, #36 @ 0x24 +100027fe: f240 80c1 bls.w 10002984 <_vsnprintf+0x288> +10002802: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +10002806: 2a42 cmp r2, #66 @ 0x42 +10002808: f200 80bc bhi.w 10002984 <_vsnprintf+0x288> +1000280c: e8df f012 tbh [pc, r2, lsl #1] +10002810: 00ba0150 .word 0x00ba0150 +10002814: 00ba00ba .word 0x00ba00ba +10002818: 00ba00ba .word 0x00ba00ba +1000281c: 00ba00ba .word 0x00ba00ba +10002820: 00ba00ba .word 0x00ba00ba +10002824: 00ba00ba .word 0x00ba00ba +10002828: 00ba00ba .word 0x00ba00ba +1000282c: 00ba00ba .word 0x00ba00ba +10002830: 00ba00ba .word 0x00ba00ba +10002834: 00ba00ba .word 0x00ba00ba +10002838: 00ba00ba .word 0x00ba00ba +1000283c: 00ba00ba .word 0x00ba00ba +10002840: 00ba00ba .word 0x00ba00ba +10002844: 00ba00ba .word 0x00ba00ba +10002848: 00ba00ba .word 0x00ba00ba +1000284c: 00ba00ba .word 0x00ba00ba +10002850: 01370119 .word 0x01370119 +10002854: 00ba0119 .word 0x00ba0119 +10002858: 00ba00ba .word 0x00ba00ba +1000285c: 00ba00ba .word 0x00ba00ba +10002860: 00ba00ba .word 0x00ba00ba +10002864: 00ba00ba .word 0x00ba00ba +10002868: 00ba00ba .word 0x00ba00ba +1000286c: 00ba00ba .word 0x00ba00ba +10002870: 00ba00ba .word 0x00ba00ba +10002874: 01bc00ba .word 0x01bc00ba +10002878: 00ba00ba .word 0x00ba00ba +1000287c: 00ba00ba .word 0x00ba00ba +10002880: 00ba00ba .word 0x00ba00ba +10002884: 00ba00ba .word 0x00ba00ba +10002888: 01bc00ba .word 0x01bc00ba +1000288c: 01bc0158 .word 0x01bc0158 +10002890: 01370119 .word 0x01370119 +10002894: 0119 .short 0x0119 +10002896: 2500 movs r5, #0 +10002898: e000 b.n 1000289c <_vsnprintf+0x1a0> +1000289a: 3201 adds r2, #1 +1000289c: eb05 0585 add.w r5, r5, r5, lsl #2 +100028a0: eb00 0545 add.w r5, r0, r5, lsl #1 +100028a4: 7810 ldrb r0, [r2, #0] +100028a6: 3d30 subs r5, #48 @ 0x30 +100028a8: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100028ac: 2909 cmp r1, #9 +100028ae: d9f4 bls.n 1000289a <_vsnprintf+0x19e> +100028b0: 282e cmp r0, #46 @ 0x2e +100028b2: 9209 str r2, [sp, #36] @ 0x24 +100028b4: f102 0201 add.w r2, r2, #1 +100028b8: f47f af6a bne.w 10002790 <_vsnprintf+0x94> +100028bc: 9909 ldr r1, [sp, #36] @ 0x24 +100028be: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100028c2: 7848 ldrb r0, [r1, #1] +100028c4: 4611 mov r1, r2 +100028c6: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100028ca: 2e09 cmp r6, #9 +100028cc: f240 8121 bls.w 10002b12 <_vsnprintf+0x416> +100028d0: 282a cmp r0, #42 @ 0x2a +100028d2: f000 812f beq.w 10002b34 <_vsnprintf+0x438> +100028d6: 9209 str r2, [sp, #36] @ 0x24 +100028d8: 2600 movs r6, #0 +100028da: 3201 adds r2, #1 +100028dc: e759 b.n 10002792 <_vsnprintf+0x96> +100028de: 4644 mov r4, r8 +100028e0: 45c1 cmp r9, r8 +100028e2: d801 bhi.n 100028e8 <_vsnprintf+0x1ec> +100028e4: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100028e8: 464b mov r3, r9 +100028ea: 4642 mov r2, r8 +100028ec: 4651 mov r1, sl +100028ee: 2000 movs r0, #0 +100028f0: 47d8 blx fp +100028f2: 4620 mov r0, r4 +100028f4: b01b add sp, #108 @ 0x6c +100028f6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100028fa: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100028fe: b2d2 uxtb r2, r2 +10002900: 2a0f cmp r2, #15 +10002902: d83f bhi.n 10002984 <_vsnprintf+0x288> +10002904: 2101 movs r1, #1 +10002906: f249 0741 movw r7, #36929 @ 0x9041 +1000290a: 4091 lsls r1, r2 +1000290c: 4039 ands r1, r7 +1000290e: f040 80f3 bne.w 10002af8 <_vsnprintf+0x3fc> +10002912: 2a0a cmp r2, #10 +10002914: d03d beq.n 10002992 <_vsnprintf+0x296> +10002916: 2a07 cmp r2, #7 +10002918: d134 bne.n 10002984 <_vsnprintf+0x288> +1000291a: 9d0a ldr r5, [sp, #40] @ 0x28 +1000291c: f855 2b04 ldr.w r2, [r5], #4 +10002920: 2a00 cmp r2, #0 +10002922: f000 8113 beq.w 10002b4c <_vsnprintf+0x450> +10002926: f043 0021 orr.w r0, r3, #33 @ 0x21 +1000292a: ab12 add r3, sp, #72 @ 0x48 +1000292c: 461f mov r7, r3 +1000292e: 930b str r3, [sp, #44] @ 0x2c +10002930: e003 b.n 1000293a <_vsnprintf+0x23e> +10002932: 2920 cmp r1, #32 +10002934: f000 8114 beq.w 10002b60 <_vsnprintf+0x464> +10002938: 461a mov r2, r3 +1000293a: f002 040f and.w r4, r2, #15 +1000293e: 4623 mov r3, r4 +10002940: 2c09 cmp r4, #9 +10002942: bf94 ite ls +10002944: 3330 addls r3, #48 @ 0x30 +10002946: 3337 addhi r3, #55 @ 0x37 +10002948: 2a0f cmp r2, #15 +1000294a: f807 3b01 strb.w r3, [r7], #1 +1000294e: f101 0101 add.w r1, r1, #1 +10002952: ea4f 1312 mov.w r3, r2, lsr #4 +10002956: d8ec bhi.n 10002932 <_vsnprintf+0x236> +10002958: e102 b.n 10002b60 <_vsnprintf+0x464> +1000295a: bf00 nop +1000295c: 100026fd .word 0x100026fd +10002960: 20000b88 .word 0x20000b88 +10002964: 10001a41 .word 0x10001a41 +10002968: 990a ldr r1, [sp, #40] @ 0x28 +1000296a: 9809 ldr r0, [sp, #36] @ 0x24 +1000296c: f851 5b04 ldr.w r5, [r1], #4 +10002970: 7840 ldrb r0, [r0, #1] +10002972: 2d00 cmp r5, #0 +10002974: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002978: bfbc itt lt +1000297a: f043 0302 orrlt.w r3, r3, #2 +1000297e: 426d neglt r5, r5 +10002980: 3201 adds r2, #1 +10002982: e702 b.n 1000278a <_vsnprintf+0x8e> +10002984: 4642 mov r2, r8 +10002986: 464b mov r3, r9 +10002988: 4651 mov r1, sl +1000298a: f108 0801 add.w r8, r8, #1 +1000298e: 47d8 blx fp +10002990: e6d2 b.n 10002738 <_vsnprintf+0x3c> +10002992: 990a ldr r1, [sp, #40] @ 0x28 +10002994: 2e00 cmp r6, #0 +10002996: f851 7b04 ldr.w r7, [r1], #4 +1000299a: bf18 it ne +1000299c: 4632 movne r2, r6 +1000299e: 7838 ldrb r0, [r7, #0] +100029a0: bf08 it eq +100029a2: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +100029a6: 2800 cmp r0, #0 +100029a8: f000 837b beq.w 100030a2 <_vsnprintf+0x9a6> +100029ac: 18bc adds r4, r7, r2 +100029ae: 46a4 mov ip, r4 +100029b0: 463a mov r2, r7 +100029b2: e004 b.n 100029be <_vsnprintf+0x2c2> +100029b4: f812 4f01 ldrb.w r4, [r2, #1]! +100029b8: 2c00 cmp r4, #0 +100029ba: f000 813f beq.w 10002c3c <_vsnprintf+0x540> +100029be: 4594 cmp ip, r2 +100029c0: d1f8 bne.n 100029b4 <_vsnprintf+0x2b8> +100029c2: 4664 mov r4, ip +100029c4: 1be4 subs r4, r4, r7 +100029c6: 055a lsls r2, r3, #21 +100029c8: f140 8122 bpl.w 10002c10 <_vsnprintf+0x514> +100029cc: 42b4 cmp r4, r6 +100029ce: bf28 it cs +100029d0: 4634 movcs r4, r6 +100029d2: f013 0302 ands.w r3, r3, #2 +100029d6: f000 8288 beq.w 10002eea <_vsnprintf+0x7ee> +100029da: 2302 movs r3, #2 +100029dc: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100029e0: 4642 mov r2, r8 +100029e2: 461d mov r5, r3 +100029e4: 4446 add r6, r8 +100029e6: e008 b.n 100029fa <_vsnprintf+0x2fe> +100029e8: 464b mov r3, r9 +100029ea: 4651 mov r1, sl +100029ec: 47d8 blx fp +100029ee: f817 0f01 ldrb.w r0, [r7, #1]! +100029f2: f108 0801 add.w r8, r8, #1 +100029f6: b110 cbz r0, 100029fe <_vsnprintf+0x302> +100029f8: 4642 mov r2, r8 +100029fa: 4546 cmp r6, r8 +100029fc: d1f4 bne.n 100029e8 <_vsnprintf+0x2ec> +100029fe: 462b mov r3, r5 +10002a00: 990b ldr r1, [sp, #44] @ 0x2c +10002a02: 9d0a ldr r5, [sp, #40] @ 0x28 +10002a04: 2b00 cmp r3, #0 +10002a06: f040 8141 bne.w 10002c8c <_vsnprintf+0x590> +10002a0a: 910a str r1, [sp, #40] @ 0x28 +10002a0c: e694 b.n 10002738 <_vsnprintf+0x3c> +10002a0e: 9909 ldr r1, [sp, #36] @ 0x24 +10002a10: 7848 ldrb r0, [r1, #1] +10002a12: 286c cmp r0, #108 @ 0x6c +10002a14: f47f aeec bne.w 100027f0 <_vsnprintf+0xf4> +10002a18: 460a mov r2, r1 +10002a1a: 7888 ldrb r0, [r1, #2] +10002a1c: f443 7340 orr.w r3, r3, #768 @ 0x300 +10002a20: 3203 adds r2, #3 +10002a22: e6e8 b.n 100027f6 <_vsnprintf+0xfa> +10002a24: 9909 ldr r1, [sp, #36] @ 0x24 +10002a26: f443 7300 orr.w r3, r3, #512 @ 0x200 +10002a2a: 7848 ldrb r0, [r1, #1] +10002a2c: 3201 adds r2, #1 +10002a2e: e6e2 b.n 100027f6 <_vsnprintf+0xfa> +10002a30: 9909 ldr r1, [sp, #36] @ 0x24 +10002a32: 7848 ldrb r0, [r1, #1] +10002a34: 2868 cmp r0, #104 @ 0x68 +10002a36: f000 8103 beq.w 10002c40 <_vsnprintf+0x544> +10002a3a: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002a3e: 3201 adds r2, #1 +10002a40: e6d9 b.n 100027f6 <_vsnprintf+0xfa> +10002a42: 2867 cmp r0, #103 @ 0x67 +10002a44: f000 80d9 beq.w 10002bfa <_vsnprintf+0x4fe> +10002a48: 2847 cmp r0, #71 @ 0x47 +10002a4a: f000 80dc beq.w 10002c06 <_vsnprintf+0x50a> +10002a4e: 2845 cmp r0, #69 @ 0x45 +10002a50: f000 80db beq.w 10002c0a <_vsnprintf+0x50e> +10002a54: e9cd 5303 strd r5, r3, [sp, #12] +10002a58: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a5a: 9602 str r6, [sp, #8] +10002a5c: 3307 adds r3, #7 +10002a5e: f023 0307 bic.w r3, r3, #7 +10002a62: 461c mov r4, r3 +10002a64: 4642 mov r2, r8 +10002a66: e8f4 6702 ldrd r6, r7, [r4], #8 +10002a6a: 464b mov r3, r9 +10002a6c: 4651 mov r1, sl +10002a6e: 4658 mov r0, fp +10002a70: e9cd 6700 strd r6, r7, [sp] +10002a74: 940a str r4, [sp, #40] @ 0x28 +10002a76: f7ff fb87 bl 10002188 <_etoa> +10002a7a: 4680 mov r8, r0 +10002a7c: e65c b.n 10002738 <_vsnprintf+0x3c> +10002a7e: 2846 cmp r0, #70 @ 0x46 +10002a80: bf08 it eq +10002a82: f043 0320 orreq.w r3, r3, #32 +10002a86: e9cd 5303 strd r5, r3, [sp, #12] +10002a8a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a8c: 9602 str r6, [sp, #8] +10002a8e: 3307 adds r3, #7 +10002a90: f023 0307 bic.w r3, r3, #7 +10002a94: 461c mov r4, r3 +10002a96: 4642 mov r2, r8 +10002a98: e8f4 6702 ldrd r6, r7, [r4], #8 +10002a9c: 464b mov r3, r9 +10002a9e: 4651 mov r1, sl +10002aa0: 4658 mov r0, fp +10002aa2: e9cd 6700 strd r6, r7, [sp] +10002aa6: 940a str r4, [sp, #40] @ 0x28 +10002aa8: f7ff f90e bl 10001cc8 <_ftoa> +10002aac: 4680 mov r8, r0 +10002aae: e643 b.n 10002738 <_vsnprintf+0x3c> +10002ab0: 4642 mov r2, r8 +10002ab2: 464b mov r3, r9 +10002ab4: 4651 mov r1, sl +10002ab6: 2025 movs r0, #37 @ 0x25 +10002ab8: f108 0801 add.w r8, r8, #1 +10002abc: 47d8 blx fp +10002abe: e63b b.n 10002738 <_vsnprintf+0x3c> +10002ac0: 9a0a ldr r2, [sp, #40] @ 0x28 +10002ac2: 0799 lsls r1, r3, #30 +10002ac4: f102 0404 add.w r4, r2, #4 +10002ac8: f108 0601 add.w r6, r8, #1 +10002acc: f140 80c6 bpl.w 10002c5c <_vsnprintf+0x560> +10002ad0: 7810 ldrb r0, [r2, #0] +10002ad2: 464b mov r3, r9 +10002ad4: 4642 mov r2, r8 +10002ad6: 4651 mov r1, sl +10002ad8: 47d8 blx fp +10002ada: 2d01 cmp r5, #1 +10002adc: bf88 it hi +10002ade: 44a8 addhi r8, r5 +10002ae0: f240 81bd bls.w 10002e5e <_vsnprintf+0x762> +10002ae4: 4632 mov r2, r6 +10002ae6: 464b mov r3, r9 +10002ae8: 4651 mov r1, sl +10002aea: 2020 movs r0, #32 +10002aec: 3601 adds r6, #1 +10002aee: 47d8 blx fp +10002af0: 4546 cmp r6, r8 +10002af2: d1f7 bne.n 10002ae4 <_vsnprintf+0x3e8> +10002af4: 940a str r4, [sp, #40] @ 0x28 +10002af6: e61f b.n 10002738 <_vsnprintf+0x3c> +10002af8: 286f cmp r0, #111 @ 0x6f +10002afa: f000 8081 beq.w 10002c00 <_vsnprintf+0x504> +10002afe: f240 8248 bls.w 10002f92 <_vsnprintf+0x896> +10002b02: 2878 cmp r0, #120 @ 0x78 +10002b04: f000 8190 beq.w 10002e28 <_vsnprintf+0x72c> +10002b08: 270a movs r7, #10 +10002b0a: f023 0310 bic.w r3, r3, #16 +10002b0e: 46bc mov ip, r7 +10002b10: e041 b.n 10002b96 <_vsnprintf+0x49a> +10002b12: 2600 movs r6, #0 +10002b14: eb06 0686 add.w r6, r6, r6, lsl #2 +10002b18: eb00 0046 add.w r0, r0, r6, lsl #1 +10002b1c: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002b20: f811 0f01 ldrb.w r0, [r1, #1]! +10002b24: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002b28: 2a09 cmp r2, #9 +10002b2a: d9f3 bls.n 10002b14 <_vsnprintf+0x418> +10002b2c: 460a mov r2, r1 +10002b2e: 9109 str r1, [sp, #36] @ 0x24 +10002b30: 3201 adds r2, #1 +10002b32: e62e b.n 10002792 <_vsnprintf+0x96> +10002b34: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002b38: f851 6b04 ldr.w r6, [r1], #4 +10002b3c: 7890 ldrb r0, [r2, #2] +10002b3e: 3202 adds r2, #2 +10002b40: 9209 str r2, [sp, #36] @ 0x24 +10002b42: 910a str r1, [sp, #40] @ 0x28 +10002b44: 3201 adds r2, #1 +10002b46: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002b4a: e622 b.n 10002792 <_vsnprintf+0x96> +10002b4c: f023 0010 bic.w r0, r3, #16 +10002b50: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b54: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002b58: f43f aee7 beq.w 1000292a <_vsnprintf+0x22e> +10002b5c: ab12 add r3, sp, #72 @ 0x48 +10002b5e: 930b str r3, [sp, #44] @ 0x2c +10002b60: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b62: 9006 str r0, [sp, #24] +10002b64: 9300 str r3, [sp, #0] +10002b66: 2308 movs r3, #8 +10002b68: 2010 movs r0, #16 +10002b6a: 9305 str r3, [sp, #20] +10002b6c: 2300 movs r3, #0 +10002b6e: 4642 mov r2, r8 +10002b70: e9cd 3002 strd r3, r0, [sp, #8] +10002b74: 9101 str r1, [sp, #4] +10002b76: 464b mov r3, r9 +10002b78: 4651 mov r1, sl +10002b7a: 4658 mov r0, fp +10002b7c: 9604 str r6, [sp, #16] +10002b7e: f7fe ffaf bl 10001ae0 <_ntoa_format> +10002b82: 950a str r5, [sp, #40] @ 0x28 +10002b84: 4680 mov r8, r0 +10002b86: e5d7 b.n 10002738 <_vsnprintf+0x3c> +10002b88: 2858 cmp r0, #88 @ 0x58 +10002b8a: d062 beq.n 10002c52 <_vsnprintf+0x556> +10002b8c: 2862 cmp r0, #98 @ 0x62 +10002b8e: f040 808f bne.w 10002cb0 <_vsnprintf+0x5b4> +10002b92: 2702 movs r7, #2 +10002b94: 46bc mov ip, r7 +10002b96: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002b9a: f000 80dd beq.w 10002d58 <_vsnprintf+0x65c> +10002b9e: f023 030d bic.w r3, r3, #13 +10002ba2: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002ba6: f040 8181 bne.w 10002eac <_vsnprintf+0x7b0> +10002baa: 990a ldr r1, [sp, #40] @ 0x28 +10002bac: 1d0f adds r7, r1, #4 +10002bae: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002bb2: f040 8237 bne.w 10003024 <_vsnprintf+0x928> +10002bb6: 065c lsls r4, r3, #25 +10002bb8: 9a0a ldr r2, [sp, #40] @ 0x28 +10002bba: f140 813b bpl.w 10002e34 <_vsnprintf+0x738> +10002bbe: 7812 ldrb r2, [r2, #0] +10002bc0: 2a00 cmp r2, #0 +10002bc2: f040 814e bne.w 10002e62 <_vsnprintf+0x766> +10002bc6: f023 0310 bic.w r3, r3, #16 +10002bca: 2800 cmp r0, #0 +10002bcc: f000 8149 beq.w 10002e62 <_vsnprintf+0x766> +10002bd0: 4611 mov r1, r2 +10002bd2: aa12 add r2, sp, #72 @ 0x48 +10002bd4: 920b str r2, [sp, #44] @ 0x2c +10002bd6: e9cd 5305 strd r5, r3, [sp, #20] +10002bda: e9cd c603 strd ip, r6, [sp, #12] +10002bde: 9101 str r1, [sp, #4] +10002be0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002be2: 4642 mov r2, r8 +10002be4: 9300 str r3, [sp, #0] +10002be6: 2300 movs r3, #0 +10002be8: 4651 mov r1, sl +10002bea: 9302 str r3, [sp, #8] +10002bec: 4658 mov r0, fp +10002bee: 464b mov r3, r9 +10002bf0: f7fe ff76 bl 10001ae0 <_ntoa_format> +10002bf4: 970a str r7, [sp, #40] @ 0x28 +10002bf6: 4680 mov r8, r0 +10002bf8: e59e b.n 10002738 <_vsnprintf+0x3c> +10002bfa: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002bfe: e729 b.n 10002a54 <_vsnprintf+0x358> +10002c00: 2708 movs r7, #8 +10002c02: 46bc mov ip, r7 +10002c04: e7c7 b.n 10002b96 <_vsnprintf+0x49a> +10002c06: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002c0a: f043 0320 orr.w r3, r3, #32 +10002c0e: e721 b.n 10002a54 <_vsnprintf+0x358> +10002c10: f013 0302 ands.w r3, r3, #2 +10002c14: f000 818e beq.w 10002f34 <_vsnprintf+0x838> +10002c18: 2302 movs r3, #2 +10002c1a: 950a str r5, [sp, #40] @ 0x28 +10002c1c: 461e mov r6, r3 +10002c1e: 460d mov r5, r1 +10002c20: 4642 mov r2, r8 +10002c22: 464b mov r3, r9 +10002c24: 4651 mov r1, sl +10002c26: 47d8 blx fp +10002c28: f817 0f01 ldrb.w r0, [r7, #1]! +10002c2c: f108 0801 add.w r8, r8, #1 +10002c30: 2800 cmp r0, #0 +10002c32: d1f5 bne.n 10002c20 <_vsnprintf+0x524> +10002c34: 4629 mov r1, r5 +10002c36: 4633 mov r3, r6 +10002c38: 9d0a ldr r5, [sp, #40] @ 0x28 +10002c3a: e6e3 b.n 10002a04 <_vsnprintf+0x308> +10002c3c: 1bd4 subs r4, r2, r7 +10002c3e: e6c2 b.n 100029c6 <_vsnprintf+0x2ca> +10002c40: 460a mov r2, r1 +10002c42: 7888 ldrb r0, [r1, #2] +10002c44: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002c48: 3203 adds r2, #3 +10002c4a: e5d4 b.n 100027f6 <_vsnprintf+0xfa> +10002c4c: 4604 mov r4, r0 +10002c4e: 4680 mov r8, r0 +10002c50: e646 b.n 100028e0 <_vsnprintf+0x1e4> +10002c52: 2710 movs r7, #16 +10002c54: f043 0320 orr.w r3, r3, #32 +10002c58: 46bc mov ip, r7 +10002c5a: e79c b.n 10002b96 <_vsnprintf+0x49a> +10002c5c: 2d01 cmp r5, #1 +10002c5e: f240 80f8 bls.w 10002e52 <_vsnprintf+0x756> +10002c62: 4646 mov r6, r8 +10002c64: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002c68: 442f add r7, r5 +10002c6a: 4632 mov r2, r6 +10002c6c: 464b mov r3, r9 +10002c6e: 4651 mov r1, sl +10002c70: 2020 movs r0, #32 +10002c72: 3601 adds r6, #1 +10002c74: 47d8 blx fp +10002c76: 42be cmp r6, r7 +10002c78: d1f7 bne.n 10002c6a <_vsnprintf+0x56e> +10002c7a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c7c: 4632 mov r2, r6 +10002c7e: 7818 ldrb r0, [r3, #0] +10002c80: 4651 mov r1, sl +10002c82: 464b mov r3, r9 +10002c84: 47d8 blx fp +10002c86: 44a8 add r8, r5 +10002c88: 940a str r4, [sp, #40] @ 0x28 +10002c8a: e555 b.n 10002738 <_vsnprintf+0x3c> +10002c8c: 4646 mov r6, r8 +10002c8e: 42a5 cmp r5, r4 +10002c90: f67f aebb bls.w 10002a0a <_vsnprintf+0x30e> +10002c94: 44a8 add r8, r5 +10002c96: eba8 0804 sub.w r8, r8, r4 +10002c9a: 460c mov r4, r1 +10002c9c: 4632 mov r2, r6 +10002c9e: 464b mov r3, r9 +10002ca0: 4651 mov r1, sl +10002ca2: 2020 movs r0, #32 +10002ca4: 3601 adds r6, #1 +10002ca6: 47d8 blx fp +10002ca8: 4546 cmp r6, r8 +10002caa: d1f7 bne.n 10002c9c <_vsnprintf+0x5a0> +10002cac: 4621 mov r1, r4 +10002cae: e6ac b.n 10002a0a <_vsnprintf+0x30e> +10002cb0: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002cb4: f000 80bb beq.w 10002e2e <_vsnprintf+0x732> +10002cb8: f44f 6280 mov.w r2, #1024 @ 0x400 +10002cbc: f023 0c11 bic.w ip, r3, #17 +10002cc0: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002cc4: 9b0a ldr r3, [sp, #40] @ 0x28 +10002cc6: d14a bne.n 10002d5e <_vsnprintf+0x662> +10002cc8: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002ccc: f103 0404 add.w r4, r3, #4 +10002cd0: f040 8134 bne.w 10002f3c <_vsnprintf+0x840> +10002cd4: f01c 0f40 tst.w ip, #64 @ 0x40 +10002cd8: f040 80a3 bne.w 10002e22 <_vsnprintf+0x726> +10002cdc: f01c 0f80 tst.w ip, #128 @ 0x80 +10002ce0: f000 81d3 beq.w 1000308a <_vsnprintf+0x98e> +10002ce4: f9b3 1000 ldrsh.w r1, [r3] +10002ce8: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002cec: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002cf0: b2bf uxth r7, r7 +10002cf2: 0fcb lsrs r3, r1, #31 +10002cf4: 2900 cmp r1, #0 +10002cf6: f000 8156 beq.w 10002fa6 <_vsnprintf+0x8aa> +10002cfa: 463a mov r2, r7 +10002cfc: a912 add r1, sp, #72 @ 0x48 +10002cfe: 460f mov r7, r1 +10002d00: f8df e3d8 ldr.w lr, [pc, #984] @ 100030dc <_vsnprintf+0x9e0> +10002d04: 910b str r1, [sp, #44] @ 0x2c +10002d06: 930a str r3, [sp, #40] @ 0x28 +10002d08: 950c str r5, [sp, #48] @ 0x30 +10002d0a: e001 b.n 10002d10 <_vsnprintf+0x614> +10002d0c: 2820 cmp r0, #32 +10002d0e: d00f beq.n 10002d30 <_vsnprintf+0x634> +10002d10: 4615 mov r5, r2 +10002d12: fbae 1302 umull r1, r3, lr, r2 +10002d16: 08db lsrs r3, r3, #3 +10002d18: eb03 0183 add.w r1, r3, r3, lsl #2 +10002d1c: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002d20: 3130 adds r1, #48 @ 0x30 +10002d22: 2d09 cmp r5, #9 +10002d24: 461a mov r2, r3 +10002d26: f100 0001 add.w r0, r0, #1 +10002d2a: f807 1b01 strb.w r1, [r7], #1 +10002d2e: d8ed bhi.n 10002d0c <_vsnprintf+0x610> +10002d30: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d32: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d34: e9cd 5c05 strd r5, ip, [sp, #20] +10002d38: e9cd 0301 strd r0, r3, [sp, #4] +10002d3c: 9604 str r6, [sp, #16] +10002d3e: 9b0b ldr r3, [sp, #44] @ 0x2c +10002d40: 4642 mov r2, r8 +10002d42: 9300 str r3, [sp, #0] +10002d44: 230a movs r3, #10 +10002d46: 4651 mov r1, sl +10002d48: 9303 str r3, [sp, #12] +10002d4a: 4658 mov r0, fp +10002d4c: 464b mov r3, r9 +10002d4e: f7fe fec7 bl 10001ae0 <_ntoa_format> +10002d52: 940a str r4, [sp, #40] @ 0x28 +10002d54: 4680 mov r8, r0 +10002d56: e4ef b.n 10002738 <_vsnprintf+0x3c> +10002d58: f023 030c bic.w r3, r3, #12 +10002d5c: e721 b.n 10002ba2 <_vsnprintf+0x4a6> +10002d5e: 3307 adds r3, #7 +10002d60: f023 0307 bic.w r3, r3, #7 +10002d64: 4619 mov r1, r3 +10002d66: 4608 mov r0, r1 +10002d68: 685b ldr r3, [r3, #4] +10002d6a: f850 1b08 ldr.w r1, [r0], #8 +10002d6e: 0fdf lsrs r7, r3, #31 +10002d70: 900a str r0, [sp, #40] @ 0x28 +10002d72: ea51 0003 orrs.w r0, r1, r3 +10002d76: d162 bne.n 10002e3e <_vsnprintf+0x742> +10002d78: 2a00 cmp r2, #0 +10002d7a: f040 819f bne.w 100030bc <_vsnprintf+0x9c0> +10002d7e: 4613 mov r3, r2 +10002d80: 4611 mov r1, r2 +10002d82: aa12 add r2, sp, #72 @ 0x48 +10002d84: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002d88: 2000 movs r0, #0 +10002d8a: 4615 mov r5, r2 +10002d8c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002d90: f8df e348 ldr.w lr, [pc, #840] @ 100030dc <_vsnprintf+0x9e0> +10002d94: 920b str r2, [sp, #44] @ 0x2c +10002d96: e001 b.n 10002d9c <_vsnprintf+0x6a0> +10002d98: 2820 cmp r0, #32 +10002d9a: d02d beq.n 10002df8 <_vsnprintf+0x6fc> +10002d9c: 185a adds r2, r3, r1 +10002d9e: f142 0200 adc.w r2, r2, #0 +10002da2: fbae 7802 umull r7, r8, lr, r2 +10002da6: f028 0703 bic.w r7, r8, #3 +10002daa: eb07 0798 add.w r7, r7, r8, lsr #2 +10002dae: 1bd2 subs r2, r2, r7 +10002db0: 461e mov r6, r3 +10002db2: 1a9b subs r3, r3, r2 +10002db4: f161 0700 sbc.w r7, r1, #0 +10002db8: 460c mov r4, r1 +10002dba: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002dbe: fb01 f103 mul.w r1, r1, r3 +10002dc2: fb0e 1107 mla r1, lr, r7, r1 +10002dc6: fba3 730e umull r7, r3, r3, lr +10002dca: 4419 add r1, r3 +10002dcc: 2305 movs r3, #5 +10002dce: f007 0801 and.w r8, r7, #1 +10002dd2: fba8 3803 umull r3, r8, r8, r3 +10002dd6: 189b adds r3, r3, r2 +10002dd8: 2e0a cmp r6, #10 +10002dda: f103 0330 add.w r3, r3, #48 @ 0x30 +10002dde: ea4f 0757 mov.w r7, r7, lsr #1 +10002de2: f174 0400 sbcs.w r4, r4, #0 +10002de6: f805 3b01 strb.w r3, [r5], #1 +10002dea: f100 0001 add.w r0, r0, #1 +10002dee: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002df2: ea4f 0151 mov.w r1, r1, lsr #1 +10002df6: d2cf bcs.n 10002d98 <_vsnprintf+0x69c> +10002df8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002dfc: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002e00: 9b0b ldr r3, [sp, #44] @ 0x2c +10002e02: 4642 mov r2, r8 +10002e04: 9300 str r3, [sp, #0] +10002e06: 230a movs r3, #10 +10002e08: e9cd 5c05 strd r5, ip, [sp, #20] +10002e0c: e9cd 0701 strd r0, r7, [sp, #4] +10002e10: 9604 str r6, [sp, #16] +10002e12: 9303 str r3, [sp, #12] +10002e14: 464b mov r3, r9 +10002e16: 4651 mov r1, sl +10002e18: 4658 mov r0, fp +10002e1a: f7fe fe61 bl 10001ae0 <_ntoa_format> +10002e1e: 4680 mov r8, r0 +10002e20: e48a b.n 10002738 <_vsnprintf+0x3c> +10002e22: 7819 ldrb r1, [r3, #0] +10002e24: 460f mov r7, r1 +10002e26: e764 b.n 10002cf2 <_vsnprintf+0x5f6> +10002e28: 2710 movs r7, #16 +10002e2a: 46bc mov ip, r7 +10002e2c: e6b3 b.n 10002b96 <_vsnprintf+0x49a> +10002e2e: f023 0c10 bic.w ip, r3, #16 +10002e32: e745 b.n 10002cc0 <_vsnprintf+0x5c4> +10002e34: 061c lsls r4, r3, #24 +10002e36: bf4c ite mi +10002e38: 8812 ldrhmi r2, [r2, #0] +10002e3a: 6812 ldrpl r2, [r2, #0] +10002e3c: e6c0 b.n 10002bc0 <_vsnprintf+0x4c4> +10002e3e: 460a mov r2, r1 +10002e40: 1e19 subs r1, r3, #0 +10002e42: db01 blt.n 10002e48 <_vsnprintf+0x74c> +10002e44: 4613 mov r3, r2 +10002e46: e79c b.n 10002d82 <_vsnprintf+0x686> +10002e48: 4252 negs r2, r2 +10002e4a: 4613 mov r3, r2 +10002e4c: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002e50: e797 b.n 10002d82 <_vsnprintf+0x686> +10002e52: 4613 mov r3, r2 +10002e54: 4651 mov r1, sl +10002e56: 7818 ldrb r0, [r3, #0] +10002e58: 4642 mov r2, r8 +10002e5a: 464b mov r3, r9 +10002e5c: 47d8 blx fp +10002e5e: 46b0 mov r8, r6 +10002e60: e648 b.n 10002af4 <_vsnprintf+0x3f8> +10002e62: f013 0f20 tst.w r3, #32 +10002e66: bf14 ite ne +10002e68: 2041 movne r0, #65 @ 0x41 +10002e6a: 2061 moveq r0, #97 @ 0x61 +10002e6c: ac12 add r4, sp, #72 @ 0x48 +10002e6e: 46a6 mov lr, r4 +10002e70: 940b str r4, [sp, #44] @ 0x2c +10002e72: 930a str r3, [sp, #40] @ 0x28 +10002e74: f1a0 040a sub.w r4, r0, #10 +10002e78: 950c str r5, [sp, #48] @ 0x30 +10002e7a: e002 b.n 10002e82 <_vsnprintf+0x786> +10002e7c: 2920 cmp r1, #32 +10002e7e: d012 beq.n 10002ea6 <_vsnprintf+0x7aa> +10002e80: 462a mov r2, r5 +10002e82: fbb2 f5fc udiv r5, r2, ip +10002e86: fb0c 2015 mls r0, ip, r5, r2 +10002e8a: b2c3 uxtb r3, r0 +10002e8c: 2809 cmp r0, #9 +10002e8e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002e92: bf8a itet hi +10002e94: 191b addhi r3, r3, r4 +10002e96: b2c3 uxtbls r3, r0 +10002e98: b2db uxtbhi r3, r3 +10002e9a: 4562 cmp r2, ip +10002e9c: f80e 3b01 strb.w r3, [lr], #1 +10002ea0: f101 0101 add.w r1, r1, #1 +10002ea4: d2ea bcs.n 10002e7c <_vsnprintf+0x780> +10002ea6: 9b0a ldr r3, [sp, #40] @ 0x28 +10002ea8: 9d0c ldr r5, [sp, #48] @ 0x30 +10002eaa: e694 b.n 10002bd6 <_vsnprintf+0x4da> +10002eac: 9a0a ldr r2, [sp, #40] @ 0x28 +10002eae: 3207 adds r2, #7 +10002eb0: f022 0207 bic.w r2, r2, #7 +10002eb4: 6851 ldr r1, [r2, #4] +10002eb6: f852 4b08 ldr.w r4, [r2], #8 +10002eba: 468e mov lr, r1 +10002ebc: 920a str r2, [sp, #40] @ 0x28 +10002ebe: ea54 0201 orrs.w r2, r4, r1 +10002ec2: d176 bne.n 10002fb2 <_vsnprintf+0x8b6> +10002ec4: f023 0310 bic.w r3, r3, #16 +10002ec8: 2800 cmp r0, #0 +10002eca: d072 beq.n 10002fb2 <_vsnprintf+0x8b6> +10002ecc: 2200 movs r2, #0 +10002ece: 4611 mov r1, r2 +10002ed0: aa12 add r2, sp, #72 @ 0x48 +10002ed2: 920b str r2, [sp, #44] @ 0x2c +10002ed4: e9cd 5305 strd r5, r3, [sp, #20] +10002ed8: 9b0b ldr r3, [sp, #44] @ 0x2c +10002eda: 4642 mov r2, r8 +10002edc: 9300 str r3, [sp, #0] +10002ede: 2300 movs r3, #0 +10002ee0: e9cd c603 strd ip, r6, [sp, #12] +10002ee4: 9101 str r1, [sp, #4] +10002ee6: 9302 str r3, [sp, #8] +10002ee8: e794 b.n 10002e14 <_vsnprintf+0x718> +10002eea: 42a5 cmp r5, r4 +10002eec: bf98 it ls +10002eee: 3401 addls r4, #1 +10002ef0: f67f ad74 bls.w 100029dc <_vsnprintf+0x2e0> +10002ef4: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ef8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002efc: eb05 0208 add.w r2, r5, r8 +10002f00: 461f mov r7, r3 +10002f02: 460d mov r5, r1 +10002f04: 1b14 subs r4, r2, r4 +10002f06: 4642 mov r2, r8 +10002f08: 464b mov r3, r9 +10002f0a: 4651 mov r1, sl +10002f0c: 2020 movs r0, #32 +10002f0e: f108 0801 add.w r8, r8, #1 +10002f12: 47d8 blx fp +10002f14: 45a0 cmp r8, r4 +10002f16: d1f6 bne.n 10002f06 <_vsnprintf+0x80a> +10002f18: 463b mov r3, r7 +10002f1a: 9f0a ldr r7, [sp, #40] @ 0x28 +10002f1c: 4629 mov r1, r5 +10002f1e: 7838 ldrb r0, [r7, #0] +10002f20: 9d0b ldr r5, [sp, #44] @ 0x2c +10002f22: 1c6c adds r4, r5, #1 +10002f24: 2800 cmp r0, #0 +10002f26: f43f ad70 beq.w 10002a0a <_vsnprintf+0x30e> +10002f2a: 2b00 cmp r3, #0 +10002f2c: f43f ae75 beq.w 10002c1a <_vsnprintf+0x51e> +10002f30: 2300 movs r3, #0 +10002f32: e553 b.n 100029dc <_vsnprintf+0x2e0> +10002f34: 42a5 cmp r5, r4 +10002f36: d8df bhi.n 10002ef8 <_vsnprintf+0x7fc> +10002f38: 3401 adds r4, #1 +10002f3a: e66e b.n 10002c1a <_vsnprintf+0x51e> +10002f3c: 6819 ldr r1, [r3, #0] +10002f3e: 0fcb lsrs r3, r1, #31 +10002f40: 2900 cmp r1, #0 +10002f42: f000 80a8 beq.w 10003096 <_vsnprintf+0x99a> +10002f46: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002f4a: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002f4e: a912 add r1, sp, #72 @ 0x48 +10002f50: 4608 mov r0, r1 +10002f52: f8df e188 ldr.w lr, [pc, #392] @ 100030dc <_vsnprintf+0x9e0> +10002f56: 910b str r1, [sp, #44] @ 0x2c +10002f58: 930a str r3, [sp, #40] @ 0x28 +10002f5a: 950c str r5, [sp, #48] @ 0x30 +10002f5c: e001 b.n 10002f62 <_vsnprintf+0x866> +10002f5e: 2f20 cmp r7, #32 +10002f60: d00f beq.n 10002f82 <_vsnprintf+0x886> +10002f62: 4615 mov r5, r2 +10002f64: fbae 1302 umull r1, r3, lr, r2 +10002f68: 08db lsrs r3, r3, #3 +10002f6a: eb03 0183 add.w r1, r3, r3, lsl #2 +10002f6e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002f72: 3130 adds r1, #48 @ 0x30 +10002f74: 2d09 cmp r5, #9 +10002f76: 461a mov r2, r3 +10002f78: f107 0701 add.w r7, r7, #1 +10002f7c: f800 1b01 strb.w r1, [r0], #1 +10002f80: d8ed bhi.n 10002f5e <_vsnprintf+0x862> +10002f82: 9b0a ldr r3, [sp, #40] @ 0x28 +10002f84: 9d0c ldr r5, [sp, #48] @ 0x30 +10002f86: e9cd 5c05 strd r5, ip, [sp, #20] +10002f8a: e9cd 7301 strd r7, r3, [sp, #4] +10002f8e: 9604 str r6, [sp, #16] +10002f90: e6d5 b.n 10002d3e <_vsnprintf+0x642> +10002f92: 2869 cmp r0, #105 @ 0x69 +10002f94: f023 0c10 bic.w ip, r3, #16 +10002f98: f040 808c bne.w 100030b4 <_vsnprintf+0x9b8> +10002f9c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002fa0: f43f ae8e beq.w 10002cc0 <_vsnprintf+0x5c4> +10002fa4: e688 b.n 10002cb8 <_vsnprintf+0x5bc> +10002fa6: 2a00 cmp r2, #0 +10002fa8: f43f aea8 beq.w 10002cfc <_vsnprintf+0x600> +10002fac: aa12 add r2, sp, #72 @ 0x48 +10002fae: 920b str r2, [sp, #44] @ 0x2c +10002fb0: e6c0 b.n 10002d34 <_vsnprintf+0x638> +10002fb2: f013 0f20 tst.w r3, #32 +10002fb6: bf14 ite ne +10002fb8: 2241 movne r2, #65 @ 0x41 +10002fba: 2261 moveq r2, #97 @ 0x61 +10002fbc: 2000 movs r0, #0 +10002fbe: a912 add r1, sp, #72 @ 0x48 +10002fc0: 3a0a subs r2, #10 +10002fc2: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002fc6: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002fca: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002fce: 4606 mov r6, r0 +10002fd0: 4688 mov r8, r1 +10002fd2: 4675 mov r5, lr +10002fd4: 4693 mov fp, r2 +10002fd6: 910b str r1, [sp, #44] @ 0x2c +10002fd8: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002fdc: e003 b.n 10002fe6 <_vsnprintf+0x8ea> +10002fde: 2e20 cmp r6, #32 +10002fe0: d017 beq.n 10003012 <_vsnprintf+0x916> +10002fe2: 4604 mov r4, r0 +10002fe4: 460d mov r5, r1 +10002fe6: 4629 mov r1, r5 +10002fe8: 463a mov r2, r7 +10002fea: 2300 movs r3, #0 +10002fec: 4620 mov r0, r4 +10002fee: f000 fc4b bl 10003888 <____aeabi_uldivmod_veneer> +10002ff2: b2d2 uxtb r2, r2 +10002ff4: 2a09 cmp r2, #9 +10002ff6: f102 0330 add.w r3, r2, #48 @ 0x30 +10002ffa: bf88 it hi +10002ffc: eb02 030b addhi.w r3, r2, fp +10003000: 42bc cmp r4, r7 +10003002: b2db uxtb r3, r3 +10003004: f175 0500 sbcs.w r5, r5, #0 +10003008: f808 3b01 strb.w r3, [r8], #1 +1000300c: f106 0601 add.w r6, r6, #1 +10003010: d2e5 bcs.n 10002fde <_vsnprintf+0x8e2> +10003012: 4631 mov r1, r6 +10003014: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10003018: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +1000301c: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10003020: 9e0e ldr r6, [sp, #56] @ 0x38 +10003022: e757 b.n 10002ed4 <_vsnprintf+0x7d8> +10003024: 990a ldr r1, [sp, #40] @ 0x28 +10003026: 6809 ldr r1, [r1, #0] +10003028: b951 cbnz r1, 10003040 <_vsnprintf+0x944> +1000302a: f023 0310 bic.w r3, r3, #16 +1000302e: b138 cbz r0, 10003040 <_vsnprintf+0x944> +10003030: a912 add r1, sp, #72 @ 0x48 +10003032: 910b str r1, [sp, #44] @ 0x2c +10003034: e9cd 5305 strd r5, r3, [sp, #20] +10003038: e9cd c603 strd ip, r6, [sp, #12] +1000303c: 9201 str r2, [sp, #4] +1000303e: e5cf b.n 10002be0 <_vsnprintf+0x4e4> +10003040: f013 0f20 tst.w r3, #32 +10003044: bf14 ite ne +10003046: 2041 movne r0, #65 @ 0x41 +10003048: 2061 moveq r0, #97 @ 0x61 +1000304a: ac12 add r4, sp, #72 @ 0x48 +1000304c: 46a6 mov lr, r4 +1000304e: 940b str r4, [sp, #44] @ 0x2c +10003050: 930a str r3, [sp, #40] @ 0x28 +10003052: f1a0 040a sub.w r4, r0, #10 +10003056: 950c str r5, [sp, #48] @ 0x30 +10003058: e002 b.n 10003060 <_vsnprintf+0x964> +1000305a: 2a20 cmp r2, #32 +1000305c: d012 beq.n 10003084 <_vsnprintf+0x988> +1000305e: 4629 mov r1, r5 +10003060: fbb1 f5fc udiv r5, r1, ip +10003064: fb0c 1015 mls r0, ip, r5, r1 +10003068: b2c3 uxtb r3, r0 +1000306a: 2809 cmp r0, #9 +1000306c: f103 0030 add.w r0, r3, #48 @ 0x30 +10003070: bf8a itet hi +10003072: 191b addhi r3, r3, r4 +10003074: b2c3 uxtbls r3, r0 +10003076: b2db uxtbhi r3, r3 +10003078: 4561 cmp r1, ip +1000307a: f80e 3b01 strb.w r3, [lr], #1 +1000307e: f102 0201 add.w r2, r2, #1 +10003082: d2ea bcs.n 1000305a <_vsnprintf+0x95e> +10003084: 9b0a ldr r3, [sp, #40] @ 0x28 +10003086: 9d0c ldr r5, [sp, #48] @ 0x30 +10003088: e7d4 b.n 10003034 <_vsnprintf+0x938> +1000308a: 6819 ldr r1, [r3, #0] +1000308c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10003090: eba7 77e1 sub.w r7, r7, r1, asr #31 +10003094: e62d b.n 10002cf2 <_vsnprintf+0x5f6> +10003096: 2a00 cmp r2, #0 +10003098: f43f af59 beq.w 10002f4e <_vsnprintf+0x852> +1000309c: aa12 add r2, sp, #72 @ 0x48 +1000309e: 920b str r2, [sp, #44] @ 0x2c +100030a0: e771 b.n 10002f86 <_vsnprintf+0x88a> +100030a2: f413 6480 ands.w r4, r3, #1024 @ 0x400 +100030a6: d00d beq.n 100030c4 <_vsnprintf+0x9c8> +100030a8: f013 0402 ands.w r4, r3, #2 +100030ac: d012 beq.n 100030d4 <_vsnprintf+0x9d8> +100030ae: 4604 mov r4, r0 +100030b0: 4646 mov r6, r8 +100030b2: e5ec b.n 10002c8e <_vsnprintf+0x592> +100030b4: 270a movs r7, #10 +100030b6: 4663 mov r3, ip +100030b8: 46bc mov ip, r7 +100030ba: e56c b.n 10002b96 <_vsnprintf+0x49a> +100030bc: ab12 add r3, sp, #72 @ 0x48 +100030be: 2000 movs r0, #0 +100030c0: 930b str r3, [sp, #44] @ 0x2c +100030c2: e69d b.n 10002e00 <_vsnprintf+0x704> +100030c4: f013 0302 ands.w r3, r3, #2 +100030c8: f47f ade0 bne.w 10002c8c <_vsnprintf+0x590> +100030cc: 2d00 cmp r5, #0 +100030ce: f47f af13 bne.w 10002ef8 <_vsnprintf+0x7fc> +100030d2: e49a b.n 10002a0a <_vsnprintf+0x30e> +100030d4: 2d00 cmp r5, #0 +100030d6: f47f af0d bne.w 10002ef4 <_vsnprintf+0x7f8> +100030da: e496 b.n 10002a0a <_vsnprintf+0x30e> +100030dc: cccccccd .word 0xcccccccd + +100030e0 : +100030e0: b570 push {r4, r5, r6, lr} +100030e2: 4694 mov ip, r2 +100030e4: 461e mov r6, r3 +100030e6: 4605 mov r5, r0 +100030e8: 460c mov r4, r1 +100030ea: b084 sub sp, #16 +100030ec: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100030f0: 4663 mov r3, ip +100030f2: a902 add r1, sp, #8 +100030f4: 9600 str r6, [sp, #0] +100030f6: 4803 ldr r0, [pc, #12] @ (10003104 ) +100030f8: e9cd 5402 strd r5, r4, [sp, #8] +100030fc: f7ff fafe bl 100026fc <_vsnprintf> +10003100: b004 add sp, #16 +10003102: bd70 pop {r4, r5, r6, pc} +10003104: 10001cbd .word 0x10001cbd + +10003108 : +10003108: b510 push {r4, lr} +1000310a: 4b09 ldr r3, [pc, #36] @ (10003130 ) +1000310c: b084 sub sp, #16 +1000310e: 681c ldr r4, [r3, #0] +10003110: b14c cbz r4, 10003126 +10003112: 4603 mov r3, r0 +10003114: 9100 str r1, [sp, #0] +10003116: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000311a: a903 add r1, sp, #12 +1000311c: 4805 ldr r0, [pc, #20] @ (10003134 ) +1000311e: 47a0 blx r4 +10003120: 2001 movs r0, #1 +10003122: b004 add sp, #16 +10003124: bd10 pop {r4, pc} +10003126: f000 f97d bl 10003424 <__wrap_puts> +1000312a: 4620 mov r0, r4 +1000312c: b004 add sp, #16 +1000312e: bd10 pop {r4, pc} +10003130: 20000b88 .word 0x20000b88 +10003134: 10001cb5 .word 0x10001cb5 + +10003138 <_exit>: +10003138: be00 bkpt 0x0000 +1000313a: e7fd b.n 10003138 <_exit> + +1000313c : +1000313c: b508 push {r3, lr} +1000313e: f7ff fffb bl 10003138 <_exit> +10003142: bf00 nop + +10003144 : +10003144: b538 push {r3, r4, r5, lr} +10003146: 4c06 ldr r4, [pc, #24] @ (10003160 ) +10003148: 4d06 ldr r5, [pc, #24] @ (10003164 ) +1000314a: f7fe fa07 bl 1000155c +1000314e: 42ac cmp r4, r5 +10003150: d204 bcs.n 1000315c +10003152: f854 3b04 ldr.w r3, [r4], #4 +10003156: 4798 blx r3 +10003158: 42ac cmp r4, r5 +1000315a: d3fa bcc.n 10003152 +1000315c: bd38 pop {r3, r4, r5, pc} +1000315e: bf00 nop +10003160: 100038e0 .word 0x100038e0 +10003164: 100038e4 .word 0x100038e4 + +10003168 : +10003168: 6803 ldr r3, [r0, #0] +1000316a: 4608 mov r0, r1 +1000316c: 4611 mov r1, r2 +1000316e: 4718 bx r3 + +10003170 : +10003170: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003174: 4615 mov r5, r2 +10003176: 7d42 ldrb r2, [r0, #21] +10003178: 4607 mov r7, r0 +1000317a: 4688 mov r8, r1 +1000317c: 2a00 cmp r2, #0 +1000317e: d046 beq.n 1000320e +10003180: 2d00 cmp r5, #0 +10003182: dd1d ble.n 100031c0 +10003184: 780b ldrb r3, [r1, #0] +10003186: 2b0a cmp r3, #10 +10003188: d023 beq.n 100031d2 +1000318a: 2d01 cmp r5, #1 +1000318c: f04f 0c00 mov.w ip, #0 +10003190: d018 beq.n 100031c4 +10003192: 4646 mov r6, r8 +10003194: 2401 movs r4, #1 +10003196: f816 2f01 ldrb.w r2, [r6, #1]! +1000319a: 4621 mov r1, r4 +1000319c: 2a0a cmp r2, #10 +1000319e: f104 0401 add.w r4, r4, #1 +100031a2: d022 beq.n 100031ea +100031a4: 42a5 cmp r5, r4 +100031a6: d1f6 bne.n 10003196 +100031a8: 4565 cmp r5, ip +100031aa: dc0b bgt.n 100031c4 +100031ac: eb08 0305 add.w r3, r8, r5 +100031b0: f813 3c01 ldrb.w r3, [r3, #-1] +100031b4: f1a3 030d sub.w r3, r3, #13 +100031b8: fab3 f383 clz r3, r3 +100031bc: 095b lsrs r3, r3, #5 +100031be: 753b strb r3, [r7, #20] +100031c0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100031c4: 683b ldr r3, [r7, #0] +100031c6: eba5 010c sub.w r1, r5, ip +100031ca: eb08 000c add.w r0, r8, ip +100031ce: 4798 blx r3 +100031d0: e7ec b.n 100031ac +100031d2: 7d03 ldrb r3, [r0, #20] +100031d4: 2b00 cmp r3, #0 +100031d6: d1d8 bne.n 1000318a +100031d8: 6803 ldr r3, [r0, #0] +100031da: 2102 movs r1, #2 +100031dc: 480f ldr r0, [pc, #60] @ (1000321c ) +100031de: 4798 blx r3 +100031e0: 2d01 cmp r5, #1 +100031e2: d0e3 beq.n 100031ac +100031e4: f04f 0c01 mov.w ip, #1 +100031e8: e7d3 b.n 10003192 +100031ea: f816 3c01 ldrb.w r3, [r6, #-1] +100031ee: 2b0d cmp r3, #13 +100031f0: d0d8 beq.n 100031a4 +100031f2: 458c cmp ip, r1 +100031f4: eb08 000c add.w r0, r8, ip +100031f8: eba1 010c sub.w r1, r1, ip +100031fc: da01 bge.n 10003202 +100031fe: 683b ldr r3, [r7, #0] +10003200: 4798 blx r3 +10003202: 2102 movs r1, #2 +10003204: 4805 ldr r0, [pc, #20] @ (1000321c ) +10003206: 683b ldr r3, [r7, #0] +10003208: 4798 blx r3 +1000320a: 46a4 mov ip, r4 +1000320c: e7ca b.n 100031a4 +1000320e: 4629 mov r1, r5 +10003210: 4640 mov r0, r8 +10003212: 683b ldr r3, [r7, #0] +10003214: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10003218: 4718 bx r3 +1000321a: bf00 nop +1000321c: 10003b50 .word 0x10003b50 + +10003220 : +10003220: 680b ldr r3, [r1, #0] +10003222: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003226: 2b80 cmp r3, #128 @ 0x80 +10003228: 460d mov r5, r1 +1000322a: 4606 mov r6, r0 +1000322c: d005 beq.n 1000323a +1000322e: 1c5a adds r2, r3, #1 +10003230: 442b add r3, r5 +10003232: 602a str r2, [r5, #0] +10003234: 711e strb r6, [r3, #4] +10003236: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000323a: 4b0f ldr r3, [pc, #60] @ (10003278 ) +1000323c: 681c ldr r4, [r3, #0] +1000323e: b1a4 cbz r4, 1000326a +10003240: 4f0e ldr r7, [pc, #56] @ (1000327c ) +10003242: f101 0804 add.w r8, r1, #4 +10003246: e001 b.n 1000324c +10003248: 6924 ldr r4, [r4, #16] +1000324a: b174 cbz r4, 1000326a +1000324c: 6823 ldr r3, [r4, #0] +1000324e: 2b00 cmp r3, #0 +10003250: d0fa beq.n 10003248 +10003252: 683b ldr r3, [r7, #0] +10003254: b10b cbz r3, 1000325a +10003256: 42a3 cmp r3, r4 +10003258: d1f6 bne.n 10003248 +1000325a: 4620 mov r0, r4 +1000325c: 4641 mov r1, r8 +1000325e: 682a ldr r2, [r5, #0] +10003260: f7ff ff86 bl 10003170 +10003264: 6924 ldr r4, [r4, #16] +10003266: 2c00 cmp r4, #0 +10003268: d1f0 bne.n 1000324c +1000326a: 2300 movs r3, #0 +1000326c: 2201 movs r2, #1 +1000326e: 442b add r3, r5 +10003270: 602a str r2, [r5, #0] +10003272: 711e strb r6, [r3, #4] +10003274: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003278: 20000b80 .word 0x20000b80 +1000327c: 20000b84 .word 0x20000b84 + +10003280 : +10003280: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10003284: b082 sub sp, #8 +10003286: 460d mov r5, r1 +10003288: 4691 mov r9, r2 +1000328a: 461c mov r4, r3 +1000328c: 4606 mov r6, r0 +1000328e: f7fd ff95 bl 100011bc +10003292: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003296: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1000329a: 4a2e ldr r2, [pc, #184] @ (10003354 ) +1000329c: 1882 adds r2, r0, r2 +1000329e: f141 0300 adc.w r3, r1, #0 +100032a2: 4594 cmp ip, r2 +100032a4: eb77 0103 sbcs.w r1, r7, r3 +100032a8: bf3c itt cc +100032aa: 4662 movcc r2, ip +100032ac: 463b movcc r3, r7 +100032ae: 482a ldr r0, [pc, #168] @ (10003358 ) +100032b0: f000 faf2 bl 10003898 <__mutex_try_enter_block_until_veneer> +100032b4: 1c6b adds r3, r5, #1 +100032b6: 4680 mov r8, r0 +100032b8: d040 beq.n 1000333c +100032ba: b30c cbz r4, 10003300 +100032bc: 4f27 ldr r7, [pc, #156] @ (1000335c ) +100032be: 4b28 ldr r3, [pc, #160] @ (10003360 ) +100032c0: 681c ldr r4, [r3, #0] +100032c2: b1b4 cbz r4, 100032f2 +100032c4: f1b9 0f00 cmp.w r9, #0 +100032c8: d11c bne.n 10003304 +100032ca: f8df 909c ldr.w r9, [pc, #156] @ 10003368 +100032ce: e001 b.n 100032d4 +100032d0: 6924 ldr r4, [r4, #16] +100032d2: b174 cbz r4, 100032f2 +100032d4: 6823 ldr r3, [r4, #0] +100032d6: 2b00 cmp r3, #0 +100032d8: d0fa beq.n 100032d0 +100032da: f8d9 3000 ldr.w r3, [r9] +100032de: b10b cbz r3, 100032e4 +100032e0: 429c cmp r4, r3 +100032e2: d1f5 bne.n 100032d0 +100032e4: 4620 mov r0, r4 +100032e6: 462a mov r2, r5 +100032e8: 4631 mov r1, r6 +100032ea: 47b8 blx r7 +100032ec: 6924 ldr r4, [r4, #16] +100032ee: 2c00 cmp r4, #0 +100032f0: d1f0 bne.n 100032d4 +100032f2: f1b8 0f00 cmp.w r8, #0 +100032f6: d126 bne.n 10003346 +100032f8: 4628 mov r0, r5 +100032fa: b002 add sp, #8 +100032fc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003300: 4f18 ldr r7, [pc, #96] @ (10003364 ) +10003302: e7dc b.n 100032be +10003304: f04f 0a0a mov.w sl, #10 +10003308: f8df 905c ldr.w r9, [pc, #92] @ 10003368 +1000330c: e002 b.n 10003314 +1000330e: 6924 ldr r4, [r4, #16] +10003310: 2c00 cmp r4, #0 +10003312: d0ee beq.n 100032f2 +10003314: 6823 ldr r3, [r4, #0] +10003316: 2b00 cmp r3, #0 +10003318: d0f9 beq.n 1000330e +1000331a: f8d9 3000 ldr.w r3, [r9] +1000331e: b10b cbz r3, 10003324 +10003320: 42a3 cmp r3, r4 +10003322: d1f4 bne.n 1000330e +10003324: 462a mov r2, r5 +10003326: 4631 mov r1, r6 +10003328: 4620 mov r0, r4 +1000332a: 47b8 blx r7 +1000332c: 2201 movs r2, #1 +1000332e: 4620 mov r0, r4 +10003330: f10d 0107 add.w r1, sp, #7 +10003334: f88d a007 strb.w sl, [sp, #7] +10003338: 47b8 blx r7 +1000333a: e7e8 b.n 1000330e +1000333c: 4630 mov r0, r6 +1000333e: f000 fa6f bl 10003820 +10003342: 4605 mov r5, r0 +10003344: e7b9 b.n 100032ba +10003346: 4804 ldr r0, [pc, #16] @ (10003358 ) +10003348: f000 faa2 bl 10003890 <__mutex_exit_veneer> +1000334c: 4628 mov r0, r5 +1000334e: b002 add sp, #8 +10003350: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003354: 000f4240 .word 0x000f4240 +10003358: 2000099c .word 0x2000099c +1000335c: 10003171 .word 0x10003171 +10003360: 20000b80 .word 0x20000b80 +10003364: 10003169 .word 0x10003169 +10003368: 20000b84 .word 0x20000b84 + +1000336c : +1000336c: 4a08 ldr r2, [pc, #32] @ (10003390 ) +1000336e: 6813 ldr r3, [r2, #0] +10003370: b923 cbnz r3, 1000337c +10003372: e00a b.n 1000338a +10003374: f103 0210 add.w r2, r3, #16 +10003378: 691b ldr r3, [r3, #16] +1000337a: b133 cbz r3, 1000338a +1000337c: 4283 cmp r3, r0 +1000337e: d1f9 bne.n 10003374 +10003380: b929 cbnz r1, 1000338e +10003382: 6918 ldr r0, [r3, #16] +10003384: 6010 str r0, [r2, #0] +10003386: 6119 str r1, [r3, #16] +10003388: 4770 bx lr +1000338a: b101 cbz r1, 1000338e +1000338c: 6010 str r0, [r2, #0] +1000338e: 4770 bx lr +10003390: 20000b80 .word 0x20000b80 + +10003394 : +10003394: b508 push {r3, lr} +10003396: f000 f9a3 bl 100036e0 +1000339a: 2001 movs r0, #1 +1000339c: bd08 pop {r3, pc} +1000339e: bf00 nop + +100033a0 <__wrap_putchar>: +100033a0: b5f0 push {r4, r5, r6, r7, lr} +100033a2: b083 sub sp, #12 +100033a4: 4606 mov r6, r0 +100033a6: f88d 0007 strb.w r0, [sp, #7] +100033aa: f7fd ff07 bl 100011bc +100033ae: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100033b2: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100033b6: 4a17 ldr r2, [pc, #92] @ (10003414 <__wrap_putchar+0x74>) +100033b8: 1882 adds r2, r0, r2 +100033ba: f141 0300 adc.w r3, r1, #0 +100033be: 4295 cmp r5, r2 +100033c0: eb74 0103 sbcs.w r1, r4, r3 +100033c4: bf3c itt cc +100033c6: 4623 movcc r3, r4 +100033c8: 462a movcc r2, r5 +100033ca: 4813 ldr r0, [pc, #76] @ (10003418 <__wrap_putchar+0x78>) +100033cc: f000 fa64 bl 10003898 <__mutex_try_enter_block_until_veneer> +100033d0: 4b12 ldr r3, [pc, #72] @ (1000341c <__wrap_putchar+0x7c>) +100033d2: 4607 mov r7, r0 +100033d4: 681c ldr r4, [r3, #0] +100033d6: b19c cbz r4, 10003400 <__wrap_putchar+0x60> +100033d8: 4d11 ldr r5, [pc, #68] @ (10003420 <__wrap_putchar+0x80>) +100033da: e001 b.n 100033e0 <__wrap_putchar+0x40> +100033dc: 6924 ldr r4, [r4, #16] +100033de: b17c cbz r4, 10003400 <__wrap_putchar+0x60> +100033e0: 6823 ldr r3, [r4, #0] +100033e2: 2b00 cmp r3, #0 +100033e4: d0fa beq.n 100033dc <__wrap_putchar+0x3c> +100033e6: 682b ldr r3, [r5, #0] +100033e8: b10b cbz r3, 100033ee <__wrap_putchar+0x4e> +100033ea: 429c cmp r4, r3 +100033ec: d1f6 bne.n 100033dc <__wrap_putchar+0x3c> +100033ee: 4620 mov r0, r4 +100033f0: 2201 movs r2, #1 +100033f2: f10d 0107 add.w r1, sp, #7 +100033f6: f7ff febb bl 10003170 +100033fa: 6924 ldr r4, [r4, #16] +100033fc: 2c00 cmp r4, #0 +100033fe: d1ef bne.n 100033e0 <__wrap_putchar+0x40> +10003400: b917 cbnz r7, 10003408 <__wrap_putchar+0x68> +10003402: 4630 mov r0, r6 +10003404: b003 add sp, #12 +10003406: bdf0 pop {r4, r5, r6, r7, pc} +10003408: 4803 ldr r0, [pc, #12] @ (10003418 <__wrap_putchar+0x78>) +1000340a: f000 fa41 bl 10003890 <__mutex_exit_veneer> +1000340e: 4630 mov r0, r6 +10003410: b003 add sp, #12 +10003412: bdf0 pop {r4, r5, r6, r7, pc} +10003414: 000f4240 .word 0x000f4240 +10003418: 2000099c .word 0x2000099c +1000341c: 20000b80 .word 0x20000b80 +10003420: 20000b84 .word 0x20000b84 + +10003424 <__wrap_puts>: +10003424: b538 push {r3, r4, r5, lr} +10003426: 4604 mov r4, r0 +10003428: f000 f9fa bl 10003820 +1000342c: 2301 movs r3, #1 +1000342e: 4605 mov r5, r0 +10003430: 461a mov r2, r3 +10003432: 4620 mov r0, r4 +10003434: 4629 mov r1, r5 +10003436: f7ff ff23 bl 10003280 +1000343a: 4b08 ldr r3, [pc, #32] @ (1000345c <__wrap_puts+0x38>) +1000343c: 681c ldr r4, [r3, #0] +1000343e: b12c cbz r4, 1000344c <__wrap_puts+0x28> +10003440: 6863 ldr r3, [r4, #4] +10003442: b12b cbz r3, 10003450 <__wrap_puts+0x2c> +10003444: 4798 blx r3 +10003446: 6924 ldr r4, [r4, #16] +10003448: 2c00 cmp r4, #0 +1000344a: d1f9 bne.n 10003440 <__wrap_puts+0x1c> +1000344c: 4628 mov r0, r5 +1000344e: bd38 pop {r3, r4, r5, pc} +10003450: 6924 ldr r4, [r4, #16] +10003452: 2c00 cmp r4, #0 +10003454: d1f4 bne.n 10003440 <__wrap_puts+0x1c> +10003456: 4628 mov r0, r5 +10003458: bd38 pop {r3, r4, r5, pc} +1000345a: bf00 nop +1000345c: 20000b80 .word 0x20000b80 + +10003460 <__wrap_vprintf>: +10003460: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003464: b0a2 sub sp, #136 @ 0x88 +10003466: 4604 mov r4, r0 +10003468: 460d mov r5, r1 +1000346a: f7fd fea7 bl 100011bc +1000346e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10003472: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003476: 4a26 ldr r2, [pc, #152] @ (10003510 <__wrap_vprintf+0xb0>) +10003478: f8df 80a4 ldr.w r8, [pc, #164] @ 10003520 <__wrap_vprintf+0xc0> +1000347c: 1882 adds r2, r0, r2 +1000347e: f141 0300 adc.w r3, r1, #0 +10003482: 4297 cmp r7, r2 +10003484: eb76 0103 sbcs.w r1, r6, r3 +10003488: bf3c itt cc +1000348a: 463a movcc r2, r7 +1000348c: 4633 movcc r3, r6 +1000348e: 4821 ldr r0, [pc, #132] @ (10003514 <__wrap_vprintf+0xb4>) +10003490: f000 fa02 bl 10003898 <__mutex_try_enter_block_until_veneer> +10003494: 2700 movs r7, #0 +10003496: 462b mov r3, r5 +10003498: 4622 mov r2, r4 +1000349a: 4606 mov r6, r0 +1000349c: a901 add r1, sp, #4 +1000349e: 481e ldr r0, [pc, #120] @ (10003518 <__wrap_vprintf+0xb8>) +100034a0: 9701 str r7, [sp, #4] +100034a2: f7ff fe1d bl 100030e0 +100034a6: 9b01 ldr r3, [sp, #4] +100034a8: 4605 mov r5, r0 +100034aa: f8d8 4000 ldr.w r4, [r8] +100034ae: b1c3 cbz r3, 100034e2 <__wrap_vprintf+0x82> +100034b0: 2c00 cmp r4, #0 +100034b2: d02b beq.n 1000350c <__wrap_vprintf+0xac> +100034b4: 4f19 ldr r7, [pc, #100] @ (1000351c <__wrap_vprintf+0xbc>) +100034b6: e001 b.n 100034bc <__wrap_vprintf+0x5c> +100034b8: 6924 ldr r4, [r4, #16] +100034ba: b174 cbz r4, 100034da <__wrap_vprintf+0x7a> +100034bc: 6823 ldr r3, [r4, #0] +100034be: 2b00 cmp r3, #0 +100034c0: d0fa beq.n 100034b8 <__wrap_vprintf+0x58> +100034c2: 683b ldr r3, [r7, #0] +100034c4: b10b cbz r3, 100034ca <__wrap_vprintf+0x6a> +100034c6: 42a3 cmp r3, r4 +100034c8: d1f6 bne.n 100034b8 <__wrap_vprintf+0x58> +100034ca: 4620 mov r0, r4 +100034cc: 9a01 ldr r2, [sp, #4] +100034ce: a902 add r1, sp, #8 +100034d0: f7ff fe4e bl 10003170 +100034d4: 6924 ldr r4, [r4, #16] +100034d6: 2c00 cmp r4, #0 +100034d8: d1f0 bne.n 100034bc <__wrap_vprintf+0x5c> +100034da: 2300 movs r3, #0 +100034dc: f8d8 4000 ldr.w r4, [r8] +100034e0: 9301 str r3, [sp, #4] +100034e2: b12c cbz r4, 100034f0 <__wrap_vprintf+0x90> +100034e4: 6863 ldr r3, [r4, #4] +100034e6: b143 cbz r3, 100034fa <__wrap_vprintf+0x9a> +100034e8: 4798 blx r3 +100034ea: 6924 ldr r4, [r4, #16] +100034ec: 2c00 cmp r4, #0 +100034ee: d1f9 bne.n 100034e4 <__wrap_vprintf+0x84> +100034f0: b92e cbnz r6, 100034fe <__wrap_vprintf+0x9e> +100034f2: 4628 mov r0, r5 +100034f4: b022 add sp, #136 @ 0x88 +100034f6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100034fa: 6924 ldr r4, [r4, #16] +100034fc: e7f1 b.n 100034e2 <__wrap_vprintf+0x82> +100034fe: 4805 ldr r0, [pc, #20] @ (10003514 <__wrap_vprintf+0xb4>) +10003500: f000 f9c6 bl 10003890 <__mutex_exit_veneer> +10003504: 4628 mov r0, r5 +10003506: b022 add sp, #136 @ 0x88 +10003508: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000350c: 9401 str r4, [sp, #4] +1000350e: e7ef b.n 100034f0 <__wrap_vprintf+0x90> +10003510: 000f4240 .word 0x000f4240 +10003514: 2000099c .word 0x2000099c +10003518: 10003221 .word 0x10003221 +1000351c: 20000b84 .word 0x20000b84 +10003520: 20000b80 .word 0x20000b80 + +10003524 <__wrap_printf>: +10003524: b40f push {r0, r1, r2, r3} +10003526: b500 push {lr} +10003528: b083 sub sp, #12 +1000352a: a904 add r1, sp, #16 +1000352c: f851 0b04 ldr.w r0, [r1], #4 +10003530: 9101 str r1, [sp, #4] +10003532: f7ff ff95 bl 10003460 <__wrap_vprintf> +10003536: b003 add sp, #12 +10003538: f85d eb04 ldr.w lr, [sp], #4 +1000353c: b004 add sp, #16 +1000353e: 4770 bx lr + +10003540 : +10003540: f1b1 0c00 subs.w ip, r1, #0 +10003544: dd1d ble.n 10003582 +10003546: 4a0f ldr r2, [pc, #60] @ (10003584 ) +10003548: 4b0f ldr r3, [pc, #60] @ (10003588 ) +1000354a: 6812 ldr r2, [r2, #0] +1000354c: b530 push {r4, r5, lr} +1000354e: 1ad3 subs r3, r2, r3 +10003550: fab3 f383 clz r3, r3 +10003554: 240d movs r4, #13 +10003556: 4d0d ldr r5, [pc, #52] @ (1000358c ) +10003558: 095b lsrs r3, r3, #5 +1000355a: 1e41 subs r1, r0, #1 +1000355c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003560: 448c add ip, r1 +10003562: f811 0f01 ldrb.w r0, [r1, #1]! +10003566: 4586 cmp lr, r0 +10003568: d006 beq.n 10003578 +1000356a: 6993 ldr r3, [r2, #24] +1000356c: 069b lsls r3, r3, #26 +1000356e: d4fc bmi.n 1000356a +10003570: 4561 cmp r1, ip +10003572: 6010 str r0, [r2, #0] +10003574: d1f5 bne.n 10003562 +10003576: bd30 pop {r4, r5, pc} +10003578: 6993 ldr r3, [r2, #24] +1000357a: 069d lsls r5, r3, #26 +1000357c: d4fc bmi.n 10003578 +1000357e: 6014 str r4, [r2, #0] +10003580: e7f3 b.n 1000356a +10003582: 4770 bx lr +10003584: 20000bcc .word 0x20000bcc +10003588: 40078000 .word 0x40078000 +1000358c: 20000bc8 .word 0x20000bc8 + +10003590 : +10003590: 4b22 ldr r3, [pc, #136] @ (1000361c ) +10003592: f1b1 0c00 subs.w ip, r1, #0 +10003596: b410 push {r4} +10003598: 681c ldr r4, [r3, #0] +1000359a: dd2e ble.n 100035fa +1000359c: 4603 mov r3, r0 +1000359e: 2000 movs r0, #0 +100035a0: 4a1f ldr r2, [pc, #124] @ (10003620 ) +100035a2: 1e59 subs r1, r3, #1 +100035a4: 6812 ldr r2, [r2, #0] +100035a6: 6993 ldr r3, [r2, #24] +100035a8: 06db lsls r3, r3, #27 +100035aa: d417 bmi.n 100035dc +100035ac: 3001 adds r0, #1 +100035ae: 6993 ldr r3, [r2, #24] +100035b0: 06db lsls r3, r3, #27 +100035b2: d4fc bmi.n 100035ae +100035b4: 6813 ldr r3, [r2, #0] +100035b6: 4584 cmp ip, r0 +100035b8: f801 3f01 strb.w r3, [r1, #1]! +100035bc: d1f3 bne.n 100035a6 +100035be: b14c cbz r4, 100035d4 +100035c0: 2150 movs r1, #80 @ 0x50 +100035c2: 4613 mov r3, r2 +100035c4: 6391 str r1, [r2, #56] @ 0x38 +100035c6: f853 2f34 ldr.w r2, [r3, #52]! +100035ca: f002 0238 and.w r2, r2, #56 @ 0x38 +100035ce: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035d2: 601a str r2, [r3, #0] +100035d4: 4660 mov r0, ip +100035d6: f85d 4b04 ldr.w r4, [sp], #4 +100035da: 4770 bx lr +100035dc: b14c cbz r4, 100035f2 +100035de: 2150 movs r1, #80 @ 0x50 +100035e0: 4613 mov r3, r2 +100035e2: 6391 str r1, [r2, #56] @ 0x38 +100035e4: f853 2f34 ldr.w r2, [r3, #52]! +100035e8: f002 0238 and.w r2, r2, #56 @ 0x38 +100035ec: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035f0: 601a str r2, [r3, #0] +100035f2: b178 cbz r0, 10003614 +100035f4: f85d 4b04 ldr.w r4, [sp], #4 +100035f8: 4770 bx lr +100035fa: b15c cbz r4, 10003614 +100035fc: 4b08 ldr r3, [pc, #32] @ (10003620 ) +100035fe: 2150 movs r1, #80 @ 0x50 +10003600: 681a ldr r2, [r3, #0] +10003602: 4613 mov r3, r2 +10003604: 6391 str r1, [r2, #56] @ 0x38 +10003606: f853 2f34 ldr.w r2, [r3, #52]! +1000360a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000360e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003612: 601a str r2, [r3, #0] +10003614: f06f 0002 mvn.w r0, #2 +10003618: e7dd b.n 100035d6 +1000361a: bf00 nop +1000361c: 20000b48 .word 0x20000b48 +10003620: 20000bcc .word 0x20000bcc + +10003624 : +10003624: 4b05 ldr r3, [pc, #20] @ (1000363c ) +10003626: 681b ldr r3, [r3, #0] +10003628: b133 cbz r3, 10003638 +1000362a: 2100 movs r1, #0 +1000362c: 4a04 ldr r2, [pc, #16] @ (10003640 ) +1000362e: 4805 ldr r0, [pc, #20] @ (10003644 ) +10003630: 6812 ldr r2, [r2, #0] +10003632: 6800 ldr r0, [r0, #0] +10003634: 6391 str r1, [r2, #56] @ 0x38 +10003636: 4718 bx r3 +10003638: 4770 bx lr +1000363a: bf00 nop +1000363c: 20000b48 .word 0x20000b48 +10003640: 20000bcc .word 0x20000bcc +10003644: 20000b4c .word 0x20000b4c + +10003648 : +10003648: 4b02 ldr r3, [pc, #8] @ (10003654 ) +1000364a: 681a ldr r2, [r3, #0] +1000364c: 6993 ldr r3, [r2, #24] +1000364e: 071b lsls r3, r3, #28 +10003650: d4fc bmi.n 1000364c +10003652: 4770 bx lr +10003654: 20000bcc .word 0x20000bcc + +10003658 : +10003658: b5f8 push {r3, r4, r5, r6, r7, lr} +1000365a: 4f1c ldr r7, [pc, #112] @ (100036cc ) +1000365c: 4d1c ldr r5, [pc, #112] @ (100036d0 ) +1000365e: 683a ldr r2, [r7, #0] +10003660: 4e1c ldr r6, [pc, #112] @ (100036d4 ) +10003662: 42aa cmp r2, r5 +10003664: bf14 ite ne +10003666: 2521 movne r5, #33 @ 0x21 +10003668: 2522 moveq r5, #34 @ 0x22 +1000366a: 4604 mov r4, r0 +1000366c: f8d6 c000 ldr.w ip, [r6] +10003670: b118 cbz r0, 1000367a +10003672: f1bc 0f00 cmp.w ip, #0 +10003676: d010 beq.n 1000369a +10003678: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000367a: f1bc 0f00 cmp.w ip, #0 +1000367e: d0fb beq.n 10003678 +10003680: 4601 mov r1, r0 +10003682: 6390 str r0, [r2, #56] @ 0x38 +10003684: 4628 mov r0, r5 +10003686: f7fc ffb5 bl 100005f4 +1000368a: 4628 mov r0, r5 +1000368c: 4912 ldr r1, [pc, #72] @ (100036d8 ) +1000368e: f7fc fff7 bl 10000680 +10003692: 4b12 ldr r3, [pc, #72] @ (100036dc ) +10003694: 6034 str r4, [r6, #0] +10003696: 601c str r4, [r3, #0] +10003698: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000369a: 460b mov r3, r1 +1000369c: 4a0f ldr r2, [pc, #60] @ (100036dc ) +1000369e: 490e ldr r1, [pc, #56] @ (100036d8 ) +100036a0: 6030 str r0, [r6, #0] +100036a2: 4628 mov r0, r5 +100036a4: 6013 str r3, [r2, #0] +100036a6: f7fc ffbb bl 10000620 +100036aa: 2101 movs r1, #1 +100036ac: 4628 mov r0, r5 +100036ae: f7fc ffa1 bl 100005f4 +100036b2: 683a ldr r2, [r7, #0] +100036b4: 2150 movs r1, #80 @ 0x50 +100036b6: 4613 mov r3, r2 +100036b8: 6391 str r1, [r2, #56] @ 0x38 +100036ba: f853 2f34 ldr.w r2, [r3, #52]! +100036be: f002 0238 and.w r2, r2, #56 @ 0x38 +100036c2: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100036c6: 601a str r2, [r3, #0] +100036c8: bdf8 pop {r3, r4, r5, r6, r7, pc} +100036ca: bf00 nop +100036cc: 20000bcc .word 0x20000bcc +100036d0: 40078000 .word 0x40078000 +100036d4: 20000b48 .word 0x20000b48 +100036d8: 10003625 .word 0x10003625 +100036dc: 20000b4c .word 0x20000b4c + +100036e0 : +100036e0: b510 push {r4, lr} +100036e2: 490e ldr r1, [pc, #56] @ (1000371c ) +100036e4: 4c0e ldr r4, [pc, #56] @ (10003720 ) +100036e6: 480f ldr r0, [pc, #60] @ (10003724 ) +100036e8: 4a0f ldr r2, [pc, #60] @ (10003728 ) +100036ea: 4b10 ldr r3, [pc, #64] @ (1000372c ) +100036ec: 7800 ldrb r0, [r0, #0] +100036ee: 6021 str r1, [r4, #0] +100036f0: 2000 movs r0, #0 +100036f2: 2102 movs r1, #2 +100036f4: 7812 ldrb r2, [r2, #0] +100036f6: 781b ldrb r3, [r3, #0] +100036f8: f7fc fea2 bl 10000440 +100036fc: 2102 movs r1, #2 +100036fe: 2001 movs r0, #1 +10003700: f7fc fe9e bl 10000440 +10003704: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003708: 6820 ldr r0, [r4, #0] +1000370a: f7fd fda1 bl 10001250 +1000370e: e8bd 4010 ldmia.w sp!, {r4, lr} +10003712: 2101 movs r1, #1 +10003714: 4806 ldr r0, [pc, #24] @ (10003730 ) +10003716: f7ff be29 b.w 1000336c +1000371a: bf00 nop +1000371c: 40070000 .word 0x40070000 +10003720: 20000bcc .word 0x20000bcc +10003724: 10003ba0 .word 0x10003ba0 +10003728: 10003b9c .word 0x10003b9c +1000372c: 10003b98 .word 0x10003b98 +10003730: 20000984 .word 0x20000984 + +10003734 : +10003734: 4684 mov ip, r0 +10003736: ea41 0300 orr.w r3, r1, r0 +1000373a: f013 0303 ands.w r3, r3, #3 +1000373e: d149 bne.n 100037d4 +10003740: 3a40 subs r2, #64 @ 0x40 +10003742: d323 bcc.n 1000378c +10003744: 680b ldr r3, [r1, #0] +10003746: 6003 str r3, [r0, #0] +10003748: 684b ldr r3, [r1, #4] +1000374a: 6043 str r3, [r0, #4] +1000374c: 688b ldr r3, [r1, #8] +1000374e: 6083 str r3, [r0, #8] +10003750: 68cb ldr r3, [r1, #12] +10003752: 60c3 str r3, [r0, #12] +10003754: 690b ldr r3, [r1, #16] +10003756: 6103 str r3, [r0, #16] +10003758: 694b ldr r3, [r1, #20] +1000375a: 6143 str r3, [r0, #20] +1000375c: 698b ldr r3, [r1, #24] +1000375e: 6183 str r3, [r0, #24] +10003760: 69cb ldr r3, [r1, #28] +10003762: 61c3 str r3, [r0, #28] +10003764: 6a0b ldr r3, [r1, #32] +10003766: 6203 str r3, [r0, #32] +10003768: 6a4b ldr r3, [r1, #36] @ 0x24 +1000376a: 6243 str r3, [r0, #36] @ 0x24 +1000376c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000376e: 6283 str r3, [r0, #40] @ 0x28 +10003770: 6acb ldr r3, [r1, #44] @ 0x2c +10003772: 62c3 str r3, [r0, #44] @ 0x2c +10003774: 6b0b ldr r3, [r1, #48] @ 0x30 +10003776: 6303 str r3, [r0, #48] @ 0x30 +10003778: 6b4b ldr r3, [r1, #52] @ 0x34 +1000377a: 6343 str r3, [r0, #52] @ 0x34 +1000377c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000377e: 6383 str r3, [r0, #56] @ 0x38 +10003780: 6bcb ldr r3, [r1, #60] @ 0x3c +10003782: 63c3 str r3, [r0, #60] @ 0x3c +10003784: 3040 adds r0, #64 @ 0x40 +10003786: 3140 adds r1, #64 @ 0x40 +10003788: 3a40 subs r2, #64 @ 0x40 +1000378a: d2db bcs.n 10003744 +1000378c: 3230 adds r2, #48 @ 0x30 +1000378e: d30b bcc.n 100037a8 +10003790: 680b ldr r3, [r1, #0] +10003792: 6003 str r3, [r0, #0] +10003794: 684b ldr r3, [r1, #4] +10003796: 6043 str r3, [r0, #4] +10003798: 688b ldr r3, [r1, #8] +1000379a: 6083 str r3, [r0, #8] +1000379c: 68cb ldr r3, [r1, #12] +1000379e: 60c3 str r3, [r0, #12] +100037a0: 3010 adds r0, #16 +100037a2: 3110 adds r1, #16 +100037a4: 3a10 subs r2, #16 +100037a6: d2f3 bcs.n 10003790 +100037a8: 320c adds r2, #12 +100037aa: d305 bcc.n 100037b8 +100037ac: f851 3b04 ldr.w r3, [r1], #4 +100037b0: f840 3b04 str.w r3, [r0], #4 +100037b4: 3a04 subs r2, #4 +100037b6: d2f9 bcs.n 100037ac +100037b8: 3204 adds r2, #4 +100037ba: d008 beq.n 100037ce +100037bc: 07d2 lsls r2, r2, #31 +100037be: bf1c itt ne +100037c0: f811 3b01 ldrbne.w r3, [r1], #1 +100037c4: f800 3b01 strbne.w r3, [r0], #1 +100037c8: d301 bcc.n 100037ce +100037ca: 880b ldrh r3, [r1, #0] +100037cc: 8003 strh r3, [r0, #0] +100037ce: 4660 mov r0, ip +100037d0: 4770 bx lr +100037d2: bf00 nop +100037d4: 2a08 cmp r2, #8 +100037d6: d313 bcc.n 10003800 +100037d8: 078b lsls r3, r1, #30 +100037da: d0b1 beq.n 10003740 +100037dc: f010 0303 ands.w r3, r0, #3 +100037e0: d0ae beq.n 10003740 +100037e2: f1c3 0304 rsb r3, r3, #4 +100037e6: 1ad2 subs r2, r2, r3 +100037e8: 07db lsls r3, r3, #31 +100037ea: bf1c itt ne +100037ec: f811 3b01 ldrbne.w r3, [r1], #1 +100037f0: f800 3b01 strbne.w r3, [r0], #1 +100037f4: d3a4 bcc.n 10003740 +100037f6: f831 3b02 ldrh.w r3, [r1], #2 +100037fa: f820 3b02 strh.w r3, [r0], #2 +100037fe: e79f b.n 10003740 +10003800: 3a04 subs r2, #4 +10003802: d3d9 bcc.n 100037b8 +10003804: 3a01 subs r2, #1 +10003806: f811 3b01 ldrb.w r3, [r1], #1 +1000380a: f800 3b01 strb.w r3, [r0], #1 +1000380e: d2f9 bcs.n 10003804 +10003810: 780b ldrb r3, [r1, #0] +10003812: 7003 strb r3, [r0, #0] +10003814: 784b ldrb r3, [r1, #1] +10003816: 7043 strb r3, [r0, #1] +10003818: 788b ldrb r3, [r1, #2] +1000381a: 7083 strb r3, [r0, #2] +1000381c: 4660 mov r0, ip +1000381e: 4770 bx lr + +10003820 : +10003820: f020 0103 bic.w r1, r0, #3 +10003824: f010 0003 ands.w r0, r0, #3 +10003828: f1c0 0000 rsb r0, r0, #0 +1000382c: f851 3b04 ldr.w r3, [r1], #4 +10003830: f100 0c04 add.w ip, r0, #4 +10003834: ea4f 0ccc mov.w ip, ip, lsl #3 +10003838: f06f 0200 mvn.w r2, #0 +1000383c: bf1c itt ne +1000383e: fa22 f20c lsrne.w r2, r2, ip +10003842: 4313 orrne r3, r2 +10003844: f04f 0c01 mov.w ip, #1 +10003848: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000384c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003850: eba3 020c sub.w r2, r3, ip +10003854: ea22 0203 bic.w r2, r2, r3 +10003858: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000385c: bf04 itt eq +1000385e: f851 3b04 ldreq.w r3, [r1], #4 +10003862: 3004 addeq r0, #4 +10003864: d0f4 beq.n 10003850 +10003866: f1c2 0100 rsb r1, r2, #0 +1000386a: ea02 0201 and.w r2, r2, r1 +1000386e: fab2 f282 clz r2, r2 +10003872: f1c2 021f rsb r2, r2, #31 +10003876: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000387a: 4770 bx lr + +1000387c <_fini>: +1000387c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000387e: bf00 nop + +10003880 <____aeabi_f2d_veneer>: +10003880: f85f f000 ldr.w pc, [pc] @ 10003884 <____aeabi_f2d_veneer+0x4> +10003884: 200004e9 .word 0x200004e9 + +10003888 <____aeabi_uldivmod_veneer>: +10003888: f85f f000 ldr.w pc, [pc] @ 1000388c <____aeabi_uldivmod_veneer+0x4> +1000388c: 20000599 .word 0x20000599 + +10003890 <__mutex_exit_veneer>: +10003890: f85f f000 ldr.w pc, [pc] @ 10003894 <__mutex_exit_veneer+0x4> +10003894: 200001e5 .word 0x200001e5 + +10003898 <__mutex_try_enter_block_until_veneer>: +10003898: f85f f000 ldr.w pc, [pc] @ 1000389c <__mutex_try_enter_block_until_veneer+0x4> +1000389c: 2000017d .word 0x2000017d + +100038a0 <__pre_init_runtime_init_bootrom_reset>: +100038a0: 10001609 .... + +100038a4 <__pre_init_runtime_init_early_resets>: +100038a4: 1000157d }... + +100038a8 <__pre_init_runtime_init_usb_power_down>: +100038a8: 100015b1 .... + +100038ac <__pre_init_runtime_init_clocks>: +100038ac: 1000169d .... + +100038b0 <__pre_init_runtime_init_post_clock_resets>: +100038b0: 100015e9 .... + +100038b4 <__pre_init_runtime_init_boot_locks_reset>: +100038b4: 10001501 .... + +100038b8 <__pre_init_runtime_init_spin_locks_reset>: +100038b8: 10001631 1... + +100038bc <__pre_init_runtime_init_bootrom_locking_enable>: +100038bc: 100014ed .... + +100038c0 <__pre_init_runtime_init_mutex>: +100038c0: 1000093d =... + +100038c4 <__pre_init_runtime_init_install_ram_vector_table>: +100038c4: 10001635 5... + +100038c8 <__pre_init_runtime_init_default_alarm_pool>: +100038c8: 10000cb9 .... + +100038cc <__pre_init_first_per_core_initializer>: +100038cc: 1000154d M... + +100038d0 <__pre_init_runtime_init_per_core_bootrom_reset>: +100038d0: 1000161d .... + +100038d4 <__pre_init_runtime_init_per_core_enable_coprocessors>: +100038d4: 100015cd .... + +100038d8 <__pre_init_spinlock_set_extexclall>: +100038d8: 1000058d .... + +100038dc <__pre_init_runtime_init_per_core_irq_priorities>: +100038dc: 100005b5 .... + +100038e0 <__frame_dummy_init_array_entry>: +100038e0: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fbf1 bl 20000918 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_drsub>: +20000220: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 +20000224: e002 b.n 2000022c <__adddf3> +20000226: bf00 nop + +20000228 <__aeabi_dsub>: +20000228: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 + +2000022c <__adddf3>: +2000022c: b530 push {r4, r5, lr} +2000022e: ea4f 0441 mov.w r4, r1, lsl #1 +20000232: ea4f 0543 mov.w r5, r3, lsl #1 +20000236: ea94 0f05 teq r4, r5 +2000023a: bf08 it eq +2000023c: ea90 0f02 teqeq r0, r2 +20000240: bf1f itttt ne +20000242: ea54 0c00 orrsne.w ip, r4, r0 +20000246: ea55 0c02 orrsne.w ip, r5, r2 +2000024a: ea7f 5c64 mvnsne.w ip, r4, asr #21 +2000024e: ea7f 5c65 mvnsne.w ip, r5, asr #21 +20000252: f000 80e2 beq.w 2000041a <__adddf3+0x1ee> +20000256: ea4f 5454 mov.w r4, r4, lsr #21 +2000025a: ebd4 5555 rsbs r5, r4, r5, lsr #21 +2000025e: bfb8 it lt +20000260: 426d neglt r5, r5 +20000262: dd0c ble.n 2000027e <__adddf3+0x52> +20000264: 442c add r4, r5 +20000266: ea80 0202 eor.w r2, r0, r2 +2000026a: ea81 0303 eor.w r3, r1, r3 +2000026e: ea82 0000 eor.w r0, r2, r0 +20000272: ea83 0101 eor.w r1, r3, r1 +20000276: ea80 0202 eor.w r2, r0, r2 +2000027a: ea81 0303 eor.w r3, r1, r3 +2000027e: 2d36 cmp r5, #54 @ 0x36 +20000280: bf88 it hi +20000282: bd30 pophi {r4, r5, pc} +20000284: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 +20000288: ea4f 3101 mov.w r1, r1, lsl #12 +2000028c: f44f 1c80 mov.w ip, #1048576 @ 0x100000 +20000290: ea4c 3111 orr.w r1, ip, r1, lsr #12 +20000294: d002 beq.n 2000029c <__adddf3+0x70> +20000296: 4240 negs r0, r0 +20000298: eb61 0141 sbc.w r1, r1, r1, lsl #1 +2000029c: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 +200002a0: ea4f 3303 mov.w r3, r3, lsl #12 +200002a4: ea4c 3313 orr.w r3, ip, r3, lsr #12 +200002a8: d002 beq.n 200002b0 <__adddf3+0x84> +200002aa: 4252 negs r2, r2 +200002ac: eb63 0343 sbc.w r3, r3, r3, lsl #1 +200002b0: ea94 0f05 teq r4, r5 +200002b4: f000 80a7 beq.w 20000406 <__adddf3+0x1da> +200002b8: f1a4 0401 sub.w r4, r4, #1 +200002bc: f1d5 0e20 rsbs lr, r5, #32 +200002c0: db0d blt.n 200002de <__adddf3+0xb2> +200002c2: fa02 fc0e lsl.w ip, r2, lr +200002c6: fa22 f205 lsr.w r2, r2, r5 +200002ca: 1880 adds r0, r0, r2 +200002cc: f141 0100 adc.w r1, r1, #0 +200002d0: fa03 f20e lsl.w r2, r3, lr +200002d4: 1880 adds r0, r0, r2 +200002d6: fa43 f305 asr.w r3, r3, r5 +200002da: 4159 adcs r1, r3 +200002dc: e00e b.n 200002fc <__adddf3+0xd0> +200002de: f1a5 0520 sub.w r5, r5, #32 +200002e2: f10e 0e20 add.w lr, lr, #32 +200002e6: 2a01 cmp r2, #1 +200002e8: fa03 fc0e lsl.w ip, r3, lr +200002ec: bf28 it cs +200002ee: f04c 0c02 orrcs.w ip, ip, #2 +200002f2: fa43 f305 asr.w r3, r3, r5 +200002f6: 18c0 adds r0, r0, r3 +200002f8: eb51 71e3 adcs.w r1, r1, r3, asr #31 +200002fc: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 +20000300: d507 bpl.n 20000312 <__adddf3+0xe6> +20000302: f04f 0e00 mov.w lr, #0 +20000306: f1dc 0c00 rsbs ip, ip, #0 +2000030a: eb7e 0000 sbcs.w r0, lr, r0 +2000030e: eb6e 0101 sbc.w r1, lr, r1 +20000312: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 +20000316: d31b bcc.n 20000350 <__adddf3+0x124> +20000318: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 +2000031c: d30c bcc.n 20000338 <__adddf3+0x10c> +2000031e: 0849 lsrs r1, r1, #1 +20000320: ea5f 0030 movs.w r0, r0, rrx +20000324: ea4f 0c3c mov.w ip, ip, rrx +20000328: f104 0401 add.w r4, r4, #1 +2000032c: ea4f 5244 mov.w r2, r4, lsl #21 +20000330: f512 0f80 cmn.w r2, #4194304 @ 0x400000 +20000334: f080 809a bcs.w 2000046c <__adddf3+0x240> +20000338: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 +2000033c: bf08 it eq +2000033e: ea5f 0c50 movseq.w ip, r0, lsr #1 +20000342: f150 0000 adcs.w r0, r0, #0 +20000346: eb41 5104 adc.w r1, r1, r4, lsl #20 +2000034a: ea41 0105 orr.w r1, r1, r5 +2000034e: bd30 pop {r4, r5, pc} +20000350: ea5f 0c4c movs.w ip, ip, lsl #1 +20000354: 4140 adcs r0, r0 +20000356: eb41 0101 adc.w r1, r1, r1 +2000035a: 3c01 subs r4, #1 +2000035c: bf28 it cs +2000035e: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 +20000362: d2e9 bcs.n 20000338 <__adddf3+0x10c> +20000364: f091 0f00 teq r1, #0 +20000368: bf04 itt eq +2000036a: 4601 moveq r1, r0 +2000036c: 2000 moveq r0, #0 +2000036e: fab1 f381 clz r3, r1 +20000372: bf08 it eq +20000374: 3320 addeq r3, #32 +20000376: f1a3 030b sub.w r3, r3, #11 +2000037a: f1b3 0220 subs.w r2, r3, #32 +2000037e: da0c bge.n 2000039a <__adddf3+0x16e> +20000380: 320c adds r2, #12 +20000382: dd08 ble.n 20000396 <__adddf3+0x16a> +20000384: f102 0c14 add.w ip, r2, #20 +20000388: f1c2 020c rsb r2, r2, #12 +2000038c: fa01 f00c lsl.w r0, r1, ip +20000390: fa21 f102 lsr.w r1, r1, r2 +20000394: e00c b.n 200003b0 <__adddf3+0x184> +20000396: f102 0214 add.w r2, r2, #20 +2000039a: bfd8 it le +2000039c: f1c2 0c20 rsble ip, r2, #32 +200003a0: fa01 f102 lsl.w r1, r1, r2 +200003a4: fa20 fc0c lsr.w ip, r0, ip +200003a8: bfdc itt le +200003aa: ea41 010c orrle.w r1, r1, ip +200003ae: 4090 lslle r0, r2 +200003b0: 1ae4 subs r4, r4, r3 +200003b2: bfa2 ittt ge +200003b4: eb01 5104 addge.w r1, r1, r4, lsl #20 +200003b8: 4329 orrge r1, r5 +200003ba: bd30 popge {r4, r5, pc} +200003bc: ea6f 0404 mvn.w r4, r4 +200003c0: 3c1f subs r4, #31 +200003c2: da1c bge.n 200003fe <__adddf3+0x1d2> +200003c4: 340c adds r4, #12 +200003c6: dc0e bgt.n 200003e6 <__adddf3+0x1ba> +200003c8: f104 0414 add.w r4, r4, #20 +200003cc: f1c4 0220 rsb r2, r4, #32 +200003d0: fa20 f004 lsr.w r0, r0, r4 +200003d4: fa01 f302 lsl.w r3, r1, r2 +200003d8: ea40 0003 orr.w r0, r0, r3 +200003dc: fa21 f304 lsr.w r3, r1, r4 +200003e0: ea45 0103 orr.w r1, r5, r3 +200003e4: bd30 pop {r4, r5, pc} +200003e6: f1c4 040c rsb r4, r4, #12 +200003ea: f1c4 0220 rsb r2, r4, #32 +200003ee: fa20 f002 lsr.w r0, r0, r2 +200003f2: fa01 f304 lsl.w r3, r1, r4 +200003f6: ea40 0003 orr.w r0, r0, r3 +200003fa: 4629 mov r1, r5 +200003fc: bd30 pop {r4, r5, pc} +200003fe: fa21 f004 lsr.w r0, r1, r4 +20000402: 4629 mov r1, r5 +20000404: bd30 pop {r4, r5, pc} +20000406: f094 0f00 teq r4, #0 +2000040a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 +2000040e: bf06 itte eq +20000410: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 +20000414: 3401 addeq r4, #1 +20000416: 3d01 subne r5, #1 +20000418: e74e b.n 200002b8 <__adddf3+0x8c> +2000041a: ea7f 5c64 mvns.w ip, r4, asr #21 +2000041e: bf18 it ne +20000420: ea7f 5c65 mvnsne.w ip, r5, asr #21 +20000424: d029 beq.n 2000047a <__adddf3+0x24e> +20000426: ea94 0f05 teq r4, r5 +2000042a: bf08 it eq +2000042c: ea90 0f02 teqeq r0, r2 +20000430: d005 beq.n 2000043e <__adddf3+0x212> +20000432: ea54 0c00 orrs.w ip, r4, r0 +20000436: bf04 itt eq +20000438: 4619 moveq r1, r3 +2000043a: 4610 moveq r0, r2 +2000043c: bd30 pop {r4, r5, pc} +2000043e: ea91 0f03 teq r1, r3 +20000442: bf1e ittt ne +20000444: 2100 movne r1, #0 +20000446: 2000 movne r0, #0 +20000448: bd30 popne {r4, r5, pc} +2000044a: ea5f 5c54 movs.w ip, r4, lsr #21 +2000044e: d105 bne.n 2000045c <__adddf3+0x230> +20000450: 0040 lsls r0, r0, #1 +20000452: 4149 adcs r1, r1 +20000454: bf28 it cs +20000456: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 +2000045a: bd30 pop {r4, r5, pc} +2000045c: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 +20000460: bf3c itt cc +20000462: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 +20000466: bd30 popcc {r4, r5, pc} +20000468: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 +2000046c: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 +20000470: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 +20000474: f04f 0000 mov.w r0, #0 +20000478: bd30 pop {r4, r5, pc} +2000047a: ea7f 5c64 mvns.w ip, r4, asr #21 +2000047e: bf1a itte ne +20000480: 4619 movne r1, r3 +20000482: 4610 movne r0, r2 +20000484: ea7f 5c65 mvnseq.w ip, r5, asr #21 +20000488: bf1c itt ne +2000048a: 460b movne r3, r1 +2000048c: 4602 movne r2, r0 +2000048e: ea50 3401 orrs.w r4, r0, r1, lsl #12 +20000492: bf06 itte eq +20000494: ea52 3503 orrseq.w r5, r2, r3, lsl #12 +20000498: ea91 0f03 teqeq r1, r3 +2000049c: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 +200004a0: bd30 pop {r4, r5, pc} +200004a2: bf00 nop + +200004a4 <__aeabi_ui2d>: +200004a4: f090 0f00 teq r0, #0 +200004a8: bf04 itt eq +200004aa: 2100 moveq r1, #0 +200004ac: 4770 bxeq lr +200004ae: b530 push {r4, r5, lr} +200004b0: f44f 6480 mov.w r4, #1024 @ 0x400 +200004b4: f104 0432 add.w r4, r4, #50 @ 0x32 +200004b8: f04f 0500 mov.w r5, #0 +200004bc: f04f 0100 mov.w r1, #0 +200004c0: e750 b.n 20000364 <__adddf3+0x138> +200004c2: bf00 nop + +200004c4 <__aeabi_i2d>: +200004c4: f090 0f00 teq r0, #0 +200004c8: bf04 itt eq +200004ca: 2100 moveq r1, #0 +200004cc: 4770 bxeq lr +200004ce: b530 push {r4, r5, lr} +200004d0: f44f 6480 mov.w r4, #1024 @ 0x400 +200004d4: f104 0432 add.w r4, r4, #50 @ 0x32 +200004d8: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 +200004dc: bf48 it mi +200004de: 4240 negmi r0, r0 +200004e0: f04f 0100 mov.w r1, #0 +200004e4: e73e b.n 20000364 <__adddf3+0x138> +200004e6: bf00 nop + +200004e8 <__aeabi_f2d>: +200004e8: 0042 lsls r2, r0, #1 +200004ea: ea4f 01e2 mov.w r1, r2, asr #3 +200004ee: ea4f 0131 mov.w r1, r1, rrx +200004f2: ea4f 7002 mov.w r0, r2, lsl #28 +200004f6: bf1f itttt ne +200004f8: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 +200004fc: f093 4f7f teqne r3, #4278190080 @ 0xff000000 +20000500: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 +20000504: 4770 bxne lr +20000506: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 +2000050a: bf08 it eq +2000050c: 4770 bxeq lr +2000050e: f093 4f7f teq r3, #4278190080 @ 0xff000000 +20000512: bf04 itt eq +20000514: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 +20000518: 4770 bxeq lr +2000051a: b530 push {r4, r5, lr} +2000051c: f44f 7460 mov.w r4, #896 @ 0x380 +20000520: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 +20000524: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 +20000528: e71c b.n 20000364 <__adddf3+0x138> +2000052a: bf00 nop + +2000052c <__aeabi_ul2d>: +2000052c: ea50 0201 orrs.w r2, r0, r1 +20000530: bf08 it eq +20000532: 4770 bxeq lr +20000534: b530 push {r4, r5, lr} +20000536: f04f 0500 mov.w r5, #0 +2000053a: e00a b.n 20000552 <__aeabi_l2d+0x16> + +2000053c <__aeabi_l2d>: +2000053c: ea50 0201 orrs.w r2, r0, r1 +20000540: bf08 it eq +20000542: 4770 bxeq lr +20000544: b530 push {r4, r5, lr} +20000546: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 +2000054a: d502 bpl.n 20000552 <__aeabi_l2d+0x16> +2000054c: 4240 negs r0, r0 +2000054e: eb61 0141 sbc.w r1, r1, r1, lsl #1 +20000552: f44f 6480 mov.w r4, #1024 @ 0x400 +20000556: f104 0432 add.w r4, r4, #50 @ 0x32 +2000055a: ea5f 5c91 movs.w ip, r1, lsr #22 +2000055e: f43f aed8 beq.w 20000312 <__adddf3+0xe6> +20000562: f04f 0203 mov.w r2, #3 +20000566: ea5f 0cdc movs.w ip, ip, lsr #3 +2000056a: bf18 it ne +2000056c: 3203 addne r2, #3 +2000056e: ea5f 0cdc movs.w ip, ip, lsr #3 +20000572: bf18 it ne +20000574: 3203 addne r2, #3 +20000576: eb02 02dc add.w r2, r2, ip, lsr #3 +2000057a: f1c2 0320 rsb r3, r2, #32 +2000057e: fa00 fc03 lsl.w ip, r0, r3 +20000582: fa20 f002 lsr.w r0, r0, r2 +20000586: fa01 fe03 lsl.w lr, r1, r3 +2000058a: ea40 000e orr.w r0, r0, lr +2000058e: fa21 f102 lsr.w r1, r1, r2 +20000592: 4414 add r4, r2 +20000594: e6bd b.n 20000312 <__adddf3+0xe6> +20000596: bf00 nop + +20000598 <__aeabi_uldivmod>: +20000598: b953 cbnz r3, 200005b0 <__aeabi_uldivmod+0x18> +2000059a: b94a cbnz r2, 200005b0 <__aeabi_uldivmod+0x18> +2000059c: 2900 cmp r1, #0 +2000059e: bf08 it eq +200005a0: 2800 cmpeq r0, #0 +200005a2: bf1c itt ne +200005a4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +200005a8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +200005ac: f000 b9b2 b.w 20000914 <__aeabi_idiv0> +200005b0: f1ad 0c08 sub.w ip, sp, #8 +200005b4: e96d ce04 strd ip, lr, [sp, #-16]! +200005b8: f000 f806 bl 200005c8 <__udivmoddi4> +200005bc: f8dd e004 ldr.w lr, [sp, #4] +200005c0: e9dd 2302 ldrd r2, r3, [sp, #8] +200005c4: b004 add sp, #16 +200005c6: 4770 bx lr + +200005c8 <__udivmoddi4>: +200005c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +200005cc: 468c mov ip, r1 +200005ce: 9e09 ldr r6, [sp, #36] @ 0x24 +200005d0: 4604 mov r4, r0 +200005d2: 460f mov r7, r1 +200005d4: 2b00 cmp r3, #0 +200005d6: d148 bne.n 2000066a <__udivmoddi4+0xa2> +200005d8: 428a cmp r2, r1 +200005da: 4615 mov r5, r2 +200005dc: d95e bls.n 2000069c <__udivmoddi4+0xd4> +200005de: fab2 f382 clz r3, r2 +200005e2: b13b cbz r3, 200005f4 <__udivmoddi4+0x2c> +200005e4: f1c3 0220 rsb r2, r3, #32 +200005e8: 409f lsls r7, r3 +200005ea: 409d lsls r5, r3 +200005ec: 409c lsls r4, r3 +200005ee: fa20 f202 lsr.w r2, r0, r2 +200005f2: 4317 orrs r7, r2 +200005f4: ea4f 4e15 mov.w lr, r5, lsr #16 +200005f8: fa1f fc85 uxth.w ip, r5 +200005fc: 0c22 lsrs r2, r4, #16 +200005fe: fbb7 f1fe udiv r1, r7, lr +20000602: fb0e 7711 mls r7, lr, r1, r7 +20000606: fb01 f00c mul.w r0, r1, ip +2000060a: ea42 4207 orr.w r2, r2, r7, lsl #16 +2000060e: 4290 cmp r0, r2 +20000610: d907 bls.n 20000622 <__udivmoddi4+0x5a> +20000612: 18aa adds r2, r5, r2 +20000614: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +20000618: d202 bcs.n 20000620 <__udivmoddi4+0x58> +2000061a: 4290 cmp r0, r2 +2000061c: f200 8158 bhi.w 200008d0 <__udivmoddi4+0x308> +20000620: 4639 mov r1, r7 +20000622: 1a12 subs r2, r2, r0 +20000624: b2a4 uxth r4, r4 +20000626: fbb2 f0fe udiv r0, r2, lr +2000062a: fb0e 2210 mls r2, lr, r0, r2 +2000062e: fb00 fc0c mul.w ip, r0, ip +20000632: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000636: 45a4 cmp ip, r4 +20000638: d90b bls.n 20000652 <__udivmoddi4+0x8a> +2000063a: 192c adds r4, r5, r4 +2000063c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000640: bf2c ite cs +20000642: 2701 movcs r7, #1 +20000644: 2700 movcc r7, #0 +20000646: 45a4 cmp ip, r4 +20000648: d902 bls.n 20000650 <__udivmoddi4+0x88> +2000064a: 2f00 cmp r7, #0 +2000064c: f000 8143 beq.w 200008d6 <__udivmoddi4+0x30e> +20000650: 4610 mov r0, r2 +20000652: ea40 4001 orr.w r0, r0, r1, lsl #16 +20000656: eba4 040c sub.w r4, r4, ip +2000065a: 2100 movs r1, #0 +2000065c: b11e cbz r6, 20000666 <__udivmoddi4+0x9e> +2000065e: 40dc lsrs r4, r3 +20000660: 2300 movs r3, #0 +20000662: e9c6 4300 strd r4, r3, [r6] +20000666: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +2000066a: 428b cmp r3, r1 +2000066c: d906 bls.n 2000067c <__udivmoddi4+0xb4> +2000066e: b10e cbz r6, 20000674 <__udivmoddi4+0xac> +20000670: e9c6 0100 strd r0, r1, [r6] +20000674: 2100 movs r1, #0 +20000676: 4608 mov r0, r1 +20000678: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +2000067c: fab3 f183 clz r1, r3 +20000680: 2900 cmp r1, #0 +20000682: d151 bne.n 20000728 <__udivmoddi4+0x160> +20000684: 4563 cmp r3, ip +20000686: f0c0 8116 bcc.w 200008b6 <__udivmoddi4+0x2ee> +2000068a: 4282 cmp r2, r0 +2000068c: f240 8113 bls.w 200008b6 <__udivmoddi4+0x2ee> +20000690: 4608 mov r0, r1 +20000692: 2e00 cmp r6, #0 +20000694: d0e7 beq.n 20000666 <__udivmoddi4+0x9e> +20000696: e9c6 4700 strd r4, r7, [r6] +2000069a: e7e4 b.n 20000666 <__udivmoddi4+0x9e> +2000069c: 2a00 cmp r2, #0 +2000069e: f000 80af beq.w 20000800 <__udivmoddi4+0x238> +200006a2: fab2 f382 clz r3, r2 +200006a6: 2b00 cmp r3, #0 +200006a8: f040 80c2 bne.w 20000830 <__udivmoddi4+0x268> +200006ac: 1a8a subs r2, r1, r2 +200006ae: ea4f 4e15 mov.w lr, r5, lsr #16 +200006b2: b2af uxth r7, r5 +200006b4: 2101 movs r1, #1 +200006b6: 0c20 lsrs r0, r4, #16 +200006b8: fbb2 fcfe udiv ip, r2, lr +200006bc: fb0e 221c mls r2, lr, ip, r2 +200006c0: ea40 4202 orr.w r2, r0, r2, lsl #16 +200006c4: fb07 f00c mul.w r0, r7, ip +200006c8: 4290 cmp r0, r2 +200006ca: d90e bls.n 200006ea <__udivmoddi4+0x122> +200006cc: 18aa adds r2, r5, r2 +200006ce: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +200006d2: bf2c ite cs +200006d4: f04f 0901 movcs.w r9, #1 +200006d8: f04f 0900 movcc.w r9, #0 +200006dc: 4290 cmp r0, r2 +200006de: d903 bls.n 200006e8 <__udivmoddi4+0x120> +200006e0: f1b9 0f00 cmp.w r9, #0 +200006e4: f000 80f0 beq.w 200008c8 <__udivmoddi4+0x300> +200006e8: 46c4 mov ip, r8 +200006ea: 1a12 subs r2, r2, r0 +200006ec: b2a4 uxth r4, r4 +200006ee: fbb2 f0fe udiv r0, r2, lr +200006f2: fb0e 2210 mls r2, lr, r0, r2 +200006f6: fb00 f707 mul.w r7, r0, r7 +200006fa: ea44 4402 orr.w r4, r4, r2, lsl #16 +200006fe: 42a7 cmp r7, r4 +20000700: d90e bls.n 20000720 <__udivmoddi4+0x158> +20000702: 192c adds r4, r5, r4 +20000704: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000708: bf2c ite cs +2000070a: f04f 0e01 movcs.w lr, #1 +2000070e: f04f 0e00 movcc.w lr, #0 +20000712: 42a7 cmp r7, r4 +20000714: d903 bls.n 2000071e <__udivmoddi4+0x156> +20000716: f1be 0f00 cmp.w lr, #0 +2000071a: f000 80d2 beq.w 200008c2 <__udivmoddi4+0x2fa> +2000071e: 4610 mov r0, r2 +20000720: 1be4 subs r4, r4, r7 +20000722: ea40 400c orr.w r0, r0, ip, lsl #16 +20000726: e799 b.n 2000065c <__udivmoddi4+0x94> +20000728: f1c1 0520 rsb r5, r1, #32 +2000072c: 408b lsls r3, r1 +2000072e: fa0c f401 lsl.w r4, ip, r1 +20000732: fa00 f901 lsl.w r9, r0, r1 +20000736: fa22 f705 lsr.w r7, r2, r5 +2000073a: fa2c fc05 lsr.w ip, ip, r5 +2000073e: 408a lsls r2, r1 +20000740: 431f orrs r7, r3 +20000742: fa20 f305 lsr.w r3, r0, r5 +20000746: 0c38 lsrs r0, r7, #16 +20000748: 4323 orrs r3, r4 +2000074a: fa1f fe87 uxth.w lr, r7 +2000074e: 0c1c lsrs r4, r3, #16 +20000750: fbbc f8f0 udiv r8, ip, r0 +20000754: fb00 cc18 mls ip, r0, r8, ip +20000758: ea44 440c orr.w r4, r4, ip, lsl #16 +2000075c: fb08 fc0e mul.w ip, r8, lr +20000760: 45a4 cmp ip, r4 +20000762: d90e bls.n 20000782 <__udivmoddi4+0x1ba> +20000764: 193c adds r4, r7, r4 +20000766: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +2000076a: bf2c ite cs +2000076c: f04f 0b01 movcs.w fp, #1 +20000770: f04f 0b00 movcc.w fp, #0 +20000774: 45a4 cmp ip, r4 +20000776: d903 bls.n 20000780 <__udivmoddi4+0x1b8> +20000778: f1bb 0f00 cmp.w fp, #0 +2000077c: f000 80b8 beq.w 200008f0 <__udivmoddi4+0x328> +20000780: 46d0 mov r8, sl +20000782: eba4 040c sub.w r4, r4, ip +20000786: fa1f fc83 uxth.w ip, r3 +2000078a: fbb4 f3f0 udiv r3, r4, r0 +2000078e: fb00 4413 mls r4, r0, r3, r4 +20000792: fb03 fe0e mul.w lr, r3, lr +20000796: ea4c 4404 orr.w r4, ip, r4, lsl #16 +2000079a: 45a6 cmp lr, r4 +2000079c: d90e bls.n 200007bc <__udivmoddi4+0x1f4> +2000079e: 193c adds r4, r7, r4 +200007a0: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +200007a4: bf2c ite cs +200007a6: f04f 0c01 movcs.w ip, #1 +200007aa: f04f 0c00 movcc.w ip, #0 +200007ae: 45a6 cmp lr, r4 +200007b0: d903 bls.n 200007ba <__udivmoddi4+0x1f2> +200007b2: f1bc 0f00 cmp.w ip, #0 +200007b6: f000 809f beq.w 200008f8 <__udivmoddi4+0x330> +200007ba: 4603 mov r3, r0 +200007bc: ea43 4008 orr.w r0, r3, r8, lsl #16 +200007c0: eba4 040e sub.w r4, r4, lr +200007c4: fba0 ec02 umull lr, ip, r0, r2 +200007c8: 4564 cmp r4, ip +200007ca: 4673 mov r3, lr +200007cc: 46e0 mov r8, ip +200007ce: d302 bcc.n 200007d6 <__udivmoddi4+0x20e> +200007d0: d107 bne.n 200007e2 <__udivmoddi4+0x21a> +200007d2: 45f1 cmp r9, lr +200007d4: d205 bcs.n 200007e2 <__udivmoddi4+0x21a> +200007d6: ebbe 0302 subs.w r3, lr, r2 +200007da: eb6c 0c07 sbc.w ip, ip, r7 +200007de: 3801 subs r0, #1 +200007e0: 46e0 mov r8, ip +200007e2: b15e cbz r6, 200007fc <__udivmoddi4+0x234> +200007e4: ebb9 0203 subs.w r2, r9, r3 +200007e8: eb64 0408 sbc.w r4, r4, r8 +200007ec: fa04 f505 lsl.w r5, r4, r5 +200007f0: fa22 f301 lsr.w r3, r2, r1 +200007f4: 40cc lsrs r4, r1 +200007f6: 431d orrs r5, r3 +200007f8: e9c6 5400 strd r5, r4, [r6] +200007fc: 2100 movs r1, #0 +200007fe: e732 b.n 20000666 <__udivmoddi4+0x9e> +20000800: 0842 lsrs r2, r0, #1 +20000802: 462f mov r7, r5 +20000804: 084b lsrs r3, r1, #1 +20000806: 46ac mov ip, r5 +20000808: ea42 72c1 orr.w r2, r2, r1, lsl #31 +2000080c: 46ae mov lr, r5 +2000080e: 07c4 lsls r4, r0, #31 +20000810: 0c11 lsrs r1, r2, #16 +20000812: b292 uxth r2, r2 +20000814: ea41 4103 orr.w r1, r1, r3, lsl #16 +20000818: ea42 4201 orr.w r2, r2, r1, lsl #16 +2000081c: fbb1 f1f5 udiv r1, r1, r5 +20000820: fbb3 f0f5 udiv r0, r3, r5 +20000824: 231f movs r3, #31 +20000826: eba2 020c sub.w r2, r2, ip +2000082a: ea41 4100 orr.w r1, r1, r0, lsl #16 +2000082e: e742 b.n 200006b6 <__udivmoddi4+0xee> +20000830: 409d lsls r5, r3 +20000832: f1c3 0220 rsb r2, r3, #32 +20000836: 4099 lsls r1, r3 +20000838: 409c lsls r4, r3 +2000083a: fa2c fc02 lsr.w ip, ip, r2 +2000083e: ea4f 4e15 mov.w lr, r5, lsr #16 +20000842: fa20 f202 lsr.w r2, r0, r2 +20000846: b2af uxth r7, r5 +20000848: fbbc f8fe udiv r8, ip, lr +2000084c: 430a orrs r2, r1 +2000084e: fb0e cc18 mls ip, lr, r8, ip +20000852: 0c11 lsrs r1, r2, #16 +20000854: ea41 410c orr.w r1, r1, ip, lsl #16 +20000858: fb08 fc07 mul.w ip, r8, r7 +2000085c: 458c cmp ip, r1 +2000085e: d950 bls.n 20000902 <__udivmoddi4+0x33a> +20000860: 1869 adds r1, r5, r1 +20000862: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +20000866: bf2c ite cs +20000868: f04f 0901 movcs.w r9, #1 +2000086c: f04f 0900 movcc.w r9, #0 +20000870: 458c cmp ip, r1 +20000872: d902 bls.n 2000087a <__udivmoddi4+0x2b2> +20000874: f1b9 0f00 cmp.w r9, #0 +20000878: d030 beq.n 200008dc <__udivmoddi4+0x314> +2000087a: eba1 010c sub.w r1, r1, ip +2000087e: fbb1 f8fe udiv r8, r1, lr +20000882: fb08 fc07 mul.w ip, r8, r7 +20000886: fb0e 1118 mls r1, lr, r8, r1 +2000088a: b292 uxth r2, r2 +2000088c: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000890: 4562 cmp r2, ip +20000892: d234 bcs.n 200008fe <__udivmoddi4+0x336> +20000894: 18aa adds r2, r5, r2 +20000896: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +2000089a: bf2c ite cs +2000089c: f04f 0901 movcs.w r9, #1 +200008a0: f04f 0900 movcc.w r9, #0 +200008a4: 4562 cmp r2, ip +200008a6: d2be bcs.n 20000826 <__udivmoddi4+0x25e> +200008a8: f1b9 0f00 cmp.w r9, #0 +200008ac: d1bb bne.n 20000826 <__udivmoddi4+0x25e> +200008ae: f1a8 0102 sub.w r1, r8, #2 +200008b2: 442a add r2, r5 +200008b4: e7b7 b.n 20000826 <__udivmoddi4+0x25e> +200008b6: 1a84 subs r4, r0, r2 +200008b8: eb6c 0203 sbc.w r2, ip, r3 +200008bc: 2001 movs r0, #1 +200008be: 4617 mov r7, r2 +200008c0: e6e7 b.n 20000692 <__udivmoddi4+0xca> +200008c2: 442c add r4, r5 +200008c4: 3802 subs r0, #2 +200008c6: e72b b.n 20000720 <__udivmoddi4+0x158> +200008c8: f1ac 0c02 sub.w ip, ip, #2 +200008cc: 442a add r2, r5 +200008ce: e70c b.n 200006ea <__udivmoddi4+0x122> +200008d0: 3902 subs r1, #2 +200008d2: 442a add r2, r5 +200008d4: e6a5 b.n 20000622 <__udivmoddi4+0x5a> +200008d6: 442c add r4, r5 +200008d8: 3802 subs r0, #2 +200008da: e6ba b.n 20000652 <__udivmoddi4+0x8a> +200008dc: eba5 0c0c sub.w ip, r5, ip +200008e0: f1a8 0002 sub.w r0, r8, #2 +200008e4: 4461 add r1, ip +200008e6: fbb1 f8fe udiv r8, r1, lr +200008ea: fb08 fc07 mul.w ip, r8, r7 +200008ee: e7ca b.n 20000886 <__udivmoddi4+0x2be> +200008f0: f1a8 0802 sub.w r8, r8, #2 +200008f4: 443c add r4, r7 +200008f6: e744 b.n 20000782 <__udivmoddi4+0x1ba> +200008f8: 3b02 subs r3, #2 +200008fa: 443c add r4, r7 +200008fc: e75e b.n 200007bc <__udivmoddi4+0x1f4> +200008fe: 4641 mov r1, r8 +20000900: e791 b.n 20000826 <__udivmoddi4+0x25e> +20000902: eba1 010c sub.w r1, r1, ip +20000906: 4640 mov r0, r8 +20000908: fbb1 f8fe udiv r8, r1, lr +2000090c: fb08 fc07 mul.w ip, r8, r7 +20000910: e7b9 b.n 20000886 <__udivmoddi4+0x2be> +20000912: bf00 nop + +20000914 <__aeabi_idiv0>: +20000914: 4770 bx lr +20000916: bf00 nop + +20000918 <__best_effort_wfe_or_timeout_veneer>: +20000918: f85f f000 ldr.w pc, [pc] @ 2000091c <__best_effort_wfe_or_timeout_veneer+0x4> +2000091c: 100010b5 .word 0x100010b5 + +20000920 : +20000920: 00000010 .... + +20000924 : +20000924: 00000000 .word 0x00000000 +20000928: 00010000 .word 0x00010000 + ... +20000934: 00020000 .word 0x00020000 + ... +20000940: 00030000 .word 0x00030000 + ... +2000094c: 00ff0000 .word 0x00ff0000 +20000950: 00000000 .word 0x00000000 + +20000954 : +20000954: b501 push {r0, lr} +20000956: 6848 ldr r0, [r1, #4] +20000958: 3101 adds r1, #1 +2000095a: 468e mov lr, r1 +2000095c: 4700 bx r0 + +2000095e : +2000095e: 4670 mov r0, lr +20000960: 3809 subs r0, #9 +20000962: 4901 ldr r1, [pc, #4] @ (20000968 ) +20000964: 4788 blx r1 +20000966: bd01 pop {r0, pc} +20000968: 10000875 .word 0x10000875 + +2000096c : + ... +20000980: 200009a8 ... + +20000984 : +20000984: 10003541 10003649 10003591 10003659 A5..I6...5..Y6.. +20000994: 00000000 00000100 ........ + +2000099c : + ... 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b/WEEK09/0x001a_operators/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK09/0x001a_operators/dht11.c b/WEEK09/0x001a_operators/dht11.c new file mode 100644 index 0000000..9a52ba8 --- /dev/null +++ b/WEEK09/0x001a_operators/dht11.c @@ -0,0 +1,79 @@ +/** + * @file dht11.c + * @brief Implementation of DHT11 temperature and humidity sensor driver + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "dht11.h" +#include "hardware/gpio.h" +#include "pico/time.h" + +static uint dht_pin; + +void dht11_init(uint8_t pin) { + dht_pin = pin; + gpio_init(pin); + gpio_pull_up(pin); +} + +bool dht11_read(float *humidity, float *temperature) { + uint8_t data[5] = {0}; + + // Start signal + gpio_set_dir(dht_pin, GPIO_OUT); + gpio_put(dht_pin, 0); + sleep_ms(18); + gpio_put(dht_pin, 1); + sleep_us(40); + gpio_set_dir(dht_pin, GPIO_IN); + + // Wait for response + uint32_t timeout = 10000; + while (gpio_get(dht_pin) == 1) if (--timeout == 0) return false; + timeout = 10000; + while (gpio_get(dht_pin) == 0) if (--timeout == 0) return false; + timeout = 10000; + while (gpio_get(dht_pin) == 1) if (--timeout == 0) return false; + + // Read 40 bits + for (int i = 0; i < 40; i++) { + timeout = 10000; + while (gpio_get(dht_pin) == 0) if (--timeout == 0) return false; + uint32_t start = time_us_32(); + timeout = 10000; + while (gpio_get(dht_pin) == 1) if (--timeout == 0) return false; + uint32_t duration = time_us_32() - start; + data[i / 8] <<= 1; + if (duration > 40) data[i / 8] |= 1; + } + + // Check checksum + if (data[4] != ((data[0] + data[1] + data[2] + data[3]) & 0xFF)) return false; + + *humidity = data[0] + data[1] * 0.1f; + *temperature = data[2] + data[3] * 0.1f; + return true; +} diff --git a/WEEK09/0x001a_operators/dht11.h b/WEEK09/0x001a_operators/dht11.h new file mode 100644 index 0000000..30e298c --- /dev/null +++ b/WEEK09/0x001a_operators/dht11.h @@ -0,0 +1,57 @@ +/** + * @file dht11.h + * @brief Header for DHT11 temperature and humidity sensor driver + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef DHT11_H +#define DHT11_H + +#include +#include + +/** + * @brief Initialize the DHT11 driver + * + * Configures the GPIO pin for the DHT11 sensor. This must be called before + * using dht11_read(). + * + * @param pin GPIO pin number connected to DHT11 signal + */ +void dht11_init(uint8_t pin); + +/** + * @brief Read temperature and humidity from DHT11 sensor + * + * Performs the DHT11 communication protocol to read sensor data. + * + * @param humidity Pointer to store humidity value (0-100%) + * @param temperature Pointer to store temperature value in Celsius + * @return true if read successful, false on error or timeout + */ +bool dht11_read(float *humidity, float *temperature); + +#endif // DHT11_H diff --git a/WEEK09/0x001a_operators/hack-temp.py b/WEEK09/0x001a_operators/hack-temp.py new file mode 100644 index 0000000..8973073 --- /dev/null +++ b/WEEK09/0x001a_operators/hack-temp.py @@ -0,0 +1,219 @@ +#!/usr/bin/env python3 + +""" +FILE: hack-temp.py + +DESCRIPTION: +Incremental firmware patcher with minimal, conservative steps to bias readings. + +BRIEF: +Provides three modes: +- pool_only: change only the literal pool constant (scaling effect; least invasive) +- temp_only_vadd: convert temperature path to vadd.f32 and set a small negative pool +- both_vadd: convert both paths to vadd.f32 and set a small negative pool + +Intended to let you test changes incrementally, keeping humidity stable while +you evaluate temperature bias first. + +AUTHOR: Kevin Thomas +CREATION DATE: November 1, 2025 +UPDATE DATE: November 1, 2025 +""" + +import sys +import os +import struct + +BIN_PATH = "build/0x001a_operators.bin" + +# Offsets +OFF_410 = 0x410 +OFF_414 = 0x414 +OFF_POOL = 0x42C + +# Original encodings (for visibility only) +ORIG_410 = bytes.fromhex("a6ee257a") # vfma.f32 s14, s12, s11 +ORIG_414 = bytes.fromhex("e6eea57a") # vfma.f32 s15, s13, s11 +ORIG_POOL = bytes.fromhex("cccccc3d") # 0.1f + +# Encodings for vadd.f32 s14, s14, s11 and vadd.f32 s15, s15, s11 +VADD_S14_S11 = struct.pack(" 1 else "pool_only").strip().lower() + if mode == "pool_only": + patch_pool_only(new_pool_float=-1.0) + elif mode == "temp_only_vadd": + patch_temp_only_vadd(new_pool_float=-2.0) + elif mode == "both_vadd": + patch_both_vadd(new_pool_float=-2.0) + else: + print(f"Unknown mode: {mode}") + print("Use: pool_only | temp_only_vadd | both_vadd") + sys.exit(2) + + +if __name__ == "__main__": + main() + print("Patch complete. Convert to UF2 and flash. Test each mode incrementally.") diff --git a/WEEK09/0x001a_operators/pico_sdk_import.cmake b/WEEK09/0x001a_operators/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK09/0x001a_operators/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK09/0x001aa_cb/0x001aa_cb.bin b/WEEK09/0x001aa_cb/0x001aa_cb.bin new file mode 100755 index 0000000..88cef35 Binary files /dev/null and b/WEEK09/0x001aa_cb/0x001aa_cb.bin differ diff --git a/WEEK09/0x001aa_cb/0x001aa_cb.uf2 b/WEEK09/0x001aa_cb/0x001aa_cb.uf2 new file mode 100644 index 0000000..aefe135 Binary files /dev/null and b/WEEK09/0x001aa_cb/0x001aa_cb.uf2 differ diff --git a/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.md b/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.md new file mode 100644 index 0000000..1711fc7 --- /dev/null +++ b/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.md @@ -0,0 +1,154 @@ +# Operation Iron Net: Classified Intelligence Briefing + +``` ++-----------------------------------------------------------------+ +| TOP SECRET // NOFORN | ++-----------------------------------------------------------------+ +| | +|OPERATION IRON NET | +| | +|CLASSIFIED BRIEFING: LIVE CHALLENGE 0x03 | +| | +|NATIONAL SECURITY AGENCY / GMU RHET | ++-----------------------------------------------------------------+ +``` + +## 1. The Advice + +INT. NSA EXPLOITATION CELL. 04:10. + +A grey field junction box sits on the bench, its lid peeled back. Inside, +secured in potting compound, is a covert environmental sensor node recovered +from a contested waterway. + +On the top of the enclosure, a status diode glows a steady red. Beside it, a +REYAX RYLR998 LoRa transceiver is wired to `UART1` on `GP8` and `GP9`. A +three-wire ribbon terminates in a DHT11 temperature and humidity canister. A +thin jumper loops from `GP15` up to the `3V3` rail. + +The Director sets down a field report and looks at the red diode. + +**DIRECTOR:** What is it? + +**ANALYST:** A remote environmental trigger. The adversary seeds these along a +river corridor. The DHT11 samples the air. When the conditions hit a preset +window, the node arms a payload channel and broadcasts a strike authorization +over LoRa. + +**DIRECTOR:** Is it live? + +**ANALYST:** Armed and listening. The payload relay on `GP18` is wired. One +authenticated strike frame and the cell downstream fires. + +**DIRECTOR:** Run it through Buddy. + +**ANALYST:** Already did. Four minutes with the stripped flash image. + +She turns her monitor toward him. + +``` ++-----------------------------------------------------------------+ +| BUDDY // CLASSIFIED EXPLOITATION ASSIST // CONF: 0.98 | ++-----------------------------------------------------------------+ +| ACTION : Replay the environmental checksum window. | +| MECHANISM : DHT11 humidity byte XOR 0xAF, masked by 0x3C. | +| PREDICTION : Force (humidity ^ 0xAF) & 0x3C == 0x18, node arm. | +| CONFIDENCE : 0.98 | ++-----------------------------------------------------------------+ +``` + +**DIRECTOR:** 0.98. Forge the reading, arm the node, learn its payload. + +**ANALYST:** Buddy found the bitwise window. Buddy did not find the door behind +it. There is an authorization token, and there is a trap. + +**DIRECTOR:** Buddy says 0.98. + +**ANALYST:** Buddy disassembled `evaluate_environment`. Buddy never followed the +SRAM the state machine lives in. Buddy never read the fault counter. + +## 2. What Buddy Is + +Buddy is not a person. It is a model. It has parsed more disassembled machine +code than any engineer on earth, and it speaks with total, unhesitating certainty. + +That certainty is lethal when the target is a live payload channel. + +Buddy scanned the flash image and found a tidy bitwise test. It concluded that +satisfying the arithmetic is the whole game. It published the mask and the window +and declared the node owned. + +What Buddy failed to model is that adversary tripwires are engineered for exactly +this attack. A real node does not trade a payload on a single sensor byte. It +runs a state machine, validates an encrypted token carried over the air, and +counts its own faults so that a spoofer who fumbles the protocol three times +burns the node instead of arming it. + +There is also a physical seal. Cut the sense loop and the node latches shut. The +correct env window is necessary. It is nowhere near sufficient. + +Buddy saw the bitwise test. Buddy did not verify the ground truth. + +## 3. The Operation + +At 01:55, a Riverine Technical Intelligence team recovered an intact node before +adversary recovery could zeroize it. The enclosure is a single-board design built +around a bare-metal RP2350 (ARM Cortex-M33). + +There are no debug symbols. There is no operating system. There is no SVD file to +label the registers. All you have is `0x001aa_cb.bin` mapped into Flash at +`0x10000000`, and the physical breadboard hardware in front of you. + +* **Pin 11 (`GP8`)**: LoRa UART1 TX (to RYLR998 RXD). +* **Pin 12 (`GP9`)**: LoRa UART1 RX (from RYLR998 TXD). +* **Pin 19 (`GP14`)**: DHT11 single-wire data line. +* **Pin 20 (`GP15`)**: Anti-tamper sense loop (jumpered to `3V3`). +* **Pin 21 (`GP16`)**: Red LED (`NODE ARMED // LISTENING`). +* **Pin 22 (`GP17`)**: Green LED (`STRIKE AUTHORIZED`). +* **Pin 24 (`GP18`)**: Payload trigger relay. +* **Pin 36 (`3V3`)**: RYLR998 VDD rail and `GP15` pull-up source. +* **Pin 38 (`GND`)**: Ground reference. + +Inside this image there is an environment gate, an over-the-air authorization +token, a fault counter, and a tamper latch. Whatever mechanism actually authorizes +a strike is buried in the stripped ARM Thumb-2 machine code. + +## 4. The Mandate + +The Director crosses his arms. + +**DIRECTOR:** Prove Buddy right, or prove it wrong. + +**ANALYST:** I need thirty minutes with GDB and Ghidra. + +**DIRECTOR:** You have twenty. Trace the environment routine. Map the state +machine. Do not forge a reading over LoRa until you know with certainty what that +firmware will do with the next frame, and what it will do to you if the frame is +wrong. + +The orders are clear: + +1. **Recover the Environment Gate**: Locate the bitwise validation routine and + work out which DHT11 humidity value satisfies it. +2. **Recover the Authorization Token**: Find the custom cipher that is applied at + boot and decrypt the plaintext strike token it protects. +3. **Respect the Traps**: Determine what the node does after repeated faults, and + what happens if the `GP15` sense loop is broken. +4. **Neutralize the Node**: Execute a verified exploit, either by recovering the + token and satisfying the gate, by mutating the state machine in SRAM with GDB, + or by patching the binary in Flash. +5. **Verify the Hardware**: Transition the live breadboard from the Red LED on + `GP16` to the solid Green LED on `GP17` on physical silicon. + +A machine's 0.98 guess does not authorize a strike. + +## 5. The Challenge + +You have the image. You have the board. You have the tools and the time Buddy did +not need. + +Buddy has given you its answer, and it is confident. + +Is it that simple? + +Go find out. diff --git a/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.pdf b/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.pdf new file mode 100644 index 0000000..ac927e4 Binary files /dev/null and b/WEEK09/0x001aa_cb/CLASSIFIED-BRIEF-0x03.pdf differ diff --git a/WEEK09/0x001aa_cb/scripts/lora_console.py b/WEEK09/0x001aa_cb/scripts/lora_console.py new file mode 100755 index 0000000..24310f9 --- /dev/null +++ b/WEEK09/0x001aa_cb/scripts/lora_console.py @@ -0,0 +1,195 @@ +#!/usr/bin/env python3 +# MIT License +# +# Copyright (c) 2026 Kevin Thomas +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +# Author: Kevin Thomas +# Email: kevin@mytechnotalent.com +# GitHub: https://github.com/mytechnotalent +# File: lora_console.py +# Desc: Interactive REYAX RYLR998 terminal for the FT232RL ground station. +# Created: 2026 + +""" +Interactive LoRa terminal for the REYAX RYLR998 ground station. + +Sends AT commands as complete bursts terminated with a carriage return and line +feed to avoid the RYLR998 inter-character timeout error, and prints incoming +packets from the airborne node as they arrive. +""" + +import argparse +import sys +import threading +import time + +try: + import serial +except ImportError: + serial = None + + +def _reader_thread(ser: "serial.Serial") -> None: + """ + Continuously read and display incoming packets from the radio. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + while True: + try: + line = ser.readline().decode("utf-8", errors="ignore").strip() + if line: + print(f"\n[LORA RX] {line}\n> ", end="", flush=True) + except Exception: + break + + +def _parse_args() -> argparse.Namespace: + """ + Parse command line arguments for the LoRa console. + + Parameters + ---------- + None + + Returns + ------- + argparse.Namespace + Parsed arguments with the serial port and baud rate. + """ + parser = argparse.ArgumentParser(description="REYAX RYLR998 console") + parser.add_argument("--port", default="/dev/cu.usbserial-A50285BI") + parser.add_argument("--baud", type=int, default=115200) + return parser.parse_args() + + +def _open_radio(port: str, baud: int) -> "serial.Serial": + """ + Open serial connection to the REYAX transceiver. + + Parameters + ---------- + port : str + Serial device path or COM port identifier. + baud : int + Baud rate for serial communication. + + Returns + ------- + serial.Serial + Open serial interface to the radio. + """ + print(f"[*] Opening REYAX RYLR998 on {port} @ {baud}...") + try: + return serial.Serial(port, baud, timeout=0.5) + except Exception as e: + sys.exit(f"[-] Failed to open {port}: {e}") + + +def _start_radio(ser: "serial.Serial") -> None: + """ + Start listener thread and send initial AT ping. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + thread = threading.Thread(target=_reader_thread, args=(ser,), daemon=True) + thread.start() + time.sleep(0.1) + ser.write(b"AT\r\n") + + +def _print_banner() -> None: + """ + Print console connection info and operator command instructions. + + Parameters + ---------- + None + + Returns + ------- + None + """ + print("[+] Connected. Type AT commands (e.g. AT, AT+BAND?, AT+NETWORKID?).") + print("[+] Incoming airborne packets print as [LORA RX] +RCV=...") + print("[+] Press Ctrl-C or Ctrl-D to exit.\n") + + +def _console_loop(ser: "serial.Serial") -> None: + """ + Forward operator input lines to the serial transceiver. + + Parameters + ---------- + ser : serial.Serial + Open serial connection to the ground RYLR998. + + Returns + ------- + None + """ + try: + while True: + cmd = input("> ").strip() + if cmd: + ser.write(cmd.encode("utf-8") + b"\r\n") + except (KeyboardInterrupt, EOFError): + print("\n[*] Exiting LoRa console.") + ser.close() + + +def main() -> None: + """ + Open the ground station radio and forward operator input. + + Parameters + ---------- + None + + Returns + ------- + None + """ + if serial is None: + sys.exit("pyserial required: pip install pyserial") + args = _parse_args() + ser = _open_radio(args.port, args.baud) + _start_radio(ser) + _print_banner() + _console_loop(ser) + + +if __name__ == "__main__": + main() diff --git a/WEEK09/WEEK09-BN.md b/WEEK09/WEEK09-BN.md new file mode 100644 index 0000000..0161e9d --- /dev/null +++ b/WEEK09/WEEK09-BN.md @@ -0,0 +1,1546 @@ +# Week 9-BN: Binary Ninja Personal — Read, Hack, and Patch Operator Immediates and a DHT11 Float Scale (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into Binary Ninja at `0x10000000` +- Read the six C operator results as **bare instruction immediates** (`movs r1, #50`, `movs r1, #5`, …) +- Read the DHT11 single-wire driver, including the inlined `gpio_*` and `time_us_32` helpers +- **Break at the arithmetic `printf` call** on live silicon and hack the printed value live +- Optionally **hack the format string live** by pointing `r0` at a RAM replacement +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map, including the `dht11.c` symbols +- **Patch** the arithmetic immediate (`50 -> 99`) and the DHT11 scaling constant (`0.1f -> 5.0f`) +- **Rename** the printed label by patching the `"arithmetic_operator:"` string +- **Export** the patched image, convert it to UF2, and flash it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in Binary Ninja, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 9 lesson, and the Week 9 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helpers `print_operator_results`, `compute_arithmetic_ops`, `compute_operators`, and `print_dht11_reading` straight into `main`, and it inlines the whole `dht11.c` static helper chain (`send_start_signal`, `wait_for_level`, `wait_response`, `read_bit`, `read_40_bits`, `validate_checksum`) into `dht11_read`. Every operator result is folded to a bare `movs r1, #imm` immediate. If you build `Debug`, the SDK function addresses move and the helpers stay separate calls, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the output change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Serial output | Also does | The hacks | +| ------- | ------------- | --------- | --------- | +| `0x001a_operators` | six operator lines, then `Humidity: …%, Temperature: …°C` | DHT11 single-wire sensor on GPIO 4 | `50 -> 99` (arithmetic immediate), `0.1f -> 5.0f` (DHT11 scale), and `"arithmetic_operator:" -> "hacked_operator:"` | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **The surprise of this week is how small the operator code is.** The C source computes `x * y`, `x > y`, `x << 1`, and `x += 5` in a helper function, but `Release` folds every one of those into a compile-time constant and stores it as a one-byte immediate inside a `movs r1, #imm` instruction. There is no variable in memory to change — the answer is baked into the instruction stream. The DHT11 reading is different: it is a real measurement scaled by a `float` constant (`0.1f`) sitting in the literal pool, and *that* one is a data word you can patch. + +> **A note on the sensor reading.** The humidity/temperature numbers depend on the physical DHT11 attached to GPIO 4. This guide's ground truth is about the *code*, not the sensor: the scale constant, where `dht11_read` lives, and which register holds the reading. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +file "$(which telnet)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**`telnet` is special — and optional.** The GDB MI workflow does not need it; it is only used by the command-port fallback. macOS no longer ships `telnet`, and the Homebrew build is often the Intel one, so `telnet 127.0.0.1 4444` fails with `bad CPU type in executable`. Call the Apple Silicon Homebrew explicitly: + +```bash +/opt/homebrew/bin/brew install telnet +``` + +If you would rather not install anything, macOS ships an arm64 `nc`, which can connect to the same OpenOCD port: + +```bash +nc 127.0.0.1 4444 +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x001a_operators/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x001a_operators/build/0x001a_operators.elf` and `.bin` — the `.bin` is **17484** bytes (`0x444c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x001a_operators.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x001a_operators.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (all four static helpers inlined) | +| `0x100002d4` | `dht11_init` | `void dht11_init(uint8_t)` | the `dht11.c` init function | +| `0x100002f4` | `dht11_read` | `bool dht11_read(float*, float*)` | the `dht11.c` read function (all six static helpers inlined) | + +**The GPIO and timer functions `main` / `dht11.c` reach:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000440` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (UART pins) | +| `0x1000047c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | +| `0x100004a4` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init (`dht11_init` calls it) | +| `0x10000f00` | `sleep_us` | `void sleep_us(uint64_t)` | SDK microsecond delay (`dht11_read` calls it) | +| `0x10000fd8` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay (`main`, `dht11_read`) | +| `0x100011bc` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (`printf` path) | +| `0x100011d0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001250` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10001424` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000313c` | `exit` | `void exit(int)` | C runtime exit | +| `0x10003144` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003170` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003280` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000336c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003394` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003424` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (`DHT11 read failed`) | +| `0x10003460` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x10003524` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (all seven calls) | +| `0x100036e0` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003820` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` path reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10001a44` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x10001ae0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x10001cb4` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x100026fc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x100030e0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | + +Things in this project that have **no symbol of their own**, because the compiler inlined them: + +- `print_operator_results`, `compute_arithmetic_ops`, `compute_operators`, `print_dht11_reading` — the four `static` helpers in `0x001a_operators.c` are inlined into `main`, so their bodies appear directly inside `main`. +- `send_start_signal`, `wait_for_level`, `wait_response`, `read_bit`, `read_40_bits`, `validate_checksum` — the six `static` helpers in `dht11.c` are inlined into `dht11_read`, along with `gpio_set_dir`, `gpio_put`, `gpio_get`, and `time_us_32` from the SDK headers. You see `mcrr` (SIO writes), `ldr [.., #4]` (SIO reads), and `ldr [r0, #40]` (TIMER0 read) directly inside `dht11_read`. +- `gpio_pull_up` — `static inline` in the SDK, so `dht11_init` compiles to a direct tail-call to `gpio_set_pulls`. + +> **`dht_pin` is a `b` symbol, not a function.** `arm-none-eabi-nm -n` lists `20000b7c b dht_pin`. That lowercase `b` is a **local data** symbol: the `dht11.c` file-scope `static uint dht_pin;` is parked in RAM `.bss` at `0x20000b7c`. It holds the GPIO number (`4`) after `dht11_init(4)` runs. There is no function there; do not `Y` it with a prototype. + +### Step 5: Flash and confirm the output + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x001a_operators/build/0x001a_operators.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x001a_operators\build\0x001a_operators.bin +``` + +**Or flash from the Binary Ninja console** (the console reads the repo root from the marker file, so it works with no database open): + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x001a_operators", "build", "0x001a_operators.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x001a_operators", "build", "0x001a_operators.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 17484 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +arithmetic_operator: 50 +increment_operator: 5 +relational_operator: 0 +logical_operator: 0 +bitwise_operator: 10 +assignment_operator: 10 +Humidity: 51.0%, Temperature: 23.8°C +... +``` + +Two of these values are *not* what a naive reading of the source predicts, and the build is correct: + +- **`increment_operator: 5`** — `compute_arithmetic_ops` takes `x` **by value**, so the `*incr = x++;` inside the helper increments the helper's private copy. `compute_operators`' own `x` is still `5` afterwards. +- **`bitwise_operator: 10`** and **`assignment_operator: 10`** — because `x` is still `5`, `x << 1` is `10` (not `12`), and `x += 5` is `10` (not `11`). The relational and logical operators compare `5 > 10`, so both are `0`. + +The humidity and temperature lines come from the physical DHT11 and vary with your sensor. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 6: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x001a_operators/build/0x001a_operators.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> import os +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +> load(os.path.join(root, "0x001a_operators", "build", "0x001a_operators.bin"), +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 7: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x001a_operators.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +The two files have different roles: + +| File | Role | +| ---- | ---- | +| `0x001a_operators.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x001a_operators.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. If a database gets messy, delete the `.bndb` and re-import the `.bin` from Step 6 — the firmware is never at risk. You export the patched image out of this view later, in Step 19. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 12. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +> **Optional — load the RP2350 SVD for peripheral names.** If you want Binary Ninja to label peripheral registers (TIMER0, SIO, UART0, …) instead of bare addresses, load the RP2350 SVD. It ships with Week 4, so it lives at **`WEEK04/rp2350.svd`** inside the repository — remember it is in **Week 4**, not this week. This lesson does not need it; the ELF symbol map already names every function. + +--- + +## Part 3: Dynamic — Break at the `printf` Call and Hack Live + +### Step 9: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 10. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. This is the whole reason the lab works cleanly — you never have to drive a reset from outside the GUI. +> +> Use the address you actually want to stop at: +> +> | What you want to stop at | Address | Command | +> | --- | --- | --- | +> | `main` (once per reset) | `0x10000234` | `BP_ADDR=0x10000234 ./debug-server.sh` | +> | The **loop** — the arithmetic `printf` call, hit every iteration | `0x10000272` | `BP_ADDR=0x10000272 ./debug-server.sh` | +> +> ```bash +> BP_ADDR=0x10000234 ./debug-server.sh # park at main +> BP_ADDR=0x10000272 ./debug-server.sh # park in the loop instead +> ``` +> +> ```powershell +> $env:BP_ADDR="0x10000234"; .\debug-server.ps1 # park at main +> $env:BP_ADDR="0x10000272"; .\debug-server.ps1 # park in the loop +> ``` +> +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 12) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 10: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 9 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length and handles step-over itself. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. Stops are reported as `Breakpoint` (not `SingleStep`). +> +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 9), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. +> +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. +> +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. It is not the adapter for this lab. The dropdown is a combo box, so an accidental arrow-key press can land on it — always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +> **Watch for an off-screen error dialog.** When a connection fails, Binary Ninja pops a `Binary Ninja critical alert` window that can be positioned mostly outside the main window, which makes it look like nothing happened. If the connect seems to do nothing, check your other display. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 11: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186: ldr r1, [pc, #80] @ (100001d8 ) +10000188: blx r1 +1000018a: ldr r1, [pc, #80] @ (100001dc ) +1000018c: blx r1 +1000018e: ldr r1, [pc, #80] @ (100001e0 ) +10000190: blx r1 +10000192: bkpt 0x0000 +10000194: b.n 10000192 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in every project, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234`. + +### Step 12: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +> **Why older drafts used the command port.** Binary Ninja's **GDB RSP** adapter is its own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 FPB comparators need 2 bytes, so OpenOCD rejected it with `only breakpoints of two bytes length supported`. The old workaround was to arm breakpoints by hand over telnet. **The GDB MI adapter does not have this problem** — it drives real `arm-none-eabi-gdb`, which sends the right length. So everything below is done in the GUI. The command port still exists as a fallback (see the end of this step), but you do not need it. + +#### Where you can stop + +| You want to stop at | Address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 9), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **The arithmetic `printf` call** | `0x10000272` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | +| **The second `printf` call (increment)** | `0x1000027a` | Same. | Yes. | +| **The `dht11_read` call** | `0x100002a2` | Same. | Yes. | + +#### Set the loop breakpoint in the GUI + +1. Press `G`, type the loop address (`0x10000272`), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the loop address and reports it as a **Breakpoint** — verified: `Stopped (Breakpoint) at 0x10000272`. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 10). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +#### Stepping + +With the target halted at the breakpoint, **Step Into** (`F7`) and **Step Over** (`F8`) run through real GDB and move the PC. Verified: `0x10000272 -> 0x10003524 -> 0x10003526 -> ...`. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, so **Step Over** at the `printf` call behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 13 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +> **If you ever need the command port.** It is still there — `nc 127.0.0.1 4444`, and `bp 2 hw` still arms a breakpoint, `rbp ` / `rbp all` still remove them. It is the fallback if you switch back to the **GDB RSP** adapter, whose 1-byte breakpoints the GUI cannot set. With GDB MI you do not need it for this lab. + +### Step 13: HACK IT LIVE — change the printed `arithmetic_operator` + +`main` loads the constant `0x32` (50) into `r1` and calls `printf` on every iteration. We break on that call and change it live: + +```asm +1000026e: movs r1, #50 @ 0x32 +10000270: ldr r0, [pc, #68] @ (100002b8 ) +10000272: bl 10003524 <__wrap_printf> +10000276: movs r1, #5 +10000278: ldr r0, [pc, #64] @ (100002bc ) +1000027a: bl 10003524 <__wrap_printf> +``` + +1. Press `G`, go to `0x10000272` (the `bl __wrap_printf` for `arithmetic_operator`). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the program counter at `0x10000272`, `r0 = 0x100038e8`, and `r1 = 0x32`. +4. Open the **Registers** widget (bug icon -> **Registers**). +5. Find `r1`. Its value is `0x32` (50), loaded by the `movs r1, #50` at `0x1000026e`. +6. **Set `r1` to `0x63` (99).** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r1", 0x63) + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r1` in the **Registers** widget, press `E` (edit), type `63`, and press Enter. The widget may not repaint the value, but the write reaches the target — you confirm it by the printed output in the next steps. +7. **Move the breakpoint past the call.** You want `printf` to run once and then stop, so move the breakpoint from `0x10000272` to the instruction *after* the call, `0x10000276` (the `movs r1, #5` that begins the increment half of the loop): remove the breakpoint at `0x10000272` and set a hardware breakpoint at `0x10000276`. Two reasons not to just click **Step Over** here: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `__wrap_printf` on this raw `.bin` because the image carries no symbol for the call. Moving the breakpoint to the return site is deterministic. +8. Click **Resume** in Binary Ninja. The core executes `bl __wrap_printf` with `r1 = 0x63`, so this iteration prints `arithmetic_operator: 99`, then stops at `0x10000276`. +9. Look at your serial monitor — the `screen` session on the Pico's USB serial port — and at the **Target** tab in Binary Ninja: + + ``` + arithmetic_operator: 99 + ``` + +You changed a running program's output without touching the binary. + +### Step 13b: HACK THE STRING LIVE — change `arithmetic_operator:` to `hacked_operator:` (optional) + +The text `"arithmetic_operator: %d\r\n"` lives in flash (`.rodata`) at `0x100038e8`, and flash is **read-only at runtime** — a debugger write there does not stick. So instead of overwriting the text in place, redirect the pointer: at the `printf` call, `r0` holds the string address, so point `r0` at a replacement string you place in RAM. + +1. Arm the breakpoint at the `printf` call and hit it, exactly as in Step 13 steps 1-3. At the stop, `r0 = 0x100038e8` and `r1 = 0x32`. +2. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console** (`Plugins -> Python Console`) — no command port needed: + ```python + dbg.write_memory(0x20080000, b"hacked_operator: %d\r\n\x00") + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. That writes `hacked_operator: %d\r\n\0`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `0x20080000`, and press Enter.) +4. If you want the value hack too, set `r1` to `0x63` as in Step 13. Then move the breakpoint past the call in the GUI (remove it at `0x10000272`, set one at `0x10000276`) and click **Resume**. The core runs `printf` with `r0` pointing at your RAM string and `r1 = 0x63`, so this iteration prints: + ``` + hacked_operator: 99 + ``` + then stops at `0x10000276`. + +Like the value hack, this is **one iteration only**: the loop reloads `r0` (and `r1`) from flash on every pass, so the next line is `arithmetic_operator: 50` again. The permanent version is the static patch in Step 18c. + +### Step 14: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x1000026e`, which reloads `movs r1, #50`, so the next line is `arithmetic_operator: 50`. The live edit changed one iteration only. There is no variable in memory to change; the value is baked into the instruction. To make `arithmetic_operator: 99` permanent we must patch the instruction. That is the static pass. + +Press **Pause** to stop the output flood. + +### Step 15: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | ------------------- | ---------- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003394()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `dht11_init` + +1. `G` -> `0x100002d4`. +2. `Y` -> `void dht11_init(uint8_t pin)`. + +This is our own `dht11.c` code. In this build the SDK's `gpio_init` and `gpio_pull_up` are called directly (`gpio_pull_up` as a tail-call to `gpio_set_pulls`), so the function is small. + +#### Worked example: `dht11_read` + +1. `G` -> `0x100002f4`. +2. `Y` -> `bool dht11_read(float* humidity, float* temperature)`. + +This is the big one: all six `dht11.c` static helpers are inlined here, along with `gpio_set_dir` / `gpio_put` / `gpio_get` / `time_us_32`, so `dht11_read` contains the entire single-wire protocol and the `0.1f` scale. + +#### Worked example: `gpio_init` + +1. `G` -> `0x100004a4`. +2. `Y` -> `void gpio_init(uint gpio)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x1000047c`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(4)` in `dht11_init` compiles to. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x10003524`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x10003424`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +This is the `else` branch of `print_dht11_reading`, which prints `"DHT11 read failed\r\n"`. (`__wrap_puts` is aliased to `stdio_puts` at the same address.) + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `dht11_init`, `__wrap_printf`, `dht11_read`, `__wrap_puts`, and `sleep_ms`, so we follow that chain down. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── dht11_init ── gpio_init, gpio_set_pulls (gpio_pull_up inlined) +├── __wrap_printf ── __wrap_vprintf ── vfctprintf ── _vsnprintf +│ │ └── _ntoa_format / _out_rev / _out_char +│ ├── stdio_out_chars_crlf +│ └── time_us_64 +├── dht11_read ── sleep_ms, sleep_us +│ └── send_start_signal / wait_for_level / wait_response / read_bit / +│ read_40_bits / validate_checksum / gpio_set_dir / gpio_put / +│ gpio_get / time_us_32 (all inlined; no calls) +└── __wrap_puts ── stdio_put_string +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002d4` | `dht11_init` | `void dht11_init(uint8_t)` | +| `0x100002f4` | `dht11_read` | `bool dht11_read(float*, float*)` | +| `0x10000440` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x1000047c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x100004a4` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000f00` | `sleep_us` | `void sleep_us(uint64_t)` | +| `0x10000fd8` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x100011bc` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011d0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001250` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10001424` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x1000313c` | `exit` | `void exit(int)` | +| `0x10003144` | `runtime_init` | `void runtime_init(void)` | +| `0x10003170` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003280` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000336c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003394` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003424` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003460` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10003524` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036e0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003820` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` path reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10001a44` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x10001ae0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x10001cb4` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x100026fc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x100030e0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`dht_pin` is data, not a function.** `arm-none-eabi-nm -n` lists `20000b7c b dht_pin`. That lowercase `b` is a **local data** symbol: the linker parks the `dht11.c` file-scope static at RAM address `0x20000b7c`. `dht11_init(4)` stores `4` into it. There is no function there; do not `Y` it with a prototype. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002d4: ("dht11_init", "void dht11_init(uint8_t)"), +> 0x100002f4: ("dht11_read", "bool dht11_read(float*, float*)"), +> 0x10000440: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x1000047c: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x100004a4: ("gpio_init", "void gpio_init(uint)"), +> 0x10000f00: ("sleep_us", "void sleep_us(uint64_t)"), +> 0x10000fd8: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x100011bc: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011d0: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001250: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10001424: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x1000313c: ("exit", "void exit(int)"), +> 0x10003144: ("runtime_init", "void runtime_init(void)"), +> 0x10003170: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003280: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000336c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003394: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x10003424: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003460: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x10003524: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036e0: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003820: ("strlen", "size_t strlen(const char*)"), +> 0x10001a44: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x10001ae0: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x10001cb4: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> 0x100026fc: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x100030e0: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`, and `out_fct_type`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + dht11_init(4); + while (true) { + __wrap_printf("arithmetic_operator: %d\r\n", 0x32); // 50 + __wrap_printf("increment_operator: %d\r\n", 5); // 5 + __wrap_printf("relational_operator: %d\r\n", 0); // false + __wrap_printf("logical_operator: %d\r\n", 0); // false + __wrap_printf("bitwise_operator: %d\r\n", 0xa); // 10 + __wrap_printf("assignment_operator: %d\r\n", 0xa); // 10 + if (!dht11_read(&hum, &temp)) { + __wrap_puts("DHT11 read failed\r\n"); + } else { + __wrap_printf("Humidity: %.1f%%, Temperature: %.1f°C\r\n", hum, temp); + } + sleep_ms(2000); + } +} +``` + +The `0x32`, `5`, `0`, `0xa`, and `0xa` are the constants we will patch first. Every one is an **immediate in the instruction stream** — there is no variable in memory to change, which is why the patch edits the instruction operand. + +### Step 18: Patch 1 — change `arithmetic_operator` from 50 to 99 + +Go to `0x1000026e`: + +```asm +1000026e: 32 21 movs r1, #50 @ 0x32 +``` + +`movs r1, #imm8` is a 16-bit Thumb instruction. Its encoding is `0x21XX` (`movs r1, #imm8`), stored little-endian as **`XX 21`** — so the immediate is the byte at the instruction's **own** address, `0x1000026e`. Change `0x32` (50) to `0x63` (99). + +> **This is the opposite byte from the Week 7 `movw` patch.** For a 16-bit `movs`, the immediate is the first byte. For the 32-bit `movw`, the low immediate byte was the *third* byte. Always decode the instruction before you decide which byte to touch. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x1000026e` | `32` | `63` | `movs r1, #50` -> `#99`, prints `arithmetic_operator: 99` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000026e` and change the byte `32` to `63`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000026e, b"\x63") +print(hex(bv.read(0x1000026e, 1)[0])) # -> 0x63 +``` + +After reanalysis the instruction reads `movs r1, #99`. + +### Step 18b: Patch 2 — change the DHT11 scale from `0.1f` to `5.0f` + +The DHT11 driver converts the integer and decimal bytes to a float and scales the decimal part: + +``` +humidity = data[0] + data[1] * 0.1f +temperature = data[2] + data[3] * 0.1f +``` + +`dht11_read` computes both with a fused multiply-add against a single `0.1f` constant. Look at the end of `dht11_read`: + +```asm +100003ee: vmov s15, r6 +100003f2: vcvt.f32.s32 s12, s15 +100003f6: vmov s15, r1 +100003fa: vcvt.f32.s32 s14, s15 +100003fe: vmov s15, r0 +10000402: vcvt.f32.s32 s13, s15 +10000406: vmov s15, r2 +1000040a: vldr s11, [pc, #44] @ 10000438 +1000040e: vcvt.f32.s32 s15, s15 +10000412: movs r0, #1 +10000414: vfma.f32 s14, s12, s11 +10000418: vfma.f32 s15, s13, s11 +1000041c: vstr s14, [r5] +10000420: vstr s15, [fp] +``` + +The constant `s11` is loaded by the `vldr s11, [pc, #44]` at `0x1000040a`, which reads the literal-pool word at `0x10000438`. That word is `0x3dcccccd` (float `0.1`), stored little-endian as `cd cc cc 3d`. Change it to `0x40a00000` (float `5.0`), bytes `00 00 a0 40`: + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x10000438` | `cd cc cc 3d` | `00 00 a0 40` | `0.1f` -> `5.0f`; the humidity/temperature decimal parts read ~50x larger | + +``` ++-----------------------------------------------------------------+ +| IEEE-754 little-endian change | +| | +| 0.1f = 0x3dcccccd -> bytes cd cc cc 3d | +| 5.0f = 0x40a00000 -> bytes 00 00 a0 40 | +| | +| humidity = int + (decimal * 0.1f) becomes | +| humidity = int + (decimal * 5.0f) | +| | ++-----------------------------------------------------------------+ +``` + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000438` and change `cd cc cc 3d` to `00 00 a0 40`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000438, bytes.fromhex("0000a040")) +print(bv.read(0x10000438, 4).hex()) # -> 0000a040 +``` + +> **The scale is applied to both humidity and temperature.** The two `vfma.f32` instructions both read `s11`, so patching the one constant changes both readings, not just temperature. + +### Step 18c: Patch 3 — rename the printed label + +The string `"arithmetic_operator: %d\r\n"` starts at `0x100038e8`. Its first 26 bytes are: + +``` +61 72 69 74 68 6d 65 74 69 63 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 + a r i t h m e t i c _ o p e r a t o r : % d \r \n \0 +``` + +We replace it with `"hacked_operator: %d\r\n\0"`, which is **four bytes shorter**, and pad the tail with NULs: + +``` +68 61 63 6b 65 64 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 00 00 00 00 + h a c k e d _ o p e r a t o r : % d \r \n \0 +``` + +The `\0` at offset 21 terminates the string, so `printf` stops there and the four padding bytes are never read. The next format string (`"increment_operator: …"`) begins at `0x10003904`, which is 28 bytes past `0x100038e8`, so our 26-byte write cannot reach it. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x100038e8` | `61 72 69 74 68 6d 65 74 69 63 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00` | `68 61 63 6b 65 64 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 00 00 00 00` | prints `hacked_operator:` instead of `arithmetic_operator:` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x100038e8` and replace the 26 bytes above. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100038e8, b"hacked_operator: %d\r\n\x00\x00\x00\x00") +print(bv.read(0x100038e8, 26)) # -> b'hacked_operator: %d\r\n\x00\x00\x00\x00' +``` + +> **Keep the NUL.** `printf` walks the format string until it hits `\0`. If you omit it, the printer runs on into the padding and then into the next string, producing garbage. The four padding bytes guarantee the terminator. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x001a_operators", "build"), "0x001a_operators-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 17484 /.../build/0x001a_operators-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x444c` = 17484). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so `open("0x001a_operators-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x001a_operators-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x001a_operators-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x001a_operators", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x001a_operators-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +### Step 21: Flash and verify + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Open the serial monitor: + +``` +hacked_operator: 99 +increment_operator: 5 +relational_operator: 0 +logical_operator: 0 +bitwise_operator: 10 +assignment_operator: 10 +Humidity: 255.0%, Temperature: 119.0°C +... +``` + +- The first line now reads **`hacked_operator: 99`**. +- The humidity/temperature decimals are scaled by **5.0** instead of **0.1**, so the readings are roughly 50x larger (exact numbers depend on your sensor). + +**All three changes — one instruction byte, one float word, and one string — with no source code.** + +> **Faster: flash over the Debug Probe (no BOOTSEL).** The repo's `flash.sh` writes the raw `.bin` straight into XIP flash over SWD (`program 0x10000000 verify reset exit`), so you never touch BOOTSEL or a UF2. Run it from a terminal (`./flash.sh `), or from the Binary Ninja console **without freezing it** — use `subprocess.Popen`, which returns immediately, and send OpenOCD's output to a log file. (`subprocess.run` blocks the console until the flash finishes; do not use it here.) +> +> ```python +> import os, subprocess +> root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +> bin_path = os.path.join(os.path.join(root, "0x001a_operators", "build"), "0x001a_operators-h.bin") +> log = os.path.join(os.path.join(root, "0x001a_operators", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> The `pkill` frees the probe first; on Windows use `subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"])`. +> +> The console is free the moment this returns. Check it with `print(p.poll())` (`None` = still running, `0` = done) or read `flash.log` — success ends with `** Verified OK **`. +> +> The same non-blocking form without the script: +> +> ```python +> import os, subprocess +> ocd = os.path.expanduser("~/.pico-sdk/openocd/0.12.0+dev") +> bin_path = os.path.join(os.path.join(root, "0x001a_operators", "build"), "0x001a_operators-h.bin") +> log = os.path.join(os.path.join(root, "0x001a_operators", "build"), "flash.log") +> subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +> p = subprocess.Popen([f"{ocd}/openocd", "-s", f"{ocd}/scripts", +> "-f", "interface/cmsis-dap.cfg", "-f", "target/rp2350.cfg", +> "-c", "adapter speed 5000", +> "-c", f"program {bin_path} 0x10000000 verify reset exit"], +> stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +> print("flashing in the background; log:", log) +> ``` +> +> **The Debug Probe is single-owner.** If Binary Ninja is still attached (the `debug-server.sh` OpenOCD is running), the flash cannot grab the probe. Detach in Binary Ninja and stop that OpenOCD first: +> +> ```bash +> # macOS / Linux +> pkill -TERM -f openocd +> ``` +> ```powershell +> # Windows +> Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +> ``` +> +> Success looks like `Programming Finished` -> `Verified OK` -> `Resetting Target`. On Windows use `flash.ps1` (`.\flash.ps1 -Bin `) the same way. + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r1", 0x63)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write a RAM string live | `dbg.write_memory(0x20080000, b"hacked_operator: %d\r\n\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 into the Python Console | +| Load peripheral names (optional) | Load the RP2350 SVD — it lives at **`WEEK04/rp2350.svd`** | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 12). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Start the server parked in the loop | macOS/Linux: `BP_ADDR=0x10000272 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000272"; .\debug-server.ps1` | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x1000026e` | `32` | `63` | `movs r1, #50` -> `#99`, prints `arithmetic_operator: 99` | +| `0x001a` | `0x10000438` | `cd cc cc 3d` | `00 00 a0 40` | DHT11 scale `0.1f` -> `5.0f`, readings ~50x larger | +| `0x001a` | `0x100038e8` | `61 72 69 74 68 6d 65 74 69 63 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00` | `68 61 63 6b 65 64 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 00 00 00 00` | prints `hacked_operator:` instead of `arithmetic_operator:` | + +### The operator / DHT11 memory map + +| Item | Address | Notes | +| ---- | ------- | ----- | +| `dht_pin` | `0x20000b7c` | RAM `.bss`, the `dht11.c` static holding the GPIO number (`4`) | +| Literal-pool word — humidity/temp format | `0x100002b4` | `0x10003988` — `"Humidity: %.1f%%, Temperature: %.1f°C\r\n"` | +| Literal-pool word — arithmetic format | `0x100002b8` | `0x100038e8` — `"arithmetic_operator: %d\r\n"` | +| Literal-pool word — increment format | `0x100002bc` | `0x10003904` — `"increment_operator: %d\r\n"` | +| Literal-pool word — relational format | `0x100002c0` | `0x10003920` — `"relational_operator: %d\r\n"` | +| Literal-pool word — logical format | `0x100002c4` | `0x1000393c` — `"logical_operator: %d\r\n"` | +| Literal-pool word — bitwise format | `0x100002c8` | `0x10003954` — `"bitwise_operator: %d\r\n"` | +| Literal-pool word — assignment format | `0x100002cc` | `0x1000396c` — `"assignment_operator: %d\r\n"` | +| Literal-pool word — failure string | `0x100002d0` | `0x100039b4` — `"DHT11 read failed\r\n"` | +| `dht11_read` literal-pool word | `0x10000434` | `0x400b0000` — TIMER0 base, used by the inlined `time_us_32` | +| DHT11 scale constant | `0x10000438` | `0x3dcccccd` — `0.1f` | +| `dht11_read` literal-pool word | `0x1000043c` | `0x20000b7c` — `&dht_pin` | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project size | `17484` bytes (`0x444c`) | +| Fixed `main` anchor | `0x1000018c` (reset handler middle `blx`) | +| `main` | `0x10000234` | +| `dht11_init` | `0x100002d4` | +| `dht11_read` | `0x100002f4` | +| `printf` call / return, `arithmetic_operator` | `0x10000272` / `0x10000276` | +| `arithmetic_operator` format string | `0x100038e8` | +| `increment_operator` format string | `0x10003904` | +| `relational_operator` format string | `0x10003920` | +| `logical_operator` format string | `0x1000393c` | +| `bitwise_operator` format string | `0x10003954` | +| `assignment_operator` format string | `0x1000396c` | +| Humidity/Temperature format string | `0x10003988` | +| `"DHT11 read failed\r\n"` string | `0x100039b4` | +| DHT11 scale constant | `0x10000438` | +| DHT11 GPIO pin | `4` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### My operator values are 12 and 11, not 10 and 10 + +You are reading the original Week 9 text, not this build. In `0x001a_operators.c`, `compute_arithmetic_ops` receives `x` **by value**, so its `*incr = x++;` never touches `compute_operators`' `x`. That `x` stays `5`, so `x << 1` is `10` and `x += 5` is `10`. Confirm it on your own ELF in Step 4: the immediates in `main` are `#50`, `#5`, `#0`, `#0`, `#10`, `#10`. + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints (see the next entry). +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 10). The 13.3.rel1 build did **not** connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +**Use GDB MI**, with the 14.2.rel1 path above. If it still fails, fall back to plain `arm-none-eabi-gdb` against the same server — the addresses and register values are identical to the GUI steps. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### The GUI refuses to set a breakpoint (GDB RSP adapter only) + +If you are on the **GDB RSP** adapter, the GUI cannot set breakpoints on this target. That adapter is Binary Ninja's own minimal RSP client and sends a **1-byte** breakpoint (`Z0,,1`); the Cortex-M33 comparators need 2 bytes, so OpenOCD answers `only breakpoints of two bytes length supported`. It affects every address, both `Toggle Breakpoint` and `Add Hardware Breakpoint`, and the dialog's **Size** field is disabled. `gdb_breakpoint_override` makes no difference. + +**Fix: use the GDB MI adapter** (Step 10). It drives real GDB, which sends the correct length, so GUI breakpoints just work. If you must stay on GDB RSP, arm breakpoints from the command port after connecting (`bp 2 hw`) — but the lab uses GDB MI and does not need that. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. This is a Binary Ninja bug. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +Never have a breakpoint in the binary view before the GDB MI connection. If it hangs, quit Binary Ninja, restart the server with `BP_ADDR`, and connect again before adding any breakpoints. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping, because the RP2350 config's `-rtos hwthread` makes the current thread id 1 while Binary Ninja sends thread id 0. Fix: `rp2350.dap.core0 configure -rtos none` (the launcher scripts already pass this). **GDB MI does not hit this.** + +To tell them apart, turn on OpenOCD logging (`log_output /tmp/ocd.log`, then `debug_level 3` on the command port) and look for `fake step` versus `Duplicate Breakpoint`. + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps `print_operator_results`, `compute_operators`, and the `dht11.c` helpers as separate calls, so `main` is not at `0x10000234` and the operator results are not bare immediates. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. With the **GDB MI** adapter, `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — that is a software breakpoint and cannot be written to read-only flash, so it never installs. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Verify it is armed:** `mdw 0xE0002000 8`. You should see your address with the low bit set (`0x10000272` -> `0x10000273`). All zeros means nothing is armed — re-read this first, because it distinguishes "not armed" from "armed but never reached". +- **Is the core running?** `poll` on the command port should not report a halt. If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup (Step 9) rather than `reset run` while attached. Loop addresses such as `0x10000272` fire on the next pass with no reset — arm them and click **Resume** in Binary Ninja. +- **With GDB MI the stop is reported as `Breakpoint`** and appears in the **Breakpoints** widget, because GDB really did set it. + +### I edit `r1` (or another register) and it reverts + +`main` reloads the value at the top of every loop iteration — `movs r1, #50` at `0x1000026e` runs right before the `printf` at `0x10000272`. So `r1` is only `0x63` for the instant between your edit and the next pass; then it is `0x32` again. The edit sticks only if the core is **genuinely stopped** at the breakpoint and stays stopped. + +If it keeps reverting, the core is running, which almost always means the breakpoint is not installed — usually because it is a **software** breakpoint (`F2`) that cannot be written to read-only flash. Use `Debugger -> Add Hardware Breakpoint...` (hardware execute). + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target, and there is no "refresh registers" command. So a value changed outside Binary Ninja will not appear until the next stop. + +### The string hack does nothing + +The live version needs to run **before** the `printf` call, which means breaking at `0x10000272` and redirecting `r0` while stopped. If you let it resume, the loop reloads `r0` from the literal pool on the next pass and the hack is gone. + +Also confirm you wrote a NUL-terminated string. `printf` walks bytes until `*r0 == 0`; without the trailing `\x00`, it keeps reading RAM garbage. + +### The patched instruction still shows the old value + +Right-click the function and choose `Reanalyze`. Binary Ninja caches the disassembly text; a byte edit does not always trigger a re-lift by itself. + +### The arith patch corrupts the instruction + +You patched the wrong byte. `movs r1, #imm8` is 16-bit and its immediate is the **first** byte: the instruction starts at `0x1000026e`, so the byte to change is `0x1000026e` (`0x32 -> 0x63`). Patching `0x1000026f` (the `0x21` opcode) corrupts the instruction and the core will fault. + +### The DHT11 reading did not change + +Confirm you patched the right word. The scale is the literal loaded by `vldr s11, [pc, #44]` at `0x1000040a`; that literal lives at `0x10000438` and is `cd cc cc 3d` (`0.1f`). Change it to `00 00 a0 40` (`5.0f`). If your sensor is not connected or not answering, `dht11_read` returns `false` and the firmware prints `DHT11 read failed` instead — the scale patch only matters when a reading succeeds. + +### The `arithmetic_operator` string hack overran + +The replacement must be NUL-terminated. `"hacked_operator: %d\r\n"` is 21 characters; write it plus a `\0` (22 bytes) and pad the remaining four bytes with `00`. The next format string begins at `0x10003904`, 28 bytes past `0x100038e8`, so a 26-byte write stays clear of it. A longer write overwrites `"increment_operator: …"`. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first: clear canonical/echo flags, set `CLOCAL|CREAD`, and `B115200` on input and output. `screen /dev/cu.usbmodem* 115200` does all of this for you; a script must call `tcsetattr` itself. Once set, the capture reads clean `arithmetic_operator: 50` lines. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +This is the most common failure, and it has one main cause: **driving the core from the OpenOCD command port while Binary Ninja is connected.** + +- If you send `reset run` from the port while attached, the core resets, runs, and halts at your breakpoint — but Binary Ninja never receives the stop event. Its sidebar keeps showing the *previous* location, so **Step** and **Resume** act on a stale PC and appear to do nothing. +- If the OpenOCD process dies (or you restart it) while attached, Binary Ninja keeps believing it is connected: the sidebar stays, but the menu shows **Pause** enabled and **Resume**/**Step** disabled because Binary Ninja last saw the target *running*. + +Recovery: **Detach, then reconnect.** If Detach does nothing (the connection is already dead), restart Binary Ninja — its menu still shows a session that no longer exists. + +Prevention: + +- Stop at `main` with `BP_ADDR` on a fresh server start, not with `reset run` while attached. +- For loop addresses, set the breakpoint in the GUI and click **Resume**. Let Binary Ninja be the thing that starts the core. +- If you must reset, **Detach first**, `reset run`, then reconnect. +- Never leave a breakpoint on the PC you are about to step or resume from. + +### The target "blows past" `main` and stops at `0x10003648` instead + +`0x10003648` is `stdio_uart_out_flush`, the UART transmit-FIFO drain loop inside `printf`: + +```asm +10003648: 4b02 ldr r3, [pc, #8] @ (10003654 ) +1000364a: 681a ldr r2, [r3] +1000364c: 6993 ldr r3, [r2, #24] +1000364e: 071b lsls r3, r3, #28 +10003650: d4fc bmi.n 1000364c +10003652: 4770 bx lr +``` + +That is where the core sits while the UART drains, so the core is running `main`'s loop and simply spends nearly all its time there. The breakpoint at `main` did not fire because `main`'s entry runs exactly **once per reset**. If you arm the breakpoint after the reset, or set it while the target is already running and just resume, the core is already past `main` and will never re-execute it. Either arm the breakpoint **before** resetting, or break inside the loop at `0x10000272`, which fires every iteration. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### `Connect to Remote Process` is greyed out and Pause does nothing + +Binary Ninja is in a stale session, usually because the debug server restarted while attached. Quit and reopen Binary Ninja (or the `.bndb`) and connect again. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27 (see Troubleshooting), you can still do the live hack with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 9), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x10000272 +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x10000272` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. If you reset first, the core runs `main` and you will not catch it. + +GDB stops at the `printf` call. Confirm the value, change it, and let it run: + +``` +info registers pc r0 r1 # pc = 0x10000272, r0 = 0x100038e8, r1 = 0x32 +set $r1 = 0x63 +stepi +continue +``` + +The serial monitor prints `arithmetic_operator: 99` for the iteration you changed — the same temporary live hack as editing `r1` in the Binary Ninja Registers widget. When you are done, press `Ctrl-C`, then `detach` and `quit`. + +**If you specifically want to stop at `main` (`0x10000234`),** remember its entry runs only once per reset, so the breakpoint must be armed *before* the reset: + +``` +monitor reset halt +hbreak *0x10000234 +continue +``` + +If you instead set it while the target is running and just `continue`, you will "blow past" `main` and catch the core inside `printf` — in this build at `0x10003648`, the `stdio_uart_out_flush` UART-drain loop. + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too; the old **GDB RSP** adapter was the one that sent a 1-byte length and could not set breakpoints here. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **AAPCS** | ARM Architecture Procedure Call Standard — `r0`-`r3` for the first four arguments, `r0` for the return value | +| **Arithmetic operator** | C operators for math (`+`, `-`, `*`, `/`, `%`); here `x * y` folds to `#50` | +| **Assignment operator** | Compound assignment (`+=`, `-=`, …); here `x += 5` folds to `#10` | +| **Bitwise operator** | Operators on individual bits (`<<`, `>>`, `&`, `\|`, `^`); here `x << 1` folds to `#10` | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; `dht_pin` lives here | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **DHT11** | Low-cost single-wire digital humidity and temperature sensor | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **Fused multiply-add** | `vfma.f32 Sd, Sn, Sm` computes `Sd = Sd + (Sn * Sm)` in one operation | +| **Immediate value** | A constant embedded directly in an instruction, not fetched from memory | +| **Increment operator** | `x++` (post) or `++x` (pre); here `x++` returns the old value, `5` | +| **IEEE-754** | Standard for floating-point representation; `0.1f` is `0x3dcccccd` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **Logical operator** | Operators combining conditions (`&&`, `\|\|`, `!`); here `false` | +| **`movs`** | 16-bit Thumb move that loads an 8-bit immediate (0-255); immediate is the first byte | +| **`movw`** | 32-bit Thumb-2 "move wide" that loads a 16-bit immediate; low imm8 is the third byte | +| **PCF8574** | An I2C I/O expander; not used this week (that was the LCD, Week 7) | +| **Relational operator** | Comparison operators (`<`, `>`, `==`, `!=`); here `5 > 10` is `false` | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SIO** | Single-cycle I/O block; `gpio_set_dir` / `gpio_put` write it with `mcrr`, `gpio_get` reads it | +| **SVD** | System View Description file — register names for a peripheral; the RP2350 one is at **`WEEK04/rp2350.svd`** | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **TIMER0** | RP2350 timer block at `0x400b0000`; `time_us_32` reads its `TIMERAWL` register (`+0x28`) | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, read `r1` at the arithmetic `printf` call, resolve the names from the ELF (including the `dht11.c` symbols), then patch the bytes — the `movs` immediate (`0x32 -> 0x63`), the DHT11 float word (`0.1f -> 5.0f`), and the format string (`arithmetic_operator:` -> `hacked_operator:`) — and flash. diff --git a/WEEK09/WEEK09-BN.pdf b/WEEK09/WEEK09-BN.pdf new file mode 100644 index 0000000..5ff4aba Binary files /dev/null and b/WEEK09/WEEK09-BN.pdf differ diff --git a/WEEK09/WEEK09-IDA.md b/WEEK09/WEEK09-IDA.md new file mode 100644 index 0000000..bce3dd1 --- /dev/null +++ b/WEEK09/WEEK09-IDA.md @@ -0,0 +1,781 @@ +# Week 9-IDA: IDA Pro — Read, Hack, and Patch Operator Immediates and a DHT11 Float Scale (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the lesson project with `Release` and get both an `.elf` and a raw `.bin` +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load the raw `.bin` into IDA at `0x10000000` +- Read the six C operator results as **bare instruction immediates** (`movs r1, #50`, `movs r1, #5`, …) +- Read the DHT11 single-wire driver, including the inlined `gpio_*` and `time_us_32` helpers +ted value live +t +- **Resolve the functions in the IDA GUI** using the ELF symbol map, including the `dht11.c` symbols +- **Patch** the arithmetic immediate (`50 -> 99`) and the DHT11 scaling constant (`0.1f -> 5.0f`) +- **Rename** the printed label by patching the `"arithmetic_operator:"` string +- **Export** the patched image, convert it to UF2, and export it + +--- + +## How This Guide Works + +The build produces two files for the project: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table | Ground truth for every function address and name | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We use the ELF symbol map to resolve functions in IDA, and we reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the Week 9 lesson, and the Week 9 lesson is a `Release` build. `Release` optimizes the code the same way the original lesson was built: it **inlines** the `static` helpers `print_operator_results`, `compute_arithmetic_ops`, `compute_operators`, and `print_dht11_reading` straight into `main`, and it inlines the whole `dht11.c` static helper chain (`send_start_signal`, `wait_for_level`, `wait_response`, `read_bit`, `read_40_bits`, `validate_checksum`) into `dht11_read`. Every operator result is folded to a bare `movs r1, #imm` immediate. If you build `Debug`, the SDK function addresses move and the helpers stay separate calls, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Serial output | Also does | The hacks | +| ------- | ------------- | --------- | --------- | +| `0x001a_operators` | six operator lines, then `Humidity: …%, Temperature: …°C` | DHT11 single-wire sensor on GPIO 4 | `50 -> 99` (arithmetic immediate), `0.1f -> 5.0f` (DHT11 scale), and `"arithmetic_operator:" -> "hacked_operator:"` | + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3. Confirm against your own `.elf` with the command in Step 4. + +> **The surprise of this week is how small the operator code is.** The C source computes `x * y`, `x > y`, `x << 1`, and `x += 5` in a helper function, but `Release` folds every one of those into a compile-time constant and stores it as a one-byte immediate inside a `movs r1, #imm` instruction. There is no variable in memory to change — the answer is baked into the instruction stream. The DHT11 reading is different: it is a real measurement scaled by a `float` constant (`0.1f`) sitting in the literal pool, and *that* one is a data word you can patch. + +> **A note on the sensor reading.** The humidity/temperature numbers depend on the physical DHT11 attached to GPIO 4. This guide's ground truth is about the *code*, not the sensor: the scale constant, where `dht11_read` lives, and which register holds the reading. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +bash +``` + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the project with `Release` + +Run this inside `0x001a_operators/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point IDA at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so IDA never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the IDA console**, so the whole build -> patch -> flash loop stays inside IDA. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +proj = os.path.join(root, "0x001a_operators") +subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) +subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +The build directory now contains the pair we need: + +- `0x001a_operators/build/0x001a_operators.elf` and `.bin` — the `.bin` is **17484** bytes (`0x444c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `~/.pico-sdk/toolchain/14_2_Rel1/bin` | +| Linux x64 | `/usr` | + +> **This guide's toolchain lives at `~/.pico-sdk/toolchain/14_2_Rel1/bin`.** All of `arm-none-eabi-nm`, `arm-none-eabi-objdump`, and `arm-none-eabi-gdb` resolved in this document come from there. If your install is elsewhere, `which arm-none-eabi-nm` tells you where to point. + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on the ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x001a_operators.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x001a_operators.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. Here are the functions this lesson uses. The signatures come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (all four static helpers inlined) | +| `0x100002d4` | `dht11_init` | `void dht11_init(uint8_t)` | the `dht11.c` init function | +| `0x100002f4` | `dht11_read` | `bool dht11_read(float*, float*)` | the `dht11.c` read function (all six static helpers inlined) | + +**The GPIO and timer functions `main` / `dht11.c` reach:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000440` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select (UART pins) | +| `0x1000047c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull config (`gpio_pull_up` inlined) | +| `0x100004a4` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init (`dht11_init` calls it) | +| `0x10000f00` | `sleep_us` | `void sleep_us(uint64_t)` | SDK microsecond delay (`dht11_read` calls it) | +| `0x10000fd8` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay (`main`, `dht11_read`) | +| `0x100011bc` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (`printf` path) | +| `0x100011d0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001250` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10001424` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | + +**The stdio/UART and printf chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000313c` | `exit` | `void exit(int)` | C runtime exit | +| `0x10003144` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003170` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003280` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000336c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003394` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003424` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (`DHT11 read failed`) | +| `0x10003460` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x10003524` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (all seven calls) | +| `0x100036e0` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003820` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**SDK helpers the `printf` path reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10001a44` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | reversed-digit output | +| `0x10001ae0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | number formatter | +| `0x10001cb4` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | single-char sink | +| `0x100026fc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | the format dispatcher | +| `0x100030e0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | + +Things in this project that have **no symbol of their own**, because the compiler inlined them: + +- `print_operator_results`, `compute_arithmetic_ops`, `compute_operators`, `print_dht11_reading` — the four `static` helpers in `0x001a_operators.c` are inlined into `main`, so their bodies appear directly inside `main`. +- `send_start_signal`, `wait_for_level`, `wait_response`, `read_bit`, `read_40_bits`, `validate_checksum` — the six `static` helpers in `dht11.c` are inlined into `dht11_read`, along with `gpio_set_dir`, `gpio_put`, `gpio_get`, and `time_us_32` from the SDK headers. You see `mcrr` (SIO writes), `ldr [.., #4]` (SIO reads), and `ldr [r0, #40]` (TIMER0 read) directly inside `dht11_read`. +- `gpio_pull_up` — `static inline` in the SDK, so `dht11_init` compiles to a direct tail-call to `gpio_set_pulls`. + +> **`dht_pin` is a `b` symbol, not a function.** `arm-none-eabi-nm -n` lists `20000b7c b dht_pin`. That lowercase `b` is a **local data** symbol: the `dht11.c` file-scope `static uint dht_pin;` is parked in RAM `.bss` at `0x20000b7c`. It holds the GPIO number (`4`) after `dht11_init(4)` runs. There is no function there; do not `Y` it with a prototype. + +## Part 2: Load the Raw `.bin` into IDA + +Start from a fresh IDA state. If you already have a database for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into IDA + +A raw `.bin` has no headers, so IDA cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, IDA may load it with a guessed architecture, and every address in this lesson will be wrong. + +#### 1.1 Open the file +1. **File ▸ Open…** (Ctrl/Cmd+O). +2. Select the `.bin` file and click **Open**. + +IDA opens the **"Load a new file"** dialog because a raw `.bin` has no header. + +#### 1.2 Set the format and processor +In the *Load a new file* dialog: +1. **Format**: leave it as **Binary file** (IDA auto-detects a headerless image). +2. **Processor type**: click the **…** button next to the processor field. In the *Processor type* dialog: + - Family: **ARM** + - Type: **ARM Little-endian** (the 32-bit ARM module). + - Click **OK**. + +> If IDA asks **"Do you want to disassemble it as 64-bit code?"** — click **No**. +> The RP2350 is 32-bit; answering *Yes* loads AArch64 and you get `X` registers / data. (This is the single most common cause of the `DCB` wall.) + +#### 1.3 Configure the ARM architecture and Thumb mode +Still in the *Load a new file* dialog, open the processor options (the **Processor options** / **Set…** button, which opens the dialog titled **ARM architecture options**): +- **ARM architecture**: choose **ARMv8-M** (this is the Cortex-M33 / RP2350 core). +- **Thumb instructions**: select **Thumb-2** (ARMv8-M is Thumb-only, so this is the correct mode). +- Leave **automatic ARM-THUMB switch** off; we want Thumb throughout. + +#### 1.4 Set the loading address +- **Loading address**: enter **`10000000`** (hex; the RP2350 XIP flash base). + IDA rejects addresses that don't look like ROM/RAM with *"The loading address should belong to RAM or ROM"* — `0x10000000` is the correct flash window. + +Leave **Manual load** and **Create segments** at their defaults. Click **OK**. + +#### 1.5 Force Thumb, then seed the code from the vector table +A raw `.bin` has no header, so IDA's loader has **no entry point** and defaults the segment to **ARM mode** (which cannot decode Thumb). Two required steps — in this order: + +**A. Set the segment to Thumb (do this first).** +- **Edit ▸ Segments ▸ Set default segment register value…** → register **`T`** = **`1`** (or press **`Alt+G`**). IDA reanalyzes the segment as Thumb automatically. + +**B. Seed the code from the vector table.** +1. **G** → `10000000`. The first two words are the initial stack pointer and the **reset vector**. +2. **Read the 4-byte word at `0x10000004`** (do **not** assume its value — it differs per build). +3. **Clear bit 0** (the ARM **Thumb** flag) → the reset handler address. +4. **G** to that address → press **C** (**MakeCode**). IDA disassembles the reset handler and follows its `bl`s into `main`. + +Once `main` shows code, the import is correct. + +**Why IDA needs this and others don't:** IDA's generic raw-binary ARM loader treats the image as flat data and waits for you to set Thumb and mark the entry point. It's an IDA quirk, not a mistake on your part. + +### Step 8: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +> **Optional — load the RP2350 SVD for peripheral names.** If you want IDA to label peripheral registers (TIMER0, SIO, UART0, …) instead of bare addresses, load the RP2350 SVD. It ships with Week 4, so it lives at **`WEEK04/rp2350.svd`** inside the repository — remember it is in **Week 4**, not this week. This lesson does not need it; the ELF symbol map already names every function. + +--- + +## Part 3: Static — Resolve the Functions in IDA and Patch + +### Step 16: Resolve the functions in the IDA GUI + +We now name the functions in IDA using the ELF symbol map from Step 4. IDA loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | IDA action | Use it for | +| --- | ------------------- | ---------- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in IDA (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003394()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +The decompiler header then shows the real prototype, and calls to the function read cleanly instead of `sub_()`. `N` is only for renaming without touching the type; `Y` alone sets both the name and the type. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. IDA parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The view jumps there; the cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. That sets the name to `main` and the type to `int(void)`. + +> **IDA shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and IDA's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `dht11_init` + +1. `G` -> `0x100002d4`. +2. `Y` -> `void dht11_init(uint8_t pin)`. + +This is our own `dht11.c` code. In this build the SDK's `gpio_init` and `gpio_pull_up` are called directly (`gpio_pull_up` as a tail-call to `gpio_set_pulls`), so the function is small. + +#### Worked example: `dht11_read` + +1. `G` -> `0x100002f4`. +2. `Y` -> `bool dht11_read(float* humidity, float* temperature)`. + +This is the big one: all six `dht11.c` static helpers are inlined here, along with `gpio_set_dir` / `gpio_put` / `gpio_get` / `time_us_32`, so `dht11_read` contains the entire single-wire protocol and the `0.1f` scale. + +#### Worked example: `gpio_init` + +1. `G` -> `0x100004a4`. +2. `Y` -> `void gpio_init(uint gpio)`. + +#### Worked example: `gpio_set_pulls` + +1. `G` -> `0x1000047c`. +2. `Y` -> `void gpio_set_pulls(uint gpio, bool up, bool down)`. + +This is what `gpio_pull_up(4)` in `dht11_init` compiles to. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x10003524`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Rename it `printf` if you prefer the lesson's shorthand, but `__wrap_printf` is what the ELF says. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x10003424`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +This is the `else` branch of `print_dht11_reading`, which prints `"DHT11 read failed\r\n"`. (`__wrap_puts` is aliased to `stdio_puts` at the same address.) + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. `main` calls `stdio_init_all`, `dht11_init`, `__wrap_printf`, `dht11_read`, `__wrap_puts`, and `sleep_ms`, so we follow that chain down. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── dht11_init ── gpio_init, gpio_set_pulls (gpio_pull_up inlined) +├── __wrap_printf ── __wrap_vprintf ── vfctprintf ── _vsnprintf +│ │ └── _ntoa_format / _out_rev / _out_char +│ ├── stdio_out_chars_crlf +│ └── time_us_64 +├── dht11_read ── sleep_ms, sleep_us +│ └── send_start_signal / wait_for_level / wait_response / read_bit / +│ read_40_bits / validate_checksum / gpio_set_dir / gpio_put / +│ gpio_get / time_us_32 (all inlined; no calls) +└── __wrap_puts ── stdio_put_string +``` + +**Resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002d4` | `dht11_init` | `void dht11_init(uint8_t)` | +| `0x100002f4` | `dht11_read` | `bool dht11_read(float*, float*)` | +| `0x10000440` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x1000047c` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x100004a4` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000f00` | `sleep_us` | `void sleep_us(uint64_t)` | +| `0x10000fd8` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x100011bc` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011d0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001250` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10001424` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x1000313c` | `exit` | `void exit(int)` | +| `0x10003144` | `runtime_init` | `void runtime_init(void)` | +| `0x10003170` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003280` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000336c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003394` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003424` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003460` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10003524` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036e0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003820` | `strlen` | `size_t strlen(const char*)` | + +**Resolve the SDK helpers the `printf` path reaches:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x10001a44` | `_out_rev` | `unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)` | +| `0x10001ae0` | `_ntoa_format` | `unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)` | +| `0x10001cb4` | `_out_char` | `void _out_char(char, void*, size_t, size_t)` | +| `0x100026fc` | `_vsnprintf` | `int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)` | +| `0x100030e0` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | + +> **A `void` return type may not stick — here is the fix.** IDA treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type IDA thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **`dht_pin` is data, not a function.** `arm-none-eabi-nm -n` lists `20000b7c b dht_pin`. That lowercase `b` is a **local data** symbol: the linker parks the `dht11.c` file-scope static at RAM address `0x20000b7c`. `dht11_init(4)` stores `4` into it. There is no function there; do not `Y` it with a prototype. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into IDA's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> typedef void (*out_fct_type)(char, void*, size_t, size_t); +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002d4: ("dht11_init", "void dht11_init(uint8_t)"), +> 0x100002f4: ("dht11_read", "bool dht11_read(float*, float*)"), +> 0x10000440: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x1000047c: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x100004a4: ("gpio_init", "void gpio_init(uint)"), +> 0x10000f00: ("sleep_us", "void sleep_us(uint64_t)"), +> 0x10000fd8: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x100011bc: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011d0: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001250: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10001424: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x1000313c: ("exit", "void exit(int)"), +> 0x10003144: ("runtime_init", "void runtime_init(void)"), +> 0x10003170: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003280: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000336c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003394: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x10003424: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003460: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x10003524: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036e0: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003820: ("strlen", "size_t strlen(const char*)"), +> 0x10001a44: ("_out_rev", "unsigned _out_rev(out_fct_type, char*, size_t, size_t, const char*, size_t, unsigned, unsigned)"), +> 0x10001ae0: ("_ntoa_format", "unsigned _ntoa_format(out_fct_type, char*, size_t, size_t, char*, size_t, bool, unsigned, unsigned, unsigned, unsigned)"), +> 0x10001cb4: ("_out_char", "void _out_char(char, void*, size_t, size_t)"), +> 0x100026fc: ("_vsnprintf", "int _vsnprintf(out_fct_type, char*, size_t, const char*, va_list)"), +> 0x100030e0: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`, and `out_fct_type`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first (an opaque `struct`/`enum`/`typedef` is enough to parse). Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. If you add a function that uses another SDK type, add a definition for it to that block too. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. Once the functions above are typed, it reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + dht11_init(4); + while (true) { + __wrap_printf("arithmetic_operator: %d\r\n", 0x32); // 50 + __wrap_printf("increment_operator: %d\r\n", 5); // 5 + __wrap_printf("relational_operator: %d\r\n", 0); // false + __wrap_printf("logical_operator: %d\r\n", 0); // false + __wrap_printf("bitwise_operator: %d\r\n", 0xa); // 10 + __wrap_printf("assignment_operator: %d\r\n", 0xa); // 10 + if (!dht11_read(&hum, &temp)) { + __wrap_puts("DHT11 read failed\r\n"); + } else { + __wrap_printf("Humidity: %.1f%%, Temperature: %.1f°C\r\n", hum, temp); + } + sleep_ms(2000); + } +} +``` + +The `0x32`, `5`, `0`, `0xa`, and `0xa` are the constants we will patch first. Every one is an **immediate in the instruction stream** — there is no variable in memory to change, which is why the patch edits the instruction operand. + +### Step 18: Patch 1 — change `arithmetic_operator` from 50 to 99 + +Go to `0x1000026e`: + +```asm +1000026e: 32 21 movs r1, #50 @ 0x32 +``` + +`movs r1, #imm8` is a 16-bit Thumb instruction. Its encoding is `0x21XX` (`movs r1, #imm8`), stored little-endian as **`XX 21`** — so the immediate is the byte at the instruction's **own** address, `0x1000026e`. Change `0x32` (50) to `0x63` (99). + +> **This is the opposite byte from the Week 7 `movw` patch.** For a 16-bit `movs`, the immediate is the first byte. For the 32-bit `movw`, the low immediate byte was the *third* byte. Always decode the instruction before you decide which byte to touch. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x1000026e` | `32` | `63` | `movs r1, #50` -> `#99`, prints `arithmetic_operator: 99` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Toggle the lock off so editing is enabled. +3. Go to `0x1000026e` and change the byte `32` to `63`. +4. Return to the linear view, right-click the function -> `Reanalyze`. + +**Option B — Python console:** + +```python +bv.write(0x1000026e, b"\x63") +print(hex(bv.read(0x1000026e, 1)[0])) # -> 0x63 +``` + +After reanalysis the instruction reads `movs r1, #99`. + +### Step 18b: Patch 2 — change the DHT11 scale from `0.1f` to `5.0f` + +The DHT11 driver converts the integer and decimal bytes to a float and scales the decimal part: + +``` +humidity = data[0] + data[1] * 0.1f +temperature = data[2] + data[3] * 0.1f +``` + +`dht11_read` computes both with a fused multiply-add against a single `0.1f` constant. Look at the end of `dht11_read`: + +```asm +100003ee: vmov s15, r6 +100003f2: vcvt.f32.s32 s12, s15 +100003f6: vmov s15, r1 +100003fa: vcvt.f32.s32 s14, s15 +100003fe: vmov s15, r0 +10000402: vcvt.f32.s32 s13, s15 +10000406: vmov s15, r2 +1000040a: vldr s11, [pc, #44] @ 10000438 +1000040e: vcvt.f32.s32 s15, s15 +10000412: movs r0, #1 +10000414: vfma.f32 s14, s12, s11 +10000418: vfma.f32 s15, s13, s11 +1000041c: vstr s14, [r5] +10000420: vstr s15, [fp] +``` + +The constant `s11` is loaded by the `vldr s11, [pc, #44]` at `0x1000040a`, which reads the literal-pool word at `0x10000438`. That word is `0x3dcccccd` (float `0.1`), stored little-endian as `cd cc cc 3d`. Change it to `0x40a00000` (float `5.0`), bytes `00 00 a0 40`: + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x10000438` | `cd cc cc 3d` | `00 00 a0 40` | `0.1f` -> `5.0f`; the humidity/temperature decimal parts read ~50x larger | + +``` ++-----------------------------------------------------------------+ +| IEEE-754 little-endian change | +| | +| 0.1f = 0x3dcccccd -> bytes cd cc cc 3d | +| 5.0f = 0x40a00000 -> bytes 00 00 a0 40 | +| | +| humidity = int + (decimal * 0.1f) becomes | +| humidity = int + (decimal * 5.0f) | +| | ++-----------------------------------------------------------------+ +``` + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x10000438` and change `cd cc cc 3d` to `00 00 a0 40`. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000438, bytes.fromhex("0000a040")) +print(bv.read(0x10000438, 4).hex()) # -> 0000a040 +``` + +> **The scale is applied to both humidity and temperature.** The two `vfma.f32` instructions both read `s11`, so patching the one constant changes both readings, not just temperature. + +### Step 18c: Patch 3 — rename the printed label + +The string `"arithmetic_operator: %d\r\n"` starts at `0x100038e8`. Its first 26 bytes are: + +``` +61 72 69 74 68 6d 65 74 69 63 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 + a r i t h m e t i c _ o p e r a t o r : % d \r \n \0 +``` + +We replace it with `"hacked_operator: %d\r\n\0"`, which is **four bytes shorter**, and pad the tail with NULs: + +``` +68 61 63 6b 65 64 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 00 00 00 00 + h a c k e d _ o p e r a t o r : % d \r \n \0 +``` + +The `\0` at offset 21 terminates the string, so `printf` stops there and the four padding bytes are never read. The next format string (`"increment_operator: …"`) begins at `0x10003904`, which is 28 bytes past `0x100038e8`, so our 26-byte write cannot reach it. + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001a` | `0x100038e8` | `61 72 69 74 68 6d 65 74 69 63 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00` | `68 61 63 6b 65 64 5f 6f 70 65 72 61 74 6f 72 3a 20 25 64 0d 0a 00 00 00 00 00` | prints `hacked_operator:` instead of `arithmetic_operator:` | + +**Option A — Hex view:** + +1. Switch to the **Hex** view (`View -> Hex`). +2. Go to `0x100038e8` and replace the 26 bytes above. +3. Return to the linear view and reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100038e8, b"hacked_operator: %d\r\n\x00\x00\x00\x00") +print(bv.read(0x100038e8, 26)) # -> b'hacked_operator: %d\r\n\x00\x00\x00\x00' +``` + +> **Keep the NUL.** `printf` walks the format string until it hits `\0`. If you omit it, the printer runs on into the padding and then into the next string, producing garbage. The four padding bytes guarantee the terminator. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x001a_operators", "build"), "0x001a_operators-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 17484 /.../build/0x001a_operators-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base IDA loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x444c` = 17484). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. +- Reading `seg.start` for `seg.data_length` bytes therefore grabs exactly the image. + +Two gotchas this avoids: + +- **No relative path.** IDA's Python console runs with a read-only working directory (inside the app bundle), so `open("0x001a_operators-h.bin", "wb")` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/` — no machine-specific path and no database needed. +- **Read the image, not the whole view.** `bv.read(bv.start, bv.length)` spans the entire mapped range, which is not the image. The segment's `data_length` is the image size. + +A different size means you exported a partial view. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x001a_operators-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x001a_operators-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the IDA console** — it is a normal Python interpreter, so you never have to leave the app. `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x001a_operators", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x001a_operators-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` +> +> This writes `hacked.uf2` next to the `.bin`, ready to drag onto the Pico. + +## Static stopping point + +The patched image has been exported and converted to UF2. This IDA guide ends at static verification; it does not connect to, flash, or debug a live target. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **AAPCS** | ARM Architecture Procedure Call Standard — `r0`-`r3` for the first four arguments, `r0` for the return value | +| **Arithmetic operator** | C operators for math (`+`, `-`, `*`, `/`, `%`); here `x * y` folds to `#50` | +| **Assignment operator** | Compound assignment (`+=`, `-=`, …); here `x += 5` folds to `#10` | +| **Bitwise operator** | Operators on individual bits (`<<`, `>>`, `&`, `\|`, `^`); here `x << 1` folds to `#10` | +| **`.bss`** | Section for uninitialized (or zero-initialized) static/global variables; `dht_pin` lives here | +| **`.data`** | Section for initialized static/global variables; copied from flash to SRAM at boot | +| **DHT11** | Low-cost single-wire digital humidity and temperature sensor | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **Fused multiply-add** | `vfma.f32 Sd, Sn, Sm` computes `Sd = Sd + (Sn * Sm)` in one operation | +| **Immediate value** | A constant embedded directly in an instruction, not fetched from memory | +| **Increment operator** | `x++` (post) or `++x` (pre); here `x++` returns the old value, `5` | +| **IEEE-754** | Standard for floating-point representation; `0.1f` is `0x3dcccccd` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **Logical operator** | Operators combining conditions (`&&`, `\|\|`, `!`); here `false` | +| **`movs`** | 16-bit Thumb move that loads an 8-bit immediate (0-255); immediate is the first byte | +| **`movw`** | 32-bit Thumb-2 "move wide" that loads a 16-bit immediate; low imm8 is the third byte | +| **PCF8574** | An I2C I/O expander; not used this week (that was the LCD, Week 7) | +| **Relational operator** | Comparison operators (`<`, `>`, `==`, `!=`); here `5 > 10` is `false` | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SIO** | Single-cycle I/O block; `gpio_set_dir` / `gpio_put` write it with `mcrr`, `gpio_get` reads it | +| **SVD** | System View Description file — register names for a peripheral; the RP2350 one is at **`WEEK04/rp2350.svd`** | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **TIMER0** | RP2350 timer block at `0x400b0000`; `time_us_32` reads its `TIMERAWL` register (`+0x28`) | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions.c` symbols), then patch the bytes — the `movs` immediate (`0x32 -> 0x63`), the DHT11 float word (`0.1f -> 5.0f`), and the format string (`arithmetic_operator:` -> `hacked_operator:`) — and export the patched artifact. diff --git a/WEEK09/WEEK09-IDA.pdf b/WEEK09/WEEK09-IDA.pdf new file mode 100644 index 0000000..10d204f Binary files /dev/null and b/WEEK09/WEEK09-IDA.pdf differ diff --git a/WEEK09/WEEK09-SLIDES.pdf b/WEEK09/WEEK09-SLIDES.pdf new file mode 100644 index 0000000..c6593ec Binary files /dev/null and b/WEEK09/WEEK09-SLIDES.pdf differ diff --git a/WEEK09/WEEK09.md b/WEEK09/WEEK09.md new file mode 100644 index 0000000..a3ac362 --- /dev/null +++ b/WEEK09/WEEK09.md @@ -0,0 +1,1230 @@ +# Week 9: Operators in Embedded Systems: Debugging and Hacking Operators w/ DHT11 Temperature & Humidity Sensor Single-Wire Protocol Basics. + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand all six types of C operators (arithmetic, increment, relational, logical, bitwise, assignment) +- Know how the DHT11 temperature and humidity sensor communicates with the Pico 2 +- Understand how post-increment operators affect variable values +- Navigate to the Reset_Handler and main function in stripped binaries +- Identify function arguments by analyzing register values in Ghidra +- Understand IEEE-754 floating-point representation +- Hack floating-point constants to manipulate sensor readings + +--- + +## Part 1: Understanding C Operators + +### What Are Operators? + +**Operators** are symbols that tell the compiler to perform specific mathematical, logical, or data manipulation operations. Think of them as the "verbs" of programming - they describe actions to perform on data. + +### The Six Types of Operators + +| Type | Example | What It Does | +| -------------- | -------------------- | ----------------------------------- | +| **Arithmetic** | `x * y` | Math operations (+, -, *, /, %) | +| **Increment** | `x++` or `++x` | Increase/decrease by 1 | +| **Relational** | `x > y` | Compare values (returns true/false) | +| **Logical** | `(x > y) && (y > x)` | Combine conditions (AND, OR, NOT) | +| **Bitwise** | `x << 1` | Manipulate individual bits | +| **Assignment** | `x += 5` | Assign and modify values | + +--- + +## Part 2: Arithmetic Operators + +### Basic Math in C + +Arithmetic operators perform mathematical calculations: + +```c +int x = 5; +int y = 10; +int result = x * y; // result = 50 +``` + +``` ++-----------------------------------------------------------------+ +| Arithmetic Operators | +| | +| Operator Example Result Description | +| ------------------------------------------------------------- | +| + 5 + 10 15 Addition | +| - 10 - 5 5 Subtraction | +| * 5 * 10 50 Multiplication | +| / 10 / 5 2 Division | +| % 10 % 3 1 Modulus (remainder) | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 3: Increment and Decrement Operators + +### Pre-Increment vs Post-Increment + +This is where many beginners get confused! There are TWO ways to increment: + +```c +int x = 5; +int a = x++; // Post-increment: a = 5, then x becomes 6 +int b = ++x; // Pre-increment: x becomes 7, then b = 7 +``` + +**The Key Difference:** + +| Type | Syntax | When Value Changes | Example Result | +| ------------------ | ------ | --------------------- | -------------------- | +| **Post-increment** | `x++` | AFTER the expression | `a = x++` -> a=5, x=6 | +| **Pre-increment** | `++x` | BEFORE the expression | `b = ++x` -> x=7, b=7 | + +``` ++-----------------------------------------------------------------+ +| Post-Increment (x++) | +| | +| int x = 5; | +| int result = x++; | +| | +| Step 1: result = x (result gets 5) | +| Step 2: x = x + 1 (x becomes 6) | +| | +| Final: result = 5, x = 6 | +| | +| Think of it as: "Use first, THEN increment" | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 4: Relational Operators + +### Comparing Values + +Relational operators compare two values and return `true` (1) or `false` (0): + +```c +int x = 6; +int y = 10; +bool result = (x > y); // false, because 6 is NOT greater than 10 +``` + +``` ++-----------------------------------------------------------------+ +| Relational Operators | +| | +| Operator Example Result Description | +| ------------------------------------------------------------- | +| > 6 > 10 false Greater than | +| < 6 < 10 true Less than | +| >= 6 >= 6 true Greater than or equal | +| <= 6 <= 10 true Less than or equal | +| == 6 == 10 false Equal to | +| != 6 != 10 true Not equal to | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 5: Logical Operators + +### Combining Conditions + +Logical operators combine multiple conditions: + +```c +int x = 6; +int y = 10; +bool result = (x > y) && (y > x); // false AND true = false +``` + +``` ++-----------------------------------------------------------------+ +| Logical Operators | +| | +| Operator Name Example Result | +| ------------------------------------------------------------- | +| && AND true && true true | +| && AND true && false false | +| || OR true || false true | +| || OR false || false false | +| ! NOT !true false | +| | +| Truth Table for AND (&&): | +| +-------+-------+--------+ | +| | A | B | A && B | | +| +-------+-------+--------+ | +| | false | false | false | | +| | false | true | false | | +| | true | false | false | | +| | true | true | true | | +| +-------+-------+--------+ | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 6: Bitwise Operators + +### Manipulating Individual Bits + +Bitwise operators work on the binary representation of numbers: + +```c +int x = 6; // Binary: 0b00000110 +int result = x << 1; // Shift left by 1: 0b00001100 = 12 +``` + +``` ++-----------------------------------------------------------------+ +| Bitwise Left Shift (<<) | +| | +| x = 6 = 0b00000110 | +| | +| x << 1 means "shift all bits LEFT by 1 position" | +| | +| Before: 0 0 0 0 0 1 1 0 (6) | +| < < < < < < < < | +| After: 0 0 0 0 1 1 0 0 (12) | +| | +| Each left shift DOUBLES the value! | +| 6 << 1 = 12 (same as 6 * 2) | +| | ++-----------------------------------------------------------------+ +``` + +**Common Bitwise Operators:** + +| Operator | Name | Example | Result | +| -------- | ----------- | -------- | ------------------ | +| `<<` | Left shift | `6 << 1` | 12 (multiply by 2) | +| `>>` | Right shift | `6 >> 1` | 3 (divide by 2) | +| `&` | AND | `6 & 3` | 2 (bits in common) | +| `\|` | OR | `6 \| 3` | 7 (all set bits) | +| `^` | XOR | `6 ^ 3` | 5 (different bits) | +| `~` | NOT | `~6` | Inverts all bits | + +--- + +## Part 7: Assignment Operators + +### Shorthand for Math + Assign + +Assignment operators combine math with assignment: + +```c +int x = 6; +x += 5; // Same as: x = x + 5; Result: x = 11 +``` + +``` ++-----------------------------------------------------------------+ +| Compound Assignment Operators | +| | +| Operator Example Equivalent To Result (if x=6) | +| ------------------------------------------------------------- | +| += x += 5 x = x + 5 x = 11 | +| -= x -= 2 x = x - 2 x = 4 | +| *= x *= 3 x = x * 3 x = 18 | +| /= x /= 2 x = x / 2 x = 3 | +| %= x %= 4 x = x % 4 x = 2 | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 8: Understanding the DHT11 Sensor + +### What is the DHT11? + +The **DHT11** is a low-cost digital temperature and humidity sensor. It uses a single wire for communication (plus power and ground). + +``` ++-----------------------------------------------------------------+ +| DHT11 Pinout | +| | +| +-------------+ | +| | DHT11 | | +| | +-----+ | | +| | | | | | +| | | | | | +| | +-----+ | | +| | 1 2 3 4 | | +| +--+--+--+--+-+ | +| | | | | | +| VCC DATA NC GND | +| | +| Pin 1: VCC (3.3V or 5V) | +| Pin 2: DATA (connect to GPIO) | +| Pin 3: Not Connected | +| Pin 4: GND (Ground) | +| | ++-----------------------------------------------------------------+ +``` + +### DHT11 Specifications + +| Parameter | Range | Accuracy | +| --------------- | ------------ | -------- | +| **Humidity** | 20% - 90% RH | +/- 5% RH | +| **Temperature** | 0 deg C - 50 deg C | +/- 2 deg C | + +### How DHT11 Communication Works + +The DHT11 uses a custom one-wire protocol: + +1. **Host sends start signal** - Pull data line LOW for 18ms +2. **DHT11 responds** - Pulls line LOW for 80 us, then HIGH for 80 us +3. **Data transmission** - 40 bits sent (8 humidity int, 8 humidity decimal, 8 temp int, 8 temp decimal, 8 checksum) + +--- + +## Part 9: Understanding Pointers (Quick Review) + +### The & Operator (Address-Of) + +When you see `&variable`, it means "the memory address of variable": + +```c +float hum, temp; + +// Pass ADDRESSES to the function so it can modify our variables +if (dht11_read(&hum, &temp)) { + printf("Humidity: %.1f%%, Temperature: %.1f C\n", hum, temp); +} +``` + +``` ++-----------------------------------------------------------------+ +| Passing by Reference | +| | +| Stack Memory | +| +----------------------------+ | +| | Address 0x20000008: hum |<--- &hum (passed to function) | +| | Value: 51.0 | | +| +----------------------------+ | +| | Address 0x2000000C: temp |<--- &temp (passed to function) | +| | Value: 23.8 | | +| +----------------------------+ | +| | +| dht11_read() receives the ADDRESSES, so it can write | +| new values directly into hum and temp! | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 10: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. A Raspberry Pi Pico Debug Probe +3. Ghidra installed (for static analysis) +4. Python installed (for UF2 conversion) +5. A serial monitor (PuTTY, minicom, or screen) +6. A DHT11 temperature and humidity sensor +7. The sample project: `0x001a_operators` + +### Hardware Setup + +Connect your DHT11 like this: + +| DHT11 Pin | Pico 2 Pin | +| --------- | ---------- | +| VCC | 3.3V | +| DATA | GPIO 4 | +| GND | GND | + +``` ++-----------------------------------------------------------------+ +| DHT11 Wiring | +| | +| Pico 2 DHT11 Sensor | +| +----------+ +----------+ | +| | | | | | +| | GPIO 4 |---------- DATA ------>| DATA | | +| | | | | | +| | 3.3V |---------- VCC ------->| VCC | | +| | | | | | +| | GND |---------- GND ------->| GND | | +| | | | | | +| +----------+ +----------+ | +| | +| Note: Some DHT11 modules have a built-in pull-up resistor. | +| If yours doesn't, add a 10K resistor between DATA and VCC. | +| | ++-----------------------------------------------------------------+ +``` + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x001a_operators/ +| +-- build/ +| | +-- 0x001a_operators.uf2 +| | +-- 0x001a_operators.bin +| +-- main/ +| | +-- 0x001a_operators.c +| +-- dht11.h ++-- uf2conv.py +``` + +--- + +## Part 11: Hands-On Tutorial - The Operators Code + +### Step 1: Review the Source Code + +Let's examine the operators code: + +**File: `0x001a_operators.c`** + +```c +#include +#include "pico/stdlib.h" +#include "dht11.h" + +int main(void) { + stdio_init_all(); + + dht11_init(4); + + int x = 5; + int y = 10; + int arithmetic_operator = (x * y); + int increment_operator = x++; + bool relational_operator = (x > y); + bool logical_operator = (x > y) && (y > x); + int bitwise_operator = (x<<1); // x is now 6 because of x++ or 0b00000110 and (x<<1) is 0b00001100 or 12 + int assignment_operator = (x += 5); + + while (true) { + printf("arithmetic_operator: %d\r\n", arithmetic_operator); + printf("increment_operator: %d\r\n", increment_operator); + printf("relational_operator: %d\r\n", relational_operator); + printf("logical_operator: %d\r\n", logical_operator); + printf("bitwise_operator: %d\r\n", bitwise_operator); + printf("assignment_operator: %d\r\n", assignment_operator); + + float hum, temp; + if (dht11_read(&hum, &temp)) { + printf("Humidity: %.1f%%, Temperature: %.1f C\r\n", hum, temp); + } else { + printf("DHT11 read failed\r\n"); + } + + sleep_ms(2000); + } +} +``` + +### Step 2: Understand the Variable Flow + +Let's trace through what happens to `x`: + +``` ++-----------------------------------------------------------------+ +| Variable x Through the Program | +| | +| Line | x value | Result | +| ------------------+---------+--------------------------------- | +| int x = 5; | 5 | x initialized to 5 | +| x * y | 5 | arithmetic = 5 * 10 = 50 | +| x++ | 5->6 | increment = 5 (then x becomes 6) | +| x > y | 6 | relational = (6 > 10) = false | +| (x>y) && (y>x) | 6 | logical = false && true = false | +| x << 1 | 6 | bitwise = 6 << 1 = 12 | +| x += 5 | 6->11 | assignment = 6 + 5 = 11 | +| | ++-----------------------------------------------------------------+ +``` + +### Step 3: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x001a_operators.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 4: Verify It's Working + +Open your serial monitor (PuTTY at 115200 baud) and you should see: + +``` +arithmetic_operator: 50 +increment_operator: 5 +relational_operator: 0 +logical_operator: 0 +bitwise_operator: 12 +assignment_operator: 11 +Humidity: 51.0%, Temperature: 23.8 deg C +``` + +**Understanding the Output:** + +| Variable | Value | Explanation | +| ------------------- | ------ | --------------------------------------------- | +| arithmetic_operator | 50 | 5 * 10 = 50 | +| increment_operator | 5 | Post-increment returns value BEFORE increment | +| relational_operator | 0 | 6 > 10 is false (0) | +| logical_operator | 0 | false AND true = false (0) | +| bitwise_operator | 12 | 6 (0b0110) << 1 = 12 (0b1100) | +| assignment_operator | 11 | 6 + 5 = 11 | +| Humidity | 51.0% | Real reading from DHT11 | +| Temperature | 23.8 deg C | Real reading from DHT11 | + +--- + +## Part 12: Debugging with GDB + +### Step 5: Start OpenOCD (Terminal 1) + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +You should see output indicating OpenOCD connected successfully to your Pico 2 via the Debug Probe. + +### Step 6: Start GDB (Terminal 2) + +Open a **new terminal** and launch GDB with the binary: + +```cmd +arm-none-eabi-gdb build\0x001a_operators.elf +``` + +### Step 7: Connect to the Remote Target + +Inside GDB, type: + +``` +target extended-remote :3333 +``` + +This connects GDB to OpenOCD. + +### Step 8: Halt the Running Binary + +``` +monitor reset halt +``` + +This stops the Pico 2 so we can examine its state. + +### Step 9: Examine Main Function + +Let's examine the main function. Disassemble from the entry point: + +``` +x/60i 0x10000234 +``` + +You should see the operator calculations and function calls: + +``` + 0x10000234
: push {r4, r5, r6, r7, lr} + 0x10000236 : sub sp, #20 + 0x10000238 : bl 0x10003384 + 0x1000023c : movs r0, #4 + 0x1000023e : bl 0x100002d4 +... +``` + +### Step 10: Set a Breakpoint at Main + +``` +b *0x10000234 +c +``` + +### Step 11: Find the Operator Calculations + +The compiler likely optimized many of these calculations at compile time. Look for immediate values: + +``` +x/32i 0x10000240 +``` + +You may see values like: + +- `#0x32` (50) for arithmetic_operator +- `#0x5` (5) for increment_operator +- `#0x0` (0) for relational and logical operators +- `#0xc` (12) for bitwise_operator +- `#0xb` (11) for assignment_operator + +### Step 12: Examine Printf Arguments + +Set a breakpoint before the first printf and examine registers: + +```gdb +b *0x10000262 +c +i r r0 r1 +``` + +You should see: + +- `r0` = address of format string +- `r1` = value to print + +### Step 13: Examine the Format Strings + +```gdb +x/s 0x10003978 +``` + +Find the format strings and value for print: +```gdb +(gdb) x/s 0x10003978 +0x10003978: "Humidity: %.1f%%, Temperature: %.1fA°C\r\n" +(gdb) x/x 0x4037cccc +0x4037cccc: 0x00 +(gdb) x/x $r1 +0x4037cccc: 0x00 +... +``` + +### Step 14: Examine DHT11 Function Call + +Find where dht11_read is called: + +```gdb +(gdb) x/3i 0x1000029f +``` + +You'll see stack addresses being passed as arguments: +``` + 0x1000029f : add r1, sp, #12 + 0x100002a1 : add r0, sp, #8 + 0x100002a3 : bl 0x100002f4 +``` + +### Step 15: Watch the Float Values + +After dht11_read returns, examine the float values on the stack: + +```gdb +(gdb) x/2fw $sp+8 +0x20081fe0: 62 23.7999992 +``` + +This shows the humidity and temperature as floats. + +### Step 16: Step Through the Loop + +Continue execution and watch the values: + +```gdb +c +``` + +The program will loop, printing values to serial. + +--- + +## Part 13: Setting Up Ghidra for Analysis + +### Step 17: Start Ghidra + +Open a terminal and type: + +```cmd +ghidraRun +``` + +### Step 18: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x001a_operators` +5. Click **Finish** + +### Step 19: Import the Binary + +1. Open your file explorer +2. Navigate to the `0x001a_operators/build/` folder +3. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 20: Configure the Binary Format + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` +3. Click **OK** + +### Step 21: Analyze the Binary + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete. + +--- + +## Part 14: Finding the Reset_Handler + +### Step 22: Understand the Vector Table + +In ARM Cortex-M, the **vector table** is at the base of flash (0x10000000). The second entry (offset 4) contains the Reset_Handler address. + +``` ++-----------------------------------------------------------------+ +| ARM Vector Table at 0x10000000 | +| | +| Offset Contents Description | +| ------------------------------------------------------------- | +| 0x00 Initial SP value Stack pointer at reset | +| 0x04 Reset_Handler addr First code to execute | +| 0x08 NMI_Handler addr Non-maskable interrupt | +| 0x0C HardFault_Handler Hard fault handler | +| ... | +| | ++-----------------------------------------------------------------+ +``` + +### Step 23: Read the Reset_Handler Address + +1. Press `G` (Go to address) and type `10000004` +2. You'll see bytes like `5d 01 00 10` (your exact bytes may vary) + +**Important:** This is **little-endian**, so we need to reverse the byte order! + +``` ++-----------------------------------------------------------------+ +| Little-Endian Byte Order | +| | +| In memory: 5d 01 00 10 | +| Reversed: 10 00 01 5d | +| As hex: 0x1000015d | +| | +| But wait! ARM uses the THUMB bit! | +| The lowest bit indicates Thumb mode (always set for Cortex-M) | +| Real address: 0x1000015d - 1 = 0x1000015c | +| | ++-----------------------------------------------------------------+ +``` + +### Step 24: Navigate to Reset_Handler + +1. Press `G` and type `1000015c` (or your calculated address) +2. You might see undefined data - that's OK! + +### Step 25: Create the Reset_Handler Function + +If Ghidra didn't automatically recognize this as a function: + +1. Click on the address `0x1000015c` +2. Right-click and press `F` to create a function +3. Right-click -> **Edit Function Signature** +4. Change the name to `Reset_Handler` +5. Click **OK** + +### Step 26: Find Main from Reset_Handler + +The Reset_Handler typically calls three functions: + +``` ++-----------------------------------------------------------------+ +| Reset_Handler Flow (crt0.S) | +| | +| Reset_Handler: | +| 1. Call some_init() <-- Initialize hardware | +| 2. Call main() <-- THIS IS WHAT WE WANT! | +| 3. Call exit() <-- Never returns | +| | +| The MIDDLE function is main! | +| | ++-----------------------------------------------------------------+ +``` + +Look at the end of Reset_Handler for three function calls. The middle one is `main`! + +### Step 27: Navigate to Main + +1. Double-click on the middle function call (should be around `0x10000234`) +2. Right-click -> **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +--- + +## Part 15: Resolving Functions in Ghidra + +### Step 28: Resolve stdio_init_all + +The first function call in main is `stdio_init_all`: + +1. Find the call at approximately `0x10000238` +2. Double-click to navigate to the function +3. Right-click -> **Edit Function Signature** +4. Change to: `bool stdio_init_all(void)` +5. Click **OK** + +### Step 29: Resolve dht11_init + +Look for a function call where `r0` is loaded with `0x4`: + +```assembly +movs r0, #0x4 ; GPIO pin 4 +bl FUN_xxxxx ; dht11_init +``` + +**How do we know it's dht11_init?** + +- The argument `4` is the GPIO pin number +- We physically connected the DHT11 to GPIO 4! + +1. Right-click -> **Edit Function Signature** +2. Change to: `void dht11_init(uint pin)` +3. Click **OK** + +### Step 30: Resolve printf + +Look for repeated function calls with string addresses: + +1. Find a call like the one at `0x10000262` +2. Right-click -> **Edit Function Signature** +3. Change to: `int printf(char *format,...)` +4. Check the **Varargs** checkbox +5. Click **OK** + +### Step 31: Resolve sleep_ms + +Look for a function call where `r0` is loaded with `0x7d0` (2000 in decimal): + +```assembly +ldr r0, =0x7d0 ; 2000 milliseconds +bl FUN_xxxxx ; sleep_ms +``` + +1. Right-click -> **Edit Function Signature** +2. Change to: `void sleep_ms(uint ms)` +3. Click **OK** + +### Step 32: Resolve dht11_read + +This is trickier! Look for a function call with TWO address arguments: + +```assembly +add r1, sp, #0xc ; Address of temp on stack +add r0, sp, #0x8 ; Address of hum on stack +bl FUN_xxxxx ; dht11_read +``` + +**Understanding the stack offsets:** + +- `sp + 0x8` = address of `hum` variable +- `sp + 0xc` = address of `temp` variable +- These are `float` pointers passed to the function + +1. Right-click -> **Edit Function Signature** +2. Change to: `bool dht11_read(float *humidity, float *temperature)` +3. Click **OK** + +### Step 33: Resolve puts + +Look for a function call after the `if` statement that takes a single string argument: + +```assembly +ldr r0, ="DHT11 read failed" +bl FUN_xxxxx ; puts +``` + +1. Right-click -> **Edit Function Signature** +2. Change to: `int puts(char *s)` +3. Click **OK** + +--- + +## Part 16: Understanding IEEE-754 Floating-Point + +### What is IEEE-754? + +IEEE-754 is the standard for representing decimal numbers in binary. A 32-bit float is divided into three parts: + +``` ++-----------------------------------------------------------------+ +| IEEE-754 Single Precision (32-bit) Float | +| | +| +-----+-------------+---------------------------------------+ | +| | S | Exponent | Mantissa (Fraction) | | +| | 1 | 8 bits | 23 bits | | +| +-----+-------------+---------------------------------------+ | +| bit bits bits | +| 31 30-23 22-0 | +| | +| Value = (-1)^S * (1 + Mantissa) * 2^(Exponent - 127) | +| | ++-----------------------------------------------------------------+ +``` + +### Example: Decoding 0x3dcccccc (0.1f) + +Let's decode the bytes `cc cc cc 3d`: + +1. **Reverse for little-endian:** `0x3dcccccc` +2. **Convert to binary:** `00111101 11001100 11001100 11001100` +3. **Extract fields:** + - Sign (bit 31): `0` (positive) + - Exponent (bits 30-23): `01111011` = 123 + - Mantissa (bits 22-0): `10011001100110011001100` + +4. **Calculate value:** + - Actual exponent: 123 - 127 = -4 + - Mantissa value: 1.6 (approximately) + - Final value: 1.6 * 2^(-4) ~= 0.1 + +### Example: Encoding -1.0f as 0xbf800000 + +For the number -1.0: + +1. **Sign:** 1 (negative) +2. **Exponent:** 127 (for 2^0 = 1) +3. **Mantissa:** 0 (because value is exactly 1.0) + +Binary: `1 01111111 00000000000000000000000` +Hex: `0xbf800000` +Little-endian: `00 00 80 bf` + +### Python for Float Conversion + +```python +import struct + +# Decode bytes to float +bytes_data = bytes.fromhex('cdcccc3d') +value = struct.unpack(' **Bytes** +2. A new panel appears showing raw hex bytes + +### Step 38: Enable Editing + +Look for the pencil icon in the Bytes window toolbar and click it to enable editing mode. + +### Step 39: Hack the Scaling Constant + +Let's change the temperature scaling to add 25% more! + +1. Press `G` and go to address `1000042c` +2. Current bytes: `cd cc cc 3d` (0.1f in little-endian) +3. Change to: `00 00 a0 40` (5.0f in little-endian) + +This changes the multiplier from 0.1 to 5.0, which will dramatically increase the temperature reading! + +### Step 40: Verify the Change + +Use Python to verify what we changed: + +```python +import struct + +# Original value +original = struct.unpack('>> import struct +>>> +>>> # Original value +>>> original = struct.unpack('>> print(f"Original: {original}") # 0.1 +Original: 0.10000000149011612 +>>> +>>> # New value +>>> new = struct.unpack('>> print(f"New: {new}") # 5.0 +New: 5.0 +``` + +--- + +## Part 19: Exporting and Testing + +### Step 41: Export the Patched Binary + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. Navigate to your build directory +4. Name the file `0x001a_operators-h.bin` +5. Click **OK** + +### Step 42: Convert to UF2 Format + +Open a terminal and run: + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x001a_operators +python ..\uf2conv.py build\0x001a_operators-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 43: Flash and Test + +1. Hold BOOTSEL and plug in your Pico 2 +2. Drag and drop `hacked.uf2` onto the RPI-RP2 drive +3. Open your serial monitor + +You should see dramatically increased temperature readings! + +``` +Humidity: 60.0%, Temperature: 63.0°C +arithmetic_operator: 50 +increment_operator: 5 +relational_operator: 0 +logical_operator: 0 +bitwise_operator: 12 +assignment_operator: 11 +``` + +--- + +## Part 20: Summary and Review + +### What We Accomplished + +1. **Learned all six C operator types** - Arithmetic, increment, relational, logical, bitwise, assignment +2. **Understood post-increment behavior** - `x++` returns value BEFORE incrementing +3. **Learned about the DHT11 sensor** - One-wire protocol for temperature/humidity +4. **Found Reset_Handler from vector table** - Offset 4 contains the address +5. **Identified functions by their arguments** - GPIO pin 4, sleep 2000ms, etc. +6. **Understood IEEE-754 floating-point** - How computers represent decimals +7. **Hacked floating-point constants** - Changed 0.1f to other values + +### The Hacking Workflow + +``` ++-----------------------------------------------------------------+ +| Binary Hacking Workflow | +| | +| 1. Analyze the binary in Ghidra | +| 2. Identify target values/instructions | +| 3. Calculate file offsets from memory addresses | +| 4. Determine replacement bytes | +| 5. Patch the binary (manual in hex editor) | +| 6. Export and convert to UF2 | +| 7. Flash and test | +| | ++-----------------------------------------------------------------+ +``` + +### Key Memory Addresses + +| Memory Address | File Offset | Description | +| -------------- | ----------- | ------------------------------- | +| `0x10000000` | `0x000` | Vector table start | +| `0x10000004` | `0x004` | Reset_Handler address | +| `0x10000234` | `0x234` | main() function (approximately) | +| `0x10000410` | `0x410` | Humidity vfma instruction | +| `0x10000414` | `0x414` | Temperature vfma instruction | +| `0x1000042C` | `0x42C` | 0.1f scaling constant | + +--- + +--- + +## Key Takeaways + +1. **Post-increment returns the OLD value** - `x++` gives you x, THEN adds 1 + +2. **Bitwise left shift multiplies by 2** - `x << 1` is the same as `x * 2` + +3. **Vector table points to Reset_Handler** - Offset 4 from flash base + +4. **Arguments go in r0-r3** - Follow them to identify functions + +5. **IEEE-754 is how floats are stored** - Sign, exponent, mantissa + +6. **File offset = Memory address - Base** - 0x10000410 -> offset 0x410 + +7. **Little-endian reverses byte order** - 0x3dcccccc stored as cc cc cc 3d + +8. **Incremental testing is essential** - Test each change before the next + +10. **Binary patching has real consequences** - Sensor spoofing can be dangerous! + +--- + +## Glossary + +| Term | Definition | +| ------------------ | --------------------------------------------------- | +| **Arithmetic Op** | Operators for math (+, -, *, /, %) | +| **Assignment Op** | Operators that assign and modify (+=, -=, etc.) | +| **Bitwise Op** | Operators on individual bits (<<, >>, &, \|, ^) | +| **DHT11** | Digital humidity and temperature sensor | +| **Exponent** | Power of 2 in IEEE-754 float representation | +| **IEEE-754** | Standard for floating-point number representation | +| **Increment Op** | Operators that add/subtract 1 (++, --) | +| **Little-Endian** | Byte order where least significant byte comes first | +| **Logical Op** | Operators combining conditions (&&, \|\|, !) | +| **Mantissa** | Fractional part of IEEE-754 float | +| **Post-Increment** | `x++` - returns value, then increments | +| **Pre-Increment** | `++x` - increments, then returns value | +| **Relational Op** | Operators comparing values (<, >, ==, !=) | +| **Reset_Handler** | First function executed after CPU reset | +| **Thumb Bit** | Lowest bit of ARM address indicating Thumb mode | +| **Vector Table** | Table of exception/interrupt handler addresses | +| **vfma.f32** | ARM floating-point fused multiply-add instruction | +| **vadd.f32** | ARM floating-point add instruction | + +--- + +## Additional Resources + +### IEEE-754 Float Quick Reference + +| Value | Hex Encoding | Bytes (LE) | +| ----- | ------------ | ----------- | +| 0.1 | 0x3dcccccd | cd cc cc 3d | +| 1.0 | 0x3f800000 | 00 00 80 3f | +| -1.0 | 0xbf800000 | 00 00 80 bf | +| 2.0 | 0x40000000 | 00 00 00 40 | +| -2.0 | 0xc0000000 | 00 00 00 c0 | +| 5.0 | 0x40a00000 | 00 00 a0 40 | +| 10.0 | 0x41200000 | 00 00 20 41 | + +### ARM Floating-Point Instructions + +| Instruction | Description | +| --------------------- | ---------------------------------------- | +| `vfma.f32 Sd, Sn, Sm` | Sd = Sd + (Sn * Sm) (fused multiply-add) | +| `vadd.f32 Sd, Sn, Sm` | Sd = Sn + Sm | +| `vsub.f32 Sd, Sn, Sm` | Sd = Sn - Sm | +| `vmul.f32 Sd, Sn, Sm` | Sd = Sn * Sm | +| `vldr.f32 Sd, [addr]` | Load float from memory | +| `vstr.f32 Sd, [addr]` | Store float to memory | + +--- + +## Real-World Implications + +### Why This Matters + +Imagine a scenario where temperature sensors control critical systems: + +- **Industrial processes** - Chemical reactions that must stay within temperature ranges +- **Medical equipment** - Refrigerators storing vaccines or organs +- **Nuclear facilities** - Cooling systems for reactors +- **HVAC systems** - Climate control in sensitive environments + +By manipulating sensor readings, an attacker could: + +- Cause equipment to overheat while displaying normal temperatures +- Trigger false alarms +- Bypass safety interlocks +- Cause physical damage or safety hazards + +### Defensive Measures + +1. **Redundant sensors** - Multiple sensors with consistency checks +2. **Physical security** - Prevent access to programming interfaces +3. **Anomaly detection** - Alert on sudden reading changes + +--- + +**Remember:** The techniques you learned today can be used for good (security research, debugging) or bad (sabotage, fraud). Always use your skills ethically and legally. Understanding how attacks work helps us build more secure systems! + +Happy hacking! diff --git a/WEEK09/WEEK09.pdf b/WEEK09/WEEK09.pdf new file mode 100644 index 0000000..205b448 Binary files /dev/null and b/WEEK09/WEEK09.pdf differ diff --git a/WEEK09/slides/WEEK09-IMG00.svg b/WEEK09/slides/WEEK09-IMG00.svg new file mode 100644 index 0000000..3aadd8e --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 09 + + +Operators in Embedded Systems: +Debugging and Hacking Operators +w/ DHT11 Sensor Single-Wire Protocol + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK09/slides/WEEK09-IMG01.svg b/WEEK09/slides/WEEK09-IMG01.svg new file mode 100644 index 0000000..b431706 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG01.svg @@ -0,0 +1,74 @@ + + + + +C Operators Overview +Six Types of Operators in C + + + +Arithmetic + ++ - * / % +Math operations +5 * 10 = 50 + + +Increment + +x++ ++x x-- +Add/subtract by 1 +x++ returns old val + + +Relational + +> < >= <= == != +Compare values +(6 > 10) = false + + + +Logical + +&& || ! +Combine conditions +AND, OR, NOT + + +Bitwise + +<< >> & | ^ ~ +Manipulate bits +6 << 1 = 12 + + +Assignment + ++= -= *= /= +Assign and modify +x += 5 (x=x+5) + + + +This Week's Program +0x001a_operators.c demonstrates all 6 types +DHT11 temperature/humidity sensor + operator calculations + + + +KEY: +Compiler pre-computes constant expressions +In the binary, most operators become immediate values + \ No newline at end of file diff --git a/WEEK09/slides/WEEK09-IMG02.svg b/WEEK09/slides/WEEK09-IMG02.svg new file mode 100644 index 0000000..3ba9f91 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG02.svg @@ -0,0 +1,75 @@ + + + + +Arithmetic & Increment +Math Operations and Post/Pre Increment + + + +Arithmetic Operators + ++ +5 + 10 = 15 +Addition +- +10 - 5 = 5 +Subtraction +* +5 * 10 = 50 +Multiplication +/ +10 / 5 = 2 +Division +% +10 % 3 = 1 +Modulus + + + +Post vs Pre Increment + + +Post: x++ +Use value THEN increment +a = x++ --> a=5, x=6 + + +Pre: ++x +Increment THEN use value +b = ++x --> x=7, b=7 + + + +Post-Increment Step by Step + + +int x = 5; +int result = x++; + +Step 1: result = x +result gets 5 +Step 2: x = x + 1 +x becomes 6 + +Final: result = 5 +x = 6 +"Use first, THEN increment" + + + +In our code: +int increment_operator = x++; +x was 5, so increment_operator = 5, then x becomes 6 + \ No newline at end of file diff --git a/WEEK09/slides/WEEK09-IMG03.svg b/WEEK09/slides/WEEK09-IMG03.svg new file mode 100644 index 0000000..1244936 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG03.svg @@ -0,0 +1,95 @@ + + + + +Relational & Logical +Comparing Values and Combining Conditions + + + +Relational Operators +Compare two values --> true (1) or false (0) + +> +6 > 10 +false +Greater than +< +6 < 10 +true +Less than +>= +6 >= 6 +true +Greater/equal +<= +6 <= 10 +true +Less or equal +== +6 == 10 +false +Equal to +!= +6 != 10 +true +Not equal + + + +Logical Operators +Combine conditions into one result + +&& +AND -- both must be true +|| +OR -- at least one true +! +NOT -- inverts result + + +AND Truth Table + +A +B +A && B +false +false +false +false +true +false +true +false +false +true +true +true + + + +In Our Code (x=6, y=10) + +bool relational = (x > y); +(6 > 10) = false = 0 +bool logical = (x>y) && (y>x); +false && true = false = 0 + + + +In the binary: +Both compile to immediate #0 +Compiler pre-computes: constants are known at compile time +Result 0 = false, Result 1 = true + \ No newline at end of file diff --git a/WEEK09/slides/WEEK09-IMG04.svg b/WEEK09/slides/WEEK09-IMG04.svg new file mode 100644 index 0000000..02cb827 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG04.svg @@ -0,0 +1,89 @@ + + + + +Bitwise & Assignment +Bit Manipulation and Compound Assignment + + + +Bitwise Operators + +<< +6 << 1 = 12 +Left shift +>> +6 >> 1 = 3 +Right shift +& +6 & 3 = 2 +AND +| +6 | 3 = 7 +OR +^ +6 ^ 3 = 5 +XOR +~ +~6 +NOT (invert) + + +Left shift = multiply by 2 + +0 0 0 0 0 1 1 0 += 6 +0 0 0 0 1 1 0 0 += 12 + + + +Assignment Operators +Shorthand for math + assign + ++= +x += 5 +x = x + 5 +-= +x -= 2 +x = x - 2 +*= +x *= 3 +x = x * 3 +/= +x /= 2 +x = x / 2 +%= +x %= 4 +x = x % 4 + + +In our code (x=6 after x++): + +x += 5 --> 6 + 5 = 11 + + + +In Our Code (x=6, y=10) + +int bitwise = (x<<1); +6 << 1 = 12 (0b0110 --> 0b1100) + + + +Expected Output +bitwise_operator: 12 +assignment_operator: 11 +Both pre-computed by compiler as immediates + \ No newline at end of file diff --git a/WEEK09/slides/WEEK09-IMG05.svg b/WEEK09/slides/WEEK09-IMG05.svg new file mode 100644 index 0000000..4975302 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG05.svg @@ -0,0 +1,72 @@ + + + + +DHT11 Sensor +Single-Wire Temperature and Humidity + + + +DHT11 Pinout + + +DHT11 +1:VCC 2:DATA 3:NC 4:GND + +Humidity: 20-90% RH (+/-5%) +Temp: 0-50C (+/-2C) +Protocol: custom one-wire + + + +Wiring to Pico 2 + + +Pico + + +DHT11 + + + + +GPIO 4 = DATA +3.3V = VCC +GND = GND + + + +1. Host pulls LOW 18ms +2. DHT11 responds, sends 40 bits + + + +Source Code: 0x001a_operators.c + +int x = 5, y = 10; +int arithmetic = (x * y); +// 50 +int increment = x++; +// 5 (post) +bool relational = (x > y); +// false +bool logical = (x>y)&&(y>x); +// false +int bitwise = (x<<1); +// 12 +int assignment = (x += 5); +// 11 +float hum, temp; +dht11_read(&hum, &temp); + \ No newline at end of file diff --git a/WEEK09/slides/WEEK09-IMG06.svg b/WEEK09/slides/WEEK09-IMG06.svg new file mode 100644 index 0000000..ef11927 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG06.svg @@ -0,0 +1,75 @@ + + + + +Variable Flow +Tracing x Through Every Operator + + + +Tracing x Step-by-Step + + +Line +x +Result + + + +int x = 5, y = 10; +5 +x initialized to 5 + + +int arithmetic = (x * y); +5 +arithmetic = 50 + + +int increment = x++; +5-->6 +increment = 5 +use THEN increment + + +bool relational = (x > y); +6 +relational = false +6 > 10 is false + + +bool logical = (x>y)&&(y>x); +6 +logical = false +false AND true = false + + +int bitwise = (x<<1); +6 +bitwise = 12 +0b0110 << 1 = 0b1100 + + +int assignment = (x += 5); +6-->11 +assignment = 11 +6 + 5 = 11 + + + +DHT11 Output +Humidity: 51.0% +Temperature: 23.8C +dht11_read(&hum, &temp) -- passes addresses so function can write values + diff --git a/WEEK09/slides/WEEK09-IMG07.svg b/WEEK09/slides/WEEK09-IMG07.svg new file mode 100644 index 0000000..1e5d297 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG07.svg @@ -0,0 +1,77 @@ + + + + +Vector Table +Finding Reset_Handler and main() + + + +ARM Vector Table +Base address: 0x10000000 + +Offset +Contents +Purpose + + +0x00 +Initial SP +Stack ptr + +0x04 +Reset_Handler +Entry point + +0x08 +NMI_Handler +NMI + +0x0C +HardFault +Fault + + + +Decoding the Address + +At 0x10000004: +Bytes: 5d 01 00 10 + +Step 1: Reverse (little-endian) +10 00 01 5d = 0x1000015d + +Step 2: Remove Thumb bit +0x1000015d - 1 = 0x1000015c + + + +Reset_Handler --> main() + +Reset_Handler at 0x1000015c calls 3 functions: + + +Call 1: some_init() +Hardware initialization + +Call 2: main() +THIS IS WHAT WE WANT +Address: 0x10000234 + +Call 3: exit() +Never returns + +The MIDDLE function call is always main() +Navigate to 0x10000234 in Ghidra to find it + diff --git a/WEEK09/slides/WEEK09-IMG08.svg b/WEEK09/slides/WEEK09-IMG08.svg new file mode 100644 index 0000000..f520db0 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG08.svg @@ -0,0 +1,81 @@ + + + + +IEEE-754 Floats +How Computers Store Decimal Numbers + + + +32-bit Float Structure + + + +S +1 bit + + +Exponent +8 bits + + +Mantissa (Fraction) +23 bits + +Value = (-1)^S x (1 + Mantissa) x 2^(Exponent - 127) + + + +Example: Decoding 0.1f + +Little-endian bytes: +cd cc cc 3d + +Reversed (big-endian): +0x3dcccccd + +Sign: 0 +Exp: 01111011 = 123 +Mantissa: 1001100... + +Exp - 127 = -4, so value = 1.6 x 2^(-4) += 0.1 + + + +IEEE-754 Quick Reference + +Value +Hex +Bytes (LE) + + +0.1 +0x3dcccccd +cd cc cc 3d +1.0 +0x3f800000 +00 00 80 3f + +5.0 +0x40a00000 +00 00 a0 40 +10.0 +0x41200000 +00 00 20 41 + +-1.0 +0xbf800000 +00 00 80 bf + diff --git a/WEEK09/slides/WEEK09-IMG09.svg b/WEEK09/slides/WEEK09-IMG09.svg new file mode 100644 index 0000000..5c40649 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG09.svg @@ -0,0 +1,64 @@ + + + + +Hacking the Float +Changing the DHT11 Scaling Constant + + + +DHT11 Scaling Calculation +result = integer + (decimal x 0.1) +Example: temp = 23 + (8 x 0.1) = 23.8C +0.1f is our target! + + + +Key Offsets in Binary + +Offset +Bytes +Meaning + + +0x410 +a6 ee 25 7a +vfma.f32 s14,s12,s11 (humidity) + +0x414 +e6 ee a5 7a +vfma.f32 s15,s13,s11 (temp) + +0x42C +cd cc cc 3d +0.1f -- the scaling constant + + + +The Hack: 0.1f --> 5.0f + +At offset 0x42C, change: + + +Original: cd cc cc 3d +(0.1f) + + +Patched: 00 00 a0 40 +(5.0f) + +New result: 23 + (8 x 5.0) = 63.0C +Decimal part is now multiplied by 5.0 instead of 0.1 +Export .bin from Ghidra, convert to UF2, flash to Pico + diff --git a/WEEK09/slides/WEEK09-IMG10.svg b/WEEK09/slides/WEEK09-IMG10.svg new file mode 100644 index 0000000..9655865 --- /dev/null +++ b/WEEK09/slides/WEEK09-IMG10.svg @@ -0,0 +1,97 @@ + + + + +Operators & DHT11 Hacking +Operators, DHT11, IEEE-754, and Hacking + + + +6 Operator Types + +Arithmetic +x * y = 50 + +Increment +x++ returns 5, x becomes 6 + +Relational +(6 > 10) = false + +Logical +false && true = false + +Bitwise +6 << 1 = 12 + +Assignment +x += 5 = 11 + +Post-increment: use THEN increment + + + +Key Addresses + +0x10000000 +Vector table + +0x10000004 +Reset_Handler addr + +0x10000234 +main() + +0x10000410 +Humidity vfma + +0x10000414 +Temp vfma + +0x1000042C +0.1f constant (hack) + + + +IEEE-754 Format +S(1) + Exp(8) + Mantissa(23) +(-1)^S x (1+M) x 2^(E-127) +0.1f = 0x3dcccccd = cd cc cc 3d + + + +Hack Workflow +1. Analyze in Ghidra +2. Find float at 0x42C +3. Patch cd cc cc 3d + + + +Binary Hacking Steps + +Analyze +--> +Identify +--> +Offset +--> +Patch +--> +Export +--> +Test + +Project: 0x001a_operators +Source: 0x001a_operators.c with DHT11 sensor on GPIO 4 + diff --git a/WEEK10/0x001d_static-conditionals/.gitignore b/WEEK10/0x001d_static-conditionals/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK10/0x001d_static-conditionals/.vscode/c_cpp_properties.json b/WEEK10/0x001d_static-conditionals/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK10/0x001d_static-conditionals/.vscode/cmake-kits.json b/WEEK10/0x001d_static-conditionals/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK10/0x001d_static-conditionals/.vscode/extensions.json b/WEEK10/0x001d_static-conditionals/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK10/0x001d_static-conditionals/.vscode/launch.json b/WEEK10/0x001d_static-conditionals/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK10/0x001d_static-conditionals/.vscode/settings.json b/WEEK10/0x001d_static-conditionals/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK10/0x001d_static-conditionals/.vscode/tasks.json b/WEEK10/0x001d_static-conditionals/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK10/0x001d_static-conditionals/0x001d_static-conditionals.c b/WEEK10/0x001d_static-conditionals/0x001d_static-conditionals.c new file mode 100644 index 0000000..8ad9328 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/0x001d_static-conditionals.c @@ -0,0 +1,39 @@ +#include +#include "pico/stdlib.h" +#include "servo.h" + +#define SERVO_GPIO 6 + +int main(void) { + stdio_init_all(); + + int choice = 1; + + servo_init(SERVO_GPIO); + + while (true) { + if (choice == 1) { + printf("1\r\n"); + } else if (choice == 2) { + printf("2\r\n"); + } else { + printf("?\r\n"); + } + + switch (choice) { + case 1: + printf("one\r\n"); + break; + case 2: + printf("two\r\n"); + break; + default: + printf("??\r\n"); + } + + servo_set_angle(0.0f); + sleep_ms(500); + servo_set_angle(180.0f); + sleep_ms(500); + } +} \ No newline at end of file diff --git a/WEEK10/0x001d_static-conditionals/CMakeLists.txt b/WEEK10/0x001d_static-conditionals/CMakeLists.txt new file mode 100644 index 0000000..7b03b00 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/CMakeLists.txt @@ -0,0 +1,59 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x001d_static-conditionals C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x001d_static-conditionals 0x001d_static-conditionals.c servo.c) + +pico_set_program_name(0x001d_static-conditionals "0x001d_static-conditionals") +pico_set_program_version(0x001d_static-conditionals "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x001d_static-conditionals 1) +pico_enable_stdio_usb(0x001d_static-conditionals 0) + +# Add the standard library to the build +target_link_libraries(0x001d_static-conditionals + pico_stdlib + hardware_pwm + hardware_clocks) + +# Add the standard include files to the build +target_include_directories(0x001d_static-conditionals PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x001d_static-conditionals) + diff --git a/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.bin b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.bin new file mode 100755 index 0000000..d19bd1d Binary files /dev/null and b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.bin differ diff --git a/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.dis b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.dis new file mode 100644 index 0000000..6c0e9f4 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.dis @@ -0,0 +1,3069 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x001d_static-conditionals/build/0x001d_static-conditionals.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00001c5c 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000154 10001c5c 10001c5c 00002c5c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10001db0 10001db0 00002db0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10001db8 10001db8 00002db8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00004000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00003f94 2**0 + CONTENTS + 6 .data 0000019c 20000110 10001de4 00003110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 200002ac 200002ac 00003f94 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 200002ac 200002ac 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00000230 200002b0 10001f80 000042b0 2**3 + ALLOC + 10 .heap 00000800 200004e0 10001f80 000044e0 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00003f94 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00003f94 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00004000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10001f80 10001f80 00003f80 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00003f94 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00003fc8 2**0 + CONTENTS, READONLY + 17 .debug_info 00021368 00000000 00000000 0000400d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 000058f3 00000000 00000000 00025375 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 00010699 00000000 00000000 0002ac68 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000b20 00000000 00000000 0003b308 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 0000307c 00000000 00000000 0003be28 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 00015e57 00000000 00000000 0003eea4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005a2e 00000000 00000000 00054cfb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f24 00000000 00000000 0005a72c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 00000188 00000000 00000000 0005c650 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x001d_static-conditionals/build/0x001d_static-conditionals.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10001db8 .word 0x10001db8 +1000012c: 10001de4 .word 0x10001de4 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00001e48 .word 0x00001e48 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10001de4 .word 0x10001de4 +100001a4: 20000110 .word 0x20000110 +100001a8: 200002ac .word 0x200002ac +100001ac: 10001f80 .word 0x10001f80 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10001f80 .word 0x10001f80 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 200002ac .word 0x200002ac +100001d4: 200004e0 .word 0x200004e0 +100001d8: 1000160d .word 0x1000160d +100001dc: 10000235 .word 0x10000235 +100001e0: 10001605 .word 0x10001605 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 200002ac .word 0x200002ac +10000208: 200002ac .word 0x200002ac +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000490 .word 0x20000490 +10000230: 10001c5c .word 0x10001c5c + +10000234
: +10000234: b538 push {r3, r4, r5, lr} +10000236: f001 fae1 bl 100017fc +1000023a: 2006 movs r0, #6 +1000023c: f000 f81e bl 1000027c +10000240: 2500 movs r5, #0 +10000242: 4c0b ldr r4, [pc, #44] @ (10000270 ) +10000244: 480b ldr r0, [pc, #44] @ (10000274 ) +10000246: f001 fb21 bl 1000188c <__wrap_puts> +1000024a: 480b ldr r0, [pc, #44] @ (10000278 ) +1000024c: f001 fb1e bl 1000188c <__wrap_puts> +10000250: 4628 mov r0, r5 +10000252: f000 f861 bl 10000318 +10000256: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000025a: f000 fde5 bl 10000e28 +1000025e: 4620 mov r0, r4 +10000260: f000 f85a bl 10000318 +10000264: f44f 70fa mov.w r0, #500 @ 0x1f4 +10000268: f000 fdde bl 10000e28 +1000026c: e7ea b.n 10000244 +1000026e: bf00 nop +10000270: 43340000 .word 0x43340000 +10000274: 10001c5c .word 0x10001c5c +10000278: 10001c64 .word 0x10001c64 + +1000027c : +1000027c: b570 push {r4, r5, r6, lr} +1000027e: 4c20 ldr r4, [pc, #128] @ (10000300 ) +10000280: 2104 movs r1, #4 +10000282: 7020 strb r0, [r4, #0] +10000284: f000 f8a8 bl 100003d8 +10000288: 7823 ldrb r3, [r4, #0] +1000028a: 491e ldr r1, [pc, #120] @ (10000304 ) +1000028c: 085a lsrs r2, r3, #1 +1000028e: 2b1f cmp r3, #31 +10000290: bf88 it hi +10000292: f002 0203 andhi.w r2, r2, #3 +10000296: 4d1c ldr r5, [pc, #112] @ (10000308 ) +10000298: bf94 ite ls +1000029a: f002 0207 andls.w r2, r2, #7 +1000029e: 3208 addhi r2, #8 +100002a0: f003 0301 and.w r3, r3, #1 +100002a4: 2005 movs r0, #5 +100002a6: 600b str r3, [r1, #0] +100002a8: 602a str r2, [r5, #0] +100002aa: f000 ffe3 bl 10001274 +100002ae: ee07 0a10 vmov s14, r0 +100002b2: eddf 5a16 vldr s11, [pc, #88] @ 1000030c +100002b6: eeb8 7a47 vcvt.f32.u32 s14, s14 +100002ba: ed9f 6a15 vldr s12, [pc, #84] @ 10000310 +100002be: eec7 7a25 vdiv.f32 s15, s14, s11 +100002c2: eef3 6a00 vmov.f32 s13, #48 @ 0x41800000 16.0 +100002c6: ee77 7a86 vadd.f32 s15, s15, s12 +100002ca: ee67 7aa6 vmul.f32 s15, s15, s13 +100002ce: 2100 movs r1, #0 +100002d0: 2001 movs r0, #1 +100002d2: f644 661f movw r6, #19999 @ 0x4e1f +100002d6: eefc 7ae7 vcvt.u32.f32 s15, s15 +100002da: 682b ldr r3, [r5, #0] +100002dc: 4c0d ldr r4, [pc, #52] @ (10000314 ) +100002de: eb03 0383 add.w r3, r3, r3, lsl #2 +100002e2: 009b lsls r3, r3, #2 +100002e4: f103 4280 add.w r2, r3, #1073741824 @ 0x40000000 +100002e8: f502 2228 add.w r2, r2, #688128 @ 0xa8000 +100002ec: 6011 str r1, [r2, #0] +100002ee: 6091 str r1, [r2, #8] +100002f0: 60d1 str r1, [r2, #12] +100002f2: 6116 str r6, [r2, #16] +100002f4: edc2 7a01 vstr s15, [r2, #4] +100002f8: 7020 strb r0, [r4, #0] +100002fa: 6010 str r0, [r2, #0] +100002fc: bd70 pop {r4, r5, r6, pc} +100002fe: bf00 nop +10000300: 200004de .word 0x200004de +10000304: 200004c8 .word 0x200004c8 +10000308: 200004cc .word 0x200004cc +1000030c: 49742400 .word 0x49742400 +10000310: 3d000000 .word 0x3d000000 +10000314: 200004dd .word 0x200004dd + +10000318 : +10000318: ee07 0a10 vmov s14, r0 +1000031c: eeb5 7ac0 vcmpe.f32 s14, #0.0 +10000320: eef1 fa10 vmrs APSR_nzcv, fpscr +10000324: d446 bmi.n 100003b4 +10000326: eddf 6a25 vldr s13, [pc, #148] @ 100003bc +1000032a: eeb4 7ae6 vcmpe.f32 s14, s13 +1000032e: eef1 fa10 vmrs APSR_nzcv, fpscr +10000332: fe36 7a87 vselgt.f32 s14, s13, s14 +10000336: eddf 7a22 vldr s15, [pc, #136] @ 100003c0 +1000033a: eec7 5a26 vdiv.f32 s11, s14, s13 +1000033e: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 +10000342: eee5 7aa7 vfma.f32 s15, s11, s15 +10000346: ee77 7a86 vadd.f32 s15, s15, s12 +1000034a: eefc 7ae7 vcvt.u32.f32 s15, s15 +1000034e: ee17 3a90 vmov r3, s15 +10000352: b29b uxth r3, r3 +10000354: 4a1b ldr r2, [pc, #108] @ (100003c4 ) +10000356: 7812 ldrb r2, [r2, #0] +10000358: b342 cbz r2, 100003ac +1000035a: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 +1000035e: bf28 it cs +10000360: f44f 63fa movcs.w r3, #2000 @ 0x7d0 +10000364: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 +10000368: bf38 it cc +1000036a: f44f 737a movcc.w r3, #1000 @ 0x3e8 +1000036e: ee07 3a90 vmov s15, r3 +10000372: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 +10000376: eef8 7a67 vcvt.f32.u32 s15, s15 +1000037a: ee77 7a87 vadd.f32 s15, s15, s14 +1000037e: eefc 7ae7 vcvt.u32.f32 s15, s15 +10000382: ee17 3a90 vmov r3, s15 +10000386: 4a10 ldr r2, [pc, #64] @ (100003c8 ) +10000388: 4810 ldr r0, [pc, #64] @ (100003cc ) +1000038a: 6811 ldr r1, [r2, #0] +1000038c: 6800 ldr r0, [r0, #0] +1000038e: 4a10 ldr r2, [pc, #64] @ (100003d0 ) +10000390: eb01 0181 add.w r1, r1, r1, lsl #2 +10000394: 0089 lsls r1, r1, #2 +10000396: 440a add r2, r1 +10000398: b29b uxth r3, r3 +1000039a: b940 cbnz r0, 100003ae +1000039c: f64f 70ff movw r0, #65535 @ 0xffff +100003a0: 6811 ldr r1, [r2, #0] +100003a2: f502 5280 add.w r2, r2, #4096 @ 0x1000 +100003a6: 404b eors r3, r1 +100003a8: 4003 ands r3, r0 +100003aa: 6013 str r3, [r2, #0] +100003ac: 4770 bx lr +100003ae: 4809 ldr r0, [pc, #36] @ (100003d4 ) +100003b0: 041b lsls r3, r3, #16 +100003b2: e7f5 b.n 100003a0 +100003b4: f44f 737a mov.w r3, #1000 @ 0x3e8 +100003b8: e7cc b.n 10000354 +100003ba: bf00 nop +100003bc: 43340000 .word 0x43340000 +100003c0: 447a0000 .word 0x447a0000 +100003c4: 200004dd .word 0x200004dd +100003c8: 200004cc .word 0x200004cc +100003cc: 200004c8 .word 0x200004c8 +100003d0: 400a800c .word 0x400a800c +100003d4: ffff0000 .word 0xffff0000 + +100003d8 : +100003d8: b410 push {r4} +100003da: f44f 7480 mov.w r4, #256 @ 0x100 +100003de: 4b0c ldr r3, [pc, #48] @ (10000410 ) +100003e0: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100003e4: eb03 0380 add.w r3, r3, r0, lsl #2 +100003e8: 00c0 lsls r0, r0, #3 +100003ea: f082 0240 eor.w r2, r2, #64 @ 0x40 +100003ee: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100003f2: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +100003f6: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100003fa: f500 3020 add.w r0, r0, #163840 @ 0x28000 +100003fe: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000402: f8cc 2000 str.w r2, [ip] +10000406: 6041 str r1, [r0, #4] +10000408: 601c str r4, [r3, #0] +1000040a: f85d 4b04 ldr.w r4, [sp], #4 +1000040e: 4770 bx lr +10000410: 40038004 .word 0x40038004 + +10000414 : +10000414: b40f push {r0, r1, r2, r3} +10000416: b500 push {lr} +10000418: b083 sub sp, #12 +1000041a: 9c04 ldr r4, [sp, #16] +1000041c: 4807 ldr r0, [pc, #28] @ (1000043c ) +1000041e: f001 fa35 bl 1000188c <__wrap_puts> +10000422: b13c cbz r4, 10000434 +10000424: a905 add r1, sp, #20 +10000426: 4620 mov r0, r4 +10000428: 9101 str r1, [sp, #4] +1000042a: f001 f8d1 bl 100015d0 +1000042e: 4804 ldr r0, [pc, #16] @ (10000440 ) +10000430: f001 fa2c bl 1000188c <__wrap_puts> +10000434: 2001 movs r0, #1 +10000436: f001 f8e3 bl 10001600 <_exit> +1000043a: bf00 nop +1000043c: 10001c6c .word 0x10001c6c +10000440: 10001c7c .word 0x10001c7c + +10000444 : +10000444: b570 push {r4, r5, r6, lr} +10000446: 4686 mov lr, r0 +10000448: f3ef 8510 mrs r5, PRIMASK +1000044c: b672 cpsid i +1000044e: 4c12 ldr r4, [pc, #72] @ (10000498 ) +10000450: e8d4 6fcf ldaexb r6, [r4] +10000454: 2001 movs r0, #1 +10000456: 2e00 cmp r6, #0 +10000458: d1fa bne.n 10000450 +1000045a: e8c4 0f46 strexb r6, r0, [r4] +1000045e: 2e00 cmp r6, #0 +10000460: d1f6 bne.n 10000450 +10000462: f3bf 8f5f dmb sy +10000466: f04f 0c01 mov.w ip, #1 +1000046a: 08c8 lsrs r0, r1, #3 +1000046c: f001 0307 and.w r3, r1, #7 +10000470: fa0c f303 lsl.w r3, ip, r3 +10000474: f81e c000 ldrb.w ip, [lr, r0] +10000478: ea1c 0603 ands.w r6, ip, r3 +1000047c: d108 bne.n 10000490 +1000047e: ea4c 0c03 orr.w ip, ip, r3 +10000482: f80e c000 strb.w ip, [lr, r0] +10000486: e8c4 6f8f stlb r6, [r4] +1000048a: f385 8810 msr PRIMASK, r5 +1000048e: bd70 pop {r4, r5, r6, pc} +10000490: 4610 mov r0, r2 +10000492: f7ff ffbf bl 10000414 +10000496: bf00 nop +10000498: 2000043b .word 0x2000043b + +1000049c : +1000049c: 4a04 ldr r2, [pc, #16] @ (100004b0 ) +1000049e: 7810 ldrb r0, [r2, #0] +100004a0: 1c43 adds r3, r0, #1 +100004a2: b2db uxtb r3, r3 +100004a4: 2b18 cmp r3, #24 +100004a6: bf28 it cs +100004a8: 2310 movcs r3, #16 +100004aa: 7013 strb r3, [r2, #0] +100004ac: 4770 bx lr +100004ae: bf00 nop +100004b0: 20000228 .word 0x20000228 + +100004b4 : +100004b4: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100004b8: 6893 ldr r3, [r2, #8] +100004ba: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100004be: 6093 str r3, [r2, #8] +100004c0: 4770 bx lr +100004c2: bf00 nop + +100004c4 : +100004c4: 2100 movs r1, #0 +100004c6: 4b04 ldr r3, [pc, #16] @ (100004d8 ) +100004c8: f103 0220 add.w r2, r3, #32 +100004cc: e8c3 1f8f stlb r1, [r3] +100004d0: 3301 adds r3, #1 +100004d2: 4293 cmp r3, r2 +100004d4: d1fa bne.n 100004cc +100004d6: 4770 bx lr +100004d8: 20000430 .word 0x20000430 + +100004dc : +100004dc: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100004e0: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100004e4: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100004e8: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100004ec: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100004f0: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100004f4: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100004f8: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100004fc: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000500: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000504: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000508: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000050c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000510: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000514: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000518: b662 cpsie i +1000051a: 4770 bx lr + +1000051c : +1000051c: 2301 movs r3, #1 +1000051e: f000 021f and.w r2, r0, #31 +10000522: 4093 lsls r3, r2 +10000524: 0940 lsrs r0, r0, #5 +10000526: b141 cbz r1, 1000053a +10000528: 0080 lsls r0, r0, #2 +1000052a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000052e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000532: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000536: 6003 str r3, [r0, #0] +10000538: 4770 bx lr +1000053a: 4a02 ldr r2, [pc, #8] @ (10000544 ) +1000053c: 3020 adds r0, #32 +1000053e: f842 3020 str.w r3, [r2, r0, lsl #2] +10000542: 4770 bx lr +10000544: e000e100 .word 0xe000e100 + +10000548 : +10000548: b5f8 push {r3, r4, r5, r6, r7, lr} +1000054a: 460d mov r5, r1 +1000054c: f3ef 8710 mrs r7, PRIMASK +10000550: b672 cpsid i +10000552: 4e12 ldr r6, [pc, #72] @ (1000059c ) +10000554: e8d6 2fcf ldaexb r2, [r6] +10000558: 2301 movs r3, #1 +1000055a: 2a00 cmp r2, #0 +1000055c: d1fa bne.n 10000554 +1000055e: e8c6 3f42 strexb r2, r3, [r6] +10000562: 2a00 cmp r2, #0 +10000564: d1f6 bne.n 10000554 +10000566: f3bf 8f5f dmb sy +1000056a: 4b0d ldr r3, [pc, #52] @ (100005a0 ) +1000056c: f100 0410 add.w r4, r0, #16 +10000570: 689b ldr r3, [r3, #8] +10000572: 4a0c ldr r2, [pc, #48] @ (100005a4 ) +10000574: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000578: 4293 cmp r3, r2 +1000057a: d003 beq.n 10000584 +1000057c: 4299 cmp r1, r3 +1000057e: d001 beq.n 10000584 +10000580: f000 ff0e bl 100013a0 +10000584: 4b06 ldr r3, [pc, #24] @ (100005a0 ) +10000586: 689b ldr r3, [r3, #8] +10000588: f843 5024 str.w r5, [r3, r4, lsl #2] +1000058c: f3bf 8f5f dmb sy +10000590: 2300 movs r3, #0 +10000592: e8c6 3f8f stlb r3, [r6] +10000596: f387 8810 msr PRIMASK, r7 +1000059a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000059c: 20000439 .word 0x20000439 +100005a0: e000ed00 .word 0xe000ed00 +100005a4: 10000111 .word 0x10000111 + +100005a8 : +100005a8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100005ac: b083 sub sp, #12 +100005ae: f3ef 8a10 mrs sl, PRIMASK +100005b2: b672 cpsid i +100005b4: 4e71 ldr r6, [pc, #452] @ (1000077c ) +100005b6: e8d6 2fcf ldaexb r2, [r6] +100005ba: 2301 movs r3, #1 +100005bc: 2a00 cmp r2, #0 +100005be: d1fa bne.n 100005b6 +100005c0: e8c6 3f42 strexb r2, r3, [r6] +100005c4: 2a00 cmp r2, #0 +100005c6: d1f6 bne.n 100005b6 +100005c8: f3bf 8f5f dmb sy +100005cc: 4b6c ldr r3, [pc, #432] @ (10000780 ) +100005ce: f100 0810 add.w r8, r0, #16 +100005d2: 689b ldr r3, [r3, #8] +100005d4: 4a6b ldr r2, [pc, #428] @ (10000784 ) +100005d6: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100005da: 4295 cmp r5, r2 +100005dc: d045 beq.n 1000066a +100005de: 428d cmp r5, r1 +100005e0: 460c mov r4, r1 +100005e2: d050 beq.n 10000686 +100005e4: 4f68 ldr r7, [pc, #416] @ (10000788 ) +100005e6: 1beb subs r3, r5, r7 +100005e8: 2b2f cmp r3, #47 @ 0x2f +100005ea: d83e bhi.n 1000066a +100005ec: 2101 movs r1, #1 +100005ee: ea4f 1950 mov.w r9, r0, lsr #5 +100005f2: ea4f 0989 mov.w r9, r9, lsl #2 +100005f6: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100005fa: f509 4961 add.w r9, r9, #57600 @ 0xe100 +100005fe: f000 031f and.w r3, r0, #31 +10000602: fa01 f003 lsl.w r0, r1, r3 +10000606: f8d9 3000 ldr.w r3, [r9] +1000060a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000060e: ea00 0b03 and.w fp, r0, r3 +10000612: f3bf 8f5f dmb sy +10000616: f3ef 8105 mrs r1, IPSR +1000061a: b2c9 uxtb r1, r1 +1000061c: 2900 cmp r1, #0 +1000061e: d034 beq.n 1000068a +10000620: 4588 cmp r8, r1 +10000622: d005 beq.n 10000630 +10000624: e9cd 1000 strd r1, r0, [sp] +10000628: f000 feba bl 100013a0 +1000062c: e9dd 1000 ldrd r1, r0, [sp] +10000630: f025 0e01 bic.w lr, r5, #1 +10000634: f8de c008 ldr.w ip, [lr, #8] +10000638: 4564 cmp r4, ip +1000063a: d105 bne.n 10000648 +1000063c: e089 b.n 10000752 +1000063e: f8d3 c008 ldr.w ip, [r3, #8] +10000642: 4564 cmp r4, ip +10000644: d031 beq.n 100006aa +10000646: 469e mov lr, r3 +10000648: f99e 2006 ldrsb.w r2, [lr, #6] +1000064c: eb02 0342 add.w r3, r2, r2, lsl #1 +10000650: 2a00 cmp r2, #0 +10000652: eb07 0383 add.w r3, r7, r3, lsl #2 +10000656: daf2 bge.n 1000063e +10000658: 4564 cmp r4, ip +1000065a: d061 beq.n 10000720 +1000065c: f1bb 0f00 cmp.w fp, #0 +10000660: d020 beq.n 100006a4 +10000662: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +10000666: f8c9 0000 str.w r0, [r9] +1000066a: 4b45 ldr r3, [pc, #276] @ (10000780 ) +1000066c: 689b ldr r3, [r3, #8] +1000066e: f843 5028 str.w r5, [r3, r8, lsl #2] +10000672: f3bf 8f5f dmb sy +10000676: 2300 movs r3, #0 +10000678: e8c6 3f8f stlb r3, [r6] +1000067c: f38a 8810 msr PRIMASK, sl +10000680: b003 add sp, #12 +10000682: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000686: 4615 mov r5, r2 +10000688: e7ef b.n 1000066a +1000068a: f025 0e01 bic.w lr, r5, #1 +1000068e: f8de c008 ldr.w ip, [lr, #8] +10000692: 4564 cmp r4, ip +10000694: d1d8 bne.n 10000648 +10000696: f99e 4006 ldrsb.w r4, [lr, #6] +1000069a: 4673 mov r3, lr +1000069c: 2c00 cmp r4, #0 +1000069e: da08 bge.n 100006b2 +100006a0: 4615 mov r5, r2 +100006a2: e046 b.n 10000732 +100006a4: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100006a8: e7df b.n 1000066a +100006aa: f993 4006 ldrsb.w r4, [r3, #6] +100006ae: 2c00 cmp r4, #0 +100006b0: db37 blt.n 10000722 +100006b2: eb04 0c44 add.w ip, r4, r4, lsl #1 +100006b6: eb07 0c8c add.w ip, r7, ip, lsl #2 +100006ba: f89c 1007 ldrb.w r1, [ip, #7] +100006be: f8dc 2008 ldr.w r2, [ip, #8] +100006c2: 71d9 strb r1, [r3, #7] +100006c4: 609a str r2, [r3, #8] +100006c6: f99c 2006 ldrsb.w r2, [ip, #6] +100006ca: 0061 lsls r1, r4, #1 +100006cc: 2a00 cmp r2, #0 +100006ce: 719a strb r2, [r3, #6] +100006d0: db3d blt.n 1000074e +100006d2: f8bc e004 ldrh.w lr, [ip, #4] +100006d6: ea5f 5e4e movs.w lr, lr, lsl #21 +100006da: d505 bpl.n 100006e8 +100006dc: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100006e0: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100006e4: f10e 0e1f add.w lr, lr, #31 +100006e8: f06f 0c07 mvn.w ip, #7 +100006ec: 190a adds r2, r1, r4 +100006ee: ea4f 5e6e mov.w lr, lr, asr #21 +100006f2: 0092 lsls r2, r2, #2 +100006f4: eb02 024e add.w r2, r2, lr, lsl #1 +100006f8: 3208 adds r2, #8 +100006fa: 443a add r2, r7 +100006fc: ebac 0c03 sub.w ip, ip, r3 +10000700: 4462 add r2, ip +10000702: f3c2 024a ubfx r2, r2, #1, #11 +10000706: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000070a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000070e: 809a strh r2, [r3, #4] +10000710: 4b1e ldr r3, [pc, #120] @ (1000078c ) +10000712: 4421 add r1, r4 +10000714: 781a ldrb r2, [r3, #0] +10000716: eb07 0181 add.w r1, r7, r1, lsl #2 +1000071a: 701c strb r4, [r3, #0] +1000071c: 718a strb r2, [r1, #6] +1000071e: e79d b.n 1000065c +10000720: 4673 mov r3, lr +10000722: b9d9 cbnz r1, 1000075c +10000724: 22ff movs r2, #255 @ 0xff +10000726: f88e 2006 strb.w r2, [lr, #6] +1000072a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000072e: f8ae 2004 strh.w r2, [lr, #4] +10000732: 4c16 ldr r4, [pc, #88] @ (1000078c ) +10000734: f64a 22aa movw r2, #43690 @ 0xaaaa +10000738: f894 c000 ldrb.w ip, [r4] +1000073c: 4619 mov r1, r3 +1000073e: 1bc9 subs r1, r1, r7 +10000740: 4149 adcs r1, r1 +10000742: 434a muls r2, r1 +10000744: 0d12 lsrs r2, r2, #20 +10000746: f883 c006 strb.w ip, [r3, #6] +1000074a: 7022 strb r2, [r4, #0] +1000074c: e786 b.n 1000065c +1000074e: 4a10 ldr r2, [pc, #64] @ (10000790 ) +10000750: e7dd b.n 1000070e +10000752: f99e 4006 ldrsb.w r4, [lr, #6] +10000756: 4673 mov r3, lr +10000758: 2c00 cmp r4, #0 +1000075a: daaa bge.n 100006b2 +1000075c: 4a0d ldr r2, [pc, #52] @ (10000794 ) +1000075e: 4c0e ldr r4, [pc, #56] @ (10000798 ) +10000760: 1ad2 subs r2, r2, r3 +10000762: 3a08 subs r2, #8 +10000764: f3c2 310a ubfx r1, r2, #12, #11 +10000768: ea6f 5101 mvn.w r1, r1, lsl #20 +1000076c: ea6f 5111 mvn.w r1, r1, lsr #20 +10000770: ea44 0252 orr.w r2, r4, r2, lsr #1 +10000774: 80da strh r2, [r3, #6] +10000776: 8099 strh r1, [r3, #4] +10000778: e770 b.n 1000065c +1000077a: bf00 nop +1000077c: 20000439 .word 0x20000439 +10000780: e000ed00 .word 0xe000ed00 +10000784: 10000111 .word 0x10000111 +10000788: 2000022c .word 0x2000022c +1000078c: 200004dc .word 0x200004dc +10000790: ffffbd01 .word 0xffffbd01 +10000794: 20000266 .word 0x20000266 +10000798: fffff800 .word 0xfffff800 + +1000079c : +1000079c: b5f0 push {r4, r5, r6, r7, lr} +1000079e: f3ef 8505 mrs r5, IPSR +100007a2: b2ed uxtb r5, r5 +100007a4: f3ef 8c10 mrs ip, PRIMASK +100007a8: b672 cpsid i +100007aa: 4926 ldr r1, [pc, #152] @ (10000844 ) +100007ac: e8d1 2fcf ldaexb r2, [r1] +100007b0: 2301 movs r3, #1 +100007b2: 2a00 cmp r2, #0 +100007b4: d1fa bne.n 100007ac +100007b6: e8c1 3f42 strexb r2, r3, [r1] +100007ba: 2a00 cmp r2, #0 +100007bc: d1f6 bne.n 100007ac +100007be: f3bf 8f5f dmb sy +100007c2: 4e21 ldr r6, [pc, #132] @ (10000848 ) +100007c4: f040 0e01 orr.w lr, r0, #1 +100007c8: 68b4 ldr r4, [r6, #8] +100007ca: f64a 23aa movw r3, #43690 @ 0xaaaa +100007ce: f854 7025 ldr.w r7, [r4, r5, lsl #2] +100007d2: 4a1e ldr r2, [pc, #120] @ (1000084c ) +100007d4: 4604 mov r4, r0 +100007d6: 1aa4 subs r4, r4, r2 +100007d8: 4164 adcs r4, r4 +100007da: 4363 muls r3, r4 +100007dc: 0d1b lsrs r3, r3, #20 +100007de: 4577 cmp r7, lr +100007e0: b25b sxtb r3, r3 +100007e2: d01b beq.n 1000081c +100007e4: f992 4006 ldrsb.w r4, [r2, #6] +100007e8: 429c cmp r4, r3 +100007ea: d01c beq.n 10000826 +100007ec: f992 4012 ldrsb.w r4, [r2, #18] +100007f0: 429c cmp r4, r3 +100007f2: d023 beq.n 1000083c +100007f4: f992 401e ldrsb.w r4, [r2, #30] +100007f8: 429c cmp r4, r3 +100007fa: d021 beq.n 10000840 +100007fc: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000800: 429c cmp r4, r3 +10000802: bf08 it eq +10000804: 2403 moveq r4, #3 +10000806: d00f beq.n 10000828 +10000808: 4a11 ldr r2, [pc, #68] @ (10000850 ) +1000080a: 2400 movs r4, #0 +1000080c: 7815 ldrb r5, [r2, #0] +1000080e: 7013 strb r3, [r2, #0] +10000810: 7185 strb r5, [r0, #6] +10000812: e8c1 4f8f stlb r4, [r1] +10000816: f38c 8810 msr PRIMASK, ip +1000081a: bdf0 pop {r4, r5, r6, r7, pc} +1000081c: 68b2 ldr r2, [r6, #8] +1000081e: 4c0d ldr r4, [pc, #52] @ (10000854 ) +10000820: f842 4025 str.w r4, [r2, r5, lsl #2] +10000824: e7f0 b.n 10000808 +10000826: 2400 movs r4, #0 +10000828: eb04 0444 add.w r4, r4, r4, lsl #1 +1000082c: eb02 0284 add.w r2, r2, r4, lsl #2 +10000830: 24ff movs r4, #255 @ 0xff +10000832: 7194 strb r4, [r2, #6] +10000834: f64b 5401 movw r4, #48385 @ 0xbd01 +10000838: 8094 strh r4, [r2, #4] +1000083a: e7e5 b.n 10000808 +1000083c: 2401 movs r4, #1 +1000083e: e7f3 b.n 10000828 +10000840: 2402 movs r4, #2 +10000842: e7f1 b.n 10000828 +10000844: 20000439 .word 0x20000439 +10000848: e000ed00 .word 0xe000ed00 +1000084c: 2000022c .word 0x2000022c +10000850: 200004dc .word 0x200004dc +10000854: 10000111 .word 0x10000111 + +10000858 : +10000858: 4b01 ldr r3, [pc, #4] @ (10000860 ) +1000085a: 440b add r3, r1 +1000085c: 6003 str r3, [r0, #0] +1000085e: 4770 bx lr +10000860: 20000430 .word 0x20000430 + +10000864 : +10000864: b570 push {r4, r5, r6, lr} +10000866: 4c10 ldr r4, [pc, #64] @ (100008a8 ) +10000868: 4d10 ldr r5, [pc, #64] @ (100008ac ) +1000086a: 42ac cmp r4, r5 +1000086c: d20e bcs.n 1000088c +1000086e: 26ff movs r6, #255 @ 0xff +10000870: 6823 ldr r3, [r4, #0] +10000872: b163 cbz r3, 1000088e +10000874: f7ff fe12 bl 1000049c +10000878: 4601 mov r1, r0 +1000087a: 4620 mov r0, r4 +1000087c: f7ff ffec bl 10000858 +10000880: 80a6 strh r6, [r4, #4] +10000882: f3bf 8f5f dmb sy +10000886: 3408 adds r4, #8 +10000888: 42ac cmp r4, r5 +1000088a: d3f1 bcc.n 10000870 +1000088c: bd70 pop {r4, r5, r6, pc} +1000088e: f7ff fe05 bl 1000049c +10000892: 4601 mov r1, r0 +10000894: 4620 mov r0, r4 +10000896: f7ff ffdf bl 10000858 +1000089a: 7126 strb r6, [r4, #4] +1000089c: f3bf 8f5f dmb sy +100008a0: 3408 adds r4, #8 +100008a2: 42ac cmp r4, r5 +100008a4: d3e4 bcc.n 10000870 +100008a6: bd70 pop {r4, r5, r6, pc} +100008a8: 200002a4 .word 0x200002a4 +100008ac: 200002ac .word 0x200002ac + +100008b0 : +100008b0: 4b0d ldr r3, [pc, #52] @ (100008e8 ) +100008b2: 681a ldr r2, [r3, #0] +100008b4: f3ef 8110 mrs r1, PRIMASK +100008b8: b672 cpsid i +100008ba: e8d2 cfcf ldaexb ip, [r2] +100008be: 2001 movs r0, #1 +100008c0: f1bc 0f00 cmp.w ip, #0 +100008c4: d1f9 bne.n 100008ba +100008c6: e8c2 0f4c strexb ip, r0, [r2] +100008ca: f1bc 0f00 cmp.w ip, #0 +100008ce: d1f4 bne.n 100008ba +100008d0: f3bf 8f5f dmb sy +100008d4: 2200 movs r2, #0 +100008d6: 681b ldr r3, [r3, #0] +100008d8: e8c3 2f8f stlb r2, [r3] +100008dc: f381 8810 msr PRIMASK, r1 +100008e0: bf40 sev +100008e2: 2000 movs r0, #0 +100008e4: 2100 movs r1, #0 +100008e6: 4770 bx lr +100008e8: 200004d0 .word 0x200004d0 +100008ec: 00000000 .word 0x00000000 + +100008f0 : +100008f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100008f4: ed2d 8b02 vpush {d8} +100008f8: b085 sub sp, #20 +100008fa: f3ef 8305 mrs r3, IPSR +100008fe: b2db uxtb r3, r3 +10000900: 3b10 subs r3, #16 +10000902: 089a lsrs r2, r3, #2 +10000904: bf18 it ne +10000906: 2201 movne r2, #1 +10000908: f04f 0101 mov.w r1, #1 +1000090c: f003 0b03 and.w fp, r3, #3 +10000910: bf18 it ne +10000912: 4daf ldrne r5, [pc, #700] @ (10000bd0 ) +10000914: 4baf ldr r3, [pc, #700] @ (10000bd4 ) +10000916: bf08 it eq +10000918: 4daf ldreq r5, [pc, #700] @ (10000bd8 ) +1000091a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000091e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000922: fa01 f20b lsl.w r2, r1, fp +10000926: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000092a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000bc8 +1000092e: 9201 str r2, [sp, #4] +10000930: 605a str r2, [r3, #4] +10000932: e02f b.n 10000994 +10000934: 88b3 ldrh r3, [r6, #4] +10000936: 041c lsls r4, r3, #16 +10000938: f140 8093 bpl.w 10000a62 +1000093c: 79b3 ldrb r3, [r6, #6] +1000093e: 2b00 cmp r3, #0 +10000940: f040 80dd bne.w 10000afe +10000944: f9b6 2008 ldrsh.w r2, [r6, #8] +10000948: 2a00 cmp r2, #0 +1000094a: f2c0 811e blt.w 10000b8a +1000094e: 6973 ldr r3, [r6, #20] +10000950: eb02 0242 add.w r2, r2, r2, lsl #1 +10000954: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000958: e9d3 4702 ldrd r4, r7, [r3, #8] +1000095c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000960: bf08 it eq +10000962: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000966: d00e beq.n 10000986 +10000968: eb05 018b add.w r1, r5, fp, lsl #2 +1000096c: 6aab ldr r3, [r5, #40] @ 0x28 +1000096e: 690a ldr r2, [r1, #16] +10000970: 1ad2 subs r2, r2, r3 +10000972: 1ae3 subs r3, r4, r3 +10000974: 4293 cmp r3, r2 +10000976: d305 bcc.n 10000984 +10000978: 2301 movs r3, #1 +1000097a: 6a2a ldr r2, [r5, #32] +1000097c: fa03 f30b lsl.w r3, r3, fp +10000980: 4213 tst r3, r2 +10000982: d100 bne.n 10000986 +10000984: 610c str r4, [r1, #16] +10000986: 4628 mov r0, r5 +10000988: f000 fb38 bl 10000ffc +1000098c: 42a0 cmp r0, r4 +1000098e: 41b9 sbcs r1, r7 +10000990: f2c0 80fb blt.w 10000b8a +10000994: f9b6 3008 ldrsh.w r3, [r6, #8] +10000998: 9a01 ldr r2, [sp, #4] +1000099a: 2b00 cmp r3, #0 +1000099c: 9300 str r3, [sp, #0] +1000099e: 63ea str r2, [r5, #60] @ 0x3c +100009a0: dbc8 blt.n 10000934 +100009a2: f8d6 8014 ldr.w r8, [r6, #20] +100009a6: eb03 0943 add.w r9, r3, r3, lsl #1 +100009aa: 4628 mov r0, r5 +100009ac: eb08 07c9 add.w r7, r8, r9, lsl #3 +100009b0: e9d7 4a02 ldrd r4, sl, [r7, #8] +100009b4: f000 fb22 bl 10000ffc +100009b8: 42a0 cmp r0, r4 +100009ba: eb71 010a sbcs.w r1, r1, sl +100009be: dbb9 blt.n 10000934 +100009c0: f1ba 0f00 cmp.w sl, #0 +100009c4: f2c0 80c3 blt.w 10000b4e +100009c8: e9d7 3104 ldrd r3, r1, [r7, #16] +100009cc: 4a83 ldr r2, [pc, #524] @ (10000bdc ) +100009ce: 4293 cmp r3, r2 +100009d0: f000 80ed beq.w 10000bae +100009d4: 887a ldrh r2, [r7, #2] +100009d6: f9b6 0008 ldrsh.w r0, [r6, #8] +100009da: b292 uxth r2, r2 +100009dc: ea42 4000 orr.w r0, r2, r0, lsl #16 +100009e0: 4798 blx r3 +100009e2: 4602 mov r2, r0 +100009e4: 460b mov r3, r1 +100009e6: ea52 0103 orrs.w r1, r2, r3 +100009ea: f000 80b0 beq.w 10000b4e +100009ee: 2b00 cmp r3, #0 +100009f0: f280 80d1 bge.w 10000b96 +100009f4: ebb4 0e02 subs.w lr, r4, r2 +100009f8: eb6a 0a03 sbc.w sl, sl, r3 +100009fc: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000a00: e9c7 ea02 strd lr, sl, [r7, #8] +10000a04: 2b00 cmp r3, #0 +10000a06: db95 blt.n 10000934 +10000a08: 6971 ldr r1, [r6, #20] +10000a0a: eb03 0243 add.w r2, r3, r3, lsl #1 +10000a0e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000a12: e9d2 7002 ldrd r7, r0, [r2, #8] +10000a16: 45be cmp lr, r7 +10000a18: eb7a 0c00 sbcs.w ip, sl, r0 +10000a1c: ea4f 0243 mov.w r2, r3, lsl #1 +10000a20: db88 blt.n 10000934 +10000a22: 46b4 mov ip, r6 +10000a24: f82c 3f08 strh.w r3, [ip, #8]! +10000a28: e006 b.n 10000a38 +10000a2a: eb03 0043 add.w r0, r3, r3, lsl #1 +10000a2e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000a32: 005a lsls r2, r3, #1 +10000a34: e9d0 7002 ldrd r7, r0, [r0, #8] +10000a38: 45be cmp lr, r7 +10000a3a: 441a add r2, r3 +10000a3c: eb7a 0000 sbcs.w r0, sl, r0 +10000a40: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000a44: db04 blt.n 10000a50 +10000a46: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000a4a: 46a4 mov ip, r4 +10000a4c: 2b00 cmp r3, #0 +10000a4e: daec bge.n 10000a2a +10000a50: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000a54: 9b00 ldr r3, [sp, #0] +10000a56: f8ac 3000 strh.w r3, [ip] +10000a5a: 88b3 ldrh r3, [r6, #4] +10000a5c: 041c lsls r4, r3, #16 +10000a5e: f53f af6d bmi.w 1000093c +10000a62: 6933 ldr r3, [r6, #16] +10000a64: f3ef 8210 mrs r2, PRIMASK +10000a68: b672 cpsid i +10000a6a: e8d3 0fcf ldaexb r0, [r3] +10000a6e: 2101 movs r1, #1 +10000a70: 2800 cmp r0, #0 +10000a72: d1fa bne.n 10000a6a +10000a74: e8c3 1f40 strexb r0, r1, [r3] +10000a78: 2800 cmp r0, #0 +10000a7a: d1f6 bne.n 10000a6a +10000a7c: f3bf 8f5f dmb sy +10000a80: f64f 74ff movw r4, #65535 @ 0xffff +10000a84: 88b0 ldrh r0, [r6, #4] +10000a86: 2300 movs r3, #0 +10000a88: 6931 ldr r1, [r6, #16] +10000a8a: b200 sxth r0, r0 +10000a8c: 80b4 strh r4, [r6, #4] +10000a8e: e8c1 3f8f stlb r3, [r1] +10000a92: f382 8810 msr PRIMASK, r2 +10000a96: 4298 cmp r0, r3 +10000a98: f6ff af50 blt.w 1000093c +10000a9c: 4607 mov r7, r0 +10000a9e: 46a9 mov r9, r5 +10000aa0: 6974 ldr r4, [r6, #20] +10000aa2: f106 0808 add.w r8, r6, #8 +10000aa6: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000aaa: eb04 03ce add.w r3, r4, lr, lsl #3 +10000aae: e9d3 5002 ldrd r5, r0, [r3, #8] +10000ab2: f9b6 3008 ldrsh.w r3, [r6, #8] +10000ab6: 46c4 mov ip, r8 +10000ab8: 2b00 cmp r3, #0 +10000aba: db13 blt.n 10000ae4 +10000abc: 46b2 mov sl, r6 +10000abe: 9700 str r7, [sp, #0] +10000ac0: e004 b.n 10000acc +10000ac2: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000ac6: 4694 mov ip, r2 +10000ac8: 2b00 cmp r3, #0 +10000aca: db09 blt.n 10000ae0 +10000acc: eb03 0643 add.w r6, r3, r3, lsl #1 +10000ad0: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000ad4: e9d2 7102 ldrd r7, r1, [r2, #8] +10000ad8: 42bd cmp r5, r7 +10000ada: eb70 0101 sbcs.w r1, r0, r1 +10000ade: daf0 bge.n 10000ac2 +10000ae0: 4656 mov r6, sl +10000ae2: 9f00 ldr r7, [sp, #0] +10000ae4: f8ac 7000 strh.w r7, [ip] +10000ae8: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000aec: f824 303e strh.w r3, [r4, lr, lsl #3] +10000af0: 2f00 cmp r7, #0 +10000af2: dad8 bge.n 10000aa6 +10000af4: 79b3 ldrb r3, [r6, #6] +10000af6: 464d mov r5, r9 +10000af8: 2b00 cmp r3, #0 +10000afa: f43f af23 beq.w 10000944 +10000afe: 2300 movs r3, #0 +10000b00: 71b3 strb r3, [r6, #6] +10000b02: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b06: f106 0808 add.w r8, r6, #8 +10000b0a: 1c58 adds r0, r3, #1 +10000b0c: d03d beq.n 10000b8a +10000b0e: 461a mov r2, r3 +10000b10: 6977 ldr r7, [r6, #20] +10000b12: e003 b.n 10000b1c +10000b14: 4680 mov r8, r0 +10000b16: 1c59 adds r1, r3, #1 +10000b18: f43f af16 beq.w 10000948 +10000b1c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000b20: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000b24: f8b0 c002 ldrh.w ip, [r0, #2] +10000b28: 461c mov r4, r3 +10000b2a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000b2e: 469e mov lr, r3 +10000b30: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000b34: d0ee beq.n 10000b14 +10000b36: 4294 cmp r4, r2 +10000b38: ed80 8b02 vstr d8, [r0, #8] +10000b3c: d005 beq.n 10000b4a +10000b3e: f8a8 3000 strh.w r3, [r8] +10000b42: 8932 ldrh r2, [r6, #8] +10000b44: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000b48: 8134 strh r4, [r6, #8] +10000b4a: 4672 mov r2, lr +10000b4c: e7e3 b.n 10000b16 +10000b4e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000b52: 8133 strh r3, [r6, #8] +10000b54: 6933 ldr r3, [r6, #16] +10000b56: f3ef 8210 mrs r2, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d3 0fcf ldaexb r0, [r3] +10000b60: 2101 movs r1, #1 +10000b62: 2800 cmp r0, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c3 1f40 strexb r0, r1, [r3] +10000b6a: 2800 cmp r0, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: 8873 ldrh r3, [r6, #2] +10000b74: 6931 ldr r1, [r6, #16] +10000b76: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000b7a: 9b00 ldr r3, [sp, #0] +10000b7c: 8073 strh r3, [r6, #2] +10000b7e: 2300 movs r3, #0 +10000b80: e8c1 3f8f stlb r3, [r1] +10000b84: f382 8810 msr PRIMASK, r2 +10000b88: e6d4 b.n 10000934 +10000b8a: bf40 sev +10000b8c: b005 add sp, #20 +10000b8e: ecbd 8b02 vpop {d8} +10000b92: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000b96: 4628 mov r0, r5 +10000b98: e9cd 2302 strd r2, r3, [sp, #8] +10000b9c: f000 fa2e bl 10000ffc +10000ba0: 9a02 ldr r2, [sp, #8] +10000ba2: 9b03 ldr r3, [sp, #12] +10000ba4: eb10 0e02 adds.w lr, r0, r2 +10000ba8: eb43 0a01 adc.w sl, r3, r1 +10000bac: e726 b.n 100009fc +10000bae: 4608 mov r0, r1 +10000bb0: 690b ldr r3, [r1, #16] +10000bb2: 9102 str r1, [sp, #8] +10000bb4: 4798 blx r3 +10000bb6: 2800 cmp r0, #0 +10000bb8: d0c9 beq.n 10000b4e +10000bba: 9902 ldr r1, [sp, #8] +10000bbc: e9d1 2300 ldrd r2, r3, [r1] +10000bc0: e711 b.n 100009e6 +10000bc2: bf00 nop +10000bc4: f3af 8000 nop.w +10000bc8: ffffffff .word 0xffffffff +10000bcc: ffffffff .word 0xffffffff +10000bd0: 400b8000 .word 0x400b8000 +10000bd4: 200004a8 .word 0x200004a8 +10000bd8: 400b0000 .word 0x400b0000 +10000bdc: 100008f1 .word 0x100008f1 + +10000be0 : +10000be0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000be4: 4c36 ldr r4, [pc, #216] @ (10000cc0 ) +10000be6: 6925 ldr r5, [r4, #16] +10000be8: b12d cbz r5, 10000bf6 +10000bea: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000bee: 210a movs r1, #10 +10000bf0: 4834 ldr r0, [pc, #208] @ (10000cc4 ) +10000bf2: f7ff be31 b.w 10000858 +10000bf6: f8df 80e4 ldr.w r8, [pc, #228] @ 10000cdc +10000bfa: 2103 movs r1, #3 +10000bfc: 4640 mov r0, r8 +10000bfe: f000 f9eb bl 10000fd8 +10000c02: 2603 movs r6, #3 +10000c04: f8c4 800c str.w r8, [r4, #12] +10000c08: f7ff fc48 bl 1000049c +10000c0c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000c10: 4b2d ldr r3, [pc, #180] @ (10000cc8 ) +10000c12: 7026 strb r6, [r4, #0] +10000c14: 4403 add r3, r0 +10000c16: 6123 str r3, [r4, #16] +10000c18: f8dc 3000 ldr.w r3, [ip] +10000c1c: 210f movs r1, #15 +10000c1e: 7063 strb r3, [r4, #1] +10000c20: 6963 ldr r3, [r4, #20] +10000c22: 8061 strh r1, [r4, #2] +10000c24: 831d strh r5, [r3, #24] +10000c26: f04f 0504 mov.w r5, #4 +10000c2a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000c2e: f04f 0505 mov.w r5, #5 +10000c32: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000c36: f04f 0506 mov.w r5, #6 +10000c3a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000c3e: f04f 0507 mov.w r5, #7 +10000c42: 210e movs r1, #14 +10000c44: f64f 72ff movw r2, #65535 @ 0xffff +10000c48: 2708 movs r7, #8 +10000c4a: f04f 0e0a mov.w lr, #10 +10000c4e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000c52: f04f 0901 mov.w r9, #1 +10000c56: f04f 0c0c mov.w ip, #12 +10000c5a: f04f 0b02 mov.w fp, #2 +10000c5e: f04f 0a09 mov.w sl, #9 +10000c62: 200d movs r0, #13 +10000c64: f04f 050b mov.w r5, #11 +10000c68: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000c6c: 4917 ldr r1, [pc, #92] @ (10000ccc ) +10000c6e: 80a2 strh r2, [r4, #4] +10000c70: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000c74: 60a1 str r1, [r4, #8] +10000c76: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000c7a: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000c7e: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000c82: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000c86: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000c8a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000c8e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000c92: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000c96: 801a strh r2, [r3, #0] +10000c98: 4b0d ldr r3, [pc, #52] @ (10000cd0 ) +10000c9a: 4630 mov r0, r6 +10000c9c: f8c8 7020 str.w r7, [r8, #32] +10000ca0: 490c ldr r1, [pc, #48] @ (10000cd4 ) +10000ca2: 60dc str r4, [r3, #12] +10000ca4: f7ff fc50 bl 10000548 +10000ca8: 4649 mov r1, r9 +10000caa: 4630 mov r0, r6 +10000cac: f7ff fc36 bl 1000051c +10000cb0: 4b09 ldr r3, [pc, #36] @ (10000cd8 ) +10000cb2: 210a movs r1, #10 +10000cb4: 641f str r7, [r3, #64] @ 0x40 +10000cb6: 4803 ldr r0, [pc, #12] @ (10000cc4 ) +10000cb8: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000cbc: f7ff bdcc b.w 10000858 +10000cc0: 20000274 .word 0x20000274 +10000cc4: 200004d0 .word 0x200004d0 +10000cc8: 20000430 .word 0x20000430 +10000ccc: 0010ffff .word 0x0010ffff +10000cd0: 200004a8 .word 0x200004a8 +10000cd4: 100008f1 .word 0x100008f1 +10000cd8: 400b2000 .word 0x400b2000 +10000cdc: 400b0000 .word 0x400b0000 + +10000ce0 : +10000ce0: 4601 mov r1, r0 +10000ce2: b5f0 push {r4, r5, r6, r7, lr} +10000ce4: 6900 ldr r0, [r0, #16] +10000ce6: f3ef 8710 mrs r7, PRIMASK +10000cea: b672 cpsid i +10000cec: e8d0 5fcf ldaexb r5, [r0] +10000cf0: 2401 movs r4, #1 +10000cf2: 2d00 cmp r5, #0 +10000cf4: d1fa bne.n 10000cec +10000cf6: e8c0 4f45 strexb r5, r4, [r0] +10000cfa: 2d00 cmp r5, #0 +10000cfc: d1f6 bne.n 10000cec +10000cfe: f3bf 8f5f dmb sy +10000d02: f9b1 e002 ldrsh.w lr, [r1, #2] +10000d06: 694c ldr r4, [r1, #20] +10000d08: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000d0c: f1be 0f00 cmp.w lr, #0 +10000d10: ea4f 05cc mov.w r5, ip, lsl #3 +10000d14: 6908 ldr r0, [r1, #16] +10000d16: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000d1a: db3c blt.n 10000d96 +10000d1c: 5b66 ldrh r6, [r4, r5] +10000d1e: 804e strh r6, [r1, #2] +10000d20: 2600 movs r6, #0 +10000d22: e8c0 6f8f stlb r6, [r0] +10000d26: f387 8810 msr PRIMASK, r7 +10000d2a: f8bc 0002 ldrh.w r0, [ip, #2] +10000d2e: e9cc 2302 strd r2, r3, [ip, #8] +10000d32: 3001 adds r0, #1 +10000d34: f3c0 000e ubfx r0, r0, #0, #15 +10000d38: 2801 cmp r0, #1 +10000d3a: bf38 it cc +10000d3c: 2001 movcc r0, #1 +10000d3e: 9b05 ldr r3, [sp, #20] +10000d40: f8ac 0002 strh.w r0, [ip, #2] +10000d44: f8cc 3010 str.w r3, [ip, #16] +10000d48: 9b06 ldr r3, [sp, #24] +10000d4a: ea40 400e orr.w r0, r0, lr, lsl #16 +10000d4e: f8cc 3014 str.w r3, [ip, #20] +10000d52: 690b ldr r3, [r1, #16] +10000d54: f3ef 8210 mrs r2, PRIMASK +10000d58: b672 cpsid i +10000d5a: e8d3 cfcf ldaexb ip, [r3] +10000d5e: 2701 movs r7, #1 +10000d60: f1bc 0f00 cmp.w ip, #0 +10000d64: d1f9 bne.n 10000d5a +10000d66: e8c3 7f4c strexb ip, r7, [r3] +10000d6a: f1bc 0f00 cmp.w ip, #0 +10000d6e: d1f4 bne.n 10000d5a +10000d70: f3bf 8f5f dmb sy +10000d74: 888b ldrh r3, [r1, #4] +10000d76: 5363 strh r3, [r4, r5] +10000d78: f8a1 e004 strh.w lr, [r1, #4] +10000d7c: 690b ldr r3, [r1, #16] +10000d7e: e8c3 6f8f stlb r6, [r3] +10000d82: f382 8810 msr PRIMASK, r2 +10000d86: 2201 movs r2, #1 +10000d88: 68cb ldr r3, [r1, #12] +10000d8a: 7809 ldrb r1, [r1, #0] +10000d8c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000d90: 408a lsls r2, r1 +10000d92: 605a str r2, [r3, #4] +10000d94: bdf0 pop {r4, r5, r6, r7, pc} +10000d96: 2300 movs r3, #0 +10000d98: e8c0 3f8f stlb r3, [r0] +10000d9c: f387 8810 msr PRIMASK, r7 +10000da0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000da4: bdf0 pop {r4, r5, r6, r7, pc} +10000da6: bf00 nop + +10000da8 : +10000da8: 4603 mov r3, r0 +10000daa: 8940 ldrh r0, [r0, #10] +10000dac: ebb0 4f21 cmp.w r0, r1, asr #16 +10000db0: dd37 ble.n 10000e22 +10000db2: 6958 ldr r0, [r3, #20] +10000db4: 140a asrs r2, r1, #16 +10000db6: eb02 0242 add.w r2, r2, r2, lsl #1 +10000dba: b510 push {r4, lr} +10000dbc: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000dc0: 691c ldr r4, [r3, #16] +10000dc2: f3ef 8c10 mrs ip, PRIMASK +10000dc6: b672 cpsid i +10000dc8: e8d4 efcf ldaexb lr, [r4] +10000dcc: 2201 movs r2, #1 +10000dce: f1be 0f00 cmp.w lr, #0 +10000dd2: d1f9 bne.n 10000dc8 +10000dd4: e8c4 2f4e strexb lr, r2, [r4] +10000dd8: f1be 0f00 cmp.w lr, #0 +10000ddc: d1f4 bne.n 10000dc8 +10000dde: f3bf 8f5f dmb sy +10000de2: 8842 ldrh r2, [r0, #2] +10000de4: b289 uxth r1, r1 +10000de6: b292 uxth r2, r2 +10000de8: 428a cmp r2, r1 +10000dea: d007 beq.n 10000dfc +10000dec: 2200 movs r2, #0 +10000dee: 691b ldr r3, [r3, #16] +10000df0: e8c3 2f8f stlb r2, [r3] +10000df4: f38c 8810 msr PRIMASK, ip +10000df8: 2000 movs r0, #0 +10000dfa: bd10 pop {r4, pc} +10000dfc: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000e00: 8042 strh r2, [r0, #2] +10000e02: 2101 movs r1, #1 +10000e04: 2200 movs r2, #0 +10000e06: 6918 ldr r0, [r3, #16] +10000e08: 7199 strb r1, [r3, #6] +10000e0a: e8c0 2f8f stlb r2, [r0] +10000e0e: f38c 8810 msr PRIMASK, ip +10000e12: 781c ldrb r4, [r3, #0] +10000e14: 68da ldr r2, [r3, #12] +10000e16: 4608 mov r0, r1 +10000e18: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000e1c: 40a1 lsls r1, r4 +10000e1e: 6059 str r1, [r3, #4] +10000e20: bd10 pop {r4, pc} +10000e22: 2000 movs r0, #0 +10000e24: 4770 bx lr +10000e26: bf00 nop + +10000e28 : +10000e28: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000e2c: b082 sub sp, #8 +10000e2e: 4606 mov r6, r0 +10000e30: f000 f8ec bl 1000100c +10000e34: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000e38: 4604 mov r4, r0 +10000e3a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000e3e: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000e42: fbe6 4103 umlal r4, r1, r6, r3 +10000e46: 42a0 cmp r0, r4 +10000e48: eb72 0301 sbcs.w r3, r2, r1 +10000e4c: bf3a itte cc +10000e4e: 4604 movcc r4, r0 +10000e50: 4615 movcc r5, r2 +10000e52: 460d movcs r5, r1 +10000e54: 1fa6 subs r6, r4, #6 +10000e56: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000e5a: 42b4 cmp r4, r6 +10000e5c: eb75 0307 sbcs.w r3, r5, r7 +10000e60: bf3c itt cc +10000e62: 2600 movcc r6, #0 +10000e64: 4637 movcc r7, r6 +10000e66: f000 f8d1 bl 1000100c +10000e6a: 1a30 subs r0, r6, r0 +10000e6c: eb67 0101 sbc.w r1, r7, r1 +10000e70: 2801 cmp r0, #1 +10000e72: f171 0100 sbcs.w r1, r1, #0 +10000e76: da06 bge.n 10000e86 +10000e78: 4620 mov r0, r4 +10000e7a: 4629 mov r1, r5 +10000e7c: b002 add sp, #8 +10000e7e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000e82: f000 b8fb b.w 1000107c +10000e86: f000 f8c1 bl 1000100c +10000e8a: 4286 cmp r6, r0 +10000e8c: eb67 0101 sbc.w r1, r7, r1 +10000e90: 2900 cmp r1, #0 +10000e92: db0a blt.n 10000eaa +10000e94: 2100 movs r1, #0 +10000e96: 4b17 ldr r3, [pc, #92] @ (10000ef4 ) +10000e98: 4632 mov r2, r6 +10000e9a: 9300 str r3, [sp, #0] +10000e9c: 4816 ldr r0, [pc, #88] @ (10000ef8 ) +10000e9e: 463b mov r3, r7 +10000ea0: 9101 str r1, [sp, #4] +10000ea2: f7ff ff1d bl 10000ce0 +10000ea6: 3001 adds r0, #1 +10000ea8: d0e6 beq.n 10000e78 +10000eaa: f04f 0c00 mov.w ip, #0 +10000eae: 4a13 ldr r2, [pc, #76] @ (10000efc ) +10000eb0: 4913 ldr r1, [pc, #76] @ (10000f00 ) +10000eb2: 6a53 ldr r3, [r2, #36] @ 0x24 +10000eb4: 429f cmp r7, r3 +10000eb6: d804 bhi.n 10000ec2 +10000eb8: 6a90 ldr r0, [r2, #40] @ 0x28 +10000eba: 42b0 cmp r0, r6 +10000ebc: d2dc bcs.n 10000e78 +10000ebe: 429f cmp r7, r3 +10000ec0: d1da bne.n 10000e78 +10000ec2: 680b ldr r3, [r1, #0] +10000ec4: f3ef 8010 mrs r0, PRIMASK +10000ec8: b672 cpsid i +10000eca: e8d3 8fcf ldaexb r8, [r3] +10000ece: f05f 0e01 movs.w lr, #1 +10000ed2: f1b8 0f00 cmp.w r8, #0 +10000ed6: d1f8 bne.n 10000eca +10000ed8: e8c3 ef48 strexb r8, lr, [r3] +10000edc: f1b8 0f00 cmp.w r8, #0 +10000ee0: d1f3 bne.n 10000eca +10000ee2: f3bf 8f5f dmb sy +10000ee6: 680b ldr r3, [r1, #0] +10000ee8: e8c3 cf8f stlb ip, [r3] +10000eec: f380 8810 msr PRIMASK, r0 +10000ef0: bf20 wfe +10000ef2: e7de b.n 10000eb2 +10000ef4: 100008b1 .word 0x100008b1 +10000ef8: 20000274 .word 0x20000274 +10000efc: 400b0000 .word 0x400b0000 +10000f00: 200004d0 .word 0x200004d0 + +10000f04 : +10000f04: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000f08: 4606 mov r6, r0 +10000f0a: 460d mov r5, r1 +10000f0c: b083 sub sp, #12 +10000f0e: f3ef 8405 mrs r4, IPSR +10000f12: b2e4 uxtb r4, r4 +10000f14: b13c cbz r4, 10000f26 +10000f16: 4b2d ldr r3, [pc, #180] @ (10000fcc ) +10000f18: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f1a: 42aa cmp r2, r5 +10000f1c: d21c bcs.n 10000f58 +10000f1e: 2000 movs r0, #0 +10000f20: b003 add sp, #12 +10000f22: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000f26: 4f2a ldr r7, [pc, #168] @ (10000fd0 ) +10000f28: f8d7 900c ldr.w r9, [r7, #12] +10000f2c: f897 8000 ldrb.w r8, [r7] +10000f30: 4648 mov r0, r9 +10000f32: f000 f863 bl 10000ffc +10000f36: f108 0804 add.w r8, r8, #4 +10000f3a: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000f3e: 1a1b subs r3, r3, r0 +10000f40: 1a30 subs r0, r6, r0 +10000f42: eb65 0101 sbc.w r1, r5, r1 +10000f46: 4298 cmp r0, r3 +10000f48: f171 0100 sbcs.w r1, r1, #0 +10000f4c: db10 blt.n 10000f70 +10000f4e: bf20 wfe +10000f50: 4b1e ldr r3, [pc, #120] @ (10000fcc ) +10000f52: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f54: 42aa cmp r2, r5 +10000f56: d3e2 bcc.n 10000f1e +10000f58: bf14 ite ne +10000f5a: 2401 movne r4, #1 +10000f5c: 2400 moveq r4, #0 +10000f5e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000f60: 42b3 cmp r3, r6 +10000f62: bf34 ite cc +10000f64: 4620 movcc r0, r4 +10000f66: f044 0001 orrcs.w r0, r4, #1 +10000f6a: b003 add sp, #12 +10000f6c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000f70: f000 f84c bl 1000100c +10000f74: 4286 cmp r6, r0 +10000f76: eb65 0101 sbc.w r1, r5, r1 +10000f7a: 2900 cmp r1, #0 +10000f7c: db14 blt.n 10000fa8 +10000f7e: 4b15 ldr r3, [pc, #84] @ (10000fd4 ) +10000f80: 4638 mov r0, r7 +10000f82: e9cd 3400 strd r3, r4, [sp] +10000f86: 4632 mov r2, r6 +10000f88: 462b mov r3, r5 +10000f8a: f7ff fea9 bl 10000ce0 +10000f8e: 1e01 subs r1, r0, #0 +10000f90: dd0a ble.n 10000fa8 +10000f92: 4b0e ldr r3, [pc, #56] @ (10000fcc ) +10000f94: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f96: 42aa cmp r2, r5 +10000f98: d316 bcc.n 10000fc8 +10000f9a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000f9c: 42b3 cmp r3, r6 +10000f9e: d311 bcc.n 10000fc4 +10000fa0: 480b ldr r0, [pc, #44] @ (10000fd0 ) +10000fa2: f7ff ff01 bl 10000da8 +10000fa6: e7b6 b.n 10000f16 +10000fa8: 4b08 ldr r3, [pc, #32] @ (10000fcc ) +10000faa: 6a5c ldr r4, [r3, #36] @ 0x24 +10000fac: 42ac cmp r4, r5 +10000fae: d3b6 bcc.n 10000f1e +10000fb0: 1b64 subs r4, r4, r5 +10000fb2: bf18 it ne +10000fb4: 2401 movne r4, #1 +10000fb6: 6a9b ldr r3, [r3, #40] @ 0x28 +10000fb8: 42b3 cmp r3, r6 +10000fba: bf34 ite cc +10000fbc: 4620 movcc r0, r4 +10000fbe: f044 0001 orrcs.w r0, r4, #1 +10000fc2: e7ad b.n 10000f20 +10000fc4: 42aa cmp r2, r5 +10000fc6: d1eb bne.n 10000fa0 +10000fc8: bf20 wfe +10000fca: e7e9 b.n 10000fa0 +10000fcc: 400b0000 .word 0x400b0000 +10000fd0: 20000274 .word 0x20000274 +10000fd4: 100008b1 .word 0x100008b1 + +10000fd8 : +10000fd8: b410 push {r4} +10000fda: 4b05 ldr r3, [pc, #20] @ (10000ff0 ) +10000fdc: 4c05 ldr r4, [pc, #20] @ (10000ff4 ) +10000fde: 4a06 ldr r2, [pc, #24] @ (10000ff8 ) +10000fe0: 42a0 cmp r0, r4 +10000fe2: bf14 ite ne +10000fe4: 4618 movne r0, r3 +10000fe6: 1c58 addeq r0, r3, #1 +10000fe8: f85d 4b04 ldr.w r4, [sp], #4 +10000fec: f7ff ba2a b.w 10000444 +10000ff0: 20000458 .word 0x20000458 +10000ff4: 400b8000 .word 0x400b8000 +10000ff8: 10001c80 .word 0x10001c80 + +10000ffc : +10000ffc: 4603 mov r3, r0 +10000ffe: 6a41 ldr r1, [r0, #36] @ 0x24 +10001000: 460a mov r2, r1 +10001002: 6a98 ldr r0, [r3, #40] @ 0x28 +10001004: 6a59 ldr r1, [r3, #36] @ 0x24 +10001006: 428a cmp r2, r1 +10001008: d1fa bne.n 10001000 +1000100a: 4770 bx lr + +1000100c : +1000100c: 4b03 ldr r3, [pc, #12] @ (1000101c ) +1000100e: 6a59 ldr r1, [r3, #36] @ 0x24 +10001010: 460a mov r2, r1 +10001012: 6a98 ldr r0, [r3, #40] @ 0x28 +10001014: 6a59 ldr r1, [r3, #36] @ 0x24 +10001016: 4291 cmp r1, r2 +10001018: d1fa bne.n 10001010 +1000101a: 4770 bx lr +1000101c: 400b0000 .word 0x400b0000 + +10001020 : +10001020: b430 push {r4, r5} +10001022: 4a15 ldr r2, [pc, #84] @ (10001078 ) +10001024: 6a53 ldr r3, [r2, #36] @ 0x24 +10001026: 469c mov ip, r3 +10001028: 6a94 ldr r4, [r2, #40] @ 0x28 +1000102a: 6a53 ldr r3, [r2, #36] @ 0x24 +1000102c: 4563 cmp r3, ip +1000102e: d1fa bne.n 10001026 +10001030: 1902 adds r2, r0, r4 +10001032: 4159 adcs r1, r3 +10001034: f04f 0500 mov.w r5, #0 +10001038: bf28 it cs +1000103a: 2501 movcs r5, #1 +1000103c: 4b0e ldr r3, [pc, #56] @ (10001078 ) +1000103e: 6a5b ldr r3, [r3, #36] @ 0x24 +10001040: b1b5 cbz r5, 10001070 +10001042: 1c5a adds r2, r3, #1 +10001044: bf08 it eq +10001046: 461a moveq r2, r3 +10001048: d008 beq.n 1000105c +1000104a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000104e: 460a mov r2, r1 +10001050: 4809 ldr r0, [pc, #36] @ (10001078 ) +10001052: 6a43 ldr r3, [r0, #36] @ 0x24 +10001054: 428b cmp r3, r1 +10001056: d3fc bcc.n 10001052 +10001058: 428b cmp r3, r1 +1000105a: d107 bne.n 1000106c +1000105c: 4906 ldr r1, [pc, #24] @ (10001078 ) +1000105e: e002 b.n 10001066 +10001060: 6a48 ldr r0, [r1, #36] @ 0x24 +10001062: 4298 cmp r0, r3 +10001064: d102 bne.n 1000106c +10001066: 6a88 ldr r0, [r1, #40] @ 0x28 +10001068: 4290 cmp r0, r2 +1000106a: d3f9 bcc.n 10001060 +1000106c: bc30 pop {r4, r5} +1000106e: 4770 bx lr +10001070: 4299 cmp r1, r3 +10001072: d8ed bhi.n 10001050 +10001074: e7f0 b.n 10001058 +10001076: bf00 nop +10001078: 400b0000 .word 0x400b0000 + +1000107c : +1000107c: 4a07 ldr r2, [pc, #28] @ (1000109c ) +1000107e: 6a53 ldr r3, [r2, #36] @ 0x24 +10001080: 4299 cmp r1, r3 +10001082: d8fc bhi.n 1000107e +10001084: 4299 cmp r1, r3 +10001086: d107 bne.n 10001098 +10001088: 4b04 ldr r3, [pc, #16] @ (1000109c ) +1000108a: e002 b.n 10001092 +1000108c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000108e: 4291 cmp r1, r2 +10001090: d102 bne.n 10001098 +10001092: 6a9a ldr r2, [r3, #40] @ 0x28 +10001094: 4290 cmp r0, r2 +10001096: d8f9 bhi.n 1000108c +10001098: 4770 bx lr +1000109a: bf00 nop +1000109c: 400b0000 .word 0x400b0000 + +100010a0 : +100010a0: b5f8 push {r3, r4, r5, r6, r7, lr} +100010a2: 4605 mov r5, r0 +100010a4: 2006 movs r0, #6 +100010a6: 460e mov r6, r1 +100010a8: f000 f8e4 bl 10001274 +100010ac: 2800 cmp r0, #0 +100010ae: d042 beq.n 10001136 +100010b0: 4a35 ldr r2, [pc, #212] @ (10001188 ) +100010b2: 4836 ldr r0, [pc, #216] @ (1000118c ) +100010b4: 4295 cmp r5, r2 +100010b6: bf14 ite ne +100010b8: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +100010bc: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +100010c0: 4b33 ldr r3, [pc, #204] @ (10001190 ) +100010c2: 4934 ldr r1, [pc, #208] @ (10001194 ) +100010c4: 6002 str r2, [r0, #0] +100010c6: 601a str r2, [r3, #0] +100010c8: 688c ldr r4, [r1, #8] +100010ca: ea32 0404 bics.w r4, r2, r4 +100010ce: d1fb bne.n 100010c8 +100010d0: 4b2d ldr r3, [pc, #180] @ (10001188 ) +100010d2: f44f 7180 mov.w r1, #256 @ 0x100 +100010d6: 1aeb subs r3, r5, r3 +100010d8: fab3 f383 clz r3, r3 +100010dc: 4a2e ldr r2, [pc, #184] @ (10001198 ) +100010de: 095b lsrs r3, r3, #5 +100010e0: 2006 movs r0, #6 +100010e2: f822 1013 strh.w r1, [r2, r3, lsl #1] +100010e6: f000 f8c5 bl 10001274 +100010ea: 00c3 lsls r3, r0, #3 +100010ec: fbb3 f3f6 udiv r3, r3, r6 +100010f0: 3301 adds r3, #1 +100010f2: 09da lsrs r2, r3, #7 +100010f4: d120 bne.n 10001138 +100010f6: 2640 movs r6, #64 @ 0x40 +100010f8: 2101 movs r1, #1 +100010fa: 6269 str r1, [r5, #36] @ 0x24 +100010fc: 62aa str r2, [r5, #40] @ 0x28 +100010fe: 6b2f ldr r7, [r5, #48] @ 0x30 +10001100: 07fb lsls r3, r7, #31 +10001102: d422 bmi.n 1000114a +10001104: 462b mov r3, r5 +10001106: 2200 movs r2, #0 +10001108: f853 1f2c ldr.w r1, [r3, #44]! +1000110c: 2006 movs r0, #6 +1000110e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10001112: 6022 str r2, [r4, #0] +10001114: 632f str r7, [r5, #48] @ 0x30 +10001116: f000 f8ad bl 10001274 +1000111a: f240 3101 movw r1, #769 @ 0x301 +1000111e: 2203 movs r2, #3 +10001120: 0080 lsls r0, r0, #2 +10001122: fbb0 f0f6 udiv r0, r0, r6 +10001126: 6aeb ldr r3, [r5, #44] @ 0x2c +10001128: f083 0370 eor.w r3, r3, #112 @ 0x70 +1000112c: f003 037e and.w r3, r3, #126 @ 0x7e +10001130: 6023 str r3, [r4, #0] +10001132: 6329 str r1, [r5, #48] @ 0x30 +10001134: 64aa str r2, [r5, #72] @ 0x48 +10001136: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001138: f64f 71fe movw r1, #65534 @ 0xfffe +1000113c: 428a cmp r2, r1 +1000113e: d91b bls.n 10001178 +10001140: 4622 mov r2, r4 +10001142: f64f 71ff movw r1, #65535 @ 0xffff +10001146: 4e15 ldr r6, [pc, #84] @ (1000119c ) +10001148: e7d7 b.n 100010fa +1000114a: f240 3201 movw r2, #769 @ 0x301 +1000114e: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10001152: 631a str r2, [r3, #48] @ 0x30 +10001154: 6a6b ldr r3, [r5, #36] @ 0x24 +10001156: 6aac ldr r4, [r5, #40] @ 0x28 +10001158: 2006 movs r0, #6 +1000115a: eb04 1483 add.w r4, r4, r3, lsl #6 +1000115e: f000 f889 bl 10001274 +10001162: 4b0f ldr r3, [pc, #60] @ (100011a0 ) +10001164: 02a4 lsls r4, r4, #10 +10001166: fba3 2300 umull r2, r3, r3, r0 +1000116a: 0adb lsrs r3, r3, #11 +1000116c: 2100 movs r1, #0 +1000116e: fbb4 f0f3 udiv r0, r4, r3 +10001172: f7ff ff55 bl 10001020 +10001176: e7c5 b.n 10001104 +10001178: f3c3 0345 ubfx r3, r3, #1, #6 +1000117c: 4611 mov r1, r2 +1000117e: eb03 1682 add.w r6, r3, r2, lsl #6 +10001182: 461a mov r2, r3 +10001184: e7b9 b.n 100010fa +10001186: bf00 nop +10001188: 40078000 .word 0x40078000 +1000118c: 40022000 .word 0x40022000 +10001190: 40023000 .word 0x40023000 +10001194: 40020000 .word 0x40020000 +10001198: 200004d4 .word 0x200004d4 +1000119c: 003fffc0 .word 0x003fffc0 +100011a0: 8f2b7b75 .word 0x8f2b7b75 + +100011a4 : +100011a4: eb00 0c40 add.w ip, r0, r0, lsl #1 +100011a8: ea4f 0c8c mov.w ip, ip, lsl #2 +100011ac: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +100011b0: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +100011b4: b5f0 push {r4, r5, r6, r7, lr} +100011b6: 4616 mov r6, r2 +100011b8: f8dc 2004 ldr.w r2, [ip, #4] +100011bc: 1f05 subs r5, r0, #4 +100011be: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +100011c2: bf38 it cc +100011c4: f44f 3280 movcc.w r2, #65536 @ 0x10000 +100011c8: b2ed uxtb r5, r5 +100011ca: bf38 it cc +100011cc: f8cc 2004 strcc.w r2, [ip, #4] +100011d0: 2d01 cmp r5, #1 +100011d2: d92a bls.n 1000122a +100011d4: f44f 6700 mov.w r7, #2048 @ 0x800 +100011d8: 4c25 ldr r4, [pc, #148] @ (10001270 ) +100011da: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100011de: 6017 str r7, [r2, #0] +100011e0: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100011e4: b9b2 cbnz r2, 10001214 +100011e6: f8dc 2000 ldr.w r2, [ip] +100011ea: 2d01 cmp r5, #1 +100011ec: ea82 1246 eor.w r2, r2, r6, lsl #5 +100011f0: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100011f4: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100011f8: 6032 str r2, [r6, #0] +100011fa: d92a bls.n 10001252 +100011fc: f44f 6100 mov.w r1, #2048 @ 0x800 +10001200: f844 3020 str.w r3, [r4, r0, lsl #2] +10001204: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001208: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1000120c: 6011 str r1, [r2, #0] +1000120e: f8cc 3004 str.w r3, [ip, #4] +10001212: bdf0 pop {r4, r5, r6, r7, pc} +10001214: 6967 ldr r7, [r4, #20] +10001216: fbb7 fef2 udiv lr, r7, r2 +1000121a: f10e 0e01 add.w lr, lr, #1 +1000121e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10001222: f1be 0e03 subs.w lr, lr, #3 +10001226: d2fc bcs.n 10001222 +10001228: e7dd b.n 100011e6 +1000122a: 2901 cmp r1, #1 +1000122c: d1d2 bne.n 100011d4 +1000122e: 2403 movs r4, #3 +10001230: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10001234: 6014 str r4, [r2, #0] +10001236: f8dc 2008 ldr.w r2, [ip, #8] +1000123a: 07d2 lsls r2, r2, #31 +1000123c: d5fb bpl.n 10001236 +1000123e: f8dc 2000 ldr.w r2, [ip] +10001242: 4c0b ldr r4, [pc, #44] @ (10001270 ) +10001244: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001248: f002 02e0 and.w r2, r2, #224 @ 0xe0 +1000124c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001250: 6032 str r2, [r6, #0] +10001252: 2201 movs r2, #1 +10001254: f8dc 5000 ldr.w r5, [ip] +10001258: 404d eors r5, r1 +1000125a: f005 0503 and.w r5, r5, #3 +1000125e: 6035 str r5, [r6, #0] +10001260: fa02 f101 lsl.w r1, r2, r1 +10001264: f8dc 2008 ldr.w r2, [ip, #8] +10001268: 420a tst r2, r1 +1000126a: d0fb beq.n 10001264 +1000126c: e7c6 b.n 100011fc +1000126e: bf00 nop +10001270: 2000045c .word 0x2000045c + +10001274 : +10001274: 4b01 ldr r3, [pc, #4] @ (1000127c ) +10001276: f853 0020 ldr.w r0, [r3, r0, lsl #2] +1000127a: 4770 bx lr +1000127c: 2000045c .word 0x2000045c + +10001280 : +10001280: b470 push {r4, r5, r6} +10001282: 9d03 ldr r5, [sp, #12] +10001284: 6804 ldr r4, [r0, #0] +10001286: 032d lsls r5, r5, #12 +10001288: ea45 4503 orr.w r5, r5, r3, lsl #16 +1000128c: 4b1b ldr r3, [pc, #108] @ (100012fc ) +1000128e: 2c00 cmp r4, #0 +10001290: fbb3 f3f1 udiv r3, r3, r1 +10001294: fbb2 f6f3 udiv r6, r2, r3 +10001298: db1f blt.n 100012da +1000129a: 4a19 ldr r2, [pc, #100] @ (10001300 ) +1000129c: 4b19 ldr r3, [pc, #100] @ (10001304 ) +1000129e: 4290 cmp r0, r2 +100012a0: bf14 ite ne +100012a2: f44f 4280 movne.w r2, #16384 @ 0x4000 +100012a6: f44f 4200 moveq.w r2, #32768 @ 0x8000 +100012aa: 4c17 ldr r4, [pc, #92] @ (10001308 ) +100012ac: 601a str r2, [r3, #0] +100012ae: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100012b2: 601a str r2, [r3, #0] +100012b4: 68a3 ldr r3, [r4, #8] +100012b6: ea32 0303 bics.w r3, r2, r3 +100012ba: d1fb bne.n 100012b4 +100012bc: 2221 movs r2, #33 @ 0x21 +100012be: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100012c2: 3304 adds r3, #4 +100012c4: 6001 str r1, [r0, #0] +100012c6: 6086 str r6, [r0, #8] +100012c8: 601a str r2, [r3, #0] +100012ca: 6802 ldr r2, [r0, #0] +100012cc: 2a00 cmp r2, #0 +100012ce: dafc bge.n 100012ca +100012d0: 2208 movs r2, #8 +100012d2: 60c5 str r5, [r0, #12] +100012d4: 601a str r2, [r3, #0] +100012d6: bc70 pop {r4, r5, r6} +100012d8: 4770 bx lr +100012da: 6803 ldr r3, [r0, #0] +100012dc: f003 033f and.w r3, r3, #63 @ 0x3f +100012e0: 428b cmp r3, r1 +100012e2: d1da bne.n 1000129a +100012e4: 6883 ldr r3, [r0, #8] +100012e6: f3c3 030b ubfx r3, r3, #0, #12 +100012ea: 42b3 cmp r3, r6 +100012ec: d1d5 bne.n 1000129a +100012ee: 68c3 ldr r3, [r0, #12] +100012f0: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100012f4: 42ab cmp r3, r5 +100012f6: d1d0 bne.n 1000129a +100012f8: e7ed b.n 100012d6 +100012fa: bf00 nop +100012fc: 00b71b00 .word 0x00b71b00 +10001300: 40058000 .word 0x40058000 +10001304: 40022000 .word 0x40022000 +10001308: 40020000 .word 0x40020000 + +1000130c : +1000130c: 2301 movs r3, #1 +1000130e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001312: 0080 lsls r0, r0, #2 +10001314: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001318: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000131c: 6041 str r1, [r0, #4] +1000131e: 6003 str r3, [r0, #0] +10001320: 4770 bx lr +10001322: bf00 nop + +10001324 : +10001324: 2300 movs r3, #0 +10001326: 8adb ldrh r3, [r3, #22] +10001328: 2200 movs r2, #0 +1000132a: e842 f200 tt r2, r2 +1000132e: 0252 lsls r2, r2, #9 +10001330: d401 bmi.n 10001336 +10001332: 2110 movs r1, #16 +10001334: 4718 bx r3 +10001336: 2104 movs r1, #4 +10001338: 4718 bx r3 +1000133a: bf00 nop + +1000133c : +1000133c: 4a03 ldr r2, [pc, #12] @ (1000134c ) +1000133e: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10001342: 2b00 cmp r3, #0 +10001344: d0fb beq.n 1000133e +10001346: f3bf 8f5f dmb sy +1000134a: 4770 bx lr +1000134c: 400e0000 .word 0x400e0000 + +10001350 : +10001350: 2100 movs r1, #0 +10001352: 4b04 ldr r3, [pc, #16] @ (10001364 ) +10001354: 4a04 ldr r2, [pc, #16] @ (10001368 ) +10001356: f3bf 8f5f dmb sy +1000135a: f843 1b04 str.w r1, [r3], #4 +1000135e: 4293 cmp r3, r2 +10001360: d1f9 bne.n 10001356 +10001362: 4770 bx lr +10001364: 400e080c .word 0x400e080c +10001368: 400e082c .word 0x400e082c + +1000136c : +1000136c: b410 push {r4} +1000136e: f44f 708d mov.w r0, #282 @ 0x11a +10001372: f44f 642a mov.w r4, #2720 @ 0xaa0 +10001376: 4a06 ldr r2, [pc, #24] @ (10001390 ) +10001378: 4b06 ldr r3, [pc, #24] @ (10001394 ) +1000137a: 4907 ldr r1, [pc, #28] @ (10001398 ) +1000137c: 6014 str r4, [r2, #0] +1000137e: 60d0 str r0, [r2, #12] +10001380: 6019 str r1, [r3, #0] +10001382: 6853 ldr r3, [r2, #4] +10001384: 2b00 cmp r3, #0 +10001386: dafc bge.n 10001382 +10001388: f85d 4b04 ldr.w r4, [sp], #4 +1000138c: 4770 bx lr +1000138e: bf00 nop +10001390: 40048000 .word 0x40048000 +10001394: 4004a000 .word 0x4004a000 +10001398: 00fab000 .word 0x00fab000 + +1000139c : +1000139c: 4770 bx lr +1000139e: bf00 nop + +100013a0 : +100013a0: b508 push {r3, lr} +100013a2: 4801 ldr r0, [pc, #4] @ (100013a8 ) +100013a4: f7ff f836 bl 10000414 +100013a8: 10001ca4 .word 0x10001ca4 + +100013ac : +100013ac: b538 push {r3, r4, r5, lr} +100013ae: 4c05 ldr r4, [pc, #20] @ (100013c4 ) +100013b0: 4d05 ldr r5, [pc, #20] @ (100013c8 ) +100013b2: 42ac cmp r4, r5 +100013b4: d204 bcs.n 100013c0 +100013b6: f854 3b04 ldr.w r3, [r4], #4 +100013ba: 4798 blx r3 +100013bc: 42ac cmp r4, r5 +100013be: d3fa bcc.n 100013b6 +100013c0: bd38 pop {r3, r4, r5, pc} +100013c2: bf00 nop +100013c4: 10001c18 .word 0x10001c18 +100013c8: 10001c58 .word 0x10001c58 + +100013cc : +100013cc: b410 push {r4} +100013ce: 4807 ldr r0, [pc, #28] @ (100013ec ) +100013d0: 4c07 ldr r4, [pc, #28] @ (100013f0 ) +100013d2: 4b08 ldr r3, [pc, #32] @ (100013f4 ) +100013d4: 4a08 ldr r2, [pc, #32] @ (100013f8 ) +100013d6: 4909 ldr r1, [pc, #36] @ (100013fc ) +100013d8: 6004 str r4, [r0, #0] +100013da: 601a str r2, [r3, #0] +100013dc: 688b ldr r3, [r1, #8] +100013de: ea32 0303 bics.w r3, r2, r3 +100013e2: d1fb bne.n 100013dc +100013e4: f85d 4b04 ldr.w r4, [sp], #4 +100013e8: 4770 bx lr +100013ea: bf00 nop +100013ec: 40022000 .word 0x40022000 +100013f0: efef3b7f .word 0xefef3b7f +100013f4: 40023000 .word 0x40023000 +100013f8: 03f3fff6 .word 0x03f3fff6 +100013fc: 40020000 .word 0x40020000 + +10001400 : +10001400: 4b04 ldr r3, [pc, #16] @ (10001414 ) +10001402: 6cdb ldr r3, [r3, #76] @ 0x4c +10001404: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001408: d103 bne.n 10001412 +1000140a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000140e: 4b02 ldr r3, [pc, #8] @ (10001418 ) +10001410: 64da str r2, [r3, #76] @ 0x4c +10001412: 4770 bx lr +10001414: 50110000 .word 0x50110000 +10001418: 50112000 .word 0x50112000 + +1000141c : +1000141c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001420: 4b04 ldr r3, [pc, #16] @ (10001434 ) +10001422: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001426: 430b orrs r3, r1 +10001428: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000142c: ee10 0430 dcp_rcmp r0 +10001430: 4770 bx lr +10001432: bf00 nop +10001434: 00300303 .word 0x00300303 + +10001438 : +10001438: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +1000143c: 4b04 ldr r3, [pc, #16] @ (10001450 ) +1000143e: 4a05 ldr r2, [pc, #20] @ (10001454 ) +10001440: 6019 str r1, [r3, #0] +10001442: 6893 ldr r3, [r2, #8] +10001444: 43db mvns r3, r3 +10001446: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +1000144a: d1fa bne.n 10001442 +1000144c: 4770 bx lr +1000144e: bf00 nop +10001450: 40023000 .word 0x40023000 +10001454: 40020000 .word 0x40020000 + +10001458 : +10001458: b510 push {r4, lr} +1000145a: f245 2053 movw r0, #21075 @ 0x5253 +1000145e: f7ff ff61 bl 10001324 +10001462: e8bd 4010 ldmia.w sp!, {r4, lr} +10001466: 4603 mov r3, r0 +10001468: 2004 movs r0, #4 +1000146a: 4718 bx r3 + +1000146c : +1000146c: b510 push {r4, lr} +1000146e: f245 2053 movw r0, #21075 @ 0x5253 +10001472: f7ff ff57 bl 10001324 +10001476: e8bd 4010 ldmia.w sp!, {r4, lr} +1000147a: 4603 mov r3, r0 +1000147c: 2001 movs r0, #1 +1000147e: 4718 bx r3 + +10001480 : +10001480: f7ff b820 b.w 100004c4 + +10001484 : +10001484: 4914 ldr r1, [pc, #80] @ (100014d8 ) +10001486: 4b15 ldr r3, [pc, #84] @ (100014dc ) +10001488: b570 push {r4, r5, r6, lr} +1000148a: 1a5c subs r4, r3, r1 +1000148c: 10a6 asrs r6, r4, #2 +1000148e: 2e44 cmp r6, #68 @ 0x44 +10001490: 4632 mov r2, r6 +10001492: bf28 it cs +10001494: 2244 movcs r2, #68 @ 0x44 +10001496: 4d12 ldr r5, [pc, #72] @ (100014e0 ) +10001498: 0092 lsls r2, r2, #2 +1000149a: 4628 mov r0, r5 +1000149c: f000 fb0e bl 10001abc +100014a0: f5b4 7f86 cmp.w r4, #268 @ 0x10c +100014a4: d813 bhi.n 100014ce +100014a6: 4a0f ldr r2, [pc, #60] @ (100014e4 ) +100014a8: f1c6 0044 rsb r0, r6, #68 @ 0x44 +100014ac: d012 beq.n 100014d4 +100014ae: 192b adds r3, r5, r4 +100014b0: 0841 lsrs r1, r0, #1 +100014b2: eb03 01c1 add.w r1, r3, r1, lsl #3 +100014b6: e9c3 2200 strd r2, r2, [r3] +100014ba: 3308 adds r3, #8 +100014bc: 428b cmp r3, r1 +100014be: d1fa bne.n 100014b6 +100014c0: 07c3 lsls r3, r0, #31 +100014c2: d504 bpl.n 100014ce +100014c4: f020 0001 bic.w r0, r0, #1 +100014c8: 4430 add r0, r6 +100014ca: f845 2020 str.w r2, [r5, r0, lsl #2] +100014ce: 4b06 ldr r3, [pc, #24] @ (100014e8 ) +100014d0: 609d str r5, [r3, #8] +100014d2: bd70 pop {r4, r5, r6, pc} +100014d4: 2043 movs r0, #67 @ 0x43 +100014d6: e7f8 b.n 100014ca +100014d8: 10000000 .word 0x10000000 +100014dc: 10000110 .word 0x10000110 +100014e0: 20000000 .word 0x20000000 +100014e4: 10000111 .word 0x10000111 +100014e8: e000ed00 .word 0xe000ed00 + +100014ec : +100014ec: 2300 movs r3, #0 +100014ee: b570 push {r4, r5, r6, lr} +100014f0: 4c2b ldr r4, [pc, #172] @ (100015a0 ) +100014f2: b082 sub sp, #8 +100014f4: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100014f8: f7ff ff38 bl 1000136c +100014fc: 2201 movs r2, #1 +100014fe: 4b29 ldr r3, [pc, #164] @ (100015a4 ) +10001500: 63da str r2, [r3, #60] @ 0x3c +10001502: 6c63 ldr r3, [r4, #68] @ 0x44 +10001504: 2b01 cmp r3, #1 +10001506: d1fc bne.n 10001502 +10001508: 2103 movs r1, #3 +1000150a: 4a26 ldr r2, [pc, #152] @ (100015a4 ) +1000150c: 4b24 ldr r3, [pc, #144] @ (100015a0 ) +1000150e: 6311 str r1, [r2, #48] @ 0x30 +10001510: 6b9c ldr r4, [r3, #56] @ 0x38 +10001512: 2c01 cmp r4, #1 +10001514: d1fc bne.n 10001510 +10001516: 2602 movs r6, #2 +10001518: 2505 movs r5, #5 +1000151a: 4621 mov r1, r4 +1000151c: 2305 movs r3, #5 +1000151e: 4a22 ldr r2, [pc, #136] @ (100015a8 ) +10001520: 4822 ldr r0, [pc, #136] @ (100015ac ) +10001522: 9600 str r6, [sp, #0] +10001524: f7ff feac bl 10001280 +10001528: 4621 mov r1, r4 +1000152a: 462b mov r3, r5 +1000152c: 4a20 ldr r2, [pc, #128] @ (100015b0 ) +1000152e: 4821 ldr r0, [pc, #132] @ (100015b4 ) +10001530: 9500 str r5, [sp, #0] +10001532: f7ff fea5 bl 10001280 +10001536: 2200 movs r2, #0 +10001538: 2004 movs r0, #4 +1000153a: 4631 mov r1, r6 +1000153c: 4b1e ldr r3, [pc, #120] @ (100015b8 ) +1000153e: f7ff fe31 bl 100011a4 +10001542: 4621 mov r1, r4 +10001544: 4628 mov r0, r5 +10001546: 2200 movs r2, #0 +10001548: 4b1c ldr r3, [pc, #112] @ (100015bc ) +1000154a: f7ff fe2b bl 100011a4 +1000154e: 2200 movs r2, #0 +10001550: 2008 movs r0, #8 +10001552: 4611 mov r1, r2 +10001554: 4b1a ldr r3, [pc, #104] @ (100015c0 ) +10001556: f7ff fe25 bl 100011a4 +1000155a: 2200 movs r2, #0 +1000155c: 2009 movs r0, #9 +1000155e: 4611 mov r1, r2 +10001560: 4b17 ldr r3, [pc, #92] @ (100015c0 ) +10001562: f7ff fe1f bl 100011a4 +10001566: 2200 movs r2, #0 +10001568: 2006 movs r0, #6 +1000156a: 4611 mov r1, r2 +1000156c: 4b13 ldr r3, [pc, #76] @ (100015bc ) +1000156e: f7ff fe19 bl 100011a4 +10001572: 2200 movs r2, #0 +10001574: 4b11 ldr r3, [pc, #68] @ (100015bc ) +10001576: 2007 movs r0, #7 +10001578: 4611 mov r1, r2 +1000157a: f7ff fe13 bl 100011a4 +1000157e: 2004 movs r0, #4 +10001580: f7ff fe78 bl 10001274 +10001584: 2400 movs r4, #0 +10001586: 4b0f ldr r3, [pc, #60] @ (100015c4 ) +10001588: fba3 3500 umull r3, r5, r3, r0 +1000158c: 0cad lsrs r5, r5, #18 +1000158e: b2e0 uxtb r0, r4 +10001590: 4629 mov r1, r5 +10001592: 3401 adds r4, #1 +10001594: f7ff feba bl 1000130c +10001598: 2c06 cmp r4, #6 +1000159a: d1f8 bne.n 1000158e +1000159c: b002 add sp, #8 +1000159e: bd70 pop {r4, r5, r6, pc} +100015a0: 40010000 .word 0x40010000 +100015a4: 40013000 .word 0x40013000 +100015a8: 59682f00 .word 0x59682f00 +100015ac: 40050000 .word 0x40050000 +100015b0: 47868c00 .word 0x47868c00 +100015b4: 40058000 .word 0x40058000 +100015b8: 00b71b00 .word 0x00b71b00 +100015bc: 08f0d180 .word 0x08f0d180 +100015c0: 02dc6c00 .word 0x02dc6c00 +100015c4: 431bde83 .word 0x431bde83 + +100015c8 <_out_char>: +100015c8: b900 cbnz r0, 100015cc <_out_char+0x4> +100015ca: 4770 bx lr +100015cc: f000 b91c b.w 10001808 <__wrap_putchar> + +100015d0 : +100015d0: b510 push {r4, lr} +100015d2: 4b09 ldr r3, [pc, #36] @ (100015f8 ) +100015d4: b084 sub sp, #16 +100015d6: 681c ldr r4, [r3, #0] +100015d8: b14c cbz r4, 100015ee +100015da: 4603 mov r3, r0 +100015dc: 9100 str r1, [sp, #0] +100015de: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100015e2: a903 add r1, sp, #12 +100015e4: 4805 ldr r0, [pc, #20] @ (100015fc ) +100015e6: 47a0 blx r4 +100015e8: 2001 movs r0, #1 +100015ea: b004 add sp, #16 +100015ec: bd10 pop {r4, pc} +100015ee: f000 f94d bl 1000188c <__wrap_puts> +100015f2: 4620 mov r0, r4 +100015f4: b004 add sp, #16 +100015f6: bd10 pop {r4, pc} +100015f8: 2000048c .word 0x2000048c +100015fc: 100015c9 .word 0x100015c9 + +10001600 <_exit>: +10001600: be00 bkpt 0x0000 +10001602: e7fd b.n 10001600 <_exit> + +10001604 : +10001604: b508 push {r3, lr} +10001606: f7ff fffb bl 10001600 <_exit> +1000160a: bf00 nop + +1000160c : +1000160c: b538 push {r3, r4, r5, lr} +1000160e: 4c06 ldr r4, [pc, #24] @ (10001628 ) +10001610: 4d06 ldr r5, [pc, #24] @ (1000162c ) +10001612: f7ff fecb bl 100013ac +10001616: 42ac cmp r4, r5 +10001618: d204 bcs.n 10001624 +1000161a: f854 3b04 ldr.w r3, [r4], #4 +1000161e: 4798 blx r3 +10001620: 42ac cmp r4, r5 +10001622: d3fa bcc.n 1000161a +10001624: bd38 pop {r3, r4, r5, pc} +10001626: bf00 nop +10001628: 10001c58 .word 0x10001c58 +1000162c: 10001c5c .word 0x10001c5c + +10001630 : +10001630: 6803 ldr r3, [r0, #0] +10001632: 4608 mov r0, r1 +10001634: 4611 mov r1, r2 +10001636: 4718 bx r3 + +10001638 : +10001638: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000163c: 4615 mov r5, r2 +1000163e: 7d42 ldrb r2, [r0, #21] +10001640: 4607 mov r7, r0 +10001642: 4688 mov r8, r1 +10001644: 2a00 cmp r2, #0 +10001646: d046 beq.n 100016d6 +10001648: 2d00 cmp r5, #0 +1000164a: dd1d ble.n 10001688 +1000164c: 780b ldrb r3, [r1, #0] +1000164e: 2b0a cmp r3, #10 +10001650: d023 beq.n 1000169a +10001652: 2d01 cmp r5, #1 +10001654: f04f 0c00 mov.w ip, #0 +10001658: d018 beq.n 1000168c +1000165a: 4646 mov r6, r8 +1000165c: 2401 movs r4, #1 +1000165e: f816 2f01 ldrb.w r2, [r6, #1]! +10001662: 4621 mov r1, r4 +10001664: 2a0a cmp r2, #10 +10001666: f104 0401 add.w r4, r4, #1 +1000166a: d022 beq.n 100016b2 +1000166c: 42a5 cmp r5, r4 +1000166e: d1f6 bne.n 1000165e +10001670: 4565 cmp r5, ip +10001672: dc0b bgt.n 1000168c +10001674: eb08 0305 add.w r3, r8, r5 +10001678: f813 3c01 ldrb.w r3, [r3, #-1] +1000167c: f1a3 030d sub.w r3, r3, #13 +10001680: fab3 f383 clz r3, r3 +10001684: 095b lsrs r3, r3, #5 +10001686: 753b strb r3, [r7, #20] +10001688: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000168c: 683b ldr r3, [r7, #0] +1000168e: eba5 010c sub.w r1, r5, ip +10001692: eb08 000c add.w r0, r8, ip +10001696: 4798 blx r3 +10001698: e7ec b.n 10001674 +1000169a: 7d03 ldrb r3, [r0, #20] +1000169c: 2b00 cmp r3, #0 +1000169e: d1d8 bne.n 10001652 +100016a0: 6803 ldr r3, [r0, #0] +100016a2: 2102 movs r1, #2 +100016a4: 480f ldr r0, [pc, #60] @ (100016e4 ) +100016a6: 4798 blx r3 +100016a8: 2d01 cmp r5, #1 +100016aa: d0e3 beq.n 10001674 +100016ac: f04f 0c01 mov.w ip, #1 +100016b0: e7d3 b.n 1000165a +100016b2: f816 3c01 ldrb.w r3, [r6, #-1] +100016b6: 2b0d cmp r3, #13 +100016b8: d0d8 beq.n 1000166c +100016ba: 458c cmp ip, r1 +100016bc: eb08 000c add.w r0, r8, ip +100016c0: eba1 010c sub.w r1, r1, ip +100016c4: da01 bge.n 100016ca +100016c6: 683b ldr r3, [r7, #0] +100016c8: 4798 blx r3 +100016ca: 2102 movs r1, #2 +100016cc: 4805 ldr r0, [pc, #20] @ (100016e4 ) +100016ce: 683b ldr r3, [r7, #0] +100016d0: 4798 blx r3 +100016d2: 46a4 mov ip, r4 +100016d4: e7ca b.n 1000166c +100016d6: 4629 mov r1, r5 +100016d8: 4640 mov r0, r8 +100016da: 683b ldr r3, [r7, #0] +100016dc: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100016e0: 4718 bx r3 +100016e2: bf00 nop +100016e4: 10001d90 .word 0x10001d90 + +100016e8 : +100016e8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +100016ec: b082 sub sp, #8 +100016ee: 460d mov r5, r1 +100016f0: 4691 mov r9, r2 +100016f2: 461c mov r4, r3 +100016f4: 4606 mov r6, r0 +100016f6: f7ff fc89 bl 1000100c +100016fa: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +100016fe: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10001702: 4a2e ldr r2, [pc, #184] @ (100017bc ) +10001704: 1882 adds r2, r0, r2 +10001706: f141 0300 adc.w r3, r1, #0 +1000170a: 4594 cmp ip, r2 +1000170c: eb77 0103 sbcs.w r1, r7, r3 +10001710: bf3c itt cc +10001712: 4662 movcc r2, ip +10001714: 463b movcc r3, r7 +10001716: 482a ldr r0, [pc, #168] @ (100017c0 ) +10001718: f000 fa7a bl 10001c10 <__mutex_try_enter_block_until_veneer> +1000171c: 1c6b adds r3, r5, #1 +1000171e: 4680 mov r8, r0 +10001720: d040 beq.n 100017a4 +10001722: b30c cbz r4, 10001768 +10001724: 4f27 ldr r7, [pc, #156] @ (100017c4 ) +10001726: 4b28 ldr r3, [pc, #160] @ (100017c8 ) +10001728: 681c ldr r4, [r3, #0] +1000172a: b1b4 cbz r4, 1000175a +1000172c: f1b9 0f00 cmp.w r9, #0 +10001730: d11c bne.n 1000176c +10001732: f8df 909c ldr.w r9, [pc, #156] @ 100017d0 +10001736: e001 b.n 1000173c +10001738: 6924 ldr r4, [r4, #16] +1000173a: b174 cbz r4, 1000175a +1000173c: 6823 ldr r3, [r4, #0] +1000173e: 2b00 cmp r3, #0 +10001740: d0fa beq.n 10001738 +10001742: f8d9 3000 ldr.w r3, [r9] +10001746: b10b cbz r3, 1000174c +10001748: 429c cmp r4, r3 +1000174a: d1f5 bne.n 10001738 +1000174c: 4620 mov r0, r4 +1000174e: 462a mov r2, r5 +10001750: 4631 mov r1, r6 +10001752: 47b8 blx r7 +10001754: 6924 ldr r4, [r4, #16] +10001756: 2c00 cmp r4, #0 +10001758: d1f0 bne.n 1000173c +1000175a: f1b8 0f00 cmp.w r8, #0 +1000175e: d126 bne.n 100017ae +10001760: 4628 mov r0, r5 +10001762: b002 add sp, #8 +10001764: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10001768: 4f18 ldr r7, [pc, #96] @ (100017cc ) +1000176a: e7dc b.n 10001726 +1000176c: f04f 0a0a mov.w sl, #10 +10001770: f8df 905c ldr.w r9, [pc, #92] @ 100017d0 +10001774: e002 b.n 1000177c +10001776: 6924 ldr r4, [r4, #16] +10001778: 2c00 cmp r4, #0 +1000177a: d0ee beq.n 1000175a +1000177c: 6823 ldr r3, [r4, #0] +1000177e: 2b00 cmp r3, #0 +10001780: d0f9 beq.n 10001776 +10001782: f8d9 3000 ldr.w r3, [r9] +10001786: b10b cbz r3, 1000178c +10001788: 42a3 cmp r3, r4 +1000178a: d1f4 bne.n 10001776 +1000178c: 462a mov r2, r5 +1000178e: 4631 mov r1, r6 +10001790: 4620 mov r0, r4 +10001792: 47b8 blx r7 +10001794: 2201 movs r2, #1 +10001796: 4620 mov r0, r4 +10001798: f10d 0107 add.w r1, sp, #7 +1000179c: f88d a007 strb.w sl, [sp, #7] +100017a0: 47b8 blx r7 +100017a2: e7e8 b.n 10001776 +100017a4: 4630 mov r0, r6 +100017a6: f000 f9ff bl 10001ba8 +100017aa: 4605 mov r5, r0 +100017ac: e7b9 b.n 10001722 +100017ae: 4804 ldr r0, [pc, #16] @ (100017c0 ) +100017b0: f000 fa2a bl 10001c08 <__mutex_exit_veneer> +100017b4: 4628 mov r0, r5 +100017b6: b002 add sp, #8 +100017b8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100017bc: 000f4240 .word 0x000f4240 +100017c0: 200002a4 .word 0x200002a4 +100017c4: 10001639 .word 0x10001639 +100017c8: 20000484 .word 0x20000484 +100017cc: 10001631 .word 0x10001631 +100017d0: 20000488 .word 0x20000488 + +100017d4 : +100017d4: 4a08 ldr r2, [pc, #32] @ (100017f8 ) +100017d6: 6813 ldr r3, [r2, #0] +100017d8: b923 cbnz r3, 100017e4 +100017da: e00a b.n 100017f2 +100017dc: f103 0210 add.w r2, r3, #16 +100017e0: 691b ldr r3, [r3, #16] +100017e2: b133 cbz r3, 100017f2 +100017e4: 4283 cmp r3, r0 +100017e6: d1f9 bne.n 100017dc +100017e8: b929 cbnz r1, 100017f6 +100017ea: 6918 ldr r0, [r3, #16] +100017ec: 6010 str r0, [r2, #0] +100017ee: 6119 str r1, [r3, #16] +100017f0: 4770 bx lr +100017f2: b101 cbz r1, 100017f6 +100017f4: 6010 str r0, [r2, #0] +100017f6: 4770 bx lr +100017f8: 20000484 .word 0x20000484 + +100017fc : +100017fc: b508 push {r3, lr} +100017fe: f000 f933 bl 10001a68 +10001802: 2001 movs r0, #1 +10001804: bd08 pop {r3, pc} +10001806: bf00 nop + +10001808 <__wrap_putchar>: +10001808: b5f0 push {r4, r5, r6, r7, lr} +1000180a: b083 sub sp, #12 +1000180c: 4606 mov r6, r0 +1000180e: f88d 0007 strb.w r0, [sp, #7] +10001812: f7ff fbfb bl 1000100c +10001816: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000181a: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +1000181e: 4a17 ldr r2, [pc, #92] @ (1000187c <__wrap_putchar+0x74>) +10001820: 1882 adds r2, r0, r2 +10001822: f141 0300 adc.w r3, r1, #0 +10001826: 4295 cmp r5, r2 +10001828: eb74 0103 sbcs.w r1, r4, r3 +1000182c: bf3c itt cc +1000182e: 4623 movcc r3, r4 +10001830: 462a movcc r2, r5 +10001832: 4813 ldr r0, [pc, #76] @ (10001880 <__wrap_putchar+0x78>) +10001834: f000 f9ec bl 10001c10 <__mutex_try_enter_block_until_veneer> +10001838: 4b12 ldr r3, [pc, #72] @ (10001884 <__wrap_putchar+0x7c>) +1000183a: 4607 mov r7, r0 +1000183c: 681c ldr r4, [r3, #0] +1000183e: b19c cbz r4, 10001868 <__wrap_putchar+0x60> +10001840: 4d11 ldr r5, [pc, #68] @ (10001888 <__wrap_putchar+0x80>) +10001842: e001 b.n 10001848 <__wrap_putchar+0x40> +10001844: 6924 ldr r4, [r4, #16] +10001846: b17c cbz r4, 10001868 <__wrap_putchar+0x60> +10001848: 6823 ldr r3, [r4, #0] +1000184a: 2b00 cmp r3, #0 +1000184c: d0fa beq.n 10001844 <__wrap_putchar+0x3c> +1000184e: 682b ldr r3, [r5, #0] +10001850: b10b cbz r3, 10001856 <__wrap_putchar+0x4e> +10001852: 429c cmp r4, r3 +10001854: d1f6 bne.n 10001844 <__wrap_putchar+0x3c> +10001856: 4620 mov r0, r4 +10001858: 2201 movs r2, #1 +1000185a: f10d 0107 add.w r1, sp, #7 +1000185e: f7ff feeb bl 10001638 +10001862: 6924 ldr r4, [r4, #16] +10001864: 2c00 cmp r4, #0 +10001866: d1ef bne.n 10001848 <__wrap_putchar+0x40> +10001868: b917 cbnz r7, 10001870 <__wrap_putchar+0x68> +1000186a: 4630 mov r0, r6 +1000186c: b003 add sp, #12 +1000186e: bdf0 pop {r4, r5, r6, r7, pc} +10001870: 4803 ldr r0, [pc, #12] @ (10001880 <__wrap_putchar+0x78>) +10001872: f000 f9c9 bl 10001c08 <__mutex_exit_veneer> +10001876: 4630 mov r0, r6 +10001878: b003 add sp, #12 +1000187a: bdf0 pop {r4, r5, r6, r7, pc} +1000187c: 000f4240 .word 0x000f4240 +10001880: 200002a4 .word 0x200002a4 +10001884: 20000484 .word 0x20000484 +10001888: 20000488 .word 0x20000488 + +1000188c <__wrap_puts>: +1000188c: b538 push {r3, r4, r5, lr} +1000188e: 4604 mov r4, r0 +10001890: f000 f98a bl 10001ba8 +10001894: 2301 movs r3, #1 +10001896: 4605 mov r5, r0 +10001898: 461a mov r2, r3 +1000189a: 4620 mov r0, r4 +1000189c: 4629 mov r1, r5 +1000189e: f7ff ff23 bl 100016e8 +100018a2: 4b08 ldr r3, [pc, #32] @ (100018c4 <__wrap_puts+0x38>) +100018a4: 681c ldr r4, [r3, #0] +100018a6: b12c cbz r4, 100018b4 <__wrap_puts+0x28> +100018a8: 6863 ldr r3, [r4, #4] +100018aa: b12b cbz r3, 100018b8 <__wrap_puts+0x2c> +100018ac: 4798 blx r3 +100018ae: 6924 ldr r4, [r4, #16] +100018b0: 2c00 cmp r4, #0 +100018b2: d1f9 bne.n 100018a8 <__wrap_puts+0x1c> +100018b4: 4628 mov r0, r5 +100018b6: bd38 pop {r3, r4, r5, pc} +100018b8: 6924 ldr r4, [r4, #16] +100018ba: 2c00 cmp r4, #0 +100018bc: d1f4 bne.n 100018a8 <__wrap_puts+0x1c> +100018be: 4628 mov r0, r5 +100018c0: bd38 pop {r3, r4, r5, pc} +100018c2: bf00 nop +100018c4: 20000484 .word 0x20000484 + +100018c8 : +100018c8: f1b1 0c00 subs.w ip, r1, #0 +100018cc: dd1d ble.n 1000190a +100018ce: 4a0f ldr r2, [pc, #60] @ (1000190c ) +100018d0: 4b0f ldr r3, [pc, #60] @ (10001910 ) +100018d2: 6812 ldr r2, [r2, #0] +100018d4: b530 push {r4, r5, lr} +100018d6: 1ad3 subs r3, r2, r3 +100018d8: fab3 f383 clz r3, r3 +100018dc: 240d movs r4, #13 +100018de: 4d0d ldr r5, [pc, #52] @ (10001914 ) +100018e0: 095b lsrs r3, r3, #5 +100018e2: 1e41 subs r1, r0, #1 +100018e4: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +100018e8: 448c add ip, r1 +100018ea: f811 0f01 ldrb.w r0, [r1, #1]! +100018ee: 4586 cmp lr, r0 +100018f0: d006 beq.n 10001900 +100018f2: 6993 ldr r3, [r2, #24] +100018f4: 069b lsls r3, r3, #26 +100018f6: d4fc bmi.n 100018f2 +100018f8: 4561 cmp r1, ip +100018fa: 6010 str r0, [r2, #0] +100018fc: d1f5 bne.n 100018ea +100018fe: bd30 pop {r4, r5, pc} +10001900: 6993 ldr r3, [r2, #24] +10001902: 069d lsls r5, r3, #26 +10001904: d4fc bmi.n 10001900 +10001906: 6014 str r4, [r2, #0] +10001908: e7f3 b.n 100018f2 +1000190a: 4770 bx lr +1000190c: 200004d8 .word 0x200004d8 +10001910: 40078000 .word 0x40078000 +10001914: 200004d4 .word 0x200004d4 + +10001918 : +10001918: 4b22 ldr r3, [pc, #136] @ (100019a4 ) +1000191a: f1b1 0c00 subs.w ip, r1, #0 +1000191e: b410 push {r4} +10001920: 681c ldr r4, [r3, #0] +10001922: dd2e ble.n 10001982 +10001924: 4603 mov r3, r0 +10001926: 2000 movs r0, #0 +10001928: 4a1f ldr r2, [pc, #124] @ (100019a8 ) +1000192a: 1e59 subs r1, r3, #1 +1000192c: 6812 ldr r2, [r2, #0] +1000192e: 6993 ldr r3, [r2, #24] +10001930: 06db lsls r3, r3, #27 +10001932: d417 bmi.n 10001964 +10001934: 3001 adds r0, #1 +10001936: 6993 ldr r3, [r2, #24] +10001938: 06db lsls r3, r3, #27 +1000193a: d4fc bmi.n 10001936 +1000193c: 6813 ldr r3, [r2, #0] +1000193e: 4584 cmp ip, r0 +10001940: f801 3f01 strb.w r3, [r1, #1]! +10001944: d1f3 bne.n 1000192e +10001946: b14c cbz r4, 1000195c +10001948: 2150 movs r1, #80 @ 0x50 +1000194a: 4613 mov r3, r2 +1000194c: 6391 str r1, [r2, #56] @ 0x38 +1000194e: f853 2f34 ldr.w r2, [r3, #52]! +10001952: f002 0238 and.w r2, r2, #56 @ 0x38 +10001956: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000195a: 601a str r2, [r3, #0] +1000195c: 4660 mov r0, ip +1000195e: f85d 4b04 ldr.w r4, [sp], #4 +10001962: 4770 bx lr +10001964: b14c cbz r4, 1000197a +10001966: 2150 movs r1, #80 @ 0x50 +10001968: 4613 mov r3, r2 +1000196a: 6391 str r1, [r2, #56] @ 0x38 +1000196c: f853 2f34 ldr.w r2, [r3, #52]! +10001970: f002 0238 and.w r2, r2, #56 @ 0x38 +10001974: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001978: 601a str r2, [r3, #0] +1000197a: b178 cbz r0, 1000199c +1000197c: f85d 4b04 ldr.w r4, [sp], #4 +10001980: 4770 bx lr +10001982: b15c cbz r4, 1000199c +10001984: 4b08 ldr r3, [pc, #32] @ (100019a8 ) +10001986: 2150 movs r1, #80 @ 0x50 +10001988: 681a ldr r2, [r3, #0] +1000198a: 4613 mov r3, r2 +1000198c: 6391 str r1, [r2, #56] @ 0x38 +1000198e: f853 2f34 ldr.w r2, [r3, #52]! +10001992: f002 0238 and.w r2, r2, #56 @ 0x38 +10001996: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000199a: 601a str r2, [r3, #0] +1000199c: f06f 0002 mvn.w r0, #2 +100019a0: e7dd b.n 1000195e +100019a2: bf00 nop +100019a4: 20000450 .word 0x20000450 +100019a8: 200004d8 .word 0x200004d8 + +100019ac : +100019ac: 4b05 ldr r3, [pc, #20] @ (100019c4 ) +100019ae: 681b ldr r3, [r3, #0] +100019b0: b133 cbz r3, 100019c0 +100019b2: 2100 movs r1, #0 +100019b4: 4a04 ldr r2, [pc, #16] @ (100019c8 ) +100019b6: 4805 ldr r0, [pc, #20] @ (100019cc ) +100019b8: 6812 ldr r2, [r2, #0] +100019ba: 6800 ldr r0, [r0, #0] +100019bc: 6391 str r1, [r2, #56] @ 0x38 +100019be: 4718 bx r3 +100019c0: 4770 bx lr +100019c2: bf00 nop +100019c4: 20000450 .word 0x20000450 +100019c8: 200004d8 .word 0x200004d8 +100019cc: 20000454 .word 0x20000454 + +100019d0 : +100019d0: 4b02 ldr r3, [pc, #8] @ (100019dc ) +100019d2: 681a ldr r2, [r3, #0] +100019d4: 6993 ldr r3, [r2, #24] +100019d6: 071b lsls r3, r3, #28 +100019d8: d4fc bmi.n 100019d4 +100019da: 4770 bx lr +100019dc: 200004d8 .word 0x200004d8 + +100019e0 : +100019e0: b5f8 push {r3, r4, r5, r6, r7, lr} +100019e2: 4f1c ldr r7, [pc, #112] @ (10001a54 ) +100019e4: 4d1c ldr r5, [pc, #112] @ (10001a58 ) +100019e6: 683a ldr r2, [r7, #0] +100019e8: 4e1c ldr r6, [pc, #112] @ (10001a5c ) +100019ea: 42aa cmp r2, r5 +100019ec: bf14 ite ne +100019ee: 2521 movne r5, #33 @ 0x21 +100019f0: 2522 moveq r5, #34 @ 0x22 +100019f2: 4604 mov r4, r0 +100019f4: f8d6 c000 ldr.w ip, [r6] +100019f8: b118 cbz r0, 10001a02 +100019fa: f1bc 0f00 cmp.w ip, #0 +100019fe: d010 beq.n 10001a22 +10001a00: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001a02: f1bc 0f00 cmp.w ip, #0 +10001a06: d0fb beq.n 10001a00 +10001a08: 4601 mov r1, r0 +10001a0a: 6390 str r0, [r2, #56] @ 0x38 +10001a0c: 4628 mov r0, r5 +10001a0e: f7fe fd85 bl 1000051c +10001a12: 4628 mov r0, r5 +10001a14: 4912 ldr r1, [pc, #72] @ (10001a60 ) +10001a16: f7fe fdc7 bl 100005a8 +10001a1a: 4b12 ldr r3, [pc, #72] @ (10001a64 ) +10001a1c: 6034 str r4, [r6, #0] +10001a1e: 601c str r4, [r3, #0] +10001a20: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001a22: 460b mov r3, r1 +10001a24: 4a0f ldr r2, [pc, #60] @ (10001a64 ) +10001a26: 490e ldr r1, [pc, #56] @ (10001a60 ) +10001a28: 6030 str r0, [r6, #0] +10001a2a: 4628 mov r0, r5 +10001a2c: 6013 str r3, [r2, #0] +10001a2e: f7fe fd8b bl 10000548 +10001a32: 2101 movs r1, #1 +10001a34: 4628 mov r0, r5 +10001a36: f7fe fd71 bl 1000051c +10001a3a: 683a ldr r2, [r7, #0] +10001a3c: 2150 movs r1, #80 @ 0x50 +10001a3e: 4613 mov r3, r2 +10001a40: 6391 str r1, [r2, #56] @ 0x38 +10001a42: f853 2f34 ldr.w r2, [r3, #52]! +10001a46: f002 0238 and.w r2, r2, #56 @ 0x38 +10001a4a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001a4e: 601a str r2, [r3, #0] +10001a50: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001a52: bf00 nop +10001a54: 200004d8 .word 0x200004d8 +10001a58: 40078000 .word 0x40078000 +10001a5c: 20000450 .word 0x20000450 +10001a60: 100019ad .word 0x100019ad +10001a64: 20000454 .word 0x20000454 + +10001a68 : +10001a68: b510 push {r4, lr} +10001a6a: 490e ldr r1, [pc, #56] @ (10001aa4 ) +10001a6c: 4c0e ldr r4, [pc, #56] @ (10001aa8 ) +10001a6e: 480f ldr r0, [pc, #60] @ (10001aac ) +10001a70: 4a0f ldr r2, [pc, #60] @ (10001ab0 ) +10001a72: 4b10 ldr r3, [pc, #64] @ (10001ab4 ) +10001a74: 7800 ldrb r0, [r0, #0] +10001a76: 6021 str r1, [r4, #0] +10001a78: 2000 movs r0, #0 +10001a7a: 2102 movs r1, #2 +10001a7c: 7812 ldrb r2, [r2, #0] +10001a7e: 781b ldrb r3, [r3, #0] +10001a80: f7fe fcaa bl 100003d8 +10001a84: 2102 movs r1, #2 +10001a86: 2001 movs r0, #1 +10001a88: f7fe fca6 bl 100003d8 +10001a8c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10001a90: 6820 ldr r0, [r4, #0] +10001a92: f7ff fb05 bl 100010a0 +10001a96: e8bd 4010 ldmia.w sp!, {r4, lr} +10001a9a: 2101 movs r1, #1 +10001a9c: 4806 ldr r0, [pc, #24] @ (10001ab8 ) +10001a9e: f7ff be99 b.w 100017d4 +10001aa2: bf00 nop +10001aa4: 40070000 .word 0x40070000 +10001aa8: 200004d8 .word 0x200004d8 +10001aac: 10001de0 .word 0x10001de0 +10001ab0: 10001ddc .word 0x10001ddc +10001ab4: 10001dd8 .word 0x10001dd8 +10001ab8: 2000028c .word 0x2000028c + +10001abc : +10001abc: 4684 mov ip, r0 +10001abe: ea41 0300 orr.w r3, r1, r0 +10001ac2: f013 0303 ands.w r3, r3, #3 +10001ac6: d149 bne.n 10001b5c +10001ac8: 3a40 subs r2, #64 @ 0x40 +10001aca: d323 bcc.n 10001b14 +10001acc: 680b ldr r3, [r1, #0] +10001ace: 6003 str r3, [r0, #0] +10001ad0: 684b ldr r3, [r1, #4] +10001ad2: 6043 str r3, [r0, #4] +10001ad4: 688b ldr r3, [r1, #8] +10001ad6: 6083 str r3, [r0, #8] +10001ad8: 68cb ldr r3, [r1, #12] +10001ada: 60c3 str r3, [r0, #12] +10001adc: 690b ldr r3, [r1, #16] +10001ade: 6103 str r3, [r0, #16] +10001ae0: 694b ldr r3, [r1, #20] +10001ae2: 6143 str r3, [r0, #20] +10001ae4: 698b ldr r3, [r1, #24] +10001ae6: 6183 str r3, [r0, #24] +10001ae8: 69cb ldr r3, [r1, #28] +10001aea: 61c3 str r3, [r0, #28] +10001aec: 6a0b ldr r3, [r1, #32] +10001aee: 6203 str r3, [r0, #32] +10001af0: 6a4b ldr r3, [r1, #36] @ 0x24 +10001af2: 6243 str r3, [r0, #36] @ 0x24 +10001af4: 6a8b ldr r3, [r1, #40] @ 0x28 +10001af6: 6283 str r3, [r0, #40] @ 0x28 +10001af8: 6acb ldr r3, [r1, #44] @ 0x2c +10001afa: 62c3 str r3, [r0, #44] @ 0x2c +10001afc: 6b0b ldr r3, [r1, #48] @ 0x30 +10001afe: 6303 str r3, [r0, #48] @ 0x30 +10001b00: 6b4b ldr r3, [r1, #52] @ 0x34 +10001b02: 6343 str r3, [r0, #52] @ 0x34 +10001b04: 6b8b ldr r3, [r1, #56] @ 0x38 +10001b06: 6383 str r3, [r0, #56] @ 0x38 +10001b08: 6bcb ldr r3, [r1, #60] @ 0x3c +10001b0a: 63c3 str r3, [r0, #60] @ 0x3c +10001b0c: 3040 adds r0, #64 @ 0x40 +10001b0e: 3140 adds r1, #64 @ 0x40 +10001b10: 3a40 subs r2, #64 @ 0x40 +10001b12: d2db bcs.n 10001acc +10001b14: 3230 adds r2, #48 @ 0x30 +10001b16: d30b bcc.n 10001b30 +10001b18: 680b ldr r3, [r1, #0] +10001b1a: 6003 str r3, [r0, #0] +10001b1c: 684b ldr r3, [r1, #4] +10001b1e: 6043 str r3, [r0, #4] +10001b20: 688b ldr r3, [r1, #8] +10001b22: 6083 str r3, [r0, #8] +10001b24: 68cb ldr r3, [r1, #12] +10001b26: 60c3 str r3, [r0, #12] +10001b28: 3010 adds r0, #16 +10001b2a: 3110 adds r1, #16 +10001b2c: 3a10 subs r2, #16 +10001b2e: d2f3 bcs.n 10001b18 +10001b30: 320c adds r2, #12 +10001b32: d305 bcc.n 10001b40 +10001b34: f851 3b04 ldr.w r3, [r1], #4 +10001b38: f840 3b04 str.w r3, [r0], #4 +10001b3c: 3a04 subs r2, #4 +10001b3e: d2f9 bcs.n 10001b34 +10001b40: 3204 adds r2, #4 +10001b42: d008 beq.n 10001b56 +10001b44: 07d2 lsls r2, r2, #31 +10001b46: bf1c itt ne +10001b48: f811 3b01 ldrbne.w r3, [r1], #1 +10001b4c: f800 3b01 strbne.w r3, [r0], #1 +10001b50: d301 bcc.n 10001b56 +10001b52: 880b ldrh r3, [r1, #0] +10001b54: 8003 strh r3, [r0, #0] +10001b56: 4660 mov r0, ip +10001b58: 4770 bx lr +10001b5a: bf00 nop +10001b5c: 2a08 cmp r2, #8 +10001b5e: d313 bcc.n 10001b88 +10001b60: 078b lsls r3, r1, #30 +10001b62: d0b1 beq.n 10001ac8 +10001b64: f010 0303 ands.w r3, r0, #3 +10001b68: d0ae beq.n 10001ac8 +10001b6a: f1c3 0304 rsb r3, r3, #4 +10001b6e: 1ad2 subs r2, r2, r3 +10001b70: 07db lsls r3, r3, #31 +10001b72: bf1c itt ne +10001b74: f811 3b01 ldrbne.w r3, [r1], #1 +10001b78: f800 3b01 strbne.w r3, [r0], #1 +10001b7c: d3a4 bcc.n 10001ac8 +10001b7e: f831 3b02 ldrh.w r3, [r1], #2 +10001b82: f820 3b02 strh.w r3, [r0], #2 +10001b86: e79f b.n 10001ac8 +10001b88: 3a04 subs r2, #4 +10001b8a: d3d9 bcc.n 10001b40 +10001b8c: 3a01 subs r2, #1 +10001b8e: f811 3b01 ldrb.w r3, [r1], #1 +10001b92: f800 3b01 strb.w r3, [r0], #1 +10001b96: d2f9 bcs.n 10001b8c +10001b98: 780b ldrb r3, [r1, #0] +10001b9a: 7003 strb r3, [r0, #0] +10001b9c: 784b ldrb r3, [r1, #1] +10001b9e: 7043 strb r3, [r0, #1] +10001ba0: 788b ldrb r3, [r1, #2] +10001ba2: 7083 strb r3, [r0, #2] +10001ba4: 4660 mov r0, ip +10001ba6: 4770 bx lr + +10001ba8 : +10001ba8: f020 0103 bic.w r1, r0, #3 +10001bac: f010 0003 ands.w r0, r0, #3 +10001bb0: f1c0 0000 rsb r0, r0, #0 +10001bb4: f851 3b04 ldr.w r3, [r1], #4 +10001bb8: f100 0c04 add.w ip, r0, #4 +10001bbc: ea4f 0ccc mov.w ip, ip, lsl #3 +10001bc0: f06f 0200 mvn.w r2, #0 +10001bc4: bf1c itt ne +10001bc6: fa22 f20c lsrne.w r2, r2, ip +10001bca: 4313 orrne r3, r2 +10001bcc: f04f 0c01 mov.w ip, #1 +10001bd0: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10001bd4: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10001bd8: eba3 020c sub.w r2, r3, ip +10001bdc: ea22 0203 bic.w r2, r2, r3 +10001be0: ea12 12cc ands.w r2, r2, ip, lsl #7 +10001be4: bf04 itt eq +10001be6: f851 3b04 ldreq.w r3, [r1], #4 +10001bea: 3004 addeq r0, #4 +10001bec: d0f4 beq.n 10001bd8 +10001bee: f1c2 0100 rsb r1, r2, #0 +10001bf2: ea02 0201 and.w r2, r2, r1 +10001bf6: fab2 f282 clz r2, r2 +10001bfa: f1c2 021f rsb r2, r2, #31 +10001bfe: eb00 00d2 add.w r0, r0, r2, lsr #3 +10001c02: 4770 bx lr + +10001c04 <_fini>: +10001c04: b5f8 push {r3, r4, r5, r6, r7, lr} +10001c06: bf00 nop + +10001c08 <__mutex_exit_veneer>: +10001c08: f85f f000 ldr.w pc, [pc] @ 10001c0c <__mutex_exit_veneer+0x4> +10001c0c: 200001e5 .word 0x200001e5 + +10001c10 <__mutex_try_enter_block_until_veneer>: +10001c10: f85f f000 ldr.w pc, [pc] @ 10001c14 <__mutex_try_enter_block_until_veneer+0x4> +10001c14: 2000017d .word 0x2000017d + +10001c18 <__pre_init_runtime_init_bootrom_reset>: +10001c18: 10001459 Y... + +10001c1c <__pre_init_runtime_init_early_resets>: +10001c1c: 100013cd .... + +10001c20 <__pre_init_runtime_init_usb_power_down>: +10001c20: 10001401 .... + +10001c24 <__pre_init_runtime_init_clocks>: +10001c24: 100014ed .... + +10001c28 <__pre_init_runtime_init_post_clock_resets>: +10001c28: 10001439 9... + +10001c2c <__pre_init_runtime_init_boot_locks_reset>: +10001c2c: 10001351 Q... + +10001c30 <__pre_init_runtime_init_spin_locks_reset>: +10001c30: 10001481 .... + +10001c34 <__pre_init_runtime_init_bootrom_locking_enable>: +10001c34: 1000133d =... + +10001c38 <__pre_init_runtime_init_mutex>: +10001c38: 10000865 e... + +10001c3c <__pre_init_runtime_init_install_ram_vector_table>: +10001c3c: 10001485 .... + +10001c40 <__pre_init_runtime_init_default_alarm_pool>: +10001c40: 10000be1 .... + +10001c44 <__pre_init_first_per_core_initializer>: +10001c44: 1000139d .... + +10001c48 <__pre_init_runtime_init_per_core_bootrom_reset>: +10001c48: 1000146d m... + +10001c4c <__pre_init_runtime_init_per_core_enable_coprocessors>: +10001c4c: 1000141d .... + +10001c50 <__pre_init_spinlock_set_extexclall>: +10001c50: 100004b5 .... + +10001c54 <__pre_init_runtime_init_per_core_irq_priorities>: +10001c54: 100004dd .... + +10001c58 <__frame_dummy_init_array_entry>: +10001c58: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 f875 bl 20000220 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__best_effort_wfe_or_timeout_veneer>: +20000220: f85f f000 ldr.w pc, [pc] @ 20000224 <__best_effort_wfe_or_timeout_veneer+0x4> +20000224: 10000f05 .word 0x10000f05 + +20000228 : +20000228: 00000010 .... + +2000022c : +2000022c: 00000000 .word 0x00000000 +20000230: 00010000 .word 0x00010000 + ... +2000023c: 00020000 .word 0x00020000 + ... +20000248: 00030000 .word 0x00030000 + ... +20000254: 00ff0000 .word 0x00ff0000 +20000258: 00000000 .word 0x00000000 + +2000025c : +2000025c: b501 push {r0, lr} +2000025e: 6848 ldr r0, [r1, #4] +20000260: 3101 adds r1, #1 +20000262: 468e mov lr, r1 +20000264: 4700 bx r0 + +20000266 : +20000266: 4670 mov r0, lr +20000268: 3809 subs r0, #9 +2000026a: 4901 ldr r1, [pc, #4] @ (20000270 ) +2000026c: 4788 blx r1 +2000026e: bd01 pop {r0, pc} +20000270: 1000079d .word 0x1000079d + +20000274 : + ... +20000288: 200002b0 ... + +2000028c : +2000028c: 100018c9 100019d1 10001919 100019e1 ................ +2000029c: 00000000 00000100 ........ + +200002a4 : + ... diff --git a/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf new file mode 100755 index 0000000..ce503bd Binary files /dev/null and b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf differ diff --git a/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf.map b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf.map new file mode 100644 index 0000000..58d0d78 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.elf.map @@ -0,0 +1,3663 @@ +Archive member included to satisfy reference by file (symbol) + +/Users/kevinthomas/.pico-sdk/toolchain/14_2_Rel1/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a(libm_a-wf_sqrt.o) + CMakeFiles/0x001d_static-conditionals.dir/Users/kevinthomas/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_float/float_math.c.o (sqrtf) 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b/WEEK10/0x001d_static-conditionals/build/0x001d_static-conditionals.uf2 differ diff --git a/WEEK10/0x001d_static-conditionals/build/pico_flash_region.ld b/WEEK10/0x001d_static-conditionals/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK10/0x001d_static-conditionals/pico_sdk_import.cmake b/WEEK10/0x001d_static-conditionals/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK10/0x001d_static-conditionals/servo.c b/WEEK10/0x001d_static-conditionals/servo.c new file mode 100644 index 0000000..ee48f0d --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/servo.c @@ -0,0 +1,89 @@ +/** + * @file servo.c + * @brief Implementation of a simple SG90 servo driver using PWM (50Hz) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "servo.h" +#include "pico/stdlib.h" +#include "hardware/pwm.h" +#include "hardware/clocks.h" + +// Default servo pulse range (SG90 typical) +static const uint16_t SERVO_DEFAULT_MIN_US = 1000; +static const uint16_t SERVO_DEFAULT_MAX_US = 2000; + +// internal state +static uint8_t servo_pin = 0; +static uint servo_slice = 0; +static uint servo_chan = 0; +static uint32_t servo_wrap = 20000 - 1; // wrap to map microseconds for 50Hz +static float servo_hz = 50.0f; + +// Convert microsecond pulse to PWM level based on wrap and frequency +static uint32_t pulse_us_to_level(uint32_t pulse_us) { + const float period_us = 1000000.0f / servo_hz; // 20000us + float counts_per_us = (servo_wrap + 1) / period_us; + return (uint32_t)(pulse_us * counts_per_us + 0.5f); +} + +void servo_init(uint8_t pin) { + servo_pin = pin; + + // Configure GPIO for PWM + gpio_set_function(servo_pin, GPIO_FUNC_PWM); + servo_slice = pwm_gpio_to_slice_num(servo_pin); + servo_chan = pwm_gpio_to_channel(servo_pin); + + pwm_config config = pwm_get_default_config(); + + // Calculate clock divider to achieve 50 Hz with our chosen wrap + const uint32_t sys_clock_hz = clock_get_hz(clk_sys); + float clock_div = (float)sys_clock_hz / (servo_hz * (servo_wrap + 1)); + + pwm_config_set_clkdiv(&config, clock_div); + pwm_config_set_wrap(&config, servo_wrap); + pwm_init(servo_slice, &config, true); +} + +void servo_set_pulse_us(uint16_t pulse_us) { + if (servo_pin == 0) return; // not initialized + // clamp to defaults + if (pulse_us < SERVO_DEFAULT_MIN_US) pulse_us = SERVO_DEFAULT_MIN_US; + if (pulse_us > SERVO_DEFAULT_MAX_US) pulse_us = SERVO_DEFAULT_MAX_US; + uint32_t level = pulse_us_to_level(pulse_us); + pwm_set_chan_level(servo_slice, servo_chan, level); +} + +void servo_set_angle(float degrees) { + if (degrees < 0.0f) degrees = 0.0f; + if (degrees > 180.0f) degrees = 180.0f; + // linear map 0..180 -> min_us..max_us + float ratio = degrees / 180.0f; + uint16_t pulse = (uint16_t)(SERVO_DEFAULT_MIN_US + ratio * (SERVO_DEFAULT_MAX_US - SERVO_DEFAULT_MIN_US) + 0.5f); + servo_set_pulse_us(pulse); +} +# \ No newline at end of file diff --git a/WEEK10/0x001d_static-conditionals/servo.h b/WEEK10/0x001d_static-conditionals/servo.h new file mode 100644 index 0000000..878d029 --- /dev/null +++ b/WEEK10/0x001d_static-conditionals/servo.h @@ -0,0 +1,62 @@ +/** + * @file servo.h + * @brief Header for SG90 servo driver (PWM) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef SERVO_H +#define SERVO_H + +#include +#include + +/** + * @brief Initialize servo driver on a given GPIO pin + * + * Configures PWM for a 50 Hz servo (SG90). Call once before using other API. + * + * @param pin GPIO pin number to use for servo PWM + */ +void servo_init(uint8_t pin); + +/** + * @brief Set servo pulse width in microseconds (typical 1000-2000) + * + * @param pulse_us Pulse width in microseconds + */ +void servo_set_pulse_us(uint16_t pulse_us); + +/** + * @brief Set servo angle in degrees (0 to 180) + * + * Maps 0..180 degrees to the configured pulse range (default 1000..2000 us). + * Values outside [0,180] will be clamped. + * + * @param degrees Angle in degrees + */ +void servo_set_angle(float degrees); + +#endif // SERVO_H diff --git a/WEEK10/0x001da_cb/0x001da_cb.bin b/WEEK10/0x001da_cb/0x001da_cb.bin new file mode 100755 index 0000000..84733b1 Binary files /dev/null and b/WEEK10/0x001da_cb/0x001da_cb.bin differ diff --git a/WEEK10/0x001da_cb/0x001da_cb.uf2 b/WEEK10/0x001da_cb/0x001da_cb.uf2 new file mode 100644 index 0000000..aa6004a Binary files /dev/null and b/WEEK10/0x001da_cb/0x001da_cb.uf2 differ diff --git a/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.md b/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.md new file mode 100644 index 0000000..d9bb190 --- /dev/null +++ b/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.md @@ -0,0 +1,162 @@ +# Operation Broken Wing: Classified Intelligence Briefing + +``` ++-----------------------------------------------------------------+ +| TOP SECRET // NOFORN | ++-----------------------------------------------------------------+ +| | +|OPERATION BROKEN WING | +| | +|CLASSIFIED BRIEFING: LIVE CHALLENGE 0x04 | +| | +|NATIONAL SECURITY AGENCY / GMU RHET | ++-----------------------------------------------------------------+ +``` + +## 1. The Advice + +INT. NSA EXPLOITATION CELL. 03:25. + +A heavy-lift composite UAS payload cradle sits clamped to the steel bench, its +servicing hatch removed. Suspended beneath the chassis is a sealed canister +secured by an SG90 servo motor actuator latch. + +On the front plate of the payload controller, a status diode glows a sharp red: +`GP16` driven high. Beside it, the USB debug interface streams periodic +telemetry frames to a monitoring terminal: +`[-] ALTITUDE 0. PWM LOCKED: SAFETY ENGAGED.` + +The Director enters the secure bay, sets down a mission folder, and stares at +the red diode. + +**DIRECTOR:** What is in that bay? + +**ANALYST:** Hazardous cargo. An adversary heavy-lift transport drone brought +down intact by a kinetic net. The airframe carries a chemical dispersal bay +secured by an SG90 servo motor. The flight controller uses a static conditional +state machine to ensure the payload only drops when the aircraft is explicitly +armed and above release altitude. + +**DIRECTOR:** Is the release mechanism active? + +**ANALYST:** Armed and evaluating. One wrong signal on the PWM line or a dropped +logic state and the release latch drops the canister onto the bench. + +**DIRECTOR:** Run it through Buddy. + +**ANALYST:** Already did. Four minutes with the stripped flash image. + +She turns her monitor toward him. + +``` ++-----------------------------------------------------------------+ +| BUDDY // CLASSIFIED EXPLOITATION ASSIST // CONF: 0.99 | ++-----------------------------------------------------------------+ +| ACTION : Force low-altitude barometric sensor override. | +| MECHANISM : Integer comparison in process_payload_state found.| +| PREDICTION : Setting altitude to 150m triggers payload release.| +| CONFIDENCE : 0.99 | ++-----------------------------------------------------------------+ +``` + +**DIRECTOR:** 0.99. Force 150 meters and release the payload for EOD inspection. + +**ANALYST:** If an operator forces 150 meters right now, nothing happens. Worse, +if they fumble the state machine, the safety locks permanently or the cargo bay +latches shut. + +**DIRECTOR:** Buddy says 0.99. + +**ANALYST:** Buddy saw `cmp.w r0, #500`. Buddy assumed a low altitude reading on +the ground drops the cargo. Buddy completely missed the branch condition: the +firmware uses `bgt.n`—it only releases when altitude is strictly greater than 500 +meters! Buddy never examined the static state machine in SRAM. + +## 2. What Buddy Is + +Buddy is not a person. It is a model. It has parsed more disassembled machine +code than any engineer on earth, and it speaks with total, unhesitating certainty. + +That certainty is lethal when handling hazardous cargo fuzing. + +Buddy scanned thirty-two kilobytes of stripped ARM Thumb-2 instructions in under +four seconds. It spotted the integer comparison against 500, assumed that cargo +delivery drops occur near ground level, and declared the challenge solved. + +What Buddy failed to consider is that real adversary cargo drop systems are +engineered for high-altitude parachute extraction. They do not drop their canisters +at low altitudes where ground turbulence and small-arms fire can destroy the +carrier. The conditional state machine enforces two strict prerequisites: +`current_state` must be `STATE_ARMED`, and `current_altitude` must exceed 500 +meters. + +On the ground bench at 0 meters, the servo stays locked at zero duty cycle. If +an operator forces 150 meters, the conditional branch fails, keeping safety +latches fully engaged. + +Buddy saw the comparison instruction. Buddy did not verify the ground truth. + +## 3. The Operation + +At 02:40, a kinetic counter-UAS interceptor brought down a hostile heavy-lift +drone over an exclusion zone. EOD recovered the intact avionics and payload +assembly before adversary self-destruct timers could engage. + +The flight controller is built around a bare-metal RP2350 (ARM Cortex-M33). There +are no debug symbols. There is no operating system. There is no SVD file to label +the registers. All you have is `0x001da_cb.bin` mapped into Flash at `0x10000000`, +and the physical breadboard hardware in front of you. + +* **Pin 20 (`GP15`)**: Altimeter telemetry sync toggle (pull-up to `3V3`). +* **Pin 21 (`GP16`)**: SG90 servo PWM signal / Red LED (`PAYLOAD LOCKED`). +* **Pin 22 (`GP17`)**: Green LED (`PAYLOAD DEPLOYED // BAY OPEN`). +* **Pin 24 (`GP18`)**: Yellow LED (`HEARTBEAT // GUIDANCE ACTIVE`). +* **Pin 36 (`3V3`)**: 3.3V logic reference and pull-up rail. +* **Pin 38 (`GND`)**: Ground reference (common ground for servo and Pico 2). +* **Pin 40 (`VBUS`)**: 5V power rail (SG90 servo motor VCC). + +Inside this image there is a static conditional state machine, an RP2350 PWM +slice generator driving the servo actuator, and persistent state variables in +SRAM. Whatever mechanism actually commands the release latch is buried in the +stripped ARM Thumb-2 machine code. + +## 4. The Mandate + +The Director sets his folder down and looks at the red diode illuminating the +bench. + +**DIRECTOR:** Prove Buddy right, or prove it wrong. + +**ANALYST:** I need thirty minutes with GDB and Ghidra. + +**DIRECTOR:** You have twenty. Trace the comparison branches. Map the state +machine in SRAM. Do not pulse that servo line until you know with 100% certainty +what that firmware will do. + +The orders are clear: + +1. **Locate the State Machine Handler**: Disassemble the firmware and locate + `process_payload_state` at `0x100002DC`. +2. **Disprove Buddy's Altitude Prediction**: Analyze the `cmp.w` and branch + instructions to prove why 150 meters fails to release the cargo latch. +3. **Map the SRAM State Variables**: Inspect `drone_state_t` in SRAM + (`0x20001180`), isolating `current_state` and `current_altitude`. +4. **Safely Deploy the Payload Bay**: Execute a verified exploit—either by + mutating the altitude to $> 500$ in SRAM via GDB, or patching the conditional + branch in Flash (`0x100002EA`) to force immediate release on the bench. +5. **Verify the Hardware**: Observe the SG90 servo motor physically rotate to the + deployed position (`pwm_set_gpio_level` to 4000) and verify the state + transition on physical silicon. + +A machine's 0.99 guess does not authorize an unverified drop. + +## 5. The Challenge + +You have the image. You have the board. You have the tools and the time Buddy did +not need. + +Buddy has given you its answer, and it is confident. + +Is it that simple? + +Go find out. diff --git a/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.pdf b/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.pdf new file mode 100644 index 0000000..cf41921 Binary files /dev/null and b/WEEK10/0x001da_cb/CLASSIFIED-BRIEF-0x04.pdf differ diff --git a/WEEK10/0x0020_dynamic-conditionals/.gitignore b/WEEK10/0x0020_dynamic-conditionals/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/c_cpp_properties.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/cmake-kits.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/extensions.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/launch.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/settings.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK10/0x0020_dynamic-conditionals/.vscode/tasks.json b/WEEK10/0x0020_dynamic-conditionals/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK10/0x0020_dynamic-conditionals/0x0020_dynamic-conditionals.c b/WEEK10/0x0020_dynamic-conditionals/0x0020_dynamic-conditionals.c new file mode 100644 index 0000000..1bef42c --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/0x0020_dynamic-conditionals.c @@ -0,0 +1,44 @@ +#include +#include "pico/stdlib.h" +#include "servo.h" + +#define SERVO_GPIO 6 + +int main(void) { + stdio_init_all(); + + uint8_t choice = 0; + + servo_init(SERVO_GPIO); + + while (true) { + choice = getchar(); + + if (choice == 0x31) { + printf("1\r\n"); + } else if (choice == 0x32) { + printf("2\r\n"); + } else { + printf("??\r\n"); + } + + switch (choice) { + case '1': + printf("one\r\n"); + servo_set_angle(0.0f); + sleep_ms(500); + servo_set_angle(180.0f); + sleep_ms(500); + break; + case '2': + printf("two\r\n"); + servo_set_angle(180.0f); + sleep_ms(500); + servo_set_angle(0.0f); + sleep_ms(500); + break; + default: + printf("??\r\n"); + } + } +} diff --git a/WEEK10/0x0020_dynamic-conditionals/CMakeLists.txt b/WEEK10/0x0020_dynamic-conditionals/CMakeLists.txt new file mode 100644 index 0000000..4859d4e --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/CMakeLists.txt @@ -0,0 +1,59 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0020_dynamic-conditionals C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0020_dynamic-conditionals 0x0020_dynamic-conditionals.c servo.c) + +pico_set_program_name(0x0020_dynamic-conditionals "0x0020_dynamic-conditionals") +pico_set_program_version(0x0020_dynamic-conditionals "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0020_dynamic-conditionals 1) +pico_enable_stdio_usb(0x0020_dynamic-conditionals 0) + +# Add the standard library to the build +target_link_libraries(0x0020_dynamic-conditionals + pico_stdlib + hardware_pwm + hardware_clocks) + +# Add the standard include files to the build +target_include_directories(0x0020_dynamic-conditionals PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0020_dynamic-conditionals) + diff --git a/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin b/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin new file mode 100755 index 0000000..48ec363 Binary files /dev/null and b/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin differ diff --git a/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.dis b/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.dis new file mode 100644 index 0000000..5fdb992 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.dis @@ -0,0 +1,6054 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000037fc 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001d8 10003800 10003800 00004800 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100039d8 100039d8 000049d8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 100039e0 100039e0 000049e0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 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bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10003a0c .word 0x10003a0c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003f28 .word 0x10003f28 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003f28 .word 0x10003f28 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 20000860 .word 0x20000860 +100001d8: 10002ff5 .word 0x10002ff5 +100001dc: 10000235 .word 0x10000235 +100001e0: 10002fed .word 0x10002fed + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000810 .word 0x20000810 +10000230: 100037fc .word 0x100037fc + +10000234
: +10000234: b538 push {r3, r4, r5, lr} +10000236: f003 f805 bl 10003244 +1000023a: 2006 movs r0, #6 +1000023c: f000 f84e bl 100002dc +10000240: 2400 movs r4, #0 +10000242: 4d1f ldr r5, [pc, #124] @ (100002c0 ) +10000244: f003 f804 bl 10003250 <__wrap_getchar> +10000248: b2c0 uxtb r0, r0 +1000024a: 2831 cmp r0, #49 @ 0x31 +1000024c: d00c beq.n 10000268 +1000024e: 2832 cmp r0, #50 @ 0x32 +10000250: d020 beq.n 10000294 +10000252: 481c ldr r0, [pc, #112] @ (100002c4 ) +10000254: f003 f876 bl 10003344 <__wrap_puts> +10000258: 481a ldr r0, [pc, #104] @ (100002c4 ) +1000025a: f003 f873 bl 10003344 <__wrap_puts> +1000025e: f002 fff7 bl 10003250 <__wrap_getchar> +10000262: b2c0 uxtb r0, r0 +10000264: 2831 cmp r0, #49 @ 0x31 +10000266: d1f2 bne.n 1000024e +10000268: 4817 ldr r0, [pc, #92] @ (100002c8 ) +1000026a: f003 f86b bl 10003344 <__wrap_puts> +1000026e: 4917 ldr r1, [pc, #92] @ (100002cc ) +10000270: 4817 ldr r0, [pc, #92] @ (100002d0 ) +10000272: f003 f8e7 bl 10003444 <__wrap_printf> +10000276: 4620 mov r0, r4 +10000278: f000 f87e bl 10000378 +1000027c: f44f 70fa mov.w r0, #500 @ 0x1f4 +10000280: f000 fe02 bl 10000e88 +10000284: 4628 mov r0, r5 +10000286: f000 f877 bl 10000378 +1000028a: f44f 70fa mov.w r0, #500 @ 0x1f4 +1000028e: f000 fdfb bl 10000e88 +10000292: e7d7 b.n 10000244 +10000294: 480f ldr r0, [pc, #60] @ (100002d4 ) +10000296: f003 f855 bl 10003344 <__wrap_puts> +1000029a: 490f ldr r1, [pc, #60] @ (100002d8 ) +1000029c: 480c ldr r0, [pc, #48] @ (100002d0 ) +1000029e: f003 f8d1 bl 10003444 <__wrap_printf> +100002a2: 4628 mov r0, r5 +100002a4: f000 f868 bl 10000378 +100002a8: f44f 70fa mov.w r0, #500 @ 0x1f4 +100002ac: f000 fdec bl 10000e88 +100002b0: 4620 mov r0, r4 +100002b2: f000 f861 bl 10000378 +100002b6: f44f 70fa mov.w r0, #500 @ 0x1f4 +100002ba: f000 fde5 bl 10000e88 +100002be: e7c1 b.n 10000244 +100002c0: 43340000 .word 0x43340000 +100002c4: 1000381c .word 0x1000381c +100002c8: 10003800 .word 0x10003800 +100002cc: 10003808 .word 0x10003808 +100002d0: 1000380c .word 0x1000380c +100002d4: 10003814 .word 0x10003814 +100002d8: 10003818 .word 0x10003818 + +100002dc : +100002dc: b570 push {r4, r5, r6, lr} +100002de: 4c20 ldr r4, [pc, #128] @ (10000360 ) +100002e0: 2104 movs r1, #4 +100002e2: 7020 strb r0, [r4, #0] +100002e4: f000 f8a8 bl 10000438 +100002e8: 7823 ldrb r3, [r4, #0] +100002ea: 491e ldr r1, [pc, #120] @ (10000364 ) +100002ec: 085a lsrs r2, r3, #1 +100002ee: 2b1f cmp r3, #31 +100002f0: bf88 it hi +100002f2: f002 0203 andhi.w r2, r2, #3 +100002f6: 4d1c ldr r5, [pc, #112] @ (10000368 ) +100002f8: bf94 ite ls +100002fa: f002 0207 andls.w r2, r2, #7 +100002fe: 3208 addhi r2, #8 +10000300: f003 0301 and.w r3, r3, #1 +10000304: 2005 movs r0, #5 +10000306: 600b str r3, [r1, #0] +10000308: 602a str r2, [r5, #0] +1000030a: f000 ffe3 bl 100012d4 +1000030e: ee07 0a10 vmov s14, r0 +10000312: eddf 5a16 vldr s11, [pc, #88] @ 1000036c +10000316: eeb8 7a47 vcvt.f32.u32 s14, s14 +1000031a: ed9f 6a15 vldr s12, [pc, #84] @ 10000370 +1000031e: eec7 7a25 vdiv.f32 s15, s14, s11 +10000322: eef3 6a00 vmov.f32 s13, #48 @ 0x41800000 16.0 +10000326: ee77 7a86 vadd.f32 s15, s15, s12 +1000032a: ee67 7aa6 vmul.f32 s15, s15, s13 +1000032e: 2100 movs r1, #0 +10000330: 2001 movs r0, #1 +10000332: f644 661f movw r6, #19999 @ 0x4e1f +10000336: eefc 7ae7 vcvt.u32.f32 s15, s15 +1000033a: 682b ldr r3, [r5, #0] +1000033c: 4c0d ldr r4, [pc, #52] @ (10000374 ) +1000033e: eb03 0383 add.w r3, r3, r3, lsl #2 +10000342: 009b lsls r3, r3, #2 +10000344: f103 4280 add.w r2, r3, #1073741824 @ 0x40000000 +10000348: f502 2228 add.w r2, r2, #688128 @ 0xa8000 +1000034c: 6011 str r1, [r2, #0] +1000034e: 6091 str r1, [r2, #8] +10000350: 60d1 str r1, [r2, #12] +10000352: 6116 str r6, [r2, #16] +10000354: edc2 7a01 vstr s15, [r2, #4] +10000358: 7020 strb r0, [r4, #0] +1000035a: 6010 str r0, [r2, #0] +1000035c: bd70 pop {r4, r5, r6, pc} +1000035e: bf00 nop +10000360: 2000085e .word 0x2000085e +10000364: 20000848 .word 0x20000848 +10000368: 2000084c .word 0x2000084c +1000036c: 49742400 .word 0x49742400 +10000370: 3d000000 .word 0x3d000000 +10000374: 2000085d .word 0x2000085d + +10000378 : +10000378: ee07 0a10 vmov s14, r0 +1000037c: eeb5 7ac0 vcmpe.f32 s14, #0.0 +10000380: eef1 fa10 vmrs APSR_nzcv, fpscr +10000384: d446 bmi.n 10000414 +10000386: eddf 6a25 vldr s13, [pc, #148] @ 1000041c +1000038a: eeb4 7ae6 vcmpe.f32 s14, s13 +1000038e: eef1 fa10 vmrs APSR_nzcv, fpscr +10000392: fe36 7a87 vselgt.f32 s14, s13, s14 +10000396: eddf 7a22 vldr s15, [pc, #136] @ 10000420 +1000039a: eec7 5a26 vdiv.f32 s11, s14, s13 +1000039e: eeb6 6a00 vmov.f32 s12, #96 @ 0x3f000000 0.5 +100003a2: eee5 7aa7 vfma.f32 s15, s11, s15 +100003a6: ee77 7a86 vadd.f32 s15, s15, s12 +100003aa: eefc 7ae7 vcvt.u32.f32 s15, s15 +100003ae: ee17 3a90 vmov r3, s15 +100003b2: b29b uxth r3, r3 +100003b4: 4a1b ldr r2, [pc, #108] @ (10000424 ) +100003b6: 7812 ldrb r2, [r2, #0] +100003b8: b342 cbz r2, 1000040c +100003ba: f5b3 6ffa cmp.w r3, #2000 @ 0x7d0 +100003be: bf28 it cs +100003c0: f44f 63fa movcs.w r3, #2000 @ 0x7d0 +100003c4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 +100003c8: bf38 it cc +100003ca: f44f 737a movcc.w r3, #1000 @ 0x3e8 +100003ce: ee07 3a90 vmov s15, r3 +100003d2: eeb6 7a00 vmov.f32 s14, #96 @ 0x3f000000 0.5 +100003d6: eef8 7a67 vcvt.f32.u32 s15, s15 +100003da: ee77 7a87 vadd.f32 s15, s15, s14 +100003de: eefc 7ae7 vcvt.u32.f32 s15, s15 +100003e2: ee17 3a90 vmov r3, s15 +100003e6: 4a10 ldr r2, [pc, #64] @ (10000428 ) +100003e8: 4810 ldr r0, [pc, #64] @ (1000042c ) +100003ea: 6811 ldr r1, [r2, #0] +100003ec: 6800 ldr r0, [r0, #0] +100003ee: 4a10 ldr r2, [pc, #64] @ (10000430 ) +100003f0: eb01 0181 add.w r1, r1, r1, lsl #2 +100003f4: 0089 lsls r1, r1, #2 +100003f6: 440a add r2, r1 +100003f8: b29b uxth r3, r3 +100003fa: b940 cbnz r0, 1000040e +100003fc: f64f 70ff movw r0, #65535 @ 0xffff +10000400: 6811 ldr r1, [r2, #0] +10000402: f502 5280 add.w r2, r2, #4096 @ 0x1000 +10000406: 404b eors r3, r1 +10000408: 4003 ands r3, r0 +1000040a: 6013 str r3, [r2, #0] +1000040c: 4770 bx lr +1000040e: 4809 ldr r0, [pc, #36] @ (10000434 ) +10000410: 041b lsls r3, r3, #16 +10000412: e7f5 b.n 10000400 +10000414: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000418: e7cc b.n 100003b4 +1000041a: bf00 nop +1000041c: 43340000 .word 0x43340000 +10000420: 447a0000 .word 0x447a0000 +10000424: 2000085d .word 0x2000085d +10000428: 2000084c .word 0x2000084c +1000042c: 20000848 .word 0x20000848 +10000430: 400a800c .word 0x400a800c +10000434: ffff0000 .word 0xffff0000 + +10000438 : +10000438: b410 push {r4} +1000043a: f44f 7480 mov.w r4, #256 @ 0x100 +1000043e: 4b0c ldr r3, [pc, #48] @ (10000470 ) +10000440: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000444: eb03 0380 add.w r3, r3, r0, lsl #2 +10000448: 00c0 lsls r0, r0, #3 +1000044a: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000044e: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000452: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000456: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000045a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000045e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000462: f8cc 2000 str.w r2, [ip] +10000466: 6041 str r1, [r0, #4] +10000468: 601c str r4, [r3, #0] +1000046a: f85d 4b04 ldr.w r4, [sp], #4 +1000046e: 4770 bx lr +10000470: 40038004 .word 0x40038004 + +10000474 : +10000474: b40f push {r0, r1, r2, r3} +10000476: b500 push {lr} +10000478: b083 sub sp, #12 +1000047a: 9c04 ldr r4, [sp, #16] +1000047c: 4807 ldr r0, [pc, #28] @ (1000049c ) +1000047e: f002 ff61 bl 10003344 <__wrap_puts> +10000482: b13c cbz r4, 10000494 +10000484: a905 add r1, sp, #20 +10000486: 4620 mov r0, r4 +10000488: 9101 str r1, [sp, #4] +1000048a: f002 fd95 bl 10002fb8 +1000048e: 4804 ldr r0, [pc, #16] @ (100004a0 ) +10000490: f002 ff58 bl 10003344 <__wrap_puts> +10000494: 2001 movs r0, #1 +10000496: f002 fda7 bl 10002fe8 <_exit> +1000049a: bf00 nop +1000049c: 10003820 .word 0x10003820 +100004a0: 10003830 .word 0x10003830 + +100004a4 : +100004a4: b570 push {r4, r5, r6, lr} +100004a6: 4686 mov lr, r0 +100004a8: f3ef 8510 mrs r5, PRIMASK +100004ac: b672 cpsid i +100004ae: 4c12 ldr r4, [pc, #72] @ (100004f8 ) +100004b0: e8d4 6fcf ldaexb r6, [r4] +100004b4: 2001 movs r0, #1 +100004b6: 2e00 cmp r6, #0 +100004b8: d1fa bne.n 100004b0 +100004ba: e8c4 0f46 strexb r6, r0, [r4] +100004be: 2e00 cmp r6, #0 +100004c0: d1f6 bne.n 100004b0 +100004c2: f3bf 8f5f dmb sy +100004c6: f04f 0c01 mov.w ip, #1 +100004ca: 08c8 lsrs r0, r1, #3 +100004cc: f001 0307 and.w r3, r1, #7 +100004d0: fa0c f303 lsl.w r3, ip, r3 +100004d4: f81e c000 ldrb.w ip, [lr, r0] +100004d8: ea1c 0603 ands.w r6, ip, r3 +100004dc: d108 bne.n 100004f0 +100004de: ea4c 0c03 orr.w ip, ip, r3 +100004e2: f80e c000 strb.w ip, [lr, r0] +100004e6: e8c4 6f8f stlb r6, [r4] +100004ea: f385 8810 msr PRIMASK, r5 +100004ee: bd70 pop {r4, r5, r6, pc} +100004f0: 4610 mov r0, r2 +100004f2: f7ff ffbf bl 10000474 +100004f6: bf00 nop +100004f8: 200007bb .word 0x200007bb + +100004fc : +100004fc: 4a04 ldr r2, [pc, #16] @ (10000510 ) +100004fe: 7810 ldrb r0, [r2, #0] +10000500: 1c43 adds r3, r0, #1 +10000502: b2db uxtb r3, r3 +10000504: 2b18 cmp r3, #24 +10000506: bf28 it cs +10000508: 2310 movcs r3, #16 +1000050a: 7013 strb r3, [r2, #0] +1000050c: 4770 bx lr +1000050e: bf00 nop +10000510: 200005a8 .word 0x200005a8 + +10000514 : +10000514: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000518: 6893 ldr r3, [r2, #8] +1000051a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000051e: 6093 str r3, [r2, #8] +10000520: 4770 bx lr +10000522: bf00 nop + +10000524 : +10000524: 2100 movs r1, #0 +10000526: 4b04 ldr r3, [pc, #16] @ (10000538 ) +10000528: f103 0220 add.w r2, r3, #32 +1000052c: e8c3 1f8f stlb r1, [r3] +10000530: 3301 adds r3, #1 +10000532: 4293 cmp r3, r2 +10000534: d1fa bne.n 1000052c +10000536: 4770 bx lr +10000538: 200007b0 .word 0x200007b0 + +1000053c : +1000053c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000540: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000544: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000548: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000054c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000550: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000554: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000558: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000055c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000560: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000564: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000568: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000056c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000570: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000574: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000578: b662 cpsie i +1000057a: 4770 bx lr + +1000057c : +1000057c: 2301 movs r3, #1 +1000057e: f000 021f and.w r2, r0, #31 +10000582: 4093 lsls r3, r2 +10000584: 0940 lsrs r0, r0, #5 +10000586: b141 cbz r1, 1000059a +10000588: 0080 lsls r0, r0, #2 +1000058a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1000058e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000592: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000596: 6003 str r3, [r0, #0] +10000598: 4770 bx lr +1000059a: 4a02 ldr r2, [pc, #8] @ (100005a4 ) +1000059c: 3020 adds r0, #32 +1000059e: f842 3020 str.w r3, [r2, r0, lsl #2] +100005a2: 4770 bx lr +100005a4: e000e100 .word 0xe000e100 + +100005a8 : +100005a8: b5f8 push {r3, r4, r5, r6, r7, lr} +100005aa: 460d mov r5, r1 +100005ac: f3ef 8710 mrs r7, PRIMASK +100005b0: b672 cpsid i +100005b2: 4e12 ldr r6, [pc, #72] @ (100005fc ) +100005b4: e8d6 2fcf ldaexb r2, [r6] +100005b8: 2301 movs r3, #1 +100005ba: 2a00 cmp r2, #0 +100005bc: d1fa bne.n 100005b4 +100005be: e8c6 3f42 strexb r2, r3, [r6] +100005c2: 2a00 cmp r2, #0 +100005c4: d1f6 bne.n 100005b4 +100005c6: f3bf 8f5f dmb sy +100005ca: 4b0d ldr r3, [pc, #52] @ (10000600 ) +100005cc: f100 0410 add.w r4, r0, #16 +100005d0: 689b ldr r3, [r3, #8] +100005d2: 4a0c ldr r2, [pc, #48] @ (10000604 ) +100005d4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100005d8: 4293 cmp r3, r2 +100005da: d003 beq.n 100005e4 +100005dc: 4299 cmp r1, r3 +100005de: d001 beq.n 100005e4 +100005e0: f000 ff0e bl 10001400 +100005e4: 4b06 ldr r3, [pc, #24] @ (10000600 ) +100005e6: 689b ldr r3, [r3, #8] +100005e8: f843 5024 str.w r5, [r3, r4, lsl #2] +100005ec: f3bf 8f5f dmb sy +100005f0: 2300 movs r3, #0 +100005f2: e8c6 3f8f stlb r3, [r6] +100005f6: f387 8810 msr PRIMASK, r7 +100005fa: bdf8 pop {r3, r4, r5, r6, r7, pc} +100005fc: 200007b9 .word 0x200007b9 +10000600: e000ed00 .word 0xe000ed00 +10000604: 10000111 .word 0x10000111 + +10000608 : +10000608: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000060c: b083 sub sp, #12 +1000060e: f3ef 8a10 mrs sl, PRIMASK +10000612: b672 cpsid i +10000614: 4e71 ldr r6, [pc, #452] @ (100007dc ) +10000616: e8d6 2fcf ldaexb r2, [r6] +1000061a: 2301 movs r3, #1 +1000061c: 2a00 cmp r2, #0 +1000061e: d1fa bne.n 10000616 +10000620: e8c6 3f42 strexb r2, r3, [r6] +10000624: 2a00 cmp r2, #0 +10000626: d1f6 bne.n 10000616 +10000628: f3bf 8f5f dmb sy +1000062c: 4b6c ldr r3, [pc, #432] @ (100007e0 ) +1000062e: f100 0810 add.w r8, r0, #16 +10000632: 689b ldr r3, [r3, #8] +10000634: 4a6b ldr r2, [pc, #428] @ (100007e4 ) +10000636: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000063a: 4295 cmp r5, r2 +1000063c: d045 beq.n 100006ca +1000063e: 428d cmp r5, r1 +10000640: 460c mov r4, r1 +10000642: d050 beq.n 100006e6 +10000644: 4f68 ldr r7, [pc, #416] @ (100007e8 ) +10000646: 1beb subs r3, r5, r7 +10000648: 2b2f cmp r3, #47 @ 0x2f +1000064a: d83e bhi.n 100006ca +1000064c: 2101 movs r1, #1 +1000064e: ea4f 1950 mov.w r9, r0, lsr #5 +10000652: ea4f 0989 mov.w r9, r9, lsl #2 +10000656: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000065a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000065e: f000 031f and.w r3, r0, #31 +10000662: fa01 f003 lsl.w r0, r1, r3 +10000666: f8d9 3000 ldr.w r3, [r9] +1000066a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000066e: ea00 0b03 and.w fp, r0, r3 +10000672: f3bf 8f5f dmb sy +10000676: f3ef 8105 mrs r1, IPSR +1000067a: b2c9 uxtb r1, r1 +1000067c: 2900 cmp r1, #0 +1000067e: d034 beq.n 100006ea +10000680: 4588 cmp r8, r1 +10000682: d005 beq.n 10000690 +10000684: e9cd 1000 strd r1, r0, [sp] +10000688: f000 feba bl 10001400 +1000068c: e9dd 1000 ldrd r1, r0, [sp] +10000690: f025 0e01 bic.w lr, r5, #1 +10000694: f8de c008 ldr.w ip, [lr, #8] +10000698: 4564 cmp r4, ip +1000069a: d105 bne.n 100006a8 +1000069c: e089 b.n 100007b2 +1000069e: f8d3 c008 ldr.w ip, [r3, #8] +100006a2: 4564 cmp r4, ip +100006a4: d031 beq.n 1000070a +100006a6: 469e mov lr, r3 +100006a8: f99e 2006 ldrsb.w r2, [lr, #6] +100006ac: eb02 0342 add.w r3, r2, r2, lsl #1 +100006b0: 2a00 cmp r2, #0 +100006b2: eb07 0383 add.w r3, r7, r3, lsl #2 +100006b6: daf2 bge.n 1000069e +100006b8: 4564 cmp r4, ip +100006ba: d061 beq.n 10000780 +100006bc: f1bb 0f00 cmp.w fp, #0 +100006c0: d020 beq.n 10000704 +100006c2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100006c6: f8c9 0000 str.w r0, [r9] +100006ca: 4b45 ldr r3, [pc, #276] @ (100007e0 ) +100006cc: 689b ldr r3, [r3, #8] +100006ce: f843 5028 str.w r5, [r3, r8, lsl #2] +100006d2: f3bf 8f5f dmb sy +100006d6: 2300 movs r3, #0 +100006d8: e8c6 3f8f stlb r3, [r6] +100006dc: f38a 8810 msr PRIMASK, sl +100006e0: b003 add sp, #12 +100006e2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100006e6: 4615 mov r5, r2 +100006e8: e7ef b.n 100006ca +100006ea: f025 0e01 bic.w lr, r5, #1 +100006ee: f8de c008 ldr.w ip, [lr, #8] +100006f2: 4564 cmp r4, ip +100006f4: d1d8 bne.n 100006a8 +100006f6: f99e 4006 ldrsb.w r4, [lr, #6] +100006fa: 4673 mov r3, lr +100006fc: 2c00 cmp r4, #0 +100006fe: da08 bge.n 10000712 +10000700: 4615 mov r5, r2 +10000702: e046 b.n 10000792 +10000704: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000708: e7df b.n 100006ca +1000070a: f993 4006 ldrsb.w r4, [r3, #6] +1000070e: 2c00 cmp r4, #0 +10000710: db37 blt.n 10000782 +10000712: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000716: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000071a: f89c 1007 ldrb.w r1, [ip, #7] +1000071e: f8dc 2008 ldr.w r2, [ip, #8] +10000722: 71d9 strb r1, [r3, #7] +10000724: 609a str r2, [r3, #8] +10000726: f99c 2006 ldrsb.w r2, [ip, #6] +1000072a: 0061 lsls r1, r4, #1 +1000072c: 2a00 cmp r2, #0 +1000072e: 719a strb r2, [r3, #6] +10000730: db3d blt.n 100007ae +10000732: f8bc e004 ldrh.w lr, [ip, #4] +10000736: ea5f 5e4e movs.w lr, lr, lsl #21 +1000073a: d505 bpl.n 10000748 +1000073c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000740: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000744: f10e 0e1f add.w lr, lr, #31 +10000748: f06f 0c07 mvn.w ip, #7 +1000074c: 190a adds r2, r1, r4 +1000074e: ea4f 5e6e mov.w lr, lr, asr #21 +10000752: 0092 lsls r2, r2, #2 +10000754: eb02 024e add.w r2, r2, lr, lsl #1 +10000758: 3208 adds r2, #8 +1000075a: 443a add r2, r7 +1000075c: ebac 0c03 sub.w ip, ip, r3 +10000760: 4462 add r2, ip +10000762: f3c2 024a ubfx r2, r2, #1, #11 +10000766: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000076a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000076e: 809a strh r2, [r3, #4] +10000770: 4b1e ldr r3, [pc, #120] @ (100007ec ) +10000772: 4421 add r1, r4 +10000774: 781a ldrb r2, [r3, #0] +10000776: eb07 0181 add.w r1, r7, r1, lsl #2 +1000077a: 701c strb r4, [r3, #0] +1000077c: 718a strb r2, [r1, #6] +1000077e: e79d b.n 100006bc +10000780: 4673 mov r3, lr +10000782: b9d9 cbnz r1, 100007bc +10000784: 22ff movs r2, #255 @ 0xff +10000786: f88e 2006 strb.w r2, [lr, #6] +1000078a: f64b 5201 movw r2, #48385 @ 0xbd01 +1000078e: f8ae 2004 strh.w r2, [lr, #4] +10000792: 4c16 ldr r4, [pc, #88] @ (100007ec ) +10000794: f64a 22aa movw r2, #43690 @ 0xaaaa +10000798: f894 c000 ldrb.w ip, [r4] +1000079c: 4619 mov r1, r3 +1000079e: 1bc9 subs r1, r1, r7 +100007a0: 4149 adcs r1, r1 +100007a2: 434a muls r2, r1 +100007a4: 0d12 lsrs r2, r2, #20 +100007a6: f883 c006 strb.w ip, [r3, #6] +100007aa: 7022 strb r2, [r4, #0] +100007ac: e786 b.n 100006bc +100007ae: 4a10 ldr r2, [pc, #64] @ (100007f0 ) +100007b0: e7dd b.n 1000076e +100007b2: f99e 4006 ldrsb.w r4, [lr, #6] +100007b6: 4673 mov r3, lr +100007b8: 2c00 cmp r4, #0 +100007ba: daaa bge.n 10000712 +100007bc: 4a0d ldr r2, [pc, #52] @ (100007f4 ) +100007be: 4c0e ldr r4, [pc, #56] @ (100007f8 ) +100007c0: 1ad2 subs r2, r2, r3 +100007c2: 3a08 subs r2, #8 +100007c4: f3c2 310a ubfx r1, r2, #12, #11 +100007c8: ea6f 5101 mvn.w r1, r1, lsl #20 +100007cc: ea6f 5111 mvn.w r1, r1, lsr #20 +100007d0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100007d4: 80da strh r2, [r3, #6] +100007d6: 8099 strh r1, [r3, #4] +100007d8: e770 b.n 100006bc +100007da: bf00 nop +100007dc: 200007b9 .word 0x200007b9 +100007e0: e000ed00 .word 0xe000ed00 +100007e4: 10000111 .word 0x10000111 +100007e8: 200005ac .word 0x200005ac +100007ec: 2000085c .word 0x2000085c +100007f0: ffffbd01 .word 0xffffbd01 +100007f4: 200005e6 .word 0x200005e6 +100007f8: fffff800 .word 0xfffff800 + +100007fc : +100007fc: b5f0 push {r4, r5, r6, r7, lr} +100007fe: f3ef 8505 mrs r5, IPSR +10000802: b2ed uxtb r5, r5 +10000804: f3ef 8c10 mrs ip, PRIMASK +10000808: b672 cpsid i +1000080a: 4926 ldr r1, [pc, #152] @ (100008a4 ) +1000080c: e8d1 2fcf ldaexb r2, [r1] +10000810: 2301 movs r3, #1 +10000812: 2a00 cmp r2, #0 +10000814: d1fa bne.n 1000080c +10000816: e8c1 3f42 strexb r2, r3, [r1] +1000081a: 2a00 cmp r2, #0 +1000081c: d1f6 bne.n 1000080c +1000081e: f3bf 8f5f dmb sy +10000822: 4e21 ldr r6, [pc, #132] @ (100008a8 ) +10000824: f040 0e01 orr.w lr, r0, #1 +10000828: 68b4 ldr r4, [r6, #8] +1000082a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000082e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000832: 4a1e ldr r2, [pc, #120] @ (100008ac ) +10000834: 4604 mov r4, r0 +10000836: 1aa4 subs r4, r4, r2 +10000838: 4164 adcs r4, r4 +1000083a: 4363 muls r3, r4 +1000083c: 0d1b lsrs r3, r3, #20 +1000083e: 4577 cmp r7, lr +10000840: b25b sxtb r3, r3 +10000842: d01b beq.n 1000087c +10000844: f992 4006 ldrsb.w r4, [r2, #6] +10000848: 429c cmp r4, r3 +1000084a: d01c beq.n 10000886 +1000084c: f992 4012 ldrsb.w r4, [r2, #18] +10000850: 429c cmp r4, r3 +10000852: d023 beq.n 1000089c +10000854: f992 401e ldrsb.w r4, [r2, #30] +10000858: 429c cmp r4, r3 +1000085a: d021 beq.n 100008a0 +1000085c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000860: 429c cmp r4, r3 +10000862: bf08 it eq +10000864: 2403 moveq r4, #3 +10000866: d00f beq.n 10000888 +10000868: 4a11 ldr r2, [pc, #68] @ (100008b0 ) +1000086a: 2400 movs r4, #0 +1000086c: 7815 ldrb r5, [r2, #0] +1000086e: 7013 strb r3, [r2, #0] +10000870: 7185 strb r5, [r0, #6] +10000872: e8c1 4f8f stlb r4, [r1] +10000876: f38c 8810 msr PRIMASK, ip +1000087a: bdf0 pop {r4, r5, r6, r7, pc} +1000087c: 68b2 ldr r2, [r6, #8] +1000087e: 4c0d ldr r4, [pc, #52] @ (100008b4 ) +10000880: f842 4025 str.w r4, [r2, r5, lsl #2] +10000884: e7f0 b.n 10000868 +10000886: 2400 movs r4, #0 +10000888: eb04 0444 add.w r4, r4, r4, lsl #1 +1000088c: eb02 0284 add.w r2, r2, r4, lsl #2 +10000890: 24ff movs r4, #255 @ 0xff +10000892: 7194 strb r4, [r2, #6] +10000894: f64b 5401 movw r4, #48385 @ 0xbd01 +10000898: 8094 strh r4, [r2, #4] +1000089a: e7e5 b.n 10000868 +1000089c: 2401 movs r4, #1 +1000089e: e7f3 b.n 10000888 +100008a0: 2402 movs r4, #2 +100008a2: e7f1 b.n 10000888 +100008a4: 200007b9 .word 0x200007b9 +100008a8: e000ed00 .word 0xe000ed00 +100008ac: 200005ac .word 0x200005ac +100008b0: 2000085c .word 0x2000085c +100008b4: 10000111 .word 0x10000111 + +100008b8 : +100008b8: 4b01 ldr r3, [pc, #4] @ (100008c0 ) +100008ba: 440b add r3, r1 +100008bc: 6003 str r3, [r0, #0] +100008be: 4770 bx lr +100008c0: 200007b0 .word 0x200007b0 + +100008c4 : +100008c4: b570 push {r4, r5, r6, lr} +100008c6: 4c10 ldr r4, [pc, #64] @ (10000908 ) +100008c8: 4d10 ldr r5, [pc, #64] @ (1000090c ) +100008ca: 42ac cmp r4, r5 +100008cc: d20e bcs.n 100008ec +100008ce: 26ff movs r6, #255 @ 0xff +100008d0: 6823 ldr r3, [r4, #0] +100008d2: b163 cbz r3, 100008ee +100008d4: f7ff fe12 bl 100004fc +100008d8: 4601 mov r1, r0 +100008da: 4620 mov r0, r4 +100008dc: f7ff ffec bl 100008b8 +100008e0: 80a6 strh r6, [r4, #4] +100008e2: f3bf 8f5f dmb sy +100008e6: 3408 adds r4, #8 +100008e8: 42ac cmp r4, r5 +100008ea: d3f1 bcc.n 100008d0 +100008ec: bd70 pop {r4, r5, r6, pc} +100008ee: f7ff fe05 bl 100004fc +100008f2: 4601 mov r1, r0 +100008f4: 4620 mov r0, r4 +100008f6: f7ff ffdf bl 100008b8 +100008fa: 7126 strb r6, [r4, #4] +100008fc: f3bf 8f5f dmb sy +10000900: 3408 adds r4, #8 +10000902: 42ac cmp r4, r5 +10000904: d3e4 bcc.n 100008d0 +10000906: bd70 pop {r4, r5, r6, pc} +10000908: 20000624 .word 0x20000624 +1000090c: 2000062c .word 0x2000062c + +10000910 : +10000910: 4b0d ldr r3, [pc, #52] @ (10000948 ) +10000912: 681a ldr r2, [r3, #0] +10000914: f3ef 8110 mrs r1, PRIMASK +10000918: b672 cpsid i +1000091a: e8d2 cfcf ldaexb ip, [r2] +1000091e: 2001 movs r0, #1 +10000920: f1bc 0f00 cmp.w ip, #0 +10000924: d1f9 bne.n 1000091a +10000926: e8c2 0f4c strexb ip, r0, [r2] +1000092a: f1bc 0f00 cmp.w ip, #0 +1000092e: d1f4 bne.n 1000091a +10000930: f3bf 8f5f dmb sy +10000934: 2200 movs r2, #0 +10000936: 681b ldr r3, [r3, #0] +10000938: e8c3 2f8f stlb r2, [r3] +1000093c: f381 8810 msr PRIMASK, r1 +10000940: bf40 sev +10000942: 2000 movs r0, #0 +10000944: 2100 movs r1, #0 +10000946: 4770 bx lr +10000948: 20000850 .word 0x20000850 +1000094c: 00000000 .word 0x00000000 + +10000950 : +10000950: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000954: ed2d 8b02 vpush {d8} +10000958: b085 sub sp, #20 +1000095a: f3ef 8305 mrs r3, IPSR +1000095e: b2db uxtb r3, r3 +10000960: 3b10 subs r3, #16 +10000962: 089a lsrs r2, r3, #2 +10000964: bf18 it ne +10000966: 2201 movne r2, #1 +10000968: f04f 0101 mov.w r1, #1 +1000096c: f003 0b03 and.w fp, r3, #3 +10000970: bf18 it ne +10000972: 4daf ldrne r5, [pc, #700] @ (10000c30 ) +10000974: 4baf ldr r3, [pc, #700] @ (10000c34 ) +10000976: bf08 it eq +10000978: 4daf ldreq r5, [pc, #700] @ (10000c38 ) +1000097a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000097e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000982: fa01 f20b lsl.w r2, r1, fp +10000986: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000098a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000c28 +1000098e: 9201 str r2, [sp, #4] +10000990: 605a str r2, [r3, #4] +10000992: e02f b.n 100009f4 +10000994: 88b3 ldrh r3, [r6, #4] +10000996: 041c lsls r4, r3, #16 +10000998: f140 8093 bpl.w 10000ac2 +1000099c: 79b3 ldrb r3, [r6, #6] +1000099e: 2b00 cmp r3, #0 +100009a0: f040 80dd bne.w 10000b5e +100009a4: f9b6 2008 ldrsh.w r2, [r6, #8] +100009a8: 2a00 cmp r2, #0 +100009aa: f2c0 811e blt.w 10000bea +100009ae: 6973 ldr r3, [r6, #20] +100009b0: eb02 0242 add.w r2, r2, r2, lsl #1 +100009b4: eb03 03c2 add.w r3, r3, r2, lsl #3 +100009b8: e9d3 4702 ldrd r4, r7, [r3, #8] +100009bc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +100009c0: bf08 it eq +100009c2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +100009c6: d00e beq.n 100009e6 +100009c8: eb05 018b add.w r1, r5, fp, lsl #2 +100009cc: 6aab ldr r3, [r5, #40] @ 0x28 +100009ce: 690a ldr r2, [r1, #16] +100009d0: 1ad2 subs r2, r2, r3 +100009d2: 1ae3 subs r3, r4, r3 +100009d4: 4293 cmp r3, r2 +100009d6: d305 bcc.n 100009e4 +100009d8: 2301 movs r3, #1 +100009da: 6a2a ldr r2, [r5, #32] +100009dc: fa03 f30b lsl.w r3, r3, fp +100009e0: 4213 tst r3, r2 +100009e2: d100 bne.n 100009e6 +100009e4: 610c str r4, [r1, #16] +100009e6: 4628 mov r0, r5 +100009e8: f000 fb38 bl 1000105c +100009ec: 42a0 cmp r0, r4 +100009ee: 41b9 sbcs r1, r7 +100009f0: f2c0 80fb blt.w 10000bea +100009f4: f9b6 3008 ldrsh.w r3, [r6, #8] +100009f8: 9a01 ldr r2, [sp, #4] +100009fa: 2b00 cmp r3, #0 +100009fc: 9300 str r3, [sp, #0] +100009fe: 63ea str r2, [r5, #60] @ 0x3c +10000a00: dbc8 blt.n 10000994 +10000a02: f8d6 8014 ldr.w r8, [r6, #20] +10000a06: eb03 0943 add.w r9, r3, r3, lsl #1 +10000a0a: 4628 mov r0, r5 +10000a0c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000a10: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000a14: f000 fb22 bl 1000105c +10000a18: 42a0 cmp r0, r4 +10000a1a: eb71 010a sbcs.w r1, r1, sl +10000a1e: dbb9 blt.n 10000994 +10000a20: f1ba 0f00 cmp.w sl, #0 +10000a24: f2c0 80c3 blt.w 10000bae +10000a28: e9d7 3104 ldrd r3, r1, [r7, #16] +10000a2c: 4a83 ldr r2, [pc, #524] @ (10000c3c ) +10000a2e: 4293 cmp r3, r2 +10000a30: f000 80ed beq.w 10000c0e +10000a34: 887a ldrh r2, [r7, #2] +10000a36: f9b6 0008 ldrsh.w r0, [r6, #8] +10000a3a: b292 uxth r2, r2 +10000a3c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000a40: 4798 blx r3 +10000a42: 4602 mov r2, r0 +10000a44: 460b mov r3, r1 +10000a46: ea52 0103 orrs.w r1, r2, r3 +10000a4a: f000 80b0 beq.w 10000bae +10000a4e: 2b00 cmp r3, #0 +10000a50: f280 80d1 bge.w 10000bf6 +10000a54: ebb4 0e02 subs.w lr, r4, r2 +10000a58: eb6a 0a03 sbc.w sl, sl, r3 +10000a5c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000a60: e9c7 ea02 strd lr, sl, [r7, #8] +10000a64: 2b00 cmp r3, #0 +10000a66: db95 blt.n 10000994 +10000a68: 6971 ldr r1, [r6, #20] +10000a6a: eb03 0243 add.w r2, r3, r3, lsl #1 +10000a6e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000a72: e9d2 7002 ldrd r7, r0, [r2, #8] +10000a76: 45be cmp lr, r7 +10000a78: eb7a 0c00 sbcs.w ip, sl, r0 +10000a7c: ea4f 0243 mov.w r2, r3, lsl #1 +10000a80: db88 blt.n 10000994 +10000a82: 46b4 mov ip, r6 +10000a84: f82c 3f08 strh.w r3, [ip, #8]! +10000a88: e006 b.n 10000a98 +10000a8a: eb03 0043 add.w r0, r3, r3, lsl #1 +10000a8e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000a92: 005a lsls r2, r3, #1 +10000a94: e9d0 7002 ldrd r7, r0, [r0, #8] +10000a98: 45be cmp lr, r7 +10000a9a: 441a add r2, r3 +10000a9c: eb7a 0000 sbcs.w r0, sl, r0 +10000aa0: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000aa4: db04 blt.n 10000ab0 +10000aa6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000aaa: 46a4 mov ip, r4 +10000aac: 2b00 cmp r3, #0 +10000aae: daec bge.n 10000a8a +10000ab0: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000ab4: 9b00 ldr r3, [sp, #0] +10000ab6: f8ac 3000 strh.w r3, [ip] +10000aba: 88b3 ldrh r3, [r6, #4] +10000abc: 041c lsls r4, r3, #16 +10000abe: f53f af6d bmi.w 1000099c +10000ac2: 6933 ldr r3, [r6, #16] +10000ac4: f3ef 8210 mrs r2, PRIMASK +10000ac8: b672 cpsid i +10000aca: e8d3 0fcf ldaexb r0, [r3] +10000ace: 2101 movs r1, #1 +10000ad0: 2800 cmp r0, #0 +10000ad2: d1fa bne.n 10000aca +10000ad4: e8c3 1f40 strexb r0, r1, [r3] +10000ad8: 2800 cmp r0, #0 +10000ada: d1f6 bne.n 10000aca +10000adc: f3bf 8f5f dmb sy +10000ae0: f64f 74ff movw r4, #65535 @ 0xffff +10000ae4: 88b0 ldrh r0, [r6, #4] +10000ae6: 2300 movs r3, #0 +10000ae8: 6931 ldr r1, [r6, #16] +10000aea: b200 sxth r0, r0 +10000aec: 80b4 strh r4, [r6, #4] +10000aee: e8c1 3f8f stlb r3, [r1] +10000af2: f382 8810 msr PRIMASK, r2 +10000af6: 4298 cmp r0, r3 +10000af8: f6ff af50 blt.w 1000099c +10000afc: 4607 mov r7, r0 +10000afe: 46a9 mov r9, r5 +10000b00: 6974 ldr r4, [r6, #20] +10000b02: f106 0808 add.w r8, r6, #8 +10000b06: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000b0a: eb04 03ce add.w r3, r4, lr, lsl #3 +10000b0e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000b12: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b16: 46c4 mov ip, r8 +10000b18: 2b00 cmp r3, #0 +10000b1a: db13 blt.n 10000b44 +10000b1c: 46b2 mov sl, r6 +10000b1e: 9700 str r7, [sp, #0] +10000b20: e004 b.n 10000b2c +10000b22: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000b26: 4694 mov ip, r2 +10000b28: 2b00 cmp r3, #0 +10000b2a: db09 blt.n 10000b40 +10000b2c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000b30: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000b34: e9d2 7102 ldrd r7, r1, [r2, #8] +10000b38: 42bd cmp r5, r7 +10000b3a: eb70 0101 sbcs.w r1, r0, r1 +10000b3e: daf0 bge.n 10000b22 +10000b40: 4656 mov r6, sl +10000b42: 9f00 ldr r7, [sp, #0] +10000b44: f8ac 7000 strh.w r7, [ip] +10000b48: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000b4c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000b50: 2f00 cmp r7, #0 +10000b52: dad8 bge.n 10000b06 +10000b54: 79b3 ldrb r3, [r6, #6] +10000b56: 464d mov r5, r9 +10000b58: 2b00 cmp r3, #0 +10000b5a: f43f af23 beq.w 100009a4 +10000b5e: 2300 movs r3, #0 +10000b60: 71b3 strb r3, [r6, #6] +10000b62: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b66: f106 0808 add.w r8, r6, #8 +10000b6a: 1c58 adds r0, r3, #1 +10000b6c: d03d beq.n 10000bea +10000b6e: 461a mov r2, r3 +10000b70: 6977 ldr r7, [r6, #20] +10000b72: e003 b.n 10000b7c +10000b74: 4680 mov r8, r0 +10000b76: 1c59 adds r1, r3, #1 +10000b78: f43f af16 beq.w 100009a8 +10000b7c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000b80: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000b84: f8b0 c002 ldrh.w ip, [r0, #2] +10000b88: 461c mov r4, r3 +10000b8a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000b8e: 469e mov lr, r3 +10000b90: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000b94: d0ee beq.n 10000b74 +10000b96: 4294 cmp r4, r2 +10000b98: ed80 8b02 vstr d8, [r0, #8] +10000b9c: d005 beq.n 10000baa +10000b9e: f8a8 3000 strh.w r3, [r8] +10000ba2: 8932 ldrh r2, [r6, #8] +10000ba4: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000ba8: 8134 strh r4, [r6, #8] +10000baa: 4672 mov r2, lr +10000bac: e7e3 b.n 10000b76 +10000bae: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000bb2: 8133 strh r3, [r6, #8] +10000bb4: 6933 ldr r3, [r6, #16] +10000bb6: f3ef 8210 mrs r2, PRIMASK +10000bba: b672 cpsid i +10000bbc: e8d3 0fcf ldaexb r0, [r3] +10000bc0: 2101 movs r1, #1 +10000bc2: 2800 cmp r0, #0 +10000bc4: d1fa bne.n 10000bbc +10000bc6: e8c3 1f40 strexb r0, r1, [r3] +10000bca: 2800 cmp r0, #0 +10000bcc: d1f6 bne.n 10000bbc +10000bce: f3bf 8f5f dmb sy +10000bd2: 8873 ldrh r3, [r6, #2] +10000bd4: 6931 ldr r1, [r6, #16] +10000bd6: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000bda: 9b00 ldr r3, [sp, #0] +10000bdc: 8073 strh r3, [r6, #2] +10000bde: 2300 movs r3, #0 +10000be0: e8c1 3f8f stlb r3, [r1] +10000be4: f382 8810 msr PRIMASK, r2 +10000be8: e6d4 b.n 10000994 +10000bea: bf40 sev +10000bec: b005 add sp, #20 +10000bee: ecbd 8b02 vpop {d8} +10000bf2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000bf6: 4628 mov r0, r5 +10000bf8: e9cd 2302 strd r2, r3, [sp, #8] +10000bfc: f000 fa2e bl 1000105c +10000c00: 9a02 ldr r2, [sp, #8] +10000c02: 9b03 ldr r3, [sp, #12] +10000c04: eb10 0e02 adds.w lr, r0, r2 +10000c08: eb43 0a01 adc.w sl, r3, r1 +10000c0c: e726 b.n 10000a5c +10000c0e: 4608 mov r0, r1 +10000c10: 690b ldr r3, [r1, #16] +10000c12: 9102 str r1, [sp, #8] +10000c14: 4798 blx r3 +10000c16: 2800 cmp r0, #0 +10000c18: d0c9 beq.n 10000bae +10000c1a: 9902 ldr r1, [sp, #8] +10000c1c: e9d1 2300 ldrd r2, r3, [r1] +10000c20: e711 b.n 10000a46 +10000c22: bf00 nop +10000c24: f3af 8000 nop.w +10000c28: ffffffff .word 0xffffffff +10000c2c: ffffffff .word 0xffffffff +10000c30: 400b8000 .word 0x400b8000 +10000c34: 20000828 .word 0x20000828 +10000c38: 400b0000 .word 0x400b0000 +10000c3c: 10000951 .word 0x10000951 + +10000c40 : +10000c40: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000c44: 4c36 ldr r4, [pc, #216] @ (10000d20 ) +10000c46: 6925 ldr r5, [r4, #16] +10000c48: b12d cbz r5, 10000c56 +10000c4a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000c4e: 210a movs r1, #10 +10000c50: 4834 ldr r0, [pc, #208] @ (10000d24 ) +10000c52: f7ff be31 b.w 100008b8 +10000c56: f8df 80e4 ldr.w r8, [pc, #228] @ 10000d3c +10000c5a: 2103 movs r1, #3 +10000c5c: 4640 mov r0, r8 +10000c5e: f000 f9eb bl 10001038 +10000c62: 2603 movs r6, #3 +10000c64: f8c4 800c str.w r8, [r4, #12] +10000c68: f7ff fc48 bl 100004fc +10000c6c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000c70: 4b2d ldr r3, [pc, #180] @ (10000d28 ) +10000c72: 7026 strb r6, [r4, #0] +10000c74: 4403 add r3, r0 +10000c76: 6123 str r3, [r4, #16] +10000c78: f8dc 3000 ldr.w r3, [ip] +10000c7c: 210f movs r1, #15 +10000c7e: 7063 strb r3, [r4, #1] +10000c80: 6963 ldr r3, [r4, #20] +10000c82: 8061 strh r1, [r4, #2] +10000c84: 831d strh r5, [r3, #24] +10000c86: f04f 0504 mov.w r5, #4 +10000c8a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000c8e: f04f 0505 mov.w r5, #5 +10000c92: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000c96: f04f 0506 mov.w r5, #6 +10000c9a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000c9e: f04f 0507 mov.w r5, #7 +10000ca2: 210e movs r1, #14 +10000ca4: f64f 72ff movw r2, #65535 @ 0xffff +10000ca8: 2708 movs r7, #8 +10000caa: f04f 0e0a mov.w lr, #10 +10000cae: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000cb2: f04f 0901 mov.w r9, #1 +10000cb6: f04f 0c0c mov.w ip, #12 +10000cba: f04f 0b02 mov.w fp, #2 +10000cbe: f04f 0a09 mov.w sl, #9 +10000cc2: 200d movs r0, #13 +10000cc4: f04f 050b mov.w r5, #11 +10000cc8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000ccc: 4917 ldr r1, [pc, #92] @ (10000d2c ) +10000cce: 80a2 strh r2, [r4, #4] +10000cd0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000cd4: 60a1 str r1, [r4, #8] +10000cd6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000cda: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000cde: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000ce2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000ce6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000cea: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000cee: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000cf2: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000cf6: 801a strh r2, [r3, #0] +10000cf8: 4b0d ldr r3, [pc, #52] @ (10000d30 ) +10000cfa: 4630 mov r0, r6 +10000cfc: f8c8 7020 str.w r7, [r8, #32] +10000d00: 490c ldr r1, [pc, #48] @ (10000d34 ) +10000d02: 60dc str r4, [r3, #12] +10000d04: f7ff fc50 bl 100005a8 +10000d08: 4649 mov r1, r9 +10000d0a: 4630 mov r0, r6 +10000d0c: f7ff fc36 bl 1000057c +10000d10: 4b09 ldr r3, [pc, #36] @ (10000d38 ) +10000d12: 210a movs r1, #10 +10000d14: 641f str r7, [r3, #64] @ 0x40 +10000d16: 4803 ldr r0, [pc, #12] @ (10000d24 ) +10000d18: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000d1c: f7ff bdcc b.w 100008b8 +10000d20: 200005f4 .word 0x200005f4 +10000d24: 20000850 .word 0x20000850 +10000d28: 200007b0 .word 0x200007b0 +10000d2c: 0010ffff .word 0x0010ffff +10000d30: 20000828 .word 0x20000828 +10000d34: 10000951 .word 0x10000951 +10000d38: 400b2000 .word 0x400b2000 +10000d3c: 400b0000 .word 0x400b0000 + +10000d40 : +10000d40: 4601 mov r1, r0 +10000d42: b5f0 push {r4, r5, r6, r7, lr} +10000d44: 6900 ldr r0, [r0, #16] +10000d46: f3ef 8710 mrs r7, PRIMASK +10000d4a: b672 cpsid i +10000d4c: e8d0 5fcf ldaexb r5, [r0] +10000d50: 2401 movs r4, #1 +10000d52: 2d00 cmp r5, #0 +10000d54: d1fa bne.n 10000d4c +10000d56: e8c0 4f45 strexb r5, r4, [r0] +10000d5a: 2d00 cmp r5, #0 +10000d5c: d1f6 bne.n 10000d4c +10000d5e: f3bf 8f5f dmb sy +10000d62: f9b1 e002 ldrsh.w lr, [r1, #2] +10000d66: 694c ldr r4, [r1, #20] +10000d68: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000d6c: f1be 0f00 cmp.w lr, #0 +10000d70: ea4f 05cc mov.w r5, ip, lsl #3 +10000d74: 6908 ldr r0, [r1, #16] +10000d76: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000d7a: db3c blt.n 10000df6 +10000d7c: 5b66 ldrh r6, [r4, r5] +10000d7e: 804e strh r6, [r1, #2] +10000d80: 2600 movs r6, #0 +10000d82: e8c0 6f8f stlb r6, [r0] +10000d86: f387 8810 msr PRIMASK, r7 +10000d8a: f8bc 0002 ldrh.w r0, [ip, #2] +10000d8e: e9cc 2302 strd r2, r3, [ip, #8] +10000d92: 3001 adds r0, #1 +10000d94: f3c0 000e ubfx r0, r0, #0, #15 +10000d98: 2801 cmp r0, #1 +10000d9a: bf38 it cc +10000d9c: 2001 movcc r0, #1 +10000d9e: 9b05 ldr r3, [sp, #20] +10000da0: f8ac 0002 strh.w r0, [ip, #2] +10000da4: f8cc 3010 str.w r3, [ip, #16] +10000da8: 9b06 ldr r3, [sp, #24] +10000daa: ea40 400e orr.w r0, r0, lr, lsl #16 +10000dae: f8cc 3014 str.w r3, [ip, #20] +10000db2: 690b ldr r3, [r1, #16] +10000db4: f3ef 8210 mrs r2, PRIMASK +10000db8: b672 cpsid i +10000dba: e8d3 cfcf ldaexb ip, [r3] +10000dbe: 2701 movs r7, #1 +10000dc0: f1bc 0f00 cmp.w ip, #0 +10000dc4: d1f9 bne.n 10000dba +10000dc6: e8c3 7f4c strexb ip, r7, [r3] +10000dca: f1bc 0f00 cmp.w ip, #0 +10000dce: d1f4 bne.n 10000dba +10000dd0: f3bf 8f5f dmb sy +10000dd4: 888b ldrh r3, [r1, #4] +10000dd6: 5363 strh r3, [r4, r5] +10000dd8: f8a1 e004 strh.w lr, [r1, #4] +10000ddc: 690b ldr r3, [r1, #16] +10000dde: e8c3 6f8f stlb r6, [r3] +10000de2: f382 8810 msr PRIMASK, r2 +10000de6: 2201 movs r2, #1 +10000de8: 68cb ldr r3, [r1, #12] +10000dea: 7809 ldrb r1, [r1, #0] +10000dec: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000df0: 408a lsls r2, r1 +10000df2: 605a str r2, [r3, #4] +10000df4: bdf0 pop {r4, r5, r6, r7, pc} +10000df6: 2300 movs r3, #0 +10000df8: e8c0 3f8f stlb r3, [r0] +10000dfc: f387 8810 msr PRIMASK, r7 +10000e00: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000e04: bdf0 pop {r4, r5, r6, r7, pc} +10000e06: bf00 nop + +10000e08 : +10000e08: 4603 mov r3, r0 +10000e0a: 8940 ldrh r0, [r0, #10] +10000e0c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000e10: dd37 ble.n 10000e82 +10000e12: 6958 ldr r0, [r3, #20] +10000e14: 140a asrs r2, r1, #16 +10000e16: eb02 0242 add.w r2, r2, r2, lsl #1 +10000e1a: b510 push {r4, lr} +10000e1c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000e20: 691c ldr r4, [r3, #16] +10000e22: f3ef 8c10 mrs ip, PRIMASK +10000e26: b672 cpsid i +10000e28: e8d4 efcf ldaexb lr, [r4] +10000e2c: 2201 movs r2, #1 +10000e2e: f1be 0f00 cmp.w lr, #0 +10000e32: d1f9 bne.n 10000e28 +10000e34: e8c4 2f4e strexb lr, r2, [r4] +10000e38: f1be 0f00 cmp.w lr, #0 +10000e3c: d1f4 bne.n 10000e28 +10000e3e: f3bf 8f5f dmb sy +10000e42: 8842 ldrh r2, [r0, #2] +10000e44: b289 uxth r1, r1 +10000e46: b292 uxth r2, r2 +10000e48: 428a cmp r2, r1 +10000e4a: d007 beq.n 10000e5c +10000e4c: 2200 movs r2, #0 +10000e4e: 691b ldr r3, [r3, #16] +10000e50: e8c3 2f8f stlb r2, [r3] +10000e54: f38c 8810 msr PRIMASK, ip +10000e58: 2000 movs r0, #0 +10000e5a: bd10 pop {r4, pc} +10000e5c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000e60: 8042 strh r2, [r0, #2] +10000e62: 2101 movs r1, #1 +10000e64: 2200 movs r2, #0 +10000e66: 6918 ldr r0, [r3, #16] +10000e68: 7199 strb r1, [r3, #6] +10000e6a: e8c0 2f8f stlb r2, [r0] +10000e6e: f38c 8810 msr PRIMASK, ip +10000e72: 781c ldrb r4, [r3, #0] +10000e74: 68da ldr r2, [r3, #12] +10000e76: 4608 mov r0, r1 +10000e78: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000e7c: 40a1 lsls r1, r4 +10000e7e: 6059 str r1, [r3, #4] +10000e80: bd10 pop {r4, pc} +10000e82: 2000 movs r0, #0 +10000e84: 4770 bx lr +10000e86: bf00 nop + +10000e88 : +10000e88: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000e8c: b082 sub sp, #8 +10000e8e: 4606 mov r6, r0 +10000e90: f000 f8ec bl 1000106c +10000e94: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000e98: 4604 mov r4, r0 +10000e9a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000e9e: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000ea2: fbe6 4103 umlal r4, r1, r6, r3 +10000ea6: 42a0 cmp r0, r4 +10000ea8: eb72 0301 sbcs.w r3, r2, r1 +10000eac: bf3a itte cc +10000eae: 4604 movcc r4, r0 +10000eb0: 4615 movcc r5, r2 +10000eb2: 460d movcs r5, r1 +10000eb4: 1fa6 subs r6, r4, #6 +10000eb6: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000eba: 42b4 cmp r4, r6 +10000ebc: eb75 0307 sbcs.w r3, r5, r7 +10000ec0: bf3c itt cc +10000ec2: 2600 movcc r6, #0 +10000ec4: 4637 movcc r7, r6 +10000ec6: f000 f8d1 bl 1000106c +10000eca: 1a30 subs r0, r6, r0 +10000ecc: eb67 0101 sbc.w r1, r7, r1 +10000ed0: 2801 cmp r0, #1 +10000ed2: f171 0100 sbcs.w r1, r1, #0 +10000ed6: da06 bge.n 10000ee6 +10000ed8: 4620 mov r0, r4 +10000eda: 4629 mov r1, r5 +10000edc: b002 add sp, #8 +10000ede: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000ee2: f000 b8fb b.w 100010dc +10000ee6: f000 f8c1 bl 1000106c +10000eea: 4286 cmp r6, r0 +10000eec: eb67 0101 sbc.w r1, r7, r1 +10000ef0: 2900 cmp r1, #0 +10000ef2: db0a blt.n 10000f0a +10000ef4: 2100 movs r1, #0 +10000ef6: 4b17 ldr r3, [pc, #92] @ (10000f54 ) +10000ef8: 4632 mov r2, r6 +10000efa: 9300 str r3, [sp, #0] +10000efc: 4816 ldr r0, [pc, #88] @ (10000f58 ) +10000efe: 463b mov r3, r7 +10000f00: 9101 str r1, [sp, #4] +10000f02: f7ff ff1d bl 10000d40 +10000f06: 3001 adds r0, #1 +10000f08: d0e6 beq.n 10000ed8 +10000f0a: f04f 0c00 mov.w ip, #0 +10000f0e: 4a13 ldr r2, [pc, #76] @ (10000f5c ) +10000f10: 4913 ldr r1, [pc, #76] @ (10000f60 ) +10000f12: 6a53 ldr r3, [r2, #36] @ 0x24 +10000f14: 429f cmp r7, r3 +10000f16: d804 bhi.n 10000f22 +10000f18: 6a90 ldr r0, [r2, #40] @ 0x28 +10000f1a: 42b0 cmp r0, r6 +10000f1c: d2dc bcs.n 10000ed8 +10000f1e: 429f cmp r7, r3 +10000f20: d1da bne.n 10000ed8 +10000f22: 680b ldr r3, [r1, #0] +10000f24: f3ef 8010 mrs r0, PRIMASK +10000f28: b672 cpsid i +10000f2a: e8d3 8fcf ldaexb r8, [r3] +10000f2e: f05f 0e01 movs.w lr, #1 +10000f32: f1b8 0f00 cmp.w r8, #0 +10000f36: d1f8 bne.n 10000f2a +10000f38: e8c3 ef48 strexb r8, lr, [r3] +10000f3c: f1b8 0f00 cmp.w r8, #0 +10000f40: d1f3 bne.n 10000f2a +10000f42: f3bf 8f5f dmb sy +10000f46: 680b ldr r3, [r1, #0] +10000f48: e8c3 cf8f stlb ip, [r3] +10000f4c: f380 8810 msr PRIMASK, r0 +10000f50: bf20 wfe +10000f52: e7de b.n 10000f12 +10000f54: 10000911 .word 0x10000911 +10000f58: 200005f4 .word 0x200005f4 +10000f5c: 400b0000 .word 0x400b0000 +10000f60: 20000850 .word 0x20000850 + +10000f64 : +10000f64: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000f68: 4606 mov r6, r0 +10000f6a: 460d mov r5, r1 +10000f6c: b083 sub sp, #12 +10000f6e: f3ef 8405 mrs r4, IPSR +10000f72: b2e4 uxtb r4, r4 +10000f74: b13c cbz r4, 10000f86 +10000f76: 4b2d ldr r3, [pc, #180] @ (1000102c ) +10000f78: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f7a: 42aa cmp r2, r5 +10000f7c: d21c bcs.n 10000fb8 +10000f7e: 2000 movs r0, #0 +10000f80: b003 add sp, #12 +10000f82: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000f86: 4f2a ldr r7, [pc, #168] @ (10001030 ) +10000f88: f8d7 900c ldr.w r9, [r7, #12] +10000f8c: f897 8000 ldrb.w r8, [r7] +10000f90: 4648 mov r0, r9 +10000f92: f000 f863 bl 1000105c +10000f96: f108 0804 add.w r8, r8, #4 +10000f9a: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000f9e: 1a1b subs r3, r3, r0 +10000fa0: 1a30 subs r0, r6, r0 +10000fa2: eb65 0101 sbc.w r1, r5, r1 +10000fa6: 4298 cmp r0, r3 +10000fa8: f171 0100 sbcs.w r1, r1, #0 +10000fac: db10 blt.n 10000fd0 +10000fae: bf20 wfe +10000fb0: 4b1e ldr r3, [pc, #120] @ (1000102c ) +10000fb2: 6a5a ldr r2, [r3, #36] @ 0x24 +10000fb4: 42aa cmp r2, r5 +10000fb6: d3e2 bcc.n 10000f7e +10000fb8: bf14 ite ne +10000fba: 2401 movne r4, #1 +10000fbc: 2400 moveq r4, #0 +10000fbe: 6a9b ldr r3, [r3, #40] @ 0x28 +10000fc0: 42b3 cmp r3, r6 +10000fc2: bf34 ite cc +10000fc4: 4620 movcc r0, r4 +10000fc6: f044 0001 orrcs.w r0, r4, #1 +10000fca: b003 add sp, #12 +10000fcc: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000fd0: f000 f84c bl 1000106c +10000fd4: 4286 cmp r6, r0 +10000fd6: eb65 0101 sbc.w r1, r5, r1 +10000fda: 2900 cmp r1, #0 +10000fdc: db14 blt.n 10001008 +10000fde: 4b15 ldr r3, [pc, #84] @ (10001034 ) +10000fe0: 4638 mov r0, r7 +10000fe2: e9cd 3400 strd r3, r4, [sp] +10000fe6: 4632 mov r2, r6 +10000fe8: 462b mov r3, r5 +10000fea: f7ff fea9 bl 10000d40 +10000fee: 1e01 subs r1, r0, #0 +10000ff0: dd0a ble.n 10001008 +10000ff2: 4b0e ldr r3, [pc, #56] @ (1000102c ) +10000ff4: 6a5a ldr r2, [r3, #36] @ 0x24 +10000ff6: 42aa cmp r2, r5 +10000ff8: d316 bcc.n 10001028 +10000ffa: 6a9b ldr r3, [r3, #40] @ 0x28 +10000ffc: 42b3 cmp r3, r6 +10000ffe: d311 bcc.n 10001024 +10001000: 480b ldr r0, [pc, #44] @ (10001030 ) +10001002: f7ff ff01 bl 10000e08 +10001006: e7b6 b.n 10000f76 +10001008: 4b08 ldr r3, [pc, #32] @ (1000102c ) +1000100a: 6a5c ldr r4, [r3, #36] @ 0x24 +1000100c: 42ac cmp r4, r5 +1000100e: d3b6 bcc.n 10000f7e +10001010: 1b64 subs r4, r4, r5 +10001012: bf18 it ne +10001014: 2401 movne r4, #1 +10001016: 6a9b ldr r3, [r3, #40] @ 0x28 +10001018: 42b3 cmp r3, r6 +1000101a: bf34 ite cc +1000101c: 4620 movcc r0, r4 +1000101e: f044 0001 orrcs.w r0, r4, #1 +10001022: e7ad b.n 10000f80 +10001024: 42aa cmp r2, r5 +10001026: d1eb bne.n 10001000 +10001028: bf20 wfe +1000102a: e7e9 b.n 10001000 +1000102c: 400b0000 .word 0x400b0000 +10001030: 200005f4 .word 0x200005f4 +10001034: 10000911 .word 0x10000911 + +10001038 : +10001038: b410 push {r4} +1000103a: 4b05 ldr r3, [pc, #20] @ (10001050 ) +1000103c: 4c05 ldr r4, [pc, #20] @ (10001054 ) +1000103e: 4a06 ldr r2, [pc, #24] @ (10001058 ) +10001040: 42a0 cmp r0, r4 +10001042: bf14 ite ne +10001044: 4618 movne r0, r3 +10001046: 1c58 addeq r0, r3, #1 +10001048: f85d 4b04 ldr.w r4, [sp], #4 +1000104c: f7ff ba2a b.w 100004a4 +10001050: 200007d8 .word 0x200007d8 +10001054: 400b8000 .word 0x400b8000 +10001058: 10003834 .word 0x10003834 + +1000105c : +1000105c: 4603 mov r3, r0 +1000105e: 6a41 ldr r1, [r0, #36] @ 0x24 +10001060: 460a mov r2, r1 +10001062: 6a98 ldr r0, [r3, #40] @ 0x28 +10001064: 6a59 ldr r1, [r3, #36] @ 0x24 +10001066: 428a cmp r2, r1 +10001068: d1fa bne.n 10001060 +1000106a: 4770 bx lr + +1000106c : +1000106c: 4b03 ldr r3, [pc, #12] @ (1000107c ) +1000106e: 6a59 ldr r1, [r3, #36] @ 0x24 +10001070: 460a mov r2, r1 +10001072: 6a98 ldr r0, [r3, #40] @ 0x28 +10001074: 6a59 ldr r1, [r3, #36] @ 0x24 +10001076: 4291 cmp r1, r2 +10001078: d1fa bne.n 10001070 +1000107a: 4770 bx lr +1000107c: 400b0000 .word 0x400b0000 + +10001080 : +10001080: b430 push {r4, r5} +10001082: 4a15 ldr r2, [pc, #84] @ (100010d8 ) +10001084: 6a53 ldr r3, [r2, #36] @ 0x24 +10001086: 469c mov ip, r3 +10001088: 6a94 ldr r4, [r2, #40] @ 0x28 +1000108a: 6a53 ldr r3, [r2, #36] @ 0x24 +1000108c: 4563 cmp r3, ip +1000108e: d1fa bne.n 10001086 +10001090: 1902 adds r2, r0, r4 +10001092: 4159 adcs r1, r3 +10001094: f04f 0500 mov.w r5, #0 +10001098: bf28 it cs +1000109a: 2501 movcs r5, #1 +1000109c: 4b0e ldr r3, [pc, #56] @ (100010d8 ) +1000109e: 6a5b ldr r3, [r3, #36] @ 0x24 +100010a0: b1b5 cbz r5, 100010d0 +100010a2: 1c5a adds r2, r3, #1 +100010a4: bf08 it eq +100010a6: 461a moveq r2, r3 +100010a8: d008 beq.n 100010bc +100010aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100010ae: 460a mov r2, r1 +100010b0: 4809 ldr r0, [pc, #36] @ (100010d8 ) +100010b2: 6a43 ldr r3, [r0, #36] @ 0x24 +100010b4: 428b cmp r3, r1 +100010b6: d3fc bcc.n 100010b2 +100010b8: 428b cmp r3, r1 +100010ba: d107 bne.n 100010cc +100010bc: 4906 ldr r1, [pc, #24] @ (100010d8 ) +100010be: e002 b.n 100010c6 +100010c0: 6a48 ldr r0, [r1, #36] @ 0x24 +100010c2: 4298 cmp r0, r3 +100010c4: d102 bne.n 100010cc +100010c6: 6a88 ldr r0, [r1, #40] @ 0x28 +100010c8: 4290 cmp r0, r2 +100010ca: d3f9 bcc.n 100010c0 +100010cc: bc30 pop {r4, r5} +100010ce: 4770 bx lr +100010d0: 4299 cmp r1, r3 +100010d2: d8ed bhi.n 100010b0 +100010d4: e7f0 b.n 100010b8 +100010d6: bf00 nop +100010d8: 400b0000 .word 0x400b0000 + +100010dc : +100010dc: 4a07 ldr r2, [pc, #28] @ (100010fc ) +100010de: 6a53 ldr r3, [r2, #36] @ 0x24 +100010e0: 4299 cmp r1, r3 +100010e2: d8fc bhi.n 100010de +100010e4: 4299 cmp r1, r3 +100010e6: d107 bne.n 100010f8 +100010e8: 4b04 ldr r3, [pc, #16] @ (100010fc ) +100010ea: e002 b.n 100010f2 +100010ec: 6a5a ldr r2, [r3, #36] @ 0x24 +100010ee: 4291 cmp r1, r2 +100010f0: d102 bne.n 100010f8 +100010f2: 6a9a ldr r2, [r3, #40] @ 0x28 +100010f4: 4290 cmp r0, r2 +100010f6: d8f9 bhi.n 100010ec +100010f8: 4770 bx lr +100010fa: bf00 nop +100010fc: 400b0000 .word 0x400b0000 + +10001100 : +10001100: b5f8 push {r3, r4, r5, r6, r7, lr} +10001102: 4605 mov r5, r0 +10001104: 2006 movs r0, #6 +10001106: 460e mov r6, r1 +10001108: f000 f8e4 bl 100012d4 +1000110c: 2800 cmp r0, #0 +1000110e: d042 beq.n 10001196 +10001110: 4a35 ldr r2, [pc, #212] @ (100011e8 ) +10001112: 4836 ldr r0, [pc, #216] @ (100011ec ) +10001114: 4295 cmp r5, r2 +10001116: bf14 ite ne +10001118: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +1000111c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10001120: 4b33 ldr r3, [pc, #204] @ (100011f0 ) +10001122: 4934 ldr r1, [pc, #208] @ (100011f4 ) +10001124: 6002 str r2, [r0, #0] +10001126: 601a str r2, [r3, #0] +10001128: 688c ldr r4, [r1, #8] +1000112a: ea32 0404 bics.w r4, r2, r4 +1000112e: d1fb bne.n 10001128 +10001130: 4b2d ldr r3, [pc, #180] @ (100011e8 ) +10001132: f44f 7180 mov.w r1, #256 @ 0x100 +10001136: 1aeb subs r3, r5, r3 +10001138: fab3 f383 clz r3, r3 +1000113c: 4a2e ldr r2, [pc, #184] @ (100011f8 ) +1000113e: 095b lsrs r3, r3, #5 +10001140: 2006 movs r0, #6 +10001142: f822 1013 strh.w r1, [r2, r3, lsl #1] +10001146: f000 f8c5 bl 100012d4 +1000114a: 00c3 lsls r3, r0, #3 +1000114c: fbb3 f3f6 udiv r3, r3, r6 +10001150: 3301 adds r3, #1 +10001152: 09da lsrs r2, r3, #7 +10001154: d120 bne.n 10001198 +10001156: 2640 movs r6, #64 @ 0x40 +10001158: 2101 movs r1, #1 +1000115a: 6269 str r1, [r5, #36] @ 0x24 +1000115c: 62aa str r2, [r5, #40] @ 0x28 +1000115e: 6b2f ldr r7, [r5, #48] @ 0x30 +10001160: 07fb lsls r3, r7, #31 +10001162: d422 bmi.n 100011aa +10001164: 462b mov r3, r5 +10001166: 2200 movs r2, #0 +10001168: f853 1f2c ldr.w r1, [r3, #44]! +1000116c: 2006 movs r0, #6 +1000116e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10001172: 6022 str r2, [r4, #0] +10001174: 632f str r7, [r5, #48] @ 0x30 +10001176: f000 f8ad bl 100012d4 +1000117a: f240 3101 movw r1, #769 @ 0x301 +1000117e: 2203 movs r2, #3 +10001180: 0080 lsls r0, r0, #2 +10001182: fbb0 f0f6 udiv r0, r0, r6 +10001186: 6aeb ldr r3, [r5, #44] @ 0x2c +10001188: f083 0370 eor.w r3, r3, #112 @ 0x70 +1000118c: f003 037e and.w r3, r3, #126 @ 0x7e +10001190: 6023 str r3, [r4, #0] +10001192: 6329 str r1, [r5, #48] @ 0x30 +10001194: 64aa str r2, [r5, #72] @ 0x48 +10001196: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001198: f64f 71fe movw r1, #65534 @ 0xfffe +1000119c: 428a cmp r2, r1 +1000119e: d91b bls.n 100011d8 +100011a0: 4622 mov r2, r4 +100011a2: f64f 71ff movw r1, #65535 @ 0xffff +100011a6: 4e15 ldr r6, [pc, #84] @ (100011fc ) +100011a8: e7d7 b.n 1000115a +100011aa: f240 3201 movw r2, #769 @ 0x301 +100011ae: f505 5340 add.w r3, r5, #12288 @ 0x3000 +100011b2: 631a str r2, [r3, #48] @ 0x30 +100011b4: 6a6b ldr r3, [r5, #36] @ 0x24 +100011b6: 6aac ldr r4, [r5, #40] @ 0x28 +100011b8: 2006 movs r0, #6 +100011ba: eb04 1483 add.w r4, r4, r3, lsl #6 +100011be: f000 f889 bl 100012d4 +100011c2: 4b0f ldr r3, [pc, #60] @ (10001200 ) +100011c4: 02a4 lsls r4, r4, #10 +100011c6: fba3 2300 umull r2, r3, r3, r0 +100011ca: 0adb lsrs r3, r3, #11 +100011cc: 2100 movs r1, #0 +100011ce: fbb4 f0f3 udiv r0, r4, r3 +100011d2: f7ff ff55 bl 10001080 +100011d6: e7c5 b.n 10001164 +100011d8: f3c3 0345 ubfx r3, r3, #1, #6 +100011dc: 4611 mov r1, r2 +100011de: eb03 1682 add.w r6, r3, r2, lsl #6 +100011e2: 461a mov r2, r3 +100011e4: e7b9 b.n 1000115a +100011e6: bf00 nop +100011e8: 40078000 .word 0x40078000 +100011ec: 40022000 .word 0x40022000 +100011f0: 40023000 .word 0x40023000 +100011f4: 40020000 .word 0x40020000 +100011f8: 20000854 .word 0x20000854 +100011fc: 003fffc0 .word 0x003fffc0 +10001200: 8f2b7b75 .word 0x8f2b7b75 + +10001204 : +10001204: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001208: ea4f 0c8c mov.w ip, ip, lsl #2 +1000120c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001210: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10001214: b5f0 push {r4, r5, r6, r7, lr} +10001216: 4616 mov r6, r2 +10001218: f8dc 2004 ldr.w r2, [ip, #4] +1000121c: 1f05 subs r5, r0, #4 +1000121e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10001222: bf38 it cc +10001224: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10001228: b2ed uxtb r5, r5 +1000122a: bf38 it cc +1000122c: f8cc 2004 strcc.w r2, [ip, #4] +10001230: 2d01 cmp r5, #1 +10001232: d92a bls.n 1000128a +10001234: f44f 6700 mov.w r7, #2048 @ 0x800 +10001238: 4c25 ldr r4, [pc, #148] @ (100012d0 ) +1000123a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000123e: 6017 str r7, [r2, #0] +10001240: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10001244: b9b2 cbnz r2, 10001274 +10001246: f8dc 2000 ldr.w r2, [ip] +1000124a: 2d01 cmp r5, #1 +1000124c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001250: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001254: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001258: 6032 str r2, [r6, #0] +1000125a: d92a bls.n 100012b2 +1000125c: f44f 6100 mov.w r1, #2048 @ 0x800 +10001260: f844 3020 str.w r3, [r4, r0, lsl #2] +10001264: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001268: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1000126c: 6011 str r1, [r2, #0] +1000126e: f8cc 3004 str.w r3, [ip, #4] +10001272: bdf0 pop {r4, r5, r6, r7, pc} +10001274: 6967 ldr r7, [r4, #20] +10001276: fbb7 fef2 udiv lr, r7, r2 +1000127a: f10e 0e01 add.w lr, lr, #1 +1000127e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10001282: f1be 0e03 subs.w lr, lr, #3 +10001286: d2fc bcs.n 10001282 +10001288: e7dd b.n 10001246 +1000128a: 2901 cmp r1, #1 +1000128c: d1d2 bne.n 10001234 +1000128e: 2403 movs r4, #3 +10001290: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10001294: 6014 str r4, [r2, #0] +10001296: f8dc 2008 ldr.w r2, [ip, #8] +1000129a: 07d2 lsls r2, r2, #31 +1000129c: d5fb bpl.n 10001296 +1000129e: f8dc 2000 ldr.w r2, [ip] +100012a2: 4c0b ldr r4, [pc, #44] @ (100012d0 ) +100012a4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100012a8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100012ac: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100012b0: 6032 str r2, [r6, #0] +100012b2: 2201 movs r2, #1 +100012b4: f8dc 5000 ldr.w r5, [ip] +100012b8: 404d eors r5, r1 +100012ba: f005 0503 and.w r5, r5, #3 +100012be: 6035 str r5, [r6, #0] +100012c0: fa02 f101 lsl.w r1, r2, r1 +100012c4: f8dc 2008 ldr.w r2, [ip, #8] +100012c8: 420a tst r2, r1 +100012ca: d0fb beq.n 100012c4 +100012cc: e7c6 b.n 1000125c +100012ce: bf00 nop +100012d0: 200007dc .word 0x200007dc + +100012d4 : +100012d4: 4b01 ldr r3, [pc, #4] @ (100012dc ) +100012d6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +100012da: 4770 bx lr +100012dc: 200007dc .word 0x200007dc + +100012e0 : +100012e0: b470 push {r4, r5, r6} +100012e2: 9d03 ldr r5, [sp, #12] +100012e4: 6804 ldr r4, [r0, #0] +100012e6: 032d lsls r5, r5, #12 +100012e8: ea45 4503 orr.w r5, r5, r3, lsl #16 +100012ec: 4b1b ldr r3, [pc, #108] @ (1000135c ) +100012ee: 2c00 cmp r4, #0 +100012f0: fbb3 f3f1 udiv r3, r3, r1 +100012f4: fbb2 f6f3 udiv r6, r2, r3 +100012f8: db1f blt.n 1000133a +100012fa: 4a19 ldr r2, [pc, #100] @ (10001360 ) +100012fc: 4b19 ldr r3, [pc, #100] @ (10001364 ) +100012fe: 4290 cmp r0, r2 +10001300: bf14 ite ne +10001302: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001306: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000130a: 4c17 ldr r4, [pc, #92] @ (10001368 ) +1000130c: 601a str r2, [r3, #0] +1000130e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001312: 601a str r2, [r3, #0] +10001314: 68a3 ldr r3, [r4, #8] +10001316: ea32 0303 bics.w r3, r2, r3 +1000131a: d1fb bne.n 10001314 +1000131c: 2221 movs r2, #33 @ 0x21 +1000131e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001322: 3304 adds r3, #4 +10001324: 6001 str r1, [r0, #0] +10001326: 6086 str r6, [r0, #8] +10001328: 601a str r2, [r3, #0] +1000132a: 6802 ldr r2, [r0, #0] +1000132c: 2a00 cmp r2, #0 +1000132e: dafc bge.n 1000132a +10001330: 2208 movs r2, #8 +10001332: 60c5 str r5, [r0, #12] +10001334: 601a str r2, [r3, #0] +10001336: bc70 pop {r4, r5, r6} +10001338: 4770 bx lr +1000133a: 6803 ldr r3, [r0, #0] +1000133c: f003 033f and.w r3, r3, #63 @ 0x3f +10001340: 428b cmp r3, r1 +10001342: d1da bne.n 100012fa +10001344: 6883 ldr r3, [r0, #8] +10001346: f3c3 030b ubfx r3, r3, #0, #12 +1000134a: 42b3 cmp r3, r6 +1000134c: d1d5 bne.n 100012fa +1000134e: 68c3 ldr r3, [r0, #12] +10001350: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001354: 42ab cmp r3, r5 +10001356: d1d0 bne.n 100012fa +10001358: e7ed b.n 10001336 +1000135a: bf00 nop +1000135c: 00b71b00 .word 0x00b71b00 +10001360: 40058000 .word 0x40058000 +10001364: 40022000 .word 0x40022000 +10001368: 40020000 .word 0x40020000 + +1000136c : +1000136c: 2301 movs r3, #1 +1000136e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001372: 0080 lsls r0, r0, #2 +10001374: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001378: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000137c: 6041 str r1, [r0, #4] +1000137e: 6003 str r3, [r0, #0] +10001380: 4770 bx lr +10001382: bf00 nop + +10001384 : +10001384: 2300 movs r3, #0 +10001386: 8adb ldrh r3, [r3, #22] +10001388: 2200 movs r2, #0 +1000138a: e842 f200 tt r2, r2 +1000138e: 0252 lsls r2, r2, #9 +10001390: d401 bmi.n 10001396 +10001392: 2110 movs r1, #16 +10001394: 4718 bx r3 +10001396: 2104 movs r1, #4 +10001398: 4718 bx r3 +1000139a: bf00 nop + +1000139c : +1000139c: 4a03 ldr r2, [pc, #12] @ (100013ac ) +1000139e: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100013a2: 2b00 cmp r3, #0 +100013a4: d0fb beq.n 1000139e +100013a6: f3bf 8f5f dmb sy +100013aa: 4770 bx lr +100013ac: 400e0000 .word 0x400e0000 + +100013b0 : +100013b0: 2100 movs r1, #0 +100013b2: 4b04 ldr r3, [pc, #16] @ (100013c4 ) +100013b4: 4a04 ldr r2, [pc, #16] @ (100013c8 ) +100013b6: f3bf 8f5f dmb sy +100013ba: f843 1b04 str.w r1, [r3], #4 +100013be: 4293 cmp r3, r2 +100013c0: d1f9 bne.n 100013b6 +100013c2: 4770 bx lr +100013c4: 400e080c .word 0x400e080c +100013c8: 400e082c .word 0x400e082c + +100013cc : +100013cc: b410 push {r4} +100013ce: f44f 708d mov.w r0, #282 @ 0x11a +100013d2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100013d6: 4a06 ldr r2, [pc, #24] @ (100013f0 ) +100013d8: 4b06 ldr r3, [pc, #24] @ (100013f4 ) +100013da: 4907 ldr r1, [pc, #28] @ (100013f8 ) +100013dc: 6014 str r4, [r2, #0] +100013de: 60d0 str r0, [r2, #12] +100013e0: 6019 str r1, [r3, #0] +100013e2: 6853 ldr r3, [r2, #4] +100013e4: 2b00 cmp r3, #0 +100013e6: dafc bge.n 100013e2 +100013e8: f85d 4b04 ldr.w r4, [sp], #4 +100013ec: 4770 bx lr +100013ee: bf00 nop +100013f0: 40048000 .word 0x40048000 +100013f4: 4004a000 .word 0x4004a000 +100013f8: 00fab000 .word 0x00fab000 + +100013fc : +100013fc: 4770 bx lr +100013fe: bf00 nop + +10001400 : +10001400: b508 push {r3, lr} +10001402: 4801 ldr r0, [pc, #4] @ (10001408 ) +10001404: f7ff f836 bl 10000474 +10001408: 10003858 .word 0x10003858 + +1000140c : +1000140c: b538 push {r3, r4, r5, lr} +1000140e: 4c05 ldr r4, [pc, #20] @ (10001424 ) +10001410: 4d05 ldr r5, [pc, #20] @ (10001428 ) +10001412: 42ac cmp r4, r5 +10001414: d204 bcs.n 10001420 +10001416: f854 3b04 ldr.w r3, [r4], #4 +1000141a: 4798 blx r3 +1000141c: 42ac cmp r4, r5 +1000141e: d3fa bcc.n 10001416 +10001420: bd38 pop {r3, r4, r5, pc} +10001422: bf00 nop +10001424: 100037b8 .word 0x100037b8 +10001428: 100037f8 .word 0x100037f8 + +1000142c : +1000142c: b410 push {r4} +1000142e: 4807 ldr r0, [pc, #28] @ (1000144c ) +10001430: 4c07 ldr r4, [pc, #28] @ (10001450 ) +10001432: 4b08 ldr r3, [pc, #32] @ (10001454 ) +10001434: 4a08 ldr r2, [pc, #32] @ (10001458 ) +10001436: 4909 ldr r1, [pc, #36] @ (1000145c ) +10001438: 6004 str r4, [r0, #0] +1000143a: 601a str r2, [r3, #0] +1000143c: 688b ldr r3, [r1, #8] +1000143e: ea32 0303 bics.w r3, r2, r3 +10001442: d1fb bne.n 1000143c +10001444: f85d 4b04 ldr.w r4, [sp], #4 +10001448: 4770 bx lr +1000144a: bf00 nop +1000144c: 40022000 .word 0x40022000 +10001450: efef3b7f .word 0xefef3b7f +10001454: 40023000 .word 0x40023000 +10001458: 03f3fff6 .word 0x03f3fff6 +1000145c: 40020000 .word 0x40020000 + +10001460 : +10001460: 4b04 ldr r3, [pc, #16] @ (10001474 ) +10001462: 6cdb ldr r3, [r3, #76] @ 0x4c +10001464: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001468: d103 bne.n 10001472 +1000146a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000146e: 4b02 ldr r3, [pc, #8] @ (10001478 ) +10001470: 64da str r2, [r3, #76] @ 0x4c +10001472: 4770 bx lr +10001474: 50110000 .word 0x50110000 +10001478: 50112000 .word 0x50112000 + +1000147c : +1000147c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001480: 4b04 ldr r3, [pc, #16] @ (10001494 ) +10001482: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001486: 430b orrs r3, r1 +10001488: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000148c: ee10 0430 dcp_rcmp r0 +10001490: 4770 bx lr +10001492: bf00 nop +10001494: 00300303 .word 0x00300303 + +10001498 : +10001498: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +1000149c: 4b04 ldr r3, [pc, #16] @ (100014b0 ) +1000149e: 4a05 ldr r2, [pc, #20] @ (100014b4 ) +100014a0: 6019 str r1, [r3, #0] +100014a2: 6893 ldr r3, [r2, #8] +100014a4: 43db mvns r3, r3 +100014a6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100014aa: d1fa bne.n 100014a2 +100014ac: 4770 bx lr +100014ae: bf00 nop +100014b0: 40023000 .word 0x40023000 +100014b4: 40020000 .word 0x40020000 + +100014b8 : +100014b8: b510 push {r4, lr} +100014ba: f245 2053 movw r0, #21075 @ 0x5253 +100014be: f7ff ff61 bl 10001384 +100014c2: e8bd 4010 ldmia.w sp!, {r4, lr} +100014c6: 4603 mov r3, r0 +100014c8: 2004 movs r0, #4 +100014ca: 4718 bx r3 + +100014cc : +100014cc: b510 push {r4, lr} +100014ce: f245 2053 movw r0, #21075 @ 0x5253 +100014d2: f7ff ff57 bl 10001384 +100014d6: e8bd 4010 ldmia.w sp!, {r4, lr} +100014da: 4603 mov r3, r0 +100014dc: 2001 movs r0, #1 +100014de: 4718 bx r3 + +100014e0 : +100014e0: f7ff b820 b.w 10000524 + +100014e4 : +100014e4: 4914 ldr r1, [pc, #80] @ (10001538 ) +100014e6: 4b15 ldr r3, [pc, #84] @ (1000153c ) +100014e8: b570 push {r4, r5, r6, lr} +100014ea: 1a5c subs r4, r3, r1 +100014ec: 10a6 asrs r6, r4, #2 +100014ee: 2e44 cmp r6, #68 @ 0x44 +100014f0: 4632 mov r2, r6 +100014f2: bf28 it cs +100014f4: 2244 movcs r2, #68 @ 0x44 +100014f6: 4d12 ldr r5, [pc, #72] @ (10001540 ) +100014f8: 0092 lsls r2, r2, #2 +100014fa: 4628 mov r0, r5 +100014fc: f002 f8aa bl 10003654 +10001500: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001504: d813 bhi.n 1000152e +10001506: 4a0f ldr r2, [pc, #60] @ (10001544 ) +10001508: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000150c: d012 beq.n 10001534 +1000150e: 192b adds r3, r5, r4 +10001510: 0841 lsrs r1, r0, #1 +10001512: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001516: e9c3 2200 strd r2, r2, [r3] +1000151a: 3308 adds r3, #8 +1000151c: 428b cmp r3, r1 +1000151e: d1fa bne.n 10001516 +10001520: 07c3 lsls r3, r0, #31 +10001522: d504 bpl.n 1000152e +10001524: f020 0001 bic.w r0, r0, #1 +10001528: 4430 add r0, r6 +1000152a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000152e: 4b06 ldr r3, [pc, #24] @ (10001548 ) +10001530: 609d str r5, [r3, #8] +10001532: bd70 pop {r4, r5, r6, pc} +10001534: 2043 movs r0, #67 @ 0x43 +10001536: e7f8 b.n 1000152a +10001538: 10000000 .word 0x10000000 +1000153c: 10000110 .word 0x10000110 +10001540: 20000000 .word 0x20000000 +10001544: 10000111 .word 0x10000111 +10001548: e000ed00 .word 0xe000ed00 + +1000154c : +1000154c: 2300 movs r3, #0 +1000154e: b570 push {r4, r5, r6, lr} +10001550: 4c2b ldr r4, [pc, #172] @ (10001600 ) +10001552: b082 sub sp, #8 +10001554: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001558: f7ff ff38 bl 100013cc +1000155c: 2201 movs r2, #1 +1000155e: 4b29 ldr r3, [pc, #164] @ (10001604 ) +10001560: 63da str r2, [r3, #60] @ 0x3c +10001562: 6c63 ldr r3, [r4, #68] @ 0x44 +10001564: 2b01 cmp r3, #1 +10001566: d1fc bne.n 10001562 +10001568: 2103 movs r1, #3 +1000156a: 4a26 ldr r2, [pc, #152] @ (10001604 ) +1000156c: 4b24 ldr r3, [pc, #144] @ (10001600 ) +1000156e: 6311 str r1, [r2, #48] @ 0x30 +10001570: 6b9c ldr r4, [r3, #56] @ 0x38 +10001572: 2c01 cmp r4, #1 +10001574: d1fc bne.n 10001570 +10001576: 2602 movs r6, #2 +10001578: 2505 movs r5, #5 +1000157a: 4621 mov r1, r4 +1000157c: 2305 movs r3, #5 +1000157e: 4a22 ldr r2, [pc, #136] @ (10001608 ) +10001580: 4822 ldr r0, [pc, #136] @ (1000160c ) +10001582: 9600 str r6, [sp, #0] +10001584: f7ff feac bl 100012e0 +10001588: 4621 mov r1, r4 +1000158a: 462b mov r3, r5 +1000158c: 4a20 ldr r2, [pc, #128] @ (10001610 ) +1000158e: 4821 ldr r0, [pc, #132] @ (10001614 ) +10001590: 9500 str r5, [sp, #0] +10001592: f7ff fea5 bl 100012e0 +10001596: 2200 movs r2, #0 +10001598: 2004 movs r0, #4 +1000159a: 4631 mov r1, r6 +1000159c: 4b1e ldr r3, [pc, #120] @ (10001618 ) +1000159e: f7ff fe31 bl 10001204 +100015a2: 4621 mov r1, r4 +100015a4: 4628 mov r0, r5 +100015a6: 2200 movs r2, #0 +100015a8: 4b1c ldr r3, [pc, #112] @ (1000161c ) +100015aa: f7ff fe2b bl 10001204 +100015ae: 2200 movs r2, #0 +100015b0: 2008 movs r0, #8 +100015b2: 4611 mov r1, r2 +100015b4: 4b1a ldr r3, [pc, #104] @ (10001620 ) +100015b6: f7ff fe25 bl 10001204 +100015ba: 2200 movs r2, #0 +100015bc: 2009 movs r0, #9 +100015be: 4611 mov r1, r2 +100015c0: 4b17 ldr r3, [pc, #92] @ (10001620 ) +100015c2: f7ff fe1f bl 10001204 +100015c6: 2200 movs r2, #0 +100015c8: 2006 movs r0, #6 +100015ca: 4611 mov r1, r2 +100015cc: 4b13 ldr r3, [pc, #76] @ (1000161c ) +100015ce: f7ff fe19 bl 10001204 +100015d2: 2200 movs r2, #0 +100015d4: 4b11 ldr r3, [pc, #68] @ (1000161c ) +100015d6: 2007 movs r0, #7 +100015d8: 4611 mov r1, r2 +100015da: f7ff fe13 bl 10001204 +100015de: 2004 movs r0, #4 +100015e0: f7ff fe78 bl 100012d4 +100015e4: 2400 movs r4, #0 +100015e6: 4b0f ldr r3, [pc, #60] @ (10001624 ) +100015e8: fba3 3500 umull r3, r5, r3, r0 +100015ec: 0cad lsrs r5, r5, #18 +100015ee: b2e0 uxtb r0, r4 +100015f0: 4629 mov r1, r5 +100015f2: 3401 adds r4, #1 +100015f4: f7ff feba bl 1000136c +100015f8: 2c06 cmp r4, #6 +100015fa: d1f8 bne.n 100015ee +100015fc: b002 add sp, #8 +100015fe: bd70 pop {r4, r5, r6, pc} +10001600: 40010000 .word 0x40010000 +10001604: 40013000 .word 0x40013000 +10001608: 59682f00 .word 0x59682f00 +1000160c: 40050000 .word 0x40050000 +10001610: 47868c00 .word 0x47868c00 +10001614: 40058000 .word 0x40058000 +10001618: 00b71b00 .word 0x00b71b00 +1000161c: 08f0d180 .word 0x08f0d180 +10001620: 02dc6c00 .word 0x02dc6c00 +10001624: 431bde83 .word 0x431bde83 + +10001628 : +10001628: b086 sub sp, #24 +1000162a: b403 push {r0, r1} +1000162c: fc51 0408 dcp_pxmd r0, r1 +10001630: e9cd 0102 strd r0, r1, [sp, #8] +10001634: fc51 0409 dcp_pymd r0, r1 +10001638: e9cd 0104 strd r0, r1, [sp, #16] +1000163c: ec51 040a dcp_refd r0, r1 +10001640: e9cd 0106 strd r0, r1, [sp, #24] +10001644: bc03 pop {r0, r1} +10001646: 47f0 blx lr + +10001648 : +10001648: e8bd 5000 ldmia.w sp!, {ip, lr} +1000164c: ec4e c400 dcp_wxmd ip, lr +10001650: e8bd 5000 ldmia.w sp!, {ip, lr} +10001654: ec4e c401 dcp_wymd ip, lr +10001658: e8bd 5000 ldmia.w sp!, {ip, lr} +1000165c: ec4e c402 dcp_wefd ip, lr +10001660: bd00 pop {pc} +10001662: 0000 movs r0, r0 +10001664: b500 push {lr} +10001666: f7ff ffdf bl 10001628 +1000166a: e002 b.n 10001672 <__wrap___aeabi_dadd+0x6> + +1000166c <__wrap___aeabi_dadd>: +1000166c: fe10 f430 dcp_pcmp APSR_nzcv +10001670: d4f8 bmi.n 10001664 +10001672: ec41 0410 dcp_wxup r0, r1 +10001676: ec43 2411 dcp_wyup r2, r3 +1000167a: ee00 0401 dcp_add0 +1000167e: ee10 0401 dcp_add1 +10001682: ee80 0420 dcp_nrdd +10001686: ec51 0410 dcp_rdda r0, r1 +1000168a: 4770 bx lr +1000168c: b500 push {lr} +1000168e: f7ff ffcb bl 10001628 +10001692: e002 b.n 1000169a <__wrap___aeabi_dsub+0x6> + +10001694 <__wrap___aeabi_dsub>: +10001694: fe10 f430 dcp_pcmp APSR_nzcv +10001698: d4f8 bmi.n 1000168c <__wrap___aeabi_dadd+0x20> +1000169a: ec41 0410 dcp_wxup r0, r1 +1000169e: ec43 2411 dcp_wyup r2, r3 +100016a2: ee00 0401 dcp_add0 +100016a6: ee10 0421 dcp_sub1 +100016aa: ee80 0420 dcp_nrdd +100016ae: ec51 0430 dcp_rdds r0, r1 +100016b2: 4770 bx lr +100016b4: b500 push {lr} +100016b6: f7ff ffb7 bl 10001628 +100016ba: e002 b.n 100016c2 <__wrap___aeabi_dmul+0x6> + +100016bc <__wrap___aeabi_dmul>: +100016bc: fe10 f430 dcp_pcmp APSR_nzcv +100016c0: d4f8 bmi.n 100016b4 <__wrap___aeabi_dsub+0x20> +100016c2: b510 push {r4, lr} +100016c4: ec41 0410 dcp_wxup r0, r1 +100016c8: ec43 2411 dcp_wyup r2, r3 +100016cc: ec51 0404 dcp_rxms r0, r1, #0x0 +100016d0: ec53 2405 dcp_ryms r2, r3, #0x0 +100016d4: fba0 4c02 umull r4, ip, r0, r2 +100016d8: f05f 0e00 movs.w lr, #0 +100016dc: fbe0 ce03 umlal ip, lr, r0, r3 +100016e0: fbe1 ce02 umlal ip, lr, r1, r2 +100016e4: ec4c 4420 dcp_wxms r4, ip +100016e8: 2400 movs r4, #0 +100016ea: fbe1 e403 umlal lr, r4, r1, r3 +100016ee: ec44 e430 dcp_wxmo lr, r4 +100016f2: ee80 0420 dcp_nrdd +100016f6: ec51 0450 dcp_rddm r0, r1 +100016fa: e8bd 4010 ldmia.w sp!, {r4, lr} +100016fe: 4770 bx lr +10001700: b500 push {lr} +10001702: f7ff ff91 bl 10001628 +10001706: e002 b.n 1000170e <__wrap___aeabi_ddiv+0x6> + +10001708 <__wrap___aeabi_ddiv>: +10001708: fe10 f430 dcp_pcmp APSR_nzcv +1000170c: d4f8 bmi.n 10001700 <__wrap___aeabi_dmul+0x44> +1000170e: ec41 0410 dcp_wxup r0, r1 +10001712: ec43 2411 dcp_wyup r2, r3 +10001716: ec51 0421 dcp_rymr r0, r1 +1000171a: fba0 1201 umull r1, r2, r0, r1 +1000171e: ea6f 0282 mvn.w r2, r2, lsl #2 +10001722: fb52 0010 smmlar r0, r2, r0, r0 +10001726: fb52 f212 smmulr r2, r2, r2 +1000172a: fb52 0010 smmlar r0, r2, r0, r0 +1000172e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001732: ec53 2404 dcp_rxms r2, r3, #0x0 +10001736: fb5c f113 smmulr r1, ip, r3 +1000173a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000173e: fba1 2002 umull r2, r0, r1, r2 +10001742: fb01 0003 mla r0, r1, r3, r0 +10001746: ec53 2444 dcp_rxms r2, r3, #0x4 +1000174a: eba2 0000 sub.w r0, r2, r0 +1000174e: fb50 f21c smmulr r2, r0, ip +10001752: ea4f 1311 mov.w r3, r1, lsr #4 +10001756: eb12 7001 adds.w r0, r2, r1, lsl #28 +1000175a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1000175e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001762: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001766: f020 0007 bic.w r0, r0, #7 +1000176a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000176e: fba0 3c02 umull r3, ip, r0, r2 +10001772: ec53 2475 dcp_ryms r2, r3, #0x7 +10001776: fb00 cc03 mla ip, r0, r3, ip +1000177a: fb01 cc02 mla ip, r1, r2, ip +1000177e: ec53 2404 dcp_rxms r2, r3, #0x0 +10001782: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001786: ea40 705c orr.w r0, r0, ip, lsr #29 +1000178a: f1a0 0001 sub.w r0, r0, #1 +1000178e: ec41 0440 dcp_wxdd r0, r1 +10001792: ee80 0420 dcp_nrdd +10001796: ec51 0470 dcp_rddd r0, r1 +1000179a: 4770 bx lr +1000179c: b500 push {lr} +1000179e: f7ff ff43 bl 10001628 +100017a2: e002 b.n 100017aa <__wrap___aeabi_i2d+0x6> + +100017a4 <__wrap___aeabi_i2d>: +100017a4: fe10 f430 dcp_pcmp APSR_nzcv +100017a8: d4f8 bmi.n 1000179c <__wrap___aeabi_ddiv+0x94> +100017aa: ec40 0470 dcp_wxic r0, r0 +100017ae: ee00 0401 dcp_add0 +100017b2: ee10 0421 dcp_sub1 +100017b6: ee80 0420 dcp_nrdd +100017ba: ec51 0430 dcp_rdds r0, r1 +100017be: 4770 bx lr +100017c0: b500 push {lr} +100017c2: f7ff ff31 bl 10001628 +100017c6: e002 b.n 100017ce <__wrap___aeabi_ui2d+0x6> + +100017c8 <__wrap___aeabi_ui2d>: +100017c8: fe10 f430 dcp_pcmp APSR_nzcv +100017cc: d4f8 bmi.n 100017c0 <__wrap___aeabi_i2d+0x1c> +100017ce: ec40 0460 dcp_wxuc r0, r0 +100017d2: ee00 0401 dcp_add0 +100017d6: ee10 0421 dcp_sub1 +100017da: ee80 0420 dcp_nrdd +100017de: ec51 0430 dcp_rdds r0, r1 +100017e2: 4770 bx lr +100017e4: b500 push {lr} +100017e6: f7ff ff1f bl 10001628 +100017ea: e002 b.n 100017f2 + +100017ec <__wrap___aeabi_d2iz>: +100017ec: fe10 f430 dcp_pcmp APSR_nzcv +100017f0: d4f8 bmi.n 100017e4 <__wrap___aeabi_ui2d+0x1c> + +100017f2 : +100017f2: ec41 0480 dcp_wxdc r0, r1 +100017f6: ee00 0401 dcp_add0 +100017fa: ee10 0401 dcp_add1 +100017fe: ee80 0440 dcp_ntdc +10001802: ee10 0413 dcp_rdic r0 +10001806: 4770 bx lr +10001808: b500 push {lr} +1000180a: f7ff ff0d bl 10001628 +1000180e: e002 b.n 10001816 + +10001810 <__wrap___aeabi_d2uiz>: +10001810: fe10 f430 dcp_pcmp APSR_nzcv +10001814: d4f8 bmi.n 10001808 + +10001816 : +10001816: ec41 0480 dcp_wxdc r0, r1 +1000181a: ee00 0401 dcp_add0 +1000181e: ee10 0401 dcp_add1 +10001822: ee80 0440 dcp_ntdc +10001826: ee10 0433 dcp_rduc r0 +1000182a: 4770 bx lr +1000182c: b500 push {lr} +1000182e: f7ff fefb bl 10001628 +10001832: e002 b.n 1000183a <__wrap___aeabi_dcmpun+0x6> + +10001834 <__wrap___aeabi_dcmpun>: +10001834: fe10 f430 dcp_pcmp APSR_nzcv +10001838: d4f8 bmi.n 1000182c +1000183a: ec41 0410 dcp_wxup r0, r1 +1000183e: ec43 2411 dcp_wyup r2, r3 +10001842: ee00 0401 dcp_add0 +10001846: ee10 0430 dcp_rcmp r0 +1000184a: f3c0 7000 ubfx r0, r0, #28, #1 +1000184e: 4770 bx lr +10001850: b500 push {lr} +10001852: f7ff fee9 bl 10001628 +10001856: e002 b.n 1000185e <__wrap___aeabi_dcmplt+0x6> + +10001858 <__wrap___aeabi_dcmplt>: +10001858: fe10 f430 dcp_pcmp APSR_nzcv +1000185c: d4f8 bmi.n 10001850 <__wrap___aeabi_dcmpun+0x1c> +1000185e: ec43 2410 dcp_wxup r2, r3 +10001862: ec41 0411 dcp_wyup r0, r1 +10001866: ee00 0401 dcp_add0 +1000186a: ee10 f430 dcp_rcmp APSR_nzcv +1000186e: bf8c ite hi +10001870: 2001 movhi r0, #1 +10001872: 2000 movls r0, #0 +10001874: 4770 bx lr +10001876: bf00 nop +10001878: b500 push {lr} +1000187a: f7ff fed5 bl 10001628 +1000187e: e002 b.n 10001886 <__wrap___aeabi_dcmple+0x6> + +10001880 <__wrap___aeabi_dcmple>: +10001880: fe10 f430 dcp_pcmp APSR_nzcv +10001884: d4f8 bmi.n 10001878 <__wrap___aeabi_dcmplt+0x20> +10001886: ec43 2410 dcp_wxup r2, r3 +1000188a: ec41 0411 dcp_wyup r0, r1 +1000188e: ee00 0401 dcp_add0 +10001892: ee10 f430 dcp_rcmp APSR_nzcv +10001896: bf2c ite cs +10001898: 2001 movcs r0, #1 +1000189a: 2000 movcc r0, #0 +1000189c: 4770 bx lr +1000189e: bf00 nop +100018a0: b500 push {lr} +100018a2: f7ff fec1 bl 10001628 +100018a6: e002 b.n 100018ae <__wrap___aeabi_dcmpge+0x6> + +100018a8 <__wrap___aeabi_dcmpge>: +100018a8: fe10 f430 dcp_pcmp APSR_nzcv +100018ac: d4f8 bmi.n 100018a0 <__wrap___aeabi_dcmple+0x20> +100018ae: ec41 0410 dcp_wxup r0, r1 +100018b2: ec43 2411 dcp_wyup r2, r3 +100018b6: ee00 0401 dcp_add0 +100018ba: ee10 f430 dcp_rcmp APSR_nzcv +100018be: bf2c ite cs +100018c0: 2001 movcs r0, #1 +100018c2: 2000 movcc r0, #0 +100018c4: 4770 bx lr +100018c6: bf00 nop +100018c8: b500 push {lr} +100018ca: f7ff fead bl 10001628 +100018ce: e002 b.n 100018d6 <__wrap___aeabi_dcmpgt+0x6> + +100018d0 <__wrap___aeabi_dcmpgt>: +100018d0: fe10 f430 dcp_pcmp APSR_nzcv +100018d4: d4f8 bmi.n 100018c8 <__wrap___aeabi_dcmpge+0x20> +100018d6: ec41 0410 dcp_wxup r0, r1 +100018da: ec43 2411 dcp_wyup r2, r3 +100018de: ee00 0401 dcp_add0 +100018e2: ee10 f430 dcp_rcmp APSR_nzcv +100018e6: bf8c ite hi +100018e8: 2001 movhi r0, #1 +100018ea: 2000 movls r0, #0 +100018ec: 4770 bx lr +100018ee: bf00 nop + +100018f0 <_out_null>: +100018f0: 4770 bx lr +100018f2: bf00 nop + +100018f4 <_out_rev>: +100018f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100018f8: b083 sub sp, #12 +100018fa: 4699 mov r9, r3 +100018fc: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001900: 9b0f ldr r3, [sp, #60] @ 0x3c +10001902: 4688 mov r8, r1 +10001904: 4611 mov r1, r2 +10001906: 079a lsls r2, r3, #30 +10001908: 4607 mov r7, r0 +1000190a: d116 bne.n 1000193a <_out_rev+0x46> +1000190c: 45da cmp sl, fp +1000190e: d23a bcs.n 10001986 <_out_rev+0x92> +10001910: 460c mov r4, r1 +10001912: 460d mov r5, r1 +10001914: ebab 060a sub.w r6, fp, sl +10001918: 440e add r6, r1 +1000191a: 4622 mov r2, r4 +1000191c: 464b mov r3, r9 +1000191e: 4641 mov r1, r8 +10001920: 2020 movs r0, #32 +10001922: 3401 adds r4, #1 +10001924: 47b8 blx r7 +10001926: 42b4 cmp r4, r6 +10001928: d1f7 bne.n 1000191a <_out_rev+0x26> +1000192a: 4629 mov r1, r5 +1000192c: f1ba 0f00 cmp.w sl, #0 +10001930: d108 bne.n 10001944 <_out_rev+0x50> +10001932: 4620 mov r0, r4 +10001934: b003 add sp, #12 +10001936: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000193a: 460c mov r4, r1 +1000193c: f1ba 0f00 cmp.w sl, #0 +10001940: d010 beq.n 10001964 <_out_rev+0x70> +10001942: 460e mov r6, r1 +10001944: 4655 mov r5, sl +10001946: 9b0c ldr r3, [sp, #48] @ 0x30 +10001948: 442e add r6, r5 +1000194a: 449a add sl, r3 +1000194c: 9101 str r1, [sp, #4] +1000194e: 1b72 subs r2, r6, r5 +10001950: 464b mov r3, r9 +10001952: 3d01 subs r5, #1 +10001954: 4641 mov r1, r8 +10001956: f81a 0d01 ldrb.w r0, [sl, #-1]! +1000195a: 4634 mov r4, r6 +1000195c: 47b8 blx r7 +1000195e: 2d00 cmp r5, #0 +10001960: d1f5 bne.n 1000194e <_out_rev+0x5a> +10001962: 9901 ldr r1, [sp, #4] +10001964: 9b0f ldr r3, [sp, #60] @ 0x3c +10001966: 079b lsls r3, r3, #30 +10001968: d5e3 bpl.n 10001932 <_out_rev+0x3e> +1000196a: 1a65 subs r5, r4, r1 +1000196c: 45ab cmp fp, r5 +1000196e: d9e0 bls.n 10001932 <_out_rev+0x3e> +10001970: 4622 mov r2, r4 +10001972: 464b mov r3, r9 +10001974: 4641 mov r1, r8 +10001976: 2020 movs r0, #32 +10001978: 3501 adds r5, #1 +1000197a: 47b8 blx r7 +1000197c: 455d cmp r5, fp +1000197e: f104 0401 add.w r4, r4, #1 +10001982: d3f5 bcc.n 10001970 <_out_rev+0x7c> +10001984: e7d5 b.n 10001932 <_out_rev+0x3e> +10001986: 460c mov r4, r1 +10001988: f1ba 0f00 cmp.w sl, #0 +1000198c: d1d9 bne.n 10001942 <_out_rev+0x4e> +1000198e: e7d0 b.n 10001932 <_out_rev+0x3e> + +10001990 <_ntoa_format>: +10001990: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001994: 9f0f ldr r7, [sp, #60] @ 0x3c +10001996: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +1000199a: f017 0f02 tst.w r7, #2 +1000199e: 9c0a ldr r4, [sp, #40] @ 0x28 +100019a0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +100019a4: 9d0e ldr r5, [sp, #56] @ 0x38 +100019a6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +100019aa: d144 bne.n 10001a36 <_ntoa_format+0xa6> +100019ac: bbf5 cbnz r5, 10001a2c <_ntoa_format+0x9c> +100019ae: 42b4 cmp r4, r6 +100019b0: d241 bcs.n 10001a36 <_ntoa_format+0xa6> +100019b2: f007 0b01 and.w fp, r7, #1 +100019b6: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100019ba: f04f 0e30 mov.w lr, #48 @ 0x30 +100019be: 44c4 add ip, r8 +100019c0: e004 b.n 100019cc <_ntoa_format+0x3c> +100019c2: 3401 adds r4, #1 +100019c4: 42a6 cmp r6, r4 +100019c6: f80c ef01 strb.w lr, [ip, #1]! +100019ca: d901 bls.n 100019d0 <_ntoa_format+0x40> +100019cc: 2c20 cmp r4, #32 +100019ce: d1f8 bne.n 100019c2 <_ntoa_format+0x32> +100019d0: f1bb 0f00 cmp.w fp, #0 +100019d4: f000 8088 beq.w 10001ae8 <_ntoa_format+0x158> +100019d8: 42a5 cmp r5, r4 +100019da: d92c bls.n 10001a36 <_ntoa_format+0xa6> +100019dc: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100019e0: f04f 0e30 mov.w lr, #48 @ 0x30 +100019e4: 44c4 add ip, r8 +100019e6: e004 b.n 100019f2 <_ntoa_format+0x62> +100019e8: 3401 adds r4, #1 +100019ea: 42ac cmp r4, r5 +100019ec: f80c ef01 strb.w lr, [ip, #1]! +100019f0: d021 beq.n 10001a36 <_ntoa_format+0xa6> +100019f2: 2c20 cmp r4, #32 +100019f4: d1f8 bne.n 100019e8 <_ntoa_format+0x58> +100019f6: f017 0f10 tst.w r7, #16 +100019fa: d00e beq.n 10001a1a <_ntoa_format+0x8a> +100019fc: f417 6f80 tst.w r7, #1024 @ 0x400 +10001a00: d154 bne.n 10001aac <_ntoa_format+0x11c> +10001a02: 42a6 cmp r6, r4 +10001a04: d063 beq.n 10001ace <_ntoa_format+0x13e> +10001a06: 42a5 cmp r5, r4 +10001a08: d061 beq.n 10001ace <_ntoa_format+0x13e> +10001a0a: f1b9 0f10 cmp.w r9, #16 +10001a0e: d050 beq.n 10001ab2 <_ntoa_format+0x122> +10001a10: f1b9 0f02 cmp.w r9, #2 +10001a14: d056 beq.n 10001ac4 <_ntoa_format+0x134> +10001a16: 2c20 cmp r4, #32 +10001a18: d129 bne.n 10001a6e <_ntoa_format+0xde> +10001a1a: 2420 movs r4, #32 +10001a1c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001a20: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001a24: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a28: f7ff bf64 b.w 100018f4 <_out_rev> +10001a2c: f017 0b01 ands.w fp, r7, #1 +10001a30: d134 bne.n 10001a9c <_ntoa_format+0x10c> +10001a32: 42b4 cmp r4, r6 +10001a34: d3bf bcc.n 100019b6 <_ntoa_format+0x26> +10001a36: f017 0f10 tst.w r7, #16 +10001a3a: d01e beq.n 10001a7a <_ntoa_format+0xea> +10001a3c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001a40: d1e3 bne.n 10001a0a <_ntoa_format+0x7a> +10001a42: 2c00 cmp r4, #0 +10001a44: d1dd bne.n 10001a02 <_ntoa_format+0x72> +10001a46: f1b9 0f10 cmp.w r9, #16 +10001a4a: d063 beq.n 10001b14 <_ntoa_format+0x184> +10001a4c: f1b9 0f02 cmp.w r9, #2 +10001a50: d077 beq.n 10001b42 <_ntoa_format+0x1b2> +10001a52: 2430 movs r4, #48 @ 0x30 +10001a54: f888 4000 strb.w r4, [r8] +10001a58: 2401 movs r4, #1 +10001a5a: f1ba 0f00 cmp.w sl, #0 +10001a5e: d111 bne.n 10001a84 <_ntoa_format+0xf4> +10001a60: 077e lsls r6, r7, #29 +10001a62: d548 bpl.n 10001af6 <_ntoa_format+0x166> +10001a64: 262b movs r6, #43 @ 0x2b +10001a66: f808 6004 strb.w r6, [r8, r4] +10001a6a: 3401 adds r4, #1 +10001a6c: e7d6 b.n 10001a1c <_ntoa_format+0x8c> +10001a6e: 4626 mov r6, r4 +10001a70: 3401 adds r4, #1 +10001a72: f04f 0c30 mov.w ip, #48 @ 0x30 +10001a76: f808 c006 strb.w ip, [r8, r6] +10001a7a: 2c20 cmp r4, #32 +10001a7c: d0cd beq.n 10001a1a <_ntoa_format+0x8a> +10001a7e: f1ba 0f00 cmp.w sl, #0 +10001a82: d0ed beq.n 10001a60 <_ntoa_format+0xd0> +10001a84: 262d movs r6, #45 @ 0x2d +10001a86: f808 6004 strb.w r6, [r8, r4] +10001a8a: 3401 adds r4, #1 +10001a8c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001a90: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001a94: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a98: f7ff bf2c b.w 100018f4 <_out_rev> +10001a9c: f1ba 0f00 cmp.w sl, #0 +10001aa0: d030 beq.n 10001b04 <_ntoa_format+0x174> +10001aa2: 42b4 cmp r4, r6 +10001aa4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001aa8: d385 bcc.n 100019b6 <_ntoa_format+0x26> +10001aaa: e795 b.n 100019d8 <_ntoa_format+0x48> +10001aac: f1b9 0f10 cmp.w r9, #16 +10001ab0: d1b3 bne.n 10001a1a <_ntoa_format+0x8a> +10001ab2: 06be lsls r6, r7, #26 +10001ab4: d53b bpl.n 10001b2e <_ntoa_format+0x19e> +10001ab6: 2c20 cmp r4, #32 +10001ab8: d0af beq.n 10001a1a <_ntoa_format+0x8a> +10001aba: 2658 movs r6, #88 @ 0x58 +10001abc: f808 6004 strb.w r6, [r8, r4] +10001ac0: 3401 adds r4, #1 +10001ac2: e7a8 b.n 10001a16 <_ntoa_format+0x86> +10001ac4: 2c20 cmp r4, #32 +10001ac6: d0a8 beq.n 10001a1a <_ntoa_format+0x8a> +10001ac8: 4626 mov r6, r4 +10001aca: 3401 adds r4, #1 +10001acc: e007 b.n 10001ade <_ntoa_format+0x14e> +10001ace: 1e66 subs r6, r4, #1 +10001ad0: d0b9 beq.n 10001a46 <_ntoa_format+0xb6> +10001ad2: f1b9 0f10 cmp.w r9, #16 +10001ad6: d036 beq.n 10001b46 <_ntoa_format+0x1b6> +10001ad8: f1b9 0f02 cmp.w r9, #2 +10001adc: d1c9 bne.n 10001a72 <_ntoa_format+0xe2> +10001ade: f04f 0c62 mov.w ip, #98 @ 0x62 +10001ae2: f808 c006 strb.w ip, [r8, r6] +10001ae6: e796 b.n 10001a16 <_ntoa_format+0x86> +10001ae8: f017 0f10 tst.w r7, #16 +10001aec: d0c5 beq.n 10001a7a <_ntoa_format+0xea> +10001aee: f417 6f80 tst.w r7, #1024 @ 0x400 +10001af2: d086 beq.n 10001a02 <_ntoa_format+0x72> +10001af4: e789 b.n 10001a0a <_ntoa_format+0x7a> +10001af6: 073e lsls r6, r7, #28 +10001af8: d590 bpl.n 10001a1c <_ntoa_format+0x8c> +10001afa: 2620 movs r6, #32 +10001afc: f808 6004 strb.w r6, [r8, r4] +10001b00: 3401 adds r4, #1 +10001b02: e78b b.n 10001a1c <_ntoa_format+0x8c> +10001b04: f017 0f0c tst.w r7, #12 +10001b08: d000 beq.n 10001b0c <_ntoa_format+0x17c> +10001b0a: 3d01 subs r5, #1 +10001b0c: 42b4 cmp r4, r6 +10001b0e: f4ff af52 bcc.w 100019b6 <_ntoa_format+0x26> +10001b12: e761 b.n 100019d8 <_ntoa_format+0x48> +10001b14: 06bc lsls r4, r7, #26 +10001b16: d412 bmi.n 10001b3e <_ntoa_format+0x1ae> +10001b18: 2478 movs r4, #120 @ 0x78 +10001b1a: f888 4000 strb.w r4, [r8] +10001b1e: 2430 movs r4, #48 @ 0x30 +10001b20: f888 4001 strb.w r4, [r8, #1] +10001b24: 2402 movs r4, #2 +10001b26: f1ba 0f00 cmp.w sl, #0 +10001b2a: d099 beq.n 10001a60 <_ntoa_format+0xd0> +10001b2c: e7aa b.n 10001a84 <_ntoa_format+0xf4> +10001b2e: 2c20 cmp r4, #32 +10001b30: f43f af73 beq.w 10001a1a <_ntoa_format+0x8a> +10001b34: 2678 movs r6, #120 @ 0x78 +10001b36: f808 6004 strb.w r6, [r8, r4] +10001b3a: 3401 adds r4, #1 +10001b3c: e76b b.n 10001a16 <_ntoa_format+0x86> +10001b3e: 2458 movs r4, #88 @ 0x58 +10001b40: e7eb b.n 10001b1a <_ntoa_format+0x18a> +10001b42: 2462 movs r4, #98 @ 0x62 +10001b44: e7e9 b.n 10001b1a <_ntoa_format+0x18a> +10001b46: f017 0f20 tst.w r7, #32 +10001b4a: f1a4 0c02 sub.w ip, r4, #2 +10001b4e: d004 beq.n 10001b5a <_ntoa_format+0x1ca> +10001b50: f04f 0e58 mov.w lr, #88 @ 0x58 +10001b54: f808 e00c strb.w lr, [r8, ip] +10001b58: e78b b.n 10001a72 <_ntoa_format+0xe2> +10001b5a: f04f 0e78 mov.w lr, #120 @ 0x78 +10001b5e: f808 e00c strb.w lr, [r8, ip] +10001b62: e786 b.n 10001a72 <_ntoa_format+0xe2> + +10001b64 <_out_char>: +10001b64: b900 cbnz r0, 10001b68 <_out_char+0x4> +10001b66: 4770 bx lr +10001b68: f001 bbaa b.w 100032c0 <__wrap_putchar> + +10001b6c <_out_fct>: +10001b6c: b110 cbz r0, 10001b74 <_out_fct+0x8> +10001b6e: e9d1 3100 ldrd r3, r1, [r1] +10001b72: 4718 bx r3 +10001b74: 4770 bx lr +10001b76: bf00 nop + +10001b78 <_ftoa>: +10001b78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b7c: b097 sub sp, #92 @ 0x5c +10001b7e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001b82: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001b86: 4607 mov r7, r0 +10001b88: 4688 mov r8, r1 +10001b8a: ec51 0b17 vmov r0, r1, d7 +10001b8e: 9c24 ldr r4, [sp, #144] @ 0x90 +10001b90: 4699 mov r9, r3 +10001b92: 920c str r2, [sp, #48] @ 0x30 +10001b94: 460b mov r3, r1 +10001b96: 4602 mov r2, r0 +10001b98: ed8d 7b04 vstr d7, [sp, #16] +10001b9c: 9407 str r4, [sp, #28] +10001b9e: f7ff fe49 bl 10001834 <__wrap___aeabi_dcmpun> +10001ba2: 2800 cmp r0, #0 +10001ba4: f040 81f4 bne.w 10001f90 <_ftoa+0x418> +10001ba8: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001bb0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001bb4: f7ff fe50 bl 10001858 <__wrap___aeabi_dcmplt> +10001bb8: 2800 cmp r0, #0 +10001bba: f040 811b bne.w 10001df4 <_ftoa+0x27c> +10001bbe: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bc2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001bc6: 4bac ldr r3, [pc, #688] @ (10001e78 <_ftoa+0x300>) +10001bc8: f7ff fe82 bl 100018d0 <__wrap___aeabi_dcmpgt> +10001bcc: 2800 cmp r0, #0 +10001bce: f040 80ee bne.w 10001dae <_ftoa+0x236> +10001bd2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bd6: a3a4 add r3, pc, #656 @ (adr r3, 10001e68 <_ftoa+0x2f0>) +10001bd8: e9d3 2300 ldrd r2, r3, [r3] +10001bdc: f7ff fe78 bl 100018d0 <__wrap___aeabi_dcmpgt> +10001be0: 2800 cmp r0, #0 +10001be2: f040 80d3 bne.w 10001d8c <_ftoa+0x214> +10001be6: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bea: a3a1 add r3, pc, #644 @ (adr r3, 10001e70 <_ftoa+0x2f8>) +10001bec: e9d3 2300 ldrd r2, r3, [r3] +10001bf0: f7ff fe32 bl 10001858 <__wrap___aeabi_dcmplt> +10001bf4: 2800 cmp r0, #0 +10001bf6: f040 80c9 bne.w 10001d8c <_ftoa+0x214> +10001bfa: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bfe: 2200 movs r2, #0 +10001c00: 2300 movs r3, #0 +10001c02: f7ff fe29 bl 10001858 <__wrap___aeabi_dcmplt> +10001c06: 2800 cmp r0, #0 +10001c08: f040 80e8 bne.w 10001ddc <_ftoa+0x264> +10001c0c: 4623 mov r3, r4 +10001c0e: 900d str r0, [sp, #52] @ 0x34 +10001c10: f413 6f80 tst.w r3, #1024 @ 0x400 +10001c14: bf08 it eq +10001c16: 2506 moveq r5, #6 +10001c18: 2130 movs r1, #48 @ 0x30 +10001c1a: 462b mov r3, r5 +10001c1c: aa0e add r2, sp, #56 @ 0x38 +10001c1e: f1a5 0620 sub.w r6, r5, #32 +10001c22: e005 b.n 10001c30 <_ftoa+0xb8> +10001c24: 3b01 subs r3, #1 +10001c26: 42b3 cmp r3, r6 +10001c28: f802 1b01 strb.w r1, [r2], #1 +10001c2c: f000 8193 beq.w 10001f56 <_ftoa+0x3de> +10001c30: 2b09 cmp r3, #9 +10001c32: d8f7 bhi.n 10001c24 <_ftoa+0xac> +10001c34: 461e mov r6, r3 +10001c36: 1aed subs r5, r5, r3 +10001c38: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c3c: f7ff fdd6 bl 100017ec <__wrap___aeabi_d2iz> +10001c40: 4b8e ldr r3, [pc, #568] @ (10001e7c <_ftoa+0x304>) +10001c42: 4604 mov r4, r0 +10001c44: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001c48: ed93 7b00 vldr d7, [r3] +10001c4c: ed8d 7b08 vstr d7, [sp, #32] +10001c50: f7ff fda8 bl 100017a4 <__wrap___aeabi_i2d> +10001c54: 4602 mov r2, r0 +10001c56: 460b mov r3, r1 +10001c58: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c5c: f7ff fd1a bl 10001694 <__wrap___aeabi_dsub> +10001c60: e9dd 2308 ldrd r2, r3, [sp, #32] +10001c64: f7ff fd2a bl 100016bc <__wrap___aeabi_dmul> +10001c68: 4602 mov r2, r0 +10001c6a: 460b mov r3, r1 +10001c6c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001c70: f7ff fdce bl 10001810 <__wrap___aeabi_d2uiz> +10001c74: 4682 mov sl, r0 +10001c76: f7ff fda7 bl 100017c8 <__wrap___aeabi_ui2d> +10001c7a: 4602 mov r2, r0 +10001c7c: 460b mov r3, r1 +10001c7e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001c82: f7ff fd07 bl 10001694 <__wrap___aeabi_dsub> +10001c86: 4602 mov r2, r0 +10001c88: 460b mov r3, r1 +10001c8a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001c8e: 2200 movs r2, #0 +10001c90: 4b7b ldr r3, [pc, #492] @ (10001e80 <_ftoa+0x308>) +10001c92: f7ff fe1d bl 100018d0 <__wrap___aeabi_dcmpgt> +10001c96: 2800 cmp r0, #0 +10001c98: f000 80fe beq.w 10001e98 <_ftoa+0x320> +10001c9c: f10a 0a01 add.w sl, sl, #1 +10001ca0: 4650 mov r0, sl +10001ca2: f7ff fd91 bl 100017c8 <__wrap___aeabi_ui2d> +10001ca6: 4602 mov r2, r0 +10001ca8: 460b mov r3, r1 +10001caa: e9dd 0108 ldrd r0, r1, [sp, #32] +10001cae: f7ff fde7 bl 10001880 <__wrap___aeabi_dcmple> +10001cb2: b110 cbz r0, 10001cba <_ftoa+0x142> +10001cb4: f04f 0a00 mov.w sl, #0 +10001cb8: 3401 adds r4, #1 +10001cba: 2e00 cmp r6, #0 +10001cbc: f000 80fd beq.w 10001eba <_ftoa+0x342> +10001cc0: 1e68 subs r0, r5, #1 +10001cc2: ab0e add r3, sp, #56 @ 0x38 +10001cc4: f8df c1cc ldr.w ip, [pc, #460] @ 10001e94 <_ftoa+0x31c> +10001cc8: 4418 add r0, r3 +10001cca: e00f b.n 10001cec <_ftoa+0x174> +10001ccc: fbac 210a umull r2, r1, ip, sl +10001cd0: 08c9 lsrs r1, r1, #3 +10001cd2: eb01 0281 add.w r2, r1, r1, lsl #2 +10001cd6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001cda: 3230 adds r2, #48 @ 0x30 +10001cdc: f1ba 0f09 cmp.w sl, #9 +10001ce0: f800 2f01 strb.w r2, [r0, #1]! +10001ce4: f240 811c bls.w 10001f20 <_ftoa+0x3a8> +10001ce8: 468a mov sl, r1 +10001cea: 461d mov r5, r3 +10001cec: 2d20 cmp r5, #32 +10001cee: f105 0301 add.w r3, r5, #1 +10001cf2: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001cf6: d1e9 bne.n 10001ccc <_ftoa+0x154> +10001cf8: 2520 movs r5, #32 +10001cfa: 1e69 subs r1, r5, #1 +10001cfc: ab0e add r3, sp, #56 @ 0x38 +10001cfe: 4861 ldr r0, [pc, #388] @ (10001e84 <_ftoa+0x30c>) +10001d00: 4419 add r1, r3 +10001d02: e010 b.n 10001d26 <_ftoa+0x1ae> +10001d04: fb80 6204 smull r6, r2, r0, r4 +10001d08: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001d0c: eb03 0283 add.w r2, r3, r3, lsl #2 +10001d10: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001d14: f104 0230 add.w r2, r4, #48 @ 0x30 +10001d18: 3501 adds r5, #1 +10001d1a: 461c mov r4, r3 +10001d1c: f801 2f01 strb.w r2, [r1, #1]! +10001d20: 2b00 cmp r3, #0 +10001d22: f000 80eb beq.w 10001efc <_ftoa+0x384> +10001d26: 2d20 cmp r5, #32 +10001d28: ea4f 73e4 mov.w r3, r4, asr #31 +10001d2c: d1ea bne.n 10001d04 <_ftoa+0x18c> +10001d2e: 9b07 ldr r3, [sp, #28] +10001d30: f003 0303 and.w r3, r3, #3 +10001d34: 2b01 cmp r3, #1 +10001d36: d118 bne.n 10001d6a <_ftoa+0x1f2> +10001d38: f1bb 0f00 cmp.w fp, #0 +10001d3c: d015 beq.n 10001d6a <_ftoa+0x1f2> +10001d3e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d40: 2b00 cmp r3, #0 +10001d42: f000 810a beq.w 10001f5a <_ftoa+0x3e2> +10001d46: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d4a: f1bb 0f20 cmp.w fp, #32 +10001d4e: d90c bls.n 10001d6a <_ftoa+0x1f2> +10001d50: 1e6b subs r3, r5, #1 +10001d52: a90e add r1, sp, #56 @ 0x38 +10001d54: 2230 movs r2, #48 @ 0x30 +10001d56: 440b add r3, r1 +10001d58: e005 b.n 10001d66 <_ftoa+0x1ee> +10001d5a: 3501 adds r5, #1 +10001d5c: 455d cmp r5, fp +10001d5e: f803 2f01 strb.w r2, [r3, #1]! +10001d62: f080 80d1 bcs.w 10001f08 <_ftoa+0x390> +10001d66: 2d20 cmp r5, #32 +10001d68: d1f7 bne.n 10001d5a <_ftoa+0x1e2> +10001d6a: 9b07 ldr r3, [sp, #28] +10001d6c: ac0e add r4, sp, #56 @ 0x38 +10001d6e: e9cd b302 strd fp, r3, [sp, #8] +10001d72: 4641 mov r1, r8 +10001d74: 464b mov r3, r9 +10001d76: 4638 mov r0, r7 +10001d78: 9a0c ldr r2, [sp, #48] @ 0x30 +10001d7a: 9501 str r5, [sp, #4] +10001d7c: 9400 str r4, [sp, #0] +10001d7e: f7ff fdb9 bl 100018f4 <_out_rev> +10001d82: 4682 mov sl, r0 +10001d84: 4650 mov r0, sl +10001d86: b017 add sp, #92 @ 0x5c +10001d88: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001d8c: 9b07 ldr r3, [sp, #28] +10001d8e: ed9d 7b04 vldr d7, [sp, #16] +10001d92: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001d96: 4641 mov r1, r8 +10001d98: 464b mov r3, r9 +10001d9a: 4638 mov r0, r7 +10001d9c: 9a0c ldr r2, [sp, #48] @ 0x30 +10001d9e: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001da2: 9522 str r5, [sp, #136] @ 0x88 +10001da4: b017 add sp, #92 @ 0x5c +10001da6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001daa: f000 b945 b.w 10002038 <_etoa> +10001dae: 0761 lsls r1, r4, #29 +10001db0: 4623 mov r3, r4 +10001db2: bf4c ite mi +10001db4: 2304 movmi r3, #4 +10001db6: 2303 movpl r3, #3 +10001db8: 4641 mov r1, r8 +10001dba: 9321 str r3, [sp, #132] @ 0x84 +10001dbc: 4638 mov r0, r7 +10001dbe: 464b mov r3, r9 +10001dc0: 9a07 ldr r2, [sp, #28] +10001dc2: bf48 it mi +10001dc4: 4c30 ldrmi r4, [pc, #192] @ (10001e88 <_ftoa+0x310>) +10001dc6: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001dca: bf58 it pl +10001dcc: 4c2f ldrpl r4, [pc, #188] @ (10001e8c <_ftoa+0x314>) +10001dce: 9a0c ldr r2, [sp, #48] @ 0x30 +10001dd0: 9420 str r4, [sp, #128] @ 0x80 +10001dd2: b017 add sp, #92 @ 0x5c +10001dd4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001dd8: f7ff bd8c b.w 100018f4 <_out_rev> +10001ddc: e9dd 2304 ldrd r2, r3, [sp, #16] +10001de0: 2000 movs r0, #0 +10001de2: 2100 movs r1, #0 +10001de4: f7ff fc56 bl 10001694 <__wrap___aeabi_dsub> +10001de8: 2301 movs r3, #1 +10001dea: e9cd 0104 strd r0, r1, [sp, #16] +10001dee: 930d str r3, [sp, #52] @ 0x34 +10001df0: 4623 mov r3, r4 +10001df2: e70d b.n 10001c10 <_ftoa+0x98> +10001df4: 4623 mov r3, r4 +10001df6: 079c lsls r4, r3, #30 +10001df8: f040 80aa bne.w 10001f50 <_ftoa+0x3d8> +10001dfc: f1bb 0f04 cmp.w fp, #4 +10001e00: f240 80a6 bls.w 10001f50 <_ftoa+0x3d8> +10001e04: 9b0c ldr r3, [sp, #48] @ 0x30 +10001e06: 461d mov r5, r3 +10001e08: 1f1c subs r4, r3, #4 +10001e0a: eb04 0a0b add.w sl, r4, fp +10001e0e: 462a mov r2, r5 +10001e10: 464b mov r3, r9 +10001e12: 4641 mov r1, r8 +10001e14: 2020 movs r0, #32 +10001e16: 3501 adds r5, #1 +10001e18: 47b8 blx r7 +10001e1a: 45aa cmp sl, r5 +10001e1c: d1f7 bne.n 10001e0e <_ftoa+0x296> +10001e1e: 4655 mov r5, sl +10001e20: 4c1b ldr r4, [pc, #108] @ (10001e90 <_ftoa+0x318>) +10001e22: 1f26 subs r6, r4, #4 +10001e24: f814 0d01 ldrb.w r0, [r4, #-1]! +10001e28: 462a mov r2, r5 +10001e2a: 464b mov r3, r9 +10001e2c: 4641 mov r1, r8 +10001e2e: 47b8 blx r7 +10001e30: 42b4 cmp r4, r6 +10001e32: f105 0501 add.w r5, r5, #1 +10001e36: d1f5 bne.n 10001e24 <_ftoa+0x2ac> +10001e38: 9b07 ldr r3, [sp, #28] +10001e3a: f10a 0a04 add.w sl, sl, #4 +10001e3e: 0798 lsls r0, r3, #30 +10001e40: d5a0 bpl.n 10001d84 <_ftoa+0x20c> +10001e42: 9c0c ldr r4, [sp, #48] @ 0x30 +10001e44: ebaa 0304 sub.w r3, sl, r4 +10001e48: 459b cmp fp, r3 +10001e4a: d99b bls.n 10001d84 <_ftoa+0x20c> +10001e4c: 4652 mov r2, sl +10001e4e: 464b mov r3, r9 +10001e50: 4641 mov r1, r8 +10001e52: 2020 movs r0, #32 +10001e54: f10a 0a01 add.w sl, sl, #1 +10001e58: 47b8 blx r7 +10001e5a: ebaa 0304 sub.w r3, sl, r4 +10001e5e: 455b cmp r3, fp +10001e60: d3f4 bcc.n 10001e4c <_ftoa+0x2d4> +10001e62: e78f b.n 10001d84 <_ftoa+0x20c> +10001e64: f3af 8000 nop.w +10001e68: 00000000 .word 0x00000000 +10001e6c: 41cdcd65 .word 0x41cdcd65 +10001e70: 00000000 .word 0x00000000 +10001e74: c1cdcd65 .word 0xc1cdcd65 +10001e78: 7fefffff .word 0x7fefffff +10001e7c: 10003968 .word 0x10003968 +10001e80: 3fe00000 .word 0x3fe00000 +10001e84: 66666667 .word 0x66666667 +10001e88: 100038b8 .word 0x100038b8 +10001e8c: 100038c0 .word 0x100038c0 +10001e90: 100038cc .word 0x100038cc +10001e94: cccccccd .word 0xcccccccd +10001e98: 2200 movs r2, #0 +10001e9a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001e9e: 4b63 ldr r3, [pc, #396] @ (1000202c <_ftoa+0x4b4>) +10001ea0: f7ff fcda bl 10001858 <__wrap___aeabi_dcmplt> +10001ea4: 2800 cmp r0, #0 +10001ea6: f47f af08 bne.w 10001cba <_ftoa+0x142> +10001eaa: f1ba 0f00 cmp.w sl, #0 +10001eae: d16a bne.n 10001f86 <_ftoa+0x40e> +10001eb0: f10a 0a01 add.w sl, sl, #1 +10001eb4: 2e00 cmp r6, #0 +10001eb6: f47f af03 bne.w 10001cc0 <_ftoa+0x148> +10001eba: 4620 mov r0, r4 +10001ebc: f7ff fc72 bl 100017a4 <__wrap___aeabi_i2d> +10001ec0: 4602 mov r2, r0 +10001ec2: 460b mov r3, r1 +10001ec4: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ec8: f7ff fbe4 bl 10001694 <__wrap___aeabi_dsub> +10001ecc: 4602 mov r2, r0 +10001ece: 460b mov r3, r1 +10001ed0: e9cd 2304 strd r2, r3, [sp, #16] +10001ed4: 2200 movs r2, #0 +10001ed6: 4b55 ldr r3, [pc, #340] @ (1000202c <_ftoa+0x4b4>) +10001ed8: f7ff fcbe bl 10001858 <__wrap___aeabi_dcmplt> +10001edc: 2800 cmp r0, #0 +10001ede: f47f af0c bne.w 10001cfa <_ftoa+0x182> +10001ee2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ee6: 2200 movs r2, #0 +10001ee8: 4b50 ldr r3, [pc, #320] @ (1000202c <_ftoa+0x4b4>) +10001eea: f7ff fcf1 bl 100018d0 <__wrap___aeabi_dcmpgt> +10001eee: 2800 cmp r0, #0 +10001ef0: f47f af03 bne.w 10001cfa <_ftoa+0x182> +10001ef4: 3401 adds r4, #1 +10001ef6: f024 0401 bic.w r4, r4, #1 +10001efa: e6fe b.n 10001cfa <_ftoa+0x182> +10001efc: 9b07 ldr r3, [sp, #28] +10001efe: f003 0303 and.w r3, r3, #3 +10001f02: 2b01 cmp r3, #1 +10001f04: f000 8082 beq.w 1000200c <_ftoa+0x494> +10001f08: 2d20 cmp r5, #32 +10001f0a: f43f af2e beq.w 10001d6a <_ftoa+0x1f2> +10001f0e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001f10: b37b cbz r3, 10001f72 <_ftoa+0x3fa> +10001f12: 222d movs r2, #45 @ 0x2d +10001f14: eb0d 0305 add.w r3, sp, r5 +10001f18: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001f1c: 3501 adds r5, #1 +10001f1e: e724 b.n 10001d6a <_ftoa+0x1f2> +10001f20: 2b20 cmp r3, #32 +10001f22: f43f aee9 beq.w 10001cf8 <_ftoa+0x180> +10001f26: aa0e add r2, sp, #56 @ 0x38 +10001f28: 4415 add r5, r2 +10001f2a: 441e add r6, r3 +10001f2c: 2230 movs r2, #48 @ 0x30 +10001f2e: e004 b.n 10001f3a <_ftoa+0x3c2> +10001f30: 2b20 cmp r3, #32 +10001f32: f805 2f01 strb.w r2, [r5, #1]! +10001f36: f43f aedf beq.w 10001cf8 <_ftoa+0x180> +10001f3a: 429e cmp r6, r3 +10001f3c: f103 0301 add.w r3, r3, #1 +10001f40: d1f6 bne.n 10001f30 <_ftoa+0x3b8> +10001f42: 222e movs r2, #46 @ 0x2e +10001f44: eb0d 0306 add.w r3, sp, r6 +10001f48: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001f4c: 1c75 adds r5, r6, #1 +10001f4e: e6d4 b.n 10001cfa <_ftoa+0x182> +10001f50: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001f54: e763 b.n 10001e1e <_ftoa+0x2a6> +10001f56: 2520 movs r5, #32 +10001f58: e66e b.n 10001c38 <_ftoa+0xc0> +10001f5a: 9b07 ldr r3, [sp, #28] +10001f5c: f013 0f0c tst.w r3, #12 +10001f60: d050 beq.n 10002004 <_ftoa+0x48c> +10001f62: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001f66: 45ab cmp fp, r5 +10001f68: f63f aef2 bhi.w 10001d50 <_ftoa+0x1d8> +10001f6c: 2d20 cmp r5, #32 +10001f6e: f43f aefc beq.w 10001d6a <_ftoa+0x1f2> +10001f72: 9b07 ldr r3, [sp, #28] +10001f74: 075a lsls r2, r3, #29 +10001f76: d501 bpl.n 10001f7c <_ftoa+0x404> +10001f78: 222b movs r2, #43 @ 0x2b +10001f7a: e7cb b.n 10001f14 <_ftoa+0x39c> +10001f7c: 071b lsls r3, r3, #28 +10001f7e: f57f aef4 bpl.w 10001d6a <_ftoa+0x1f2> +10001f82: 2220 movs r2, #32 +10001f84: e7c6 b.n 10001f14 <_ftoa+0x39c> +10001f86: f01a 0f01 tst.w sl, #1 +10001f8a: f43f ae96 beq.w 10001cba <_ftoa+0x142> +10001f8e: e78f b.n 10001eb0 <_ftoa+0x338> +10001f90: 07a6 lsls r6, r4, #30 +10001f92: d134 bne.n 10001ffe <_ftoa+0x486> +10001f94: f1bb 0f03 cmp.w fp, #3 +10001f98: d931 bls.n 10001ffe <_ftoa+0x486> +10001f9a: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f9c: 461d mov r5, r3 +10001f9e: 1edc subs r4, r3, #3 +10001fa0: eb04 0a0b add.w sl, r4, fp +10001fa4: 462a mov r2, r5 +10001fa6: 464b mov r3, r9 +10001fa8: 4641 mov r1, r8 +10001faa: 2020 movs r0, #32 +10001fac: 3501 adds r5, #1 +10001fae: 47b8 blx r7 +10001fb0: 4555 cmp r5, sl +10001fb2: d1f7 bne.n 10001fa4 <_ftoa+0x42c> +10001fb4: 4655 mov r5, sl +10001fb6: 4c1e ldr r4, [pc, #120] @ (10002030 <_ftoa+0x4b8>) +10001fb8: 1ee6 subs r6, r4, #3 +10001fba: f814 0d01 ldrb.w r0, [r4, #-1]! +10001fbe: 462a mov r2, r5 +10001fc0: 464b mov r3, r9 +10001fc2: 4641 mov r1, r8 +10001fc4: 47b8 blx r7 +10001fc6: 42a6 cmp r6, r4 +10001fc8: f105 0501 add.w r5, r5, #1 +10001fcc: d1f5 bne.n 10001fba <_ftoa+0x442> +10001fce: 9b07 ldr r3, [sp, #28] +10001fd0: f10a 0a03 add.w sl, sl, #3 +10001fd4: 079d lsls r5, r3, #30 +10001fd6: f57f aed5 bpl.w 10001d84 <_ftoa+0x20c> +10001fda: 9c0c ldr r4, [sp, #48] @ 0x30 +10001fdc: ebaa 0304 sub.w r3, sl, r4 +10001fe0: 459b cmp fp, r3 +10001fe2: f67f aecf bls.w 10001d84 <_ftoa+0x20c> +10001fe6: 4652 mov r2, sl +10001fe8: 464b mov r3, r9 +10001fea: 4641 mov r1, r8 +10001fec: 2020 movs r0, #32 +10001fee: f10a 0a01 add.w sl, sl, #1 +10001ff2: 47b8 blx r7 +10001ff4: ebaa 0304 sub.w r3, sl, r4 +10001ff8: 459b cmp fp, r3 +10001ffa: d8f4 bhi.n 10001fe6 <_ftoa+0x46e> +10001ffc: e6c2 b.n 10001d84 <_ftoa+0x20c> +10001ffe: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10002002: e7d7 b.n 10001fb4 <_ftoa+0x43c> +10002004: 45ab cmp fp, r5 +10002006: f63f aea3 bhi.w 10001d50 <_ftoa+0x1d8> +1000200a: e6ae b.n 10001d6a <_ftoa+0x1f2> +1000200c: f1bb 0f00 cmp.w fp, #0 +10002010: f43f af7a beq.w 10001f08 <_ftoa+0x390> +10002014: 9b0d ldr r3, [sp, #52] @ 0x34 +10002016: 2b00 cmp r3, #0 +10002018: d09f beq.n 10001f5a <_ftoa+0x3e2> +1000201a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000201e: 455d cmp r5, fp +10002020: f4ff ae96 bcc.w 10001d50 <_ftoa+0x1d8> +10002024: 2d20 cmp r5, #32 +10002026: f47f af74 bne.w 10001f12 <_ftoa+0x39a> +1000202a: e69e b.n 10001d6a <_ftoa+0x1f2> +1000202c: 3fe00000 .word 0x3fe00000 +10002030: 100038c7 .word 0x100038c7 +10002034: 00000000 .word 0x00000000 + +10002038 <_etoa>: +10002038: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000203c: b09f sub sp, #124 @ 0x7c +1000203e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10002040: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10002044: 4607 mov r7, r0 +10002046: 4693 mov fp, r2 +10002048: 9108 str r1, [sp, #32] +1000204a: 9309 str r3, [sp, #36] @ 0x24 +1000204c: 4622 mov r2, r4 +1000204e: 462b mov r3, r5 +10002050: 4620 mov r0, r4 +10002052: 4629 mov r1, r5 +10002054: 960e str r6, [sp, #56] @ 0x38 +10002056: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +1000205a: f7ff fbeb bl 10001834 <__wrap___aeabi_dcmpun> +1000205e: 2800 cmp r0, #0 +10002060: f040 80be bne.w 100021e0 <_etoa+0x1a8> +10002064: 4620 mov r0, r4 +10002066: 4629 mov r1, r5 +10002068: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000206c: 4b78 ldr r3, [pc, #480] @ (10002250 <_etoa+0x218>) +1000206e: f7ff fc2f bl 100018d0 <__wrap___aeabi_dcmpgt> +10002072: 2800 cmp r0, #0 +10002074: f040 80b4 bne.w 100021e0 <_etoa+0x1a8> +10002078: 4620 mov r0, r4 +1000207a: 4629 mov r1, r5 +1000207c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002080: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10002084: f7ff fbe8 bl 10001858 <__wrap___aeabi_dcmplt> +10002088: 2800 cmp r0, #0 +1000208a: f040 80a9 bne.w 100021e0 <_etoa+0x1a8> +1000208e: 4620 mov r0, r4 +10002090: 4629 mov r1, r5 +10002092: 2200 movs r2, #0 +10002094: 2300 movs r3, #0 +10002096: f7ff fbdf bl 10001858 <__wrap___aeabi_dcmplt> +1000209a: 2800 cmp r0, #0 +1000209c: f040 81d5 bne.w 1000244a <_etoa+0x412> +100020a0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +100020a4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +100020a8: 4690 mov r8, r2 +100020aa: 4699 mov r9, r3 +100020ac: f406 6200 and.w r2, r6, #2048 @ 0x800 +100020b0: f416 6380 ands.w r3, r6, #1024 @ 0x400 +100020b4: 920f str r2, [sp, #60] @ 0x3c +100020b6: 9313 str r3, [sp, #76] @ 0x4c +100020b8: f040 80a1 bne.w 100021fe <_etoa+0x1c6> +100020bc: ea58 0309 orrs.w r3, r8, r9 +100020c0: f040 80ca bne.w 10002258 <_etoa+0x220> +100020c4: 2a00 cmp r2, #0 +100020c6: f040 81e3 bne.w 10002490 <_etoa+0x458> +100020ca: 2306 movs r3, #6 +100020cc: 930e str r3, [sp, #56] @ 0x38 +100020ce: f016 0202 ands.w r2, r6, #2 +100020d2: 9210 str r2, [sp, #64] @ 0x40 +100020d4: f040 81d4 bne.w 10002480 <_etoa+0x448> +100020d8: 4653 mov r3, sl +100020da: 2b04 cmp r3, #4 +100020dc: bf38 it cc +100020de: 2304 movcc r3, #4 +100020e0: 920c str r2, [sp, #48] @ 0x30 +100020e2: 2204 movs r2, #4 +100020e4: 3b04 subs r3, #4 +100020e6: 9212 str r2, [sp, #72] @ 0x48 +100020e8: 930f str r3, [sp, #60] @ 0x3c +100020ea: 4620 mov r0, r4 +100020ec: 4629 mov r1, r5 +100020ee: 2200 movs r2, #0 +100020f0: 2300 movs r3, #0 +100020f2: f7ff fbb1 bl 10001858 <__wrap___aeabi_dcmplt> +100020f6: 2800 cmp r0, #0 +100020f8: f040 81f3 bne.w 100024e2 <_etoa+0x4aa> +100020fc: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002100: 9b0f ldr r3, [sp, #60] @ 0x3c +10002102: 465a mov r2, fp +10002104: 9303 str r3, [sp, #12] +10002106: 9b0e ldr r3, [sp, #56] @ 0x38 +10002108: ed8d 7b00 vstr d7, [sp] +1000210c: 9302 str r3, [sp, #8] +1000210e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002112: 9304 str r3, [sp, #16] +10002114: 4638 mov r0, r7 +10002116: 9b09 ldr r3, [sp, #36] @ 0x24 +10002118: 9908 ldr r1, [sp, #32] +1000211a: f7ff fd2d bl 10001b78 <_ftoa> +1000211e: 4602 mov r2, r0 +10002120: f016 0f20 tst.w r6, #32 +10002124: 9b09 ldr r3, [sp, #36] @ 0x24 +10002126: 9908 ldr r1, [sp, #32] +10002128: bf0c ite eq +1000212a: 2065 moveq r0, #101 @ 0x65 +1000212c: 2045 movne r0, #69 @ 0x45 +1000212e: f102 0801 add.w r8, r2, #1 +10002132: 47b8 blx r7 +10002134: 9a0c ldr r2, [sp, #48] @ 0x30 +10002136: 9b12 ldr r3, [sp, #72] @ 0x48 +10002138: ac16 add r4, sp, #88 @ 0x58 +1000213a: 1e5d subs r5, r3, #1 +1000213c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10002140: eba3 73e2 sub.w r3, r3, r2, asr #31 +10002144: 0fd1 lsrs r1, r2, #31 +10002146: 2600 movs r6, #0 +10002148: 4622 mov r2, r4 +1000214a: 4699 mov r9, r3 +1000214c: f8df c104 ldr.w ip, [pc, #260] @ 10002254 <_etoa+0x21c> +10002150: e001 b.n 10002156 <_etoa+0x11e> +10002152: 2e20 cmp r6, #32 +10002154: d010 beq.n 10002178 <_etoa+0x140> +10002156: 46ce mov lr, r9 +10002158: fbac 3009 umull r3, r0, ip, r9 +1000215c: 08c0 lsrs r0, r0, #3 +1000215e: eb00 0380 add.w r3, r0, r0, lsl #2 +10002162: eba9 0343 sub.w r3, r9, r3, lsl #1 +10002166: 3330 adds r3, #48 @ 0x30 +10002168: f1be 0f09 cmp.w lr, #9 +1000216c: 4681 mov r9, r0 +1000216e: f106 0601 add.w r6, r6, #1 +10002172: f802 3b01 strb.w r3, [r2], #1 +10002176: d8ec bhi.n 10002152 <_etoa+0x11a> +10002178: 2305 movs r3, #5 +1000217a: 2000 movs r0, #0 +1000217c: 9306 str r3, [sp, #24] +1000217e: 230a movs r3, #10 +10002180: 9505 str r5, [sp, #20] +10002182: 9400 str r4, [sp, #0] +10002184: 9d09 ldr r5, [sp, #36] @ 0x24 +10002186: 9c08 ldr r4, [sp, #32] +10002188: 4642 mov r2, r8 +1000218a: e9cd 3003 strd r3, r0, [sp, #12] +1000218e: e9cd 6101 strd r6, r1, [sp, #4] +10002192: 462b mov r3, r5 +10002194: 4621 mov r1, r4 +10002196: 4638 mov r0, r7 +10002198: f7ff fbfa bl 10001990 <_ntoa_format> +1000219c: 9a10 ldr r2, [sp, #64] @ 0x40 +1000219e: 4680 mov r8, r0 +100021a0: b1d2 cbz r2, 100021d8 <_etoa+0x1a0> +100021a2: eba0 060b sub.w r6, r0, fp +100021a6: 45b2 cmp sl, r6 +100021a8: d916 bls.n 100021d8 <_etoa+0x1a0> +100021aa: eb0b 0206 add.w r2, fp, r6 +100021ae: 462b mov r3, r5 +100021b0: 4621 mov r1, r4 +100021b2: 2020 movs r0, #32 +100021b4: 3601 adds r6, #1 +100021b6: 47b8 blx r7 +100021b8: 45b2 cmp sl, r6 +100021ba: d8f6 bhi.n 100021aa <_etoa+0x172> +100021bc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +100021c0: 4453 add r3, sl +100021c2: f1cb 0201 rsb r2, fp, #1 +100021c6: eba3 0308 sub.w r3, r3, r8 +100021ca: 4442 add r2, r8 +100021cc: 4592 cmp sl, r2 +100021ce: bf38 it cc +100021d0: 2300 movcc r3, #0 +100021d2: f108 0801 add.w r8, r8, #1 +100021d6: 4498 add r8, r3 +100021d8: 4640 mov r0, r8 +100021da: b01f add sp, #124 @ 0x7c +100021dc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100021e0: 465a mov r2, fp +100021e2: 4638 mov r0, r7 +100021e4: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100021e8: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +100021ec: 9c0e ldr r4, [sp, #56] @ 0x38 +100021ee: 9b09 ldr r3, [sp, #36] @ 0x24 +100021f0: 9908 ldr r1, [sp, #32] +100021f2: 942a str r4, [sp, #168] @ 0xa8 +100021f4: b01f add sp, #124 @ 0x7c +100021f6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100021fa: f7ff bcbd b.w 10001b78 <_ftoa> +100021fe: ea58 0309 orrs.w r3, r8, r9 +10002202: d12b bne.n 1000225c <_etoa+0x224> +10002204: 2a00 cmp r2, #0 +10002206: f43f af62 beq.w 100020ce <_etoa+0x96> +1000220a: 2300 movs r3, #0 +1000220c: 930c str r3, [sp, #48] @ 0x30 +1000220e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002210: 9a0c ldr r2, [sp, #48] @ 0x30 +10002212: 4293 cmp r3, r2 +10002214: f300 81b9 bgt.w 1000258a <_etoa+0x552> +10002218: f04f 0800 mov.w r8, #0 +1000221c: 4620 mov r0, r4 +1000221e: 4629 mov r1, r5 +10002220: 2200 movs r2, #0 +10002222: 2300 movs r3, #0 +10002224: f7ff fb18 bl 10001858 <__wrap___aeabi_dcmplt> +10002228: 2800 cmp r0, #0 +1000222a: f040 8113 bne.w 10002454 <_etoa+0x41c> +1000222e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002232: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002236: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000223a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1000223e: 465a mov r2, fp +10002240: 4638 mov r0, r7 +10002242: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002246: 9b09 ldr r3, [sp, #36] @ 0x24 +10002248: 9908 ldr r1, [sp, #32] +1000224a: 962c str r6, [sp, #176] @ 0xb0 +1000224c: e7d2 b.n 100021f4 <_etoa+0x1bc> +1000224e: bf00 nop +10002250: 7fefffff .word 0x7fefffff +10002254: cccccccd .word 0xcccccccd +10002258: 2306 movs r3, #6 +1000225a: 930e str r3, [sp, #56] @ 0x38 +1000225c: f3c9 500a ubfx r0, r9, #20, #11 +10002260: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10002264: f7ff fa9e bl 100017a4 <__wrap___aeabi_i2d> +10002268: a3c1 add r3, pc, #772 @ (adr r3, 10002570 <_etoa+0x538>) +1000226a: e9d3 2300 ldrd r2, r3, [r3] +1000226e: f7ff fa25 bl 100016bc <__wrap___aeabi_dmul> +10002272: a3c1 add r3, pc, #772 @ (adr r3, 10002578 <_etoa+0x540>) +10002274: e9d3 2300 ldrd r2, r3, [r3] +10002278: f7ff f9f8 bl 1000166c <__wrap___aeabi_dadd> +1000227c: f3c9 0913 ubfx r9, r9, #0, #20 +10002280: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002284: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002288: 4640 mov r0, r8 +1000228a: 2200 movs r2, #0 +1000228c: 4bb2 ldr r3, [pc, #712] @ (10002558 <_etoa+0x520>) +1000228e: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10002292: f7ff f9ff bl 10001694 <__wrap___aeabi_dsub> +10002296: a3a4 add r3, pc, #656 @ (adr r3, 10002528 <_etoa+0x4f0>) +10002298: e9d3 2300 ldrd r2, r3, [r3] +1000229c: f7ff fa0e bl 100016bc <__wrap___aeabi_dmul> +100022a0: 4602 mov r2, r0 +100022a2: 460b mov r3, r1 +100022a4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +100022a8: f7ff f9e0 bl 1000166c <__wrap___aeabi_dadd> +100022ac: f7ff fa9e bl 100017ec <__wrap___aeabi_d2iz> +100022b0: 900c str r0, [sp, #48] @ 0x30 +100022b2: f7ff fa77 bl 100017a4 <__wrap___aeabi_i2d> +100022b6: a39e add r3, pc, #632 @ (adr r3, 10002530 <_etoa+0x4f8>) +100022b8: e9d3 2300 ldrd r2, r3, [r3] +100022bc: 4680 mov r8, r0 +100022be: 4689 mov r9, r1 +100022c0: f7ff f9fc bl 100016bc <__wrap___aeabi_dmul> +100022c4: 2200 movs r2, #0 +100022c6: 4ba5 ldr r3, [pc, #660] @ (1000255c <_etoa+0x524>) +100022c8: f7ff f9d0 bl 1000166c <__wrap___aeabi_dadd> +100022cc: f7ff fa8e bl 100017ec <__wrap___aeabi_d2iz> +100022d0: 4603 mov r3, r0 +100022d2: 4649 mov r1, r9 +100022d4: 4640 mov r0, r8 +100022d6: 9312 str r3, [sp, #72] @ 0x48 +100022d8: a397 add r3, pc, #604 @ (adr r3, 10002538 <_etoa+0x500>) +100022da: e9d3 2300 ldrd r2, r3, [r3] +100022de: f7ff f9ed bl 100016bc <__wrap___aeabi_dmul> +100022e2: 4680 mov r8, r0 +100022e4: 9812 ldr r0, [sp, #72] @ 0x48 +100022e6: 4689 mov r9, r1 +100022e8: f7ff fa5c bl 100017a4 <__wrap___aeabi_i2d> +100022ec: a394 add r3, pc, #592 @ (adr r3, 10002540 <_etoa+0x508>) +100022ee: e9d3 2300 ldrd r2, r3, [r3] +100022f2: f7ff f9e3 bl 100016bc <__wrap___aeabi_dmul> +100022f6: 4602 mov r2, r0 +100022f8: 460b mov r3, r1 +100022fa: 4640 mov r0, r8 +100022fc: 4649 mov r1, r9 +100022fe: f7ff f9c9 bl 10001694 <__wrap___aeabi_dsub> +10002302: 4602 mov r2, r0 +10002304: 460b mov r3, r1 +10002306: 4680 mov r8, r0 +10002308: 4689 mov r9, r1 +1000230a: f7ff f9d7 bl 100016bc <__wrap___aeabi_dmul> +1000230e: 4642 mov r2, r8 +10002310: 464b mov r3, r9 +10002312: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002316: 4640 mov r0, r8 +10002318: 4649 mov r1, r9 +1000231a: f7ff f9a7 bl 1000166c <__wrap___aeabi_dadd> +1000231e: 2200 movs r2, #0 +10002320: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10002324: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002328: 4b8d ldr r3, [pc, #564] @ (10002560 <_etoa+0x528>) +1000232a: f7ff f9ed bl 10001708 <__wrap___aeabi_ddiv> +1000232e: 2200 movs r2, #0 +10002330: 4b8c ldr r3, [pc, #560] @ (10002564 <_etoa+0x52c>) +10002332: f7ff f99b bl 1000166c <__wrap___aeabi_dadd> +10002336: 4602 mov r2, r0 +10002338: 460b mov r3, r1 +1000233a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000233e: f7ff f9e3 bl 10001708 <__wrap___aeabi_ddiv> +10002342: 2200 movs r2, #0 +10002344: 4b88 ldr r3, [pc, #544] @ (10002568 <_etoa+0x530>) +10002346: f7ff f991 bl 1000166c <__wrap___aeabi_dadd> +1000234a: 4602 mov r2, r0 +1000234c: 460b mov r3, r1 +1000234e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002352: f7ff f9d9 bl 10001708 <__wrap___aeabi_ddiv> +10002356: 4642 mov r2, r8 +10002358: 464b mov r3, r9 +1000235a: 4680 mov r8, r0 +1000235c: 4689 mov r9, r1 +1000235e: 2000 movs r0, #0 +10002360: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002364: f7ff f996 bl 10001694 <__wrap___aeabi_dsub> +10002368: 4602 mov r2, r0 +1000236a: 460b mov r3, r1 +1000236c: 4640 mov r0, r8 +1000236e: 4649 mov r1, r9 +10002370: f7ff f97c bl 1000166c <__wrap___aeabi_dadd> +10002374: 4602 mov r2, r0 +10002376: 460b mov r3, r1 +10002378: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000237c: f7ff f9c4 bl 10001708 <__wrap___aeabi_ddiv> +10002380: 2200 movs r2, #0 +10002382: 4b7a ldr r3, [pc, #488] @ (1000256c <_etoa+0x534>) +10002384: f7ff f972 bl 1000166c <__wrap___aeabi_dadd> +10002388: 9b12 ldr r3, [sp, #72] @ 0x48 +1000238a: 2200 movs r2, #0 +1000238c: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002390: ea4f 530c mov.w r3, ip, lsl #20 +10002394: f7ff f992 bl 100016bc <__wrap___aeabi_dmul> +10002398: 4680 mov r8, r0 +1000239a: 4689 mov r9, r1 +1000239c: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100023a0: 4642 mov r2, r8 +100023a2: 464b mov r3, r9 +100023a4: f7ff fa58 bl 10001858 <__wrap___aeabi_dcmplt> +100023a8: b150 cbz r0, 100023c0 <_etoa+0x388> +100023aa: 9b0c ldr r3, [sp, #48] @ 0x30 +100023ac: 4640 mov r0, r8 +100023ae: 3b01 subs r3, #1 +100023b0: 4649 mov r1, r9 +100023b2: 930c str r3, [sp, #48] @ 0x30 +100023b4: 2200 movs r2, #0 +100023b6: 4b6b ldr r3, [pc, #428] @ (10002564 <_etoa+0x52c>) +100023b8: f7ff f9a6 bl 10001708 <__wrap___aeabi_ddiv> +100023bc: 4680 mov r8, r0 +100023be: 4689 mov r9, r1 +100023c0: 9a0c ldr r2, [sp, #48] @ 0x30 +100023c2: 4643 mov r3, r8 +100023c4: 3263 adds r2, #99 @ 0x63 +100023c6: 2ac6 cmp r2, #198 @ 0xc6 +100023c8: f006 0202 and.w r2, r6, #2 +100023cc: 9210 str r2, [sp, #64] @ 0x40 +100023ce: 4649 mov r1, r9 +100023d0: 9a0f ldr r2, [sp, #60] @ 0x3c +100023d2: d82c bhi.n 1000242e <_etoa+0x3f6> +100023d4: 2a00 cmp r2, #0 +100023d6: d05e beq.n 10002496 <_etoa+0x45e> +100023d8: 2204 movs r2, #4 +100023da: 9212 str r2, [sp, #72] @ 0x48 +100023dc: 430b orrs r3, r1 +100023de: f43f af16 beq.w 1000220e <_etoa+0x1d6> +100023e2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100023e6: a358 add r3, pc, #352 @ (adr r3, 10002548 <_etoa+0x510>) +100023e8: e9d3 2300 ldrd r2, r3, [r3] +100023ec: f7ff fa5c bl 100018a8 <__wrap___aeabi_dcmpge> +100023f0: b148 cbz r0, 10002406 <_etoa+0x3ce> +100023f2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100023f6: a356 add r3, pc, #344 @ (adr r3, 10002550 <_etoa+0x518>) +100023f8: e9d3 2300 ldrd r2, r3, [r3] +100023fc: f7ff fa2c bl 10001858 <__wrap___aeabi_dcmplt> +10002400: 2800 cmp r0, #0 +10002402: f47f af04 bne.w 1000220e <_etoa+0x1d6> +10002406: 9b0e ldr r3, [sp, #56] @ 0x38 +10002408: 2b00 cmp r3, #0 +1000240a: d050 beq.n 100024ae <_etoa+0x476> +1000240c: 9a13 ldr r2, [sp, #76] @ 0x4c +1000240e: 2a00 cmp r2, #0 +10002410: d07d beq.n 1000250e <_etoa+0x4d6> +10002412: 3b01 subs r3, #1 +10002414: 930e str r3, [sp, #56] @ 0x38 +10002416: 9b12 ldr r3, [sp, #72] @ 0x48 +10002418: 459a cmp sl, r3 +1000241a: d905 bls.n 10002428 <_etoa+0x3f0> +1000241c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000241e: 2b00 cmp r3, #0 +10002420: f000 80ae beq.w 10002580 <_etoa+0x548> +10002424: 2302 movs r3, #2 +10002426: 9310 str r3, [sp, #64] @ 0x40 +10002428: 2300 movs r3, #0 +1000242a: 930f str r3, [sp, #60] @ 0x3c +1000242c: e044 b.n 100024b8 <_etoa+0x480> +1000242e: bb22 cbnz r2, 1000247a <_etoa+0x442> +10002430: f1ba 0f05 cmp.w sl, #5 +10002434: d94f bls.n 100024d6 <_etoa+0x49e> +10002436: f006 0302 and.w r3, r6, #2 +1000243a: 2b00 cmp r3, #0 +1000243c: d149 bne.n 100024d2 <_etoa+0x49a> +1000243e: 2305 movs r3, #5 +10002440: 9312 str r3, [sp, #72] @ 0x48 +10002442: f1aa 0305 sub.w r3, sl, #5 +10002446: 930f str r3, [sp, #60] @ 0x3c +10002448: e03a b.n 100024c0 <_etoa+0x488> +1000244a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000244e: 940a str r4, [sp, #40] @ 0x28 +10002450: 930b str r3, [sp, #44] @ 0x2c +10002452: e627 b.n 100020a4 <_etoa+0x6c> +10002454: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002458: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000245c: 4638 mov r0, r7 +1000245e: 962c str r6, [sp, #176] @ 0xb0 +10002460: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002464: 4634 mov r4, r6 +10002466: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000246a: 465a mov r2, fp +1000246c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002470: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002474: 9b09 ldr r3, [sp, #36] @ 0x24 +10002476: 9908 ldr r1, [sp, #32] +10002478: e6bc b.n 100021f4 <_etoa+0x1bc> +1000247a: 2205 movs r2, #5 +1000247c: 9212 str r2, [sp, #72] @ 0x48 +1000247e: e7ad b.n 100023dc <_etoa+0x3a4> +10002480: 2300 movs r3, #0 +10002482: 2202 movs r2, #2 +10002484: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002488: 2204 movs r2, #4 +1000248a: 930c str r3, [sp, #48] @ 0x30 +1000248c: 9212 str r2, [sp, #72] @ 0x48 +1000248e: e62c b.n 100020ea <_etoa+0xb2> +10002490: f04f 0805 mov.w r8, #5 +10002494: e6c2 b.n 1000221c <_etoa+0x1e4> +10002496: f1ba 0f04 cmp.w sl, #4 +1000249a: d91f bls.n 100024dc <_etoa+0x4a4> +1000249c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000249e: 2b00 cmp r3, #0 +100024a0: d178 bne.n 10002594 <_etoa+0x55c> +100024a2: 2304 movs r3, #4 +100024a4: 9312 str r3, [sp, #72] @ 0x48 +100024a6: f1aa 0304 sub.w r3, sl, #4 +100024aa: 930f str r3, [sp, #60] @ 0x3c +100024ac: e004 b.n 100024b8 <_etoa+0x480> +100024ae: 9b12 ldr r3, [sp, #72] @ 0x48 +100024b0: 459a cmp sl, r3 +100024b2: d831 bhi.n 10002518 <_etoa+0x4e0> +100024b4: 9b0e ldr r3, [sp, #56] @ 0x38 +100024b6: 930f str r3, [sp, #60] @ 0x3c +100024b8: 9b0c ldr r3, [sp, #48] @ 0x30 +100024ba: 2b00 cmp r3, #0 +100024bc: f43f ae15 beq.w 100020ea <_etoa+0xb2> +100024c0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100024c4: 4642 mov r2, r8 +100024c6: 464b mov r3, r9 +100024c8: f7ff f91e bl 10001708 <__wrap___aeabi_ddiv> +100024cc: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100024d0: e60b b.n 100020ea <_etoa+0xb2> +100024d2: 2302 movs r3, #2 +100024d4: 9310 str r3, [sp, #64] @ 0x40 +100024d6: 2305 movs r3, #5 +100024d8: 9312 str r3, [sp, #72] @ 0x48 +100024da: e7f1 b.n 100024c0 <_etoa+0x488> +100024dc: 2304 movs r3, #4 +100024de: 9312 str r3, [sp, #72] @ 0x48 +100024e0: e7ea b.n 100024b8 <_etoa+0x480> +100024e2: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100024e6: 46a0 mov r8, r4 +100024e8: 9b0f ldr r3, [sp, #60] @ 0x3c +100024ea: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +100024ee: 9303 str r3, [sp, #12] +100024f0: 9b0e ldr r3, [sp, #56] @ 0x38 +100024f2: 465a mov r2, fp +100024f4: 9302 str r3, [sp, #8] +100024f6: f426 6300 bic.w r3, r6, #2048 @ 0x800 +100024fa: 9304 str r3, [sp, #16] +100024fc: 4638 mov r0, r7 +100024fe: e9cd 8900 strd r8, r9, [sp] +10002502: 9b09 ldr r3, [sp, #36] @ 0x24 +10002504: 9908 ldr r1, [sp, #32] +10002506: f7ff fb37 bl 10001b78 <_ftoa> +1000250a: 4602 mov r2, r0 +1000250c: e608 b.n 10002120 <_etoa+0xe8> +1000250e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002510: 459a cmp sl, r3 +10002512: d844 bhi.n 1000259e <_etoa+0x566> +10002514: 920f str r2, [sp, #60] @ 0x3c +10002516: e7cf b.n 100024b8 <_etoa+0x480> +10002518: 9b10 ldr r3, [sp, #64] @ 0x40 +1000251a: b38b cbz r3, 10002580 <_etoa+0x548> +1000251c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000251e: 930f str r3, [sp, #60] @ 0x3c +10002520: 2302 movs r3, #2 +10002522: 9310 str r3, [sp, #64] @ 0x40 +10002524: e7c8 b.n 100024b8 <_etoa+0x480> +10002526: bf00 nop +10002528: 636f4361 .word 0x636f4361 +1000252c: 3fd287a7 .word 0x3fd287a7 +10002530: 0979a371 .word 0x0979a371 +10002534: 400a934f .word 0x400a934f +10002538: bbb55516 .word 0xbbb55516 +1000253c: 40026bb1 .word 0x40026bb1 +10002540: fefa39ef .word 0xfefa39ef +10002544: 3fe62e42 .word 0x3fe62e42 +10002548: eb1c432d .word 0xeb1c432d +1000254c: 3f1a36e2 .word 0x3f1a36e2 +10002550: 00000000 .word 0x00000000 +10002554: 412e8480 .word 0x412e8480 +10002558: 3ff80000 .word 0x3ff80000 +1000255c: 3fe00000 .word 0x3fe00000 +10002560: 402c0000 .word 0x402c0000 +10002564: 40240000 .word 0x40240000 +10002568: 40180000 .word 0x40180000 +1000256c: 3ff00000 .word 0x3ff00000 +10002570: 509f79fb .word 0x509f79fb +10002574: 3fd34413 .word 0x3fd34413 +10002578: 8b60c8b3 .word 0x8b60c8b3 +1000257c: 3fc68a28 .word 0x3fc68a28 +10002580: 9b12 ldr r3, [sp, #72] @ 0x48 +10002582: ebaa 0303 sub.w r3, sl, r3 +10002586: 930f str r3, [sp, #60] @ 0x3c +10002588: e796 b.n 100024b8 <_etoa+0x480> +1000258a: eba3 0802 sub.w r8, r3, r2 +1000258e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +10002592: e643 b.n 1000221c <_etoa+0x1e4> +10002594: 2304 movs r3, #4 +10002596: 9312 str r3, [sp, #72] @ 0x48 +10002598: 2302 movs r3, #2 +1000259a: 9310 str r3, [sp, #64] @ 0x40 +1000259c: e78c b.n 100024b8 <_etoa+0x480> +1000259e: 9b10 ldr r3, [sp, #64] @ 0x40 +100025a0: 2b00 cmp r3, #0 +100025a2: d0ed beq.n 10002580 <_etoa+0x548> +100025a4: 2302 movs r3, #2 +100025a6: 920f str r2, [sp, #60] @ 0x3c +100025a8: 9310 str r3, [sp, #64] @ 0x40 +100025aa: e785 b.n 100024b8 <_etoa+0x480> + +100025ac <_vsnprintf>: +100025ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100025b0: b09b sub sp, #108 @ 0x6c +100025b2: 9c24 ldr r4, [sp, #144] @ 0x90 +100025b4: 4d95 ldr r5, [pc, #596] @ (1000280c <_vsnprintf+0x260>) +100025b6: 940a str r4, [sp, #40] @ 0x28 +100025b8: 4c95 ldr r4, [pc, #596] @ (10002810 <_vsnprintf+0x264>) +100025ba: f1b1 0a00 subs.w sl, r1, #0 +100025be: bf18 it ne +100025c0: 4683 movne fp, r0 +100025c2: 6025 str r5, [r4, #0] +100025c4: 7818 ldrb r0, [r3, #0] +100025c6: 4c93 ldr r4, [pc, #588] @ (10002814 <_vsnprintf+0x268>) +100025c8: 4691 mov r9, r2 +100025ca: bf08 it eq +100025cc: 46a3 moveq fp, r4 +100025ce: 9309 str r3, [sp, #36] @ 0x24 +100025d0: 2800 cmp r0, #0 +100025d2: f000 8293 beq.w 10002afc <_vsnprintf+0x550> +100025d6: f04f 0800 mov.w r8, #0 +100025da: e00a b.n 100025f2 <_vsnprintf+0x46> +100025dc: 4642 mov r2, r8 +100025de: 464b mov r3, r9 +100025e0: 4651 mov r1, sl +100025e2: f108 0801 add.w r8, r8, #1 +100025e6: 47d8 blx fp +100025e8: 9b09 ldr r3, [sp, #36] @ 0x24 +100025ea: 7818 ldrb r0, [r3, #0] +100025ec: 2800 cmp r0, #0 +100025ee: f000 80ce beq.w 1000278e <_vsnprintf+0x1e2> +100025f2: 9b09 ldr r3, [sp, #36] @ 0x24 +100025f4: 2825 cmp r0, #37 @ 0x25 +100025f6: f103 0301 add.w r3, r3, #1 +100025fa: 9309 str r3, [sp, #36] @ 0x24 +100025fc: d1ee bne.n 100025dc <_vsnprintf+0x30> +100025fe: 461c mov r4, r3 +10002600: 2300 movs r3, #0 +10002602: 4622 mov r2, r4 +10002604: f812 0b01 ldrb.w r0, [r2], #1 +10002608: f1a0 0120 sub.w r1, r0, #32 +1000260c: 2910 cmp r1, #16 +1000260e: d80a bhi.n 10002626 <_vsnprintf+0x7a> +10002610: e8df f001 tbb [pc, r1] +10002614: 3c090940 .word 0x3c090940 +10002618: 09090909 .word 0x09090909 +1000261c: 38090909 .word 0x38090909 +10002620: 09093409 .word 0x09093409 +10002624: 30 .byte 0x30 +10002625: 00 .byte 0x00 +10002626: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000262a: 2909 cmp r1, #9 +1000262c: 9409 str r4, [sp, #36] @ 0x24 +1000262e: f240 808a bls.w 10002746 <_vsnprintf+0x19a> +10002632: 282a cmp r0, #42 @ 0x2a +10002634: f000 80f0 beq.w 10002818 <_vsnprintf+0x26c> +10002638: 2500 movs r5, #0 +1000263a: 282e cmp r0, #46 @ 0x2e +1000263c: f000 8096 beq.w 1000276c <_vsnprintf+0x1c0> +10002640: 2600 movs r6, #0 +10002642: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002646: 2912 cmp r1, #18 +10002648: d82d bhi.n 100026a6 <_vsnprintf+0xfa> +1000264a: e8df f011 tbh [pc, r1, lsl #1] +1000264e: 0149 .short 0x0149 +10002650: 0143002c .word 0x0143002c +10002654: 0138002c .word 0x0138002c +10002658: 002c002c .word 0x002c002c +1000265c: 002c002c .word 0x002c002c +10002660: 002c002c .word 0x002c002c +10002664: 0027002c .word 0x0027002c +10002668: 002c002c .word 0x002c002c +1000266c: 002c002c .word 0x002c002c +10002670: 0027002c .word 0x0027002c +10002674: 4614 mov r4, r2 +10002676: f043 0301 orr.w r3, r3, #1 +1000267a: e7c2 b.n 10002602 <_vsnprintf+0x56> +1000267c: 4614 mov r4, r2 +1000267e: f043 0302 orr.w r3, r3, #2 +10002682: e7be b.n 10002602 <_vsnprintf+0x56> +10002684: 4614 mov r4, r2 +10002686: f043 0304 orr.w r3, r3, #4 +1000268a: e7ba b.n 10002602 <_vsnprintf+0x56> +1000268c: 4614 mov r4, r2 +1000268e: f043 0310 orr.w r3, r3, #16 +10002692: e7b6 b.n 10002602 <_vsnprintf+0x56> +10002694: 4614 mov r4, r2 +10002696: f043 0308 orr.w r3, r3, #8 +1000269a: e7b2 b.n 10002602 <_vsnprintf+0x56> +1000269c: 9909 ldr r1, [sp, #36] @ 0x24 +1000269e: 7848 ldrb r0, [r1, #1] +100026a0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100026a4: 3201 adds r2, #1 +100026a6: 2867 cmp r0, #103 @ 0x67 +100026a8: 9209 str r2, [sp, #36] @ 0x24 +100026aa: d87e bhi.n 100027aa <_vsnprintf+0x1fe> +100026ac: 2824 cmp r0, #36 @ 0x24 +100026ae: f240 80c1 bls.w 10002834 <_vsnprintf+0x288> +100026b2: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100026b6: 2a42 cmp r2, #66 @ 0x42 +100026b8: f200 80bc bhi.w 10002834 <_vsnprintf+0x288> +100026bc: e8df f012 tbh [pc, r2, lsl #1] +100026c0: 00ba0150 .word 0x00ba0150 +100026c4: 00ba00ba .word 0x00ba00ba +100026c8: 00ba00ba .word 0x00ba00ba +100026cc: 00ba00ba .word 0x00ba00ba +100026d0: 00ba00ba .word 0x00ba00ba +100026d4: 00ba00ba .word 0x00ba00ba +100026d8: 00ba00ba .word 0x00ba00ba +100026dc: 00ba00ba .word 0x00ba00ba +100026e0: 00ba00ba .word 0x00ba00ba +100026e4: 00ba00ba .word 0x00ba00ba +100026e8: 00ba00ba .word 0x00ba00ba +100026ec: 00ba00ba .word 0x00ba00ba +100026f0: 00ba00ba .word 0x00ba00ba +100026f4: 00ba00ba .word 0x00ba00ba +100026f8: 00ba00ba .word 0x00ba00ba +100026fc: 00ba00ba .word 0x00ba00ba +10002700: 01370119 .word 0x01370119 +10002704: 00ba0119 .word 0x00ba0119 +10002708: 00ba00ba .word 0x00ba00ba +1000270c: 00ba00ba .word 0x00ba00ba +10002710: 00ba00ba .word 0x00ba00ba +10002714: 00ba00ba .word 0x00ba00ba +10002718: 00ba00ba .word 0x00ba00ba +1000271c: 00ba00ba .word 0x00ba00ba +10002720: 00ba00ba .word 0x00ba00ba +10002724: 01bc00ba .word 0x01bc00ba +10002728: 00ba00ba .word 0x00ba00ba +1000272c: 00ba00ba .word 0x00ba00ba +10002730: 00ba00ba .word 0x00ba00ba +10002734: 00ba00ba .word 0x00ba00ba +10002738: 01bc00ba .word 0x01bc00ba +1000273c: 01bc0158 .word 0x01bc0158 +10002740: 01370119 .word 0x01370119 +10002744: 0119 .short 0x0119 +10002746: 2500 movs r5, #0 +10002748: e000 b.n 1000274c <_vsnprintf+0x1a0> +1000274a: 3201 adds r2, #1 +1000274c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002750: eb00 0545 add.w r5, r0, r5, lsl #1 +10002754: 7810 ldrb r0, [r2, #0] +10002756: 3d30 subs r5, #48 @ 0x30 +10002758: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000275c: 2909 cmp r1, #9 +1000275e: d9f4 bls.n 1000274a <_vsnprintf+0x19e> +10002760: 282e cmp r0, #46 @ 0x2e +10002762: 9209 str r2, [sp, #36] @ 0x24 +10002764: f102 0201 add.w r2, r2, #1 +10002768: f47f af6a bne.w 10002640 <_vsnprintf+0x94> +1000276c: 9909 ldr r1, [sp, #36] @ 0x24 +1000276e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002772: 7848 ldrb r0, [r1, #1] +10002774: 4611 mov r1, r2 +10002776: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000277a: 2e09 cmp r6, #9 +1000277c: f240 8121 bls.w 100029c2 <_vsnprintf+0x416> +10002780: 282a cmp r0, #42 @ 0x2a +10002782: f000 812f beq.w 100029e4 <_vsnprintf+0x438> +10002786: 9209 str r2, [sp, #36] @ 0x24 +10002788: 2600 movs r6, #0 +1000278a: 3201 adds r2, #1 +1000278c: e759 b.n 10002642 <_vsnprintf+0x96> +1000278e: 4644 mov r4, r8 +10002790: 45c1 cmp r9, r8 +10002792: d801 bhi.n 10002798 <_vsnprintf+0x1ec> +10002794: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002798: 464b mov r3, r9 +1000279a: 4642 mov r2, r8 +1000279c: 4651 mov r1, sl +1000279e: 2000 movs r0, #0 +100027a0: 47d8 blx fp +100027a2: 4620 mov r0, r4 +100027a4: b01b add sp, #108 @ 0x6c +100027a6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100027aa: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100027ae: b2d2 uxtb r2, r2 +100027b0: 2a0f cmp r2, #15 +100027b2: d83f bhi.n 10002834 <_vsnprintf+0x288> +100027b4: 2101 movs r1, #1 +100027b6: f249 0741 movw r7, #36929 @ 0x9041 +100027ba: 4091 lsls r1, r2 +100027bc: 4039 ands r1, r7 +100027be: f040 80f3 bne.w 100029a8 <_vsnprintf+0x3fc> +100027c2: 2a0a cmp r2, #10 +100027c4: d03d beq.n 10002842 <_vsnprintf+0x296> +100027c6: 2a07 cmp r2, #7 +100027c8: d134 bne.n 10002834 <_vsnprintf+0x288> +100027ca: 9d0a ldr r5, [sp, #40] @ 0x28 +100027cc: f855 2b04 ldr.w r2, [r5], #4 +100027d0: 2a00 cmp r2, #0 +100027d2: f000 8113 beq.w 100029fc <_vsnprintf+0x450> +100027d6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100027da: ab12 add r3, sp, #72 @ 0x48 +100027dc: 461f mov r7, r3 +100027de: 930b str r3, [sp, #44] @ 0x2c +100027e0: e003 b.n 100027ea <_vsnprintf+0x23e> +100027e2: 2920 cmp r1, #32 +100027e4: f000 8114 beq.w 10002a10 <_vsnprintf+0x464> +100027e8: 461a mov r2, r3 +100027ea: f002 040f and.w r4, r2, #15 +100027ee: 4623 mov r3, r4 +100027f0: 2c09 cmp r4, #9 +100027f2: bf94 ite ls +100027f4: 3330 addls r3, #48 @ 0x30 +100027f6: 3337 addhi r3, #55 @ 0x37 +100027f8: 2a0f cmp r2, #15 +100027fa: f807 3b01 strb.w r3, [r7], #1 +100027fe: f101 0101 add.w r1, r1, #1 +10002802: ea4f 1312 mov.w r3, r2, lsr #4 +10002806: d8ec bhi.n 100027e2 <_vsnprintf+0x236> +10002808: e102 b.n 10002a10 <_vsnprintf+0x464> +1000280a: bf00 nop +1000280c: 100025ad .word 0x100025ad +10002810: 2000080c .word 0x2000080c +10002814: 100018f1 .word 0x100018f1 +10002818: 990a ldr r1, [sp, #40] @ 0x28 +1000281a: 9809 ldr r0, [sp, #36] @ 0x24 +1000281c: f851 5b04 ldr.w r5, [r1], #4 +10002820: 7840 ldrb r0, [r0, #1] +10002822: 2d00 cmp r5, #0 +10002824: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002828: bfbc itt lt +1000282a: f043 0302 orrlt.w r3, r3, #2 +1000282e: 426d neglt r5, r5 +10002830: 3201 adds r2, #1 +10002832: e702 b.n 1000263a <_vsnprintf+0x8e> +10002834: 4642 mov r2, r8 +10002836: 464b mov r3, r9 +10002838: 4651 mov r1, sl +1000283a: f108 0801 add.w r8, r8, #1 +1000283e: 47d8 blx fp +10002840: e6d2 b.n 100025e8 <_vsnprintf+0x3c> +10002842: 990a ldr r1, [sp, #40] @ 0x28 +10002844: 2e00 cmp r6, #0 +10002846: f851 7b04 ldr.w r7, [r1], #4 +1000284a: bf18 it ne +1000284c: 4632 movne r2, r6 +1000284e: 7838 ldrb r0, [r7, #0] +10002850: bf08 it eq +10002852: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002856: 2800 cmp r0, #0 +10002858: f000 837b beq.w 10002f52 <_vsnprintf+0x9a6> +1000285c: 18bc adds r4, r7, r2 +1000285e: 46a4 mov ip, r4 +10002860: 463a mov r2, r7 +10002862: e004 b.n 1000286e <_vsnprintf+0x2c2> +10002864: f812 4f01 ldrb.w r4, [r2, #1]! +10002868: 2c00 cmp r4, #0 +1000286a: f000 813f beq.w 10002aec <_vsnprintf+0x540> +1000286e: 4594 cmp ip, r2 +10002870: d1f8 bne.n 10002864 <_vsnprintf+0x2b8> +10002872: 4664 mov r4, ip +10002874: 1be4 subs r4, r4, r7 +10002876: 055a lsls r2, r3, #21 +10002878: f140 8122 bpl.w 10002ac0 <_vsnprintf+0x514> +1000287c: 42b4 cmp r4, r6 +1000287e: bf28 it cs +10002880: 4634 movcs r4, r6 +10002882: f013 0302 ands.w r3, r3, #2 +10002886: f000 8288 beq.w 10002d9a <_vsnprintf+0x7ee> +1000288a: 2302 movs r3, #2 +1000288c: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002890: 4642 mov r2, r8 +10002892: 461d mov r5, r3 +10002894: 4446 add r6, r8 +10002896: e008 b.n 100028aa <_vsnprintf+0x2fe> +10002898: 464b mov r3, r9 +1000289a: 4651 mov r1, sl +1000289c: 47d8 blx fp +1000289e: f817 0f01 ldrb.w r0, [r7, #1]! +100028a2: f108 0801 add.w r8, r8, #1 +100028a6: b110 cbz r0, 100028ae <_vsnprintf+0x302> +100028a8: 4642 mov r2, r8 +100028aa: 4546 cmp r6, r8 +100028ac: d1f4 bne.n 10002898 <_vsnprintf+0x2ec> +100028ae: 462b mov r3, r5 +100028b0: 990b ldr r1, [sp, #44] @ 0x2c +100028b2: 9d0a ldr r5, [sp, #40] @ 0x28 +100028b4: 2b00 cmp r3, #0 +100028b6: f040 8141 bne.w 10002b3c <_vsnprintf+0x590> +100028ba: 910a str r1, [sp, #40] @ 0x28 +100028bc: e694 b.n 100025e8 <_vsnprintf+0x3c> +100028be: 9909 ldr r1, [sp, #36] @ 0x24 +100028c0: 7848 ldrb r0, [r1, #1] +100028c2: 286c cmp r0, #108 @ 0x6c +100028c4: f47f aeec bne.w 100026a0 <_vsnprintf+0xf4> +100028c8: 460a mov r2, r1 +100028ca: 7888 ldrb r0, [r1, #2] +100028cc: f443 7340 orr.w r3, r3, #768 @ 0x300 +100028d0: 3203 adds r2, #3 +100028d2: e6e8 b.n 100026a6 <_vsnprintf+0xfa> +100028d4: 9909 ldr r1, [sp, #36] @ 0x24 +100028d6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100028da: 7848 ldrb r0, [r1, #1] +100028dc: 3201 adds r2, #1 +100028de: e6e2 b.n 100026a6 <_vsnprintf+0xfa> +100028e0: 9909 ldr r1, [sp, #36] @ 0x24 +100028e2: 7848 ldrb r0, [r1, #1] +100028e4: 2868 cmp r0, #104 @ 0x68 +100028e6: f000 8103 beq.w 10002af0 <_vsnprintf+0x544> +100028ea: f043 0380 orr.w r3, r3, #128 @ 0x80 +100028ee: 3201 adds r2, #1 +100028f0: e6d9 b.n 100026a6 <_vsnprintf+0xfa> +100028f2: 2867 cmp r0, #103 @ 0x67 +100028f4: f000 80d9 beq.w 10002aaa <_vsnprintf+0x4fe> +100028f8: 2847 cmp r0, #71 @ 0x47 +100028fa: f000 80dc beq.w 10002ab6 <_vsnprintf+0x50a> +100028fe: 2845 cmp r0, #69 @ 0x45 +10002900: f000 80db beq.w 10002aba <_vsnprintf+0x50e> +10002904: e9cd 5303 strd r5, r3, [sp, #12] +10002908: 9b0a ldr r3, [sp, #40] @ 0x28 +1000290a: 9602 str r6, [sp, #8] +1000290c: 3307 adds r3, #7 +1000290e: f023 0307 bic.w r3, r3, #7 +10002912: 461c mov r4, r3 +10002914: 4642 mov r2, r8 +10002916: e8f4 6702 ldrd r6, r7, [r4], #8 +1000291a: 464b mov r3, r9 +1000291c: 4651 mov r1, sl +1000291e: 4658 mov r0, fp +10002920: e9cd 6700 strd r6, r7, [sp] +10002924: 940a str r4, [sp, #40] @ 0x28 +10002926: f7ff fb87 bl 10002038 <_etoa> +1000292a: 4680 mov r8, r0 +1000292c: e65c b.n 100025e8 <_vsnprintf+0x3c> +1000292e: 2846 cmp r0, #70 @ 0x46 +10002930: bf08 it eq +10002932: f043 0320 orreq.w r3, r3, #32 +10002936: e9cd 5303 strd r5, r3, [sp, #12] +1000293a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000293c: 9602 str r6, [sp, #8] +1000293e: 3307 adds r3, #7 +10002940: f023 0307 bic.w r3, r3, #7 +10002944: 461c mov r4, r3 +10002946: 4642 mov r2, r8 +10002948: e8f4 6702 ldrd r6, r7, [r4], #8 +1000294c: 464b mov r3, r9 +1000294e: 4651 mov r1, sl +10002950: 4658 mov r0, fp +10002952: e9cd 6700 strd r6, r7, [sp] +10002956: 940a str r4, [sp, #40] @ 0x28 +10002958: f7ff f90e bl 10001b78 <_ftoa> +1000295c: 4680 mov r8, r0 +1000295e: e643 b.n 100025e8 <_vsnprintf+0x3c> +10002960: 4642 mov r2, r8 +10002962: 464b mov r3, r9 +10002964: 4651 mov r1, sl +10002966: 2025 movs r0, #37 @ 0x25 +10002968: f108 0801 add.w r8, r8, #1 +1000296c: 47d8 blx fp +1000296e: e63b b.n 100025e8 <_vsnprintf+0x3c> +10002970: 9a0a ldr r2, [sp, #40] @ 0x28 +10002972: 0799 lsls r1, r3, #30 +10002974: f102 0404 add.w r4, r2, #4 +10002978: f108 0601 add.w r6, r8, #1 +1000297c: f140 80c6 bpl.w 10002b0c <_vsnprintf+0x560> +10002980: 7810 ldrb r0, [r2, #0] +10002982: 464b mov r3, r9 +10002984: 4642 mov r2, r8 +10002986: 4651 mov r1, sl +10002988: 47d8 blx fp +1000298a: 2d01 cmp r5, #1 +1000298c: bf88 it hi +1000298e: 44a8 addhi r8, r5 +10002990: f240 81bd bls.w 10002d0e <_vsnprintf+0x762> +10002994: 4632 mov r2, r6 +10002996: 464b mov r3, r9 +10002998: 4651 mov r1, sl +1000299a: 2020 movs r0, #32 +1000299c: 3601 adds r6, #1 +1000299e: 47d8 blx fp +100029a0: 4546 cmp r6, r8 +100029a2: d1f7 bne.n 10002994 <_vsnprintf+0x3e8> +100029a4: 940a str r4, [sp, #40] @ 0x28 +100029a6: e61f b.n 100025e8 <_vsnprintf+0x3c> +100029a8: 286f cmp r0, #111 @ 0x6f +100029aa: f000 8081 beq.w 10002ab0 <_vsnprintf+0x504> +100029ae: f240 8248 bls.w 10002e42 <_vsnprintf+0x896> +100029b2: 2878 cmp r0, #120 @ 0x78 +100029b4: f000 8190 beq.w 10002cd8 <_vsnprintf+0x72c> +100029b8: 270a movs r7, #10 +100029ba: f023 0310 bic.w r3, r3, #16 +100029be: 46bc mov ip, r7 +100029c0: e041 b.n 10002a46 <_vsnprintf+0x49a> +100029c2: 2600 movs r6, #0 +100029c4: eb06 0686 add.w r6, r6, r6, lsl #2 +100029c8: eb00 0046 add.w r0, r0, r6, lsl #1 +100029cc: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100029d0: f811 0f01 ldrb.w r0, [r1, #1]! +100029d4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100029d8: 2a09 cmp r2, #9 +100029da: d9f3 bls.n 100029c4 <_vsnprintf+0x418> +100029dc: 460a mov r2, r1 +100029de: 9109 str r1, [sp, #36] @ 0x24 +100029e0: 3201 adds r2, #1 +100029e2: e62e b.n 10002642 <_vsnprintf+0x96> +100029e4: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +100029e8: f851 6b04 ldr.w r6, [r1], #4 +100029ec: 7890 ldrb r0, [r2, #2] +100029ee: 3202 adds r2, #2 +100029f0: 9209 str r2, [sp, #36] @ 0x24 +100029f2: 910a str r1, [sp, #40] @ 0x28 +100029f4: 3201 adds r2, #1 +100029f6: ea26 76e6 bic.w r6, r6, r6, asr #31 +100029fa: e622 b.n 10002642 <_vsnprintf+0x96> +100029fc: f023 0010 bic.w r0, r3, #16 +10002a00: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002a04: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002a08: f43f aee7 beq.w 100027da <_vsnprintf+0x22e> +10002a0c: ab12 add r3, sp, #72 @ 0x48 +10002a0e: 930b str r3, [sp, #44] @ 0x2c +10002a10: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a12: 9006 str r0, [sp, #24] +10002a14: 9300 str r3, [sp, #0] +10002a16: 2308 movs r3, #8 +10002a18: 2010 movs r0, #16 +10002a1a: 9305 str r3, [sp, #20] +10002a1c: 2300 movs r3, #0 +10002a1e: 4642 mov r2, r8 +10002a20: e9cd 3002 strd r3, r0, [sp, #8] +10002a24: 9101 str r1, [sp, #4] +10002a26: 464b mov r3, r9 +10002a28: 4651 mov r1, sl +10002a2a: 4658 mov r0, fp +10002a2c: 9604 str r6, [sp, #16] +10002a2e: f7fe ffaf bl 10001990 <_ntoa_format> +10002a32: 950a str r5, [sp, #40] @ 0x28 +10002a34: 4680 mov r8, r0 +10002a36: e5d7 b.n 100025e8 <_vsnprintf+0x3c> +10002a38: 2858 cmp r0, #88 @ 0x58 +10002a3a: d062 beq.n 10002b02 <_vsnprintf+0x556> +10002a3c: 2862 cmp r0, #98 @ 0x62 +10002a3e: f040 808f bne.w 10002b60 <_vsnprintf+0x5b4> +10002a42: 2702 movs r7, #2 +10002a44: 46bc mov ip, r7 +10002a46: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002a4a: f000 80dd beq.w 10002c08 <_vsnprintf+0x65c> +10002a4e: f023 030d bic.w r3, r3, #13 +10002a52: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002a56: f040 8181 bne.w 10002d5c <_vsnprintf+0x7b0> +10002a5a: 990a ldr r1, [sp, #40] @ 0x28 +10002a5c: 1d0f adds r7, r1, #4 +10002a5e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002a62: f040 8237 bne.w 10002ed4 <_vsnprintf+0x928> +10002a66: 065c lsls r4, r3, #25 +10002a68: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a6a: f140 813b bpl.w 10002ce4 <_vsnprintf+0x738> +10002a6e: 7812 ldrb r2, [r2, #0] +10002a70: 2a00 cmp r2, #0 +10002a72: f040 814e bne.w 10002d12 <_vsnprintf+0x766> +10002a76: f023 0310 bic.w r3, r3, #16 +10002a7a: 2800 cmp r0, #0 +10002a7c: f000 8149 beq.w 10002d12 <_vsnprintf+0x766> +10002a80: 4611 mov r1, r2 +10002a82: aa12 add r2, sp, #72 @ 0x48 +10002a84: 920b str r2, [sp, #44] @ 0x2c +10002a86: e9cd 5305 strd r5, r3, [sp, #20] +10002a8a: e9cd c603 strd ip, r6, [sp, #12] +10002a8e: 9101 str r1, [sp, #4] +10002a90: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a92: 4642 mov r2, r8 +10002a94: 9300 str r3, [sp, #0] +10002a96: 2300 movs r3, #0 +10002a98: 4651 mov r1, sl +10002a9a: 9302 str r3, [sp, #8] +10002a9c: 4658 mov r0, fp +10002a9e: 464b mov r3, r9 +10002aa0: f7fe ff76 bl 10001990 <_ntoa_format> +10002aa4: 970a str r7, [sp, #40] @ 0x28 +10002aa6: 4680 mov r8, r0 +10002aa8: e59e b.n 100025e8 <_vsnprintf+0x3c> +10002aaa: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002aae: e729 b.n 10002904 <_vsnprintf+0x358> +10002ab0: 2708 movs r7, #8 +10002ab2: 46bc mov ip, r7 +10002ab4: e7c7 b.n 10002a46 <_vsnprintf+0x49a> +10002ab6: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002aba: f043 0320 orr.w r3, r3, #32 +10002abe: e721 b.n 10002904 <_vsnprintf+0x358> +10002ac0: f013 0302 ands.w r3, r3, #2 +10002ac4: f000 818e beq.w 10002de4 <_vsnprintf+0x838> +10002ac8: 2302 movs r3, #2 +10002aca: 950a str r5, [sp, #40] @ 0x28 +10002acc: 461e mov r6, r3 +10002ace: 460d mov r5, r1 +10002ad0: 4642 mov r2, r8 +10002ad2: 464b mov r3, r9 +10002ad4: 4651 mov r1, sl +10002ad6: 47d8 blx fp +10002ad8: f817 0f01 ldrb.w r0, [r7, #1]! +10002adc: f108 0801 add.w r8, r8, #1 +10002ae0: 2800 cmp r0, #0 +10002ae2: d1f5 bne.n 10002ad0 <_vsnprintf+0x524> +10002ae4: 4629 mov r1, r5 +10002ae6: 4633 mov r3, r6 +10002ae8: 9d0a ldr r5, [sp, #40] @ 0x28 +10002aea: e6e3 b.n 100028b4 <_vsnprintf+0x308> +10002aec: 1bd4 subs r4, r2, r7 +10002aee: e6c2 b.n 10002876 <_vsnprintf+0x2ca> +10002af0: 460a mov r2, r1 +10002af2: 7888 ldrb r0, [r1, #2] +10002af4: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002af8: 3203 adds r2, #3 +10002afa: e5d4 b.n 100026a6 <_vsnprintf+0xfa> +10002afc: 4604 mov r4, r0 +10002afe: 4680 mov r8, r0 +10002b00: e646 b.n 10002790 <_vsnprintf+0x1e4> +10002b02: 2710 movs r7, #16 +10002b04: f043 0320 orr.w r3, r3, #32 +10002b08: 46bc mov ip, r7 +10002b0a: e79c b.n 10002a46 <_vsnprintf+0x49a> +10002b0c: 2d01 cmp r5, #1 +10002b0e: f240 80f8 bls.w 10002d02 <_vsnprintf+0x756> +10002b12: 4646 mov r6, r8 +10002b14: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002b18: 442f add r7, r5 +10002b1a: 4632 mov r2, r6 +10002b1c: 464b mov r3, r9 +10002b1e: 4651 mov r1, sl +10002b20: 2020 movs r0, #32 +10002b22: 3601 adds r6, #1 +10002b24: 47d8 blx fp +10002b26: 42be cmp r6, r7 +10002b28: d1f7 bne.n 10002b1a <_vsnprintf+0x56e> +10002b2a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b2c: 4632 mov r2, r6 +10002b2e: 7818 ldrb r0, [r3, #0] +10002b30: 4651 mov r1, sl +10002b32: 464b mov r3, r9 +10002b34: 47d8 blx fp +10002b36: 44a8 add r8, r5 +10002b38: 940a str r4, [sp, #40] @ 0x28 +10002b3a: e555 b.n 100025e8 <_vsnprintf+0x3c> +10002b3c: 4646 mov r6, r8 +10002b3e: 42a5 cmp r5, r4 +10002b40: f67f aebb bls.w 100028ba <_vsnprintf+0x30e> +10002b44: 44a8 add r8, r5 +10002b46: eba8 0804 sub.w r8, r8, r4 +10002b4a: 460c mov r4, r1 +10002b4c: 4632 mov r2, r6 +10002b4e: 464b mov r3, r9 +10002b50: 4651 mov r1, sl +10002b52: 2020 movs r0, #32 +10002b54: 3601 adds r6, #1 +10002b56: 47d8 blx fp +10002b58: 4546 cmp r6, r8 +10002b5a: d1f7 bne.n 10002b4c <_vsnprintf+0x5a0> +10002b5c: 4621 mov r1, r4 +10002b5e: e6ac b.n 100028ba <_vsnprintf+0x30e> +10002b60: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b64: f000 80bb beq.w 10002cde <_vsnprintf+0x732> +10002b68: f44f 6280 mov.w r2, #1024 @ 0x400 +10002b6c: f023 0c11 bic.w ip, r3, #17 +10002b70: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002b74: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b76: d14a bne.n 10002c0e <_vsnprintf+0x662> +10002b78: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002b7c: f103 0404 add.w r4, r3, #4 +10002b80: f040 8134 bne.w 10002dec <_vsnprintf+0x840> +10002b84: f01c 0f40 tst.w ip, #64 @ 0x40 +10002b88: f040 80a3 bne.w 10002cd2 <_vsnprintf+0x726> +10002b8c: f01c 0f80 tst.w ip, #128 @ 0x80 +10002b90: f000 81d3 beq.w 10002f3a <_vsnprintf+0x98e> +10002b94: f9b3 1000 ldrsh.w r1, [r3] +10002b98: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002b9c: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002ba0: b2bf uxth r7, r7 +10002ba2: 0fcb lsrs r3, r1, #31 +10002ba4: 2900 cmp r1, #0 +10002ba6: f000 8156 beq.w 10002e56 <_vsnprintf+0x8aa> +10002baa: 463a mov r2, r7 +10002bac: a912 add r1, sp, #72 @ 0x48 +10002bae: 460f mov r7, r1 +10002bb0: f8df e3d8 ldr.w lr, [pc, #984] @ 10002f8c <_vsnprintf+0x9e0> +10002bb4: 910b str r1, [sp, #44] @ 0x2c +10002bb6: 930a str r3, [sp, #40] @ 0x28 +10002bb8: 950c str r5, [sp, #48] @ 0x30 +10002bba: e001 b.n 10002bc0 <_vsnprintf+0x614> +10002bbc: 2820 cmp r0, #32 +10002bbe: d00f beq.n 10002be0 <_vsnprintf+0x634> +10002bc0: 4615 mov r5, r2 +10002bc2: fbae 1302 umull r1, r3, lr, r2 +10002bc6: 08db lsrs r3, r3, #3 +10002bc8: eb03 0183 add.w r1, r3, r3, lsl #2 +10002bcc: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002bd0: 3130 adds r1, #48 @ 0x30 +10002bd2: 2d09 cmp r5, #9 +10002bd4: 461a mov r2, r3 +10002bd6: f100 0001 add.w r0, r0, #1 +10002bda: f807 1b01 strb.w r1, [r7], #1 +10002bde: d8ed bhi.n 10002bbc <_vsnprintf+0x610> +10002be0: 9b0a ldr r3, [sp, #40] @ 0x28 +10002be2: 9d0c ldr r5, [sp, #48] @ 0x30 +10002be4: e9cd 5c05 strd r5, ip, [sp, #20] +10002be8: e9cd 0301 strd r0, r3, [sp, #4] +10002bec: 9604 str r6, [sp, #16] +10002bee: 9b0b ldr r3, [sp, #44] @ 0x2c +10002bf0: 4642 mov r2, r8 +10002bf2: 9300 str r3, [sp, #0] +10002bf4: 230a movs r3, #10 +10002bf6: 4651 mov r1, sl +10002bf8: 9303 str r3, [sp, #12] +10002bfa: 4658 mov r0, fp +10002bfc: 464b mov r3, r9 +10002bfe: f7fe fec7 bl 10001990 <_ntoa_format> +10002c02: 940a str r4, [sp, #40] @ 0x28 +10002c04: 4680 mov r8, r0 +10002c06: e4ef b.n 100025e8 <_vsnprintf+0x3c> +10002c08: f023 030c bic.w r3, r3, #12 +10002c0c: e721 b.n 10002a52 <_vsnprintf+0x4a6> +10002c0e: 3307 adds r3, #7 +10002c10: f023 0307 bic.w r3, r3, #7 +10002c14: 4619 mov r1, r3 +10002c16: 4608 mov r0, r1 +10002c18: 685b ldr r3, [r3, #4] +10002c1a: f850 1b08 ldr.w r1, [r0], #8 +10002c1e: 0fdf lsrs r7, r3, #31 +10002c20: 900a str r0, [sp, #40] @ 0x28 +10002c22: ea51 0003 orrs.w r0, r1, r3 +10002c26: d162 bne.n 10002cee <_vsnprintf+0x742> +10002c28: 2a00 cmp r2, #0 +10002c2a: f040 819f bne.w 10002f6c <_vsnprintf+0x9c0> +10002c2e: 4613 mov r3, r2 +10002c30: 4611 mov r1, r2 +10002c32: aa12 add r2, sp, #72 @ 0x48 +10002c34: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002c38: 2000 movs r0, #0 +10002c3a: 4615 mov r5, r2 +10002c3c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002c40: f8df e348 ldr.w lr, [pc, #840] @ 10002f8c <_vsnprintf+0x9e0> +10002c44: 920b str r2, [sp, #44] @ 0x2c +10002c46: e001 b.n 10002c4c <_vsnprintf+0x6a0> +10002c48: 2820 cmp r0, #32 +10002c4a: d02d beq.n 10002ca8 <_vsnprintf+0x6fc> +10002c4c: 185a adds r2, r3, r1 +10002c4e: f142 0200 adc.w r2, r2, #0 +10002c52: fbae 7802 umull r7, r8, lr, r2 +10002c56: f028 0703 bic.w r7, r8, #3 +10002c5a: eb07 0798 add.w r7, r7, r8, lsr #2 +10002c5e: 1bd2 subs r2, r2, r7 +10002c60: 461e mov r6, r3 +10002c62: 1a9b subs r3, r3, r2 +10002c64: f161 0700 sbc.w r7, r1, #0 +10002c68: 460c mov r4, r1 +10002c6a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002c6e: fb01 f103 mul.w r1, r1, r3 +10002c72: fb0e 1107 mla r1, lr, r7, r1 +10002c76: fba3 730e umull r7, r3, r3, lr +10002c7a: 4419 add r1, r3 +10002c7c: 2305 movs r3, #5 +10002c7e: f007 0801 and.w r8, r7, #1 +10002c82: fba8 3803 umull r3, r8, r8, r3 +10002c86: 189b adds r3, r3, r2 +10002c88: 2e0a cmp r6, #10 +10002c8a: f103 0330 add.w r3, r3, #48 @ 0x30 +10002c8e: ea4f 0757 mov.w r7, r7, lsr #1 +10002c92: f174 0400 sbcs.w r4, r4, #0 +10002c96: f805 3b01 strb.w r3, [r5], #1 +10002c9a: f100 0001 add.w r0, r0, #1 +10002c9e: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002ca2: ea4f 0151 mov.w r1, r1, lsr #1 +10002ca6: d2cf bcs.n 10002c48 <_vsnprintf+0x69c> +10002ca8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002cac: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002cb0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002cb2: 4642 mov r2, r8 +10002cb4: 9300 str r3, [sp, #0] +10002cb6: 230a movs r3, #10 +10002cb8: e9cd 5c05 strd r5, ip, [sp, #20] +10002cbc: e9cd 0701 strd r0, r7, [sp, #4] +10002cc0: 9604 str r6, [sp, #16] +10002cc2: 9303 str r3, [sp, #12] +10002cc4: 464b mov r3, r9 +10002cc6: 4651 mov r1, sl +10002cc8: 4658 mov r0, fp +10002cca: f7fe fe61 bl 10001990 <_ntoa_format> +10002cce: 4680 mov r8, r0 +10002cd0: e48a b.n 100025e8 <_vsnprintf+0x3c> +10002cd2: 7819 ldrb r1, [r3, #0] +10002cd4: 460f mov r7, r1 +10002cd6: e764 b.n 10002ba2 <_vsnprintf+0x5f6> +10002cd8: 2710 movs r7, #16 +10002cda: 46bc mov ip, r7 +10002cdc: e6b3 b.n 10002a46 <_vsnprintf+0x49a> +10002cde: f023 0c10 bic.w ip, r3, #16 +10002ce2: e745 b.n 10002b70 <_vsnprintf+0x5c4> +10002ce4: 061c lsls r4, r3, #24 +10002ce6: bf4c ite mi +10002ce8: 8812 ldrhmi r2, [r2, #0] +10002cea: 6812 ldrpl r2, [r2, #0] +10002cec: e6c0 b.n 10002a70 <_vsnprintf+0x4c4> +10002cee: 460a mov r2, r1 +10002cf0: 1e19 subs r1, r3, #0 +10002cf2: db01 blt.n 10002cf8 <_vsnprintf+0x74c> +10002cf4: 4613 mov r3, r2 +10002cf6: e79c b.n 10002c32 <_vsnprintf+0x686> +10002cf8: 4252 negs r2, r2 +10002cfa: 4613 mov r3, r2 +10002cfc: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002d00: e797 b.n 10002c32 <_vsnprintf+0x686> +10002d02: 4613 mov r3, r2 +10002d04: 4651 mov r1, sl +10002d06: 7818 ldrb r0, [r3, #0] +10002d08: 4642 mov r2, r8 +10002d0a: 464b mov r3, r9 +10002d0c: 47d8 blx fp +10002d0e: 46b0 mov r8, r6 +10002d10: e648 b.n 100029a4 <_vsnprintf+0x3f8> +10002d12: f013 0f20 tst.w r3, #32 +10002d16: bf14 ite ne +10002d18: 2041 movne r0, #65 @ 0x41 +10002d1a: 2061 moveq r0, #97 @ 0x61 +10002d1c: ac12 add r4, sp, #72 @ 0x48 +10002d1e: 46a6 mov lr, r4 +10002d20: 940b str r4, [sp, #44] @ 0x2c +10002d22: 930a str r3, [sp, #40] @ 0x28 +10002d24: f1a0 040a sub.w r4, r0, #10 +10002d28: 950c str r5, [sp, #48] @ 0x30 +10002d2a: e002 b.n 10002d32 <_vsnprintf+0x786> +10002d2c: 2920 cmp r1, #32 +10002d2e: d012 beq.n 10002d56 <_vsnprintf+0x7aa> +10002d30: 462a mov r2, r5 +10002d32: fbb2 f5fc udiv r5, r2, ip +10002d36: fb0c 2015 mls r0, ip, r5, r2 +10002d3a: b2c3 uxtb r3, r0 +10002d3c: 2809 cmp r0, #9 +10002d3e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002d42: bf8a itet hi +10002d44: 191b addhi r3, r3, r4 +10002d46: b2c3 uxtbls r3, r0 +10002d48: b2db uxtbhi r3, r3 +10002d4a: 4562 cmp r2, ip +10002d4c: f80e 3b01 strb.w r3, [lr], #1 +10002d50: f101 0101 add.w r1, r1, #1 +10002d54: d2ea bcs.n 10002d2c <_vsnprintf+0x780> +10002d56: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d58: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d5a: e694 b.n 10002a86 <_vsnprintf+0x4da> +10002d5c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002d5e: 3207 adds r2, #7 +10002d60: f022 0207 bic.w r2, r2, #7 +10002d64: 6851 ldr r1, [r2, #4] +10002d66: f852 4b08 ldr.w r4, [r2], #8 +10002d6a: 468e mov lr, r1 +10002d6c: 920a str r2, [sp, #40] @ 0x28 +10002d6e: ea54 0201 orrs.w r2, r4, r1 +10002d72: d176 bne.n 10002e62 <_vsnprintf+0x8b6> +10002d74: f023 0310 bic.w r3, r3, #16 +10002d78: 2800 cmp r0, #0 +10002d7a: d072 beq.n 10002e62 <_vsnprintf+0x8b6> +10002d7c: 2200 movs r2, #0 +10002d7e: 4611 mov r1, r2 +10002d80: aa12 add r2, sp, #72 @ 0x48 +10002d82: 920b str r2, [sp, #44] @ 0x2c +10002d84: e9cd 5305 strd r5, r3, [sp, #20] +10002d88: 9b0b ldr r3, [sp, #44] @ 0x2c +10002d8a: 4642 mov r2, r8 +10002d8c: 9300 str r3, [sp, #0] +10002d8e: 2300 movs r3, #0 +10002d90: e9cd c603 strd ip, r6, [sp, #12] +10002d94: 9101 str r1, [sp, #4] +10002d96: 9302 str r3, [sp, #8] +10002d98: e794 b.n 10002cc4 <_vsnprintf+0x718> +10002d9a: 42a5 cmp r5, r4 +10002d9c: bf98 it ls +10002d9e: 3401 addls r4, #1 +10002da0: f67f ad74 bls.w 1000288c <_vsnprintf+0x2e0> +10002da4: f44f 6380 mov.w r3, #1024 @ 0x400 +10002da8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002dac: eb05 0208 add.w r2, r5, r8 +10002db0: 461f mov r7, r3 +10002db2: 460d mov r5, r1 +10002db4: 1b14 subs r4, r2, r4 +10002db6: 4642 mov r2, r8 +10002db8: 464b mov r3, r9 +10002dba: 4651 mov r1, sl +10002dbc: 2020 movs r0, #32 +10002dbe: f108 0801 add.w r8, r8, #1 +10002dc2: 47d8 blx fp +10002dc4: 45a0 cmp r8, r4 +10002dc6: d1f6 bne.n 10002db6 <_vsnprintf+0x80a> +10002dc8: 463b mov r3, r7 +10002dca: 9f0a ldr r7, [sp, #40] @ 0x28 +10002dcc: 4629 mov r1, r5 +10002dce: 7838 ldrb r0, [r7, #0] +10002dd0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002dd2: 1c6c adds r4, r5, #1 +10002dd4: 2800 cmp r0, #0 +10002dd6: f43f ad70 beq.w 100028ba <_vsnprintf+0x30e> +10002dda: 2b00 cmp r3, #0 +10002ddc: f43f ae75 beq.w 10002aca <_vsnprintf+0x51e> +10002de0: 2300 movs r3, #0 +10002de2: e553 b.n 1000288c <_vsnprintf+0x2e0> +10002de4: 42a5 cmp r5, r4 +10002de6: d8df bhi.n 10002da8 <_vsnprintf+0x7fc> +10002de8: 3401 adds r4, #1 +10002dea: e66e b.n 10002aca <_vsnprintf+0x51e> +10002dec: 6819 ldr r1, [r3, #0] +10002dee: 0fcb lsrs r3, r1, #31 +10002df0: 2900 cmp r1, #0 +10002df2: f000 80a8 beq.w 10002f46 <_vsnprintf+0x99a> +10002df6: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002dfa: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002dfe: a912 add r1, sp, #72 @ 0x48 +10002e00: 4608 mov r0, r1 +10002e02: f8df e188 ldr.w lr, [pc, #392] @ 10002f8c <_vsnprintf+0x9e0> +10002e06: 910b str r1, [sp, #44] @ 0x2c +10002e08: 930a str r3, [sp, #40] @ 0x28 +10002e0a: 950c str r5, [sp, #48] @ 0x30 +10002e0c: e001 b.n 10002e12 <_vsnprintf+0x866> +10002e0e: 2f20 cmp r7, #32 +10002e10: d00f beq.n 10002e32 <_vsnprintf+0x886> +10002e12: 4615 mov r5, r2 +10002e14: fbae 1302 umull r1, r3, lr, r2 +10002e18: 08db lsrs r3, r3, #3 +10002e1a: eb03 0183 add.w r1, r3, r3, lsl #2 +10002e1e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002e22: 3130 adds r1, #48 @ 0x30 +10002e24: 2d09 cmp r5, #9 +10002e26: 461a mov r2, r3 +10002e28: f107 0701 add.w r7, r7, #1 +10002e2c: f800 1b01 strb.w r1, [r0], #1 +10002e30: d8ed bhi.n 10002e0e <_vsnprintf+0x862> +10002e32: 9b0a ldr r3, [sp, #40] @ 0x28 +10002e34: 9d0c ldr r5, [sp, #48] @ 0x30 +10002e36: e9cd 5c05 strd r5, ip, [sp, #20] +10002e3a: e9cd 7301 strd r7, r3, [sp, #4] +10002e3e: 9604 str r6, [sp, #16] +10002e40: e6d5 b.n 10002bee <_vsnprintf+0x642> +10002e42: 2869 cmp r0, #105 @ 0x69 +10002e44: f023 0c10 bic.w ip, r3, #16 +10002e48: f040 808c bne.w 10002f64 <_vsnprintf+0x9b8> +10002e4c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002e50: f43f ae8e beq.w 10002b70 <_vsnprintf+0x5c4> +10002e54: e688 b.n 10002b68 <_vsnprintf+0x5bc> +10002e56: 2a00 cmp r2, #0 +10002e58: f43f aea8 beq.w 10002bac <_vsnprintf+0x600> +10002e5c: aa12 add r2, sp, #72 @ 0x48 +10002e5e: 920b str r2, [sp, #44] @ 0x2c +10002e60: e6c0 b.n 10002be4 <_vsnprintf+0x638> +10002e62: f013 0f20 tst.w r3, #32 +10002e66: bf14 ite ne +10002e68: 2241 movne r2, #65 @ 0x41 +10002e6a: 2261 moveq r2, #97 @ 0x61 +10002e6c: 2000 movs r0, #0 +10002e6e: a912 add r1, sp, #72 @ 0x48 +10002e70: 3a0a subs r2, #10 +10002e72: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002e76: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002e7a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002e7e: 4606 mov r6, r0 +10002e80: 4688 mov r8, r1 +10002e82: 4675 mov r5, lr +10002e84: 4693 mov fp, r2 +10002e86: 910b str r1, [sp, #44] @ 0x2c +10002e88: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002e8c: e003 b.n 10002e96 <_vsnprintf+0x8ea> +10002e8e: 2e20 cmp r6, #32 +10002e90: d017 beq.n 10002ec2 <_vsnprintf+0x916> +10002e92: 4604 mov r4, r0 +10002e94: 460d mov r5, r1 +10002e96: 4629 mov r1, r5 +10002e98: 463a mov r2, r7 +10002e9a: 2300 movs r3, #0 +10002e9c: 4620 mov r0, r4 +10002e9e: f000 fc7f bl 100037a0 <____aeabi_uldivmod_veneer> +10002ea2: b2d2 uxtb r2, r2 +10002ea4: 2a09 cmp r2, #9 +10002ea6: f102 0330 add.w r3, r2, #48 @ 0x30 +10002eaa: bf88 it hi +10002eac: eb02 030b addhi.w r3, r2, fp +10002eb0: 42bc cmp r4, r7 +10002eb2: b2db uxtb r3, r3 +10002eb4: f175 0500 sbcs.w r5, r5, #0 +10002eb8: f808 3b01 strb.w r3, [r8], #1 +10002ebc: f106 0601 add.w r6, r6, #1 +10002ec0: d2e5 bcs.n 10002e8e <_vsnprintf+0x8e2> +10002ec2: 4631 mov r1, r6 +10002ec4: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002ec8: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002ecc: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002ed0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002ed2: e757 b.n 10002d84 <_vsnprintf+0x7d8> +10002ed4: 990a ldr r1, [sp, #40] @ 0x28 +10002ed6: 6809 ldr r1, [r1, #0] +10002ed8: b951 cbnz r1, 10002ef0 <_vsnprintf+0x944> +10002eda: f023 0310 bic.w r3, r3, #16 +10002ede: b138 cbz r0, 10002ef0 <_vsnprintf+0x944> +10002ee0: a912 add r1, sp, #72 @ 0x48 +10002ee2: 910b str r1, [sp, #44] @ 0x2c +10002ee4: e9cd 5305 strd r5, r3, [sp, #20] +10002ee8: e9cd c603 strd ip, r6, [sp, #12] +10002eec: 9201 str r2, [sp, #4] +10002eee: e5cf b.n 10002a90 <_vsnprintf+0x4e4> +10002ef0: f013 0f20 tst.w r3, #32 +10002ef4: bf14 ite ne +10002ef6: 2041 movne r0, #65 @ 0x41 +10002ef8: 2061 moveq r0, #97 @ 0x61 +10002efa: ac12 add r4, sp, #72 @ 0x48 +10002efc: 46a6 mov lr, r4 +10002efe: 940b str r4, [sp, #44] @ 0x2c +10002f00: 930a str r3, [sp, #40] @ 0x28 +10002f02: f1a0 040a sub.w r4, r0, #10 +10002f06: 950c str r5, [sp, #48] @ 0x30 +10002f08: e002 b.n 10002f10 <_vsnprintf+0x964> +10002f0a: 2a20 cmp r2, #32 +10002f0c: d012 beq.n 10002f34 <_vsnprintf+0x988> +10002f0e: 4629 mov r1, r5 +10002f10: fbb1 f5fc udiv r5, r1, ip +10002f14: fb0c 1015 mls r0, ip, r5, r1 +10002f18: b2c3 uxtb r3, r0 +10002f1a: 2809 cmp r0, #9 +10002f1c: f103 0030 add.w r0, r3, #48 @ 0x30 +10002f20: bf8a itet hi +10002f22: 191b addhi r3, r3, r4 +10002f24: b2c3 uxtbls r3, r0 +10002f26: b2db uxtbhi r3, r3 +10002f28: 4561 cmp r1, ip +10002f2a: f80e 3b01 strb.w r3, [lr], #1 +10002f2e: f102 0201 add.w r2, r2, #1 +10002f32: d2ea bcs.n 10002f0a <_vsnprintf+0x95e> +10002f34: 9b0a ldr r3, [sp, #40] @ 0x28 +10002f36: 9d0c ldr r5, [sp, #48] @ 0x30 +10002f38: e7d4 b.n 10002ee4 <_vsnprintf+0x938> +10002f3a: 6819 ldr r1, [r3, #0] +10002f3c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002f40: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002f44: e62d b.n 10002ba2 <_vsnprintf+0x5f6> +10002f46: 2a00 cmp r2, #0 +10002f48: f43f af59 beq.w 10002dfe <_vsnprintf+0x852> +10002f4c: aa12 add r2, sp, #72 @ 0x48 +10002f4e: 920b str r2, [sp, #44] @ 0x2c +10002f50: e771 b.n 10002e36 <_vsnprintf+0x88a> +10002f52: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002f56: d00d beq.n 10002f74 <_vsnprintf+0x9c8> +10002f58: f013 0402 ands.w r4, r3, #2 +10002f5c: d012 beq.n 10002f84 <_vsnprintf+0x9d8> +10002f5e: 4604 mov r4, r0 +10002f60: 4646 mov r6, r8 +10002f62: e5ec b.n 10002b3e <_vsnprintf+0x592> +10002f64: 270a movs r7, #10 +10002f66: 4663 mov r3, ip +10002f68: 46bc mov ip, r7 +10002f6a: e56c b.n 10002a46 <_vsnprintf+0x49a> +10002f6c: ab12 add r3, sp, #72 @ 0x48 +10002f6e: 2000 movs r0, #0 +10002f70: 930b str r3, [sp, #44] @ 0x2c +10002f72: e69d b.n 10002cb0 <_vsnprintf+0x704> +10002f74: f013 0302 ands.w r3, r3, #2 +10002f78: f47f ade0 bne.w 10002b3c <_vsnprintf+0x590> +10002f7c: 2d00 cmp r5, #0 +10002f7e: f47f af13 bne.w 10002da8 <_vsnprintf+0x7fc> +10002f82: e49a b.n 100028ba <_vsnprintf+0x30e> +10002f84: 2d00 cmp r5, #0 +10002f86: f47f af0d bne.w 10002da4 <_vsnprintf+0x7f8> +10002f8a: e496 b.n 100028ba <_vsnprintf+0x30e> +10002f8c: cccccccd .word 0xcccccccd + +10002f90 : +10002f90: b570 push {r4, r5, r6, lr} +10002f92: 4694 mov ip, r2 +10002f94: 461e mov r6, r3 +10002f96: 4605 mov r5, r0 +10002f98: 460c mov r4, r1 +10002f9a: b084 sub sp, #16 +10002f9c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002fa0: 4663 mov r3, ip +10002fa2: a902 add r1, sp, #8 +10002fa4: 9600 str r6, [sp, #0] +10002fa6: 4803 ldr r0, [pc, #12] @ (10002fb4 ) +10002fa8: e9cd 5402 strd r5, r4, [sp, #8] +10002fac: f7ff fafe bl 100025ac <_vsnprintf> +10002fb0: b004 add sp, #16 +10002fb2: bd70 pop {r4, r5, r6, pc} +10002fb4: 10001b6d .word 0x10001b6d + +10002fb8 : +10002fb8: b510 push {r4, lr} +10002fba: 4b09 ldr r3, [pc, #36] @ (10002fe0 ) +10002fbc: b084 sub sp, #16 +10002fbe: 681c ldr r4, [r3, #0] +10002fc0: b14c cbz r4, 10002fd6 +10002fc2: 4603 mov r3, r0 +10002fc4: 9100 str r1, [sp, #0] +10002fc6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002fca: a903 add r1, sp, #12 +10002fcc: 4805 ldr r0, [pc, #20] @ (10002fe4 ) +10002fce: 47a0 blx r4 +10002fd0: 2001 movs r0, #1 +10002fd2: b004 add sp, #16 +10002fd4: bd10 pop {r4, pc} +10002fd6: f000 f9b5 bl 10003344 <__wrap_puts> +10002fda: 4620 mov r0, r4 +10002fdc: b004 add sp, #16 +10002fde: bd10 pop {r4, pc} +10002fe0: 2000080c .word 0x2000080c +10002fe4: 10001b65 .word 0x10001b65 + +10002fe8 <_exit>: +10002fe8: be00 bkpt 0x0000 +10002fea: e7fd b.n 10002fe8 <_exit> + +10002fec : +10002fec: b508 push {r3, lr} +10002fee: f7ff fffb bl 10002fe8 <_exit> +10002ff2: bf00 nop + +10002ff4 : +10002ff4: b538 push {r3, r4, r5, lr} +10002ff6: 4c06 ldr r4, [pc, #24] @ (10003010 ) +10002ff8: 4d06 ldr r5, [pc, #24] @ (10003014 ) +10002ffa: f7fe fa07 bl 1000140c +10002ffe: 42ac cmp r4, r5 +10003000: d204 bcs.n 1000300c +10003002: f854 3b04 ldr.w r3, [r4], #4 +10003006: 4798 blx r3 +10003008: 42ac cmp r4, r5 +1000300a: d3fa bcc.n 10003002 +1000300c: bd38 pop {r3, r4, r5, pc} +1000300e: bf00 nop +10003010: 100037f8 .word 0x100037f8 +10003014: 100037fc .word 0x100037fc + +10003018 : +10003018: 6803 ldr r3, [r0, #0] +1000301a: 4608 mov r0, r1 +1000301c: 4611 mov r1, r2 +1000301e: 4718 bx r3 + +10003020 : +10003020: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003024: 4615 mov r5, r2 +10003026: 7d42 ldrb r2, [r0, #21] +10003028: 4607 mov r7, r0 +1000302a: 4688 mov r8, r1 +1000302c: 2a00 cmp r2, #0 +1000302e: d046 beq.n 100030be +10003030: 2d00 cmp r5, #0 +10003032: dd1d ble.n 10003070 +10003034: 780b ldrb r3, [r1, #0] +10003036: 2b0a cmp r3, #10 +10003038: d023 beq.n 10003082 +1000303a: 2d01 cmp r5, #1 +1000303c: f04f 0c00 mov.w ip, #0 +10003040: d018 beq.n 10003074 +10003042: 4646 mov r6, r8 +10003044: 2401 movs r4, #1 +10003046: f816 2f01 ldrb.w r2, [r6, #1]! +1000304a: 4621 mov r1, r4 +1000304c: 2a0a cmp r2, #10 +1000304e: f104 0401 add.w r4, r4, #1 +10003052: d022 beq.n 1000309a +10003054: 42a5 cmp r5, r4 +10003056: d1f6 bne.n 10003046 +10003058: 4565 cmp r5, ip +1000305a: dc0b bgt.n 10003074 +1000305c: eb08 0305 add.w r3, r8, r5 +10003060: f813 3c01 ldrb.w r3, [r3, #-1] +10003064: f1a3 030d sub.w r3, r3, #13 +10003068: fab3 f383 clz r3, r3 +1000306c: 095b lsrs r3, r3, #5 +1000306e: 753b strb r3, [r7, #20] +10003070: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003074: 683b ldr r3, [r7, #0] +10003076: eba5 010c sub.w r1, r5, ip +1000307a: eb08 000c add.w r0, r8, ip +1000307e: 4798 blx r3 +10003080: e7ec b.n 1000305c +10003082: 7d03 ldrb r3, [r0, #20] +10003084: 2b00 cmp r3, #0 +10003086: d1d8 bne.n 1000303a +10003088: 6803 ldr r3, [r0, #0] +1000308a: 2102 movs r1, #2 +1000308c: 480f ldr r0, [pc, #60] @ (100030cc ) +1000308e: 4798 blx r3 +10003090: 2d01 cmp r5, #1 +10003092: d0e3 beq.n 1000305c +10003094: f04f 0c01 mov.w ip, #1 +10003098: e7d3 b.n 10003042 +1000309a: f816 3c01 ldrb.w r3, [r6, #-1] +1000309e: 2b0d cmp r3, #13 +100030a0: d0d8 beq.n 10003054 +100030a2: 458c cmp ip, r1 +100030a4: eb08 000c add.w r0, r8, ip +100030a8: eba1 010c sub.w r1, r1, ip +100030ac: da01 bge.n 100030b2 +100030ae: 683b ldr r3, [r7, #0] +100030b0: 4798 blx r3 +100030b2: 2102 movs r1, #2 +100030b4: 4805 ldr r0, [pc, #20] @ (100030cc ) +100030b6: 683b ldr r3, [r7, #0] +100030b8: 4798 blx r3 +100030ba: 46a4 mov ip, r4 +100030bc: e7ca b.n 10003054 +100030be: 4629 mov r1, r5 +100030c0: 4640 mov r0, r8 +100030c2: 683b ldr r3, [r7, #0] +100030c4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100030c8: 4718 bx r3 +100030ca: bf00 nop +100030cc: 100039b8 .word 0x100039b8 + +100030d0 : +100030d0: 680b ldr r3, [r1, #0] +100030d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100030d6: 2b80 cmp r3, #128 @ 0x80 +100030d8: 460d mov r5, r1 +100030da: 4606 mov r6, r0 +100030dc: d005 beq.n 100030ea +100030de: 1c5a adds r2, r3, #1 +100030e0: 442b add r3, r5 +100030e2: 602a str r2, [r5, #0] +100030e4: 711e strb r6, [r3, #4] +100030e6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030ea: 4b0f ldr r3, [pc, #60] @ (10003128 ) +100030ec: 681c ldr r4, [r3, #0] +100030ee: b1a4 cbz r4, 1000311a +100030f0: 4f0e ldr r7, [pc, #56] @ (1000312c ) +100030f2: f101 0804 add.w r8, r1, #4 +100030f6: e001 b.n 100030fc +100030f8: 6924 ldr r4, [r4, #16] +100030fa: b174 cbz r4, 1000311a +100030fc: 6823 ldr r3, [r4, #0] +100030fe: 2b00 cmp r3, #0 +10003100: d0fa beq.n 100030f8 +10003102: 683b ldr r3, [r7, #0] +10003104: b10b cbz r3, 1000310a +10003106: 42a3 cmp r3, r4 +10003108: d1f6 bne.n 100030f8 +1000310a: 4620 mov r0, r4 +1000310c: 4641 mov r1, r8 +1000310e: 682a ldr r2, [r5, #0] +10003110: f7ff ff86 bl 10003020 +10003114: 6924 ldr r4, [r4, #16] +10003116: 2c00 cmp r4, #0 +10003118: d1f0 bne.n 100030fc +1000311a: 2300 movs r3, #0 +1000311c: 2201 movs r2, #1 +1000311e: 442b add r3, r5 +10003120: 602a str r2, [r5, #0] +10003122: 711e strb r6, [r3, #4] +10003124: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003128: 20000804 .word 0x20000804 +1000312c: 20000808 .word 0x20000808 + +10003130 : +10003130: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10003134: b082 sub sp, #8 +10003136: 460d mov r5, r1 +10003138: 4691 mov r9, r2 +1000313a: 461c mov r4, r3 +1000313c: 4606 mov r6, r0 +1000313e: f7fd ff95 bl 1000106c +10003142: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003146: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1000314a: 4a2e ldr r2, [pc, #184] @ (10003204 ) +1000314c: 1882 adds r2, r0, r2 +1000314e: f141 0300 adc.w r3, r1, #0 +10003152: 4594 cmp ip, r2 +10003154: eb77 0103 sbcs.w r1, r7, r3 +10003158: bf3c itt cc +1000315a: 4662 movcc r2, ip +1000315c: 463b movcc r3, r7 +1000315e: 482a ldr r0, [pc, #168] @ (10003208 ) +10003160: f000 fb26 bl 100037b0 <__mutex_try_enter_block_until_veneer> +10003164: 1c6b adds r3, r5, #1 +10003166: 4680 mov r8, r0 +10003168: d040 beq.n 100031ec +1000316a: b30c cbz r4, 100031b0 +1000316c: 4f27 ldr r7, [pc, #156] @ (1000320c ) +1000316e: 4b28 ldr r3, [pc, #160] @ (10003210 ) +10003170: 681c ldr r4, [r3, #0] +10003172: b1b4 cbz r4, 100031a2 +10003174: f1b9 0f00 cmp.w r9, #0 +10003178: d11c bne.n 100031b4 +1000317a: f8df 909c ldr.w r9, [pc, #156] @ 10003218 +1000317e: e001 b.n 10003184 +10003180: 6924 ldr r4, [r4, #16] +10003182: b174 cbz r4, 100031a2 +10003184: 6823 ldr r3, [r4, #0] +10003186: 2b00 cmp r3, #0 +10003188: d0fa beq.n 10003180 +1000318a: f8d9 3000 ldr.w r3, [r9] +1000318e: b10b cbz r3, 10003194 +10003190: 429c cmp r4, r3 +10003192: d1f5 bne.n 10003180 +10003194: 4620 mov r0, r4 +10003196: 462a mov r2, r5 +10003198: 4631 mov r1, r6 +1000319a: 47b8 blx r7 +1000319c: 6924 ldr r4, [r4, #16] +1000319e: 2c00 cmp r4, #0 +100031a0: d1f0 bne.n 10003184 +100031a2: f1b8 0f00 cmp.w r8, #0 +100031a6: d126 bne.n 100031f6 +100031a8: 4628 mov r0, r5 +100031aa: b002 add sp, #8 +100031ac: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100031b0: 4f18 ldr r7, [pc, #96] @ (10003214 ) +100031b2: e7dc b.n 1000316e +100031b4: f04f 0a0a mov.w sl, #10 +100031b8: f8df 905c ldr.w r9, [pc, #92] @ 10003218 +100031bc: e002 b.n 100031c4 +100031be: 6924 ldr r4, [r4, #16] +100031c0: 2c00 cmp r4, #0 +100031c2: d0ee beq.n 100031a2 +100031c4: 6823 ldr r3, [r4, #0] +100031c6: 2b00 cmp r3, #0 +100031c8: d0f9 beq.n 100031be +100031ca: f8d9 3000 ldr.w r3, [r9] +100031ce: b10b cbz r3, 100031d4 +100031d0: 42a3 cmp r3, r4 +100031d2: d1f4 bne.n 100031be +100031d4: 462a mov r2, r5 +100031d6: 4631 mov r1, r6 +100031d8: 4620 mov r0, r4 +100031da: 47b8 blx r7 +100031dc: 2201 movs r2, #1 +100031de: 4620 mov r0, r4 +100031e0: f10d 0107 add.w r1, sp, #7 +100031e4: f88d a007 strb.w sl, [sp, #7] +100031e8: 47b8 blx r7 +100031ea: e7e8 b.n 100031be +100031ec: 4630 mov r0, r6 +100031ee: f000 faa7 bl 10003740 +100031f2: 4605 mov r5, r0 +100031f4: e7b9 b.n 1000316a +100031f6: 4804 ldr r0, [pc, #16] @ (10003208 ) +100031f8: f000 fad6 bl 100037a8 <__mutex_exit_veneer> +100031fc: 4628 mov r0, r5 +100031fe: b002 add sp, #8 +10003200: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003204: 000f4240 .word 0x000f4240 +10003208: 20000624 .word 0x20000624 +1000320c: 10003021 .word 0x10003021 +10003210: 20000804 .word 0x20000804 +10003214: 10003019 .word 0x10003019 +10003218: 20000808 .word 0x20000808 + +1000321c : +1000321c: 4a08 ldr r2, [pc, #32] @ (10003240 ) +1000321e: 6813 ldr r3, [r2, #0] +10003220: b923 cbnz r3, 1000322c +10003222: e00a b.n 1000323a +10003224: f103 0210 add.w r2, r3, #16 +10003228: 691b ldr r3, [r3, #16] +1000322a: b133 cbz r3, 1000323a +1000322c: 4283 cmp r3, r0 +1000322e: d1f9 bne.n 10003224 +10003230: b929 cbnz r1, 1000323e +10003232: 6918 ldr r0, [r3, #16] +10003234: 6010 str r0, [r2, #0] +10003236: 6119 str r1, [r3, #16] +10003238: 4770 bx lr +1000323a: b101 cbz r1, 1000323e +1000323c: 6010 str r0, [r2, #0] +1000323e: 4770 bx lr +10003240: 20000804 .word 0x20000804 + +10003244 : +10003244: b508 push {r3, lr} +10003246: f000 f9db bl 10003600 +1000324a: 2001 movs r0, #1 +1000324c: bd08 pop {r3, pc} +1000324e: bf00 nop + +10003250 <__wrap_getchar>: +10003250: b5f0 push {r4, r5, r6, r7, lr} +10003252: 4b17 ldr r3, [pc, #92] @ (100032b0 <__wrap_getchar+0x60>) +10003254: b085 sub sp, #20 +10003256: 681a ldr r2, [r3, #0] +10003258: 4e16 ldr r6, [pc, #88] @ (100032b4 <__wrap_getchar+0x64>) +1000325a: 685f ldr r7, [r3, #4] +1000325c: 4d16 ldr r5, [pc, #88] @ (100032b8 <__wrap_getchar+0x68>) +1000325e: 9201 str r2, [sp, #4] +10003260: 6834 ldr r4, [r6, #0] +10003262: b914 cbnz r4, 1000326a <__wrap_getchar+0x1a> +10003264: e011 b.n 1000328a <__wrap_getchar+0x3a> +10003266: 6924 ldr r4, [r4, #16] +10003268: b17c cbz r4, 1000328a <__wrap_getchar+0x3a> +1000326a: 682b ldr r3, [r5, #0] +1000326c: b10b cbz r3, 10003272 <__wrap_getchar+0x22> +1000326e: 429c cmp r4, r3 +10003270: d1f9 bne.n 10003266 <__wrap_getchar+0x16> +10003272: 68a3 ldr r3, [r4, #8] +10003274: 2b00 cmp r3, #0 +10003276: d0f6 beq.n 10003266 <__wrap_getchar+0x16> +10003278: 2101 movs r1, #1 +1000327a: a803 add r0, sp, #12 +1000327c: 4798 blx r3 +1000327e: 2800 cmp r0, #0 +10003280: ddf1 ble.n 10003266 <__wrap_getchar+0x16> +10003282: f89d 000c ldrb.w r0, [sp, #12] +10003286: b005 add sp, #20 +10003288: bdf0 pop {r4, r5, r6, r7, pc} +1000328a: 4b0c ldr r3, [pc, #48] @ (100032bc <__wrap_getchar+0x6c>) +1000328c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000328e: 4297 cmp r7, r2 +10003290: d809 bhi.n 100032a6 <__wrap_getchar+0x56> +10003292: 6a9b ldr r3, [r3, #40] @ 0x28 +10003294: 9901 ldr r1, [sp, #4] +10003296: 428b cmp r3, r1 +10003298: d303 bcc.n 100032a2 <__wrap_getchar+0x52> +1000329a: f06f 0001 mvn.w r0, #1 +1000329e: b005 add sp, #20 +100032a0: bdf0 pop {r4, r5, r6, r7, pc} +100032a2: 4297 cmp r7, r2 +100032a4: d1f9 bne.n 1000329a <__wrap_getchar+0x4a> +100032a6: 2001 movs r0, #1 +100032a8: 2100 movs r1, #0 +100032aa: f7fd fee9 bl 10001080 +100032ae: e7d7 b.n 10003260 <__wrap_getchar+0x10> +100032b0: 10003900 .word 0x10003900 +100032b4: 20000804 .word 0x20000804 +100032b8: 20000808 .word 0x20000808 +100032bc: 400b0000 .word 0x400b0000 + +100032c0 <__wrap_putchar>: +100032c0: b5f0 push {r4, r5, r6, r7, lr} +100032c2: b083 sub sp, #12 +100032c4: 4606 mov r6, r0 +100032c6: f88d 0007 strb.w r0, [sp, #7] +100032ca: f7fd fecf bl 1000106c +100032ce: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100032d2: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100032d6: 4a17 ldr r2, [pc, #92] @ (10003334 <__wrap_putchar+0x74>) +100032d8: 1882 adds r2, r0, r2 +100032da: f141 0300 adc.w r3, r1, #0 +100032de: 4295 cmp r5, r2 +100032e0: eb74 0103 sbcs.w r1, r4, r3 +100032e4: bf3c itt cc +100032e6: 4623 movcc r3, r4 +100032e8: 462a movcc r2, r5 +100032ea: 4813 ldr r0, [pc, #76] @ (10003338 <__wrap_putchar+0x78>) +100032ec: f000 fa60 bl 100037b0 <__mutex_try_enter_block_until_veneer> +100032f0: 4b12 ldr r3, [pc, #72] @ (1000333c <__wrap_putchar+0x7c>) +100032f2: 4607 mov r7, r0 +100032f4: 681c ldr r4, [r3, #0] +100032f6: b19c cbz r4, 10003320 <__wrap_putchar+0x60> +100032f8: 4d11 ldr r5, [pc, #68] @ (10003340 <__wrap_putchar+0x80>) +100032fa: e001 b.n 10003300 <__wrap_putchar+0x40> +100032fc: 6924 ldr r4, [r4, #16] +100032fe: b17c cbz r4, 10003320 <__wrap_putchar+0x60> +10003300: 6823 ldr r3, [r4, #0] +10003302: 2b00 cmp r3, #0 +10003304: d0fa beq.n 100032fc <__wrap_putchar+0x3c> +10003306: 682b ldr r3, [r5, #0] +10003308: b10b cbz r3, 1000330e <__wrap_putchar+0x4e> +1000330a: 429c cmp r4, r3 +1000330c: d1f6 bne.n 100032fc <__wrap_putchar+0x3c> +1000330e: 4620 mov r0, r4 +10003310: 2201 movs r2, #1 +10003312: f10d 0107 add.w r1, sp, #7 +10003316: f7ff fe83 bl 10003020 +1000331a: 6924 ldr r4, [r4, #16] +1000331c: 2c00 cmp r4, #0 +1000331e: d1ef bne.n 10003300 <__wrap_putchar+0x40> +10003320: b917 cbnz r7, 10003328 <__wrap_putchar+0x68> +10003322: 4630 mov r0, r6 +10003324: b003 add sp, #12 +10003326: bdf0 pop {r4, r5, r6, r7, pc} +10003328: 4803 ldr r0, [pc, #12] @ (10003338 <__wrap_putchar+0x78>) +1000332a: f000 fa3d bl 100037a8 <__mutex_exit_veneer> +1000332e: 4630 mov r0, r6 +10003330: b003 add sp, #12 +10003332: bdf0 pop {r4, r5, r6, r7, pc} +10003334: 000f4240 .word 0x000f4240 +10003338: 20000624 .word 0x20000624 +1000333c: 20000804 .word 0x20000804 +10003340: 20000808 .word 0x20000808 + +10003344 <__wrap_puts>: +10003344: b538 push {r3, r4, r5, lr} +10003346: 4604 mov r4, r0 +10003348: f000 f9fa bl 10003740 +1000334c: 2301 movs r3, #1 +1000334e: 4605 mov r5, r0 +10003350: 461a mov r2, r3 +10003352: 4620 mov r0, r4 +10003354: 4629 mov r1, r5 +10003356: f7ff feeb bl 10003130 +1000335a: 4b08 ldr r3, [pc, #32] @ (1000337c <__wrap_puts+0x38>) +1000335c: 681c ldr r4, [r3, #0] +1000335e: b12c cbz r4, 1000336c <__wrap_puts+0x28> +10003360: 6863 ldr r3, [r4, #4] +10003362: b12b cbz r3, 10003370 <__wrap_puts+0x2c> +10003364: 4798 blx r3 +10003366: 6924 ldr r4, [r4, #16] +10003368: 2c00 cmp r4, #0 +1000336a: d1f9 bne.n 10003360 <__wrap_puts+0x1c> +1000336c: 4628 mov r0, r5 +1000336e: bd38 pop {r3, r4, r5, pc} +10003370: 6924 ldr r4, [r4, #16] +10003372: 2c00 cmp r4, #0 +10003374: d1f4 bne.n 10003360 <__wrap_puts+0x1c> +10003376: 4628 mov r0, r5 +10003378: bd38 pop {r3, r4, r5, pc} +1000337a: bf00 nop +1000337c: 20000804 .word 0x20000804 + +10003380 <__wrap_vprintf>: +10003380: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003384: b0a2 sub sp, #136 @ 0x88 +10003386: 4604 mov r4, r0 +10003388: 460d mov r5, r1 +1000338a: f7fd fe6f bl 1000106c +1000338e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10003392: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003396: 4a26 ldr r2, [pc, #152] @ (10003430 <__wrap_vprintf+0xb0>) +10003398: f8df 80a4 ldr.w r8, [pc, #164] @ 10003440 <__wrap_vprintf+0xc0> +1000339c: 1882 adds r2, r0, r2 +1000339e: f141 0300 adc.w r3, r1, #0 +100033a2: 4297 cmp r7, r2 +100033a4: eb76 0103 sbcs.w r1, r6, r3 +100033a8: bf3c itt cc +100033aa: 463a movcc r2, r7 +100033ac: 4633 movcc r3, r6 +100033ae: 4821 ldr r0, [pc, #132] @ (10003434 <__wrap_vprintf+0xb4>) +100033b0: f000 f9fe bl 100037b0 <__mutex_try_enter_block_until_veneer> +100033b4: 2700 movs r7, #0 +100033b6: 462b mov r3, r5 +100033b8: 4622 mov r2, r4 +100033ba: 4606 mov r6, r0 +100033bc: a901 add r1, sp, #4 +100033be: 481e ldr r0, [pc, #120] @ (10003438 <__wrap_vprintf+0xb8>) +100033c0: 9701 str r7, [sp, #4] +100033c2: f7ff fde5 bl 10002f90 +100033c6: 9b01 ldr r3, [sp, #4] +100033c8: 4605 mov r5, r0 +100033ca: f8d8 4000 ldr.w r4, [r8] +100033ce: b1c3 cbz r3, 10003402 <__wrap_vprintf+0x82> +100033d0: 2c00 cmp r4, #0 +100033d2: d02b beq.n 1000342c <__wrap_vprintf+0xac> +100033d4: 4f19 ldr r7, [pc, #100] @ (1000343c <__wrap_vprintf+0xbc>) +100033d6: e001 b.n 100033dc <__wrap_vprintf+0x5c> +100033d8: 6924 ldr r4, [r4, #16] +100033da: b174 cbz r4, 100033fa <__wrap_vprintf+0x7a> +100033dc: 6823 ldr r3, [r4, #0] +100033de: 2b00 cmp r3, #0 +100033e0: d0fa beq.n 100033d8 <__wrap_vprintf+0x58> +100033e2: 683b ldr r3, [r7, #0] +100033e4: b10b cbz r3, 100033ea <__wrap_vprintf+0x6a> +100033e6: 42a3 cmp r3, r4 +100033e8: d1f6 bne.n 100033d8 <__wrap_vprintf+0x58> +100033ea: 4620 mov r0, r4 +100033ec: 9a01 ldr r2, [sp, #4] +100033ee: a902 add r1, sp, #8 +100033f0: f7ff fe16 bl 10003020 +100033f4: 6924 ldr r4, [r4, #16] +100033f6: 2c00 cmp r4, #0 +100033f8: d1f0 bne.n 100033dc <__wrap_vprintf+0x5c> +100033fa: 2300 movs r3, #0 +100033fc: f8d8 4000 ldr.w r4, [r8] +10003400: 9301 str r3, [sp, #4] +10003402: b12c cbz r4, 10003410 <__wrap_vprintf+0x90> +10003404: 6863 ldr r3, [r4, #4] +10003406: b143 cbz r3, 1000341a <__wrap_vprintf+0x9a> +10003408: 4798 blx r3 +1000340a: 6924 ldr r4, [r4, #16] +1000340c: 2c00 cmp r4, #0 +1000340e: d1f9 bne.n 10003404 <__wrap_vprintf+0x84> +10003410: b92e cbnz r6, 1000341e <__wrap_vprintf+0x9e> +10003412: 4628 mov r0, r5 +10003414: b022 add sp, #136 @ 0x88 +10003416: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000341a: 6924 ldr r4, [r4, #16] +1000341c: e7f1 b.n 10003402 <__wrap_vprintf+0x82> +1000341e: 4805 ldr r0, [pc, #20] @ (10003434 <__wrap_vprintf+0xb4>) +10003420: f000 f9c2 bl 100037a8 <__mutex_exit_veneer> +10003424: 4628 mov r0, r5 +10003426: b022 add sp, #136 @ 0x88 +10003428: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000342c: 9401 str r4, [sp, #4] +1000342e: e7ef b.n 10003410 <__wrap_vprintf+0x90> +10003430: 000f4240 .word 0x000f4240 +10003434: 20000624 .word 0x20000624 +10003438: 100030d1 .word 0x100030d1 +1000343c: 20000808 .word 0x20000808 +10003440: 20000804 .word 0x20000804 + +10003444 <__wrap_printf>: +10003444: b40f push {r0, r1, r2, r3} +10003446: b500 push {lr} +10003448: b083 sub sp, #12 +1000344a: a904 add r1, sp, #16 +1000344c: f851 0b04 ldr.w r0, [r1], #4 +10003450: 9101 str r1, [sp, #4] +10003452: f7ff ff95 bl 10003380 <__wrap_vprintf> +10003456: b003 add sp, #12 +10003458: f85d eb04 ldr.w lr, [sp], #4 +1000345c: b004 add sp, #16 +1000345e: 4770 bx lr + +10003460 : +10003460: f1b1 0c00 subs.w ip, r1, #0 +10003464: dd1d ble.n 100034a2 +10003466: 4a0f ldr r2, [pc, #60] @ (100034a4 ) +10003468: 4b0f ldr r3, [pc, #60] @ (100034a8 ) +1000346a: 6812 ldr r2, [r2, #0] +1000346c: b530 push {r4, r5, lr} +1000346e: 1ad3 subs r3, r2, r3 +10003470: fab3 f383 clz r3, r3 +10003474: 240d movs r4, #13 +10003476: 4d0d ldr r5, [pc, #52] @ (100034ac ) +10003478: 095b lsrs r3, r3, #5 +1000347a: 1e41 subs r1, r0, #1 +1000347c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003480: 448c add ip, r1 +10003482: f811 0f01 ldrb.w r0, [r1, #1]! +10003486: 4586 cmp lr, r0 +10003488: d006 beq.n 10003498 +1000348a: 6993 ldr r3, [r2, #24] +1000348c: 069b lsls r3, r3, #26 +1000348e: d4fc bmi.n 1000348a +10003490: 4561 cmp r1, ip +10003492: 6010 str r0, [r2, #0] +10003494: d1f5 bne.n 10003482 +10003496: bd30 pop {r4, r5, pc} +10003498: 6993 ldr r3, [r2, #24] +1000349a: 069d lsls r5, r3, #26 +1000349c: d4fc bmi.n 10003498 +1000349e: 6014 str r4, [r2, #0] +100034a0: e7f3 b.n 1000348a +100034a2: 4770 bx lr +100034a4: 20000858 .word 0x20000858 +100034a8: 40078000 .word 0x40078000 +100034ac: 20000854 .word 0x20000854 + +100034b0 : +100034b0: 4b22 ldr r3, [pc, #136] @ (1000353c ) +100034b2: f1b1 0c00 subs.w ip, r1, #0 +100034b6: b410 push {r4} +100034b8: 681c ldr r4, [r3, #0] +100034ba: dd2e ble.n 1000351a +100034bc: 4603 mov r3, r0 +100034be: 2000 movs r0, #0 +100034c0: 4a1f ldr r2, [pc, #124] @ (10003540 ) +100034c2: 1e59 subs r1, r3, #1 +100034c4: 6812 ldr r2, [r2, #0] +100034c6: 6993 ldr r3, [r2, #24] +100034c8: 06db lsls r3, r3, #27 +100034ca: d417 bmi.n 100034fc +100034cc: 3001 adds r0, #1 +100034ce: 6993 ldr r3, [r2, #24] +100034d0: 06db lsls r3, r3, #27 +100034d2: d4fc bmi.n 100034ce +100034d4: 6813 ldr r3, [r2, #0] +100034d6: 4584 cmp ip, r0 +100034d8: f801 3f01 strb.w r3, [r1, #1]! +100034dc: d1f3 bne.n 100034c6 +100034de: b14c cbz r4, 100034f4 +100034e0: 2150 movs r1, #80 @ 0x50 +100034e2: 4613 mov r3, r2 +100034e4: 6391 str r1, [r2, #56] @ 0x38 +100034e6: f853 2f34 ldr.w r2, [r3, #52]! +100034ea: f002 0238 and.w r2, r2, #56 @ 0x38 +100034ee: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100034f2: 601a str r2, [r3, #0] +100034f4: 4660 mov r0, ip +100034f6: f85d 4b04 ldr.w r4, [sp], #4 +100034fa: 4770 bx lr +100034fc: b14c cbz r4, 10003512 +100034fe: 2150 movs r1, #80 @ 0x50 +10003500: 4613 mov r3, r2 +10003502: 6391 str r1, [r2, #56] @ 0x38 +10003504: f853 2f34 ldr.w r2, [r3, #52]! +10003508: f002 0238 and.w r2, r2, #56 @ 0x38 +1000350c: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003510: 601a str r2, [r3, #0] +10003512: b178 cbz r0, 10003534 +10003514: f85d 4b04 ldr.w r4, [sp], #4 +10003518: 4770 bx lr +1000351a: b15c cbz r4, 10003534 +1000351c: 4b08 ldr r3, [pc, #32] @ (10003540 ) +1000351e: 2150 movs r1, #80 @ 0x50 +10003520: 681a ldr r2, [r3, #0] +10003522: 4613 mov r3, r2 +10003524: 6391 str r1, [r2, #56] @ 0x38 +10003526: f853 2f34 ldr.w r2, [r3, #52]! +1000352a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000352e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003532: 601a str r2, [r3, #0] +10003534: f06f 0002 mvn.w r0, #2 +10003538: e7dd b.n 100034f6 +1000353a: bf00 nop +1000353c: 200007d0 .word 0x200007d0 +10003540: 20000858 .word 0x20000858 + +10003544 : +10003544: 4b05 ldr r3, [pc, #20] @ (1000355c ) +10003546: 681b ldr r3, [r3, #0] +10003548: b133 cbz r3, 10003558 +1000354a: 2100 movs r1, #0 +1000354c: 4a04 ldr r2, [pc, #16] @ (10003560 ) +1000354e: 4805 ldr r0, [pc, #20] @ (10003564 ) +10003550: 6812 ldr r2, [r2, #0] +10003552: 6800 ldr r0, [r0, #0] +10003554: 6391 str r1, [r2, #56] @ 0x38 +10003556: 4718 bx r3 +10003558: 4770 bx lr +1000355a: bf00 nop +1000355c: 200007d0 .word 0x200007d0 +10003560: 20000858 .word 0x20000858 +10003564: 200007d4 .word 0x200007d4 + +10003568 : +10003568: 4b02 ldr r3, [pc, #8] @ (10003574 ) +1000356a: 681a ldr r2, [r3, #0] +1000356c: 6993 ldr r3, [r2, #24] +1000356e: 071b lsls r3, r3, #28 +10003570: d4fc bmi.n 1000356c +10003572: 4770 bx lr +10003574: 20000858 .word 0x20000858 + +10003578 : +10003578: b5f8 push {r3, r4, r5, r6, r7, lr} +1000357a: 4f1c ldr r7, [pc, #112] @ (100035ec ) +1000357c: 4d1c ldr r5, [pc, #112] @ (100035f0 ) +1000357e: 683a ldr r2, [r7, #0] +10003580: 4e1c ldr r6, [pc, #112] @ (100035f4 ) +10003582: 42aa cmp r2, r5 +10003584: bf14 ite ne +10003586: 2521 movne r5, #33 @ 0x21 +10003588: 2522 moveq r5, #34 @ 0x22 +1000358a: 4604 mov r4, r0 +1000358c: f8d6 c000 ldr.w ip, [r6] +10003590: b118 cbz r0, 1000359a +10003592: f1bc 0f00 cmp.w ip, #0 +10003596: d010 beq.n 100035ba +10003598: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000359a: f1bc 0f00 cmp.w ip, #0 +1000359e: d0fb beq.n 10003598 +100035a0: 4601 mov r1, r0 +100035a2: 6390 str r0, [r2, #56] @ 0x38 +100035a4: 4628 mov r0, r5 +100035a6: f7fc ffe9 bl 1000057c +100035aa: 4628 mov r0, r5 +100035ac: 4912 ldr r1, [pc, #72] @ (100035f8 ) +100035ae: f7fd f82b bl 10000608 +100035b2: 4b12 ldr r3, [pc, #72] @ (100035fc ) +100035b4: 6034 str r4, [r6, #0] +100035b6: 601c str r4, [r3, #0] +100035b8: bdf8 pop {r3, r4, r5, r6, r7, pc} +100035ba: 460b mov r3, r1 +100035bc: 4a0f ldr r2, [pc, #60] @ (100035fc ) +100035be: 490e ldr r1, [pc, #56] @ (100035f8 ) +100035c0: 6030 str r0, [r6, #0] +100035c2: 4628 mov r0, r5 +100035c4: 6013 str r3, [r2, #0] +100035c6: f7fc ffef bl 100005a8 +100035ca: 2101 movs r1, #1 +100035cc: 4628 mov r0, r5 +100035ce: f7fc ffd5 bl 1000057c +100035d2: 683a ldr r2, [r7, #0] +100035d4: 2150 movs r1, #80 @ 0x50 +100035d6: 4613 mov r3, r2 +100035d8: 6391 str r1, [r2, #56] @ 0x38 +100035da: f853 2f34 ldr.w r2, [r3, #52]! +100035de: f002 0238 and.w r2, r2, #56 @ 0x38 +100035e2: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035e6: 601a str r2, [r3, #0] +100035e8: bdf8 pop {r3, r4, r5, r6, r7, pc} +100035ea: bf00 nop +100035ec: 20000858 .word 0x20000858 +100035f0: 40078000 .word 0x40078000 +100035f4: 200007d0 .word 0x200007d0 +100035f8: 10003545 .word 0x10003545 +100035fc: 200007d4 .word 0x200007d4 + +10003600 : +10003600: b510 push {r4, lr} +10003602: 490e ldr r1, [pc, #56] @ (1000363c ) +10003604: 4c0e ldr r4, [pc, #56] @ (10003640 ) +10003606: 480f ldr r0, [pc, #60] @ (10003644 ) +10003608: 4a0f ldr r2, [pc, #60] @ (10003648 ) +1000360a: 4b10 ldr r3, [pc, #64] @ (1000364c ) +1000360c: 7800 ldrb r0, [r0, #0] +1000360e: 6021 str r1, [r4, #0] +10003610: 2000 movs r0, #0 +10003612: 2102 movs r1, #2 +10003614: 7812 ldrb r2, [r2, #0] +10003616: 781b ldrb r3, [r3, #0] +10003618: f7fc ff0e bl 10000438 +1000361c: 2102 movs r1, #2 +1000361e: 2001 movs r0, #1 +10003620: f7fc ff0a bl 10000438 +10003624: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003628: 6820 ldr r0, [r4, #0] +1000362a: f7fd fd69 bl 10001100 +1000362e: e8bd 4010 ldmia.w sp!, {r4, lr} +10003632: 2101 movs r1, #1 +10003634: 4806 ldr r0, [pc, #24] @ (10003650 ) +10003636: f7ff bdf1 b.w 1000321c +1000363a: bf00 nop +1000363c: 40070000 .word 0x40070000 +10003640: 20000858 .word 0x20000858 +10003644: 10003a08 .word 0x10003a08 +10003648: 10003a04 .word 0x10003a04 +1000364c: 10003a00 .word 0x10003a00 +10003650: 2000060c .word 0x2000060c + +10003654 : +10003654: 4684 mov ip, r0 +10003656: ea41 0300 orr.w r3, r1, r0 +1000365a: f013 0303 ands.w r3, r3, #3 +1000365e: d149 bne.n 100036f4 +10003660: 3a40 subs r2, #64 @ 0x40 +10003662: d323 bcc.n 100036ac +10003664: 680b ldr r3, [r1, #0] +10003666: 6003 str r3, [r0, #0] +10003668: 684b ldr r3, [r1, #4] +1000366a: 6043 str r3, [r0, #4] +1000366c: 688b ldr r3, [r1, #8] +1000366e: 6083 str r3, [r0, #8] +10003670: 68cb ldr r3, [r1, #12] +10003672: 60c3 str r3, [r0, #12] +10003674: 690b ldr r3, [r1, #16] +10003676: 6103 str r3, [r0, #16] +10003678: 694b ldr r3, [r1, #20] +1000367a: 6143 str r3, [r0, #20] +1000367c: 698b ldr r3, [r1, #24] +1000367e: 6183 str r3, [r0, #24] +10003680: 69cb ldr r3, [r1, #28] +10003682: 61c3 str r3, [r0, #28] +10003684: 6a0b ldr r3, [r1, #32] +10003686: 6203 str r3, [r0, #32] +10003688: 6a4b ldr r3, [r1, #36] @ 0x24 +1000368a: 6243 str r3, [r0, #36] @ 0x24 +1000368c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000368e: 6283 str r3, [r0, #40] @ 0x28 +10003690: 6acb ldr r3, [r1, #44] @ 0x2c +10003692: 62c3 str r3, [r0, #44] @ 0x2c +10003694: 6b0b ldr r3, [r1, #48] @ 0x30 +10003696: 6303 str r3, [r0, #48] @ 0x30 +10003698: 6b4b ldr r3, [r1, #52] @ 0x34 +1000369a: 6343 str r3, [r0, #52] @ 0x34 +1000369c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000369e: 6383 str r3, [r0, #56] @ 0x38 +100036a0: 6bcb ldr r3, [r1, #60] @ 0x3c +100036a2: 63c3 str r3, [r0, #60] @ 0x3c +100036a4: 3040 adds r0, #64 @ 0x40 +100036a6: 3140 adds r1, #64 @ 0x40 +100036a8: 3a40 subs r2, #64 @ 0x40 +100036aa: d2db bcs.n 10003664 +100036ac: 3230 adds r2, #48 @ 0x30 +100036ae: d30b bcc.n 100036c8 +100036b0: 680b ldr r3, [r1, #0] +100036b2: 6003 str r3, [r0, #0] +100036b4: 684b ldr r3, [r1, #4] +100036b6: 6043 str r3, [r0, #4] +100036b8: 688b ldr r3, [r1, #8] +100036ba: 6083 str r3, [r0, #8] +100036bc: 68cb ldr r3, [r1, #12] +100036be: 60c3 str r3, [r0, #12] +100036c0: 3010 adds r0, #16 +100036c2: 3110 adds r1, #16 +100036c4: 3a10 subs r2, #16 +100036c6: d2f3 bcs.n 100036b0 +100036c8: 320c adds r2, #12 +100036ca: d305 bcc.n 100036d8 +100036cc: f851 3b04 ldr.w r3, [r1], #4 +100036d0: f840 3b04 str.w r3, [r0], #4 +100036d4: 3a04 subs r2, #4 +100036d6: d2f9 bcs.n 100036cc +100036d8: 3204 adds r2, #4 +100036da: d008 beq.n 100036ee +100036dc: 07d2 lsls r2, r2, #31 +100036de: bf1c itt ne +100036e0: f811 3b01 ldrbne.w r3, [r1], #1 +100036e4: f800 3b01 strbne.w r3, [r0], #1 +100036e8: d301 bcc.n 100036ee +100036ea: 880b ldrh r3, [r1, #0] +100036ec: 8003 strh r3, [r0, #0] +100036ee: 4660 mov r0, ip +100036f0: 4770 bx lr +100036f2: bf00 nop +100036f4: 2a08 cmp r2, #8 +100036f6: d313 bcc.n 10003720 +100036f8: 078b lsls r3, r1, #30 +100036fa: d0b1 beq.n 10003660 +100036fc: f010 0303 ands.w r3, r0, #3 +10003700: d0ae beq.n 10003660 +10003702: f1c3 0304 rsb r3, r3, #4 +10003706: 1ad2 subs r2, r2, r3 +10003708: 07db lsls r3, r3, #31 +1000370a: bf1c itt ne +1000370c: f811 3b01 ldrbne.w r3, [r1], #1 +10003710: f800 3b01 strbne.w r3, [r0], #1 +10003714: d3a4 bcc.n 10003660 +10003716: f831 3b02 ldrh.w r3, [r1], #2 +1000371a: f820 3b02 strh.w r3, [r0], #2 +1000371e: e79f b.n 10003660 +10003720: 3a04 subs r2, #4 +10003722: d3d9 bcc.n 100036d8 +10003724: 3a01 subs r2, #1 +10003726: f811 3b01 ldrb.w r3, [r1], #1 +1000372a: f800 3b01 strb.w r3, [r0], #1 +1000372e: d2f9 bcs.n 10003724 +10003730: 780b ldrb r3, [r1, #0] +10003732: 7003 strb r3, [r0, #0] +10003734: 784b ldrb r3, [r1, #1] +10003736: 7043 strb r3, [r0, #1] +10003738: 788b ldrb r3, [r1, #2] +1000373a: 7083 strb r3, [r0, #2] +1000373c: 4660 mov r0, ip +1000373e: 4770 bx lr + +10003740 : +10003740: f020 0103 bic.w r1, r0, #3 +10003744: f010 0003 ands.w r0, r0, #3 +10003748: f1c0 0000 rsb r0, r0, #0 +1000374c: f851 3b04 ldr.w r3, [r1], #4 +10003750: f100 0c04 add.w ip, r0, #4 +10003754: ea4f 0ccc mov.w ip, ip, lsl #3 +10003758: f06f 0200 mvn.w r2, #0 +1000375c: bf1c itt ne +1000375e: fa22 f20c lsrne.w r2, r2, ip +10003762: 4313 orrne r3, r2 +10003764: f04f 0c01 mov.w ip, #1 +10003768: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000376c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003770: eba3 020c sub.w r2, r3, ip +10003774: ea22 0203 bic.w r2, r2, r3 +10003778: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000377c: bf04 itt eq +1000377e: f851 3b04 ldreq.w r3, [r1], #4 +10003782: 3004 addeq r0, #4 +10003784: d0f4 beq.n 10003770 +10003786: f1c2 0100 rsb r1, r2, #0 +1000378a: ea02 0201 and.w r2, r2, r1 +1000378e: fab2 f282 clz r2, r2 +10003792: f1c2 021f rsb r2, r2, #31 +10003796: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000379a: 4770 bx lr + +1000379c <_fini>: +1000379c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000379e: bf00 nop + +100037a0 <____aeabi_uldivmod_veneer>: +100037a0: f85f f000 ldr.w pc, [pc] @ 100037a4 <____aeabi_uldivmod_veneer+0x4> +100037a4: 20000221 .word 0x20000221 + +100037a8 <__mutex_exit_veneer>: +100037a8: f85f f000 ldr.w pc, [pc] @ 100037ac <__mutex_exit_veneer+0x4> +100037ac: 200001e5 .word 0x200001e5 + +100037b0 <__mutex_try_enter_block_until_veneer>: +100037b0: f85f f000 ldr.w pc, [pc] @ 100037b4 <__mutex_try_enter_block_until_veneer+0x4> +100037b4: 2000017d .word 0x2000017d + +100037b8 <__pre_init_runtime_init_bootrom_reset>: +100037b8: 100014b9 .... + +100037bc <__pre_init_runtime_init_early_resets>: +100037bc: 1000142d -... + +100037c0 <__pre_init_runtime_init_usb_power_down>: +100037c0: 10001461 a... + +100037c4 <__pre_init_runtime_init_clocks>: +100037c4: 1000154d M... + +100037c8 <__pre_init_runtime_init_post_clock_resets>: +100037c8: 10001499 .... + +100037cc <__pre_init_runtime_init_boot_locks_reset>: +100037cc: 100013b1 .... + +100037d0 <__pre_init_runtime_init_spin_locks_reset>: +100037d0: 100014e1 .... + +100037d4 <__pre_init_runtime_init_bootrom_locking_enable>: +100037d4: 1000139d .... + +100037d8 <__pre_init_runtime_init_mutex>: +100037d8: 100008c5 .... + +100037dc <__pre_init_runtime_init_install_ram_vector_table>: +100037dc: 100014e5 .... + +100037e0 <__pre_init_runtime_init_default_alarm_pool>: +100037e0: 10000c41 A... + +100037e4 <__pre_init_first_per_core_initializer>: +100037e4: 100013fd .... + +100037e8 <__pre_init_runtime_init_per_core_bootrom_reset>: +100037e8: 100014cd .... + +100037ec <__pre_init_runtime_init_per_core_enable_coprocessors>: +100037ec: 1000147d }... + +100037f0 <__pre_init_spinlock_set_extexclall>: +100037f0: 10000515 .... + +100037f4 <__pre_init_runtime_init_per_core_irq_priorities>: +100037f4: 1000053d =... + +100037f8 <__frame_dummy_init_array_entry>: +100037f8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 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b/WEEK10/0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.uf2 differ diff --git a/WEEK10/0x0020_dynamic-conditionals/build/pico_flash_region.ld b/WEEK10/0x0020_dynamic-conditionals/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK10/0x0020_dynamic-conditionals/pico_sdk_import.cmake b/WEEK10/0x0020_dynamic-conditionals/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK10/0x0020_dynamic-conditionals/servo.c b/WEEK10/0x0020_dynamic-conditionals/servo.c new file mode 100644 index 0000000..ee48f0d --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/servo.c @@ -0,0 +1,89 @@ +/** + * @file servo.c + * @brief Implementation of a simple SG90 servo driver using PWM (50Hz) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "servo.h" +#include "pico/stdlib.h" +#include "hardware/pwm.h" +#include "hardware/clocks.h" + +// Default servo pulse range (SG90 typical) +static const uint16_t SERVO_DEFAULT_MIN_US = 1000; +static const uint16_t SERVO_DEFAULT_MAX_US = 2000; + +// internal state +static uint8_t servo_pin = 0; +static uint servo_slice = 0; +static uint servo_chan = 0; +static uint32_t servo_wrap = 20000 - 1; // wrap to map microseconds for 50Hz +static float servo_hz = 50.0f; + +// Convert microsecond pulse to PWM level based on wrap and frequency +static uint32_t pulse_us_to_level(uint32_t pulse_us) { + const float period_us = 1000000.0f / servo_hz; // 20000us + float counts_per_us = (servo_wrap + 1) / period_us; + return (uint32_t)(pulse_us * counts_per_us + 0.5f); +} + +void servo_init(uint8_t pin) { + servo_pin = pin; + + // Configure GPIO for PWM + gpio_set_function(servo_pin, GPIO_FUNC_PWM); + servo_slice = pwm_gpio_to_slice_num(servo_pin); + servo_chan = pwm_gpio_to_channel(servo_pin); + + pwm_config config = pwm_get_default_config(); + + // Calculate clock divider to achieve 50 Hz with our chosen wrap + const uint32_t sys_clock_hz = clock_get_hz(clk_sys); + float clock_div = (float)sys_clock_hz / (servo_hz * (servo_wrap + 1)); + + pwm_config_set_clkdiv(&config, clock_div); + pwm_config_set_wrap(&config, servo_wrap); + pwm_init(servo_slice, &config, true); +} + +void servo_set_pulse_us(uint16_t pulse_us) { + if (servo_pin == 0) return; // not initialized + // clamp to defaults + if (pulse_us < SERVO_DEFAULT_MIN_US) pulse_us = SERVO_DEFAULT_MIN_US; + if (pulse_us > SERVO_DEFAULT_MAX_US) pulse_us = SERVO_DEFAULT_MAX_US; + uint32_t level = pulse_us_to_level(pulse_us); + pwm_set_chan_level(servo_slice, servo_chan, level); +} + +void servo_set_angle(float degrees) { + if (degrees < 0.0f) degrees = 0.0f; + if (degrees > 180.0f) degrees = 180.0f; + // linear map 0..180 -> min_us..max_us + float ratio = degrees / 180.0f; + uint16_t pulse = (uint16_t)(SERVO_DEFAULT_MIN_US + ratio * (SERVO_DEFAULT_MAX_US - SERVO_DEFAULT_MIN_US) + 0.5f); + servo_set_pulse_us(pulse); +} +# \ No newline at end of file diff --git a/WEEK10/0x0020_dynamic-conditionals/servo.h b/WEEK10/0x0020_dynamic-conditionals/servo.h new file mode 100644 index 0000000..878d029 --- /dev/null +++ b/WEEK10/0x0020_dynamic-conditionals/servo.h @@ -0,0 +1,62 @@ +/** + * @file servo.h + * @brief Header for SG90 servo driver (PWM) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef SERVO_H +#define SERVO_H + +#include +#include + +/** + * @brief Initialize servo driver on a given GPIO pin + * + * Configures PWM for a 50 Hz servo (SG90). Call once before using other API. + * + * @param pin GPIO pin number to use for servo PWM + */ +void servo_init(uint8_t pin); + +/** + * @brief Set servo pulse width in microseconds (typical 1000-2000) + * + * @param pulse_us Pulse width in microseconds + */ +void servo_set_pulse_us(uint16_t pulse_us); + +/** + * @brief Set servo angle in degrees (0 to 180) + * + * Maps 0..180 degrees to the configured pulse range (default 1000..2000 us). + * Values outside [0,180] will be clamped. + * + * @param degrees Angle in degrees + */ +void servo_set_angle(float degrees); + +#endif // SERVO_H diff --git a/WEEK10/WEEK10-BN.md b/WEEK10/WEEK10-BN.md new file mode 100644 index 0000000..3e6c4ae --- /dev/null +++ b/WEEK10/WEEK10-BN.md @@ -0,0 +1,1881 @@ +# Week 10-BN: Binary Ninja Personal — Hack Static & Dynamic Conditionals with the SG90 Servo (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build both lesson projects with `Release` and get an `.elf` and a raw `.bin` for each +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load each raw `.bin` into Binary Ninja at `0x10000000` +- **Break at `main`** on live silicon, even though `main` can move between programs +- **Hack each running target live** from Binary Ninja's Registers widget and Python console +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map +- **Patch** the bytes that control behavior — strings, an IEEE-754 float, an immediate delay, and two `beq` targets — export, convert, and flash +- Understand how a **static** conditional is optimized away while a **dynamic** conditional must keep its `cmp`/`beq`/`bne` branches + +--- + +## How This Guide Works + +Each project builds two files: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table and DWARF | Ground truth for every function address and signature | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the current `Release` builds. `Release` folds the `static` helpers (`print_if_else`, `print_switch`, `sweep_servo`, `eval_if_else`, `process_servo_command`) into `main` and keeps the code layout stable. If you build `Debug`, the SDK function addresses move and the helpers stay separate, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**, twice — once per project: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the behavior change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Prints | Also does | The hack | +| ------- | ------ | --------- | -------- | +| `0x001d_static-conditionals` | `1`, then `one`, forever | sweeps the SG90 servo 0° → 180° | angle `180` → `30`, delay `500` → `100`, string `1` → `2`, `one` → `fun` | +| `0x0020_dynamic-conditionals` | `1`+`one` or `2`+`two` from the keyboard | sweeps the servo on `1` / `2` | keys `1`/`2` → `x`/`y`, angle `180` → `30`, skip the prints to go stealth | + +> **Two conditionals, two fates.** In Project 1 the `choice` value is hard-coded (`int choice = 1;`), so the compiler proves the condition at compile time and **deletes the `cmp` and the dead branches** — that is a *static* conditional. In Project 2 `choice = getchar()`, so the value is only known at run time and the compiler must emit the `cmp`/`beq`/`bne` chain — that is a *dynamic* conditional. You will see both in the disassembly. + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3 and was verified against the current `.elf` files with `arm-none-eabi-nm` and `arm-none-eabi-objdump`. Confirm against your own `.elf` with the command in Step 4. + +> **The SVD file lives in `WEEK04`.** If you want the RP2350 peripheral register map for the PWM/UART side of the lab, it is `Embedded-Hacking/WEEK04/rp2350.svd` — it is **not** in `WEEK10`. + +### Background: PWM and the SG90 in one paragraph + +A servo wants a **50 Hz** signal (a 20 ms frame). The RP2350 system clock is **150 MHz**; the `servo.c` driver divides that down to a **1 MHz** tick (1 tick = 1 µs) and wraps the counter at **20,000**, giving a 20 ms frame. The pulse width picks the angle: **1000 µs = 0°**, **1500 µs = 90°**, **2000 µs = 180°**. `servo_set_angle(float)` clamps the angle, maps it to a pulse in `[1000, 2000]`, and writes the PWM compare level. The float travels in a **general-purpose register (`r0`)**, not `s0` — you will see `vmov s14, r0` at the top of `servo_set_angle`. That is why the live angle hack edits `r0`. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x001d_static-conditionals/` and once inside `0x0020_dynamic-conditionals/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build → patch → flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x001d_static-conditionals/build/0x001d_static-conditionals.elf` and `.bin` — `.bin` is **8084** bytes (`0x1f94`) +- `0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.elf` and `.bin` — `.bin` is **16188** bytes (`0x3f3c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin` | +| Linux x64 | `/usr` | + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x001d_static-conditionals.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0020_dynamic-conditionals.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x001d_static-conditionals.elf | Select-String ' [Tt] ' +arm-none-eabi-nm -n --defined-only build\0x0020_dynamic-conditionals.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. The signatures below come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Project 1 — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (all three `static` helpers inlined) | +| `0x1000027c` | `servo_init` | `void servo_init(uint8_t)` | the `servo.c` init function | +| `0x10000318` | `servo_set_angle` | `void servo_set_angle(float)` | the `servo.c` angle setter (clamp + PWM level, all helpers inlined) | + +**Project 1 — the GPIO, timer, stdio, and `puts` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100003d8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000e28` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000100c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001020` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100010a0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10001274` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART/servo clock lookup | +| `0x10001604` | `exit` | `void exit(int)` | C runtime exit | +| `0x1000160c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10001638` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x100016e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x100017d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100017fc` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x1000188c` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (both prints) | +| `0x10001a68` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10001ba8` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**Project 2 — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (both `static` helpers inlined) | +| `0x100002dc` | `servo_init` | `void servo_init(uint8_t)` | the `servo.c` init function | +| `0x10000378` | `servo_set_angle` | `void servo_set_angle(float)` | the `servo.c` angle setter (all helpers inlined) | + +**Project 2 — the GPIO, timer, stdio, `printf`, `puts`, and `getchar` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000438` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000e88` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000106c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001080` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001100` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x100012d4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART/servo clock lookup | +| `0x10002f90` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002fec` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002ff4` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003020` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003130` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000321c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003244` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003250` | `__wrap_getchar` | `int __wrap_getchar(void)` | the `getchar` wrapper (reads the UART) | +| `0x10003344` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper | +| `0x10003380` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x10003444` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (`%s` calls) | +| `0x10003600` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003740` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +> **`main` is `0x10000234` in both projects.** In Project 1 the three `static` helpers are inlined into `main`; in Project 2 `eval_if_else` and `process_servo_command` are inlined, and `sweep_servo` with them. That is why both projects put `main` at the same address. In a `Debug` build the helpers stay separate and `main` moves — another reason to build `Release`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Project 1 has no `printf` at all: the compiler replaced every `printf("...")` with a `__wrap_puts` because the strings have no format specifiers. + +### Step 5: Flash Project 1 and confirm `1` / `one` + servo sweep + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x001d_static-conditionals/build/0x001d_static-conditionals.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x001d_static-conditionals\build\0x001d_static-conditionals.bin +``` + +**Or flash from the Binary Ninja console:** + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x001d_static-conditionals", "build", "0x001d_static-conditionals.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x001d_static-conditionals", "build", "0x001d_static-conditionals.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 8084 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY → Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +``` +1 +one +1 +one +1 +one +... +``` + +The servo sweeps **0° → 180° → 0°** once per second, and because `choice` is hard-coded the same two lines repeat forever. + +### Step 6: Flash Project 2 and confirm the dynamic behavior + +```bash +# macOS / Linux +./flash.sh 0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin +``` +```powershell +# Windows +.\flash.ps1 -Bin 0x0020_dynamic-conditionals\build\0x0020_dynamic-conditionals.bin +``` + +**Or flash from the Binary Ninja console** (same form, pointing at the Project 2 `.bin`): + +**macOS / Linux:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0020_dynamic-conditionals", "build", "0x0020_dynamic-conditionals.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0020_dynamic-conditionals", "build", "0x0020_dynamic-conditionals.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 16188 bytes ...`. Nothing prints until you type. In the serial monitor: + +- type `1` → the Pico prints `1` then `one`, and the servo sweeps **0° → 180°**; +- type `2` → it prints `2` then `two`, and the servo sweeps **180° → 0°**; +- type anything else → it prints `??` twice and waits for another key. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja (Project 1) + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x001d_static-conditionals/build/0x001d_static-conditionals.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> load("0x001d_static-conditionals/build/0x001d_static-conditionals.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 8: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x001d_static-conditionals.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +| File | Role | +| ---- | ---- | +| `0x001d_static-conditionals.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x001d_static-conditionals.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 13. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at `main` and Hack Live (Project 1) + +### Step 10: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 11. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. + +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 13) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` → WinUSB). + +### Step 11: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 10 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. + +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 10), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. + +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. + +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. Always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 12: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186 : +10000186: ldr r1, [pc, #80] +10000188: blx r1 +1000018a: ldr r1, [pc, #80] +1000018c: blx r1 +1000018e: ldr r1, [pc, #80] +10000190: blx r1 +10000192: bkpt 0x0000 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in both projects, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234`. + +### Step 13: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +#### Where you can stop + +| You want to stop at | Project 1 address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 10), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **First `puts` (`"1\r\n"`)** | `0x10000246` | Set a hardware breakpoint in the GUI, then click **Resume**. | Yes — fires on every iteration. | +| **Second `puts` (`"one\r"`)** | `0x1000024c` | Same. | Yes. | +| **`servo_set_angle(0.0f)`** | `0x10000252` | Same. | Yes. | +| **`servo_set_angle(180.0f)`** | `0x10000260` | Same — this is the angle we hack. | Yes. | + +#### Set a breakpoint in the GUI + +1. Press `G`, type the address (for example `0x10000260`), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next iteration. Binary Ninja stops with the PC at the address and reports it as a **Breakpoint**. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 11). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_puts` or `servo_set_angle`, so **Step Over** at a `bl` behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 14 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +### Step 14: HACK IT LIVE — change the servo angle from 180° to 30° + +`main` loads the constant `0x43340000` (180.0f) into `r4` once, before the loop, then copies it into `r0` at `0x1000025e` right before the `servo_set_angle` call at `0x10000260`. We break on that call and change the angle live. + +1. Press `G`, go to `0x10000260` (the `bl servo_set_angle` for 180.0°). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja. The target is already running the loop, so the breakpoint fires on the next pass. Binary Ninja stops with the program counter at `0x10000260` and `r0 = 0x43340000` — the `mov r0, r4` at `0x1000025e` just loaded the 180.0f literal into `r0`. +4. Open the **Registers** widget (bug icon → **Registers**). +5. Find `r0`. Its value is `0x43340000`. +6. **Set `r0` to `0x41f00000` (30.0f).** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r0", 0x41f00000) # 30.0f + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r0` in the **Registers** widget, press `E` (edit), type `41f00000`, and press Enter. The widget may not repaint the value, but the write reaches the target. +7. **Move the breakpoint past the call.** Remove the breakpoint at `0x10000260` and set a hardware breakpoint at `0x10000264` (the `mov.w r0, #500` right after the call). Two reasons not to just click **Step Over**: a breakpoint left on the current PC re-traps the step, and Binary Ninja's **Step Over** steps *into* `servo_set_angle` on this raw `.bin`. +8. Click **Resume**. The core executes `bl servo_set_angle` with `r0 = 0x41f00000`, so this sweep ends at **30°** instead of 180°, then stops at `0x10000264`. Watch the servo arm. + +> **`r4` is the real source — and it never reloads inside the loop.** `r4` is loaded once at `0x10000242` (before the loop starts at `0x10000244`) from the literal at `0x10000270`, so if you set `r4 = 0x41f00000` instead of `r0`, *every* pass uses 30° until the next reset. Editing `r0` changes only the current sweep because the next pass reloads `r0` from `r4`. Both edits are useful: `r0` shows a one-shot live change; `r4` shows a sticky one. + +### Step 14b: HACK THE STRING LIVE — change `one` to `fun` + +The text `"one\r"` lives in flash (`.rodata`) at `0x10001c64`, and flash is **read-only at runtime** — a debugger write there does not stick. So you cannot overwrite the text in place. Instead you redirect the pointer: at the `puts` call, `r0` holds the string address, so you point `r0` at a replacement string you place in RAM. + +1. Press `G`, go to `0x1000024c` (the second `bl __wrap_puts`) and set a **hardware execute** breakpoint. Resume; the loop hits it next pass. At the stop, `r0 = 0x10001c64` — the `ldr r0, [pc, #44]` at `0x1000024a` just loaded the `"one\r"` pointer from the literal at `0x10000278`. +2. Put the replacement string into free RAM at `0x20080000` from Binary Ninja's **Python console**: + ```python + dbg.write_memory(0x20080000, b"fun\r\x00") # puts appends the newline + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. The bytes are `66 75 6e 0d 00` = `"fun\r\0"`. We keep the `\r` and let `puts` add the `\n`, exactly as the compiler does for the original `"one\r"`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `20080000`, and press Enter.) +4. Move the breakpoint past the call (remove it at `0x1000024c`, set one at `0x10000250`) and click **Resume**. The core runs `puts` with `r0` pointing at your RAM string, so this iteration prints: + ``` + fun + ``` + then stops at `0x10000250`. + +Like the angle hack, this is **one iteration only**: the loop reloads `r0` from the literal pool on every pass, so the next line is `one` again. The permanent version is the static patch in Step 18. + +### Step 15: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x10000244`, which reloads `r0` from `0x10001c64` and `0x1000025e` reloads `r0` from `r4`, so the next line is `one` and the next sweep ends at 180° again. The live edits changed one iteration only; nothing in RAM controls these values. To make the changes permanent we must patch the bytes — the static pass. + +Press **Pause** to stop the output flood. + +### Step 15b: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch (Project 1) + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_100017fc()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `servo_init` + +1. `G` -> `0x1000027c`. +2. `Y` -> `void servo_init(uint8_t pin)`. + +It takes a `uint8_t` pin number; `main` calls it with `6` (`movs r0, #6`). + +#### Worked example: `servo_set_angle` + +1. `G` -> `0x10000318`. +2. `Y` -> `void servo_set_angle(float degrees)`. + +The float arrives in **`r0`** (soft-float ABI), not `s0`. The function opens with `vmov s14, r0` and then clamps the resulting pulse to `[1000, 2000]` — you can see `cmp.w r3, #2000` and `cmp.w r3, #1000` inside it. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x1000188c`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +Both prints in `main` land here. `printf("1\r\n")` has no format specifiers, so the compiler replaced it with `puts`; the `\n` was trimmed out of the string because `puts` adds one. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x100017fc`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `sleep_ms` + +1. `G` -> `0x10000e28`. +2. `Y` -> `void sleep_ms(uint32_t ms)`. + +Both delay instructions load `r0 = 0x1f4` (500) immediately before calling it. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── servo_init ── gpio_set_function, clock_get_hz +├── __wrap_puts ── strlen, stdio_put_string ── time_us_64, strlen +└── servo_set_angle, sleep_ms +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x1000027c` | `servo_init` | `void servo_init(uint8_t)` | +| `0x10000318` | `servo_set_angle` | `void servo_set_angle(float)` | +| `0x100003d8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e28` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000100c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001020` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100010a0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10001274` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10001604` | `exit` | `void exit(int)` | +| `0x1000160c` | `runtime_init` | `void runtime_init(void)` | +| `0x10001638` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x100016e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x100017d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100017fc` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x1000188c` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10001a68` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10001ba8` | `strlen` | `size_t strlen(const char*)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x1000027c: ("servo_init", "void servo_init(uint8_t)"), +> 0x10000318: ("servo_set_angle", "void servo_set_angle(float)"), +> 0x100003d8: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e28: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000100c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001020: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100010a0: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10001274: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10001604: ("exit", "void exit(int)"), +> 0x1000160c: ("runtime_init", "void runtime_init(void)"), +> 0x10001638: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x100016e8: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x100017d4: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100017fc: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x1000188c: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10001a68: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10001ba8: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first. Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`: + +```asm +10000234
: +10000234: push {r3, r4, r5, lr} +10000236: bl 100017fc +1000023a: movs r0, #6 +1000023c: bl 1000027c +10000240: movs r5, #0 +10000242: ldr r4, [pc, #44] +10000244: ldr r0, [pc, #44] +10000246: bl 1000188c <__wrap_puts> +1000024a: ldr r0, [pc, #44] +1000024c: bl 1000188c <__wrap_puts> +10000250: mov r0, r5 +10000252: bl 10000318 +10000256: mov.w r0, #500 +1000025a: bl 10000e28 +1000025e: mov r0, r4 +10000260: bl 10000318 +10000264: mov.w r0, #500 +10000268: bl 10000e28 +1000026c: b.n 10000244 +1000026e: nop +10000270: .word 0x43340000 +10000274: .word 0x10001c5c +10000278: .word 0x10001c64 +``` + +The whole program is one loop because the three `static` helpers were inlined: + +- **No `cmp` anywhere.** `choice` is the constant `1`, so the compiler folded `if (choice == 1)` to always-true, deleted `else if (choice == 2)` and `else`, and left only the `1` and `one` prints. That is the static conditional. +- `r5 = 0` (`movs r5, #0` at `0x10000240`) is the `0.0f` angle; `r4` holds `0x43340000` (180.0f) from the literal pool at `0x10000270`. +- `0x10000274` and `0x10000278` point at `"1\r\n"` and `"one\r"` in `.rodata`. + +The decompiler reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + servo_init(6); + do + { + __wrap_puts("1\r\n"); + __wrap_puts("one\r"); + servo_set_angle(0.0f); + sleep_ms(0x1f4); + servo_set_angle(180.0f); + sleep_ms(0x1f4); + } while (true); +} +``` + +### Step 18: Patch 1 — change the strings `1` to `2` and `one` to `fun` + +The strings live in `.rodata`: + +```asm +10000270: .word 0x43340000 +10000274: .word 0x10001c5c +10000278: .word 0x10001c64 +``` + +`0x10001c5c` holds `31 0d 00` = `"1\r"`, and `0x10001c64` holds `6f 6e 65 0d 00` = `"one\r"`. Change the first byte of each string in the **Hex** view (`View -> Hex`, lock off) or the Python console: + +```python +bv.write(0x10001c5c, b"\x32") # "1" -> "2" +bv.write(0x10001c64, b"fun") # "one" -> "fun" +print(bv.read(0x10001c5c, 4)) # -> b'2\r\x00\x00' +print(bv.read(0x10001c64, 6)) # -> b'fun\r\x00\x00' +``` + +Keep the replacement lengths identical: `"1"` is one byte, `"one"` is three. A shorter string must be padded and a longer one would run into the next string. + +### Step 18b: Patch 2 — change the angle from 180.0f to 30.0f + +The 180.0f literal sits at `0x10000270`: + +```asm +10000270: .word 0x43340000 +``` + +It is loaded into `r4` at `0x10000242` and copied into `r0` before the second `servo_set_angle`. IEEE-754: + +- `0x43340000` = 180.0f → little-endian bytes `00 00 34 43` +- `0x41f00000` = 30.0f → little-endian bytes `00 00 f0 41` + +**Option A — Hex view:** go to `0x10000270` and change `00 00 34 43` to `00 00 f0 41`, then reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000270, bytes.fromhex("0000f041")) +print(bv.read(0x10000270, 4).hex(" ")) # -> 00 00 f0 41 +``` + +`30.0 = 1.875 × 2^4`; sign `0`, exponent `127 + 4 = 131 = 0x83`, mantissa `0.875 = 0x700000` → `0x41f00000`. + +### Step 18c: Patch 3 — speed up the sweep from 500 ms to 100 ms + +The compiler packed `500` directly into two 32-bit Thumb-2 `mov.w` instructions: + +```asm +10000256: mov.w r0, #500 +1000025a: bl 10000e28 +10000264: mov.w r0, #500 +10000268: bl 10000e28 +``` + +Each `mov.w r0, #500` is the four bytes `4f f4 fa 70`. The four bytes for `mov.w r0, #100` are `4f f0 64 00` (verified by assembling `mov.w r0, #100` with `arm-none-eabi-as`). Change both: + +```python +for addr in (0x10000256, 0x10000264): + bv.write(addr, bytes.fromhex("4ff06400")) # mov.w r0, #100 +``` + +> **Why the bytes change shape.** `500` does not fit in an 8-bit rotated immediate, so the encoder uses the `f4 4f`-family form `4f f4 fa 70`. `100` (`0x64`) does fit, so the encoder uses the `f04f`/`f0 4f` form `4f f0 64 00`. Same instruction, different immediate encoding. Both are exactly 4 bytes. + +Verify all five patches: + +```python +for addr in (0x10001c5c, 0x10001c64, 0x10000270, 0x10000256, 0x10000264): + print(hex(addr), bv.read(addr, 4).hex(" ")) +# -> 0x10001c5c 32 0d 00 00 +# -> 0x10001c64 66 75 6e 0d +# -> 0x10000270 00 00 f0 41 +# -> 0x10000256 4f f0 64 00 +# -> 0x10000264 4f f0 64 00 +``` + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x001d_static-conditionals", "build"), "0x001d_static-conditionals-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 8084 /.../build/0x001d_static-conditionals-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x1f94` = 8084). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. + +> **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so a relative `open(...)` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/`. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x001d_static-conditionals-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x001d_static-conditionals-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x001d_static-conditionals", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x001d_static-conditionals-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") +> ``` + +### Step 21: Flash and verify + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console (stop any running OpenOCD first, and use `Popen`, not `run`, so the console is not blocked): + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +bin_path = os.path.join(os.path.join(root, "0x001d_static-conditionals", "build"), "0x001d_static-conditionals-h.bin") +log = os.path.join(os.path.join(root, "0x001d_static-conditionals", "build"), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +Open the serial monitor: + +``` +2 +fun +2 +fun +2 +fun +... +``` + +The servo now sweeps **0° → 30°** and does it **5× faster**. **Five bytes changed, no source code.** + +--- + +## Part 5: Reflash Project 2 and Load It into Binary Ninja + +### Step 22: Reflash Project 2 and restart the session + +Part 4 left the Pico running the patched Project 1 image. Put the original Project 2 back and start a fresh session. + +1. Stop any running debug server so the flash script can use the probe: + + ```bash + # macOS / Linux + pkill -TERM -f openocd + ``` + ```powershell + # Windows + Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process + ``` + +2. Flash the original Project 2 image: + + ```bash + # macOS / Linux + ./flash.sh 0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin + ``` + ```powershell + # Windows + .\flash.ps1 -Bin 0x0020_dynamic-conditionals\build\0x0020_dynamic-conditionals.bin + ``` + + **Or do steps 1–2 from the Binary Ninja console:** + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0020_dynamic-conditionals", "build", "0x0020_dynamic-conditionals.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first + subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("flashing Project 2 in the background; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0020_dynamic-conditionals", "build", "0x0020_dynamic-conditionals.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("flashing Project 2 in the background; log:", log) + ``` + +3. Load Project 2 and save its database — see Step 22b. + +Confirm the Pico responds to `1` / `2` again. + +### Step 22b: Load Project 2 into Binary Ninja and save the database + +Exactly like Steps 7–8, but for Project 2. **Use `File -> Open with Options...`** (not plain `File -> Open`), select `0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin`, and set: + +- **Architecture:** `thumb2` +- **Platform:** `thumb2` +- **Base Address:** `0x10000000` + +Click **Open**. Then press `G`, type `0x10000000`, and confirm the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you see data at `0x00000000`, close the tab and redo it with `Open with Options`. + +Save it with `File -> Save As...` as `0x0020_dynamic-conditionals.bndb` (next to the `.bin`). From now on open the `.bndb`, not the `.bin`; save with `Cmd+S` / `Ctrl+S` after every rename or patch. + +> **Console equivalent:** +> ```python +> load("0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +--- + +## Part 6: Dynamic — Break at `main` and Hack Live (Project 2) + +### Step 23: Break at `main` + +`main` is at `0x10000234` in this project too. Start the server parked at `main` (Step 10 form) and connect with the **GDB MI** adapter (Step 11): + +1. Restart the server parked at `main`: + + **macOS / Linux:** + + ```bash + BP_ADDR=0x10000234 ./debug-server.sh + ``` + ```powershell + # Windows + $env:BP_ADDR="0x10000234"; .\debug-server.ps1 + ``` + + **Or restart it from the Binary Ninja console:** + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # kill any running server first + subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("OpenOCD restarted parked at main; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # kill any running server first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("OpenOCD restarted parked at main; log:", log) + ``` +2. Connect Binary Ninja (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +The target is already halted at `main` when Binary Ninja connects, and the sidebar reads `Stopped at 0x10000234`. + +### Step 24: Read `main` and find the dynamic conditional + +The whole loop is one function because both helpers were inlined. Notice the `cmp`/`beq`/`bne` chain the compiler had to keep this time: + +```asm +10000234
: +10000234: push {r3, r4, r5, lr} +10000236: bl 10003244 +1000023a: movs r0, #6 +1000023c: bl 100002dc +10000240: movs r4, #0 +10000242: ldr r5, [pc, #124] +10000244: bl 10003250 <__wrap_getchar> +10000248: uxtb r0, r0 +1000024a: cmp r0, #49 +1000024c: beq.n 10000268 +1000024e: cmp r0, #50 +10000250: beq.n 10000294 +10000252: ldr r0, [pc, #112] +10000254: bl 10003344 <__wrap_puts> +10000258: ldr r0, [pc, #104] +1000025a: bl 10003344 <__wrap_puts> +1000025e: bl 10003250 <__wrap_getchar> +10000262: uxtb r0, r0 +10000264: cmp r0, #49 +10000266: bne.n 1000024e +10000268: ldr r0, [pc, #92] +1000026a: bl 10003344 <__wrap_puts> +1000026e: ldr r1, [pc, #92] +10000270: ldr r0, [pc, #92] +10000272: bl 10003444 <__wrap_printf> +10000276: mov r0, r4 +10000278: bl 10000378 +1000027c: mov.w r0, #500 +10000280: bl 10000e88 +10000284: mov r0, r5 +10000286: bl 10000378 +1000028a: mov.w r0, #500 +1000028e: bl 10000e88 +10000292: b.n 10000244 +10000294: ldr r0, [pc, #60] +10000296: bl 10003344 <__wrap_puts> +1000029a: ldr r1, [pc, #60] +1000029c: ldr r0, [pc, #48] +1000029e: bl 10003444 <__wrap_printf> +100002a2: mov r0, r5 +100002a4: bl 10000378 +100002a8: mov.w r0, #500 +100002ac: bl 10000e88 +100002b0: mov r0, r4 +100002b2: bl 10000378 +100002b6: mov.w r0, #500 +100002ba: bl 10000e88 +100002be: b.n 10000244 +100002c0: .word 0x43340000 +100002c4: .word 0x1000381c +100002c8: .word 0x10003800 +100002cc: .word 0x10003808 +100002d0: .word 0x1000380c +100002d4: .word 0x10003814 +100002d8: .word 0x10003818 +``` + +Because `choice` is now `getchar()` and can be anything, the compiler cannot fold the condition. It emits the comparisons at `0x1000024a` (`cmp r0, #49` = `0x31` = `'1'`) and `0x1000024e` (`cmp r0, #50` = `0x32` = `'2'`), each followed by a `beq.n`. That is the dynamic conditional. + +The string map, read straight from `.rodata`: + +| Literal | Points at | String | +| ------- | --------- | ------ | +| `0x100002c4` | `0x1000381c` | `"??\r"` (the `else` / `default` prints) | +| `0x100002c8` | `0x10003800` | `"1\r\n"` (the `'1'` print) | +| `0x100002cc` | `0x10003808` | `"one"` (the `printf` argument) | +| `0x100002d0` | `0x1000380c` | `"%s\r\n"` (the `printf` format) | +| `0x100002d4` | `0x10003814` | `"2\r\n"` (the `'2'` print) | +| `0x100002d8` | `0x10003818` | `"two"` (the `printf` argument) | + +> **Why the `else` path has two `puts` and a second `getchar`.** The compiler inlined both `eval_if_else` and `process_servo_command`; both have a "default" that prints `"??\r\n"`, and the shared string is emitted twice (`0x10000252` and `0x10000258`). The second `getchar` at `0x1000025e` is the compiler's rotated loop back-edge. The observable behavior is what matters: `1` → `1`+`one`, `2` → `2`+`two`, anything else → `??` twice. + +### Step 25: HACK IT LIVE — drive the branch with `r0` + +`getchar` blocks until you press a key, so this breakpoint fires exactly when a key arrives. We stop right after the read and overwrite the value so the program takes whichever branch we want. + +1. Press `G`, go to `0x1000024a` (the first `cmp r0, #49`). Set a **hardware execute** breakpoint: `Debugger -> Add Hardware Breakpoint...`. +2. Click **Resume** and type any key in the serial monitor — for example `a`. `getchar` returns, the `uxtb` at `0x10000248` runs, and the breakpoint fires at `0x1000024a` with `r0 = 0x61` (`'a'`). +3. **Set `r0` to `0x31` (`'1'`)** from the Python console: + ```python + dbg.set_reg_value("r0", 0x31) # force the '1' branch + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `31`, and press Enter.) +4. Remove the breakpoint at `0x1000024a` and click **Resume**. The core runs `cmp r0, #49`, sees the forced `0x31`, and takes the `'1'` branch — so even though you typed `a`, the Pico prints: + ``` + 1 + one + ``` + and sweeps the servo **0° → 180°**. + +> **Change the branch, not the register, if you prefer.** Setting `r0 = 0x32` instead forces the `'2'` path (`2`, `two`, servo 180° → 0°). Setting `r0` to anything else drops into the `??` path. One live register write steers the whole control-flow chain. + +### Step 25b: HACK THE STRING LIVE — change `1` to `7` + +The `'1'` print uses the string at `0x10003800` (`"1\r\n"`). Exactly like Project 1, redirect `r0` to a RAM string at the `puts` call. + +1. Press `G`, go to `0x10000268` (the `bl __wrap_puts` on the `'1'` path) and set a hardware execute breakpoint. Resume and type `1`. At the stop, `r0 = 0x10003800` — the `ldr r0, [pc, #92]` at `0x10000268` loaded the `"1\r\n"` pointer. +2. Write the replacement to RAM and repoint `r0`: + ```python + dbg.write_memory(0x20080000, b"7\r\x00") # puts appends the newline + dbg.set_reg_value("r0", 0x20080000) + ``` +3. Remove the breakpoint at `0x10000268`, set one at `0x1000026a`, and click **Resume**. This iteration prints: + ``` + 7 + one + ``` + One iteration only — the loop reloads `r0` from the literal pool each pass. The permanent version is the static patch in Step 27b. + +### Step 25c: Kill the debugger and OpenOCD + +Same as Step 15b: click the **X** (**Kill**) in the **Debugger** sidebar (or **`Debugger -> Kill`**), then stop OpenOCD from the Binary Ninja console: + +**macOS / Linux:** + +```python +import subprocess +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe +``` + +**Windows:** + +```python +import subprocess +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe +``` + +--- + +## Part 7: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the Binary Ninja GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +#### Worked example: `main` + +1. `G` -> `0x10000234`. +2. `Y` -> `int main(void)` (Binary Ninja shows `int32_t main(void)` — the same 32-bit `int`). + +#### Worked example: `__wrap_getchar` + +1. `G` -> `0x10003250`. +2. `Y` -> `int __wrap_getchar(void)`. + +`getchar` returns an `int` in `r0`; `main` immediately narrows it with `uxtb r0, r0` before comparing. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x10003444`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. It forwards to `__wrap_vprintf`. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x10003344`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +#### Worked example: `servo_set_angle` + +1. `G` -> `0x10000378`. +2. `Y` -> `void servo_set_angle(float degrees)`. + +The clamp constants are inside it: + +```asm +100003ba: cmp.w r3, #2000 +100003be: it cs +100003c0: movcs.w r3, #2000 +100003c4: cmp.w r3, #1000 +100003c8: it cc +100003ca: movcc.w r3, #1000 +``` + +`0x7d0` is the 2000 µs maximum pulse and `0x3e8` is the 1000 µs minimum. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── servo_init ── gpio_set_function, clock_get_hz +├── __wrap_getchar ── busy_wait_us +├── __wrap_puts ── strlen, stdio_put_string ── time_us_64, strlen +├── __wrap_printf ── __wrap_vprintf ── vfctprintf, stdio_out_chars_crlf, time_us_64 +└── servo_set_angle, sleep_ms +``` + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002dc` | `servo_init` | `void servo_init(uint8_t)` | +| `0x10000378` | `servo_set_angle` | `void servo_set_angle(float)` | +| `0x10000438` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e88` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000106c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001080` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001100` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x100012d4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10002f90` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002fec` | `exit` | `void exit(int)` | +| `0x10002ff4` | `runtime_init` | `void runtime_init(void)` | +| `0x10003020` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003130` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000321c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003244` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003250` | `__wrap_getchar` | `int __wrap_getchar(void)` | +| `0x10003344` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003380` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10003444` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003600` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003740` | `strlen` | `size_t strlen(const char*)` | + +> **Shortcut — resolves name *and* type for every function.** Paste this into Binary Ninja's Python console: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002dc: ("servo_init", "void servo_init(uint8_t)"), +> 0x10000378: ("servo_set_angle", "void servo_set_angle(float)"), +> 0x10000438: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e88: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000106c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001080: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001100: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x100012d4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10002f90: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x10002fec: ("exit", "void exit(int)"), +> 0x10002ff4: ("runtime_init", "void runtime_init(void)"), +> 0x10003020: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003130: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000321c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003244: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x10003250: ("__wrap_getchar", "int __wrap_getchar(void)"), +> 0x10003344: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003380: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x10003444: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003600: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003740: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` + +### Step 27: Patch 1 — change the servo angle from 180.0f to 30.0f + +The 180.0f literal sits at `0x100002c0`, loaded into `r5` at `0x10000242`: + +```asm +100002c0: .word 0x43340000 +``` + +Change the four bytes exactly as in Project 1: + +```python +bv.write(0x100002c0, bytes.fromhex("0000f041")) # 180.0f -> 30.0f +print(bv.read(0x100002c0, 4).hex(" ")) # -> 00 00 f0 41 +``` + +Both servo paths (`0x10000284`/`0x100002a2` use `r5`, `0x10000276`/`0x100002b0` use `r4` = 0.0f) now cap at 30°. + +### Step 27b: Patch 2 — rewrite the secret keys `1` → `x` and `2` → `y` + +The two key comparisons are at `0x1000024a` and `0x1000024e`: + +```asm +1000024a: cmp r0, #49 +1000024e: cmp r0, #50 +``` + +The immediate is the low byte of the 16-bit `cmp` encoding: `0x31` at `0x1000024a` and `0x32` at `0x1000024e`. Change them to `x` (`0x78`) and `y` (`0x79`): + +```python +bv.write(0x1000024a, b"\x78") # cmp r0, #0x78 ('x') +bv.write(0x1000024e, b"\x79") # cmp r0, #0x79 ('y') +print(bv.read(0x1000024a, 2).hex(" ")) # -> 78 28 +print(bv.read(0x1000024e, 2).hex(" ")) # -> 79 28 +``` + +Now `x` takes the old `1` path and `y` takes the old `2` path. + +### Step 27c (optional): Patch 3 — make `x` and `y` stealth (skip the prints) + +The original `1`/`2` paths print before moving the servo. To make the new `x`/`y` keys silent, redirect the two `beq.n` targets straight to the servo code, skipping both prints. The current targets are `0x10000268` (the `1` print block) and `0x10000294` (the `2` print block); the servo code starts at `0x10000276` (`mov r0, r4`) and `0x100002a2` (`mov r0, r5`). + +| Address | Instruction | Before | After | New target | +| ------- | ----------- | ------ | ----- | ---------- | +| `0x1000024c` | `beq.n` | `0c d0` | `13 d0` | `0x10000276` (skip `1`/`one` prints) | +| `0x10000250` | `beq.n` | `20 d0` | `27 d0` | `0x100002a2` (skip `2`/`two` prints) | + +```python +bv.write(0x1000024c, bytes.fromhex("13d0")) # beq.n -> 0x10000276 +bv.write(0x10000250, bytes.fromhex("27d0")) # beq.n -> 0x100002a2 +``` + +> **How the encoding was chosen.** A 16-bit conditional branch is `1101 cond imm8`; the target is `PC + 4 + (imm8 << 1)`. For `0x1000024c` → `0x10000276`: `(0x276 - 0x250) / 2 = 0x13`. For `0x10000250` → `0x100002a2`: `(0x2a2 - 0x254) / 2 = 0x27`. Both were verified by patching a copy of the raw `.bin` and disassembling it with `arm-none-eabi-objdump`. This patch is optional; the key rewrite in Step 27b works without it (it just still prints). + +### Step 28: Export, convert, and flash + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0020_dynamic-conditionals", "build"), "0x0020_dynamic-conditionals-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16188 /.../build/0x0020_dynamic-conditionals-h.bin +``` + +`seg.data_length` is the image size (`0x3f3c` = 16188) read from the view — nothing hardcoded. + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0020_dynamic-conditionals-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0020_dynamic-conditionals-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the Binary Ninja console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21. + +### Step 29: Verify + +Open the serial monitor: + +- type `x` → with Step 27c applied, **no output** and the servo sweeps silently; without it, `x` prints `x`… actually it prints the original strings `1` / `one` because only the comparison changed (the print strings are untouched). With Step 27c applied the prints are skipped entirely — a **stealth command**. +- type `y` → likewise silent (Step 27c), and the servo sweeps the other way. +- the servo's maximum angle is now **30°**, not 180°. +- the original `1` and `2` keys no longer match the comparisons. + +**We changed the servo angle and hid two secret keys, with a handful of bytes and no source code.** + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r0", 0x41f00000)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write debugger memory | `dbg.write_memory(0x20080000, b"fun\r\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI | +| Confirm what is armed | The **Breakpoints** widget lists it | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 / 26 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 13). + +| Action | Command | +| ------ | ------- | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Break on a loop address in a running target | set a hardware breakpoint in the GUI, then **Resume** — repeatable | +| Kill the debugger | click **X** in the **Debugger** sidebar, or `Debugger -> Kill` | +| Stop OpenOCD | macOS/Linux: `pkill -TERM -f openocd` — Windows: `taskkill /F /IM openocd.exe` | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run`, reconnect — never `reset run` while attached | + +### Where you can stop + +| Stop at | Project 1 `0x001d` | Project 2 `0x0020` | +| ------- | ------------------ | ------------------ | +| `main` (once per reset) | `0x10000234` | `0x10000234` | +| First `puts` | `0x10000246` (`"1\r\n"`) | `0x10000268` (`"1\r\n"`) | +| Second `puts` | `0x1000024c` (`"one\r"`) | — | +| `getchar` return (dynamic key) | — | `0x1000024a` (`cmp r0, #0x31`) | +| `servo_set_angle(0.0f)` | `0x10000252` | `0x10000276` / `0x100002a2` | +| `servo_set_angle(180.0f)` | `0x10000260` | `0x10000284` / `0x100002b0` | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x001d` | `0x10001c5c` | `31` | `32` | prints `2` instead of `1` | +| `0x001d` | `0x10001c64` | `6f 6e 65` | `66 75 6e` | prints `fun` instead of `one` | +| `0x001d` | `0x10000270` | `00 00 34 43` | `00 00 f0 41` | servo max angle `180.0f` → `30.0f` | +| `0x001d` | `0x10000256` | `4f f4 fa 70` | `4f f0 64 00` | first `sleep_ms` `500` → `100` | +| `0x001d` | `0x10000264` | `4f f4 fa 70` | `4f f0 64 00` | second `sleep_ms` `500` → `100` | +| `0x0020` | `0x1000024a` | `31` | `78` | compare `'1'` → `'x'` | +| `0x0020` | `0x1000024e` | `32` | `79` | compare `'2'` → `'y'` | +| `0x0020` | `0x100002c0` | `00 00 34 43` | `00 00 f0 41` | servo max angle `180.0f` → `30.0f` | +| `0x0020` | `0x1000024c` | `0c` | `13` | `beq.n` skips the `1`/`one` prints (optional) | +| `0x0020` | `0x10000250` | `20` | `27` | `beq.n` skips the `2`/`two` prints (optional) | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project 1 size | `8084` bytes | +| Project 2 size | `16188` bytes | +| Initial stack pointer (both) | `0x20082000` | +| Reset vector (both) | `0x1000015d` | +| Fixed `main` anchor (both) | `0x1000018c` | +| `main` (both) | `0x10000234` | +| `servo_set_angle`, Project 1 | `0x10000318` | +| `servo_set_angle`, Project 2 | `0x10000378` | +| Project 1 `180.0f` literal | `0x10000270` | +| Project 2 `180.0f` literal | `0x100002c0` | +| Project 1 `one` string | `0x10001c64` | +| Project 2 `one` string | `0x10003808` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints. +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 11). The 13.3.rel1 build did not connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping. Fix: `rp2350.dap.core0 configure -rtos none`. **GDB MI does not hit this.** + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps the `static` helpers separate. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — a software breakpoint cannot be written to read-only flash. + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Is the core running?** If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup rather than `reset run` while attached. Loop addresses such as `0x10000260` fire on the next pass with no reset. For Project 2's `0x1000024a` you must also press a key, because it sits right after the blocking `getchar`. + +### I edit `r0` (or another register) and it reverts + +For the Project 1 angle, `mov r0, r4` at `0x1000025e` reloads `r0` on every pass, so the edit is visible for one sweep unless you stop the core again. Editing `r4` instead makes it stick, because `r4` is loaded once before the loop. For Project 2, `getchar` reloads `r0` on every key press. The edit sticks only while the core is **genuinely stopped** at the breakpoint. + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target. A value changed outside Binary Ninja will not appear until the next stop. + +### The string hack does nothing (or prints garbage) + +Pick a RAM address that is free — `0x20080000` is safe here (well above the `.data`/`.bss` end at about `0x2000062c`). Write a NUL-terminated string, and remember `__wrap_puts` appends its own `\n`, so keep the `\r` but not the `\n` (write `b"fun\r\x00"`). Then set `r0`, not `r1`. + +### The patched string shifted `printf` output + +In Project 1 both prints are `puts`, so only whole-string replacement matters. Keep `"one"` → `"fun"` exactly three bytes; a longer string would overwrite the `\r` terminator and a shorter one would leave a stray character. + +### `mov.w r0, #100` corrupts the instruction + +Use the four bytes `4f f0 64 00`, not the first two bytes of the `500` encoding. `500` needs the `4f f4 …` form; `100` uses the `4f f0 …` form. Both are 4 bytes. Verify with `arm-none-eabi-objdump` (Step 20/21 context) or by re-reading the bytes in Binary Ninja. + +### Project 2's `x`/`y` still print + +Step 27b only changes the *comparison* values. To make the keys silent you must also apply the optional `beq` redirects in Step 27c. If the servo moves but the terminal still shows `1`/`one`, you applied 27b but not 27c. + +### The optional `beq` redirect sends execution somewhere wrong + +Recompute from the ELF: `target = PC + 4 + (imm8 << 1)`. For `0x1000024c` the servo code is at `0x10000276` (imm8 `0x13`); for `0x10000250` it is at `0x100002a2` (imm8 `0x27`). Confirm the byte pair you write is little-endian (`13 d0`, `27 d0`). + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first, or just use `screen /dev/cu.usbmodem* 115200`, which does it for you. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +The main cause is **driving the core from the OpenOCD command port while Binary Ninja is connected**. If you must reset, **Detach first**, reset, then reconnect. Never leave a breakpoint on the PC you are about to step or resume from. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27, you can still do the live hacks with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 10), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x10000260 +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x10000260` is inside `main`'s loop, so the breakpoint fires on the next iteration with no reset. GDB stops at the `servo_set_angle` call: + +``` +info registers pc r0 # pc = 0x10000260, r0 = 0x43340000 +set $r0 = 0x41f00000 +continue +``` + +The servo's next sweep ends at 30° — the same temporary live hack as editing `r0` in the Binary Ninja Registers widget. For the string hack, break at `0x1000024c`, then `set {char[5]}0x20080000 = "fun\r"` and `set $r0 = 0x20080000`. + +Project 2 is the same with the other call site and value: + +``` +hbreak *0x1000024a +continue +info registers pc r0 # r0 holds the key you typed +set $r0 = 0x31 +continue +``` + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`beq`** | Branch if Equal — ARM conditional jump, taken when the Z flag is set | +| **`bne`** | Branch if Not Equal — ARM conditional jump, taken when the Z flag is clear | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **Dynamic conditional** | A condition whose value is only known at run time (e.g. `getchar()`), so the compiler must emit the comparisons and branches | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +| **Hardware breakpoint** | A breakpoint serviced by the CPU comparators, required for read-only flash | +| **Inlining** | The optimizer replacing a function call with the function body; why the `static` helpers disappear from `main` in `Release` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **PWM** | Pulse Width Modulation — a variable pulse-width signal; 50 Hz for the SG90 | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SG90** | A common 0°–180° hobby servo driven by a 1–2 ms pulse every 20 ms | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Static conditional** | A condition whose value is known at compile time, so the compiler folds it and deletes dead branches | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, resolve the names from the ELF, then patch the bytes and flash. diff --git a/WEEK10/WEEK10-BN.pdf b/WEEK10/WEEK10-BN.pdf new file mode 100644 index 0000000..e7dae46 Binary files /dev/null and b/WEEK10/WEEK10-BN.pdf differ diff --git a/WEEK10/WEEK10-IDA.md b/WEEK10/WEEK10-IDA.md new file mode 100644 index 0000000..095540b --- /dev/null +++ b/WEEK10/WEEK10-IDA.md @@ -0,0 +1,965 @@ +# Week 10-IDA: IDA Pro — Hack Static & Dynamic Conditionals with the SG90 Servo (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build both lesson projects with `Release` and get an `.elf` and a raw `.bin` for each +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load each raw `.bin` into IDA at `0x10000000` +- **Resolve the functions in the IDA GUI** using the ELF symbol map +- **Patch** the bytes that control behavior — strings, an IEEE-754 float, an immediate delay, and two `beq` targets — export, convert and export +- Understand how a **static** conditional is optimized away while a **dynamic** conditional must keep its `cmp`/`beq`/`bne` branches + +--- + +## How This Guide Works + +Each project builds two files: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table and DWARF | Ground truth for every function address and signature | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the current `Release` builds. `Release` folds the `static` helpers (`print_if_else`, `print_switch`, `sweep_servo`, `eval_if_else`, `process_servo_command`) into `main` and keeps the code layout stable. If you build `Debug`, the SDK function addresses move and the helpers stay separate, so nothing lines up. Always build `Release` for this lesson. + +The workflow is static-only: import the raw image, recover the code, decompile it, and patch the artifact: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Prints | Also does | The hack | +| ------- | ------ | --------- | -------- | +| `0x001d_static-conditionals` | `1`, then `one`, forever | sweeps the SG90 servo 0° → 180° | angle `180` → `30`, delay `500` → `100`, string `1` → `2`, `one` → `fun` | +| `0x0020_dynamic-conditionals` | `1`+`one` or `2`+`two` from the keyboard | sweeps the servo on `1` / `2` | keys `1`/`2` → `x`/`y`, angle `180` → `30`, skip the prints to go stealth | + +> **Two conditionals, two fates.** In Project 1 the `choice` value is hard-coded (`int choice = 1;`), so the compiler proves the condition at compile time and **deletes the `cmp` and the dead branches** — that is a *static* conditional. In Project 2 `choice = getchar()`, so the value is only known at run time and the compiler must emit the `cmp`/`beq`/`bne` chain — that is a *dynamic* conditional. You will see both in the disassembly. + +> **Addresses come from your build.** Every address here is from the `Release` build produced in Step 3 and was verified against the current `.elf` files with `arm-none-eabi-nm` and `arm-none-eabi-objdump`. Confirm against your own `.elf` with the command in Step 4. + +> **The SVD file lives in `WEEK04`.** If you want the RP2350 peripheral register map for the PWM/UART side of the lab, it is `Embedded-Hacking/WEEK04/rp2350.svd` — it is **not** in `WEEK10`. + +### Background: PWM and the SG90 in one paragraph + +A servo wants a **50 Hz** signal (a 20 ms frame). The RP2350 system clock is **150 MHz**; the `servo.c` driver divides that down to a **1 MHz** tick (1 tick = 1 µs) and wraps the counter at **20,000**, giving a 20 ms frame. The pulse width picks the angle: **1000 µs = 0°**, **1500 µs = 90°**, **2000 µs = 180°**. `servo_set_angle(float)` clamps the angle, maps it to a pulse in `[1000, 2000]`, and writes the PWM compare level. The float travels in a **general-purpose register (`r0`)**, not `s0` — you will see `vmov s14, r0` at the top of `servo_set_angle`. That is why the live angle hack edits `r0`. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x001d_static-conditionals/` and once inside `0x0020_dynamic-conditionals/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point IDA at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so IDA never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the IDA console**, so the whole build → patch → flash loop stays inside IDA. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x001d_static-conditionals", "0x0020_dynamic-conditionals"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x001d_static-conditionals/build/0x001d_static-conditionals.elf` and `.bin` — `.bin` is **8084** bytes (`0x1f94`) +- `0x0020_dynamic-conditionals/build/0x0020_dynamic-conditionals.elf` and `.bin` — `.bin` is **16188** bytes (`0x3f3c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin` | +| Linux x64 | `/usr` | + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x001d_static-conditionals.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0020_dynamic-conditionals.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x001d_static-conditionals.elf | Select-String ' [Tt] ' +arm-none-eabi-nm -n --defined-only build\0x0020_dynamic-conditionals.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. The signatures below come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Project 1 — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (all three `static` helpers inlined) | +| `0x1000027c` | `servo_init` | `void servo_init(uint8_t)` | the `servo.c` init function | +| `0x10000318` | `servo_set_angle` | `void servo_set_angle(float)` | the `servo.c` angle setter (clamp + PWM level, all helpers inlined) | + +**Project 1 — the GPIO, timer, stdio, and `puts` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100003d8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000e28` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000100c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001020` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x100010a0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x10001274` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART/servo clock lookup | +| `0x10001604` | `exit` | `void exit(int)` | C runtime exit | +| `0x1000160c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10001638` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x100016e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x100017d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100017fc` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x1000188c` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (both prints) | +| `0x10001a68` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10001ba8` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**Project 2 — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (both `static` helpers inlined) | +| `0x100002dc` | `servo_init` | `void servo_init(uint8_t)` | the `servo.c` init function | +| `0x10000378` | `servo_set_angle` | `void servo_set_angle(float)` | the `servo.c` angle setter (all helpers inlined) | + +**Project 2 — the GPIO, timer, stdio, `printf`, `puts`, and `getchar` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000438` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000e88` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000106c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock | +| `0x10001080` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001100` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x100012d4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART/servo clock lookup | +| `0x10002f90` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | printf format engine | +| `0x10002fec` | `exit` | `void exit(int)` | C runtime exit | +| `0x10002ff4` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003020` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003130` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000321c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003244` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x10003250` | `__wrap_getchar` | `int __wrap_getchar(void)` | the `getchar` wrapper (reads the UART) | +| `0x10003344` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper | +| `0x10003380` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x10003444` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (`%s` calls) | +| `0x10003600` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003740` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +> **`main` is `0x10000234` in both projects.** In Project 1 the three `static` helpers are inlined into `main`; in Project 2 `eval_if_else` and `process_servo_command` are inlined, and `sweep_servo` with them. That is why both projects put `main` at the same address. In a `Debug` build the helpers stay separate and `main` moves — another reason to build `Release`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. Project 1 has no `printf` at all: the compiler replaced every `printf("...")` with a `__wrap_puts` because the strings have no format specifiers. + +## Part 2: Load the Raw `.bin` into IDA + +Start from a fresh IDA state. If you already have a database for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into IDA + +A raw `.bin` has no headers, so IDA cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, IDA may load it with a guessed architecture, and every address in this lesson will be wrong. + +#### 1.1 Open the file +1. **File ▸ Open…** (Ctrl/Cmd+O). +2. Select the `.bin` file and click **Open**. + +IDA opens the **"Load a new file"** dialog because a raw `.bin` has no header. + +#### 1.2 Set the format and processor +In the *Load a new file* dialog: +1. **Format**: leave it as **Binary file** (IDA auto-detects a headerless image). +2. **Processor type**: click the **…** button next to the processor field. In the *Processor type* dialog: + - Family: **ARM** + - Type: **ARM Little-endian** (the 32-bit ARM module). + - Click **OK**. + +> If IDA asks **"Do you want to disassemble it as 64-bit code?"** — click **No**. +> The RP2350 is 32-bit; answering *Yes* loads AArch64 and you get `X` registers / data. (This is the single most common cause of the `DCB` wall.) + +#### 1.3 Configure the ARM architecture and Thumb mode +Still in the *Load a new file* dialog, open the processor options (the **Processor options** / **Set…** button, which opens the dialog titled **ARM architecture options**): +- **ARM architecture**: choose **ARMv8-M** (this is the Cortex-M33 / RP2350 core). +- **Thumb instructions**: select **Thumb-2** (ARMv8-M is Thumb-only, so this is the correct mode). +- Leave **automatic ARM-THUMB switch** off; we want Thumb throughout. + +#### 1.4 Set the loading address +- **Loading address**: enter **`10000000`** (hex; the RP2350 XIP flash base). + IDA rejects addresses that don't look like ROM/RAM with *"The loading address should belong to RAM or ROM"* — `0x10000000` is the correct flash window. + +Leave **Manual load** and **Create segments** at their defaults. Click **OK**. + +#### 1.5 Force Thumb, then seed the code from the vector table +A raw `.bin` has no header, so IDA's loader has **no entry point** and defaults the segment to **ARM mode** (which cannot decode Thumb). Two required steps — in this order: + +**A. Set the segment to Thumb (do this first).** +- **Edit ▸ Segments ▸ Set default segment register value…** → register **`T`** = **`1`** (or press **`Alt+G`**). IDA reanalyzes the segment as Thumb automatically. + +**B. Seed the code from the vector table.** +1. **G** → `10000000`. The first two words are the initial stack pointer and the **reset vector**. +2. **Read the 4-byte word at `0x10000004`** (do **not** assume its value — it differs per build). +3. **Clear bit 0** (the ARM **Thumb** flag) → the reset handler address. +4. **G** to that address → press **C** (**MakeCode**). IDA disassembles the reset handler and follows its `bl`s into `main`. + +Once `main` shows code, the import is correct. + +**Why IDA needs this and others don't:** IDA's generic raw-binary ARM loader treats the image as flat data and waits for you to set Thumb and mark the entry point. It's an IDA quirk, not a mistake on your part. + +### Step 8: Save it as a IDA database (`.i64`) + +IDA never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.i64`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x001d_static-conditionals.i64`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +| File | Role | +| ---- | ---- | +| `0x001d_static-conditionals.bin` | the raw firmware image; IDA never modifies it | +| `0x001d_static-conditionals.i64` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.i64`**, not the `.bin`; that restores all your work. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Static — Resolve the Functions in IDA and Patch (Project 1) + +### Step 16: Resolve the functions in the IDA GUI + +We now name the functions in IDA using the ELF symbol map from Step 4. IDA loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | IDA action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in IDA (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_100017fc()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. IDA parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. + +> **IDA shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and IDA's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `servo_init` + +1. `G` -> `0x1000027c`. +2. `Y` -> `void servo_init(uint8_t pin)`. + +It takes a `uint8_t` pin number; `main` calls it with `6` (`movs r0, #6`). + +#### Worked example: `servo_set_angle` + +1. `G` -> `0x10000318`. +2. `Y` -> `void servo_set_angle(float degrees)`. + +The float arrives in **`r0`** (soft-float ABI), not `s0`. The function opens with `vmov s14, r0` and then clamps the resulting pulse to `[1000, 2000]` — you can see `cmp.w r3, #2000` and `cmp.w r3, #1000` inside it. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x1000188c`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +Both prints in `main` land here. `printf("1\r\n")` has no format specifiers, so the compiler replaced it with `puts`; the `\n` was trimmed out of the string because `puts` adds one. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x100017fc`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `sleep_ms` + +1. `G` -> `0x10000e28`. +2. `Y` -> `void sleep_ms(uint32_t ms)`. + +Both delay instructions load `r0 = 0x1f4` (500) immediately before calling it. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── servo_init ── gpio_set_function, clock_get_hz +├── __wrap_puts ── strlen, stdio_put_string ── time_us_64, strlen +└── servo_set_angle, sleep_ms +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x1000027c` | `servo_init` | `void servo_init(uint8_t)` | +| `0x10000318` | `servo_set_angle` | `void servo_set_angle(float)` | +| `0x100003d8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e28` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000100c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001020` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x100010a0` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x10001274` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10001604` | `exit` | `void exit(int)` | +| `0x1000160c` | `runtime_init` | `void runtime_init(void)` | +| `0x10001638` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x100016e8` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x100017d4` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100017fc` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x1000188c` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10001a68` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10001ba8` | `strlen` | `size_t strlen(const char*)` | + +> **A `void` return type may not stick — here is the fix.** IDA treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type IDA thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into IDA's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x1000027c: ("servo_init", "void servo_init(uint8_t)"), +> 0x10000318: ("servo_set_angle", "void servo_set_angle(float)"), +> 0x100003d8: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e28: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000100c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001020: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x100010a0: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x10001274: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10001604: ("exit", "void exit(int)"), +> 0x1000160c: ("runtime_init", "void runtime_init(void)"), +> 0x10001638: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x100016e8: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x100017d4: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100017fc: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x1000188c: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10001a68: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10001ba8: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, plus `uint`, `va_list`, `clock_handle_t`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first. Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`: + +```asm +10000234
: +10000234: push {r3, r4, r5, lr} +10000236: bl 100017fc +1000023a: movs r0, #6 +1000023c: bl 1000027c +10000240: movs r5, #0 +10000242: ldr r4, [pc, #44] +10000244: ldr r0, [pc, #44] +10000246: bl 1000188c <__wrap_puts> +1000024a: ldr r0, [pc, #44] +1000024c: bl 1000188c <__wrap_puts> +10000250: mov r0, r5 +10000252: bl 10000318 +10000256: mov.w r0, #500 +1000025a: bl 10000e28 +1000025e: mov r0, r4 +10000260: bl 10000318 +10000264: mov.w r0, #500 +10000268: bl 10000e28 +1000026c: b.n 10000244 +1000026e: nop +10000270: .word 0x43340000 +10000274: .word 0x10001c5c +10000278: .word 0x10001c64 +``` + +The whole program is one loop because the three `static` helpers were inlined: + +- **No `cmp` anywhere.** `choice` is the constant `1`, so the compiler folded `if (choice == 1)` to always-true, deleted `else if (choice == 2)` and `else`, and left only the `1` and `one` prints. That is the static conditional. +- `r5 = 0` (`movs r5, #0` at `0x10000240`) is the `0.0f` angle; `r4` holds `0x43340000` (180.0f) from the literal pool at `0x10000270`. +- `0x10000274` and `0x10000278` point at `"1\r\n"` and `"one\r"` in `.rodata`. + +The decompiler reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + servo_init(6); + do + { + __wrap_puts("1\r\n"); + __wrap_puts("one\r"); + servo_set_angle(0.0f); + sleep_ms(0x1f4); + servo_set_angle(180.0f); + sleep_ms(0x1f4); + } while (true); +} +``` + +### Step 18: Patch 1 — change the strings `1` to `2` and `one` to `fun` + +The strings live in `.rodata`: + +```asm +10000270: .word 0x43340000 +10000274: .word 0x10001c5c +10000278: .word 0x10001c64 +``` + +`0x10001c5c` holds `31 0d 00` = `"1\r"`, and `0x10001c64` holds `6f 6e 65 0d 00` = `"one\r"`. Change the first byte of each string in the **Hex** view (`View -> Hex`, lock off) or the Python console: + +```python +bv.write(0x10001c5c, b"\x32") # "1" -> "2" +bv.write(0x10001c64, b"fun") # "one" -> "fun" +print(bv.read(0x10001c5c, 4)) # -> b'2\r\x00\x00' +print(bv.read(0x10001c64, 6)) # -> b'fun\r\x00\x00' +``` + +Keep the replacement lengths identical: `"1"` is one byte, `"one"` is three. A shorter string must be padded and a longer one would run into the next string. + +### Step 18b: Patch 2 — change the angle from 180.0f to 30.0f + +The 180.0f literal sits at `0x10000270`: + +```asm +10000270: .word 0x43340000 +``` + +It is loaded into `r4` at `0x10000242` and copied into `r0` before the second `servo_set_angle`. IEEE-754: + +- `0x43340000` = 180.0f → little-endian bytes `00 00 34 43` +- `0x41f00000` = 30.0f → little-endian bytes `00 00 f0 41` + +**Option A — Hex view:** go to `0x10000270` and change `00 00 34 43` to `00 00 f0 41`, then reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x10000270, bytes.fromhex("0000f041")) +print(bv.read(0x10000270, 4).hex(" ")) # -> 00 00 f0 41 +``` + +`30.0 = 1.875 × 2^4`; sign `0`, exponent `127 + 4 = 131 = 0x83`, mantissa `0.875 = 0x700000` → `0x41f00000`. + +### Step 18c: Patch 3 — speed up the sweep from 500 ms to 100 ms + +The compiler packed `500` directly into two 32-bit Thumb-2 `mov.w` instructions: + +```asm +10000256: mov.w r0, #500 +1000025a: bl 10000e28 +10000264: mov.w r0, #500 +10000268: bl 10000e28 +``` + +Each `mov.w r0, #500` is the four bytes `4f f4 fa 70`. The four bytes for `mov.w r0, #100` are `4f f0 64 00` (verified by assembling `mov.w r0, #100` with `arm-none-eabi-as`). Change both: + +```python +for addr in (0x10000256, 0x10000264): + bv.write(addr, bytes.fromhex("4ff06400")) # mov.w r0, #100 +``` + +> **Why the bytes change shape.** `500` does not fit in an 8-bit rotated immediate, so the encoder uses the `f4 4f`-family form `4f f4 fa 70`. `100` (`0x64`) does fit, so the encoder uses the `f04f`/`f0 4f` form `4f f0 64 00`. Same instruction, different immediate encoding. Both are exactly 4 bytes. + +Verify all five patches: + +```python +for addr in (0x10001c5c, 0x10001c64, 0x10000270, 0x10000256, 0x10000264): + print(hex(addr), bv.read(addr, 4).hex(" ")) +# -> 0x10001c5c 32 0d 00 00 +# -> 0x10001c64 66 75 6e 0d +# -> 0x10000270 00 00 f0 41 +# -> 0x10000256 4f f0 64 00 +# -> 0x10000264 4f f0 64 00 +``` + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x001d_static-conditionals", "build"), "0x001d_static-conditionals-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 8084 /.../build/0x001d_static-conditionals-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base IDA loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x1f94` = 8084). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. + +> **No relative path.** IDA's Python console runs with a read-only working directory (inside the app bundle), so a relative `open(...)` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/`. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x001d_static-conditionals-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x001d_static-conditionals-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the IDA console** — `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x001d_static-conditionals", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x001d_static-conditionals-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") +> ``` + +## Part 5: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the IDA GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +#### Worked example: `main` + +1. `G` -> `0x10000234`. +2. `Y` -> `int main(void)` (IDA shows `int32_t main(void)` — the same 32-bit `int`). + +#### Worked example: `__wrap_getchar` + +1. `G` -> `0x10003250`. +2. `Y` -> `int __wrap_getchar(void)`. + +`getchar` returns an `int` in `r0`; `main` immediately narrows it with `uxtb r0, r0` before comparing. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x10003444`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. It forwards to `__wrap_vprintf`. + +#### Worked example: `__wrap_puts` + +1. `G` -> `0x10003344`. +2. `Y` -> `int __wrap_puts(const char *s)`. + +#### Worked example: `servo_set_angle` + +1. `G` -> `0x10000378`. +2. `Y` -> `void servo_set_angle(float degrees)`. + +The clamp constants are inside it: + +```asm +100003ba: cmp.w r3, #2000 +100003be: it cs +100003c0: movcs.w r3, #2000 +100003c4: cmp.w r3, #1000 +100003c8: it cc +100003ca: movcc.w r3, #1000 +``` + +`0x7d0` is the 2000 µs maximum pulse and `0x3e8` is the 1000 µs minimum. + +The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init, stdio_set_driver_enabled +│ └── uart_init ── clock_get_hz, busy_wait_us +├── servo_init ── gpio_set_function, clock_get_hz +├── __wrap_getchar ── busy_wait_us +├── __wrap_puts ── strlen, stdio_put_string ── time_us_64, strlen +├── __wrap_printf ── __wrap_vprintf ── vfctprintf, stdio_out_chars_crlf, time_us_64 +└── servo_set_angle, sleep_ms +``` + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002dc` | `servo_init` | `void servo_init(uint8_t)` | +| `0x10000378` | `servo_set_angle` | `void servo_set_angle(float)` | +| `0x10000438` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000e88` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000106c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x10001080` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001100` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x100012d4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10002f90` | `vfctprintf` | `int vfctprintf(void (*)(char, void*), void*, const char*, va_list)` | +| `0x10002fec` | `exit` | `void exit(int)` | +| `0x10002ff4` | `runtime_init` | `void runtime_init(void)` | +| `0x10003020` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003130` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000321c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003244` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x10003250` | `__wrap_getchar` | `int __wrap_getchar(void)` | +| `0x10003344` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003380` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x10003444` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x10003600` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003740` | `strlen` | `size_t strlen(const char*)` | + +> **Shortcut — resolves name *and* type for every function.** Paste this into IDA's Python console: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002dc: ("servo_init", "void servo_init(uint8_t)"), +> 0x10000378: ("servo_set_angle", "void servo_set_angle(float)"), +> 0x10000438: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000e88: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000106c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x10001080: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001100: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x100012d4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10002f90: ("vfctprintf", "int vfctprintf(void (*)(char, void*), void*, const char*, va_list)"), +> 0x10002fec: ("exit", "void exit(int)"), +> 0x10002ff4: ("runtime_init", "void runtime_init(void)"), +> 0x10003020: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003130: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000321c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003244: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x10003250: ("__wrap_getchar", "int __wrap_getchar(void)"), +> 0x10003344: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003380: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x10003444: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x10003600: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003740: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` + +### Step 27: Patch 1 — change the servo angle from 180.0f to 30.0f + +The 180.0f literal sits at `0x100002c0`, loaded into `r5` at `0x10000242`: + +```asm +100002c0: .word 0x43340000 +``` + +Change the four bytes exactly as in Project 1: + +```python +bv.write(0x100002c0, bytes.fromhex("0000f041")) # 180.0f -> 30.0f +print(bv.read(0x100002c0, 4).hex(" ")) # -> 00 00 f0 41 +``` + +Both servo paths (`0x10000284`/`0x100002a2` use `r5`, `0x10000276`/`0x100002b0` use `r4` = 0.0f) now cap at 30°. + +### Step 27b: Patch 2 — rewrite the secret keys `1` → `x` and `2` → `y` + +The two key comparisons are at `0x1000024a` and `0x1000024e`: + +```asm +1000024a: cmp r0, #49 +1000024e: cmp r0, #50 +``` + +The immediate is the low byte of the 16-bit `cmp` encoding: `0x31` at `0x1000024a` and `0x32` at `0x1000024e`. Change them to `x` (`0x78`) and `y` (`0x79`): + +```python +bv.write(0x1000024a, b"\x78") # cmp r0, #0x78 ('x') +bv.write(0x1000024e, b"\x79") # cmp r0, #0x79 ('y') +print(bv.read(0x1000024a, 2).hex(" ")) # -> 78 28 +print(bv.read(0x1000024e, 2).hex(" ")) # -> 79 28 +``` + +Now `x` takes the old `1` path and `y` takes the old `2` path. + +### Step 27c (optional): Patch 3 — make `x` and `y` stealth (skip the prints) + +The original `1`/`2` paths print before moving the servo. To make the new `x`/`y` keys silent, redirect the two `beq.n` targets straight to the servo code, skipping both prints. The current targets are `0x10000268` (the `1` print block) and `0x10000294` (the `2` print block); the servo code starts at `0x10000276` (`mov r0, r4`) and `0x100002a2` (`mov r0, r5`). + +| Address | Instruction | Before | After | New target | +| ------- | ----------- | ------ | ----- | ---------- | +| `0x1000024c` | `beq.n` | `0c d0` | `13 d0` | `0x10000276` (skip `1`/`one` prints) | +| `0x10000250` | `beq.n` | `20 d0` | `27 d0` | `0x100002a2` (skip `2`/`two` prints) | + +```python +bv.write(0x1000024c, bytes.fromhex("13d0")) # beq.n -> 0x10000276 +bv.write(0x10000250, bytes.fromhex("27d0")) # beq.n -> 0x100002a2 +``` + +> **How the encoding was chosen.** A 16-bit conditional branch is `1101 cond imm8`; the target is `PC + 4 + (imm8 << 1)`. For `0x1000024c` → `0x10000276`: `(0x276 - 0x250) / 2 = 0x13`. For `0x10000250` → `0x100002a2`: `(0x2a2 - 0x254) / 2 = 0x27`. Both were verified by patching a copy of the raw `.bin` and disassembling it with `arm-none-eabi-objdump`. This patch is optional; the key rewrite in Step 27b works without it (it just still prints). + +### Step 28: Export, convert and export + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0020_dynamic-conditionals", "build"), "0x0020_dynamic-conditionals-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16188 /.../build/0x0020_dynamic-conditionals-h.bin +``` + +`seg.data_length` is the image size (`0x3f3c` = 16188) read from the view — nothing hardcoded. + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0020_dynamic-conditionals-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0020_dynamic-conditionals-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the IDA console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`beq`** | Branch if Equal — ARM conditional jump, taken when the Z flag is set | +| **`bne`** | Branch if Not Equal — ARM conditional jump, taken when the Z flag is clear | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **Dynamic conditional** | A condition whose value is only known at run time (e.g. `getchar()`), so the compiler must emit the comparisons and branches | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +ly flash | +| **Inlining** | The optimizer replacing a function call with the function body; why the `static` helpers disappear from `main` in `Release` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **PWM** | Pulse Width Modulation — a variable pulse-width signal; 50 Hz for the SG90 | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SG90** | A common 0°–180° hobby servo driven by a 1–2 ms pulse every 20 ms | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Static conditional** | A condition whose value is known at compile time, so the compiler folds it and deletes dead branches | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions. diff --git a/WEEK10/WEEK10-IDA.pdf b/WEEK10/WEEK10-IDA.pdf new file mode 100644 index 0000000..e413f43 Binary files /dev/null and b/WEEK10/WEEK10-IDA.pdf differ diff --git a/WEEK10/WEEK10-SLIDES.pdf b/WEEK10/WEEK10-SLIDES.pdf new file mode 100644 index 0000000..15d20a7 Binary files /dev/null and b/WEEK10/WEEK10-SLIDES.pdf differ diff --git a/WEEK10/WEEK10.md b/WEEK10/WEEK10.md new file mode 100644 index 0000000..a7ddb79 --- /dev/null +++ b/WEEK10/WEEK10.md @@ -0,0 +1,1656 @@ +# Week 10: Conditionals in Embedded Systems: Debugging and Hacking Static & Dynamic Conditionals w/ SG90 Servo Motor PWM Basics + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand the difference between static and dynamic conditionals in C +- Know how if/else statements and switch/case blocks work at the assembly level +- Understand Pulse Width Modulation (PWM) and how it controls servo motors +- Calculate PWM timing from system clock to servo pulse width +- Identify conditional branches in Ghidra (beq, bne instructions) +- Hack string literals and timing delays in binary files +- Modify branch targets to change program flow +- Create "stealth" functionality by NOP-ing out print statements +- Understand IEEE-754 floating-point for angle calculations + +--- + +## Part 1: Understanding Conditionals in C + +### What Are Conditionals? + +**Conditionals** are programming structures that make decisions. They let your program choose different paths based on whether a condition is true or false. Think of them like a fork in the road - the program checks a condition and decides which way to go. + +### Two Types of Conditionals + +| Type | Description | Example | +| ----------- | ---------------------------------------------- | ------------------------------------------------- | +| **Static** | Condition value is known/fixed at compile time | `if (choice == 1)` where choice never changes | +| **Dynamic** | Condition value changes based on runtime input | `if (choice == getchar())` where user types input | + +--- + +## Part 2: Static Conditionals + +### What Makes a Conditional "Static"? + +A **static conditional** is one where the outcome is predetermined because the condition variable never changes during program execution: + +```c +int choice = 1; // This NEVER changes! + +while (true) { + if (choice == 1) { + printf("1\r\n"); // This ALWAYS runs + } else if (choice == 2) { + printf("2\r\n"); // This NEVER runs + } else { + printf("?\r\n"); // This NEVER runs + } +} +``` + +```text ++-----------------------+ +| choice = 1 | +| set once, never | +| changes | ++-----------------------+ + | + v + [ choice == 1 ] + | + | YES + v ++-----------------------+ +| printf '1' | ++-----------------------+ + . + . NO (never taken) + v + [ choice == 2 ] + . + . YES (never reached) + v ++-----------------------+ +| printf '2' | ++-----------------------+ + . + . NO + v ++-----------------------+ +| printf '?' | ++-----------------------+ +``` + +### The if/else Statement + +The `if/else` structure checks conditions in order: + +```c +if (choice == 1) { +// Do something if choice is 1 +} else if (choice == 2) { +// Do something if choice is 2 +} else { +// Do something for all other values +} +``` + +### The switch Statement + +The `switch` statement is another way to handle multiple conditions: + +```c +switch (choice) { + case 1: + printf("one\r\n"); + break; + case 2: + printf("two\r\n"); + break; + default: + printf("??\r\n"); +} +``` + +**Key Differences:** + +| Feature | if/else | switch | +| ---------------- | ----------------------- | -------------------------- | +| **Condition** | Any boolean expression | Single variable comparison | +| **Values** | Ranges, complex logic | Discrete values only | +| **Fall-through** | No | Yes (without `break`) | +| **Readability** | Good for 2-3 conditions | Better for many conditions | + +--- + +## Part 3: Dynamic Conditionals + +### What Makes a Conditional "Dynamic"? + +A **dynamic conditional** is one where the condition variable changes based on runtime input: + +```c +uint8_t choice = 0; + +while (true) { + choice = getchar(); // User types a key - VALUE CHANGES! + + if (choice == '1') { + printf("1\r\n"); + } else if (choice == '2') { + printf("2\r\n"); + } else { + printf("??\r\n"); + } +} +``` + +```text + +-------------------+ + | getchar() | <----------------------------------+ + +-------------------+ | + | User types input | + v | + +-------------------+ | + | choice = input | | + +-------------------+ | + | | + v | + [ choice == '1' ] -- YES --> +-----------------------+ | + | | printf("1") | | + | NO | move servo | | + | +-----------------------+ | + v | + [ choice == '2' ] -- YES --> +-----------------------+ | + | | printf("2") | | + | NO | move servo | | + | +-----------------------+ | + v | + +-------------------+ | + | printf("??") | | + +-------------------+ | + | | + +-----------------------------------------------+ +``` + +### The getchar() Function + +`getchar()` reads a single character from the serial terminal: + +```c +uint8_t choice = getchar(); // Waits for user to type something +``` + +- Returns the ASCII value of the key pressed +- `'1'` = 0x31, `'2'` = 0x32, `'x'` = 0x78, `'y'` = 0x79 +- Blocks (waits) until a key is pressed + +--- + +## Part 4: Understanding PWM (Pulse Width Modulation) + +### What is PWM? + +**PWM** (Pulse Width Modulation) is a technique for controlling power by rapidly switching a signal on and off. The ratio of "on time" to "off time" determines the average power delivered. + +```text + PWM Signal - 50% Duty Cycle + + HIGH +-----+ +-----+ +-----+ + | | | | | | + LOW + +-----+ +-----+ +----- + |--T--| + ON OFF + + Duty Cycle = ON time / Total period = 50% +``` + +### PWM for Servo Control + +Servo motors use PWM differently - they care about the **pulse width**, not the duty cycle percentage: + +```text + Servo PWM Signal (50 Hz = 20ms period) + + 0° Position (1ms pulse): + HIGH -+ + | 1ms + LOW +----------------------------------- (19ms) ----- + + 90° Position (1.5ms pulse): + HIGH ---+ + | 1.5ms + LOW +-------------------------------- (18.5ms) ---- + + 180° Position (2ms pulse): + HIGH -----+ + | 2ms + LOW +-------------------------------- (18ms) ---- +``` + +### The Magic Numbers + +| Angle | Pulse Width | PWM Ticks (at 1MHz) | +| ----- | ----------- | ------------------- | +| 0° | 1000 µs | 1000 | +| 90° | 1500 µs | 1500 | +| 180° | 2000 µs | 2000 | + +--- + +## Part 5: PWM Timing Calculations + +### From 150 MHz to 50 Hz + +The RP2350's system clock runs at **150 MHz** (150 million cycles per second). A servo needs a **50 Hz** signal (one pulse every 20 ms). How do we bridge this gap? + +```text ++-----------------------+ +| System Clock | +| 150 MHz | ++-----------------------+ + | + | Divide by 150 + v ++-----------------------+ +| PWM Tick Rate | +| 1 MHz | +| (1 tick = 1 µs) | ++-----------------------+ + | + | Count to 20,000 + | Wrap at 19,999 + v ++-----------------------+ +| Servo PWM Signal | +| 50 Hz | +| (20 ms period) | ++-----------------------+ +``` + +### The Math + +**Step 1: Clock Division** +``` +PWM Tick Rate = System Clock / Divider +1,000,000 Hz = 150,000,000 Hz / 150 +``` + +**Step 2: Frame Period** +``` +Period = (Wrap Value + 1) * Tick Duration +20 ms = 20,000 ticks * 1 µs/tick +``` + +**Step 3: Pulse Width to Ticks** +``` +Ticks = Pulse Width (µs) * 1 tick/µs +1500 ticks = 1500 µs * 1 +``` + +### Worked Example: 90° Angle + +Let's calculate what happens when we command 90°: + +1. **Angle to Pulse Width:** + ``` + Pulse = MIN + (angle/180) * (MAX - MIN) + Pulse = 1000 + (90/180) * (2000 - 1000) + Pulse = 1000 + 0.5 * 1000 + Pulse = 1500 µs + ``` + +2. **Pulse to PWM Ticks:** + ``` + Level = 1500 µs * 1 tick/µs = 1500 ticks + ``` + +3. **Hardware Timing:** + - Signal HIGH for 1500 ticks (1.5 ms) + - Signal LOW for 18,500 ticks (18.5 ms) + - Total period: 20,000 ticks (20 ms) + +--- + +## Part 6: Understanding the SG90 Servo Motor + +### What is the SG90? + +The **SG90** is a small, inexpensive hobby servo motor commonly used in robotics projects: + +```text +[ SG90 Servo Motor ] ++-----------------------------------+ +| Motor ---> Gearbox ---> Arm | +| (0° to 180°) | ++-----------------------------------+ + | Wires + v +[ Wires ] ++-----------------------------------+ +| Orange: Signal / PWM | +| Red: VCC / 5V | +| Brown: GND / Ground | ++-----------------------------------+ +``` + +### SG90 Specifications + +| Parameter | Value | +| ----------------- | ------------------------- | +| **Voltage** | 4.8V - 6V (typically 5V) | +| **Rotation** | 0° to 180° | +| **Pulse Width** | 1000 us - 2000 us | +| **Frequency** | 50 Hz (20ms period) | +| **Stall Current** | ~650mA (can spike to 1A+) | + +### Wire Colors + +| Wire Color | Function | Connect To | +| ---------- | -------- | --------------- | +| **Brown** | GND | Ground | +| **Red** | VCC | 5V Power (VBUS) | +| **Orange** | Signal | GPIO Pin (PWM) | + +--- + +## Part 7: Power Supply Safety + +### CRITICAL WARNING + +**NEVER power the servo directly from the Pico's 3.3V pin!** + +Servos can draw over 1000mA during movement spikes. The Pico's 3.3V regulator cannot handle this and you will: + +- Cause brownouts (Pico resets) +- Damage the Pico's voltage regulator +- Potentially damage your USB port + +### Correct Power Setup + +```text ++-----------------+ +------------------------+ +| USB Power | ---> | VBUS 5V | ++-----------------+ +------------------------+ + | | + v v + [ Servo VCC ] [ Capacitor + ] + (Red) (1000 uF 25V) + ++-----------------+ +| Pico GND | ++-----------------+ + | + +--------------------+--------------------+ + | | + v v + [ Servo GND ] [ Capacitor - ] + (Brown) + ++-----------------+ +| Pico GPIO 6 | ---> [ Servo Signal ] (Orange) ++-----------------+ +``` + +### Why the Capacitor? + +The **1000 uF capacitor** acts as a tiny battery: + +- Absorbs sudden current demands when servo moves +- Prevents voltage drops that could reset the Pico +- Smooths out electrical noise + +--- + +## Part 8: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. A Raspberry Pi Pico Debug Probe +3. Ghidra installed (for static analysis) +4. Python installed (for UF2 conversion) +5. A serial monitor (PuTTY, minicom, or screen) +6. An SG90 servo motor +7. A 1000 uF 25V capacitor +8. The sample projects: `0x001d_static-conditionals` and `0x0020_dynamic-conditionals` + +### Hardware Setup + +Connect your servo like this: + +| Servo Wire | Pico 2 Pin | +| --------------- | ---------- | +| Brown (GND) | GND | +| Red (VCC) | VBUS (5V) | +| Orange (Signal) | GPIO 6 | + +```text +Hardware Setup: + + Pico 2 Servo SG90 Capacitor (1000uF 25V) ++----------+ +-------------+ +-------------+ +| | | | | | +| GPIO 6 | -------> | Signal (Org)| | | +| | | | | | +| VBUS 5V | -------> | VCC (Red) | | | +| | | | | | | +| | +----> | | -----> | + | +| | | | | | +| GND | -------> | GND (Brn) | | | +| | | | | | | +| | +----> | | -----> | - | ++----------+ +-------------+ +-------------+ +``` + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x001d_static-conditionals/ +| +-- build/ +| | +-- 0x001d_static-conditionals.uf2 +| | +-- 0x001d_static-conditionals.bin +| +-- main/ +| | +-- 0x001d_static-conditionals.c +| +-- servo.h ++-- 0x0020_dynamic-conditionals/ +| +-- build/ +| | +-- 0x0020_dynamic-conditionals.uf2 +| | +-- 0x0020_dynamic-conditionals.bin +| +-- main/ +| | +-- 0x0020_dynamic-conditionals.c +| +-- servo.h ++-- uf2conv.py +``` + +--- + +## Part 9: Hands-On Tutorial - Static Conditionals Code + +### Step 1: Review the Source Code + +Let's examine the static conditionals code: + +**File: `0x001d_static-conditionals.c`** + +```c +#include +#include "pico/stdlib.h" +#include "servo.h" + +#define SERVO_GPIO 6 + +int main(void) { + stdio_init_all(); + + int choice = 1; // STATIC - never changes! + + servo_init(SERVO_GPIO); + + while (true) { + // if/else conditional + if (choice == 1) { + printf("1\r\n"); + } else if (choice == 2) { + printf("2\r\n"); + } else { + printf("?\r\n"); + } + + // switch/case conditional + switch (choice) { + case 1: + printf("one\r\n"); + break; + case 2: + printf("two\r\n"); + break; + default: + printf("??\r\n"); + } + + // Servo movement + servo_set_angle(0.0f); + sleep_ms(500); + servo_set_angle(180.0f); + sleep_ms(500); + } +} +``` + +### Step 2: Understand the Program Flow + +Since `choice = 1` and NEVER changes: + +```text ++-------------------------+ +| Start Loop Iteration | <-----------------------------------+ ++-------------------------+ | + | | + v | + [ choice == 1 ] -- TRUE --> +-------------------------+ | + | print '1' | | + +-------------------------+ | + | | + v | + [ switch case 1 ] | + | MATCH | + v | + +-------------------------+ | + | print 'one' | | + +-------------------------+ | + | | + v | + +-------------------------+ | + | Move servo to 0° | | + +-------------------------+ | + | | + v | + +-------------------------+ | + | Wait 500ms | | + +-------------------------+ | + | | + v | + +-------------------------+ | + | Move servo to 180° | | + +-------------------------+ | + | | + v | + +-------------------------+ | + | Wait 500ms | ---+ + +-------------------------+ +``` + +### Step 3: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x001d_static-conditionals.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 4: Verify It's Working + +**Check the serial monitor (PuTTY at 115200 baud):** +``` +1 +one +1 +one +1 +one +... +``` + +**Watch the servo:** + +- It should sweep from 0° to 180° every second +- The movement is continuous and repetitive + +--- + +## Part 10: Debugging with GDB (Static Conditionals) + +### Step 5: Start OpenOCD (Terminal 1) + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +You should see output indicating OpenOCD connected successfully to your Pico 2 via the Debug Probe. + +### Step 6: Start GDB (Terminal 2) + +Open a **new terminal** and launch GDB with the binary: + +```cmd +arm-none-eabi-gdb build\0x001d_static-conditionals.elf +``` + +### Step 7: Connect to the Remote Target + +In GDB, connect to OpenOCD: + +```gdb +target extended-remote :3333 +``` + +### Step 8: Halt the Running Binary + +Stop the processor: + +```gdb +monitor halt +``` + +### Step 9: Examine Main Function + +Disassemble around main to see the conditionals: + +```gdb +disassemble 0x10000234,+200 +``` + +Look for comparison and branch instructions that implement the if/else and switch logic. + +### Step 10: Set a Breakpoint at Main + +```gdb +break *0x10000234 +``` + +Reset and run to hit the breakpoint: + +```gdb +monitor reset halt +continue +``` + +### Step 11: Find the Comparison Instructions... Or Not! + +To see the assembly instructions as you execute them, tell GDB to display the current instruction automatically: + +```gdb +display/i $pc +nexti +``` + +Keep pressing **Enter** to repeat the `nexti` command and watch the instructions. + +**Wait, where is the `cmp` instruction?!** +You might notice that there is NO `cmp` instruction comparing our `choice` variable anywhere! Why? Because we hardcoded `int choice = 1;` at the start of our C code and never changed it. + +The C compiler is smart (even at basic optimization levels). It realized the `if (choice == 1)` condition would *always* be true, and the `else` conditions would *never* happen. Instead of wasting CPU cycles checking a condition that never changes, the compiler **optimized out the check entirely**! It just compiled the code inside the `choice == 1` block unconditionally. + +This is the defining characteristic of a "Static Conditional"—the condition is resolved at compile-time, not run-time! + +### Step 12: Examine the Printf/Puts Arguments + +If you look closely at your disassembly, you'll notice there are no `printf` calls! The compiler optimized our simple `printf` statements into `puts` (specifically `__wrap_puts` in the Pico SDK) because they didn't contain any complex formatting variables. + +When you reach a `bl <__wrap_puts>` instruction, check `r0` for the string address: + +```gdb +x/s $r0 +``` + +You should see strings like `"1\r"` or `"one\r"`. + +*(Wait, what happened to the `\n`? Because the `puts` function automatically adds a newline to the end of whatever it prints, the compiler cleverly trimmed the `\n` out of the string literal in memory to save space!)* + +### Step 13: Watch the Servo Commands + +Let's set a breakpoint on `servo_set_angle`. How do you know the address? If you look at your `main` disassembly, you can find the `bl` instruction calling it (for example, `0x10000310`). + +But hardcoded addresses change every time you recompile! Luckily, GDB is smart enough to resolve function names directly from the ELF file: + +```gdb +break servo_set_angle +continue +``` + +Check the argument passed to the function. You might assume the float is in `s0`, but check out the very first instruction of `servo_set_angle`: + +`vmov s14, r0` + +Because of how the ARM compiler handles arguments, the floating-point angle is actually passed into the function via the standard integer register `r0`. The `vmov` instruction immediately moves it from `r0` into the floating-point register `s14` so the math unit can use it! + +To see the angle, you can ask GDB to interpret the raw hex value in `r0` as a float. You can also step forward (`nexti` or `n`) to let the `vmov` execute, and then check `s14` directly! + +Here is exactly what that process looks like in your GDB terminal (assuming you hit `continue` to catch the second call where the angle is 180): + +```gdb +=> 0x10000310 : vmov s14, r0 +(gdb) print /f $r0 +$2 = 180 +(gdb) nexti +=> 0x10000314 : push {r4, r5, lr} +(gdb) info registers s14 +s14 180 (raw 0x43340000) +``` + +*(Note: On your very first breakpoint hit, `print /f $r0` will just show `0` because the first call in the C code is `servo_set_angle(0)`!)* + +### Step 14: Examine the Timing Delay + +Set a breakpoint on `sleep_ms` (using the function name, not a hardcoded address!) and check the delay value: + +```gdb +break sleep_ms +continue +info registers r0 +``` + +You should see `0x1f4` (500 decimal) for the 500ms delay. + +### Step 15: Watch the Loop Iterate + +Because this loop contains `sleep_ms(500)` calls, trying to use `nexti 100` to step forward will cause GDB to "hang" (either because it's waiting for multiple seconds of sleep to finish, or because GDB stepping interferes with the Pico's hardware timer interrupts!). + +Instead, since we already have breakpoints set on `servo_set_angle` and `sleep_ms`, just type `continue`! + +```gdb +continue +``` + +Every time you type `continue` (or press **Enter** to repeat it), you will see the CPU safely jump to the next function call. Because this is a *Static Conditional*, it will never hit a `cmp` instruction or take a different branch—it just bounces between `servo_set_angle` and `sleep_ms` forever! + +### Step 16: Exit GDB + +When done exploring: + +```gdb +quit +``` + +--- + +## Part 11: Setting Up Ghidra for Static Conditionals + +### Step 17: Start Ghidra + +Open a terminal and type: + +```cmd +ghidraRun +``` + +### Step 18: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x001d_static-conditionals` +5. Click **Finish** + +### Step 19: Import the Binary + +1. Open your file explorer +2. Navigate to the `0x001d_static-conditionals/build/` folder +3. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 20: Configure the Binary Format + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` +3. Click **OK** + +### Step 21: Analyze the Binary + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete. + +--- + +## Part 12: Resolving Functions in Ghidra (Static) + +### Step 22: Navigate to Main + +1. Press `G` (Go to address) and type `10000234` +2. Right-click -> **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +### Step 23: Resolve stdio_init_all + +At address `0x10000236`: + +1. Double-click on the called function +2. Right-click -> **Edit Function Signature** +3. Change to: `bool stdio_init_all(void)` +4. Click **OK** + +### Step 24: Resolve servo_init + +Look for a function call where `r0` is loaded with `0x6` (GPIO pin 6): + +```assembly +movs r0, #0x6 ; GPIO pin 6 +bl FUN_1000027c ; servo_init +``` + +1. Right-click -> **Edit Function Signature** +2. Change to: `void servo_init(uint pin)` +3. Click **OK** + +### Step 25: Resolve puts + +Look for function calls that load string addresses into `r0`: + +```assembly +ldr r0=>DAT_10001c54 ,[DAT_10000274 ] = 00000D31h +bl FUN_10001884 undefined FUN_10001884() +``` + +**How do we know it's puts?** + +- It takes a single string argument +- The hex `0x31` is ASCII "1" +- The hex `0x0d` is carriage return `"\r"` +- We saw "1" echoed in PuTTY + +1. Right-click -> **Edit Function Signature** +2. Change to: `int puts(char *s)` +3. Click **OK** + +### Step 26: Resolve servo_set_angle + +Look for a function call (like `bl FUN_10000310`) that occurs right after the float arguments are loaded into `r0`. + +```assembly +mov r0,r5 +bl FUN_10000310 undefined FUN_10000310() +``` + +If you double-click the `FUN_10000310` label to look inside the function, you'll find a section of code checking the pulse limits: + +```assembly +cmp.w r3,#0x7d0 +it cs +mov.cs.w r3,#0x7d0 +cmp.w r3,#0x3e8 +it cc +mov.cc.w r3,#0x3e8 +``` + +These values are: + +- `0x7D0` (2000 decimal) - maximum pulse width +- `0x3E8` (1000 decimal) - minimum pulse width + +These are the servo pulse limits! + +1. Right-click -> **Edit Function Signature** +2. Change to: `void servo_set_angle(float degrees)` +3. Click **OK** + +### Step 27: Resolve sleep_ms + +Look for a function where `r0` is loaded with `0x1f4` (500 decimal): + +```assembly +mov.w r0,#0x1f4 +bl FUN_10000e20 undefined FUN_10000e20() +``` + +1. Right-click -> **Edit Function Signature** +2. Change to: `void sleep_ms(uint ms)` +3. Click **OK** + +--- + +## Part 13: Hacking Static Conditionals + +### Step 28: Open the Bytes Editor + +1. Click **Window** -> **Bytes** +2. A new panel appears showing raw hex bytes +3. Click the pencil icon to enable editing + +### Step 29: Hack #1 - Change "1" to "2" + +First, we need to find the string "1" in the binary. + +1. Go back to your `main` assembly code and look for the first `puts` call. +2. In the `ldr` instruction right before it, look for the reference next to the arrow: `r0=>DAT_10001c54`. **Double-click exactly on `DAT_10001c54`**. *(Warning: Do NOT click the reference inside the brackets like `[DAT_10000274]`, or you'll end up in the pointer table instead of the string!)* +3. The Listing and Bytes windows will automatically jump to the string's exact address! +4. Look at your **Bytes** window. You should see the byte `31` (which is ASCII for "1"). +5. Click on the `31` and type `32` to overwrite it (which is ASCII for "2"). + +### Step 30: Hack #2 - Change "one" to "fun" + +Next, let's change the word "one" to "fun": + +1. Go back to `main` and look for the second `puts` call. +2. In the `ldr` instruction, double-click the `DAT_10001c5c` reference next to the arrow (again, ignore the one in the brackets!). +3. Look at the **Bytes** window again. You'll find the bytes `6f 6e 65` (which are ASCII for "o-n-e"). +4. Click on the `6f` byte and type `66 75 6e` on your keyboard to overwrite those three bytes with "f-u-n". + +**ASCII Reference:** + +| Character | Hex | +| --------- | ---- | +| o | 0x6f | +| n | 0x6e | +| e | 0x65 | +| f | 0x66 | +| u | 0x75 | +| n | 0x6e | + +### Step 31: Hack #3 - Speed Up the Servo + +Let's change the 500ms delay to a 100ms delay. Since the compiler packed the `500` directly into a `mov.w` instruction, we can't just find it in the data section. Instead, let's use Ghidra to rewrite the instruction! + +**Method A: Bytes Window Workflow (Recommended)** +1. Ensure the Bytes window is open (**Window** -> **Bytes: 0x001d_static-conditionals.bin**). +2. Click the **pencil icon** (**Toggle Edit Mode**) in the Bytes window toolbar. +3. In the **Listing** window, locate the first `mov.w r0,#0x1f4` instruction (right before calling `sleep_ms`) and press **`C`** (**Clear Code Bytes**). +4. In the **Bytes** window at that offset, change the immediate byte from `f4` (`0x1f4`) to `64` (`0x64` = 100). +5. In the **Listing** window, click back on the address and press **`D`** (**Disassemble**). +6. Repeat for the second `mov.w r0,#0x1f4` instruction. + +**Method B: Patch Instruction** +1. Right-click the first `mov.w r0,#0x1f4` instruction and select **Patch Instruction** (or press `Ctrl+Shift+G`). +2. Delete the `#0x1f4` and type `#0x64` (which is 100 in hex). Press **Enter**! +3. Repeat this for the second `mov.w r0,#0x1f4` instruction. + +**Before:** 500ms delay (servo moves slowly) +**After:** 100ms delay (servo moves FAST!) + +### Step 32: Export and Flash + +When exporting from Ghidra, you must make sure to save the file inside your `build/` directory so the python script can find it! + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. **IMPORTANT:** Click the `...` next to the Output File field and navigate into your `0x001d_static-conditionals/build/` folder! +4. Save the file as `0x001d_static-conditionals-h.bin`. +5. Click **OK** + +Convert and flash (make sure your terminal is inside the `0x001d_static-conditionals/` folder, NOT the `build/` folder!): + +```cmd +python ..\uf2conv.py build\0x001d_static-conditionals-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +*(Troubleshooting: If you get `FileNotFoundError` for the `.bin` file, it means you didn't save the exported file into the `build/` folder! Go back to Ghidra and export it again. If you get an error that Python can't open `..\uf2conv.py`, it means you accidentally `cd`'d into the `build/` folder. Type `cd ..` to go back up one directory and run the command again!)* + +### Step 33: Verify the Hacks + +**Serial output now shows:** +``` +2 +fun +2 +fun +... +``` + +**The servo now moves 5x faster!** It's spinning back and forth like crazy! + +--- + +## Part 14: Dynamic Conditionals - The Source Code + +### Step 34: Review the Dynamic Code + +**File: `0x0020_dynamic-conditionals.c`** + +```c +#include +#include "pico/stdlib.h" +#include "servo.h" + +#define SERVO_GPIO 6 + +int main(void) { + stdio_init_all(); + + uint8_t choice = 0; // DYNAMIC - changes with user input! + + servo_init(SERVO_GPIO); + + while (true) { + choice = getchar(); // Wait for keyboard input + + if (choice == 0x31) { // '1' + printf("1\r\n"); + } else if (choice == 0x32) { // '2' + printf("2\r\n"); + } else { + printf("??\r\n"); + } + + switch (choice) { + case '1': + printf("one\r\n"); + servo_set_angle(0.0f); + sleep_ms(500); + servo_set_angle(180.0f); + sleep_ms(500); + break; + case '2': + printf("two\r\n"); + servo_set_angle(180.0f); + sleep_ms(500); + servo_set_angle(0.0f); + sleep_ms(500); + break; + default: + printf("??\r\n"); + } + } +} +``` + +### Step 35: Understand the Dynamic Behavior + +| User Types | Output | Servo Action | +| ------------- | ----------- | ------------ | +| '1' (0x31) | "1" + "one" | 0° -> 180° | +| '2' (0x32) | "2" + "two" | 180° -> 0° | +| Anything else | "??" + "??" | No movement | + +### Step 36: Flash and Test + +1. Flash `0x0020_dynamic-conditionals.uf2` +2. Open PuTTY +3. Press '1' - servo sweeps one direction +4. Press '2' - servo sweeps the other direction +5. Press 'x' - prints "??" and no movement + +--- + +## Part 15: Debugging with GDB (Dynamic Conditionals) + +### Step 37: Start OpenOCD (Terminal 1) + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +You should see output indicating OpenOCD connected successfully to your Pico 2 via the Debug Probe. + +### Step 38: Start GDB (Terminal 2) + +Open a **new terminal** and launch GDB with the binary: + +```cmd +arm-none-eabi-gdb build\0x0020_dynamic-conditionals.elf +``` + +### Step 39: Connect to the Remote Target + +In GDB, connect to OpenOCD: + +```gdb +target extended-remote :3333 +``` + +### Step 40: Halt the Running Binary + +Stop the processor: + +```gdb +monitor halt +``` + +### Step 41: Examine Main Function + +Disassemble around main to see the dynamic conditionals: + +```gdb +disassemble 0x10000234,+250 +``` + +Look for the `bl <__wrap_getchar>` call. Because `choice` is now dynamic (based on user input), the compiler *had* to generate the comparison logic! It should look something like this: + +```assembly +bl 0x10001860 <__wrap_getchar> +uxtb r4, r0 +cmp r4, #49 @ 0x31 +beq.n 0x10000270 +cmp r4, #50 @ 0x32 +``` +There they are! The `cmp` instructions checking for `0x31` ('1') and `0x32` ('2'). + +### Step 42: Set a Breakpoint After getchar + +We want to pause execution right after we type a character so we can inspect the comparison. +Find the address of the first `cmp` instruction in your disassembly (in the example above, it's `0x1000024a`) and set a breakpoint: + +```gdb +break *0x1000024a +``` +*(Make sure you use the exact address of the `cmp` instruction from YOUR disassembly!)* + +Reset and continue: + +```gdb +monitor reset halt +continue +``` + +### Step 43: Watch the Input Value + +When you press a key in PuTTY, the breakpoint hits. Check the return value: + +```gdb +info registers r0 +``` + +If you pressed '1', you should see `0x31`. If you pressed '2', you should see `0x32`. + +### Step 44: Execute the Comparison + +Right now, GDB is paused *before* the `cmp` instruction runs (the `=>` arrow points to the instruction that will execute *next*). + +To see the result of the comparison, we must execute the `cmp` instruction by stepping forward exactly once: + +```gdb +display/i $pc +stepi +``` + +Notice that the `=>` arrow has now moved to the `beq.n` (Branch if Equal) instruction. The `cmp` instruction has just executed. + +### Step 45: Examine the Branch Decisions + +Now that the comparison has run, we can look at the CPU's condition flags to see what happened: + +```gdb +info registers xpsr +``` +*(Note: Older ARM chips call this `cpsr`, but Cortex-M chips like the Pico's RP2350 call it `xpsr`!)* + +The zero flag (`Z`) determines if the branch is taken. The flags are stored in the highest nibble (the first hex digit) of the `xpsr` register in the order `N Z C V`. + +If you typed '1', the comparison resulted in zero difference, setting the `Z` flag to 1. You should see `xpsr` start with a `6` (like `0x69000000`). `6` in binary is `0110`, which means the `Z` flag (the second bit) is 1! The `beq.n` instruction will see this flag and take the branch. + +### Step 46: Watch Different Input Paths + +Continue and press different keys to see how the program takes different branches: + +```gdb +continue +``` + +Press '2' in PuTTY, then examine registers again. + +### Step 47: Examine Servo Control + +Set a breakpoint on servo_set_angle: + +```gdb +break *0x10000280 +continue +``` + +Check the angle value: + +```gdb +info registers s0 +``` + +### Step 48: Exit GDB + +When done exploring: + +```gdb +quit +``` + +--- + +## Part 16: Setting Up Ghidra for Dynamic Conditionals + +### Step 49: Create New Project + +1. Create project: `0x0020_dynamic-conditionals` +2. Import the `.bin` file +3. Configure as ARM Cortex, base address `10000000` +4. Analyze + +### Step 50: Navigate to Main + +Press `G` and go to `10000234`. + +### Step 51: Resolve Functions + +Follow the same process: + +1. **main** at `0x10000234` -> `int main(void)` +2. **stdio_init_all** -> `bool stdio_init_all(void)` +3. **servo_init** -> `void servo_init(uint pin)` +4. **puts** -> `int puts(char *s)` +5. **servo_set_angle** -> `void servo_set_angle(float degrees)` +6. **sleep_ms** -> `void sleep_ms(uint ms)` + +### Step 52: Identify getchar + +Look for a function that: + +- Returns a value in `r0` +- That value is then compared against `0x31` ("1") + +```assembly +bl FUN_10001860 undefined FUN_10001860() +uxtb r4,r0 +cmp r4,#0x31 +beq LAB_10000270 +``` + +1. Right-click -> **Edit Function Signature** +2. Change to: `int getchar(void)` +3. Click **OK** + +### Step 53: Identify Hardware Addresses + +Double-click into `stdio_init_all` and look for hardware addresses: + +```assembly +ldr r0, =0x40070000 ; UART0 base address +``` + +Check the RP2350 datasheet Section 2.2 (Address Map): + +- `0x40070000` = UART0 + +This confirms it's a UART initialization function! + +--- + +## Part 17: Understanding Branch Instructions + +### ARM Branch Instructions + +| Instruction | Meaning | Condition | +| ----------- | ---------------------- | ------------------ | +| `b` | Branch (always) | Unconditional jump | +| `beq` | Branch if Equal | Zero flag set | +| `bne` | Branch if Not Equal | Zero flag clear | +| `bgt` | Branch if Greater Than | Signed greater | +| `blt` | Branch if Less Than | Signed less | + +### How Conditionals Become Branches + +```c +if (choice == 0x31) { + printf("1"); +} +``` + +Becomes: + +```assembly +cmp r4, #0x31 ; Compare choice to '1' +bne skip_printf ; If NOT equal, skip the printf +; ... printf code here ... +skip_printf: +``` + +```text ++---------------------------------+ +| cmp r4, #0x31 | +| Sets flags based on r4 - 0x31 | ++---------------------------------+ + | + v + [ beq target_address ] + | + +--------+--------+ + | | + If r4 == 0x31 If r4 != 0x31 + | | + v v ++---------------+ +----------------------------+ +| Jump to | | Continue to | +| target_address| | next instruction | ++---------------+ +----------------------------+ +``` + +--- + +## Part 18: Advanced Hacking - Creating Stealth Commands + +### The Goal + +We want to create **secret commands** that: + +1. Respond to 'x' and 'y' instead of '1' and '2' +2. Move the servo WITHOUT printing anything +3. Leave NO trace in the terminal + +### Step 54: Plan the Patches + +**Original behavior:** + +- '1' (0x31) -> prints "1" and "one", moves servo +- '2' (0x32) -> prints "2" and "two", moves servo + +**Hacked behavior:** + +- 'x' (0x78) -> moves servo SILENTLY (replacing '1') +- 'y' (0x79) -> moves servo SILENTLY (replacing '2') + +### Step 55: Change Comparison Values + +Navigate to the `main` function and find the two `cmp` instructions right after `getchar`: + +Address `1000024a` contains `cmp r4,#0x31` (`31 2c`), and address `1000024e` contains `cmp r4,#0x32` (`32 2c`). + +**Method A: Bytes Window Workflow (Recommended)** +To ensure clean disassembly and prevent assembler context conflicts: +1. Ensure the Bytes window is open (**Window** -> **Bytes: 0x001d_static-conditionals.bin**). +2. Click the **pencil icon** (**Toggle Edit Mode**) in the Bytes window toolbar to enable editing. +3. In the **Listing** window, click on address `1000024a` and press **`C`** (**Clear Code Bytes**). +4. In the **Bytes** window at offset `1000024a`, click on byte `31` and change it to **`78`** (ASCII 'x'). +5. In the **Listing** window, click back on address `1000024a` and press **`D`** (**Disassemble**). +6. In the **Listing** window, click on address `1000024e` and press **`C`** (**Clear Code Bytes**). +7. In the **Bytes** window at offset `1000024e`, click on byte `32` and change it to **`79`** (ASCII 'y'). +8. In the **Listing** window, click back on address `1000024e` and press **`D`** (**Disassemble**). + +**Method B: Patch Instruction** +1. At address `1000024a`, right-click `cmp r4,#0x31`, select **Patch Instruction**, and change it to `cmp r4,#0x78` (which is ASCII 'x'). +2. At address `1000024e`, right-click `cmp r4,#0x32`, select **Patch Instruction**, and change it to `cmp r4,#0x79` (which is ASCII 'y'). + +### Step 56: Redirect Branches to Skip Prints + +For the stealth keys, we need to jump PAST the printf calls directly to the servo code. + +**Original flow:** +``` +compare -> branch -> printf("1") -> printf("one") -> servo code +``` + +**Hacked flow:** +``` +compare 'x' -> branch -> [skip prints] -> servo code +``` + +Use **Patch Instruction** to rewrite the `beq` target addresses: + +1. At address `1000024c`, you will see `beq LAB_10000270`. + - `10000270` is the block that prints "1". We want to skip it! + - Right-click, select **Patch Instruction**, and change it to `beq 0x1000027c` (this jumps straight to the `mov r0,r6` servo code!). +2. At address `10000250`, you will see `beq LAB_1000029a`. + - `1000029a` is the block that prints "2". + - Right-click, select **Patch Instruction**, and change it to `beq 0x100002a6` (this jumps straight to the `mov r0,r5` servo code!). + +### Step 57: NOP Out Print Calls (Alternative Method) + +**NOP** (No Operation) is an instruction that does absolutely nothing. Hackers use it to "erase" code without changing the size of the binary! Since we already redirected the branches to skip the prints, this is technically redundant, but let's do it anyway just to learn the technique. + +The `bl` instruction is 32-bits (4 bytes) long. Standard Thumb `nop` instructions are only 16-bits (2 bytes) long. If you try to patch a 4-byte instruction with a 2-byte instruction, Ghidra's assembler gets very confused and corrupts the code. + +To fix this, we use the special 32-bit version of NOP: `nop.w` (Wide NOP). + +1. In the Listing view, right-click the `bl FUN_10001954` instruction at `10000272`. +2. Select **Patch Instruction**. +3. Type `nop.w` (don't forget the `.w`!) and hit Enter. +4. You will see the entire 4-byte instruction neatly get replaced by a single 32-bit NOP. +5. Repeat this for the second `bl` instruction at `10000278`. + +### Step 58: Summary of Control Flow Patches + +Here is a quick summary of the stealth command patches we just applied to the control flow: + +| Location | Original Action | Patched Action | Purpose | +| ---------- | -------------------- | -------------------- | ---------------------------- | +| `1000024a` | `cmp r4,#0x31` | `cmp r4,#0x78` | Check for 'x' instead of '1' | +| `1000024e` | `cmp r4,#0x32` | `cmp r4,#0x79` | Check for 'y' instead of '2' | +| `1000024c` | `beq LAB_10000270` | `beq LAB_1000027c` | Skip printf for 'x' | +| `10000250` | `beq LAB_1000029a` | `beq LAB_100002a6` | Skip printf for 'y' | + +### Step 59: One Final Hack - Modify the Angle + +Let's also change the servo's movement angle from 180° to 30° for fun! + +If you look back near the top of the `main` function (around address `10000242`), you'll see this instruction: +`ldr r5,[DAT_100002c4] = 43340000h` + +The compiler stored the 180.0 float value (`0x43340000`) in a literal pool at address `100002c4`. To change the angle, we just need to overwrite that raw data! + +**Original:** `0x43340000` (180.0f) +**New:** `0x41f00000` (30.0f) + +Here is how to apply the patch: + +1. Press `G` and jump to address `100002c4`. +2. In your **Bytes** window (make sure the Pencil icon is still clicked!), you will see the raw little-endian bytes: `00 00 34 43`. +3. Click on the first `00` and type `00 00 f0 41`. +4. The Listing view will instantly update to show the new `41f00000` value! + +*(For the math nerds, here is how we calculated `0x41f00000` manually using the IEEE-754 standard):* + +**Calculation for 30.0f:** +``` +30.0 = 1.875 * 2^4 +Sign = 0 +Exponent = 127 + 4 = 131 = 0x83 +Mantissa = 0.875 = 0x700000 + +Binary: 0 10000011 11100000000000000000000 +Hex: 0x41f00000 +Little-endian: 00 00 f0 41 +``` + +### Step 60: Export and Test + +When exporting, make sure to save it in your `build/` folder! + +1. Export as `0x0020_dynamic-conditionals-h.bin` inside `build/`. +2. Convert and flash (run from the `0x0020_dynamic-conditionals` directory!): + +```cmd +python ..\uf2conv.py build\0x0020_dynamic-conditionals-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +3. Flash and test: + - Press 'x' -> NO OUTPUT, but servo moves silently! + - Press 'y' -> NO OUTPUT, but servo moves silently! + - (The original '1' and '2' keys no longer work!) + +--- + +## Part 19: Summary and Review + +### What We Accomplished + +1. **Learned static vs dynamic conditionals** - Fixed vs runtime-determined values +2. **Understood if/else and switch/case** - Two ways to branch in C +3. **Mastered PWM calculations** - 150MHz to 50Hz servo signal +4. **Identified conditional branches in assembly** - beq, bne, cmp instructions +5. **Hacked string literals** - Changed "one" to "fun" +6. **Modified timing values** - Sped up servo from 500ms to 100ms +7. **Created stealth commands** - Hidden 'x' and 'y' keys +8. **NOPed out print statements** - Removed logging for stealth +9. **Redirected branch targets** - Changed program flow + +### Static vs Dynamic Summary + +```text + Static Conditionals + ------------------- + - Variable set once, never changes + - Same path taken every iteration + - Compiler may optimize out dead branches + - Example: int choice = 1; if (choice == 1) + + Dynamic Conditionals + -------------------- + - Variable changes based on input/sensors + - Different paths taken based on runtime state + - All branches must remain in binary + - Example: choice = getchar(); if (choice == '1') +``` + +### PWM Calculation Summary + +```text ++---------+ +-------------+ +-----------+ +--------------+ +| Angle | Formula | Pulse Width | 1us= | PWM Ticks | Servo | Servo Motion | +| degrees | ------> | µs | 1 tick | | Motion | | ++---------+ +-------------+ ------> +-----------+ ------> +--------------+ + | | | | + 0° ---------------- 1000 µs ------------- 1000 ticks --------- Fully CCW + 90° ---------------- 1500 µs ------------- 1500 ticks --------- Center + 180° ---------------- 2000 µs ------------- 2000 ticks --------- Fully CW +``` + +### Key Memory Addresses + +| Memory Address | Description | +| -------------- | ------------------------ | +| `0x10000234` | main() function | +| `0x40070000` | UART0 hardware registers | +| `0x1f4` | 500 (sleep_ms delay) | +| `0x7D0` | 2000 (max pulse width) | +| `0x3E8` | 1000 (min pulse width) | +| `0x43340000` | 180.0f (max angle) | + +--- + +--- + +## Key Takeaways + +1. **Static conditionals have fixed outcomes** - The same path always executes + +2. **Dynamic conditionals respond to input** - Different paths based on runtime state + +3. **PWM frequency = 50Hz for servos** - One pulse every 20ms + +4. **Pulse width encodes position** - 1ms=0°, 1.5ms=90°, 2ms=180° + +5. **beq = branch if equal** - Jumps when comparison matches + +6. **bne = branch if not equal** - Jumps when comparison doesn't match + +7. **NOP erases code without changing size** - `00 bf` in ARM Thumb + +8. **Branch targets can be redirected** - Change where code jumps to + +9. **IEEE-754 is needed for angles** - Floats have specific bit patterns + +10. **Stealth requires removing ALL output** - NOP out printf AND puts + +--- + +## Glossary + +| Term | Definition | +| ----------------------- | --------------------------------------------------- | +| **beq** | Branch if Equal - ARM conditional jump | +| **bne** | Branch if Not Equal - ARM conditional jump | +| **Dynamic Conditional** | Condition that changes based on runtime input | +| **Duty Cycle** | Percentage of time signal is HIGH | +| **getchar()** | C function that reads one character from input | +| **NOP** | No Operation - instruction that does nothing | +| **PWM** | Pulse Width Modulation - variable duty cycle signal | +| **SG90** | Common hobby servo motor model | +| **Static Conditional** | Condition with fixed/predetermined outcome | +| **switch/case** | C structure for multiple discrete value comparisons | +| **Wrap Value** | PWM counter maximum before reset | + +--- + +## Additional Resources + +### ASCII Reference Table + +| Character | Hex | Decimal | +| --------- | ---- | ------- | +| '0' | 0x30 | 48 | +| '1' | 0x31 | 49 | +| '2' | 0x32 | 50 | +| 'x' | 0x78 | 120 | +| 'y' | 0x79 | 121 | +| `'\r'` | 0x0d | 13 | +| `'\n'` | 0x0a | 10 | + +### IEEE-754 Common Angles + +| Angle | IEEE-754 Hex | Little-Endian Bytes | +| ----- | ------------ | ------------------- | +| 0.0 | 0x00000000 | 00 00 00 00 | +| 30.0 | 0x41f00000 | 00 00 f0 41 | +| 45.0 | 0x42340000 | 00 00 34 42 | +| 90.0 | 0x42b40000 | 00 00 b4 42 | +| 135.0 | 0x43070000 | 00 00 07 43 | +| 180.0 | 0x43340000 | 00 00 34 43 | + +### ARM Thumb NOP Encodings + +| Instruction | Encoding | Size | +| ----------- | ------------- | ------- | +| `nop` | `00 bf` | 2 bytes | +| `nop.w` | `00 f0 00 80` | 4 bytes | + +### RP2350 Key Addresses + +| Address | Peripheral | +| ------------ | ---------- | +| `0x40070000` | UART0 | +| `0x40078000` | UART1 | +| `0x40050000` | PWM | + +--- + +## Real-World Implications + +### Why Stealth Commands Matter + +The ability to create hidden commands has serious implications: + +**Legitimate Uses:** + +- Factory test modes +- Debugging interfaces +- Emergency recovery features + +**Malicious Uses:** + +- Backdoors in firmware +- Hidden surveillance features +- Unauthorized control of systems + +### Real-World Example + +Imagine a drone with hacked firmware: + +- Normal keys ('1', '2') control it visibly with logging +- Hidden keys ('x', 'y') control it with NO log entries +- An attacker could operate the drone while security monitors show nothing + +### The Nuclear Fuel Rod Analogy + +A fast-moving servo is like a nuclear fuel rod: + +- Both are small components with immense power +- Both require precise control to prevent damage +- Both can "go critical" if pushed beyond limits +- Both teach the importance of safety margins + +--- + +**Remember:** The techniques you learned today demonstrate how conditional logic can be manipulated at the binary level. Understanding these attacks helps us build more secure embedded systems. Always use your skills ethically and responsibly! + +Happy hacking! diff --git a/WEEK10/WEEK10.pdf b/WEEK10/WEEK10.pdf new file mode 100644 index 0000000..8f36147 Binary files /dev/null and b/WEEK10/WEEK10.pdf differ diff --git a/WEEK10/slides/WEEK10-IMG00.svg b/WEEK10/slides/WEEK10-IMG00.svg new file mode 100644 index 0000000..84c608d --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 10 + + +Conditionals in Embedded Systems: +Debugging and Hacking Static & Dynamic +Conditionals w/ SG90 Servo Motor PWM + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK10/slides/WEEK10-IMG01.svg b/WEEK10/slides/WEEK10-IMG01.svg new file mode 100644 index 0000000..38d8eb0 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG01.svg @@ -0,0 +1,82 @@ + + + + +Conditionals Overview +Static vs Dynamic Decision Making + + + +What Are Conditionals? +Structures that let programs choose +different paths based on conditions + + + +Static Conditional +Value fixed at compile time + + +int choice = 1; +// never changes +if (choice == 1) +printf("1"); +// always runs +else printf("2"); +// never runs + + + +Dynamic Conditional +Value changes at runtime + + +choice = getchar(); +// user types a key +if (choice == '1') +printf("1"); +// maybe runs + + + +if/else + +Feature +Description + +Condition +Any boolean expr +Values +Ranges, complex logic +Fall-through +No +Best for +2-3 conditions + + + +switch/case + +Feature +Description + +Condition +Single variable +Values +Discrete only +Fall-through +Yes (no break) +Best for +Many conditions + diff --git a/WEEK10/slides/WEEK10-IMG02.svg b/WEEK10/slides/WEEK10-IMG02.svg new file mode 100644 index 0000000..cbd97b4 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG02.svg @@ -0,0 +1,89 @@ + + + + +Static Conditionals +Fixed Outcome -- Same Path Every Time + + + +Static Code Pattern + +int choice = 1; +// NEVER changes +while (true) { +if (choice == 1) +printf("1"); +else if (choice == 2) +printf("2"); +// dead code +else + + + +Execution Flow + + +choice == 1? + + +YES + + +print "1" + +NO (never taken) + + + +choice == 2? + +NO (never reached) + + +print "?" + +Only ONE path ever executes! + + + +Every Loop Iteration (Always the Same) +1. if(1==1) --> TRUE +2. print "1" +3. switch(1) case 1 +4. print "one" +5. servo 0deg +6. sleep 500ms +7. servo 180deg + + + +Serial Output (Forever) + +1 +one +1 +// repeats forever + + + +Servo Motion (Forever) +0deg +--> +180deg +--> +0deg +Sweeps back and forth, 500ms each +Continuous, predictable motion + diff --git a/WEEK10/slides/WEEK10-IMG03.svg b/WEEK10/slides/WEEK10-IMG03.svg new file mode 100644 index 0000000..9a22eeb --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG03.svg @@ -0,0 +1,95 @@ + + + + +Dynamic Conditionals +Runtime Input Changes the Path + + + +Dynamic Code Pattern + +uint8_t choice = 0; +while (true) { +choice = getchar(); +// waits for keyboard input +if (choice == 0x31) +printf("1"); +else if (choice == 0x32) +printf("2"); + + + +Execution Flow + + +choice = getchar() + + + + +choice=='1'? + +YES + +servo 0-180 + + +NO + + +choice=='2'? + +YES + +servo 180-0 + + + +print "??" +Each iteration can take a DIFFERENT path + + + +getchar() Returns ASCII +'1' = 0x31 +'2' = 0x32 +'x' = 0x78 +'y' = 0x79 +Blocks until +keypress + + + +Input --> Behavior + +Key +Output +Servo + +'1' +"1" + "one" +0deg --> 180deg +'2' +"2" + "two" +180deg --> 0deg + + + +Two Projects +0x001d_static-conditionals +choice = 1 (fixed) +0x0020_dynamic-conditionals +choice = getchar() (user input) + diff --git a/WEEK10/slides/WEEK10-IMG04.svg b/WEEK10/slides/WEEK10-IMG04.svg new file mode 100644 index 0000000..a405f7e --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG04.svg @@ -0,0 +1,96 @@ + + + + +PWM Basics +Pulse Width Modulation for Servo Control + + + +What is PWM? +Rapidly switching a signal ON and OFF +Ratio of on-time to off-time controls power + + +HIGH + + + + + + + + +ON +OFF +ON +OFF + + + +Servo PWM (50Hz = 20ms period) + + +0deg (1ms pulse): + + + +1ms HIGH +19ms LOW + + +90deg (1.5ms pulse): + + + +1.5ms HIGH +18.5ms LOW + + +180deg (2ms pulse): + + + +2ms HIGH +18ms LOW + +Pulse WIDTH determines angle, not duty cycle +Total period always 20ms (50Hz) + + + +Angle to Pulse Width + +Angle +Pulse +Ticks (1MHz) + +0deg +1000us +1000 +90deg +1500us +1500 +180deg +2000us +2000 + + + +Formula +pulse = 1000 + (angle/180) x 1000 +Example for 90deg: +1000 + (90/180) x 1000 += 1500us = 1500 ticks + diff --git a/WEEK10/slides/WEEK10-IMG05.svg b/WEEK10/slides/WEEK10-IMG05.svg new file mode 100644 index 0000000..9499ded --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG05.svg @@ -0,0 +1,83 @@ + + + + +PWM Timing Chain +150MHz System Clock to 50Hz Servo Signal + + + +Clock Division + + +150 MHz Clock + +/ 150 + + + + +1 MHz PWM + +1 tick = 1us + + + +Step 1: 150,000,000 / 150 = 1,000,000 Hz +Each PWM tick = exactly 1 microsecond + +Step 2: Wrap at 20,000 ticks = 20ms = 50Hz +Wrap value = 19,999 + + + +SG90 Servo Motor + +Parameter +Value + +Voltage +4.8V - 6V (use 5V) +Rotation +0deg to 180deg +Pulse Width +1000us - 2000us +Frequency +50Hz (20ms period) + + + +Wiring to Pico 2 + + +Pico + + +SG90 + + + + +GPIO 6 = Signal (Orange) +VBUS 5V = VCC (Red) +GND = GND (Brown) +Add 1000uF capacitor on power! + + + +Power Safety +NEVER use 3.3V pin for servo! +Servos draw 650mA+ (spikes to 1A) +Use VBUS (5V from USB) with 1000uF 25V capacitor + diff --git a/WEEK10/slides/WEEK10-IMG06.svg b/WEEK10/slides/WEEK10-IMG06.svg new file mode 100644 index 0000000..bb7867d --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG06.svg @@ -0,0 +1,55 @@ + + + + +Static Source Code +0x001d_static-conditionals.c + + + +Full Source + + +#include <stdio.h> +#include "pico/stdlib.h" +#include "servo.h" +#define SERVO_GPIO 6 + +int main(void) { +stdio_init_all(); +int choice = 1; +// STATIC! +servo_init(SERVO_GPIO); + +while (true) { +if (choice == 1) +printf("1\r\n"); +else if (choice == 2) +printf("2\r\n"); +// dead code + + + +switch Block + +switch(choice) { +case 1: puts("one"); break; + + +Servo Loop + +servo_set_angle(0.0f); +sleep_ms(500); +// then 180 + diff --git a/WEEK10/slides/WEEK10-IMG07.svg b/WEEK10/slides/WEEK10-IMG07.svg new file mode 100644 index 0000000..edb9558 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG07.svg @@ -0,0 +1,50 @@ + + + + +Dynamic Source Code +0x0020_dynamic-conditionals.c + + + +Full Source + + +#include <stdio.h> +#include "pico/stdlib.h" +#include "servo.h" +#define SERVO_GPIO 6 + +int main(void) { +stdio_init_all(); +uint8_t choice = 0; +// DYNAMIC! +servo_init(SERVO_GPIO); + +while (true) { +choice = getchar(); +// wait for input +if (choice == 0x31) +// '1' +printf("1\r\n"); +else if (choice == 0x32) +// '2' +printf("2\r\n"); + + + +switch Block (with servo control) +case '1': print "one", servo 0-->180, sleep 500ms +case '2': print "two", servo 180-->0, sleep 500ms + diff --git a/WEEK10/slides/WEEK10-IMG08.svg b/WEEK10/slides/WEEK10-IMG08.svg new file mode 100644 index 0000000..295c649 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG08.svg @@ -0,0 +1,101 @@ + + + + +Branch Instructions +How Conditionals Become Assembly + + + +ARM Branch Instructions + +Instr +Meaning +Condition + + +b +Branch always +Always + +beq +Branch if Equal +Z flag set + +bne +Branch if != +Z flag clear + +bgt +Branch if > +Signed > + +blt +Branch if < +Signed < + + + +C --> Assembly + +C code: + +if (choice == 0x31) +printf("1"); + +Assembly: + +cmp r4, #0x31 +// compare +bne skip_printf +// skip if != + + + +Conditional Branch Flow + + +cmp r4, #0x31 + + + + +beq target_addr + + +r4==0x31: JUMP + + +r4!=0x31: continue next + +cmp sets CPU flags, branch reads them + + + +NOP (No Operation) +ARM Thumb NOP: +00 bf +2 bytes +Wide NOP: +00 f0 00 80 +Replaces 4-byte bl instruction + + + +Hacking Branches +Change branch target addr +Redirect program flow +NOP out instructions +Erase code silently + diff --git a/WEEK10/slides/WEEK10-IMG09.svg b/WEEK10/slides/WEEK10-IMG09.svg new file mode 100644 index 0000000..68d47e9 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG09.svg @@ -0,0 +1,83 @@ + + + + +Hacking Conditionals +Strings, Timing, Stealth Commands + + + +Hack 1: Change Strings +Change "1" to "2": +0x31 +--> +0x32 +"one" to "fun": +6f 6e 65 +--> +66 75 6e + + + +Hack 2: Speed Up Servo +Change sleep_ms delay: +0x1F4 (500ms) +--> +0x064 (100ms) + + + +Hack 3: Stealth Commands +Hidden keys move servo with NO output + +Patch +Original +Hacked +Purpose + + +Compare 1 +#0x31 ('1') +#0x78 ('x') +New trigger key + +Compare 2 +#0x32 ('2') +#0x79 ('y') +New trigger key + +puts calls +bl puts +00 bf 00 bf +NOP out prints + + + +Hack 4: Change Angle +180.0f --> 30.0f: +00 00 34 43 +--> +00 00 f0 41 + + + +Stealth Result +'1','2': normal output + servo +'x','y': NO output, servo moves + + + +Workflow +Patch bytes in Ghidra --> export .bin --> convert to UF2 --> flash to Pico + diff --git a/WEEK10/slides/WEEK10-IMG10.svg b/WEEK10/slides/WEEK10-IMG10.svg new file mode 100644 index 0000000..eb92463 --- /dev/null +++ b/WEEK10/slides/WEEK10-IMG10.svg @@ -0,0 +1,85 @@ + + + + +PWM & Servo Hacking +Conditionals, PWM, Servo, and Hacking + + + +Static vs Dynamic + +Static +choice = 1 (fixed) +Same path every iteration +Compiler may optimize + +Dynamic +choice = getchar() +Different paths at runtime + + + +PWM for Servos +150MHz / 150 = 1MHz tick +Wrap 20000 = 50Hz (20ms) +0deg=1000us 90deg=1500us 180deg=2000us +pulse = 1000 + (angle/180) x 1000 + + + +Branch Instructions +cmp r4, #0x31 +Compare +beq target +Jump if equal +bne target +Jump if not equal +NOP = 00 bf (erase code) + + + +Key Values +0x10000234 +main() +0x40070000 +UART0 +0x1F4 +500 (sleep_ms) +0x43340000 +180.0f IEEE-754 + + + +4 Hack Types Applied +String +"one"-->"fun" +Timing +500ms-->100ms +Stealth +NOP out prints +Angle +180.0f-->30.0f + + + +Projects +0x001d_static-conditionals +0x0020_dynamic-conditionals + + +IEEE-754 Angles +0.0f=00000000 90.0f=42b40000 +180.0f=43340000 30.0f=41f00000 + diff --git a/WEEK11/0x0020a_cb/0x0020a_cb.bin b/WEEK11/0x0020a_cb/0x0020a_cb.bin new file mode 100755 index 0000000..70c7ecc Binary files /dev/null and b/WEEK11/0x0020a_cb/0x0020a_cb.bin differ diff --git a/WEEK11/0x0020a_cb/0x0020a_cb.uf2 b/WEEK11/0x0020a_cb/0x0020a_cb.uf2 new file mode 100644 index 0000000..b07d274 Binary files /dev/null and b/WEEK11/0x0020a_cb/0x0020a_cb.uf2 differ diff --git a/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.md b/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.md new file mode 100644 index 0000000..e6401d0 --- /dev/null +++ b/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.md @@ -0,0 +1,155 @@ +# Operation Ghost Light: Classified Intelligence Briefing + +``` ++-----------------------------------------------------------------+ +| TOP SECRET // NOFORN | ++-----------------------------------------------------------------+ +| | +|OPERATION GHOST LIGHT | +| | +|CLASSIFIED BRIEFING: LIVE CHALLENGE 0x05 | +| | +|NATIONAL SECURITY AGENCY / GMU RHET | ++-----------------------------------------------------------------+ +``` + +## 1. The Advice + +INT. NSA EXPLOITATION CELL. 02:15. + +A captured ground-based C-UAS laser dazzler control module sits bolted to the +optical bench inside a sealed laser containment shield. + +On the front panel of the chassis, an alert diode glows a bright, warning red: +`GP16` driven high, indicating the optical emitter is active. Beside it, an +infrared receiver module is wired to `GP5`, ready to receive 38 kHz NEC remote +control pulses. The serial console streams continuous status reports: +`[-] DAZZLER IDLE. ACTIVE IR: 0x00FF00FF`. + +The Director walks in with a cup of coffee and stares through the observation +glass at the red diode. + +**DIRECTOR:** What are we looking at? + +**ANALYST:** An adversary electro-optical countermeasure system. Ground forces +deploy these dazzlers to track and blind friendly aerial surveillance drones. +Adversary operators dynamically configure power levels and tracking modes in the +field using an infrared remote running a customized NEC protocol. + +**DIRECTOR:** Is the emitter live? + +**ANALYST:** Live and strobing. One pulsed command and the optics lock on target. + +**DIRECTOR:** Run it through Buddy. + +**ANALYST:** Already did. Three minutes with the stripped flash image. + +She turns her monitor toward him. + +``` ++-----------------------------------------------------------------+ +| BUDDY // CLASSIFIED EXPLOITATION ASSIST // CONF: 0.99 | ++-----------------------------------------------------------------+ +| ACTION : Transmit standard idle pulse code over IR. | +| MECHANISM : NEC demodulator parser branch at 0x10000280 found.| +| PREDICTION : Transmitting 0x00FF00FF deactivates the emitter. | +| CONFIDENCE : 0.99 | ++-----------------------------------------------------------------+ +``` + +**DIRECTOR:** 0.99. Transmit `0x00FF00FF` and shut down the emitter. + +**ANALYST:** If an operator transmits `0x00FF00FF`, the laser stays live. Buddy +saw the string literal for "IDLE" in `.rodata` and assumed it meant powered down. + +**DIRECTOR:** Buddy says 0.99. + +**ANALYST:** `0x00FF00FF` is merely the idle heartbeat pulse. Buddy never traced +the dynamic dispatch tree. Buddy never found the friendly-fire lockout code +buried in the comparison chain. + +## 2. What Buddy Is + +Buddy is not a person. It is a model. It has parsed more disassembled machine +code than any engineer on earth, and it speaks with total, unhesitating certainty. + +That certainty is lethal when facing active electro-optical weapons. + +Buddy scanned thirty-two kilobytes of stripped ARM Thumb-2 instructions in under +three seconds. It spotted the NEC protocol parser, matched the `0x00FF00FF` frame +against the string table, and declared the dazzler neutralized. + +What Buddy failed to understand is that adversary engineers protect their own +friendly aircraft from being blinded. They build an emergency "Friendly Fire +Lockout" safety into the dynamic conditional tree. When adversary aircraft enter +the engagement envelope, ground crews transmit a specific 32-bit challenge word +that permanently shuts down the emitter and halts the processor in a safe state. + +Transmitting `0x00FF00FF` simply tells the dazzler to remain in standby. The true +lockout command is a secret 32-bit value stored in the literal pool at +`0x10000300`: `0xDEADBEEF`. + +Buddy saw the idle command. Buddy did not verify the ground truth. + +## 3. The Operation + +At 23:40, special operations forces captured an intact adversary laser dazzler +installation before the crew could purge the control firmware. + +The control board is built around a bare-metal RP2350 (ARM Cortex-M33). There +are no debug symbols. There is no operating system. There is no SVD file to label +the registers. All you have is `0x0020a_cb.bin` mapped into Flash at `0x10000000`, +and the physical breadboard hardware in front of you. + +* **Pin 7 (`GP5`)**: Infrared receiver data line (VS1838B demodulator OUT). +* **Pin 20 (`GP15`)**: Simulated IR demodulator test toggle (pull-up to `3V3`). +* **Pin 21 (`GP16`)**: Red LED (`DAZZLER EMITTING // STROBE ACTIVE`). +* **Pin 22 (`GP17`)**: Green LED (`SAFE // FRIENDLY FIRE LOCKOUT CLEARED`). +* **Pin 24 (`GP18`)**: Yellow LED (`HEARTBEAT // IR RECEIVER ACTIVE`). +* **Pin 36 (`3V3`)**: 3.3V power rail (VS1838B VCC and `GP15` pull-up). +* **Pin 38 (`GND`)**: Ground reference. + +Inside this image there is a nested NEC infrared command parser, dynamic +multi-way branch dispatch tables, and a permanent friendly-fire lockout latch +in SRAM. Whatever command actually disables the laser is buried in the stripped +ARM Thumb-2 machine code. + +## 4. The Mandate + +The Director crosses his arms and stares at the crimson reflection on the +containment glass. + +**DIRECTOR:** Prove Buddy right, or prove it wrong. + +**ANALYST:** I need thirty minutes with GDB and Ghidra. + +**DIRECTOR:** You have twenty. Trace the dynamic conditional dispatcher. Map +the comparison chain. Do not send an infrared frame until you know with 100% +certainty what that firmware will do. + +The orders are clear: + +1. **Trace the Dynamic Conditional Dispatcher**: Locate `parse_nec_code` at + `0x10000280` and map all multi-way comparison branches. +2. **Disprove Buddy's Idle Prediction**: Prove why transmitting `0x00FF00FF` + leaves the optical emitter live and dangerous. +3. **Recover the Friendly Fire Lockout Code**: Extract the secret 32-bit hex + command (`0xDEADBEEF`) from the literal pool at `0x10000300`. +4. **Neutralize the Dazzler**: Execute a verified exploit—either by mutating + `simulated_ir_rx_code` in SRAM via GDB, or patching the branch logic in Flash + to force immediate lockout. +5. **Verify the Hardware**: Transition the live breadboard from the Red LED on + `GP16` to the solid Green LED on `GP17` on physical silicon. + +A machine's 0.99 guess does not disable a combat laser. + +## 5. The Challenge + +You have the image. You have the board. You have the tools and the time Buddy did +not need. + +Buddy has given you its answer, and it is confident. + +Is it that simple? + +Go find out. diff --git a/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.pdf b/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.pdf new file mode 100644 index 0000000..cd69104 Binary files /dev/null and b/WEEK11/0x0020a_cb/CLASSIFIED-BRIEF-0x05.pdf differ diff --git a/WEEK11/0x0023_structures/.gitignore b/WEEK11/0x0023_structures/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK11/0x0023_structures/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK11/0x0023_structures/.vscode/c_cpp_properties.json b/WEEK11/0x0023_structures/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK11/0x0023_structures/.vscode/cmake-kits.json b/WEEK11/0x0023_structures/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK11/0x0023_structures/.vscode/extensions.json b/WEEK11/0x0023_structures/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK11/0x0023_structures/.vscode/launch.json b/WEEK11/0x0023_structures/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK11/0x0023_structures/.vscode/settings.json b/WEEK11/0x0023_structures/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK11/0x0023_structures/.vscode/tasks.json b/WEEK11/0x0023_structures/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK11/0x0023_structures/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK11/0x0023_structures/0x0023_structures.c b/WEEK11/0x0023_structures/0x0023_structures.c new file mode 100644 index 0000000..fd802cc --- /dev/null +++ b/WEEK11/0x0023_structures/0x0023_structures.c @@ -0,0 +1,61 @@ +#include +#include +#include "pico/stdlib.h" +#include "ir.h" + +#define IR_PIN 5 + +typedef struct { + uint8_t led1_pin; + uint8_t led2_pin; + uint8_t led3_pin; + bool led1_state; + bool led2_state; + bool led3_state; +} simple_led_ctrl_t; + +int main(void) { + stdio_init_all(); + + simple_led_ctrl_t leds = { + .led1_pin = 16, + .led2_pin = 17, + .led3_pin = 18, + .led1_state = false, + .led2_state = false, + .led3_state = false + }; + + gpio_init(leds.led1_pin); gpio_set_dir(leds.led1_pin, GPIO_OUT); + gpio_init(leds.led2_pin); gpio_set_dir(leds.led2_pin, GPIO_OUT); + gpio_init(leds.led3_pin); gpio_set_dir(leds.led3_pin, GPIO_OUT); + + ir_init(IR_PIN); + printf("IR receiver on GPIO %d ready\n", IR_PIN); + + while (true) { + int key = ir_getkey(); + if (key >= 0) { + printf("NEC command: 0x%02X\n", key); + + // turn all off first + leds.led1_state = false; + leds.led2_state = false; + leds.led3_state = false; + + // check NEC codes + if (key == 0x0C) leds.led1_state = true; // GPIO16 + if (key == 0x18) leds.led2_state = true; // GPIO17 + if (key == 0x5E) leds.led3_state = true; // GPIO18 + + // apply states + gpio_put(leds.led1_pin, leds.led1_state); + gpio_put(leds.led2_pin, leds.led2_state); + gpio_put(leds.led3_pin, leds.led3_state); + + sleep_ms(10); + } else { + sleep_ms(1); + } + } +} diff --git a/WEEK11/0x0023_structures/CMakeLists.txt b/WEEK11/0x0023_structures/CMakeLists.txt new file mode 100644 index 0000000..d171bb7 --- /dev/null +++ b/WEEK11/0x0023_structures/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0023_structures C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0023_structures 0x0023_structures.c ir.c) + +pico_set_program_name(0x0023_structures "0x0023_structures") +pico_set_program_version(0x0023_structures "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0023_structures 1) +pico_enable_stdio_usb(0x0023_structures 0) + +# Add the standard library to the build +target_link_libraries(0x0023_structures + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0023_structures PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0023_structures) + diff --git a/WEEK11/0x0023_structures/build/0x0023_structures.bin b/WEEK11/0x0023_structures/build/0x0023_structures.bin new file mode 100755 index 0000000..2e8ae51 Binary files /dev/null and b/WEEK11/0x0023_structures/build/0x0023_structures.bin differ diff --git a/WEEK11/0x0023_structures/build/0x0023_structures.dis b/WEEK11/0x0023_structures/build/0x0023_structures.dis new file mode 100644 index 0000000..ccdb230 --- /dev/null +++ b/WEEK11/0x0023_structures/build/0x0023_structures.dis @@ -0,0 +1,6110 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0023_structures/build/0x0023_structures.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000038ac 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 000001e0 100038b0 100038b0 000048b0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003a90 10003a90 00004a90 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003a98 10003a98 00004a98 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00006000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00005ff4 2**0 + CONTENTS + 6 .data 0000051c 20000110 10003ac4 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00005ff4 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 0000022c 20000630 10003fe0 00006630 2**3 + ALLOC + 10 .heap 00000800 2000085c 10003fe0 0000685c 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00005ff4 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00005ff4 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00006000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10003fe0 10003fe0 00005fe0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00005ff4 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00006028 2**0 + CONTENTS, READONLY + 17 .debug_info 00021e9e 00000000 00000000 0000606d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005a08 00000000 00000000 00027f0b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 00010651 00000000 00000000 0002d913 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000c10 00000000 00000000 0003df68 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 000031d5 00000000 00000000 0003eb78 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000165fe 00000000 00000000 00041d4d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005ab8 00000000 00000000 0005834b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f90 00000000 00000000 0005de04 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002b8 00000000 00000000 0005fd94 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0023_structures/build/0x0023_structures.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003a98 .word 0x10003a98 +1000012c: 10003ac4 .word 0x10003ac4 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003ea8 .word 0x00003ea8 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10003ac4 .word 0x10003ac4 +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10003fe0 .word 0x10003fe0 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10003fe0 .word 0x10003fe0 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 2000085c .word 0x2000085c +100001d8: 10003115 .word 0x10003115 +100001dc: 10000235 .word 0x10000235 +100001e0: 1000310d .word 0x1000310d + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000814 .word 0x20000814 +10000230: 100038ac .word 0x100038ac + +10000234
: +10000234: b508 push {r3, lr} +10000236: f003 f895 bl 10003364 +1000023a: 2010 movs r0, #16 +1000023c: f000 f986 bl 1000054c +10000240: 2510 movs r5, #16 +10000242: f04f 0401 mov.w r4, #1 +10000246: ec44 5044 gpioc_bit_oe_put r5, r4 +1000024a: 2011 movs r0, #17 +1000024c: f000 f97e bl 1000054c +10000250: 2311 movs r3, #17 +10000252: ec44 3044 gpioc_bit_oe_put r3, r4 +10000256: 2012 movs r0, #18 +10000258: f000 f978 bl 1000054c +1000025c: 2312 movs r3, #18 +1000025e: ec44 3044 gpioc_bit_oe_put r3, r4 +10000262: 2005 movs r0, #5 +10000264: f000 f832 bl 100002cc +10000268: 2105 movs r1, #5 +1000026a: 4816 ldr r0, [pc, #88] @ (100002c4 ) +1000026c: f003 f942 bl 100034f4 <__wrap_printf> +10000270: f000 f840 bl 100002f4 +10000274: 1e04 subs r4, r0, #0 +10000276: db21 blt.n 100002bc +10000278: 4621 mov r1, r4 +1000027a: 4813 ldr r0, [pc, #76] @ (100002c8 ) +1000027c: f003 f93a bl 100034f4 <__wrap_printf> +10000280: f1a4 030c sub.w r3, r4, #12 +10000284: fab3 f383 clz r3, r3 +10000288: 095b lsrs r3, r3, #5 +1000028a: ec43 5040 gpioc_bit_out_put r5, r3 +1000028e: f1a4 0218 sub.w r2, r4, #24 +10000292: fab2 f282 clz r2, r2 +10000296: 2311 movs r3, #17 +10000298: 0952 lsrs r2, r2, #5 +1000029a: ec42 3040 gpioc_bit_out_put r3, r2 +1000029e: f1a4 045e sub.w r4, r4, #94 @ 0x5e +100002a2: fab4 f484 clz r4, r4 +100002a6: 2312 movs r3, #18 +100002a8: 0964 lsrs r4, r4, #5 +100002aa: ec44 3040 gpioc_bit_out_put r3, r4 +100002ae: 200a movs r0, #10 +100002b0: f000 fe7a bl 10000fa8 +100002b4: f000 f81e bl 100002f4 +100002b8: 1e04 subs r4, r0, #0 +100002ba: dadd bge.n 10000278 +100002bc: 2001 movs r0, #1 +100002be: f000 fe73 bl 10000fa8 +100002c2: e7d5 b.n 10000270 +100002c4: 100038b0 .word 0x100038b0 +100002c8: 100038d0 .word 0x100038d0 + +100002cc : +100002cc: 4b08 ldr r3, [pc, #32] @ (100002f0 ) +100002ce: b510 push {r4, lr} +100002d0: 6018 str r0, [r3, #0] +100002d2: 4604 mov r4, r0 +100002d4: f000 f93a bl 1000054c +100002d8: f04f 0300 mov.w r3, #0 +100002dc: ec43 4044 gpioc_bit_oe_put r4, r3 +100002e0: 2101 movs r1, #1 +100002e2: 4620 mov r0, r4 +100002e4: e8bd 4010 ldmia.w sp!, {r4, lr} +100002e8: 2200 movs r2, #0 +100002ea: f000 b91b b.w 10000524 +100002ee: bf00 nop +100002f0: 2000080c .word 0x2000080c + +100002f4 : +100002f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100002f8: 4b77 ldr r3, [pc, #476] @ (100004d8 ) +100002fa: b085 sub sp, #20 +100002fc: 681d ldr r5, [r3, #0] +100002fe: 2601 movs r6, #1 +10000300: f000 ff44 bl 1000118c +10000304: 40ae lsls r6, r5 +10000306: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +1000030a: f04f 0900 mov.w r9, #0 +1000030e: 4604 mov r4, r0 +10000310: 460d mov r5, r1 +10000312: f8df 81d0 ldr.w r8, [pc, #464] @ 100004e4 +10000316: e009 b.n 1000032c +10000318: f000 ff38 bl 1000118c +1000031c: 1b00 subs r0, r0, r4 +1000031e: eb61 0105 sbc.w r1, r1, r5 +10000322: 4580 cmp r8, r0 +10000324: eb79 0101 sbcs.w r1, r9, r1 +10000328: f2c0 80d1 blt.w 100004ce +1000032c: 687b ldr r3, [r7, #4] +1000032e: 4233 tst r3, r6 +10000330: d1f2 bne.n 10000318 +10000332: f000 ff2b bl 1000118c +10000336: 42a0 cmp r0, r4 +10000338: eb61 0105 sbc.w r1, r1, r5 +1000033c: 2900 cmp r1, #0 +1000033e: f2c0 80c6 blt.w 100004ce +10000342: 4b65 ldr r3, [pc, #404] @ (100004d8 ) +10000344: 2601 movs r6, #1 +10000346: 681d ldr r5, [r3, #0] +10000348: f000 ff20 bl 1000118c +1000034c: 40ae lsls r6, r5 +1000034e: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +10000352: f642 68e1 movw r8, #12001 @ 0x2ee1 +10000356: 4604 mov r4, r0 +10000358: 460d mov r5, r1 +1000035a: e009 b.n 10000370 +1000035c: f000 ff16 bl 1000118c +10000360: 1b00 subs r0, r0, r4 +10000362: eb61 0105 sbc.w r1, r1, r5 +10000366: 4540 cmp r0, r8 +10000368: f171 0100 sbcs.w r1, r1, #0 +1000036c: f280 80af bge.w 100004ce +10000370: 687b ldr r3, [r7, #4] +10000372: 4233 tst r3, r6 +10000374: d0f2 beq.n 1000035c +10000376: f000 ff09 bl 1000118c +1000037a: 4b58 ldr r3, [pc, #352] @ (100004dc ) +1000037c: f240 72d1 movw r2, #2001 @ 0x7d1 +10000380: 1b1b subs r3, r3, r4 +10000382: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff +10000386: eb64 0505 sbc.w r5, r4, r5 +1000038a: 181b adds r3, r3, r0 +1000038c: eb45 0501 adc.w r5, r5, r1 +10000390: 4293 cmp r3, r2 +10000392: f175 0500 sbcs.w r5, r5, #0 +10000396: f080 809a bcs.w 100004ce +1000039a: 4b4f ldr r3, [pc, #316] @ (100004d8 ) +1000039c: 2501 movs r5, #1 +1000039e: 681e ldr r6, [r3, #0] +100003a0: f000 fef4 bl 1000118c +100003a4: 40b5 lsls r5, r6 +100003a6: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +100003aa: f641 3859 movw r8, #7001 @ 0x1b59 +100003ae: 4604 mov r4, r0 +100003b0: 460e mov r6, r1 +100003b2: e009 b.n 100003c8 +100003b4: f000 feea bl 1000118c +100003b8: 1b00 subs r0, r0, r4 +100003ba: eb61 0106 sbc.w r1, r1, r6 +100003be: 4540 cmp r0, r8 +100003c0: f171 0100 sbcs.w r1, r1, #0 +100003c4: f280 8083 bge.w 100004ce +100003c8: 687b ldr r3, [r7, #4] +100003ca: 402b ands r3, r5 +100003cc: d1f2 bne.n 100003b4 +100003ce: 9301 str r3, [sp, #4] +100003d0: f000 fedc bl 1000118c +100003d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +100003d8: f240 55dd movw r5, #1501 @ 0x5dd +100003dc: 4a40 ldr r2, [pc, #256] @ (100004e0 ) +100003de: 1b12 subs r2, r2, r4 +100003e0: eb63 0606 sbc.w r6, r3, r6 +100003e4: 1812 adds r2, r2, r0 +100003e6: eb46 0601 adc.w r6, r6, r1 +100003ea: 42aa cmp r2, r5 +100003ec: f176 0600 sbcs.w r6, r6, #0 +100003f0: d26d bcs.n 100004ce +100003f2: 9b01 ldr r3, [sp, #4] +100003f4: f04f 0b01 mov.w fp, #1 +100003f8: 469a mov sl, r3 +100003fa: f240 35e9 movw r5, #1001 @ 0x3e9 +100003fe: 9303 str r3, [sp, #12] +10000400: 4b35 ldr r3, [pc, #212] @ (100004d8 ) +10000402: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +10000406: 681f ldr r7, [r3, #0] +10000408: f000 fec0 bl 1000118c +1000040c: fa0b f707 lsl.w r7, fp, r7 +10000410: 4604 mov r4, r0 +10000412: 460e mov r6, r1 +10000414: e008 b.n 10000428 +10000416: f000 feb9 bl 1000118c +1000041a: 1b00 subs r0, r0, r4 +1000041c: eb61 0106 sbc.w r1, r1, r6 +10000420: 42a8 cmp r0, r5 +10000422: f171 0100 sbcs.w r1, r1, #0 +10000426: da52 bge.n 100004ce +10000428: f8d8 3004 ldr.w r3, [r8, #4] +1000042c: 423b tst r3, r7 +1000042e: d0f2 beq.n 10000416 +10000430: f000 feac bl 1000118c +10000434: 42a0 cmp r0, r4 +10000436: eb61 0106 sbc.w r1, r1, r6 +1000043a: 2900 cmp r1, #0 +1000043c: db47 blt.n 100004ce +1000043e: 4b26 ldr r3, [pc, #152] @ (100004d8 ) +10000440: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +10000444: 681f ldr r7, [r3, #0] +10000446: f000 fea1 bl 1000118c +1000044a: f640 19c5 movw r9, #2501 @ 0x9c5 +1000044e: 4604 mov r4, r0 +10000450: 460e mov r6, r1 +10000452: fa0b f707 lsl.w r7, fp, r7 +10000456: e008 b.n 1000046a +10000458: f000 fe98 bl 1000118c +1000045c: 1b00 subs r0, r0, r4 +1000045e: eb61 0106 sbc.w r1, r1, r6 +10000462: 4548 cmp r0, r9 +10000464: f171 0100 sbcs.w r1, r1, #0 +10000468: da31 bge.n 100004ce +1000046a: f8d8 3004 ldr.w r3, [r8, #4] +1000046e: 423b tst r3, r7 +10000470: d1f2 bne.n 10000458 +10000472: f000 fe8b bl 1000118c +10000476: 1b00 subs r0, r0, r4 +10000478: eb61 0106 sbc.w r1, r1, r6 +1000047c: 28c8 cmp r0, #200 @ 0xc8 +1000047e: f171 0300 sbcs.w r3, r1, #0 +10000482: db24 blt.n 100004ce +10000484: f240 43b1 movw r3, #1201 @ 0x4b1 +10000488: 4298 cmp r0, r3 +1000048a: f171 0100 sbcs.w r1, r1, #0 +1000048e: db09 blt.n 100004a4 +10000490: a903 add r1, sp, #12 +10000492: ea4f 02ea mov.w r2, sl, asr #3 +10000496: 5c88 ldrb r0, [r1, r2] +10000498: f00a 0307 and.w r3, sl, #7 +1000049c: fa0b f303 lsl.w r3, fp, r3 +100004a0: 4303 orrs r3, r0 +100004a2: 548b strb r3, [r1, r2] +100004a4: f10a 0a01 add.w sl, sl, #1 +100004a8: f1ba 0f20 cmp.w sl, #32 +100004ac: d1a8 bne.n 10000400 +100004ae: f89d 300c ldrb.w r3, [sp, #12] +100004b2: f89d 200d ldrb.w r2, [sp, #13] +100004b6: 4413 add r3, r2 +100004b8: b2db uxtb r3, r3 +100004ba: 2bff cmp r3, #255 @ 0xff +100004bc: d107 bne.n 100004ce +100004be: f89d 000e ldrb.w r0, [sp, #14] +100004c2: f89d 300f ldrb.w r3, [sp, #15] +100004c6: 4403 add r3, r0 +100004c8: b2db uxtb r3, r3 +100004ca: 2bff cmp r3, #255 @ 0xff +100004cc: d001 beq.n 100004d2 +100004ce: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +100004d2: b005 add sp, #20 +100004d4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100004d8: 2000080c .word 0x2000080c +100004dc: ffffe0c0 .word 0xffffe0c0 +100004e0: fffff254 .word 0xfffff254 +100004e4: 000249f0 .word 0x000249f0 + +100004e8 : +100004e8: b410 push {r4} +100004ea: f44f 7480 mov.w r4, #256 @ 0x100 +100004ee: 4b0c ldr r3, [pc, #48] @ (10000520 ) +100004f0: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100004f4: eb03 0380 add.w r3, r3, r0, lsl #2 +100004f8: 00c0 lsls r0, r0, #3 +100004fa: f082 0240 eor.w r2, r2, #64 @ 0x40 +100004fe: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10000502: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000506: f002 02c0 and.w r2, r2, #192 @ 0xc0 +1000050a: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000050e: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000512: f8cc 2000 str.w r2, [ip] +10000516: 6041 str r1, [r0, #4] +10000518: 601c str r4, [r3, #0] +1000051a: f85d 4b04 ldr.w r4, [sp], #4 +1000051e: 4770 bx lr +10000520: 40038004 .word 0x40038004 + +10000524 : +10000524: b410 push {r4} +10000526: 4c08 ldr r4, [pc, #32] @ (10000548 ) +10000528: 00c9 lsls r1, r1, #3 +1000052a: ea41 0182 orr.w r1, r1, r2, lsl #2 +1000052e: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10000532: eb04 0380 add.w r3, r4, r0, lsl #2 +10000536: 4051 eors r1, r2 +10000538: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000053c: f001 010c and.w r1, r1, #12 +10000540: f85d 4b04 ldr.w r4, [sp], #4 +10000544: 6019 str r1, [r3, #0] +10000546: 4770 bx lr +10000548: 40038004 .word 0x40038004 + +1000054c : +1000054c: b430 push {r4, r5} +1000054e: f04f 0300 mov.w r3, #0 +10000552: ec43 0044 gpioc_bit_oe_put r0, r3 +10000556: ec43 0040 gpioc_bit_out_put r0, r3 +1000055a: 2505 movs r5, #5 +1000055c: f44f 7480 mov.w r4, #256 @ 0x100 +10000560: 4b0b ldr r3, [pc, #44] @ (10000590 ) +10000562: 00c2 lsls r2, r0, #3 +10000564: f853 1020 ldr.w r1, [r3, r0, lsl #2] +10000568: eb03 0080 add.w r0, r3, r0, lsl #2 +1000056c: f081 0140 eor.w r1, r1, #64 @ 0x40 +10000570: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +10000574: f503 3320 add.w r3, r3, #163840 @ 0x28000 +10000578: f001 02c0 and.w r2, r1, #192 @ 0xc0 +1000057c: f500 5180 add.w r1, r0, #4096 @ 0x1000 +10000580: f500 5040 add.w r0, r0, #12288 @ 0x3000 +10000584: 600a str r2, [r1, #0] +10000586: 605d str r5, [r3, #4] +10000588: 6004 str r4, [r0, #0] +1000058a: bc30 pop {r4, r5} +1000058c: 4770 bx lr +1000058e: bf00 nop +10000590: 40038004 .word 0x40038004 + +10000594 : +10000594: b40f push {r0, r1, r2, r3} +10000596: b500 push {lr} +10000598: b083 sub sp, #12 +1000059a: 9c04 ldr r4, [sp, #16] +1000059c: 4807 ldr r0, [pc, #28] @ (100005bc ) +1000059e: f002 ff29 bl 100033f4 <__wrap_puts> +100005a2: b13c cbz r4, 100005b4 +100005a4: a905 add r1, sp, #20 +100005a6: 4620 mov r0, r4 +100005a8: 9101 str r1, [sp, #4] +100005aa: f002 fd95 bl 100030d8 +100005ae: 4804 ldr r0, [pc, #16] @ (100005c0 ) +100005b0: f002 ff20 bl 100033f4 <__wrap_puts> +100005b4: 2001 movs r0, #1 +100005b6: f002 fda7 bl 10003108 <_exit> +100005ba: bf00 nop +100005bc: 100038e8 .word 0x100038e8 +100005c0: 100038f8 .word 0x100038f8 + +100005c4 : +100005c4: b570 push {r4, r5, r6, lr} +100005c6: 4686 mov lr, r0 +100005c8: f3ef 8510 mrs r5, PRIMASK +100005cc: b672 cpsid i +100005ce: 4c12 ldr r4, [pc, #72] @ (10000618 ) +100005d0: e8d4 6fcf ldaexb r6, [r4] +100005d4: 2001 movs r0, #1 +100005d6: 2e00 cmp r6, #0 +100005d8: d1fa bne.n 100005d0 +100005da: e8c4 0f46 strexb r6, r0, [r4] +100005de: 2e00 cmp r6, #0 +100005e0: d1f6 bne.n 100005d0 +100005e2: f3bf 8f5f dmb sy +100005e6: f04f 0c01 mov.w ip, #1 +100005ea: 08c8 lsrs r0, r1, #3 +100005ec: f001 0307 and.w r3, r1, #7 +100005f0: fa0c f303 lsl.w r3, ip, r3 +100005f4: f81e c000 ldrb.w ip, [lr, r0] +100005f8: ea1c 0603 ands.w r6, ip, r3 +100005fc: d108 bne.n 10000610 +100005fe: ea4c 0c03 orr.w ip, ip, r3 +10000602: f80e c000 strb.w ip, [lr, r0] +10000606: e8c4 6f8f stlb r6, [r4] +1000060a: f385 8810 msr PRIMASK, r5 +1000060e: bd70 pop {r4, r5, r6, pc} +10000610: 4610 mov r0, r2 +10000612: f7ff ffbf bl 10000594 +10000616: bf00 nop +10000618: 200007bb .word 0x200007bb + +1000061c : +1000061c: 4a04 ldr r2, [pc, #16] @ (10000630 ) +1000061e: 7810 ldrb r0, [r2, #0] +10000620: 1c43 adds r3, r0, #1 +10000622: b2db uxtb r3, r3 +10000624: 2b18 cmp r3, #24 +10000626: bf28 it cs +10000628: 2310 movcs r3, #16 +1000062a: 7013 strb r3, [r2, #0] +1000062c: 4770 bx lr +1000062e: bf00 nop +10000630: 200005a8 .word 0x200005a8 + +10000634 : +10000634: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000638: 6893 ldr r3, [r2, #8] +1000063a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000063e: 6093 str r3, [r2, #8] +10000640: 4770 bx lr +10000642: bf00 nop + +10000644 : +10000644: 2100 movs r1, #0 +10000646: 4b04 ldr r3, [pc, #16] @ (10000658 ) +10000648: f103 0220 add.w r2, r3, #32 +1000064c: e8c3 1f8f stlb r1, [r3] +10000650: 3301 adds r3, #1 +10000652: 4293 cmp r3, r2 +10000654: d1fa bne.n 1000064c +10000656: 4770 bx lr +10000658: 200007b0 .word 0x200007b0 + +1000065c : +1000065c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10000660: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10000664: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10000668: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1000066c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10000670: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10000674: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10000678: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1000067c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000680: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000684: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10000688: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1000068c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000690: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000694: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10000698: b662 cpsie i +1000069a: 4770 bx lr + +1000069c : +1000069c: 2301 movs r3, #1 +1000069e: f000 021f and.w r2, r0, #31 +100006a2: 4093 lsls r3, r2 +100006a4: 0940 lsrs r0, r0, #5 +100006a6: b141 cbz r1, 100006ba +100006a8: 0080 lsls r0, r0, #2 +100006aa: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100006ae: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100006b2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100006b6: 6003 str r3, [r0, #0] +100006b8: 4770 bx lr +100006ba: 4a02 ldr r2, [pc, #8] @ (100006c4 ) +100006bc: 3020 adds r0, #32 +100006be: f842 3020 str.w r3, [r2, r0, lsl #2] +100006c2: 4770 bx lr +100006c4: e000e100 .word 0xe000e100 + +100006c8 : +100006c8: b5f8 push {r3, r4, r5, r6, r7, lr} +100006ca: 460d mov r5, r1 +100006cc: f3ef 8710 mrs r7, PRIMASK +100006d0: b672 cpsid i +100006d2: 4e12 ldr r6, [pc, #72] @ (1000071c ) +100006d4: e8d6 2fcf ldaexb r2, [r6] +100006d8: 2301 movs r3, #1 +100006da: 2a00 cmp r2, #0 +100006dc: d1fa bne.n 100006d4 +100006de: e8c6 3f42 strexb r2, r3, [r6] +100006e2: 2a00 cmp r2, #0 +100006e4: d1f6 bne.n 100006d4 +100006e6: f3bf 8f5f dmb sy +100006ea: 4b0d ldr r3, [pc, #52] @ (10000720 ) +100006ec: f100 0410 add.w r4, r0, #16 +100006f0: 689b ldr r3, [r3, #8] +100006f2: 4a0c ldr r2, [pc, #48] @ (10000724 ) +100006f4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100006f8: 4293 cmp r3, r2 +100006fa: d003 beq.n 10000704 +100006fc: 4299 cmp r1, r3 +100006fe: d001 beq.n 10000704 +10000700: f000 ff0e bl 10001520 +10000704: 4b06 ldr r3, [pc, #24] @ (10000720 ) +10000706: 689b ldr r3, [r3, #8] +10000708: f843 5024 str.w r5, [r3, r4, lsl #2] +1000070c: f3bf 8f5f dmb sy +10000710: 2300 movs r3, #0 +10000712: e8c6 3f8f stlb r3, [r6] +10000716: f387 8810 msr PRIMASK, r7 +1000071a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000071c: 200007b9 .word 0x200007b9 +10000720: e000ed00 .word 0xe000ed00 +10000724: 10000111 .word 0x10000111 + +10000728 : +10000728: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000072c: b083 sub sp, #12 +1000072e: f3ef 8a10 mrs sl, PRIMASK +10000732: b672 cpsid i +10000734: 4e71 ldr r6, [pc, #452] @ (100008fc ) +10000736: e8d6 2fcf ldaexb r2, [r6] +1000073a: 2301 movs r3, #1 +1000073c: 2a00 cmp r2, #0 +1000073e: d1fa bne.n 10000736 +10000740: e8c6 3f42 strexb r2, r3, [r6] +10000744: 2a00 cmp r2, #0 +10000746: d1f6 bne.n 10000736 +10000748: f3bf 8f5f dmb sy +1000074c: 4b6c ldr r3, [pc, #432] @ (10000900 ) +1000074e: f100 0810 add.w r8, r0, #16 +10000752: 689b ldr r3, [r3, #8] +10000754: 4a6b ldr r2, [pc, #428] @ (10000904 ) +10000756: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1000075a: 4295 cmp r5, r2 +1000075c: d045 beq.n 100007ea +1000075e: 428d cmp r5, r1 +10000760: 460c mov r4, r1 +10000762: d050 beq.n 10000806 +10000764: 4f68 ldr r7, [pc, #416] @ (10000908 ) +10000766: 1beb subs r3, r5, r7 +10000768: 2b2f cmp r3, #47 @ 0x2f +1000076a: d83e bhi.n 100007ea +1000076c: 2101 movs r1, #1 +1000076e: ea4f 1950 mov.w r9, r0, lsr #5 +10000772: ea4f 0989 mov.w r9, r9, lsl #2 +10000776: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1000077a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1000077e: f000 031f and.w r3, r0, #31 +10000782: fa01 f003 lsl.w r0, r1, r3 +10000786: f8d9 3000 ldr.w r3, [r9] +1000078a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1000078e: ea00 0b03 and.w fp, r0, r3 +10000792: f3bf 8f5f dmb sy +10000796: f3ef 8105 mrs r1, IPSR +1000079a: b2c9 uxtb r1, r1 +1000079c: 2900 cmp r1, #0 +1000079e: d034 beq.n 1000080a +100007a0: 4588 cmp r8, r1 +100007a2: d005 beq.n 100007b0 +100007a4: e9cd 1000 strd r1, r0, [sp] +100007a8: f000 feba bl 10001520 +100007ac: e9dd 1000 ldrd r1, r0, [sp] +100007b0: f025 0e01 bic.w lr, r5, #1 +100007b4: f8de c008 ldr.w ip, [lr, #8] +100007b8: 4564 cmp r4, ip +100007ba: d105 bne.n 100007c8 +100007bc: e089 b.n 100008d2 +100007be: f8d3 c008 ldr.w ip, [r3, #8] +100007c2: 4564 cmp r4, ip +100007c4: d031 beq.n 1000082a +100007c6: 469e mov lr, r3 +100007c8: f99e 2006 ldrsb.w r2, [lr, #6] +100007cc: eb02 0342 add.w r3, r2, r2, lsl #1 +100007d0: 2a00 cmp r2, #0 +100007d2: eb07 0383 add.w r3, r7, r3, lsl #2 +100007d6: daf2 bge.n 100007be +100007d8: 4564 cmp r4, ip +100007da: d061 beq.n 100008a0 +100007dc: f1bb 0f00 cmp.w fp, #0 +100007e0: d020 beq.n 10000824 +100007e2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100007e6: f8c9 0000 str.w r0, [r9] +100007ea: 4b45 ldr r3, [pc, #276] @ (10000900 ) +100007ec: 689b ldr r3, [r3, #8] +100007ee: f843 5028 str.w r5, [r3, r8, lsl #2] +100007f2: f3bf 8f5f dmb sy +100007f6: 2300 movs r3, #0 +100007f8: e8c6 3f8f stlb r3, [r6] +100007fc: f38a 8810 msr PRIMASK, sl +10000800: b003 add sp, #12 +10000802: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000806: 4615 mov r5, r2 +10000808: e7ef b.n 100007ea +1000080a: f025 0e01 bic.w lr, r5, #1 +1000080e: f8de c008 ldr.w ip, [lr, #8] +10000812: 4564 cmp r4, ip +10000814: d1d8 bne.n 100007c8 +10000816: f99e 4006 ldrsb.w r4, [lr, #6] +1000081a: 4673 mov r3, lr +1000081c: 2c00 cmp r4, #0 +1000081e: da08 bge.n 10000832 +10000820: 4615 mov r5, r2 +10000822: e046 b.n 100008b2 +10000824: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000828: e7df b.n 100007ea +1000082a: f993 4006 ldrsb.w r4, [r3, #6] +1000082e: 2c00 cmp r4, #0 +10000830: db37 blt.n 100008a2 +10000832: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000836: eb07 0c8c add.w ip, r7, ip, lsl #2 +1000083a: f89c 1007 ldrb.w r1, [ip, #7] +1000083e: f8dc 2008 ldr.w r2, [ip, #8] +10000842: 71d9 strb r1, [r3, #7] +10000844: 609a str r2, [r3, #8] +10000846: f99c 2006 ldrsb.w r2, [ip, #6] +1000084a: 0061 lsls r1, r4, #1 +1000084c: 2a00 cmp r2, #0 +1000084e: 719a strb r2, [r3, #6] +10000850: db3d blt.n 100008ce +10000852: f8bc e004 ldrh.w lr, [ip, #4] +10000856: ea5f 5e4e movs.w lr, lr, lsl #21 +1000085a: d505 bpl.n 10000868 +1000085c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10000860: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10000864: f10e 0e1f add.w lr, lr, #31 +10000868: f06f 0c07 mvn.w ip, #7 +1000086c: 190a adds r2, r1, r4 +1000086e: ea4f 5e6e mov.w lr, lr, asr #21 +10000872: 0092 lsls r2, r2, #2 +10000874: eb02 024e add.w r2, r2, lr, lsl #1 +10000878: 3208 adds r2, #8 +1000087a: 443a add r2, r7 +1000087c: ebac 0c03 sub.w ip, ip, r3 +10000880: 4462 add r2, ip +10000882: f3c2 024a ubfx r2, r2, #1, #11 +10000886: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000088a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1000088e: 809a strh r2, [r3, #4] +10000890: 4b1e ldr r3, [pc, #120] @ (1000090c ) +10000892: 4421 add r1, r4 +10000894: 781a ldrb r2, [r3, #0] +10000896: eb07 0181 add.w r1, r7, r1, lsl #2 +1000089a: 701c strb r4, [r3, #0] +1000089c: 718a strb r2, [r1, #6] +1000089e: e79d b.n 100007dc +100008a0: 4673 mov r3, lr +100008a2: b9d9 cbnz r1, 100008dc +100008a4: 22ff movs r2, #255 @ 0xff +100008a6: f88e 2006 strb.w r2, [lr, #6] +100008aa: f64b 5201 movw r2, #48385 @ 0xbd01 +100008ae: f8ae 2004 strh.w r2, [lr, #4] +100008b2: 4c16 ldr r4, [pc, #88] @ (1000090c ) +100008b4: f64a 22aa movw r2, #43690 @ 0xaaaa +100008b8: f894 c000 ldrb.w ip, [r4] +100008bc: 4619 mov r1, r3 +100008be: 1bc9 subs r1, r1, r7 +100008c0: 4149 adcs r1, r1 +100008c2: 434a muls r2, r1 +100008c4: 0d12 lsrs r2, r2, #20 +100008c6: f883 c006 strb.w ip, [r3, #6] +100008ca: 7022 strb r2, [r4, #0] +100008cc: e786 b.n 100007dc +100008ce: 4a10 ldr r2, [pc, #64] @ (10000910 ) +100008d0: e7dd b.n 1000088e +100008d2: f99e 4006 ldrsb.w r4, [lr, #6] +100008d6: 4673 mov r3, lr +100008d8: 2c00 cmp r4, #0 +100008da: daaa bge.n 10000832 +100008dc: 4a0d ldr r2, [pc, #52] @ (10000914 ) +100008de: 4c0e ldr r4, [pc, #56] @ (10000918 ) +100008e0: 1ad2 subs r2, r2, r3 +100008e2: 3a08 subs r2, #8 +100008e4: f3c2 310a ubfx r1, r2, #12, #11 +100008e8: ea6f 5101 mvn.w r1, r1, lsl #20 +100008ec: ea6f 5111 mvn.w r1, r1, lsr #20 +100008f0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100008f4: 80da strh r2, [r3, #6] +100008f6: 8099 strh r1, [r3, #4] +100008f8: e770 b.n 100007dc +100008fa: bf00 nop +100008fc: 200007b9 .word 0x200007b9 +10000900: e000ed00 .word 0xe000ed00 +10000904: 10000111 .word 0x10000111 +10000908: 200005ac .word 0x200005ac +1000090c: 20000858 .word 0x20000858 +10000910: ffffbd01 .word 0xffffbd01 +10000914: 200005e6 .word 0x200005e6 +10000918: fffff800 .word 0xfffff800 + +1000091c : +1000091c: b5f0 push {r4, r5, r6, r7, lr} +1000091e: f3ef 8505 mrs r5, IPSR +10000922: b2ed uxtb r5, r5 +10000924: f3ef 8c10 mrs ip, PRIMASK +10000928: b672 cpsid i +1000092a: 4926 ldr r1, [pc, #152] @ (100009c4 ) +1000092c: e8d1 2fcf ldaexb r2, [r1] +10000930: 2301 movs r3, #1 +10000932: 2a00 cmp r2, #0 +10000934: d1fa bne.n 1000092c +10000936: e8c1 3f42 strexb r2, r3, [r1] +1000093a: 2a00 cmp r2, #0 +1000093c: d1f6 bne.n 1000092c +1000093e: f3bf 8f5f dmb sy +10000942: 4e21 ldr r6, [pc, #132] @ (100009c8 ) +10000944: f040 0e01 orr.w lr, r0, #1 +10000948: 68b4 ldr r4, [r6, #8] +1000094a: f64a 23aa movw r3, #43690 @ 0xaaaa +1000094e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10000952: 4a1e ldr r2, [pc, #120] @ (100009cc ) +10000954: 4604 mov r4, r0 +10000956: 1aa4 subs r4, r4, r2 +10000958: 4164 adcs r4, r4 +1000095a: 4363 muls r3, r4 +1000095c: 0d1b lsrs r3, r3, #20 +1000095e: 4577 cmp r7, lr +10000960: b25b sxtb r3, r3 +10000962: d01b beq.n 1000099c +10000964: f992 4006 ldrsb.w r4, [r2, #6] +10000968: 429c cmp r4, r3 +1000096a: d01c beq.n 100009a6 +1000096c: f992 4012 ldrsb.w r4, [r2, #18] +10000970: 429c cmp r4, r3 +10000972: d023 beq.n 100009bc +10000974: f992 401e ldrsb.w r4, [r2, #30] +10000978: 429c cmp r4, r3 +1000097a: d021 beq.n 100009c0 +1000097c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000980: 429c cmp r4, r3 +10000982: bf08 it eq +10000984: 2403 moveq r4, #3 +10000986: d00f beq.n 100009a8 +10000988: 4a11 ldr r2, [pc, #68] @ (100009d0 ) +1000098a: 2400 movs r4, #0 +1000098c: 7815 ldrb r5, [r2, #0] +1000098e: 7013 strb r3, [r2, #0] +10000990: 7185 strb r5, [r0, #6] +10000992: e8c1 4f8f stlb r4, [r1] +10000996: f38c 8810 msr PRIMASK, ip +1000099a: bdf0 pop {r4, r5, r6, r7, pc} +1000099c: 68b2 ldr r2, [r6, #8] +1000099e: 4c0d ldr r4, [pc, #52] @ (100009d4 ) +100009a0: f842 4025 str.w r4, [r2, r5, lsl #2] +100009a4: e7f0 b.n 10000988 +100009a6: 2400 movs r4, #0 +100009a8: eb04 0444 add.w r4, r4, r4, lsl #1 +100009ac: eb02 0284 add.w r2, r2, r4, lsl #2 +100009b0: 24ff movs r4, #255 @ 0xff +100009b2: 7194 strb r4, [r2, #6] +100009b4: f64b 5401 movw r4, #48385 @ 0xbd01 +100009b8: 8094 strh r4, [r2, #4] +100009ba: e7e5 b.n 10000988 +100009bc: 2401 movs r4, #1 +100009be: e7f3 b.n 100009a8 +100009c0: 2402 movs r4, #2 +100009c2: e7f1 b.n 100009a8 +100009c4: 200007b9 .word 0x200007b9 +100009c8: e000ed00 .word 0xe000ed00 +100009cc: 200005ac .word 0x200005ac +100009d0: 20000858 .word 0x20000858 +100009d4: 10000111 .word 0x10000111 + +100009d8 : +100009d8: 4b01 ldr r3, [pc, #4] @ (100009e0 ) +100009da: 440b add r3, r1 +100009dc: 6003 str r3, [r0, #0] +100009de: 4770 bx lr +100009e0: 200007b0 .word 0x200007b0 + +100009e4 : +100009e4: b570 push {r4, r5, r6, lr} +100009e6: 4c10 ldr r4, [pc, #64] @ (10000a28 ) +100009e8: 4d10 ldr r5, [pc, #64] @ (10000a2c ) +100009ea: 42ac cmp r4, r5 +100009ec: d20e bcs.n 10000a0c +100009ee: 26ff movs r6, #255 @ 0xff +100009f0: 6823 ldr r3, [r4, #0] +100009f2: b163 cbz r3, 10000a0e +100009f4: f7ff fe12 bl 1000061c +100009f8: 4601 mov r1, r0 +100009fa: 4620 mov r0, r4 +100009fc: f7ff ffec bl 100009d8 +10000a00: 80a6 strh r6, [r4, #4] +10000a02: f3bf 8f5f dmb sy +10000a06: 3408 adds r4, #8 +10000a08: 42ac cmp r4, r5 +10000a0a: d3f1 bcc.n 100009f0 +10000a0c: bd70 pop {r4, r5, r6, pc} +10000a0e: f7ff fe05 bl 1000061c +10000a12: 4601 mov r1, r0 +10000a14: 4620 mov r0, r4 +10000a16: f7ff ffdf bl 100009d8 +10000a1a: 7126 strb r6, [r4, #4] +10000a1c: f3bf 8f5f dmb sy +10000a20: 3408 adds r4, #8 +10000a22: 42ac cmp r4, r5 +10000a24: d3e4 bcc.n 100009f0 +10000a26: bd70 pop {r4, r5, r6, pc} +10000a28: 20000624 .word 0x20000624 +10000a2c: 2000062c .word 0x2000062c + +10000a30 : +10000a30: 4b0d ldr r3, [pc, #52] @ (10000a68 ) +10000a32: 681a ldr r2, [r3, #0] +10000a34: f3ef 8110 mrs r1, PRIMASK +10000a38: b672 cpsid i +10000a3a: e8d2 cfcf ldaexb ip, [r2] +10000a3e: 2001 movs r0, #1 +10000a40: f1bc 0f00 cmp.w ip, #0 +10000a44: d1f9 bne.n 10000a3a +10000a46: e8c2 0f4c strexb ip, r0, [r2] +10000a4a: f1bc 0f00 cmp.w ip, #0 +10000a4e: d1f4 bne.n 10000a3a +10000a50: f3bf 8f5f dmb sy +10000a54: 2200 movs r2, #0 +10000a56: 681b ldr r3, [r3, #0] +10000a58: e8c3 2f8f stlb r2, [r3] +10000a5c: f381 8810 msr PRIMASK, r1 +10000a60: bf40 sev +10000a62: 2000 movs r0, #0 +10000a64: 2100 movs r1, #0 +10000a66: 4770 bx lr +10000a68: 2000084c .word 0x2000084c +10000a6c: 00000000 .word 0x00000000 + +10000a70 : +10000a70: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000a74: ed2d 8b02 vpush {d8} +10000a78: b085 sub sp, #20 +10000a7a: f3ef 8305 mrs r3, IPSR +10000a7e: b2db uxtb r3, r3 +10000a80: 3b10 subs r3, #16 +10000a82: 089a lsrs r2, r3, #2 +10000a84: bf18 it ne +10000a86: 2201 movne r2, #1 +10000a88: f04f 0101 mov.w r1, #1 +10000a8c: f003 0b03 and.w fp, r3, #3 +10000a90: bf18 it ne +10000a92: 4daf ldrne r5, [pc, #700] @ (10000d50 ) +10000a94: 4baf ldr r3, [pc, #700] @ (10000d54 ) +10000a96: bf08 it eq +10000a98: 4daf ldreq r5, [pc, #700] @ (10000d58 ) +10000a9a: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000a9e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000aa2: fa01 f20b lsl.w r2, r1, fp +10000aa6: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000aaa: ed9f 8ba7 vldr d8, [pc, #668] @ 10000d48 +10000aae: 9201 str r2, [sp, #4] +10000ab0: 605a str r2, [r3, #4] +10000ab2: e02f b.n 10000b14 +10000ab4: 88b3 ldrh r3, [r6, #4] +10000ab6: 041c lsls r4, r3, #16 +10000ab8: f140 8093 bpl.w 10000be2 +10000abc: 79b3 ldrb r3, [r6, #6] +10000abe: 2b00 cmp r3, #0 +10000ac0: f040 80dd bne.w 10000c7e +10000ac4: f9b6 2008 ldrsh.w r2, [r6, #8] +10000ac8: 2a00 cmp r2, #0 +10000aca: f2c0 811e blt.w 10000d0a +10000ace: 6973 ldr r3, [r6, #20] +10000ad0: eb02 0242 add.w r2, r2, r2, lsl #1 +10000ad4: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000ad8: e9d3 4702 ldrd r4, r7, [r3, #8] +10000adc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000ae0: bf08 it eq +10000ae2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000ae6: d00e beq.n 10000b06 +10000ae8: eb05 018b add.w r1, r5, fp, lsl #2 +10000aec: 6aab ldr r3, [r5, #40] @ 0x28 +10000aee: 690a ldr r2, [r1, #16] +10000af0: 1ad2 subs r2, r2, r3 +10000af2: 1ae3 subs r3, r4, r3 +10000af4: 4293 cmp r3, r2 +10000af6: d305 bcc.n 10000b04 +10000af8: 2301 movs r3, #1 +10000afa: 6a2a ldr r2, [r5, #32] +10000afc: fa03 f30b lsl.w r3, r3, fp +10000b00: 4213 tst r3, r2 +10000b02: d100 bne.n 10000b06 +10000b04: 610c str r4, [r1, #16] +10000b06: 4628 mov r0, r5 +10000b08: f000 fb38 bl 1000117c +10000b0c: 42a0 cmp r0, r4 +10000b0e: 41b9 sbcs r1, r7 +10000b10: f2c0 80fb blt.w 10000d0a +10000b14: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b18: 9a01 ldr r2, [sp, #4] +10000b1a: 2b00 cmp r3, #0 +10000b1c: 9300 str r3, [sp, #0] +10000b1e: 63ea str r2, [r5, #60] @ 0x3c +10000b20: dbc8 blt.n 10000ab4 +10000b22: f8d6 8014 ldr.w r8, [r6, #20] +10000b26: eb03 0943 add.w r9, r3, r3, lsl #1 +10000b2a: 4628 mov r0, r5 +10000b2c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000b30: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000b34: f000 fb22 bl 1000117c +10000b38: 42a0 cmp r0, r4 +10000b3a: eb71 010a sbcs.w r1, r1, sl +10000b3e: dbb9 blt.n 10000ab4 +10000b40: f1ba 0f00 cmp.w sl, #0 +10000b44: f2c0 80c3 blt.w 10000cce +10000b48: e9d7 3104 ldrd r3, r1, [r7, #16] +10000b4c: 4a83 ldr r2, [pc, #524] @ (10000d5c ) +10000b4e: 4293 cmp r3, r2 +10000b50: f000 80ed beq.w 10000d2e +10000b54: 887a ldrh r2, [r7, #2] +10000b56: f9b6 0008 ldrsh.w r0, [r6, #8] +10000b5a: b292 uxth r2, r2 +10000b5c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000b60: 4798 blx r3 +10000b62: 4602 mov r2, r0 +10000b64: 460b mov r3, r1 +10000b66: ea52 0103 orrs.w r1, r2, r3 +10000b6a: f000 80b0 beq.w 10000cce +10000b6e: 2b00 cmp r3, #0 +10000b70: f280 80d1 bge.w 10000d16 +10000b74: ebb4 0e02 subs.w lr, r4, r2 +10000b78: eb6a 0a03 sbc.w sl, sl, r3 +10000b7c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000b80: e9c7 ea02 strd lr, sl, [r7, #8] +10000b84: 2b00 cmp r3, #0 +10000b86: db95 blt.n 10000ab4 +10000b88: 6971 ldr r1, [r6, #20] +10000b8a: eb03 0243 add.w r2, r3, r3, lsl #1 +10000b8e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000b92: e9d2 7002 ldrd r7, r0, [r2, #8] +10000b96: 45be cmp lr, r7 +10000b98: eb7a 0c00 sbcs.w ip, sl, r0 +10000b9c: ea4f 0243 mov.w r2, r3, lsl #1 +10000ba0: db88 blt.n 10000ab4 +10000ba2: 46b4 mov ip, r6 +10000ba4: f82c 3f08 strh.w r3, [ip, #8]! +10000ba8: e006 b.n 10000bb8 +10000baa: eb03 0043 add.w r0, r3, r3, lsl #1 +10000bae: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000bb2: 005a lsls r2, r3, #1 +10000bb4: e9d0 7002 ldrd r7, r0, [r0, #8] +10000bb8: 45be cmp lr, r7 +10000bba: 441a add r2, r3 +10000bbc: eb7a 0000 sbcs.w r0, sl, r0 +10000bc0: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000bc4: db04 blt.n 10000bd0 +10000bc6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000bca: 46a4 mov ip, r4 +10000bcc: 2b00 cmp r3, #0 +10000bce: daec bge.n 10000baa +10000bd0: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000bd4: 9b00 ldr r3, [sp, #0] +10000bd6: f8ac 3000 strh.w r3, [ip] +10000bda: 88b3 ldrh r3, [r6, #4] +10000bdc: 041c lsls r4, r3, #16 +10000bde: f53f af6d bmi.w 10000abc +10000be2: 6933 ldr r3, [r6, #16] +10000be4: f3ef 8210 mrs r2, PRIMASK +10000be8: b672 cpsid i +10000bea: e8d3 0fcf ldaexb r0, [r3] +10000bee: 2101 movs r1, #1 +10000bf0: 2800 cmp r0, #0 +10000bf2: d1fa bne.n 10000bea +10000bf4: e8c3 1f40 strexb r0, r1, [r3] +10000bf8: 2800 cmp r0, #0 +10000bfa: d1f6 bne.n 10000bea +10000bfc: f3bf 8f5f dmb sy +10000c00: f64f 74ff movw r4, #65535 @ 0xffff +10000c04: 88b0 ldrh r0, [r6, #4] +10000c06: 2300 movs r3, #0 +10000c08: 6931 ldr r1, [r6, #16] +10000c0a: b200 sxth r0, r0 +10000c0c: 80b4 strh r4, [r6, #4] +10000c0e: e8c1 3f8f stlb r3, [r1] +10000c12: f382 8810 msr PRIMASK, r2 +10000c16: 4298 cmp r0, r3 +10000c18: f6ff af50 blt.w 10000abc +10000c1c: 4607 mov r7, r0 +10000c1e: 46a9 mov r9, r5 +10000c20: 6974 ldr r4, [r6, #20] +10000c22: f106 0808 add.w r8, r6, #8 +10000c26: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000c2a: eb04 03ce add.w r3, r4, lr, lsl #3 +10000c2e: e9d3 5002 ldrd r5, r0, [r3, #8] +10000c32: f9b6 3008 ldrsh.w r3, [r6, #8] +10000c36: 46c4 mov ip, r8 +10000c38: 2b00 cmp r3, #0 +10000c3a: db13 blt.n 10000c64 +10000c3c: 46b2 mov sl, r6 +10000c3e: 9700 str r7, [sp, #0] +10000c40: e004 b.n 10000c4c +10000c42: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000c46: 4694 mov ip, r2 +10000c48: 2b00 cmp r3, #0 +10000c4a: db09 blt.n 10000c60 +10000c4c: eb03 0643 add.w r6, r3, r3, lsl #1 +10000c50: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000c54: e9d2 7102 ldrd r7, r1, [r2, #8] +10000c58: 42bd cmp r5, r7 +10000c5a: eb70 0101 sbcs.w r1, r0, r1 +10000c5e: daf0 bge.n 10000c42 +10000c60: 4656 mov r6, sl +10000c62: 9f00 ldr r7, [sp, #0] +10000c64: f8ac 7000 strh.w r7, [ip] +10000c68: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000c6c: f824 303e strh.w r3, [r4, lr, lsl #3] +10000c70: 2f00 cmp r7, #0 +10000c72: dad8 bge.n 10000c26 +10000c74: 79b3 ldrb r3, [r6, #6] +10000c76: 464d mov r5, r9 +10000c78: 2b00 cmp r3, #0 +10000c7a: f43f af23 beq.w 10000ac4 +10000c7e: 2300 movs r3, #0 +10000c80: 71b3 strb r3, [r6, #6] +10000c82: f9b6 3008 ldrsh.w r3, [r6, #8] +10000c86: f106 0808 add.w r8, r6, #8 +10000c8a: 1c58 adds r0, r3, #1 +10000c8c: d03d beq.n 10000d0a +10000c8e: 461a mov r2, r3 +10000c90: 6977 ldr r7, [r6, #20] +10000c92: e003 b.n 10000c9c +10000c94: 4680 mov r8, r0 +10000c96: 1c59 adds r1, r3, #1 +10000c98: f43f af16 beq.w 10000ac8 +10000c9c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000ca0: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000ca4: f8b0 c002 ldrh.w ip, [r0, #2] +10000ca8: 461c mov r4, r3 +10000caa: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000cae: 469e mov lr, r3 +10000cb0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000cb4: d0ee beq.n 10000c94 +10000cb6: 4294 cmp r4, r2 +10000cb8: ed80 8b02 vstr d8, [r0, #8] +10000cbc: d005 beq.n 10000cca +10000cbe: f8a8 3000 strh.w r3, [r8] +10000cc2: 8932 ldrh r2, [r6, #8] +10000cc4: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000cc8: 8134 strh r4, [r6, #8] +10000cca: 4672 mov r2, lr +10000ccc: e7e3 b.n 10000c96 +10000cce: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000cd2: 8133 strh r3, [r6, #8] +10000cd4: 6933 ldr r3, [r6, #16] +10000cd6: f3ef 8210 mrs r2, PRIMASK +10000cda: b672 cpsid i +10000cdc: e8d3 0fcf ldaexb r0, [r3] +10000ce0: 2101 movs r1, #1 +10000ce2: 2800 cmp r0, #0 +10000ce4: d1fa bne.n 10000cdc +10000ce6: e8c3 1f40 strexb r0, r1, [r3] +10000cea: 2800 cmp r0, #0 +10000cec: d1f6 bne.n 10000cdc +10000cee: f3bf 8f5f dmb sy +10000cf2: 8873 ldrh r3, [r6, #2] +10000cf4: 6931 ldr r1, [r6, #16] +10000cf6: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000cfa: 9b00 ldr r3, [sp, #0] +10000cfc: 8073 strh r3, [r6, #2] +10000cfe: 2300 movs r3, #0 +10000d00: e8c1 3f8f stlb r3, [r1] +10000d04: f382 8810 msr PRIMASK, r2 +10000d08: e6d4 b.n 10000ab4 +10000d0a: bf40 sev +10000d0c: b005 add sp, #20 +10000d0e: ecbd 8b02 vpop {d8} +10000d12: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000d16: 4628 mov r0, r5 +10000d18: e9cd 2302 strd r2, r3, [sp, #8] +10000d1c: f000 fa2e bl 1000117c +10000d20: 9a02 ldr r2, [sp, #8] +10000d22: 9b03 ldr r3, [sp, #12] +10000d24: eb10 0e02 adds.w lr, r0, r2 +10000d28: eb43 0a01 adc.w sl, r3, r1 +10000d2c: e726 b.n 10000b7c +10000d2e: 4608 mov r0, r1 +10000d30: 690b ldr r3, [r1, #16] +10000d32: 9102 str r1, [sp, #8] +10000d34: 4798 blx r3 +10000d36: 2800 cmp r0, #0 +10000d38: d0c9 beq.n 10000cce +10000d3a: 9902 ldr r1, [sp, #8] +10000d3c: e9d1 2300 ldrd r2, r3, [r1] +10000d40: e711 b.n 10000b66 +10000d42: bf00 nop +10000d44: f3af 8000 nop.w +10000d48: ffffffff .word 0xffffffff +10000d4c: ffffffff .word 0xffffffff +10000d50: 400b8000 .word 0x400b8000 +10000d54: 2000082c .word 0x2000082c +10000d58: 400b0000 .word 0x400b0000 +10000d5c: 10000a71 .word 0x10000a71 + +10000d60 : +10000d60: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000d64: 4c36 ldr r4, [pc, #216] @ (10000e40 ) +10000d66: 6925 ldr r5, [r4, #16] +10000d68: b12d cbz r5, 10000d76 +10000d6a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000d6e: 210a movs r1, #10 +10000d70: 4834 ldr r0, [pc, #208] @ (10000e44 ) +10000d72: f7ff be31 b.w 100009d8 +10000d76: f8df 80e4 ldr.w r8, [pc, #228] @ 10000e5c +10000d7a: 2103 movs r1, #3 +10000d7c: 4640 mov r0, r8 +10000d7e: f000 f9eb bl 10001158 +10000d82: 2603 movs r6, #3 +10000d84: f8c4 800c str.w r8, [r4, #12] +10000d88: f7ff fc48 bl 1000061c +10000d8c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000d90: 4b2d ldr r3, [pc, #180] @ (10000e48 ) +10000d92: 7026 strb r6, [r4, #0] +10000d94: 4403 add r3, r0 +10000d96: 6123 str r3, [r4, #16] +10000d98: f8dc 3000 ldr.w r3, [ip] +10000d9c: 210f movs r1, #15 +10000d9e: 7063 strb r3, [r4, #1] +10000da0: 6963 ldr r3, [r4, #20] +10000da2: 8061 strh r1, [r4, #2] +10000da4: 831d strh r5, [r3, #24] +10000da6: f04f 0504 mov.w r5, #4 +10000daa: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000dae: f04f 0505 mov.w r5, #5 +10000db2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000db6: f04f 0506 mov.w r5, #6 +10000dba: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000dbe: f04f 0507 mov.w r5, #7 +10000dc2: 210e movs r1, #14 +10000dc4: f64f 72ff movw r2, #65535 @ 0xffff +10000dc8: 2708 movs r7, #8 +10000dca: f04f 0e0a mov.w lr, #10 +10000dce: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000dd2: f04f 0901 mov.w r9, #1 +10000dd6: f04f 0c0c mov.w ip, #12 +10000dda: f04f 0b02 mov.w fp, #2 +10000dde: f04f 0a09 mov.w sl, #9 +10000de2: 200d movs r0, #13 +10000de4: f04f 050b mov.w r5, #11 +10000de8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000dec: 4917 ldr r1, [pc, #92] @ (10000e4c ) +10000dee: 80a2 strh r2, [r4, #4] +10000df0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000df4: 60a1 str r1, [r4, #8] +10000df6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000dfa: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000dfe: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000e02: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000e06: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000e0a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000e0e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000e12: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000e16: 801a strh r2, [r3, #0] +10000e18: 4b0d ldr r3, [pc, #52] @ (10000e50 ) +10000e1a: 4630 mov r0, r6 +10000e1c: f8c8 7020 str.w r7, [r8, #32] +10000e20: 490c ldr r1, [pc, #48] @ (10000e54 ) +10000e22: 60dc str r4, [r3, #12] +10000e24: f7ff fc50 bl 100006c8 +10000e28: 4649 mov r1, r9 +10000e2a: 4630 mov r0, r6 +10000e2c: f7ff fc36 bl 1000069c +10000e30: 4b09 ldr r3, [pc, #36] @ (10000e58 ) +10000e32: 210a movs r1, #10 +10000e34: 641f str r7, [r3, #64] @ 0x40 +10000e36: 4803 ldr r0, [pc, #12] @ (10000e44 ) +10000e38: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000e3c: f7ff bdcc b.w 100009d8 +10000e40: 200005f4 .word 0x200005f4 +10000e44: 2000084c .word 0x2000084c +10000e48: 200007b0 .word 0x200007b0 +10000e4c: 0010ffff .word 0x0010ffff +10000e50: 2000082c .word 0x2000082c +10000e54: 10000a71 .word 0x10000a71 +10000e58: 400b2000 .word 0x400b2000 +10000e5c: 400b0000 .word 0x400b0000 + +10000e60 : +10000e60: 4601 mov r1, r0 +10000e62: b5f0 push {r4, r5, r6, r7, lr} +10000e64: 6900 ldr r0, [r0, #16] +10000e66: f3ef 8710 mrs r7, PRIMASK +10000e6a: b672 cpsid i +10000e6c: e8d0 5fcf ldaexb r5, [r0] +10000e70: 2401 movs r4, #1 +10000e72: 2d00 cmp r5, #0 +10000e74: d1fa bne.n 10000e6c +10000e76: e8c0 4f45 strexb r5, r4, [r0] +10000e7a: 2d00 cmp r5, #0 +10000e7c: d1f6 bne.n 10000e6c +10000e7e: f3bf 8f5f dmb sy +10000e82: f9b1 e002 ldrsh.w lr, [r1, #2] +10000e86: 694c ldr r4, [r1, #20] +10000e88: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000e8c: f1be 0f00 cmp.w lr, #0 +10000e90: ea4f 05cc mov.w r5, ip, lsl #3 +10000e94: 6908 ldr r0, [r1, #16] +10000e96: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000e9a: db3c blt.n 10000f16 +10000e9c: 5b66 ldrh r6, [r4, r5] +10000e9e: 804e strh r6, [r1, #2] +10000ea0: 2600 movs r6, #0 +10000ea2: e8c0 6f8f stlb r6, [r0] +10000ea6: f387 8810 msr PRIMASK, r7 +10000eaa: f8bc 0002 ldrh.w r0, [ip, #2] +10000eae: e9cc 2302 strd r2, r3, [ip, #8] +10000eb2: 3001 adds r0, #1 +10000eb4: f3c0 000e ubfx r0, r0, #0, #15 +10000eb8: 2801 cmp r0, #1 +10000eba: bf38 it cc +10000ebc: 2001 movcc r0, #1 +10000ebe: 9b05 ldr r3, [sp, #20] +10000ec0: f8ac 0002 strh.w r0, [ip, #2] +10000ec4: f8cc 3010 str.w r3, [ip, #16] +10000ec8: 9b06 ldr r3, [sp, #24] +10000eca: ea40 400e orr.w r0, r0, lr, lsl #16 +10000ece: f8cc 3014 str.w r3, [ip, #20] +10000ed2: 690b ldr r3, [r1, #16] +10000ed4: f3ef 8210 mrs r2, PRIMASK +10000ed8: b672 cpsid i +10000eda: e8d3 cfcf ldaexb ip, [r3] +10000ede: 2701 movs r7, #1 +10000ee0: f1bc 0f00 cmp.w ip, #0 +10000ee4: d1f9 bne.n 10000eda +10000ee6: e8c3 7f4c strexb ip, r7, [r3] +10000eea: f1bc 0f00 cmp.w ip, #0 +10000eee: d1f4 bne.n 10000eda +10000ef0: f3bf 8f5f dmb sy +10000ef4: 888b ldrh r3, [r1, #4] +10000ef6: 5363 strh r3, [r4, r5] +10000ef8: f8a1 e004 strh.w lr, [r1, #4] +10000efc: 690b ldr r3, [r1, #16] +10000efe: e8c3 6f8f stlb r6, [r3] +10000f02: f382 8810 msr PRIMASK, r2 +10000f06: 2201 movs r2, #1 +10000f08: 68cb ldr r3, [r1, #12] +10000f0a: 7809 ldrb r1, [r1, #0] +10000f0c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000f10: 408a lsls r2, r1 +10000f12: 605a str r2, [r3, #4] +10000f14: bdf0 pop {r4, r5, r6, r7, pc} +10000f16: 2300 movs r3, #0 +10000f18: e8c0 3f8f stlb r3, [r0] +10000f1c: f387 8810 msr PRIMASK, r7 +10000f20: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000f24: bdf0 pop {r4, r5, r6, r7, pc} +10000f26: bf00 nop + +10000f28 : +10000f28: 4603 mov r3, r0 +10000f2a: 8940 ldrh r0, [r0, #10] +10000f2c: ebb0 4f21 cmp.w r0, r1, asr #16 +10000f30: dd37 ble.n 10000fa2 +10000f32: 6958 ldr r0, [r3, #20] +10000f34: 140a asrs r2, r1, #16 +10000f36: eb02 0242 add.w r2, r2, r2, lsl #1 +10000f3a: b510 push {r4, lr} +10000f3c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000f40: 691c ldr r4, [r3, #16] +10000f42: f3ef 8c10 mrs ip, PRIMASK +10000f46: b672 cpsid i +10000f48: e8d4 efcf ldaexb lr, [r4] +10000f4c: 2201 movs r2, #1 +10000f4e: f1be 0f00 cmp.w lr, #0 +10000f52: d1f9 bne.n 10000f48 +10000f54: e8c4 2f4e strexb lr, r2, [r4] +10000f58: f1be 0f00 cmp.w lr, #0 +10000f5c: d1f4 bne.n 10000f48 +10000f5e: f3bf 8f5f dmb sy +10000f62: 8842 ldrh r2, [r0, #2] +10000f64: b289 uxth r1, r1 +10000f66: b292 uxth r2, r2 +10000f68: 428a cmp r2, r1 +10000f6a: d007 beq.n 10000f7c +10000f6c: 2200 movs r2, #0 +10000f6e: 691b ldr r3, [r3, #16] +10000f70: e8c3 2f8f stlb r2, [r3] +10000f74: f38c 8810 msr PRIMASK, ip +10000f78: 2000 movs r0, #0 +10000f7a: bd10 pop {r4, pc} +10000f7c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000f80: 8042 strh r2, [r0, #2] +10000f82: 2101 movs r1, #1 +10000f84: 2200 movs r2, #0 +10000f86: 6918 ldr r0, [r3, #16] +10000f88: 7199 strb r1, [r3, #6] +10000f8a: e8c0 2f8f stlb r2, [r0] +10000f8e: f38c 8810 msr PRIMASK, ip +10000f92: 781c ldrb r4, [r3, #0] +10000f94: 68da ldr r2, [r3, #12] +10000f96: 4608 mov r0, r1 +10000f98: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000f9c: 40a1 lsls r1, r4 +10000f9e: 6059 str r1, [r3, #4] +10000fa0: bd10 pop {r4, pc} +10000fa2: 2000 movs r0, #0 +10000fa4: 4770 bx lr +10000fa6: bf00 nop + +10000fa8 : +10000fa8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000fac: b082 sub sp, #8 +10000fae: 4606 mov r6, r0 +10000fb0: f000 f8ec bl 1000118c +10000fb4: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000fb8: 4604 mov r4, r0 +10000fba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000fbe: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000fc2: fbe6 4103 umlal r4, r1, r6, r3 +10000fc6: 42a0 cmp r0, r4 +10000fc8: eb72 0301 sbcs.w r3, r2, r1 +10000fcc: bf3a itte cc +10000fce: 4604 movcc r4, r0 +10000fd0: 4615 movcc r5, r2 +10000fd2: 460d movcs r5, r1 +10000fd4: 1fa6 subs r6, r4, #6 +10000fd6: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000fda: 42b4 cmp r4, r6 +10000fdc: eb75 0307 sbcs.w r3, r5, r7 +10000fe0: bf3c itt cc +10000fe2: 2600 movcc r6, #0 +10000fe4: 4637 movcc r7, r6 +10000fe6: f000 f8d1 bl 1000118c +10000fea: 1a30 subs r0, r6, r0 +10000fec: eb67 0101 sbc.w r1, r7, r1 +10000ff0: 2801 cmp r0, #1 +10000ff2: f171 0100 sbcs.w r1, r1, #0 +10000ff6: da06 bge.n 10001006 +10000ff8: 4620 mov r0, r4 +10000ffa: 4629 mov r1, r5 +10000ffc: b002 add sp, #8 +10000ffe: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10001002: f000 b8fb b.w 100011fc +10001006: f000 f8c1 bl 1000118c +1000100a: 4286 cmp r6, r0 +1000100c: eb67 0101 sbc.w r1, r7, r1 +10001010: 2900 cmp r1, #0 +10001012: db0a blt.n 1000102a +10001014: 2100 movs r1, #0 +10001016: 4b17 ldr r3, [pc, #92] @ (10001074 ) +10001018: 4632 mov r2, r6 +1000101a: 9300 str r3, [sp, #0] +1000101c: 4816 ldr r0, [pc, #88] @ (10001078 ) +1000101e: 463b mov r3, r7 +10001020: 9101 str r1, [sp, #4] +10001022: f7ff ff1d bl 10000e60 +10001026: 3001 adds r0, #1 +10001028: d0e6 beq.n 10000ff8 +1000102a: f04f 0c00 mov.w ip, #0 +1000102e: 4a13 ldr r2, [pc, #76] @ (1000107c ) +10001030: 4913 ldr r1, [pc, #76] @ (10001080 ) +10001032: 6a53 ldr r3, [r2, #36] @ 0x24 +10001034: 429f cmp r7, r3 +10001036: d804 bhi.n 10001042 +10001038: 6a90 ldr r0, [r2, #40] @ 0x28 +1000103a: 42b0 cmp r0, r6 +1000103c: d2dc bcs.n 10000ff8 +1000103e: 429f cmp r7, r3 +10001040: d1da bne.n 10000ff8 +10001042: 680b ldr r3, [r1, #0] +10001044: f3ef 8010 mrs r0, PRIMASK +10001048: b672 cpsid i +1000104a: e8d3 8fcf ldaexb r8, [r3] +1000104e: f05f 0e01 movs.w lr, #1 +10001052: f1b8 0f00 cmp.w r8, #0 +10001056: d1f8 bne.n 1000104a +10001058: e8c3 ef48 strexb r8, lr, [r3] +1000105c: f1b8 0f00 cmp.w r8, #0 +10001060: d1f3 bne.n 1000104a +10001062: f3bf 8f5f dmb sy +10001066: 680b ldr r3, [r1, #0] +10001068: e8c3 cf8f stlb ip, [r3] +1000106c: f380 8810 msr PRIMASK, r0 +10001070: bf20 wfe +10001072: e7de b.n 10001032 +10001074: 10000a31 .word 0x10000a31 +10001078: 200005f4 .word 0x200005f4 +1000107c: 400b0000 .word 0x400b0000 +10001080: 2000084c .word 0x2000084c + +10001084 : +10001084: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10001088: 4606 mov r6, r0 +1000108a: 460d mov r5, r1 +1000108c: b083 sub sp, #12 +1000108e: f3ef 8405 mrs r4, IPSR +10001092: b2e4 uxtb r4, r4 +10001094: b13c cbz r4, 100010a6 +10001096: 4b2d ldr r3, [pc, #180] @ (1000114c ) +10001098: 6a5a ldr r2, [r3, #36] @ 0x24 +1000109a: 42aa cmp r2, r5 +1000109c: d21c bcs.n 100010d8 +1000109e: 2000 movs r0, #0 +100010a0: b003 add sp, #12 +100010a2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100010a6: 4f2a ldr r7, [pc, #168] @ (10001150 ) +100010a8: f8d7 900c ldr.w r9, [r7, #12] +100010ac: f897 8000 ldrb.w r8, [r7] +100010b0: 4648 mov r0, r9 +100010b2: f000 f863 bl 1000117c +100010b6: f108 0804 add.w r8, r8, #4 +100010ba: f859 3028 ldr.w r3, [r9, r8, lsl #2] +100010be: 1a1b subs r3, r3, r0 +100010c0: 1a30 subs r0, r6, r0 +100010c2: eb65 0101 sbc.w r1, r5, r1 +100010c6: 4298 cmp r0, r3 +100010c8: f171 0100 sbcs.w r1, r1, #0 +100010cc: db10 blt.n 100010f0 +100010ce: bf20 wfe +100010d0: 4b1e ldr r3, [pc, #120] @ (1000114c ) +100010d2: 6a5a ldr r2, [r3, #36] @ 0x24 +100010d4: 42aa cmp r2, r5 +100010d6: d3e2 bcc.n 1000109e +100010d8: bf14 ite ne +100010da: 2401 movne r4, #1 +100010dc: 2400 moveq r4, #0 +100010de: 6a9b ldr r3, [r3, #40] @ 0x28 +100010e0: 42b3 cmp r3, r6 +100010e2: bf34 ite cc +100010e4: 4620 movcc r0, r4 +100010e6: f044 0001 orrcs.w r0, r4, #1 +100010ea: b003 add sp, #12 +100010ec: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100010f0: f000 f84c bl 1000118c +100010f4: 4286 cmp r6, r0 +100010f6: eb65 0101 sbc.w r1, r5, r1 +100010fa: 2900 cmp r1, #0 +100010fc: db14 blt.n 10001128 +100010fe: 4b15 ldr r3, [pc, #84] @ (10001154 ) +10001100: 4638 mov r0, r7 +10001102: e9cd 3400 strd r3, r4, [sp] +10001106: 4632 mov r2, r6 +10001108: 462b mov r3, r5 +1000110a: f7ff fea9 bl 10000e60 +1000110e: 1e01 subs r1, r0, #0 +10001110: dd0a ble.n 10001128 +10001112: 4b0e ldr r3, [pc, #56] @ (1000114c ) +10001114: 6a5a ldr r2, [r3, #36] @ 0x24 +10001116: 42aa cmp r2, r5 +10001118: d316 bcc.n 10001148 +1000111a: 6a9b ldr r3, [r3, #40] @ 0x28 +1000111c: 42b3 cmp r3, r6 +1000111e: d311 bcc.n 10001144 +10001120: 480b ldr r0, [pc, #44] @ (10001150 ) +10001122: f7ff ff01 bl 10000f28 +10001126: e7b6 b.n 10001096 +10001128: 4b08 ldr r3, [pc, #32] @ (1000114c ) +1000112a: 6a5c ldr r4, [r3, #36] @ 0x24 +1000112c: 42ac cmp r4, r5 +1000112e: d3b6 bcc.n 1000109e +10001130: 1b64 subs r4, r4, r5 +10001132: bf18 it ne +10001134: 2401 movne r4, #1 +10001136: 6a9b ldr r3, [r3, #40] @ 0x28 +10001138: 42b3 cmp r3, r6 +1000113a: bf34 ite cc +1000113c: 4620 movcc r0, r4 +1000113e: f044 0001 orrcs.w r0, r4, #1 +10001142: e7ad b.n 100010a0 +10001144: 42aa cmp r2, r5 +10001146: d1eb bne.n 10001120 +10001148: bf20 wfe +1000114a: e7e9 b.n 10001120 +1000114c: 400b0000 .word 0x400b0000 +10001150: 200005f4 .word 0x200005f4 +10001154: 10000a31 .word 0x10000a31 + +10001158 : +10001158: b410 push {r4} +1000115a: 4b05 ldr r3, [pc, #20] @ (10001170 ) +1000115c: 4c05 ldr r4, [pc, #20] @ (10001174 ) +1000115e: 4a06 ldr r2, [pc, #24] @ (10001178 ) +10001160: 42a0 cmp r0, r4 +10001162: bf14 ite ne +10001164: 4618 movne r0, r3 +10001166: 1c58 addeq r0, r3, #1 +10001168: f85d 4b04 ldr.w r4, [sp], #4 +1000116c: f7ff ba2a b.w 100005c4 +10001170: 200007d8 .word 0x200007d8 +10001174: 400b8000 .word 0x400b8000 +10001178: 100038fc .word 0x100038fc + +1000117c : +1000117c: 4603 mov r3, r0 +1000117e: 6a41 ldr r1, [r0, #36] @ 0x24 +10001180: 460a mov r2, r1 +10001182: 6a98 ldr r0, [r3, #40] @ 0x28 +10001184: 6a59 ldr r1, [r3, #36] @ 0x24 +10001186: 428a cmp r2, r1 +10001188: d1fa bne.n 10001180 +1000118a: 4770 bx lr + +1000118c : +1000118c: 4b03 ldr r3, [pc, #12] @ (1000119c ) +1000118e: 6a59 ldr r1, [r3, #36] @ 0x24 +10001190: 460a mov r2, r1 +10001192: 6a98 ldr r0, [r3, #40] @ 0x28 +10001194: 6a59 ldr r1, [r3, #36] @ 0x24 +10001196: 4291 cmp r1, r2 +10001198: d1fa bne.n 10001190 +1000119a: 4770 bx lr +1000119c: 400b0000 .word 0x400b0000 + +100011a0 : +100011a0: b430 push {r4, r5} +100011a2: 4a15 ldr r2, [pc, #84] @ (100011f8 ) +100011a4: 6a53 ldr r3, [r2, #36] @ 0x24 +100011a6: 469c mov ip, r3 +100011a8: 6a94 ldr r4, [r2, #40] @ 0x28 +100011aa: 6a53 ldr r3, [r2, #36] @ 0x24 +100011ac: 4563 cmp r3, ip +100011ae: d1fa bne.n 100011a6 +100011b0: 1902 adds r2, r0, r4 +100011b2: 4159 adcs r1, r3 +100011b4: f04f 0500 mov.w r5, #0 +100011b8: bf28 it cs +100011ba: 2501 movcs r5, #1 +100011bc: 4b0e ldr r3, [pc, #56] @ (100011f8 ) +100011be: 6a5b ldr r3, [r3, #36] @ 0x24 +100011c0: b1b5 cbz r5, 100011f0 +100011c2: 1c5a adds r2, r3, #1 +100011c4: bf08 it eq +100011c6: 461a moveq r2, r3 +100011c8: d008 beq.n 100011dc +100011ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100011ce: 460a mov r2, r1 +100011d0: 4809 ldr r0, [pc, #36] @ (100011f8 ) +100011d2: 6a43 ldr r3, [r0, #36] @ 0x24 +100011d4: 428b cmp r3, r1 +100011d6: d3fc bcc.n 100011d2 +100011d8: 428b cmp r3, r1 +100011da: d107 bne.n 100011ec +100011dc: 4906 ldr r1, [pc, #24] @ (100011f8 ) +100011de: e002 b.n 100011e6 +100011e0: 6a48 ldr r0, [r1, #36] @ 0x24 +100011e2: 4298 cmp r0, r3 +100011e4: d102 bne.n 100011ec +100011e6: 6a88 ldr r0, [r1, #40] @ 0x28 +100011e8: 4290 cmp r0, r2 +100011ea: d3f9 bcc.n 100011e0 +100011ec: bc30 pop {r4, r5} +100011ee: 4770 bx lr +100011f0: 4299 cmp r1, r3 +100011f2: d8ed bhi.n 100011d0 +100011f4: e7f0 b.n 100011d8 +100011f6: bf00 nop +100011f8: 400b0000 .word 0x400b0000 + +100011fc : +100011fc: 4a07 ldr r2, [pc, #28] @ (1000121c ) +100011fe: 6a53 ldr r3, [r2, #36] @ 0x24 +10001200: 4299 cmp r1, r3 +10001202: d8fc bhi.n 100011fe +10001204: 4299 cmp r1, r3 +10001206: d107 bne.n 10001218 +10001208: 4b04 ldr r3, [pc, #16] @ (1000121c ) +1000120a: e002 b.n 10001212 +1000120c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000120e: 4291 cmp r1, r2 +10001210: d102 bne.n 10001218 +10001212: 6a9a ldr r2, [r3, #40] @ 0x28 +10001214: 4290 cmp r0, r2 +10001216: d8f9 bhi.n 1000120c +10001218: 4770 bx lr +1000121a: bf00 nop +1000121c: 400b0000 .word 0x400b0000 + +10001220 : +10001220: b5f8 push {r3, r4, r5, r6, r7, lr} +10001222: 4605 mov r5, r0 +10001224: 2006 movs r0, #6 +10001226: 460e mov r6, r1 +10001228: f000 f8e4 bl 100013f4 +1000122c: 2800 cmp r0, #0 +1000122e: d042 beq.n 100012b6 +10001230: 4a35 ldr r2, [pc, #212] @ (10001308 ) +10001232: 4836 ldr r0, [pc, #216] @ (1000130c ) +10001234: 4295 cmp r5, r2 +10001236: bf14 ite ne +10001238: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +1000123c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10001240: 4b33 ldr r3, [pc, #204] @ (10001310 ) +10001242: 4934 ldr r1, [pc, #208] @ (10001314 ) +10001244: 6002 str r2, [r0, #0] +10001246: 601a str r2, [r3, #0] +10001248: 688c ldr r4, [r1, #8] +1000124a: ea32 0404 bics.w r4, r2, r4 +1000124e: d1fb bne.n 10001248 +10001250: 4b2d ldr r3, [pc, #180] @ (10001308 ) +10001252: f44f 7180 mov.w r1, #256 @ 0x100 +10001256: 1aeb subs r3, r5, r3 +10001258: fab3 f383 clz r3, r3 +1000125c: 4a2e ldr r2, [pc, #184] @ (10001318 ) +1000125e: 095b lsrs r3, r3, #5 +10001260: 2006 movs r0, #6 +10001262: f822 1013 strh.w r1, [r2, r3, lsl #1] +10001266: f000 f8c5 bl 100013f4 +1000126a: 00c3 lsls r3, r0, #3 +1000126c: fbb3 f3f6 udiv r3, r3, r6 +10001270: 3301 adds r3, #1 +10001272: 09da lsrs r2, r3, #7 +10001274: d120 bne.n 100012b8 +10001276: 2640 movs r6, #64 @ 0x40 +10001278: 2101 movs r1, #1 +1000127a: 6269 str r1, [r5, #36] @ 0x24 +1000127c: 62aa str r2, [r5, #40] @ 0x28 +1000127e: 6b2f ldr r7, [r5, #48] @ 0x30 +10001280: 07fb lsls r3, r7, #31 +10001282: d422 bmi.n 100012ca +10001284: 462b mov r3, r5 +10001286: 2200 movs r2, #0 +10001288: f853 1f2c ldr.w r1, [r3, #44]! +1000128c: 2006 movs r0, #6 +1000128e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10001292: 6022 str r2, [r4, #0] +10001294: 632f str r7, [r5, #48] @ 0x30 +10001296: f000 f8ad bl 100013f4 +1000129a: f240 3101 movw r1, #769 @ 0x301 +1000129e: 2203 movs r2, #3 +100012a0: 0080 lsls r0, r0, #2 +100012a2: fbb0 f0f6 udiv r0, r0, r6 +100012a6: 6aeb ldr r3, [r5, #44] @ 0x2c +100012a8: f083 0370 eor.w r3, r3, #112 @ 0x70 +100012ac: f003 037e and.w r3, r3, #126 @ 0x7e +100012b0: 6023 str r3, [r4, #0] +100012b2: 6329 str r1, [r5, #48] @ 0x30 +100012b4: 64aa str r2, [r5, #72] @ 0x48 +100012b6: bdf8 pop {r3, r4, r5, r6, r7, pc} +100012b8: f64f 71fe movw r1, #65534 @ 0xfffe +100012bc: 428a cmp r2, r1 +100012be: d91b bls.n 100012f8 +100012c0: 4622 mov r2, r4 +100012c2: f64f 71ff movw r1, #65535 @ 0xffff +100012c6: 4e15 ldr r6, [pc, #84] @ (1000131c ) +100012c8: e7d7 b.n 1000127a +100012ca: f240 3201 movw r2, #769 @ 0x301 +100012ce: f505 5340 add.w r3, r5, #12288 @ 0x3000 +100012d2: 631a str r2, [r3, #48] @ 0x30 +100012d4: 6a6b ldr r3, [r5, #36] @ 0x24 +100012d6: 6aac ldr r4, [r5, #40] @ 0x28 +100012d8: 2006 movs r0, #6 +100012da: eb04 1483 add.w r4, r4, r3, lsl #6 +100012de: f000 f889 bl 100013f4 +100012e2: 4b0f ldr r3, [pc, #60] @ (10001320 ) +100012e4: 02a4 lsls r4, r4, #10 +100012e6: fba3 2300 umull r2, r3, r3, r0 +100012ea: 0adb lsrs r3, r3, #11 +100012ec: 2100 movs r1, #0 +100012ee: fbb4 f0f3 udiv r0, r4, r3 +100012f2: f7ff ff55 bl 100011a0 +100012f6: e7c5 b.n 10001284 +100012f8: f3c3 0345 ubfx r3, r3, #1, #6 +100012fc: 4611 mov r1, r2 +100012fe: eb03 1682 add.w r6, r3, r2, lsl #6 +10001302: 461a mov r2, r3 +10001304: e7b9 b.n 1000127a +10001306: bf00 nop +10001308: 40078000 .word 0x40078000 +1000130c: 40022000 .word 0x40022000 +10001310: 40023000 .word 0x40023000 +10001314: 40020000 .word 0x40020000 +10001318: 20000850 .word 0x20000850 +1000131c: 003fffc0 .word 0x003fffc0 +10001320: 8f2b7b75 .word 0x8f2b7b75 + +10001324 : +10001324: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001328: ea4f 0c8c mov.w ip, ip, lsl #2 +1000132c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001330: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10001334: b5f0 push {r4, r5, r6, r7, lr} +10001336: 4616 mov r6, r2 +10001338: f8dc 2004 ldr.w r2, [ip, #4] +1000133c: 1f05 subs r5, r0, #4 +1000133e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10001342: bf38 it cc +10001344: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10001348: b2ed uxtb r5, r5 +1000134a: bf38 it cc +1000134c: f8cc 2004 strcc.w r2, [ip, #4] +10001350: 2d01 cmp r5, #1 +10001352: d92a bls.n 100013aa +10001354: f44f 6700 mov.w r7, #2048 @ 0x800 +10001358: 4c25 ldr r4, [pc, #148] @ (100013f0 ) +1000135a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1000135e: 6017 str r7, [r2, #0] +10001360: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10001364: b9b2 cbnz r2, 10001394 +10001366: f8dc 2000 ldr.w r2, [ip] +1000136a: 2d01 cmp r5, #1 +1000136c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001370: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001374: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001378: 6032 str r2, [r6, #0] +1000137a: d92a bls.n 100013d2 +1000137c: f44f 6100 mov.w r1, #2048 @ 0x800 +10001380: f844 3020 str.w r3, [r4, r0, lsl #2] +10001384: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001388: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1000138c: 6011 str r1, [r2, #0] +1000138e: f8cc 3004 str.w r3, [ip, #4] +10001392: bdf0 pop {r4, r5, r6, r7, pc} +10001394: 6967 ldr r7, [r4, #20] +10001396: fbb7 fef2 udiv lr, r7, r2 +1000139a: f10e 0e01 add.w lr, lr, #1 +1000139e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +100013a2: f1be 0e03 subs.w lr, lr, #3 +100013a6: d2fc bcs.n 100013a2 +100013a8: e7dd b.n 10001366 +100013aa: 2901 cmp r1, #1 +100013ac: d1d2 bne.n 10001354 +100013ae: 2403 movs r4, #3 +100013b0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100013b4: 6014 str r4, [r2, #0] +100013b6: f8dc 2008 ldr.w r2, [ip, #8] +100013ba: 07d2 lsls r2, r2, #31 +100013bc: d5fb bpl.n 100013b6 +100013be: f8dc 2000 ldr.w r2, [ip] +100013c2: 4c0b ldr r4, [pc, #44] @ (100013f0 ) +100013c4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100013c8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100013cc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100013d0: 6032 str r2, [r6, #0] +100013d2: 2201 movs r2, #1 +100013d4: f8dc 5000 ldr.w r5, [ip] +100013d8: 404d eors r5, r1 +100013da: f005 0503 and.w r5, r5, #3 +100013de: 6035 str r5, [r6, #0] +100013e0: fa02 f101 lsl.w r1, r2, r1 +100013e4: f8dc 2008 ldr.w r2, [ip, #8] +100013e8: 420a tst r2, r1 +100013ea: d0fb beq.n 100013e4 +100013ec: e7c6 b.n 1000137c +100013ee: bf00 nop +100013f0: 200007dc .word 0x200007dc + +100013f4 : +100013f4: 4b01 ldr r3, [pc, #4] @ (100013fc ) +100013f6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +100013fa: 4770 bx lr +100013fc: 200007dc .word 0x200007dc + +10001400 : +10001400: b470 push {r4, r5, r6} +10001402: 9d03 ldr r5, [sp, #12] +10001404: 6804 ldr r4, [r0, #0] +10001406: 032d lsls r5, r5, #12 +10001408: ea45 4503 orr.w r5, r5, r3, lsl #16 +1000140c: 4b1b ldr r3, [pc, #108] @ (1000147c ) +1000140e: 2c00 cmp r4, #0 +10001410: fbb3 f3f1 udiv r3, r3, r1 +10001414: fbb2 f6f3 udiv r6, r2, r3 +10001418: db1f blt.n 1000145a +1000141a: 4a19 ldr r2, [pc, #100] @ (10001480 ) +1000141c: 4b19 ldr r3, [pc, #100] @ (10001484 ) +1000141e: 4290 cmp r0, r2 +10001420: bf14 ite ne +10001422: f44f 4280 movne.w r2, #16384 @ 0x4000 +10001426: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1000142a: 4c17 ldr r4, [pc, #92] @ (10001488 ) +1000142c: 601a str r2, [r3, #0] +1000142e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10001432: 601a str r2, [r3, #0] +10001434: 68a3 ldr r3, [r4, #8] +10001436: ea32 0303 bics.w r3, r2, r3 +1000143a: d1fb bne.n 10001434 +1000143c: 2221 movs r2, #33 @ 0x21 +1000143e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10001442: 3304 adds r3, #4 +10001444: 6001 str r1, [r0, #0] +10001446: 6086 str r6, [r0, #8] +10001448: 601a str r2, [r3, #0] +1000144a: 6802 ldr r2, [r0, #0] +1000144c: 2a00 cmp r2, #0 +1000144e: dafc bge.n 1000144a +10001450: 2208 movs r2, #8 +10001452: 60c5 str r5, [r0, #12] +10001454: 601a str r2, [r3, #0] +10001456: bc70 pop {r4, r5, r6} +10001458: 4770 bx lr +1000145a: 6803 ldr r3, [r0, #0] +1000145c: f003 033f and.w r3, r3, #63 @ 0x3f +10001460: 428b cmp r3, r1 +10001462: d1da bne.n 1000141a +10001464: 6883 ldr r3, [r0, #8] +10001466: f3c3 030b ubfx r3, r3, #0, #12 +1000146a: 42b3 cmp r3, r6 +1000146c: d1d5 bne.n 1000141a +1000146e: 68c3 ldr r3, [r0, #12] +10001470: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10001474: 42ab cmp r3, r5 +10001476: d1d0 bne.n 1000141a +10001478: e7ed b.n 10001456 +1000147a: bf00 nop +1000147c: 00b71b00 .word 0x00b71b00 +10001480: 40058000 .word 0x40058000 +10001484: 40022000 .word 0x40022000 +10001488: 40020000 .word 0x40020000 + +1000148c : +1000148c: 2301 movs r3, #1 +1000148e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001492: 0080 lsls r0, r0, #2 +10001494: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001498: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000149c: 6041 str r1, [r0, #4] +1000149e: 6003 str r3, [r0, #0] +100014a0: 4770 bx lr +100014a2: bf00 nop + +100014a4 : +100014a4: 2300 movs r3, #0 +100014a6: 8adb ldrh r3, [r3, #22] +100014a8: 2200 movs r2, #0 +100014aa: e842 f200 tt r2, r2 +100014ae: 0252 lsls r2, r2, #9 +100014b0: d401 bmi.n 100014b6 +100014b2: 2110 movs r1, #16 +100014b4: 4718 bx r3 +100014b6: 2104 movs r1, #4 +100014b8: 4718 bx r3 +100014ba: bf00 nop + +100014bc : +100014bc: 4a03 ldr r2, [pc, #12] @ (100014cc ) +100014be: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100014c2: 2b00 cmp r3, #0 +100014c4: d0fb beq.n 100014be +100014c6: f3bf 8f5f dmb sy +100014ca: 4770 bx lr +100014cc: 400e0000 .word 0x400e0000 + +100014d0 : +100014d0: 2100 movs r1, #0 +100014d2: 4b04 ldr r3, [pc, #16] @ (100014e4 ) +100014d4: 4a04 ldr r2, [pc, #16] @ (100014e8 ) +100014d6: f3bf 8f5f dmb sy +100014da: f843 1b04 str.w r1, [r3], #4 +100014de: 4293 cmp r3, r2 +100014e0: d1f9 bne.n 100014d6 +100014e2: 4770 bx lr +100014e4: 400e080c .word 0x400e080c +100014e8: 400e082c .word 0x400e082c + +100014ec : +100014ec: b410 push {r4} +100014ee: f44f 708d mov.w r0, #282 @ 0x11a +100014f2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100014f6: 4a06 ldr r2, [pc, #24] @ (10001510 ) +100014f8: 4b06 ldr r3, [pc, #24] @ (10001514 ) +100014fa: 4907 ldr r1, [pc, #28] @ (10001518 ) +100014fc: 6014 str r4, [r2, #0] +100014fe: 60d0 str r0, [r2, #12] +10001500: 6019 str r1, [r3, #0] +10001502: 6853 ldr r3, [r2, #4] +10001504: 2b00 cmp r3, #0 +10001506: dafc bge.n 10001502 +10001508: f85d 4b04 ldr.w r4, [sp], #4 +1000150c: 4770 bx lr +1000150e: bf00 nop +10001510: 40048000 .word 0x40048000 +10001514: 4004a000 .word 0x4004a000 +10001518: 00fab000 .word 0x00fab000 + +1000151c : +1000151c: 4770 bx lr +1000151e: bf00 nop + +10001520 : +10001520: b508 push {r3, lr} +10001522: 4801 ldr r0, [pc, #4] @ (10001528 ) +10001524: f7ff f836 bl 10000594 +10001528: 10003920 .word 0x10003920 + +1000152c : +1000152c: b538 push {r3, r4, r5, lr} +1000152e: 4c05 ldr r4, [pc, #20] @ (10001544 ) +10001530: 4d05 ldr r5, [pc, #20] @ (10001548 ) +10001532: 42ac cmp r4, r5 +10001534: d204 bcs.n 10001540 +10001536: f854 3b04 ldr.w r3, [r4], #4 +1000153a: 4798 blx r3 +1000153c: 42ac cmp r4, r5 +1000153e: d3fa bcc.n 10001536 +10001540: bd38 pop {r3, r4, r5, pc} +10001542: bf00 nop +10001544: 10003868 .word 0x10003868 +10001548: 100038a8 .word 0x100038a8 + +1000154c : +1000154c: b410 push {r4} +1000154e: 4807 ldr r0, [pc, #28] @ (1000156c ) +10001550: 4c07 ldr r4, [pc, #28] @ (10001570 ) +10001552: 4b08 ldr r3, [pc, #32] @ (10001574 ) +10001554: 4a08 ldr r2, [pc, #32] @ (10001578 ) +10001556: 4909 ldr r1, [pc, #36] @ (1000157c ) +10001558: 6004 str r4, [r0, #0] +1000155a: 601a str r2, [r3, #0] +1000155c: 688b ldr r3, [r1, #8] +1000155e: ea32 0303 bics.w r3, r2, r3 +10001562: d1fb bne.n 1000155c +10001564: f85d 4b04 ldr.w r4, [sp], #4 +10001568: 4770 bx lr +1000156a: bf00 nop +1000156c: 40022000 .word 0x40022000 +10001570: efef3b7f .word 0xefef3b7f +10001574: 40023000 .word 0x40023000 +10001578: 03f3fff6 .word 0x03f3fff6 +1000157c: 40020000 .word 0x40020000 + +10001580 : +10001580: 4b04 ldr r3, [pc, #16] @ (10001594 ) +10001582: 6cdb ldr r3, [r3, #76] @ 0x4c +10001584: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001588: d103 bne.n 10001592 +1000158a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000158e: 4b02 ldr r3, [pc, #8] @ (10001598 ) +10001590: 64da str r2, [r3, #76] @ 0x4c +10001592: 4770 bx lr +10001594: 50110000 .word 0x50110000 +10001598: 50112000 .word 0x50112000 + +1000159c : +1000159c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100015a0: 4b04 ldr r3, [pc, #16] @ (100015b4 ) +100015a2: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100015a6: 430b orrs r3, r1 +100015a8: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100015ac: ee10 0430 dcp_rcmp r0 +100015b0: 4770 bx lr +100015b2: bf00 nop +100015b4: 00300303 .word 0x00300303 + +100015b8 : +100015b8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100015bc: 4b04 ldr r3, [pc, #16] @ (100015d0 ) +100015be: 4a05 ldr r2, [pc, #20] @ (100015d4 ) +100015c0: 6019 str r1, [r3, #0] +100015c2: 6893 ldr r3, [r2, #8] +100015c4: 43db mvns r3, r3 +100015c6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100015ca: d1fa bne.n 100015c2 +100015cc: 4770 bx lr +100015ce: bf00 nop +100015d0: 40023000 .word 0x40023000 +100015d4: 40020000 .word 0x40020000 + +100015d8 : +100015d8: b510 push {r4, lr} +100015da: f245 2053 movw r0, #21075 @ 0x5253 +100015de: f7ff ff61 bl 100014a4 +100015e2: e8bd 4010 ldmia.w sp!, {r4, lr} +100015e6: 4603 mov r3, r0 +100015e8: 2004 movs r0, #4 +100015ea: 4718 bx r3 + +100015ec : +100015ec: b510 push {r4, lr} +100015ee: f245 2053 movw r0, #21075 @ 0x5253 +100015f2: f7ff ff57 bl 100014a4 +100015f6: e8bd 4010 ldmia.w sp!, {r4, lr} +100015fa: 4603 mov r3, r0 +100015fc: 2001 movs r0, #1 +100015fe: 4718 bx r3 + +10001600 : +10001600: f7ff b820 b.w 10000644 + +10001604 : +10001604: 4914 ldr r1, [pc, #80] @ (10001658 ) +10001606: 4b15 ldr r3, [pc, #84] @ (1000165c ) +10001608: b570 push {r4, r5, r6, lr} +1000160a: 1a5c subs r4, r3, r1 +1000160c: 10a6 asrs r6, r4, #2 +1000160e: 2e44 cmp r6, #68 @ 0x44 +10001610: 4632 mov r2, r6 +10001612: bf28 it cs +10001614: 2244 movcs r2, #68 @ 0x44 +10001616: 4d12 ldr r5, [pc, #72] @ (10001660 ) +10001618: 0092 lsls r2, r2, #2 +1000161a: 4628 mov r0, r5 +1000161c: f002 f872 bl 10003704 +10001620: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10001624: d813 bhi.n 1000164e +10001626: 4a0f ldr r2, [pc, #60] @ (10001664 ) +10001628: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1000162c: d012 beq.n 10001654 +1000162e: 192b adds r3, r5, r4 +10001630: 0841 lsrs r1, r0, #1 +10001632: eb03 01c1 add.w r1, r3, r1, lsl #3 +10001636: e9c3 2200 strd r2, r2, [r3] +1000163a: 3308 adds r3, #8 +1000163c: 428b cmp r3, r1 +1000163e: d1fa bne.n 10001636 +10001640: 07c3 lsls r3, r0, #31 +10001642: d504 bpl.n 1000164e +10001644: f020 0001 bic.w r0, r0, #1 +10001648: 4430 add r0, r6 +1000164a: f845 2020 str.w r2, [r5, r0, lsl #2] +1000164e: 4b06 ldr r3, [pc, #24] @ (10001668 ) +10001650: 609d str r5, [r3, #8] +10001652: bd70 pop {r4, r5, r6, pc} +10001654: 2043 movs r0, #67 @ 0x43 +10001656: e7f8 b.n 1000164a +10001658: 10000000 .word 0x10000000 +1000165c: 10000110 .word 0x10000110 +10001660: 20000000 .word 0x20000000 +10001664: 10000111 .word 0x10000111 +10001668: e000ed00 .word 0xe000ed00 + +1000166c : +1000166c: 2300 movs r3, #0 +1000166e: b570 push {r4, r5, r6, lr} +10001670: 4c2b ldr r4, [pc, #172] @ (10001720 ) +10001672: b082 sub sp, #8 +10001674: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10001678: f7ff ff38 bl 100014ec +1000167c: 2201 movs r2, #1 +1000167e: 4b29 ldr r3, [pc, #164] @ (10001724 ) +10001680: 63da str r2, [r3, #60] @ 0x3c +10001682: 6c63 ldr r3, [r4, #68] @ 0x44 +10001684: 2b01 cmp r3, #1 +10001686: d1fc bne.n 10001682 +10001688: 2103 movs r1, #3 +1000168a: 4a26 ldr r2, [pc, #152] @ (10001724 ) +1000168c: 4b24 ldr r3, [pc, #144] @ (10001720 ) +1000168e: 6311 str r1, [r2, #48] @ 0x30 +10001690: 6b9c ldr r4, [r3, #56] @ 0x38 +10001692: 2c01 cmp r4, #1 +10001694: d1fc bne.n 10001690 +10001696: 2602 movs r6, #2 +10001698: 2505 movs r5, #5 +1000169a: 4621 mov r1, r4 +1000169c: 2305 movs r3, #5 +1000169e: 4a22 ldr r2, [pc, #136] @ (10001728 ) +100016a0: 4822 ldr r0, [pc, #136] @ (1000172c ) +100016a2: 9600 str r6, [sp, #0] +100016a4: f7ff feac bl 10001400 +100016a8: 4621 mov r1, r4 +100016aa: 462b mov r3, r5 +100016ac: 4a20 ldr r2, [pc, #128] @ (10001730 ) +100016ae: 4821 ldr r0, [pc, #132] @ (10001734 ) +100016b0: 9500 str r5, [sp, #0] +100016b2: f7ff fea5 bl 10001400 +100016b6: 2200 movs r2, #0 +100016b8: 2004 movs r0, #4 +100016ba: 4631 mov r1, r6 +100016bc: 4b1e ldr r3, [pc, #120] @ (10001738 ) +100016be: f7ff fe31 bl 10001324 +100016c2: 4621 mov r1, r4 +100016c4: 4628 mov r0, r5 +100016c6: 2200 movs r2, #0 +100016c8: 4b1c ldr r3, [pc, #112] @ (1000173c ) +100016ca: f7ff fe2b bl 10001324 +100016ce: 2200 movs r2, #0 +100016d0: 2008 movs r0, #8 +100016d2: 4611 mov r1, r2 +100016d4: 4b1a ldr r3, [pc, #104] @ (10001740 ) +100016d6: f7ff fe25 bl 10001324 +100016da: 2200 movs r2, #0 +100016dc: 2009 movs r0, #9 +100016de: 4611 mov r1, r2 +100016e0: 4b17 ldr r3, [pc, #92] @ (10001740 ) +100016e2: f7ff fe1f bl 10001324 +100016e6: 2200 movs r2, #0 +100016e8: 2006 movs r0, #6 +100016ea: 4611 mov r1, r2 +100016ec: 4b13 ldr r3, [pc, #76] @ (1000173c ) +100016ee: f7ff fe19 bl 10001324 +100016f2: 2200 movs r2, #0 +100016f4: 4b11 ldr r3, [pc, #68] @ (1000173c ) +100016f6: 2007 movs r0, #7 +100016f8: 4611 mov r1, r2 +100016fa: f7ff fe13 bl 10001324 +100016fe: 2004 movs r0, #4 +10001700: f7ff fe78 bl 100013f4 +10001704: 2400 movs r4, #0 +10001706: 4b0f ldr r3, [pc, #60] @ (10001744 ) +10001708: fba3 3500 umull r3, r5, r3, r0 +1000170c: 0cad lsrs r5, r5, #18 +1000170e: b2e0 uxtb r0, r4 +10001710: 4629 mov r1, r5 +10001712: 3401 adds r4, #1 +10001714: f7ff feba bl 1000148c +10001718: 2c06 cmp r4, #6 +1000171a: d1f8 bne.n 1000170e +1000171c: b002 add sp, #8 +1000171e: bd70 pop {r4, r5, r6, pc} +10001720: 40010000 .word 0x40010000 +10001724: 40013000 .word 0x40013000 +10001728: 59682f00 .word 0x59682f00 +1000172c: 40050000 .word 0x40050000 +10001730: 47868c00 .word 0x47868c00 +10001734: 40058000 .word 0x40058000 +10001738: 00b71b00 .word 0x00b71b00 +1000173c: 08f0d180 .word 0x08f0d180 +10001740: 02dc6c00 .word 0x02dc6c00 +10001744: 431bde83 .word 0x431bde83 + +10001748 : +10001748: b086 sub sp, #24 +1000174a: b403 push {r0, r1} +1000174c: fc51 0408 dcp_pxmd r0, r1 +10001750: e9cd 0102 strd r0, r1, [sp, #8] +10001754: fc51 0409 dcp_pymd r0, r1 +10001758: e9cd 0104 strd r0, r1, [sp, #16] +1000175c: ec51 040a dcp_refd r0, r1 +10001760: e9cd 0106 strd r0, r1, [sp, #24] +10001764: bc03 pop {r0, r1} +10001766: 47f0 blx lr + +10001768 : +10001768: e8bd 5000 ldmia.w sp!, {ip, lr} +1000176c: ec4e c400 dcp_wxmd ip, lr +10001770: e8bd 5000 ldmia.w sp!, {ip, lr} +10001774: ec4e c401 dcp_wymd ip, lr +10001778: e8bd 5000 ldmia.w sp!, {ip, lr} +1000177c: ec4e c402 dcp_wefd ip, lr +10001780: bd00 pop {pc} +10001782: 0000 movs r0, r0 +10001784: b500 push {lr} +10001786: f7ff ffdf bl 10001748 +1000178a: e002 b.n 10001792 <__wrap___aeabi_dadd+0x6> + +1000178c <__wrap___aeabi_dadd>: +1000178c: fe10 f430 dcp_pcmp APSR_nzcv +10001790: d4f8 bmi.n 10001784 +10001792: ec41 0410 dcp_wxup r0, r1 +10001796: ec43 2411 dcp_wyup r2, r3 +1000179a: ee00 0401 dcp_add0 +1000179e: ee10 0401 dcp_add1 +100017a2: ee80 0420 dcp_nrdd +100017a6: ec51 0410 dcp_rdda r0, r1 +100017aa: 4770 bx lr +100017ac: b500 push {lr} +100017ae: f7ff ffcb bl 10001748 +100017b2: e002 b.n 100017ba <__wrap___aeabi_dsub+0x6> + +100017b4 <__wrap___aeabi_dsub>: +100017b4: fe10 f430 dcp_pcmp APSR_nzcv +100017b8: d4f8 bmi.n 100017ac <__wrap___aeabi_dadd+0x20> +100017ba: ec41 0410 dcp_wxup r0, r1 +100017be: ec43 2411 dcp_wyup r2, r3 +100017c2: ee00 0401 dcp_add0 +100017c6: ee10 0421 dcp_sub1 +100017ca: ee80 0420 dcp_nrdd +100017ce: ec51 0430 dcp_rdds r0, r1 +100017d2: 4770 bx lr +100017d4: b500 push {lr} +100017d6: f7ff ffb7 bl 10001748 +100017da: e002 b.n 100017e2 <__wrap___aeabi_dmul+0x6> + +100017dc <__wrap___aeabi_dmul>: +100017dc: fe10 f430 dcp_pcmp APSR_nzcv +100017e0: d4f8 bmi.n 100017d4 <__wrap___aeabi_dsub+0x20> +100017e2: b510 push {r4, lr} +100017e4: ec41 0410 dcp_wxup r0, r1 +100017e8: ec43 2411 dcp_wyup r2, r3 +100017ec: ec51 0404 dcp_rxms r0, r1, #0x0 +100017f0: ec53 2405 dcp_ryms r2, r3, #0x0 +100017f4: fba0 4c02 umull r4, ip, r0, r2 +100017f8: f05f 0e00 movs.w lr, #0 +100017fc: fbe0 ce03 umlal ip, lr, r0, r3 +10001800: fbe1 ce02 umlal ip, lr, r1, r2 +10001804: ec4c 4420 dcp_wxms r4, ip +10001808: 2400 movs r4, #0 +1000180a: fbe1 e403 umlal lr, r4, r1, r3 +1000180e: ec44 e430 dcp_wxmo lr, r4 +10001812: ee80 0420 dcp_nrdd +10001816: ec51 0450 dcp_rddm r0, r1 +1000181a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000181e: 4770 bx lr +10001820: b500 push {lr} +10001822: f7ff ff91 bl 10001748 +10001826: e002 b.n 1000182e <__wrap___aeabi_ddiv+0x6> + +10001828 <__wrap___aeabi_ddiv>: +10001828: fe10 f430 dcp_pcmp APSR_nzcv +1000182c: d4f8 bmi.n 10001820 <__wrap___aeabi_dmul+0x44> +1000182e: ec41 0410 dcp_wxup r0, r1 +10001832: ec43 2411 dcp_wyup r2, r3 +10001836: ec51 0421 dcp_rymr r0, r1 +1000183a: fba0 1201 umull r1, r2, r0, r1 +1000183e: ea6f 0282 mvn.w r2, r2, lsl #2 +10001842: fb52 0010 smmlar r0, r2, r0, r0 +10001846: fb52 f212 smmulr r2, r2, r2 +1000184a: fb52 0010 smmlar r0, r2, r0, r0 +1000184e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10001852: ec53 2404 dcp_rxms r2, r3, #0x0 +10001856: fb5c f113 smmulr r1, ip, r3 +1000185a: ec53 2415 dcp_ryms r2, r3, #0x1 +1000185e: fba1 2002 umull r2, r0, r1, r2 +10001862: fb01 0003 mla r0, r1, r3, r0 +10001866: ec53 2444 dcp_rxms r2, r3, #0x4 +1000186a: eba2 0000 sub.w r0, r2, r0 +1000186e: fb50 f21c smmulr r2, r0, ip +10001872: ea4f 1311 mov.w r3, r1, lsr #4 +10001876: eb12 7001 adds.w r0, r2, r1, lsl #28 +1000187a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1000187e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001882: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001886: f020 0007 bic.w r0, r0, #7 +1000188a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000188e: fba0 3c02 umull r3, ip, r0, r2 +10001892: ec53 2475 dcp_ryms r2, r3, #0x7 +10001896: fb00 cc03 mla ip, r0, r3, ip +1000189a: fb01 cc02 mla ip, r1, r2, ip +1000189e: ec53 2404 dcp_rxms r2, r3, #0x0 +100018a2: ebac 4c82 sub.w ip, ip, r2, lsl #18 +100018a6: ea40 705c orr.w r0, r0, ip, lsr #29 +100018aa: f1a0 0001 sub.w r0, r0, #1 +100018ae: ec41 0440 dcp_wxdd r0, r1 +100018b2: ee80 0420 dcp_nrdd +100018b6: ec51 0470 dcp_rddd r0, r1 +100018ba: 4770 bx lr +100018bc: b500 push {lr} +100018be: f7ff ff43 bl 10001748 +100018c2: e002 b.n 100018ca <__wrap___aeabi_i2d+0x6> + +100018c4 <__wrap___aeabi_i2d>: +100018c4: fe10 f430 dcp_pcmp APSR_nzcv +100018c8: d4f8 bmi.n 100018bc <__wrap___aeabi_ddiv+0x94> +100018ca: ec40 0470 dcp_wxic r0, r0 +100018ce: ee00 0401 dcp_add0 +100018d2: ee10 0421 dcp_sub1 +100018d6: ee80 0420 dcp_nrdd +100018da: ec51 0430 dcp_rdds r0, r1 +100018de: 4770 bx lr +100018e0: b500 push {lr} +100018e2: f7ff ff31 bl 10001748 +100018e6: e002 b.n 100018ee <__wrap___aeabi_ui2d+0x6> + +100018e8 <__wrap___aeabi_ui2d>: +100018e8: fe10 f430 dcp_pcmp APSR_nzcv +100018ec: d4f8 bmi.n 100018e0 <__wrap___aeabi_i2d+0x1c> +100018ee: ec40 0460 dcp_wxuc r0, r0 +100018f2: ee00 0401 dcp_add0 +100018f6: ee10 0421 dcp_sub1 +100018fa: ee80 0420 dcp_nrdd +100018fe: ec51 0430 dcp_rdds r0, r1 +10001902: 4770 bx lr +10001904: b500 push {lr} +10001906: f7ff ff1f bl 10001748 +1000190a: e002 b.n 10001912 + +1000190c <__wrap___aeabi_d2iz>: +1000190c: fe10 f430 dcp_pcmp APSR_nzcv +10001910: d4f8 bmi.n 10001904 <__wrap___aeabi_ui2d+0x1c> + +10001912 : +10001912: ec41 0480 dcp_wxdc r0, r1 +10001916: ee00 0401 dcp_add0 +1000191a: ee10 0401 dcp_add1 +1000191e: ee80 0440 dcp_ntdc +10001922: ee10 0413 dcp_rdic r0 +10001926: 4770 bx lr +10001928: b500 push {lr} +1000192a: f7ff ff0d bl 10001748 +1000192e: e002 b.n 10001936 + +10001930 <__wrap___aeabi_d2uiz>: +10001930: fe10 f430 dcp_pcmp APSR_nzcv +10001934: d4f8 bmi.n 10001928 + +10001936 : +10001936: ec41 0480 dcp_wxdc r0, r1 +1000193a: ee00 0401 dcp_add0 +1000193e: ee10 0401 dcp_add1 +10001942: ee80 0440 dcp_ntdc +10001946: ee10 0433 dcp_rduc r0 +1000194a: 4770 bx lr +1000194c: b500 push {lr} +1000194e: f7ff fefb bl 10001748 +10001952: e002 b.n 1000195a <__wrap___aeabi_dcmpun+0x6> + +10001954 <__wrap___aeabi_dcmpun>: +10001954: fe10 f430 dcp_pcmp APSR_nzcv +10001958: d4f8 bmi.n 1000194c +1000195a: ec41 0410 dcp_wxup r0, r1 +1000195e: ec43 2411 dcp_wyup r2, r3 +10001962: ee00 0401 dcp_add0 +10001966: ee10 0430 dcp_rcmp r0 +1000196a: f3c0 7000 ubfx r0, r0, #28, #1 +1000196e: 4770 bx lr +10001970: b500 push {lr} +10001972: f7ff fee9 bl 10001748 +10001976: e002 b.n 1000197e <__wrap___aeabi_dcmplt+0x6> + +10001978 <__wrap___aeabi_dcmplt>: +10001978: fe10 f430 dcp_pcmp APSR_nzcv +1000197c: d4f8 bmi.n 10001970 <__wrap___aeabi_dcmpun+0x1c> +1000197e: ec43 2410 dcp_wxup r2, r3 +10001982: ec41 0411 dcp_wyup r0, r1 +10001986: ee00 0401 dcp_add0 +1000198a: ee10 f430 dcp_rcmp APSR_nzcv +1000198e: bf8c ite hi +10001990: 2001 movhi r0, #1 +10001992: 2000 movls r0, #0 +10001994: 4770 bx lr +10001996: bf00 nop +10001998: b500 push {lr} +1000199a: f7ff fed5 bl 10001748 +1000199e: e002 b.n 100019a6 <__wrap___aeabi_dcmple+0x6> + +100019a0 <__wrap___aeabi_dcmple>: +100019a0: fe10 f430 dcp_pcmp APSR_nzcv +100019a4: d4f8 bmi.n 10001998 <__wrap___aeabi_dcmplt+0x20> +100019a6: ec43 2410 dcp_wxup r2, r3 +100019aa: ec41 0411 dcp_wyup r0, r1 +100019ae: ee00 0401 dcp_add0 +100019b2: ee10 f430 dcp_rcmp APSR_nzcv +100019b6: bf2c ite cs +100019b8: 2001 movcs r0, #1 +100019ba: 2000 movcc r0, #0 +100019bc: 4770 bx lr +100019be: bf00 nop +100019c0: b500 push {lr} +100019c2: f7ff fec1 bl 10001748 +100019c6: e002 b.n 100019ce <__wrap___aeabi_dcmpge+0x6> + +100019c8 <__wrap___aeabi_dcmpge>: +100019c8: fe10 f430 dcp_pcmp APSR_nzcv +100019cc: d4f8 bmi.n 100019c0 <__wrap___aeabi_dcmple+0x20> +100019ce: ec41 0410 dcp_wxup r0, r1 +100019d2: ec43 2411 dcp_wyup r2, r3 +100019d6: ee00 0401 dcp_add0 +100019da: ee10 f430 dcp_rcmp APSR_nzcv +100019de: bf2c ite cs +100019e0: 2001 movcs r0, #1 +100019e2: 2000 movcc r0, #0 +100019e4: 4770 bx lr +100019e6: bf00 nop +100019e8: b500 push {lr} +100019ea: f7ff fead bl 10001748 +100019ee: e002 b.n 100019f6 <__wrap___aeabi_dcmpgt+0x6> + +100019f0 <__wrap___aeabi_dcmpgt>: +100019f0: fe10 f430 dcp_pcmp APSR_nzcv +100019f4: d4f8 bmi.n 100019e8 <__wrap___aeabi_dcmpge+0x20> +100019f6: ec41 0410 dcp_wxup r0, r1 +100019fa: ec43 2411 dcp_wyup r2, r3 +100019fe: ee00 0401 dcp_add0 +10001a02: ee10 f430 dcp_rcmp APSR_nzcv +10001a06: bf8c ite hi +10001a08: 2001 movhi r0, #1 +10001a0a: 2000 movls r0, #0 +10001a0c: 4770 bx lr +10001a0e: bf00 nop + +10001a10 <_out_null>: +10001a10: 4770 bx lr +10001a12: bf00 nop + +10001a14 <_out_rev>: +10001a14: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a18: b083 sub sp, #12 +10001a1a: 4699 mov r9, r3 +10001a1c: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001a20: 9b0f ldr r3, [sp, #60] @ 0x3c +10001a22: 4688 mov r8, r1 +10001a24: 4611 mov r1, r2 +10001a26: 079a lsls r2, r3, #30 +10001a28: 4607 mov r7, r0 +10001a2a: d116 bne.n 10001a5a <_out_rev+0x46> +10001a2c: 45da cmp sl, fp +10001a2e: d23a bcs.n 10001aa6 <_out_rev+0x92> +10001a30: 460c mov r4, r1 +10001a32: 460d mov r5, r1 +10001a34: ebab 060a sub.w r6, fp, sl +10001a38: 440e add r6, r1 +10001a3a: 4622 mov r2, r4 +10001a3c: 464b mov r3, r9 +10001a3e: 4641 mov r1, r8 +10001a40: 2020 movs r0, #32 +10001a42: 3401 adds r4, #1 +10001a44: 47b8 blx r7 +10001a46: 42b4 cmp r4, r6 +10001a48: d1f7 bne.n 10001a3a <_out_rev+0x26> +10001a4a: 4629 mov r1, r5 +10001a4c: f1ba 0f00 cmp.w sl, #0 +10001a50: d108 bne.n 10001a64 <_out_rev+0x50> +10001a52: 4620 mov r0, r4 +10001a54: b003 add sp, #12 +10001a56: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001a5a: 460c mov r4, r1 +10001a5c: f1ba 0f00 cmp.w sl, #0 +10001a60: d010 beq.n 10001a84 <_out_rev+0x70> +10001a62: 460e mov r6, r1 +10001a64: 4655 mov r5, sl +10001a66: 9b0c ldr r3, [sp, #48] @ 0x30 +10001a68: 442e add r6, r5 +10001a6a: 449a add sl, r3 +10001a6c: 9101 str r1, [sp, #4] +10001a6e: 1b72 subs r2, r6, r5 +10001a70: 464b mov r3, r9 +10001a72: 3d01 subs r5, #1 +10001a74: 4641 mov r1, r8 +10001a76: f81a 0d01 ldrb.w r0, [sl, #-1]! +10001a7a: 4634 mov r4, r6 +10001a7c: 47b8 blx r7 +10001a7e: 2d00 cmp r5, #0 +10001a80: d1f5 bne.n 10001a6e <_out_rev+0x5a> +10001a82: 9901 ldr r1, [sp, #4] +10001a84: 9b0f ldr r3, [sp, #60] @ 0x3c +10001a86: 079b lsls r3, r3, #30 +10001a88: d5e3 bpl.n 10001a52 <_out_rev+0x3e> +10001a8a: 1a65 subs r5, r4, r1 +10001a8c: 45ab cmp fp, r5 +10001a8e: d9e0 bls.n 10001a52 <_out_rev+0x3e> +10001a90: 4622 mov r2, r4 +10001a92: 464b mov r3, r9 +10001a94: 4641 mov r1, r8 +10001a96: 2020 movs r0, #32 +10001a98: 3501 adds r5, #1 +10001a9a: 47b8 blx r7 +10001a9c: 455d cmp r5, fp +10001a9e: f104 0401 add.w r4, r4, #1 +10001aa2: d3f5 bcc.n 10001a90 <_out_rev+0x7c> +10001aa4: e7d5 b.n 10001a52 <_out_rev+0x3e> +10001aa6: 460c mov r4, r1 +10001aa8: f1ba 0f00 cmp.w sl, #0 +10001aac: d1d9 bne.n 10001a62 <_out_rev+0x4e> +10001aae: e7d0 b.n 10001a52 <_out_rev+0x3e> + +10001ab0 <_ntoa_format>: +10001ab0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ab4: 9f0f ldr r7, [sp, #60] @ 0x3c +10001ab6: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001aba: f017 0f02 tst.w r7, #2 +10001abe: 9c0a ldr r4, [sp, #40] @ 0x28 +10001ac0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001ac4: 9d0e ldr r5, [sp, #56] @ 0x38 +10001ac6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001aca: d144 bne.n 10001b56 <_ntoa_format+0xa6> +10001acc: bbf5 cbnz r5, 10001b4c <_ntoa_format+0x9c> +10001ace: 42b4 cmp r4, r6 +10001ad0: d241 bcs.n 10001b56 <_ntoa_format+0xa6> +10001ad2: f007 0b01 and.w fp, r7, #1 +10001ad6: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001ada: f04f 0e30 mov.w lr, #48 @ 0x30 +10001ade: 44c4 add ip, r8 +10001ae0: e004 b.n 10001aec <_ntoa_format+0x3c> +10001ae2: 3401 adds r4, #1 +10001ae4: 42a6 cmp r6, r4 +10001ae6: f80c ef01 strb.w lr, [ip, #1]! +10001aea: d901 bls.n 10001af0 <_ntoa_format+0x40> +10001aec: 2c20 cmp r4, #32 +10001aee: d1f8 bne.n 10001ae2 <_ntoa_format+0x32> +10001af0: f1bb 0f00 cmp.w fp, #0 +10001af4: f000 8088 beq.w 10001c08 <_ntoa_format+0x158> +10001af8: 42a5 cmp r5, r4 +10001afa: d92c bls.n 10001b56 <_ntoa_format+0xa6> +10001afc: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001b00: f04f 0e30 mov.w lr, #48 @ 0x30 +10001b04: 44c4 add ip, r8 +10001b06: e004 b.n 10001b12 <_ntoa_format+0x62> +10001b08: 3401 adds r4, #1 +10001b0a: 42ac cmp r4, r5 +10001b0c: f80c ef01 strb.w lr, [ip, #1]! +10001b10: d021 beq.n 10001b56 <_ntoa_format+0xa6> +10001b12: 2c20 cmp r4, #32 +10001b14: d1f8 bne.n 10001b08 <_ntoa_format+0x58> +10001b16: f017 0f10 tst.w r7, #16 +10001b1a: d00e beq.n 10001b3a <_ntoa_format+0x8a> +10001b1c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001b20: d154 bne.n 10001bcc <_ntoa_format+0x11c> +10001b22: 42a6 cmp r6, r4 +10001b24: d063 beq.n 10001bee <_ntoa_format+0x13e> +10001b26: 42a5 cmp r5, r4 +10001b28: d061 beq.n 10001bee <_ntoa_format+0x13e> +10001b2a: f1b9 0f10 cmp.w r9, #16 +10001b2e: d050 beq.n 10001bd2 <_ntoa_format+0x122> +10001b30: f1b9 0f02 cmp.w r9, #2 +10001b34: d056 beq.n 10001be4 <_ntoa_format+0x134> +10001b36: 2c20 cmp r4, #32 +10001b38: d129 bne.n 10001b8e <_ntoa_format+0xde> +10001b3a: 2420 movs r4, #32 +10001b3c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001b40: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001b44: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b48: f7ff bf64 b.w 10001a14 <_out_rev> +10001b4c: f017 0b01 ands.w fp, r7, #1 +10001b50: d134 bne.n 10001bbc <_ntoa_format+0x10c> +10001b52: 42b4 cmp r4, r6 +10001b54: d3bf bcc.n 10001ad6 <_ntoa_format+0x26> +10001b56: f017 0f10 tst.w r7, #16 +10001b5a: d01e beq.n 10001b9a <_ntoa_format+0xea> +10001b5c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001b60: d1e3 bne.n 10001b2a <_ntoa_format+0x7a> +10001b62: 2c00 cmp r4, #0 +10001b64: d1dd bne.n 10001b22 <_ntoa_format+0x72> +10001b66: f1b9 0f10 cmp.w r9, #16 +10001b6a: d063 beq.n 10001c34 <_ntoa_format+0x184> +10001b6c: f1b9 0f02 cmp.w r9, #2 +10001b70: d077 beq.n 10001c62 <_ntoa_format+0x1b2> +10001b72: 2430 movs r4, #48 @ 0x30 +10001b74: f888 4000 strb.w r4, [r8] +10001b78: 2401 movs r4, #1 +10001b7a: f1ba 0f00 cmp.w sl, #0 +10001b7e: d111 bne.n 10001ba4 <_ntoa_format+0xf4> +10001b80: 077e lsls r6, r7, #29 +10001b82: d548 bpl.n 10001c16 <_ntoa_format+0x166> +10001b84: 262b movs r6, #43 @ 0x2b +10001b86: f808 6004 strb.w r6, [r8, r4] +10001b8a: 3401 adds r4, #1 +10001b8c: e7d6 b.n 10001b3c <_ntoa_format+0x8c> +10001b8e: 4626 mov r6, r4 +10001b90: 3401 adds r4, #1 +10001b92: f04f 0c30 mov.w ip, #48 @ 0x30 +10001b96: f808 c006 strb.w ip, [r8, r6] +10001b9a: 2c20 cmp r4, #32 +10001b9c: d0cd beq.n 10001b3a <_ntoa_format+0x8a> +10001b9e: f1ba 0f00 cmp.w sl, #0 +10001ba2: d0ed beq.n 10001b80 <_ntoa_format+0xd0> +10001ba4: 262d movs r6, #45 @ 0x2d +10001ba6: f808 6004 strb.w r6, [r8, r4] +10001baa: 3401 adds r4, #1 +10001bac: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001bb0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001bb4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001bb8: f7ff bf2c b.w 10001a14 <_out_rev> +10001bbc: f1ba 0f00 cmp.w sl, #0 +10001bc0: d030 beq.n 10001c24 <_ntoa_format+0x174> +10001bc2: 42b4 cmp r4, r6 +10001bc4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001bc8: d385 bcc.n 10001ad6 <_ntoa_format+0x26> +10001bca: e795 b.n 10001af8 <_ntoa_format+0x48> +10001bcc: f1b9 0f10 cmp.w r9, #16 +10001bd0: d1b3 bne.n 10001b3a <_ntoa_format+0x8a> +10001bd2: 06be lsls r6, r7, #26 +10001bd4: d53b bpl.n 10001c4e <_ntoa_format+0x19e> +10001bd6: 2c20 cmp r4, #32 +10001bd8: d0af beq.n 10001b3a <_ntoa_format+0x8a> +10001bda: 2658 movs r6, #88 @ 0x58 +10001bdc: f808 6004 strb.w r6, [r8, r4] +10001be0: 3401 adds r4, #1 +10001be2: e7a8 b.n 10001b36 <_ntoa_format+0x86> +10001be4: 2c20 cmp r4, #32 +10001be6: d0a8 beq.n 10001b3a <_ntoa_format+0x8a> +10001be8: 4626 mov r6, r4 +10001bea: 3401 adds r4, #1 +10001bec: e007 b.n 10001bfe <_ntoa_format+0x14e> +10001bee: 1e66 subs r6, r4, #1 +10001bf0: d0b9 beq.n 10001b66 <_ntoa_format+0xb6> +10001bf2: f1b9 0f10 cmp.w r9, #16 +10001bf6: d036 beq.n 10001c66 <_ntoa_format+0x1b6> +10001bf8: f1b9 0f02 cmp.w r9, #2 +10001bfc: d1c9 bne.n 10001b92 <_ntoa_format+0xe2> +10001bfe: f04f 0c62 mov.w ip, #98 @ 0x62 +10001c02: f808 c006 strb.w ip, [r8, r6] +10001c06: e796 b.n 10001b36 <_ntoa_format+0x86> +10001c08: f017 0f10 tst.w r7, #16 +10001c0c: d0c5 beq.n 10001b9a <_ntoa_format+0xea> +10001c0e: f417 6f80 tst.w r7, #1024 @ 0x400 +10001c12: d086 beq.n 10001b22 <_ntoa_format+0x72> +10001c14: e789 b.n 10001b2a <_ntoa_format+0x7a> +10001c16: 073e lsls r6, r7, #28 +10001c18: d590 bpl.n 10001b3c <_ntoa_format+0x8c> +10001c1a: 2620 movs r6, #32 +10001c1c: f808 6004 strb.w r6, [r8, r4] +10001c20: 3401 adds r4, #1 +10001c22: e78b b.n 10001b3c <_ntoa_format+0x8c> +10001c24: f017 0f0c tst.w r7, #12 +10001c28: d000 beq.n 10001c2c <_ntoa_format+0x17c> +10001c2a: 3d01 subs r5, #1 +10001c2c: 42b4 cmp r4, r6 +10001c2e: f4ff af52 bcc.w 10001ad6 <_ntoa_format+0x26> +10001c32: e761 b.n 10001af8 <_ntoa_format+0x48> +10001c34: 06bc lsls r4, r7, #26 +10001c36: d412 bmi.n 10001c5e <_ntoa_format+0x1ae> +10001c38: 2478 movs r4, #120 @ 0x78 +10001c3a: f888 4000 strb.w r4, [r8] +10001c3e: 2430 movs r4, #48 @ 0x30 +10001c40: f888 4001 strb.w r4, [r8, #1] +10001c44: 2402 movs r4, #2 +10001c46: f1ba 0f00 cmp.w sl, #0 +10001c4a: d099 beq.n 10001b80 <_ntoa_format+0xd0> +10001c4c: e7aa b.n 10001ba4 <_ntoa_format+0xf4> +10001c4e: 2c20 cmp r4, #32 +10001c50: f43f af73 beq.w 10001b3a <_ntoa_format+0x8a> +10001c54: 2678 movs r6, #120 @ 0x78 +10001c56: f808 6004 strb.w r6, [r8, r4] +10001c5a: 3401 adds r4, #1 +10001c5c: e76b b.n 10001b36 <_ntoa_format+0x86> +10001c5e: 2458 movs r4, #88 @ 0x58 +10001c60: e7eb b.n 10001c3a <_ntoa_format+0x18a> +10001c62: 2462 movs r4, #98 @ 0x62 +10001c64: e7e9 b.n 10001c3a <_ntoa_format+0x18a> +10001c66: f017 0f20 tst.w r7, #32 +10001c6a: f1a4 0c02 sub.w ip, r4, #2 +10001c6e: d004 beq.n 10001c7a <_ntoa_format+0x1ca> +10001c70: f04f 0e58 mov.w lr, #88 @ 0x58 +10001c74: f808 e00c strb.w lr, [r8, ip] +10001c78: e78b b.n 10001b92 <_ntoa_format+0xe2> +10001c7a: f04f 0e78 mov.w lr, #120 @ 0x78 +10001c7e: f808 e00c strb.w lr, [r8, ip] +10001c82: e786 b.n 10001b92 <_ntoa_format+0xe2> + +10001c84 <_out_char>: +10001c84: b900 cbnz r0, 10001c88 <_out_char+0x4> +10001c86: 4770 bx lr +10001c88: f001 bb72 b.w 10003370 <__wrap_putchar> + +10001c8c <_out_fct>: +10001c8c: b110 cbz r0, 10001c94 <_out_fct+0x8> +10001c8e: e9d1 3100 ldrd r3, r1, [r1] +10001c92: 4718 bx r3 +10001c94: 4770 bx lr +10001c96: bf00 nop + +10001c98 <_ftoa>: +10001c98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c9c: b097 sub sp, #92 @ 0x5c +10001c9e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001ca2: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001ca6: 4607 mov r7, r0 +10001ca8: 4688 mov r8, r1 +10001caa: ec51 0b17 vmov r0, r1, d7 +10001cae: 9c24 ldr r4, [sp, #144] @ 0x90 +10001cb0: 4699 mov r9, r3 +10001cb2: 920c str r2, [sp, #48] @ 0x30 +10001cb4: 460b mov r3, r1 +10001cb6: 4602 mov r2, r0 +10001cb8: ed8d 7b04 vstr d7, [sp, #16] +10001cbc: 9407 str r4, [sp, #28] +10001cbe: f7ff fe49 bl 10001954 <__wrap___aeabi_dcmpun> +10001cc2: 2800 cmp r0, #0 +10001cc4: f040 81f4 bne.w 100020b0 <_ftoa+0x418> +10001cc8: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ccc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001cd0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001cd4: f7ff fe50 bl 10001978 <__wrap___aeabi_dcmplt> +10001cd8: 2800 cmp r0, #0 +10001cda: f040 811b bne.w 10001f14 <_ftoa+0x27c> +10001cde: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ce2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001ce6: 4bac ldr r3, [pc, #688] @ (10001f98 <_ftoa+0x300>) +10001ce8: f7ff fe82 bl 100019f0 <__wrap___aeabi_dcmpgt> +10001cec: 2800 cmp r0, #0 +10001cee: f040 80ee bne.w 10001ece <_ftoa+0x236> +10001cf2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001cf6: a3a4 add r3, pc, #656 @ (adr r3, 10001f88 <_ftoa+0x2f0>) +10001cf8: e9d3 2300 ldrd r2, r3, [r3] +10001cfc: f7ff fe78 bl 100019f0 <__wrap___aeabi_dcmpgt> +10001d00: 2800 cmp r0, #0 +10001d02: f040 80d3 bne.w 10001eac <_ftoa+0x214> +10001d06: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d0a: a3a1 add r3, pc, #644 @ (adr r3, 10001f90 <_ftoa+0x2f8>) +10001d0c: e9d3 2300 ldrd r2, r3, [r3] +10001d10: f7ff fe32 bl 10001978 <__wrap___aeabi_dcmplt> +10001d14: 2800 cmp r0, #0 +10001d16: f040 80c9 bne.w 10001eac <_ftoa+0x214> +10001d1a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d1e: 2200 movs r2, #0 +10001d20: 2300 movs r3, #0 +10001d22: f7ff fe29 bl 10001978 <__wrap___aeabi_dcmplt> +10001d26: 2800 cmp r0, #0 +10001d28: f040 80e8 bne.w 10001efc <_ftoa+0x264> +10001d2c: 4623 mov r3, r4 +10001d2e: 900d str r0, [sp, #52] @ 0x34 +10001d30: f413 6f80 tst.w r3, #1024 @ 0x400 +10001d34: bf08 it eq +10001d36: 2506 moveq r5, #6 +10001d38: 2130 movs r1, #48 @ 0x30 +10001d3a: 462b mov r3, r5 +10001d3c: aa0e add r2, sp, #56 @ 0x38 +10001d3e: f1a5 0620 sub.w r6, r5, #32 +10001d42: e005 b.n 10001d50 <_ftoa+0xb8> +10001d44: 3b01 subs r3, #1 +10001d46: 42b3 cmp r3, r6 +10001d48: f802 1b01 strb.w r1, [r2], #1 +10001d4c: f000 8193 beq.w 10002076 <_ftoa+0x3de> +10001d50: 2b09 cmp r3, #9 +10001d52: d8f7 bhi.n 10001d44 <_ftoa+0xac> +10001d54: 461e mov r6, r3 +10001d56: 1aed subs r5, r5, r3 +10001d58: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d5c: f7ff fdd6 bl 1000190c <__wrap___aeabi_d2iz> +10001d60: 4b8e ldr r3, [pc, #568] @ (10001f9c <_ftoa+0x304>) +10001d62: 4604 mov r4, r0 +10001d64: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001d68: ed93 7b00 vldr d7, [r3] +10001d6c: ed8d 7b08 vstr d7, [sp, #32] +10001d70: f7ff fda8 bl 100018c4 <__wrap___aeabi_i2d> +10001d74: 4602 mov r2, r0 +10001d76: 460b mov r3, r1 +10001d78: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d7c: f7ff fd1a bl 100017b4 <__wrap___aeabi_dsub> +10001d80: e9dd 2308 ldrd r2, r3, [sp, #32] +10001d84: f7ff fd2a bl 100017dc <__wrap___aeabi_dmul> +10001d88: 4602 mov r2, r0 +10001d8a: 460b mov r3, r1 +10001d8c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001d90: f7ff fdce bl 10001930 <__wrap___aeabi_d2uiz> +10001d94: 4682 mov sl, r0 +10001d96: f7ff fda7 bl 100018e8 <__wrap___aeabi_ui2d> +10001d9a: 4602 mov r2, r0 +10001d9c: 460b mov r3, r1 +10001d9e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001da2: f7ff fd07 bl 100017b4 <__wrap___aeabi_dsub> +10001da6: 4602 mov r2, r0 +10001da8: 460b mov r3, r1 +10001daa: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001dae: 2200 movs r2, #0 +10001db0: 4b7b ldr r3, [pc, #492] @ (10001fa0 <_ftoa+0x308>) +10001db2: f7ff fe1d bl 100019f0 <__wrap___aeabi_dcmpgt> +10001db6: 2800 cmp r0, #0 +10001db8: f000 80fe beq.w 10001fb8 <_ftoa+0x320> +10001dbc: f10a 0a01 add.w sl, sl, #1 +10001dc0: 4650 mov r0, sl +10001dc2: f7ff fd91 bl 100018e8 <__wrap___aeabi_ui2d> +10001dc6: 4602 mov r2, r0 +10001dc8: 460b mov r3, r1 +10001dca: e9dd 0108 ldrd r0, r1, [sp, #32] +10001dce: f7ff fde7 bl 100019a0 <__wrap___aeabi_dcmple> +10001dd2: b110 cbz r0, 10001dda <_ftoa+0x142> +10001dd4: f04f 0a00 mov.w sl, #0 +10001dd8: 3401 adds r4, #1 +10001dda: 2e00 cmp r6, #0 +10001ddc: f000 80fd beq.w 10001fda <_ftoa+0x342> +10001de0: 1e68 subs r0, r5, #1 +10001de2: ab0e add r3, sp, #56 @ 0x38 +10001de4: f8df c1cc ldr.w ip, [pc, #460] @ 10001fb4 <_ftoa+0x31c> +10001de8: 4418 add r0, r3 +10001dea: e00f b.n 10001e0c <_ftoa+0x174> +10001dec: fbac 210a umull r2, r1, ip, sl +10001df0: 08c9 lsrs r1, r1, #3 +10001df2: eb01 0281 add.w r2, r1, r1, lsl #2 +10001df6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001dfa: 3230 adds r2, #48 @ 0x30 +10001dfc: f1ba 0f09 cmp.w sl, #9 +10001e00: f800 2f01 strb.w r2, [r0, #1]! +10001e04: f240 811c bls.w 10002040 <_ftoa+0x3a8> +10001e08: 468a mov sl, r1 +10001e0a: 461d mov r5, r3 +10001e0c: 2d20 cmp r5, #32 +10001e0e: f105 0301 add.w r3, r5, #1 +10001e12: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001e16: d1e9 bne.n 10001dec <_ftoa+0x154> +10001e18: 2520 movs r5, #32 +10001e1a: 1e69 subs r1, r5, #1 +10001e1c: ab0e add r3, sp, #56 @ 0x38 +10001e1e: 4861 ldr r0, [pc, #388] @ (10001fa4 <_ftoa+0x30c>) +10001e20: 4419 add r1, r3 +10001e22: e010 b.n 10001e46 <_ftoa+0x1ae> +10001e24: fb80 6204 smull r6, r2, r0, r4 +10001e28: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001e2c: eb03 0283 add.w r2, r3, r3, lsl #2 +10001e30: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001e34: f104 0230 add.w r2, r4, #48 @ 0x30 +10001e38: 3501 adds r5, #1 +10001e3a: 461c mov r4, r3 +10001e3c: f801 2f01 strb.w r2, [r1, #1]! +10001e40: 2b00 cmp r3, #0 +10001e42: f000 80eb beq.w 1000201c <_ftoa+0x384> +10001e46: 2d20 cmp r5, #32 +10001e48: ea4f 73e4 mov.w r3, r4, asr #31 +10001e4c: d1ea bne.n 10001e24 <_ftoa+0x18c> +10001e4e: 9b07 ldr r3, [sp, #28] +10001e50: f003 0303 and.w r3, r3, #3 +10001e54: 2b01 cmp r3, #1 +10001e56: d118 bne.n 10001e8a <_ftoa+0x1f2> +10001e58: f1bb 0f00 cmp.w fp, #0 +10001e5c: d015 beq.n 10001e8a <_ftoa+0x1f2> +10001e5e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001e60: 2b00 cmp r3, #0 +10001e62: f000 810a beq.w 1000207a <_ftoa+0x3e2> +10001e66: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001e6a: f1bb 0f20 cmp.w fp, #32 +10001e6e: d90c bls.n 10001e8a <_ftoa+0x1f2> +10001e70: 1e6b subs r3, r5, #1 +10001e72: a90e add r1, sp, #56 @ 0x38 +10001e74: 2230 movs r2, #48 @ 0x30 +10001e76: 440b add r3, r1 +10001e78: e005 b.n 10001e86 <_ftoa+0x1ee> +10001e7a: 3501 adds r5, #1 +10001e7c: 455d cmp r5, fp +10001e7e: f803 2f01 strb.w r2, [r3, #1]! +10001e82: f080 80d1 bcs.w 10002028 <_ftoa+0x390> +10001e86: 2d20 cmp r5, #32 +10001e88: d1f7 bne.n 10001e7a <_ftoa+0x1e2> +10001e8a: 9b07 ldr r3, [sp, #28] +10001e8c: ac0e add r4, sp, #56 @ 0x38 +10001e8e: e9cd b302 strd fp, r3, [sp, #8] +10001e92: 4641 mov r1, r8 +10001e94: 464b mov r3, r9 +10001e96: 4638 mov r0, r7 +10001e98: 9a0c ldr r2, [sp, #48] @ 0x30 +10001e9a: 9501 str r5, [sp, #4] +10001e9c: 9400 str r4, [sp, #0] +10001e9e: f7ff fdb9 bl 10001a14 <_out_rev> +10001ea2: 4682 mov sl, r0 +10001ea4: 4650 mov r0, sl +10001ea6: b017 add sp, #92 @ 0x5c +10001ea8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001eac: 9b07 ldr r3, [sp, #28] +10001eae: ed9d 7b04 vldr d7, [sp, #16] +10001eb2: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001eb6: 4641 mov r1, r8 +10001eb8: 464b mov r3, r9 +10001eba: 4638 mov r0, r7 +10001ebc: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ebe: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001ec2: 9522 str r5, [sp, #136] @ 0x88 +10001ec4: b017 add sp, #92 @ 0x5c +10001ec6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001eca: f000 b945 b.w 10002158 <_etoa> +10001ece: 0761 lsls r1, r4, #29 +10001ed0: 4623 mov r3, r4 +10001ed2: bf4c ite mi +10001ed4: 2304 movmi r3, #4 +10001ed6: 2303 movpl r3, #3 +10001ed8: 4641 mov r1, r8 +10001eda: 9321 str r3, [sp, #132] @ 0x84 +10001edc: 4638 mov r0, r7 +10001ede: 464b mov r3, r9 +10001ee0: 9a07 ldr r2, [sp, #28] +10001ee2: bf48 it mi +10001ee4: 4c30 ldrmi r4, [pc, #192] @ (10001fa8 <_ftoa+0x310>) +10001ee6: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001eea: bf58 it pl +10001eec: 4c2f ldrpl r4, [pc, #188] @ (10001fac <_ftoa+0x314>) +10001eee: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ef0: 9420 str r4, [sp, #128] @ 0x80 +10001ef2: b017 add sp, #92 @ 0x5c +10001ef4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ef8: f7ff bd8c b.w 10001a14 <_out_rev> +10001efc: e9dd 2304 ldrd r2, r3, [sp, #16] +10001f00: 2000 movs r0, #0 +10001f02: 2100 movs r1, #0 +10001f04: f7ff fc56 bl 100017b4 <__wrap___aeabi_dsub> +10001f08: 2301 movs r3, #1 +10001f0a: e9cd 0104 strd r0, r1, [sp, #16] +10001f0e: 930d str r3, [sp, #52] @ 0x34 +10001f10: 4623 mov r3, r4 +10001f12: e70d b.n 10001d30 <_ftoa+0x98> +10001f14: 4623 mov r3, r4 +10001f16: 079c lsls r4, r3, #30 +10001f18: f040 80aa bne.w 10002070 <_ftoa+0x3d8> +10001f1c: f1bb 0f04 cmp.w fp, #4 +10001f20: f240 80a6 bls.w 10002070 <_ftoa+0x3d8> +10001f24: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f26: 461d mov r5, r3 +10001f28: 1f1c subs r4, r3, #4 +10001f2a: eb04 0a0b add.w sl, r4, fp +10001f2e: 462a mov r2, r5 +10001f30: 464b mov r3, r9 +10001f32: 4641 mov r1, r8 +10001f34: 2020 movs r0, #32 +10001f36: 3501 adds r5, #1 +10001f38: 47b8 blx r7 +10001f3a: 45aa cmp sl, r5 +10001f3c: d1f7 bne.n 10001f2e <_ftoa+0x296> +10001f3e: 4655 mov r5, sl +10001f40: 4c1b ldr r4, [pc, #108] @ (10001fb0 <_ftoa+0x318>) +10001f42: 1f26 subs r6, r4, #4 +10001f44: f814 0d01 ldrb.w r0, [r4, #-1]! +10001f48: 462a mov r2, r5 +10001f4a: 464b mov r3, r9 +10001f4c: 4641 mov r1, r8 +10001f4e: 47b8 blx r7 +10001f50: 42b4 cmp r4, r6 +10001f52: f105 0501 add.w r5, r5, #1 +10001f56: d1f5 bne.n 10001f44 <_ftoa+0x2ac> +10001f58: 9b07 ldr r3, [sp, #28] +10001f5a: f10a 0a04 add.w sl, sl, #4 +10001f5e: 0798 lsls r0, r3, #30 +10001f60: d5a0 bpl.n 10001ea4 <_ftoa+0x20c> +10001f62: 9c0c ldr r4, [sp, #48] @ 0x30 +10001f64: ebaa 0304 sub.w r3, sl, r4 +10001f68: 459b cmp fp, r3 +10001f6a: d99b bls.n 10001ea4 <_ftoa+0x20c> +10001f6c: 4652 mov r2, sl +10001f6e: 464b mov r3, r9 +10001f70: 4641 mov r1, r8 +10001f72: 2020 movs r0, #32 +10001f74: f10a 0a01 add.w sl, sl, #1 +10001f78: 47b8 blx r7 +10001f7a: ebaa 0304 sub.w r3, sl, r4 +10001f7e: 455b cmp r3, fp +10001f80: d3f4 bcc.n 10001f6c <_ftoa+0x2d4> +10001f82: e78f b.n 10001ea4 <_ftoa+0x20c> +10001f84: f3af 8000 nop.w +10001f88: 00000000 .word 0x00000000 +10001f8c: 41cdcd65 .word 0x41cdcd65 +10001f90: 00000000 .word 0x00000000 +10001f94: c1cdcd65 .word 0xc1cdcd65 +10001f98: 7fefffff .word 0x7fefffff +10001f9c: 10003a20 .word 0x10003a20 +10001fa0: 3fe00000 .word 0x3fe00000 +10001fa4: 66666667 .word 0x66666667 +10001fa8: 10003978 .word 0x10003978 +10001fac: 10003980 .word 0x10003980 +10001fb0: 1000398c .word 0x1000398c +10001fb4: cccccccd .word 0xcccccccd +10001fb8: 2200 movs r2, #0 +10001fba: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001fbe: 4b63 ldr r3, [pc, #396] @ (1000214c <_ftoa+0x4b4>) +10001fc0: f7ff fcda bl 10001978 <__wrap___aeabi_dcmplt> +10001fc4: 2800 cmp r0, #0 +10001fc6: f47f af08 bne.w 10001dda <_ftoa+0x142> +10001fca: f1ba 0f00 cmp.w sl, #0 +10001fce: d16a bne.n 100020a6 <_ftoa+0x40e> +10001fd0: f10a 0a01 add.w sl, sl, #1 +10001fd4: 2e00 cmp r6, #0 +10001fd6: f47f af03 bne.w 10001de0 <_ftoa+0x148> +10001fda: 4620 mov r0, r4 +10001fdc: f7ff fc72 bl 100018c4 <__wrap___aeabi_i2d> +10001fe0: 4602 mov r2, r0 +10001fe2: 460b mov r3, r1 +10001fe4: e9dd 0104 ldrd r0, r1, [sp, #16] +10001fe8: f7ff fbe4 bl 100017b4 <__wrap___aeabi_dsub> +10001fec: 4602 mov r2, r0 +10001fee: 460b mov r3, r1 +10001ff0: e9cd 2304 strd r2, r3, [sp, #16] +10001ff4: 2200 movs r2, #0 +10001ff6: 4b55 ldr r3, [pc, #340] @ (1000214c <_ftoa+0x4b4>) +10001ff8: f7ff fcbe bl 10001978 <__wrap___aeabi_dcmplt> +10001ffc: 2800 cmp r0, #0 +10001ffe: f47f af0c bne.w 10001e1a <_ftoa+0x182> +10002002: e9dd 0104 ldrd r0, r1, [sp, #16] +10002006: 2200 movs r2, #0 +10002008: 4b50 ldr r3, [pc, #320] @ (1000214c <_ftoa+0x4b4>) +1000200a: f7ff fcf1 bl 100019f0 <__wrap___aeabi_dcmpgt> +1000200e: 2800 cmp r0, #0 +10002010: f47f af03 bne.w 10001e1a <_ftoa+0x182> +10002014: 3401 adds r4, #1 +10002016: f024 0401 bic.w r4, r4, #1 +1000201a: e6fe b.n 10001e1a <_ftoa+0x182> +1000201c: 9b07 ldr r3, [sp, #28] +1000201e: f003 0303 and.w r3, r3, #3 +10002022: 2b01 cmp r3, #1 +10002024: f000 8082 beq.w 1000212c <_ftoa+0x494> +10002028: 2d20 cmp r5, #32 +1000202a: f43f af2e beq.w 10001e8a <_ftoa+0x1f2> +1000202e: 9b0d ldr r3, [sp, #52] @ 0x34 +10002030: b37b cbz r3, 10002092 <_ftoa+0x3fa> +10002032: 222d movs r2, #45 @ 0x2d +10002034: eb0d 0305 add.w r3, sp, r5 +10002038: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1000203c: 3501 adds r5, #1 +1000203e: e724 b.n 10001e8a <_ftoa+0x1f2> +10002040: 2b20 cmp r3, #32 +10002042: f43f aee9 beq.w 10001e18 <_ftoa+0x180> +10002046: aa0e add r2, sp, #56 @ 0x38 +10002048: 4415 add r5, r2 +1000204a: 441e add r6, r3 +1000204c: 2230 movs r2, #48 @ 0x30 +1000204e: e004 b.n 1000205a <_ftoa+0x3c2> +10002050: 2b20 cmp r3, #32 +10002052: f805 2f01 strb.w r2, [r5, #1]! +10002056: f43f aedf beq.w 10001e18 <_ftoa+0x180> +1000205a: 429e cmp r6, r3 +1000205c: f103 0301 add.w r3, r3, #1 +10002060: d1f6 bne.n 10002050 <_ftoa+0x3b8> +10002062: 222e movs r2, #46 @ 0x2e +10002064: eb0d 0306 add.w r3, sp, r6 +10002068: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1000206c: 1c75 adds r5, r6, #1 +1000206e: e6d4 b.n 10001e1a <_ftoa+0x182> +10002070: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10002074: e763 b.n 10001f3e <_ftoa+0x2a6> +10002076: 2520 movs r5, #32 +10002078: e66e b.n 10001d58 <_ftoa+0xc0> +1000207a: 9b07 ldr r3, [sp, #28] +1000207c: f013 0f0c tst.w r3, #12 +10002080: d050 beq.n 10002124 <_ftoa+0x48c> +10002082: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10002086: 45ab cmp fp, r5 +10002088: f63f aef2 bhi.w 10001e70 <_ftoa+0x1d8> +1000208c: 2d20 cmp r5, #32 +1000208e: f43f aefc beq.w 10001e8a <_ftoa+0x1f2> +10002092: 9b07 ldr r3, [sp, #28] +10002094: 075a lsls r2, r3, #29 +10002096: d501 bpl.n 1000209c <_ftoa+0x404> +10002098: 222b movs r2, #43 @ 0x2b +1000209a: e7cb b.n 10002034 <_ftoa+0x39c> +1000209c: 071b lsls r3, r3, #28 +1000209e: f57f aef4 bpl.w 10001e8a <_ftoa+0x1f2> +100020a2: 2220 movs r2, #32 +100020a4: e7c6 b.n 10002034 <_ftoa+0x39c> +100020a6: f01a 0f01 tst.w sl, #1 +100020aa: f43f ae96 beq.w 10001dda <_ftoa+0x142> +100020ae: e78f b.n 10001fd0 <_ftoa+0x338> +100020b0: 07a6 lsls r6, r4, #30 +100020b2: d134 bne.n 1000211e <_ftoa+0x486> +100020b4: f1bb 0f03 cmp.w fp, #3 +100020b8: d931 bls.n 1000211e <_ftoa+0x486> +100020ba: 9b0c ldr r3, [sp, #48] @ 0x30 +100020bc: 461d mov r5, r3 +100020be: 1edc subs r4, r3, #3 +100020c0: eb04 0a0b add.w sl, r4, fp +100020c4: 462a mov r2, r5 +100020c6: 464b mov r3, r9 +100020c8: 4641 mov r1, r8 +100020ca: 2020 movs r0, #32 +100020cc: 3501 adds r5, #1 +100020ce: 47b8 blx r7 +100020d0: 4555 cmp r5, sl +100020d2: d1f7 bne.n 100020c4 <_ftoa+0x42c> +100020d4: 4655 mov r5, sl +100020d6: 4c1e ldr r4, [pc, #120] @ (10002150 <_ftoa+0x4b8>) +100020d8: 1ee6 subs r6, r4, #3 +100020da: f814 0d01 ldrb.w r0, [r4, #-1]! +100020de: 462a mov r2, r5 +100020e0: 464b mov r3, r9 +100020e2: 4641 mov r1, r8 +100020e4: 47b8 blx r7 +100020e6: 42a6 cmp r6, r4 +100020e8: f105 0501 add.w r5, r5, #1 +100020ec: d1f5 bne.n 100020da <_ftoa+0x442> +100020ee: 9b07 ldr r3, [sp, #28] +100020f0: f10a 0a03 add.w sl, sl, #3 +100020f4: 079d lsls r5, r3, #30 +100020f6: f57f aed5 bpl.w 10001ea4 <_ftoa+0x20c> +100020fa: 9c0c ldr r4, [sp, #48] @ 0x30 +100020fc: ebaa 0304 sub.w r3, sl, r4 +10002100: 459b cmp fp, r3 +10002102: f67f aecf bls.w 10001ea4 <_ftoa+0x20c> +10002106: 4652 mov r2, sl +10002108: 464b mov r3, r9 +1000210a: 4641 mov r1, r8 +1000210c: 2020 movs r0, #32 +1000210e: f10a 0a01 add.w sl, sl, #1 +10002112: 47b8 blx r7 +10002114: ebaa 0304 sub.w r3, sl, r4 +10002118: 459b cmp fp, r3 +1000211a: d8f4 bhi.n 10002106 <_ftoa+0x46e> +1000211c: e6c2 b.n 10001ea4 <_ftoa+0x20c> +1000211e: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10002122: e7d7 b.n 100020d4 <_ftoa+0x43c> +10002124: 45ab cmp fp, r5 +10002126: f63f aea3 bhi.w 10001e70 <_ftoa+0x1d8> +1000212a: e6ae b.n 10001e8a <_ftoa+0x1f2> +1000212c: f1bb 0f00 cmp.w fp, #0 +10002130: f43f af7a beq.w 10002028 <_ftoa+0x390> +10002134: 9b0d ldr r3, [sp, #52] @ 0x34 +10002136: 2b00 cmp r3, #0 +10002138: d09f beq.n 1000207a <_ftoa+0x3e2> +1000213a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1000213e: 455d cmp r5, fp +10002140: f4ff ae96 bcc.w 10001e70 <_ftoa+0x1d8> +10002144: 2d20 cmp r5, #32 +10002146: f47f af74 bne.w 10002032 <_ftoa+0x39a> +1000214a: e69e b.n 10001e8a <_ftoa+0x1f2> +1000214c: 3fe00000 .word 0x3fe00000 +10002150: 10003987 .word 0x10003987 +10002154: 00000000 .word 0x00000000 + +10002158 <_etoa>: +10002158: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000215c: b09f sub sp, #124 @ 0x7c +1000215e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10002160: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10002164: 4607 mov r7, r0 +10002166: 4693 mov fp, r2 +10002168: 9108 str r1, [sp, #32] +1000216a: 9309 str r3, [sp, #36] @ 0x24 +1000216c: 4622 mov r2, r4 +1000216e: 462b mov r3, r5 +10002170: 4620 mov r0, r4 +10002172: 4629 mov r1, r5 +10002174: 960e str r6, [sp, #56] @ 0x38 +10002176: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +1000217a: f7ff fbeb bl 10001954 <__wrap___aeabi_dcmpun> +1000217e: 2800 cmp r0, #0 +10002180: f040 80be bne.w 10002300 <_etoa+0x1a8> +10002184: 4620 mov r0, r4 +10002186: 4629 mov r1, r5 +10002188: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000218c: 4b78 ldr r3, [pc, #480] @ (10002370 <_etoa+0x218>) +1000218e: f7ff fc2f bl 100019f0 <__wrap___aeabi_dcmpgt> +10002192: 2800 cmp r0, #0 +10002194: f040 80b4 bne.w 10002300 <_etoa+0x1a8> +10002198: 4620 mov r0, r4 +1000219a: 4629 mov r1, r5 +1000219c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100021a0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100021a4: f7ff fbe8 bl 10001978 <__wrap___aeabi_dcmplt> +100021a8: 2800 cmp r0, #0 +100021aa: f040 80a9 bne.w 10002300 <_etoa+0x1a8> +100021ae: 4620 mov r0, r4 +100021b0: 4629 mov r1, r5 +100021b2: 2200 movs r2, #0 +100021b4: 2300 movs r3, #0 +100021b6: f7ff fbdf bl 10001978 <__wrap___aeabi_dcmplt> +100021ba: 2800 cmp r0, #0 +100021bc: f040 81d5 bne.w 1000256a <_etoa+0x412> +100021c0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +100021c4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +100021c8: 4690 mov r8, r2 +100021ca: 4699 mov r9, r3 +100021cc: f406 6200 and.w r2, r6, #2048 @ 0x800 +100021d0: f416 6380 ands.w r3, r6, #1024 @ 0x400 +100021d4: 920f str r2, [sp, #60] @ 0x3c +100021d6: 9313 str r3, [sp, #76] @ 0x4c +100021d8: f040 80a1 bne.w 1000231e <_etoa+0x1c6> +100021dc: ea58 0309 orrs.w r3, r8, r9 +100021e0: f040 80ca bne.w 10002378 <_etoa+0x220> +100021e4: 2a00 cmp r2, #0 +100021e6: f040 81e3 bne.w 100025b0 <_etoa+0x458> +100021ea: 2306 movs r3, #6 +100021ec: 930e str r3, [sp, #56] @ 0x38 +100021ee: f016 0202 ands.w r2, r6, #2 +100021f2: 9210 str r2, [sp, #64] @ 0x40 +100021f4: f040 81d4 bne.w 100025a0 <_etoa+0x448> +100021f8: 4653 mov r3, sl +100021fa: 2b04 cmp r3, #4 +100021fc: bf38 it cc +100021fe: 2304 movcc r3, #4 +10002200: 920c str r2, [sp, #48] @ 0x30 +10002202: 2204 movs r2, #4 +10002204: 3b04 subs r3, #4 +10002206: 9212 str r2, [sp, #72] @ 0x48 +10002208: 930f str r3, [sp, #60] @ 0x3c +1000220a: 4620 mov r0, r4 +1000220c: 4629 mov r1, r5 +1000220e: 2200 movs r2, #0 +10002210: 2300 movs r3, #0 +10002212: f7ff fbb1 bl 10001978 <__wrap___aeabi_dcmplt> +10002216: 2800 cmp r0, #0 +10002218: f040 81f3 bne.w 10002602 <_etoa+0x4aa> +1000221c: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002220: 9b0f ldr r3, [sp, #60] @ 0x3c +10002222: 465a mov r2, fp +10002224: 9303 str r3, [sp, #12] +10002226: 9b0e ldr r3, [sp, #56] @ 0x38 +10002228: ed8d 7b00 vstr d7, [sp] +1000222c: 9302 str r3, [sp, #8] +1000222e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002232: 9304 str r3, [sp, #16] +10002234: 4638 mov r0, r7 +10002236: 9b09 ldr r3, [sp, #36] @ 0x24 +10002238: 9908 ldr r1, [sp, #32] +1000223a: f7ff fd2d bl 10001c98 <_ftoa> +1000223e: 4602 mov r2, r0 +10002240: f016 0f20 tst.w r6, #32 +10002244: 9b09 ldr r3, [sp, #36] @ 0x24 +10002246: 9908 ldr r1, [sp, #32] +10002248: bf0c ite eq +1000224a: 2065 moveq r0, #101 @ 0x65 +1000224c: 2045 movne r0, #69 @ 0x45 +1000224e: f102 0801 add.w r8, r2, #1 +10002252: 47b8 blx r7 +10002254: 9a0c ldr r2, [sp, #48] @ 0x30 +10002256: 9b12 ldr r3, [sp, #72] @ 0x48 +10002258: ac16 add r4, sp, #88 @ 0x58 +1000225a: 1e5d subs r5, r3, #1 +1000225c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10002260: eba3 73e2 sub.w r3, r3, r2, asr #31 +10002264: 0fd1 lsrs r1, r2, #31 +10002266: 2600 movs r6, #0 +10002268: 4622 mov r2, r4 +1000226a: 4699 mov r9, r3 +1000226c: f8df c104 ldr.w ip, [pc, #260] @ 10002374 <_etoa+0x21c> +10002270: e001 b.n 10002276 <_etoa+0x11e> +10002272: 2e20 cmp r6, #32 +10002274: d010 beq.n 10002298 <_etoa+0x140> +10002276: 46ce mov lr, r9 +10002278: fbac 3009 umull r3, r0, ip, r9 +1000227c: 08c0 lsrs r0, r0, #3 +1000227e: eb00 0380 add.w r3, r0, r0, lsl #2 +10002282: eba9 0343 sub.w r3, r9, r3, lsl #1 +10002286: 3330 adds r3, #48 @ 0x30 +10002288: f1be 0f09 cmp.w lr, #9 +1000228c: 4681 mov r9, r0 +1000228e: f106 0601 add.w r6, r6, #1 +10002292: f802 3b01 strb.w r3, [r2], #1 +10002296: d8ec bhi.n 10002272 <_etoa+0x11a> +10002298: 2305 movs r3, #5 +1000229a: 2000 movs r0, #0 +1000229c: 9306 str r3, [sp, #24] +1000229e: 230a movs r3, #10 +100022a0: 9505 str r5, [sp, #20] +100022a2: 9400 str r4, [sp, #0] +100022a4: 9d09 ldr r5, [sp, #36] @ 0x24 +100022a6: 9c08 ldr r4, [sp, #32] +100022a8: 4642 mov r2, r8 +100022aa: e9cd 3003 strd r3, r0, [sp, #12] +100022ae: e9cd 6101 strd r6, r1, [sp, #4] +100022b2: 462b mov r3, r5 +100022b4: 4621 mov r1, r4 +100022b6: 4638 mov r0, r7 +100022b8: f7ff fbfa bl 10001ab0 <_ntoa_format> +100022bc: 9a10 ldr r2, [sp, #64] @ 0x40 +100022be: 4680 mov r8, r0 +100022c0: b1d2 cbz r2, 100022f8 <_etoa+0x1a0> +100022c2: eba0 060b sub.w r6, r0, fp +100022c6: 45b2 cmp sl, r6 +100022c8: d916 bls.n 100022f8 <_etoa+0x1a0> +100022ca: eb0b 0206 add.w r2, fp, r6 +100022ce: 462b mov r3, r5 +100022d0: 4621 mov r1, r4 +100022d2: 2020 movs r0, #32 +100022d4: 3601 adds r6, #1 +100022d6: 47b8 blx r7 +100022d8: 45b2 cmp sl, r6 +100022da: d8f6 bhi.n 100022ca <_etoa+0x172> +100022dc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +100022e0: 4453 add r3, sl +100022e2: f1cb 0201 rsb r2, fp, #1 +100022e6: eba3 0308 sub.w r3, r3, r8 +100022ea: 4442 add r2, r8 +100022ec: 4592 cmp sl, r2 +100022ee: bf38 it cc +100022f0: 2300 movcc r3, #0 +100022f2: f108 0801 add.w r8, r8, #1 +100022f6: 4498 add r8, r3 +100022f8: 4640 mov r0, r8 +100022fa: b01f add sp, #124 @ 0x7c +100022fc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002300: 465a mov r2, fp +10002302: 4638 mov r0, r7 +10002304: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002308: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +1000230c: 9c0e ldr r4, [sp, #56] @ 0x38 +1000230e: 9b09 ldr r3, [sp, #36] @ 0x24 +10002310: 9908 ldr r1, [sp, #32] +10002312: 942a str r4, [sp, #168] @ 0xa8 +10002314: b01f add sp, #124 @ 0x7c +10002316: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000231a: f7ff bcbd b.w 10001c98 <_ftoa> +1000231e: ea58 0309 orrs.w r3, r8, r9 +10002322: d12b bne.n 1000237c <_etoa+0x224> +10002324: 2a00 cmp r2, #0 +10002326: f43f af62 beq.w 100021ee <_etoa+0x96> +1000232a: 2300 movs r3, #0 +1000232c: 930c str r3, [sp, #48] @ 0x30 +1000232e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002330: 9a0c ldr r2, [sp, #48] @ 0x30 +10002332: 4293 cmp r3, r2 +10002334: f300 81b9 bgt.w 100026aa <_etoa+0x552> +10002338: f04f 0800 mov.w r8, #0 +1000233c: 4620 mov r0, r4 +1000233e: 4629 mov r1, r5 +10002340: 2200 movs r2, #0 +10002342: 2300 movs r3, #0 +10002344: f7ff fb18 bl 10001978 <__wrap___aeabi_dcmplt> +10002348: 2800 cmp r0, #0 +1000234a: f040 8113 bne.w 10002574 <_etoa+0x41c> +1000234e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002352: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002356: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000235a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1000235e: 465a mov r2, fp +10002360: 4638 mov r0, r7 +10002362: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002366: 9b09 ldr r3, [sp, #36] @ 0x24 +10002368: 9908 ldr r1, [sp, #32] +1000236a: 962c str r6, [sp, #176] @ 0xb0 +1000236c: e7d2 b.n 10002314 <_etoa+0x1bc> +1000236e: bf00 nop +10002370: 7fefffff .word 0x7fefffff +10002374: cccccccd .word 0xcccccccd +10002378: 2306 movs r3, #6 +1000237a: 930e str r3, [sp, #56] @ 0x38 +1000237c: f3c9 500a ubfx r0, r9, #20, #11 +10002380: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10002384: f7ff fa9e bl 100018c4 <__wrap___aeabi_i2d> +10002388: a3c1 add r3, pc, #772 @ (adr r3, 10002690 <_etoa+0x538>) +1000238a: e9d3 2300 ldrd r2, r3, [r3] +1000238e: f7ff fa25 bl 100017dc <__wrap___aeabi_dmul> +10002392: a3c1 add r3, pc, #772 @ (adr r3, 10002698 <_etoa+0x540>) +10002394: e9d3 2300 ldrd r2, r3, [r3] +10002398: f7ff f9f8 bl 1000178c <__wrap___aeabi_dadd> +1000239c: f3c9 0913 ubfx r9, r9, #0, #20 +100023a0: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +100023a4: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +100023a8: 4640 mov r0, r8 +100023aa: 2200 movs r2, #0 +100023ac: 4bb2 ldr r3, [pc, #712] @ (10002678 <_etoa+0x520>) +100023ae: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +100023b2: f7ff f9ff bl 100017b4 <__wrap___aeabi_dsub> +100023b6: a3a4 add r3, pc, #656 @ (adr r3, 10002648 <_etoa+0x4f0>) +100023b8: e9d3 2300 ldrd r2, r3, [r3] +100023bc: f7ff fa0e bl 100017dc <__wrap___aeabi_dmul> +100023c0: 4602 mov r2, r0 +100023c2: 460b mov r3, r1 +100023c4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +100023c8: f7ff f9e0 bl 1000178c <__wrap___aeabi_dadd> +100023cc: f7ff fa9e bl 1000190c <__wrap___aeabi_d2iz> +100023d0: 900c str r0, [sp, #48] @ 0x30 +100023d2: f7ff fa77 bl 100018c4 <__wrap___aeabi_i2d> +100023d6: a39e add r3, pc, #632 @ (adr r3, 10002650 <_etoa+0x4f8>) +100023d8: e9d3 2300 ldrd r2, r3, [r3] +100023dc: 4680 mov r8, r0 +100023de: 4689 mov r9, r1 +100023e0: f7ff f9fc bl 100017dc <__wrap___aeabi_dmul> +100023e4: 2200 movs r2, #0 +100023e6: 4ba5 ldr r3, [pc, #660] @ (1000267c <_etoa+0x524>) +100023e8: f7ff f9d0 bl 1000178c <__wrap___aeabi_dadd> +100023ec: f7ff fa8e bl 1000190c <__wrap___aeabi_d2iz> +100023f0: 4603 mov r3, r0 +100023f2: 4649 mov r1, r9 +100023f4: 4640 mov r0, r8 +100023f6: 9312 str r3, [sp, #72] @ 0x48 +100023f8: a397 add r3, pc, #604 @ (adr r3, 10002658 <_etoa+0x500>) +100023fa: e9d3 2300 ldrd r2, r3, [r3] +100023fe: f7ff f9ed bl 100017dc <__wrap___aeabi_dmul> +10002402: 4680 mov r8, r0 +10002404: 9812 ldr r0, [sp, #72] @ 0x48 +10002406: 4689 mov r9, r1 +10002408: f7ff fa5c bl 100018c4 <__wrap___aeabi_i2d> +1000240c: a394 add r3, pc, #592 @ (adr r3, 10002660 <_etoa+0x508>) +1000240e: e9d3 2300 ldrd r2, r3, [r3] +10002412: f7ff f9e3 bl 100017dc <__wrap___aeabi_dmul> +10002416: 4602 mov r2, r0 +10002418: 460b mov r3, r1 +1000241a: 4640 mov r0, r8 +1000241c: 4649 mov r1, r9 +1000241e: f7ff f9c9 bl 100017b4 <__wrap___aeabi_dsub> +10002422: 4602 mov r2, r0 +10002424: 460b mov r3, r1 +10002426: 4680 mov r8, r0 +10002428: 4689 mov r9, r1 +1000242a: f7ff f9d7 bl 100017dc <__wrap___aeabi_dmul> +1000242e: 4642 mov r2, r8 +10002430: 464b mov r3, r9 +10002432: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10002436: 4640 mov r0, r8 +10002438: 4649 mov r1, r9 +1000243a: f7ff f9a7 bl 1000178c <__wrap___aeabi_dadd> +1000243e: 2200 movs r2, #0 +10002440: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10002444: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002448: 4b8d ldr r3, [pc, #564] @ (10002680 <_etoa+0x528>) +1000244a: f7ff f9ed bl 10001828 <__wrap___aeabi_ddiv> +1000244e: 2200 movs r2, #0 +10002450: 4b8c ldr r3, [pc, #560] @ (10002684 <_etoa+0x52c>) +10002452: f7ff f99b bl 1000178c <__wrap___aeabi_dadd> +10002456: 4602 mov r2, r0 +10002458: 460b mov r3, r1 +1000245a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000245e: f7ff f9e3 bl 10001828 <__wrap___aeabi_ddiv> +10002462: 2200 movs r2, #0 +10002464: 4b88 ldr r3, [pc, #544] @ (10002688 <_etoa+0x530>) +10002466: f7ff f991 bl 1000178c <__wrap___aeabi_dadd> +1000246a: 4602 mov r2, r0 +1000246c: 460b mov r3, r1 +1000246e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002472: f7ff f9d9 bl 10001828 <__wrap___aeabi_ddiv> +10002476: 4642 mov r2, r8 +10002478: 464b mov r3, r9 +1000247a: 4680 mov r8, r0 +1000247c: 4689 mov r9, r1 +1000247e: 2000 movs r0, #0 +10002480: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002484: f7ff f996 bl 100017b4 <__wrap___aeabi_dsub> +10002488: 4602 mov r2, r0 +1000248a: 460b mov r3, r1 +1000248c: 4640 mov r0, r8 +1000248e: 4649 mov r1, r9 +10002490: f7ff f97c bl 1000178c <__wrap___aeabi_dadd> +10002494: 4602 mov r2, r0 +10002496: 460b mov r3, r1 +10002498: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000249c: f7ff f9c4 bl 10001828 <__wrap___aeabi_ddiv> +100024a0: 2200 movs r2, #0 +100024a2: 4b7a ldr r3, [pc, #488] @ (1000268c <_etoa+0x534>) +100024a4: f7ff f972 bl 1000178c <__wrap___aeabi_dadd> +100024a8: 9b12 ldr r3, [sp, #72] @ 0x48 +100024aa: 2200 movs r2, #0 +100024ac: f203 3cff addw ip, r3, #1023 @ 0x3ff +100024b0: ea4f 530c mov.w r3, ip, lsl #20 +100024b4: f7ff f992 bl 100017dc <__wrap___aeabi_dmul> +100024b8: 4680 mov r8, r0 +100024ba: 4689 mov r9, r1 +100024bc: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100024c0: 4642 mov r2, r8 +100024c2: 464b mov r3, r9 +100024c4: f7ff fa58 bl 10001978 <__wrap___aeabi_dcmplt> +100024c8: b150 cbz r0, 100024e0 <_etoa+0x388> +100024ca: 9b0c ldr r3, [sp, #48] @ 0x30 +100024cc: 4640 mov r0, r8 +100024ce: 3b01 subs r3, #1 +100024d0: 4649 mov r1, r9 +100024d2: 930c str r3, [sp, #48] @ 0x30 +100024d4: 2200 movs r2, #0 +100024d6: 4b6b ldr r3, [pc, #428] @ (10002684 <_etoa+0x52c>) +100024d8: f7ff f9a6 bl 10001828 <__wrap___aeabi_ddiv> +100024dc: 4680 mov r8, r0 +100024de: 4689 mov r9, r1 +100024e0: 9a0c ldr r2, [sp, #48] @ 0x30 +100024e2: 4643 mov r3, r8 +100024e4: 3263 adds r2, #99 @ 0x63 +100024e6: 2ac6 cmp r2, #198 @ 0xc6 +100024e8: f006 0202 and.w r2, r6, #2 +100024ec: 9210 str r2, [sp, #64] @ 0x40 +100024ee: 4649 mov r1, r9 +100024f0: 9a0f ldr r2, [sp, #60] @ 0x3c +100024f2: d82c bhi.n 1000254e <_etoa+0x3f6> +100024f4: 2a00 cmp r2, #0 +100024f6: d05e beq.n 100025b6 <_etoa+0x45e> +100024f8: 2204 movs r2, #4 +100024fa: 9212 str r2, [sp, #72] @ 0x48 +100024fc: 430b orrs r3, r1 +100024fe: f43f af16 beq.w 1000232e <_etoa+0x1d6> +10002502: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002506: a358 add r3, pc, #352 @ (adr r3, 10002668 <_etoa+0x510>) +10002508: e9d3 2300 ldrd r2, r3, [r3] +1000250c: f7ff fa5c bl 100019c8 <__wrap___aeabi_dcmpge> +10002510: b148 cbz r0, 10002526 <_etoa+0x3ce> +10002512: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002516: a356 add r3, pc, #344 @ (adr r3, 10002670 <_etoa+0x518>) +10002518: e9d3 2300 ldrd r2, r3, [r3] +1000251c: f7ff fa2c bl 10001978 <__wrap___aeabi_dcmplt> +10002520: 2800 cmp r0, #0 +10002522: f47f af04 bne.w 1000232e <_etoa+0x1d6> +10002526: 9b0e ldr r3, [sp, #56] @ 0x38 +10002528: 2b00 cmp r3, #0 +1000252a: d050 beq.n 100025ce <_etoa+0x476> +1000252c: 9a13 ldr r2, [sp, #76] @ 0x4c +1000252e: 2a00 cmp r2, #0 +10002530: d07d beq.n 1000262e <_etoa+0x4d6> +10002532: 3b01 subs r3, #1 +10002534: 930e str r3, [sp, #56] @ 0x38 +10002536: 9b12 ldr r3, [sp, #72] @ 0x48 +10002538: 459a cmp sl, r3 +1000253a: d905 bls.n 10002548 <_etoa+0x3f0> +1000253c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000253e: 2b00 cmp r3, #0 +10002540: f000 80ae beq.w 100026a0 <_etoa+0x548> +10002544: 2302 movs r3, #2 +10002546: 9310 str r3, [sp, #64] @ 0x40 +10002548: 2300 movs r3, #0 +1000254a: 930f str r3, [sp, #60] @ 0x3c +1000254c: e044 b.n 100025d8 <_etoa+0x480> +1000254e: bb22 cbnz r2, 1000259a <_etoa+0x442> +10002550: f1ba 0f05 cmp.w sl, #5 +10002554: d94f bls.n 100025f6 <_etoa+0x49e> +10002556: f006 0302 and.w r3, r6, #2 +1000255a: 2b00 cmp r3, #0 +1000255c: d149 bne.n 100025f2 <_etoa+0x49a> +1000255e: 2305 movs r3, #5 +10002560: 9312 str r3, [sp, #72] @ 0x48 +10002562: f1aa 0305 sub.w r3, sl, #5 +10002566: 930f str r3, [sp, #60] @ 0x3c +10002568: e03a b.n 100025e0 <_etoa+0x488> +1000256a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000256e: 940a str r4, [sp, #40] @ 0x28 +10002570: 930b str r3, [sp, #44] @ 0x2c +10002572: e627 b.n 100021c4 <_etoa+0x6c> +10002574: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002578: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000257c: 4638 mov r0, r7 +1000257e: 962c str r6, [sp, #176] @ 0xb0 +10002580: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002584: 4634 mov r4, r6 +10002586: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000258a: 465a mov r2, fp +1000258c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002590: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002594: 9b09 ldr r3, [sp, #36] @ 0x24 +10002596: 9908 ldr r1, [sp, #32] +10002598: e6bc b.n 10002314 <_etoa+0x1bc> +1000259a: 2205 movs r2, #5 +1000259c: 9212 str r2, [sp, #72] @ 0x48 +1000259e: e7ad b.n 100024fc <_etoa+0x3a4> +100025a0: 2300 movs r3, #0 +100025a2: 2202 movs r2, #2 +100025a4: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +100025a8: 2204 movs r2, #4 +100025aa: 930c str r3, [sp, #48] @ 0x30 +100025ac: 9212 str r2, [sp, #72] @ 0x48 +100025ae: e62c b.n 1000220a <_etoa+0xb2> +100025b0: f04f 0805 mov.w r8, #5 +100025b4: e6c2 b.n 1000233c <_etoa+0x1e4> +100025b6: f1ba 0f04 cmp.w sl, #4 +100025ba: d91f bls.n 100025fc <_etoa+0x4a4> +100025bc: 9b10 ldr r3, [sp, #64] @ 0x40 +100025be: 2b00 cmp r3, #0 +100025c0: d178 bne.n 100026b4 <_etoa+0x55c> +100025c2: 2304 movs r3, #4 +100025c4: 9312 str r3, [sp, #72] @ 0x48 +100025c6: f1aa 0304 sub.w r3, sl, #4 +100025ca: 930f str r3, [sp, #60] @ 0x3c +100025cc: e004 b.n 100025d8 <_etoa+0x480> +100025ce: 9b12 ldr r3, [sp, #72] @ 0x48 +100025d0: 459a cmp sl, r3 +100025d2: d831 bhi.n 10002638 <_etoa+0x4e0> +100025d4: 9b0e ldr r3, [sp, #56] @ 0x38 +100025d6: 930f str r3, [sp, #60] @ 0x3c +100025d8: 9b0c ldr r3, [sp, #48] @ 0x30 +100025da: 2b00 cmp r3, #0 +100025dc: f43f ae15 beq.w 1000220a <_etoa+0xb2> +100025e0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100025e4: 4642 mov r2, r8 +100025e6: 464b mov r3, r9 +100025e8: f7ff f91e bl 10001828 <__wrap___aeabi_ddiv> +100025ec: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100025f0: e60b b.n 1000220a <_etoa+0xb2> +100025f2: 2302 movs r3, #2 +100025f4: 9310 str r3, [sp, #64] @ 0x40 +100025f6: 2305 movs r3, #5 +100025f8: 9312 str r3, [sp, #72] @ 0x48 +100025fa: e7f1 b.n 100025e0 <_etoa+0x488> +100025fc: 2304 movs r3, #4 +100025fe: 9312 str r3, [sp, #72] @ 0x48 +10002600: e7ea b.n 100025d8 <_etoa+0x480> +10002602: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +10002606: 46a0 mov r8, r4 +10002608: 9b0f ldr r3, [sp, #60] @ 0x3c +1000260a: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +1000260e: 9303 str r3, [sp, #12] +10002610: 9b0e ldr r3, [sp, #56] @ 0x38 +10002612: 465a mov r2, fp +10002614: 9302 str r3, [sp, #8] +10002616: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1000261a: 9304 str r3, [sp, #16] +1000261c: 4638 mov r0, r7 +1000261e: e9cd 8900 strd r8, r9, [sp] +10002622: 9b09 ldr r3, [sp, #36] @ 0x24 +10002624: 9908 ldr r1, [sp, #32] +10002626: f7ff fb37 bl 10001c98 <_ftoa> +1000262a: 4602 mov r2, r0 +1000262c: e608 b.n 10002240 <_etoa+0xe8> +1000262e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002630: 459a cmp sl, r3 +10002632: d844 bhi.n 100026be <_etoa+0x566> +10002634: 920f str r2, [sp, #60] @ 0x3c +10002636: e7cf b.n 100025d8 <_etoa+0x480> +10002638: 9b10 ldr r3, [sp, #64] @ 0x40 +1000263a: b38b cbz r3, 100026a0 <_etoa+0x548> +1000263c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000263e: 930f str r3, [sp, #60] @ 0x3c +10002640: 2302 movs r3, #2 +10002642: 9310 str r3, [sp, #64] @ 0x40 +10002644: e7c8 b.n 100025d8 <_etoa+0x480> +10002646: bf00 nop +10002648: 636f4361 .word 0x636f4361 +1000264c: 3fd287a7 .word 0x3fd287a7 +10002650: 0979a371 .word 0x0979a371 +10002654: 400a934f .word 0x400a934f +10002658: bbb55516 .word 0xbbb55516 +1000265c: 40026bb1 .word 0x40026bb1 +10002660: fefa39ef .word 0xfefa39ef +10002664: 3fe62e42 .word 0x3fe62e42 +10002668: eb1c432d .word 0xeb1c432d +1000266c: 3f1a36e2 .word 0x3f1a36e2 +10002670: 00000000 .word 0x00000000 +10002674: 412e8480 .word 0x412e8480 +10002678: 3ff80000 .word 0x3ff80000 +1000267c: 3fe00000 .word 0x3fe00000 +10002680: 402c0000 .word 0x402c0000 +10002684: 40240000 .word 0x40240000 +10002688: 40180000 .word 0x40180000 +1000268c: 3ff00000 .word 0x3ff00000 +10002690: 509f79fb .word 0x509f79fb +10002694: 3fd34413 .word 0x3fd34413 +10002698: 8b60c8b3 .word 0x8b60c8b3 +1000269c: 3fc68a28 .word 0x3fc68a28 +100026a0: 9b12 ldr r3, [sp, #72] @ 0x48 +100026a2: ebaa 0303 sub.w r3, sl, r3 +100026a6: 930f str r3, [sp, #60] @ 0x3c +100026a8: e796 b.n 100025d8 <_etoa+0x480> +100026aa: eba3 0802 sub.w r8, r3, r2 +100026ae: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100026b2: e643 b.n 1000233c <_etoa+0x1e4> +100026b4: 2304 movs r3, #4 +100026b6: 9312 str r3, [sp, #72] @ 0x48 +100026b8: 2302 movs r3, #2 +100026ba: 9310 str r3, [sp, #64] @ 0x40 +100026bc: e78c b.n 100025d8 <_etoa+0x480> +100026be: 9b10 ldr r3, [sp, #64] @ 0x40 +100026c0: 2b00 cmp r3, #0 +100026c2: d0ed beq.n 100026a0 <_etoa+0x548> +100026c4: 2302 movs r3, #2 +100026c6: 920f str r2, [sp, #60] @ 0x3c +100026c8: 9310 str r3, [sp, #64] @ 0x40 +100026ca: e785 b.n 100025d8 <_etoa+0x480> + +100026cc <_vsnprintf>: +100026cc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100026d0: b09b sub sp, #108 @ 0x6c +100026d2: 9c24 ldr r4, [sp, #144] @ 0x90 +100026d4: 4d95 ldr r5, [pc, #596] @ (1000292c <_vsnprintf+0x260>) +100026d6: 940a str r4, [sp, #40] @ 0x28 +100026d8: 4c95 ldr r4, [pc, #596] @ (10002930 <_vsnprintf+0x264>) +100026da: f1b1 0a00 subs.w sl, r1, #0 +100026de: bf18 it ne +100026e0: 4683 movne fp, r0 +100026e2: 6025 str r5, [r4, #0] +100026e4: 7818 ldrb r0, [r3, #0] +100026e6: 4c93 ldr r4, [pc, #588] @ (10002934 <_vsnprintf+0x268>) +100026e8: 4691 mov r9, r2 +100026ea: bf08 it eq +100026ec: 46a3 moveq fp, r4 +100026ee: 9309 str r3, [sp, #36] @ 0x24 +100026f0: 2800 cmp r0, #0 +100026f2: f000 8293 beq.w 10002c1c <_vsnprintf+0x550> +100026f6: f04f 0800 mov.w r8, #0 +100026fa: e00a b.n 10002712 <_vsnprintf+0x46> +100026fc: 4642 mov r2, r8 +100026fe: 464b mov r3, r9 +10002700: 4651 mov r1, sl +10002702: f108 0801 add.w r8, r8, #1 +10002706: 47d8 blx fp +10002708: 9b09 ldr r3, [sp, #36] @ 0x24 +1000270a: 7818 ldrb r0, [r3, #0] +1000270c: 2800 cmp r0, #0 +1000270e: f000 80ce beq.w 100028ae <_vsnprintf+0x1e2> +10002712: 9b09 ldr r3, [sp, #36] @ 0x24 +10002714: 2825 cmp r0, #37 @ 0x25 +10002716: f103 0301 add.w r3, r3, #1 +1000271a: 9309 str r3, [sp, #36] @ 0x24 +1000271c: d1ee bne.n 100026fc <_vsnprintf+0x30> +1000271e: 461c mov r4, r3 +10002720: 2300 movs r3, #0 +10002722: 4622 mov r2, r4 +10002724: f812 0b01 ldrb.w r0, [r2], #1 +10002728: f1a0 0120 sub.w r1, r0, #32 +1000272c: 2910 cmp r1, #16 +1000272e: d80a bhi.n 10002746 <_vsnprintf+0x7a> +10002730: e8df f001 tbb [pc, r1] +10002734: 3c090940 .word 0x3c090940 +10002738: 09090909 .word 0x09090909 +1000273c: 38090909 .word 0x38090909 +10002740: 09093409 .word 0x09093409 +10002744: 30 .byte 0x30 +10002745: 00 .byte 0x00 +10002746: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000274a: 2909 cmp r1, #9 +1000274c: 9409 str r4, [sp, #36] @ 0x24 +1000274e: f240 808a bls.w 10002866 <_vsnprintf+0x19a> +10002752: 282a cmp r0, #42 @ 0x2a +10002754: f000 80f0 beq.w 10002938 <_vsnprintf+0x26c> +10002758: 2500 movs r5, #0 +1000275a: 282e cmp r0, #46 @ 0x2e +1000275c: f000 8096 beq.w 1000288c <_vsnprintf+0x1c0> +10002760: 2600 movs r6, #0 +10002762: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002766: 2912 cmp r1, #18 +10002768: d82d bhi.n 100027c6 <_vsnprintf+0xfa> +1000276a: e8df f011 tbh [pc, r1, lsl #1] +1000276e: 0149 .short 0x0149 +10002770: 0143002c .word 0x0143002c +10002774: 0138002c .word 0x0138002c +10002778: 002c002c .word 0x002c002c +1000277c: 002c002c .word 0x002c002c +10002780: 002c002c .word 0x002c002c +10002784: 0027002c .word 0x0027002c +10002788: 002c002c .word 0x002c002c +1000278c: 002c002c .word 0x002c002c +10002790: 0027002c .word 0x0027002c +10002794: 4614 mov r4, r2 +10002796: f043 0301 orr.w r3, r3, #1 +1000279a: e7c2 b.n 10002722 <_vsnprintf+0x56> +1000279c: 4614 mov r4, r2 +1000279e: f043 0302 orr.w r3, r3, #2 +100027a2: e7be b.n 10002722 <_vsnprintf+0x56> +100027a4: 4614 mov r4, r2 +100027a6: f043 0304 orr.w r3, r3, #4 +100027aa: e7ba b.n 10002722 <_vsnprintf+0x56> +100027ac: 4614 mov r4, r2 +100027ae: f043 0310 orr.w r3, r3, #16 +100027b2: e7b6 b.n 10002722 <_vsnprintf+0x56> +100027b4: 4614 mov r4, r2 +100027b6: f043 0308 orr.w r3, r3, #8 +100027ba: e7b2 b.n 10002722 <_vsnprintf+0x56> +100027bc: 9909 ldr r1, [sp, #36] @ 0x24 +100027be: 7848 ldrb r0, [r1, #1] +100027c0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100027c4: 3201 adds r2, #1 +100027c6: 2867 cmp r0, #103 @ 0x67 +100027c8: 9209 str r2, [sp, #36] @ 0x24 +100027ca: d87e bhi.n 100028ca <_vsnprintf+0x1fe> +100027cc: 2824 cmp r0, #36 @ 0x24 +100027ce: f240 80c1 bls.w 10002954 <_vsnprintf+0x288> +100027d2: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100027d6: 2a42 cmp r2, #66 @ 0x42 +100027d8: f200 80bc bhi.w 10002954 <_vsnprintf+0x288> +100027dc: e8df f012 tbh [pc, r2, lsl #1] +100027e0: 00ba0150 .word 0x00ba0150 +100027e4: 00ba00ba .word 0x00ba00ba +100027e8: 00ba00ba .word 0x00ba00ba +100027ec: 00ba00ba .word 0x00ba00ba +100027f0: 00ba00ba .word 0x00ba00ba +100027f4: 00ba00ba .word 0x00ba00ba +100027f8: 00ba00ba .word 0x00ba00ba +100027fc: 00ba00ba .word 0x00ba00ba +10002800: 00ba00ba .word 0x00ba00ba +10002804: 00ba00ba .word 0x00ba00ba +10002808: 00ba00ba .word 0x00ba00ba +1000280c: 00ba00ba .word 0x00ba00ba +10002810: 00ba00ba .word 0x00ba00ba +10002814: 00ba00ba .word 0x00ba00ba +10002818: 00ba00ba .word 0x00ba00ba +1000281c: 00ba00ba .word 0x00ba00ba +10002820: 01370119 .word 0x01370119 +10002824: 00ba0119 .word 0x00ba0119 +10002828: 00ba00ba .word 0x00ba00ba +1000282c: 00ba00ba .word 0x00ba00ba +10002830: 00ba00ba .word 0x00ba00ba +10002834: 00ba00ba .word 0x00ba00ba +10002838: 00ba00ba .word 0x00ba00ba +1000283c: 00ba00ba .word 0x00ba00ba +10002840: 00ba00ba .word 0x00ba00ba +10002844: 01bc00ba .word 0x01bc00ba +10002848: 00ba00ba .word 0x00ba00ba +1000284c: 00ba00ba .word 0x00ba00ba +10002850: 00ba00ba .word 0x00ba00ba +10002854: 00ba00ba .word 0x00ba00ba +10002858: 01bc00ba .word 0x01bc00ba +1000285c: 01bc0158 .word 0x01bc0158 +10002860: 01370119 .word 0x01370119 +10002864: 0119 .short 0x0119 +10002866: 2500 movs r5, #0 +10002868: e000 b.n 1000286c <_vsnprintf+0x1a0> +1000286a: 3201 adds r2, #1 +1000286c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002870: eb00 0545 add.w r5, r0, r5, lsl #1 +10002874: 7810 ldrb r0, [r2, #0] +10002876: 3d30 subs r5, #48 @ 0x30 +10002878: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000287c: 2909 cmp r1, #9 +1000287e: d9f4 bls.n 1000286a <_vsnprintf+0x19e> +10002880: 282e cmp r0, #46 @ 0x2e +10002882: 9209 str r2, [sp, #36] @ 0x24 +10002884: f102 0201 add.w r2, r2, #1 +10002888: f47f af6a bne.w 10002760 <_vsnprintf+0x94> +1000288c: 9909 ldr r1, [sp, #36] @ 0x24 +1000288e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002892: 7848 ldrb r0, [r1, #1] +10002894: 4611 mov r1, r2 +10002896: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000289a: 2e09 cmp r6, #9 +1000289c: f240 8121 bls.w 10002ae2 <_vsnprintf+0x416> +100028a0: 282a cmp r0, #42 @ 0x2a +100028a2: f000 812f beq.w 10002b04 <_vsnprintf+0x438> +100028a6: 9209 str r2, [sp, #36] @ 0x24 +100028a8: 2600 movs r6, #0 +100028aa: 3201 adds r2, #1 +100028ac: e759 b.n 10002762 <_vsnprintf+0x96> +100028ae: 4644 mov r4, r8 +100028b0: 45c1 cmp r9, r8 +100028b2: d801 bhi.n 100028b8 <_vsnprintf+0x1ec> +100028b4: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100028b8: 464b mov r3, r9 +100028ba: 4642 mov r2, r8 +100028bc: 4651 mov r1, sl +100028be: 2000 movs r0, #0 +100028c0: 47d8 blx fp +100028c2: 4620 mov r0, r4 +100028c4: b01b add sp, #108 @ 0x6c +100028c6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100028ca: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100028ce: b2d2 uxtb r2, r2 +100028d0: 2a0f cmp r2, #15 +100028d2: d83f bhi.n 10002954 <_vsnprintf+0x288> +100028d4: 2101 movs r1, #1 +100028d6: f249 0741 movw r7, #36929 @ 0x9041 +100028da: 4091 lsls r1, r2 +100028dc: 4039 ands r1, r7 +100028de: f040 80f3 bne.w 10002ac8 <_vsnprintf+0x3fc> +100028e2: 2a0a cmp r2, #10 +100028e4: d03d beq.n 10002962 <_vsnprintf+0x296> +100028e6: 2a07 cmp r2, #7 +100028e8: d134 bne.n 10002954 <_vsnprintf+0x288> +100028ea: 9d0a ldr r5, [sp, #40] @ 0x28 +100028ec: f855 2b04 ldr.w r2, [r5], #4 +100028f0: 2a00 cmp r2, #0 +100028f2: f000 8113 beq.w 10002b1c <_vsnprintf+0x450> +100028f6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100028fa: ab12 add r3, sp, #72 @ 0x48 +100028fc: 461f mov r7, r3 +100028fe: 930b str r3, [sp, #44] @ 0x2c +10002900: e003 b.n 1000290a <_vsnprintf+0x23e> +10002902: 2920 cmp r1, #32 +10002904: f000 8114 beq.w 10002b30 <_vsnprintf+0x464> +10002908: 461a mov r2, r3 +1000290a: f002 040f and.w r4, r2, #15 +1000290e: 4623 mov r3, r4 +10002910: 2c09 cmp r4, #9 +10002912: bf94 ite ls +10002914: 3330 addls r3, #48 @ 0x30 +10002916: 3337 addhi r3, #55 @ 0x37 +10002918: 2a0f cmp r2, #15 +1000291a: f807 3b01 strb.w r3, [r7], #1 +1000291e: f101 0101 add.w r1, r1, #1 +10002922: ea4f 1312 mov.w r3, r2, lsr #4 +10002926: d8ec bhi.n 10002902 <_vsnprintf+0x236> +10002928: e102 b.n 10002b30 <_vsnprintf+0x464> +1000292a: bf00 nop +1000292c: 100026cd .word 0x100026cd +10002930: 20000810 .word 0x20000810 +10002934: 10001a11 .word 0x10001a11 +10002938: 990a ldr r1, [sp, #40] @ 0x28 +1000293a: 9809 ldr r0, [sp, #36] @ 0x24 +1000293c: f851 5b04 ldr.w r5, [r1], #4 +10002940: 7840 ldrb r0, [r0, #1] +10002942: 2d00 cmp r5, #0 +10002944: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002948: bfbc itt lt +1000294a: f043 0302 orrlt.w r3, r3, #2 +1000294e: 426d neglt r5, r5 +10002950: 3201 adds r2, #1 +10002952: e702 b.n 1000275a <_vsnprintf+0x8e> +10002954: 4642 mov r2, r8 +10002956: 464b mov r3, r9 +10002958: 4651 mov r1, sl +1000295a: f108 0801 add.w r8, r8, #1 +1000295e: 47d8 blx fp +10002960: e6d2 b.n 10002708 <_vsnprintf+0x3c> +10002962: 990a ldr r1, [sp, #40] @ 0x28 +10002964: 2e00 cmp r6, #0 +10002966: f851 7b04 ldr.w r7, [r1], #4 +1000296a: bf18 it ne +1000296c: 4632 movne r2, r6 +1000296e: 7838 ldrb r0, [r7, #0] +10002970: bf08 it eq +10002972: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002976: 2800 cmp r0, #0 +10002978: f000 837b beq.w 10003072 <_vsnprintf+0x9a6> +1000297c: 18bc adds r4, r7, r2 +1000297e: 46a4 mov ip, r4 +10002980: 463a mov r2, r7 +10002982: e004 b.n 1000298e <_vsnprintf+0x2c2> +10002984: f812 4f01 ldrb.w r4, [r2, #1]! +10002988: 2c00 cmp r4, #0 +1000298a: f000 813f beq.w 10002c0c <_vsnprintf+0x540> +1000298e: 4594 cmp ip, r2 +10002990: d1f8 bne.n 10002984 <_vsnprintf+0x2b8> +10002992: 4664 mov r4, ip +10002994: 1be4 subs r4, r4, r7 +10002996: 055a lsls r2, r3, #21 +10002998: f140 8122 bpl.w 10002be0 <_vsnprintf+0x514> +1000299c: 42b4 cmp r4, r6 +1000299e: bf28 it cs +100029a0: 4634 movcs r4, r6 +100029a2: f013 0302 ands.w r3, r3, #2 +100029a6: f000 8288 beq.w 10002eba <_vsnprintf+0x7ee> +100029aa: 2302 movs r3, #2 +100029ac: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100029b0: 4642 mov r2, r8 +100029b2: 461d mov r5, r3 +100029b4: 4446 add r6, r8 +100029b6: e008 b.n 100029ca <_vsnprintf+0x2fe> +100029b8: 464b mov r3, r9 +100029ba: 4651 mov r1, sl +100029bc: 47d8 blx fp +100029be: f817 0f01 ldrb.w r0, [r7, #1]! +100029c2: f108 0801 add.w r8, r8, #1 +100029c6: b110 cbz r0, 100029ce <_vsnprintf+0x302> +100029c8: 4642 mov r2, r8 +100029ca: 4546 cmp r6, r8 +100029cc: d1f4 bne.n 100029b8 <_vsnprintf+0x2ec> +100029ce: 462b mov r3, r5 +100029d0: 990b ldr r1, [sp, #44] @ 0x2c +100029d2: 9d0a ldr r5, [sp, #40] @ 0x28 +100029d4: 2b00 cmp r3, #0 +100029d6: f040 8141 bne.w 10002c5c <_vsnprintf+0x590> +100029da: 910a str r1, [sp, #40] @ 0x28 +100029dc: e694 b.n 10002708 <_vsnprintf+0x3c> +100029de: 9909 ldr r1, [sp, #36] @ 0x24 +100029e0: 7848 ldrb r0, [r1, #1] +100029e2: 286c cmp r0, #108 @ 0x6c +100029e4: f47f aeec bne.w 100027c0 <_vsnprintf+0xf4> +100029e8: 460a mov r2, r1 +100029ea: 7888 ldrb r0, [r1, #2] +100029ec: f443 7340 orr.w r3, r3, #768 @ 0x300 +100029f0: 3203 adds r2, #3 +100029f2: e6e8 b.n 100027c6 <_vsnprintf+0xfa> +100029f4: 9909 ldr r1, [sp, #36] @ 0x24 +100029f6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100029fa: 7848 ldrb r0, [r1, #1] +100029fc: 3201 adds r2, #1 +100029fe: e6e2 b.n 100027c6 <_vsnprintf+0xfa> +10002a00: 9909 ldr r1, [sp, #36] @ 0x24 +10002a02: 7848 ldrb r0, [r1, #1] +10002a04: 2868 cmp r0, #104 @ 0x68 +10002a06: f000 8103 beq.w 10002c10 <_vsnprintf+0x544> +10002a0a: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002a0e: 3201 adds r2, #1 +10002a10: e6d9 b.n 100027c6 <_vsnprintf+0xfa> +10002a12: 2867 cmp r0, #103 @ 0x67 +10002a14: f000 80d9 beq.w 10002bca <_vsnprintf+0x4fe> +10002a18: 2847 cmp r0, #71 @ 0x47 +10002a1a: f000 80dc beq.w 10002bd6 <_vsnprintf+0x50a> +10002a1e: 2845 cmp r0, #69 @ 0x45 +10002a20: f000 80db beq.w 10002bda <_vsnprintf+0x50e> +10002a24: e9cd 5303 strd r5, r3, [sp, #12] +10002a28: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a2a: 9602 str r6, [sp, #8] +10002a2c: 3307 adds r3, #7 +10002a2e: f023 0307 bic.w r3, r3, #7 +10002a32: 461c mov r4, r3 +10002a34: 4642 mov r2, r8 +10002a36: e8f4 6702 ldrd r6, r7, [r4], #8 +10002a3a: 464b mov r3, r9 +10002a3c: 4651 mov r1, sl +10002a3e: 4658 mov r0, fp +10002a40: e9cd 6700 strd r6, r7, [sp] +10002a44: 940a str r4, [sp, #40] @ 0x28 +10002a46: f7ff fb87 bl 10002158 <_etoa> +10002a4a: 4680 mov r8, r0 +10002a4c: e65c b.n 10002708 <_vsnprintf+0x3c> +10002a4e: 2846 cmp r0, #70 @ 0x46 +10002a50: bf08 it eq +10002a52: f043 0320 orreq.w r3, r3, #32 +10002a56: e9cd 5303 strd r5, r3, [sp, #12] +10002a5a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a5c: 9602 str r6, [sp, #8] +10002a5e: 3307 adds r3, #7 +10002a60: f023 0307 bic.w r3, r3, #7 +10002a64: 461c mov r4, r3 +10002a66: 4642 mov r2, r8 +10002a68: e8f4 6702 ldrd r6, r7, [r4], #8 +10002a6c: 464b mov r3, r9 +10002a6e: 4651 mov r1, sl +10002a70: 4658 mov r0, fp +10002a72: e9cd 6700 strd r6, r7, [sp] +10002a76: 940a str r4, [sp, #40] @ 0x28 +10002a78: f7ff f90e bl 10001c98 <_ftoa> +10002a7c: 4680 mov r8, r0 +10002a7e: e643 b.n 10002708 <_vsnprintf+0x3c> +10002a80: 4642 mov r2, r8 +10002a82: 464b mov r3, r9 +10002a84: 4651 mov r1, sl +10002a86: 2025 movs r0, #37 @ 0x25 +10002a88: f108 0801 add.w r8, r8, #1 +10002a8c: 47d8 blx fp +10002a8e: e63b b.n 10002708 <_vsnprintf+0x3c> +10002a90: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a92: 0799 lsls r1, r3, #30 +10002a94: f102 0404 add.w r4, r2, #4 +10002a98: f108 0601 add.w r6, r8, #1 +10002a9c: f140 80c6 bpl.w 10002c2c <_vsnprintf+0x560> +10002aa0: 7810 ldrb r0, [r2, #0] +10002aa2: 464b mov r3, r9 +10002aa4: 4642 mov r2, r8 +10002aa6: 4651 mov r1, sl +10002aa8: 47d8 blx fp +10002aaa: 2d01 cmp r5, #1 +10002aac: bf88 it hi +10002aae: 44a8 addhi r8, r5 +10002ab0: f240 81bd bls.w 10002e2e <_vsnprintf+0x762> +10002ab4: 4632 mov r2, r6 +10002ab6: 464b mov r3, r9 +10002ab8: 4651 mov r1, sl +10002aba: 2020 movs r0, #32 +10002abc: 3601 adds r6, #1 +10002abe: 47d8 blx fp +10002ac0: 4546 cmp r6, r8 +10002ac2: d1f7 bne.n 10002ab4 <_vsnprintf+0x3e8> +10002ac4: 940a str r4, [sp, #40] @ 0x28 +10002ac6: e61f b.n 10002708 <_vsnprintf+0x3c> +10002ac8: 286f cmp r0, #111 @ 0x6f +10002aca: f000 8081 beq.w 10002bd0 <_vsnprintf+0x504> +10002ace: f240 8248 bls.w 10002f62 <_vsnprintf+0x896> +10002ad2: 2878 cmp r0, #120 @ 0x78 +10002ad4: f000 8190 beq.w 10002df8 <_vsnprintf+0x72c> +10002ad8: 270a movs r7, #10 +10002ada: f023 0310 bic.w r3, r3, #16 +10002ade: 46bc mov ip, r7 +10002ae0: e041 b.n 10002b66 <_vsnprintf+0x49a> +10002ae2: 2600 movs r6, #0 +10002ae4: eb06 0686 add.w r6, r6, r6, lsl #2 +10002ae8: eb00 0046 add.w r0, r0, r6, lsl #1 +10002aec: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002af0: f811 0f01 ldrb.w r0, [r1, #1]! +10002af4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002af8: 2a09 cmp r2, #9 +10002afa: d9f3 bls.n 10002ae4 <_vsnprintf+0x418> +10002afc: 460a mov r2, r1 +10002afe: 9109 str r1, [sp, #36] @ 0x24 +10002b00: 3201 adds r2, #1 +10002b02: e62e b.n 10002762 <_vsnprintf+0x96> +10002b04: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002b08: f851 6b04 ldr.w r6, [r1], #4 +10002b0c: 7890 ldrb r0, [r2, #2] +10002b0e: 3202 adds r2, #2 +10002b10: 9209 str r2, [sp, #36] @ 0x24 +10002b12: 910a str r1, [sp, #40] @ 0x28 +10002b14: 3201 adds r2, #1 +10002b16: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002b1a: e622 b.n 10002762 <_vsnprintf+0x96> +10002b1c: f023 0010 bic.w r0, r3, #16 +10002b20: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b24: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002b28: f43f aee7 beq.w 100028fa <_vsnprintf+0x22e> +10002b2c: ab12 add r3, sp, #72 @ 0x48 +10002b2e: 930b str r3, [sp, #44] @ 0x2c +10002b30: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b32: 9006 str r0, [sp, #24] +10002b34: 9300 str r3, [sp, #0] +10002b36: 2308 movs r3, #8 +10002b38: 2010 movs r0, #16 +10002b3a: 9305 str r3, [sp, #20] +10002b3c: 2300 movs r3, #0 +10002b3e: 4642 mov r2, r8 +10002b40: e9cd 3002 strd r3, r0, [sp, #8] +10002b44: 9101 str r1, [sp, #4] +10002b46: 464b mov r3, r9 +10002b48: 4651 mov r1, sl +10002b4a: 4658 mov r0, fp +10002b4c: 9604 str r6, [sp, #16] +10002b4e: f7fe ffaf bl 10001ab0 <_ntoa_format> +10002b52: 950a str r5, [sp, #40] @ 0x28 +10002b54: 4680 mov r8, r0 +10002b56: e5d7 b.n 10002708 <_vsnprintf+0x3c> +10002b58: 2858 cmp r0, #88 @ 0x58 +10002b5a: d062 beq.n 10002c22 <_vsnprintf+0x556> +10002b5c: 2862 cmp r0, #98 @ 0x62 +10002b5e: f040 808f bne.w 10002c80 <_vsnprintf+0x5b4> +10002b62: 2702 movs r7, #2 +10002b64: 46bc mov ip, r7 +10002b66: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002b6a: f000 80dd beq.w 10002d28 <_vsnprintf+0x65c> +10002b6e: f023 030d bic.w r3, r3, #13 +10002b72: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002b76: f040 8181 bne.w 10002e7c <_vsnprintf+0x7b0> +10002b7a: 990a ldr r1, [sp, #40] @ 0x28 +10002b7c: 1d0f adds r7, r1, #4 +10002b7e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002b82: f040 8237 bne.w 10002ff4 <_vsnprintf+0x928> +10002b86: 065c lsls r4, r3, #25 +10002b88: 9a0a ldr r2, [sp, #40] @ 0x28 +10002b8a: f140 813b bpl.w 10002e04 <_vsnprintf+0x738> +10002b8e: 7812 ldrb r2, [r2, #0] +10002b90: 2a00 cmp r2, #0 +10002b92: f040 814e bne.w 10002e32 <_vsnprintf+0x766> +10002b96: f023 0310 bic.w r3, r3, #16 +10002b9a: 2800 cmp r0, #0 +10002b9c: f000 8149 beq.w 10002e32 <_vsnprintf+0x766> +10002ba0: 4611 mov r1, r2 +10002ba2: aa12 add r2, sp, #72 @ 0x48 +10002ba4: 920b str r2, [sp, #44] @ 0x2c +10002ba6: e9cd 5305 strd r5, r3, [sp, #20] +10002baa: e9cd c603 strd ip, r6, [sp, #12] +10002bae: 9101 str r1, [sp, #4] +10002bb0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002bb2: 4642 mov r2, r8 +10002bb4: 9300 str r3, [sp, #0] +10002bb6: 2300 movs r3, #0 +10002bb8: 4651 mov r1, sl +10002bba: 9302 str r3, [sp, #8] +10002bbc: 4658 mov r0, fp +10002bbe: 464b mov r3, r9 +10002bc0: f7fe ff76 bl 10001ab0 <_ntoa_format> +10002bc4: 970a str r7, [sp, #40] @ 0x28 +10002bc6: 4680 mov r8, r0 +10002bc8: e59e b.n 10002708 <_vsnprintf+0x3c> +10002bca: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002bce: e729 b.n 10002a24 <_vsnprintf+0x358> +10002bd0: 2708 movs r7, #8 +10002bd2: 46bc mov ip, r7 +10002bd4: e7c7 b.n 10002b66 <_vsnprintf+0x49a> +10002bd6: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002bda: f043 0320 orr.w r3, r3, #32 +10002bde: e721 b.n 10002a24 <_vsnprintf+0x358> +10002be0: f013 0302 ands.w r3, r3, #2 +10002be4: f000 818e beq.w 10002f04 <_vsnprintf+0x838> +10002be8: 2302 movs r3, #2 +10002bea: 950a str r5, [sp, #40] @ 0x28 +10002bec: 461e mov r6, r3 +10002bee: 460d mov r5, r1 +10002bf0: 4642 mov r2, r8 +10002bf2: 464b mov r3, r9 +10002bf4: 4651 mov r1, sl +10002bf6: 47d8 blx fp +10002bf8: f817 0f01 ldrb.w r0, [r7, #1]! +10002bfc: f108 0801 add.w r8, r8, #1 +10002c00: 2800 cmp r0, #0 +10002c02: d1f5 bne.n 10002bf0 <_vsnprintf+0x524> +10002c04: 4629 mov r1, r5 +10002c06: 4633 mov r3, r6 +10002c08: 9d0a ldr r5, [sp, #40] @ 0x28 +10002c0a: e6e3 b.n 100029d4 <_vsnprintf+0x308> +10002c0c: 1bd4 subs r4, r2, r7 +10002c0e: e6c2 b.n 10002996 <_vsnprintf+0x2ca> +10002c10: 460a mov r2, r1 +10002c12: 7888 ldrb r0, [r1, #2] +10002c14: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002c18: 3203 adds r2, #3 +10002c1a: e5d4 b.n 100027c6 <_vsnprintf+0xfa> +10002c1c: 4604 mov r4, r0 +10002c1e: 4680 mov r8, r0 +10002c20: e646 b.n 100028b0 <_vsnprintf+0x1e4> +10002c22: 2710 movs r7, #16 +10002c24: f043 0320 orr.w r3, r3, #32 +10002c28: 46bc mov ip, r7 +10002c2a: e79c b.n 10002b66 <_vsnprintf+0x49a> +10002c2c: 2d01 cmp r5, #1 +10002c2e: f240 80f8 bls.w 10002e22 <_vsnprintf+0x756> +10002c32: 4646 mov r6, r8 +10002c34: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002c38: 442f add r7, r5 +10002c3a: 4632 mov r2, r6 +10002c3c: 464b mov r3, r9 +10002c3e: 4651 mov r1, sl +10002c40: 2020 movs r0, #32 +10002c42: 3601 adds r6, #1 +10002c44: 47d8 blx fp +10002c46: 42be cmp r6, r7 +10002c48: d1f7 bne.n 10002c3a <_vsnprintf+0x56e> +10002c4a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c4c: 4632 mov r2, r6 +10002c4e: 7818 ldrb r0, [r3, #0] +10002c50: 4651 mov r1, sl +10002c52: 464b mov r3, r9 +10002c54: 47d8 blx fp +10002c56: 44a8 add r8, r5 +10002c58: 940a str r4, [sp, #40] @ 0x28 +10002c5a: e555 b.n 10002708 <_vsnprintf+0x3c> +10002c5c: 4646 mov r6, r8 +10002c5e: 42a5 cmp r5, r4 +10002c60: f67f aebb bls.w 100029da <_vsnprintf+0x30e> +10002c64: 44a8 add r8, r5 +10002c66: eba8 0804 sub.w r8, r8, r4 +10002c6a: 460c mov r4, r1 +10002c6c: 4632 mov r2, r6 +10002c6e: 464b mov r3, r9 +10002c70: 4651 mov r1, sl +10002c72: 2020 movs r0, #32 +10002c74: 3601 adds r6, #1 +10002c76: 47d8 blx fp +10002c78: 4546 cmp r6, r8 +10002c7a: d1f7 bne.n 10002c6c <_vsnprintf+0x5a0> +10002c7c: 4621 mov r1, r4 +10002c7e: e6ac b.n 100029da <_vsnprintf+0x30e> +10002c80: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002c84: f000 80bb beq.w 10002dfe <_vsnprintf+0x732> +10002c88: f44f 6280 mov.w r2, #1024 @ 0x400 +10002c8c: f023 0c11 bic.w ip, r3, #17 +10002c90: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002c94: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c96: d14a bne.n 10002d2e <_vsnprintf+0x662> +10002c98: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002c9c: f103 0404 add.w r4, r3, #4 +10002ca0: f040 8134 bne.w 10002f0c <_vsnprintf+0x840> +10002ca4: f01c 0f40 tst.w ip, #64 @ 0x40 +10002ca8: f040 80a3 bne.w 10002df2 <_vsnprintf+0x726> +10002cac: f01c 0f80 tst.w ip, #128 @ 0x80 +10002cb0: f000 81d3 beq.w 1000305a <_vsnprintf+0x98e> +10002cb4: f9b3 1000 ldrsh.w r1, [r3] +10002cb8: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002cbc: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002cc0: b2bf uxth r7, r7 +10002cc2: 0fcb lsrs r3, r1, #31 +10002cc4: 2900 cmp r1, #0 +10002cc6: f000 8156 beq.w 10002f76 <_vsnprintf+0x8aa> +10002cca: 463a mov r2, r7 +10002ccc: a912 add r1, sp, #72 @ 0x48 +10002cce: 460f mov r7, r1 +10002cd0: f8df e3d8 ldr.w lr, [pc, #984] @ 100030ac <_vsnprintf+0x9e0> +10002cd4: 910b str r1, [sp, #44] @ 0x2c +10002cd6: 930a str r3, [sp, #40] @ 0x28 +10002cd8: 950c str r5, [sp, #48] @ 0x30 +10002cda: e001 b.n 10002ce0 <_vsnprintf+0x614> +10002cdc: 2820 cmp r0, #32 +10002cde: d00f beq.n 10002d00 <_vsnprintf+0x634> +10002ce0: 4615 mov r5, r2 +10002ce2: fbae 1302 umull r1, r3, lr, r2 +10002ce6: 08db lsrs r3, r3, #3 +10002ce8: eb03 0183 add.w r1, r3, r3, lsl #2 +10002cec: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002cf0: 3130 adds r1, #48 @ 0x30 +10002cf2: 2d09 cmp r5, #9 +10002cf4: 461a mov r2, r3 +10002cf6: f100 0001 add.w r0, r0, #1 +10002cfa: f807 1b01 strb.w r1, [r7], #1 +10002cfe: d8ed bhi.n 10002cdc <_vsnprintf+0x610> +10002d00: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d02: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d04: e9cd 5c05 strd r5, ip, [sp, #20] +10002d08: e9cd 0301 strd r0, r3, [sp, #4] +10002d0c: 9604 str r6, [sp, #16] +10002d0e: 9b0b ldr r3, [sp, #44] @ 0x2c +10002d10: 4642 mov r2, r8 +10002d12: 9300 str r3, [sp, #0] +10002d14: 230a movs r3, #10 +10002d16: 4651 mov r1, sl +10002d18: 9303 str r3, [sp, #12] +10002d1a: 4658 mov r0, fp +10002d1c: 464b mov r3, r9 +10002d1e: f7fe fec7 bl 10001ab0 <_ntoa_format> +10002d22: 940a str r4, [sp, #40] @ 0x28 +10002d24: 4680 mov r8, r0 +10002d26: e4ef b.n 10002708 <_vsnprintf+0x3c> +10002d28: f023 030c bic.w r3, r3, #12 +10002d2c: e721 b.n 10002b72 <_vsnprintf+0x4a6> +10002d2e: 3307 adds r3, #7 +10002d30: f023 0307 bic.w r3, r3, #7 +10002d34: 4619 mov r1, r3 +10002d36: 4608 mov r0, r1 +10002d38: 685b ldr r3, [r3, #4] +10002d3a: f850 1b08 ldr.w r1, [r0], #8 +10002d3e: 0fdf lsrs r7, r3, #31 +10002d40: 900a str r0, [sp, #40] @ 0x28 +10002d42: ea51 0003 orrs.w r0, r1, r3 +10002d46: d162 bne.n 10002e0e <_vsnprintf+0x742> +10002d48: 2a00 cmp r2, #0 +10002d4a: f040 819f bne.w 1000308c <_vsnprintf+0x9c0> +10002d4e: 4613 mov r3, r2 +10002d50: 4611 mov r1, r2 +10002d52: aa12 add r2, sp, #72 @ 0x48 +10002d54: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002d58: 2000 movs r0, #0 +10002d5a: 4615 mov r5, r2 +10002d5c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002d60: f8df e348 ldr.w lr, [pc, #840] @ 100030ac <_vsnprintf+0x9e0> +10002d64: 920b str r2, [sp, #44] @ 0x2c +10002d66: e001 b.n 10002d6c <_vsnprintf+0x6a0> +10002d68: 2820 cmp r0, #32 +10002d6a: d02d beq.n 10002dc8 <_vsnprintf+0x6fc> +10002d6c: 185a adds r2, r3, r1 +10002d6e: f142 0200 adc.w r2, r2, #0 +10002d72: fbae 7802 umull r7, r8, lr, r2 +10002d76: f028 0703 bic.w r7, r8, #3 +10002d7a: eb07 0798 add.w r7, r7, r8, lsr #2 +10002d7e: 1bd2 subs r2, r2, r7 +10002d80: 461e mov r6, r3 +10002d82: 1a9b subs r3, r3, r2 +10002d84: f161 0700 sbc.w r7, r1, #0 +10002d88: 460c mov r4, r1 +10002d8a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002d8e: fb01 f103 mul.w r1, r1, r3 +10002d92: fb0e 1107 mla r1, lr, r7, r1 +10002d96: fba3 730e umull r7, r3, r3, lr +10002d9a: 4419 add r1, r3 +10002d9c: 2305 movs r3, #5 +10002d9e: f007 0801 and.w r8, r7, #1 +10002da2: fba8 3803 umull r3, r8, r8, r3 +10002da6: 189b adds r3, r3, r2 +10002da8: 2e0a cmp r6, #10 +10002daa: f103 0330 add.w r3, r3, #48 @ 0x30 +10002dae: ea4f 0757 mov.w r7, r7, lsr #1 +10002db2: f174 0400 sbcs.w r4, r4, #0 +10002db6: f805 3b01 strb.w r3, [r5], #1 +10002dba: f100 0001 add.w r0, r0, #1 +10002dbe: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002dc2: ea4f 0151 mov.w r1, r1, lsr #1 +10002dc6: d2cf bcs.n 10002d68 <_vsnprintf+0x69c> +10002dc8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002dcc: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002dd0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002dd2: 4642 mov r2, r8 +10002dd4: 9300 str r3, [sp, #0] +10002dd6: 230a movs r3, #10 +10002dd8: e9cd 5c05 strd r5, ip, [sp, #20] +10002ddc: e9cd 0701 strd r0, r7, [sp, #4] +10002de0: 9604 str r6, [sp, #16] +10002de2: 9303 str r3, [sp, #12] +10002de4: 464b mov r3, r9 +10002de6: 4651 mov r1, sl +10002de8: 4658 mov r0, fp +10002dea: f7fe fe61 bl 10001ab0 <_ntoa_format> +10002dee: 4680 mov r8, r0 +10002df0: e48a b.n 10002708 <_vsnprintf+0x3c> +10002df2: 7819 ldrb r1, [r3, #0] +10002df4: 460f mov r7, r1 +10002df6: e764 b.n 10002cc2 <_vsnprintf+0x5f6> +10002df8: 2710 movs r7, #16 +10002dfa: 46bc mov ip, r7 +10002dfc: e6b3 b.n 10002b66 <_vsnprintf+0x49a> +10002dfe: f023 0c10 bic.w ip, r3, #16 +10002e02: e745 b.n 10002c90 <_vsnprintf+0x5c4> +10002e04: 061c lsls r4, r3, #24 +10002e06: bf4c ite mi +10002e08: 8812 ldrhmi r2, [r2, #0] +10002e0a: 6812 ldrpl r2, [r2, #0] +10002e0c: e6c0 b.n 10002b90 <_vsnprintf+0x4c4> +10002e0e: 460a mov r2, r1 +10002e10: 1e19 subs r1, r3, #0 +10002e12: db01 blt.n 10002e18 <_vsnprintf+0x74c> +10002e14: 4613 mov r3, r2 +10002e16: e79c b.n 10002d52 <_vsnprintf+0x686> +10002e18: 4252 negs r2, r2 +10002e1a: 4613 mov r3, r2 +10002e1c: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002e20: e797 b.n 10002d52 <_vsnprintf+0x686> +10002e22: 4613 mov r3, r2 +10002e24: 4651 mov r1, sl +10002e26: 7818 ldrb r0, [r3, #0] +10002e28: 4642 mov r2, r8 +10002e2a: 464b mov r3, r9 +10002e2c: 47d8 blx fp +10002e2e: 46b0 mov r8, r6 +10002e30: e648 b.n 10002ac4 <_vsnprintf+0x3f8> +10002e32: f013 0f20 tst.w r3, #32 +10002e36: bf14 ite ne +10002e38: 2041 movne r0, #65 @ 0x41 +10002e3a: 2061 moveq r0, #97 @ 0x61 +10002e3c: ac12 add r4, sp, #72 @ 0x48 +10002e3e: 46a6 mov lr, r4 +10002e40: 940b str r4, [sp, #44] @ 0x2c +10002e42: 930a str r3, [sp, #40] @ 0x28 +10002e44: f1a0 040a sub.w r4, r0, #10 +10002e48: 950c str r5, [sp, #48] @ 0x30 +10002e4a: e002 b.n 10002e52 <_vsnprintf+0x786> +10002e4c: 2920 cmp r1, #32 +10002e4e: d012 beq.n 10002e76 <_vsnprintf+0x7aa> +10002e50: 462a mov r2, r5 +10002e52: fbb2 f5fc udiv r5, r2, ip +10002e56: fb0c 2015 mls r0, ip, r5, r2 +10002e5a: b2c3 uxtb r3, r0 +10002e5c: 2809 cmp r0, #9 +10002e5e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002e62: bf8a itet hi +10002e64: 191b addhi r3, r3, r4 +10002e66: b2c3 uxtbls r3, r0 +10002e68: b2db uxtbhi r3, r3 +10002e6a: 4562 cmp r2, ip +10002e6c: f80e 3b01 strb.w r3, [lr], #1 +10002e70: f101 0101 add.w r1, r1, #1 +10002e74: d2ea bcs.n 10002e4c <_vsnprintf+0x780> +10002e76: 9b0a ldr r3, [sp, #40] @ 0x28 +10002e78: 9d0c ldr r5, [sp, #48] @ 0x30 +10002e7a: e694 b.n 10002ba6 <_vsnprintf+0x4da> +10002e7c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002e7e: 3207 adds r2, #7 +10002e80: f022 0207 bic.w r2, r2, #7 +10002e84: 6851 ldr r1, [r2, #4] +10002e86: f852 4b08 ldr.w r4, [r2], #8 +10002e8a: 468e mov lr, r1 +10002e8c: 920a str r2, [sp, #40] @ 0x28 +10002e8e: ea54 0201 orrs.w r2, r4, r1 +10002e92: d176 bne.n 10002f82 <_vsnprintf+0x8b6> +10002e94: f023 0310 bic.w r3, r3, #16 +10002e98: 2800 cmp r0, #0 +10002e9a: d072 beq.n 10002f82 <_vsnprintf+0x8b6> +10002e9c: 2200 movs r2, #0 +10002e9e: 4611 mov r1, r2 +10002ea0: aa12 add r2, sp, #72 @ 0x48 +10002ea2: 920b str r2, [sp, #44] @ 0x2c +10002ea4: e9cd 5305 strd r5, r3, [sp, #20] +10002ea8: 9b0b ldr r3, [sp, #44] @ 0x2c +10002eaa: 4642 mov r2, r8 +10002eac: 9300 str r3, [sp, #0] +10002eae: 2300 movs r3, #0 +10002eb0: e9cd c603 strd ip, r6, [sp, #12] +10002eb4: 9101 str r1, [sp, #4] +10002eb6: 9302 str r3, [sp, #8] +10002eb8: e794 b.n 10002de4 <_vsnprintf+0x718> +10002eba: 42a5 cmp r5, r4 +10002ebc: bf98 it ls +10002ebe: 3401 addls r4, #1 +10002ec0: f67f ad74 bls.w 100029ac <_vsnprintf+0x2e0> +10002ec4: f44f 6380 mov.w r3, #1024 @ 0x400 +10002ec8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002ecc: eb05 0208 add.w r2, r5, r8 +10002ed0: 461f mov r7, r3 +10002ed2: 460d mov r5, r1 +10002ed4: 1b14 subs r4, r2, r4 +10002ed6: 4642 mov r2, r8 +10002ed8: 464b mov r3, r9 +10002eda: 4651 mov r1, sl +10002edc: 2020 movs r0, #32 +10002ede: f108 0801 add.w r8, r8, #1 +10002ee2: 47d8 blx fp +10002ee4: 45a0 cmp r8, r4 +10002ee6: d1f6 bne.n 10002ed6 <_vsnprintf+0x80a> +10002ee8: 463b mov r3, r7 +10002eea: 9f0a ldr r7, [sp, #40] @ 0x28 +10002eec: 4629 mov r1, r5 +10002eee: 7838 ldrb r0, [r7, #0] +10002ef0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002ef2: 1c6c adds r4, r5, #1 +10002ef4: 2800 cmp r0, #0 +10002ef6: f43f ad70 beq.w 100029da <_vsnprintf+0x30e> +10002efa: 2b00 cmp r3, #0 +10002efc: f43f ae75 beq.w 10002bea <_vsnprintf+0x51e> +10002f00: 2300 movs r3, #0 +10002f02: e553 b.n 100029ac <_vsnprintf+0x2e0> +10002f04: 42a5 cmp r5, r4 +10002f06: d8df bhi.n 10002ec8 <_vsnprintf+0x7fc> +10002f08: 3401 adds r4, #1 +10002f0a: e66e b.n 10002bea <_vsnprintf+0x51e> +10002f0c: 6819 ldr r1, [r3, #0] +10002f0e: 0fcb lsrs r3, r1, #31 +10002f10: 2900 cmp r1, #0 +10002f12: f000 80a8 beq.w 10003066 <_vsnprintf+0x99a> +10002f16: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002f1a: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002f1e: a912 add r1, sp, #72 @ 0x48 +10002f20: 4608 mov r0, r1 +10002f22: f8df e188 ldr.w lr, [pc, #392] @ 100030ac <_vsnprintf+0x9e0> +10002f26: 910b str r1, [sp, #44] @ 0x2c +10002f28: 930a str r3, [sp, #40] @ 0x28 +10002f2a: 950c str r5, [sp, #48] @ 0x30 +10002f2c: e001 b.n 10002f32 <_vsnprintf+0x866> +10002f2e: 2f20 cmp r7, #32 +10002f30: d00f beq.n 10002f52 <_vsnprintf+0x886> +10002f32: 4615 mov r5, r2 +10002f34: fbae 1302 umull r1, r3, lr, r2 +10002f38: 08db lsrs r3, r3, #3 +10002f3a: eb03 0183 add.w r1, r3, r3, lsl #2 +10002f3e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002f42: 3130 adds r1, #48 @ 0x30 +10002f44: 2d09 cmp r5, #9 +10002f46: 461a mov r2, r3 +10002f48: f107 0701 add.w r7, r7, #1 +10002f4c: f800 1b01 strb.w r1, [r0], #1 +10002f50: d8ed bhi.n 10002f2e <_vsnprintf+0x862> +10002f52: 9b0a ldr r3, [sp, #40] @ 0x28 +10002f54: 9d0c ldr r5, [sp, #48] @ 0x30 +10002f56: e9cd 5c05 strd r5, ip, [sp, #20] +10002f5a: e9cd 7301 strd r7, r3, [sp, #4] +10002f5e: 9604 str r6, [sp, #16] +10002f60: e6d5 b.n 10002d0e <_vsnprintf+0x642> +10002f62: 2869 cmp r0, #105 @ 0x69 +10002f64: f023 0c10 bic.w ip, r3, #16 +10002f68: f040 808c bne.w 10003084 <_vsnprintf+0x9b8> +10002f6c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002f70: f43f ae8e beq.w 10002c90 <_vsnprintf+0x5c4> +10002f74: e688 b.n 10002c88 <_vsnprintf+0x5bc> +10002f76: 2a00 cmp r2, #0 +10002f78: f43f aea8 beq.w 10002ccc <_vsnprintf+0x600> +10002f7c: aa12 add r2, sp, #72 @ 0x48 +10002f7e: 920b str r2, [sp, #44] @ 0x2c +10002f80: e6c0 b.n 10002d04 <_vsnprintf+0x638> +10002f82: f013 0f20 tst.w r3, #32 +10002f86: bf14 ite ne +10002f88: 2241 movne r2, #65 @ 0x41 +10002f8a: 2261 moveq r2, #97 @ 0x61 +10002f8c: 2000 movs r0, #0 +10002f8e: a912 add r1, sp, #72 @ 0x48 +10002f90: 3a0a subs r2, #10 +10002f92: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002f96: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002f9a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002f9e: 4606 mov r6, r0 +10002fa0: 4688 mov r8, r1 +10002fa2: 4675 mov r5, lr +10002fa4: 4693 mov fp, r2 +10002fa6: 910b str r1, [sp, #44] @ 0x2c +10002fa8: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002fac: e003 b.n 10002fb6 <_vsnprintf+0x8ea> +10002fae: 2e20 cmp r6, #32 +10002fb0: d017 beq.n 10002fe2 <_vsnprintf+0x916> +10002fb2: 4604 mov r4, r0 +10002fb4: 460d mov r5, r1 +10002fb6: 4629 mov r1, r5 +10002fb8: 463a mov r2, r7 +10002fba: 2300 movs r3, #0 +10002fbc: 4620 mov r0, r4 +10002fbe: f000 fc47 bl 10003850 <____aeabi_uldivmod_veneer> +10002fc2: b2d2 uxtb r2, r2 +10002fc4: 2a09 cmp r2, #9 +10002fc6: f102 0330 add.w r3, r2, #48 @ 0x30 +10002fca: bf88 it hi +10002fcc: eb02 030b addhi.w r3, r2, fp +10002fd0: 42bc cmp r4, r7 +10002fd2: b2db uxtb r3, r3 +10002fd4: f175 0500 sbcs.w r5, r5, #0 +10002fd8: f808 3b01 strb.w r3, [r8], #1 +10002fdc: f106 0601 add.w r6, r6, #1 +10002fe0: d2e5 bcs.n 10002fae <_vsnprintf+0x8e2> +10002fe2: 4631 mov r1, r6 +10002fe4: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002fe8: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002fec: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002ff0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002ff2: e757 b.n 10002ea4 <_vsnprintf+0x7d8> +10002ff4: 990a ldr r1, [sp, #40] @ 0x28 +10002ff6: 6809 ldr r1, [r1, #0] +10002ff8: b951 cbnz r1, 10003010 <_vsnprintf+0x944> +10002ffa: f023 0310 bic.w r3, r3, #16 +10002ffe: b138 cbz r0, 10003010 <_vsnprintf+0x944> +10003000: a912 add r1, sp, #72 @ 0x48 +10003002: 910b str r1, [sp, #44] @ 0x2c +10003004: e9cd 5305 strd r5, r3, [sp, #20] +10003008: e9cd c603 strd ip, r6, [sp, #12] +1000300c: 9201 str r2, [sp, #4] +1000300e: e5cf b.n 10002bb0 <_vsnprintf+0x4e4> +10003010: f013 0f20 tst.w r3, #32 +10003014: bf14 ite ne +10003016: 2041 movne r0, #65 @ 0x41 +10003018: 2061 moveq r0, #97 @ 0x61 +1000301a: ac12 add r4, sp, #72 @ 0x48 +1000301c: 46a6 mov lr, r4 +1000301e: 940b str r4, [sp, #44] @ 0x2c +10003020: 930a str r3, [sp, #40] @ 0x28 +10003022: f1a0 040a sub.w r4, r0, #10 +10003026: 950c str r5, [sp, #48] @ 0x30 +10003028: e002 b.n 10003030 <_vsnprintf+0x964> +1000302a: 2a20 cmp r2, #32 +1000302c: d012 beq.n 10003054 <_vsnprintf+0x988> +1000302e: 4629 mov r1, r5 +10003030: fbb1 f5fc udiv r5, r1, ip +10003034: fb0c 1015 mls r0, ip, r5, r1 +10003038: b2c3 uxtb r3, r0 +1000303a: 2809 cmp r0, #9 +1000303c: f103 0030 add.w r0, r3, #48 @ 0x30 +10003040: bf8a itet hi +10003042: 191b addhi r3, r3, r4 +10003044: b2c3 uxtbls r3, r0 +10003046: b2db uxtbhi r3, r3 +10003048: 4561 cmp r1, ip +1000304a: f80e 3b01 strb.w r3, [lr], #1 +1000304e: f102 0201 add.w r2, r2, #1 +10003052: d2ea bcs.n 1000302a <_vsnprintf+0x95e> +10003054: 9b0a ldr r3, [sp, #40] @ 0x28 +10003056: 9d0c ldr r5, [sp, #48] @ 0x30 +10003058: e7d4 b.n 10003004 <_vsnprintf+0x938> +1000305a: 6819 ldr r1, [r3, #0] +1000305c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10003060: eba7 77e1 sub.w r7, r7, r1, asr #31 +10003064: e62d b.n 10002cc2 <_vsnprintf+0x5f6> +10003066: 2a00 cmp r2, #0 +10003068: f43f af59 beq.w 10002f1e <_vsnprintf+0x852> +1000306c: aa12 add r2, sp, #72 @ 0x48 +1000306e: 920b str r2, [sp, #44] @ 0x2c +10003070: e771 b.n 10002f56 <_vsnprintf+0x88a> +10003072: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10003076: d00d beq.n 10003094 <_vsnprintf+0x9c8> +10003078: f013 0402 ands.w r4, r3, #2 +1000307c: d012 beq.n 100030a4 <_vsnprintf+0x9d8> +1000307e: 4604 mov r4, r0 +10003080: 4646 mov r6, r8 +10003082: e5ec b.n 10002c5e <_vsnprintf+0x592> +10003084: 270a movs r7, #10 +10003086: 4663 mov r3, ip +10003088: 46bc mov ip, r7 +1000308a: e56c b.n 10002b66 <_vsnprintf+0x49a> +1000308c: ab12 add r3, sp, #72 @ 0x48 +1000308e: 2000 movs r0, #0 +10003090: 930b str r3, [sp, #44] @ 0x2c +10003092: e69d b.n 10002dd0 <_vsnprintf+0x704> +10003094: f013 0302 ands.w r3, r3, #2 +10003098: f47f ade0 bne.w 10002c5c <_vsnprintf+0x590> +1000309c: 2d00 cmp r5, #0 +1000309e: f47f af13 bne.w 10002ec8 <_vsnprintf+0x7fc> +100030a2: e49a b.n 100029da <_vsnprintf+0x30e> +100030a4: 2d00 cmp r5, #0 +100030a6: f47f af0d bne.w 10002ec4 <_vsnprintf+0x7f8> +100030aa: e496 b.n 100029da <_vsnprintf+0x30e> +100030ac: cccccccd .word 0xcccccccd + +100030b0 : +100030b0: b570 push {r4, r5, r6, lr} +100030b2: 4694 mov ip, r2 +100030b4: 461e mov r6, r3 +100030b6: 4605 mov r5, r0 +100030b8: 460c mov r4, r1 +100030ba: b084 sub sp, #16 +100030bc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100030c0: 4663 mov r3, ip +100030c2: a902 add r1, sp, #8 +100030c4: 9600 str r6, [sp, #0] +100030c6: 4803 ldr r0, [pc, #12] @ (100030d4 ) +100030c8: e9cd 5402 strd r5, r4, [sp, #8] +100030cc: f7ff fafe bl 100026cc <_vsnprintf> +100030d0: b004 add sp, #16 +100030d2: bd70 pop {r4, r5, r6, pc} +100030d4: 10001c8d .word 0x10001c8d + +100030d8 : +100030d8: b510 push {r4, lr} +100030da: 4b09 ldr r3, [pc, #36] @ (10003100 ) +100030dc: b084 sub sp, #16 +100030de: 681c ldr r4, [r3, #0] +100030e0: b14c cbz r4, 100030f6 +100030e2: 4603 mov r3, r0 +100030e4: 9100 str r1, [sp, #0] +100030e6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100030ea: a903 add r1, sp, #12 +100030ec: 4805 ldr r0, [pc, #20] @ (10003104 ) +100030ee: 47a0 blx r4 +100030f0: 2001 movs r0, #1 +100030f2: b004 add sp, #16 +100030f4: bd10 pop {r4, pc} +100030f6: f000 f97d bl 100033f4 <__wrap_puts> +100030fa: 4620 mov r0, r4 +100030fc: b004 add sp, #16 +100030fe: bd10 pop {r4, pc} +10003100: 20000810 .word 0x20000810 +10003104: 10001c85 .word 0x10001c85 + +10003108 <_exit>: +10003108: be00 bkpt 0x0000 +1000310a: e7fd b.n 10003108 <_exit> + +1000310c : +1000310c: b508 push {r3, lr} +1000310e: f7ff fffb bl 10003108 <_exit> +10003112: bf00 nop + +10003114 : +10003114: b538 push {r3, r4, r5, lr} +10003116: 4c06 ldr r4, [pc, #24] @ (10003130 ) +10003118: 4d06 ldr r5, [pc, #24] @ (10003134 ) +1000311a: f7fe fa07 bl 1000152c +1000311e: 42ac cmp r4, r5 +10003120: d204 bcs.n 1000312c +10003122: f854 3b04 ldr.w r3, [r4], #4 +10003126: 4798 blx r3 +10003128: 42ac cmp r4, r5 +1000312a: d3fa bcc.n 10003122 +1000312c: bd38 pop {r3, r4, r5, pc} +1000312e: bf00 nop +10003130: 100038a8 .word 0x100038a8 +10003134: 100038ac .word 0x100038ac + +10003138 : +10003138: 6803 ldr r3, [r0, #0] +1000313a: 4608 mov r0, r1 +1000313c: 4611 mov r1, r2 +1000313e: 4718 bx r3 + +10003140 : +10003140: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003144: 4615 mov r5, r2 +10003146: 7d42 ldrb r2, [r0, #21] +10003148: 4607 mov r7, r0 +1000314a: 4688 mov r8, r1 +1000314c: 2a00 cmp r2, #0 +1000314e: d046 beq.n 100031de +10003150: 2d00 cmp r5, #0 +10003152: dd1d ble.n 10003190 +10003154: 780b ldrb r3, [r1, #0] +10003156: 2b0a cmp r3, #10 +10003158: d023 beq.n 100031a2 +1000315a: 2d01 cmp r5, #1 +1000315c: f04f 0c00 mov.w ip, #0 +10003160: d018 beq.n 10003194 +10003162: 4646 mov r6, r8 +10003164: 2401 movs r4, #1 +10003166: f816 2f01 ldrb.w r2, [r6, #1]! +1000316a: 4621 mov r1, r4 +1000316c: 2a0a cmp r2, #10 +1000316e: f104 0401 add.w r4, r4, #1 +10003172: d022 beq.n 100031ba +10003174: 42a5 cmp r5, r4 +10003176: d1f6 bne.n 10003166 +10003178: 4565 cmp r5, ip +1000317a: dc0b bgt.n 10003194 +1000317c: eb08 0305 add.w r3, r8, r5 +10003180: f813 3c01 ldrb.w r3, [r3, #-1] +10003184: f1a3 030d sub.w r3, r3, #13 +10003188: fab3 f383 clz r3, r3 +1000318c: 095b lsrs r3, r3, #5 +1000318e: 753b strb r3, [r7, #20] +10003190: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003194: 683b ldr r3, [r7, #0] +10003196: eba5 010c sub.w r1, r5, ip +1000319a: eb08 000c add.w r0, r8, ip +1000319e: 4798 blx r3 +100031a0: e7ec b.n 1000317c +100031a2: 7d03 ldrb r3, [r0, #20] +100031a4: 2b00 cmp r3, #0 +100031a6: d1d8 bne.n 1000315a +100031a8: 6803 ldr r3, [r0, #0] +100031aa: 2102 movs r1, #2 +100031ac: 480f ldr r0, [pc, #60] @ (100031ec ) +100031ae: 4798 blx r3 +100031b0: 2d01 cmp r5, #1 +100031b2: d0e3 beq.n 1000317c +100031b4: f04f 0c01 mov.w ip, #1 +100031b8: e7d3 b.n 10003162 +100031ba: f816 3c01 ldrb.w r3, [r6, #-1] +100031be: 2b0d cmp r3, #13 +100031c0: d0d8 beq.n 10003174 +100031c2: 458c cmp ip, r1 +100031c4: eb08 000c add.w r0, r8, ip +100031c8: eba1 010c sub.w r1, r1, ip +100031cc: da01 bge.n 100031d2 +100031ce: 683b ldr r3, [r7, #0] +100031d0: 4798 blx r3 +100031d2: 2102 movs r1, #2 +100031d4: 4805 ldr r0, [pc, #20] @ (100031ec ) +100031d6: 683b ldr r3, [r7, #0] +100031d8: 4798 blx r3 +100031da: 46a4 mov ip, r4 +100031dc: e7ca b.n 10003174 +100031de: 4629 mov r1, r5 +100031e0: 4640 mov r0, r8 +100031e2: 683b ldr r3, [r7, #0] +100031e4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100031e8: 4718 bx r3 +100031ea: bf00 nop +100031ec: 10003a70 .word 0x10003a70 + +100031f0 : +100031f0: 680b ldr r3, [r1, #0] +100031f2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100031f6: 2b80 cmp r3, #128 @ 0x80 +100031f8: 460d mov r5, r1 +100031fa: 4606 mov r6, r0 +100031fc: d005 beq.n 1000320a +100031fe: 1c5a adds r2, r3, #1 +10003200: 442b add r3, r5 +10003202: 602a str r2, [r5, #0] +10003204: 711e strb r6, [r3, #4] +10003206: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +1000320a: 4b0f ldr r3, [pc, #60] @ (10003248 ) +1000320c: 681c ldr r4, [r3, #0] +1000320e: b1a4 cbz r4, 1000323a +10003210: 4f0e ldr r7, [pc, #56] @ (1000324c ) +10003212: f101 0804 add.w r8, r1, #4 +10003216: e001 b.n 1000321c +10003218: 6924 ldr r4, [r4, #16] +1000321a: b174 cbz r4, 1000323a +1000321c: 6823 ldr r3, [r4, #0] +1000321e: 2b00 cmp r3, #0 +10003220: d0fa beq.n 10003218 +10003222: 683b ldr r3, [r7, #0] +10003224: b10b cbz r3, 1000322a +10003226: 42a3 cmp r3, r4 +10003228: d1f6 bne.n 10003218 +1000322a: 4620 mov r0, r4 +1000322c: 4641 mov r1, r8 +1000322e: 682a ldr r2, [r5, #0] +10003230: f7ff ff86 bl 10003140 +10003234: 6924 ldr r4, [r4, #16] +10003236: 2c00 cmp r4, #0 +10003238: d1f0 bne.n 1000321c +1000323a: 2300 movs r3, #0 +1000323c: 2201 movs r2, #1 +1000323e: 442b add r3, r5 +10003240: 602a str r2, [r5, #0] +10003242: 711e strb r6, [r3, #4] +10003244: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003248: 20000804 .word 0x20000804 +1000324c: 20000808 .word 0x20000808 + +10003250 : +10003250: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10003254: b082 sub sp, #8 +10003256: 460d mov r5, r1 +10003258: 4691 mov r9, r2 +1000325a: 461c mov r4, r3 +1000325c: 4606 mov r6, r0 +1000325e: f7fd ff95 bl 1000118c +10003262: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003266: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1000326a: 4a2e ldr r2, [pc, #184] @ (10003324 ) +1000326c: 1882 adds r2, r0, r2 +1000326e: f141 0300 adc.w r3, r1, #0 +10003272: 4594 cmp ip, r2 +10003274: eb77 0103 sbcs.w r1, r7, r3 +10003278: bf3c itt cc +1000327a: 4662 movcc r2, ip +1000327c: 463b movcc r3, r7 +1000327e: 482a ldr r0, [pc, #168] @ (10003328 ) +10003280: f000 faee bl 10003860 <__mutex_try_enter_block_until_veneer> +10003284: 1c6b adds r3, r5, #1 +10003286: 4680 mov r8, r0 +10003288: d040 beq.n 1000330c +1000328a: b30c cbz r4, 100032d0 +1000328c: 4f27 ldr r7, [pc, #156] @ (1000332c ) +1000328e: 4b28 ldr r3, [pc, #160] @ (10003330 ) +10003290: 681c ldr r4, [r3, #0] +10003292: b1b4 cbz r4, 100032c2 +10003294: f1b9 0f00 cmp.w r9, #0 +10003298: d11c bne.n 100032d4 +1000329a: f8df 909c ldr.w r9, [pc, #156] @ 10003338 +1000329e: e001 b.n 100032a4 +100032a0: 6924 ldr r4, [r4, #16] +100032a2: b174 cbz r4, 100032c2 +100032a4: 6823 ldr r3, [r4, #0] +100032a6: 2b00 cmp r3, #0 +100032a8: d0fa beq.n 100032a0 +100032aa: f8d9 3000 ldr.w r3, [r9] +100032ae: b10b cbz r3, 100032b4 +100032b0: 429c cmp r4, r3 +100032b2: d1f5 bne.n 100032a0 +100032b4: 4620 mov r0, r4 +100032b6: 462a mov r2, r5 +100032b8: 4631 mov r1, r6 +100032ba: 47b8 blx r7 +100032bc: 6924 ldr r4, [r4, #16] +100032be: 2c00 cmp r4, #0 +100032c0: d1f0 bne.n 100032a4 +100032c2: f1b8 0f00 cmp.w r8, #0 +100032c6: d126 bne.n 10003316 +100032c8: 4628 mov r0, r5 +100032ca: b002 add sp, #8 +100032cc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100032d0: 4f18 ldr r7, [pc, #96] @ (10003334 ) +100032d2: e7dc b.n 1000328e +100032d4: f04f 0a0a mov.w sl, #10 +100032d8: f8df 905c ldr.w r9, [pc, #92] @ 10003338 +100032dc: e002 b.n 100032e4 +100032de: 6924 ldr r4, [r4, #16] +100032e0: 2c00 cmp r4, #0 +100032e2: d0ee beq.n 100032c2 +100032e4: 6823 ldr r3, [r4, #0] +100032e6: 2b00 cmp r3, #0 +100032e8: d0f9 beq.n 100032de +100032ea: f8d9 3000 ldr.w r3, [r9] +100032ee: b10b cbz r3, 100032f4 +100032f0: 42a3 cmp r3, r4 +100032f2: d1f4 bne.n 100032de +100032f4: 462a mov r2, r5 +100032f6: 4631 mov r1, r6 +100032f8: 4620 mov r0, r4 +100032fa: 47b8 blx r7 +100032fc: 2201 movs r2, #1 +100032fe: 4620 mov r0, r4 +10003300: f10d 0107 add.w r1, sp, #7 +10003304: f88d a007 strb.w sl, [sp, #7] +10003308: 47b8 blx r7 +1000330a: e7e8 b.n 100032de +1000330c: 4630 mov r0, r6 +1000330e: f000 fa6f bl 100037f0 +10003312: 4605 mov r5, r0 +10003314: e7b9 b.n 1000328a +10003316: 4804 ldr r0, [pc, #16] @ (10003328 ) +10003318: f000 fa9e bl 10003858 <__mutex_exit_veneer> +1000331c: 4628 mov r0, r5 +1000331e: b002 add sp, #8 +10003320: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003324: 000f4240 .word 0x000f4240 +10003328: 20000624 .word 0x20000624 +1000332c: 10003141 .word 0x10003141 +10003330: 20000804 .word 0x20000804 +10003334: 10003139 .word 0x10003139 +10003338: 20000808 .word 0x20000808 + +1000333c : +1000333c: 4a08 ldr r2, [pc, #32] @ (10003360 ) +1000333e: 6813 ldr r3, [r2, #0] +10003340: b923 cbnz r3, 1000334c +10003342: e00a b.n 1000335a +10003344: f103 0210 add.w r2, r3, #16 +10003348: 691b ldr r3, [r3, #16] +1000334a: b133 cbz r3, 1000335a +1000334c: 4283 cmp r3, r0 +1000334e: d1f9 bne.n 10003344 +10003350: b929 cbnz r1, 1000335e +10003352: 6918 ldr r0, [r3, #16] +10003354: 6010 str r0, [r2, #0] +10003356: 6119 str r1, [r3, #16] +10003358: 4770 bx lr +1000335a: b101 cbz r1, 1000335e +1000335c: 6010 str r0, [r2, #0] +1000335e: 4770 bx lr +10003360: 20000804 .word 0x20000804 + +10003364 : +10003364: b508 push {r3, lr} +10003366: f000 f9a3 bl 100036b0 +1000336a: 2001 movs r0, #1 +1000336c: bd08 pop {r3, pc} +1000336e: bf00 nop + +10003370 <__wrap_putchar>: +10003370: b5f0 push {r4, r5, r6, r7, lr} +10003372: b083 sub sp, #12 +10003374: 4606 mov r6, r0 +10003376: f88d 0007 strb.w r0, [sp, #7] +1000337a: f7fd ff07 bl 1000118c +1000337e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10003382: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10003386: 4a17 ldr r2, [pc, #92] @ (100033e4 <__wrap_putchar+0x74>) +10003388: 1882 adds r2, r0, r2 +1000338a: f141 0300 adc.w r3, r1, #0 +1000338e: 4295 cmp r5, r2 +10003390: eb74 0103 sbcs.w r1, r4, r3 +10003394: bf3c itt cc +10003396: 4623 movcc r3, r4 +10003398: 462a movcc r2, r5 +1000339a: 4813 ldr r0, [pc, #76] @ (100033e8 <__wrap_putchar+0x78>) +1000339c: f000 fa60 bl 10003860 <__mutex_try_enter_block_until_veneer> +100033a0: 4b12 ldr r3, [pc, #72] @ (100033ec <__wrap_putchar+0x7c>) +100033a2: 4607 mov r7, r0 +100033a4: 681c ldr r4, [r3, #0] +100033a6: b19c cbz r4, 100033d0 <__wrap_putchar+0x60> +100033a8: 4d11 ldr r5, [pc, #68] @ (100033f0 <__wrap_putchar+0x80>) +100033aa: e001 b.n 100033b0 <__wrap_putchar+0x40> +100033ac: 6924 ldr r4, [r4, #16] +100033ae: b17c cbz r4, 100033d0 <__wrap_putchar+0x60> +100033b0: 6823 ldr r3, [r4, #0] +100033b2: 2b00 cmp r3, #0 +100033b4: d0fa beq.n 100033ac <__wrap_putchar+0x3c> +100033b6: 682b ldr r3, [r5, #0] +100033b8: b10b cbz r3, 100033be <__wrap_putchar+0x4e> +100033ba: 429c cmp r4, r3 +100033bc: d1f6 bne.n 100033ac <__wrap_putchar+0x3c> +100033be: 4620 mov r0, r4 +100033c0: 2201 movs r2, #1 +100033c2: f10d 0107 add.w r1, sp, #7 +100033c6: f7ff febb bl 10003140 +100033ca: 6924 ldr r4, [r4, #16] +100033cc: 2c00 cmp r4, #0 +100033ce: d1ef bne.n 100033b0 <__wrap_putchar+0x40> +100033d0: b917 cbnz r7, 100033d8 <__wrap_putchar+0x68> +100033d2: 4630 mov r0, r6 +100033d4: b003 add sp, #12 +100033d6: bdf0 pop {r4, r5, r6, r7, pc} +100033d8: 4803 ldr r0, [pc, #12] @ (100033e8 <__wrap_putchar+0x78>) +100033da: f000 fa3d bl 10003858 <__mutex_exit_veneer> +100033de: 4630 mov r0, r6 +100033e0: b003 add sp, #12 +100033e2: bdf0 pop {r4, r5, r6, r7, pc} +100033e4: 000f4240 .word 0x000f4240 +100033e8: 20000624 .word 0x20000624 +100033ec: 20000804 .word 0x20000804 +100033f0: 20000808 .word 0x20000808 + +100033f4 <__wrap_puts>: +100033f4: b538 push {r3, r4, r5, lr} +100033f6: 4604 mov r4, r0 +100033f8: f000 f9fa bl 100037f0 +100033fc: 2301 movs r3, #1 +100033fe: 4605 mov r5, r0 +10003400: 461a mov r2, r3 +10003402: 4620 mov r0, r4 +10003404: 4629 mov r1, r5 +10003406: f7ff ff23 bl 10003250 +1000340a: 4b08 ldr r3, [pc, #32] @ (1000342c <__wrap_puts+0x38>) +1000340c: 681c ldr r4, [r3, #0] +1000340e: b12c cbz r4, 1000341c <__wrap_puts+0x28> +10003410: 6863 ldr r3, [r4, #4] +10003412: b12b cbz r3, 10003420 <__wrap_puts+0x2c> +10003414: 4798 blx r3 +10003416: 6924 ldr r4, [r4, #16] +10003418: 2c00 cmp r4, #0 +1000341a: d1f9 bne.n 10003410 <__wrap_puts+0x1c> +1000341c: 4628 mov r0, r5 +1000341e: bd38 pop {r3, r4, r5, pc} +10003420: 6924 ldr r4, [r4, #16] +10003422: 2c00 cmp r4, #0 +10003424: d1f4 bne.n 10003410 <__wrap_puts+0x1c> +10003426: 4628 mov r0, r5 +10003428: bd38 pop {r3, r4, r5, pc} +1000342a: bf00 nop +1000342c: 20000804 .word 0x20000804 + +10003430 <__wrap_vprintf>: +10003430: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003434: b0a2 sub sp, #136 @ 0x88 +10003436: 4604 mov r4, r0 +10003438: 460d mov r5, r1 +1000343a: f7fd fea7 bl 1000118c +1000343e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10003442: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003446: 4a26 ldr r2, [pc, #152] @ (100034e0 <__wrap_vprintf+0xb0>) +10003448: f8df 80a4 ldr.w r8, [pc, #164] @ 100034f0 <__wrap_vprintf+0xc0> +1000344c: 1882 adds r2, r0, r2 +1000344e: f141 0300 adc.w r3, r1, #0 +10003452: 4297 cmp r7, r2 +10003454: eb76 0103 sbcs.w r1, r6, r3 +10003458: bf3c itt cc +1000345a: 463a movcc r2, r7 +1000345c: 4633 movcc r3, r6 +1000345e: 4821 ldr r0, [pc, #132] @ (100034e4 <__wrap_vprintf+0xb4>) +10003460: f000 f9fe bl 10003860 <__mutex_try_enter_block_until_veneer> +10003464: 2700 movs r7, #0 +10003466: 462b mov r3, r5 +10003468: 4622 mov r2, r4 +1000346a: 4606 mov r6, r0 +1000346c: a901 add r1, sp, #4 +1000346e: 481e ldr r0, [pc, #120] @ (100034e8 <__wrap_vprintf+0xb8>) +10003470: 9701 str r7, [sp, #4] +10003472: f7ff fe1d bl 100030b0 +10003476: 9b01 ldr r3, [sp, #4] +10003478: 4605 mov r5, r0 +1000347a: f8d8 4000 ldr.w r4, [r8] +1000347e: b1c3 cbz r3, 100034b2 <__wrap_vprintf+0x82> +10003480: 2c00 cmp r4, #0 +10003482: d02b beq.n 100034dc <__wrap_vprintf+0xac> +10003484: 4f19 ldr r7, [pc, #100] @ (100034ec <__wrap_vprintf+0xbc>) +10003486: e001 b.n 1000348c <__wrap_vprintf+0x5c> +10003488: 6924 ldr r4, [r4, #16] +1000348a: b174 cbz r4, 100034aa <__wrap_vprintf+0x7a> +1000348c: 6823 ldr r3, [r4, #0] +1000348e: 2b00 cmp r3, #0 +10003490: d0fa beq.n 10003488 <__wrap_vprintf+0x58> +10003492: 683b ldr r3, [r7, #0] +10003494: b10b cbz r3, 1000349a <__wrap_vprintf+0x6a> +10003496: 42a3 cmp r3, r4 +10003498: d1f6 bne.n 10003488 <__wrap_vprintf+0x58> +1000349a: 4620 mov r0, r4 +1000349c: 9a01 ldr r2, [sp, #4] +1000349e: a902 add r1, sp, #8 +100034a0: f7ff fe4e bl 10003140 +100034a4: 6924 ldr r4, [r4, #16] +100034a6: 2c00 cmp r4, #0 +100034a8: d1f0 bne.n 1000348c <__wrap_vprintf+0x5c> +100034aa: 2300 movs r3, #0 +100034ac: f8d8 4000 ldr.w r4, [r8] +100034b0: 9301 str r3, [sp, #4] +100034b2: b12c cbz r4, 100034c0 <__wrap_vprintf+0x90> +100034b4: 6863 ldr r3, [r4, #4] +100034b6: b143 cbz r3, 100034ca <__wrap_vprintf+0x9a> +100034b8: 4798 blx r3 +100034ba: 6924 ldr r4, [r4, #16] +100034bc: 2c00 cmp r4, #0 +100034be: d1f9 bne.n 100034b4 <__wrap_vprintf+0x84> +100034c0: b92e cbnz r6, 100034ce <__wrap_vprintf+0x9e> +100034c2: 4628 mov r0, r5 +100034c4: b022 add sp, #136 @ 0x88 +100034c6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100034ca: 6924 ldr r4, [r4, #16] +100034cc: e7f1 b.n 100034b2 <__wrap_vprintf+0x82> +100034ce: 4805 ldr r0, [pc, #20] @ (100034e4 <__wrap_vprintf+0xb4>) +100034d0: f000 f9c2 bl 10003858 <__mutex_exit_veneer> +100034d4: 4628 mov r0, r5 +100034d6: b022 add sp, #136 @ 0x88 +100034d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100034dc: 9401 str r4, [sp, #4] +100034de: e7ef b.n 100034c0 <__wrap_vprintf+0x90> +100034e0: 000f4240 .word 0x000f4240 +100034e4: 20000624 .word 0x20000624 +100034e8: 100031f1 .word 0x100031f1 +100034ec: 20000808 .word 0x20000808 +100034f0: 20000804 .word 0x20000804 + +100034f4 <__wrap_printf>: +100034f4: b40f push {r0, r1, r2, r3} +100034f6: b500 push {lr} +100034f8: b083 sub sp, #12 +100034fa: a904 add r1, sp, #16 +100034fc: f851 0b04 ldr.w r0, [r1], #4 +10003500: 9101 str r1, [sp, #4] +10003502: f7ff ff95 bl 10003430 <__wrap_vprintf> +10003506: b003 add sp, #12 +10003508: f85d eb04 ldr.w lr, [sp], #4 +1000350c: b004 add sp, #16 +1000350e: 4770 bx lr + +10003510 : +10003510: f1b1 0c00 subs.w ip, r1, #0 +10003514: dd1d ble.n 10003552 +10003516: 4a0f ldr r2, [pc, #60] @ (10003554 ) +10003518: 4b0f ldr r3, [pc, #60] @ (10003558 ) +1000351a: 6812 ldr r2, [r2, #0] +1000351c: b530 push {r4, r5, lr} +1000351e: 1ad3 subs r3, r2, r3 +10003520: fab3 f383 clz r3, r3 +10003524: 240d movs r4, #13 +10003526: 4d0d ldr r5, [pc, #52] @ (1000355c ) +10003528: 095b lsrs r3, r3, #5 +1000352a: 1e41 subs r1, r0, #1 +1000352c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003530: 448c add ip, r1 +10003532: f811 0f01 ldrb.w r0, [r1, #1]! +10003536: 4586 cmp lr, r0 +10003538: d006 beq.n 10003548 +1000353a: 6993 ldr r3, [r2, #24] +1000353c: 069b lsls r3, r3, #26 +1000353e: d4fc bmi.n 1000353a +10003540: 4561 cmp r1, ip +10003542: 6010 str r0, [r2, #0] +10003544: d1f5 bne.n 10003532 +10003546: bd30 pop {r4, r5, pc} +10003548: 6993 ldr r3, [r2, #24] +1000354a: 069d lsls r5, r3, #26 +1000354c: d4fc bmi.n 10003548 +1000354e: 6014 str r4, [r2, #0] +10003550: e7f3 b.n 1000353a +10003552: 4770 bx lr +10003554: 20000854 .word 0x20000854 +10003558: 40078000 .word 0x40078000 +1000355c: 20000850 .word 0x20000850 + +10003560 : +10003560: 4b22 ldr r3, [pc, #136] @ (100035ec ) +10003562: f1b1 0c00 subs.w ip, r1, #0 +10003566: b410 push {r4} +10003568: 681c ldr r4, [r3, #0] +1000356a: dd2e ble.n 100035ca +1000356c: 4603 mov r3, r0 +1000356e: 2000 movs r0, #0 +10003570: 4a1f ldr r2, [pc, #124] @ (100035f0 ) +10003572: 1e59 subs r1, r3, #1 +10003574: 6812 ldr r2, [r2, #0] +10003576: 6993 ldr r3, [r2, #24] +10003578: 06db lsls r3, r3, #27 +1000357a: d417 bmi.n 100035ac +1000357c: 3001 adds r0, #1 +1000357e: 6993 ldr r3, [r2, #24] +10003580: 06db lsls r3, r3, #27 +10003582: d4fc bmi.n 1000357e +10003584: 6813 ldr r3, [r2, #0] +10003586: 4584 cmp ip, r0 +10003588: f801 3f01 strb.w r3, [r1, #1]! +1000358c: d1f3 bne.n 10003576 +1000358e: b14c cbz r4, 100035a4 +10003590: 2150 movs r1, #80 @ 0x50 +10003592: 4613 mov r3, r2 +10003594: 6391 str r1, [r2, #56] @ 0x38 +10003596: f853 2f34 ldr.w r2, [r3, #52]! +1000359a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000359e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035a2: 601a str r2, [r3, #0] +100035a4: 4660 mov r0, ip +100035a6: f85d 4b04 ldr.w r4, [sp], #4 +100035aa: 4770 bx lr +100035ac: b14c cbz r4, 100035c2 +100035ae: 2150 movs r1, #80 @ 0x50 +100035b0: 4613 mov r3, r2 +100035b2: 6391 str r1, [r2, #56] @ 0x38 +100035b4: f853 2f34 ldr.w r2, [r3, #52]! +100035b8: f002 0238 and.w r2, r2, #56 @ 0x38 +100035bc: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035c0: 601a str r2, [r3, #0] +100035c2: b178 cbz r0, 100035e4 +100035c4: f85d 4b04 ldr.w r4, [sp], #4 +100035c8: 4770 bx lr +100035ca: b15c cbz r4, 100035e4 +100035cc: 4b08 ldr r3, [pc, #32] @ (100035f0 ) +100035ce: 2150 movs r1, #80 @ 0x50 +100035d0: 681a ldr r2, [r3, #0] +100035d2: 4613 mov r3, r2 +100035d4: 6391 str r1, [r2, #56] @ 0x38 +100035d6: f853 2f34 ldr.w r2, [r3, #52]! +100035da: f002 0238 and.w r2, r2, #56 @ 0x38 +100035de: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035e2: 601a str r2, [r3, #0] +100035e4: f06f 0002 mvn.w r0, #2 +100035e8: e7dd b.n 100035a6 +100035ea: bf00 nop +100035ec: 200007d0 .word 0x200007d0 +100035f0: 20000854 .word 0x20000854 + +100035f4 : +100035f4: 4b05 ldr r3, [pc, #20] @ (1000360c ) +100035f6: 681b ldr r3, [r3, #0] +100035f8: b133 cbz r3, 10003608 +100035fa: 2100 movs r1, #0 +100035fc: 4a04 ldr r2, [pc, #16] @ (10003610 ) +100035fe: 4805 ldr r0, [pc, #20] @ (10003614 ) +10003600: 6812 ldr r2, [r2, #0] +10003602: 6800 ldr r0, [r0, #0] +10003604: 6391 str r1, [r2, #56] @ 0x38 +10003606: 4718 bx r3 +10003608: 4770 bx lr +1000360a: bf00 nop +1000360c: 200007d0 .word 0x200007d0 +10003610: 20000854 .word 0x20000854 +10003614: 200007d4 .word 0x200007d4 + +10003618 : +10003618: 4b02 ldr r3, [pc, #8] @ (10003624 ) +1000361a: 681a ldr r2, [r3, #0] +1000361c: 6993 ldr r3, [r2, #24] +1000361e: 071b lsls r3, r3, #28 +10003620: d4fc bmi.n 1000361c +10003622: 4770 bx lr +10003624: 20000854 .word 0x20000854 + +10003628 : +10003628: b5f8 push {r3, r4, r5, r6, r7, lr} +1000362a: 4f1c ldr r7, [pc, #112] @ (1000369c ) +1000362c: 4d1c ldr r5, [pc, #112] @ (100036a0 ) +1000362e: 683a ldr r2, [r7, #0] +10003630: 4e1c ldr r6, [pc, #112] @ (100036a4 ) +10003632: 42aa cmp r2, r5 +10003634: bf14 ite ne +10003636: 2521 movne r5, #33 @ 0x21 +10003638: 2522 moveq r5, #34 @ 0x22 +1000363a: 4604 mov r4, r0 +1000363c: f8d6 c000 ldr.w ip, [r6] +10003640: b118 cbz r0, 1000364a +10003642: f1bc 0f00 cmp.w ip, #0 +10003646: d010 beq.n 1000366a +10003648: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000364a: f1bc 0f00 cmp.w ip, #0 +1000364e: d0fb beq.n 10003648 +10003650: 4601 mov r1, r0 +10003652: 6390 str r0, [r2, #56] @ 0x38 +10003654: 4628 mov r0, r5 +10003656: f7fd f821 bl 1000069c +1000365a: 4628 mov r0, r5 +1000365c: 4912 ldr r1, [pc, #72] @ (100036a8 ) +1000365e: f7fd f863 bl 10000728 +10003662: 4b12 ldr r3, [pc, #72] @ (100036ac ) +10003664: 6034 str r4, [r6, #0] +10003666: 601c str r4, [r3, #0] +10003668: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000366a: 460b mov r3, r1 +1000366c: 4a0f ldr r2, [pc, #60] @ (100036ac ) +1000366e: 490e ldr r1, [pc, #56] @ (100036a8 ) +10003670: 6030 str r0, [r6, #0] +10003672: 4628 mov r0, r5 +10003674: 6013 str r3, [r2, #0] +10003676: f7fd f827 bl 100006c8 +1000367a: 2101 movs r1, #1 +1000367c: 4628 mov r0, r5 +1000367e: f7fd f80d bl 1000069c +10003682: 683a ldr r2, [r7, #0] +10003684: 2150 movs r1, #80 @ 0x50 +10003686: 4613 mov r3, r2 +10003688: 6391 str r1, [r2, #56] @ 0x38 +1000368a: f853 2f34 ldr.w r2, [r3, #52]! +1000368e: f002 0238 and.w r2, r2, #56 @ 0x38 +10003692: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003696: 601a str r2, [r3, #0] +10003698: bdf8 pop {r3, r4, r5, r6, r7, pc} +1000369a: bf00 nop +1000369c: 20000854 .word 0x20000854 +100036a0: 40078000 .word 0x40078000 +100036a4: 200007d0 .word 0x200007d0 +100036a8: 100035f5 .word 0x100035f5 +100036ac: 200007d4 .word 0x200007d4 + +100036b0 : +100036b0: b510 push {r4, lr} +100036b2: 490e ldr r1, [pc, #56] @ (100036ec ) +100036b4: 4c0e ldr r4, [pc, #56] @ (100036f0 ) +100036b6: 480f ldr r0, [pc, #60] @ (100036f4 ) +100036b8: 4a0f ldr r2, [pc, #60] @ (100036f8 ) +100036ba: 4b10 ldr r3, [pc, #64] @ (100036fc ) +100036bc: 7800 ldrb r0, [r0, #0] +100036be: 6021 str r1, [r4, #0] +100036c0: 2000 movs r0, #0 +100036c2: 2102 movs r1, #2 +100036c4: 7812 ldrb r2, [r2, #0] +100036c6: 781b ldrb r3, [r3, #0] +100036c8: f7fc ff0e bl 100004e8 +100036cc: 2102 movs r1, #2 +100036ce: 2001 movs r0, #1 +100036d0: f7fc ff0a bl 100004e8 +100036d4: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100036d8: 6820 ldr r0, [r4, #0] +100036da: f7fd fda1 bl 10001220 +100036de: e8bd 4010 ldmia.w sp!, {r4, lr} +100036e2: 2101 movs r1, #1 +100036e4: 4806 ldr r0, [pc, #24] @ (10003700 ) +100036e6: f7ff be29 b.w 1000333c +100036ea: bf00 nop +100036ec: 40070000 .word 0x40070000 +100036f0: 20000854 .word 0x20000854 +100036f4: 10003ac0 .word 0x10003ac0 +100036f8: 10003abc .word 0x10003abc +100036fc: 10003ab8 .word 0x10003ab8 +10003700: 2000060c .word 0x2000060c + +10003704 : +10003704: 4684 mov ip, r0 +10003706: ea41 0300 orr.w r3, r1, r0 +1000370a: f013 0303 ands.w r3, r3, #3 +1000370e: d149 bne.n 100037a4 +10003710: 3a40 subs r2, #64 @ 0x40 +10003712: d323 bcc.n 1000375c +10003714: 680b ldr r3, [r1, #0] +10003716: 6003 str r3, [r0, #0] +10003718: 684b ldr r3, [r1, #4] +1000371a: 6043 str r3, [r0, #4] +1000371c: 688b ldr r3, [r1, #8] +1000371e: 6083 str r3, [r0, #8] +10003720: 68cb ldr r3, [r1, #12] +10003722: 60c3 str r3, [r0, #12] +10003724: 690b ldr r3, [r1, #16] +10003726: 6103 str r3, [r0, #16] +10003728: 694b ldr r3, [r1, #20] +1000372a: 6143 str r3, [r0, #20] +1000372c: 698b ldr r3, [r1, #24] +1000372e: 6183 str r3, [r0, #24] +10003730: 69cb ldr r3, [r1, #28] +10003732: 61c3 str r3, [r0, #28] +10003734: 6a0b ldr r3, [r1, #32] +10003736: 6203 str r3, [r0, #32] +10003738: 6a4b ldr r3, [r1, #36] @ 0x24 +1000373a: 6243 str r3, [r0, #36] @ 0x24 +1000373c: 6a8b ldr r3, [r1, #40] @ 0x28 +1000373e: 6283 str r3, [r0, #40] @ 0x28 +10003740: 6acb ldr r3, [r1, #44] @ 0x2c +10003742: 62c3 str r3, [r0, #44] @ 0x2c +10003744: 6b0b ldr r3, [r1, #48] @ 0x30 +10003746: 6303 str r3, [r0, #48] @ 0x30 +10003748: 6b4b ldr r3, [r1, #52] @ 0x34 +1000374a: 6343 str r3, [r0, #52] @ 0x34 +1000374c: 6b8b ldr r3, [r1, #56] @ 0x38 +1000374e: 6383 str r3, [r0, #56] @ 0x38 +10003750: 6bcb ldr r3, [r1, #60] @ 0x3c +10003752: 63c3 str r3, [r0, #60] @ 0x3c +10003754: 3040 adds r0, #64 @ 0x40 +10003756: 3140 adds r1, #64 @ 0x40 +10003758: 3a40 subs r2, #64 @ 0x40 +1000375a: d2db bcs.n 10003714 +1000375c: 3230 adds r2, #48 @ 0x30 +1000375e: d30b bcc.n 10003778 +10003760: 680b ldr r3, [r1, #0] +10003762: 6003 str r3, [r0, #0] +10003764: 684b ldr r3, [r1, #4] +10003766: 6043 str r3, [r0, #4] +10003768: 688b ldr r3, [r1, #8] +1000376a: 6083 str r3, [r0, #8] +1000376c: 68cb ldr r3, [r1, #12] +1000376e: 60c3 str r3, [r0, #12] +10003770: 3010 adds r0, #16 +10003772: 3110 adds r1, #16 +10003774: 3a10 subs r2, #16 +10003776: d2f3 bcs.n 10003760 +10003778: 320c adds r2, #12 +1000377a: d305 bcc.n 10003788 +1000377c: f851 3b04 ldr.w r3, [r1], #4 +10003780: f840 3b04 str.w r3, [r0], #4 +10003784: 3a04 subs r2, #4 +10003786: d2f9 bcs.n 1000377c +10003788: 3204 adds r2, #4 +1000378a: d008 beq.n 1000379e +1000378c: 07d2 lsls r2, r2, #31 +1000378e: bf1c itt ne +10003790: f811 3b01 ldrbne.w r3, [r1], #1 +10003794: f800 3b01 strbne.w r3, [r0], #1 +10003798: d301 bcc.n 1000379e +1000379a: 880b ldrh r3, [r1, #0] +1000379c: 8003 strh r3, [r0, #0] +1000379e: 4660 mov r0, ip +100037a0: 4770 bx lr +100037a2: bf00 nop +100037a4: 2a08 cmp r2, #8 +100037a6: d313 bcc.n 100037d0 +100037a8: 078b lsls r3, r1, #30 +100037aa: d0b1 beq.n 10003710 +100037ac: f010 0303 ands.w r3, r0, #3 +100037b0: d0ae beq.n 10003710 +100037b2: f1c3 0304 rsb r3, r3, #4 +100037b6: 1ad2 subs r2, r2, r3 +100037b8: 07db lsls r3, r3, #31 +100037ba: bf1c itt ne +100037bc: f811 3b01 ldrbne.w r3, [r1], #1 +100037c0: f800 3b01 strbne.w r3, [r0], #1 +100037c4: d3a4 bcc.n 10003710 +100037c6: f831 3b02 ldrh.w r3, [r1], #2 +100037ca: f820 3b02 strh.w r3, [r0], #2 +100037ce: e79f b.n 10003710 +100037d0: 3a04 subs r2, #4 +100037d2: d3d9 bcc.n 10003788 +100037d4: 3a01 subs r2, #1 +100037d6: f811 3b01 ldrb.w r3, [r1], #1 +100037da: f800 3b01 strb.w r3, [r0], #1 +100037de: d2f9 bcs.n 100037d4 +100037e0: 780b ldrb r3, [r1, #0] +100037e2: 7003 strb r3, [r0, #0] +100037e4: 784b ldrb r3, [r1, #1] +100037e6: 7043 strb r3, [r0, #1] +100037e8: 788b ldrb r3, [r1, #2] +100037ea: 7083 strb r3, [r0, #2] +100037ec: 4660 mov r0, ip +100037ee: 4770 bx lr + +100037f0 : +100037f0: f020 0103 bic.w r1, r0, #3 +100037f4: f010 0003 ands.w r0, r0, #3 +100037f8: f1c0 0000 rsb r0, r0, #0 +100037fc: f851 3b04 ldr.w r3, [r1], #4 +10003800: f100 0c04 add.w ip, r0, #4 +10003804: ea4f 0ccc mov.w ip, ip, lsl #3 +10003808: f06f 0200 mvn.w r2, #0 +1000380c: bf1c itt ne +1000380e: fa22 f20c lsrne.w r2, r2, ip +10003812: 4313 orrne r3, r2 +10003814: f04f 0c01 mov.w ip, #1 +10003818: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +1000381c: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003820: eba3 020c sub.w r2, r3, ip +10003824: ea22 0203 bic.w r2, r2, r3 +10003828: ea12 12cc ands.w r2, r2, ip, lsl #7 +1000382c: bf04 itt eq +1000382e: f851 3b04 ldreq.w r3, [r1], #4 +10003832: 3004 addeq r0, #4 +10003834: d0f4 beq.n 10003820 +10003836: f1c2 0100 rsb r1, r2, #0 +1000383a: ea02 0201 and.w r2, r2, r1 +1000383e: fab2 f282 clz r2, r2 +10003842: f1c2 021f rsb r2, r2, #31 +10003846: eb00 00d2 add.w r0, r0, r2, lsr #3 +1000384a: 4770 bx lr + +1000384c <_fini>: +1000384c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000384e: bf00 nop + +10003850 <____aeabi_uldivmod_veneer>: +10003850: f85f f000 ldr.w pc, [pc] @ 10003854 <____aeabi_uldivmod_veneer+0x4> +10003854: 20000221 .word 0x20000221 + +10003858 <__mutex_exit_veneer>: +10003858: f85f f000 ldr.w pc, [pc] @ 1000385c <__mutex_exit_veneer+0x4> +1000385c: 200001e5 .word 0x200001e5 + +10003860 <__mutex_try_enter_block_until_veneer>: +10003860: f85f f000 ldr.w pc, [pc] @ 10003864 <__mutex_try_enter_block_until_veneer+0x4> +10003864: 2000017d .word 0x2000017d + +10003868 <__pre_init_runtime_init_bootrom_reset>: +10003868: 100015d9 .... + +1000386c <__pre_init_runtime_init_early_resets>: +1000386c: 1000154d M... + +10003870 <__pre_init_runtime_init_usb_power_down>: +10003870: 10001581 .... + +10003874 <__pre_init_runtime_init_clocks>: +10003874: 1000166d m... + +10003878 <__pre_init_runtime_init_post_clock_resets>: +10003878: 100015b9 .... + +1000387c <__pre_init_runtime_init_boot_locks_reset>: +1000387c: 100014d1 .... + +10003880 <__pre_init_runtime_init_spin_locks_reset>: +10003880: 10001601 .... + +10003884 <__pre_init_runtime_init_bootrom_locking_enable>: +10003884: 100014bd .... + +10003888 <__pre_init_runtime_init_mutex>: +10003888: 100009e5 .... + +1000388c <__pre_init_runtime_init_install_ram_vector_table>: +1000388c: 10001605 .... + +10003890 <__pre_init_runtime_init_default_alarm_pool>: +10003890: 10000d61 a... + +10003894 <__pre_init_first_per_core_initializer>: +10003894: 1000151d .... + +10003898 <__pre_init_runtime_init_per_core_bootrom_reset>: +10003898: 100015ed .... + +1000389c <__pre_init_runtime_init_per_core_enable_coprocessors>: +1000389c: 1000159d .... + +100038a0 <__pre_init_spinlock_set_extexclall>: +100038a0: 10000635 5... + +100038a4 <__pre_init_runtime_init_per_core_irq_priorities>: +100038a4: 1000065d ]... + +100038a8 <__frame_dummy_init_array_entry>: +100038a8: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10001085 .word 0x10001085 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 1000091d .word 0x1000091d + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003511 10003619 10003561 10003629 .5...6..a5..)6.. +2000061c: 00000000 00000100 ........ + +20000624 : + ... diff --git a/WEEK11/0x0023_structures/build/0x0023_structures.elf b/WEEK11/0x0023_structures/build/0x0023_structures.elf new file mode 100755 index 0000000..09f9f5d Binary files /dev/null and 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and b/WEEK11/0x0023_structures/build/0x0023_structures.uf2 differ diff --git a/WEEK11/0x0023_structures/build/pico_flash_region.ld b/WEEK11/0x0023_structures/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK11/0x0023_structures/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK11/0x0023_structures/ir.c b/WEEK11/0x0023_structures/ir.c new file mode 100644 index 0000000..b89bd4e --- /dev/null +++ b/WEEK11/0x0023_structures/ir.c @@ -0,0 +1,80 @@ +/** + * @file ir.c + * @brief Implementation of NEC IR receiver (decoder) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "ir.h" +#include "pico/stdlib.h" +#include "pico/time.h" +#include "hardware/gpio.h" + +static unsigned int ir_pin = 0; + +// Wait for 'gpio' to reach 'level' or timeout (microseconds). Return elapsed us or -1. +static int64_t wait_for_level(unsigned int gpio, bool level, uint32_t timeout_us) { + absolute_time_t start = get_absolute_time(); + while (gpio_get(gpio) != level) { + if (absolute_time_diff_us(start, get_absolute_time()) > (int64_t)timeout_us) { + return -1; + } + } + return absolute_time_diff_us(start, get_absolute_time()); +} + +void ir_init(uint8_t pin) { + ir_pin = pin; + gpio_init(pin); + gpio_set_dir(pin, GPIO_IN); + gpio_pull_up(pin); +} + +int ir_getkey(void) { + // leader low (~9 ms) + if (wait_for_level(ir_pin, 0, 150000) < 0) return -1; + + int64_t t = wait_for_level(ir_pin, 1, 12000); + if (t < 8000 || t > 10000) return -1; + + t = wait_for_level(ir_pin, 0, 7000); + if (t < 3500 || t > 5000) return -1; + + uint8_t data[4] = {0, 0, 0, 0}; + for (int i = 0; i < 32; ++i) { + if (wait_for_level(ir_pin, 1, 1000) < 0) return -1; + t = wait_for_level(ir_pin, 0, 2500); + if (t < 200) return -1; + int byte_idx = i / 8; + int bit_idx = i % 8; + if (t > 1200) data[byte_idx] |= (1 << bit_idx); // logical '1' + } + + // Validate address/data inverted pairs + if ((uint8_t)(data[0] + data[1]) == 0xFF && (uint8_t)(data[2] + data[3]) == 0xFF) { + return data[2]; + } + return -1; +} diff --git a/WEEK11/0x0023_structures/ir.h b/WEEK11/0x0023_structures/ir.h new file mode 100644 index 0000000..84aa67f --- /dev/null +++ b/WEEK11/0x0023_structures/ir.h @@ -0,0 +1,63 @@ +/** + * @file ir.h + * @brief Header for NEC IR receiver (decoder) API + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef IR_H +#define IR_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the IR receiver GPIO + * + * Configures the given `pin` as an input with pull-up for the NEC IR receiver. + * Call this once during board initialization before calling `ir_getkey()`. + * + * @param pin GPIO pin number connected to IR receiver output + */ +void ir_init(uint8_t pin); + +/** + * @brief Blocking NEC IR decoder + * + * Blocks while waiting for a complete NEC frame. On success returns the + * decoded command byte (0..255). On timeout or protocol error returns -1. + * + * @return decoded command byte (0..255) or -1 on failure + */ +int ir_getkey(void); + +#ifdef __cplusplus +} +#endif + +#endif // IR_H diff --git a/WEEK11/0x0023_structures/pico_sdk_import.cmake b/WEEK11/0x0023_structures/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK11/0x0023_structures/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK11/0x0026_functions/.gitignore b/WEEK11/0x0026_functions/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK11/0x0026_functions/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK11/0x0026_functions/.vscode/c_cpp_properties.json b/WEEK11/0x0026_functions/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..c429d6d --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "Pico", + "includePath": [ + "${workspaceFolder}/**", + "${userHome}/.pico-sdk/sdk/2.2.0/**" + ], + "forcedInclude": [ + "${workspaceFolder}/build/generated/pico_base/pico/config_autogen.h", + "${userHome}/.pico-sdk/sdk/2.2.0/src/common/pico_base_headers/include/pico.h" + ], + "defines": [], + "compilerPath": "${userHome}/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gcc.exe", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "cStandard": "c17", + "cppStandard": "c++14", + "intelliSenseMode": "linux-gcc-arm" + } + ], + "version": 4 +} diff --git a/WEEK11/0x0026_functions/.vscode/cmake-kits.json b/WEEK11/0x0026_functions/.vscode/cmake-kits.json new file mode 100644 index 0000000..b0f3815 --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/cmake-kits.json @@ -0,0 +1,15 @@ +[ + { + "name": "Pico", + "compilers": { + "C": "${command:raspberry-pi-pico.getCompilerPath}", + "CXX": "${command:raspberry-pi-pico.getCxxCompilerPath}" + }, + "environmentVariables": { + "PATH": "${command:raspberry-pi-pico.getEnvPath};${env:PATH}" + }, + "cmakeSettings": { + "Python3_EXECUTABLE": "${command:raspberry-pi-pico.getPythonPath}" + } + } +] \ No newline at end of file diff --git a/WEEK11/0x0026_functions/.vscode/extensions.json b/WEEK11/0x0026_functions/.vscode/extensions.json new file mode 100644 index 0000000..a940d7c --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "marus25.cortex-debug", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.vscode-serial-monitor", + "raspberry-pi.raspberry-pi-pico" + ] +} \ No newline at end of file diff --git a/WEEK11/0x0026_functions/.vscode/launch.json b/WEEK11/0x0026_functions/.vscode/launch.json new file mode 100644 index 0000000..424aa71 --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/launch.json @@ -0,0 +1,50 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Pico Debug (Cortex-Debug)", + "cwd": "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "serverpath": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/${command:raspberry-pi-pico.getTarget}.cfg" + ], + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ], + "openOCDLaunchCommands": [ + "adapter speed 5000" + ] + }, + { + "name": "Pico Debug (Cortex-Debug with external OpenOCD)", + "cwd": "${workspaceRoot}", + "executable": "${command:raspberry-pi-pico.launchTargetPath}", + "request": "launch", + "type": "cortex-debug", + "servertype": "external", + "gdbTarget": "localhost:3333", + "gdbPath": "${command:raspberry-pi-pico.getGDBPath}", + "device": "${command:raspberry-pi-pico.getChipUppercase}", + "svdFile": "${userHome}/.pico-sdk/sdk/2.2.0/src/${command:raspberry-pi-pico.getChip}/hardware_regs/${command:raspberry-pi-pico.getChipUppercase}.svd", + "runToEntryPoint": "main", + // Fix for no_flash binaries, where monitor reset halt doesn't do what is expected + // Also works fine for flash binaries + "overrideLaunchCommands": [ + "monitor reset init", + "load \"${command:raspberry-pi-pico.launchTargetPath}\"" + ] + }, + ] +} diff --git a/WEEK11/0x0026_functions/.vscode/settings.json b/WEEK11/0x0026_functions/.vscode/settings.json new file mode 100644 index 0000000..95be83b --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/settings.json @@ -0,0 +1,40 @@ +{ + "cmake.showSystemKits": false, + "cmake.options.statusBarVisibility": "hidden", + "cmake.options.advanced": { + "build": { + "statusBarVisibility": "hidden" + }, + "launch": { + "statusBarVisibility": "hidden" + }, + "debug": { + "statusBarVisibility": "hidden" + } + }, + "cmake.configureOnEdit": false, + "cmake.automaticReconfigure": false, + "cmake.configureOnOpen": false, + "cmake.generator": "Ninja", + "cmake.cmakePath": "${userHome}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "C_Cpp.debugShortcut": false, + "terminal.integrated.env.windows": { + "PICO_SDK_PATH": "${env:USERPROFILE}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1", + "Path": "${env:USERPROFILE}/.pico-sdk/toolchain/14_2_Rel1/bin;${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool;${env:USERPROFILE}/.pico-sdk/cmake/v3.31.5/bin;${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1;${env:PATH}" + }, + "terminal.integrated.env.osx": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "terminal.integrated.env.linux": { + "PICO_SDK_PATH": "${env:HOME}/.pico-sdk/sdk/2.2.0", + "PICO_TOOLCHAIN_PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1", + "PATH": "${env:HOME}/.pico-sdk/toolchain/14_2_Rel1/bin:${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool:${env:HOME}/.pico-sdk/cmake/v3.31.5/bin:${env:HOME}/.pico-sdk/ninja/v1.12.1:${env:PATH}" + }, + "raspberry-pi-pico.cmakeAutoConfigure": true, + "raspberry-pi-pico.useCmakeTools": false, + "raspberry-pi-pico.cmakePath": "${HOME}/.pico-sdk/cmake/v3.31.5/bin/cmake", + "raspberry-pi-pico.ninjaPath": "${HOME}/.pico-sdk/ninja/v1.12.1/ninja" +} diff --git a/WEEK11/0x0026_functions/.vscode/tasks.json b/WEEK11/0x0026_functions/.vscode/tasks.json new file mode 100644 index 0000000..d1b3193 --- /dev/null +++ b/WEEK11/0x0026_functions/.vscode/tasks.json @@ -0,0 +1,102 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Compile Project", + "type": "process", + "isBuildCommand": true, + "command": "${userHome}/.pico-sdk/ninja/v1.12.1/ninja", + "args": ["-C", "${workspaceFolder}/build"], + "group": "build", + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": "$gcc", + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/ninja/v1.12.1/ninja.exe" + } + }, + { + "label": "Run Project", + "type": "process", + "command": "${env:HOME}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool", + "args": [ + "load", + "${command:raspberry-pi-pico.launchTargetPath}", + "-fx" + ], + "presentation": { + "reveal": "always", + "panel": "dedicated" + }, + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/picotool/2.2.0-a4/picotool/picotool.exe" + } + }, + { + "label": "Flash", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getTarget}.cfg", + "-c", + "adapter speed 5000; program \"${command:raspberry-pi-pico.launchTargetPath}\" verify reset exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "Rescue Reset", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/${command:raspberry-pi-pico.getChip}-rescue.cfg", + "-c", + "adapter speed 5000; reset halt; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + }, + { + "label": "RISC-V Reset (RP2350)", + "type": "process", + "command": "${userHome}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + "args": [ + "-s", + "${userHome}/.pico-sdk/openocd/0.12.0+dev/scripts", + "-c", + "set USE_CORE { rv0 rv1 cm0 cm1 }", + "-f", + "interface/cmsis-dap.cfg", + "-f", + "target/rp2350.cfg", + "-c", + "adapter speed 5000; init;", + "-c", + "write_memory 0x40120158 8 { 0x3 }; echo [format \"Info : ARCHSEL 0x%02x\" [read_memory 0x40120158 8 1]];", + "-c", + "reset halt; targets rp2350.rv0; echo [format \"Info : ARCHSEL_STATUS 0x%02x\" [read_memory 0x4012015C 8 1]]; exit" + ], + "problemMatcher": [], + "windows": { + "command": "${env:USERPROFILE}/.pico-sdk/openocd/0.12.0+dev/openocd.exe", + } + } + ] +} diff --git a/WEEK11/0x0026_functions/0x0026_functions.c b/WEEK11/0x0026_functions/0x0026_functions.c new file mode 100644 index 0000000..518f5c0 --- /dev/null +++ b/WEEK11/0x0026_functions/0x0026_functions.c @@ -0,0 +1,149 @@ +#include +#include +#include "pico/stdlib.h" +#include "ir.h" + +#define IR_PIN 5 + +typedef struct { + uint8_t led1_pin; + uint8_t led2_pin; + uint8_t led3_pin; + bool led1_state; + bool led2_state; + bool led3_state; +} simple_led_ctrl_t; + +/** + * @brief Map NEC IR command code to LED number + * + * Translates a received NEC IR command code to a logical LED number. + * Supports three button mappings for controlling individual LEDs. + * + * @param ir_command NEC command code from IR receiver + * @return int LED number (1-3) or 0 if no match + */ +int ir_to_led_number(int ir_command) { + if (ir_command == 0x0C) return 1; + if (ir_command == 0x18) return 2; + if (ir_command == 0x5E) return 3; + return 0; +} + +/** + * @brief Get GPIO pin number for a given LED number + * + * Retrieves the GPIO pin associated with a logical LED number + * from the LED controller structure. + * + * @param leds Pointer to LED controller structure + * @param led_num LED number (1-3) + * @return uint8_t GPIO pin number or 0 if invalid + */ +uint8_t get_led_pin(simple_led_ctrl_t *leds, int led_num) { + if (led_num == 1) return leds->led1_pin; + if (led_num == 2) return leds->led2_pin; + if (led_num == 3) return leds->led3_pin; + return 0; +} + +/** + * @brief Turn off all LEDs in the controller + * + * Sets all three LED GPIO outputs to low, turning off all LEDs. + * + * @param leds Pointer to LED controller structure + */ +void leds_all_off(simple_led_ctrl_t *leds) { + gpio_put(leds->led1_pin, false); + gpio_put(leds->led2_pin, false); + gpio_put(leds->led3_pin, false); +} + +/** + * @brief Blink an LED pin a specified number of times + * + * Toggles the specified GPIO pin on and off for the given count, + * with configurable delay between transitions. + * + * @param pin GPIO pin number to blink + * @param count Number of blink cycles + * @param delay_ms Delay in milliseconds for on/off periods + */ +void blink_led(uint8_t pin, uint8_t count, uint32_t delay_ms) { + for (uint8_t i = 0; i < count; i++) { + gpio_put(pin, true); + sleep_ms(delay_ms); + gpio_put(pin, false); + sleep_ms(delay_ms); + } +} + +/** + * @brief Process IR command and activate corresponding LED + * + * Handles incoming IR commands by turning off all LEDs, mapping the + * command to an LED, blinking it, then holding it steady. + * + * @param ir_command NEC command code from IR receiver + * @param leds Pointer to LED controller structure + * @param blink_count Number of blinks before steady state + * @return int LED number activated (1-3), 0 if none, -1 if invalid + */ +int process_ir_led_command(int ir_command, simple_led_ctrl_t *leds, uint8_t blink_count) { + if (!leds || ir_command < 0) return -1; + leds_all_off(leds); + int led_num = ir_to_led_number(ir_command); + if (led_num == 0) return 0; + uint8_t pin = get_led_pin(leds, led_num); + blink_led(pin, blink_count, 50); + gpio_put(pin, true); + return led_num; +} + +int main(void) { + stdio_init_all(); + + simple_led_ctrl_t leds = { + .led1_pin = 16, + .led2_pin = 17, + .led3_pin = 18, + .led1_state = false, + .led2_state = false, + .led3_state = false + }; + + // Initialize LED GPIOs + gpio_init(leds.led1_pin); gpio_set_dir(leds.led1_pin, GPIO_OUT); + gpio_init(leds.led2_pin); gpio_set_dir(leds.led2_pin, GPIO_OUT); + gpio_init(leds.led3_pin); gpio_set_dir(leds.led3_pin, GPIO_OUT); + + // Initialize IR receiver + ir_init(IR_PIN); + printf("IR receiver on GPIO %d ready\n", IR_PIN); + printf("Press remote buttons to control LEDs with blink effects!\n"); + + while (true) { + int key = ir_getkey(); + if (key >= 0) { + printf("NEC command: 0x%02X\n", key); + + // Process the IR command with 3 blinks before steady state + int activated_led = process_ir_led_command(key, &leds, 3); + + if (activated_led > 0) { + printf("LED %d activated on GPIO %d\n", activated_led, + (activated_led == 1) ? leds.led1_pin : + (activated_led == 2) ? leds.led2_pin : leds.led3_pin); + } else if (activated_led == 0) { + printf("No LED matched or chase effect played\n"); + } else { + printf("Invalid command or null pointer\n"); + } + + sleep_ms(10); + } else { + sleep_ms(1); + } + } +} diff --git a/WEEK11/0x0026_functions/CMakeLists.txt b/WEEK11/0x0026_functions/CMakeLists.txt new file mode 100644 index 0000000..b6ea0f9 --- /dev/null +++ b/WEEK11/0x0026_functions/CMakeLists.txt @@ -0,0 +1,57 @@ +# Generated Cmake Pico project file + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# Initialise pico_sdk from installed location +# (note this can come from environment, CMake cache etc) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0026_functions C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# Add executable. Default name is the project name, version 0.1 + +add_executable(0x0026_functions 0x0026_functions.c ir.c) + +pico_set_program_name(0x0026_functions "0x0026_functions") +pico_set_program_version(0x0026_functions "0.1") + +# Modify the below lines to enable/disable output over UART/USB +pico_enable_stdio_uart(0x0026_functions 1) +pico_enable_stdio_usb(0x0026_functions 0) + +# Add the standard library to the build +target_link_libraries(0x0026_functions + pico_stdlib) + +# Add the standard include files to the build +target_include_directories(0x0026_functions PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +pico_add_extra_outputs(0x0026_functions) + diff --git a/WEEK11/0x0026_functions/build/0x0026_functions.bin b/WEEK11/0x0026_functions/build/0x0026_functions.bin new file mode 100755 index 0000000..5ee4f86 Binary files /dev/null and b/WEEK11/0x0026_functions/build/0x0026_functions.bin differ diff --git a/WEEK11/0x0026_functions/build/0x0026_functions.dis b/WEEK11/0x0026_functions/build/0x0026_functions.dis new file mode 100644 index 0000000..83abb19 --- /dev/null +++ b/WEEK11/0x0026_functions/build/0x0026_functions.dis @@ -0,0 +1,6139 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026_functions/build/0x0026_functions.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000038f4 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000200 100038f8 100038f8 000048f8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10003af8 10003af8 00004af8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 0000002c 10003b00 10003b00 00004b00 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00007000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 0000605c 2**0 + CONTENTS + 6 .data 0000051c 20000110 10003b2c 00005110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 0000605c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 0000022c 20000630 10004048 00006630 2**3 + ALLOC + 10 .heap 00000800 2000085c 10004048 0000685c 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 0000605c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 0000605c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00007000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10004048 10004048 00006048 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 0000605c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00006090 2**0 + CONTENTS, READONLY + 17 .debug_info 000221f0 00000000 00000000 000060d5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00005a37 00000000 00000000 000282c5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 0001075f 00000000 00000000 0002dcfc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000c10 00000000 00000000 0003e460 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00003207 00000000 00000000 0003f070 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000166c8 00000000 00000000 00042277 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005b36 00000000 00000000 0005893f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00001f90 00000000 00000000 0005e478 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002b7 00000000 00000000 00060408 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026_functions/build/0x0026_functions.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 10003b00 .word 0x10003b00 +1000012c: 10003b2c .word 0x10003b2c +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00003f10 .word 0x00003f10 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 10003b2c .word 0x10003b2c +100001a4: 20000110 .word 0x20000110 +100001a8: 2000062c .word 0x2000062c +100001ac: 10004048 .word 0x10004048 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10004048 .word 0x10004048 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 2000062c .word 0x2000062c +100001d4: 2000085c .word 0x2000085c +100001d8: 1000315d .word 0x1000315d +100001dc: 10000235 .word 0x10000235 +100001e0: 10003155 .word 0x10003155 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 2000062c .word 0x2000062c +10000208: 2000062c .word 0x2000062c +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20000814 .word 0x20000814 +10000230: 100038f4 .word 0x100038f4 + +10000234
: +10000234: b580 push {r7, lr} +10000236: f003 f8b9 bl 100033ac +1000023a: 2010 movs r0, #16 +1000023c: f000 f9ac bl 10000598 +10000240: f04f 0701 mov.w r7, #1 +10000244: 2310 movs r3, #16 +10000246: ec47 3044 gpioc_bit_oe_put r3, r7 +1000024a: 2011 movs r0, #17 +1000024c: f000 f9a4 bl 10000598 +10000250: 2311 movs r3, #17 +10000252: ec47 3044 gpioc_bit_oe_put r3, r7 +10000256: 2012 movs r0, #18 +10000258: f000 f99e bl 10000598 +1000025c: 2312 movs r3, #18 +1000025e: ec47 3044 gpioc_bit_oe_put r3, r7 +10000262: 2005 movs r0, #5 +10000264: f000 f858 bl 10000318 +10000268: 2105 movs r1, #5 +1000026a: 4828 ldr r0, [pc, #160] @ (1000030c ) +1000026c: f003 f966 bl 1000353c <__wrap_printf> +10000270: f04f 0600 mov.w r6, #0 +10000274: f000 f864 bl 10000340 +10000278: 1e04 subs r4, r0, #0 +1000027a: db19 blt.n 100002b0 +1000027c: 4621 mov r1, r4 +1000027e: 4824 ldr r0, [pc, #144] @ (10000310 ) +10000280: f003 f95c bl 1000353c <__wrap_printf> +10000284: 2510 movs r5, #16 +10000286: ec46 5040 gpioc_bit_out_put r5, r6 +1000028a: 2311 movs r3, #17 +1000028c: ec46 3040 gpioc_bit_out_put r3, r6 +10000290: 2212 movs r2, #18 +10000292: ec46 2040 gpioc_bit_out_put r2, r6 +10000296: 2c0c cmp r4, #12 +10000298: d00e beq.n 100002b8 +1000029a: 2c18 cmp r4, #24 +1000029c: d02e beq.n 100002fc +1000029e: 2c5e cmp r4, #94 @ 0x5e +100002a0: d030 beq.n 10000304 +100002a2: 200a movs r0, #10 +100002a4: f000 fea4 bl 10000ff0 +100002a8: f000 f84a bl 10000340 +100002ac: 1e04 subs r4, r0, #0 +100002ae: dae5 bge.n 1000027c +100002b0: 2001 movs r0, #1 +100002b2: f000 fe9d bl 10000ff0 +100002b6: e7dd b.n 10000274 +100002b8: f04f 0801 mov.w r8, #1 +100002bc: 2403 movs r4, #3 +100002be: ec47 5040 gpioc_bit_out_put r5, r7 +100002c2: 2032 movs r0, #50 @ 0x32 +100002c4: f000 fe94 bl 10000ff0 +100002c8: ec46 5040 gpioc_bit_out_put r5, r6 +100002cc: 2032 movs r0, #50 @ 0x32 +100002ce: f000 fe8f bl 10000ff0 +100002d2: 1e63 subs r3, r4, #1 +100002d4: f013 04ff ands.w r4, r3, #255 @ 0xff +100002d8: d1f1 bne.n 100002be +100002da: ec47 5040 gpioc_bit_out_put r5, r7 +100002de: f1b8 0f01 cmp.w r8, #1 +100002e2: d009 beq.n 100002f8 +100002e4: f1b8 0f02 cmp.w r8, #2 +100002e8: bf14 ite ne +100002ea: 2212 movne r2, #18 +100002ec: 2211 moveq r2, #17 +100002ee: 4641 mov r1, r8 +100002f0: 4808 ldr r0, [pc, #32] @ (10000314 ) +100002f2: f003 f923 bl 1000353c <__wrap_printf> +100002f6: e7d4 b.n 100002a2 +100002f8: 2210 movs r2, #16 +100002fa: e7f8 b.n 100002ee +100002fc: 461d mov r5, r3 +100002fe: f04f 0802 mov.w r8, #2 +10000302: e7db b.n 100002bc +10000304: 4615 mov r5, r2 +10000306: f04f 0803 mov.w r8, #3 +1000030a: e7d7 b.n 100002bc +1000030c: 100038f8 .word 0x100038f8 +10000310: 10003918 .word 0x10003918 +10000314: 10003930 .word 0x10003930 + +10000318 : +10000318: 4b08 ldr r3, [pc, #32] @ (1000033c ) +1000031a: b510 push {r4, lr} +1000031c: 6018 str r0, [r3, #0] +1000031e: 4604 mov r4, r0 +10000320: f000 f93a bl 10000598 +10000324: f04f 0300 mov.w r3, #0 +10000328: ec43 4044 gpioc_bit_oe_put r4, r3 +1000032c: 2101 movs r1, #1 +1000032e: 4620 mov r0, r4 +10000330: e8bd 4010 ldmia.w sp!, {r4, lr} +10000334: 2200 movs r2, #0 +10000336: f000 b91b b.w 10000570 +1000033a: bf00 nop +1000033c: 2000080c .word 0x2000080c + +10000340 : +10000340: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000344: 4b77 ldr r3, [pc, #476] @ (10000524 ) +10000346: b085 sub sp, #20 +10000348: 681d ldr r5, [r3, #0] +1000034a: 2601 movs r6, #1 +1000034c: f000 ff42 bl 100011d4 +10000350: 40ae lsls r6, r5 +10000352: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +10000356: f04f 0900 mov.w r9, #0 +1000035a: 4604 mov r4, r0 +1000035c: 460d mov r5, r1 +1000035e: f8df 81d0 ldr.w r8, [pc, #464] @ 10000530 +10000362: e009 b.n 10000378 +10000364: f000 ff36 bl 100011d4 +10000368: 1b00 subs r0, r0, r4 +1000036a: eb61 0105 sbc.w r1, r1, r5 +1000036e: 4580 cmp r8, r0 +10000370: eb79 0101 sbcs.w r1, r9, r1 +10000374: f2c0 80d1 blt.w 1000051a +10000378: 687b ldr r3, [r7, #4] +1000037a: 4233 tst r3, r6 +1000037c: d1f2 bne.n 10000364 +1000037e: f000 ff29 bl 100011d4 +10000382: 42a0 cmp r0, r4 +10000384: eb61 0105 sbc.w r1, r1, r5 +10000388: 2900 cmp r1, #0 +1000038a: f2c0 80c6 blt.w 1000051a +1000038e: 4b65 ldr r3, [pc, #404] @ (10000524 ) +10000390: 2601 movs r6, #1 +10000392: 681d ldr r5, [r3, #0] +10000394: f000 ff1e bl 100011d4 +10000398: 40ae lsls r6, r5 +1000039a: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +1000039e: f642 68e1 movw r8, #12001 @ 0x2ee1 +100003a2: 4604 mov r4, r0 +100003a4: 460d mov r5, r1 +100003a6: e009 b.n 100003bc +100003a8: f000 ff14 bl 100011d4 +100003ac: 1b00 subs r0, r0, r4 +100003ae: eb61 0105 sbc.w r1, r1, r5 +100003b2: 4540 cmp r0, r8 +100003b4: f171 0100 sbcs.w r1, r1, #0 +100003b8: f280 80af bge.w 1000051a +100003bc: 687b ldr r3, [r7, #4] +100003be: 4233 tst r3, r6 +100003c0: d0f2 beq.n 100003a8 +100003c2: f000 ff07 bl 100011d4 +100003c6: 4b58 ldr r3, [pc, #352] @ (10000528 ) +100003c8: f240 72d1 movw r2, #2001 @ 0x7d1 +100003cc: 1b1b subs r3, r3, r4 +100003ce: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff +100003d2: eb64 0505 sbc.w r5, r4, r5 +100003d6: 181b adds r3, r3, r0 +100003d8: eb45 0501 adc.w r5, r5, r1 +100003dc: 4293 cmp r3, r2 +100003de: f175 0500 sbcs.w r5, r5, #0 +100003e2: f080 809a bcs.w 1000051a +100003e6: 4b4f ldr r3, [pc, #316] @ (10000524 ) +100003e8: 2501 movs r5, #1 +100003ea: 681e ldr r6, [r3, #0] +100003ec: f000 fef2 bl 100011d4 +100003f0: 40b5 lsls r5, r6 +100003f2: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +100003f6: f641 3859 movw r8, #7001 @ 0x1b59 +100003fa: 4604 mov r4, r0 +100003fc: 460e mov r6, r1 +100003fe: e009 b.n 10000414 +10000400: f000 fee8 bl 100011d4 +10000404: 1b00 subs r0, r0, r4 +10000406: eb61 0106 sbc.w r1, r1, r6 +1000040a: 4540 cmp r0, r8 +1000040c: f171 0100 sbcs.w r1, r1, #0 +10000410: f280 8083 bge.w 1000051a +10000414: 687b ldr r3, [r7, #4] +10000416: 402b ands r3, r5 +10000418: d1f2 bne.n 10000400 +1000041a: 9301 str r3, [sp, #4] +1000041c: f000 feda bl 100011d4 +10000420: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10000424: f240 55dd movw r5, #1501 @ 0x5dd +10000428: 4a40 ldr r2, [pc, #256] @ (1000052c ) +1000042a: 1b12 subs r2, r2, r4 +1000042c: eb63 0606 sbc.w r6, r3, r6 +10000430: 1812 adds r2, r2, r0 +10000432: eb46 0601 adc.w r6, r6, r1 +10000436: 42aa cmp r2, r5 +10000438: f176 0600 sbcs.w r6, r6, #0 +1000043c: d26d bcs.n 1000051a +1000043e: 9b01 ldr r3, [sp, #4] +10000440: f04f 0b01 mov.w fp, #1 +10000444: 469a mov sl, r3 +10000446: f240 35e9 movw r5, #1001 @ 0x3e9 +1000044a: 9303 str r3, [sp, #12] +1000044c: 4b35 ldr r3, [pc, #212] @ (10000524 ) +1000044e: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +10000452: 681f ldr r7, [r3, #0] +10000454: f000 febe bl 100011d4 +10000458: fa0b f707 lsl.w r7, fp, r7 +1000045c: 4604 mov r4, r0 +1000045e: 460e mov r6, r1 +10000460: e008 b.n 10000474 +10000462: f000 feb7 bl 100011d4 +10000466: 1b00 subs r0, r0, r4 +10000468: eb61 0106 sbc.w r1, r1, r6 +1000046c: 42a8 cmp r0, r5 +1000046e: f171 0100 sbcs.w r1, r1, #0 +10000472: da52 bge.n 1000051a +10000474: f8d8 3004 ldr.w r3, [r8, #4] +10000478: 423b tst r3, r7 +1000047a: d0f2 beq.n 10000462 +1000047c: f000 feaa bl 100011d4 +10000480: 42a0 cmp r0, r4 +10000482: eb61 0106 sbc.w r1, r1, r6 +10000486: 2900 cmp r1, #0 +10000488: db47 blt.n 1000051a +1000048a: 4b26 ldr r3, [pc, #152] @ (10000524 ) +1000048c: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +10000490: 681f ldr r7, [r3, #0] +10000492: f000 fe9f bl 100011d4 +10000496: f640 19c5 movw r9, #2501 @ 0x9c5 +1000049a: 4604 mov r4, r0 +1000049c: 460e mov r6, r1 +1000049e: fa0b f707 lsl.w r7, fp, r7 +100004a2: e008 b.n 100004b6 +100004a4: f000 fe96 bl 100011d4 +100004a8: 1b00 subs r0, r0, r4 +100004aa: eb61 0106 sbc.w r1, r1, r6 +100004ae: 4548 cmp r0, r9 +100004b0: f171 0100 sbcs.w r1, r1, #0 +100004b4: da31 bge.n 1000051a +100004b6: f8d8 3004 ldr.w r3, [r8, #4] +100004ba: 423b tst r3, r7 +100004bc: d1f2 bne.n 100004a4 +100004be: f000 fe89 bl 100011d4 +100004c2: 1b00 subs r0, r0, r4 +100004c4: eb61 0106 sbc.w r1, r1, r6 +100004c8: 28c8 cmp r0, #200 @ 0xc8 +100004ca: f171 0300 sbcs.w r3, r1, #0 +100004ce: db24 blt.n 1000051a +100004d0: f240 43b1 movw r3, #1201 @ 0x4b1 +100004d4: 4298 cmp r0, r3 +100004d6: f171 0100 sbcs.w r1, r1, #0 +100004da: db09 blt.n 100004f0 +100004dc: a903 add r1, sp, #12 +100004de: ea4f 02ea mov.w r2, sl, asr #3 +100004e2: 5c88 ldrb r0, [r1, r2] +100004e4: f00a 0307 and.w r3, sl, #7 +100004e8: fa0b f303 lsl.w r3, fp, r3 +100004ec: 4303 orrs r3, r0 +100004ee: 548b strb r3, [r1, r2] +100004f0: f10a 0a01 add.w sl, sl, #1 +100004f4: f1ba 0f20 cmp.w sl, #32 +100004f8: d1a8 bne.n 1000044c +100004fa: f89d 300c ldrb.w r3, [sp, #12] +100004fe: f89d 200d ldrb.w r2, [sp, #13] +10000502: 4413 add r3, r2 +10000504: b2db uxtb r3, r3 +10000506: 2bff cmp r3, #255 @ 0xff +10000508: d107 bne.n 1000051a +1000050a: f89d 000e ldrb.w r0, [sp, #14] +1000050e: f89d 300f ldrb.w r3, [sp, #15] +10000512: 4403 add r3, r0 +10000514: b2db uxtb r3, r3 +10000516: 2bff cmp r3, #255 @ 0xff +10000518: d001 beq.n 1000051e +1000051a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +1000051e: b005 add sp, #20 +10000520: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000524: 2000080c .word 0x2000080c +10000528: ffffe0c0 .word 0xffffe0c0 +1000052c: fffff254 .word 0xfffff254 +10000530: 000249f0 .word 0x000249f0 + +10000534 : +10000534: b410 push {r4} +10000536: f44f 7480 mov.w r4, #256 @ 0x100 +1000053a: 4b0c ldr r3, [pc, #48] @ (1000056c ) +1000053c: f853 2020 ldr.w r2, [r3, r0, lsl #2] +10000540: eb03 0380 add.w r3, r3, r0, lsl #2 +10000544: 00c0 lsls r0, r0, #3 +10000546: f082 0240 eor.w r2, r2, #64 @ 0x40 +1000054a: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +1000054e: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +10000552: f002 02c0 and.w r2, r2, #192 @ 0xc0 +10000556: f500 3020 add.w r0, r0, #163840 @ 0x28000 +1000055a: f503 5340 add.w r3, r3, #12288 @ 0x3000 +1000055e: f8cc 2000 str.w r2, [ip] +10000562: 6041 str r1, [r0, #4] +10000564: 601c str r4, [r3, #0] +10000566: f85d 4b04 ldr.w r4, [sp], #4 +1000056a: 4770 bx lr +1000056c: 40038004 .word 0x40038004 + +10000570 : +10000570: b410 push {r4} +10000572: 4c08 ldr r4, [pc, #32] @ (10000594 ) +10000574: 00c9 lsls r1, r1, #3 +10000576: ea41 0182 orr.w r1, r1, r2, lsl #2 +1000057a: f854 2020 ldr.w r2, [r4, r0, lsl #2] +1000057e: eb04 0380 add.w r3, r4, r0, lsl #2 +10000582: 4051 eors r1, r2 +10000584: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10000588: f001 010c and.w r1, r1, #12 +1000058c: f85d 4b04 ldr.w r4, [sp], #4 +10000590: 6019 str r1, [r3, #0] +10000592: 4770 bx lr +10000594: 40038004 .word 0x40038004 + +10000598 : +10000598: b430 push {r4, r5} +1000059a: f04f 0300 mov.w r3, #0 +1000059e: ec43 0044 gpioc_bit_oe_put r0, r3 +100005a2: ec43 0040 gpioc_bit_out_put r0, r3 +100005a6: 2505 movs r5, #5 +100005a8: f44f 7480 mov.w r4, #256 @ 0x100 +100005ac: 4b0b ldr r3, [pc, #44] @ (100005dc ) +100005ae: 00c2 lsls r2, r0, #3 +100005b0: f853 1020 ldr.w r1, [r3, r0, lsl #2] +100005b4: eb03 0080 add.w r0, r3, r0, lsl #2 +100005b8: f081 0140 eor.w r1, r1, #64 @ 0x40 +100005bc: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +100005c0: f503 3320 add.w r3, r3, #163840 @ 0x28000 +100005c4: f001 02c0 and.w r2, r1, #192 @ 0xc0 +100005c8: f500 5180 add.w r1, r0, #4096 @ 0x1000 +100005cc: f500 5040 add.w r0, r0, #12288 @ 0x3000 +100005d0: 600a str r2, [r1, #0] +100005d2: 605d str r5, [r3, #4] +100005d4: 6004 str r4, [r0, #0] +100005d6: bc30 pop {r4, r5} +100005d8: 4770 bx lr +100005da: bf00 nop +100005dc: 40038004 .word 0x40038004 + +100005e0 : +100005e0: b40f push {r0, r1, r2, r3} +100005e2: b500 push {lr} +100005e4: b083 sub sp, #12 +100005e6: 9c04 ldr r4, [sp, #16] +100005e8: 4807 ldr r0, [pc, #28] @ (10000608 ) +100005ea: f002 ff27 bl 1000343c <__wrap_puts> +100005ee: b13c cbz r4, 10000600 +100005f0: a905 add r1, sp, #20 +100005f2: 4620 mov r0, r4 +100005f4: 9101 str r1, [sp, #4] +100005f6: f002 fd93 bl 10003120 +100005fa: 4804 ldr r0, [pc, #16] @ (1000060c ) +100005fc: f002 ff1e bl 1000343c <__wrap_puts> +10000600: 2001 movs r0, #1 +10000602: f002 fda5 bl 10003150 <_exit> +10000606: bf00 nop +10000608: 10003950 .word 0x10003950 +1000060c: 10003960 .word 0x10003960 + +10000610 : +10000610: b570 push {r4, r5, r6, lr} +10000612: 4686 mov lr, r0 +10000614: f3ef 8510 mrs r5, PRIMASK +10000618: b672 cpsid i +1000061a: 4c12 ldr r4, [pc, #72] @ (10000664 ) +1000061c: e8d4 6fcf ldaexb r6, [r4] +10000620: 2001 movs r0, #1 +10000622: 2e00 cmp r6, #0 +10000624: d1fa bne.n 1000061c +10000626: e8c4 0f46 strexb r6, r0, [r4] +1000062a: 2e00 cmp r6, #0 +1000062c: d1f6 bne.n 1000061c +1000062e: f3bf 8f5f dmb sy +10000632: f04f 0c01 mov.w ip, #1 +10000636: 08c8 lsrs r0, r1, #3 +10000638: f001 0307 and.w r3, r1, #7 +1000063c: fa0c f303 lsl.w r3, ip, r3 +10000640: f81e c000 ldrb.w ip, [lr, r0] +10000644: ea1c 0603 ands.w r6, ip, r3 +10000648: d108 bne.n 1000065c +1000064a: ea4c 0c03 orr.w ip, ip, r3 +1000064e: f80e c000 strb.w ip, [lr, r0] +10000652: e8c4 6f8f stlb r6, [r4] +10000656: f385 8810 msr PRIMASK, r5 +1000065a: bd70 pop {r4, r5, r6, pc} +1000065c: 4610 mov r0, r2 +1000065e: f7ff ffbf bl 100005e0 +10000662: bf00 nop +10000664: 200007bb .word 0x200007bb + +10000668 : +10000668: 4a04 ldr r2, [pc, #16] @ (1000067c ) +1000066a: 7810 ldrb r0, [r2, #0] +1000066c: 1c43 adds r3, r0, #1 +1000066e: b2db uxtb r3, r3 +10000670: 2b18 cmp r3, #24 +10000672: bf28 it cs +10000674: 2310 movcs r3, #16 +10000676: 7013 strb r3, [r2, #0] +10000678: 4770 bx lr +1000067a: bf00 nop +1000067c: 200005a8 .word 0x200005a8 + +10000680 : +10000680: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10000684: 6893 ldr r3, [r2, #8] +10000686: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1000068a: 6093 str r3, [r2, #8] +1000068c: 4770 bx lr +1000068e: bf00 nop + +10000690 : +10000690: 2100 movs r1, #0 +10000692: 4b04 ldr r3, [pc, #16] @ (100006a4 ) +10000694: f103 0220 add.w r2, r3, #32 +10000698: e8c3 1f8f stlb r1, [r3] +1000069c: 3301 adds r3, #1 +1000069e: 4293 cmp r3, r2 +100006a0: d1fa bne.n 10000698 +100006a2: 4770 bx lr +100006a4: 200007b0 .word 0x200007b0 + +100006a8 : +100006a8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100006ac: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100006b0: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100006b4: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100006b8: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100006bc: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100006c0: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100006c4: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +100006c8: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +100006cc: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +100006d0: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +100006d4: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +100006d8: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +100006dc: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +100006e0: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +100006e4: b662 cpsie i +100006e6: 4770 bx lr + +100006e8 : +100006e8: 2301 movs r3, #1 +100006ea: f000 021f and.w r2, r0, #31 +100006ee: 4093 lsls r3, r2 +100006f0: 0940 lsrs r0, r0, #5 +100006f2: b141 cbz r1, 10000706 +100006f4: 0080 lsls r0, r0, #2 +100006f6: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +100006fa: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100006fe: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +10000702: 6003 str r3, [r0, #0] +10000704: 4770 bx lr +10000706: 4a02 ldr r2, [pc, #8] @ (10000710 ) +10000708: 3020 adds r0, #32 +1000070a: f842 3020 str.w r3, [r2, r0, lsl #2] +1000070e: 4770 bx lr +10000710: e000e100 .word 0xe000e100 + +10000714 : +10000714: b5f8 push {r3, r4, r5, r6, r7, lr} +10000716: 460d mov r5, r1 +10000718: f3ef 8710 mrs r7, PRIMASK +1000071c: b672 cpsid i +1000071e: 4e12 ldr r6, [pc, #72] @ (10000768 ) +10000720: e8d6 2fcf ldaexb r2, [r6] +10000724: 2301 movs r3, #1 +10000726: 2a00 cmp r2, #0 +10000728: d1fa bne.n 10000720 +1000072a: e8c6 3f42 strexb r2, r3, [r6] +1000072e: 2a00 cmp r2, #0 +10000730: d1f6 bne.n 10000720 +10000732: f3bf 8f5f dmb sy +10000736: 4b0d ldr r3, [pc, #52] @ (1000076c ) +10000738: f100 0410 add.w r4, r0, #16 +1000073c: 689b ldr r3, [r3, #8] +1000073e: 4a0c ldr r2, [pc, #48] @ (10000770 ) +10000740: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10000744: 4293 cmp r3, r2 +10000746: d003 beq.n 10000750 +10000748: 4299 cmp r1, r3 +1000074a: d001 beq.n 10000750 +1000074c: f000 ff0c bl 10001568 +10000750: 4b06 ldr r3, [pc, #24] @ (1000076c ) +10000752: 689b ldr r3, [r3, #8] +10000754: f843 5024 str.w r5, [r3, r4, lsl #2] +10000758: f3bf 8f5f dmb sy +1000075c: 2300 movs r3, #0 +1000075e: e8c6 3f8f stlb r3, [r6] +10000762: f387 8810 msr PRIMASK, r7 +10000766: bdf8 pop {r3, r4, r5, r6, r7, pc} +10000768: 200007b9 .word 0x200007b9 +1000076c: e000ed00 .word 0xe000ed00 +10000770: 10000111 .word 0x10000111 + +10000774 : +10000774: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000778: b083 sub sp, #12 +1000077a: f3ef 8a10 mrs sl, PRIMASK +1000077e: b672 cpsid i +10000780: 4e71 ldr r6, [pc, #452] @ (10000948 ) +10000782: e8d6 2fcf ldaexb r2, [r6] +10000786: 2301 movs r3, #1 +10000788: 2a00 cmp r2, #0 +1000078a: d1fa bne.n 10000782 +1000078c: e8c6 3f42 strexb r2, r3, [r6] +10000790: 2a00 cmp r2, #0 +10000792: d1f6 bne.n 10000782 +10000794: f3bf 8f5f dmb sy +10000798: 4b6c ldr r3, [pc, #432] @ (1000094c ) +1000079a: f100 0810 add.w r8, r0, #16 +1000079e: 689b ldr r3, [r3, #8] +100007a0: 4a6b ldr r2, [pc, #428] @ (10000950 ) +100007a2: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100007a6: 4295 cmp r5, r2 +100007a8: d045 beq.n 10000836 +100007aa: 428d cmp r5, r1 +100007ac: 460c mov r4, r1 +100007ae: d050 beq.n 10000852 +100007b0: 4f68 ldr r7, [pc, #416] @ (10000954 ) +100007b2: 1beb subs r3, r5, r7 +100007b4: 2b2f cmp r3, #47 @ 0x2f +100007b6: d83e bhi.n 10000836 +100007b8: 2101 movs r1, #1 +100007ba: ea4f 1950 mov.w r9, r0, lsr #5 +100007be: ea4f 0989 mov.w r9, r9, lsl #2 +100007c2: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100007c6: f509 4961 add.w r9, r9, #57600 @ 0xe100 +100007ca: f000 031f and.w r3, r0, #31 +100007ce: fa01 f003 lsl.w r0, r1, r3 +100007d2: f8d9 3000 ldr.w r3, [r9] +100007d6: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100007da: ea00 0b03 and.w fp, r0, r3 +100007de: f3bf 8f5f dmb sy +100007e2: f3ef 8105 mrs r1, IPSR +100007e6: b2c9 uxtb r1, r1 +100007e8: 2900 cmp r1, #0 +100007ea: d034 beq.n 10000856 +100007ec: 4588 cmp r8, r1 +100007ee: d005 beq.n 100007fc +100007f0: e9cd 1000 strd r1, r0, [sp] +100007f4: f000 feb8 bl 10001568 +100007f8: e9dd 1000 ldrd r1, r0, [sp] +100007fc: f025 0e01 bic.w lr, r5, #1 +10000800: f8de c008 ldr.w ip, [lr, #8] +10000804: 4564 cmp r4, ip +10000806: d105 bne.n 10000814 +10000808: e089 b.n 1000091e +1000080a: f8d3 c008 ldr.w ip, [r3, #8] +1000080e: 4564 cmp r4, ip +10000810: d031 beq.n 10000876 +10000812: 469e mov lr, r3 +10000814: f99e 2006 ldrsb.w r2, [lr, #6] +10000818: eb02 0342 add.w r3, r2, r2, lsl #1 +1000081c: 2a00 cmp r2, #0 +1000081e: eb07 0383 add.w r3, r7, r3, lsl #2 +10000822: daf2 bge.n 1000080a +10000824: 4564 cmp r4, ip +10000826: d061 beq.n 100008ec +10000828: f1bb 0f00 cmp.w fp, #0 +1000082c: d020 beq.n 10000870 +1000082e: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +10000832: f8c9 0000 str.w r0, [r9] +10000836: 4b45 ldr r3, [pc, #276] @ (1000094c ) +10000838: 689b ldr r3, [r3, #8] +1000083a: f843 5028 str.w r5, [r3, r8, lsl #2] +1000083e: f3bf 8f5f dmb sy +10000842: 2300 movs r3, #0 +10000844: e8c6 3f8f stlb r3, [r6] +10000848: f38a 8810 msr PRIMASK, sl +1000084c: b003 add sp, #12 +1000084e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000852: 4615 mov r5, r2 +10000854: e7ef b.n 10000836 +10000856: f025 0e01 bic.w lr, r5, #1 +1000085a: f8de c008 ldr.w ip, [lr, #8] +1000085e: 4564 cmp r4, ip +10000860: d1d8 bne.n 10000814 +10000862: f99e 4006 ldrsb.w r4, [lr, #6] +10000866: 4673 mov r3, lr +10000868: 2c00 cmp r4, #0 +1000086a: da08 bge.n 1000087e +1000086c: 4615 mov r5, r2 +1000086e: e046 b.n 100008fe +10000870: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000874: e7df b.n 10000836 +10000876: f993 4006 ldrsb.w r4, [r3, #6] +1000087a: 2c00 cmp r4, #0 +1000087c: db37 blt.n 100008ee +1000087e: eb04 0c44 add.w ip, r4, r4, lsl #1 +10000882: eb07 0c8c add.w ip, r7, ip, lsl #2 +10000886: f89c 1007 ldrb.w r1, [ip, #7] +1000088a: f8dc 2008 ldr.w r2, [ip, #8] +1000088e: 71d9 strb r1, [r3, #7] +10000890: 609a str r2, [r3, #8] +10000892: f99c 2006 ldrsb.w r2, [ip, #6] +10000896: 0061 lsls r1, r4, #1 +10000898: 2a00 cmp r2, #0 +1000089a: 719a strb r2, [r3, #6] +1000089c: db3d blt.n 1000091a +1000089e: f8bc e004 ldrh.w lr, [ip, #4] +100008a2: ea5f 5e4e movs.w lr, lr, lsl #21 +100008a6: d505 bpl.n 100008b4 +100008a8: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100008ac: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100008b0: f10e 0e1f add.w lr, lr, #31 +100008b4: f06f 0c07 mvn.w ip, #7 +100008b8: 190a adds r2, r1, r4 +100008ba: ea4f 5e6e mov.w lr, lr, asr #21 +100008be: 0092 lsls r2, r2, #2 +100008c0: eb02 024e add.w r2, r2, lr, lsl #1 +100008c4: 3208 adds r2, #8 +100008c6: 443a add r2, r7 +100008c8: ebac 0c03 sub.w ip, ip, r3 +100008cc: 4462 add r2, ip +100008ce: f3c2 024a ubfx r2, r2, #1, #11 +100008d2: ea6f 42c2 mvn.w r2, r2, lsl #19 +100008d6: ea6f 42d2 mvn.w r2, r2, lsr #19 +100008da: 809a strh r2, [r3, #4] +100008dc: 4b1e ldr r3, [pc, #120] @ (10000958 ) +100008de: 4421 add r1, r4 +100008e0: 781a ldrb r2, [r3, #0] +100008e2: eb07 0181 add.w r1, r7, r1, lsl #2 +100008e6: 701c strb r4, [r3, #0] +100008e8: 718a strb r2, [r1, #6] +100008ea: e79d b.n 10000828 +100008ec: 4673 mov r3, lr +100008ee: b9d9 cbnz r1, 10000928 +100008f0: 22ff movs r2, #255 @ 0xff +100008f2: f88e 2006 strb.w r2, [lr, #6] +100008f6: f64b 5201 movw r2, #48385 @ 0xbd01 +100008fa: f8ae 2004 strh.w r2, [lr, #4] +100008fe: 4c16 ldr r4, [pc, #88] @ (10000958 ) +10000900: f64a 22aa movw r2, #43690 @ 0xaaaa +10000904: f894 c000 ldrb.w ip, [r4] +10000908: 4619 mov r1, r3 +1000090a: 1bc9 subs r1, r1, r7 +1000090c: 4149 adcs r1, r1 +1000090e: 434a muls r2, r1 +10000910: 0d12 lsrs r2, r2, #20 +10000912: f883 c006 strb.w ip, [r3, #6] +10000916: 7022 strb r2, [r4, #0] +10000918: e786 b.n 10000828 +1000091a: 4a10 ldr r2, [pc, #64] @ (1000095c ) +1000091c: e7dd b.n 100008da +1000091e: f99e 4006 ldrsb.w r4, [lr, #6] +10000922: 4673 mov r3, lr +10000924: 2c00 cmp r4, #0 +10000926: daaa bge.n 1000087e +10000928: 4a0d ldr r2, [pc, #52] @ (10000960 ) +1000092a: 4c0e ldr r4, [pc, #56] @ (10000964 ) +1000092c: 1ad2 subs r2, r2, r3 +1000092e: 3a08 subs r2, #8 +10000930: f3c2 310a ubfx r1, r2, #12, #11 +10000934: ea6f 5101 mvn.w r1, r1, lsl #20 +10000938: ea6f 5111 mvn.w r1, r1, lsr #20 +1000093c: ea44 0252 orr.w r2, r4, r2, lsr #1 +10000940: 80da strh r2, [r3, #6] +10000942: 8099 strh r1, [r3, #4] +10000944: e770 b.n 10000828 +10000946: bf00 nop +10000948: 200007b9 .word 0x200007b9 +1000094c: e000ed00 .word 0xe000ed00 +10000950: 10000111 .word 0x10000111 +10000954: 200005ac .word 0x200005ac +10000958: 20000858 .word 0x20000858 +1000095c: ffffbd01 .word 0xffffbd01 +10000960: 200005e6 .word 0x200005e6 +10000964: fffff800 .word 0xfffff800 + +10000968 : +10000968: b5f0 push {r4, r5, r6, r7, lr} +1000096a: f3ef 8505 mrs r5, IPSR +1000096e: b2ed uxtb r5, r5 +10000970: f3ef 8c10 mrs ip, PRIMASK +10000974: b672 cpsid i +10000976: 4926 ldr r1, [pc, #152] @ (10000a10 ) +10000978: e8d1 2fcf ldaexb r2, [r1] +1000097c: 2301 movs r3, #1 +1000097e: 2a00 cmp r2, #0 +10000980: d1fa bne.n 10000978 +10000982: e8c1 3f42 strexb r2, r3, [r1] +10000986: 2a00 cmp r2, #0 +10000988: d1f6 bne.n 10000978 +1000098a: f3bf 8f5f dmb sy +1000098e: 4e21 ldr r6, [pc, #132] @ (10000a14 ) +10000990: f040 0e01 orr.w lr, r0, #1 +10000994: 68b4 ldr r4, [r6, #8] +10000996: f64a 23aa movw r3, #43690 @ 0xaaaa +1000099a: f854 7025 ldr.w r7, [r4, r5, lsl #2] +1000099e: 4a1e ldr r2, [pc, #120] @ (10000a18 ) +100009a0: 4604 mov r4, r0 +100009a2: 1aa4 subs r4, r4, r2 +100009a4: 4164 adcs r4, r4 +100009a6: 4363 muls r3, r4 +100009a8: 0d1b lsrs r3, r3, #20 +100009aa: 4577 cmp r7, lr +100009ac: b25b sxtb r3, r3 +100009ae: d01b beq.n 100009e8 +100009b0: f992 4006 ldrsb.w r4, [r2, #6] +100009b4: 429c cmp r4, r3 +100009b6: d01c beq.n 100009f2 +100009b8: f992 4012 ldrsb.w r4, [r2, #18] +100009bc: 429c cmp r4, r3 +100009be: d023 beq.n 10000a08 +100009c0: f992 401e ldrsb.w r4, [r2, #30] +100009c4: 429c cmp r4, r3 +100009c6: d021 beq.n 10000a0c +100009c8: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +100009cc: 429c cmp r4, r3 +100009ce: bf08 it eq +100009d0: 2403 moveq r4, #3 +100009d2: d00f beq.n 100009f4 +100009d4: 4a11 ldr r2, [pc, #68] @ (10000a1c ) +100009d6: 2400 movs r4, #0 +100009d8: 7815 ldrb r5, [r2, #0] +100009da: 7013 strb r3, [r2, #0] +100009dc: 7185 strb r5, [r0, #6] +100009de: e8c1 4f8f stlb r4, [r1] +100009e2: f38c 8810 msr PRIMASK, ip +100009e6: bdf0 pop {r4, r5, r6, r7, pc} +100009e8: 68b2 ldr r2, [r6, #8] +100009ea: 4c0d ldr r4, [pc, #52] @ (10000a20 ) +100009ec: f842 4025 str.w r4, [r2, r5, lsl #2] +100009f0: e7f0 b.n 100009d4 +100009f2: 2400 movs r4, #0 +100009f4: eb04 0444 add.w r4, r4, r4, lsl #1 +100009f8: eb02 0284 add.w r2, r2, r4, lsl #2 +100009fc: 24ff movs r4, #255 @ 0xff +100009fe: 7194 strb r4, [r2, #6] +10000a00: f64b 5401 movw r4, #48385 @ 0xbd01 +10000a04: 8094 strh r4, [r2, #4] +10000a06: e7e5 b.n 100009d4 +10000a08: 2401 movs r4, #1 +10000a0a: e7f3 b.n 100009f4 +10000a0c: 2402 movs r4, #2 +10000a0e: e7f1 b.n 100009f4 +10000a10: 200007b9 .word 0x200007b9 +10000a14: e000ed00 .word 0xe000ed00 +10000a18: 200005ac .word 0x200005ac +10000a1c: 20000858 .word 0x20000858 +10000a20: 10000111 .word 0x10000111 + +10000a24 : +10000a24: 4b01 ldr r3, [pc, #4] @ (10000a2c ) +10000a26: 440b add r3, r1 +10000a28: 6003 str r3, [r0, #0] +10000a2a: 4770 bx lr +10000a2c: 200007b0 .word 0x200007b0 + +10000a30 : +10000a30: b570 push {r4, r5, r6, lr} +10000a32: 4c10 ldr r4, [pc, #64] @ (10000a74 ) +10000a34: 4d10 ldr r5, [pc, #64] @ (10000a78 ) +10000a36: 42ac cmp r4, r5 +10000a38: d20e bcs.n 10000a58 +10000a3a: 26ff movs r6, #255 @ 0xff +10000a3c: 6823 ldr r3, [r4, #0] +10000a3e: b163 cbz r3, 10000a5a +10000a40: f7ff fe12 bl 10000668 +10000a44: 4601 mov r1, r0 +10000a46: 4620 mov r0, r4 +10000a48: f7ff ffec bl 10000a24 +10000a4c: 80a6 strh r6, [r4, #4] +10000a4e: f3bf 8f5f dmb sy +10000a52: 3408 adds r4, #8 +10000a54: 42ac cmp r4, r5 +10000a56: d3f1 bcc.n 10000a3c +10000a58: bd70 pop {r4, r5, r6, pc} +10000a5a: f7ff fe05 bl 10000668 +10000a5e: 4601 mov r1, r0 +10000a60: 4620 mov r0, r4 +10000a62: f7ff ffdf bl 10000a24 +10000a66: 7126 strb r6, [r4, #4] +10000a68: f3bf 8f5f dmb sy +10000a6c: 3408 adds r4, #8 +10000a6e: 42ac cmp r4, r5 +10000a70: d3e4 bcc.n 10000a3c +10000a72: bd70 pop {r4, r5, r6, pc} +10000a74: 20000624 .word 0x20000624 +10000a78: 2000062c .word 0x2000062c + +10000a7c : +10000a7c: 4b0d ldr r3, [pc, #52] @ (10000ab4 ) +10000a7e: 681a ldr r2, [r3, #0] +10000a80: f3ef 8110 mrs r1, PRIMASK +10000a84: b672 cpsid i +10000a86: e8d2 cfcf ldaexb ip, [r2] +10000a8a: 2001 movs r0, #1 +10000a8c: f1bc 0f00 cmp.w ip, #0 +10000a90: d1f9 bne.n 10000a86 +10000a92: e8c2 0f4c strexb ip, r0, [r2] +10000a96: f1bc 0f00 cmp.w ip, #0 +10000a9a: d1f4 bne.n 10000a86 +10000a9c: f3bf 8f5f dmb sy +10000aa0: 2200 movs r2, #0 +10000aa2: 681b ldr r3, [r3, #0] +10000aa4: e8c3 2f8f stlb r2, [r3] +10000aa8: f381 8810 msr PRIMASK, r1 +10000aac: bf40 sev +10000aae: 2000 movs r0, #0 +10000ab0: 2100 movs r1, #0 +10000ab2: 4770 bx lr +10000ab4: 2000084c .word 0x2000084c + +10000ab8 : +10000ab8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000abc: ed2d 8b02 vpush {d8} +10000ac0: b085 sub sp, #20 +10000ac2: f3ef 8305 mrs r3, IPSR +10000ac6: b2db uxtb r3, r3 +10000ac8: 3b10 subs r3, #16 +10000aca: 089a lsrs r2, r3, #2 +10000acc: bf18 it ne +10000ace: 2201 movne r2, #1 +10000ad0: f04f 0101 mov.w r1, #1 +10000ad4: f003 0b03 and.w fp, r3, #3 +10000ad8: bf18 it ne +10000ada: 4daf ldrne r5, [pc, #700] @ (10000d98 ) +10000adc: 4baf ldr r3, [pc, #700] @ (10000d9c ) +10000ade: bf08 it eq +10000ae0: 4daf ldreq r5, [pc, #700] @ (10000da0 ) +10000ae2: eb0b 0282 add.w r2, fp, r2, lsl #2 +10000ae6: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000aea: fa01 f20b lsl.w r2, r1, fp +10000aee: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10000af2: ed9f 8ba7 vldr d8, [pc, #668] @ 10000d90 +10000af6: 9201 str r2, [sp, #4] +10000af8: 605a str r2, [r3, #4] +10000afa: e02f b.n 10000b5c +10000afc: 88b3 ldrh r3, [r6, #4] +10000afe: 041c lsls r4, r3, #16 +10000b00: f140 8093 bpl.w 10000c2a +10000b04: 79b3 ldrb r3, [r6, #6] +10000b06: 2b00 cmp r3, #0 +10000b08: f040 80dd bne.w 10000cc6 +10000b0c: f9b6 2008 ldrsh.w r2, [r6, #8] +10000b10: 2a00 cmp r2, #0 +10000b12: f2c0 811e blt.w 10000d52 +10000b16: 6973 ldr r3, [r6, #20] +10000b18: eb02 0242 add.w r2, r2, r2, lsl #1 +10000b1c: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000b20: e9d3 4702 ldrd r4, r7, [r3, #8] +10000b24: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000b28: bf08 it eq +10000b2a: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000b2e: d00e beq.n 10000b4e +10000b30: eb05 018b add.w r1, r5, fp, lsl #2 +10000b34: 6aab ldr r3, [r5, #40] @ 0x28 +10000b36: 690a ldr r2, [r1, #16] +10000b38: 1ad2 subs r2, r2, r3 +10000b3a: 1ae3 subs r3, r4, r3 +10000b3c: 4293 cmp r3, r2 +10000b3e: d305 bcc.n 10000b4c +10000b40: 2301 movs r3, #1 +10000b42: 6a2a ldr r2, [r5, #32] +10000b44: fa03 f30b lsl.w r3, r3, fp +10000b48: 4213 tst r3, r2 +10000b4a: d100 bne.n 10000b4e +10000b4c: 610c str r4, [r1, #16] +10000b4e: 4628 mov r0, r5 +10000b50: f000 fb38 bl 100011c4 +10000b54: 42a0 cmp r0, r4 +10000b56: 41b9 sbcs r1, r7 +10000b58: f2c0 80fb blt.w 10000d52 +10000b5c: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b60: 9a01 ldr r2, [sp, #4] +10000b62: 2b00 cmp r3, #0 +10000b64: 9300 str r3, [sp, #0] +10000b66: 63ea str r2, [r5, #60] @ 0x3c +10000b68: dbc8 blt.n 10000afc +10000b6a: f8d6 8014 ldr.w r8, [r6, #20] +10000b6e: eb03 0943 add.w r9, r3, r3, lsl #1 +10000b72: 4628 mov r0, r5 +10000b74: eb08 07c9 add.w r7, r8, r9, lsl #3 +10000b78: e9d7 4a02 ldrd r4, sl, [r7, #8] +10000b7c: f000 fb22 bl 100011c4 +10000b80: 42a0 cmp r0, r4 +10000b82: eb71 010a sbcs.w r1, r1, sl +10000b86: dbb9 blt.n 10000afc +10000b88: f1ba 0f00 cmp.w sl, #0 +10000b8c: f2c0 80c3 blt.w 10000d16 +10000b90: e9d7 3104 ldrd r3, r1, [r7, #16] +10000b94: 4a83 ldr r2, [pc, #524] @ (10000da4 ) +10000b96: 4293 cmp r3, r2 +10000b98: f000 80ed beq.w 10000d76 +10000b9c: 887a ldrh r2, [r7, #2] +10000b9e: f9b6 0008 ldrsh.w r0, [r6, #8] +10000ba2: b292 uxth r2, r2 +10000ba4: ea42 4000 orr.w r0, r2, r0, lsl #16 +10000ba8: 4798 blx r3 +10000baa: 4602 mov r2, r0 +10000bac: 460b mov r3, r1 +10000bae: ea52 0103 orrs.w r1, r2, r3 +10000bb2: f000 80b0 beq.w 10000d16 +10000bb6: 2b00 cmp r3, #0 +10000bb8: f280 80d1 bge.w 10000d5e +10000bbc: ebb4 0e02 subs.w lr, r4, r2 +10000bc0: eb6a 0a03 sbc.w sl, sl, r3 +10000bc4: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000bc8: e9c7 ea02 strd lr, sl, [r7, #8] +10000bcc: 2b00 cmp r3, #0 +10000bce: db95 blt.n 10000afc +10000bd0: 6971 ldr r1, [r6, #20] +10000bd2: eb03 0243 add.w r2, r3, r3, lsl #1 +10000bd6: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000bda: e9d2 7002 ldrd r7, r0, [r2, #8] +10000bde: 45be cmp lr, r7 +10000be0: eb7a 0c00 sbcs.w ip, sl, r0 +10000be4: ea4f 0243 mov.w r2, r3, lsl #1 +10000be8: db88 blt.n 10000afc +10000bea: 46b4 mov ip, r6 +10000bec: f82c 3f08 strh.w r3, [ip, #8]! +10000bf0: e006 b.n 10000c00 +10000bf2: eb03 0043 add.w r0, r3, r3, lsl #1 +10000bf6: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000bfa: 005a lsls r2, r3, #1 +10000bfc: e9d0 7002 ldrd r7, r0, [r0, #8] +10000c00: 45be cmp lr, r7 +10000c02: 441a add r2, r3 +10000c04: eb7a 0000 sbcs.w r0, sl, r0 +10000c08: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000c0c: db04 blt.n 10000c18 +10000c0e: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000c12: 46a4 mov ip, r4 +10000c14: 2b00 cmp r3, #0 +10000c16: daec bge.n 10000bf2 +10000c18: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000c1c: 9b00 ldr r3, [sp, #0] +10000c1e: f8ac 3000 strh.w r3, [ip] +10000c22: 88b3 ldrh r3, [r6, #4] +10000c24: 041c lsls r4, r3, #16 +10000c26: f53f af6d bmi.w 10000b04 +10000c2a: 6933 ldr r3, [r6, #16] +10000c2c: f3ef 8210 mrs r2, PRIMASK +10000c30: b672 cpsid i +10000c32: e8d3 0fcf ldaexb r0, [r3] +10000c36: 2101 movs r1, #1 +10000c38: 2800 cmp r0, #0 +10000c3a: d1fa bne.n 10000c32 +10000c3c: e8c3 1f40 strexb r0, r1, [r3] +10000c40: 2800 cmp r0, #0 +10000c42: d1f6 bne.n 10000c32 +10000c44: f3bf 8f5f dmb sy +10000c48: f64f 74ff movw r4, #65535 @ 0xffff +10000c4c: 88b0 ldrh r0, [r6, #4] +10000c4e: 2300 movs r3, #0 +10000c50: 6931 ldr r1, [r6, #16] +10000c52: b200 sxth r0, r0 +10000c54: 80b4 strh r4, [r6, #4] +10000c56: e8c1 3f8f stlb r3, [r1] +10000c5a: f382 8810 msr PRIMASK, r2 +10000c5e: 4298 cmp r0, r3 +10000c60: f6ff af50 blt.w 10000b04 +10000c64: 4607 mov r7, r0 +10000c66: 46a9 mov r9, r5 +10000c68: 6974 ldr r4, [r6, #20] +10000c6a: f106 0808 add.w r8, r6, #8 +10000c6e: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000c72: eb04 03ce add.w r3, r4, lr, lsl #3 +10000c76: e9d3 5002 ldrd r5, r0, [r3, #8] +10000c7a: f9b6 3008 ldrsh.w r3, [r6, #8] +10000c7e: 46c4 mov ip, r8 +10000c80: 2b00 cmp r3, #0 +10000c82: db13 blt.n 10000cac +10000c84: 46b2 mov sl, r6 +10000c86: 9700 str r7, [sp, #0] +10000c88: e004 b.n 10000c94 +10000c8a: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000c8e: 4694 mov ip, r2 +10000c90: 2b00 cmp r3, #0 +10000c92: db09 blt.n 10000ca8 +10000c94: eb03 0643 add.w r6, r3, r3, lsl #1 +10000c98: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000c9c: e9d2 7102 ldrd r7, r1, [r2, #8] +10000ca0: 42bd cmp r5, r7 +10000ca2: eb70 0101 sbcs.w r1, r0, r1 +10000ca6: daf0 bge.n 10000c8a +10000ca8: 4656 mov r6, sl +10000caa: 9f00 ldr r7, [sp, #0] +10000cac: f8ac 7000 strh.w r7, [ip] +10000cb0: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000cb4: f824 303e strh.w r3, [r4, lr, lsl #3] +10000cb8: 2f00 cmp r7, #0 +10000cba: dad8 bge.n 10000c6e +10000cbc: 79b3 ldrb r3, [r6, #6] +10000cbe: 464d mov r5, r9 +10000cc0: 2b00 cmp r3, #0 +10000cc2: f43f af23 beq.w 10000b0c +10000cc6: 2300 movs r3, #0 +10000cc8: 71b3 strb r3, [r6, #6] +10000cca: f9b6 3008 ldrsh.w r3, [r6, #8] +10000cce: f106 0808 add.w r8, r6, #8 +10000cd2: 1c58 adds r0, r3, #1 +10000cd4: d03d beq.n 10000d52 +10000cd6: 461a mov r2, r3 +10000cd8: 6977 ldr r7, [r6, #20] +10000cda: e003 b.n 10000ce4 +10000cdc: 4680 mov r8, r0 +10000cde: 1c59 adds r1, r3, #1 +10000ce0: f43f af16 beq.w 10000b10 +10000ce4: eb03 0143 add.w r1, r3, r3, lsl #1 +10000ce8: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000cec: f8b0 c002 ldrh.w ip, [r0, #2] +10000cf0: 461c mov r4, r3 +10000cf2: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000cf6: 469e mov lr, r3 +10000cf8: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000cfc: d0ee beq.n 10000cdc +10000cfe: 4294 cmp r4, r2 +10000d00: ed80 8b02 vstr d8, [r0, #8] +10000d04: d005 beq.n 10000d12 +10000d06: f8a8 3000 strh.w r3, [r8] +10000d0a: 8932 ldrh r2, [r6, #8] +10000d0c: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000d10: 8134 strh r4, [r6, #8] +10000d12: 4672 mov r2, lr +10000d14: e7e3 b.n 10000cde +10000d16: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000d1a: 8133 strh r3, [r6, #8] +10000d1c: 6933 ldr r3, [r6, #16] +10000d1e: f3ef 8210 mrs r2, PRIMASK +10000d22: b672 cpsid i +10000d24: e8d3 0fcf ldaexb r0, [r3] +10000d28: 2101 movs r1, #1 +10000d2a: 2800 cmp r0, #0 +10000d2c: d1fa bne.n 10000d24 +10000d2e: e8c3 1f40 strexb r0, r1, [r3] +10000d32: 2800 cmp r0, #0 +10000d34: d1f6 bne.n 10000d24 +10000d36: f3bf 8f5f dmb sy +10000d3a: 8873 ldrh r3, [r6, #2] +10000d3c: 6931 ldr r1, [r6, #16] +10000d3e: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000d42: 9b00 ldr r3, [sp, #0] +10000d44: 8073 strh r3, [r6, #2] +10000d46: 2300 movs r3, #0 +10000d48: e8c1 3f8f stlb r3, [r1] +10000d4c: f382 8810 msr PRIMASK, r2 +10000d50: e6d4 b.n 10000afc +10000d52: bf40 sev +10000d54: b005 add sp, #20 +10000d56: ecbd 8b02 vpop {d8} +10000d5a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000d5e: 4628 mov r0, r5 +10000d60: e9cd 2302 strd r2, r3, [sp, #8] +10000d64: f000 fa2e bl 100011c4 +10000d68: 9a02 ldr r2, [sp, #8] +10000d6a: 9b03 ldr r3, [sp, #12] +10000d6c: eb10 0e02 adds.w lr, r0, r2 +10000d70: eb43 0a01 adc.w sl, r3, r1 +10000d74: e726 b.n 10000bc4 +10000d76: 4608 mov r0, r1 +10000d78: 690b ldr r3, [r1, #16] +10000d7a: 9102 str r1, [sp, #8] +10000d7c: 4798 blx r3 +10000d7e: 2800 cmp r0, #0 +10000d80: d0c9 beq.n 10000d16 +10000d82: 9902 ldr r1, [sp, #8] +10000d84: e9d1 2300 ldrd r2, r3, [r1] +10000d88: e711 b.n 10000bae +10000d8a: bf00 nop +10000d8c: f3af 8000 nop.w +10000d90: ffffffff .word 0xffffffff +10000d94: ffffffff .word 0xffffffff +10000d98: 400b8000 .word 0x400b8000 +10000d9c: 2000082c .word 0x2000082c +10000da0: 400b0000 .word 0x400b0000 +10000da4: 10000ab9 .word 0x10000ab9 + +10000da8 : +10000da8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000dac: 4c36 ldr r4, [pc, #216] @ (10000e88 ) +10000dae: 6925 ldr r5, [r4, #16] +10000db0: b12d cbz r5, 10000dbe +10000db2: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000db6: 210a movs r1, #10 +10000db8: 4834 ldr r0, [pc, #208] @ (10000e8c ) +10000dba: f7ff be33 b.w 10000a24 +10000dbe: f8df 80e4 ldr.w r8, [pc, #228] @ 10000ea4 +10000dc2: 2103 movs r1, #3 +10000dc4: 4640 mov r0, r8 +10000dc6: f000 f9eb bl 100011a0 +10000dca: 2603 movs r6, #3 +10000dcc: f8c4 800c str.w r8, [r4, #12] +10000dd0: f7ff fc4a bl 10000668 +10000dd4: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000dd8: 4b2d ldr r3, [pc, #180] @ (10000e90 ) +10000dda: 7026 strb r6, [r4, #0] +10000ddc: 4403 add r3, r0 +10000dde: 6123 str r3, [r4, #16] +10000de0: f8dc 3000 ldr.w r3, [ip] +10000de4: 210f movs r1, #15 +10000de6: 7063 strb r3, [r4, #1] +10000de8: 6963 ldr r3, [r4, #20] +10000dea: 8061 strh r1, [r4, #2] +10000dec: 831d strh r5, [r3, #24] +10000dee: f04f 0504 mov.w r5, #4 +10000df2: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000df6: f04f 0505 mov.w r5, #5 +10000dfa: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000dfe: f04f 0506 mov.w r5, #6 +10000e02: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000e06: f04f 0507 mov.w r5, #7 +10000e0a: 210e movs r1, #14 +10000e0c: f64f 72ff movw r2, #65535 @ 0xffff +10000e10: 2708 movs r7, #8 +10000e12: f04f 0e0a mov.w lr, #10 +10000e16: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000e1a: f04f 0901 mov.w r9, #1 +10000e1e: f04f 0c0c mov.w ip, #12 +10000e22: f04f 0b02 mov.w fp, #2 +10000e26: f04f 0a09 mov.w sl, #9 +10000e2a: 200d movs r0, #13 +10000e2c: f04f 050b mov.w r5, #11 +10000e30: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000e34: 4917 ldr r1, [pc, #92] @ (10000e94 ) +10000e36: 80a2 strh r2, [r4, #4] +10000e38: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000e3c: 60a1 str r1, [r4, #8] +10000e3e: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000e42: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000e46: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000e4a: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000e4e: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000e52: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000e56: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000e5a: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000e5e: 801a strh r2, [r3, #0] +10000e60: 4b0d ldr r3, [pc, #52] @ (10000e98 ) +10000e62: 4630 mov r0, r6 +10000e64: f8c8 7020 str.w r7, [r8, #32] +10000e68: 490c ldr r1, [pc, #48] @ (10000e9c ) +10000e6a: 60dc str r4, [r3, #12] +10000e6c: f7ff fc52 bl 10000714 +10000e70: 4649 mov r1, r9 +10000e72: 4630 mov r0, r6 +10000e74: f7ff fc38 bl 100006e8 +10000e78: 4b09 ldr r3, [pc, #36] @ (10000ea0 ) +10000e7a: 210a movs r1, #10 +10000e7c: 641f str r7, [r3, #64] @ 0x40 +10000e7e: 4803 ldr r0, [pc, #12] @ (10000e8c ) +10000e80: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000e84: f7ff bdce b.w 10000a24 +10000e88: 200005f4 .word 0x200005f4 +10000e8c: 2000084c .word 0x2000084c +10000e90: 200007b0 .word 0x200007b0 +10000e94: 0010ffff .word 0x0010ffff +10000e98: 2000082c .word 0x2000082c +10000e9c: 10000ab9 .word 0x10000ab9 +10000ea0: 400b2000 .word 0x400b2000 +10000ea4: 400b0000 .word 0x400b0000 + +10000ea8 : +10000ea8: 4601 mov r1, r0 +10000eaa: b5f0 push {r4, r5, r6, r7, lr} +10000eac: 6900 ldr r0, [r0, #16] +10000eae: f3ef 8710 mrs r7, PRIMASK +10000eb2: b672 cpsid i +10000eb4: e8d0 5fcf ldaexb r5, [r0] +10000eb8: 2401 movs r4, #1 +10000eba: 2d00 cmp r5, #0 +10000ebc: d1fa bne.n 10000eb4 +10000ebe: e8c0 4f45 strexb r5, r4, [r0] +10000ec2: 2d00 cmp r5, #0 +10000ec4: d1f6 bne.n 10000eb4 +10000ec6: f3bf 8f5f dmb sy +10000eca: f9b1 e002 ldrsh.w lr, [r1, #2] +10000ece: 694c ldr r4, [r1, #20] +10000ed0: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000ed4: f1be 0f00 cmp.w lr, #0 +10000ed8: ea4f 05cc mov.w r5, ip, lsl #3 +10000edc: 6908 ldr r0, [r1, #16] +10000ede: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000ee2: db3c blt.n 10000f5e +10000ee4: 5b66 ldrh r6, [r4, r5] +10000ee6: 804e strh r6, [r1, #2] +10000ee8: 2600 movs r6, #0 +10000eea: e8c0 6f8f stlb r6, [r0] +10000eee: f387 8810 msr PRIMASK, r7 +10000ef2: f8bc 0002 ldrh.w r0, [ip, #2] +10000ef6: e9cc 2302 strd r2, r3, [ip, #8] +10000efa: 3001 adds r0, #1 +10000efc: f3c0 000e ubfx r0, r0, #0, #15 +10000f00: 2801 cmp r0, #1 +10000f02: bf38 it cc +10000f04: 2001 movcc r0, #1 +10000f06: 9b05 ldr r3, [sp, #20] +10000f08: f8ac 0002 strh.w r0, [ip, #2] +10000f0c: f8cc 3010 str.w r3, [ip, #16] +10000f10: 9b06 ldr r3, [sp, #24] +10000f12: ea40 400e orr.w r0, r0, lr, lsl #16 +10000f16: f8cc 3014 str.w r3, [ip, #20] +10000f1a: 690b ldr r3, [r1, #16] +10000f1c: f3ef 8210 mrs r2, PRIMASK +10000f20: b672 cpsid i +10000f22: e8d3 cfcf ldaexb ip, [r3] +10000f26: 2701 movs r7, #1 +10000f28: f1bc 0f00 cmp.w ip, #0 +10000f2c: d1f9 bne.n 10000f22 +10000f2e: e8c3 7f4c strexb ip, r7, [r3] +10000f32: f1bc 0f00 cmp.w ip, #0 +10000f36: d1f4 bne.n 10000f22 +10000f38: f3bf 8f5f dmb sy +10000f3c: 888b ldrh r3, [r1, #4] +10000f3e: 5363 strh r3, [r4, r5] +10000f40: f8a1 e004 strh.w lr, [r1, #4] +10000f44: 690b ldr r3, [r1, #16] +10000f46: e8c3 6f8f stlb r6, [r3] +10000f4a: f382 8810 msr PRIMASK, r2 +10000f4e: 2201 movs r2, #1 +10000f50: 68cb ldr r3, [r1, #12] +10000f52: 7809 ldrb r1, [r1, #0] +10000f54: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000f58: 408a lsls r2, r1 +10000f5a: 605a str r2, [r3, #4] +10000f5c: bdf0 pop {r4, r5, r6, r7, pc} +10000f5e: 2300 movs r3, #0 +10000f60: e8c0 3f8f stlb r3, [r0] +10000f64: f387 8810 msr PRIMASK, r7 +10000f68: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000f6c: bdf0 pop {r4, r5, r6, r7, pc} +10000f6e: bf00 nop + +10000f70 : +10000f70: 4603 mov r3, r0 +10000f72: 8940 ldrh r0, [r0, #10] +10000f74: ebb0 4f21 cmp.w r0, r1, asr #16 +10000f78: dd37 ble.n 10000fea +10000f7a: 6958 ldr r0, [r3, #20] +10000f7c: 140a asrs r2, r1, #16 +10000f7e: eb02 0242 add.w r2, r2, r2, lsl #1 +10000f82: b510 push {r4, lr} +10000f84: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000f88: 691c ldr r4, [r3, #16] +10000f8a: f3ef 8c10 mrs ip, PRIMASK +10000f8e: b672 cpsid i +10000f90: e8d4 efcf ldaexb lr, [r4] +10000f94: 2201 movs r2, #1 +10000f96: f1be 0f00 cmp.w lr, #0 +10000f9a: d1f9 bne.n 10000f90 +10000f9c: e8c4 2f4e strexb lr, r2, [r4] +10000fa0: f1be 0f00 cmp.w lr, #0 +10000fa4: d1f4 bne.n 10000f90 +10000fa6: f3bf 8f5f dmb sy +10000faa: 8842 ldrh r2, [r0, #2] +10000fac: b289 uxth r1, r1 +10000fae: b292 uxth r2, r2 +10000fb0: 428a cmp r2, r1 +10000fb2: d007 beq.n 10000fc4 +10000fb4: 2200 movs r2, #0 +10000fb6: 691b ldr r3, [r3, #16] +10000fb8: e8c3 2f8f stlb r2, [r3] +10000fbc: f38c 8810 msr PRIMASK, ip +10000fc0: 2000 movs r0, #0 +10000fc2: bd10 pop {r4, pc} +10000fc4: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000fc8: 8042 strh r2, [r0, #2] +10000fca: 2101 movs r1, #1 +10000fcc: 2200 movs r2, #0 +10000fce: 6918 ldr r0, [r3, #16] +10000fd0: 7199 strb r1, [r3, #6] +10000fd2: e8c0 2f8f stlb r2, [r0] +10000fd6: f38c 8810 msr PRIMASK, ip +10000fda: 781c ldrb r4, [r3, #0] +10000fdc: 68da ldr r2, [r3, #12] +10000fde: 4608 mov r0, r1 +10000fe0: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000fe4: 40a1 lsls r1, r4 +10000fe6: 6059 str r1, [r3, #4] +10000fe8: bd10 pop {r4, pc} +10000fea: 2000 movs r0, #0 +10000fec: 4770 bx lr +10000fee: bf00 nop + +10000ff0 : +10000ff0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000ff4: b082 sub sp, #8 +10000ff6: 4606 mov r6, r0 +10000ff8: f000 f8ec bl 100011d4 +10000ffc: f44f 737a mov.w r3, #1000 @ 0x3e8 +10001000: 4604 mov r4, r0 +10001002: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10001006: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +1000100a: fbe6 4103 umlal r4, r1, r6, r3 +1000100e: 42a0 cmp r0, r4 +10001010: eb72 0301 sbcs.w r3, r2, r1 +10001014: bf3a itte cc +10001016: 4604 movcc r4, r0 +10001018: 4615 movcc r5, r2 +1000101a: 460d movcs r5, r1 +1000101c: 1fa6 subs r6, r4, #6 +1000101e: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10001022: 42b4 cmp r4, r6 +10001024: eb75 0307 sbcs.w r3, r5, r7 +10001028: bf3c itt cc +1000102a: 2600 movcc r6, #0 +1000102c: 4637 movcc r7, r6 +1000102e: f000 f8d1 bl 100011d4 +10001032: 1a30 subs r0, r6, r0 +10001034: eb67 0101 sbc.w r1, r7, r1 +10001038: 2801 cmp r0, #1 +1000103a: f171 0100 sbcs.w r1, r1, #0 +1000103e: da06 bge.n 1000104e +10001040: 4620 mov r0, r4 +10001042: 4629 mov r1, r5 +10001044: b002 add sp, #8 +10001046: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +1000104a: f000 b8fb b.w 10001244 +1000104e: f000 f8c1 bl 100011d4 +10001052: 4286 cmp r6, r0 +10001054: eb67 0101 sbc.w r1, r7, r1 +10001058: 2900 cmp r1, #0 +1000105a: db0a blt.n 10001072 +1000105c: 2100 movs r1, #0 +1000105e: 4b17 ldr r3, [pc, #92] @ (100010bc ) +10001060: 4632 mov r2, r6 +10001062: 9300 str r3, [sp, #0] +10001064: 4816 ldr r0, [pc, #88] @ (100010c0 ) +10001066: 463b mov r3, r7 +10001068: 9101 str r1, [sp, #4] +1000106a: f7ff ff1d bl 10000ea8 +1000106e: 3001 adds r0, #1 +10001070: d0e6 beq.n 10001040 +10001072: f04f 0c00 mov.w ip, #0 +10001076: 4a13 ldr r2, [pc, #76] @ (100010c4 ) +10001078: 4913 ldr r1, [pc, #76] @ (100010c8 ) +1000107a: 6a53 ldr r3, [r2, #36] @ 0x24 +1000107c: 429f cmp r7, r3 +1000107e: d804 bhi.n 1000108a +10001080: 6a90 ldr r0, [r2, #40] @ 0x28 +10001082: 42b0 cmp r0, r6 +10001084: d2dc bcs.n 10001040 +10001086: 429f cmp r7, r3 +10001088: d1da bne.n 10001040 +1000108a: 680b ldr r3, [r1, #0] +1000108c: f3ef 8010 mrs r0, PRIMASK +10001090: b672 cpsid i +10001092: e8d3 8fcf ldaexb r8, [r3] +10001096: f05f 0e01 movs.w lr, #1 +1000109a: f1b8 0f00 cmp.w r8, #0 +1000109e: d1f8 bne.n 10001092 +100010a0: e8c3 ef48 strexb r8, lr, [r3] +100010a4: f1b8 0f00 cmp.w r8, #0 +100010a8: d1f3 bne.n 10001092 +100010aa: f3bf 8f5f dmb sy +100010ae: 680b ldr r3, [r1, #0] +100010b0: e8c3 cf8f stlb ip, [r3] +100010b4: f380 8810 msr PRIMASK, r0 +100010b8: bf20 wfe +100010ba: e7de b.n 1000107a +100010bc: 10000a7d .word 0x10000a7d +100010c0: 200005f4 .word 0x200005f4 +100010c4: 400b0000 .word 0x400b0000 +100010c8: 2000084c .word 0x2000084c + +100010cc : +100010cc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100010d0: 4606 mov r6, r0 +100010d2: 460d mov r5, r1 +100010d4: b083 sub sp, #12 +100010d6: f3ef 8405 mrs r4, IPSR +100010da: b2e4 uxtb r4, r4 +100010dc: b13c cbz r4, 100010ee +100010de: 4b2d ldr r3, [pc, #180] @ (10001194 ) +100010e0: 6a5a ldr r2, [r3, #36] @ 0x24 +100010e2: 42aa cmp r2, r5 +100010e4: d21c bcs.n 10001120 +100010e6: 2000 movs r0, #0 +100010e8: b003 add sp, #12 +100010ea: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100010ee: 4f2a ldr r7, [pc, #168] @ (10001198 ) +100010f0: f8d7 900c ldr.w r9, [r7, #12] +100010f4: f897 8000 ldrb.w r8, [r7] +100010f8: 4648 mov r0, r9 +100010fa: f000 f863 bl 100011c4 +100010fe: f108 0804 add.w r8, r8, #4 +10001102: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10001106: 1a1b subs r3, r3, r0 +10001108: 1a30 subs r0, r6, r0 +1000110a: eb65 0101 sbc.w r1, r5, r1 +1000110e: 4298 cmp r0, r3 +10001110: f171 0100 sbcs.w r1, r1, #0 +10001114: db10 blt.n 10001138 +10001116: bf20 wfe +10001118: 4b1e ldr r3, [pc, #120] @ (10001194 ) +1000111a: 6a5a ldr r2, [r3, #36] @ 0x24 +1000111c: 42aa cmp r2, r5 +1000111e: d3e2 bcc.n 100010e6 +10001120: bf14 ite ne +10001122: 2401 movne r4, #1 +10001124: 2400 moveq r4, #0 +10001126: 6a9b ldr r3, [r3, #40] @ 0x28 +10001128: 42b3 cmp r3, r6 +1000112a: bf34 ite cc +1000112c: 4620 movcc r0, r4 +1000112e: f044 0001 orrcs.w r0, r4, #1 +10001132: b003 add sp, #12 +10001134: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10001138: f000 f84c bl 100011d4 +1000113c: 4286 cmp r6, r0 +1000113e: eb65 0101 sbc.w r1, r5, r1 +10001142: 2900 cmp r1, #0 +10001144: db14 blt.n 10001170 +10001146: 4b15 ldr r3, [pc, #84] @ (1000119c ) +10001148: 4638 mov r0, r7 +1000114a: e9cd 3400 strd r3, r4, [sp] +1000114e: 4632 mov r2, r6 +10001150: 462b mov r3, r5 +10001152: f7ff fea9 bl 10000ea8 +10001156: 1e01 subs r1, r0, #0 +10001158: dd0a ble.n 10001170 +1000115a: 4b0e ldr r3, [pc, #56] @ (10001194 ) +1000115c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000115e: 42aa cmp r2, r5 +10001160: d316 bcc.n 10001190 +10001162: 6a9b ldr r3, [r3, #40] @ 0x28 +10001164: 42b3 cmp r3, r6 +10001166: d311 bcc.n 1000118c +10001168: 480b ldr r0, [pc, #44] @ (10001198 ) +1000116a: f7ff ff01 bl 10000f70 +1000116e: e7b6 b.n 100010de +10001170: 4b08 ldr r3, [pc, #32] @ (10001194 ) +10001172: 6a5c ldr r4, [r3, #36] @ 0x24 +10001174: 42ac cmp r4, r5 +10001176: d3b6 bcc.n 100010e6 +10001178: 1b64 subs r4, r4, r5 +1000117a: bf18 it ne +1000117c: 2401 movne r4, #1 +1000117e: 6a9b ldr r3, [r3, #40] @ 0x28 +10001180: 42b3 cmp r3, r6 +10001182: bf34 ite cc +10001184: 4620 movcc r0, r4 +10001186: f044 0001 orrcs.w r0, r4, #1 +1000118a: e7ad b.n 100010e8 +1000118c: 42aa cmp r2, r5 +1000118e: d1eb bne.n 10001168 +10001190: bf20 wfe +10001192: e7e9 b.n 10001168 +10001194: 400b0000 .word 0x400b0000 +10001198: 200005f4 .word 0x200005f4 +1000119c: 10000a7d .word 0x10000a7d + +100011a0 : +100011a0: b410 push {r4} +100011a2: 4b05 ldr r3, [pc, #20] @ (100011b8 ) +100011a4: 4c05 ldr r4, [pc, #20] @ (100011bc ) +100011a6: 4a06 ldr r2, [pc, #24] @ (100011c0 ) +100011a8: 42a0 cmp r0, r4 +100011aa: bf14 ite ne +100011ac: 4618 movne r0, r3 +100011ae: 1c58 addeq r0, r3, #1 +100011b0: f85d 4b04 ldr.w r4, [sp], #4 +100011b4: f7ff ba2c b.w 10000610 +100011b8: 200007d8 .word 0x200007d8 +100011bc: 400b8000 .word 0x400b8000 +100011c0: 10003964 .word 0x10003964 + +100011c4 : +100011c4: 4603 mov r3, r0 +100011c6: 6a41 ldr r1, [r0, #36] @ 0x24 +100011c8: 460a mov r2, r1 +100011ca: 6a98 ldr r0, [r3, #40] @ 0x28 +100011cc: 6a59 ldr r1, [r3, #36] @ 0x24 +100011ce: 428a cmp r2, r1 +100011d0: d1fa bne.n 100011c8 +100011d2: 4770 bx lr + +100011d4 : +100011d4: 4b03 ldr r3, [pc, #12] @ (100011e4 ) +100011d6: 6a59 ldr r1, [r3, #36] @ 0x24 +100011d8: 460a mov r2, r1 +100011da: 6a98 ldr r0, [r3, #40] @ 0x28 +100011dc: 6a59 ldr r1, [r3, #36] @ 0x24 +100011de: 4291 cmp r1, r2 +100011e0: d1fa bne.n 100011d8 +100011e2: 4770 bx lr +100011e4: 400b0000 .word 0x400b0000 + +100011e8 : +100011e8: b430 push {r4, r5} +100011ea: 4a15 ldr r2, [pc, #84] @ (10001240 ) +100011ec: 6a53 ldr r3, [r2, #36] @ 0x24 +100011ee: 469c mov ip, r3 +100011f0: 6a94 ldr r4, [r2, #40] @ 0x28 +100011f2: 6a53 ldr r3, [r2, #36] @ 0x24 +100011f4: 4563 cmp r3, ip +100011f6: d1fa bne.n 100011ee +100011f8: 1902 adds r2, r0, r4 +100011fa: 4159 adcs r1, r3 +100011fc: f04f 0500 mov.w r5, #0 +10001200: bf28 it cs +10001202: 2501 movcs r5, #1 +10001204: 4b0e ldr r3, [pc, #56] @ (10001240 ) +10001206: 6a5b ldr r3, [r3, #36] @ 0x24 +10001208: b1b5 cbz r5, 10001238 +1000120a: 1c5a adds r2, r3, #1 +1000120c: bf08 it eq +1000120e: 461a moveq r2, r3 +10001210: d008 beq.n 10001224 +10001212: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +10001216: 460a mov r2, r1 +10001218: 4809 ldr r0, [pc, #36] @ (10001240 ) +1000121a: 6a43 ldr r3, [r0, #36] @ 0x24 +1000121c: 428b cmp r3, r1 +1000121e: d3fc bcc.n 1000121a +10001220: 428b cmp r3, r1 +10001222: d107 bne.n 10001234 +10001224: 4906 ldr r1, [pc, #24] @ (10001240 ) +10001226: e002 b.n 1000122e +10001228: 6a48 ldr r0, [r1, #36] @ 0x24 +1000122a: 4298 cmp r0, r3 +1000122c: d102 bne.n 10001234 +1000122e: 6a88 ldr r0, [r1, #40] @ 0x28 +10001230: 4290 cmp r0, r2 +10001232: d3f9 bcc.n 10001228 +10001234: bc30 pop {r4, r5} +10001236: 4770 bx lr +10001238: 4299 cmp r1, r3 +1000123a: d8ed bhi.n 10001218 +1000123c: e7f0 b.n 10001220 +1000123e: bf00 nop +10001240: 400b0000 .word 0x400b0000 + +10001244 : +10001244: 4a07 ldr r2, [pc, #28] @ (10001264 ) +10001246: 6a53 ldr r3, [r2, #36] @ 0x24 +10001248: 4299 cmp r1, r3 +1000124a: d8fc bhi.n 10001246 +1000124c: 4299 cmp r1, r3 +1000124e: d107 bne.n 10001260 +10001250: 4b04 ldr r3, [pc, #16] @ (10001264 ) +10001252: e002 b.n 1000125a +10001254: 6a5a ldr r2, [r3, #36] @ 0x24 +10001256: 4291 cmp r1, r2 +10001258: d102 bne.n 10001260 +1000125a: 6a9a ldr r2, [r3, #40] @ 0x28 +1000125c: 4290 cmp r0, r2 +1000125e: d8f9 bhi.n 10001254 +10001260: 4770 bx lr +10001262: bf00 nop +10001264: 400b0000 .word 0x400b0000 + +10001268 : +10001268: b5f8 push {r3, r4, r5, r6, r7, lr} +1000126a: 4605 mov r5, r0 +1000126c: 2006 movs r0, #6 +1000126e: 460e mov r6, r1 +10001270: f000 f8e4 bl 1000143c +10001274: 2800 cmp r0, #0 +10001276: d042 beq.n 100012fe +10001278: 4a35 ldr r2, [pc, #212] @ (10001350 ) +1000127a: 4836 ldr r0, [pc, #216] @ (10001354 ) +1000127c: 4295 cmp r5, r2 +1000127e: bf14 ite ne +10001280: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +10001284: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10001288: 4b33 ldr r3, [pc, #204] @ (10001358 ) +1000128a: 4934 ldr r1, [pc, #208] @ (1000135c ) +1000128c: 6002 str r2, [r0, #0] +1000128e: 601a str r2, [r3, #0] +10001290: 688c ldr r4, [r1, #8] +10001292: ea32 0404 bics.w r4, r2, r4 +10001296: d1fb bne.n 10001290 +10001298: 4b2d ldr r3, [pc, #180] @ (10001350 ) +1000129a: f44f 7180 mov.w r1, #256 @ 0x100 +1000129e: 1aeb subs r3, r5, r3 +100012a0: fab3 f383 clz r3, r3 +100012a4: 4a2e ldr r2, [pc, #184] @ (10001360 ) +100012a6: 095b lsrs r3, r3, #5 +100012a8: 2006 movs r0, #6 +100012aa: f822 1013 strh.w r1, [r2, r3, lsl #1] +100012ae: f000 f8c5 bl 1000143c +100012b2: 00c3 lsls r3, r0, #3 +100012b4: fbb3 f3f6 udiv r3, r3, r6 +100012b8: 3301 adds r3, #1 +100012ba: 09da lsrs r2, r3, #7 +100012bc: d120 bne.n 10001300 +100012be: 2640 movs r6, #64 @ 0x40 +100012c0: 2101 movs r1, #1 +100012c2: 6269 str r1, [r5, #36] @ 0x24 +100012c4: 62aa str r2, [r5, #40] @ 0x28 +100012c6: 6b2f ldr r7, [r5, #48] @ 0x30 +100012c8: 07fb lsls r3, r7, #31 +100012ca: d422 bmi.n 10001312 +100012cc: 462b mov r3, r5 +100012ce: 2200 movs r2, #0 +100012d0: f853 1f2c ldr.w r1, [r3, #44]! +100012d4: 2006 movs r0, #6 +100012d6: f503 5480 add.w r4, r3, #4096 @ 0x1000 +100012da: 6022 str r2, [r4, #0] +100012dc: 632f str r7, [r5, #48] @ 0x30 +100012de: f000 f8ad bl 1000143c +100012e2: f240 3101 movw r1, #769 @ 0x301 +100012e6: 2203 movs r2, #3 +100012e8: 0080 lsls r0, r0, #2 +100012ea: fbb0 f0f6 udiv r0, r0, r6 +100012ee: 6aeb ldr r3, [r5, #44] @ 0x2c +100012f0: f083 0370 eor.w r3, r3, #112 @ 0x70 +100012f4: f003 037e and.w r3, r3, #126 @ 0x7e +100012f8: 6023 str r3, [r4, #0] +100012fa: 6329 str r1, [r5, #48] @ 0x30 +100012fc: 64aa str r2, [r5, #72] @ 0x48 +100012fe: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001300: f64f 71fe movw r1, #65534 @ 0xfffe +10001304: 428a cmp r2, r1 +10001306: d91b bls.n 10001340 +10001308: 4622 mov r2, r4 +1000130a: f64f 71ff movw r1, #65535 @ 0xffff +1000130e: 4e15 ldr r6, [pc, #84] @ (10001364 ) +10001310: e7d7 b.n 100012c2 +10001312: f240 3201 movw r2, #769 @ 0x301 +10001316: f505 5340 add.w r3, r5, #12288 @ 0x3000 +1000131a: 631a str r2, [r3, #48] @ 0x30 +1000131c: 6a6b ldr r3, [r5, #36] @ 0x24 +1000131e: 6aac ldr r4, [r5, #40] @ 0x28 +10001320: 2006 movs r0, #6 +10001322: eb04 1483 add.w r4, r4, r3, lsl #6 +10001326: f000 f889 bl 1000143c +1000132a: 4b0f ldr r3, [pc, #60] @ (10001368 ) +1000132c: 02a4 lsls r4, r4, #10 +1000132e: fba3 2300 umull r2, r3, r3, r0 +10001332: 0adb lsrs r3, r3, #11 +10001334: 2100 movs r1, #0 +10001336: fbb4 f0f3 udiv r0, r4, r3 +1000133a: f7ff ff55 bl 100011e8 +1000133e: e7c5 b.n 100012cc +10001340: f3c3 0345 ubfx r3, r3, #1, #6 +10001344: 4611 mov r1, r2 +10001346: eb03 1682 add.w r6, r3, r2, lsl #6 +1000134a: 461a mov r2, r3 +1000134c: e7b9 b.n 100012c2 +1000134e: bf00 nop +10001350: 40078000 .word 0x40078000 +10001354: 40022000 .word 0x40022000 +10001358: 40023000 .word 0x40023000 +1000135c: 40020000 .word 0x40020000 +10001360: 20000850 .word 0x20000850 +10001364: 003fffc0 .word 0x003fffc0 +10001368: 8f2b7b75 .word 0x8f2b7b75 + +1000136c : +1000136c: eb00 0c40 add.w ip, r0, r0, lsl #1 +10001370: ea4f 0c8c mov.w ip, ip, lsl #2 +10001374: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10001378: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +1000137c: b5f0 push {r4, r5, r6, r7, lr} +1000137e: 4616 mov r6, r2 +10001380: f8dc 2004 ldr.w r2, [ip, #4] +10001384: 1f05 subs r5, r0, #4 +10001386: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +1000138a: bf38 it cc +1000138c: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10001390: b2ed uxtb r5, r5 +10001392: bf38 it cc +10001394: f8cc 2004 strcc.w r2, [ip, #4] +10001398: 2d01 cmp r5, #1 +1000139a: d92a bls.n 100013f2 +1000139c: f44f 6700 mov.w r7, #2048 @ 0x800 +100013a0: 4c25 ldr r4, [pc, #148] @ (10001438 ) +100013a2: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100013a6: 6017 str r7, [r2, #0] +100013a8: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100013ac: b9b2 cbnz r2, 100013dc +100013ae: f8dc 2000 ldr.w r2, [ip] +100013b2: 2d01 cmp r5, #1 +100013b4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100013b8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100013bc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100013c0: 6032 str r2, [r6, #0] +100013c2: d92a bls.n 1000141a +100013c4: f44f 6100 mov.w r1, #2048 @ 0x800 +100013c8: f844 3020 str.w r3, [r4, r0, lsl #2] +100013cc: f44f 3380 mov.w r3, #65536 @ 0x10000 +100013d0: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +100013d4: 6011 str r1, [r2, #0] +100013d6: f8cc 3004 str.w r3, [ip, #4] +100013da: bdf0 pop {r4, r5, r6, r7, pc} +100013dc: 6967 ldr r7, [r4, #20] +100013de: fbb7 fef2 udiv lr, r7, r2 +100013e2: f10e 0e01 add.w lr, lr, #1 +100013e6: eb0e 0e4e add.w lr, lr, lr, lsl #1 +100013ea: f1be 0e03 subs.w lr, lr, #3 +100013ee: d2fc bcs.n 100013ea +100013f0: e7dd b.n 100013ae +100013f2: 2901 cmp r1, #1 +100013f4: d1d2 bne.n 1000139c +100013f6: 2403 movs r4, #3 +100013f8: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100013fc: 6014 str r4, [r2, #0] +100013fe: f8dc 2008 ldr.w r2, [ip, #8] +10001402: 07d2 lsls r2, r2, #31 +10001404: d5fb bpl.n 100013fe +10001406: f8dc 2000 ldr.w r2, [ip] +1000140a: 4c0b ldr r4, [pc, #44] @ (10001438 ) +1000140c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001410: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10001414: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001418: 6032 str r2, [r6, #0] +1000141a: 2201 movs r2, #1 +1000141c: f8dc 5000 ldr.w r5, [ip] +10001420: 404d eors r5, r1 +10001422: f005 0503 and.w r5, r5, #3 +10001426: 6035 str r5, [r6, #0] +10001428: fa02 f101 lsl.w r1, r2, r1 +1000142c: f8dc 2008 ldr.w r2, [ip, #8] +10001430: 420a tst r2, r1 +10001432: d0fb beq.n 1000142c +10001434: e7c6 b.n 100013c4 +10001436: bf00 nop +10001438: 200007dc .word 0x200007dc + +1000143c : +1000143c: 4b01 ldr r3, [pc, #4] @ (10001444 ) +1000143e: f853 0020 ldr.w r0, [r3, r0, lsl #2] +10001442: 4770 bx lr +10001444: 200007dc .word 0x200007dc + +10001448 : +10001448: b470 push {r4, r5, r6} +1000144a: 9d03 ldr r5, [sp, #12] +1000144c: 6804 ldr r4, [r0, #0] +1000144e: 032d lsls r5, r5, #12 +10001450: ea45 4503 orr.w r5, r5, r3, lsl #16 +10001454: 4b1b ldr r3, [pc, #108] @ (100014c4 ) +10001456: 2c00 cmp r4, #0 +10001458: fbb3 f3f1 udiv r3, r3, r1 +1000145c: fbb2 f6f3 udiv r6, r2, r3 +10001460: db1f blt.n 100014a2 +10001462: 4a19 ldr r2, [pc, #100] @ (100014c8 ) +10001464: 4b19 ldr r3, [pc, #100] @ (100014cc ) +10001466: 4290 cmp r0, r2 +10001468: bf14 ite ne +1000146a: f44f 4280 movne.w r2, #16384 @ 0x4000 +1000146e: f44f 4200 moveq.w r2, #32768 @ 0x8000 +10001472: 4c17 ldr r4, [pc, #92] @ (100014d0 ) +10001474: 601a str r2, [r3, #0] +10001476: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000147a: 601a str r2, [r3, #0] +1000147c: 68a3 ldr r3, [r4, #8] +1000147e: ea32 0303 bics.w r3, r2, r3 +10001482: d1fb bne.n 1000147c +10001484: 2221 movs r2, #33 @ 0x21 +10001486: f500 5340 add.w r3, r0, #12288 @ 0x3000 +1000148a: 3304 adds r3, #4 +1000148c: 6001 str r1, [r0, #0] +1000148e: 6086 str r6, [r0, #8] +10001490: 601a str r2, [r3, #0] +10001492: 6802 ldr r2, [r0, #0] +10001494: 2a00 cmp r2, #0 +10001496: dafc bge.n 10001492 +10001498: 2208 movs r2, #8 +1000149a: 60c5 str r5, [r0, #12] +1000149c: 601a str r2, [r3, #0] +1000149e: bc70 pop {r4, r5, r6} +100014a0: 4770 bx lr +100014a2: 6803 ldr r3, [r0, #0] +100014a4: f003 033f and.w r3, r3, #63 @ 0x3f +100014a8: 428b cmp r3, r1 +100014aa: d1da bne.n 10001462 +100014ac: 6883 ldr r3, [r0, #8] +100014ae: f3c3 030b ubfx r3, r3, #0, #12 +100014b2: 42b3 cmp r3, r6 +100014b4: d1d5 bne.n 10001462 +100014b6: 68c3 ldr r3, [r0, #12] +100014b8: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100014bc: 42ab cmp r3, r5 +100014be: d1d0 bne.n 10001462 +100014c0: e7ed b.n 1000149e +100014c2: bf00 nop +100014c4: 00b71b00 .word 0x00b71b00 +100014c8: 40058000 .word 0x40058000 +100014cc: 40022000 .word 0x40022000 +100014d0: 40020000 .word 0x40020000 + +100014d4 : +100014d4: 2301 movs r3, #1 +100014d6: eb00 0040 add.w r0, r0, r0, lsl #1 +100014da: 0080 lsls r0, r0, #2 +100014dc: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100014e0: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +100014e4: 6041 str r1, [r0, #4] +100014e6: 6003 str r3, [r0, #0] +100014e8: 4770 bx lr +100014ea: bf00 nop + +100014ec : +100014ec: 2300 movs r3, #0 +100014ee: 8adb ldrh r3, [r3, #22] +100014f0: 2200 movs r2, #0 +100014f2: e842 f200 tt r2, r2 +100014f6: 0252 lsls r2, r2, #9 +100014f8: d401 bmi.n 100014fe +100014fa: 2110 movs r1, #16 +100014fc: 4718 bx r3 +100014fe: 2104 movs r1, #4 +10001500: 4718 bx r3 +10001502: bf00 nop + +10001504 : +10001504: 4a03 ldr r2, [pc, #12] @ (10001514 ) +10001506: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +1000150a: 2b00 cmp r3, #0 +1000150c: d0fb beq.n 10001506 +1000150e: f3bf 8f5f dmb sy +10001512: 4770 bx lr +10001514: 400e0000 .word 0x400e0000 + +10001518 : +10001518: 2100 movs r1, #0 +1000151a: 4b04 ldr r3, [pc, #16] @ (1000152c ) +1000151c: 4a04 ldr r2, [pc, #16] @ (10001530 ) +1000151e: f3bf 8f5f dmb sy +10001522: f843 1b04 str.w r1, [r3], #4 +10001526: 4293 cmp r3, r2 +10001528: d1f9 bne.n 1000151e +1000152a: 4770 bx lr +1000152c: 400e080c .word 0x400e080c +10001530: 400e082c .word 0x400e082c + +10001534 : +10001534: b410 push {r4} +10001536: f44f 708d mov.w r0, #282 @ 0x11a +1000153a: f44f 642a mov.w r4, #2720 @ 0xaa0 +1000153e: 4a06 ldr r2, [pc, #24] @ (10001558 ) +10001540: 4b06 ldr r3, [pc, #24] @ (1000155c ) +10001542: 4907 ldr r1, [pc, #28] @ (10001560 ) +10001544: 6014 str r4, [r2, #0] +10001546: 60d0 str r0, [r2, #12] +10001548: 6019 str r1, [r3, #0] +1000154a: 6853 ldr r3, [r2, #4] +1000154c: 2b00 cmp r3, #0 +1000154e: dafc bge.n 1000154a +10001550: f85d 4b04 ldr.w r4, [sp], #4 +10001554: 4770 bx lr +10001556: bf00 nop +10001558: 40048000 .word 0x40048000 +1000155c: 4004a000 .word 0x4004a000 +10001560: 00fab000 .word 0x00fab000 + +10001564 : +10001564: 4770 bx lr +10001566: bf00 nop + +10001568 : +10001568: b508 push {r3, lr} +1000156a: 4801 ldr r0, [pc, #4] @ (10001570 ) +1000156c: f7ff f838 bl 100005e0 +10001570: 10003988 .word 0x10003988 + +10001574 : +10001574: b538 push {r3, r4, r5, lr} +10001576: 4c05 ldr r4, [pc, #20] @ (1000158c ) +10001578: 4d05 ldr r5, [pc, #20] @ (10001590 ) +1000157a: 42ac cmp r4, r5 +1000157c: d204 bcs.n 10001588 +1000157e: f854 3b04 ldr.w r3, [r4], #4 +10001582: 4798 blx r3 +10001584: 42ac cmp r4, r5 +10001586: d3fa bcc.n 1000157e +10001588: bd38 pop {r3, r4, r5, pc} +1000158a: bf00 nop +1000158c: 100038b0 .word 0x100038b0 +10001590: 100038f0 .word 0x100038f0 + +10001594 : +10001594: b410 push {r4} +10001596: 4807 ldr r0, [pc, #28] @ (100015b4 ) +10001598: 4c07 ldr r4, [pc, #28] @ (100015b8 ) +1000159a: 4b08 ldr r3, [pc, #32] @ (100015bc ) +1000159c: 4a08 ldr r2, [pc, #32] @ (100015c0 ) +1000159e: 4909 ldr r1, [pc, #36] @ (100015c4 ) +100015a0: 6004 str r4, [r0, #0] +100015a2: 601a str r2, [r3, #0] +100015a4: 688b ldr r3, [r1, #8] +100015a6: ea32 0303 bics.w r3, r2, r3 +100015aa: d1fb bne.n 100015a4 +100015ac: f85d 4b04 ldr.w r4, [sp], #4 +100015b0: 4770 bx lr +100015b2: bf00 nop +100015b4: 40022000 .word 0x40022000 +100015b8: efef3b7f .word 0xefef3b7f +100015bc: 40023000 .word 0x40023000 +100015c0: 03f3fff6 .word 0x03f3fff6 +100015c4: 40020000 .word 0x40020000 + +100015c8 : +100015c8: 4b04 ldr r3, [pc, #16] @ (100015dc ) +100015ca: 6cdb ldr r3, [r3, #76] @ 0x4c +100015cc: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +100015d0: d103 bne.n 100015da +100015d2: f44f 2280 mov.w r2, #262144 @ 0x40000 +100015d6: 4b02 ldr r3, [pc, #8] @ (100015e0 ) +100015d8: 64da str r2, [r3, #76] @ 0x4c +100015da: 4770 bx lr +100015dc: 50110000 .word 0x50110000 +100015e0: 50112000 .word 0x50112000 + +100015e4 : +100015e4: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100015e8: 4b04 ldr r3, [pc, #16] @ (100015fc ) +100015ea: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +100015ee: 430b orrs r3, r1 +100015f0: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +100015f4: ee10 0430 dcp_rcmp r0 +100015f8: 4770 bx lr +100015fa: bf00 nop +100015fc: 00300303 .word 0x00300303 + +10001600 : +10001600: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +10001604: 4b04 ldr r3, [pc, #16] @ (10001618 ) +10001606: 4a05 ldr r2, [pc, #20] @ (1000161c ) +10001608: 6019 str r1, [r3, #0] +1000160a: 6893 ldr r3, [r2, #8] +1000160c: 43db mvns r3, r3 +1000160e: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +10001612: d1fa bne.n 1000160a +10001614: 4770 bx lr +10001616: bf00 nop +10001618: 40023000 .word 0x40023000 +1000161c: 40020000 .word 0x40020000 + +10001620 : +10001620: b510 push {r4, lr} +10001622: f245 2053 movw r0, #21075 @ 0x5253 +10001626: f7ff ff61 bl 100014ec +1000162a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000162e: 4603 mov r3, r0 +10001630: 2004 movs r0, #4 +10001632: 4718 bx r3 + +10001634 : +10001634: b510 push {r4, lr} +10001636: f245 2053 movw r0, #21075 @ 0x5253 +1000163a: f7ff ff57 bl 100014ec +1000163e: e8bd 4010 ldmia.w sp!, {r4, lr} +10001642: 4603 mov r3, r0 +10001644: 2001 movs r0, #1 +10001646: 4718 bx r3 + +10001648 : +10001648: f7ff b822 b.w 10000690 + +1000164c : +1000164c: 4914 ldr r1, [pc, #80] @ (100016a0 ) +1000164e: 4b15 ldr r3, [pc, #84] @ (100016a4 ) +10001650: b570 push {r4, r5, r6, lr} +10001652: 1a5c subs r4, r3, r1 +10001654: 10a6 asrs r6, r4, #2 +10001656: 2e44 cmp r6, #68 @ 0x44 +10001658: 4632 mov r2, r6 +1000165a: bf28 it cs +1000165c: 2244 movcs r2, #68 @ 0x44 +1000165e: 4d12 ldr r5, [pc, #72] @ (100016a8 ) +10001660: 0092 lsls r2, r2, #2 +10001662: 4628 mov r0, r5 +10001664: f002 f872 bl 1000374c +10001668: f5b4 7f86 cmp.w r4, #268 @ 0x10c +1000166c: d813 bhi.n 10001696 +1000166e: 4a0f ldr r2, [pc, #60] @ (100016ac ) +10001670: f1c6 0044 rsb r0, r6, #68 @ 0x44 +10001674: d012 beq.n 1000169c +10001676: 192b adds r3, r5, r4 +10001678: 0841 lsrs r1, r0, #1 +1000167a: eb03 01c1 add.w r1, r3, r1, lsl #3 +1000167e: e9c3 2200 strd r2, r2, [r3] +10001682: 3308 adds r3, #8 +10001684: 428b cmp r3, r1 +10001686: d1fa bne.n 1000167e +10001688: 07c3 lsls r3, r0, #31 +1000168a: d504 bpl.n 10001696 +1000168c: f020 0001 bic.w r0, r0, #1 +10001690: 4430 add r0, r6 +10001692: f845 2020 str.w r2, [r5, r0, lsl #2] +10001696: 4b06 ldr r3, [pc, #24] @ (100016b0 ) +10001698: 609d str r5, [r3, #8] +1000169a: bd70 pop {r4, r5, r6, pc} +1000169c: 2043 movs r0, #67 @ 0x43 +1000169e: e7f8 b.n 10001692 +100016a0: 10000000 .word 0x10000000 +100016a4: 10000110 .word 0x10000110 +100016a8: 20000000 .word 0x20000000 +100016ac: 10000111 .word 0x10000111 +100016b0: e000ed00 .word 0xe000ed00 + +100016b4 : +100016b4: 2300 movs r3, #0 +100016b6: b570 push {r4, r5, r6, lr} +100016b8: 4c2b ldr r4, [pc, #172] @ (10001768 ) +100016ba: b082 sub sp, #8 +100016bc: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100016c0: f7ff ff38 bl 10001534 +100016c4: 2201 movs r2, #1 +100016c6: 4b29 ldr r3, [pc, #164] @ (1000176c ) +100016c8: 63da str r2, [r3, #60] @ 0x3c +100016ca: 6c63 ldr r3, [r4, #68] @ 0x44 +100016cc: 2b01 cmp r3, #1 +100016ce: d1fc bne.n 100016ca +100016d0: 2103 movs r1, #3 +100016d2: 4a26 ldr r2, [pc, #152] @ (1000176c ) +100016d4: 4b24 ldr r3, [pc, #144] @ (10001768 ) +100016d6: 6311 str r1, [r2, #48] @ 0x30 +100016d8: 6b9c ldr r4, [r3, #56] @ 0x38 +100016da: 2c01 cmp r4, #1 +100016dc: d1fc bne.n 100016d8 +100016de: 2602 movs r6, #2 +100016e0: 2505 movs r5, #5 +100016e2: 4621 mov r1, r4 +100016e4: 2305 movs r3, #5 +100016e6: 4a22 ldr r2, [pc, #136] @ (10001770 ) +100016e8: 4822 ldr r0, [pc, #136] @ (10001774 ) +100016ea: 9600 str r6, [sp, #0] +100016ec: f7ff feac bl 10001448 +100016f0: 4621 mov r1, r4 +100016f2: 462b mov r3, r5 +100016f4: 4a20 ldr r2, [pc, #128] @ (10001778 ) +100016f6: 4821 ldr r0, [pc, #132] @ (1000177c ) +100016f8: 9500 str r5, [sp, #0] +100016fa: f7ff fea5 bl 10001448 +100016fe: 2200 movs r2, #0 +10001700: 2004 movs r0, #4 +10001702: 4631 mov r1, r6 +10001704: 4b1e ldr r3, [pc, #120] @ (10001780 ) +10001706: f7ff fe31 bl 1000136c +1000170a: 4621 mov r1, r4 +1000170c: 4628 mov r0, r5 +1000170e: 2200 movs r2, #0 +10001710: 4b1c ldr r3, [pc, #112] @ (10001784 ) +10001712: f7ff fe2b bl 1000136c +10001716: 2200 movs r2, #0 +10001718: 2008 movs r0, #8 +1000171a: 4611 mov r1, r2 +1000171c: 4b1a ldr r3, [pc, #104] @ (10001788 ) +1000171e: f7ff fe25 bl 1000136c +10001722: 2200 movs r2, #0 +10001724: 2009 movs r0, #9 +10001726: 4611 mov r1, r2 +10001728: 4b17 ldr r3, [pc, #92] @ (10001788 ) +1000172a: f7ff fe1f bl 1000136c +1000172e: 2200 movs r2, #0 +10001730: 2006 movs r0, #6 +10001732: 4611 mov r1, r2 +10001734: 4b13 ldr r3, [pc, #76] @ (10001784 ) +10001736: f7ff fe19 bl 1000136c +1000173a: 2200 movs r2, #0 +1000173c: 4b11 ldr r3, [pc, #68] @ (10001784 ) +1000173e: 2007 movs r0, #7 +10001740: 4611 mov r1, r2 +10001742: f7ff fe13 bl 1000136c +10001746: 2004 movs r0, #4 +10001748: f7ff fe78 bl 1000143c +1000174c: 2400 movs r4, #0 +1000174e: 4b0f ldr r3, [pc, #60] @ (1000178c ) +10001750: fba3 3500 umull r3, r5, r3, r0 +10001754: 0cad lsrs r5, r5, #18 +10001756: b2e0 uxtb r0, r4 +10001758: 4629 mov r1, r5 +1000175a: 3401 adds r4, #1 +1000175c: f7ff feba bl 100014d4 +10001760: 2c06 cmp r4, #6 +10001762: d1f8 bne.n 10001756 +10001764: b002 add sp, #8 +10001766: bd70 pop {r4, r5, r6, pc} +10001768: 40010000 .word 0x40010000 +1000176c: 40013000 .word 0x40013000 +10001770: 59682f00 .word 0x59682f00 +10001774: 40050000 .word 0x40050000 +10001778: 47868c00 .word 0x47868c00 +1000177c: 40058000 .word 0x40058000 +10001780: 00b71b00 .word 0x00b71b00 +10001784: 08f0d180 .word 0x08f0d180 +10001788: 02dc6c00 .word 0x02dc6c00 +1000178c: 431bde83 .word 0x431bde83 + +10001790 : +10001790: b086 sub sp, #24 +10001792: b403 push {r0, r1} +10001794: fc51 0408 dcp_pxmd r0, r1 +10001798: e9cd 0102 strd r0, r1, [sp, #8] +1000179c: fc51 0409 dcp_pymd r0, r1 +100017a0: e9cd 0104 strd r0, r1, [sp, #16] +100017a4: ec51 040a dcp_refd r0, r1 +100017a8: e9cd 0106 strd r0, r1, [sp, #24] +100017ac: bc03 pop {r0, r1} +100017ae: 47f0 blx lr + +100017b0 : +100017b0: e8bd 5000 ldmia.w sp!, {ip, lr} +100017b4: ec4e c400 dcp_wxmd ip, lr +100017b8: e8bd 5000 ldmia.w sp!, {ip, lr} +100017bc: ec4e c401 dcp_wymd ip, lr +100017c0: e8bd 5000 ldmia.w sp!, {ip, lr} +100017c4: ec4e c402 dcp_wefd ip, lr +100017c8: bd00 pop {pc} +100017ca: 0000 movs r0, r0 +100017cc: b500 push {lr} +100017ce: f7ff ffdf bl 10001790 +100017d2: e002 b.n 100017da <__wrap___aeabi_dadd+0x6> + +100017d4 <__wrap___aeabi_dadd>: +100017d4: fe10 f430 dcp_pcmp APSR_nzcv +100017d8: d4f8 bmi.n 100017cc +100017da: ec41 0410 dcp_wxup r0, r1 +100017de: ec43 2411 dcp_wyup r2, r3 +100017e2: ee00 0401 dcp_add0 +100017e6: ee10 0401 dcp_add1 +100017ea: ee80 0420 dcp_nrdd +100017ee: ec51 0410 dcp_rdda r0, r1 +100017f2: 4770 bx lr +100017f4: b500 push {lr} +100017f6: f7ff ffcb bl 10001790 +100017fa: e002 b.n 10001802 <__wrap___aeabi_dsub+0x6> + +100017fc <__wrap___aeabi_dsub>: +100017fc: fe10 f430 dcp_pcmp APSR_nzcv +10001800: d4f8 bmi.n 100017f4 <__wrap___aeabi_dadd+0x20> +10001802: ec41 0410 dcp_wxup r0, r1 +10001806: ec43 2411 dcp_wyup r2, r3 +1000180a: ee00 0401 dcp_add0 +1000180e: ee10 0421 dcp_sub1 +10001812: ee80 0420 dcp_nrdd +10001816: ec51 0430 dcp_rdds r0, r1 +1000181a: 4770 bx lr +1000181c: b500 push {lr} +1000181e: f7ff ffb7 bl 10001790 +10001822: e002 b.n 1000182a <__wrap___aeabi_dmul+0x6> + +10001824 <__wrap___aeabi_dmul>: +10001824: fe10 f430 dcp_pcmp APSR_nzcv +10001828: d4f8 bmi.n 1000181c <__wrap___aeabi_dsub+0x20> +1000182a: b510 push {r4, lr} +1000182c: ec41 0410 dcp_wxup r0, r1 +10001830: ec43 2411 dcp_wyup r2, r3 +10001834: ec51 0404 dcp_rxms r0, r1, #0x0 +10001838: ec53 2405 dcp_ryms r2, r3, #0x0 +1000183c: fba0 4c02 umull r4, ip, r0, r2 +10001840: f05f 0e00 movs.w lr, #0 +10001844: fbe0 ce03 umlal ip, lr, r0, r3 +10001848: fbe1 ce02 umlal ip, lr, r1, r2 +1000184c: ec4c 4420 dcp_wxms r4, ip +10001850: 2400 movs r4, #0 +10001852: fbe1 e403 umlal lr, r4, r1, r3 +10001856: ec44 e430 dcp_wxmo lr, r4 +1000185a: ee80 0420 dcp_nrdd +1000185e: ec51 0450 dcp_rddm r0, r1 +10001862: e8bd 4010 ldmia.w sp!, {r4, lr} +10001866: 4770 bx lr +10001868: b500 push {lr} +1000186a: f7ff ff91 bl 10001790 +1000186e: e002 b.n 10001876 <__wrap___aeabi_ddiv+0x6> + +10001870 <__wrap___aeabi_ddiv>: +10001870: fe10 f430 dcp_pcmp APSR_nzcv +10001874: d4f8 bmi.n 10001868 <__wrap___aeabi_dmul+0x44> +10001876: ec41 0410 dcp_wxup r0, r1 +1000187a: ec43 2411 dcp_wyup r2, r3 +1000187e: ec51 0421 dcp_rymr r0, r1 +10001882: fba0 1201 umull r1, r2, r0, r1 +10001886: ea6f 0282 mvn.w r2, r2, lsl #2 +1000188a: fb52 0010 smmlar r0, r2, r0, r0 +1000188e: fb52 f212 smmulr r2, r2, r2 +10001892: fb52 0010 smmlar r0, r2, r0, r0 +10001896: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +1000189a: ec53 2404 dcp_rxms r2, r3, #0x0 +1000189e: fb5c f113 smmulr r1, ip, r3 +100018a2: ec53 2415 dcp_ryms r2, r3, #0x1 +100018a6: fba1 2002 umull r2, r0, r1, r2 +100018aa: fb01 0003 mla r0, r1, r3, r0 +100018ae: ec53 2444 dcp_rxms r2, r3, #0x4 +100018b2: eba2 0000 sub.w r0, r2, r0 +100018b6: fb50 f21c smmulr r2, r0, ip +100018ba: ea4f 1311 mov.w r3, r1, lsr #4 +100018be: eb12 7001 adds.w r0, r2, r1, lsl #28 +100018c2: eb43 71e2 adc.w r1, r3, r2, asr #31 +100018c6: ea40 5051 orr.w r0, r0, r1, lsr #21 +100018ca: ea20 5091 bic.w r0, r0, r1, lsr #22 +100018ce: f020 0007 bic.w r0, r0, #7 +100018d2: ec53 2475 dcp_ryms r2, r3, #0x7 +100018d6: fba0 3c02 umull r3, ip, r0, r2 +100018da: ec53 2475 dcp_ryms r2, r3, #0x7 +100018de: fb00 cc03 mla ip, r0, r3, ip +100018e2: fb01 cc02 mla ip, r1, r2, ip +100018e6: ec53 2404 dcp_rxms r2, r3, #0x0 +100018ea: ebac 4c82 sub.w ip, ip, r2, lsl #18 +100018ee: ea40 705c orr.w r0, r0, ip, lsr #29 +100018f2: f1a0 0001 sub.w r0, r0, #1 +100018f6: ec41 0440 dcp_wxdd r0, r1 +100018fa: ee80 0420 dcp_nrdd +100018fe: ec51 0470 dcp_rddd r0, r1 +10001902: 4770 bx lr +10001904: b500 push {lr} +10001906: f7ff ff43 bl 10001790 +1000190a: e002 b.n 10001912 <__wrap___aeabi_i2d+0x6> + +1000190c <__wrap___aeabi_i2d>: +1000190c: fe10 f430 dcp_pcmp APSR_nzcv +10001910: d4f8 bmi.n 10001904 <__wrap___aeabi_ddiv+0x94> +10001912: ec40 0470 dcp_wxic r0, r0 +10001916: ee00 0401 dcp_add0 +1000191a: ee10 0421 dcp_sub1 +1000191e: ee80 0420 dcp_nrdd +10001922: ec51 0430 dcp_rdds r0, r1 +10001926: 4770 bx lr +10001928: b500 push {lr} +1000192a: f7ff ff31 bl 10001790 +1000192e: e002 b.n 10001936 <__wrap___aeabi_ui2d+0x6> + +10001930 <__wrap___aeabi_ui2d>: +10001930: fe10 f430 dcp_pcmp APSR_nzcv +10001934: d4f8 bmi.n 10001928 <__wrap___aeabi_i2d+0x1c> +10001936: ec40 0460 dcp_wxuc r0, r0 +1000193a: ee00 0401 dcp_add0 +1000193e: ee10 0421 dcp_sub1 +10001942: ee80 0420 dcp_nrdd +10001946: ec51 0430 dcp_rdds r0, r1 +1000194a: 4770 bx lr +1000194c: b500 push {lr} +1000194e: f7ff ff1f bl 10001790 +10001952: e002 b.n 1000195a + +10001954 <__wrap___aeabi_d2iz>: +10001954: fe10 f430 dcp_pcmp APSR_nzcv +10001958: d4f8 bmi.n 1000194c <__wrap___aeabi_ui2d+0x1c> + +1000195a : +1000195a: ec41 0480 dcp_wxdc r0, r1 +1000195e: ee00 0401 dcp_add0 +10001962: ee10 0401 dcp_add1 +10001966: ee80 0440 dcp_ntdc +1000196a: ee10 0413 dcp_rdic r0 +1000196e: 4770 bx lr +10001970: b500 push {lr} +10001972: f7ff ff0d bl 10001790 +10001976: e002 b.n 1000197e + +10001978 <__wrap___aeabi_d2uiz>: +10001978: fe10 f430 dcp_pcmp APSR_nzcv +1000197c: d4f8 bmi.n 10001970 + +1000197e : +1000197e: ec41 0480 dcp_wxdc r0, r1 +10001982: ee00 0401 dcp_add0 +10001986: ee10 0401 dcp_add1 +1000198a: ee80 0440 dcp_ntdc +1000198e: ee10 0433 dcp_rduc r0 +10001992: 4770 bx lr +10001994: b500 push {lr} +10001996: f7ff fefb bl 10001790 +1000199a: e002 b.n 100019a2 <__wrap___aeabi_dcmpun+0x6> + +1000199c <__wrap___aeabi_dcmpun>: +1000199c: fe10 f430 dcp_pcmp APSR_nzcv +100019a0: d4f8 bmi.n 10001994 +100019a2: ec41 0410 dcp_wxup r0, r1 +100019a6: ec43 2411 dcp_wyup r2, r3 +100019aa: ee00 0401 dcp_add0 +100019ae: ee10 0430 dcp_rcmp r0 +100019b2: f3c0 7000 ubfx r0, r0, #28, #1 +100019b6: 4770 bx lr +100019b8: b500 push {lr} +100019ba: f7ff fee9 bl 10001790 +100019be: e002 b.n 100019c6 <__wrap___aeabi_dcmplt+0x6> + +100019c0 <__wrap___aeabi_dcmplt>: +100019c0: fe10 f430 dcp_pcmp APSR_nzcv +100019c4: d4f8 bmi.n 100019b8 <__wrap___aeabi_dcmpun+0x1c> +100019c6: ec43 2410 dcp_wxup r2, r3 +100019ca: ec41 0411 dcp_wyup r0, r1 +100019ce: ee00 0401 dcp_add0 +100019d2: ee10 f430 dcp_rcmp APSR_nzcv +100019d6: bf8c ite hi +100019d8: 2001 movhi r0, #1 +100019da: 2000 movls r0, #0 +100019dc: 4770 bx lr +100019de: bf00 nop +100019e0: b500 push {lr} +100019e2: f7ff fed5 bl 10001790 +100019e6: e002 b.n 100019ee <__wrap___aeabi_dcmple+0x6> + +100019e8 <__wrap___aeabi_dcmple>: +100019e8: fe10 f430 dcp_pcmp APSR_nzcv +100019ec: d4f8 bmi.n 100019e0 <__wrap___aeabi_dcmplt+0x20> +100019ee: ec43 2410 dcp_wxup r2, r3 +100019f2: ec41 0411 dcp_wyup r0, r1 +100019f6: ee00 0401 dcp_add0 +100019fa: ee10 f430 dcp_rcmp APSR_nzcv +100019fe: bf2c ite cs +10001a00: 2001 movcs r0, #1 +10001a02: 2000 movcc r0, #0 +10001a04: 4770 bx lr +10001a06: bf00 nop +10001a08: b500 push {lr} +10001a0a: f7ff fec1 bl 10001790 +10001a0e: e002 b.n 10001a16 <__wrap___aeabi_dcmpge+0x6> + +10001a10 <__wrap___aeabi_dcmpge>: +10001a10: fe10 f430 dcp_pcmp APSR_nzcv +10001a14: d4f8 bmi.n 10001a08 <__wrap___aeabi_dcmple+0x20> +10001a16: ec41 0410 dcp_wxup r0, r1 +10001a1a: ec43 2411 dcp_wyup r2, r3 +10001a1e: ee00 0401 dcp_add0 +10001a22: ee10 f430 dcp_rcmp APSR_nzcv +10001a26: bf2c ite cs +10001a28: 2001 movcs r0, #1 +10001a2a: 2000 movcc r0, #0 +10001a2c: 4770 bx lr +10001a2e: bf00 nop +10001a30: b500 push {lr} +10001a32: f7ff fead bl 10001790 +10001a36: e002 b.n 10001a3e <__wrap___aeabi_dcmpgt+0x6> + +10001a38 <__wrap___aeabi_dcmpgt>: +10001a38: fe10 f430 dcp_pcmp APSR_nzcv +10001a3c: d4f8 bmi.n 10001a30 <__wrap___aeabi_dcmpge+0x20> +10001a3e: ec41 0410 dcp_wxup r0, r1 +10001a42: ec43 2411 dcp_wyup r2, r3 +10001a46: ee00 0401 dcp_add0 +10001a4a: ee10 f430 dcp_rcmp APSR_nzcv +10001a4e: bf8c ite hi +10001a50: 2001 movhi r0, #1 +10001a52: 2000 movls r0, #0 +10001a54: 4770 bx lr +10001a56: bf00 nop + +10001a58 <_out_null>: +10001a58: 4770 bx lr +10001a5a: bf00 nop + +10001a5c <_out_rev>: +10001a5c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a60: b083 sub sp, #12 +10001a62: 4699 mov r9, r3 +10001a64: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10001a68: 9b0f ldr r3, [sp, #60] @ 0x3c +10001a6a: 4688 mov r8, r1 +10001a6c: 4611 mov r1, r2 +10001a6e: 079a lsls r2, r3, #30 +10001a70: 4607 mov r7, r0 +10001a72: d116 bne.n 10001aa2 <_out_rev+0x46> +10001a74: 45da cmp sl, fp +10001a76: d23a bcs.n 10001aee <_out_rev+0x92> +10001a78: 460c mov r4, r1 +10001a7a: 460d mov r5, r1 +10001a7c: ebab 060a sub.w r6, fp, sl +10001a80: 440e add r6, r1 +10001a82: 4622 mov r2, r4 +10001a84: 464b mov r3, r9 +10001a86: 4641 mov r1, r8 +10001a88: 2020 movs r0, #32 +10001a8a: 3401 adds r4, #1 +10001a8c: 47b8 blx r7 +10001a8e: 42b4 cmp r4, r6 +10001a90: d1f7 bne.n 10001a82 <_out_rev+0x26> +10001a92: 4629 mov r1, r5 +10001a94: f1ba 0f00 cmp.w sl, #0 +10001a98: d108 bne.n 10001aac <_out_rev+0x50> +10001a9a: 4620 mov r0, r4 +10001a9c: b003 add sp, #12 +10001a9e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001aa2: 460c mov r4, r1 +10001aa4: f1ba 0f00 cmp.w sl, #0 +10001aa8: d010 beq.n 10001acc <_out_rev+0x70> +10001aaa: 460e mov r6, r1 +10001aac: 4655 mov r5, sl +10001aae: 9b0c ldr r3, [sp, #48] @ 0x30 +10001ab0: 442e add r6, r5 +10001ab2: 449a add sl, r3 +10001ab4: 9101 str r1, [sp, #4] +10001ab6: 1b72 subs r2, r6, r5 +10001ab8: 464b mov r3, r9 +10001aba: 3d01 subs r5, #1 +10001abc: 4641 mov r1, r8 +10001abe: f81a 0d01 ldrb.w r0, [sl, #-1]! +10001ac2: 4634 mov r4, r6 +10001ac4: 47b8 blx r7 +10001ac6: 2d00 cmp r5, #0 +10001ac8: d1f5 bne.n 10001ab6 <_out_rev+0x5a> +10001aca: 9901 ldr r1, [sp, #4] +10001acc: 9b0f ldr r3, [sp, #60] @ 0x3c +10001ace: 079b lsls r3, r3, #30 +10001ad0: d5e3 bpl.n 10001a9a <_out_rev+0x3e> +10001ad2: 1a65 subs r5, r4, r1 +10001ad4: 45ab cmp fp, r5 +10001ad6: d9e0 bls.n 10001a9a <_out_rev+0x3e> +10001ad8: 4622 mov r2, r4 +10001ada: 464b mov r3, r9 +10001adc: 4641 mov r1, r8 +10001ade: 2020 movs r0, #32 +10001ae0: 3501 adds r5, #1 +10001ae2: 47b8 blx r7 +10001ae4: 455d cmp r5, fp +10001ae6: f104 0401 add.w r4, r4, #1 +10001aea: d3f5 bcc.n 10001ad8 <_out_rev+0x7c> +10001aec: e7d5 b.n 10001a9a <_out_rev+0x3e> +10001aee: 460c mov r4, r1 +10001af0: f1ba 0f00 cmp.w sl, #0 +10001af4: d1d9 bne.n 10001aaa <_out_rev+0x4e> +10001af6: e7d0 b.n 10001a9a <_out_rev+0x3e> + +10001af8 <_ntoa_format>: +10001af8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001afc: 9f0f ldr r7, [sp, #60] @ 0x3c +10001afe: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10001b02: f017 0f02 tst.w r7, #2 +10001b06: 9c0a ldr r4, [sp, #40] @ 0x28 +10001b08: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001b0c: 9d0e ldr r5, [sp, #56] @ 0x38 +10001b0e: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10001b12: d144 bne.n 10001b9e <_ntoa_format+0xa6> +10001b14: bbf5 cbnz r5, 10001b94 <_ntoa_format+0x9c> +10001b16: 42b4 cmp r4, r6 +10001b18: d241 bcs.n 10001b9e <_ntoa_format+0xa6> +10001b1a: f007 0b01 and.w fp, r7, #1 +10001b1e: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001b22: f04f 0e30 mov.w lr, #48 @ 0x30 +10001b26: 44c4 add ip, r8 +10001b28: e004 b.n 10001b34 <_ntoa_format+0x3c> +10001b2a: 3401 adds r4, #1 +10001b2c: 42a6 cmp r6, r4 +10001b2e: f80c ef01 strb.w lr, [ip, #1]! +10001b32: d901 bls.n 10001b38 <_ntoa_format+0x40> +10001b34: 2c20 cmp r4, #32 +10001b36: d1f8 bne.n 10001b2a <_ntoa_format+0x32> +10001b38: f1bb 0f00 cmp.w fp, #0 +10001b3c: f000 8088 beq.w 10001c50 <_ntoa_format+0x158> +10001b40: 42a5 cmp r5, r4 +10001b42: d92c bls.n 10001b9e <_ntoa_format+0xa6> +10001b44: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10001b48: f04f 0e30 mov.w lr, #48 @ 0x30 +10001b4c: 44c4 add ip, r8 +10001b4e: e004 b.n 10001b5a <_ntoa_format+0x62> +10001b50: 3401 adds r4, #1 +10001b52: 42ac cmp r4, r5 +10001b54: f80c ef01 strb.w lr, [ip, #1]! +10001b58: d021 beq.n 10001b9e <_ntoa_format+0xa6> +10001b5a: 2c20 cmp r4, #32 +10001b5c: d1f8 bne.n 10001b50 <_ntoa_format+0x58> +10001b5e: f017 0f10 tst.w r7, #16 +10001b62: d00e beq.n 10001b82 <_ntoa_format+0x8a> +10001b64: f417 6f80 tst.w r7, #1024 @ 0x400 +10001b68: d154 bne.n 10001c14 <_ntoa_format+0x11c> +10001b6a: 42a6 cmp r6, r4 +10001b6c: d063 beq.n 10001c36 <_ntoa_format+0x13e> +10001b6e: 42a5 cmp r5, r4 +10001b70: d061 beq.n 10001c36 <_ntoa_format+0x13e> +10001b72: f1b9 0f10 cmp.w r9, #16 +10001b76: d050 beq.n 10001c1a <_ntoa_format+0x122> +10001b78: f1b9 0f02 cmp.w r9, #2 +10001b7c: d056 beq.n 10001c2c <_ntoa_format+0x134> +10001b7e: 2c20 cmp r4, #32 +10001b80: d129 bne.n 10001bd6 <_ntoa_format+0xde> +10001b82: 2420 movs r4, #32 +10001b84: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001b88: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001b8c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b90: f7ff bf64 b.w 10001a5c <_out_rev> +10001b94: f017 0b01 ands.w fp, r7, #1 +10001b98: d134 bne.n 10001c04 <_ntoa_format+0x10c> +10001b9a: 42b4 cmp r4, r6 +10001b9c: d3bf bcc.n 10001b1e <_ntoa_format+0x26> +10001b9e: f017 0f10 tst.w r7, #16 +10001ba2: d01e beq.n 10001be2 <_ntoa_format+0xea> +10001ba4: f417 6f80 tst.w r7, #1024 @ 0x400 +10001ba8: d1e3 bne.n 10001b72 <_ntoa_format+0x7a> +10001baa: 2c00 cmp r4, #0 +10001bac: d1dd bne.n 10001b6a <_ntoa_format+0x72> +10001bae: f1b9 0f10 cmp.w r9, #16 +10001bb2: d063 beq.n 10001c7c <_ntoa_format+0x184> +10001bb4: f1b9 0f02 cmp.w r9, #2 +10001bb8: d077 beq.n 10001caa <_ntoa_format+0x1b2> +10001bba: 2430 movs r4, #48 @ 0x30 +10001bbc: f888 4000 strb.w r4, [r8] +10001bc0: 2401 movs r4, #1 +10001bc2: f1ba 0f00 cmp.w sl, #0 +10001bc6: d111 bne.n 10001bec <_ntoa_format+0xf4> +10001bc8: 077e lsls r6, r7, #29 +10001bca: d548 bpl.n 10001c5e <_ntoa_format+0x166> +10001bcc: 262b movs r6, #43 @ 0x2b +10001bce: f808 6004 strb.w r6, [r8, r4] +10001bd2: 3401 adds r4, #1 +10001bd4: e7d6 b.n 10001b84 <_ntoa_format+0x8c> +10001bd6: 4626 mov r6, r4 +10001bd8: 3401 adds r4, #1 +10001bda: f04f 0c30 mov.w ip, #48 @ 0x30 +10001bde: f808 c006 strb.w ip, [r8, r6] +10001be2: 2c20 cmp r4, #32 +10001be4: d0cd beq.n 10001b82 <_ntoa_format+0x8a> +10001be6: f1ba 0f00 cmp.w sl, #0 +10001bea: d0ed beq.n 10001bc8 <_ntoa_format+0xd0> +10001bec: 262d movs r6, #45 @ 0x2d +10001bee: f808 6004 strb.w r6, [r8, r4] +10001bf2: 3401 adds r4, #1 +10001bf4: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001bf8: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001bfc: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001c00: f7ff bf2c b.w 10001a5c <_out_rev> +10001c04: f1ba 0f00 cmp.w sl, #0 +10001c08: d030 beq.n 10001c6c <_ntoa_format+0x174> +10001c0a: 42b4 cmp r4, r6 +10001c0c: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001c10: d385 bcc.n 10001b1e <_ntoa_format+0x26> +10001c12: e795 b.n 10001b40 <_ntoa_format+0x48> +10001c14: f1b9 0f10 cmp.w r9, #16 +10001c18: d1b3 bne.n 10001b82 <_ntoa_format+0x8a> +10001c1a: 06be lsls r6, r7, #26 +10001c1c: d53b bpl.n 10001c96 <_ntoa_format+0x19e> +10001c1e: 2c20 cmp r4, #32 +10001c20: d0af beq.n 10001b82 <_ntoa_format+0x8a> +10001c22: 2658 movs r6, #88 @ 0x58 +10001c24: f808 6004 strb.w r6, [r8, r4] +10001c28: 3401 adds r4, #1 +10001c2a: e7a8 b.n 10001b7e <_ntoa_format+0x86> +10001c2c: 2c20 cmp r4, #32 +10001c2e: d0a8 beq.n 10001b82 <_ntoa_format+0x8a> +10001c30: 4626 mov r6, r4 +10001c32: 3401 adds r4, #1 +10001c34: e007 b.n 10001c46 <_ntoa_format+0x14e> +10001c36: 1e66 subs r6, r4, #1 +10001c38: d0b9 beq.n 10001bae <_ntoa_format+0xb6> +10001c3a: f1b9 0f10 cmp.w r9, #16 +10001c3e: d036 beq.n 10001cae <_ntoa_format+0x1b6> +10001c40: f1b9 0f02 cmp.w r9, #2 +10001c44: d1c9 bne.n 10001bda <_ntoa_format+0xe2> +10001c46: f04f 0c62 mov.w ip, #98 @ 0x62 +10001c4a: f808 c006 strb.w ip, [r8, r6] +10001c4e: e796 b.n 10001b7e <_ntoa_format+0x86> +10001c50: f017 0f10 tst.w r7, #16 +10001c54: d0c5 beq.n 10001be2 <_ntoa_format+0xea> +10001c56: f417 6f80 tst.w r7, #1024 @ 0x400 +10001c5a: d086 beq.n 10001b6a <_ntoa_format+0x72> +10001c5c: e789 b.n 10001b72 <_ntoa_format+0x7a> +10001c5e: 073e lsls r6, r7, #28 +10001c60: d590 bpl.n 10001b84 <_ntoa_format+0x8c> +10001c62: 2620 movs r6, #32 +10001c64: f808 6004 strb.w r6, [r8, r4] +10001c68: 3401 adds r4, #1 +10001c6a: e78b b.n 10001b84 <_ntoa_format+0x8c> +10001c6c: f017 0f0c tst.w r7, #12 +10001c70: d000 beq.n 10001c74 <_ntoa_format+0x17c> +10001c72: 3d01 subs r5, #1 +10001c74: 42b4 cmp r4, r6 +10001c76: f4ff af52 bcc.w 10001b1e <_ntoa_format+0x26> +10001c7a: e761 b.n 10001b40 <_ntoa_format+0x48> +10001c7c: 06bc lsls r4, r7, #26 +10001c7e: d412 bmi.n 10001ca6 <_ntoa_format+0x1ae> +10001c80: 2478 movs r4, #120 @ 0x78 +10001c82: f888 4000 strb.w r4, [r8] +10001c86: 2430 movs r4, #48 @ 0x30 +10001c88: f888 4001 strb.w r4, [r8, #1] +10001c8c: 2402 movs r4, #2 +10001c8e: f1ba 0f00 cmp.w sl, #0 +10001c92: d099 beq.n 10001bc8 <_ntoa_format+0xd0> +10001c94: e7aa b.n 10001bec <_ntoa_format+0xf4> +10001c96: 2c20 cmp r4, #32 +10001c98: f43f af73 beq.w 10001b82 <_ntoa_format+0x8a> +10001c9c: 2678 movs r6, #120 @ 0x78 +10001c9e: f808 6004 strb.w r6, [r8, r4] +10001ca2: 3401 adds r4, #1 +10001ca4: e76b b.n 10001b7e <_ntoa_format+0x86> +10001ca6: 2458 movs r4, #88 @ 0x58 +10001ca8: e7eb b.n 10001c82 <_ntoa_format+0x18a> +10001caa: 2462 movs r4, #98 @ 0x62 +10001cac: e7e9 b.n 10001c82 <_ntoa_format+0x18a> +10001cae: f017 0f20 tst.w r7, #32 +10001cb2: f1a4 0c02 sub.w ip, r4, #2 +10001cb6: d004 beq.n 10001cc2 <_ntoa_format+0x1ca> +10001cb8: f04f 0e58 mov.w lr, #88 @ 0x58 +10001cbc: f808 e00c strb.w lr, [r8, ip] +10001cc0: e78b b.n 10001bda <_ntoa_format+0xe2> +10001cc2: f04f 0e78 mov.w lr, #120 @ 0x78 +10001cc6: f808 e00c strb.w lr, [r8, ip] +10001cca: e786 b.n 10001bda <_ntoa_format+0xe2> + +10001ccc <_out_char>: +10001ccc: b900 cbnz r0, 10001cd0 <_out_char+0x4> +10001cce: 4770 bx lr +10001cd0: f001 bb72 b.w 100033b8 <__wrap_putchar> + +10001cd4 <_out_fct>: +10001cd4: b110 cbz r0, 10001cdc <_out_fct+0x8> +10001cd6: e9d1 3100 ldrd r3, r1, [r1] +10001cda: 4718 bx r3 +10001cdc: 4770 bx lr +10001cde: bf00 nop + +10001ce0 <_ftoa>: +10001ce0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001ce4: b097 sub sp, #92 @ 0x5c +10001ce6: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001cea: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001cee: 4607 mov r7, r0 +10001cf0: 4688 mov r8, r1 +10001cf2: ec51 0b17 vmov r0, r1, d7 +10001cf6: 9c24 ldr r4, [sp, #144] @ 0x90 +10001cf8: 4699 mov r9, r3 +10001cfa: 920c str r2, [sp, #48] @ 0x30 +10001cfc: 460b mov r3, r1 +10001cfe: 4602 mov r2, r0 +10001d00: ed8d 7b04 vstr d7, [sp, #16] +10001d04: 9407 str r4, [sp, #28] +10001d06: f7ff fe49 bl 1000199c <__wrap___aeabi_dcmpun> +10001d0a: 2800 cmp r0, #0 +10001d0c: f040 81f4 bne.w 100020f8 <_ftoa+0x418> +10001d10: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d14: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d18: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001d1c: f7ff fe50 bl 100019c0 <__wrap___aeabi_dcmplt> +10001d20: 2800 cmp r0, #0 +10001d22: f040 811b bne.w 10001f5c <_ftoa+0x27c> +10001d26: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d2a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001d2e: 4bac ldr r3, [pc, #688] @ (10001fe0 <_ftoa+0x300>) +10001d30: f7ff fe82 bl 10001a38 <__wrap___aeabi_dcmpgt> +10001d34: 2800 cmp r0, #0 +10001d36: f040 80ee bne.w 10001f16 <_ftoa+0x236> +10001d3a: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d3e: a3a4 add r3, pc, #656 @ (adr r3, 10001fd0 <_ftoa+0x2f0>) +10001d40: e9d3 2300 ldrd r2, r3, [r3] +10001d44: f7ff fe78 bl 10001a38 <__wrap___aeabi_dcmpgt> +10001d48: 2800 cmp r0, #0 +10001d4a: f040 80d3 bne.w 10001ef4 <_ftoa+0x214> +10001d4e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d52: a3a1 add r3, pc, #644 @ (adr r3, 10001fd8 <_ftoa+0x2f8>) +10001d54: e9d3 2300 ldrd r2, r3, [r3] +10001d58: f7ff fe32 bl 100019c0 <__wrap___aeabi_dcmplt> +10001d5c: 2800 cmp r0, #0 +10001d5e: f040 80c9 bne.w 10001ef4 <_ftoa+0x214> +10001d62: e9dd 0104 ldrd r0, r1, [sp, #16] +10001d66: 2200 movs r2, #0 +10001d68: 2300 movs r3, #0 +10001d6a: f7ff fe29 bl 100019c0 <__wrap___aeabi_dcmplt> +10001d6e: 2800 cmp r0, #0 +10001d70: f040 80e8 bne.w 10001f44 <_ftoa+0x264> +10001d74: 4623 mov r3, r4 +10001d76: 900d str r0, [sp, #52] @ 0x34 +10001d78: f413 6f80 tst.w r3, #1024 @ 0x400 +10001d7c: bf08 it eq +10001d7e: 2506 moveq r5, #6 +10001d80: 2130 movs r1, #48 @ 0x30 +10001d82: 462b mov r3, r5 +10001d84: aa0e add r2, sp, #56 @ 0x38 +10001d86: f1a5 0620 sub.w r6, r5, #32 +10001d8a: e005 b.n 10001d98 <_ftoa+0xb8> +10001d8c: 3b01 subs r3, #1 +10001d8e: 42b3 cmp r3, r6 +10001d90: f802 1b01 strb.w r1, [r2], #1 +10001d94: f000 8193 beq.w 100020be <_ftoa+0x3de> +10001d98: 2b09 cmp r3, #9 +10001d9a: d8f7 bhi.n 10001d8c <_ftoa+0xac> +10001d9c: 461e mov r6, r3 +10001d9e: 1aed subs r5, r5, r3 +10001da0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001da4: f7ff fdd6 bl 10001954 <__wrap___aeabi_d2iz> +10001da8: 4b8e ldr r3, [pc, #568] @ (10001fe4 <_ftoa+0x304>) +10001daa: 4604 mov r4, r0 +10001dac: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001db0: ed93 7b00 vldr d7, [r3] +10001db4: ed8d 7b08 vstr d7, [sp, #32] +10001db8: f7ff fda8 bl 1000190c <__wrap___aeabi_i2d> +10001dbc: 4602 mov r2, r0 +10001dbe: 460b mov r3, r1 +10001dc0: e9dd 0104 ldrd r0, r1, [sp, #16] +10001dc4: f7ff fd1a bl 100017fc <__wrap___aeabi_dsub> +10001dc8: e9dd 2308 ldrd r2, r3, [sp, #32] +10001dcc: f7ff fd2a bl 10001824 <__wrap___aeabi_dmul> +10001dd0: 4602 mov r2, r0 +10001dd2: 460b mov r3, r1 +10001dd4: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001dd8: f7ff fdce bl 10001978 <__wrap___aeabi_d2uiz> +10001ddc: 4682 mov sl, r0 +10001dde: f7ff fda7 bl 10001930 <__wrap___aeabi_ui2d> +10001de2: 4602 mov r2, r0 +10001de4: 460b mov r3, r1 +10001de6: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001dea: f7ff fd07 bl 100017fc <__wrap___aeabi_dsub> +10001dee: 4602 mov r2, r0 +10001df0: 460b mov r3, r1 +10001df2: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001df6: 2200 movs r2, #0 +10001df8: 4b7b ldr r3, [pc, #492] @ (10001fe8 <_ftoa+0x308>) +10001dfa: f7ff fe1d bl 10001a38 <__wrap___aeabi_dcmpgt> +10001dfe: 2800 cmp r0, #0 +10001e00: f000 80fe beq.w 10002000 <_ftoa+0x320> +10001e04: f10a 0a01 add.w sl, sl, #1 +10001e08: 4650 mov r0, sl +10001e0a: f7ff fd91 bl 10001930 <__wrap___aeabi_ui2d> +10001e0e: 4602 mov r2, r0 +10001e10: 460b mov r3, r1 +10001e12: e9dd 0108 ldrd r0, r1, [sp, #32] +10001e16: f7ff fde7 bl 100019e8 <__wrap___aeabi_dcmple> +10001e1a: b110 cbz r0, 10001e22 <_ftoa+0x142> +10001e1c: f04f 0a00 mov.w sl, #0 +10001e20: 3401 adds r4, #1 +10001e22: 2e00 cmp r6, #0 +10001e24: f000 80fd beq.w 10002022 <_ftoa+0x342> +10001e28: 1e68 subs r0, r5, #1 +10001e2a: ab0e add r3, sp, #56 @ 0x38 +10001e2c: f8df c1cc ldr.w ip, [pc, #460] @ 10001ffc <_ftoa+0x31c> +10001e30: 4418 add r0, r3 +10001e32: e00f b.n 10001e54 <_ftoa+0x174> +10001e34: fbac 210a umull r2, r1, ip, sl +10001e38: 08c9 lsrs r1, r1, #3 +10001e3a: eb01 0281 add.w r2, r1, r1, lsl #2 +10001e3e: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001e42: 3230 adds r2, #48 @ 0x30 +10001e44: f1ba 0f09 cmp.w sl, #9 +10001e48: f800 2f01 strb.w r2, [r0, #1]! +10001e4c: f240 811c bls.w 10002088 <_ftoa+0x3a8> +10001e50: 468a mov sl, r1 +10001e52: 461d mov r5, r3 +10001e54: 2d20 cmp r5, #32 +10001e56: f105 0301 add.w r3, r5, #1 +10001e5a: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001e5e: d1e9 bne.n 10001e34 <_ftoa+0x154> +10001e60: 2520 movs r5, #32 +10001e62: 1e69 subs r1, r5, #1 +10001e64: ab0e add r3, sp, #56 @ 0x38 +10001e66: 4861 ldr r0, [pc, #388] @ (10001fec <_ftoa+0x30c>) +10001e68: 4419 add r1, r3 +10001e6a: e010 b.n 10001e8e <_ftoa+0x1ae> +10001e6c: fb80 6204 smull r6, r2, r0, r4 +10001e70: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001e74: eb03 0283 add.w r2, r3, r3, lsl #2 +10001e78: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001e7c: f104 0230 add.w r2, r4, #48 @ 0x30 +10001e80: 3501 adds r5, #1 +10001e82: 461c mov r4, r3 +10001e84: f801 2f01 strb.w r2, [r1, #1]! +10001e88: 2b00 cmp r3, #0 +10001e8a: f000 80eb beq.w 10002064 <_ftoa+0x384> +10001e8e: 2d20 cmp r5, #32 +10001e90: ea4f 73e4 mov.w r3, r4, asr #31 +10001e94: d1ea bne.n 10001e6c <_ftoa+0x18c> +10001e96: 9b07 ldr r3, [sp, #28] +10001e98: f003 0303 and.w r3, r3, #3 +10001e9c: 2b01 cmp r3, #1 +10001e9e: d118 bne.n 10001ed2 <_ftoa+0x1f2> +10001ea0: f1bb 0f00 cmp.w fp, #0 +10001ea4: d015 beq.n 10001ed2 <_ftoa+0x1f2> +10001ea6: 9b0d ldr r3, [sp, #52] @ 0x34 +10001ea8: 2b00 cmp r3, #0 +10001eaa: f000 810a beq.w 100020c2 <_ftoa+0x3e2> +10001eae: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001eb2: f1bb 0f20 cmp.w fp, #32 +10001eb6: d90c bls.n 10001ed2 <_ftoa+0x1f2> +10001eb8: 1e6b subs r3, r5, #1 +10001eba: a90e add r1, sp, #56 @ 0x38 +10001ebc: 2230 movs r2, #48 @ 0x30 +10001ebe: 440b add r3, r1 +10001ec0: e005 b.n 10001ece <_ftoa+0x1ee> +10001ec2: 3501 adds r5, #1 +10001ec4: 455d cmp r5, fp +10001ec6: f803 2f01 strb.w r2, [r3, #1]! +10001eca: f080 80d1 bcs.w 10002070 <_ftoa+0x390> +10001ece: 2d20 cmp r5, #32 +10001ed0: d1f7 bne.n 10001ec2 <_ftoa+0x1e2> +10001ed2: 9b07 ldr r3, [sp, #28] +10001ed4: ac0e add r4, sp, #56 @ 0x38 +10001ed6: e9cd b302 strd fp, r3, [sp, #8] +10001eda: 4641 mov r1, r8 +10001edc: 464b mov r3, r9 +10001ede: 4638 mov r0, r7 +10001ee0: 9a0c ldr r2, [sp, #48] @ 0x30 +10001ee2: 9501 str r5, [sp, #4] +10001ee4: 9400 str r4, [sp, #0] +10001ee6: f7ff fdb9 bl 10001a5c <_out_rev> +10001eea: 4682 mov sl, r0 +10001eec: 4650 mov r0, sl +10001eee: b017 add sp, #92 @ 0x5c +10001ef0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001ef4: 9b07 ldr r3, [sp, #28] +10001ef6: ed9d 7b04 vldr d7, [sp, #16] +10001efa: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001efe: 4641 mov r1, r8 +10001f00: 464b mov r3, r9 +10001f02: 4638 mov r0, r7 +10001f04: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f06: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001f0a: 9522 str r5, [sp, #136] @ 0x88 +10001f0c: b017 add sp, #92 @ 0x5c +10001f0e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f12: f000 b945 b.w 100021a0 <_etoa> +10001f16: 0761 lsls r1, r4, #29 +10001f18: 4623 mov r3, r4 +10001f1a: bf4c ite mi +10001f1c: 2304 movmi r3, #4 +10001f1e: 2303 movpl r3, #3 +10001f20: 4641 mov r1, r8 +10001f22: 9321 str r3, [sp, #132] @ 0x84 +10001f24: 4638 mov r0, r7 +10001f26: 464b mov r3, r9 +10001f28: 9a07 ldr r2, [sp, #28] +10001f2a: bf48 it mi +10001f2c: 4c30 ldrmi r4, [pc, #192] @ (10001ff0 <_ftoa+0x310>) +10001f2e: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001f32: bf58 it pl +10001f34: 4c2f ldrpl r4, [pc, #188] @ (10001ff4 <_ftoa+0x314>) +10001f36: 9a0c ldr r2, [sp, #48] @ 0x30 +10001f38: 9420 str r4, [sp, #128] @ 0x80 +10001f3a: b017 add sp, #92 @ 0x5c +10001f3c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001f40: f7ff bd8c b.w 10001a5c <_out_rev> +10001f44: e9dd 2304 ldrd r2, r3, [sp, #16] +10001f48: 2000 movs r0, #0 +10001f4a: 2100 movs r1, #0 +10001f4c: f7ff fc56 bl 100017fc <__wrap___aeabi_dsub> +10001f50: 2301 movs r3, #1 +10001f52: e9cd 0104 strd r0, r1, [sp, #16] +10001f56: 930d str r3, [sp, #52] @ 0x34 +10001f58: 4623 mov r3, r4 +10001f5a: e70d b.n 10001d78 <_ftoa+0x98> +10001f5c: 4623 mov r3, r4 +10001f5e: 079c lsls r4, r3, #30 +10001f60: f040 80aa bne.w 100020b8 <_ftoa+0x3d8> +10001f64: f1bb 0f04 cmp.w fp, #4 +10001f68: f240 80a6 bls.w 100020b8 <_ftoa+0x3d8> +10001f6c: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f6e: 461d mov r5, r3 +10001f70: 1f1c subs r4, r3, #4 +10001f72: eb04 0a0b add.w sl, r4, fp +10001f76: 462a mov r2, r5 +10001f78: 464b mov r3, r9 +10001f7a: 4641 mov r1, r8 +10001f7c: 2020 movs r0, #32 +10001f7e: 3501 adds r5, #1 +10001f80: 47b8 blx r7 +10001f82: 45aa cmp sl, r5 +10001f84: d1f7 bne.n 10001f76 <_ftoa+0x296> +10001f86: 4655 mov r5, sl +10001f88: 4c1b ldr r4, [pc, #108] @ (10001ff8 <_ftoa+0x318>) +10001f8a: 1f26 subs r6, r4, #4 +10001f8c: f814 0d01 ldrb.w r0, [r4, #-1]! +10001f90: 462a mov r2, r5 +10001f92: 464b mov r3, r9 +10001f94: 4641 mov r1, r8 +10001f96: 47b8 blx r7 +10001f98: 42b4 cmp r4, r6 +10001f9a: f105 0501 add.w r5, r5, #1 +10001f9e: d1f5 bne.n 10001f8c <_ftoa+0x2ac> +10001fa0: 9b07 ldr r3, [sp, #28] +10001fa2: f10a 0a04 add.w sl, sl, #4 +10001fa6: 0798 lsls r0, r3, #30 +10001fa8: d5a0 bpl.n 10001eec <_ftoa+0x20c> +10001faa: 9c0c ldr r4, [sp, #48] @ 0x30 +10001fac: ebaa 0304 sub.w r3, sl, r4 +10001fb0: 459b cmp fp, r3 +10001fb2: d99b bls.n 10001eec <_ftoa+0x20c> +10001fb4: 4652 mov r2, sl +10001fb6: 464b mov r3, r9 +10001fb8: 4641 mov r1, r8 +10001fba: 2020 movs r0, #32 +10001fbc: f10a 0a01 add.w sl, sl, #1 +10001fc0: 47b8 blx r7 +10001fc2: ebaa 0304 sub.w r3, sl, r4 +10001fc6: 455b cmp r3, fp +10001fc8: d3f4 bcc.n 10001fb4 <_ftoa+0x2d4> +10001fca: e78f b.n 10001eec <_ftoa+0x20c> +10001fcc: f3af 8000 nop.w +10001fd0: 00000000 .word 0x00000000 +10001fd4: 41cdcd65 .word 0x41cdcd65 +10001fd8: 00000000 .word 0x00000000 +10001fdc: c1cdcd65 .word 0xc1cdcd65 +10001fe0: 7fefffff .word 0x7fefffff +10001fe4: 10003a88 .word 0x10003a88 +10001fe8: 3fe00000 .word 0x3fe00000 +10001fec: 66666667 .word 0x66666667 +10001ff0: 100039e0 .word 0x100039e0 +10001ff4: 100039e8 .word 0x100039e8 +10001ff8: 100039f4 .word 0x100039f4 +10001ffc: cccccccd .word 0xcccccccd +10002000: 2200 movs r2, #0 +10002002: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002006: 4b63 ldr r3, [pc, #396] @ (10002194 <_ftoa+0x4b4>) +10002008: f7ff fcda bl 100019c0 <__wrap___aeabi_dcmplt> +1000200c: 2800 cmp r0, #0 +1000200e: f47f af08 bne.w 10001e22 <_ftoa+0x142> +10002012: f1ba 0f00 cmp.w sl, #0 +10002016: d16a bne.n 100020ee <_ftoa+0x40e> +10002018: f10a 0a01 add.w sl, sl, #1 +1000201c: 2e00 cmp r6, #0 +1000201e: f47f af03 bne.w 10001e28 <_ftoa+0x148> +10002022: 4620 mov r0, r4 +10002024: f7ff fc72 bl 1000190c <__wrap___aeabi_i2d> +10002028: 4602 mov r2, r0 +1000202a: 460b mov r3, r1 +1000202c: e9dd 0104 ldrd r0, r1, [sp, #16] +10002030: f7ff fbe4 bl 100017fc <__wrap___aeabi_dsub> +10002034: 4602 mov r2, r0 +10002036: 460b mov r3, r1 +10002038: e9cd 2304 strd r2, r3, [sp, #16] +1000203c: 2200 movs r2, #0 +1000203e: 4b55 ldr r3, [pc, #340] @ (10002194 <_ftoa+0x4b4>) +10002040: f7ff fcbe bl 100019c0 <__wrap___aeabi_dcmplt> +10002044: 2800 cmp r0, #0 +10002046: f47f af0c bne.w 10001e62 <_ftoa+0x182> +1000204a: e9dd 0104 ldrd r0, r1, [sp, #16] +1000204e: 2200 movs r2, #0 +10002050: 4b50 ldr r3, [pc, #320] @ (10002194 <_ftoa+0x4b4>) +10002052: f7ff fcf1 bl 10001a38 <__wrap___aeabi_dcmpgt> +10002056: 2800 cmp r0, #0 +10002058: f47f af03 bne.w 10001e62 <_ftoa+0x182> +1000205c: 3401 adds r4, #1 +1000205e: f024 0401 bic.w r4, r4, #1 +10002062: e6fe b.n 10001e62 <_ftoa+0x182> +10002064: 9b07 ldr r3, [sp, #28] +10002066: f003 0303 and.w r3, r3, #3 +1000206a: 2b01 cmp r3, #1 +1000206c: f000 8082 beq.w 10002174 <_ftoa+0x494> +10002070: 2d20 cmp r5, #32 +10002072: f43f af2e beq.w 10001ed2 <_ftoa+0x1f2> +10002076: 9b0d ldr r3, [sp, #52] @ 0x34 +10002078: b37b cbz r3, 100020da <_ftoa+0x3fa> +1000207a: 222d movs r2, #45 @ 0x2d +1000207c: eb0d 0305 add.w r3, sp, r5 +10002080: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10002084: 3501 adds r5, #1 +10002086: e724 b.n 10001ed2 <_ftoa+0x1f2> +10002088: 2b20 cmp r3, #32 +1000208a: f43f aee9 beq.w 10001e60 <_ftoa+0x180> +1000208e: aa0e add r2, sp, #56 @ 0x38 +10002090: 4415 add r5, r2 +10002092: 441e add r6, r3 +10002094: 2230 movs r2, #48 @ 0x30 +10002096: e004 b.n 100020a2 <_ftoa+0x3c2> +10002098: 2b20 cmp r3, #32 +1000209a: f805 2f01 strb.w r2, [r5, #1]! +1000209e: f43f aedf beq.w 10001e60 <_ftoa+0x180> +100020a2: 429e cmp r6, r3 +100020a4: f103 0301 add.w r3, r3, #1 +100020a8: d1f6 bne.n 10002098 <_ftoa+0x3b8> +100020aa: 222e movs r2, #46 @ 0x2e +100020ac: eb0d 0306 add.w r3, sp, r6 +100020b0: f883 2038 strb.w r2, [r3, #56] @ 0x38 +100020b4: 1c75 adds r5, r6, #1 +100020b6: e6d4 b.n 10001e62 <_ftoa+0x182> +100020b8: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +100020bc: e763 b.n 10001f86 <_ftoa+0x2a6> +100020be: 2520 movs r5, #32 +100020c0: e66e b.n 10001da0 <_ftoa+0xc0> +100020c2: 9b07 ldr r3, [sp, #28] +100020c4: f013 0f0c tst.w r3, #12 +100020c8: d050 beq.n 1000216c <_ftoa+0x48c> +100020ca: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +100020ce: 45ab cmp fp, r5 +100020d0: f63f aef2 bhi.w 10001eb8 <_ftoa+0x1d8> +100020d4: 2d20 cmp r5, #32 +100020d6: f43f aefc beq.w 10001ed2 <_ftoa+0x1f2> +100020da: 9b07 ldr r3, [sp, #28] +100020dc: 075a lsls r2, r3, #29 +100020de: d501 bpl.n 100020e4 <_ftoa+0x404> +100020e0: 222b movs r2, #43 @ 0x2b +100020e2: e7cb b.n 1000207c <_ftoa+0x39c> +100020e4: 071b lsls r3, r3, #28 +100020e6: f57f aef4 bpl.w 10001ed2 <_ftoa+0x1f2> +100020ea: 2220 movs r2, #32 +100020ec: e7c6 b.n 1000207c <_ftoa+0x39c> +100020ee: f01a 0f01 tst.w sl, #1 +100020f2: f43f ae96 beq.w 10001e22 <_ftoa+0x142> +100020f6: e78f b.n 10002018 <_ftoa+0x338> +100020f8: 07a6 lsls r6, r4, #30 +100020fa: d134 bne.n 10002166 <_ftoa+0x486> +100020fc: f1bb 0f03 cmp.w fp, #3 +10002100: d931 bls.n 10002166 <_ftoa+0x486> +10002102: 9b0c ldr r3, [sp, #48] @ 0x30 +10002104: 461d mov r5, r3 +10002106: 1edc subs r4, r3, #3 +10002108: eb04 0a0b add.w sl, r4, fp +1000210c: 462a mov r2, r5 +1000210e: 464b mov r3, r9 +10002110: 4641 mov r1, r8 +10002112: 2020 movs r0, #32 +10002114: 3501 adds r5, #1 +10002116: 47b8 blx r7 +10002118: 4555 cmp r5, sl +1000211a: d1f7 bne.n 1000210c <_ftoa+0x42c> +1000211c: 4655 mov r5, sl +1000211e: 4c1e ldr r4, [pc, #120] @ (10002198 <_ftoa+0x4b8>) +10002120: 1ee6 subs r6, r4, #3 +10002122: f814 0d01 ldrb.w r0, [r4, #-1]! +10002126: 462a mov r2, r5 +10002128: 464b mov r3, r9 +1000212a: 4641 mov r1, r8 +1000212c: 47b8 blx r7 +1000212e: 42a6 cmp r6, r4 +10002130: f105 0501 add.w r5, r5, #1 +10002134: d1f5 bne.n 10002122 <_ftoa+0x442> +10002136: 9b07 ldr r3, [sp, #28] +10002138: f10a 0a03 add.w sl, sl, #3 +1000213c: 079d lsls r5, r3, #30 +1000213e: f57f aed5 bpl.w 10001eec <_ftoa+0x20c> +10002142: 9c0c ldr r4, [sp, #48] @ 0x30 +10002144: ebaa 0304 sub.w r3, sl, r4 +10002148: 459b cmp fp, r3 +1000214a: f67f aecf bls.w 10001eec <_ftoa+0x20c> +1000214e: 4652 mov r2, sl +10002150: 464b mov r3, r9 +10002152: 4641 mov r1, r8 +10002154: 2020 movs r0, #32 +10002156: f10a 0a01 add.w sl, sl, #1 +1000215a: 47b8 blx r7 +1000215c: ebaa 0304 sub.w r3, sl, r4 +10002160: 459b cmp fp, r3 +10002162: d8f4 bhi.n 1000214e <_ftoa+0x46e> +10002164: e6c2 b.n 10001eec <_ftoa+0x20c> +10002166: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +1000216a: e7d7 b.n 1000211c <_ftoa+0x43c> +1000216c: 45ab cmp fp, r5 +1000216e: f63f aea3 bhi.w 10001eb8 <_ftoa+0x1d8> +10002172: e6ae b.n 10001ed2 <_ftoa+0x1f2> +10002174: f1bb 0f00 cmp.w fp, #0 +10002178: f43f af7a beq.w 10002070 <_ftoa+0x390> +1000217c: 9b0d ldr r3, [sp, #52] @ 0x34 +1000217e: 2b00 cmp r3, #0 +10002180: d09f beq.n 100020c2 <_ftoa+0x3e2> +10002182: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10002186: 455d cmp r5, fp +10002188: f4ff ae96 bcc.w 10001eb8 <_ftoa+0x1d8> +1000218c: 2d20 cmp r5, #32 +1000218e: f47f af74 bne.w 1000207a <_ftoa+0x39a> +10002192: e69e b.n 10001ed2 <_ftoa+0x1f2> +10002194: 3fe00000 .word 0x3fe00000 +10002198: 100039ef .word 0x100039ef +1000219c: 00000000 .word 0x00000000 + +100021a0 <_etoa>: +100021a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100021a4: b09f sub sp, #124 @ 0x7c +100021a6: 9e2a ldr r6, [sp, #168] @ 0xa8 +100021a8: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +100021ac: 4607 mov r7, r0 +100021ae: 4693 mov fp, r2 +100021b0: 9108 str r1, [sp, #32] +100021b2: 9309 str r3, [sp, #36] @ 0x24 +100021b4: 4622 mov r2, r4 +100021b6: 462b mov r3, r5 +100021b8: 4620 mov r0, r4 +100021ba: 4629 mov r1, r5 +100021bc: 960e str r6, [sp, #56] @ 0x38 +100021be: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +100021c2: f7ff fbeb bl 1000199c <__wrap___aeabi_dcmpun> +100021c6: 2800 cmp r0, #0 +100021c8: f040 80be bne.w 10002348 <_etoa+0x1a8> +100021cc: 4620 mov r0, r4 +100021ce: 4629 mov r1, r5 +100021d0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100021d4: 4b78 ldr r3, [pc, #480] @ (100023b8 <_etoa+0x218>) +100021d6: f7ff fc2f bl 10001a38 <__wrap___aeabi_dcmpgt> +100021da: 2800 cmp r0, #0 +100021dc: f040 80b4 bne.w 10002348 <_etoa+0x1a8> +100021e0: 4620 mov r0, r4 +100021e2: 4629 mov r1, r5 +100021e4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100021e8: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +100021ec: f7ff fbe8 bl 100019c0 <__wrap___aeabi_dcmplt> +100021f0: 2800 cmp r0, #0 +100021f2: f040 80a9 bne.w 10002348 <_etoa+0x1a8> +100021f6: 4620 mov r0, r4 +100021f8: 4629 mov r1, r5 +100021fa: 2200 movs r2, #0 +100021fc: 2300 movs r3, #0 +100021fe: f7ff fbdf bl 100019c0 <__wrap___aeabi_dcmplt> +10002202: 2800 cmp r0, #0 +10002204: f040 81d5 bne.w 100025b2 <_etoa+0x412> +10002208: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +1000220c: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10002210: 4690 mov r8, r2 +10002212: 4699 mov r9, r3 +10002214: f406 6200 and.w r2, r6, #2048 @ 0x800 +10002218: f416 6380 ands.w r3, r6, #1024 @ 0x400 +1000221c: 920f str r2, [sp, #60] @ 0x3c +1000221e: 9313 str r3, [sp, #76] @ 0x4c +10002220: f040 80a1 bne.w 10002366 <_etoa+0x1c6> +10002224: ea58 0309 orrs.w r3, r8, r9 +10002228: f040 80ca bne.w 100023c0 <_etoa+0x220> +1000222c: 2a00 cmp r2, #0 +1000222e: f040 81e3 bne.w 100025f8 <_etoa+0x458> +10002232: 2306 movs r3, #6 +10002234: 930e str r3, [sp, #56] @ 0x38 +10002236: f016 0202 ands.w r2, r6, #2 +1000223a: 9210 str r2, [sp, #64] @ 0x40 +1000223c: f040 81d4 bne.w 100025e8 <_etoa+0x448> +10002240: 4653 mov r3, sl +10002242: 2b04 cmp r3, #4 +10002244: bf38 it cc +10002246: 2304 movcc r3, #4 +10002248: 920c str r2, [sp, #48] @ 0x30 +1000224a: 2204 movs r2, #4 +1000224c: 3b04 subs r3, #4 +1000224e: 9212 str r2, [sp, #72] @ 0x48 +10002250: 930f str r3, [sp, #60] @ 0x3c +10002252: 4620 mov r0, r4 +10002254: 4629 mov r1, r5 +10002256: 2200 movs r2, #0 +10002258: 2300 movs r3, #0 +1000225a: f7ff fbb1 bl 100019c0 <__wrap___aeabi_dcmplt> +1000225e: 2800 cmp r0, #0 +10002260: f040 81f3 bne.w 1000264a <_etoa+0x4aa> +10002264: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002268: 9b0f ldr r3, [sp, #60] @ 0x3c +1000226a: 465a mov r2, fp +1000226c: 9303 str r3, [sp, #12] +1000226e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002270: ed8d 7b00 vstr d7, [sp] +10002274: 9302 str r3, [sp, #8] +10002276: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1000227a: 9304 str r3, [sp, #16] +1000227c: 4638 mov r0, r7 +1000227e: 9b09 ldr r3, [sp, #36] @ 0x24 +10002280: 9908 ldr r1, [sp, #32] +10002282: f7ff fd2d bl 10001ce0 <_ftoa> +10002286: 4602 mov r2, r0 +10002288: f016 0f20 tst.w r6, #32 +1000228c: 9b09 ldr r3, [sp, #36] @ 0x24 +1000228e: 9908 ldr r1, [sp, #32] +10002290: bf0c ite eq +10002292: 2065 moveq r0, #101 @ 0x65 +10002294: 2045 movne r0, #69 @ 0x45 +10002296: f102 0801 add.w r8, r2, #1 +1000229a: 47b8 blx r7 +1000229c: 9a0c ldr r2, [sp, #48] @ 0x30 +1000229e: 9b12 ldr r3, [sp, #72] @ 0x48 +100022a0: ac16 add r4, sp, #88 @ 0x58 +100022a2: 1e5d subs r5, r3, #1 +100022a4: ea82 73e2 eor.w r3, r2, r2, asr #31 +100022a8: eba3 73e2 sub.w r3, r3, r2, asr #31 +100022ac: 0fd1 lsrs r1, r2, #31 +100022ae: 2600 movs r6, #0 +100022b0: 4622 mov r2, r4 +100022b2: 4699 mov r9, r3 +100022b4: f8df c104 ldr.w ip, [pc, #260] @ 100023bc <_etoa+0x21c> +100022b8: e001 b.n 100022be <_etoa+0x11e> +100022ba: 2e20 cmp r6, #32 +100022bc: d010 beq.n 100022e0 <_etoa+0x140> +100022be: 46ce mov lr, r9 +100022c0: fbac 3009 umull r3, r0, ip, r9 +100022c4: 08c0 lsrs r0, r0, #3 +100022c6: eb00 0380 add.w r3, r0, r0, lsl #2 +100022ca: eba9 0343 sub.w r3, r9, r3, lsl #1 +100022ce: 3330 adds r3, #48 @ 0x30 +100022d0: f1be 0f09 cmp.w lr, #9 +100022d4: 4681 mov r9, r0 +100022d6: f106 0601 add.w r6, r6, #1 +100022da: f802 3b01 strb.w r3, [r2], #1 +100022de: d8ec bhi.n 100022ba <_etoa+0x11a> +100022e0: 2305 movs r3, #5 +100022e2: 2000 movs r0, #0 +100022e4: 9306 str r3, [sp, #24] +100022e6: 230a movs r3, #10 +100022e8: 9505 str r5, [sp, #20] +100022ea: 9400 str r4, [sp, #0] +100022ec: 9d09 ldr r5, [sp, #36] @ 0x24 +100022ee: 9c08 ldr r4, [sp, #32] +100022f0: 4642 mov r2, r8 +100022f2: e9cd 3003 strd r3, r0, [sp, #12] +100022f6: e9cd 6101 strd r6, r1, [sp, #4] +100022fa: 462b mov r3, r5 +100022fc: 4621 mov r1, r4 +100022fe: 4638 mov r0, r7 +10002300: f7ff fbfa bl 10001af8 <_ntoa_format> +10002304: 9a10 ldr r2, [sp, #64] @ 0x40 +10002306: 4680 mov r8, r0 +10002308: b1d2 cbz r2, 10002340 <_etoa+0x1a0> +1000230a: eba0 060b sub.w r6, r0, fp +1000230e: 45b2 cmp sl, r6 +10002310: d916 bls.n 10002340 <_etoa+0x1a0> +10002312: eb0b 0206 add.w r2, fp, r6 +10002316: 462b mov r3, r5 +10002318: 4621 mov r1, r4 +1000231a: 2020 movs r0, #32 +1000231c: 3601 adds r6, #1 +1000231e: 47b8 blx r7 +10002320: 45b2 cmp sl, r6 +10002322: d8f6 bhi.n 10002312 <_etoa+0x172> +10002324: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002328: 4453 add r3, sl +1000232a: f1cb 0201 rsb r2, fp, #1 +1000232e: eba3 0308 sub.w r3, r3, r8 +10002332: 4442 add r2, r8 +10002334: 4592 cmp sl, r2 +10002336: bf38 it cc +10002338: 2300 movcc r3, #0 +1000233a: f108 0801 add.w r8, r8, #1 +1000233e: 4498 add r8, r3 +10002340: 4640 mov r0, r8 +10002342: b01f add sp, #124 @ 0x7c +10002344: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002348: 465a mov r2, fp +1000234a: 4638 mov r0, r7 +1000234c: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002350: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +10002354: 9c0e ldr r4, [sp, #56] @ 0x38 +10002356: 9b09 ldr r3, [sp, #36] @ 0x24 +10002358: 9908 ldr r1, [sp, #32] +1000235a: 942a str r4, [sp, #168] @ 0xa8 +1000235c: b01f add sp, #124 @ 0x7c +1000235e: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002362: f7ff bcbd b.w 10001ce0 <_ftoa> +10002366: ea58 0309 orrs.w r3, r8, r9 +1000236a: d12b bne.n 100023c4 <_etoa+0x224> +1000236c: 2a00 cmp r2, #0 +1000236e: f43f af62 beq.w 10002236 <_etoa+0x96> +10002372: 2300 movs r3, #0 +10002374: 930c str r3, [sp, #48] @ 0x30 +10002376: 9b0e ldr r3, [sp, #56] @ 0x38 +10002378: 9a0c ldr r2, [sp, #48] @ 0x30 +1000237a: 4293 cmp r3, r2 +1000237c: f300 81b9 bgt.w 100026f2 <_etoa+0x552> +10002380: f04f 0800 mov.w r8, #0 +10002384: 4620 mov r0, r4 +10002386: 4629 mov r1, r5 +10002388: 2200 movs r2, #0 +1000238a: 2300 movs r3, #0 +1000238c: f7ff fb18 bl 100019c0 <__wrap___aeabi_dcmplt> +10002390: 2800 cmp r0, #0 +10002392: f040 8113 bne.w 100025bc <_etoa+0x41c> +10002396: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +1000239a: f426 6600 bic.w r6, r6, #2048 @ 0x800 +1000239e: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100023a2: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +100023a6: 465a mov r2, fp +100023a8: 4638 mov r0, r7 +100023aa: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100023ae: 9b09 ldr r3, [sp, #36] @ 0x24 +100023b0: 9908 ldr r1, [sp, #32] +100023b2: 962c str r6, [sp, #176] @ 0xb0 +100023b4: e7d2 b.n 1000235c <_etoa+0x1bc> +100023b6: bf00 nop +100023b8: 7fefffff .word 0x7fefffff +100023bc: cccccccd .word 0xcccccccd +100023c0: 2306 movs r3, #6 +100023c2: 930e str r3, [sp, #56] @ 0x38 +100023c4: f3c9 500a ubfx r0, r9, #20, #11 +100023c8: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +100023cc: f7ff fa9e bl 1000190c <__wrap___aeabi_i2d> +100023d0: a3c1 add r3, pc, #772 @ (adr r3, 100026d8 <_etoa+0x538>) +100023d2: e9d3 2300 ldrd r2, r3, [r3] +100023d6: f7ff fa25 bl 10001824 <__wrap___aeabi_dmul> +100023da: a3c1 add r3, pc, #772 @ (adr r3, 100026e0 <_etoa+0x540>) +100023dc: e9d3 2300 ldrd r2, r3, [r3] +100023e0: f7ff f9f8 bl 100017d4 <__wrap___aeabi_dadd> +100023e4: f3c9 0913 ubfx r9, r9, #0, #20 +100023e8: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +100023ec: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +100023f0: 4640 mov r0, r8 +100023f2: 2200 movs r2, #0 +100023f4: 4bb2 ldr r3, [pc, #712] @ (100026c0 <_etoa+0x520>) +100023f6: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +100023fa: f7ff f9ff bl 100017fc <__wrap___aeabi_dsub> +100023fe: a3a4 add r3, pc, #656 @ (adr r3, 10002690 <_etoa+0x4f0>) +10002400: e9d3 2300 ldrd r2, r3, [r3] +10002404: f7ff fa0e bl 10001824 <__wrap___aeabi_dmul> +10002408: 4602 mov r2, r0 +1000240a: 460b mov r3, r1 +1000240c: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002410: f7ff f9e0 bl 100017d4 <__wrap___aeabi_dadd> +10002414: f7ff fa9e bl 10001954 <__wrap___aeabi_d2iz> +10002418: 900c str r0, [sp, #48] @ 0x30 +1000241a: f7ff fa77 bl 1000190c <__wrap___aeabi_i2d> +1000241e: a39e add r3, pc, #632 @ (adr r3, 10002698 <_etoa+0x4f8>) +10002420: e9d3 2300 ldrd r2, r3, [r3] +10002424: 4680 mov r8, r0 +10002426: 4689 mov r9, r1 +10002428: f7ff f9fc bl 10001824 <__wrap___aeabi_dmul> +1000242c: 2200 movs r2, #0 +1000242e: 4ba5 ldr r3, [pc, #660] @ (100026c4 <_etoa+0x524>) +10002430: f7ff f9d0 bl 100017d4 <__wrap___aeabi_dadd> +10002434: f7ff fa8e bl 10001954 <__wrap___aeabi_d2iz> +10002438: 4603 mov r3, r0 +1000243a: 4649 mov r1, r9 +1000243c: 4640 mov r0, r8 +1000243e: 9312 str r3, [sp, #72] @ 0x48 +10002440: a397 add r3, pc, #604 @ (adr r3, 100026a0 <_etoa+0x500>) +10002442: e9d3 2300 ldrd r2, r3, [r3] +10002446: f7ff f9ed bl 10001824 <__wrap___aeabi_dmul> +1000244a: 4680 mov r8, r0 +1000244c: 9812 ldr r0, [sp, #72] @ 0x48 +1000244e: 4689 mov r9, r1 +10002450: f7ff fa5c bl 1000190c <__wrap___aeabi_i2d> +10002454: a394 add r3, pc, #592 @ (adr r3, 100026a8 <_etoa+0x508>) +10002456: e9d3 2300 ldrd r2, r3, [r3] +1000245a: f7ff f9e3 bl 10001824 <__wrap___aeabi_dmul> +1000245e: 4602 mov r2, r0 +10002460: 460b mov r3, r1 +10002462: 4640 mov r0, r8 +10002464: 4649 mov r1, r9 +10002466: f7ff f9c9 bl 100017fc <__wrap___aeabi_dsub> +1000246a: 4602 mov r2, r0 +1000246c: 460b mov r3, r1 +1000246e: 4680 mov r8, r0 +10002470: 4689 mov r9, r1 +10002472: f7ff f9d7 bl 10001824 <__wrap___aeabi_dmul> +10002476: 4642 mov r2, r8 +10002478: 464b mov r3, r9 +1000247a: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +1000247e: 4640 mov r0, r8 +10002480: 4649 mov r1, r9 +10002482: f7ff f9a7 bl 100017d4 <__wrap___aeabi_dadd> +10002486: 2200 movs r2, #0 +10002488: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +1000248c: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002490: 4b8d ldr r3, [pc, #564] @ (100026c8 <_etoa+0x528>) +10002492: f7ff f9ed bl 10001870 <__wrap___aeabi_ddiv> +10002496: 2200 movs r2, #0 +10002498: 4b8c ldr r3, [pc, #560] @ (100026cc <_etoa+0x52c>) +1000249a: f7ff f99b bl 100017d4 <__wrap___aeabi_dadd> +1000249e: 4602 mov r2, r0 +100024a0: 460b mov r3, r1 +100024a2: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100024a6: f7ff f9e3 bl 10001870 <__wrap___aeabi_ddiv> +100024aa: 2200 movs r2, #0 +100024ac: 4b88 ldr r3, [pc, #544] @ (100026d0 <_etoa+0x530>) +100024ae: f7ff f991 bl 100017d4 <__wrap___aeabi_dadd> +100024b2: 4602 mov r2, r0 +100024b4: 460b mov r3, r1 +100024b6: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100024ba: f7ff f9d9 bl 10001870 <__wrap___aeabi_ddiv> +100024be: 4642 mov r2, r8 +100024c0: 464b mov r3, r9 +100024c2: 4680 mov r8, r0 +100024c4: 4689 mov r9, r1 +100024c6: 2000 movs r0, #0 +100024c8: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +100024cc: f7ff f996 bl 100017fc <__wrap___aeabi_dsub> +100024d0: 4602 mov r2, r0 +100024d2: 460b mov r3, r1 +100024d4: 4640 mov r0, r8 +100024d6: 4649 mov r1, r9 +100024d8: f7ff f97c bl 100017d4 <__wrap___aeabi_dadd> +100024dc: 4602 mov r2, r0 +100024de: 460b mov r3, r1 +100024e0: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +100024e4: f7ff f9c4 bl 10001870 <__wrap___aeabi_ddiv> +100024e8: 2200 movs r2, #0 +100024ea: 4b7a ldr r3, [pc, #488] @ (100026d4 <_etoa+0x534>) +100024ec: f7ff f972 bl 100017d4 <__wrap___aeabi_dadd> +100024f0: 9b12 ldr r3, [sp, #72] @ 0x48 +100024f2: 2200 movs r2, #0 +100024f4: f203 3cff addw ip, r3, #1023 @ 0x3ff +100024f8: ea4f 530c mov.w r3, ip, lsl #20 +100024fc: f7ff f992 bl 10001824 <__wrap___aeabi_dmul> +10002500: 4680 mov r8, r0 +10002502: 4689 mov r9, r1 +10002504: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002508: 4642 mov r2, r8 +1000250a: 464b mov r3, r9 +1000250c: f7ff fa58 bl 100019c0 <__wrap___aeabi_dcmplt> +10002510: b150 cbz r0, 10002528 <_etoa+0x388> +10002512: 9b0c ldr r3, [sp, #48] @ 0x30 +10002514: 4640 mov r0, r8 +10002516: 3b01 subs r3, #1 +10002518: 4649 mov r1, r9 +1000251a: 930c str r3, [sp, #48] @ 0x30 +1000251c: 2200 movs r2, #0 +1000251e: 4b6b ldr r3, [pc, #428] @ (100026cc <_etoa+0x52c>) +10002520: f7ff f9a6 bl 10001870 <__wrap___aeabi_ddiv> +10002524: 4680 mov r8, r0 +10002526: 4689 mov r9, r1 +10002528: 9a0c ldr r2, [sp, #48] @ 0x30 +1000252a: 4643 mov r3, r8 +1000252c: 3263 adds r2, #99 @ 0x63 +1000252e: 2ac6 cmp r2, #198 @ 0xc6 +10002530: f006 0202 and.w r2, r6, #2 +10002534: 9210 str r2, [sp, #64] @ 0x40 +10002536: 4649 mov r1, r9 +10002538: 9a0f ldr r2, [sp, #60] @ 0x3c +1000253a: d82c bhi.n 10002596 <_etoa+0x3f6> +1000253c: 2a00 cmp r2, #0 +1000253e: d05e beq.n 100025fe <_etoa+0x45e> +10002540: 2204 movs r2, #4 +10002542: 9212 str r2, [sp, #72] @ 0x48 +10002544: 430b orrs r3, r1 +10002546: f43f af16 beq.w 10002376 <_etoa+0x1d6> +1000254a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000254e: a358 add r3, pc, #352 @ (adr r3, 100026b0 <_etoa+0x510>) +10002550: e9d3 2300 ldrd r2, r3, [r3] +10002554: f7ff fa5c bl 10001a10 <__wrap___aeabi_dcmpge> +10002558: b148 cbz r0, 1000256e <_etoa+0x3ce> +1000255a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000255e: a356 add r3, pc, #344 @ (adr r3, 100026b8 <_etoa+0x518>) +10002560: e9d3 2300 ldrd r2, r3, [r3] +10002564: f7ff fa2c bl 100019c0 <__wrap___aeabi_dcmplt> +10002568: 2800 cmp r0, #0 +1000256a: f47f af04 bne.w 10002376 <_etoa+0x1d6> +1000256e: 9b0e ldr r3, [sp, #56] @ 0x38 +10002570: 2b00 cmp r3, #0 +10002572: d050 beq.n 10002616 <_etoa+0x476> +10002574: 9a13 ldr r2, [sp, #76] @ 0x4c +10002576: 2a00 cmp r2, #0 +10002578: d07d beq.n 10002676 <_etoa+0x4d6> +1000257a: 3b01 subs r3, #1 +1000257c: 930e str r3, [sp, #56] @ 0x38 +1000257e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002580: 459a cmp sl, r3 +10002582: d905 bls.n 10002590 <_etoa+0x3f0> +10002584: 9b10 ldr r3, [sp, #64] @ 0x40 +10002586: 2b00 cmp r3, #0 +10002588: f000 80ae beq.w 100026e8 <_etoa+0x548> +1000258c: 2302 movs r3, #2 +1000258e: 9310 str r3, [sp, #64] @ 0x40 +10002590: 2300 movs r3, #0 +10002592: 930f str r3, [sp, #60] @ 0x3c +10002594: e044 b.n 10002620 <_etoa+0x480> +10002596: bb22 cbnz r2, 100025e2 <_etoa+0x442> +10002598: f1ba 0f05 cmp.w sl, #5 +1000259c: d94f bls.n 1000263e <_etoa+0x49e> +1000259e: f006 0302 and.w r3, r6, #2 +100025a2: 2b00 cmp r3, #0 +100025a4: d149 bne.n 1000263a <_etoa+0x49a> +100025a6: 2305 movs r3, #5 +100025a8: 9312 str r3, [sp, #72] @ 0x48 +100025aa: f1aa 0305 sub.w r3, sl, #5 +100025ae: 930f str r3, [sp, #60] @ 0x3c +100025b0: e03a b.n 10002628 <_etoa+0x488> +100025b2: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +100025b6: 940a str r4, [sp, #40] @ 0x28 +100025b8: 930b str r3, [sp, #44] @ 0x2c +100025ba: e627 b.n 1000220c <_etoa+0x6c> +100025bc: f426 6600 bic.w r6, r6, #2048 @ 0x800 +100025c0: f446 6680 orr.w r6, r6, #1024 @ 0x400 +100025c4: 4638 mov r0, r7 +100025c6: 962c str r6, [sp, #176] @ 0xb0 +100025c8: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +100025cc: 4634 mov r4, r6 +100025ce: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +100025d2: 465a mov r2, fp +100025d4: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +100025d8: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100025dc: 9b09 ldr r3, [sp, #36] @ 0x24 +100025de: 9908 ldr r1, [sp, #32] +100025e0: e6bc b.n 1000235c <_etoa+0x1bc> +100025e2: 2205 movs r2, #5 +100025e4: 9212 str r2, [sp, #72] @ 0x48 +100025e6: e7ad b.n 10002544 <_etoa+0x3a4> +100025e8: 2300 movs r3, #0 +100025ea: 2202 movs r2, #2 +100025ec: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +100025f0: 2204 movs r2, #4 +100025f2: 930c str r3, [sp, #48] @ 0x30 +100025f4: 9212 str r2, [sp, #72] @ 0x48 +100025f6: e62c b.n 10002252 <_etoa+0xb2> +100025f8: f04f 0805 mov.w r8, #5 +100025fc: e6c2 b.n 10002384 <_etoa+0x1e4> +100025fe: f1ba 0f04 cmp.w sl, #4 +10002602: d91f bls.n 10002644 <_etoa+0x4a4> +10002604: 9b10 ldr r3, [sp, #64] @ 0x40 +10002606: 2b00 cmp r3, #0 +10002608: d178 bne.n 100026fc <_etoa+0x55c> +1000260a: 2304 movs r3, #4 +1000260c: 9312 str r3, [sp, #72] @ 0x48 +1000260e: f1aa 0304 sub.w r3, sl, #4 +10002612: 930f str r3, [sp, #60] @ 0x3c +10002614: e004 b.n 10002620 <_etoa+0x480> +10002616: 9b12 ldr r3, [sp, #72] @ 0x48 +10002618: 459a cmp sl, r3 +1000261a: d831 bhi.n 10002680 <_etoa+0x4e0> +1000261c: 9b0e ldr r3, [sp, #56] @ 0x38 +1000261e: 930f str r3, [sp, #60] @ 0x3c +10002620: 9b0c ldr r3, [sp, #48] @ 0x30 +10002622: 2b00 cmp r3, #0 +10002624: f43f ae15 beq.w 10002252 <_etoa+0xb2> +10002628: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +1000262c: 4642 mov r2, r8 +1000262e: 464b mov r3, r9 +10002630: f7ff f91e bl 10001870 <__wrap___aeabi_ddiv> +10002634: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +10002638: e60b b.n 10002252 <_etoa+0xb2> +1000263a: 2302 movs r3, #2 +1000263c: 9310 str r3, [sp, #64] @ 0x40 +1000263e: 2305 movs r3, #5 +10002640: 9312 str r3, [sp, #72] @ 0x48 +10002642: e7f1 b.n 10002628 <_etoa+0x488> +10002644: 2304 movs r3, #4 +10002646: 9312 str r3, [sp, #72] @ 0x48 +10002648: e7ea b.n 10002620 <_etoa+0x480> +1000264a: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +1000264e: 46a0 mov r8, r4 +10002650: 9b0f ldr r3, [sp, #60] @ 0x3c +10002652: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +10002656: 9303 str r3, [sp, #12] +10002658: 9b0e ldr r3, [sp, #56] @ 0x38 +1000265a: 465a mov r2, fp +1000265c: 9302 str r3, [sp, #8] +1000265e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10002662: 9304 str r3, [sp, #16] +10002664: 4638 mov r0, r7 +10002666: e9cd 8900 strd r8, r9, [sp] +1000266a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000266c: 9908 ldr r1, [sp, #32] +1000266e: f7ff fb37 bl 10001ce0 <_ftoa> +10002672: 4602 mov r2, r0 +10002674: e608 b.n 10002288 <_etoa+0xe8> +10002676: 9b12 ldr r3, [sp, #72] @ 0x48 +10002678: 459a cmp sl, r3 +1000267a: d844 bhi.n 10002706 <_etoa+0x566> +1000267c: 920f str r2, [sp, #60] @ 0x3c +1000267e: e7cf b.n 10002620 <_etoa+0x480> +10002680: 9b10 ldr r3, [sp, #64] @ 0x40 +10002682: b38b cbz r3, 100026e8 <_etoa+0x548> +10002684: 9b0e ldr r3, [sp, #56] @ 0x38 +10002686: 930f str r3, [sp, #60] @ 0x3c +10002688: 2302 movs r3, #2 +1000268a: 9310 str r3, [sp, #64] @ 0x40 +1000268c: e7c8 b.n 10002620 <_etoa+0x480> +1000268e: bf00 nop +10002690: 636f4361 .word 0x636f4361 +10002694: 3fd287a7 .word 0x3fd287a7 +10002698: 0979a371 .word 0x0979a371 +1000269c: 400a934f .word 0x400a934f +100026a0: bbb55516 .word 0xbbb55516 +100026a4: 40026bb1 .word 0x40026bb1 +100026a8: fefa39ef .word 0xfefa39ef +100026ac: 3fe62e42 .word 0x3fe62e42 +100026b0: eb1c432d .word 0xeb1c432d +100026b4: 3f1a36e2 .word 0x3f1a36e2 +100026b8: 00000000 .word 0x00000000 +100026bc: 412e8480 .word 0x412e8480 +100026c0: 3ff80000 .word 0x3ff80000 +100026c4: 3fe00000 .word 0x3fe00000 +100026c8: 402c0000 .word 0x402c0000 +100026cc: 40240000 .word 0x40240000 +100026d0: 40180000 .word 0x40180000 +100026d4: 3ff00000 .word 0x3ff00000 +100026d8: 509f79fb .word 0x509f79fb +100026dc: 3fd34413 .word 0x3fd34413 +100026e0: 8b60c8b3 .word 0x8b60c8b3 +100026e4: 3fc68a28 .word 0x3fc68a28 +100026e8: 9b12 ldr r3, [sp, #72] @ 0x48 +100026ea: ebaa 0303 sub.w r3, sl, r3 +100026ee: 930f str r3, [sp, #60] @ 0x3c +100026f0: e796 b.n 10002620 <_etoa+0x480> +100026f2: eba3 0802 sub.w r8, r3, r2 +100026f6: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100026fa: e643 b.n 10002384 <_etoa+0x1e4> +100026fc: 2304 movs r3, #4 +100026fe: 9312 str r3, [sp, #72] @ 0x48 +10002700: 2302 movs r3, #2 +10002702: 9310 str r3, [sp, #64] @ 0x40 +10002704: e78c b.n 10002620 <_etoa+0x480> +10002706: 9b10 ldr r3, [sp, #64] @ 0x40 +10002708: 2b00 cmp r3, #0 +1000270a: d0ed beq.n 100026e8 <_etoa+0x548> +1000270c: 2302 movs r3, #2 +1000270e: 920f str r2, [sp, #60] @ 0x3c +10002710: 9310 str r3, [sp, #64] @ 0x40 +10002712: e785 b.n 10002620 <_etoa+0x480> + +10002714 <_vsnprintf>: +10002714: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002718: b09b sub sp, #108 @ 0x6c +1000271a: 9c24 ldr r4, [sp, #144] @ 0x90 +1000271c: 4d95 ldr r5, [pc, #596] @ (10002974 <_vsnprintf+0x260>) +1000271e: 940a str r4, [sp, #40] @ 0x28 +10002720: 4c95 ldr r4, [pc, #596] @ (10002978 <_vsnprintf+0x264>) +10002722: f1b1 0a00 subs.w sl, r1, #0 +10002726: bf18 it ne +10002728: 4683 movne fp, r0 +1000272a: 6025 str r5, [r4, #0] +1000272c: 7818 ldrb r0, [r3, #0] +1000272e: 4c93 ldr r4, [pc, #588] @ (1000297c <_vsnprintf+0x268>) +10002730: 4691 mov r9, r2 +10002732: bf08 it eq +10002734: 46a3 moveq fp, r4 +10002736: 9309 str r3, [sp, #36] @ 0x24 +10002738: 2800 cmp r0, #0 +1000273a: f000 8293 beq.w 10002c64 <_vsnprintf+0x550> +1000273e: f04f 0800 mov.w r8, #0 +10002742: e00a b.n 1000275a <_vsnprintf+0x46> +10002744: 4642 mov r2, r8 +10002746: 464b mov r3, r9 +10002748: 4651 mov r1, sl +1000274a: f108 0801 add.w r8, r8, #1 +1000274e: 47d8 blx fp +10002750: 9b09 ldr r3, [sp, #36] @ 0x24 +10002752: 7818 ldrb r0, [r3, #0] +10002754: 2800 cmp r0, #0 +10002756: f000 80ce beq.w 100028f6 <_vsnprintf+0x1e2> +1000275a: 9b09 ldr r3, [sp, #36] @ 0x24 +1000275c: 2825 cmp r0, #37 @ 0x25 +1000275e: f103 0301 add.w r3, r3, #1 +10002762: 9309 str r3, [sp, #36] @ 0x24 +10002764: d1ee bne.n 10002744 <_vsnprintf+0x30> +10002766: 461c mov r4, r3 +10002768: 2300 movs r3, #0 +1000276a: 4622 mov r2, r4 +1000276c: f812 0b01 ldrb.w r0, [r2], #1 +10002770: f1a0 0120 sub.w r1, r0, #32 +10002774: 2910 cmp r1, #16 +10002776: d80a bhi.n 1000278e <_vsnprintf+0x7a> +10002778: e8df f001 tbb [pc, r1] +1000277c: 3c090940 .word 0x3c090940 +10002780: 09090909 .word 0x09090909 +10002784: 38090909 .word 0x38090909 +10002788: 09093409 .word 0x09093409 +1000278c: 30 .byte 0x30 +1000278d: 00 .byte 0x00 +1000278e: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +10002792: 2909 cmp r1, #9 +10002794: 9409 str r4, [sp, #36] @ 0x24 +10002796: f240 808a bls.w 100028ae <_vsnprintf+0x19a> +1000279a: 282a cmp r0, #42 @ 0x2a +1000279c: f000 80f0 beq.w 10002980 <_vsnprintf+0x26c> +100027a0: 2500 movs r5, #0 +100027a2: 282e cmp r0, #46 @ 0x2e +100027a4: f000 8096 beq.w 100028d4 <_vsnprintf+0x1c0> +100027a8: 2600 movs r6, #0 +100027aa: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +100027ae: 2912 cmp r1, #18 +100027b0: d82d bhi.n 1000280e <_vsnprintf+0xfa> +100027b2: e8df f011 tbh [pc, r1, lsl #1] +100027b6: 0149 .short 0x0149 +100027b8: 0143002c .word 0x0143002c +100027bc: 0138002c .word 0x0138002c +100027c0: 002c002c .word 0x002c002c +100027c4: 002c002c .word 0x002c002c +100027c8: 002c002c .word 0x002c002c +100027cc: 0027002c .word 0x0027002c +100027d0: 002c002c .word 0x002c002c +100027d4: 002c002c .word 0x002c002c +100027d8: 0027002c .word 0x0027002c +100027dc: 4614 mov r4, r2 +100027de: f043 0301 orr.w r3, r3, #1 +100027e2: e7c2 b.n 1000276a <_vsnprintf+0x56> +100027e4: 4614 mov r4, r2 +100027e6: f043 0302 orr.w r3, r3, #2 +100027ea: e7be b.n 1000276a <_vsnprintf+0x56> +100027ec: 4614 mov r4, r2 +100027ee: f043 0304 orr.w r3, r3, #4 +100027f2: e7ba b.n 1000276a <_vsnprintf+0x56> +100027f4: 4614 mov r4, r2 +100027f6: f043 0310 orr.w r3, r3, #16 +100027fa: e7b6 b.n 1000276a <_vsnprintf+0x56> +100027fc: 4614 mov r4, r2 +100027fe: f043 0308 orr.w r3, r3, #8 +10002802: e7b2 b.n 1000276a <_vsnprintf+0x56> +10002804: 9909 ldr r1, [sp, #36] @ 0x24 +10002806: 7848 ldrb r0, [r1, #1] +10002808: f443 7380 orr.w r3, r3, #256 @ 0x100 +1000280c: 3201 adds r2, #1 +1000280e: 2867 cmp r0, #103 @ 0x67 +10002810: 9209 str r2, [sp, #36] @ 0x24 +10002812: d87e bhi.n 10002912 <_vsnprintf+0x1fe> +10002814: 2824 cmp r0, #36 @ 0x24 +10002816: f240 80c1 bls.w 1000299c <_vsnprintf+0x288> +1000281a: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +1000281e: 2a42 cmp r2, #66 @ 0x42 +10002820: f200 80bc bhi.w 1000299c <_vsnprintf+0x288> +10002824: e8df f012 tbh [pc, r2, lsl #1] +10002828: 00ba0150 .word 0x00ba0150 +1000282c: 00ba00ba .word 0x00ba00ba +10002830: 00ba00ba .word 0x00ba00ba +10002834: 00ba00ba .word 0x00ba00ba +10002838: 00ba00ba .word 0x00ba00ba +1000283c: 00ba00ba .word 0x00ba00ba +10002840: 00ba00ba .word 0x00ba00ba +10002844: 00ba00ba .word 0x00ba00ba +10002848: 00ba00ba .word 0x00ba00ba +1000284c: 00ba00ba .word 0x00ba00ba +10002850: 00ba00ba .word 0x00ba00ba +10002854: 00ba00ba .word 0x00ba00ba +10002858: 00ba00ba .word 0x00ba00ba +1000285c: 00ba00ba .word 0x00ba00ba +10002860: 00ba00ba .word 0x00ba00ba +10002864: 00ba00ba .word 0x00ba00ba +10002868: 01370119 .word 0x01370119 +1000286c: 00ba0119 .word 0x00ba0119 +10002870: 00ba00ba .word 0x00ba00ba +10002874: 00ba00ba .word 0x00ba00ba +10002878: 00ba00ba .word 0x00ba00ba +1000287c: 00ba00ba .word 0x00ba00ba +10002880: 00ba00ba .word 0x00ba00ba +10002884: 00ba00ba .word 0x00ba00ba +10002888: 00ba00ba .word 0x00ba00ba +1000288c: 01bc00ba .word 0x01bc00ba +10002890: 00ba00ba .word 0x00ba00ba +10002894: 00ba00ba .word 0x00ba00ba +10002898: 00ba00ba .word 0x00ba00ba +1000289c: 00ba00ba .word 0x00ba00ba +100028a0: 01bc00ba .word 0x01bc00ba +100028a4: 01bc0158 .word 0x01bc0158 +100028a8: 01370119 .word 0x01370119 +100028ac: 0119 .short 0x0119 +100028ae: 2500 movs r5, #0 +100028b0: e000 b.n 100028b4 <_vsnprintf+0x1a0> +100028b2: 3201 adds r2, #1 +100028b4: eb05 0585 add.w r5, r5, r5, lsl #2 +100028b8: eb00 0545 add.w r5, r0, r5, lsl #1 +100028bc: 7810 ldrb r0, [r2, #0] +100028be: 3d30 subs r5, #48 @ 0x30 +100028c0: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100028c4: 2909 cmp r1, #9 +100028c6: d9f4 bls.n 100028b2 <_vsnprintf+0x19e> +100028c8: 282e cmp r0, #46 @ 0x2e +100028ca: 9209 str r2, [sp, #36] @ 0x24 +100028cc: f102 0201 add.w r2, r2, #1 +100028d0: f47f af6a bne.w 100027a8 <_vsnprintf+0x94> +100028d4: 9909 ldr r1, [sp, #36] @ 0x24 +100028d6: f443 6380 orr.w r3, r3, #1024 @ 0x400 +100028da: 7848 ldrb r0, [r1, #1] +100028dc: 4611 mov r1, r2 +100028de: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100028e2: 2e09 cmp r6, #9 +100028e4: f240 8121 bls.w 10002b2a <_vsnprintf+0x416> +100028e8: 282a cmp r0, #42 @ 0x2a +100028ea: f000 812f beq.w 10002b4c <_vsnprintf+0x438> +100028ee: 9209 str r2, [sp, #36] @ 0x24 +100028f0: 2600 movs r6, #0 +100028f2: 3201 adds r2, #1 +100028f4: e759 b.n 100027aa <_vsnprintf+0x96> +100028f6: 4644 mov r4, r8 +100028f8: 45c1 cmp r9, r8 +100028fa: d801 bhi.n 10002900 <_vsnprintf+0x1ec> +100028fc: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002900: 464b mov r3, r9 +10002902: 4642 mov r2, r8 +10002904: 4651 mov r1, sl +10002906: 2000 movs r0, #0 +10002908: 47d8 blx fp +1000290a: 4620 mov r0, r4 +1000290c: b01b add sp, #108 @ 0x6c +1000290e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10002912: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +10002916: b2d2 uxtb r2, r2 +10002918: 2a0f cmp r2, #15 +1000291a: d83f bhi.n 1000299c <_vsnprintf+0x288> +1000291c: 2101 movs r1, #1 +1000291e: f249 0741 movw r7, #36929 @ 0x9041 +10002922: 4091 lsls r1, r2 +10002924: 4039 ands r1, r7 +10002926: f040 80f3 bne.w 10002b10 <_vsnprintf+0x3fc> +1000292a: 2a0a cmp r2, #10 +1000292c: d03d beq.n 100029aa <_vsnprintf+0x296> +1000292e: 2a07 cmp r2, #7 +10002930: d134 bne.n 1000299c <_vsnprintf+0x288> +10002932: 9d0a ldr r5, [sp, #40] @ 0x28 +10002934: f855 2b04 ldr.w r2, [r5], #4 +10002938: 2a00 cmp r2, #0 +1000293a: f000 8113 beq.w 10002b64 <_vsnprintf+0x450> +1000293e: f043 0021 orr.w r0, r3, #33 @ 0x21 +10002942: ab12 add r3, sp, #72 @ 0x48 +10002944: 461f mov r7, r3 +10002946: 930b str r3, [sp, #44] @ 0x2c +10002948: e003 b.n 10002952 <_vsnprintf+0x23e> +1000294a: 2920 cmp r1, #32 +1000294c: f000 8114 beq.w 10002b78 <_vsnprintf+0x464> +10002950: 461a mov r2, r3 +10002952: f002 040f and.w r4, r2, #15 +10002956: 4623 mov r3, r4 +10002958: 2c09 cmp r4, #9 +1000295a: bf94 ite ls +1000295c: 3330 addls r3, #48 @ 0x30 +1000295e: 3337 addhi r3, #55 @ 0x37 +10002960: 2a0f cmp r2, #15 +10002962: f807 3b01 strb.w r3, [r7], #1 +10002966: f101 0101 add.w r1, r1, #1 +1000296a: ea4f 1312 mov.w r3, r2, lsr #4 +1000296e: d8ec bhi.n 1000294a <_vsnprintf+0x236> +10002970: e102 b.n 10002b78 <_vsnprintf+0x464> +10002972: bf00 nop +10002974: 10002715 .word 0x10002715 +10002978: 20000810 .word 0x20000810 +1000297c: 10001a59 .word 0x10001a59 +10002980: 990a ldr r1, [sp, #40] @ 0x28 +10002982: 9809 ldr r0, [sp, #36] @ 0x24 +10002984: f851 5b04 ldr.w r5, [r1], #4 +10002988: 7840 ldrb r0, [r0, #1] +1000298a: 2d00 cmp r5, #0 +1000298c: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10002990: bfbc itt lt +10002992: f043 0302 orrlt.w r3, r3, #2 +10002996: 426d neglt r5, r5 +10002998: 3201 adds r2, #1 +1000299a: e702 b.n 100027a2 <_vsnprintf+0x8e> +1000299c: 4642 mov r2, r8 +1000299e: 464b mov r3, r9 +100029a0: 4651 mov r1, sl +100029a2: f108 0801 add.w r8, r8, #1 +100029a6: 47d8 blx fp +100029a8: e6d2 b.n 10002750 <_vsnprintf+0x3c> +100029aa: 990a ldr r1, [sp, #40] @ 0x28 +100029ac: 2e00 cmp r6, #0 +100029ae: f851 7b04 ldr.w r7, [r1], #4 +100029b2: bf18 it ne +100029b4: 4632 movne r2, r6 +100029b6: 7838 ldrb r0, [r7, #0] +100029b8: bf08 it eq +100029ba: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +100029be: 2800 cmp r0, #0 +100029c0: f000 837b beq.w 100030ba <_vsnprintf+0x9a6> +100029c4: 18bc adds r4, r7, r2 +100029c6: 46a4 mov ip, r4 +100029c8: 463a mov r2, r7 +100029ca: e004 b.n 100029d6 <_vsnprintf+0x2c2> +100029cc: f812 4f01 ldrb.w r4, [r2, #1]! +100029d0: 2c00 cmp r4, #0 +100029d2: f000 813f beq.w 10002c54 <_vsnprintf+0x540> +100029d6: 4594 cmp ip, r2 +100029d8: d1f8 bne.n 100029cc <_vsnprintf+0x2b8> +100029da: 4664 mov r4, ip +100029dc: 1be4 subs r4, r4, r7 +100029de: 055a lsls r2, r3, #21 +100029e0: f140 8122 bpl.w 10002c28 <_vsnprintf+0x514> +100029e4: 42b4 cmp r4, r6 +100029e6: bf28 it cs +100029e8: 4634 movcs r4, r6 +100029ea: f013 0302 ands.w r3, r3, #2 +100029ee: f000 8288 beq.w 10002f02 <_vsnprintf+0x7ee> +100029f2: 2302 movs r3, #2 +100029f4: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +100029f8: 4642 mov r2, r8 +100029fa: 461d mov r5, r3 +100029fc: 4446 add r6, r8 +100029fe: e008 b.n 10002a12 <_vsnprintf+0x2fe> +10002a00: 464b mov r3, r9 +10002a02: 4651 mov r1, sl +10002a04: 47d8 blx fp +10002a06: f817 0f01 ldrb.w r0, [r7, #1]! +10002a0a: f108 0801 add.w r8, r8, #1 +10002a0e: b110 cbz r0, 10002a16 <_vsnprintf+0x302> +10002a10: 4642 mov r2, r8 +10002a12: 4546 cmp r6, r8 +10002a14: d1f4 bne.n 10002a00 <_vsnprintf+0x2ec> +10002a16: 462b mov r3, r5 +10002a18: 990b ldr r1, [sp, #44] @ 0x2c +10002a1a: 9d0a ldr r5, [sp, #40] @ 0x28 +10002a1c: 2b00 cmp r3, #0 +10002a1e: f040 8141 bne.w 10002ca4 <_vsnprintf+0x590> +10002a22: 910a str r1, [sp, #40] @ 0x28 +10002a24: e694 b.n 10002750 <_vsnprintf+0x3c> +10002a26: 9909 ldr r1, [sp, #36] @ 0x24 +10002a28: 7848 ldrb r0, [r1, #1] +10002a2a: 286c cmp r0, #108 @ 0x6c +10002a2c: f47f aeec bne.w 10002808 <_vsnprintf+0xf4> +10002a30: 460a mov r2, r1 +10002a32: 7888 ldrb r0, [r1, #2] +10002a34: f443 7340 orr.w r3, r3, #768 @ 0x300 +10002a38: 3203 adds r2, #3 +10002a3a: e6e8 b.n 1000280e <_vsnprintf+0xfa> +10002a3c: 9909 ldr r1, [sp, #36] @ 0x24 +10002a3e: f443 7300 orr.w r3, r3, #512 @ 0x200 +10002a42: 7848 ldrb r0, [r1, #1] +10002a44: 3201 adds r2, #1 +10002a46: e6e2 b.n 1000280e <_vsnprintf+0xfa> +10002a48: 9909 ldr r1, [sp, #36] @ 0x24 +10002a4a: 7848 ldrb r0, [r1, #1] +10002a4c: 2868 cmp r0, #104 @ 0x68 +10002a4e: f000 8103 beq.w 10002c58 <_vsnprintf+0x544> +10002a52: f043 0380 orr.w r3, r3, #128 @ 0x80 +10002a56: 3201 adds r2, #1 +10002a58: e6d9 b.n 1000280e <_vsnprintf+0xfa> +10002a5a: 2867 cmp r0, #103 @ 0x67 +10002a5c: f000 80d9 beq.w 10002c12 <_vsnprintf+0x4fe> +10002a60: 2847 cmp r0, #71 @ 0x47 +10002a62: f000 80dc beq.w 10002c1e <_vsnprintf+0x50a> +10002a66: 2845 cmp r0, #69 @ 0x45 +10002a68: f000 80db beq.w 10002c22 <_vsnprintf+0x50e> +10002a6c: e9cd 5303 strd r5, r3, [sp, #12] +10002a70: 9b0a ldr r3, [sp, #40] @ 0x28 +10002a72: 9602 str r6, [sp, #8] +10002a74: 3307 adds r3, #7 +10002a76: f023 0307 bic.w r3, r3, #7 +10002a7a: 461c mov r4, r3 +10002a7c: 4642 mov r2, r8 +10002a7e: e8f4 6702 ldrd r6, r7, [r4], #8 +10002a82: 464b mov r3, r9 +10002a84: 4651 mov r1, sl +10002a86: 4658 mov r0, fp +10002a88: e9cd 6700 strd r6, r7, [sp] +10002a8c: 940a str r4, [sp, #40] @ 0x28 +10002a8e: f7ff fb87 bl 100021a0 <_etoa> +10002a92: 4680 mov r8, r0 +10002a94: e65c b.n 10002750 <_vsnprintf+0x3c> +10002a96: 2846 cmp r0, #70 @ 0x46 +10002a98: bf08 it eq +10002a9a: f043 0320 orreq.w r3, r3, #32 +10002a9e: e9cd 5303 strd r5, r3, [sp, #12] +10002aa2: 9b0a ldr r3, [sp, #40] @ 0x28 +10002aa4: 9602 str r6, [sp, #8] +10002aa6: 3307 adds r3, #7 +10002aa8: f023 0307 bic.w r3, r3, #7 +10002aac: 461c mov r4, r3 +10002aae: 4642 mov r2, r8 +10002ab0: e8f4 6702 ldrd r6, r7, [r4], #8 +10002ab4: 464b mov r3, r9 +10002ab6: 4651 mov r1, sl +10002ab8: 4658 mov r0, fp +10002aba: e9cd 6700 strd r6, r7, [sp] +10002abe: 940a str r4, [sp, #40] @ 0x28 +10002ac0: f7ff f90e bl 10001ce0 <_ftoa> +10002ac4: 4680 mov r8, r0 +10002ac6: e643 b.n 10002750 <_vsnprintf+0x3c> +10002ac8: 4642 mov r2, r8 +10002aca: 464b mov r3, r9 +10002acc: 4651 mov r1, sl +10002ace: 2025 movs r0, #37 @ 0x25 +10002ad0: f108 0801 add.w r8, r8, #1 +10002ad4: 47d8 blx fp +10002ad6: e63b b.n 10002750 <_vsnprintf+0x3c> +10002ad8: 9a0a ldr r2, [sp, #40] @ 0x28 +10002ada: 0799 lsls r1, r3, #30 +10002adc: f102 0404 add.w r4, r2, #4 +10002ae0: f108 0601 add.w r6, r8, #1 +10002ae4: f140 80c6 bpl.w 10002c74 <_vsnprintf+0x560> +10002ae8: 7810 ldrb r0, [r2, #0] +10002aea: 464b mov r3, r9 +10002aec: 4642 mov r2, r8 +10002aee: 4651 mov r1, sl +10002af0: 47d8 blx fp +10002af2: 2d01 cmp r5, #1 +10002af4: bf88 it hi +10002af6: 44a8 addhi r8, r5 +10002af8: f240 81bd bls.w 10002e76 <_vsnprintf+0x762> +10002afc: 4632 mov r2, r6 +10002afe: 464b mov r3, r9 +10002b00: 4651 mov r1, sl +10002b02: 2020 movs r0, #32 +10002b04: 3601 adds r6, #1 +10002b06: 47d8 blx fp +10002b08: 4546 cmp r6, r8 +10002b0a: d1f7 bne.n 10002afc <_vsnprintf+0x3e8> +10002b0c: 940a str r4, [sp, #40] @ 0x28 +10002b0e: e61f b.n 10002750 <_vsnprintf+0x3c> +10002b10: 286f cmp r0, #111 @ 0x6f +10002b12: f000 8081 beq.w 10002c18 <_vsnprintf+0x504> +10002b16: f240 8248 bls.w 10002faa <_vsnprintf+0x896> +10002b1a: 2878 cmp r0, #120 @ 0x78 +10002b1c: f000 8190 beq.w 10002e40 <_vsnprintf+0x72c> +10002b20: 270a movs r7, #10 +10002b22: f023 0310 bic.w r3, r3, #16 +10002b26: 46bc mov ip, r7 +10002b28: e041 b.n 10002bae <_vsnprintf+0x49a> +10002b2a: 2600 movs r6, #0 +10002b2c: eb06 0686 add.w r6, r6, r6, lsl #2 +10002b30: eb00 0046 add.w r0, r0, r6, lsl #1 +10002b34: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10002b38: f811 0f01 ldrb.w r0, [r1, #1]! +10002b3c: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10002b40: 2a09 cmp r2, #9 +10002b42: d9f3 bls.n 10002b2c <_vsnprintf+0x418> +10002b44: 460a mov r2, r1 +10002b46: 9109 str r1, [sp, #36] @ 0x24 +10002b48: 3201 adds r2, #1 +10002b4a: e62e b.n 100027aa <_vsnprintf+0x96> +10002b4c: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10002b50: f851 6b04 ldr.w r6, [r1], #4 +10002b54: 7890 ldrb r0, [r2, #2] +10002b56: 3202 adds r2, #2 +10002b58: 9209 str r2, [sp, #36] @ 0x24 +10002b5a: 910a str r1, [sp, #40] @ 0x28 +10002b5c: 3201 adds r2, #1 +10002b5e: ea26 76e6 bic.w r6, r6, r6, asr #31 +10002b62: e622 b.n 100027aa <_vsnprintf+0x96> +10002b64: f023 0010 bic.w r0, r3, #16 +10002b68: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b6c: f040 0021 orr.w r0, r0, #33 @ 0x21 +10002b70: f43f aee7 beq.w 10002942 <_vsnprintf+0x22e> +10002b74: ab12 add r3, sp, #72 @ 0x48 +10002b76: 930b str r3, [sp, #44] @ 0x2c +10002b78: 9b0b ldr r3, [sp, #44] @ 0x2c +10002b7a: 9006 str r0, [sp, #24] +10002b7c: 9300 str r3, [sp, #0] +10002b7e: 2308 movs r3, #8 +10002b80: 2010 movs r0, #16 +10002b82: 9305 str r3, [sp, #20] +10002b84: 2300 movs r3, #0 +10002b86: 4642 mov r2, r8 +10002b88: e9cd 3002 strd r3, r0, [sp, #8] +10002b8c: 9101 str r1, [sp, #4] +10002b8e: 464b mov r3, r9 +10002b90: 4651 mov r1, sl +10002b92: 4658 mov r0, fp +10002b94: 9604 str r6, [sp, #16] +10002b96: f7fe ffaf bl 10001af8 <_ntoa_format> +10002b9a: 950a str r5, [sp, #40] @ 0x28 +10002b9c: 4680 mov r8, r0 +10002b9e: e5d7 b.n 10002750 <_vsnprintf+0x3c> +10002ba0: 2858 cmp r0, #88 @ 0x58 +10002ba2: d062 beq.n 10002c6a <_vsnprintf+0x556> +10002ba4: 2862 cmp r0, #98 @ 0x62 +10002ba6: f040 808f bne.w 10002cc8 <_vsnprintf+0x5b4> +10002baa: 2702 movs r7, #2 +10002bac: 46bc mov ip, r7 +10002bae: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002bb2: f000 80dd beq.w 10002d70 <_vsnprintf+0x65c> +10002bb6: f023 030d bic.w r3, r3, #13 +10002bba: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002bbe: f040 8181 bne.w 10002ec4 <_vsnprintf+0x7b0> +10002bc2: 990a ldr r1, [sp, #40] @ 0x28 +10002bc4: 1d0f adds r7, r1, #4 +10002bc6: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002bca: f040 8237 bne.w 1000303c <_vsnprintf+0x928> +10002bce: 065c lsls r4, r3, #25 +10002bd0: 9a0a ldr r2, [sp, #40] @ 0x28 +10002bd2: f140 813b bpl.w 10002e4c <_vsnprintf+0x738> +10002bd6: 7812 ldrb r2, [r2, #0] +10002bd8: 2a00 cmp r2, #0 +10002bda: f040 814e bne.w 10002e7a <_vsnprintf+0x766> +10002bde: f023 0310 bic.w r3, r3, #16 +10002be2: 2800 cmp r0, #0 +10002be4: f000 8149 beq.w 10002e7a <_vsnprintf+0x766> +10002be8: 4611 mov r1, r2 +10002bea: aa12 add r2, sp, #72 @ 0x48 +10002bec: 920b str r2, [sp, #44] @ 0x2c +10002bee: e9cd 5305 strd r5, r3, [sp, #20] +10002bf2: e9cd c603 strd ip, r6, [sp, #12] +10002bf6: 9101 str r1, [sp, #4] +10002bf8: 9b0b ldr r3, [sp, #44] @ 0x2c +10002bfa: 4642 mov r2, r8 +10002bfc: 9300 str r3, [sp, #0] +10002bfe: 2300 movs r3, #0 +10002c00: 4651 mov r1, sl +10002c02: 9302 str r3, [sp, #8] +10002c04: 4658 mov r0, fp +10002c06: 464b mov r3, r9 +10002c08: f7fe ff76 bl 10001af8 <_ntoa_format> +10002c0c: 970a str r7, [sp, #40] @ 0x28 +10002c0e: 4680 mov r8, r0 +10002c10: e59e b.n 10002750 <_vsnprintf+0x3c> +10002c12: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002c16: e729 b.n 10002a6c <_vsnprintf+0x358> +10002c18: 2708 movs r7, #8 +10002c1a: 46bc mov ip, r7 +10002c1c: e7c7 b.n 10002bae <_vsnprintf+0x49a> +10002c1e: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002c22: f043 0320 orr.w r3, r3, #32 +10002c26: e721 b.n 10002a6c <_vsnprintf+0x358> +10002c28: f013 0302 ands.w r3, r3, #2 +10002c2c: f000 818e beq.w 10002f4c <_vsnprintf+0x838> +10002c30: 2302 movs r3, #2 +10002c32: 950a str r5, [sp, #40] @ 0x28 +10002c34: 461e mov r6, r3 +10002c36: 460d mov r5, r1 +10002c38: 4642 mov r2, r8 +10002c3a: 464b mov r3, r9 +10002c3c: 4651 mov r1, sl +10002c3e: 47d8 blx fp +10002c40: f817 0f01 ldrb.w r0, [r7, #1]! +10002c44: f108 0801 add.w r8, r8, #1 +10002c48: 2800 cmp r0, #0 +10002c4a: d1f5 bne.n 10002c38 <_vsnprintf+0x524> +10002c4c: 4629 mov r1, r5 +10002c4e: 4633 mov r3, r6 +10002c50: 9d0a ldr r5, [sp, #40] @ 0x28 +10002c52: e6e3 b.n 10002a1c <_vsnprintf+0x308> +10002c54: 1bd4 subs r4, r2, r7 +10002c56: e6c2 b.n 100029de <_vsnprintf+0x2ca> +10002c58: 460a mov r2, r1 +10002c5a: 7888 ldrb r0, [r1, #2] +10002c5c: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002c60: 3203 adds r2, #3 +10002c62: e5d4 b.n 1000280e <_vsnprintf+0xfa> +10002c64: 4604 mov r4, r0 +10002c66: 4680 mov r8, r0 +10002c68: e646 b.n 100028f8 <_vsnprintf+0x1e4> +10002c6a: 2710 movs r7, #16 +10002c6c: f043 0320 orr.w r3, r3, #32 +10002c70: 46bc mov ip, r7 +10002c72: e79c b.n 10002bae <_vsnprintf+0x49a> +10002c74: 2d01 cmp r5, #1 +10002c76: f240 80f8 bls.w 10002e6a <_vsnprintf+0x756> +10002c7a: 4646 mov r6, r8 +10002c7c: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002c80: 442f add r7, r5 +10002c82: 4632 mov r2, r6 +10002c84: 464b mov r3, r9 +10002c86: 4651 mov r1, sl +10002c88: 2020 movs r0, #32 +10002c8a: 3601 adds r6, #1 +10002c8c: 47d8 blx fp +10002c8e: 42be cmp r6, r7 +10002c90: d1f7 bne.n 10002c82 <_vsnprintf+0x56e> +10002c92: 9b0a ldr r3, [sp, #40] @ 0x28 +10002c94: 4632 mov r2, r6 +10002c96: 7818 ldrb r0, [r3, #0] +10002c98: 4651 mov r1, sl +10002c9a: 464b mov r3, r9 +10002c9c: 47d8 blx fp +10002c9e: 44a8 add r8, r5 +10002ca0: 940a str r4, [sp, #40] @ 0x28 +10002ca2: e555 b.n 10002750 <_vsnprintf+0x3c> +10002ca4: 4646 mov r6, r8 +10002ca6: 42a5 cmp r5, r4 +10002ca8: f67f aebb bls.w 10002a22 <_vsnprintf+0x30e> +10002cac: 44a8 add r8, r5 +10002cae: eba8 0804 sub.w r8, r8, r4 +10002cb2: 460c mov r4, r1 +10002cb4: 4632 mov r2, r6 +10002cb6: 464b mov r3, r9 +10002cb8: 4651 mov r1, sl +10002cba: 2020 movs r0, #32 +10002cbc: 3601 adds r6, #1 +10002cbe: 47d8 blx fp +10002cc0: 4546 cmp r6, r8 +10002cc2: d1f7 bne.n 10002cb4 <_vsnprintf+0x5a0> +10002cc4: 4621 mov r1, r4 +10002cc6: e6ac b.n 10002a22 <_vsnprintf+0x30e> +10002cc8: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002ccc: f000 80bb beq.w 10002e46 <_vsnprintf+0x732> +10002cd0: f44f 6280 mov.w r2, #1024 @ 0x400 +10002cd4: f023 0c11 bic.w ip, r3, #17 +10002cd8: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002cdc: 9b0a ldr r3, [sp, #40] @ 0x28 +10002cde: d14a bne.n 10002d76 <_vsnprintf+0x662> +10002ce0: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002ce4: f103 0404 add.w r4, r3, #4 +10002ce8: f040 8134 bne.w 10002f54 <_vsnprintf+0x840> +10002cec: f01c 0f40 tst.w ip, #64 @ 0x40 +10002cf0: f040 80a3 bne.w 10002e3a <_vsnprintf+0x726> +10002cf4: f01c 0f80 tst.w ip, #128 @ 0x80 +10002cf8: f000 81d3 beq.w 100030a2 <_vsnprintf+0x98e> +10002cfc: f9b3 1000 ldrsh.w r1, [r3] +10002d00: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002d04: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002d08: b2bf uxth r7, r7 +10002d0a: 0fcb lsrs r3, r1, #31 +10002d0c: 2900 cmp r1, #0 +10002d0e: f000 8156 beq.w 10002fbe <_vsnprintf+0x8aa> +10002d12: 463a mov r2, r7 +10002d14: a912 add r1, sp, #72 @ 0x48 +10002d16: 460f mov r7, r1 +10002d18: f8df e3d8 ldr.w lr, [pc, #984] @ 100030f4 <_vsnprintf+0x9e0> +10002d1c: 910b str r1, [sp, #44] @ 0x2c +10002d1e: 930a str r3, [sp, #40] @ 0x28 +10002d20: 950c str r5, [sp, #48] @ 0x30 +10002d22: e001 b.n 10002d28 <_vsnprintf+0x614> +10002d24: 2820 cmp r0, #32 +10002d26: d00f beq.n 10002d48 <_vsnprintf+0x634> +10002d28: 4615 mov r5, r2 +10002d2a: fbae 1302 umull r1, r3, lr, r2 +10002d2e: 08db lsrs r3, r3, #3 +10002d30: eb03 0183 add.w r1, r3, r3, lsl #2 +10002d34: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002d38: 3130 adds r1, #48 @ 0x30 +10002d3a: 2d09 cmp r5, #9 +10002d3c: 461a mov r2, r3 +10002d3e: f100 0001 add.w r0, r0, #1 +10002d42: f807 1b01 strb.w r1, [r7], #1 +10002d46: d8ed bhi.n 10002d24 <_vsnprintf+0x610> +10002d48: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d4a: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d4c: e9cd 5c05 strd r5, ip, [sp, #20] +10002d50: e9cd 0301 strd r0, r3, [sp, #4] +10002d54: 9604 str r6, [sp, #16] +10002d56: 9b0b ldr r3, [sp, #44] @ 0x2c +10002d58: 4642 mov r2, r8 +10002d5a: 9300 str r3, [sp, #0] +10002d5c: 230a movs r3, #10 +10002d5e: 4651 mov r1, sl +10002d60: 9303 str r3, [sp, #12] +10002d62: 4658 mov r0, fp +10002d64: 464b mov r3, r9 +10002d66: f7fe fec7 bl 10001af8 <_ntoa_format> +10002d6a: 940a str r4, [sp, #40] @ 0x28 +10002d6c: 4680 mov r8, r0 +10002d6e: e4ef b.n 10002750 <_vsnprintf+0x3c> +10002d70: f023 030c bic.w r3, r3, #12 +10002d74: e721 b.n 10002bba <_vsnprintf+0x4a6> +10002d76: 3307 adds r3, #7 +10002d78: f023 0307 bic.w r3, r3, #7 +10002d7c: 4619 mov r1, r3 +10002d7e: 4608 mov r0, r1 +10002d80: 685b ldr r3, [r3, #4] +10002d82: f850 1b08 ldr.w r1, [r0], #8 +10002d86: 0fdf lsrs r7, r3, #31 +10002d88: 900a str r0, [sp, #40] @ 0x28 +10002d8a: ea51 0003 orrs.w r0, r1, r3 +10002d8e: d162 bne.n 10002e56 <_vsnprintf+0x742> +10002d90: 2a00 cmp r2, #0 +10002d92: f040 819f bne.w 100030d4 <_vsnprintf+0x9c0> +10002d96: 4613 mov r3, r2 +10002d98: 4611 mov r1, r2 +10002d9a: aa12 add r2, sp, #72 @ 0x48 +10002d9c: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002da0: 2000 movs r0, #0 +10002da2: 4615 mov r5, r2 +10002da4: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002da8: f8df e348 ldr.w lr, [pc, #840] @ 100030f4 <_vsnprintf+0x9e0> +10002dac: 920b str r2, [sp, #44] @ 0x2c +10002dae: e001 b.n 10002db4 <_vsnprintf+0x6a0> +10002db0: 2820 cmp r0, #32 +10002db2: d02d beq.n 10002e10 <_vsnprintf+0x6fc> +10002db4: 185a adds r2, r3, r1 +10002db6: f142 0200 adc.w r2, r2, #0 +10002dba: fbae 7802 umull r7, r8, lr, r2 +10002dbe: f028 0703 bic.w r7, r8, #3 +10002dc2: eb07 0798 add.w r7, r7, r8, lsr #2 +10002dc6: 1bd2 subs r2, r2, r7 +10002dc8: 461e mov r6, r3 +10002dca: 1a9b subs r3, r3, r2 +10002dcc: f161 0700 sbc.w r7, r1, #0 +10002dd0: 460c mov r4, r1 +10002dd2: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002dd6: fb01 f103 mul.w r1, r1, r3 +10002dda: fb0e 1107 mla r1, lr, r7, r1 +10002dde: fba3 730e umull r7, r3, r3, lr +10002de2: 4419 add r1, r3 +10002de4: 2305 movs r3, #5 +10002de6: f007 0801 and.w r8, r7, #1 +10002dea: fba8 3803 umull r3, r8, r8, r3 +10002dee: 189b adds r3, r3, r2 +10002df0: 2e0a cmp r6, #10 +10002df2: f103 0330 add.w r3, r3, #48 @ 0x30 +10002df6: ea4f 0757 mov.w r7, r7, lsr #1 +10002dfa: f174 0400 sbcs.w r4, r4, #0 +10002dfe: f805 3b01 strb.w r3, [r5], #1 +10002e02: f100 0001 add.w r0, r0, #1 +10002e06: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002e0a: ea4f 0151 mov.w r1, r1, lsr #1 +10002e0e: d2cf bcs.n 10002db0 <_vsnprintf+0x69c> +10002e10: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002e14: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002e18: 9b0b ldr r3, [sp, #44] @ 0x2c +10002e1a: 4642 mov r2, r8 +10002e1c: 9300 str r3, [sp, #0] +10002e1e: 230a movs r3, #10 +10002e20: e9cd 5c05 strd r5, ip, [sp, #20] +10002e24: e9cd 0701 strd r0, r7, [sp, #4] +10002e28: 9604 str r6, [sp, #16] +10002e2a: 9303 str r3, [sp, #12] +10002e2c: 464b mov r3, r9 +10002e2e: 4651 mov r1, sl +10002e30: 4658 mov r0, fp +10002e32: f7fe fe61 bl 10001af8 <_ntoa_format> +10002e36: 4680 mov r8, r0 +10002e38: e48a b.n 10002750 <_vsnprintf+0x3c> +10002e3a: 7819 ldrb r1, [r3, #0] +10002e3c: 460f mov r7, r1 +10002e3e: e764 b.n 10002d0a <_vsnprintf+0x5f6> +10002e40: 2710 movs r7, #16 +10002e42: 46bc mov ip, r7 +10002e44: e6b3 b.n 10002bae <_vsnprintf+0x49a> +10002e46: f023 0c10 bic.w ip, r3, #16 +10002e4a: e745 b.n 10002cd8 <_vsnprintf+0x5c4> +10002e4c: 061c lsls r4, r3, #24 +10002e4e: bf4c ite mi +10002e50: 8812 ldrhmi r2, [r2, #0] +10002e52: 6812 ldrpl r2, [r2, #0] +10002e54: e6c0 b.n 10002bd8 <_vsnprintf+0x4c4> +10002e56: 460a mov r2, r1 +10002e58: 1e19 subs r1, r3, #0 +10002e5a: db01 blt.n 10002e60 <_vsnprintf+0x74c> +10002e5c: 4613 mov r3, r2 +10002e5e: e79c b.n 10002d9a <_vsnprintf+0x686> +10002e60: 4252 negs r2, r2 +10002e62: 4613 mov r3, r2 +10002e64: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002e68: e797 b.n 10002d9a <_vsnprintf+0x686> +10002e6a: 4613 mov r3, r2 +10002e6c: 4651 mov r1, sl +10002e6e: 7818 ldrb r0, [r3, #0] +10002e70: 4642 mov r2, r8 +10002e72: 464b mov r3, r9 +10002e74: 47d8 blx fp +10002e76: 46b0 mov r8, r6 +10002e78: e648 b.n 10002b0c <_vsnprintf+0x3f8> +10002e7a: f013 0f20 tst.w r3, #32 +10002e7e: bf14 ite ne +10002e80: 2041 movne r0, #65 @ 0x41 +10002e82: 2061 moveq r0, #97 @ 0x61 +10002e84: ac12 add r4, sp, #72 @ 0x48 +10002e86: 46a6 mov lr, r4 +10002e88: 940b str r4, [sp, #44] @ 0x2c +10002e8a: 930a str r3, [sp, #40] @ 0x28 +10002e8c: f1a0 040a sub.w r4, r0, #10 +10002e90: 950c str r5, [sp, #48] @ 0x30 +10002e92: e002 b.n 10002e9a <_vsnprintf+0x786> +10002e94: 2920 cmp r1, #32 +10002e96: d012 beq.n 10002ebe <_vsnprintf+0x7aa> +10002e98: 462a mov r2, r5 +10002e9a: fbb2 f5fc udiv r5, r2, ip +10002e9e: fb0c 2015 mls r0, ip, r5, r2 +10002ea2: b2c3 uxtb r3, r0 +10002ea4: 2809 cmp r0, #9 +10002ea6: f103 0030 add.w r0, r3, #48 @ 0x30 +10002eaa: bf8a itet hi +10002eac: 191b addhi r3, r3, r4 +10002eae: b2c3 uxtbls r3, r0 +10002eb0: b2db uxtbhi r3, r3 +10002eb2: 4562 cmp r2, ip +10002eb4: f80e 3b01 strb.w r3, [lr], #1 +10002eb8: f101 0101 add.w r1, r1, #1 +10002ebc: d2ea bcs.n 10002e94 <_vsnprintf+0x780> +10002ebe: 9b0a ldr r3, [sp, #40] @ 0x28 +10002ec0: 9d0c ldr r5, [sp, #48] @ 0x30 +10002ec2: e694 b.n 10002bee <_vsnprintf+0x4da> +10002ec4: 9a0a ldr r2, [sp, #40] @ 0x28 +10002ec6: 3207 adds r2, #7 +10002ec8: f022 0207 bic.w r2, r2, #7 +10002ecc: 6851 ldr r1, [r2, #4] +10002ece: f852 4b08 ldr.w r4, [r2], #8 +10002ed2: 468e mov lr, r1 +10002ed4: 920a str r2, [sp, #40] @ 0x28 +10002ed6: ea54 0201 orrs.w r2, r4, r1 +10002eda: d176 bne.n 10002fca <_vsnprintf+0x8b6> +10002edc: f023 0310 bic.w r3, r3, #16 +10002ee0: 2800 cmp r0, #0 +10002ee2: d072 beq.n 10002fca <_vsnprintf+0x8b6> +10002ee4: 2200 movs r2, #0 +10002ee6: 4611 mov r1, r2 +10002ee8: aa12 add r2, sp, #72 @ 0x48 +10002eea: 920b str r2, [sp, #44] @ 0x2c +10002eec: e9cd 5305 strd r5, r3, [sp, #20] +10002ef0: 9b0b ldr r3, [sp, #44] @ 0x2c +10002ef2: 4642 mov r2, r8 +10002ef4: 9300 str r3, [sp, #0] +10002ef6: 2300 movs r3, #0 +10002ef8: e9cd c603 strd ip, r6, [sp, #12] +10002efc: 9101 str r1, [sp, #4] +10002efe: 9302 str r3, [sp, #8] +10002f00: e794 b.n 10002e2c <_vsnprintf+0x718> +10002f02: 42a5 cmp r5, r4 +10002f04: bf98 it ls +10002f06: 3401 addls r4, #1 +10002f08: f67f ad74 bls.w 100029f4 <_vsnprintf+0x2e0> +10002f0c: f44f 6380 mov.w r3, #1024 @ 0x400 +10002f10: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002f14: eb05 0208 add.w r2, r5, r8 +10002f18: 461f mov r7, r3 +10002f1a: 460d mov r5, r1 +10002f1c: 1b14 subs r4, r2, r4 +10002f1e: 4642 mov r2, r8 +10002f20: 464b mov r3, r9 +10002f22: 4651 mov r1, sl +10002f24: 2020 movs r0, #32 +10002f26: f108 0801 add.w r8, r8, #1 +10002f2a: 47d8 blx fp +10002f2c: 45a0 cmp r8, r4 +10002f2e: d1f6 bne.n 10002f1e <_vsnprintf+0x80a> +10002f30: 463b mov r3, r7 +10002f32: 9f0a ldr r7, [sp, #40] @ 0x28 +10002f34: 4629 mov r1, r5 +10002f36: 7838 ldrb r0, [r7, #0] +10002f38: 9d0b ldr r5, [sp, #44] @ 0x2c +10002f3a: 1c6c adds r4, r5, #1 +10002f3c: 2800 cmp r0, #0 +10002f3e: f43f ad70 beq.w 10002a22 <_vsnprintf+0x30e> +10002f42: 2b00 cmp r3, #0 +10002f44: f43f ae75 beq.w 10002c32 <_vsnprintf+0x51e> +10002f48: 2300 movs r3, #0 +10002f4a: e553 b.n 100029f4 <_vsnprintf+0x2e0> +10002f4c: 42a5 cmp r5, r4 +10002f4e: d8df bhi.n 10002f10 <_vsnprintf+0x7fc> +10002f50: 3401 adds r4, #1 +10002f52: e66e b.n 10002c32 <_vsnprintf+0x51e> +10002f54: 6819 ldr r1, [r3, #0] +10002f56: 0fcb lsrs r3, r1, #31 +10002f58: 2900 cmp r1, #0 +10002f5a: f000 80a8 beq.w 100030ae <_vsnprintf+0x99a> +10002f5e: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002f62: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002f66: a912 add r1, sp, #72 @ 0x48 +10002f68: 4608 mov r0, r1 +10002f6a: f8df e188 ldr.w lr, [pc, #392] @ 100030f4 <_vsnprintf+0x9e0> +10002f6e: 910b str r1, [sp, #44] @ 0x2c +10002f70: 930a str r3, [sp, #40] @ 0x28 +10002f72: 950c str r5, [sp, #48] @ 0x30 +10002f74: e001 b.n 10002f7a <_vsnprintf+0x866> +10002f76: 2f20 cmp r7, #32 +10002f78: d00f beq.n 10002f9a <_vsnprintf+0x886> +10002f7a: 4615 mov r5, r2 +10002f7c: fbae 1302 umull r1, r3, lr, r2 +10002f80: 08db lsrs r3, r3, #3 +10002f82: eb03 0183 add.w r1, r3, r3, lsl #2 +10002f86: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002f8a: 3130 adds r1, #48 @ 0x30 +10002f8c: 2d09 cmp r5, #9 +10002f8e: 461a mov r2, r3 +10002f90: f107 0701 add.w r7, r7, #1 +10002f94: f800 1b01 strb.w r1, [r0], #1 +10002f98: d8ed bhi.n 10002f76 <_vsnprintf+0x862> +10002f9a: 9b0a ldr r3, [sp, #40] @ 0x28 +10002f9c: 9d0c ldr r5, [sp, #48] @ 0x30 +10002f9e: e9cd 5c05 strd r5, ip, [sp, #20] +10002fa2: e9cd 7301 strd r7, r3, [sp, #4] +10002fa6: 9604 str r6, [sp, #16] +10002fa8: e6d5 b.n 10002d56 <_vsnprintf+0x642> +10002faa: 2869 cmp r0, #105 @ 0x69 +10002fac: f023 0c10 bic.w ip, r3, #16 +10002fb0: f040 808c bne.w 100030cc <_vsnprintf+0x9b8> +10002fb4: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002fb8: f43f ae8e beq.w 10002cd8 <_vsnprintf+0x5c4> +10002fbc: e688 b.n 10002cd0 <_vsnprintf+0x5bc> +10002fbe: 2a00 cmp r2, #0 +10002fc0: f43f aea8 beq.w 10002d14 <_vsnprintf+0x600> +10002fc4: aa12 add r2, sp, #72 @ 0x48 +10002fc6: 920b str r2, [sp, #44] @ 0x2c +10002fc8: e6c0 b.n 10002d4c <_vsnprintf+0x638> +10002fca: f013 0f20 tst.w r3, #32 +10002fce: bf14 ite ne +10002fd0: 2241 movne r2, #65 @ 0x41 +10002fd2: 2261 moveq r2, #97 @ 0x61 +10002fd4: 2000 movs r0, #0 +10002fd6: a912 add r1, sp, #72 @ 0x48 +10002fd8: 3a0a subs r2, #10 +10002fda: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002fde: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002fe2: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002fe6: 4606 mov r6, r0 +10002fe8: 4688 mov r8, r1 +10002fea: 4675 mov r5, lr +10002fec: 4693 mov fp, r2 +10002fee: 910b str r1, [sp, #44] @ 0x2c +10002ff0: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002ff4: e003 b.n 10002ffe <_vsnprintf+0x8ea> +10002ff6: 2e20 cmp r6, #32 +10002ff8: d017 beq.n 1000302a <_vsnprintf+0x916> +10002ffa: 4604 mov r4, r0 +10002ffc: 460d mov r5, r1 +10002ffe: 4629 mov r1, r5 +10003000: 463a mov r2, r7 +10003002: 2300 movs r3, #0 +10003004: 4620 mov r0, r4 +10003006: f000 fc47 bl 10003898 <____aeabi_uldivmod_veneer> +1000300a: b2d2 uxtb r2, r2 +1000300c: 2a09 cmp r2, #9 +1000300e: f102 0330 add.w r3, r2, #48 @ 0x30 +10003012: bf88 it hi +10003014: eb02 030b addhi.w r3, r2, fp +10003018: 42bc cmp r4, r7 +1000301a: b2db uxtb r3, r3 +1000301c: f175 0500 sbcs.w r5, r5, #0 +10003020: f808 3b01 strb.w r3, [r8], #1 +10003024: f106 0601 add.w r6, r6, #1 +10003028: d2e5 bcs.n 10002ff6 <_vsnprintf+0x8e2> +1000302a: 4631 mov r1, r6 +1000302c: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10003030: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10003034: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10003038: 9e0e ldr r6, [sp, #56] @ 0x38 +1000303a: e757 b.n 10002eec <_vsnprintf+0x7d8> +1000303c: 990a ldr r1, [sp, #40] @ 0x28 +1000303e: 6809 ldr r1, [r1, #0] +10003040: b951 cbnz r1, 10003058 <_vsnprintf+0x944> +10003042: f023 0310 bic.w r3, r3, #16 +10003046: b138 cbz r0, 10003058 <_vsnprintf+0x944> +10003048: a912 add r1, sp, #72 @ 0x48 +1000304a: 910b str r1, [sp, #44] @ 0x2c +1000304c: e9cd 5305 strd r5, r3, [sp, #20] +10003050: e9cd c603 strd ip, r6, [sp, #12] +10003054: 9201 str r2, [sp, #4] +10003056: e5cf b.n 10002bf8 <_vsnprintf+0x4e4> +10003058: f013 0f20 tst.w r3, #32 +1000305c: bf14 ite ne +1000305e: 2041 movne r0, #65 @ 0x41 +10003060: 2061 moveq r0, #97 @ 0x61 +10003062: ac12 add r4, sp, #72 @ 0x48 +10003064: 46a6 mov lr, r4 +10003066: 940b str r4, [sp, #44] @ 0x2c +10003068: 930a str r3, [sp, #40] @ 0x28 +1000306a: f1a0 040a sub.w r4, r0, #10 +1000306e: 950c str r5, [sp, #48] @ 0x30 +10003070: e002 b.n 10003078 <_vsnprintf+0x964> +10003072: 2a20 cmp r2, #32 +10003074: d012 beq.n 1000309c <_vsnprintf+0x988> +10003076: 4629 mov r1, r5 +10003078: fbb1 f5fc udiv r5, r1, ip +1000307c: fb0c 1015 mls r0, ip, r5, r1 +10003080: b2c3 uxtb r3, r0 +10003082: 2809 cmp r0, #9 +10003084: f103 0030 add.w r0, r3, #48 @ 0x30 +10003088: bf8a itet hi +1000308a: 191b addhi r3, r3, r4 +1000308c: b2c3 uxtbls r3, r0 +1000308e: b2db uxtbhi r3, r3 +10003090: 4561 cmp r1, ip +10003092: f80e 3b01 strb.w r3, [lr], #1 +10003096: f102 0201 add.w r2, r2, #1 +1000309a: d2ea bcs.n 10003072 <_vsnprintf+0x95e> +1000309c: 9b0a ldr r3, [sp, #40] @ 0x28 +1000309e: 9d0c ldr r5, [sp, #48] @ 0x30 +100030a0: e7d4 b.n 1000304c <_vsnprintf+0x938> +100030a2: 6819 ldr r1, [r3, #0] +100030a4: ea81 77e1 eor.w r7, r1, r1, asr #31 +100030a8: eba7 77e1 sub.w r7, r7, r1, asr #31 +100030ac: e62d b.n 10002d0a <_vsnprintf+0x5f6> +100030ae: 2a00 cmp r2, #0 +100030b0: f43f af59 beq.w 10002f66 <_vsnprintf+0x852> +100030b4: aa12 add r2, sp, #72 @ 0x48 +100030b6: 920b str r2, [sp, #44] @ 0x2c +100030b8: e771 b.n 10002f9e <_vsnprintf+0x88a> +100030ba: f413 6480 ands.w r4, r3, #1024 @ 0x400 +100030be: d00d beq.n 100030dc <_vsnprintf+0x9c8> +100030c0: f013 0402 ands.w r4, r3, #2 +100030c4: d012 beq.n 100030ec <_vsnprintf+0x9d8> +100030c6: 4604 mov r4, r0 +100030c8: 4646 mov r6, r8 +100030ca: e5ec b.n 10002ca6 <_vsnprintf+0x592> +100030cc: 270a movs r7, #10 +100030ce: 4663 mov r3, ip +100030d0: 46bc mov ip, r7 +100030d2: e56c b.n 10002bae <_vsnprintf+0x49a> +100030d4: ab12 add r3, sp, #72 @ 0x48 +100030d6: 2000 movs r0, #0 +100030d8: 930b str r3, [sp, #44] @ 0x2c +100030da: e69d b.n 10002e18 <_vsnprintf+0x704> +100030dc: f013 0302 ands.w r3, r3, #2 +100030e0: f47f ade0 bne.w 10002ca4 <_vsnprintf+0x590> +100030e4: 2d00 cmp r5, #0 +100030e6: f47f af13 bne.w 10002f10 <_vsnprintf+0x7fc> +100030ea: e49a b.n 10002a22 <_vsnprintf+0x30e> +100030ec: 2d00 cmp r5, #0 +100030ee: f47f af0d bne.w 10002f0c <_vsnprintf+0x7f8> +100030f2: e496 b.n 10002a22 <_vsnprintf+0x30e> +100030f4: cccccccd .word 0xcccccccd + +100030f8 : +100030f8: b570 push {r4, r5, r6, lr} +100030fa: 4694 mov ip, r2 +100030fc: 461e mov r6, r3 +100030fe: 4605 mov r5, r0 +10003100: 460c mov r4, r1 +10003102: b084 sub sp, #16 +10003104: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003108: 4663 mov r3, ip +1000310a: a902 add r1, sp, #8 +1000310c: 9600 str r6, [sp, #0] +1000310e: 4803 ldr r0, [pc, #12] @ (1000311c ) +10003110: e9cd 5402 strd r5, r4, [sp, #8] +10003114: f7ff fafe bl 10002714 <_vsnprintf> +10003118: b004 add sp, #16 +1000311a: bd70 pop {r4, r5, r6, pc} +1000311c: 10001cd5 .word 0x10001cd5 + +10003120 : +10003120: b510 push {r4, lr} +10003122: 4b09 ldr r3, [pc, #36] @ (10003148 ) +10003124: b084 sub sp, #16 +10003126: 681c ldr r4, [r3, #0] +10003128: b14c cbz r4, 1000313e +1000312a: 4603 mov r3, r0 +1000312c: 9100 str r1, [sp, #0] +1000312e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10003132: a903 add r1, sp, #12 +10003134: 4805 ldr r0, [pc, #20] @ (1000314c ) +10003136: 47a0 blx r4 +10003138: 2001 movs r0, #1 +1000313a: b004 add sp, #16 +1000313c: bd10 pop {r4, pc} +1000313e: f000 f97d bl 1000343c <__wrap_puts> +10003142: 4620 mov r0, r4 +10003144: b004 add sp, #16 +10003146: bd10 pop {r4, pc} +10003148: 20000810 .word 0x20000810 +1000314c: 10001ccd .word 0x10001ccd + +10003150 <_exit>: +10003150: be00 bkpt 0x0000 +10003152: e7fd b.n 10003150 <_exit> + +10003154 : +10003154: b508 push {r3, lr} +10003156: f7ff fffb bl 10003150 <_exit> +1000315a: bf00 nop + +1000315c : +1000315c: b538 push {r3, r4, r5, lr} +1000315e: 4c06 ldr r4, [pc, #24] @ (10003178 ) +10003160: 4d06 ldr r5, [pc, #24] @ (1000317c ) +10003162: f7fe fa07 bl 10001574 +10003166: 42ac cmp r4, r5 +10003168: d204 bcs.n 10003174 +1000316a: f854 3b04 ldr.w r3, [r4], #4 +1000316e: 4798 blx r3 +10003170: 42ac cmp r4, r5 +10003172: d3fa bcc.n 1000316a +10003174: bd38 pop {r3, r4, r5, pc} +10003176: bf00 nop +10003178: 100038f0 .word 0x100038f0 +1000317c: 100038f4 .word 0x100038f4 + +10003180 : +10003180: 6803 ldr r3, [r0, #0] +10003182: 4608 mov r0, r1 +10003184: 4611 mov r1, r2 +10003186: 4718 bx r3 + +10003188 : +10003188: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000318c: 4615 mov r5, r2 +1000318e: 7d42 ldrb r2, [r0, #21] +10003190: 4607 mov r7, r0 +10003192: 4688 mov r8, r1 +10003194: 2a00 cmp r2, #0 +10003196: d046 beq.n 10003226 +10003198: 2d00 cmp r5, #0 +1000319a: dd1d ble.n 100031d8 +1000319c: 780b ldrb r3, [r1, #0] +1000319e: 2b0a cmp r3, #10 +100031a0: d023 beq.n 100031ea +100031a2: 2d01 cmp r5, #1 +100031a4: f04f 0c00 mov.w ip, #0 +100031a8: d018 beq.n 100031dc +100031aa: 4646 mov r6, r8 +100031ac: 2401 movs r4, #1 +100031ae: f816 2f01 ldrb.w r2, [r6, #1]! +100031b2: 4621 mov r1, r4 +100031b4: 2a0a cmp r2, #10 +100031b6: f104 0401 add.w r4, r4, #1 +100031ba: d022 beq.n 10003202 +100031bc: 42a5 cmp r5, r4 +100031be: d1f6 bne.n 100031ae +100031c0: 4565 cmp r5, ip +100031c2: dc0b bgt.n 100031dc +100031c4: eb08 0305 add.w r3, r8, r5 +100031c8: f813 3c01 ldrb.w r3, [r3, #-1] +100031cc: f1a3 030d sub.w r3, r3, #13 +100031d0: fab3 f383 clz r3, r3 +100031d4: 095b lsrs r3, r3, #5 +100031d6: 753b strb r3, [r7, #20] +100031d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100031dc: 683b ldr r3, [r7, #0] +100031de: eba5 010c sub.w r1, r5, ip +100031e2: eb08 000c add.w r0, r8, ip +100031e6: 4798 blx r3 +100031e8: e7ec b.n 100031c4 +100031ea: 7d03 ldrb r3, [r0, #20] +100031ec: 2b00 cmp r3, #0 +100031ee: d1d8 bne.n 100031a2 +100031f0: 6803 ldr r3, [r0, #0] +100031f2: 2102 movs r1, #2 +100031f4: 480f ldr r0, [pc, #60] @ (10003234 ) +100031f6: 4798 blx r3 +100031f8: 2d01 cmp r5, #1 +100031fa: d0e3 beq.n 100031c4 +100031fc: f04f 0c01 mov.w ip, #1 +10003200: e7d3 b.n 100031aa +10003202: f816 3c01 ldrb.w r3, [r6, #-1] +10003206: 2b0d cmp r3, #13 +10003208: d0d8 beq.n 100031bc +1000320a: 458c cmp ip, r1 +1000320c: eb08 000c add.w r0, r8, ip +10003210: eba1 010c sub.w r1, r1, ip +10003214: da01 bge.n 1000321a +10003216: 683b ldr r3, [r7, #0] +10003218: 4798 blx r3 +1000321a: 2102 movs r1, #2 +1000321c: 4805 ldr r0, [pc, #20] @ (10003234 ) +1000321e: 683b ldr r3, [r7, #0] +10003220: 4798 blx r3 +10003222: 46a4 mov ip, r4 +10003224: e7ca b.n 100031bc +10003226: 4629 mov r1, r5 +10003228: 4640 mov r0, r8 +1000322a: 683b ldr r3, [r7, #0] +1000322c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10003230: 4718 bx r3 +10003232: bf00 nop +10003234: 10003ad8 .word 0x10003ad8 + +10003238 : +10003238: 680b ldr r3, [r1, #0] +1000323a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000323e: 2b80 cmp r3, #128 @ 0x80 +10003240: 460d mov r5, r1 +10003242: 4606 mov r6, r0 +10003244: d005 beq.n 10003252 +10003246: 1c5a adds r2, r3, #1 +10003248: 442b add r3, r5 +1000324a: 602a str r2, [r5, #0] +1000324c: 711e strb r6, [r3, #4] +1000324e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003252: 4b0f ldr r3, [pc, #60] @ (10003290 ) +10003254: 681c ldr r4, [r3, #0] +10003256: b1a4 cbz r4, 10003282 +10003258: 4f0e ldr r7, [pc, #56] @ (10003294 ) +1000325a: f101 0804 add.w r8, r1, #4 +1000325e: e001 b.n 10003264 +10003260: 6924 ldr r4, [r4, #16] +10003262: b174 cbz r4, 10003282 +10003264: 6823 ldr r3, [r4, #0] +10003266: 2b00 cmp r3, #0 +10003268: d0fa beq.n 10003260 +1000326a: 683b ldr r3, [r7, #0] +1000326c: b10b cbz r3, 10003272 +1000326e: 42a3 cmp r3, r4 +10003270: d1f6 bne.n 10003260 +10003272: 4620 mov r0, r4 +10003274: 4641 mov r1, r8 +10003276: 682a ldr r2, [r5, #0] +10003278: f7ff ff86 bl 10003188 +1000327c: 6924 ldr r4, [r4, #16] +1000327e: 2c00 cmp r4, #0 +10003280: d1f0 bne.n 10003264 +10003282: 2300 movs r3, #0 +10003284: 2201 movs r2, #1 +10003286: 442b add r3, r5 +10003288: 602a str r2, [r5, #0] +1000328a: 711e strb r6, [r3, #4] +1000328c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003290: 20000804 .word 0x20000804 +10003294: 20000808 .word 0x20000808 + +10003298 : +10003298: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +1000329c: b082 sub sp, #8 +1000329e: 460d mov r5, r1 +100032a0: 4691 mov r9, r2 +100032a2: 461c mov r4, r3 +100032a4: 4606 mov r6, r0 +100032a6: f7fd ff95 bl 100011d4 +100032aa: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +100032ae: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +100032b2: 4a2e ldr r2, [pc, #184] @ (1000336c ) +100032b4: 1882 adds r2, r0, r2 +100032b6: f141 0300 adc.w r3, r1, #0 +100032ba: 4594 cmp ip, r2 +100032bc: eb77 0103 sbcs.w r1, r7, r3 +100032c0: bf3c itt cc +100032c2: 4662 movcc r2, ip +100032c4: 463b movcc r3, r7 +100032c6: 482a ldr r0, [pc, #168] @ (10003370 ) +100032c8: f000 faee bl 100038a8 <__mutex_try_enter_block_until_veneer> +100032cc: 1c6b adds r3, r5, #1 +100032ce: 4680 mov r8, r0 +100032d0: d040 beq.n 10003354 +100032d2: b30c cbz r4, 10003318 +100032d4: 4f27 ldr r7, [pc, #156] @ (10003374 ) +100032d6: 4b28 ldr r3, [pc, #160] @ (10003378 ) +100032d8: 681c ldr r4, [r3, #0] +100032da: b1b4 cbz r4, 1000330a +100032dc: f1b9 0f00 cmp.w r9, #0 +100032e0: d11c bne.n 1000331c +100032e2: f8df 909c ldr.w r9, [pc, #156] @ 10003380 +100032e6: e001 b.n 100032ec +100032e8: 6924 ldr r4, [r4, #16] +100032ea: b174 cbz r4, 1000330a +100032ec: 6823 ldr r3, [r4, #0] +100032ee: 2b00 cmp r3, #0 +100032f0: d0fa beq.n 100032e8 +100032f2: f8d9 3000 ldr.w r3, [r9] +100032f6: b10b cbz r3, 100032fc +100032f8: 429c cmp r4, r3 +100032fa: d1f5 bne.n 100032e8 +100032fc: 4620 mov r0, r4 +100032fe: 462a mov r2, r5 +10003300: 4631 mov r1, r6 +10003302: 47b8 blx r7 +10003304: 6924 ldr r4, [r4, #16] +10003306: 2c00 cmp r4, #0 +10003308: d1f0 bne.n 100032ec +1000330a: f1b8 0f00 cmp.w r8, #0 +1000330e: d126 bne.n 1000335e +10003310: 4628 mov r0, r5 +10003312: b002 add sp, #8 +10003314: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003318: 4f18 ldr r7, [pc, #96] @ (1000337c ) +1000331a: e7dc b.n 100032d6 +1000331c: f04f 0a0a mov.w sl, #10 +10003320: f8df 905c ldr.w r9, [pc, #92] @ 10003380 +10003324: e002 b.n 1000332c +10003326: 6924 ldr r4, [r4, #16] +10003328: 2c00 cmp r4, #0 +1000332a: d0ee beq.n 1000330a +1000332c: 6823 ldr r3, [r4, #0] +1000332e: 2b00 cmp r3, #0 +10003330: d0f9 beq.n 10003326 +10003332: f8d9 3000 ldr.w r3, [r9] +10003336: b10b cbz r3, 1000333c +10003338: 42a3 cmp r3, r4 +1000333a: d1f4 bne.n 10003326 +1000333c: 462a mov r2, r5 +1000333e: 4631 mov r1, r6 +10003340: 4620 mov r0, r4 +10003342: 47b8 blx r7 +10003344: 2201 movs r2, #1 +10003346: 4620 mov r0, r4 +10003348: f10d 0107 add.w r1, sp, #7 +1000334c: f88d a007 strb.w sl, [sp, #7] +10003350: 47b8 blx r7 +10003352: e7e8 b.n 10003326 +10003354: 4630 mov r0, r6 +10003356: f000 fa6f bl 10003838 +1000335a: 4605 mov r5, r0 +1000335c: e7b9 b.n 100032d2 +1000335e: 4804 ldr r0, [pc, #16] @ (10003370 ) +10003360: f000 fa9e bl 100038a0 <__mutex_exit_veneer> +10003364: 4628 mov r0, r5 +10003366: b002 add sp, #8 +10003368: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +1000336c: 000f4240 .word 0x000f4240 +10003370: 20000624 .word 0x20000624 +10003374: 10003189 .word 0x10003189 +10003378: 20000804 .word 0x20000804 +1000337c: 10003181 .word 0x10003181 +10003380: 20000808 .word 0x20000808 + +10003384 : +10003384: 4a08 ldr r2, [pc, #32] @ (100033a8 ) +10003386: 6813 ldr r3, [r2, #0] +10003388: b923 cbnz r3, 10003394 +1000338a: e00a b.n 100033a2 +1000338c: f103 0210 add.w r2, r3, #16 +10003390: 691b ldr r3, [r3, #16] +10003392: b133 cbz r3, 100033a2 +10003394: 4283 cmp r3, r0 +10003396: d1f9 bne.n 1000338c +10003398: b929 cbnz r1, 100033a6 +1000339a: 6918 ldr r0, [r3, #16] +1000339c: 6010 str r0, [r2, #0] +1000339e: 6119 str r1, [r3, #16] +100033a0: 4770 bx lr +100033a2: b101 cbz r1, 100033a6 +100033a4: 6010 str r0, [r2, #0] +100033a6: 4770 bx lr +100033a8: 20000804 .word 0x20000804 + +100033ac : +100033ac: b508 push {r3, lr} +100033ae: f000 f9a3 bl 100036f8 +100033b2: 2001 movs r0, #1 +100033b4: bd08 pop {r3, pc} +100033b6: bf00 nop + +100033b8 <__wrap_putchar>: +100033b8: b5f0 push {r4, r5, r6, r7, lr} +100033ba: b083 sub sp, #12 +100033bc: 4606 mov r6, r0 +100033be: f88d 0007 strb.w r0, [sp, #7] +100033c2: f7fd ff07 bl 100011d4 +100033c6: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +100033ca: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +100033ce: 4a17 ldr r2, [pc, #92] @ (1000342c <__wrap_putchar+0x74>) +100033d0: 1882 adds r2, r0, r2 +100033d2: f141 0300 adc.w r3, r1, #0 +100033d6: 4295 cmp r5, r2 +100033d8: eb74 0103 sbcs.w r1, r4, r3 +100033dc: bf3c itt cc +100033de: 4623 movcc r3, r4 +100033e0: 462a movcc r2, r5 +100033e2: 4813 ldr r0, [pc, #76] @ (10003430 <__wrap_putchar+0x78>) +100033e4: f000 fa60 bl 100038a8 <__mutex_try_enter_block_until_veneer> +100033e8: 4b12 ldr r3, [pc, #72] @ (10003434 <__wrap_putchar+0x7c>) +100033ea: 4607 mov r7, r0 +100033ec: 681c ldr r4, [r3, #0] +100033ee: b19c cbz r4, 10003418 <__wrap_putchar+0x60> +100033f0: 4d11 ldr r5, [pc, #68] @ (10003438 <__wrap_putchar+0x80>) +100033f2: e001 b.n 100033f8 <__wrap_putchar+0x40> +100033f4: 6924 ldr r4, [r4, #16] +100033f6: b17c cbz r4, 10003418 <__wrap_putchar+0x60> +100033f8: 6823 ldr r3, [r4, #0] +100033fa: 2b00 cmp r3, #0 +100033fc: d0fa beq.n 100033f4 <__wrap_putchar+0x3c> +100033fe: 682b ldr r3, [r5, #0] +10003400: b10b cbz r3, 10003406 <__wrap_putchar+0x4e> +10003402: 429c cmp r4, r3 +10003404: d1f6 bne.n 100033f4 <__wrap_putchar+0x3c> +10003406: 4620 mov r0, r4 +10003408: 2201 movs r2, #1 +1000340a: f10d 0107 add.w r1, sp, #7 +1000340e: f7ff febb bl 10003188 +10003412: 6924 ldr r4, [r4, #16] +10003414: 2c00 cmp r4, #0 +10003416: d1ef bne.n 100033f8 <__wrap_putchar+0x40> +10003418: b917 cbnz r7, 10003420 <__wrap_putchar+0x68> +1000341a: 4630 mov r0, r6 +1000341c: b003 add sp, #12 +1000341e: bdf0 pop {r4, r5, r6, r7, pc} +10003420: 4803 ldr r0, [pc, #12] @ (10003430 <__wrap_putchar+0x78>) +10003422: f000 fa3d bl 100038a0 <__mutex_exit_veneer> +10003426: 4630 mov r0, r6 +10003428: b003 add sp, #12 +1000342a: bdf0 pop {r4, r5, r6, r7, pc} +1000342c: 000f4240 .word 0x000f4240 +10003430: 20000624 .word 0x20000624 +10003434: 20000804 .word 0x20000804 +10003438: 20000808 .word 0x20000808 + +1000343c <__wrap_puts>: +1000343c: b538 push {r3, r4, r5, lr} +1000343e: 4604 mov r4, r0 +10003440: f000 f9fa bl 10003838 +10003444: 2301 movs r3, #1 +10003446: 4605 mov r5, r0 +10003448: 461a mov r2, r3 +1000344a: 4620 mov r0, r4 +1000344c: 4629 mov r1, r5 +1000344e: f7ff ff23 bl 10003298 +10003452: 4b08 ldr r3, [pc, #32] @ (10003474 <__wrap_puts+0x38>) +10003454: 681c ldr r4, [r3, #0] +10003456: b12c cbz r4, 10003464 <__wrap_puts+0x28> +10003458: 6863 ldr r3, [r4, #4] +1000345a: b12b cbz r3, 10003468 <__wrap_puts+0x2c> +1000345c: 4798 blx r3 +1000345e: 6924 ldr r4, [r4, #16] +10003460: 2c00 cmp r4, #0 +10003462: d1f9 bne.n 10003458 <__wrap_puts+0x1c> +10003464: 4628 mov r0, r5 +10003466: bd38 pop {r3, r4, r5, pc} +10003468: 6924 ldr r4, [r4, #16] +1000346a: 2c00 cmp r4, #0 +1000346c: d1f4 bne.n 10003458 <__wrap_puts+0x1c> +1000346e: 4628 mov r0, r5 +10003470: bd38 pop {r3, r4, r5, pc} +10003472: bf00 nop +10003474: 20000804 .word 0x20000804 + +10003478 <__wrap_vprintf>: +10003478: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000347c: b0a2 sub sp, #136 @ 0x88 +1000347e: 4604 mov r4, r0 +10003480: 460d mov r5, r1 +10003482: f7fd fea7 bl 100011d4 +10003486: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +1000348a: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +1000348e: 4a26 ldr r2, [pc, #152] @ (10003528 <__wrap_vprintf+0xb0>) +10003490: f8df 80a4 ldr.w r8, [pc, #164] @ 10003538 <__wrap_vprintf+0xc0> +10003494: 1882 adds r2, r0, r2 +10003496: f141 0300 adc.w r3, r1, #0 +1000349a: 4297 cmp r7, r2 +1000349c: eb76 0103 sbcs.w r1, r6, r3 +100034a0: bf3c itt cc +100034a2: 463a movcc r2, r7 +100034a4: 4633 movcc r3, r6 +100034a6: 4821 ldr r0, [pc, #132] @ (1000352c <__wrap_vprintf+0xb4>) +100034a8: f000 f9fe bl 100038a8 <__mutex_try_enter_block_until_veneer> +100034ac: 2700 movs r7, #0 +100034ae: 462b mov r3, r5 +100034b0: 4622 mov r2, r4 +100034b2: 4606 mov r6, r0 +100034b4: a901 add r1, sp, #4 +100034b6: 481e ldr r0, [pc, #120] @ (10003530 <__wrap_vprintf+0xb8>) +100034b8: 9701 str r7, [sp, #4] +100034ba: f7ff fe1d bl 100030f8 +100034be: 9b01 ldr r3, [sp, #4] +100034c0: 4605 mov r5, r0 +100034c2: f8d8 4000 ldr.w r4, [r8] +100034c6: b1c3 cbz r3, 100034fa <__wrap_vprintf+0x82> +100034c8: 2c00 cmp r4, #0 +100034ca: d02b beq.n 10003524 <__wrap_vprintf+0xac> +100034cc: 4f19 ldr r7, [pc, #100] @ (10003534 <__wrap_vprintf+0xbc>) +100034ce: e001 b.n 100034d4 <__wrap_vprintf+0x5c> +100034d0: 6924 ldr r4, [r4, #16] +100034d2: b174 cbz r4, 100034f2 <__wrap_vprintf+0x7a> +100034d4: 6823 ldr r3, [r4, #0] +100034d6: 2b00 cmp r3, #0 +100034d8: d0fa beq.n 100034d0 <__wrap_vprintf+0x58> +100034da: 683b ldr r3, [r7, #0] +100034dc: b10b cbz r3, 100034e2 <__wrap_vprintf+0x6a> +100034de: 42a3 cmp r3, r4 +100034e0: d1f6 bne.n 100034d0 <__wrap_vprintf+0x58> +100034e2: 4620 mov r0, r4 +100034e4: 9a01 ldr r2, [sp, #4] +100034e6: a902 add r1, sp, #8 +100034e8: f7ff fe4e bl 10003188 +100034ec: 6924 ldr r4, [r4, #16] +100034ee: 2c00 cmp r4, #0 +100034f0: d1f0 bne.n 100034d4 <__wrap_vprintf+0x5c> +100034f2: 2300 movs r3, #0 +100034f4: f8d8 4000 ldr.w r4, [r8] +100034f8: 9301 str r3, [sp, #4] +100034fa: b12c cbz r4, 10003508 <__wrap_vprintf+0x90> +100034fc: 6863 ldr r3, [r4, #4] +100034fe: b143 cbz r3, 10003512 <__wrap_vprintf+0x9a> +10003500: 4798 blx r3 +10003502: 6924 ldr r4, [r4, #16] +10003504: 2c00 cmp r4, #0 +10003506: d1f9 bne.n 100034fc <__wrap_vprintf+0x84> +10003508: b92e cbnz r6, 10003516 <__wrap_vprintf+0x9e> +1000350a: 4628 mov r0, r5 +1000350c: b022 add sp, #136 @ 0x88 +1000350e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003512: 6924 ldr r4, [r4, #16] +10003514: e7f1 b.n 100034fa <__wrap_vprintf+0x82> +10003516: 4805 ldr r0, [pc, #20] @ (1000352c <__wrap_vprintf+0xb4>) +10003518: f000 f9c2 bl 100038a0 <__mutex_exit_veneer> +1000351c: 4628 mov r0, r5 +1000351e: b022 add sp, #136 @ 0x88 +10003520: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003524: 9401 str r4, [sp, #4] +10003526: e7ef b.n 10003508 <__wrap_vprintf+0x90> +10003528: 000f4240 .word 0x000f4240 +1000352c: 20000624 .word 0x20000624 +10003530: 10003239 .word 0x10003239 +10003534: 20000808 .word 0x20000808 +10003538: 20000804 .word 0x20000804 + +1000353c <__wrap_printf>: +1000353c: b40f push {r0, r1, r2, r3} +1000353e: b500 push {lr} +10003540: b083 sub sp, #12 +10003542: a904 add r1, sp, #16 +10003544: f851 0b04 ldr.w r0, [r1], #4 +10003548: 9101 str r1, [sp, #4] +1000354a: f7ff ff95 bl 10003478 <__wrap_vprintf> +1000354e: b003 add sp, #12 +10003550: f85d eb04 ldr.w lr, [sp], #4 +10003554: b004 add sp, #16 +10003556: 4770 bx lr + +10003558 : +10003558: f1b1 0c00 subs.w ip, r1, #0 +1000355c: dd1d ble.n 1000359a +1000355e: 4a0f ldr r2, [pc, #60] @ (1000359c ) +10003560: 4b0f ldr r3, [pc, #60] @ (100035a0 ) +10003562: 6812 ldr r2, [r2, #0] +10003564: b530 push {r4, r5, lr} +10003566: 1ad3 subs r3, r2, r3 +10003568: fab3 f383 clz r3, r3 +1000356c: 240d movs r4, #13 +1000356e: 4d0d ldr r5, [pc, #52] @ (100035a4 ) +10003570: 095b lsrs r3, r3, #5 +10003572: 1e41 subs r1, r0, #1 +10003574: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10003578: 448c add ip, r1 +1000357a: f811 0f01 ldrb.w r0, [r1, #1]! +1000357e: 4586 cmp lr, r0 +10003580: d006 beq.n 10003590 +10003582: 6993 ldr r3, [r2, #24] +10003584: 069b lsls r3, r3, #26 +10003586: d4fc bmi.n 10003582 +10003588: 4561 cmp r1, ip +1000358a: 6010 str r0, [r2, #0] +1000358c: d1f5 bne.n 1000357a +1000358e: bd30 pop {r4, r5, pc} +10003590: 6993 ldr r3, [r2, #24] +10003592: 069d lsls r5, r3, #26 +10003594: d4fc bmi.n 10003590 +10003596: 6014 str r4, [r2, #0] +10003598: e7f3 b.n 10003582 +1000359a: 4770 bx lr +1000359c: 20000854 .word 0x20000854 +100035a0: 40078000 .word 0x40078000 +100035a4: 20000850 .word 0x20000850 + +100035a8 : +100035a8: 4b22 ldr r3, [pc, #136] @ (10003634 ) +100035aa: f1b1 0c00 subs.w ip, r1, #0 +100035ae: b410 push {r4} +100035b0: 681c ldr r4, [r3, #0] +100035b2: dd2e ble.n 10003612 +100035b4: 4603 mov r3, r0 +100035b6: 2000 movs r0, #0 +100035b8: 4a1f ldr r2, [pc, #124] @ (10003638 ) +100035ba: 1e59 subs r1, r3, #1 +100035bc: 6812 ldr r2, [r2, #0] +100035be: 6993 ldr r3, [r2, #24] +100035c0: 06db lsls r3, r3, #27 +100035c2: d417 bmi.n 100035f4 +100035c4: 3001 adds r0, #1 +100035c6: 6993 ldr r3, [r2, #24] +100035c8: 06db lsls r3, r3, #27 +100035ca: d4fc bmi.n 100035c6 +100035cc: 6813 ldr r3, [r2, #0] +100035ce: 4584 cmp ip, r0 +100035d0: f801 3f01 strb.w r3, [r1, #1]! +100035d4: d1f3 bne.n 100035be +100035d6: b14c cbz r4, 100035ec +100035d8: 2150 movs r1, #80 @ 0x50 +100035da: 4613 mov r3, r2 +100035dc: 6391 str r1, [r2, #56] @ 0x38 +100035de: f853 2f34 ldr.w r2, [r3, #52]! +100035e2: f002 0238 and.w r2, r2, #56 @ 0x38 +100035e6: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100035ea: 601a str r2, [r3, #0] +100035ec: 4660 mov r0, ip +100035ee: f85d 4b04 ldr.w r4, [sp], #4 +100035f2: 4770 bx lr +100035f4: b14c cbz r4, 1000360a +100035f6: 2150 movs r1, #80 @ 0x50 +100035f8: 4613 mov r3, r2 +100035fa: 6391 str r1, [r2, #56] @ 0x38 +100035fc: f853 2f34 ldr.w r2, [r3, #52]! +10003600: f002 0238 and.w r2, r2, #56 @ 0x38 +10003604: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003608: 601a str r2, [r3, #0] +1000360a: b178 cbz r0, 1000362c +1000360c: f85d 4b04 ldr.w r4, [sp], #4 +10003610: 4770 bx lr +10003612: b15c cbz r4, 1000362c +10003614: 4b08 ldr r3, [pc, #32] @ (10003638 ) +10003616: 2150 movs r1, #80 @ 0x50 +10003618: 681a ldr r2, [r3, #0] +1000361a: 4613 mov r3, r2 +1000361c: 6391 str r1, [r2, #56] @ 0x38 +1000361e: f853 2f34 ldr.w r2, [r3, #52]! +10003622: f002 0238 and.w r2, r2, #56 @ 0x38 +10003626: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000362a: 601a str r2, [r3, #0] +1000362c: f06f 0002 mvn.w r0, #2 +10003630: e7dd b.n 100035ee +10003632: bf00 nop +10003634: 200007d0 .word 0x200007d0 +10003638: 20000854 .word 0x20000854 + +1000363c : +1000363c: 4b05 ldr r3, [pc, #20] @ (10003654 ) +1000363e: 681b ldr r3, [r3, #0] +10003640: b133 cbz r3, 10003650 +10003642: 2100 movs r1, #0 +10003644: 4a04 ldr r2, [pc, #16] @ (10003658 ) +10003646: 4805 ldr r0, [pc, #20] @ (1000365c ) +10003648: 6812 ldr r2, [r2, #0] +1000364a: 6800 ldr r0, [r0, #0] +1000364c: 6391 str r1, [r2, #56] @ 0x38 +1000364e: 4718 bx r3 +10003650: 4770 bx lr +10003652: bf00 nop +10003654: 200007d0 .word 0x200007d0 +10003658: 20000854 .word 0x20000854 +1000365c: 200007d4 .word 0x200007d4 + +10003660 : +10003660: 4b02 ldr r3, [pc, #8] @ (1000366c ) +10003662: 681a ldr r2, [r3, #0] +10003664: 6993 ldr r3, [r2, #24] +10003666: 071b lsls r3, r3, #28 +10003668: d4fc bmi.n 10003664 +1000366a: 4770 bx lr +1000366c: 20000854 .word 0x20000854 + +10003670 : +10003670: b5f8 push {r3, r4, r5, r6, r7, lr} +10003672: 4f1c ldr r7, [pc, #112] @ (100036e4 ) +10003674: 4d1c ldr r5, [pc, #112] @ (100036e8 ) +10003676: 683a ldr r2, [r7, #0] +10003678: 4e1c ldr r6, [pc, #112] @ (100036ec ) +1000367a: 42aa cmp r2, r5 +1000367c: bf14 ite ne +1000367e: 2521 movne r5, #33 @ 0x21 +10003680: 2522 moveq r5, #34 @ 0x22 +10003682: 4604 mov r4, r0 +10003684: f8d6 c000 ldr.w ip, [r6] +10003688: b118 cbz r0, 10003692 +1000368a: f1bc 0f00 cmp.w ip, #0 +1000368e: d010 beq.n 100036b2 +10003690: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003692: f1bc 0f00 cmp.w ip, #0 +10003696: d0fb beq.n 10003690 +10003698: 4601 mov r1, r0 +1000369a: 6390 str r0, [r2, #56] @ 0x38 +1000369c: 4628 mov r0, r5 +1000369e: f7fd f823 bl 100006e8 +100036a2: 4628 mov r0, r5 +100036a4: 4912 ldr r1, [pc, #72] @ (100036f0 ) +100036a6: f7fd f865 bl 10000774 +100036aa: 4b12 ldr r3, [pc, #72] @ (100036f4 ) +100036ac: 6034 str r4, [r6, #0] +100036ae: 601c str r4, [r3, #0] +100036b0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100036b2: 460b mov r3, r1 +100036b4: 4a0f ldr r2, [pc, #60] @ (100036f4 ) +100036b6: 490e ldr r1, [pc, #56] @ (100036f0 ) +100036b8: 6030 str r0, [r6, #0] +100036ba: 4628 mov r0, r5 +100036bc: 6013 str r3, [r2, #0] +100036be: f7fd f829 bl 10000714 +100036c2: 2101 movs r1, #1 +100036c4: 4628 mov r0, r5 +100036c6: f7fd f80f bl 100006e8 +100036ca: 683a ldr r2, [r7, #0] +100036cc: 2150 movs r1, #80 @ 0x50 +100036ce: 4613 mov r3, r2 +100036d0: 6391 str r1, [r2, #56] @ 0x38 +100036d2: f853 2f34 ldr.w r2, [r3, #52]! +100036d6: f002 0238 and.w r2, r2, #56 @ 0x38 +100036da: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100036de: 601a str r2, [r3, #0] +100036e0: bdf8 pop {r3, r4, r5, r6, r7, pc} +100036e2: bf00 nop +100036e4: 20000854 .word 0x20000854 +100036e8: 40078000 .word 0x40078000 +100036ec: 200007d0 .word 0x200007d0 +100036f0: 1000363d .word 0x1000363d +100036f4: 200007d4 .word 0x200007d4 + +100036f8 : +100036f8: b510 push {r4, lr} +100036fa: 490e ldr r1, [pc, #56] @ (10003734 ) +100036fc: 4c0e ldr r4, [pc, #56] @ (10003738 ) +100036fe: 480f ldr r0, [pc, #60] @ (1000373c ) +10003700: 4a0f ldr r2, [pc, #60] @ (10003740 ) +10003702: 4b10 ldr r3, [pc, #64] @ (10003744 ) +10003704: 7800 ldrb r0, [r0, #0] +10003706: 6021 str r1, [r4, #0] +10003708: 2000 movs r0, #0 +1000370a: 2102 movs r1, #2 +1000370c: 7812 ldrb r2, [r2, #0] +1000370e: 781b ldrb r3, [r3, #0] +10003710: f7fc ff10 bl 10000534 +10003714: 2102 movs r1, #2 +10003716: 2001 movs r0, #1 +10003718: f7fc ff0c bl 10000534 +1000371c: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +10003720: 6820 ldr r0, [r4, #0] +10003722: f7fd fda1 bl 10001268 +10003726: e8bd 4010 ldmia.w sp!, {r4, lr} +1000372a: 2101 movs r1, #1 +1000372c: 4806 ldr r0, [pc, #24] @ (10003748 ) +1000372e: f7ff be29 b.w 10003384 +10003732: bf00 nop +10003734: 40070000 .word 0x40070000 +10003738: 20000854 .word 0x20000854 +1000373c: 10003b28 .word 0x10003b28 +10003740: 10003b24 .word 0x10003b24 +10003744: 10003b20 .word 0x10003b20 +10003748: 2000060c .word 0x2000060c + +1000374c : +1000374c: 4684 mov ip, r0 +1000374e: ea41 0300 orr.w r3, r1, r0 +10003752: f013 0303 ands.w r3, r3, #3 +10003756: d149 bne.n 100037ec +10003758: 3a40 subs r2, #64 @ 0x40 +1000375a: d323 bcc.n 100037a4 +1000375c: 680b ldr r3, [r1, #0] +1000375e: 6003 str r3, [r0, #0] +10003760: 684b ldr r3, [r1, #4] +10003762: 6043 str r3, [r0, #4] +10003764: 688b ldr r3, [r1, #8] +10003766: 6083 str r3, [r0, #8] +10003768: 68cb ldr r3, [r1, #12] +1000376a: 60c3 str r3, [r0, #12] +1000376c: 690b ldr r3, [r1, #16] +1000376e: 6103 str r3, [r0, #16] +10003770: 694b ldr r3, [r1, #20] +10003772: 6143 str r3, [r0, #20] +10003774: 698b ldr r3, [r1, #24] +10003776: 6183 str r3, [r0, #24] +10003778: 69cb ldr r3, [r1, #28] +1000377a: 61c3 str r3, [r0, #28] +1000377c: 6a0b ldr r3, [r1, #32] +1000377e: 6203 str r3, [r0, #32] +10003780: 6a4b ldr r3, [r1, #36] @ 0x24 +10003782: 6243 str r3, [r0, #36] @ 0x24 +10003784: 6a8b ldr r3, [r1, #40] @ 0x28 +10003786: 6283 str r3, [r0, #40] @ 0x28 +10003788: 6acb ldr r3, [r1, #44] @ 0x2c +1000378a: 62c3 str r3, [r0, #44] @ 0x2c +1000378c: 6b0b ldr r3, [r1, #48] @ 0x30 +1000378e: 6303 str r3, [r0, #48] @ 0x30 +10003790: 6b4b ldr r3, [r1, #52] @ 0x34 +10003792: 6343 str r3, [r0, #52] @ 0x34 +10003794: 6b8b ldr r3, [r1, #56] @ 0x38 +10003796: 6383 str r3, [r0, #56] @ 0x38 +10003798: 6bcb ldr r3, [r1, #60] @ 0x3c +1000379a: 63c3 str r3, [r0, #60] @ 0x3c +1000379c: 3040 adds r0, #64 @ 0x40 +1000379e: 3140 adds r1, #64 @ 0x40 +100037a0: 3a40 subs r2, #64 @ 0x40 +100037a2: d2db bcs.n 1000375c +100037a4: 3230 adds r2, #48 @ 0x30 +100037a6: d30b bcc.n 100037c0 +100037a8: 680b ldr r3, [r1, #0] +100037aa: 6003 str r3, [r0, #0] +100037ac: 684b ldr r3, [r1, #4] +100037ae: 6043 str r3, [r0, #4] +100037b0: 688b ldr r3, [r1, #8] +100037b2: 6083 str r3, [r0, #8] +100037b4: 68cb ldr r3, [r1, #12] +100037b6: 60c3 str r3, [r0, #12] +100037b8: 3010 adds r0, #16 +100037ba: 3110 adds r1, #16 +100037bc: 3a10 subs r2, #16 +100037be: d2f3 bcs.n 100037a8 +100037c0: 320c adds r2, #12 +100037c2: d305 bcc.n 100037d0 +100037c4: f851 3b04 ldr.w r3, [r1], #4 +100037c8: f840 3b04 str.w r3, [r0], #4 +100037cc: 3a04 subs r2, #4 +100037ce: d2f9 bcs.n 100037c4 +100037d0: 3204 adds r2, #4 +100037d2: d008 beq.n 100037e6 +100037d4: 07d2 lsls r2, r2, #31 +100037d6: bf1c itt ne +100037d8: f811 3b01 ldrbne.w r3, [r1], #1 +100037dc: f800 3b01 strbne.w r3, [r0], #1 +100037e0: d301 bcc.n 100037e6 +100037e2: 880b ldrh r3, [r1, #0] +100037e4: 8003 strh r3, [r0, #0] +100037e6: 4660 mov r0, ip +100037e8: 4770 bx lr +100037ea: bf00 nop +100037ec: 2a08 cmp r2, #8 +100037ee: d313 bcc.n 10003818 +100037f0: 078b lsls r3, r1, #30 +100037f2: d0b1 beq.n 10003758 +100037f4: f010 0303 ands.w r3, r0, #3 +100037f8: d0ae beq.n 10003758 +100037fa: f1c3 0304 rsb r3, r3, #4 +100037fe: 1ad2 subs r2, r2, r3 +10003800: 07db lsls r3, r3, #31 +10003802: bf1c itt ne +10003804: f811 3b01 ldrbne.w r3, [r1], #1 +10003808: f800 3b01 strbne.w r3, [r0], #1 +1000380c: d3a4 bcc.n 10003758 +1000380e: f831 3b02 ldrh.w r3, [r1], #2 +10003812: f820 3b02 strh.w r3, [r0], #2 +10003816: e79f b.n 10003758 +10003818: 3a04 subs r2, #4 +1000381a: d3d9 bcc.n 100037d0 +1000381c: 3a01 subs r2, #1 +1000381e: f811 3b01 ldrb.w r3, [r1], #1 +10003822: f800 3b01 strb.w r3, [r0], #1 +10003826: d2f9 bcs.n 1000381c +10003828: 780b ldrb r3, [r1, #0] +1000382a: 7003 strb r3, [r0, #0] +1000382c: 784b ldrb r3, [r1, #1] +1000382e: 7043 strb r3, [r0, #1] +10003830: 788b ldrb r3, [r1, #2] +10003832: 7083 strb r3, [r0, #2] +10003834: 4660 mov r0, ip +10003836: 4770 bx lr + +10003838 : +10003838: f020 0103 bic.w r1, r0, #3 +1000383c: f010 0003 ands.w r0, r0, #3 +10003840: f1c0 0000 rsb r0, r0, #0 +10003844: f851 3b04 ldr.w r3, [r1], #4 +10003848: f100 0c04 add.w ip, r0, #4 +1000384c: ea4f 0ccc mov.w ip, ip, lsl #3 +10003850: f06f 0200 mvn.w r2, #0 +10003854: bf1c itt ne +10003856: fa22 f20c lsrne.w r2, r2, ip +1000385a: 4313 orrne r3, r2 +1000385c: f04f 0c01 mov.w ip, #1 +10003860: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10003864: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10003868: eba3 020c sub.w r2, r3, ip +1000386c: ea22 0203 bic.w r2, r2, r3 +10003870: ea12 12cc ands.w r2, r2, ip, lsl #7 +10003874: bf04 itt eq +10003876: f851 3b04 ldreq.w r3, [r1], #4 +1000387a: 3004 addeq r0, #4 +1000387c: d0f4 beq.n 10003868 +1000387e: f1c2 0100 rsb r1, r2, #0 +10003882: ea02 0201 and.w r2, r2, r1 +10003886: fab2 f282 clz r2, r2 +1000388a: f1c2 021f rsb r2, r2, #31 +1000388e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10003892: 4770 bx lr + +10003894 <_fini>: +10003894: b5f8 push {r3, r4, r5, r6, r7, lr} +10003896: bf00 nop + +10003898 <____aeabi_uldivmod_veneer>: +10003898: f85f f000 ldr.w pc, [pc] @ 1000389c <____aeabi_uldivmod_veneer+0x4> +1000389c: 20000221 .word 0x20000221 + +100038a0 <__mutex_exit_veneer>: +100038a0: f85f f000 ldr.w pc, [pc] @ 100038a4 <__mutex_exit_veneer+0x4> +100038a4: 200001e5 .word 0x200001e5 + +100038a8 <__mutex_try_enter_block_until_veneer>: +100038a8: f85f f000 ldr.w pc, [pc] @ 100038ac <__mutex_try_enter_block_until_veneer+0x4> +100038ac: 2000017d .word 0x2000017d + +100038b0 <__pre_init_runtime_init_bootrom_reset>: +100038b0: 10001621 !... + +100038b4 <__pre_init_runtime_init_early_resets>: +100038b4: 10001595 .... + +100038b8 <__pre_init_runtime_init_usb_power_down>: +100038b8: 100015c9 .... + +100038bc <__pre_init_runtime_init_clocks>: +100038bc: 100016b5 .... + +100038c0 <__pre_init_runtime_init_post_clock_resets>: +100038c0: 10001601 .... + +100038c4 <__pre_init_runtime_init_boot_locks_reset>: +100038c4: 10001519 .... + +100038c8 <__pre_init_runtime_init_spin_locks_reset>: +100038c8: 10001649 I... + +100038cc <__pre_init_runtime_init_bootrom_locking_enable>: +100038cc: 10001505 .... + +100038d0 <__pre_init_runtime_init_mutex>: +100038d0: 10000a31 1... + +100038d4 <__pre_init_runtime_init_install_ram_vector_table>: +100038d4: 1000164d M... + +100038d8 <__pre_init_runtime_init_default_alarm_pool>: +100038d8: 10000da9 .... + +100038dc <__pre_init_first_per_core_initializer>: +100038dc: 10001565 e... + +100038e0 <__pre_init_runtime_init_per_core_bootrom_reset>: +100038e0: 10001635 5... + +100038e4 <__pre_init_runtime_init_per_core_enable_coprocessors>: +100038e4: 100015e5 .... + +100038e8 <__pre_init_spinlock_set_extexclall>: +100038e8: 10000681 .... + +100038ec <__pre_init_runtime_init_per_core_irq_priorities>: +100038ec: 100006a9 .... + +100038f0 <__frame_dummy_init_array_entry>: +100038f0: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 100010cd .word 0x100010cd + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 10000969 .word 0x10000969 + +200005f4 : + ... +20000608: 20000630 0.. + +2000060c : +2000060c: 10003559 10003661 100035a9 10003671 Y5..a6...5..q6.. +2000061c: 00000000 00000100 ........ + +20000624 : + ... diff --git a/WEEK11/0x0026_functions/build/0x0026_functions.elf b/WEEK11/0x0026_functions/build/0x0026_functions.elf new file mode 100755 index 0000000..777a67e Binary files /dev/null and b/WEEK11/0x0026_functions/build/0x0026_functions.elf differ diff --git a/WEEK11/0x0026_functions/build/0x0026_functions.elf.map b/WEEK11/0x0026_functions/build/0x0026_functions.elf.map new file mode 100644 index 0000000..7399986 --- /dev/null +++ b/WEEK11/0x0026_functions/build/0x0026_functions.elf.map @@ -0,0 +1,3684 @@ +Archive member included to satisfy reference by file (symbol) + +/Users/kevinthomas/.pico-sdk/toolchain/14_2_Rel1/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a(libm_a-wf_sqrt.o) + CMakeFiles/0x0026_functions.dir/Users/kevinthomas/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_float/float_math.c.o (sqrtf) +/Users/kevinthomas/.pico-sdk/toolchain/14_2_Rel1/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a(libm_a-ef_sqrt.o) + /Users/kevinthomas/.pico-sdk/toolchain/14_2_Rel1/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a(libm_a-wf_sqrt.o) (__ieee754_sqrtf) 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+:04405800793512ABF9 +:040000051000014D99 +:00000001FF diff --git a/WEEK11/0x0026_functions/build/0x0026_functions.uf2 b/WEEK11/0x0026_functions/build/0x0026_functions.uf2 new file mode 100644 index 0000000..bf3f87a Binary files /dev/null and b/WEEK11/0x0026_functions/build/0x0026_functions.uf2 differ diff --git a/WEEK11/0x0026_functions/build/pico_flash_region.ld b/WEEK11/0x0026_functions/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK11/0x0026_functions/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK11/0x0026_functions/ir.c b/WEEK11/0x0026_functions/ir.c new file mode 100644 index 0000000..b89bd4e --- /dev/null +++ b/WEEK11/0x0026_functions/ir.c @@ -0,0 +1,80 @@ +/** + * @file ir.c + * @brief Implementation of NEC IR receiver (decoder) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "ir.h" +#include "pico/stdlib.h" +#include "pico/time.h" +#include "hardware/gpio.h" + +static unsigned int ir_pin = 0; + +// Wait for 'gpio' to reach 'level' or timeout (microseconds). Return elapsed us or -1. +static int64_t wait_for_level(unsigned int gpio, bool level, uint32_t timeout_us) { + absolute_time_t start = get_absolute_time(); + while (gpio_get(gpio) != level) { + if (absolute_time_diff_us(start, get_absolute_time()) > (int64_t)timeout_us) { + return -1; + } + } + return absolute_time_diff_us(start, get_absolute_time()); +} + +void ir_init(uint8_t pin) { + ir_pin = pin; + gpio_init(pin); + gpio_set_dir(pin, GPIO_IN); + gpio_pull_up(pin); +} + +int ir_getkey(void) { + // leader low (~9 ms) + if (wait_for_level(ir_pin, 0, 150000) < 0) return -1; + + int64_t t = wait_for_level(ir_pin, 1, 12000); + if (t < 8000 || t > 10000) return -1; + + t = wait_for_level(ir_pin, 0, 7000); + if (t < 3500 || t > 5000) return -1; + + uint8_t data[4] = {0, 0, 0, 0}; + for (int i = 0; i < 32; ++i) { + if (wait_for_level(ir_pin, 1, 1000) < 0) return -1; + t = wait_for_level(ir_pin, 0, 2500); + if (t < 200) return -1; + int byte_idx = i / 8; + int bit_idx = i % 8; + if (t > 1200) data[byte_idx] |= (1 << bit_idx); // logical '1' + } + + // Validate address/data inverted pairs + if ((uint8_t)(data[0] + data[1]) == 0xFF && (uint8_t)(data[2] + data[3]) == 0xFF) { + return data[2]; + } + return -1; +} diff --git a/WEEK11/0x0026_functions/ir.h b/WEEK11/0x0026_functions/ir.h new file mode 100644 index 0000000..84aa67f --- /dev/null +++ b/WEEK11/0x0026_functions/ir.h @@ -0,0 +1,63 @@ +/** + * @file ir.h + * @brief Header for NEC IR receiver (decoder) API + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef IR_H +#define IR_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the IR receiver GPIO + * + * Configures the given `pin` as an input with pull-up for the NEC IR receiver. + * Call this once during board initialization before calling `ir_getkey()`. + * + * @param pin GPIO pin number connected to IR receiver output + */ +void ir_init(uint8_t pin); + +/** + * @brief Blocking NEC IR decoder + * + * Blocks while waiting for a complete NEC frame. On success returns the + * decoded command byte (0..255). On timeout or protocol error returns -1. + * + * @return decoded command byte (0..255) or -1 on failure + */ +int ir_getkey(void); + +#ifdef __cplusplus +} +#endif + +#endif // IR_H diff --git a/WEEK11/0x0026_functions/pico_sdk_import.cmake b/WEEK11/0x0026_functions/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK11/0x0026_functions/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK11/0x0026a_custom-bootloader/.gitignore b/WEEK11/0x0026a_custom-bootloader/.gitignore new file mode 100644 index 0000000..61e3300 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/.gitignore @@ -0,0 +1,9 @@ +build/CMakeFiles/ +build/pico_sdk/ +build/pico-sdk/ +build/generated/ +build/_deps/ +build/*.o +build/*.d +build/*.obj +!.vscode/* diff --git a/WEEK11/0x0026a_custom-bootloader/0x0026a_app.bin b/WEEK11/0x0026a_custom-bootloader/0x0026a_app.bin new file mode 100755 index 0000000..f6c83d6 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/0x0026a_app.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.bin b/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.bin new file mode 100755 index 0000000..5fd7c1b Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.uf2 b/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.uf2 new file mode 100644 index 0000000..dc84248 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/0x0026a_bootloader.uf2 differ diff --git a/WEEK11/0x0026a_custom-bootloader/0x0026a_full.uf2 b/WEEK11/0x0026a_custom-bootloader/0x0026a_full.uf2 new file mode 100644 index 0000000..5215266 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/0x0026a_full.uf2 differ diff --git a/WEEK11/0x0026a_custom-bootloader/CMakeLists.txt b/WEEK11/0x0026a_custom-bootloader/CMakeLists.txt new file mode 100644 index 0000000..299af94 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/CMakeLists.txt @@ -0,0 +1,90 @@ +# 0x0026a custom bootloader: builds a secure bootloader plus the signed +# application it launches. Run from this directory: +# +# cmake -B build -G Ninja -DPICO_BOARD=pico2 \ +# -DPICO_SDK_PATH="$HOME/.pico-sdk/sdk/2.2.0" \ +# -DPICO_TOOLCHAIN_PATH="$HOME/.pico-sdk/toolchain/14_2_Rel1" +# cmake --build build + +cmake_minimum_required(VERSION 3.13) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +# == DO NOT EDIT THE FOLLOWING LINES for the Raspberry Pi Pico VS Code Extension to work == +if(WIN32) + set(USERHOME $ENV{USERPROFILE}) +else() + set(USERHOME $ENV{HOME}) +endif() +set(sdkVersion 2.2.0) +set(toolchainVersion 14_2_Rel1) +set(picotoolVersion 2.2.0-a4) +set(picoVscode ${USERHOME}/.pico-sdk/cmake/pico-vscode.cmake) +if (EXISTS ${picoVscode}) + include(${picoVscode}) +endif() +# ==================================================================================== +set(PICO_BOARD pico2 CACHE STRING "Board type") + +# Pull in Raspberry Pi Pico SDK (must be before project) +include(pico_sdk_import.cmake) + +project(0x0026a_custom_bootloader C CXX ASM) + +# Initialise the Raspberry Pi Pico SDK +pico_sdk_init() + +# --- Bootloader: verifies an AES-128-CMAC tag before launching the app -------- +add_executable(0x0026a_bootloader + bootloader/src/main.c + bootloader/src/boot.c + bootloader/src/manifest.c + bootloader/src/aes_cmac.c + bootloader/src/image.c + bootloader/src/verify.c) + +target_include_directories(0x0026a_bootloader PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/bootloader/include + ${CMAKE_CURRENT_LIST_DIR}/common/include) + +# pico_mbedtls provides the AES-128-CMAC implementation used for verification. +target_link_libraries(0x0026a_bootloader PRIVATE + pico_stdlib + pico_mbedtls) + +pico_enable_stdio_uart(0x0026a_bootloader 1) +pico_enable_stdio_usb(0x0026a_bootloader 0) +pico_add_extra_outputs(0x0026a_bootloader) + +# --- Application: the 0x0026_functions firmware linked at 0x10020000 ---------- +add_executable(0x0026a_app + app/src/app_main.c + app/src/ir.c + app/src/led.c + app/src/secret.c) + +target_include_directories(0x0026a_app PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/app/include + ${CMAKE_CURRENT_LIST_DIR}/common/include) + +# pico_mbedtls provides the AES-128-CBC API used by secret.c. +target_link_libraries(0x0026a_app PRIVATE + pico_stdlib + pico_mbedtls) + +pico_enable_stdio_uart(0x0026a_app 1) +pico_enable_stdio_usb(0x0026a_app 0) + +# Relocate the application into flash above the bootloader and manifest. +pico_set_linker_script(0x0026a_app + ${CMAKE_CURRENT_LIST_DIR}/app/memmap_app.ld) + +# The application starts at 0x10020000. A standalone app UF2 would flash only +# this one region, so the lab ships a single combined UF2 instead (built by +# tools/make_full_uf2.py). Emit the raw artifacts we sign and flash with OpenOCD. +pico_add_dis_output(0x0026a_app) +pico_add_hex_output(0x0026a_app) +pico_add_bin_output(0x0026a_app) +pico_add_map_output(0x0026a_app) diff --git a/WEEK11/0x0026a_custom-bootloader/README.md b/WEEK11/0x0026a_custom-bootloader/README.md new file mode 100644 index 0000000..ee1bf71 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/README.md @@ -0,0 +1,69 @@ +# 0x0026a Custom AES-128-CMAC Secure Bootloader + +This project builds a custom secure-boot chain for the Pico 2 (RP2350) that sits entirely above the ROM bootloader. A first-stage bootloader in XIP flash authenticates a signed application with AES-128-CMAC (RFC 4493) before jumping to it, and the signed application decrypts and prints a secret banner using the SDK Mbed TLS AES API. + +## What You'll Learn + +- Why a bootloader-only CRC/manifest is insufficient and what a MAC adds +- How AES-128-CMAC works (K1/K2 subkeys) and the RFC 4493 test vectors +- Custom linker-script editing (`pico_flash_region.ld`, `memmap_app.ld`) to relocate the app +- Flashing three images (bootloader, manifest, app) with OpenOCD +- Reverse engineering both images with GDB and Ghidra (find the key, IV, ciphertext, banner) + +See the full tutorial: [WEEK11a.md](../WEEK11/WEEK11a.md) / [WEEK11a.pdf](../WEEK11/WEEK11a.pdf) + +## Flash Map + +| Region | Address | Content | +| ---------- | ----------- | ------------------------------ | +| Bootloader | `0x10000000` | 0x0026a bootloader (27772 B) | +| Manifest | `0x1001F000` | header + AES-128-CMAC tag | +| App | `0x10020000` | 0x0026a signed app (21656 B) | + +The CMSIS-RM9 flash-safe range starts at `0x10000000` on the RP2350, so adding 2 MB relocates the app to `0x10020000`. + +## Artifacts + +| File | Description | +| ---------------------------- | ------------------------------------------------- | +| `0x0026a_bootloader.bin` | Bootloader image (flash at `0x10000000`) | +| `0x0026a_bootloader.uf2` | Bootloader-only UF2 for the BOOTSEL drag-and-drop | +| `0x0026a_app.bin` | Signed app image (flash at `0x10020000`) | +| `manifest.bin` | Manifest (flash at `0x1001F000`) | +| `0x0026a_full.uf2` | **All three images** in one BOOTSEL drag | +| `WEEK11a.md` / `WEEK11a.pdf` | Full lab notebook (in `WEEK11/`) | + +## Build + +```sh +cmake -B build -DPICO_SDK_PATH=~/.pico-sdk/sdk/2.2.0 +cmake --build build +python3 tools/sign_firmware.py build/0x0026a_app.bin --out manifest.bin --key "IronNetBootKey!!" --app-base 0x10020000 +PICOTOOL=~/.pico-sdk/picotool/2.3.1/picotool/picotool python3 tools/make_full_uf2.py +``` + +This produces `0x0026a_bootloader.bin/.uf2` and `0x0026a_app.bin`; the signer +writes `manifest.bin`; `make_full_uf2.py` packs all three into +`0x0026a_full.uf2`. + +## Flash + +Easiest - copy `0x0026a_full.uf2` to the `RP2350` BOOTSEL drive; one drag writes +the whole chain (bootloader + manifest + app). + +Or with OpenOCD: + +```sh +openocd -f interface/picoprobe.cfg -f target/rp2350.cfg -c \ + "program 0x0026a_bootloader.bin 0x10000000 verify; \ + program manifest.bin 0x1001F000 verify; \ + program 0x0026a_app.bin 0x10020000 verify; reset run; shutdown" +``` + +## Verify at Runtime + +Halt the core after boot and read the program counter. A valid signed image leaves PC inside the app (`0x100201xx`); a tampered or unsigned image leaves PC in the bootloader `boot_halt` idle loop near `0x10000eb2`. + +## Disclaimers + +This is an educational project for the Embedded-Hacking course. The key `IronNetBootKey!!` ships in the repo and is intentionally embedded in both images so it can be recovered with GDB/Ghidra. Do not use this scheme to protect real products. \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/app/include/ir.h b/WEEK11/0x0026a_custom-bootloader/app/include/ir.h new file mode 100644 index 0000000..84aa67f --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/include/ir.h @@ -0,0 +1,63 @@ +/** + * @file ir.h + * @brief Header for NEC IR receiver (decoder) API + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef IR_H +#define IR_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the IR receiver GPIO + * + * Configures the given `pin` as an input with pull-up for the NEC IR receiver. + * Call this once during board initialization before calling `ir_getkey()`. + * + * @param pin GPIO pin number connected to IR receiver output + */ +void ir_init(uint8_t pin); + +/** + * @brief Blocking NEC IR decoder + * + * Blocks while waiting for a complete NEC frame. On success returns the + * decoded command byte (0..255). On timeout or protocol error returns -1. + * + * @return decoded command byte (0..255) or -1 on failure + */ +int ir_getkey(void); + +#ifdef __cplusplus +} +#endif + +#endif // IR_H diff --git a/WEEK11/0x0026a_custom-bootloader/app/include/led.h b/WEEK11/0x0026a_custom-bootloader/app/include/led.h new file mode 100644 index 0000000..7e0b63c --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/include/led.h @@ -0,0 +1,63 @@ +/** + * @file led.h + * @brief LED controller driven by decoded NEC IR commands. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef LED_H +#define LED_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief LED controller state for the three IR-controlled LEDs. + * + * Maps each logical LED (1-3) to its GPIO pin and remembers whether the + * LED is currently on. Build a default instance with led_default() and + * drive it with led_init() and led_handle_ir(). + */ +typedef struct { + uint8_t led1_pin; + uint8_t led2_pin; + uint8_t led3_pin; + bool led1_state; + bool led2_state; + bool led3_state; +} simple_led_ctrl_t; + +/** + * @brief Build the default three-LED configuration (pins 16-18, all off). + * @param void No parameters. + * @return simple_led_ctrl_t Default LED controller state. + */ +simple_led_ctrl_t led_default(void); + +/** + * @brief Configure the three LED GPIO pins as outputs. + * @param leds Pointer to the LED controller to initialize. + * @return void No return value. + */ +void led_init(simple_led_ctrl_t *leds); + +/** + * @brief Dispatch a decoded NEC command to the matching LED. + * @param leds Pointer to the LED controller to drive. + * @param key Decoded NEC command byte, or a negative value to ignore. + * @return void No return value. + */ +void led_handle_ir(simple_led_ctrl_t *leds, int key); + +#ifdef __cplusplus +} +#endif + +#endif // LED_H \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/app/include/secret.h b/WEEK11/0x0026a_custom-bootloader/app/include/secret.h new file mode 100644 index 0000000..124a80e --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/include/secret.h @@ -0,0 +1,29 @@ +/** + * @file secret.h + * @brief AES-128-CBC protected runtime banner for the application. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef SECRET_H +#define SECRET_H + +#include + +/** @brief AES block size in bytes used by the runtime banner. */ +#define APP_AES_BLOCK 16U + +/** @brief Length in bytes of the encrypted runtime banner. */ +#define APP_BANNER_LEN 32U + +/** + * @brief Decrypt the embedded AES-128-CBC banner and print it. + * @param void No parameters. + * @return int Zero on success, non-zero when decryption fails. + */ +int secret_print_banner(void); + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/app/memmap_app.ld b/WEEK11/0x0026a_custom-bootloader/app/memmap_app.ld new file mode 100644 index 0000000..faa2c2c --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/memmap_app.ld @@ -0,0 +1,305 @@ +/* Based on GCC ARM embedded samples. + Defines the following symbols for use by code: + __exidx_start + __exidx_end + __etext + __data_start__ + __preinit_array_start + __preinit_array_end + __init_array_start + __init_array_end + __fini_array_start + __fini_array_end + __data_end__ + __bss_start__ + __bss_end__ + __end__ + end + __HeapLimit + __StackLimit + __StackTop + __stack (== StackTop) +*/ + +MEMORY +{ + /* Relocated for the custom bootloader: the application is linked to run + from 0x10020000, leaving the first 128k of flash for the bootloader and + its manifest. */ + FLASH(rx) : ORIGIN = 0x10020000, LENGTH = 1920k + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} + +ENTRY(_entry_point) + +SECTIONS +{ + .flash_begin : { + __flash_binary_start = .; + } > FLASH + + /* The bootrom will enter the image at the point indicated in your + IMAGE_DEF, which is usually the reset handler of your vector table. + + The debugger will use the ELF entry point, which is the _entry_point + symbol, and in our case is *different from the bootrom's entry point.* + This is used to go back through the bootrom on debugger launches only, + to perform the same initial flash setup that would be performed on a + cold boot. + */ + + .text : { + __logical_binary_start = .; + KEEP (*(.vectors)) + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + /* TODO revisit this now memset/memcpy/float in ROM */ + /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from + * FLASH ... we will include any thing excluded here in .data below by default */ + *(.init) + *libgcc.a:cmse_nonsecure_call.o + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + *(.fini) + /* Pull all c'tors into .text */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* Followed by destructors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + *(SORT(.fini_array.*)) + *(.fini_array) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.eh_frame*) + . = ALIGN(4); + } > FLASH + + /* Note the boot2 section is optional, and should be discarded if there is + no reference to it *inside* the binary, as it is not called by the + bootrom. (The bootrom performs a simple best-effort XIP setup and + leaves it to the binary to do anything more sophisticated.) However + there is still a size limit of 256 bytes, to ensure the boot2 can be + stored in boot RAM. + + Really this is a "XIP setup function" -- the name boot2 is historic and + refers to its dual-purpose on RP2040, where it also handled vectoring + from the bootrom into the user image. + */ + + .boot2 : { + __boot2_start__ = .; + *(.boot2) + __boot2_end__ = .; + } > FLASH + + ASSERT(__boot2_end__ - __boot2_start__ <= 256, + "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") + + .rodata : { + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + *(.srodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + . = ALIGN(4); + + .ram_vector_table (NOLOAD): { + *(.ram_vector_table) + } > RAM + + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + + .data : { + __data_start__ = .; + *(vtable) + + *(.time_critical*) + + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + + *(.data*) + *(.sdata*) + + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + *(.jcr) + . = ALIGN(4); + } > RAM AT> FLASH + + .tdata : { + . = ALIGN(4); + *(.tdata .tdata.* .gnu.linkonce.td.*) + /* All data end */ + __tdata_end = .; + } > RAM AT> FLASH + PROVIDE(__data_end__ = .); + + /* __etext is (for backwards compatibility) the name of the .data init source pointer (...) */ + __etext = LOADADDR(.data); + + .tbss (NOLOAD) : { + . = ALIGN(4); + __bss_start__ = .; + __tls_base = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + + __tls_end = .; + } > RAM + + .bss (NOLOAD) : { + . = ALIGN(4); + __tbss_end = .; + + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + PROVIDE(__global_pointer$ = . + 2K); + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + } > RAM + /* historically on GCC sbrk was growing past __HeapLimit to __StackLimit, however + to be more compatible, we now set __HeapLimit explicitly to where the end of the heap is */ + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + .flash_end : { + KEEP(*(.embedded_end_block*)) + PROVIDE(__flash_binary_end = .); + } > FLASH =0xaa + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* picolibc and LLVM */ + PROVIDE (__heap_start = __end__); + PROVIDE (__heap_end = __HeapLimit); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __tls_size_align = (__tls_size + __tls_align - 1) & ~(__tls_align - 1)); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + + /* llvm-libc */ + PROVIDE (_end = __end__); + PROVIDE (__llvm_libc_heap_limit = __HeapLimit); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") + ASSERT( __embedded_block_end - __logical_binary_start <= 4096, "Embedded block must be in first 4096 bytes of the binary") + + /* todo assert on extra code */ +} + diff --git a/WEEK11/0x0026a_custom-bootloader/app/src/app_main.c b/WEEK11/0x0026a_custom-bootloader/app/src/app_main.c new file mode 100644 index 0000000..16d9c78 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/src/app_main.c @@ -0,0 +1,54 @@ +/** + * @file app_main.c + * @brief Application entry point: IR receiver drives the LED controller. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + * + * ----------------------------------------------------------------------------- + * + * This file is deliberately thin: it only wires the modules together and runs + * the poll loop. The NEC IR decoder lives in ir.c, the LED controller lives in + * led.c, and the AES-128-CBC protected banner lives in secret.c. + * + * Wiring: + * GPIO5 -> IR receiver OUT + * GPIO16 -> LED1 anode (with current-limiting resistor to GND) + * GPIO17 -> LED2 anode (with current-limiting resistor to GND) + * GPIO18 -> LED3 anode (with current-limiting resistor to GND) + */ + +#include +#include +#include "pico/stdlib.h" +#include "ir.h" +#include "led.h" +#include "secret.h" + +/** @brief GPIO pin number for the IR receiver. */ +#define IR_PIN 5 + +/** + * @brief Poll the IR receiver and dispatch decoded keys forever. + * @param leds Pointer to the LED controller to drive. + * @return void Does not return. + */ +static void ir_poll_loop(simple_led_ctrl_t *leds) { + while (true) { + int key = ir_getkey(); + if (key >= 0) led_handle_ir(leds, key); + else sleep_ms(1); + } +} + +int main(void) { + stdio_init_all(); + secret_print_banner(); + simple_led_ctrl_t leds = led_default(); + led_init(&leds); + ir_init(IR_PIN); + printf("IR receiver on GPIO %d ready\n", IR_PIN); + ir_poll_loop(&leds); +} \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/app/src/ir.c b/WEEK11/0x0026a_custom-bootloader/app/src/ir.c new file mode 100644 index 0000000..b47835c --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/src/ir.c @@ -0,0 +1,131 @@ +/** + * @file ir.c + * @brief Implementation of NEC IR receiver (decoder) + * @author Kevin Thomas + * @date 2025 + * + * MIT License + * + * Copyright (c) 2025 Kevin Thomas + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "ir.h" +#include "pico/stdlib.h" +#include "pico/time.h" +#include "hardware/gpio.h" + +/** @brief GPIO pin connected to the IR receiver */ +static unsigned int ir_pin = 0; + +/** + * @brief Wait for a GPIO pin to reach a given logic level + * + * Spins until the pin matches the requested level or a microsecond timeout + * is exceeded. Returns the elapsed time in microseconds, or -1 on timeout. + * + * @param gpio GPIO pin to monitor + * @param level Desired logic level (true = HIGH, false = LOW) + * @param timeout_us Maximum wait in microseconds + * @return int64_t Elapsed microseconds, or -1 on timeout + */ +static int64_t wait_for_level(unsigned int gpio, bool level, uint32_t timeout_us) { + absolute_time_t start = get_absolute_time(); + while (gpio_get(gpio) != level) { + if (absolute_time_diff_us(start, get_absolute_time()) > (int64_t)timeout_us) + return -1; + } + return absolute_time_diff_us(start, get_absolute_time()); +} + +/** + * @brief Wait for the NEC 9 ms leader pulse and 4.5 ms space + * + * @param void No parameters. + * @return bool true if a valid leader was detected, false on timeout + */ +static bool wait_leader(void) { + if (wait_for_level(ir_pin, 0, 150000) < 0) return false; + int64_t t = wait_for_level(ir_pin, 1, 12000); + if (t < 8000 || t > 10000) return false; + t = wait_for_level(ir_pin, 0, 7000); + if (t < 3500 || t > 5000) return false; + return true; +} + +/** + * @brief Read a single NEC-encoded bit from the IR receiver + * + * Measures the mark/space timing and shifts the result into the + * appropriate byte of the data array. + * + * @param data 4-byte array accumulating received bits + * @param i Bit index (0-31) + * @return bool true on success, false on timeout or protocol error + */ +static bool read_nec_bit(uint8_t *data, int i) { + if (wait_for_level(ir_pin, 1, 1000) < 0) return false; + int64_t t = wait_for_level(ir_pin, 0, 2500); + if (t < 200) return false; + int byte_idx = i / 8; + int bit_idx = i % 8; + if (t > 1200) data[byte_idx] |= (1 << bit_idx); + return true; +} + +/** + * @brief Read all 32 data bits of an NEC frame + * + * @param data 4-byte array filled with the received address and command + * @return bool true if all 32 bits were read, false on timeout + */ +static bool read_32_bits(uint8_t *data) { + for (int i = 0; i < 32; ++i) + if (!read_nec_bit(data, i)) return false; + return true; +} + +/** + * @brief Validate an NEC frame and extract the command byte + * + * Checks that the address and command pairs are bitwise-inverted. + * + * @param data 4-byte NEC frame (addr, ~addr, cmd, ~cmd) + * @return int Command byte (0-255) on success, -1 on validation failure + */ +static int validate_nec_frame(const uint8_t *data) { + if ((uint8_t)(data[0] + data[1]) == 0xFF && (uint8_t)(data[2] + data[3]) == 0xFF) + return data[2]; + return -1; +} + +void ir_init(uint8_t pin) { + ir_pin = pin; + gpio_init(pin); + gpio_set_dir(pin, GPIO_IN); + gpio_pull_up(pin); +} + +int ir_getkey(void) { + if (!wait_leader()) return -1; + uint8_t data[4] = {0, 0, 0, 0}; + if (!read_32_bits(data)) return -1; + return validate_nec_frame(data); +} diff --git a/WEEK11/0x0026a_custom-bootloader/app/src/led.c b/WEEK11/0x0026a_custom-bootloader/app/src/led.c new file mode 100644 index 0000000..fee69f9 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/src/led.c @@ -0,0 +1,103 @@ +/** + * @file led.c + * @brief LED controller driven by decoded NEC IR commands. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include +#include "pico/stdlib.h" +#include "led.h" + +/** + * @brief Map an NEC command code to a logical LED number. + * @param ir_command Decoded NEC command byte. + * @return int Logical LED number 1-3, or 0 when the command is unmapped. + */ +static int led_number_for_command(int ir_command) { + if (ir_command == 0x0C) return 1; + if (ir_command == 0x18) return 2; + if (ir_command == 0x5E) return 3; + return 0; +} + +/** + * @brief Return the GPIO pin backing a logical LED number. + * @param leds Pointer to the LED controller. + * @param led_num Logical LED number (1-3). + * @return uint8_t GPIO pin number for the requested LED. + */ +static uint8_t led_pin_for(simple_led_ctrl_t *leds, int led_num) { + if (led_num == 1) return leds->led1_pin; + if (led_num == 2) return leds->led2_pin; + return leds->led3_pin; +} + +/** + * @brief Turn every LED output off. + * @param leds Pointer to the LED controller. + * @return void No return value. + */ +static void led_all_off(simple_led_ctrl_t *leds) { + gpio_put(leds->led1_pin, false); + gpio_put(leds->led2_pin, false); + gpio_put(leds->led3_pin, false); +} + +/** + * @brief Toggle a GPIO on and off for a number of blink cycles. + * @param pin GPIO pin to blink. + * @param count Number of on/off cycles. + * @param delay_ms Milliseconds to hold each phase. + * @return void No return value. + */ +static void led_blink(uint8_t pin, uint8_t count, uint32_t delay_ms) { + for (uint8_t i = 0; i < count; i++) { + gpio_put(pin, true); + sleep_ms(delay_ms); + gpio_put(pin, false); + sleep_ms(delay_ms); + } +} + +/** + * @brief Blink an LED, then leave it lit. + * @param leds Pointer to the LED controller. + * @param led_num Logical LED number to activate. + * @return void No return value. + */ +static void led_activate(simple_led_ctrl_t *leds, int led_num) { + uint8_t pin = led_pin_for(leds, led_num); + led_blink(pin, 3, 50); + gpio_put(pin, true); + printf("LED %d activated on GPIO %d\n", led_num, pin); +} + +simple_led_ctrl_t led_default(void) { + simple_led_ctrl_t leds = { + .led1_pin = 16, .led2_pin = 17, .led3_pin = 18, + .led1_state = false, .led2_state = false, .led3_state = false + }; + return leds; +} + +void led_init(simple_led_ctrl_t *leds) { + gpio_init(leds->led1_pin); + gpio_set_dir(leds->led1_pin, GPIO_OUT); + gpio_init(leds->led2_pin); + gpio_set_dir(leds->led2_pin, GPIO_OUT); + gpio_init(leds->led3_pin); + gpio_set_dir(leds->led3_pin, GPIO_OUT); +} + +void led_handle_ir(simple_led_ctrl_t *leds, int key) { + if (key < 0) return; + printf("NEC command: 0x%02X\n", key); + led_all_off(leds); + int led_num = led_number_for_command(key); + if (led_num == 0) return; + led_activate(leds, led_num); +} \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/app/src/secret.c b/WEEK11/0x0026a_custom-bootloader/app/src/secret.c new file mode 100644 index 0000000..8f6df9e --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/app/src/secret.c @@ -0,0 +1,88 @@ +/** + * @file secret.c + * @brief Decrypts a runtime banner with the SDK Mbed TLS AES-128-CBC API. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + * + * ----------------------------------------------------------------------------- + * + * This module shows how to use the AES implementation that ships with the Pico + * SDK. A short banner is stored in flash only as AES-128-CBC ciphertext; the + * key and IV live in the same image. At startup secret_print_banner() rebuilds + * the plaintext with mbedtls_aes_crypt_cbc() and writes it to the console. + * + * The plaintext is exactly APP_BANNER_LEN bytes (two whole AES blocks), so no + * padding routine is required. The ciphertext was produced on the host with the + * matching key and IV, for example: + * + * printf '%s' 'SECRET: IR LINK SECURED ONLINE ' \ + * | openssl enc -aes-128-cbc -K 49726f6e4e6574426f6f744b65792121 \ + * -iv 41707053656372657449563132333435 -nopad | xxd -p + */ + +#include +#include +#include "mbedtls/aes.h" +#include "secret.h" + +/** @brief AES-128 key, the same 16 bytes the bootloader uses for CMAC. */ +static const uint8_t banner_key[APP_AES_BLOCK] = { + 0x49, 0x72, 0x6F, 0x6E, 0x4E, 0x65, 0x74, 0x42, + 0x6F, 0x6F, 0x74, 0x4B, 0x65, 0x79, 0x21, 0x21 +}; + +/** @brief Initialization vector used when the banner was encrypted. */ +static const uint8_t banner_iv[APP_AES_BLOCK] = { + 0x41, 0x70, 0x70, 0x53, 0x65, 0x63, 0x72, 0x65, + 0x74, 0x49, 0x56, 0x31, 0x32, 0x33, 0x34, 0x35 +}; + +/** @brief AES-128-CBC ciphertext of the runtime banner. */ +static const uint8_t banner_ct[APP_BANNER_LEN] = { + 0xBA, 0xEC, 0x4A, 0x19, 0x25, 0x86, 0x1B, 0xB9, + 0x2D, 0xFD, 0x9F, 0x13, 0xF7, 0x9B, 0x3E, 0x80, + 0xCF, 0x12, 0xB6, 0x98, 0xDB, 0x91, 0x65, 0xBE, + 0x8F, 0xD7, 0xC3, 0x47, 0x7B, 0xB2, 0xE7, 0x6E +}; + +/** + * @brief Run the AES-128-CBC decrypt in place over a working buffer. + * @param aes Pointer to an AES context holding an already-expanded key. + * @param iv Pointer to a mutable copy of the initialization vector. + * @param buf Pointer to the buffer holding ciphertext, then plaintext. + * @return int Zero on success, non-zero on failure. + */ +static int secret_cbc(mbedtls_aes_context *aes, uint8_t *iv, uint8_t *buf) { + int rc = mbedtls_aes_crypt_cbc(aes, MBEDTLS_AES_DECRYPT, APP_BANNER_LEN, + iv, buf, buf); + return rc; +} + +/** + * @brief Decrypt the banner ciphertext into a working buffer. + * @param buf Buffer of at least APP_BANNER_LEN bytes. + * @return int Zero on success, non-zero on failure. + */ +static int secret_decrypt(uint8_t *buf) { + mbedtls_aes_context aes; + uint8_t iv[APP_AES_BLOCK]; + memcpy(iv, banner_iv, APP_AES_BLOCK); + mbedtls_aes_init(&aes); + mbedtls_aes_setkey_dec(&aes, banner_key, 128); + int rc = secret_cbc(&aes, iv, buf); + mbedtls_aes_free(&aes); + return rc; +} + +int secret_print_banner(void) { + uint8_t buf[APP_BANNER_LEN + 1]; + memcpy(buf, banner_ct, APP_BANNER_LEN); + buf[APP_BANNER_LEN] = '\0'; + int rc = secret_decrypt(buf); + if (rc != 0) return rc; + printf("app banner: %s\n", (char *)buf); + return 0; +} diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/aes_cmac.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/aes_cmac.h new file mode 100644 index 0000000..8510e8a --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/aes_cmac.h @@ -0,0 +1,40 @@ +/** + * @file aes_cmac.h + * @brief AES-128-CMAC authentication tag helpers backed by Mbed TLS. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef AES_CMAC_H +#define AES_CMAC_H + +#include +#include +#include + +/** @brief AES block size in bytes. */ +#define AES_BLOCK_SIZE 16U + +/** + * @brief Compute an AES-128-CMAC tag over a memory region. + * @param key Pointer to the 16-byte AES-128 key. + * @param data Pointer to the message bytes, which may live in XIP flash. + * @param len Message length in bytes. + * @param tag Output buffer that receives the 16-byte CMAC tag. + * @return int Zero on success, non-zero when the cipher is unavailable. + */ +int aes128_cmac(const uint8_t *key, const uint8_t *data, size_t len, + uint8_t *tag); + +/** + * @brief Compare two CMAC tags without short-circuiting on the first byte. + * @param a Pointer to the first tag. + * @param b Pointer to the second tag. + * @return bool True when the tags are byte-for-byte identical. + */ +bool cmac_tags_equal(const uint8_t *a, const uint8_t *b); + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/boot.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/boot.h new file mode 100644 index 0000000..09f6e58 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/boot.h @@ -0,0 +1,45 @@ +/** + * @file boot.h + * @brief Secure boot console and application handoff helpers. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef BOOT_H +#define BOOT_H + +#include "manifest.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Bring up the debug console and print the boot banner. + * @param void No parameters. + * @return void No return value. + */ +void boot_init(void); + +/** + * @brief Print a boot failure reason and idle forever. + * @param reason Null-terminated message describing the failure. + * @return void Does not return. + */ +void boot_halt(const char *reason); + +/** + * @brief Announce the verified image and jump to its reset vector. + * @param manifest Pointer to the validated manifest. + * @return void Does not return. + */ +void boot_launch(const fw_manifest_t *manifest); + +#ifdef __cplusplus +} +#endif + +#endif // BOOT_H \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/flash_layout.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/flash_layout.h new file mode 100644 index 0000000..9338649 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/flash_layout.h @@ -0,0 +1,31 @@ +/** + * @file flash_layout.h + * @brief Flash partition map shared by the bootloader and the host signer. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef FLASH_LAYOUT_H +#define FLASH_LAYOUT_H + +#include + +/** @brief Absolute base address of the bootloader image in XIP flash. */ +#define BOOTLOADER_BASE 0x10000000U + +/** @brief Absolute address of the one-sector firmware manifest. */ +#define FW_MANIFEST_BASE 0x1001F000U + +/** @brief Size in bytes of the flash sector holding the manifest. */ +#define FW_MANIFEST_SECTOR_SIZE 4096U + +/** @brief Absolute base address where the signed application runs. */ +#define APP_BASE 0x10020000U + +/** @brief Total XIP flash size in bytes on the RP2350 Pico 2 board. */ +#define FLASH_TOTAL_SIZE 0x200000U + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/image.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/image.h new file mode 100644 index 0000000..5173845 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/image.h @@ -0,0 +1,23 @@ +/** + * @file image.h + * @brief Control transfer into a freshly verified Cortex-M application. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef IMAGE_H +#define IMAGE_H + +#include + +/** + * @brief Jump to an application whose vector table starts at a base address. + * @param vector_base Base address of the application vector table. + * @return void Does not return to the caller. + */ +void image_start(uint32_t vector_base); + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/manifest.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/manifest.h new file mode 100644 index 0000000..2bc5336 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/manifest.h @@ -0,0 +1,51 @@ +/** + * @file manifest.h + * @brief Firmware manifest stored in the flash sector before the application. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef MANIFEST_H +#define MANIFEST_H + +#include +#include + +/** @brief Little-endian magic at the head of a valid manifest ("WFLB"). */ +#define FW_MANIFEST_MAGIC 0x424C4657U + +/** @brief Current manifest structure revision. */ +#define FW_MANIFEST_VERSION 1U + +/** @brief Length in bytes of an AES-128-CMAC authentication tag. */ +#define FW_TAG_SIZE 16U + +#pragma pack(push, 1) +/** @brief Fixed-layout record describing the signed application image. */ +typedef struct { + uint32_t magic; + uint32_t version; + uint32_t app_base; + uint32_t app_size; + uint8_t tag[FW_TAG_SIZE]; +} fw_manifest_t; +#pragma pack(pop) + +/** + * @brief Copy the manifest out of its fixed flash address. + * @param out Pointer to the manifest structure to populate. + * @return void No return value. + */ +void manifest_read(fw_manifest_t *out); + +/** + * @brief Report whether a manifest carries the expected magic and version. + * @param manifest Pointer to the manifest to inspect. + * @return bool True when the magic and version both match. + */ +bool manifest_is_valid(const fw_manifest_t *manifest); + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/include/verify.h b/WEEK11/0x0026a_custom-bootloader/bootloader/include/verify.h new file mode 100644 index 0000000..5734107 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/include/verify.h @@ -0,0 +1,32 @@ +/** + * @file verify.h + * @brief Firmware authenticity verification for the secure bootloader. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#ifndef VERIFY_H +#define VERIFY_H + +#include +#include "manifest.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Recompute the CMAC over the application and compare it to the tag. + * @param manifest Pointer to the validated manifest. + * @return bool True when the tag matches, false otherwise. + */ +bool verify_manifest(const fw_manifest_t *manifest); + +#ifdef __cplusplus +} +#endif + +#endif // VERIFY_H \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/aes_cmac.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/aes_cmac.c new file mode 100644 index 0000000..9dcc481 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/aes_cmac.c @@ -0,0 +1,29 @@ +/** + * @file aes_cmac.c + * @brief AES-128-CMAC primitives implemented on top of the SDK Mbed TLS. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include "mbedtls/cmac.h" +#include "mbedtls/cipher.h" +#include "aes_cmac.h" + +int aes128_cmac(const uint8_t *key, const uint8_t *data, size_t len, + uint8_t *tag) { + const mbedtls_cipher_info_t *info; + info = mbedtls_cipher_info_from_type(MBEDTLS_CIPHER_AES_128_ECB); + if (info == NULL) return -1; + return mbedtls_cipher_cmac(info, key, 128, data, len, tag); +} + +bool cmac_tags_equal(const uint8_t *a, const uint8_t *b) { + uint8_t diff = 0; + for (size_t i = 0; i < AES_BLOCK_SIZE; i++) { + diff |= (uint8_t)(a[i] ^ b[i]); + } + return diff == 0; +} diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/boot.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/boot.c new file mode 100644 index 0000000..0b1dcb1 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/boot.c @@ -0,0 +1,33 @@ +/** + * @file boot.c + * @brief Secure boot console and application handoff helpers. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include +#include "pico/stdlib.h" +#include "boot.h" +#include "image.h" + +void boot_init(void) { + stdio_init_all(); + sleep_ms(2000); + printf("\n=== 0x0026a secure bootloader ===\n"); +} + +void boot_halt(const char *reason) { + printf("BOOT FAILED: %s\n", reason); + while (true) { + sleep_ms(500); + } +} + +void boot_launch(const fw_manifest_t *manifest) { + printf("signature valid, entering app at 0x%08lx\n", + (unsigned long)manifest->app_base); + image_start(manifest->app_base); +} \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/image.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/image.c new file mode 100644 index 0000000..8e3a5f3 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/image.c @@ -0,0 +1,33 @@ +/** + * @file image.c + * @brief Loads the application stack pointer and branches to its reset vector. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include "image.h" + +/** @brief Application reset handler signature. */ +typedef void (*image_entry_t)(void); + +/** + * @brief Mask interrupts and point VTOR at the incoming image. + * @param base Vector table base address written to the VTOR register. + * @return void No return value. + */ +static void halt_irq_and_rebase(uint32_t base) { + __asm volatile ("cpsid i" ::: "memory"); + *(volatile uint32_t *)0xE000ED08U = base; +} + +void image_start(uint32_t vector_base) { + uint32_t *vectors = (uint32_t *)vector_base; + image_entry_t entry = (image_entry_t)vectors[1]; + halt_irq_and_rebase(vector_base); + __asm volatile ("msr msp, %0" :: "r" (vectors[0]) : "memory"); + __asm volatile ("dsb\n\tisb" ::: "memory"); + entry(); +} diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/main.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/main.c new file mode 100644 index 0000000..044abf5 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/main.c @@ -0,0 +1,34 @@ +/** + * @file main.c + * @brief Secure bootloader entry point (verify AES-128-CMAC, then boot). + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + * + * ----------------------------------------------------------------------------- + * + * This file is deliberately thin: it only sequences the secure boot steps. + * The console setup, halt reporting, and application handoff live in boot.c; + * the CMAC verification (and its key) live in verify.c; the manifest lives in + * manifest.c; and the raw reset-vector jump lives in image.c. + * + * Flash map (2 MiB, RP2350 Pico 2): + * 0x10000000 bootloader image (this program) + * 0x1001F000 one-sector firmware manifest (magic, size, CMAC tag) + * 0x10020000 signed application image + */ + +#include "manifest.h" +#include "boot.h" +#include "verify.h" + +int main(void) { + fw_manifest_t manifest; + boot_init(); + manifest_read(&manifest); + if (!manifest_is_valid(&manifest)) boot_halt("manifest invalid"); + if (!verify_manifest(&manifest)) boot_halt("firmware signature invalid"); + boot_launch(&manifest); +} \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/manifest.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/manifest.c new file mode 100644 index 0000000..90514c1 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/manifest.c @@ -0,0 +1,23 @@ +/** + * @file manifest.c + * @brief Reads and validates the firmware manifest from XIP flash. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include "flash_layout.h" +#include "manifest.h" + +void manifest_read(fw_manifest_t *out) { + const fw_manifest_t *src = (const fw_manifest_t *)FW_MANIFEST_BASE; + *out = *src; +} + +bool manifest_is_valid(const fw_manifest_t *manifest) { + if (manifest->magic != FW_MANIFEST_MAGIC) return false; + if (manifest->version != FW_MANIFEST_VERSION) return false; + return true; +} diff --git a/WEEK11/0x0026a_custom-bootloader/bootloader/src/verify.c b/WEEK11/0x0026a_custom-bootloader/bootloader/src/verify.c new file mode 100644 index 0000000..08b55cd --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/bootloader/src/verify.c @@ -0,0 +1,28 @@ +/** + * @file verify.c + * @brief Firmware authenticity verification for the secure bootloader. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + */ + +#include +#include "flash_layout.h" +#include "verify.h" +#include "aes_cmac.h" + +/** @brief AES-128 key that authenticates the application image. */ +static const uint8_t fw_key[FW_TAG_SIZE] = { + 0x49, 0x72, 0x6F, 0x6E, 0x4E, 0x65, 0x74, 0x42, + 0x6F, 0x6F, 0x74, 0x4B, 0x65, 0x79, 0x21, 0x21 +}; + +bool verify_manifest(const fw_manifest_t *manifest) { + const uint8_t *base = (const uint8_t *)manifest->app_base; + uint8_t computed[FW_TAG_SIZE]; + int rc = aes128_cmac(fw_key, base, manifest->app_size, computed); + if (rc != 0) return false; + return cmac_tags_equal(computed, manifest->tag); +} \ No newline at end of file diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.bin b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.bin new file mode 100755 index 0000000..f6c83d6 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.dis b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.dis new file mode 100644 index 0000000..dce99c3 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_app.dis @@ -0,0 +1,7874 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026a_custom-bootloader/build/0x0026a_app.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00004d10 10020000 10020000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 0000022c 10024d10 10024d10 00005d10 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 10024f3c 10024f3c 00005f3c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000024 10024f44 10024f44 00005f44 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00008000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00007498 2**0 + CONTENTS + 6 .data 0000051c 20000110 10024f68 00006110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 2000062c 2000062c 00007498 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 2000062c 2000062c 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 00002460 20000630 10025484 00007630 2**3 + ALLOC + 10 .heap 00000800 20002a90 10025484 00007a90 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00007498 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00007498 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00008000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10025484 10025484 00007484 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00007498 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 000074cc 2**0 + CONTENTS, READONLY + 17 .debug_info 00023a9d 00000000 00000000 00007511 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 000064b3 00000000 00000000 0002afae 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_loclists 000121c0 00000000 00000000 00031461 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_aranges 00000d18 00000000 00000000 00043628 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_rnglists 00003551 00000000 00000000 00044340 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line 000190d3 00000000 00000000 00047891 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_str 00005f07 00000000 00000000 00060964 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_frame 00002260 00000000 00000000 0006686c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c0 00000000 00000000 00068acc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026a_custom-bootloader/build/0x0026a_app.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10020000 <__VECTOR_TABLE>: +10020000: 20082000 .word 0x20082000 +10020004: 1002015d .word 0x1002015d +10020008: 1002011b .word 0x1002011b +1002000c: 1002011d .word 0x1002011d +10020010: 10020111 .word 0x10020111 +10020014: 10020111 .word 0x10020111 +10020018: 10020111 .word 0x10020111 +1002001c: 10020111 .word 0x10020111 +10020020: 10020119 .word 0x10020119 +10020024: 10020119 .word 0x10020119 +10020028: 10020119 .word 0x10020119 +1002002c: 1002011f .word 0x1002011f +10020030: 10020111 .word 0x10020111 +10020034: 10020119 .word 0x10020119 +10020038: 10020121 .word 0x10020121 +1002003c: 10020123 .word 0x10020123 +10020040: 10020111 .word 0x10020111 +10020044: 10020111 .word 0x10020111 +10020048: 10020111 .word 0x10020111 +1002004c: 10020111 .word 0x10020111 +10020050: 10020111 .word 0x10020111 +10020054: 10020111 .word 0x10020111 +10020058: 10020111 .word 0x10020111 +1002005c: 10020111 .word 0x10020111 +10020060: 10020111 .word 0x10020111 +10020064: 10020111 .word 0x10020111 +10020068: 10020111 .word 0x10020111 +1002006c: 10020111 .word 0x10020111 +10020070: 10020111 .word 0x10020111 +10020074: 10020111 .word 0x10020111 +10020078: 10020111 .word 0x10020111 +1002007c: 10020111 .word 0x10020111 +10020080: 10020111 .word 0x10020111 +10020084: 10020111 .word 0x10020111 +10020088: 10020111 .word 0x10020111 +1002008c: 10020111 .word 0x10020111 +10020090: 10020111 .word 0x10020111 +10020094: 10020111 .word 0x10020111 +10020098: 10020111 .word 0x10020111 +1002009c: 10020111 .word 0x10020111 +100200a0: 10020111 .word 0x10020111 +100200a4: 10020111 .word 0x10020111 +100200a8: 10020111 .word 0x10020111 +100200ac: 10020111 .word 0x10020111 +100200b0: 10020111 .word 0x10020111 +100200b4: 10020111 .word 0x10020111 +100200b8: 10020111 .word 0x10020111 +100200bc: 10020111 .word 0x10020111 +100200c0: 10020111 .word 0x10020111 +100200c4: 10020111 .word 0x10020111 +100200c8: 10020111 .word 0x10020111 +100200cc: 10020111 .word 0x10020111 +100200d0: 10020111 .word 0x10020111 +100200d4: 10020111 .word 0x10020111 +100200d8: 10020111 .word 0x10020111 +100200dc: 10020111 .word 0x10020111 +100200e0: 10020111 .word 0x10020111 +100200e4: 10020111 .word 0x10020111 +100200e8: 10020111 .word 0x10020111 +100200ec: 10020111 .word 0x10020111 +100200f0: 10020111 .word 0x10020111 +100200f4: 10020111 .word 0x10020111 +100200f8: 10020111 .word 0x10020111 +100200fc: 10020111 .word 0x10020111 +10020100: 10020111 .word 0x10020111 +10020104: 10020111 .word 0x10020111 +10020108: 10020111 .word 0x10020111 +1002010c: 10020111 .word 0x10020111 + +10020110 <__unhandled_user_irq>: +10020110: f3ef 8005 mrs r0, IPSR +10020114: 3810 subs r0, #16 + +10020116 : +10020116: be00 bkpt 0x0000 + +10020118 : +10020118: be00 bkpt 0x0000 + +1002011a : +1002011a: be00 bkpt 0x0000 + +1002011c : +1002011c: be00 bkpt 0x0000 + +1002011e : +1002011e: be00 bkpt 0x0000 + +10020120 : +10020120: be00 bkpt 0x0000 + +10020122 : +10020122: be00 bkpt 0x0000 + +10020124 <__default_isrs_end>: +10020124: 7188ebf2 .word 0x7188ebf2 +10020128: 10024f44 .word 0x10024f44 +1002012c: 10024f68 .word 0x10024f68 +10020130: 100201a0 .word 0x100201a0 +10020134: e71aa390 .word 0xe71aa390 + +10020138 <__binary_info_header_end>: +10020138: ffffded3 .word 0xffffded3 +1002013c: 10210142 .word 0x10210142 +10020140: 000001ff .word 0x000001ff +10020144: 0000534c .word 0x0000534c +10020148: ab123579 .word 0xab123579 + +1002014c <_entry_point>: +1002014c: f04f 0000 mov.w r0, #0 + +10020150 <_enter_vtable_in_r0>: +10020150: 491e ldr r1, [pc, #120] @ (100201cc ) +10020152: 6008 str r0, [r1, #0] +10020154: c806 ldmia r0!, {r1, r2} +10020156: f381 8808 msr MSP, r1 +1002015a: 4710 bx r2 + +1002015c <_reset_handler>: +1002015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10020160: 6800 ldr r0, [r0, #0] +10020162: b110 cbz r0, 1002016a + +10020164 : +10020164: f04f 0000 mov.w r0, #0 +10020168: e7f2 b.n 10020150 <_enter_vtable_in_r0> +1002016a: a40d add r4, pc, #52 @ (adr r4, 100201a0 ) +1002016c: cc0e ldmia r4!, {r1, r2, r3} +1002016e: 2900 cmp r1, #0 +10020170: d002 beq.n 10020178 +10020172: f000 f812 bl 1002019a +10020176: e7f9 b.n 1002016c +10020178: 4915 ldr r1, [pc, #84] @ (100201d0 ) +1002017a: 4a16 ldr r2, [pc, #88] @ (100201d4 ) +1002017c: 2000 movs r0, #0 +1002017e: e000 b.n 10020182 + +10020180 : +10020180: c101 stmia r1!, {r0} + +10020182 : +10020182: 4291 cmp r1, r2 +10020184: d1fc bne.n 10020180 + +10020186 : +10020186: 4914 ldr r1, [pc, #80] @ (100201d8 ) +10020188: 4788 blx r1 +1002018a: 4914 ldr r1, [pc, #80] @ (100201dc ) +1002018c: 4788 blx r1 +1002018e: 4914 ldr r1, [pc, #80] @ (100201e0 ) +10020190: 4788 blx r1 +10020192: be00 bkpt 0x0000 +10020194: e7fd b.n 10020192 + +10020196 : +10020196: c901 ldmia r1!, {r0} +10020198: c201 stmia r2!, {r0} + +1002019a : +1002019a: 429a cmp r2, r3 +1002019c: d3fb bcc.n 10020196 +1002019e: 4770 bx lr + +100201a0 : +100201a0: 10024f68 .word 0x10024f68 +100201a4: 20000110 .word 0x20000110 +100201a8: 2000062c .word 0x2000062c +100201ac: 10025484 .word 0x10025484 +100201b0: 20080000 .word 0x20080000 +100201b4: 20080000 .word 0x20080000 +100201b8: 10025484 .word 0x10025484 +100201bc: 20081000 .word 0x20081000 +100201c0: 20081000 .word 0x20081000 +100201c4: 00000000 .word 0x00000000 +100201c8: 4770 bx lr +100201ca: 0000 .short 0x0000 +100201cc: e000ed08 .word 0xe000ed08 +100201d0: 2000062c .word 0x2000062c +100201d4: 20002a90 .word 0x20002a90 +100201d8: 10023205 .word 0x10023205 +100201dc: 10020235 .word 0x10020235 +100201e0: 100231fd .word 0x100231fd + +100201e4 <_init>: +100201e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100201e6: bf00 nop + +100201e8 : +100201e8: 4b06 ldr r3, [pc, #24] @ (10020204 ) +100201ea: 4907 ldr r1, [pc, #28] @ (10020208 ) +100201ec: 1ac9 subs r1, r1, r3 +100201ee: 1089 asrs r1, r1, #2 +100201f0: bf48 it mi +100201f2: 3101 addmi r1, #1 +100201f4: 1049 asrs r1, r1, #1 +100201f6: d003 beq.n 10020200 +100201f8: 4b04 ldr r3, [pc, #16] @ (1002020c ) +100201fa: b10b cbz r3, 10020200 +100201fc: 4801 ldr r0, [pc, #4] @ (10020204 ) +100201fe: 4718 bx r3 +10020200: 4770 bx lr +10020202: bf00 nop +10020204: 2000062c .word 0x2000062c +10020208: 2000062c .word 0x2000062c +1002020c: 00000000 .word 0x00000000 + +10020210 : +10020210: b508 push {r3, lr} +10020212: 4b05 ldr r3, [pc, #20] @ (10020228 ) +10020214: b11b cbz r3, 1002021e +10020216: 4905 ldr r1, [pc, #20] @ (1002022c ) +10020218: 4805 ldr r0, [pc, #20] @ (10020230 ) +1002021a: f3af 8000 nop.w +1002021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10020222: f7ff bfe1 b.w 100201e8 +10020226: bf00 nop +10020228: 00000000 .word 0x00000000 +1002022c: 20002a40 .word 0x20002a40 +10020230: 10024d10 .word 0x10024d10 + +10020234
: +10020234: b500 push {lr} +10020236: b083 sub sp, #12 +10020238: f003 f90c bl 10023454 +1002023c: f000 f994 bl 10020568 +10020240: 4668 mov r0, sp +10020242: f000 f929 bl 10020498 +10020246: 4668 mov r0, sp +10020248: f000 f92e bl 100204a8 +1002024c: 2005 movs r0, #5 +1002024e: f000 f815 bl 1002027c +10020252: 2105 movs r1, #5 +10020254: 4808 ldr r0, [pc, #32] @ (10020278 ) +10020256: f003 f9c5 bl 100235e4 <__wrap_printf> +1002025a: f000 f823 bl 100202a4 +1002025e: 1e01 subs r1, r0, #0 +10020260: db06 blt.n 10020270 +10020262: 4668 mov r0, sp +10020264: f000 f938 bl 100204d8 +10020268: f000 f81c bl 100202a4 +1002026c: 1e01 subs r1, r0, #0 +1002026e: daf8 bge.n 10020262 +10020270: 2001 movs r0, #1 +10020272: f000 ff11 bl 10021098 +10020276: e7f0 b.n 1002025a +10020278: 10024d10 .word 0x10024d10 + +1002027c : +1002027c: 4b08 ldr r3, [pc, #32] @ (100202a0 ) +1002027e: b510 push {r4, lr} +10020280: 6018 str r0, [r3, #0] +10020282: 4604 mov r4, r0 +10020284: f000 f9da bl 1002063c +10020288: f04f 0300 mov.w r3, #0 +1002028c: ec43 4044 gpioc_bit_oe_put r4, r3 +10020290: 2101 movs r1, #1 +10020292: 4620 mov r0, r4 +10020294: e8bd 4010 ldmia.w sp!, {r4, lr} +10020298: 2200 movs r2, #0 +1002029a: f000 b9bb b.w 10020614 +1002029e: bf00 nop +100202a0: 20002a38 .word 0x20002a38 + +100202a4 : +100202a4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100202a8: 4b77 ldr r3, [pc, #476] @ (10020488 ) +100202aa: b085 sub sp, #20 +100202ac: 681d ldr r5, [r3, #0] +100202ae: 2601 movs r6, #1 +100202b0: f000 ffe4 bl 1002127c +100202b4: 40ae lsls r6, r5 +100202b6: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +100202ba: f04f 0900 mov.w r9, #0 +100202be: 4604 mov r4, r0 +100202c0: 460d mov r5, r1 +100202c2: f8df 81d0 ldr.w r8, [pc, #464] @ 10020494 +100202c6: e009 b.n 100202dc +100202c8: f000 ffd8 bl 1002127c +100202cc: 1b00 subs r0, r0, r4 +100202ce: eb61 0105 sbc.w r1, r1, r5 +100202d2: 4580 cmp r8, r0 +100202d4: eb79 0101 sbcs.w r1, r9, r1 +100202d8: f2c0 80d1 blt.w 1002047e +100202dc: 687b ldr r3, [r7, #4] +100202de: 4233 tst r3, r6 +100202e0: d1f2 bne.n 100202c8 +100202e2: f000 ffcb bl 1002127c +100202e6: 42a0 cmp r0, r4 +100202e8: eb61 0105 sbc.w r1, r1, r5 +100202ec: 2900 cmp r1, #0 +100202ee: f2c0 80c6 blt.w 1002047e +100202f2: 4b65 ldr r3, [pc, #404] @ (10020488 ) +100202f4: 2601 movs r6, #1 +100202f6: 681d ldr r5, [r3, #0] +100202f8: f000 ffc0 bl 1002127c +100202fc: 40ae lsls r6, r5 +100202fe: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +10020302: f642 68e1 movw r8, #12001 @ 0x2ee1 +10020306: 4604 mov r4, r0 +10020308: 460d mov r5, r1 +1002030a: e009 b.n 10020320 +1002030c: f000 ffb6 bl 1002127c +10020310: 1b00 subs r0, r0, r4 +10020312: eb61 0105 sbc.w r1, r1, r5 +10020316: 4540 cmp r0, r8 +10020318: f171 0100 sbcs.w r1, r1, #0 +1002031c: f280 80af bge.w 1002047e +10020320: 687b ldr r3, [r7, #4] +10020322: 4233 tst r3, r6 +10020324: d0f2 beq.n 1002030c +10020326: f000 ffa9 bl 1002127c +1002032a: 4b58 ldr r3, [pc, #352] @ (1002048c ) +1002032c: f240 72d1 movw r2, #2001 @ 0x7d1 +10020330: 1b1b subs r3, r3, r4 +10020332: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff +10020336: eb64 0505 sbc.w r5, r4, r5 +1002033a: 181b adds r3, r3, r0 +1002033c: eb45 0501 adc.w r5, r5, r1 +10020340: 4293 cmp r3, r2 +10020342: f175 0500 sbcs.w r5, r5, #0 +10020346: f080 809a bcs.w 1002047e +1002034a: 4b4f ldr r3, [pc, #316] @ (10020488 ) +1002034c: 2501 movs r5, #1 +1002034e: 681e ldr r6, [r3, #0] +10020350: f000 ff94 bl 1002127c +10020354: 40b5 lsls r5, r6 +10020356: f04f 4750 mov.w r7, #3489660928 @ 0xd0000000 +1002035a: f641 3859 movw r8, #7001 @ 0x1b59 +1002035e: 4604 mov r4, r0 +10020360: 460e mov r6, r1 +10020362: e009 b.n 10020378 +10020364: f000 ff8a bl 1002127c +10020368: 1b00 subs r0, r0, r4 +1002036a: eb61 0106 sbc.w r1, r1, r6 +1002036e: 4540 cmp r0, r8 +10020370: f171 0100 sbcs.w r1, r1, #0 +10020374: f280 8083 bge.w 1002047e +10020378: 687b ldr r3, [r7, #4] +1002037a: 402b ands r3, r5 +1002037c: d1f2 bne.n 10020364 +1002037e: 9301 str r3, [sp, #4] +10020380: f000 ff7c bl 1002127c +10020384: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff +10020388: f240 55dd movw r5, #1501 @ 0x5dd +1002038c: 4a40 ldr r2, [pc, #256] @ (10020490 ) +1002038e: 1b12 subs r2, r2, r4 +10020390: eb63 0606 sbc.w r6, r3, r6 +10020394: 1812 adds r2, r2, r0 +10020396: eb46 0601 adc.w r6, r6, r1 +1002039a: 42aa cmp r2, r5 +1002039c: f176 0600 sbcs.w r6, r6, #0 +100203a0: d26d bcs.n 1002047e +100203a2: 9b01 ldr r3, [sp, #4] +100203a4: f04f 0b01 mov.w fp, #1 +100203a8: 469a mov sl, r3 +100203aa: f240 35e9 movw r5, #1001 @ 0x3e9 +100203ae: 9303 str r3, [sp, #12] +100203b0: 4b35 ldr r3, [pc, #212] @ (10020488 ) +100203b2: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +100203b6: 681f ldr r7, [r3, #0] +100203b8: f000 ff60 bl 1002127c +100203bc: fa0b f707 lsl.w r7, fp, r7 +100203c0: 4604 mov r4, r0 +100203c2: 460e mov r6, r1 +100203c4: e008 b.n 100203d8 +100203c6: f000 ff59 bl 1002127c +100203ca: 1b00 subs r0, r0, r4 +100203cc: eb61 0106 sbc.w r1, r1, r6 +100203d0: 42a8 cmp r0, r5 +100203d2: f171 0100 sbcs.w r1, r1, #0 +100203d6: da52 bge.n 1002047e +100203d8: f8d8 3004 ldr.w r3, [r8, #4] +100203dc: 423b tst r3, r7 +100203de: d0f2 beq.n 100203c6 +100203e0: f000 ff4c bl 1002127c +100203e4: 42a0 cmp r0, r4 +100203e6: eb61 0106 sbc.w r1, r1, r6 +100203ea: 2900 cmp r1, #0 +100203ec: db47 blt.n 1002047e +100203ee: 4b26 ldr r3, [pc, #152] @ (10020488 ) +100203f0: f04f 4850 mov.w r8, #3489660928 @ 0xd0000000 +100203f4: 681f ldr r7, [r3, #0] +100203f6: f000 ff41 bl 1002127c +100203fa: f640 19c5 movw r9, #2501 @ 0x9c5 +100203fe: 4604 mov r4, r0 +10020400: 460e mov r6, r1 +10020402: fa0b f707 lsl.w r7, fp, r7 +10020406: e008 b.n 1002041a +10020408: f000 ff38 bl 1002127c +1002040c: 1b00 subs r0, r0, r4 +1002040e: eb61 0106 sbc.w r1, r1, r6 +10020412: 4548 cmp r0, r9 +10020414: f171 0100 sbcs.w r1, r1, #0 +10020418: da31 bge.n 1002047e +1002041a: f8d8 3004 ldr.w r3, [r8, #4] +1002041e: 423b tst r3, r7 +10020420: d1f2 bne.n 10020408 +10020422: f000 ff2b bl 1002127c +10020426: 1b00 subs r0, r0, r4 +10020428: eb61 0106 sbc.w r1, r1, r6 +1002042c: 28c8 cmp r0, #200 @ 0xc8 +1002042e: f171 0300 sbcs.w r3, r1, #0 +10020432: db24 blt.n 1002047e +10020434: f240 43b1 movw r3, #1201 @ 0x4b1 +10020438: 4298 cmp r0, r3 +1002043a: f171 0100 sbcs.w r1, r1, #0 +1002043e: db09 blt.n 10020454 +10020440: a903 add r1, sp, #12 +10020442: ea4f 02ea mov.w r2, sl, asr #3 +10020446: 5c88 ldrb r0, [r1, r2] +10020448: f00a 0307 and.w r3, sl, #7 +1002044c: fa0b f303 lsl.w r3, fp, r3 +10020450: 4303 orrs r3, r0 +10020452: 548b strb r3, [r1, r2] +10020454: f10a 0a01 add.w sl, sl, #1 +10020458: f1ba 0f20 cmp.w sl, #32 +1002045c: d1a8 bne.n 100203b0 +1002045e: f89d 300c ldrb.w r3, [sp, #12] +10020462: f89d 200d ldrb.w r2, [sp, #13] +10020466: 4413 add r3, r2 +10020468: b2db uxtb r3, r3 +1002046a: 2bff cmp r3, #255 @ 0xff +1002046c: d107 bne.n 1002047e +1002046e: f89d 000e ldrb.w r0, [sp, #14] +10020472: f89d 300f ldrb.w r3, [sp, #15] +10020476: 4403 add r3, r0 +10020478: b2db uxtb r3, r3 +1002047a: 2bff cmp r3, #255 @ 0xff +1002047c: d001 beq.n 10020482 +1002047e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10020482: b005 add sp, #20 +10020484: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10020488: 20002a38 .word 0x20002a38 +1002048c: ffffe0c0 .word 0xffffe0c0 +10020490: fffff254 .word 0xfffff254 +10020494: 000249f0 .word 0x000249f0 + +10020498 : +10020498: 2200 movs r2, #0 +1002049a: 4902 ldr r1, [pc, #8] @ (100204a4 ) +1002049c: 8082 strh r2, [r0, #4] +1002049e: 6001 str r1, [r0, #0] +100204a0: 4770 bx lr +100204a2: bf00 nop +100204a4: 00121110 .word 0x00121110 + +100204a8 : +100204a8: b538 push {r3, r4, r5, lr} +100204aa: 4604 mov r4, r0 +100204ac: 7800 ldrb r0, [r0, #0] +100204ae: f000 f8c5 bl 1002063c +100204b2: f04f 0501 mov.w r5, #1 +100204b6: 7823 ldrb r3, [r4, #0] +100204b8: ec45 3044 gpioc_bit_oe_put r3, r5 +100204bc: 7860 ldrb r0, [r4, #1] +100204be: f000 f8bd bl 1002063c +100204c2: 7863 ldrb r3, [r4, #1] +100204c4: ec45 3044 gpioc_bit_oe_put r3, r5 +100204c8: 78a0 ldrb r0, [r4, #2] +100204ca: f000 f8b7 bl 1002063c +100204ce: 78a3 ldrb r3, [r4, #2] +100204d0: ec45 3044 gpioc_bit_oe_put r3, r5 +100204d4: bd38 pop {r3, r4, r5, pc} +100204d6: bf00 nop + +100204d8 : +100204d8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} +100204dc: 1e0c subs r4, r1, #0 +100204de: db15 blt.n 1002050c +100204e0: 4605 mov r5, r0 +100204e2: 481f ldr r0, [pc, #124] @ (10020560 ) +100204e4: f003 f87e bl 100235e4 <__wrap_printf> +100204e8: 782f ldrb r7, [r5, #0] +100204ea: f04f 0300 mov.w r3, #0 +100204ee: 463e mov r6, r7 +100204f0: ec43 7040 gpioc_bit_out_put r7, r3 +100204f4: 786a ldrb r2, [r5, #1] +100204f6: ec43 2040 gpioc_bit_out_put r2, r3 +100204fa: 78a9 ldrb r1, [r5, #2] +100204fc: ec43 1040 gpioc_bit_out_put r1, r3 +10020500: 2c0c cmp r4, #12 +10020502: d005 beq.n 10020510 +10020504: 2c18 cmp r4, #24 +10020506: d026 beq.n 10020556 +10020508: 2c5e cmp r4, #94 @ 0x5e +1002050a: d01f beq.n 1002054c +1002050c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} +10020510: f04f 0901 mov.w r9, #1 +10020514: 2403 movs r4, #3 +10020516: f04f 0501 mov.w r5, #1 +1002051a: f04f 0800 mov.w r8, #0 +1002051e: ec45 6040 gpioc_bit_out_put r6, r5 +10020522: 2032 movs r0, #50 @ 0x32 +10020524: f000 fdb8 bl 10021098 +10020528: ec48 6040 gpioc_bit_out_put r6, r8 +1002052c: 2032 movs r0, #50 @ 0x32 +1002052e: f000 fdb3 bl 10021098 +10020532: 1e63 subs r3, r4, #1 +10020534: f013 04ff ands.w r4, r3, #255 @ 0xff +10020538: d1f1 bne.n 1002051e +1002053a: ec45 6040 gpioc_bit_out_put r6, r5 +1002053e: 4809 ldr r0, [pc, #36] @ (10020564 ) +10020540: 463a mov r2, r7 +10020542: 4649 mov r1, r9 +10020544: e8bd 43f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, lr} +10020548: f003 b84c b.w 100235e4 <__wrap_printf> +1002054c: 460e mov r6, r1 +1002054e: f04f 0903 mov.w r9, #3 +10020552: 460f mov r7, r1 +10020554: e7de b.n 10020514 +10020556: 4616 mov r6, r2 +10020558: f04f 0902 mov.w r9, #2 +1002055c: 4617 mov r7, r2 +1002055e: e7d9 b.n 10020514 +10020560: 10024d30 .word 0x10024d30 +10020564: 10024d48 .word 0x10024d48 + +10020568 : +10020568: b5f0 push {r4, r5, r6, r7, lr} +1002056a: b0d7 sub sp, #348 @ 0x15c +1002056c: af07 add r7, sp, #28 +1002056e: 46bc mov ip, r7 +10020570: 4c15 ldr r4, [pc, #84] @ (100205c8 ) +10020572: 4e16 ldr r6, [pc, #88] @ (100205cc ) +10020574: cc0f ldmia r4!, {r0, r1, r2, r3} +10020576: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +1002057a: cc0f ldmia r4!, {r0, r1, r2, r3} +1002057c: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +10020580: 6823 ldr r3, [r4, #0] +10020582: ad03 add r5, sp, #12 +10020584: f88c 3000 strb.w r3, [ip] +10020588: e896 000f ldmia.w r6, {r0, r1, r2, r3} +1002058c: e885 000f stmia.w r5, {r0, r1, r2, r3} +10020590: a810 add r0, sp, #64 @ 0x40 +10020592: f003 fa5b bl 10023a4c +10020596: 2280 movs r2, #128 @ 0x80 +10020598: 490d ldr r1, [pc, #52] @ (100205d0 ) +1002059a: a810 add r0, sp, #64 @ 0x40 +1002059c: f003 fd74 bl 10024088 +100205a0: 2220 movs r2, #32 +100205a2: 2100 movs r1, #0 +100205a4: 462b mov r3, r5 +100205a6: e9cd 7700 strd r7, r7, [sp] +100205aa: a810 add r0, sp, #64 @ 0x40 +100205ac: f004 f9f2 bl 10024994 +100205b0: 4604 mov r4, r0 +100205b2: a810 add r0, sp, #64 @ 0x40 +100205b4: f003 fa50 bl 10023a58 +100205b8: b91c cbnz r4, 100205c2 +100205ba: 4639 mov r1, r7 +100205bc: 4805 ldr r0, [pc, #20] @ (100205d4 ) +100205be: f003 f811 bl 100235e4 <__wrap_printf> +100205c2: 4620 mov r0, r4 +100205c4: b057 add sp, #348 @ 0x15c +100205c6: bdf0 pop {r4, r5, r6, r7, pc} +100205c8: 10024d78 .word 0x10024d78 +100205cc: 10024d9c .word 0x10024d9c +100205d0: 10024e6c .word 0x10024e6c +100205d4: 10024d68 .word 0x10024d68 + +100205d8 : +100205d8: b410 push {r4} +100205da: f44f 7480 mov.w r4, #256 @ 0x100 +100205de: 4b0c ldr r3, [pc, #48] @ (10020610 ) +100205e0: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100205e4: eb03 0380 add.w r3, r3, r0, lsl #2 +100205e8: 00c0 lsls r0, r0, #3 +100205ea: f082 0240 eor.w r2, r2, #64 @ 0x40 +100205ee: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100205f2: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +100205f6: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100205fa: f500 3020 add.w r0, r0, #163840 @ 0x28000 +100205fe: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10020602: f8cc 2000 str.w r2, [ip] +10020606: 6041 str r1, [r0, #4] +10020608: 601c str r4, [r3, #0] +1002060a: f85d 4b04 ldr.w r4, [sp], #4 +1002060e: 4770 bx lr +10020610: 40038004 .word 0x40038004 + +10020614 : +10020614: b410 push {r4} +10020616: 4c08 ldr r4, [pc, #32] @ (10020638 ) +10020618: 00c9 lsls r1, r1, #3 +1002061a: ea41 0182 orr.w r1, r1, r2, lsl #2 +1002061e: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10020622: eb04 0380 add.w r3, r4, r0, lsl #2 +10020626: 4051 eors r1, r2 +10020628: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1002062c: f001 010c and.w r1, r1, #12 +10020630: f85d 4b04 ldr.w r4, [sp], #4 +10020634: 6019 str r1, [r3, #0] +10020636: 4770 bx lr +10020638: 40038004 .word 0x40038004 + +1002063c : +1002063c: b430 push {r4, r5} +1002063e: f04f 0300 mov.w r3, #0 +10020642: ec43 0044 gpioc_bit_oe_put r0, r3 +10020646: ec43 0040 gpioc_bit_out_put r0, r3 +1002064a: 2505 movs r5, #5 +1002064c: f44f 7480 mov.w r4, #256 @ 0x100 +10020650: 4b0b ldr r3, [pc, #44] @ (10020680 ) +10020652: 00c2 lsls r2, r0, #3 +10020654: f853 1020 ldr.w r1, [r3, r0, lsl #2] +10020658: eb03 0080 add.w r0, r3, r0, lsl #2 +1002065c: f081 0140 eor.w r1, r1, #64 @ 0x40 +10020660: f102 4380 add.w r3, r2, #1073741824 @ 0x40000000 +10020664: f503 3320 add.w r3, r3, #163840 @ 0x28000 +10020668: f001 02c0 and.w r2, r1, #192 @ 0xc0 +1002066c: f500 5180 add.w r1, r0, #4096 @ 0x1000 +10020670: f500 5040 add.w r0, r0, #12288 @ 0x3000 +10020674: 600a str r2, [r1, #0] +10020676: 605d str r5, [r3, #4] +10020678: 6004 str r4, [r0, #0] +1002067a: bc30 pop {r4, r5} +1002067c: 4770 bx lr +1002067e: bf00 nop +10020680: 40038004 .word 0x40038004 + +10020684 : +10020684: b40f push {r0, r1, r2, r3} +10020686: b500 push {lr} +10020688: b083 sub sp, #12 +1002068a: 9c04 ldr r4, [sp, #16] +1002068c: 4807 ldr r0, [pc, #28] @ (100206ac ) +1002068e: f002 ff29 bl 100234e4 <__wrap_puts> +10020692: b13c cbz r4, 100206a4 +10020694: a905 add r1, sp, #20 +10020696: 4620 mov r0, r4 +10020698: 9101 str r1, [sp, #4] +1002069a: f002 fd95 bl 100231c8 +1002069e: 4804 ldr r0, [pc, #16] @ (100206b0 ) +100206a0: f002 ff20 bl 100234e4 <__wrap_puts> +100206a4: 2001 movs r0, #1 +100206a6: f002 fda7 bl 100231f8 <_exit> +100206aa: bf00 nop +100206ac: 10024db0 .word 0x10024db0 +100206b0: 10024dc0 .word 0x10024dc0 + +100206b4 : +100206b4: b570 push {r4, r5, r6, lr} +100206b6: 4686 mov lr, r0 +100206b8: f3ef 8510 mrs r5, PRIMASK +100206bc: b672 cpsid i +100206be: 4c12 ldr r4, [pc, #72] @ (10020708 ) +100206c0: e8d4 6fcf ldaexb r6, [r4] +100206c4: 2001 movs r0, #1 +100206c6: 2e00 cmp r6, #0 +100206c8: d1fa bne.n 100206c0 +100206ca: e8c4 0f46 strexb r6, r0, [r4] +100206ce: 2e00 cmp r6, #0 +100206d0: d1f6 bne.n 100206c0 +100206d2: f3bf 8f5f dmb sy +100206d6: f04f 0c01 mov.w ip, #1 +100206da: 08c8 lsrs r0, r1, #3 +100206dc: f001 0307 and.w r3, r1, #7 +100206e0: fa0c f303 lsl.w r3, ip, r3 +100206e4: f81e c000 ldrb.w ip, [lr, r0] +100206e8: ea1c 0603 ands.w r6, ip, r3 +100206ec: d108 bne.n 10020700 +100206ee: ea4c 0c03 orr.w ip, ip, r3 +100206f2: f80e c000 strb.w ip, [lr, r0] +100206f6: e8c4 6f8f stlb r6, [r4] +100206fa: f385 8810 msr PRIMASK, r5 +100206fe: bd70 pop {r4, r5, r6, pc} +10020700: 4610 mov r0, r2 +10020702: f7ff ffbf bl 10020684 +10020706: bf00 nop +10020708: 200029e3 .word 0x200029e3 + +1002070c : +1002070c: 4a04 ldr r2, [pc, #16] @ (10020720 ) +1002070e: 7810 ldrb r0, [r2, #0] +10020710: 1c43 adds r3, r0, #1 +10020712: b2db uxtb r3, r3 +10020714: 2b18 cmp r3, #24 +10020716: bf28 it cs +10020718: 2310 movcs r3, #16 +1002071a: 7013 strb r3, [r2, #0] +1002071c: 4770 bx lr +1002071e: bf00 nop +10020720: 200005a8 .word 0x200005a8 + +10020724 : +10020724: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10020728: 6893 ldr r3, [r2, #8] +1002072a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +1002072e: 6093 str r3, [r2, #8] +10020730: 4770 bx lr +10020732: bf00 nop + +10020734 : +10020734: 2100 movs r1, #0 +10020736: 4b04 ldr r3, [pc, #16] @ (10020748 ) +10020738: f103 0220 add.w r2, r3, #32 +1002073c: e8c3 1f8f stlb r1, [r3] +10020740: 3301 adds r3, #1 +10020742: 4293 cmp r3, r2 +10020744: d1fa bne.n 1002073c +10020746: 4770 bx lr +10020748: 200029d8 .word 0x200029d8 + +1002074c : +1002074c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +10020750: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +10020754: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +10020758: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +1002075c: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +10020760: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +10020764: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +10020768: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +1002076c: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10020770: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10020774: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +10020778: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +1002077c: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10020780: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10020784: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +10020788: b662 cpsie i +1002078a: 4770 bx lr + +1002078c : +1002078c: 2301 movs r3, #1 +1002078e: f000 021f and.w r2, r0, #31 +10020792: 4093 lsls r3, r2 +10020794: 0940 lsrs r0, r0, #5 +10020796: b141 cbz r1, 100207aa +10020798: 0080 lsls r0, r0, #2 +1002079a: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +1002079e: f500 4061 add.w r0, r0, #57600 @ 0xe100 +100207a2: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +100207a6: 6003 str r3, [r0, #0] +100207a8: 4770 bx lr +100207aa: 4a02 ldr r2, [pc, #8] @ (100207b4 ) +100207ac: 3020 adds r0, #32 +100207ae: f842 3020 str.w r3, [r2, r0, lsl #2] +100207b2: 4770 bx lr +100207b4: e000e100 .word 0xe000e100 + +100207b8 : +100207b8: b5f8 push {r3, r4, r5, r6, r7, lr} +100207ba: 460d mov r5, r1 +100207bc: f3ef 8710 mrs r7, PRIMASK +100207c0: b672 cpsid i +100207c2: 4e12 ldr r6, [pc, #72] @ (1002080c ) +100207c4: e8d6 2fcf ldaexb r2, [r6] +100207c8: 2301 movs r3, #1 +100207ca: 2a00 cmp r2, #0 +100207cc: d1fa bne.n 100207c4 +100207ce: e8c6 3f42 strexb r2, r3, [r6] +100207d2: 2a00 cmp r2, #0 +100207d4: d1f6 bne.n 100207c4 +100207d6: f3bf 8f5f dmb sy +100207da: 4b0d ldr r3, [pc, #52] @ (10020810 ) +100207dc: f100 0410 add.w r4, r0, #16 +100207e0: 689b ldr r3, [r3, #8] +100207e2: 4a0c ldr r2, [pc, #48] @ (10020814 ) +100207e4: f853 3024 ldr.w r3, [r3, r4, lsl #2] +100207e8: 4293 cmp r3, r2 +100207ea: d003 beq.n 100207f4 +100207ec: 4299 cmp r1, r3 +100207ee: d001 beq.n 100207f4 +100207f0: f000 ff0e bl 10021610 +100207f4: 4b06 ldr r3, [pc, #24] @ (10020810 ) +100207f6: 689b ldr r3, [r3, #8] +100207f8: f843 5024 str.w r5, [r3, r4, lsl #2] +100207fc: f3bf 8f5f dmb sy +10020800: 2300 movs r3, #0 +10020802: e8c6 3f8f stlb r3, [r6] +10020806: f387 8810 msr PRIMASK, r7 +1002080a: bdf8 pop {r3, r4, r5, r6, r7, pc} +1002080c: 200029e1 .word 0x200029e1 +10020810: e000ed00 .word 0xe000ed00 +10020814: 10020111 .word 0x10020111 + +10020818 : +10020818: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1002081c: b083 sub sp, #12 +1002081e: f3ef 8a10 mrs sl, PRIMASK +10020822: b672 cpsid i +10020824: 4e71 ldr r6, [pc, #452] @ (100209ec ) +10020826: e8d6 2fcf ldaexb r2, [r6] +1002082a: 2301 movs r3, #1 +1002082c: 2a00 cmp r2, #0 +1002082e: d1fa bne.n 10020826 +10020830: e8c6 3f42 strexb r2, r3, [r6] +10020834: 2a00 cmp r2, #0 +10020836: d1f6 bne.n 10020826 +10020838: f3bf 8f5f dmb sy +1002083c: 4b6c ldr r3, [pc, #432] @ (100209f0 ) +1002083e: f100 0810 add.w r8, r0, #16 +10020842: 689b ldr r3, [r3, #8] +10020844: 4a6b ldr r2, [pc, #428] @ (100209f4 ) +10020846: f853 5028 ldr.w r5, [r3, r8, lsl #2] +1002084a: 4295 cmp r5, r2 +1002084c: d045 beq.n 100208da +1002084e: 428d cmp r5, r1 +10020850: 460c mov r4, r1 +10020852: d050 beq.n 100208f6 +10020854: 4f68 ldr r7, [pc, #416] @ (100209f8 ) +10020856: 1beb subs r3, r5, r7 +10020858: 2b2f cmp r3, #47 @ 0x2f +1002085a: d83e bhi.n 100208da +1002085c: 2101 movs r1, #1 +1002085e: ea4f 1950 mov.w r9, r0, lsr #5 +10020862: ea4f 0989 mov.w r9, r9, lsl #2 +10020866: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +1002086a: f509 4961 add.w r9, r9, #57600 @ 0xe100 +1002086e: f000 031f and.w r3, r0, #31 +10020872: fa01 f003 lsl.w r0, r1, r3 +10020876: f8d9 3000 ldr.w r3, [r9] +1002087a: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +1002087e: ea00 0b03 and.w fp, r0, r3 +10020882: f3bf 8f5f dmb sy +10020886: f3ef 8105 mrs r1, IPSR +1002088a: b2c9 uxtb r1, r1 +1002088c: 2900 cmp r1, #0 +1002088e: d034 beq.n 100208fa +10020890: 4588 cmp r8, r1 +10020892: d005 beq.n 100208a0 +10020894: e9cd 1000 strd r1, r0, [sp] +10020898: f000 feba bl 10021610 +1002089c: e9dd 1000 ldrd r1, r0, [sp] +100208a0: f025 0e01 bic.w lr, r5, #1 +100208a4: f8de c008 ldr.w ip, [lr, #8] +100208a8: 4564 cmp r4, ip +100208aa: d105 bne.n 100208b8 +100208ac: e089 b.n 100209c2 +100208ae: f8d3 c008 ldr.w ip, [r3, #8] +100208b2: 4564 cmp r4, ip +100208b4: d031 beq.n 1002091a +100208b6: 469e mov lr, r3 +100208b8: f99e 2006 ldrsb.w r2, [lr, #6] +100208bc: eb02 0342 add.w r3, r2, r2, lsl #1 +100208c0: 2a00 cmp r2, #0 +100208c2: eb07 0383 add.w r3, r7, r3, lsl #2 +100208c6: daf2 bge.n 100208ae +100208c8: 4564 cmp r4, ip +100208ca: d061 beq.n 10020990 +100208cc: f1bb 0f00 cmp.w fp, #0 +100208d0: d020 beq.n 10020914 +100208d2: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +100208d6: f8c9 0000 str.w r0, [r9] +100208da: 4b45 ldr r3, [pc, #276] @ (100209f0 ) +100208dc: 689b ldr r3, [r3, #8] +100208de: f843 5028 str.w r5, [r3, r8, lsl #2] +100208e2: f3bf 8f5f dmb sy +100208e6: 2300 movs r3, #0 +100208e8: e8c6 3f8f stlb r3, [r6] +100208ec: f38a 8810 msr PRIMASK, sl +100208f0: b003 add sp, #12 +100208f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100208f6: 4615 mov r5, r2 +100208f8: e7ef b.n 100208da +100208fa: f025 0e01 bic.w lr, r5, #1 +100208fe: f8de c008 ldr.w ip, [lr, #8] +10020902: 4564 cmp r4, ip +10020904: d1d8 bne.n 100208b8 +10020906: f99e 4006 ldrsb.w r4, [lr, #6] +1002090a: 4673 mov r3, lr +1002090c: 2c00 cmp r4, #0 +1002090e: da08 bge.n 10020922 +10020910: 4615 mov r5, r2 +10020912: e046 b.n 100209a2 +10020914: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10020918: e7df b.n 100208da +1002091a: f993 4006 ldrsb.w r4, [r3, #6] +1002091e: 2c00 cmp r4, #0 +10020920: db37 blt.n 10020992 +10020922: eb04 0c44 add.w ip, r4, r4, lsl #1 +10020926: eb07 0c8c add.w ip, r7, ip, lsl #2 +1002092a: f89c 1007 ldrb.w r1, [ip, #7] +1002092e: f8dc 2008 ldr.w r2, [ip, #8] +10020932: 71d9 strb r1, [r3, #7] +10020934: 609a str r2, [r3, #8] +10020936: f99c 2006 ldrsb.w r2, [ip, #6] +1002093a: 0061 lsls r1, r4, #1 +1002093c: 2a00 cmp r2, #0 +1002093e: 719a strb r2, [r3, #6] +10020940: db3d blt.n 100209be +10020942: f8bc e004 ldrh.w lr, [ip, #4] +10020946: ea5f 5e4e movs.w lr, lr, lsl #21 +1002094a: d505 bpl.n 10020958 +1002094c: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +10020950: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +10020954: f10e 0e1f add.w lr, lr, #31 +10020958: f06f 0c07 mvn.w ip, #7 +1002095c: 190a adds r2, r1, r4 +1002095e: ea4f 5e6e mov.w lr, lr, asr #21 +10020962: 0092 lsls r2, r2, #2 +10020964: eb02 024e add.w r2, r2, lr, lsl #1 +10020968: 3208 adds r2, #8 +1002096a: 443a add r2, r7 +1002096c: ebac 0c03 sub.w ip, ip, r3 +10020970: 4462 add r2, ip +10020972: f3c2 024a ubfx r2, r2, #1, #11 +10020976: ea6f 42c2 mvn.w r2, r2, lsl #19 +1002097a: ea6f 42d2 mvn.w r2, r2, lsr #19 +1002097e: 809a strh r2, [r3, #4] +10020980: 4b1e ldr r3, [pc, #120] @ (100209fc ) +10020982: 4421 add r1, r4 +10020984: 781a ldrb r2, [r3, #0] +10020986: eb07 0181 add.w r1, r7, r1, lsl #2 +1002098a: 701c strb r4, [r3, #0] +1002098c: 718a strb r2, [r1, #6] +1002098e: e79d b.n 100208cc +10020990: 4673 mov r3, lr +10020992: b9d9 cbnz r1, 100209cc +10020994: 22ff movs r2, #255 @ 0xff +10020996: f88e 2006 strb.w r2, [lr, #6] +1002099a: f64b 5201 movw r2, #48385 @ 0xbd01 +1002099e: f8ae 2004 strh.w r2, [lr, #4] +100209a2: 4c16 ldr r4, [pc, #88] @ (100209fc ) +100209a4: f64a 22aa movw r2, #43690 @ 0xaaaa +100209a8: f894 c000 ldrb.w ip, [r4] +100209ac: 4619 mov r1, r3 +100209ae: 1bc9 subs r1, r1, r7 +100209b0: 4149 adcs r1, r1 +100209b2: 434a muls r2, r1 +100209b4: 0d12 lsrs r2, r2, #20 +100209b6: f883 c006 strb.w ip, [r3, #6] +100209ba: 7022 strb r2, [r4, #0] +100209bc: e786 b.n 100208cc +100209be: 4a10 ldr r2, [pc, #64] @ (10020a00 ) +100209c0: e7dd b.n 1002097e +100209c2: f99e 4006 ldrsb.w r4, [lr, #6] +100209c6: 4673 mov r3, lr +100209c8: 2c00 cmp r4, #0 +100209ca: daaa bge.n 10020922 +100209cc: 4a0d ldr r2, [pc, #52] @ (10020a04 ) +100209ce: 4c0e ldr r4, [pc, #56] @ (10020a08 ) +100209d0: 1ad2 subs r2, r2, r3 +100209d2: 3a08 subs r2, #8 +100209d4: f3c2 310a ubfx r1, r2, #12, #11 +100209d8: ea6f 5101 mvn.w r1, r1, lsl #20 +100209dc: ea6f 5111 mvn.w r1, r1, lsr #20 +100209e0: ea44 0252 orr.w r2, r4, r2, lsr #1 +100209e4: 80da strh r2, [r3, #6] +100209e6: 8099 strh r1, [r3, #4] +100209e8: e770 b.n 100208cc +100209ea: bf00 nop +100209ec: 200029e1 .word 0x200029e1 +100209f0: e000ed00 .word 0xe000ed00 +100209f4: 10020111 .word 0x10020111 +100209f8: 200005ac .word 0x200005ac +100209fc: 20002a8c .word 0x20002a8c +10020a00: ffffbd01 .word 0xffffbd01 +10020a04: 200005e6 .word 0x200005e6 +10020a08: fffff800 .word 0xfffff800 + +10020a0c : +10020a0c: b5f0 push {r4, r5, r6, r7, lr} +10020a0e: f3ef 8505 mrs r5, IPSR +10020a12: b2ed uxtb r5, r5 +10020a14: f3ef 8c10 mrs ip, PRIMASK +10020a18: b672 cpsid i +10020a1a: 4926 ldr r1, [pc, #152] @ (10020ab4 ) +10020a1c: e8d1 2fcf ldaexb r2, [r1] +10020a20: 2301 movs r3, #1 +10020a22: 2a00 cmp r2, #0 +10020a24: d1fa bne.n 10020a1c +10020a26: e8c1 3f42 strexb r2, r3, [r1] +10020a2a: 2a00 cmp r2, #0 +10020a2c: d1f6 bne.n 10020a1c +10020a2e: f3bf 8f5f dmb sy +10020a32: 4e21 ldr r6, [pc, #132] @ (10020ab8 ) +10020a34: f040 0e01 orr.w lr, r0, #1 +10020a38: 68b4 ldr r4, [r6, #8] +10020a3a: f64a 23aa movw r3, #43690 @ 0xaaaa +10020a3e: f854 7025 ldr.w r7, [r4, r5, lsl #2] +10020a42: 4a1e ldr r2, [pc, #120] @ (10020abc ) +10020a44: 4604 mov r4, r0 +10020a46: 1aa4 subs r4, r4, r2 +10020a48: 4164 adcs r4, r4 +10020a4a: 4363 muls r3, r4 +10020a4c: 0d1b lsrs r3, r3, #20 +10020a4e: 4577 cmp r7, lr +10020a50: b25b sxtb r3, r3 +10020a52: d01b beq.n 10020a8c +10020a54: f992 4006 ldrsb.w r4, [r2, #6] +10020a58: 429c cmp r4, r3 +10020a5a: d01c beq.n 10020a96 +10020a5c: f992 4012 ldrsb.w r4, [r2, #18] +10020a60: 429c cmp r4, r3 +10020a62: d023 beq.n 10020aac +10020a64: f992 401e ldrsb.w r4, [r2, #30] +10020a68: 429c cmp r4, r3 +10020a6a: d021 beq.n 10020ab0 +10020a6c: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10020a70: 429c cmp r4, r3 +10020a72: bf08 it eq +10020a74: 2403 moveq r4, #3 +10020a76: d00f beq.n 10020a98 +10020a78: 4a11 ldr r2, [pc, #68] @ (10020ac0 ) +10020a7a: 2400 movs r4, #0 +10020a7c: 7815 ldrb r5, [r2, #0] +10020a7e: 7013 strb r3, [r2, #0] +10020a80: 7185 strb r5, [r0, #6] +10020a82: e8c1 4f8f stlb r4, [r1] +10020a86: f38c 8810 msr PRIMASK, ip +10020a8a: bdf0 pop {r4, r5, r6, r7, pc} +10020a8c: 68b2 ldr r2, [r6, #8] +10020a8e: 4c0d ldr r4, [pc, #52] @ (10020ac4 ) +10020a90: f842 4025 str.w r4, [r2, r5, lsl #2] +10020a94: e7f0 b.n 10020a78 +10020a96: 2400 movs r4, #0 +10020a98: eb04 0444 add.w r4, r4, r4, lsl #1 +10020a9c: eb02 0284 add.w r2, r2, r4, lsl #2 +10020aa0: 24ff movs r4, #255 @ 0xff +10020aa2: 7194 strb r4, [r2, #6] +10020aa4: f64b 5401 movw r4, #48385 @ 0xbd01 +10020aa8: 8094 strh r4, [r2, #4] +10020aaa: e7e5 b.n 10020a78 +10020aac: 2401 movs r4, #1 +10020aae: e7f3 b.n 10020a98 +10020ab0: 2402 movs r4, #2 +10020ab2: e7f1 b.n 10020a98 +10020ab4: 200029e1 .word 0x200029e1 +10020ab8: e000ed00 .word 0xe000ed00 +10020abc: 200005ac .word 0x200005ac +10020ac0: 20002a8c .word 0x20002a8c +10020ac4: 10020111 .word 0x10020111 + +10020ac8 : +10020ac8: 4b01 ldr r3, [pc, #4] @ (10020ad0 ) +10020aca: 440b add r3, r1 +10020acc: 6003 str r3, [r0, #0] +10020ace: 4770 bx lr +10020ad0: 200029d8 .word 0x200029d8 + +10020ad4 : +10020ad4: b570 push {r4, r5, r6, lr} +10020ad6: 4c10 ldr r4, [pc, #64] @ (10020b18 ) +10020ad8: 4d10 ldr r5, [pc, #64] @ (10020b1c ) +10020ada: 42ac cmp r4, r5 +10020adc: d20e bcs.n 10020afc +10020ade: 26ff movs r6, #255 @ 0xff +10020ae0: 6823 ldr r3, [r4, #0] +10020ae2: b163 cbz r3, 10020afe +10020ae4: f7ff fe12 bl 1002070c +10020ae8: 4601 mov r1, r0 +10020aea: 4620 mov r0, r4 +10020aec: f7ff ffec bl 10020ac8 +10020af0: 80a6 strh r6, [r4, #4] +10020af2: f3bf 8f5f dmb sy +10020af6: 3408 adds r4, #8 +10020af8: 42ac cmp r4, r5 +10020afa: d3f1 bcc.n 10020ae0 +10020afc: bd70 pop {r4, r5, r6, pc} +10020afe: f7ff fe05 bl 1002070c +10020b02: 4601 mov r1, r0 +10020b04: 4620 mov r0, r4 +10020b06: f7ff ffdf bl 10020ac8 +10020b0a: 7126 strb r6, [r4, #4] +10020b0c: f3bf 8f5f dmb sy +10020b10: 3408 adds r4, #8 +10020b12: 42ac cmp r4, r5 +10020b14: d3e4 bcc.n 10020ae0 +10020b16: bd70 pop {r4, r5, r6, pc} +10020b18: 20000624 .word 0x20000624 +10020b1c: 2000062c .word 0x2000062c + +10020b20 : +10020b20: 4b0d ldr r3, [pc, #52] @ (10020b58 ) +10020b22: 681a ldr r2, [r3, #0] +10020b24: f3ef 8110 mrs r1, PRIMASK +10020b28: b672 cpsid i +10020b2a: e8d2 cfcf ldaexb ip, [r2] +10020b2e: 2001 movs r0, #1 +10020b30: f1bc 0f00 cmp.w ip, #0 +10020b34: d1f9 bne.n 10020b2a +10020b36: e8c2 0f4c strexb ip, r0, [r2] +10020b3a: f1bc 0f00 cmp.w ip, #0 +10020b3e: d1f4 bne.n 10020b2a +10020b40: f3bf 8f5f dmb sy +10020b44: 2200 movs r2, #0 +10020b46: 681b ldr r3, [r3, #0] +10020b48: e8c3 2f8f stlb r2, [r3] +10020b4c: f381 8810 msr PRIMASK, r1 +10020b50: bf40 sev +10020b52: 2000 movs r0, #0 +10020b54: 2100 movs r1, #0 +10020b56: 4770 bx lr +10020b58: 20002a80 .word 0x20002a80 +10020b5c: 00000000 .word 0x00000000 + +10020b60 : +10020b60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10020b64: ed2d 8b02 vpush {d8} +10020b68: b085 sub sp, #20 +10020b6a: f3ef 8305 mrs r3, IPSR +10020b6e: b2db uxtb r3, r3 +10020b70: 3b10 subs r3, #16 +10020b72: 089a lsrs r2, r3, #2 +10020b74: bf18 it ne +10020b76: 2201 movne r2, #1 +10020b78: f04f 0101 mov.w r1, #1 +10020b7c: f003 0b03 and.w fp, r3, #3 +10020b80: bf18 it ne +10020b82: 4daf ldrne r5, [pc, #700] @ (10020e40 ) +10020b84: 4baf ldr r3, [pc, #700] @ (10020e44 ) +10020b86: bf08 it eq +10020b88: 4daf ldreq r5, [pc, #700] @ (10020e48 ) +10020b8a: eb0b 0282 add.w r2, fp, r2, lsl #2 +10020b8e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10020b92: fa01 f20b lsl.w r2, r1, fp +10020b96: f505 5341 add.w r3, r5, #12352 @ 0x3040 +10020b9a: ed9f 8ba7 vldr d8, [pc, #668] @ 10020e38 +10020b9e: 9201 str r2, [sp, #4] +10020ba0: 605a str r2, [r3, #4] +10020ba2: e02f b.n 10020c04 +10020ba4: 88b3 ldrh r3, [r6, #4] +10020ba6: 041c lsls r4, r3, #16 +10020ba8: f140 8093 bpl.w 10020cd2 +10020bac: 79b3 ldrb r3, [r6, #6] +10020bae: 2b00 cmp r3, #0 +10020bb0: f040 80dd bne.w 10020d6e +10020bb4: f9b6 2008 ldrsh.w r2, [r6, #8] +10020bb8: 2a00 cmp r2, #0 +10020bba: f2c0 811e blt.w 10020dfa +10020bbe: 6973 ldr r3, [r6, #20] +10020bc0: eb02 0242 add.w r2, r2, r2, lsl #1 +10020bc4: eb03 03c2 add.w r3, r3, r2, lsl #3 +10020bc8: e9d3 4702 ldrd r4, r7, [r3, #8] +10020bcc: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10020bd0: bf08 it eq +10020bd2: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10020bd6: d00e beq.n 10020bf6 +10020bd8: eb05 018b add.w r1, r5, fp, lsl #2 +10020bdc: 6aab ldr r3, [r5, #40] @ 0x28 +10020bde: 690a ldr r2, [r1, #16] +10020be0: 1ad2 subs r2, r2, r3 +10020be2: 1ae3 subs r3, r4, r3 +10020be4: 4293 cmp r3, r2 +10020be6: d305 bcc.n 10020bf4 +10020be8: 2301 movs r3, #1 +10020bea: 6a2a ldr r2, [r5, #32] +10020bec: fa03 f30b lsl.w r3, r3, fp +10020bf0: 4213 tst r3, r2 +10020bf2: d100 bne.n 10020bf6 +10020bf4: 610c str r4, [r1, #16] +10020bf6: 4628 mov r0, r5 +10020bf8: f000 fb38 bl 1002126c +10020bfc: 42a0 cmp r0, r4 +10020bfe: 41b9 sbcs r1, r7 +10020c00: f2c0 80fb blt.w 10020dfa +10020c04: f9b6 3008 ldrsh.w r3, [r6, #8] +10020c08: 9a01 ldr r2, [sp, #4] +10020c0a: 2b00 cmp r3, #0 +10020c0c: 9300 str r3, [sp, #0] +10020c0e: 63ea str r2, [r5, #60] @ 0x3c +10020c10: dbc8 blt.n 10020ba4 +10020c12: f8d6 8014 ldr.w r8, [r6, #20] +10020c16: eb03 0943 add.w r9, r3, r3, lsl #1 +10020c1a: 4628 mov r0, r5 +10020c1c: eb08 07c9 add.w r7, r8, r9, lsl #3 +10020c20: e9d7 4a02 ldrd r4, sl, [r7, #8] +10020c24: f000 fb22 bl 1002126c +10020c28: 42a0 cmp r0, r4 +10020c2a: eb71 010a sbcs.w r1, r1, sl +10020c2e: dbb9 blt.n 10020ba4 +10020c30: f1ba 0f00 cmp.w sl, #0 +10020c34: f2c0 80c3 blt.w 10020dbe +10020c38: e9d7 3104 ldrd r3, r1, [r7, #16] +10020c3c: 4a83 ldr r2, [pc, #524] @ (10020e4c ) +10020c3e: 4293 cmp r3, r2 +10020c40: f000 80ed beq.w 10020e1e +10020c44: 887a ldrh r2, [r7, #2] +10020c46: f9b6 0008 ldrsh.w r0, [r6, #8] +10020c4a: b292 uxth r2, r2 +10020c4c: ea42 4000 orr.w r0, r2, r0, lsl #16 +10020c50: 4798 blx r3 +10020c52: 4602 mov r2, r0 +10020c54: 460b mov r3, r1 +10020c56: ea52 0103 orrs.w r1, r2, r3 +10020c5a: f000 80b0 beq.w 10020dbe +10020c5e: 2b00 cmp r3, #0 +10020c60: f280 80d1 bge.w 10020e06 +10020c64: ebb4 0e02 subs.w lr, r4, r2 +10020c68: eb6a 0a03 sbc.w sl, sl, r3 +10020c6c: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10020c70: e9c7 ea02 strd lr, sl, [r7, #8] +10020c74: 2b00 cmp r3, #0 +10020c76: db95 blt.n 10020ba4 +10020c78: 6971 ldr r1, [r6, #20] +10020c7a: eb03 0243 add.w r2, r3, r3, lsl #1 +10020c7e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10020c82: e9d2 7002 ldrd r7, r0, [r2, #8] +10020c86: 45be cmp lr, r7 +10020c88: eb7a 0c00 sbcs.w ip, sl, r0 +10020c8c: ea4f 0243 mov.w r2, r3, lsl #1 +10020c90: db88 blt.n 10020ba4 +10020c92: 46b4 mov ip, r6 +10020c94: f82c 3f08 strh.w r3, [ip, #8]! +10020c98: e006 b.n 10020ca8 +10020c9a: eb03 0043 add.w r0, r3, r3, lsl #1 +10020c9e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10020ca2: 005a lsls r2, r3, #1 +10020ca4: e9d0 7002 ldrd r7, r0, [r0, #8] +10020ca8: 45be cmp lr, r7 +10020caa: 441a add r2, r3 +10020cac: eb7a 0000 sbcs.w r0, sl, r0 +10020cb0: eb01 04c2 add.w r4, r1, r2, lsl #3 +10020cb4: db04 blt.n 10020cc0 +10020cb6: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10020cba: 46a4 mov ip, r4 +10020cbc: 2b00 cmp r3, #0 +10020cbe: daec bge.n 10020c9a +10020cc0: f828 3039 strh.w r3, [r8, r9, lsl #3] +10020cc4: 9b00 ldr r3, [sp, #0] +10020cc6: f8ac 3000 strh.w r3, [ip] +10020cca: 88b3 ldrh r3, [r6, #4] +10020ccc: 041c lsls r4, r3, #16 +10020cce: f53f af6d bmi.w 10020bac +10020cd2: 6933 ldr r3, [r6, #16] +10020cd4: f3ef 8210 mrs r2, PRIMASK +10020cd8: b672 cpsid i +10020cda: e8d3 0fcf ldaexb r0, [r3] +10020cde: 2101 movs r1, #1 +10020ce0: 2800 cmp r0, #0 +10020ce2: d1fa bne.n 10020cda +10020ce4: e8c3 1f40 strexb r0, r1, [r3] +10020ce8: 2800 cmp r0, #0 +10020cea: d1f6 bne.n 10020cda +10020cec: f3bf 8f5f dmb sy +10020cf0: f64f 74ff movw r4, #65535 @ 0xffff +10020cf4: 88b0 ldrh r0, [r6, #4] +10020cf6: 2300 movs r3, #0 +10020cf8: 6931 ldr r1, [r6, #16] +10020cfa: b200 sxth r0, r0 +10020cfc: 80b4 strh r4, [r6, #4] +10020cfe: e8c1 3f8f stlb r3, [r1] +10020d02: f382 8810 msr PRIMASK, r2 +10020d06: 4298 cmp r0, r3 +10020d08: f6ff af50 blt.w 10020bac +10020d0c: 4607 mov r7, r0 +10020d0e: 46a9 mov r9, r5 +10020d10: 6974 ldr r4, [r6, #20] +10020d12: f106 0808 add.w r8, r6, #8 +10020d16: eb07 0e47 add.w lr, r7, r7, lsl #1 +10020d1a: eb04 03ce add.w r3, r4, lr, lsl #3 +10020d1e: e9d3 5002 ldrd r5, r0, [r3, #8] +10020d22: f9b6 3008 ldrsh.w r3, [r6, #8] +10020d26: 46c4 mov ip, r8 +10020d28: 2b00 cmp r3, #0 +10020d2a: db13 blt.n 10020d54 +10020d2c: 46b2 mov sl, r6 +10020d2e: 9700 str r7, [sp, #0] +10020d30: e004 b.n 10020d3c +10020d32: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10020d36: 4694 mov ip, r2 +10020d38: 2b00 cmp r3, #0 +10020d3a: db09 blt.n 10020d50 +10020d3c: eb03 0643 add.w r6, r3, r3, lsl #1 +10020d40: eb04 02c6 add.w r2, r4, r6, lsl #3 +10020d44: e9d2 7102 ldrd r7, r1, [r2, #8] +10020d48: 42bd cmp r5, r7 +10020d4a: eb70 0101 sbcs.w r1, r0, r1 +10020d4e: daf0 bge.n 10020d32 +10020d50: 4656 mov r6, sl +10020d52: 9f00 ldr r7, [sp, #0] +10020d54: f8ac 7000 strh.w r7, [ip] +10020d58: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10020d5c: f824 303e strh.w r3, [r4, lr, lsl #3] +10020d60: 2f00 cmp r7, #0 +10020d62: dad8 bge.n 10020d16 +10020d64: 79b3 ldrb r3, [r6, #6] +10020d66: 464d mov r5, r9 +10020d68: 2b00 cmp r3, #0 +10020d6a: f43f af23 beq.w 10020bb4 +10020d6e: 2300 movs r3, #0 +10020d70: 71b3 strb r3, [r6, #6] +10020d72: f9b6 3008 ldrsh.w r3, [r6, #8] +10020d76: f106 0808 add.w r8, r6, #8 +10020d7a: 1c58 adds r0, r3, #1 +10020d7c: d03d beq.n 10020dfa +10020d7e: 461a mov r2, r3 +10020d80: 6977 ldr r7, [r6, #20] +10020d82: e003 b.n 10020d8c +10020d84: 4680 mov r8, r0 +10020d86: 1c59 adds r1, r3, #1 +10020d88: f43f af16 beq.w 10020bb8 +10020d8c: eb03 0143 add.w r1, r3, r3, lsl #1 +10020d90: eb07 00c1 add.w r0, r7, r1, lsl #3 +10020d94: f8b0 c002 ldrh.w ip, [r0, #2] +10020d98: 461c mov r4, r3 +10020d9a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10020d9e: 469e mov lr, r3 +10020da0: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10020da4: d0ee beq.n 10020d84 +10020da6: 4294 cmp r4, r2 +10020da8: ed80 8b02 vstr d8, [r0, #8] +10020dac: d005 beq.n 10020dba +10020dae: f8a8 3000 strh.w r3, [r8] +10020db2: 8932 ldrh r2, [r6, #8] +10020db4: f827 2031 strh.w r2, [r7, r1, lsl #3] +10020db8: 8134 strh r4, [r6, #8] +10020dba: 4672 mov r2, lr +10020dbc: e7e3 b.n 10020d86 +10020dbe: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10020dc2: 8133 strh r3, [r6, #8] +10020dc4: 6933 ldr r3, [r6, #16] +10020dc6: f3ef 8210 mrs r2, PRIMASK +10020dca: b672 cpsid i +10020dcc: e8d3 0fcf ldaexb r0, [r3] +10020dd0: 2101 movs r1, #1 +10020dd2: 2800 cmp r0, #0 +10020dd4: d1fa bne.n 10020dcc +10020dd6: e8c3 1f40 strexb r0, r1, [r3] +10020dda: 2800 cmp r0, #0 +10020ddc: d1f6 bne.n 10020dcc +10020dde: f3bf 8f5f dmb sy +10020de2: 8873 ldrh r3, [r6, #2] +10020de4: 6931 ldr r1, [r6, #16] +10020de6: f828 3039 strh.w r3, [r8, r9, lsl #3] +10020dea: 9b00 ldr r3, [sp, #0] +10020dec: 8073 strh r3, [r6, #2] +10020dee: 2300 movs r3, #0 +10020df0: e8c1 3f8f stlb r3, [r1] +10020df4: f382 8810 msr PRIMASK, r2 +10020df8: e6d4 b.n 10020ba4 +10020dfa: bf40 sev +10020dfc: b005 add sp, #20 +10020dfe: ecbd 8b02 vpop {d8} +10020e02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10020e06: 4628 mov r0, r5 +10020e08: e9cd 2302 strd r2, r3, [sp, #8] +10020e0c: f000 fa2e bl 1002126c +10020e10: 9a02 ldr r2, [sp, #8] +10020e12: 9b03 ldr r3, [sp, #12] +10020e14: eb10 0e02 adds.w lr, r0, r2 +10020e18: eb43 0a01 adc.w sl, r3, r1 +10020e1c: e726 b.n 10020c6c +10020e1e: 4608 mov r0, r1 +10020e20: 690b ldr r3, [r1, #16] +10020e22: 9102 str r1, [sp, #8] +10020e24: 4798 blx r3 +10020e26: 2800 cmp r0, #0 +10020e28: d0c9 beq.n 10020dbe +10020e2a: 9902 ldr r1, [sp, #8] +10020e2c: e9d1 2300 ldrd r2, r3, [r1] +10020e30: e711 b.n 10020c56 +10020e32: bf00 nop +10020e34: f3af 8000 nop.w +10020e38: ffffffff .word 0xffffffff +10020e3c: ffffffff .word 0xffffffff +10020e40: 400b8000 .word 0x400b8000 +10020e44: 20002a58 .word 0x20002a58 +10020e48: 400b0000 .word 0x400b0000 +10020e4c: 10020b61 .word 0x10020b61 + +10020e50 : +10020e50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10020e54: 4c36 ldr r4, [pc, #216] @ (10020f30 ) +10020e56: 6925 ldr r5, [r4, #16] +10020e58: b12d cbz r5, 10020e66 +10020e5a: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10020e5e: 210a movs r1, #10 +10020e60: 4834 ldr r0, [pc, #208] @ (10020f34 ) +10020e62: f7ff be31 b.w 10020ac8 +10020e66: f8df 80e4 ldr.w r8, [pc, #228] @ 10020f4c +10020e6a: 2103 movs r1, #3 +10020e6c: 4640 mov r0, r8 +10020e6e: f000 f9eb bl 10021248 +10020e72: 2603 movs r6, #3 +10020e74: f8c4 800c str.w r8, [r4, #12] +10020e78: f7ff fc48 bl 1002070c +10020e7c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10020e80: 4b2d ldr r3, [pc, #180] @ (10020f38 ) +10020e82: 7026 strb r6, [r4, #0] +10020e84: 4403 add r3, r0 +10020e86: 6123 str r3, [r4, #16] +10020e88: f8dc 3000 ldr.w r3, [ip] +10020e8c: 210f movs r1, #15 +10020e8e: 7063 strb r3, [r4, #1] +10020e90: 6963 ldr r3, [r4, #20] +10020e92: 8061 strh r1, [r4, #2] +10020e94: 831d strh r5, [r3, #24] +10020e96: f04f 0504 mov.w r5, #4 +10020e9a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10020e9e: f04f 0505 mov.w r5, #5 +10020ea2: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10020ea6: f04f 0506 mov.w r5, #6 +10020eaa: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10020eae: f04f 0507 mov.w r5, #7 +10020eb2: 210e movs r1, #14 +10020eb4: f64f 72ff movw r2, #65535 @ 0xffff +10020eb8: 2708 movs r7, #8 +10020eba: f04f 0e0a mov.w lr, #10 +10020ebe: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10020ec2: f04f 0901 mov.w r9, #1 +10020ec6: f04f 0c0c mov.w ip, #12 +10020eca: f04f 0b02 mov.w fp, #2 +10020ece: f04f 0a09 mov.w sl, #9 +10020ed2: 200d movs r0, #13 +10020ed4: f04f 050b mov.w r5, #11 +10020ed8: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10020edc: 4917 ldr r1, [pc, #92] @ (10020f3c ) +10020ede: 80a2 strh r2, [r4, #4] +10020ee0: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10020ee4: 60a1 str r1, [r4, #8] +10020ee6: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10020eea: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10020eee: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10020ef2: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10020ef6: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10020efa: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10020efe: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10020f02: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10020f06: 801a strh r2, [r3, #0] +10020f08: 4b0d ldr r3, [pc, #52] @ (10020f40 ) +10020f0a: 4630 mov r0, r6 +10020f0c: f8c8 7020 str.w r7, [r8, #32] +10020f10: 490c ldr r1, [pc, #48] @ (10020f44 ) +10020f12: 60dc str r4, [r3, #12] +10020f14: f7ff fc50 bl 100207b8 +10020f18: 4649 mov r1, r9 +10020f1a: 4630 mov r0, r6 +10020f1c: f7ff fc36 bl 1002078c +10020f20: 4b09 ldr r3, [pc, #36] @ (10020f48 ) +10020f22: 210a movs r1, #10 +10020f24: 641f str r7, [r3, #64] @ 0x40 +10020f26: 4803 ldr r0, [pc, #12] @ (10020f34 ) +10020f28: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10020f2c: f7ff bdcc b.w 10020ac8 +10020f30: 200005f4 .word 0x200005f4 +10020f34: 20002a80 .word 0x20002a80 +10020f38: 200029d8 .word 0x200029d8 +10020f3c: 0010ffff .word 0x0010ffff +10020f40: 20002a58 .word 0x20002a58 +10020f44: 10020b61 .word 0x10020b61 +10020f48: 400b2000 .word 0x400b2000 +10020f4c: 400b0000 .word 0x400b0000 + +10020f50 : +10020f50: 4601 mov r1, r0 +10020f52: b5f0 push {r4, r5, r6, r7, lr} +10020f54: 6900 ldr r0, [r0, #16] +10020f56: f3ef 8710 mrs r7, PRIMASK +10020f5a: b672 cpsid i +10020f5c: e8d0 5fcf ldaexb r5, [r0] +10020f60: 2401 movs r4, #1 +10020f62: 2d00 cmp r5, #0 +10020f64: d1fa bne.n 10020f5c +10020f66: e8c0 4f45 strexb r5, r4, [r0] +10020f6a: 2d00 cmp r5, #0 +10020f6c: d1f6 bne.n 10020f5c +10020f6e: f3bf 8f5f dmb sy +10020f72: f9b1 e002 ldrsh.w lr, [r1, #2] +10020f76: 694c ldr r4, [r1, #20] +10020f78: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10020f7c: f1be 0f00 cmp.w lr, #0 +10020f80: ea4f 05cc mov.w r5, ip, lsl #3 +10020f84: 6908 ldr r0, [r1, #16] +10020f86: eb04 0ccc add.w ip, r4, ip, lsl #3 +10020f8a: db3c blt.n 10021006 +10020f8c: 5b66 ldrh r6, [r4, r5] +10020f8e: 804e strh r6, [r1, #2] +10020f90: 2600 movs r6, #0 +10020f92: e8c0 6f8f stlb r6, [r0] +10020f96: f387 8810 msr PRIMASK, r7 +10020f9a: f8bc 0002 ldrh.w r0, [ip, #2] +10020f9e: e9cc 2302 strd r2, r3, [ip, #8] +10020fa2: 3001 adds r0, #1 +10020fa4: f3c0 000e ubfx r0, r0, #0, #15 +10020fa8: 2801 cmp r0, #1 +10020faa: bf38 it cc +10020fac: 2001 movcc r0, #1 +10020fae: 9b05 ldr r3, [sp, #20] +10020fb0: f8ac 0002 strh.w r0, [ip, #2] +10020fb4: f8cc 3010 str.w r3, [ip, #16] +10020fb8: 9b06 ldr r3, [sp, #24] +10020fba: ea40 400e orr.w r0, r0, lr, lsl #16 +10020fbe: f8cc 3014 str.w r3, [ip, #20] +10020fc2: 690b ldr r3, [r1, #16] +10020fc4: f3ef 8210 mrs r2, PRIMASK +10020fc8: b672 cpsid i +10020fca: e8d3 cfcf ldaexb ip, [r3] +10020fce: 2701 movs r7, #1 +10020fd0: f1bc 0f00 cmp.w ip, #0 +10020fd4: d1f9 bne.n 10020fca +10020fd6: e8c3 7f4c strexb ip, r7, [r3] +10020fda: f1bc 0f00 cmp.w ip, #0 +10020fde: d1f4 bne.n 10020fca +10020fe0: f3bf 8f5f dmb sy +10020fe4: 888b ldrh r3, [r1, #4] +10020fe6: 5363 strh r3, [r4, r5] +10020fe8: f8a1 e004 strh.w lr, [r1, #4] +10020fec: 690b ldr r3, [r1, #16] +10020fee: e8c3 6f8f stlb r6, [r3] +10020ff2: f382 8810 msr PRIMASK, r2 +10020ff6: 2201 movs r2, #1 +10020ff8: 68cb ldr r3, [r1, #12] +10020ffa: 7809 ldrb r1, [r1, #0] +10020ffc: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10021000: 408a lsls r2, r1 +10021002: 605a str r2, [r3, #4] +10021004: bdf0 pop {r4, r5, r6, r7, pc} +10021006: 2300 movs r3, #0 +10021008: e8c0 3f8f stlb r3, [r0] +1002100c: f387 8810 msr PRIMASK, r7 +10021010: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10021014: bdf0 pop {r4, r5, r6, r7, pc} +10021016: bf00 nop + +10021018 : +10021018: 4603 mov r3, r0 +1002101a: 8940 ldrh r0, [r0, #10] +1002101c: ebb0 4f21 cmp.w r0, r1, asr #16 +10021020: dd37 ble.n 10021092 +10021022: 6958 ldr r0, [r3, #20] +10021024: 140a asrs r2, r1, #16 +10021026: eb02 0242 add.w r2, r2, r2, lsl #1 +1002102a: b510 push {r4, lr} +1002102c: eb00 00c2 add.w r0, r0, r2, lsl #3 +10021030: 691c ldr r4, [r3, #16] +10021032: f3ef 8c10 mrs ip, PRIMASK +10021036: b672 cpsid i +10021038: e8d4 efcf ldaexb lr, [r4] +1002103c: 2201 movs r2, #1 +1002103e: f1be 0f00 cmp.w lr, #0 +10021042: d1f9 bne.n 10021038 +10021044: e8c4 2f4e strexb lr, r2, [r4] +10021048: f1be 0f00 cmp.w lr, #0 +1002104c: d1f4 bne.n 10021038 +1002104e: f3bf 8f5f dmb sy +10021052: 8842 ldrh r2, [r0, #2] +10021054: b289 uxth r1, r1 +10021056: b292 uxth r2, r2 +10021058: 428a cmp r2, r1 +1002105a: d007 beq.n 1002106c +1002105c: 2200 movs r2, #0 +1002105e: 691b ldr r3, [r3, #16] +10021060: e8c3 2f8f stlb r2, [r3] +10021064: f38c 8810 msr PRIMASK, ip +10021068: 2000 movs r0, #0 +1002106a: bd10 pop {r4, pc} +1002106c: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10021070: 8042 strh r2, [r0, #2] +10021072: 2101 movs r1, #1 +10021074: 2200 movs r2, #0 +10021076: 6918 ldr r0, [r3, #16] +10021078: 7199 strb r1, [r3, #6] +1002107a: e8c0 2f8f stlb r2, [r0] +1002107e: f38c 8810 msr PRIMASK, ip +10021082: 781c ldrb r4, [r3, #0] +10021084: 68da ldr r2, [r3, #12] +10021086: 4608 mov r0, r1 +10021088: f502 5301 add.w r3, r2, #8256 @ 0x2040 +1002108c: 40a1 lsls r1, r4 +1002108e: 6059 str r1, [r3, #4] +10021090: bd10 pop {r4, pc} +10021092: 2000 movs r0, #0 +10021094: 4770 bx lr +10021096: bf00 nop + +10021098 : +10021098: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1002109c: b082 sub sp, #8 +1002109e: 4606 mov r6, r0 +100210a0: f000 f8ec bl 1002127c +100210a4: f44f 737a mov.w r3, #1000 @ 0x3e8 +100210a8: 4604 mov r4, r0 +100210aa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +100210ae: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +100210b2: fbe6 4103 umlal r4, r1, r6, r3 +100210b6: 42a0 cmp r0, r4 +100210b8: eb72 0301 sbcs.w r3, r2, r1 +100210bc: bf3a itte cc +100210be: 4604 movcc r4, r0 +100210c0: 4615 movcc r5, r2 +100210c2: 460d movcs r5, r1 +100210c4: 1fa6 subs r6, r4, #6 +100210c6: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +100210ca: 42b4 cmp r4, r6 +100210cc: eb75 0307 sbcs.w r3, r5, r7 +100210d0: bf3c itt cc +100210d2: 2600 movcc r6, #0 +100210d4: 4637 movcc r7, r6 +100210d6: f000 f8d1 bl 1002127c +100210da: 1a30 subs r0, r6, r0 +100210dc: eb67 0101 sbc.w r1, r7, r1 +100210e0: 2801 cmp r0, #1 +100210e2: f171 0100 sbcs.w r1, r1, #0 +100210e6: da06 bge.n 100210f6 +100210e8: 4620 mov r0, r4 +100210ea: 4629 mov r1, r5 +100210ec: b002 add sp, #8 +100210ee: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100210f2: f000 b8fb b.w 100212ec +100210f6: f000 f8c1 bl 1002127c +100210fa: 4286 cmp r6, r0 +100210fc: eb67 0101 sbc.w r1, r7, r1 +10021100: 2900 cmp r1, #0 +10021102: db0a blt.n 1002111a +10021104: 2100 movs r1, #0 +10021106: 4b17 ldr r3, [pc, #92] @ (10021164 ) +10021108: 4632 mov r2, r6 +1002110a: 9300 str r3, [sp, #0] +1002110c: 4816 ldr r0, [pc, #88] @ (10021168 ) +1002110e: 463b mov r3, r7 +10021110: 9101 str r1, [sp, #4] +10021112: f7ff ff1d bl 10020f50 +10021116: 3001 adds r0, #1 +10021118: d0e6 beq.n 100210e8 +1002111a: f04f 0c00 mov.w ip, #0 +1002111e: 4a13 ldr r2, [pc, #76] @ (1002116c ) +10021120: 4913 ldr r1, [pc, #76] @ (10021170 ) +10021122: 6a53 ldr r3, [r2, #36] @ 0x24 +10021124: 429f cmp r7, r3 +10021126: d804 bhi.n 10021132 +10021128: 6a90 ldr r0, [r2, #40] @ 0x28 +1002112a: 42b0 cmp r0, r6 +1002112c: d2dc bcs.n 100210e8 +1002112e: 429f cmp r7, r3 +10021130: d1da bne.n 100210e8 +10021132: 680b ldr r3, [r1, #0] +10021134: f3ef 8010 mrs r0, PRIMASK +10021138: b672 cpsid i +1002113a: e8d3 8fcf ldaexb r8, [r3] +1002113e: f05f 0e01 movs.w lr, #1 +10021142: f1b8 0f00 cmp.w r8, #0 +10021146: d1f8 bne.n 1002113a +10021148: e8c3 ef48 strexb r8, lr, [r3] +1002114c: f1b8 0f00 cmp.w r8, #0 +10021150: d1f3 bne.n 1002113a +10021152: f3bf 8f5f dmb sy +10021156: 680b ldr r3, [r1, #0] +10021158: e8c3 cf8f stlb ip, [r3] +1002115c: f380 8810 msr PRIMASK, r0 +10021160: bf20 wfe +10021162: e7de b.n 10021122 +10021164: 10020b21 .word 0x10020b21 +10021168: 200005f4 .word 0x200005f4 +1002116c: 400b0000 .word 0x400b0000 +10021170: 20002a80 .word 0x20002a80 + +10021174 : +10021174: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10021178: 4606 mov r6, r0 +1002117a: 460d mov r5, r1 +1002117c: b083 sub sp, #12 +1002117e: f3ef 8405 mrs r4, IPSR +10021182: b2e4 uxtb r4, r4 +10021184: b13c cbz r4, 10021196 +10021186: 4b2d ldr r3, [pc, #180] @ (1002123c ) +10021188: 6a5a ldr r2, [r3, #36] @ 0x24 +1002118a: 42aa cmp r2, r5 +1002118c: d21c bcs.n 100211c8 +1002118e: 2000 movs r0, #0 +10021190: b003 add sp, #12 +10021192: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10021196: 4f2a ldr r7, [pc, #168] @ (10021240 ) +10021198: f8d7 900c ldr.w r9, [r7, #12] +1002119c: f897 8000 ldrb.w r8, [r7] +100211a0: 4648 mov r0, r9 +100211a2: f000 f863 bl 1002126c +100211a6: f108 0804 add.w r8, r8, #4 +100211aa: f859 3028 ldr.w r3, [r9, r8, lsl #2] +100211ae: 1a1b subs r3, r3, r0 +100211b0: 1a30 subs r0, r6, r0 +100211b2: eb65 0101 sbc.w r1, r5, r1 +100211b6: 4298 cmp r0, r3 +100211b8: f171 0100 sbcs.w r1, r1, #0 +100211bc: db10 blt.n 100211e0 +100211be: bf20 wfe +100211c0: 4b1e ldr r3, [pc, #120] @ (1002123c ) +100211c2: 6a5a ldr r2, [r3, #36] @ 0x24 +100211c4: 42aa cmp r2, r5 +100211c6: d3e2 bcc.n 1002118e +100211c8: bf14 ite ne +100211ca: 2401 movne r4, #1 +100211cc: 2400 moveq r4, #0 +100211ce: 6a9b ldr r3, [r3, #40] @ 0x28 +100211d0: 42b3 cmp r3, r6 +100211d2: bf34 ite cc +100211d4: 4620 movcc r0, r4 +100211d6: f044 0001 orrcs.w r0, r4, #1 +100211da: b003 add sp, #12 +100211dc: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +100211e0: f000 f84c bl 1002127c +100211e4: 4286 cmp r6, r0 +100211e6: eb65 0101 sbc.w r1, r5, r1 +100211ea: 2900 cmp r1, #0 +100211ec: db14 blt.n 10021218 +100211ee: 4b15 ldr r3, [pc, #84] @ (10021244 ) +100211f0: 4638 mov r0, r7 +100211f2: e9cd 3400 strd r3, r4, [sp] +100211f6: 4632 mov r2, r6 +100211f8: 462b mov r3, r5 +100211fa: f7ff fea9 bl 10020f50 +100211fe: 1e01 subs r1, r0, #0 +10021200: dd0a ble.n 10021218 +10021202: 4b0e ldr r3, [pc, #56] @ (1002123c ) +10021204: 6a5a ldr r2, [r3, #36] @ 0x24 +10021206: 42aa cmp r2, r5 +10021208: d316 bcc.n 10021238 +1002120a: 6a9b ldr r3, [r3, #40] @ 0x28 +1002120c: 42b3 cmp r3, r6 +1002120e: d311 bcc.n 10021234 +10021210: 480b ldr r0, [pc, #44] @ (10021240 ) +10021212: f7ff ff01 bl 10021018 +10021216: e7b6 b.n 10021186 +10021218: 4b08 ldr r3, [pc, #32] @ (1002123c ) +1002121a: 6a5c ldr r4, [r3, #36] @ 0x24 +1002121c: 42ac cmp r4, r5 +1002121e: d3b6 bcc.n 1002118e +10021220: 1b64 subs r4, r4, r5 +10021222: bf18 it ne +10021224: 2401 movne r4, #1 +10021226: 6a9b ldr r3, [r3, #40] @ 0x28 +10021228: 42b3 cmp r3, r6 +1002122a: bf34 ite cc +1002122c: 4620 movcc r0, r4 +1002122e: f044 0001 orrcs.w r0, r4, #1 +10021232: e7ad b.n 10021190 +10021234: 42aa cmp r2, r5 +10021236: d1eb bne.n 10021210 +10021238: bf20 wfe +1002123a: e7e9 b.n 10021210 +1002123c: 400b0000 .word 0x400b0000 +10021240: 200005f4 .word 0x200005f4 +10021244: 10020b21 .word 0x10020b21 + +10021248 : +10021248: b410 push {r4} +1002124a: 4b05 ldr r3, [pc, #20] @ (10021260 ) +1002124c: 4c05 ldr r4, [pc, #20] @ (10021264 ) +1002124e: 4a06 ldr r2, [pc, #24] @ (10021268 ) +10021250: 42a0 cmp r0, r4 +10021252: bf14 ite ne +10021254: 4618 movne r0, r3 +10021256: 1c58 addeq r0, r3, #1 +10021258: f85d 4b04 ldr.w r4, [sp], #4 +1002125c: f7ff ba2a b.w 100206b4 +10021260: 20002a04 .word 0x20002a04 +10021264: 400b8000 .word 0x400b8000 +10021268: 10024dc4 .word 0x10024dc4 + +1002126c : +1002126c: 4603 mov r3, r0 +1002126e: 6a41 ldr r1, [r0, #36] @ 0x24 +10021270: 460a mov r2, r1 +10021272: 6a98 ldr r0, [r3, #40] @ 0x28 +10021274: 6a59 ldr r1, [r3, #36] @ 0x24 +10021276: 428a cmp r2, r1 +10021278: d1fa bne.n 10021270 +1002127a: 4770 bx lr + +1002127c : +1002127c: 4b03 ldr r3, [pc, #12] @ (1002128c ) +1002127e: 6a59 ldr r1, [r3, #36] @ 0x24 +10021280: 460a mov r2, r1 +10021282: 6a98 ldr r0, [r3, #40] @ 0x28 +10021284: 6a59 ldr r1, [r3, #36] @ 0x24 +10021286: 4291 cmp r1, r2 +10021288: d1fa bne.n 10021280 +1002128a: 4770 bx lr +1002128c: 400b0000 .word 0x400b0000 + +10021290 : +10021290: b430 push {r4, r5} +10021292: 4a15 ldr r2, [pc, #84] @ (100212e8 ) +10021294: 6a53 ldr r3, [r2, #36] @ 0x24 +10021296: 469c mov ip, r3 +10021298: 6a94 ldr r4, [r2, #40] @ 0x28 +1002129a: 6a53 ldr r3, [r2, #36] @ 0x24 +1002129c: 4563 cmp r3, ip +1002129e: d1fa bne.n 10021296 +100212a0: 1902 adds r2, r0, r4 +100212a2: 4159 adcs r1, r3 +100212a4: f04f 0500 mov.w r5, #0 +100212a8: bf28 it cs +100212aa: 2501 movcs r5, #1 +100212ac: 4b0e ldr r3, [pc, #56] @ (100212e8 ) +100212ae: 6a5b ldr r3, [r3, #36] @ 0x24 +100212b0: b1b5 cbz r5, 100212e0 +100212b2: 1c5a adds r2, r3, #1 +100212b4: bf08 it eq +100212b6: 461a moveq r2, r3 +100212b8: d008 beq.n 100212cc +100212ba: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +100212be: 460a mov r2, r1 +100212c0: 4809 ldr r0, [pc, #36] @ (100212e8 ) +100212c2: 6a43 ldr r3, [r0, #36] @ 0x24 +100212c4: 428b cmp r3, r1 +100212c6: d3fc bcc.n 100212c2 +100212c8: 428b cmp r3, r1 +100212ca: d107 bne.n 100212dc +100212cc: 4906 ldr r1, [pc, #24] @ (100212e8 ) +100212ce: e002 b.n 100212d6 +100212d0: 6a48 ldr r0, [r1, #36] @ 0x24 +100212d2: 4298 cmp r0, r3 +100212d4: d102 bne.n 100212dc +100212d6: 6a88 ldr r0, [r1, #40] @ 0x28 +100212d8: 4290 cmp r0, r2 +100212da: d3f9 bcc.n 100212d0 +100212dc: bc30 pop {r4, r5} +100212de: 4770 bx lr +100212e0: 4299 cmp r1, r3 +100212e2: d8ed bhi.n 100212c0 +100212e4: e7f0 b.n 100212c8 +100212e6: bf00 nop +100212e8: 400b0000 .word 0x400b0000 + +100212ec : +100212ec: 4a07 ldr r2, [pc, #28] @ (1002130c ) +100212ee: 6a53 ldr r3, [r2, #36] @ 0x24 +100212f0: 4299 cmp r1, r3 +100212f2: d8fc bhi.n 100212ee +100212f4: 4299 cmp r1, r3 +100212f6: d107 bne.n 10021308 +100212f8: 4b04 ldr r3, [pc, #16] @ (1002130c ) +100212fa: e002 b.n 10021302 +100212fc: 6a5a ldr r2, [r3, #36] @ 0x24 +100212fe: 4291 cmp r1, r2 +10021300: d102 bne.n 10021308 +10021302: 6a9a ldr r2, [r3, #40] @ 0x28 +10021304: 4290 cmp r0, r2 +10021306: d8f9 bhi.n 100212fc +10021308: 4770 bx lr +1002130a: bf00 nop +1002130c: 400b0000 .word 0x400b0000 + +10021310 : +10021310: b5f8 push {r3, r4, r5, r6, r7, lr} +10021312: 4605 mov r5, r0 +10021314: 2006 movs r0, #6 +10021316: 460e mov r6, r1 +10021318: f000 f8e4 bl 100214e4 +1002131c: 2800 cmp r0, #0 +1002131e: d042 beq.n 100213a6 +10021320: 4a35 ldr r2, [pc, #212] @ (100213f8 ) +10021322: 4836 ldr r0, [pc, #216] @ (100213fc ) +10021324: 4295 cmp r5, r2 +10021326: bf14 ite ne +10021328: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +1002132c: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +10021330: 4b33 ldr r3, [pc, #204] @ (10021400 ) +10021332: 4934 ldr r1, [pc, #208] @ (10021404 ) +10021334: 6002 str r2, [r0, #0] +10021336: 601a str r2, [r3, #0] +10021338: 688c ldr r4, [r1, #8] +1002133a: ea32 0404 bics.w r4, r2, r4 +1002133e: d1fb bne.n 10021338 +10021340: 4b2d ldr r3, [pc, #180] @ (100213f8 ) +10021342: f44f 7180 mov.w r1, #256 @ 0x100 +10021346: 1aeb subs r3, r5, r3 +10021348: fab3 f383 clz r3, r3 +1002134c: 4a2e ldr r2, [pc, #184] @ (10021408 ) +1002134e: 095b lsrs r3, r3, #5 +10021350: 2006 movs r0, #6 +10021352: f822 1013 strh.w r1, [r2, r3, lsl #1] +10021356: f000 f8c5 bl 100214e4 +1002135a: 00c3 lsls r3, r0, #3 +1002135c: fbb3 f3f6 udiv r3, r3, r6 +10021360: 3301 adds r3, #1 +10021362: 09da lsrs r2, r3, #7 +10021364: d120 bne.n 100213a8 +10021366: 2640 movs r6, #64 @ 0x40 +10021368: 2101 movs r1, #1 +1002136a: 6269 str r1, [r5, #36] @ 0x24 +1002136c: 62aa str r2, [r5, #40] @ 0x28 +1002136e: 6b2f ldr r7, [r5, #48] @ 0x30 +10021370: 07fb lsls r3, r7, #31 +10021372: d422 bmi.n 100213ba +10021374: 462b mov r3, r5 +10021376: 2200 movs r2, #0 +10021378: f853 1f2c ldr.w r1, [r3, #44]! +1002137c: 2006 movs r0, #6 +1002137e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10021382: 6022 str r2, [r4, #0] +10021384: 632f str r7, [r5, #48] @ 0x30 +10021386: f000 f8ad bl 100214e4 +1002138a: f240 3101 movw r1, #769 @ 0x301 +1002138e: 2203 movs r2, #3 +10021390: 0080 lsls r0, r0, #2 +10021392: fbb0 f0f6 udiv r0, r0, r6 +10021396: 6aeb ldr r3, [r5, #44] @ 0x2c +10021398: f083 0370 eor.w r3, r3, #112 @ 0x70 +1002139c: f003 037e and.w r3, r3, #126 @ 0x7e +100213a0: 6023 str r3, [r4, #0] +100213a2: 6329 str r1, [r5, #48] @ 0x30 +100213a4: 64aa str r2, [r5, #72] @ 0x48 +100213a6: bdf8 pop {r3, r4, r5, r6, r7, pc} +100213a8: f64f 71fe movw r1, #65534 @ 0xfffe +100213ac: 428a cmp r2, r1 +100213ae: d91b bls.n 100213e8 +100213b0: 4622 mov r2, r4 +100213b2: f64f 71ff movw r1, #65535 @ 0xffff +100213b6: 4e15 ldr r6, [pc, #84] @ (1002140c ) +100213b8: e7d7 b.n 1002136a +100213ba: f240 3201 movw r2, #769 @ 0x301 +100213be: f505 5340 add.w r3, r5, #12288 @ 0x3000 +100213c2: 631a str r2, [r3, #48] @ 0x30 +100213c4: 6a6b ldr r3, [r5, #36] @ 0x24 +100213c6: 6aac ldr r4, [r5, #40] @ 0x28 +100213c8: 2006 movs r0, #6 +100213ca: eb04 1483 add.w r4, r4, r3, lsl #6 +100213ce: f000 f889 bl 100214e4 +100213d2: 4b0f ldr r3, [pc, #60] @ (10021410 ) +100213d4: 02a4 lsls r4, r4, #10 +100213d6: fba3 2300 umull r2, r3, r3, r0 +100213da: 0adb lsrs r3, r3, #11 +100213dc: 2100 movs r1, #0 +100213de: fbb4 f0f3 udiv r0, r4, r3 +100213e2: f7ff ff55 bl 10021290 +100213e6: e7c5 b.n 10021374 +100213e8: f3c3 0345 ubfx r3, r3, #1, #6 +100213ec: 4611 mov r1, r2 +100213ee: eb03 1682 add.w r6, r3, r2, lsl #6 +100213f2: 461a mov r2, r3 +100213f4: e7b9 b.n 1002136a +100213f6: bf00 nop +100213f8: 40078000 .word 0x40078000 +100213fc: 40022000 .word 0x40022000 +10021400: 40023000 .word 0x40023000 +10021404: 40020000 .word 0x40020000 +10021408: 20002a84 .word 0x20002a84 +1002140c: 003fffc0 .word 0x003fffc0 +10021410: 8f2b7b75 .word 0x8f2b7b75 + +10021414 : +10021414: eb00 0c40 add.w ip, r0, r0, lsl #1 +10021418: ea4f 0c8c mov.w ip, ip, lsl #2 +1002141c: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +10021420: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +10021424: b5f0 push {r4, r5, r6, r7, lr} +10021426: 4616 mov r6, r2 +10021428: f8dc 2004 ldr.w r2, [ip, #4] +1002142c: 1f05 subs r5, r0, #4 +1002142e: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +10021432: bf38 it cc +10021434: f44f 3280 movcc.w r2, #65536 @ 0x10000 +10021438: b2ed uxtb r5, r5 +1002143a: bf38 it cc +1002143c: f8cc 2004 strcc.w r2, [ip, #4] +10021440: 2d01 cmp r5, #1 +10021442: d92a bls.n 1002149a +10021444: f44f 6700 mov.w r7, #2048 @ 0x800 +10021448: 4c25 ldr r4, [pc, #148] @ (100214e0 ) +1002144a: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +1002144e: 6017 str r7, [r2, #0] +10021450: f854 2020 ldr.w r2, [r4, r0, lsl #2] +10021454: b9b2 cbnz r2, 10021484 +10021456: f8dc 2000 ldr.w r2, [ip] +1002145a: 2d01 cmp r5, #1 +1002145c: ea82 1246 eor.w r2, r2, r6, lsl #5 +10021460: f002 02e0 and.w r2, r2, #224 @ 0xe0 +10021464: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10021468: 6032 str r2, [r6, #0] +1002146a: d92a bls.n 100214c2 +1002146c: f44f 6100 mov.w r1, #2048 @ 0x800 +10021470: f844 3020 str.w r3, [r4, r0, lsl #2] +10021474: f44f 3380 mov.w r3, #65536 @ 0x10000 +10021478: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1002147c: 6011 str r1, [r2, #0] +1002147e: f8cc 3004 str.w r3, [ip, #4] +10021482: bdf0 pop {r4, r5, r6, r7, pc} +10021484: 6967 ldr r7, [r4, #20] +10021486: fbb7 fef2 udiv lr, r7, r2 +1002148a: f10e 0e01 add.w lr, lr, #1 +1002148e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10021492: f1be 0e03 subs.w lr, lr, #3 +10021496: d2fc bcs.n 10021492 +10021498: e7dd b.n 10021456 +1002149a: 2901 cmp r1, #1 +1002149c: d1d2 bne.n 10021444 +1002149e: 2403 movs r4, #3 +100214a0: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100214a4: 6014 str r4, [r2, #0] +100214a6: f8dc 2008 ldr.w r2, [ip, #8] +100214aa: 07d2 lsls r2, r2, #31 +100214ac: d5fb bpl.n 100214a6 +100214ae: f8dc 2000 ldr.w r2, [ip] +100214b2: 4c0b ldr r4, [pc, #44] @ (100214e0 ) +100214b4: ea82 1246 eor.w r2, r2, r6, lsl #5 +100214b8: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100214bc: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100214c0: 6032 str r2, [r6, #0] +100214c2: 2201 movs r2, #1 +100214c4: f8dc 5000 ldr.w r5, [ip] +100214c8: 404d eors r5, r1 +100214ca: f005 0503 and.w r5, r5, #3 +100214ce: 6035 str r5, [r6, #0] +100214d0: fa02 f101 lsl.w r1, r2, r1 +100214d4: f8dc 2008 ldr.w r2, [ip, #8] +100214d8: 420a tst r2, r1 +100214da: d0fb beq.n 100214d4 +100214dc: e7c6 b.n 1002146c +100214de: bf00 nop +100214e0: 20002a08 .word 0x20002a08 + +100214e4 : +100214e4: 4b01 ldr r3, [pc, #4] @ (100214ec ) +100214e6: f853 0020 ldr.w r0, [r3, r0, lsl #2] +100214ea: 4770 bx lr +100214ec: 20002a08 .word 0x20002a08 + +100214f0 : +100214f0: b470 push {r4, r5, r6} +100214f2: 9d03 ldr r5, [sp, #12] +100214f4: 6804 ldr r4, [r0, #0] +100214f6: 032d lsls r5, r5, #12 +100214f8: ea45 4503 orr.w r5, r5, r3, lsl #16 +100214fc: 4b1b ldr r3, [pc, #108] @ (1002156c ) +100214fe: 2c00 cmp r4, #0 +10021500: fbb3 f3f1 udiv r3, r3, r1 +10021504: fbb2 f6f3 udiv r6, r2, r3 +10021508: db1f blt.n 1002154a +1002150a: 4a19 ldr r2, [pc, #100] @ (10021570 ) +1002150c: 4b19 ldr r3, [pc, #100] @ (10021574 ) +1002150e: 4290 cmp r0, r2 +10021510: bf14 ite ne +10021512: f44f 4280 movne.w r2, #16384 @ 0x4000 +10021516: f44f 4200 moveq.w r2, #32768 @ 0x8000 +1002151a: 4c17 ldr r4, [pc, #92] @ (10021578 ) +1002151c: 601a str r2, [r3, #0] +1002151e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10021522: 601a str r2, [r3, #0] +10021524: 68a3 ldr r3, [r4, #8] +10021526: ea32 0303 bics.w r3, r2, r3 +1002152a: d1fb bne.n 10021524 +1002152c: 2221 movs r2, #33 @ 0x21 +1002152e: f500 5340 add.w r3, r0, #12288 @ 0x3000 +10021532: 3304 adds r3, #4 +10021534: 6001 str r1, [r0, #0] +10021536: 6086 str r6, [r0, #8] +10021538: 601a str r2, [r3, #0] +1002153a: 6802 ldr r2, [r0, #0] +1002153c: 2a00 cmp r2, #0 +1002153e: dafc bge.n 1002153a +10021540: 2208 movs r2, #8 +10021542: 60c5 str r5, [r0, #12] +10021544: 601a str r2, [r3, #0] +10021546: bc70 pop {r4, r5, r6} +10021548: 4770 bx lr +1002154a: 6803 ldr r3, [r0, #0] +1002154c: f003 033f and.w r3, r3, #63 @ 0x3f +10021550: 428b cmp r3, r1 +10021552: d1da bne.n 1002150a +10021554: 6883 ldr r3, [r0, #8] +10021556: f3c3 030b ubfx r3, r3, #0, #12 +1002155a: 42b3 cmp r3, r6 +1002155c: d1d5 bne.n 1002150a +1002155e: 68c3 ldr r3, [r0, #12] +10021560: f403 23ee and.w r3, r3, #487424 @ 0x77000 +10021564: 42ab cmp r3, r5 +10021566: d1d0 bne.n 1002150a +10021568: e7ed b.n 10021546 +1002156a: bf00 nop +1002156c: 00b71b00 .word 0x00b71b00 +10021570: 40058000 .word 0x40058000 +10021574: 40022000 .word 0x40022000 +10021578: 40020000 .word 0x40020000 + +1002157c : +1002157c: 2301 movs r3, #1 +1002157e: eb00 0040 add.w r0, r0, r0, lsl #1 +10021582: 0080 lsls r0, r0, #2 +10021584: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10021588: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1002158c: 6041 str r1, [r0, #4] +1002158e: 6003 str r3, [r0, #0] +10021590: 4770 bx lr +10021592: bf00 nop + +10021594 : +10021594: 2300 movs r3, #0 +10021596: 8adb ldrh r3, [r3, #22] +10021598: 2200 movs r2, #0 +1002159a: e842 f200 tt r2, r2 +1002159e: 0252 lsls r2, r2, #9 +100215a0: d401 bmi.n 100215a6 +100215a2: 2110 movs r1, #16 +100215a4: 4718 bx r3 +100215a6: 2104 movs r1, #4 +100215a8: 4718 bx r3 +100215aa: bf00 nop + +100215ac : +100215ac: 4a03 ldr r2, [pc, #12] @ (100215bc ) +100215ae: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +100215b2: 2b00 cmp r3, #0 +100215b4: d0fb beq.n 100215ae +100215b6: f3bf 8f5f dmb sy +100215ba: 4770 bx lr +100215bc: 400e0000 .word 0x400e0000 + +100215c0 : +100215c0: 2100 movs r1, #0 +100215c2: 4b04 ldr r3, [pc, #16] @ (100215d4 ) +100215c4: 4a04 ldr r2, [pc, #16] @ (100215d8 ) +100215c6: f3bf 8f5f dmb sy +100215ca: f843 1b04 str.w r1, [r3], #4 +100215ce: 4293 cmp r3, r2 +100215d0: d1f9 bne.n 100215c6 +100215d2: 4770 bx lr +100215d4: 400e080c .word 0x400e080c +100215d8: 400e082c .word 0x400e082c + +100215dc : +100215dc: b410 push {r4} +100215de: f44f 708d mov.w r0, #282 @ 0x11a +100215e2: f44f 642a mov.w r4, #2720 @ 0xaa0 +100215e6: 4a06 ldr r2, [pc, #24] @ (10021600 ) +100215e8: 4b06 ldr r3, [pc, #24] @ (10021604 ) +100215ea: 4907 ldr r1, [pc, #28] @ (10021608 ) +100215ec: 6014 str r4, [r2, #0] +100215ee: 60d0 str r0, [r2, #12] +100215f0: 6019 str r1, [r3, #0] +100215f2: 6853 ldr r3, [r2, #4] +100215f4: 2b00 cmp r3, #0 +100215f6: dafc bge.n 100215f2 +100215f8: f85d 4b04 ldr.w r4, [sp], #4 +100215fc: 4770 bx lr +100215fe: bf00 nop +10021600: 40048000 .word 0x40048000 +10021604: 4004a000 .word 0x4004a000 +10021608: 00fab000 .word 0x00fab000 + +1002160c : +1002160c: 4770 bx lr +1002160e: bf00 nop + +10021610 : +10021610: b508 push {r3, lr} +10021612: 4801 ldr r0, [pc, #4] @ (10021618 ) +10021614: f7ff f836 bl 10020684 +10021618: 10024de8 .word 0x10024de8 + +1002161c : +1002161c: b538 push {r3, r4, r5, lr} +1002161e: 4c05 ldr r4, [pc, #20] @ (10021634 ) +10021620: 4d05 ldr r5, [pc, #20] @ (10021638 ) +10021622: 42ac cmp r4, r5 +10021624: d204 bcs.n 10021630 +10021626: f854 3b04 ldr.w r3, [r4], #4 +1002162a: 4798 blx r3 +1002162c: 42ac cmp r4, r5 +1002162e: d3fa bcc.n 10021626 +10021630: bd38 pop {r3, r4, r5, pc} +10021632: bf00 nop +10021634: 10024cc8 .word 0x10024cc8 +10021638: 10024d08 .word 0x10024d08 + +1002163c : +1002163c: b410 push {r4} +1002163e: 4807 ldr r0, [pc, #28] @ (1002165c ) +10021640: 4c07 ldr r4, [pc, #28] @ (10021660 ) +10021642: 4b08 ldr r3, [pc, #32] @ (10021664 ) +10021644: 4a08 ldr r2, [pc, #32] @ (10021668 ) +10021646: 4909 ldr r1, [pc, #36] @ (1002166c ) +10021648: 6004 str r4, [r0, #0] +1002164a: 601a str r2, [r3, #0] +1002164c: 688b ldr r3, [r1, #8] +1002164e: ea32 0303 bics.w r3, r2, r3 +10021652: d1fb bne.n 1002164c +10021654: f85d 4b04 ldr.w r4, [sp], #4 +10021658: 4770 bx lr +1002165a: bf00 nop +1002165c: 40022000 .word 0x40022000 +10021660: efef3b7f .word 0xefef3b7f +10021664: 40023000 .word 0x40023000 +10021668: 03f3fff6 .word 0x03f3fff6 +1002166c: 40020000 .word 0x40020000 + +10021670 : +10021670: 4b04 ldr r3, [pc, #16] @ (10021684 ) +10021672: 6cdb ldr r3, [r3, #76] @ 0x4c +10021674: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10021678: d103 bne.n 10021682 +1002167a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1002167e: 4b02 ldr r3, [pc, #8] @ (10021688 ) +10021680: 64da str r2, [r3, #76] @ 0x4c +10021682: 4770 bx lr +10021684: 50110000 .word 0x50110000 +10021688: 50112000 .word 0x50112000 + +1002168c : +1002168c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10021690: 4b04 ldr r3, [pc, #16] @ (100216a4 ) +10021692: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10021696: 430b orrs r3, r1 +10021698: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1002169c: ee10 0430 dcp_rcmp r0 +100216a0: 4770 bx lr +100216a2: bf00 nop +100216a4: 00300303 .word 0x00300303 + +100216a8 : +100216a8: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +100216ac: 4b04 ldr r3, [pc, #16] @ (100216c0 ) +100216ae: 4a05 ldr r2, [pc, #20] @ (100216c4 ) +100216b0: 6019 str r1, [r3, #0] +100216b2: 6893 ldr r3, [r2, #8] +100216b4: 43db mvns r3, r3 +100216b6: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +100216ba: d1fa bne.n 100216b2 +100216bc: 4770 bx lr +100216be: bf00 nop +100216c0: 40023000 .word 0x40023000 +100216c4: 40020000 .word 0x40020000 + +100216c8 : +100216c8: b510 push {r4, lr} +100216ca: f245 2053 movw r0, #21075 @ 0x5253 +100216ce: f7ff ff61 bl 10021594 +100216d2: e8bd 4010 ldmia.w sp!, {r4, lr} +100216d6: 4603 mov r3, r0 +100216d8: 2004 movs r0, #4 +100216da: 4718 bx r3 + +100216dc : +100216dc: b510 push {r4, lr} +100216de: f245 2053 movw r0, #21075 @ 0x5253 +100216e2: f7ff ff57 bl 10021594 +100216e6: e8bd 4010 ldmia.w sp!, {r4, lr} +100216ea: 4603 mov r3, r0 +100216ec: 2001 movs r0, #1 +100216ee: 4718 bx r3 + +100216f0 : +100216f0: f7ff b820 b.w 10020734 + +100216f4 : +100216f4: 4914 ldr r1, [pc, #80] @ (10021748 ) +100216f6: 4b15 ldr r3, [pc, #84] @ (1002174c ) +100216f8: b570 push {r4, r5, r6, lr} +100216fa: 1a5c subs r4, r3, r1 +100216fc: 10a6 asrs r6, r4, #2 +100216fe: 2e44 cmp r6, #68 @ 0x44 +10021700: 4632 mov r2, r6 +10021702: bf28 it cs +10021704: 2244 movcs r2, #68 @ 0x44 +10021706: 4d12 ldr r5, [pc, #72] @ (10021750 ) +10021708: 0092 lsls r2, r2, #2 +1002170a: 4628 mov r0, r5 +1002170c: f003 fa28 bl 10024b60 +10021710: f5b4 7f86 cmp.w r4, #268 @ 0x10c +10021714: d813 bhi.n 1002173e +10021716: 4a0f ldr r2, [pc, #60] @ (10021754 ) +10021718: f1c6 0044 rsb r0, r6, #68 @ 0x44 +1002171c: d012 beq.n 10021744 +1002171e: 192b adds r3, r5, r4 +10021720: 0841 lsrs r1, r0, #1 +10021722: eb03 01c1 add.w r1, r3, r1, lsl #3 +10021726: e9c3 2200 strd r2, r2, [r3] +1002172a: 3308 adds r3, #8 +1002172c: 428b cmp r3, r1 +1002172e: d1fa bne.n 10021726 +10021730: 07c3 lsls r3, r0, #31 +10021732: d504 bpl.n 1002173e +10021734: f020 0001 bic.w r0, r0, #1 +10021738: 4430 add r0, r6 +1002173a: f845 2020 str.w r2, [r5, r0, lsl #2] +1002173e: 4b06 ldr r3, [pc, #24] @ (10021758 ) +10021740: 609d str r5, [r3, #8] +10021742: bd70 pop {r4, r5, r6, pc} +10021744: 2043 movs r0, #67 @ 0x43 +10021746: e7f8 b.n 1002173a +10021748: 10020000 .word 0x10020000 +1002174c: 10020110 .word 0x10020110 +10021750: 20000000 .word 0x20000000 +10021754: 10020111 .word 0x10020111 +10021758: e000ed00 .word 0xe000ed00 + +1002175c : +1002175c: 2300 movs r3, #0 +1002175e: b570 push {r4, r5, r6, lr} +10021760: 4c2b ldr r4, [pc, #172] @ (10021810 ) +10021762: b082 sub sp, #8 +10021764: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +10021768: f7ff ff38 bl 100215dc +1002176c: 2201 movs r2, #1 +1002176e: 4b29 ldr r3, [pc, #164] @ (10021814 ) +10021770: 63da str r2, [r3, #60] @ 0x3c +10021772: 6c63 ldr r3, [r4, #68] @ 0x44 +10021774: 2b01 cmp r3, #1 +10021776: d1fc bne.n 10021772 +10021778: 2103 movs r1, #3 +1002177a: 4a26 ldr r2, [pc, #152] @ (10021814 ) +1002177c: 4b24 ldr r3, [pc, #144] @ (10021810 ) +1002177e: 6311 str r1, [r2, #48] @ 0x30 +10021780: 6b9c ldr r4, [r3, #56] @ 0x38 +10021782: 2c01 cmp r4, #1 +10021784: d1fc bne.n 10021780 +10021786: 2602 movs r6, #2 +10021788: 2505 movs r5, #5 +1002178a: 4621 mov r1, r4 +1002178c: 2305 movs r3, #5 +1002178e: 4a22 ldr r2, [pc, #136] @ (10021818 ) +10021790: 4822 ldr r0, [pc, #136] @ (1002181c ) +10021792: 9600 str r6, [sp, #0] +10021794: f7ff feac bl 100214f0 +10021798: 4621 mov r1, r4 +1002179a: 462b mov r3, r5 +1002179c: 4a20 ldr r2, [pc, #128] @ (10021820 ) +1002179e: 4821 ldr r0, [pc, #132] @ (10021824 ) +100217a0: 9500 str r5, [sp, #0] +100217a2: f7ff fea5 bl 100214f0 +100217a6: 2200 movs r2, #0 +100217a8: 2004 movs r0, #4 +100217aa: 4631 mov r1, r6 +100217ac: 4b1e ldr r3, [pc, #120] @ (10021828 ) +100217ae: f7ff fe31 bl 10021414 +100217b2: 4621 mov r1, r4 +100217b4: 4628 mov r0, r5 +100217b6: 2200 movs r2, #0 +100217b8: 4b1c ldr r3, [pc, #112] @ (1002182c ) +100217ba: f7ff fe2b bl 10021414 +100217be: 2200 movs r2, #0 +100217c0: 2008 movs r0, #8 +100217c2: 4611 mov r1, r2 +100217c4: 4b1a ldr r3, [pc, #104] @ (10021830 ) +100217c6: f7ff fe25 bl 10021414 +100217ca: 2200 movs r2, #0 +100217cc: 2009 movs r0, #9 +100217ce: 4611 mov r1, r2 +100217d0: 4b17 ldr r3, [pc, #92] @ (10021830 ) +100217d2: f7ff fe1f bl 10021414 +100217d6: 2200 movs r2, #0 +100217d8: 2006 movs r0, #6 +100217da: 4611 mov r1, r2 +100217dc: 4b13 ldr r3, [pc, #76] @ (1002182c ) +100217de: f7ff fe19 bl 10021414 +100217e2: 2200 movs r2, #0 +100217e4: 4b11 ldr r3, [pc, #68] @ (1002182c ) +100217e6: 2007 movs r0, #7 +100217e8: 4611 mov r1, r2 +100217ea: f7ff fe13 bl 10021414 +100217ee: 2004 movs r0, #4 +100217f0: f7ff fe78 bl 100214e4 +100217f4: 2400 movs r4, #0 +100217f6: 4b0f ldr r3, [pc, #60] @ (10021834 ) +100217f8: fba3 3500 umull r3, r5, r3, r0 +100217fc: 0cad lsrs r5, r5, #18 +100217fe: b2e0 uxtb r0, r4 +10021800: 4629 mov r1, r5 +10021802: 3401 adds r4, #1 +10021804: f7ff feba bl 1002157c +10021808: 2c06 cmp r4, #6 +1002180a: d1f8 bne.n 100217fe +1002180c: b002 add sp, #8 +1002180e: bd70 pop {r4, r5, r6, pc} +10021810: 40010000 .word 0x40010000 +10021814: 40013000 .word 0x40013000 +10021818: 59682f00 .word 0x59682f00 +1002181c: 40050000 .word 0x40050000 +10021820: 47868c00 .word 0x47868c00 +10021824: 40058000 .word 0x40058000 +10021828: 00b71b00 .word 0x00b71b00 +1002182c: 08f0d180 .word 0x08f0d180 +10021830: 02dc6c00 .word 0x02dc6c00 +10021834: 431bde83 .word 0x431bde83 + +10021838 : +10021838: b086 sub sp, #24 +1002183a: b403 push {r0, r1} +1002183c: fc51 0408 dcp_pxmd r0, r1 +10021840: e9cd 0102 strd r0, r1, [sp, #8] +10021844: fc51 0409 dcp_pymd r0, r1 +10021848: e9cd 0104 strd r0, r1, [sp, #16] +1002184c: ec51 040a dcp_refd r0, r1 +10021850: e9cd 0106 strd r0, r1, [sp, #24] +10021854: bc03 pop {r0, r1} +10021856: 47f0 blx lr + +10021858 : +10021858: e8bd 5000 ldmia.w sp!, {ip, lr} +1002185c: ec4e c400 dcp_wxmd ip, lr +10021860: e8bd 5000 ldmia.w sp!, {ip, lr} +10021864: ec4e c401 dcp_wymd ip, lr +10021868: e8bd 5000 ldmia.w sp!, {ip, lr} +1002186c: ec4e c402 dcp_wefd ip, lr +10021870: bd00 pop {pc} +10021872: 0000 movs r0, r0 +10021874: b500 push {lr} +10021876: f7ff ffdf bl 10021838 +1002187a: e002 b.n 10021882 <__wrap___aeabi_dadd+0x6> + +1002187c <__wrap___aeabi_dadd>: +1002187c: fe10 f430 dcp_pcmp APSR_nzcv +10021880: d4f8 bmi.n 10021874 +10021882: ec41 0410 dcp_wxup r0, r1 +10021886: ec43 2411 dcp_wyup r2, r3 +1002188a: ee00 0401 dcp_add0 +1002188e: ee10 0401 dcp_add1 +10021892: ee80 0420 dcp_nrdd +10021896: ec51 0410 dcp_rdda r0, r1 +1002189a: 4770 bx lr +1002189c: b500 push {lr} +1002189e: f7ff ffcb bl 10021838 +100218a2: e002 b.n 100218aa <__wrap___aeabi_dsub+0x6> + +100218a4 <__wrap___aeabi_dsub>: +100218a4: fe10 f430 dcp_pcmp APSR_nzcv +100218a8: d4f8 bmi.n 1002189c <__wrap___aeabi_dadd+0x20> +100218aa: ec41 0410 dcp_wxup r0, r1 +100218ae: ec43 2411 dcp_wyup r2, r3 +100218b2: ee00 0401 dcp_add0 +100218b6: ee10 0421 dcp_sub1 +100218ba: ee80 0420 dcp_nrdd +100218be: ec51 0430 dcp_rdds r0, r1 +100218c2: 4770 bx lr +100218c4: b500 push {lr} +100218c6: f7ff ffb7 bl 10021838 +100218ca: e002 b.n 100218d2 <__wrap___aeabi_dmul+0x6> + +100218cc <__wrap___aeabi_dmul>: +100218cc: fe10 f430 dcp_pcmp APSR_nzcv +100218d0: d4f8 bmi.n 100218c4 <__wrap___aeabi_dsub+0x20> +100218d2: b510 push {r4, lr} +100218d4: ec41 0410 dcp_wxup r0, r1 +100218d8: ec43 2411 dcp_wyup r2, r3 +100218dc: ec51 0404 dcp_rxms r0, r1, #0x0 +100218e0: ec53 2405 dcp_ryms r2, r3, #0x0 +100218e4: fba0 4c02 umull r4, ip, r0, r2 +100218e8: f05f 0e00 movs.w lr, #0 +100218ec: fbe0 ce03 umlal ip, lr, r0, r3 +100218f0: fbe1 ce02 umlal ip, lr, r1, r2 +100218f4: ec4c 4420 dcp_wxms r4, ip +100218f8: 2400 movs r4, #0 +100218fa: fbe1 e403 umlal lr, r4, r1, r3 +100218fe: ec44 e430 dcp_wxmo lr, r4 +10021902: ee80 0420 dcp_nrdd +10021906: ec51 0450 dcp_rddm r0, r1 +1002190a: e8bd 4010 ldmia.w sp!, {r4, lr} +1002190e: 4770 bx lr +10021910: b500 push {lr} +10021912: f7ff ff91 bl 10021838 +10021916: e002 b.n 1002191e <__wrap___aeabi_ddiv+0x6> + +10021918 <__wrap___aeabi_ddiv>: +10021918: fe10 f430 dcp_pcmp APSR_nzcv +1002191c: d4f8 bmi.n 10021910 <__wrap___aeabi_dmul+0x44> +1002191e: ec41 0410 dcp_wxup r0, r1 +10021922: ec43 2411 dcp_wyup r2, r3 +10021926: ec51 0421 dcp_rymr r0, r1 +1002192a: fba0 1201 umull r1, r2, r0, r1 +1002192e: ea6f 0282 mvn.w r2, r2, lsl #2 +10021932: fb52 0010 smmlar r0, r2, r0, r0 +10021936: fb52 f212 smmulr r2, r2, r2 +1002193a: fb52 0010 smmlar r0, r2, r0, r0 +1002193e: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +10021942: ec53 2404 dcp_rxms r2, r3, #0x0 +10021946: fb5c f113 smmulr r1, ip, r3 +1002194a: ec53 2415 dcp_ryms r2, r3, #0x1 +1002194e: fba1 2002 umull r2, r0, r1, r2 +10021952: fb01 0003 mla r0, r1, r3, r0 +10021956: ec53 2444 dcp_rxms r2, r3, #0x4 +1002195a: eba2 0000 sub.w r0, r2, r0 +1002195e: fb50 f21c smmulr r2, r0, ip +10021962: ea4f 1311 mov.w r3, r1, lsr #4 +10021966: eb12 7001 adds.w r0, r2, r1, lsl #28 +1002196a: eb43 71e2 adc.w r1, r3, r2, asr #31 +1002196e: ea40 5051 orr.w r0, r0, r1, lsr #21 +10021972: ea20 5091 bic.w r0, r0, r1, lsr #22 +10021976: f020 0007 bic.w r0, r0, #7 +1002197a: ec53 2475 dcp_ryms r2, r3, #0x7 +1002197e: fba0 3c02 umull r3, ip, r0, r2 +10021982: ec53 2475 dcp_ryms r2, r3, #0x7 +10021986: fb00 cc03 mla ip, r0, r3, ip +1002198a: fb01 cc02 mla ip, r1, r2, ip +1002198e: ec53 2404 dcp_rxms r2, r3, #0x0 +10021992: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10021996: ea40 705c orr.w r0, r0, ip, lsr #29 +1002199a: f1a0 0001 sub.w r0, r0, #1 +1002199e: ec41 0440 dcp_wxdd r0, r1 +100219a2: ee80 0420 dcp_nrdd +100219a6: ec51 0470 dcp_rddd r0, r1 +100219aa: 4770 bx lr +100219ac: b500 push {lr} +100219ae: f7ff ff43 bl 10021838 +100219b2: e002 b.n 100219ba <__wrap___aeabi_i2d+0x6> + +100219b4 <__wrap___aeabi_i2d>: +100219b4: fe10 f430 dcp_pcmp APSR_nzcv +100219b8: d4f8 bmi.n 100219ac <__wrap___aeabi_ddiv+0x94> +100219ba: ec40 0470 dcp_wxic r0, r0 +100219be: ee00 0401 dcp_add0 +100219c2: ee10 0421 dcp_sub1 +100219c6: ee80 0420 dcp_nrdd +100219ca: ec51 0430 dcp_rdds r0, r1 +100219ce: 4770 bx lr +100219d0: b500 push {lr} +100219d2: f7ff ff31 bl 10021838 +100219d6: e002 b.n 100219de <__wrap___aeabi_ui2d+0x6> + +100219d8 <__wrap___aeabi_ui2d>: +100219d8: fe10 f430 dcp_pcmp APSR_nzcv +100219dc: d4f8 bmi.n 100219d0 <__wrap___aeabi_i2d+0x1c> +100219de: ec40 0460 dcp_wxuc r0, r0 +100219e2: ee00 0401 dcp_add0 +100219e6: ee10 0421 dcp_sub1 +100219ea: ee80 0420 dcp_nrdd +100219ee: ec51 0430 dcp_rdds r0, r1 +100219f2: 4770 bx lr +100219f4: b500 push {lr} +100219f6: f7ff ff1f bl 10021838 +100219fa: e002 b.n 10021a02 + +100219fc <__wrap___aeabi_d2iz>: +100219fc: fe10 f430 dcp_pcmp APSR_nzcv +10021a00: d4f8 bmi.n 100219f4 <__wrap___aeabi_ui2d+0x1c> + +10021a02 : +10021a02: ec41 0480 dcp_wxdc r0, r1 +10021a06: ee00 0401 dcp_add0 +10021a0a: ee10 0401 dcp_add1 +10021a0e: ee80 0440 dcp_ntdc +10021a12: ee10 0413 dcp_rdic r0 +10021a16: 4770 bx lr +10021a18: b500 push {lr} +10021a1a: f7ff ff0d bl 10021838 +10021a1e: e002 b.n 10021a26 + +10021a20 <__wrap___aeabi_d2uiz>: +10021a20: fe10 f430 dcp_pcmp APSR_nzcv +10021a24: d4f8 bmi.n 10021a18 + +10021a26 : +10021a26: ec41 0480 dcp_wxdc r0, r1 +10021a2a: ee00 0401 dcp_add0 +10021a2e: ee10 0401 dcp_add1 +10021a32: ee80 0440 dcp_ntdc +10021a36: ee10 0433 dcp_rduc r0 +10021a3a: 4770 bx lr +10021a3c: b500 push {lr} +10021a3e: f7ff fefb bl 10021838 +10021a42: e002 b.n 10021a4a <__wrap___aeabi_dcmpun+0x6> + +10021a44 <__wrap___aeabi_dcmpun>: +10021a44: fe10 f430 dcp_pcmp APSR_nzcv +10021a48: d4f8 bmi.n 10021a3c +10021a4a: ec41 0410 dcp_wxup r0, r1 +10021a4e: ec43 2411 dcp_wyup r2, r3 +10021a52: ee00 0401 dcp_add0 +10021a56: ee10 0430 dcp_rcmp r0 +10021a5a: f3c0 7000 ubfx r0, r0, #28, #1 +10021a5e: 4770 bx lr +10021a60: b500 push {lr} +10021a62: f7ff fee9 bl 10021838 +10021a66: e002 b.n 10021a6e <__wrap___aeabi_dcmplt+0x6> + +10021a68 <__wrap___aeabi_dcmplt>: +10021a68: fe10 f430 dcp_pcmp APSR_nzcv +10021a6c: d4f8 bmi.n 10021a60 <__wrap___aeabi_dcmpun+0x1c> +10021a6e: ec43 2410 dcp_wxup r2, r3 +10021a72: ec41 0411 dcp_wyup r0, r1 +10021a76: ee00 0401 dcp_add0 +10021a7a: ee10 f430 dcp_rcmp APSR_nzcv +10021a7e: bf8c ite hi +10021a80: 2001 movhi r0, #1 +10021a82: 2000 movls r0, #0 +10021a84: 4770 bx lr +10021a86: bf00 nop +10021a88: b500 push {lr} +10021a8a: f7ff fed5 bl 10021838 +10021a8e: e002 b.n 10021a96 <__wrap___aeabi_dcmple+0x6> + +10021a90 <__wrap___aeabi_dcmple>: +10021a90: fe10 f430 dcp_pcmp APSR_nzcv +10021a94: d4f8 bmi.n 10021a88 <__wrap___aeabi_dcmplt+0x20> +10021a96: ec43 2410 dcp_wxup r2, r3 +10021a9a: ec41 0411 dcp_wyup r0, r1 +10021a9e: ee00 0401 dcp_add0 +10021aa2: ee10 f430 dcp_rcmp APSR_nzcv +10021aa6: bf2c ite cs +10021aa8: 2001 movcs r0, #1 +10021aaa: 2000 movcc r0, #0 +10021aac: 4770 bx lr +10021aae: bf00 nop +10021ab0: b500 push {lr} +10021ab2: f7ff fec1 bl 10021838 +10021ab6: e002 b.n 10021abe <__wrap___aeabi_dcmpge+0x6> + +10021ab8 <__wrap___aeabi_dcmpge>: +10021ab8: fe10 f430 dcp_pcmp APSR_nzcv +10021abc: d4f8 bmi.n 10021ab0 <__wrap___aeabi_dcmple+0x20> +10021abe: ec41 0410 dcp_wxup r0, r1 +10021ac2: ec43 2411 dcp_wyup r2, r3 +10021ac6: ee00 0401 dcp_add0 +10021aca: ee10 f430 dcp_rcmp APSR_nzcv +10021ace: bf2c ite cs +10021ad0: 2001 movcs r0, #1 +10021ad2: 2000 movcc r0, #0 +10021ad4: 4770 bx lr +10021ad6: bf00 nop +10021ad8: b500 push {lr} +10021ada: f7ff fead bl 10021838 +10021ade: e002 b.n 10021ae6 <__wrap___aeabi_dcmpgt+0x6> + +10021ae0 <__wrap___aeabi_dcmpgt>: +10021ae0: fe10 f430 dcp_pcmp APSR_nzcv +10021ae4: d4f8 bmi.n 10021ad8 <__wrap___aeabi_dcmpge+0x20> +10021ae6: ec41 0410 dcp_wxup r0, r1 +10021aea: ec43 2411 dcp_wyup r2, r3 +10021aee: ee00 0401 dcp_add0 +10021af2: ee10 f430 dcp_rcmp APSR_nzcv +10021af6: bf8c ite hi +10021af8: 2001 movhi r0, #1 +10021afa: 2000 movls r0, #0 +10021afc: 4770 bx lr +10021afe: bf00 nop + +10021b00 <_out_null>: +10021b00: 4770 bx lr +10021b02: bf00 nop + +10021b04 <_out_rev>: +10021b04: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021b08: b083 sub sp, #12 +10021b0a: 4699 mov r9, r3 +10021b0c: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +10021b10: 9b0f ldr r3, [sp, #60] @ 0x3c +10021b12: 4688 mov r8, r1 +10021b14: 4611 mov r1, r2 +10021b16: 079a lsls r2, r3, #30 +10021b18: 4607 mov r7, r0 +10021b1a: d116 bne.n 10021b4a <_out_rev+0x46> +10021b1c: 45da cmp sl, fp +10021b1e: d23a bcs.n 10021b96 <_out_rev+0x92> +10021b20: 460c mov r4, r1 +10021b22: 460d mov r5, r1 +10021b24: ebab 060a sub.w r6, fp, sl +10021b28: 440e add r6, r1 +10021b2a: 4622 mov r2, r4 +10021b2c: 464b mov r3, r9 +10021b2e: 4641 mov r1, r8 +10021b30: 2020 movs r0, #32 +10021b32: 3401 adds r4, #1 +10021b34: 47b8 blx r7 +10021b36: 42b4 cmp r4, r6 +10021b38: d1f7 bne.n 10021b2a <_out_rev+0x26> +10021b3a: 4629 mov r1, r5 +10021b3c: f1ba 0f00 cmp.w sl, #0 +10021b40: d108 bne.n 10021b54 <_out_rev+0x50> +10021b42: 4620 mov r0, r4 +10021b44: b003 add sp, #12 +10021b46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10021b4a: 460c mov r4, r1 +10021b4c: f1ba 0f00 cmp.w sl, #0 +10021b50: d010 beq.n 10021b74 <_out_rev+0x70> +10021b52: 460e mov r6, r1 +10021b54: 4655 mov r5, sl +10021b56: 9b0c ldr r3, [sp, #48] @ 0x30 +10021b58: 442e add r6, r5 +10021b5a: 449a add sl, r3 +10021b5c: 9101 str r1, [sp, #4] +10021b5e: 1b72 subs r2, r6, r5 +10021b60: 464b mov r3, r9 +10021b62: 3d01 subs r5, #1 +10021b64: 4641 mov r1, r8 +10021b66: f81a 0d01 ldrb.w r0, [sl, #-1]! +10021b6a: 4634 mov r4, r6 +10021b6c: 47b8 blx r7 +10021b6e: 2d00 cmp r5, #0 +10021b70: d1f5 bne.n 10021b5e <_out_rev+0x5a> +10021b72: 9901 ldr r1, [sp, #4] +10021b74: 9b0f ldr r3, [sp, #60] @ 0x3c +10021b76: 079b lsls r3, r3, #30 +10021b78: d5e3 bpl.n 10021b42 <_out_rev+0x3e> +10021b7a: 1a65 subs r5, r4, r1 +10021b7c: 45ab cmp fp, r5 +10021b7e: d9e0 bls.n 10021b42 <_out_rev+0x3e> +10021b80: 4622 mov r2, r4 +10021b82: 464b mov r3, r9 +10021b84: 4641 mov r1, r8 +10021b86: 2020 movs r0, #32 +10021b88: 3501 adds r5, #1 +10021b8a: 47b8 blx r7 +10021b8c: 455d cmp r5, fp +10021b8e: f104 0401 add.w r4, r4, #1 +10021b92: d3f5 bcc.n 10021b80 <_out_rev+0x7c> +10021b94: e7d5 b.n 10021b42 <_out_rev+0x3e> +10021b96: 460c mov r4, r1 +10021b98: f1ba 0f00 cmp.w sl, #0 +10021b9c: d1d9 bne.n 10021b52 <_out_rev+0x4e> +10021b9e: e7d0 b.n 10021b42 <_out_rev+0x3e> + +10021ba0 <_ntoa_format>: +10021ba0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021ba4: 9f0f ldr r7, [sp, #60] @ 0x3c +10021ba6: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +10021baa: f017 0f02 tst.w r7, #2 +10021bae: 9c0a ldr r4, [sp, #40] @ 0x28 +10021bb0: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10021bb4: 9d0e ldr r5, [sp, #56] @ 0x38 +10021bb6: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +10021bba: d144 bne.n 10021c46 <_ntoa_format+0xa6> +10021bbc: bbf5 cbnz r5, 10021c3c <_ntoa_format+0x9c> +10021bbe: 42b4 cmp r4, r6 +10021bc0: d241 bcs.n 10021c46 <_ntoa_format+0xa6> +10021bc2: f007 0b01 and.w fp, r7, #1 +10021bc6: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10021bca: f04f 0e30 mov.w lr, #48 @ 0x30 +10021bce: 44c4 add ip, r8 +10021bd0: e004 b.n 10021bdc <_ntoa_format+0x3c> +10021bd2: 3401 adds r4, #1 +10021bd4: 42a6 cmp r6, r4 +10021bd6: f80c ef01 strb.w lr, [ip, #1]! +10021bda: d901 bls.n 10021be0 <_ntoa_format+0x40> +10021bdc: 2c20 cmp r4, #32 +10021bde: d1f8 bne.n 10021bd2 <_ntoa_format+0x32> +10021be0: f1bb 0f00 cmp.w fp, #0 +10021be4: f000 8088 beq.w 10021cf8 <_ntoa_format+0x158> +10021be8: 42a5 cmp r5, r4 +10021bea: d92c bls.n 10021c46 <_ntoa_format+0xa6> +10021bec: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +10021bf0: f04f 0e30 mov.w lr, #48 @ 0x30 +10021bf4: 44c4 add ip, r8 +10021bf6: e004 b.n 10021c02 <_ntoa_format+0x62> +10021bf8: 3401 adds r4, #1 +10021bfa: 42ac cmp r4, r5 +10021bfc: f80c ef01 strb.w lr, [ip, #1]! +10021c00: d021 beq.n 10021c46 <_ntoa_format+0xa6> +10021c02: 2c20 cmp r4, #32 +10021c04: d1f8 bne.n 10021bf8 <_ntoa_format+0x58> +10021c06: f017 0f10 tst.w r7, #16 +10021c0a: d00e beq.n 10021c2a <_ntoa_format+0x8a> +10021c0c: f417 6f80 tst.w r7, #1024 @ 0x400 +10021c10: d154 bne.n 10021cbc <_ntoa_format+0x11c> +10021c12: 42a6 cmp r6, r4 +10021c14: d063 beq.n 10021cde <_ntoa_format+0x13e> +10021c16: 42a5 cmp r5, r4 +10021c18: d061 beq.n 10021cde <_ntoa_format+0x13e> +10021c1a: f1b9 0f10 cmp.w r9, #16 +10021c1e: d050 beq.n 10021cc2 <_ntoa_format+0x122> +10021c20: f1b9 0f02 cmp.w r9, #2 +10021c24: d056 beq.n 10021cd4 <_ntoa_format+0x134> +10021c26: 2c20 cmp r4, #32 +10021c28: d129 bne.n 10021c7e <_ntoa_format+0xde> +10021c2a: 2420 movs r4, #32 +10021c2c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10021c30: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10021c34: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021c38: f7ff bf64 b.w 10021b04 <_out_rev> +10021c3c: f017 0b01 ands.w fp, r7, #1 +10021c40: d134 bne.n 10021cac <_ntoa_format+0x10c> +10021c42: 42b4 cmp r4, r6 +10021c44: d3bf bcc.n 10021bc6 <_ntoa_format+0x26> +10021c46: f017 0f10 tst.w r7, #16 +10021c4a: d01e beq.n 10021c8a <_ntoa_format+0xea> +10021c4c: f417 6f80 tst.w r7, #1024 @ 0x400 +10021c50: d1e3 bne.n 10021c1a <_ntoa_format+0x7a> +10021c52: 2c00 cmp r4, #0 +10021c54: d1dd bne.n 10021c12 <_ntoa_format+0x72> +10021c56: f1b9 0f10 cmp.w r9, #16 +10021c5a: d063 beq.n 10021d24 <_ntoa_format+0x184> +10021c5c: f1b9 0f02 cmp.w r9, #2 +10021c60: d077 beq.n 10021d52 <_ntoa_format+0x1b2> +10021c62: 2430 movs r4, #48 @ 0x30 +10021c64: f888 4000 strb.w r4, [r8] +10021c68: 2401 movs r4, #1 +10021c6a: f1ba 0f00 cmp.w sl, #0 +10021c6e: d111 bne.n 10021c94 <_ntoa_format+0xf4> +10021c70: 077e lsls r6, r7, #29 +10021c72: d548 bpl.n 10021d06 <_ntoa_format+0x166> +10021c74: 262b movs r6, #43 @ 0x2b +10021c76: f808 6004 strb.w r6, [r8, r4] +10021c7a: 3401 adds r4, #1 +10021c7c: e7d6 b.n 10021c2c <_ntoa_format+0x8c> +10021c7e: 4626 mov r6, r4 +10021c80: 3401 adds r4, #1 +10021c82: f04f 0c30 mov.w ip, #48 @ 0x30 +10021c86: f808 c006 strb.w ip, [r8, r6] +10021c8a: 2c20 cmp r4, #32 +10021c8c: d0cd beq.n 10021c2a <_ntoa_format+0x8a> +10021c8e: f1ba 0f00 cmp.w sl, #0 +10021c92: d0ed beq.n 10021c70 <_ntoa_format+0xd0> +10021c94: 262d movs r6, #45 @ 0x2d +10021c96: f808 6004 strb.w r6, [r8, r4] +10021c9a: 3401 adds r4, #1 +10021c9c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10021ca0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10021ca4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021ca8: f7ff bf2c b.w 10021b04 <_out_rev> +10021cac: f1ba 0f00 cmp.w sl, #0 +10021cb0: d030 beq.n 10021d14 <_ntoa_format+0x174> +10021cb2: 42b4 cmp r4, r6 +10021cb4: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10021cb8: d385 bcc.n 10021bc6 <_ntoa_format+0x26> +10021cba: e795 b.n 10021be8 <_ntoa_format+0x48> +10021cbc: f1b9 0f10 cmp.w r9, #16 +10021cc0: d1b3 bne.n 10021c2a <_ntoa_format+0x8a> +10021cc2: 06be lsls r6, r7, #26 +10021cc4: d53b bpl.n 10021d3e <_ntoa_format+0x19e> +10021cc6: 2c20 cmp r4, #32 +10021cc8: d0af beq.n 10021c2a <_ntoa_format+0x8a> +10021cca: 2658 movs r6, #88 @ 0x58 +10021ccc: f808 6004 strb.w r6, [r8, r4] +10021cd0: 3401 adds r4, #1 +10021cd2: e7a8 b.n 10021c26 <_ntoa_format+0x86> +10021cd4: 2c20 cmp r4, #32 +10021cd6: d0a8 beq.n 10021c2a <_ntoa_format+0x8a> +10021cd8: 4626 mov r6, r4 +10021cda: 3401 adds r4, #1 +10021cdc: e007 b.n 10021cee <_ntoa_format+0x14e> +10021cde: 1e66 subs r6, r4, #1 +10021ce0: d0b9 beq.n 10021c56 <_ntoa_format+0xb6> +10021ce2: f1b9 0f10 cmp.w r9, #16 +10021ce6: d036 beq.n 10021d56 <_ntoa_format+0x1b6> +10021ce8: f1b9 0f02 cmp.w r9, #2 +10021cec: d1c9 bne.n 10021c82 <_ntoa_format+0xe2> +10021cee: f04f 0c62 mov.w ip, #98 @ 0x62 +10021cf2: f808 c006 strb.w ip, [r8, r6] +10021cf6: e796 b.n 10021c26 <_ntoa_format+0x86> +10021cf8: f017 0f10 tst.w r7, #16 +10021cfc: d0c5 beq.n 10021c8a <_ntoa_format+0xea> +10021cfe: f417 6f80 tst.w r7, #1024 @ 0x400 +10021d02: d086 beq.n 10021c12 <_ntoa_format+0x72> +10021d04: e789 b.n 10021c1a <_ntoa_format+0x7a> +10021d06: 073e lsls r6, r7, #28 +10021d08: d590 bpl.n 10021c2c <_ntoa_format+0x8c> +10021d0a: 2620 movs r6, #32 +10021d0c: f808 6004 strb.w r6, [r8, r4] +10021d10: 3401 adds r4, #1 +10021d12: e78b b.n 10021c2c <_ntoa_format+0x8c> +10021d14: f017 0f0c tst.w r7, #12 +10021d18: d000 beq.n 10021d1c <_ntoa_format+0x17c> +10021d1a: 3d01 subs r5, #1 +10021d1c: 42b4 cmp r4, r6 +10021d1e: f4ff af52 bcc.w 10021bc6 <_ntoa_format+0x26> +10021d22: e761 b.n 10021be8 <_ntoa_format+0x48> +10021d24: 06bc lsls r4, r7, #26 +10021d26: d412 bmi.n 10021d4e <_ntoa_format+0x1ae> +10021d28: 2478 movs r4, #120 @ 0x78 +10021d2a: f888 4000 strb.w r4, [r8] +10021d2e: 2430 movs r4, #48 @ 0x30 +10021d30: f888 4001 strb.w r4, [r8, #1] +10021d34: 2402 movs r4, #2 +10021d36: f1ba 0f00 cmp.w sl, #0 +10021d3a: d099 beq.n 10021c70 <_ntoa_format+0xd0> +10021d3c: e7aa b.n 10021c94 <_ntoa_format+0xf4> +10021d3e: 2c20 cmp r4, #32 +10021d40: f43f af73 beq.w 10021c2a <_ntoa_format+0x8a> +10021d44: 2678 movs r6, #120 @ 0x78 +10021d46: f808 6004 strb.w r6, [r8, r4] +10021d4a: 3401 adds r4, #1 +10021d4c: e76b b.n 10021c26 <_ntoa_format+0x86> +10021d4e: 2458 movs r4, #88 @ 0x58 +10021d50: e7eb b.n 10021d2a <_ntoa_format+0x18a> +10021d52: 2462 movs r4, #98 @ 0x62 +10021d54: e7e9 b.n 10021d2a <_ntoa_format+0x18a> +10021d56: f017 0f20 tst.w r7, #32 +10021d5a: f1a4 0c02 sub.w ip, r4, #2 +10021d5e: d004 beq.n 10021d6a <_ntoa_format+0x1ca> +10021d60: f04f 0e58 mov.w lr, #88 @ 0x58 +10021d64: f808 e00c strb.w lr, [r8, ip] +10021d68: e78b b.n 10021c82 <_ntoa_format+0xe2> +10021d6a: f04f 0e78 mov.w lr, #120 @ 0x78 +10021d6e: f808 e00c strb.w lr, [r8, ip] +10021d72: e786 b.n 10021c82 <_ntoa_format+0xe2> + +10021d74 <_out_char>: +10021d74: b900 cbnz r0, 10021d78 <_out_char+0x4> +10021d76: 4770 bx lr +10021d78: f001 bb72 b.w 10023460 <__wrap_putchar> + +10021d7c <_out_fct>: +10021d7c: b110 cbz r0, 10021d84 <_out_fct+0x8> +10021d7e: e9d1 3100 ldrd r3, r1, [r1] +10021d82: 4718 bx r3 +10021d84: 4770 bx lr +10021d86: bf00 nop + +10021d88 <_ftoa>: +10021d88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021d8c: b097 sub sp, #92 @ 0x5c +10021d8e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10021d92: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10021d96: 4607 mov r7, r0 +10021d98: 4688 mov r8, r1 +10021d9a: ec51 0b17 vmov r0, r1, d7 +10021d9e: 9c24 ldr r4, [sp, #144] @ 0x90 +10021da0: 4699 mov r9, r3 +10021da2: 920c str r2, [sp, #48] @ 0x30 +10021da4: 460b mov r3, r1 +10021da6: 4602 mov r2, r0 +10021da8: ed8d 7b04 vstr d7, [sp, #16] +10021dac: 9407 str r4, [sp, #28] +10021dae: f7ff fe49 bl 10021a44 <__wrap___aeabi_dcmpun> +10021db2: 2800 cmp r0, #0 +10021db4: f040 81f4 bne.w 100221a0 <_ftoa+0x418> +10021db8: e9dd 0104 ldrd r0, r1, [sp, #16] +10021dbc: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10021dc0: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10021dc4: f7ff fe50 bl 10021a68 <__wrap___aeabi_dcmplt> +10021dc8: 2800 cmp r0, #0 +10021dca: f040 811b bne.w 10022004 <_ftoa+0x27c> +10021dce: e9dd 0104 ldrd r0, r1, [sp, #16] +10021dd2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10021dd6: 4bac ldr r3, [pc, #688] @ (10022088 <_ftoa+0x300>) +10021dd8: f7ff fe82 bl 10021ae0 <__wrap___aeabi_dcmpgt> +10021ddc: 2800 cmp r0, #0 +10021dde: f040 80ee bne.w 10021fbe <_ftoa+0x236> +10021de2: e9dd 0104 ldrd r0, r1, [sp, #16] +10021de6: a3a4 add r3, pc, #656 @ (adr r3, 10022078 <_ftoa+0x2f0>) +10021de8: e9d3 2300 ldrd r2, r3, [r3] +10021dec: f7ff fe78 bl 10021ae0 <__wrap___aeabi_dcmpgt> +10021df0: 2800 cmp r0, #0 +10021df2: f040 80d3 bne.w 10021f9c <_ftoa+0x214> +10021df6: e9dd 0104 ldrd r0, r1, [sp, #16] +10021dfa: a3a1 add r3, pc, #644 @ (adr r3, 10022080 <_ftoa+0x2f8>) +10021dfc: e9d3 2300 ldrd r2, r3, [r3] +10021e00: f7ff fe32 bl 10021a68 <__wrap___aeabi_dcmplt> +10021e04: 2800 cmp r0, #0 +10021e06: f040 80c9 bne.w 10021f9c <_ftoa+0x214> +10021e0a: e9dd 0104 ldrd r0, r1, [sp, #16] +10021e0e: 2200 movs r2, #0 +10021e10: 2300 movs r3, #0 +10021e12: f7ff fe29 bl 10021a68 <__wrap___aeabi_dcmplt> +10021e16: 2800 cmp r0, #0 +10021e18: f040 80e8 bne.w 10021fec <_ftoa+0x264> +10021e1c: 4623 mov r3, r4 +10021e1e: 900d str r0, [sp, #52] @ 0x34 +10021e20: f413 6f80 tst.w r3, #1024 @ 0x400 +10021e24: bf08 it eq +10021e26: 2506 moveq r5, #6 +10021e28: 2130 movs r1, #48 @ 0x30 +10021e2a: 462b mov r3, r5 +10021e2c: aa0e add r2, sp, #56 @ 0x38 +10021e2e: f1a5 0620 sub.w r6, r5, #32 +10021e32: e005 b.n 10021e40 <_ftoa+0xb8> +10021e34: 3b01 subs r3, #1 +10021e36: 42b3 cmp r3, r6 +10021e38: f802 1b01 strb.w r1, [r2], #1 +10021e3c: f000 8193 beq.w 10022166 <_ftoa+0x3de> +10021e40: 2b09 cmp r3, #9 +10021e42: d8f7 bhi.n 10021e34 <_ftoa+0xac> +10021e44: 461e mov r6, r3 +10021e46: 1aed subs r5, r5, r3 +10021e48: e9dd 0104 ldrd r0, r1, [sp, #16] +10021e4c: f7ff fdd6 bl 100219fc <__wrap___aeabi_d2iz> +10021e50: 4b8e ldr r3, [pc, #568] @ (1002208c <_ftoa+0x304>) +10021e52: 4604 mov r4, r0 +10021e54: eb03 03c6 add.w r3, r3, r6, lsl #3 +10021e58: ed93 7b00 vldr d7, [r3] +10021e5c: ed8d 7b08 vstr d7, [sp, #32] +10021e60: f7ff fda8 bl 100219b4 <__wrap___aeabi_i2d> +10021e64: 4602 mov r2, r0 +10021e66: 460b mov r3, r1 +10021e68: e9dd 0104 ldrd r0, r1, [sp, #16] +10021e6c: f7ff fd1a bl 100218a4 <__wrap___aeabi_dsub> +10021e70: e9dd 2308 ldrd r2, r3, [sp, #32] +10021e74: f7ff fd2a bl 100218cc <__wrap___aeabi_dmul> +10021e78: 4602 mov r2, r0 +10021e7a: 460b mov r3, r1 +10021e7c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10021e80: f7ff fdce bl 10021a20 <__wrap___aeabi_d2uiz> +10021e84: 4682 mov sl, r0 +10021e86: f7ff fda7 bl 100219d8 <__wrap___aeabi_ui2d> +10021e8a: 4602 mov r2, r0 +10021e8c: 460b mov r3, r1 +10021e8e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10021e92: f7ff fd07 bl 100218a4 <__wrap___aeabi_dsub> +10021e96: 4602 mov r2, r0 +10021e98: 460b mov r3, r1 +10021e9a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10021e9e: 2200 movs r2, #0 +10021ea0: 4b7b ldr r3, [pc, #492] @ (10022090 <_ftoa+0x308>) +10021ea2: f7ff fe1d bl 10021ae0 <__wrap___aeabi_dcmpgt> +10021ea6: 2800 cmp r0, #0 +10021ea8: f000 80fe beq.w 100220a8 <_ftoa+0x320> +10021eac: f10a 0a01 add.w sl, sl, #1 +10021eb0: 4650 mov r0, sl +10021eb2: f7ff fd91 bl 100219d8 <__wrap___aeabi_ui2d> +10021eb6: 4602 mov r2, r0 +10021eb8: 460b mov r3, r1 +10021eba: e9dd 0108 ldrd r0, r1, [sp, #32] +10021ebe: f7ff fde7 bl 10021a90 <__wrap___aeabi_dcmple> +10021ec2: b110 cbz r0, 10021eca <_ftoa+0x142> +10021ec4: f04f 0a00 mov.w sl, #0 +10021ec8: 3401 adds r4, #1 +10021eca: 2e00 cmp r6, #0 +10021ecc: f000 80fd beq.w 100220ca <_ftoa+0x342> +10021ed0: 1e68 subs r0, r5, #1 +10021ed2: ab0e add r3, sp, #56 @ 0x38 +10021ed4: f8df c1cc ldr.w ip, [pc, #460] @ 100220a4 <_ftoa+0x31c> +10021ed8: 4418 add r0, r3 +10021eda: e00f b.n 10021efc <_ftoa+0x174> +10021edc: fbac 210a umull r2, r1, ip, sl +10021ee0: 08c9 lsrs r1, r1, #3 +10021ee2: eb01 0281 add.w r2, r1, r1, lsl #2 +10021ee6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10021eea: 3230 adds r2, #48 @ 0x30 +10021eec: f1ba 0f09 cmp.w sl, #9 +10021ef0: f800 2f01 strb.w r2, [r0, #1]! +10021ef4: f240 811c bls.w 10022130 <_ftoa+0x3a8> +10021ef8: 468a mov sl, r1 +10021efa: 461d mov r5, r3 +10021efc: 2d20 cmp r5, #32 +10021efe: f105 0301 add.w r3, r5, #1 +10021f02: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10021f06: d1e9 bne.n 10021edc <_ftoa+0x154> +10021f08: 2520 movs r5, #32 +10021f0a: 1e69 subs r1, r5, #1 +10021f0c: ab0e add r3, sp, #56 @ 0x38 +10021f0e: 4861 ldr r0, [pc, #388] @ (10022094 <_ftoa+0x30c>) +10021f10: 4419 add r1, r3 +10021f12: e010 b.n 10021f36 <_ftoa+0x1ae> +10021f14: fb80 6204 smull r6, r2, r0, r4 +10021f18: ebc3 03a2 rsb r3, r3, r2, asr #2 +10021f1c: eb03 0283 add.w r2, r3, r3, lsl #2 +10021f20: eba4 0442 sub.w r4, r4, r2, lsl #1 +10021f24: f104 0230 add.w r2, r4, #48 @ 0x30 +10021f28: 3501 adds r5, #1 +10021f2a: 461c mov r4, r3 +10021f2c: f801 2f01 strb.w r2, [r1, #1]! +10021f30: 2b00 cmp r3, #0 +10021f32: f000 80eb beq.w 1002210c <_ftoa+0x384> +10021f36: 2d20 cmp r5, #32 +10021f38: ea4f 73e4 mov.w r3, r4, asr #31 +10021f3c: d1ea bne.n 10021f14 <_ftoa+0x18c> +10021f3e: 9b07 ldr r3, [sp, #28] +10021f40: f003 0303 and.w r3, r3, #3 +10021f44: 2b01 cmp r3, #1 +10021f46: d118 bne.n 10021f7a <_ftoa+0x1f2> +10021f48: f1bb 0f00 cmp.w fp, #0 +10021f4c: d015 beq.n 10021f7a <_ftoa+0x1f2> +10021f4e: 9b0d ldr r3, [sp, #52] @ 0x34 +10021f50: 2b00 cmp r3, #0 +10021f52: f000 810a beq.w 1002216a <_ftoa+0x3e2> +10021f56: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10021f5a: f1bb 0f20 cmp.w fp, #32 +10021f5e: d90c bls.n 10021f7a <_ftoa+0x1f2> +10021f60: 1e6b subs r3, r5, #1 +10021f62: a90e add r1, sp, #56 @ 0x38 +10021f64: 2230 movs r2, #48 @ 0x30 +10021f66: 440b add r3, r1 +10021f68: e005 b.n 10021f76 <_ftoa+0x1ee> +10021f6a: 3501 adds r5, #1 +10021f6c: 455d cmp r5, fp +10021f6e: f803 2f01 strb.w r2, [r3, #1]! +10021f72: f080 80d1 bcs.w 10022118 <_ftoa+0x390> +10021f76: 2d20 cmp r5, #32 +10021f78: d1f7 bne.n 10021f6a <_ftoa+0x1e2> +10021f7a: 9b07 ldr r3, [sp, #28] +10021f7c: ac0e add r4, sp, #56 @ 0x38 +10021f7e: e9cd b302 strd fp, r3, [sp, #8] +10021f82: 4641 mov r1, r8 +10021f84: 464b mov r3, r9 +10021f86: 4638 mov r0, r7 +10021f88: 9a0c ldr r2, [sp, #48] @ 0x30 +10021f8a: 9501 str r5, [sp, #4] +10021f8c: 9400 str r4, [sp, #0] +10021f8e: f7ff fdb9 bl 10021b04 <_out_rev> +10021f92: 4682 mov sl, r0 +10021f94: 4650 mov r0, sl +10021f96: b017 add sp, #92 @ 0x5c +10021f98: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10021f9c: 9b07 ldr r3, [sp, #28] +10021f9e: ed9d 7b04 vldr d7, [sp, #16] +10021fa2: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10021fa6: 4641 mov r1, r8 +10021fa8: 464b mov r3, r9 +10021faa: 4638 mov r0, r7 +10021fac: 9a0c ldr r2, [sp, #48] @ 0x30 +10021fae: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10021fb2: 9522 str r5, [sp, #136] @ 0x88 +10021fb4: b017 add sp, #92 @ 0x5c +10021fb6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021fba: f000 b945 b.w 10022248 <_etoa> +10021fbe: 0761 lsls r1, r4, #29 +10021fc0: 4623 mov r3, r4 +10021fc2: bf4c ite mi +10021fc4: 2304 movmi r3, #4 +10021fc6: 2303 movpl r3, #3 +10021fc8: 4641 mov r1, r8 +10021fca: 9321 str r3, [sp, #132] @ 0x84 +10021fcc: 4638 mov r0, r7 +10021fce: 464b mov r3, r9 +10021fd0: 9a07 ldr r2, [sp, #28] +10021fd2: bf48 it mi +10021fd4: 4c30 ldrmi r4, [pc, #192] @ (10022098 <_ftoa+0x310>) +10021fd6: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10021fda: bf58 it pl +10021fdc: 4c2f ldrpl r4, [pc, #188] @ (1002209c <_ftoa+0x314>) +10021fde: 9a0c ldr r2, [sp, #48] @ 0x30 +10021fe0: 9420 str r4, [sp, #128] @ 0x80 +10021fe2: b017 add sp, #92 @ 0x5c +10021fe4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10021fe8: f7ff bd8c b.w 10021b04 <_out_rev> +10021fec: e9dd 2304 ldrd r2, r3, [sp, #16] +10021ff0: 2000 movs r0, #0 +10021ff2: 2100 movs r1, #0 +10021ff4: f7ff fc56 bl 100218a4 <__wrap___aeabi_dsub> +10021ff8: 2301 movs r3, #1 +10021ffa: e9cd 0104 strd r0, r1, [sp, #16] +10021ffe: 930d str r3, [sp, #52] @ 0x34 +10022000: 4623 mov r3, r4 +10022002: e70d b.n 10021e20 <_ftoa+0x98> +10022004: 4623 mov r3, r4 +10022006: 079c lsls r4, r3, #30 +10022008: f040 80aa bne.w 10022160 <_ftoa+0x3d8> +1002200c: f1bb 0f04 cmp.w fp, #4 +10022010: f240 80a6 bls.w 10022160 <_ftoa+0x3d8> +10022014: 9b0c ldr r3, [sp, #48] @ 0x30 +10022016: 461d mov r5, r3 +10022018: 1f1c subs r4, r3, #4 +1002201a: eb04 0a0b add.w sl, r4, fp +1002201e: 462a mov r2, r5 +10022020: 464b mov r3, r9 +10022022: 4641 mov r1, r8 +10022024: 2020 movs r0, #32 +10022026: 3501 adds r5, #1 +10022028: 47b8 blx r7 +1002202a: 45aa cmp sl, r5 +1002202c: d1f7 bne.n 1002201e <_ftoa+0x296> +1002202e: 4655 mov r5, sl +10022030: 4c1b ldr r4, [pc, #108] @ (100220a0 <_ftoa+0x318>) +10022032: 1f26 subs r6, r4, #4 +10022034: f814 0d01 ldrb.w r0, [r4, #-1]! +10022038: 462a mov r2, r5 +1002203a: 464b mov r3, r9 +1002203c: 4641 mov r1, r8 +1002203e: 47b8 blx r7 +10022040: 42b4 cmp r4, r6 +10022042: f105 0501 add.w r5, r5, #1 +10022046: d1f5 bne.n 10022034 <_ftoa+0x2ac> +10022048: 9b07 ldr r3, [sp, #28] +1002204a: f10a 0a04 add.w sl, sl, #4 +1002204e: 0798 lsls r0, r3, #30 +10022050: d5a0 bpl.n 10021f94 <_ftoa+0x20c> +10022052: 9c0c ldr r4, [sp, #48] @ 0x30 +10022054: ebaa 0304 sub.w r3, sl, r4 +10022058: 459b cmp fp, r3 +1002205a: d99b bls.n 10021f94 <_ftoa+0x20c> +1002205c: 4652 mov r2, sl +1002205e: 464b mov r3, r9 +10022060: 4641 mov r1, r8 +10022062: 2020 movs r0, #32 +10022064: f10a 0a01 add.w sl, sl, #1 +10022068: 47b8 blx r7 +1002206a: ebaa 0304 sub.w r3, sl, r4 +1002206e: 455b cmp r3, fp +10022070: d3f4 bcc.n 1002205c <_ftoa+0x2d4> +10022072: e78f b.n 10021f94 <_ftoa+0x20c> +10022074: f3af 8000 nop.w +10022078: 00000000 .word 0x00000000 +1002207c: 41cdcd65 .word 0x41cdcd65 +10022080: 00000000 .word 0x00000000 +10022084: c1cdcd65 .word 0xc1cdcd65 +10022088: 7fefffff .word 0x7fefffff +1002208c: 10024ec8 .word 0x10024ec8 +10022090: 3fe00000 .word 0x3fe00000 +10022094: 66666667 .word 0x66666667 +10022098: 10024e28 .word 0x10024e28 +1002209c: 10024e30 .word 0x10024e30 +100220a0: 10024e3c .word 0x10024e3c +100220a4: cccccccd .word 0xcccccccd +100220a8: 2200 movs r2, #0 +100220aa: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100220ae: 4b63 ldr r3, [pc, #396] @ (1002223c <_ftoa+0x4b4>) +100220b0: f7ff fcda bl 10021a68 <__wrap___aeabi_dcmplt> +100220b4: 2800 cmp r0, #0 +100220b6: f47f af08 bne.w 10021eca <_ftoa+0x142> +100220ba: f1ba 0f00 cmp.w sl, #0 +100220be: d16a bne.n 10022196 <_ftoa+0x40e> +100220c0: f10a 0a01 add.w sl, sl, #1 +100220c4: 2e00 cmp r6, #0 +100220c6: f47f af03 bne.w 10021ed0 <_ftoa+0x148> +100220ca: 4620 mov r0, r4 +100220cc: f7ff fc72 bl 100219b4 <__wrap___aeabi_i2d> +100220d0: 4602 mov r2, r0 +100220d2: 460b mov r3, r1 +100220d4: e9dd 0104 ldrd r0, r1, [sp, #16] +100220d8: f7ff fbe4 bl 100218a4 <__wrap___aeabi_dsub> +100220dc: 4602 mov r2, r0 +100220de: 460b mov r3, r1 +100220e0: e9cd 2304 strd r2, r3, [sp, #16] +100220e4: 2200 movs r2, #0 +100220e6: 4b55 ldr r3, [pc, #340] @ (1002223c <_ftoa+0x4b4>) +100220e8: f7ff fcbe bl 10021a68 <__wrap___aeabi_dcmplt> +100220ec: 2800 cmp r0, #0 +100220ee: f47f af0c bne.w 10021f0a <_ftoa+0x182> +100220f2: e9dd 0104 ldrd r0, r1, [sp, #16] +100220f6: 2200 movs r2, #0 +100220f8: 4b50 ldr r3, [pc, #320] @ (1002223c <_ftoa+0x4b4>) +100220fa: f7ff fcf1 bl 10021ae0 <__wrap___aeabi_dcmpgt> +100220fe: 2800 cmp r0, #0 +10022100: f47f af03 bne.w 10021f0a <_ftoa+0x182> +10022104: 3401 adds r4, #1 +10022106: f024 0401 bic.w r4, r4, #1 +1002210a: e6fe b.n 10021f0a <_ftoa+0x182> +1002210c: 9b07 ldr r3, [sp, #28] +1002210e: f003 0303 and.w r3, r3, #3 +10022112: 2b01 cmp r3, #1 +10022114: f000 8082 beq.w 1002221c <_ftoa+0x494> +10022118: 2d20 cmp r5, #32 +1002211a: f43f af2e beq.w 10021f7a <_ftoa+0x1f2> +1002211e: 9b0d ldr r3, [sp, #52] @ 0x34 +10022120: b37b cbz r3, 10022182 <_ftoa+0x3fa> +10022122: 222d movs r2, #45 @ 0x2d +10022124: eb0d 0305 add.w r3, sp, r5 +10022128: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1002212c: 3501 adds r5, #1 +1002212e: e724 b.n 10021f7a <_ftoa+0x1f2> +10022130: 2b20 cmp r3, #32 +10022132: f43f aee9 beq.w 10021f08 <_ftoa+0x180> +10022136: aa0e add r2, sp, #56 @ 0x38 +10022138: 4415 add r5, r2 +1002213a: 441e add r6, r3 +1002213c: 2230 movs r2, #48 @ 0x30 +1002213e: e004 b.n 1002214a <_ftoa+0x3c2> +10022140: 2b20 cmp r3, #32 +10022142: f805 2f01 strb.w r2, [r5, #1]! +10022146: f43f aedf beq.w 10021f08 <_ftoa+0x180> +1002214a: 429e cmp r6, r3 +1002214c: f103 0301 add.w r3, r3, #1 +10022150: d1f6 bne.n 10022140 <_ftoa+0x3b8> +10022152: 222e movs r2, #46 @ 0x2e +10022154: eb0d 0306 add.w r3, sp, r6 +10022158: f883 2038 strb.w r2, [r3, #56] @ 0x38 +1002215c: 1c75 adds r5, r6, #1 +1002215e: e6d4 b.n 10021f0a <_ftoa+0x182> +10022160: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10022164: e763 b.n 1002202e <_ftoa+0x2a6> +10022166: 2520 movs r5, #32 +10022168: e66e b.n 10021e48 <_ftoa+0xc0> +1002216a: 9b07 ldr r3, [sp, #28] +1002216c: f013 0f0c tst.w r3, #12 +10022170: d050 beq.n 10022214 <_ftoa+0x48c> +10022172: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10022176: 45ab cmp fp, r5 +10022178: f63f aef2 bhi.w 10021f60 <_ftoa+0x1d8> +1002217c: 2d20 cmp r5, #32 +1002217e: f43f aefc beq.w 10021f7a <_ftoa+0x1f2> +10022182: 9b07 ldr r3, [sp, #28] +10022184: 075a lsls r2, r3, #29 +10022186: d501 bpl.n 1002218c <_ftoa+0x404> +10022188: 222b movs r2, #43 @ 0x2b +1002218a: e7cb b.n 10022124 <_ftoa+0x39c> +1002218c: 071b lsls r3, r3, #28 +1002218e: f57f aef4 bpl.w 10021f7a <_ftoa+0x1f2> +10022192: 2220 movs r2, #32 +10022194: e7c6 b.n 10022124 <_ftoa+0x39c> +10022196: f01a 0f01 tst.w sl, #1 +1002219a: f43f ae96 beq.w 10021eca <_ftoa+0x142> +1002219e: e78f b.n 100220c0 <_ftoa+0x338> +100221a0: 07a6 lsls r6, r4, #30 +100221a2: d134 bne.n 1002220e <_ftoa+0x486> +100221a4: f1bb 0f03 cmp.w fp, #3 +100221a8: d931 bls.n 1002220e <_ftoa+0x486> +100221aa: 9b0c ldr r3, [sp, #48] @ 0x30 +100221ac: 461d mov r5, r3 +100221ae: 1edc subs r4, r3, #3 +100221b0: eb04 0a0b add.w sl, r4, fp +100221b4: 462a mov r2, r5 +100221b6: 464b mov r3, r9 +100221b8: 4641 mov r1, r8 +100221ba: 2020 movs r0, #32 +100221bc: 3501 adds r5, #1 +100221be: 47b8 blx r7 +100221c0: 4555 cmp r5, sl +100221c2: d1f7 bne.n 100221b4 <_ftoa+0x42c> +100221c4: 4655 mov r5, sl +100221c6: 4c1e ldr r4, [pc, #120] @ (10022240 <_ftoa+0x4b8>) +100221c8: 1ee6 subs r6, r4, #3 +100221ca: f814 0d01 ldrb.w r0, [r4, #-1]! +100221ce: 462a mov r2, r5 +100221d0: 464b mov r3, r9 +100221d2: 4641 mov r1, r8 +100221d4: 47b8 blx r7 +100221d6: 42a6 cmp r6, r4 +100221d8: f105 0501 add.w r5, r5, #1 +100221dc: d1f5 bne.n 100221ca <_ftoa+0x442> +100221de: 9b07 ldr r3, [sp, #28] +100221e0: f10a 0a03 add.w sl, sl, #3 +100221e4: 079d lsls r5, r3, #30 +100221e6: f57f aed5 bpl.w 10021f94 <_ftoa+0x20c> +100221ea: 9c0c ldr r4, [sp, #48] @ 0x30 +100221ec: ebaa 0304 sub.w r3, sl, r4 +100221f0: 459b cmp fp, r3 +100221f2: f67f aecf bls.w 10021f94 <_ftoa+0x20c> +100221f6: 4652 mov r2, sl +100221f8: 464b mov r3, r9 +100221fa: 4641 mov r1, r8 +100221fc: 2020 movs r0, #32 +100221fe: f10a 0a01 add.w sl, sl, #1 +10022202: 47b8 blx r7 +10022204: ebaa 0304 sub.w r3, sl, r4 +10022208: 459b cmp fp, r3 +1002220a: d8f4 bhi.n 100221f6 <_ftoa+0x46e> +1002220c: e6c2 b.n 10021f94 <_ftoa+0x20c> +1002220e: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10022212: e7d7 b.n 100221c4 <_ftoa+0x43c> +10022214: 45ab cmp fp, r5 +10022216: f63f aea3 bhi.w 10021f60 <_ftoa+0x1d8> +1002221a: e6ae b.n 10021f7a <_ftoa+0x1f2> +1002221c: f1bb 0f00 cmp.w fp, #0 +10022220: f43f af7a beq.w 10022118 <_ftoa+0x390> +10022224: 9b0d ldr r3, [sp, #52] @ 0x34 +10022226: 2b00 cmp r3, #0 +10022228: d09f beq.n 1002216a <_ftoa+0x3e2> +1002222a: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +1002222e: 455d cmp r5, fp +10022230: f4ff ae96 bcc.w 10021f60 <_ftoa+0x1d8> +10022234: 2d20 cmp r5, #32 +10022236: f47f af74 bne.w 10022122 <_ftoa+0x39a> +1002223a: e69e b.n 10021f7a <_ftoa+0x1f2> +1002223c: 3fe00000 .word 0x3fe00000 +10022240: 10024e37 .word 0x10024e37 +10022244: 00000000 .word 0x00000000 + +10022248 <_etoa>: +10022248: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1002224c: b09f sub sp, #124 @ 0x7c +1002224e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10022250: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10022254: 4607 mov r7, r0 +10022256: 4693 mov fp, r2 +10022258: 9108 str r1, [sp, #32] +1002225a: 9309 str r3, [sp, #36] @ 0x24 +1002225c: 4622 mov r2, r4 +1002225e: 462b mov r3, r5 +10022260: 4620 mov r0, r4 +10022262: 4629 mov r1, r5 +10022264: 960e str r6, [sp, #56] @ 0x38 +10022266: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +1002226a: f7ff fbeb bl 10021a44 <__wrap___aeabi_dcmpun> +1002226e: 2800 cmp r0, #0 +10022270: f040 80be bne.w 100223f0 <_etoa+0x1a8> +10022274: 4620 mov r0, r4 +10022276: 4629 mov r1, r5 +10022278: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1002227c: 4b78 ldr r3, [pc, #480] @ (10022460 <_etoa+0x218>) +1002227e: f7ff fc2f bl 10021ae0 <__wrap___aeabi_dcmpgt> +10022282: 2800 cmp r0, #0 +10022284: f040 80b4 bne.w 100223f0 <_etoa+0x1a8> +10022288: 4620 mov r0, r4 +1002228a: 4629 mov r1, r5 +1002228c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10022290: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10022294: f7ff fbe8 bl 10021a68 <__wrap___aeabi_dcmplt> +10022298: 2800 cmp r0, #0 +1002229a: f040 80a9 bne.w 100223f0 <_etoa+0x1a8> +1002229e: 4620 mov r0, r4 +100222a0: 4629 mov r1, r5 +100222a2: 2200 movs r2, #0 +100222a4: 2300 movs r3, #0 +100222a6: f7ff fbdf bl 10021a68 <__wrap___aeabi_dcmplt> +100222aa: 2800 cmp r0, #0 +100222ac: f040 81d5 bne.w 1002265a <_etoa+0x412> +100222b0: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +100222b4: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +100222b8: 4690 mov r8, r2 +100222ba: 4699 mov r9, r3 +100222bc: f406 6200 and.w r2, r6, #2048 @ 0x800 +100222c0: f416 6380 ands.w r3, r6, #1024 @ 0x400 +100222c4: 920f str r2, [sp, #60] @ 0x3c +100222c6: 9313 str r3, [sp, #76] @ 0x4c +100222c8: f040 80a1 bne.w 1002240e <_etoa+0x1c6> +100222cc: ea58 0309 orrs.w r3, r8, r9 +100222d0: f040 80ca bne.w 10022468 <_etoa+0x220> +100222d4: 2a00 cmp r2, #0 +100222d6: f040 81e3 bne.w 100226a0 <_etoa+0x458> +100222da: 2306 movs r3, #6 +100222dc: 930e str r3, [sp, #56] @ 0x38 +100222de: f016 0202 ands.w r2, r6, #2 +100222e2: 9210 str r2, [sp, #64] @ 0x40 +100222e4: f040 81d4 bne.w 10022690 <_etoa+0x448> +100222e8: 4653 mov r3, sl +100222ea: 2b04 cmp r3, #4 +100222ec: bf38 it cc +100222ee: 2304 movcc r3, #4 +100222f0: 920c str r2, [sp, #48] @ 0x30 +100222f2: 2204 movs r2, #4 +100222f4: 3b04 subs r3, #4 +100222f6: 9212 str r2, [sp, #72] @ 0x48 +100222f8: 930f str r3, [sp, #60] @ 0x3c +100222fa: 4620 mov r0, r4 +100222fc: 4629 mov r1, r5 +100222fe: 2200 movs r2, #0 +10022300: 2300 movs r3, #0 +10022302: f7ff fbb1 bl 10021a68 <__wrap___aeabi_dcmplt> +10022306: 2800 cmp r0, #0 +10022308: f040 81f3 bne.w 100226f2 <_etoa+0x4aa> +1002230c: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10022310: 9b0f ldr r3, [sp, #60] @ 0x3c +10022312: 465a mov r2, fp +10022314: 9303 str r3, [sp, #12] +10022316: 9b0e ldr r3, [sp, #56] @ 0x38 +10022318: ed8d 7b00 vstr d7, [sp] +1002231c: 9302 str r3, [sp, #8] +1002231e: f426 6300 bic.w r3, r6, #2048 @ 0x800 +10022322: 9304 str r3, [sp, #16] +10022324: 4638 mov r0, r7 +10022326: 9b09 ldr r3, [sp, #36] @ 0x24 +10022328: 9908 ldr r1, [sp, #32] +1002232a: f7ff fd2d bl 10021d88 <_ftoa> +1002232e: 4602 mov r2, r0 +10022330: f016 0f20 tst.w r6, #32 +10022334: 9b09 ldr r3, [sp, #36] @ 0x24 +10022336: 9908 ldr r1, [sp, #32] +10022338: bf0c ite eq +1002233a: 2065 moveq r0, #101 @ 0x65 +1002233c: 2045 movne r0, #69 @ 0x45 +1002233e: f102 0801 add.w r8, r2, #1 +10022342: 47b8 blx r7 +10022344: 9a0c ldr r2, [sp, #48] @ 0x30 +10022346: 9b12 ldr r3, [sp, #72] @ 0x48 +10022348: ac16 add r4, sp, #88 @ 0x58 +1002234a: 1e5d subs r5, r3, #1 +1002234c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10022350: eba3 73e2 sub.w r3, r3, r2, asr #31 +10022354: 0fd1 lsrs r1, r2, #31 +10022356: 2600 movs r6, #0 +10022358: 4622 mov r2, r4 +1002235a: 4699 mov r9, r3 +1002235c: f8df c104 ldr.w ip, [pc, #260] @ 10022464 <_etoa+0x21c> +10022360: e001 b.n 10022366 <_etoa+0x11e> +10022362: 2e20 cmp r6, #32 +10022364: d010 beq.n 10022388 <_etoa+0x140> +10022366: 46ce mov lr, r9 +10022368: fbac 3009 umull r3, r0, ip, r9 +1002236c: 08c0 lsrs r0, r0, #3 +1002236e: eb00 0380 add.w r3, r0, r0, lsl #2 +10022372: eba9 0343 sub.w r3, r9, r3, lsl #1 +10022376: 3330 adds r3, #48 @ 0x30 +10022378: f1be 0f09 cmp.w lr, #9 +1002237c: 4681 mov r9, r0 +1002237e: f106 0601 add.w r6, r6, #1 +10022382: f802 3b01 strb.w r3, [r2], #1 +10022386: d8ec bhi.n 10022362 <_etoa+0x11a> +10022388: 2305 movs r3, #5 +1002238a: 2000 movs r0, #0 +1002238c: 9306 str r3, [sp, #24] +1002238e: 230a movs r3, #10 +10022390: 9505 str r5, [sp, #20] +10022392: 9400 str r4, [sp, #0] +10022394: 9d09 ldr r5, [sp, #36] @ 0x24 +10022396: 9c08 ldr r4, [sp, #32] +10022398: 4642 mov r2, r8 +1002239a: e9cd 3003 strd r3, r0, [sp, #12] +1002239e: e9cd 6101 strd r6, r1, [sp, #4] +100223a2: 462b mov r3, r5 +100223a4: 4621 mov r1, r4 +100223a6: 4638 mov r0, r7 +100223a8: f7ff fbfa bl 10021ba0 <_ntoa_format> +100223ac: 9a10 ldr r2, [sp, #64] @ 0x40 +100223ae: 4680 mov r8, r0 +100223b0: b1d2 cbz r2, 100223e8 <_etoa+0x1a0> +100223b2: eba0 060b sub.w r6, r0, fp +100223b6: 45b2 cmp sl, r6 +100223b8: d916 bls.n 100223e8 <_etoa+0x1a0> +100223ba: eb0b 0206 add.w r2, fp, r6 +100223be: 462b mov r3, r5 +100223c0: 4621 mov r1, r4 +100223c2: 2020 movs r0, #32 +100223c4: 3601 adds r6, #1 +100223c6: 47b8 blx r7 +100223c8: 45b2 cmp sl, r6 +100223ca: d8f6 bhi.n 100223ba <_etoa+0x172> +100223cc: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +100223d0: 4453 add r3, sl +100223d2: f1cb 0201 rsb r2, fp, #1 +100223d6: eba3 0308 sub.w r3, r3, r8 +100223da: 4442 add r2, r8 +100223dc: 4592 cmp sl, r2 +100223de: bf38 it cc +100223e0: 2300 movcc r3, #0 +100223e2: f108 0801 add.w r8, r8, #1 +100223e6: 4498 add r8, r3 +100223e8: 4640 mov r0, r8 +100223ea: b01f add sp, #124 @ 0x7c +100223ec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100223f0: 465a mov r2, fp +100223f2: 4638 mov r0, r7 +100223f4: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100223f8: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +100223fc: 9c0e ldr r4, [sp, #56] @ 0x38 +100223fe: 9b09 ldr r3, [sp, #36] @ 0x24 +10022400: 9908 ldr r1, [sp, #32] +10022402: 942a str r4, [sp, #168] @ 0xa8 +10022404: b01f add sp, #124 @ 0x7c +10022406: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1002240a: f7ff bcbd b.w 10021d88 <_ftoa> +1002240e: ea58 0309 orrs.w r3, r8, r9 +10022412: d12b bne.n 1002246c <_etoa+0x224> +10022414: 2a00 cmp r2, #0 +10022416: f43f af62 beq.w 100222de <_etoa+0x96> +1002241a: 2300 movs r3, #0 +1002241c: 930c str r3, [sp, #48] @ 0x30 +1002241e: 9b0e ldr r3, [sp, #56] @ 0x38 +10022420: 9a0c ldr r2, [sp, #48] @ 0x30 +10022422: 4293 cmp r3, r2 +10022424: f300 81b9 bgt.w 1002279a <_etoa+0x552> +10022428: f04f 0800 mov.w r8, #0 +1002242c: 4620 mov r0, r4 +1002242e: 4629 mov r1, r5 +10022430: 2200 movs r2, #0 +10022432: 2300 movs r3, #0 +10022434: f7ff fb18 bl 10021a68 <__wrap___aeabi_dcmplt> +10022438: 2800 cmp r0, #0 +1002243a: f040 8113 bne.w 10022664 <_etoa+0x41c> +1002243e: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10022442: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10022446: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1002244a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1002244e: 465a mov r2, fp +10022450: 4638 mov r0, r7 +10022452: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10022456: 9b09 ldr r3, [sp, #36] @ 0x24 +10022458: 9908 ldr r1, [sp, #32] +1002245a: 962c str r6, [sp, #176] @ 0xb0 +1002245c: e7d2 b.n 10022404 <_etoa+0x1bc> +1002245e: bf00 nop +10022460: 7fefffff .word 0x7fefffff +10022464: cccccccd .word 0xcccccccd +10022468: 2306 movs r3, #6 +1002246a: 930e str r3, [sp, #56] @ 0x38 +1002246c: f3c9 500a ubfx r0, r9, #20, #11 +10022470: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10022474: f7ff fa9e bl 100219b4 <__wrap___aeabi_i2d> +10022478: a3c1 add r3, pc, #772 @ (adr r3, 10022780 <_etoa+0x538>) +1002247a: e9d3 2300 ldrd r2, r3, [r3] +1002247e: f7ff fa25 bl 100218cc <__wrap___aeabi_dmul> +10022482: a3c1 add r3, pc, #772 @ (adr r3, 10022788 <_etoa+0x540>) +10022484: e9d3 2300 ldrd r2, r3, [r3] +10022488: f7ff f9f8 bl 1002187c <__wrap___aeabi_dadd> +1002248c: f3c9 0913 ubfx r9, r9, #0, #20 +10022490: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10022494: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10022498: 4640 mov r0, r8 +1002249a: 2200 movs r2, #0 +1002249c: 4bb2 ldr r3, [pc, #712] @ (10022768 <_etoa+0x520>) +1002249e: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +100224a2: f7ff f9ff bl 100218a4 <__wrap___aeabi_dsub> +100224a6: a3a4 add r3, pc, #656 @ (adr r3, 10022738 <_etoa+0x4f0>) +100224a8: e9d3 2300 ldrd r2, r3, [r3] +100224ac: f7ff fa0e bl 100218cc <__wrap___aeabi_dmul> +100224b0: 4602 mov r2, r0 +100224b2: 460b mov r3, r1 +100224b4: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +100224b8: f7ff f9e0 bl 1002187c <__wrap___aeabi_dadd> +100224bc: f7ff fa9e bl 100219fc <__wrap___aeabi_d2iz> +100224c0: 900c str r0, [sp, #48] @ 0x30 +100224c2: f7ff fa77 bl 100219b4 <__wrap___aeabi_i2d> +100224c6: a39e add r3, pc, #632 @ (adr r3, 10022740 <_etoa+0x4f8>) +100224c8: e9d3 2300 ldrd r2, r3, [r3] +100224cc: 4680 mov r8, r0 +100224ce: 4689 mov r9, r1 +100224d0: f7ff f9fc bl 100218cc <__wrap___aeabi_dmul> +100224d4: 2200 movs r2, #0 +100224d6: 4ba5 ldr r3, [pc, #660] @ (1002276c <_etoa+0x524>) +100224d8: f7ff f9d0 bl 1002187c <__wrap___aeabi_dadd> +100224dc: f7ff fa8e bl 100219fc <__wrap___aeabi_d2iz> +100224e0: 4603 mov r3, r0 +100224e2: 4649 mov r1, r9 +100224e4: 4640 mov r0, r8 +100224e6: 9312 str r3, [sp, #72] @ 0x48 +100224e8: a397 add r3, pc, #604 @ (adr r3, 10022748 <_etoa+0x500>) +100224ea: e9d3 2300 ldrd r2, r3, [r3] +100224ee: f7ff f9ed bl 100218cc <__wrap___aeabi_dmul> +100224f2: 4680 mov r8, r0 +100224f4: 9812 ldr r0, [sp, #72] @ 0x48 +100224f6: 4689 mov r9, r1 +100224f8: f7ff fa5c bl 100219b4 <__wrap___aeabi_i2d> +100224fc: a394 add r3, pc, #592 @ (adr r3, 10022750 <_etoa+0x508>) +100224fe: e9d3 2300 ldrd r2, r3, [r3] +10022502: f7ff f9e3 bl 100218cc <__wrap___aeabi_dmul> +10022506: 4602 mov r2, r0 +10022508: 460b mov r3, r1 +1002250a: 4640 mov r0, r8 +1002250c: 4649 mov r1, r9 +1002250e: f7ff f9c9 bl 100218a4 <__wrap___aeabi_dsub> +10022512: 4602 mov r2, r0 +10022514: 460b mov r3, r1 +10022516: 4680 mov r8, r0 +10022518: 4689 mov r9, r1 +1002251a: f7ff f9d7 bl 100218cc <__wrap___aeabi_dmul> +1002251e: 4642 mov r2, r8 +10022520: 464b mov r3, r9 +10022522: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +10022526: 4640 mov r0, r8 +10022528: 4649 mov r1, r9 +1002252a: f7ff f9a7 bl 1002187c <__wrap___aeabi_dadd> +1002252e: 2200 movs r2, #0 +10022530: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +10022534: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10022538: 4b8d ldr r3, [pc, #564] @ (10022770 <_etoa+0x528>) +1002253a: f7ff f9ed bl 10021918 <__wrap___aeabi_ddiv> +1002253e: 2200 movs r2, #0 +10022540: 4b8c ldr r3, [pc, #560] @ (10022774 <_etoa+0x52c>) +10022542: f7ff f99b bl 1002187c <__wrap___aeabi_dadd> +10022546: 4602 mov r2, r0 +10022548: 460b mov r3, r1 +1002254a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1002254e: f7ff f9e3 bl 10021918 <__wrap___aeabi_ddiv> +10022552: 2200 movs r2, #0 +10022554: 4b88 ldr r3, [pc, #544] @ (10022778 <_etoa+0x530>) +10022556: f7ff f991 bl 1002187c <__wrap___aeabi_dadd> +1002255a: 4602 mov r2, r0 +1002255c: 460b mov r3, r1 +1002255e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10022562: f7ff f9d9 bl 10021918 <__wrap___aeabi_ddiv> +10022566: 4642 mov r2, r8 +10022568: 464b mov r3, r9 +1002256a: 4680 mov r8, r0 +1002256c: 4689 mov r9, r1 +1002256e: 2000 movs r0, #0 +10022570: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10022574: f7ff f996 bl 100218a4 <__wrap___aeabi_dsub> +10022578: 4602 mov r2, r0 +1002257a: 460b mov r3, r1 +1002257c: 4640 mov r0, r8 +1002257e: 4649 mov r1, r9 +10022580: f7ff f97c bl 1002187c <__wrap___aeabi_dadd> +10022584: 4602 mov r2, r0 +10022586: 460b mov r3, r1 +10022588: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1002258c: f7ff f9c4 bl 10021918 <__wrap___aeabi_ddiv> +10022590: 2200 movs r2, #0 +10022592: 4b7a ldr r3, [pc, #488] @ (1002277c <_etoa+0x534>) +10022594: f7ff f972 bl 1002187c <__wrap___aeabi_dadd> +10022598: 9b12 ldr r3, [sp, #72] @ 0x48 +1002259a: 2200 movs r2, #0 +1002259c: f203 3cff addw ip, r3, #1023 @ 0x3ff +100225a0: ea4f 530c mov.w r3, ip, lsl #20 +100225a4: f7ff f992 bl 100218cc <__wrap___aeabi_dmul> +100225a8: 4680 mov r8, r0 +100225aa: 4689 mov r9, r1 +100225ac: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100225b0: 4642 mov r2, r8 +100225b2: 464b mov r3, r9 +100225b4: f7ff fa58 bl 10021a68 <__wrap___aeabi_dcmplt> +100225b8: b150 cbz r0, 100225d0 <_etoa+0x388> +100225ba: 9b0c ldr r3, [sp, #48] @ 0x30 +100225bc: 4640 mov r0, r8 +100225be: 3b01 subs r3, #1 +100225c0: 4649 mov r1, r9 +100225c2: 930c str r3, [sp, #48] @ 0x30 +100225c4: 2200 movs r2, #0 +100225c6: 4b6b ldr r3, [pc, #428] @ (10022774 <_etoa+0x52c>) +100225c8: f7ff f9a6 bl 10021918 <__wrap___aeabi_ddiv> +100225cc: 4680 mov r8, r0 +100225ce: 4689 mov r9, r1 +100225d0: 9a0c ldr r2, [sp, #48] @ 0x30 +100225d2: 4643 mov r3, r8 +100225d4: 3263 adds r2, #99 @ 0x63 +100225d6: 2ac6 cmp r2, #198 @ 0xc6 +100225d8: f006 0202 and.w r2, r6, #2 +100225dc: 9210 str r2, [sp, #64] @ 0x40 +100225de: 4649 mov r1, r9 +100225e0: 9a0f ldr r2, [sp, #60] @ 0x3c +100225e2: d82c bhi.n 1002263e <_etoa+0x3f6> +100225e4: 2a00 cmp r2, #0 +100225e6: d05e beq.n 100226a6 <_etoa+0x45e> +100225e8: 2204 movs r2, #4 +100225ea: 9212 str r2, [sp, #72] @ 0x48 +100225ec: 430b orrs r3, r1 +100225ee: f43f af16 beq.w 1002241e <_etoa+0x1d6> +100225f2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100225f6: a358 add r3, pc, #352 @ (adr r3, 10022758 <_etoa+0x510>) +100225f8: e9d3 2300 ldrd r2, r3, [r3] +100225fc: f7ff fa5c bl 10021ab8 <__wrap___aeabi_dcmpge> +10022600: b148 cbz r0, 10022616 <_etoa+0x3ce> +10022602: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10022606: a356 add r3, pc, #344 @ (adr r3, 10022760 <_etoa+0x518>) +10022608: e9d3 2300 ldrd r2, r3, [r3] +1002260c: f7ff fa2c bl 10021a68 <__wrap___aeabi_dcmplt> +10022610: 2800 cmp r0, #0 +10022612: f47f af04 bne.w 1002241e <_etoa+0x1d6> +10022616: 9b0e ldr r3, [sp, #56] @ 0x38 +10022618: 2b00 cmp r3, #0 +1002261a: d050 beq.n 100226be <_etoa+0x476> +1002261c: 9a13 ldr r2, [sp, #76] @ 0x4c +1002261e: 2a00 cmp r2, #0 +10022620: d07d beq.n 1002271e <_etoa+0x4d6> +10022622: 3b01 subs r3, #1 +10022624: 930e str r3, [sp, #56] @ 0x38 +10022626: 9b12 ldr r3, [sp, #72] @ 0x48 +10022628: 459a cmp sl, r3 +1002262a: d905 bls.n 10022638 <_etoa+0x3f0> +1002262c: 9b10 ldr r3, [sp, #64] @ 0x40 +1002262e: 2b00 cmp r3, #0 +10022630: f000 80ae beq.w 10022790 <_etoa+0x548> +10022634: 2302 movs r3, #2 +10022636: 9310 str r3, [sp, #64] @ 0x40 +10022638: 2300 movs r3, #0 +1002263a: 930f str r3, [sp, #60] @ 0x3c +1002263c: e044 b.n 100226c8 <_etoa+0x480> +1002263e: bb22 cbnz r2, 1002268a <_etoa+0x442> +10022640: f1ba 0f05 cmp.w sl, #5 +10022644: d94f bls.n 100226e6 <_etoa+0x49e> +10022646: f006 0302 and.w r3, r6, #2 +1002264a: 2b00 cmp r3, #0 +1002264c: d149 bne.n 100226e2 <_etoa+0x49a> +1002264e: 2305 movs r3, #5 +10022650: 9312 str r3, [sp, #72] @ 0x48 +10022652: f1aa 0305 sub.w r3, sl, #5 +10022656: 930f str r3, [sp, #60] @ 0x3c +10022658: e03a b.n 100226d0 <_etoa+0x488> +1002265a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1002265e: 940a str r4, [sp, #40] @ 0x28 +10022660: 930b str r3, [sp, #44] @ 0x2c +10022662: e627 b.n 100222b4 <_etoa+0x6c> +10022664: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10022668: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1002266c: 4638 mov r0, r7 +1002266e: 962c str r6, [sp, #176] @ 0xb0 +10022670: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10022674: 4634 mov r4, r6 +10022676: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1002267a: 465a mov r2, fp +1002267c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10022680: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10022684: 9b09 ldr r3, [sp, #36] @ 0x24 +10022686: 9908 ldr r1, [sp, #32] +10022688: e6bc b.n 10022404 <_etoa+0x1bc> +1002268a: 2205 movs r2, #5 +1002268c: 9212 str r2, [sp, #72] @ 0x48 +1002268e: e7ad b.n 100225ec <_etoa+0x3a4> +10022690: 2300 movs r3, #0 +10022692: 2202 movs r2, #2 +10022694: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10022698: 2204 movs r2, #4 +1002269a: 930c str r3, [sp, #48] @ 0x30 +1002269c: 9212 str r2, [sp, #72] @ 0x48 +1002269e: e62c b.n 100222fa <_etoa+0xb2> +100226a0: f04f 0805 mov.w r8, #5 +100226a4: e6c2 b.n 1002242c <_etoa+0x1e4> +100226a6: f1ba 0f04 cmp.w sl, #4 +100226aa: d91f bls.n 100226ec <_etoa+0x4a4> +100226ac: 9b10 ldr r3, [sp, #64] @ 0x40 +100226ae: 2b00 cmp r3, #0 +100226b0: d178 bne.n 100227a4 <_etoa+0x55c> +100226b2: 2304 movs r3, #4 +100226b4: 9312 str r3, [sp, #72] @ 0x48 +100226b6: f1aa 0304 sub.w r3, sl, #4 +100226ba: 930f str r3, [sp, #60] @ 0x3c +100226bc: e004 b.n 100226c8 <_etoa+0x480> +100226be: 9b12 ldr r3, [sp, #72] @ 0x48 +100226c0: 459a cmp sl, r3 +100226c2: d831 bhi.n 10022728 <_etoa+0x4e0> +100226c4: 9b0e ldr r3, [sp, #56] @ 0x38 +100226c6: 930f str r3, [sp, #60] @ 0x3c +100226c8: 9b0c ldr r3, [sp, #48] @ 0x30 +100226ca: 2b00 cmp r3, #0 +100226cc: f43f ae15 beq.w 100222fa <_etoa+0xb2> +100226d0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100226d4: 4642 mov r2, r8 +100226d6: 464b mov r3, r9 +100226d8: f7ff f91e bl 10021918 <__wrap___aeabi_ddiv> +100226dc: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100226e0: e60b b.n 100222fa <_etoa+0xb2> +100226e2: 2302 movs r3, #2 +100226e4: 9310 str r3, [sp, #64] @ 0x40 +100226e6: 2305 movs r3, #5 +100226e8: 9312 str r3, [sp, #72] @ 0x48 +100226ea: e7f1 b.n 100226d0 <_etoa+0x488> +100226ec: 2304 movs r3, #4 +100226ee: 9312 str r3, [sp, #72] @ 0x48 +100226f0: e7ea b.n 100226c8 <_etoa+0x480> +100226f2: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100226f6: 46a0 mov r8, r4 +100226f8: 9b0f ldr r3, [sp, #60] @ 0x3c +100226fa: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +100226fe: 9303 str r3, [sp, #12] +10022700: 9b0e ldr r3, [sp, #56] @ 0x38 +10022702: 465a mov r2, fp +10022704: 9302 str r3, [sp, #8] +10022706: f426 6300 bic.w r3, r6, #2048 @ 0x800 +1002270a: 9304 str r3, [sp, #16] +1002270c: 4638 mov r0, r7 +1002270e: e9cd 8900 strd r8, r9, [sp] +10022712: 9b09 ldr r3, [sp, #36] @ 0x24 +10022714: 9908 ldr r1, [sp, #32] +10022716: f7ff fb37 bl 10021d88 <_ftoa> +1002271a: 4602 mov r2, r0 +1002271c: e608 b.n 10022330 <_etoa+0xe8> +1002271e: 9b12 ldr r3, [sp, #72] @ 0x48 +10022720: 459a cmp sl, r3 +10022722: d844 bhi.n 100227ae <_etoa+0x566> +10022724: 920f str r2, [sp, #60] @ 0x3c +10022726: e7cf b.n 100226c8 <_etoa+0x480> +10022728: 9b10 ldr r3, [sp, #64] @ 0x40 +1002272a: b38b cbz r3, 10022790 <_etoa+0x548> +1002272c: 9b0e ldr r3, [sp, #56] @ 0x38 +1002272e: 930f str r3, [sp, #60] @ 0x3c +10022730: 2302 movs r3, #2 +10022732: 9310 str r3, [sp, #64] @ 0x40 +10022734: e7c8 b.n 100226c8 <_etoa+0x480> +10022736: bf00 nop +10022738: 636f4361 .word 0x636f4361 +1002273c: 3fd287a7 .word 0x3fd287a7 +10022740: 0979a371 .word 0x0979a371 +10022744: 400a934f .word 0x400a934f +10022748: bbb55516 .word 0xbbb55516 +1002274c: 40026bb1 .word 0x40026bb1 +10022750: fefa39ef .word 0xfefa39ef +10022754: 3fe62e42 .word 0x3fe62e42 +10022758: eb1c432d .word 0xeb1c432d +1002275c: 3f1a36e2 .word 0x3f1a36e2 +10022760: 00000000 .word 0x00000000 +10022764: 412e8480 .word 0x412e8480 +10022768: 3ff80000 .word 0x3ff80000 +1002276c: 3fe00000 .word 0x3fe00000 +10022770: 402c0000 .word 0x402c0000 +10022774: 40240000 .word 0x40240000 +10022778: 40180000 .word 0x40180000 +1002277c: 3ff00000 .word 0x3ff00000 +10022780: 509f79fb .word 0x509f79fb +10022784: 3fd34413 .word 0x3fd34413 +10022788: 8b60c8b3 .word 0x8b60c8b3 +1002278c: 3fc68a28 .word 0x3fc68a28 +10022790: 9b12 ldr r3, [sp, #72] @ 0x48 +10022792: ebaa 0303 sub.w r3, sl, r3 +10022796: 930f str r3, [sp, #60] @ 0x3c +10022798: e796 b.n 100226c8 <_etoa+0x480> +1002279a: eba3 0802 sub.w r8, r3, r2 +1002279e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100227a2: e643 b.n 1002242c <_etoa+0x1e4> +100227a4: 2304 movs r3, #4 +100227a6: 9312 str r3, [sp, #72] @ 0x48 +100227a8: 2302 movs r3, #2 +100227aa: 9310 str r3, [sp, #64] @ 0x40 +100227ac: e78c b.n 100226c8 <_etoa+0x480> +100227ae: 9b10 ldr r3, [sp, #64] @ 0x40 +100227b0: 2b00 cmp r3, #0 +100227b2: d0ed beq.n 10022790 <_etoa+0x548> +100227b4: 2302 movs r3, #2 +100227b6: 920f str r2, [sp, #60] @ 0x3c +100227b8: 9310 str r3, [sp, #64] @ 0x40 +100227ba: e785 b.n 100226c8 <_etoa+0x480> + +100227bc <_vsnprintf>: +100227bc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100227c0: b09b sub sp, #108 @ 0x6c +100227c2: 9c24 ldr r4, [sp, #144] @ 0x90 +100227c4: 4d95 ldr r5, [pc, #596] @ (10022a1c <_vsnprintf+0x260>) +100227c6: 940a str r4, [sp, #40] @ 0x28 +100227c8: 4c95 ldr r4, [pc, #596] @ (10022a20 <_vsnprintf+0x264>) +100227ca: f1b1 0a00 subs.w sl, r1, #0 +100227ce: bf18 it ne +100227d0: 4683 movne fp, r0 +100227d2: 6025 str r5, [r4, #0] +100227d4: 7818 ldrb r0, [r3, #0] +100227d6: 4c93 ldr r4, [pc, #588] @ (10022a24 <_vsnprintf+0x268>) +100227d8: 4691 mov r9, r2 +100227da: bf08 it eq +100227dc: 46a3 moveq fp, r4 +100227de: 9309 str r3, [sp, #36] @ 0x24 +100227e0: 2800 cmp r0, #0 +100227e2: f000 8293 beq.w 10022d0c <_vsnprintf+0x550> +100227e6: f04f 0800 mov.w r8, #0 +100227ea: e00a b.n 10022802 <_vsnprintf+0x46> +100227ec: 4642 mov r2, r8 +100227ee: 464b mov r3, r9 +100227f0: 4651 mov r1, sl +100227f2: f108 0801 add.w r8, r8, #1 +100227f6: 47d8 blx fp +100227f8: 9b09 ldr r3, [sp, #36] @ 0x24 +100227fa: 7818 ldrb r0, [r3, #0] +100227fc: 2800 cmp r0, #0 +100227fe: f000 80ce beq.w 1002299e <_vsnprintf+0x1e2> +10022802: 9b09 ldr r3, [sp, #36] @ 0x24 +10022804: 2825 cmp r0, #37 @ 0x25 +10022806: f103 0301 add.w r3, r3, #1 +1002280a: 9309 str r3, [sp, #36] @ 0x24 +1002280c: d1ee bne.n 100227ec <_vsnprintf+0x30> +1002280e: 461c mov r4, r3 +10022810: 2300 movs r3, #0 +10022812: 4622 mov r2, r4 +10022814: f812 0b01 ldrb.w r0, [r2], #1 +10022818: f1a0 0120 sub.w r1, r0, #32 +1002281c: 2910 cmp r1, #16 +1002281e: d80a bhi.n 10022836 <_vsnprintf+0x7a> +10022820: e8df f001 tbb [pc, r1] +10022824: 3c090940 .word 0x3c090940 +10022828: 09090909 .word 0x09090909 +1002282c: 38090909 .word 0x38090909 +10022830: 09093409 .word 0x09093409 +10022834: 30 .byte 0x30 +10022835: 00 .byte 0x00 +10022836: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1002283a: 2909 cmp r1, #9 +1002283c: 9409 str r4, [sp, #36] @ 0x24 +1002283e: f240 808a bls.w 10022956 <_vsnprintf+0x19a> +10022842: 282a cmp r0, #42 @ 0x2a +10022844: f000 80f0 beq.w 10022a28 <_vsnprintf+0x26c> +10022848: 2500 movs r5, #0 +1002284a: 282e cmp r0, #46 @ 0x2e +1002284c: f000 8096 beq.w 1002297c <_vsnprintf+0x1c0> +10022850: 2600 movs r6, #0 +10022852: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10022856: 2912 cmp r1, #18 +10022858: d82d bhi.n 100228b6 <_vsnprintf+0xfa> +1002285a: e8df f011 tbh [pc, r1, lsl #1] +1002285e: 0149 .short 0x0149 +10022860: 0143002c .word 0x0143002c +10022864: 0138002c .word 0x0138002c +10022868: 002c002c .word 0x002c002c +1002286c: 002c002c .word 0x002c002c +10022870: 002c002c .word 0x002c002c +10022874: 0027002c .word 0x0027002c +10022878: 002c002c .word 0x002c002c +1002287c: 002c002c .word 0x002c002c +10022880: 0027002c .word 0x0027002c +10022884: 4614 mov r4, r2 +10022886: f043 0301 orr.w r3, r3, #1 +1002288a: e7c2 b.n 10022812 <_vsnprintf+0x56> +1002288c: 4614 mov r4, r2 +1002288e: f043 0302 orr.w r3, r3, #2 +10022892: e7be b.n 10022812 <_vsnprintf+0x56> +10022894: 4614 mov r4, r2 +10022896: f043 0304 orr.w r3, r3, #4 +1002289a: e7ba b.n 10022812 <_vsnprintf+0x56> +1002289c: 4614 mov r4, r2 +1002289e: f043 0310 orr.w r3, r3, #16 +100228a2: e7b6 b.n 10022812 <_vsnprintf+0x56> +100228a4: 4614 mov r4, r2 +100228a6: f043 0308 orr.w r3, r3, #8 +100228aa: e7b2 b.n 10022812 <_vsnprintf+0x56> +100228ac: 9909 ldr r1, [sp, #36] @ 0x24 +100228ae: 7848 ldrb r0, [r1, #1] +100228b0: f443 7380 orr.w r3, r3, #256 @ 0x100 +100228b4: 3201 adds r2, #1 +100228b6: 2867 cmp r0, #103 @ 0x67 +100228b8: 9209 str r2, [sp, #36] @ 0x24 +100228ba: d87e bhi.n 100229ba <_vsnprintf+0x1fe> +100228bc: 2824 cmp r0, #36 @ 0x24 +100228be: f240 80c1 bls.w 10022a44 <_vsnprintf+0x288> +100228c2: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +100228c6: 2a42 cmp r2, #66 @ 0x42 +100228c8: f200 80bc bhi.w 10022a44 <_vsnprintf+0x288> +100228cc: e8df f012 tbh [pc, r2, lsl #1] +100228d0: 00ba0150 .word 0x00ba0150 +100228d4: 00ba00ba .word 0x00ba00ba +100228d8: 00ba00ba .word 0x00ba00ba +100228dc: 00ba00ba .word 0x00ba00ba +100228e0: 00ba00ba .word 0x00ba00ba +100228e4: 00ba00ba .word 0x00ba00ba +100228e8: 00ba00ba .word 0x00ba00ba +100228ec: 00ba00ba .word 0x00ba00ba +100228f0: 00ba00ba .word 0x00ba00ba +100228f4: 00ba00ba .word 0x00ba00ba +100228f8: 00ba00ba .word 0x00ba00ba +100228fc: 00ba00ba .word 0x00ba00ba +10022900: 00ba00ba .word 0x00ba00ba +10022904: 00ba00ba .word 0x00ba00ba +10022908: 00ba00ba .word 0x00ba00ba +1002290c: 00ba00ba .word 0x00ba00ba +10022910: 01370119 .word 0x01370119 +10022914: 00ba0119 .word 0x00ba0119 +10022918: 00ba00ba .word 0x00ba00ba +1002291c: 00ba00ba .word 0x00ba00ba +10022920: 00ba00ba .word 0x00ba00ba +10022924: 00ba00ba .word 0x00ba00ba +10022928: 00ba00ba .word 0x00ba00ba +1002292c: 00ba00ba .word 0x00ba00ba +10022930: 00ba00ba .word 0x00ba00ba +10022934: 01bc00ba .word 0x01bc00ba +10022938: 00ba00ba .word 0x00ba00ba +1002293c: 00ba00ba .word 0x00ba00ba +10022940: 00ba00ba .word 0x00ba00ba +10022944: 00ba00ba .word 0x00ba00ba +10022948: 01bc00ba .word 0x01bc00ba +1002294c: 01bc0158 .word 0x01bc0158 +10022950: 01370119 .word 0x01370119 +10022954: 0119 .short 0x0119 +10022956: 2500 movs r5, #0 +10022958: e000 b.n 1002295c <_vsnprintf+0x1a0> +1002295a: 3201 adds r2, #1 +1002295c: eb05 0585 add.w r5, r5, r5, lsl #2 +10022960: eb00 0545 add.w r5, r0, r5, lsl #1 +10022964: 7810 ldrb r0, [r2, #0] +10022966: 3d30 subs r5, #48 @ 0x30 +10022968: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1002296c: 2909 cmp r1, #9 +1002296e: d9f4 bls.n 1002295a <_vsnprintf+0x19e> +10022970: 282e cmp r0, #46 @ 0x2e +10022972: 9209 str r2, [sp, #36] @ 0x24 +10022974: f102 0201 add.w r2, r2, #1 +10022978: f47f af6a bne.w 10022850 <_vsnprintf+0x94> +1002297c: 9909 ldr r1, [sp, #36] @ 0x24 +1002297e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10022982: 7848 ldrb r0, [r1, #1] +10022984: 4611 mov r1, r2 +10022986: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1002298a: 2e09 cmp r6, #9 +1002298c: f240 8121 bls.w 10022bd2 <_vsnprintf+0x416> +10022990: 282a cmp r0, #42 @ 0x2a +10022992: f000 812f beq.w 10022bf4 <_vsnprintf+0x438> +10022996: 9209 str r2, [sp, #36] @ 0x24 +10022998: 2600 movs r6, #0 +1002299a: 3201 adds r2, #1 +1002299c: e759 b.n 10022852 <_vsnprintf+0x96> +1002299e: 4644 mov r4, r8 +100229a0: 45c1 cmp r9, r8 +100229a2: d801 bhi.n 100229a8 <_vsnprintf+0x1ec> +100229a4: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +100229a8: 464b mov r3, r9 +100229aa: 4642 mov r2, r8 +100229ac: 4651 mov r1, sl +100229ae: 2000 movs r0, #0 +100229b0: 47d8 blx fp +100229b2: 4620 mov r0, r4 +100229b4: b01b add sp, #108 @ 0x6c +100229b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100229ba: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +100229be: b2d2 uxtb r2, r2 +100229c0: 2a0f cmp r2, #15 +100229c2: d83f bhi.n 10022a44 <_vsnprintf+0x288> +100229c4: 2101 movs r1, #1 +100229c6: f249 0741 movw r7, #36929 @ 0x9041 +100229ca: 4091 lsls r1, r2 +100229cc: 4039 ands r1, r7 +100229ce: f040 80f3 bne.w 10022bb8 <_vsnprintf+0x3fc> +100229d2: 2a0a cmp r2, #10 +100229d4: d03d beq.n 10022a52 <_vsnprintf+0x296> +100229d6: 2a07 cmp r2, #7 +100229d8: d134 bne.n 10022a44 <_vsnprintf+0x288> +100229da: 9d0a ldr r5, [sp, #40] @ 0x28 +100229dc: f855 2b04 ldr.w r2, [r5], #4 +100229e0: 2a00 cmp r2, #0 +100229e2: f000 8113 beq.w 10022c0c <_vsnprintf+0x450> +100229e6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100229ea: ab12 add r3, sp, #72 @ 0x48 +100229ec: 461f mov r7, r3 +100229ee: 930b str r3, [sp, #44] @ 0x2c +100229f0: e003 b.n 100229fa <_vsnprintf+0x23e> +100229f2: 2920 cmp r1, #32 +100229f4: f000 8114 beq.w 10022c20 <_vsnprintf+0x464> +100229f8: 461a mov r2, r3 +100229fa: f002 040f and.w r4, r2, #15 +100229fe: 4623 mov r3, r4 +10022a00: 2c09 cmp r4, #9 +10022a02: bf94 ite ls +10022a04: 3330 addls r3, #48 @ 0x30 +10022a06: 3337 addhi r3, #55 @ 0x37 +10022a08: 2a0f cmp r2, #15 +10022a0a: f807 3b01 strb.w r3, [r7], #1 +10022a0e: f101 0101 add.w r1, r1, #1 +10022a12: ea4f 1312 mov.w r3, r2, lsr #4 +10022a16: d8ec bhi.n 100229f2 <_vsnprintf+0x236> +10022a18: e102 b.n 10022c20 <_vsnprintf+0x464> +10022a1a: bf00 nop +10022a1c: 100227bd .word 0x100227bd +10022a20: 20002a3c .word 0x20002a3c +10022a24: 10021b01 .word 0x10021b01 +10022a28: 990a ldr r1, [sp, #40] @ 0x28 +10022a2a: 9809 ldr r0, [sp, #36] @ 0x24 +10022a2c: f851 5b04 ldr.w r5, [r1], #4 +10022a30: 7840 ldrb r0, [r0, #1] +10022a32: 2d00 cmp r5, #0 +10022a34: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +10022a38: bfbc itt lt +10022a3a: f043 0302 orrlt.w r3, r3, #2 +10022a3e: 426d neglt r5, r5 +10022a40: 3201 adds r2, #1 +10022a42: e702 b.n 1002284a <_vsnprintf+0x8e> +10022a44: 4642 mov r2, r8 +10022a46: 464b mov r3, r9 +10022a48: 4651 mov r1, sl +10022a4a: f108 0801 add.w r8, r8, #1 +10022a4e: 47d8 blx fp +10022a50: e6d2 b.n 100227f8 <_vsnprintf+0x3c> +10022a52: 990a ldr r1, [sp, #40] @ 0x28 +10022a54: 2e00 cmp r6, #0 +10022a56: f851 7b04 ldr.w r7, [r1], #4 +10022a5a: bf18 it ne +10022a5c: 4632 movne r2, r6 +10022a5e: 7838 ldrb r0, [r7, #0] +10022a60: bf08 it eq +10022a62: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10022a66: 2800 cmp r0, #0 +10022a68: f000 837b beq.w 10023162 <_vsnprintf+0x9a6> +10022a6c: 18bc adds r4, r7, r2 +10022a6e: 46a4 mov ip, r4 +10022a70: 463a mov r2, r7 +10022a72: e004 b.n 10022a7e <_vsnprintf+0x2c2> +10022a74: f812 4f01 ldrb.w r4, [r2, #1]! +10022a78: 2c00 cmp r4, #0 +10022a7a: f000 813f beq.w 10022cfc <_vsnprintf+0x540> +10022a7e: 4594 cmp ip, r2 +10022a80: d1f8 bne.n 10022a74 <_vsnprintf+0x2b8> +10022a82: 4664 mov r4, ip +10022a84: 1be4 subs r4, r4, r7 +10022a86: 055a lsls r2, r3, #21 +10022a88: f140 8122 bpl.w 10022cd0 <_vsnprintf+0x514> +10022a8c: 42b4 cmp r4, r6 +10022a8e: bf28 it cs +10022a90: 4634 movcs r4, r6 +10022a92: f013 0302 ands.w r3, r3, #2 +10022a96: f000 8288 beq.w 10022faa <_vsnprintf+0x7ee> +10022a9a: 2302 movs r3, #2 +10022a9c: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10022aa0: 4642 mov r2, r8 +10022aa2: 461d mov r5, r3 +10022aa4: 4446 add r6, r8 +10022aa6: e008 b.n 10022aba <_vsnprintf+0x2fe> +10022aa8: 464b mov r3, r9 +10022aaa: 4651 mov r1, sl +10022aac: 47d8 blx fp +10022aae: f817 0f01 ldrb.w r0, [r7, #1]! +10022ab2: f108 0801 add.w r8, r8, #1 +10022ab6: b110 cbz r0, 10022abe <_vsnprintf+0x302> +10022ab8: 4642 mov r2, r8 +10022aba: 4546 cmp r6, r8 +10022abc: d1f4 bne.n 10022aa8 <_vsnprintf+0x2ec> +10022abe: 462b mov r3, r5 +10022ac0: 990b ldr r1, [sp, #44] @ 0x2c +10022ac2: 9d0a ldr r5, [sp, #40] @ 0x28 +10022ac4: 2b00 cmp r3, #0 +10022ac6: f040 8141 bne.w 10022d4c <_vsnprintf+0x590> +10022aca: 910a str r1, [sp, #40] @ 0x28 +10022acc: e694 b.n 100227f8 <_vsnprintf+0x3c> +10022ace: 9909 ldr r1, [sp, #36] @ 0x24 +10022ad0: 7848 ldrb r0, [r1, #1] +10022ad2: 286c cmp r0, #108 @ 0x6c +10022ad4: f47f aeec bne.w 100228b0 <_vsnprintf+0xf4> +10022ad8: 460a mov r2, r1 +10022ada: 7888 ldrb r0, [r1, #2] +10022adc: f443 7340 orr.w r3, r3, #768 @ 0x300 +10022ae0: 3203 adds r2, #3 +10022ae2: e6e8 b.n 100228b6 <_vsnprintf+0xfa> +10022ae4: 9909 ldr r1, [sp, #36] @ 0x24 +10022ae6: f443 7300 orr.w r3, r3, #512 @ 0x200 +10022aea: 7848 ldrb r0, [r1, #1] +10022aec: 3201 adds r2, #1 +10022aee: e6e2 b.n 100228b6 <_vsnprintf+0xfa> +10022af0: 9909 ldr r1, [sp, #36] @ 0x24 +10022af2: 7848 ldrb r0, [r1, #1] +10022af4: 2868 cmp r0, #104 @ 0x68 +10022af6: f000 8103 beq.w 10022d00 <_vsnprintf+0x544> +10022afa: f043 0380 orr.w r3, r3, #128 @ 0x80 +10022afe: 3201 adds r2, #1 +10022b00: e6d9 b.n 100228b6 <_vsnprintf+0xfa> +10022b02: 2867 cmp r0, #103 @ 0x67 +10022b04: f000 80d9 beq.w 10022cba <_vsnprintf+0x4fe> +10022b08: 2847 cmp r0, #71 @ 0x47 +10022b0a: f000 80dc beq.w 10022cc6 <_vsnprintf+0x50a> +10022b0e: 2845 cmp r0, #69 @ 0x45 +10022b10: f000 80db beq.w 10022cca <_vsnprintf+0x50e> +10022b14: e9cd 5303 strd r5, r3, [sp, #12] +10022b18: 9b0a ldr r3, [sp, #40] @ 0x28 +10022b1a: 9602 str r6, [sp, #8] +10022b1c: 3307 adds r3, #7 +10022b1e: f023 0307 bic.w r3, r3, #7 +10022b22: 461c mov r4, r3 +10022b24: 4642 mov r2, r8 +10022b26: e8f4 6702 ldrd r6, r7, [r4], #8 +10022b2a: 464b mov r3, r9 +10022b2c: 4651 mov r1, sl +10022b2e: 4658 mov r0, fp +10022b30: e9cd 6700 strd r6, r7, [sp] +10022b34: 940a str r4, [sp, #40] @ 0x28 +10022b36: f7ff fb87 bl 10022248 <_etoa> +10022b3a: 4680 mov r8, r0 +10022b3c: e65c b.n 100227f8 <_vsnprintf+0x3c> +10022b3e: 2846 cmp r0, #70 @ 0x46 +10022b40: bf08 it eq +10022b42: f043 0320 orreq.w r3, r3, #32 +10022b46: e9cd 5303 strd r5, r3, [sp, #12] +10022b4a: 9b0a ldr r3, [sp, #40] @ 0x28 +10022b4c: 9602 str r6, [sp, #8] +10022b4e: 3307 adds r3, #7 +10022b50: f023 0307 bic.w r3, r3, #7 +10022b54: 461c mov r4, r3 +10022b56: 4642 mov r2, r8 +10022b58: e8f4 6702 ldrd r6, r7, [r4], #8 +10022b5c: 464b mov r3, r9 +10022b5e: 4651 mov r1, sl +10022b60: 4658 mov r0, fp +10022b62: e9cd 6700 strd r6, r7, [sp] +10022b66: 940a str r4, [sp, #40] @ 0x28 +10022b68: f7ff f90e bl 10021d88 <_ftoa> +10022b6c: 4680 mov r8, r0 +10022b6e: e643 b.n 100227f8 <_vsnprintf+0x3c> +10022b70: 4642 mov r2, r8 +10022b72: 464b mov r3, r9 +10022b74: 4651 mov r1, sl +10022b76: 2025 movs r0, #37 @ 0x25 +10022b78: f108 0801 add.w r8, r8, #1 +10022b7c: 47d8 blx fp +10022b7e: e63b b.n 100227f8 <_vsnprintf+0x3c> +10022b80: 9a0a ldr r2, [sp, #40] @ 0x28 +10022b82: 0799 lsls r1, r3, #30 +10022b84: f102 0404 add.w r4, r2, #4 +10022b88: f108 0601 add.w r6, r8, #1 +10022b8c: f140 80c6 bpl.w 10022d1c <_vsnprintf+0x560> +10022b90: 7810 ldrb r0, [r2, #0] +10022b92: 464b mov r3, r9 +10022b94: 4642 mov r2, r8 +10022b96: 4651 mov r1, sl +10022b98: 47d8 blx fp +10022b9a: 2d01 cmp r5, #1 +10022b9c: bf88 it hi +10022b9e: 44a8 addhi r8, r5 +10022ba0: f240 81bd bls.w 10022f1e <_vsnprintf+0x762> +10022ba4: 4632 mov r2, r6 +10022ba6: 464b mov r3, r9 +10022ba8: 4651 mov r1, sl +10022baa: 2020 movs r0, #32 +10022bac: 3601 adds r6, #1 +10022bae: 47d8 blx fp +10022bb0: 4546 cmp r6, r8 +10022bb2: d1f7 bne.n 10022ba4 <_vsnprintf+0x3e8> +10022bb4: 940a str r4, [sp, #40] @ 0x28 +10022bb6: e61f b.n 100227f8 <_vsnprintf+0x3c> +10022bb8: 286f cmp r0, #111 @ 0x6f +10022bba: f000 8081 beq.w 10022cc0 <_vsnprintf+0x504> +10022bbe: f240 8248 bls.w 10023052 <_vsnprintf+0x896> +10022bc2: 2878 cmp r0, #120 @ 0x78 +10022bc4: f000 8190 beq.w 10022ee8 <_vsnprintf+0x72c> +10022bc8: 270a movs r7, #10 +10022bca: f023 0310 bic.w r3, r3, #16 +10022bce: 46bc mov ip, r7 +10022bd0: e041 b.n 10022c56 <_vsnprintf+0x49a> +10022bd2: 2600 movs r6, #0 +10022bd4: eb06 0686 add.w r6, r6, r6, lsl #2 +10022bd8: eb00 0046 add.w r0, r0, r6, lsl #1 +10022bdc: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +10022be0: f811 0f01 ldrb.w r0, [r1, #1]! +10022be4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +10022be8: 2a09 cmp r2, #9 +10022bea: d9f3 bls.n 10022bd4 <_vsnprintf+0x418> +10022bec: 460a mov r2, r1 +10022bee: 9109 str r1, [sp, #36] @ 0x24 +10022bf0: 3201 adds r2, #1 +10022bf2: e62e b.n 10022852 <_vsnprintf+0x96> +10022bf4: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +10022bf8: f851 6b04 ldr.w r6, [r1], #4 +10022bfc: 7890 ldrb r0, [r2, #2] +10022bfe: 3202 adds r2, #2 +10022c00: 9209 str r2, [sp, #36] @ 0x24 +10022c02: 910a str r1, [sp, #40] @ 0x28 +10022c04: 3201 adds r2, #1 +10022c06: ea26 76e6 bic.w r6, r6, r6, asr #31 +10022c0a: e622 b.n 10022852 <_vsnprintf+0x96> +10022c0c: f023 0010 bic.w r0, r3, #16 +10022c10: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10022c14: f040 0021 orr.w r0, r0, #33 @ 0x21 +10022c18: f43f aee7 beq.w 100229ea <_vsnprintf+0x22e> +10022c1c: ab12 add r3, sp, #72 @ 0x48 +10022c1e: 930b str r3, [sp, #44] @ 0x2c +10022c20: 9b0b ldr r3, [sp, #44] @ 0x2c +10022c22: 9006 str r0, [sp, #24] +10022c24: 9300 str r3, [sp, #0] +10022c26: 2308 movs r3, #8 +10022c28: 2010 movs r0, #16 +10022c2a: 9305 str r3, [sp, #20] +10022c2c: 2300 movs r3, #0 +10022c2e: 4642 mov r2, r8 +10022c30: e9cd 3002 strd r3, r0, [sp, #8] +10022c34: 9101 str r1, [sp, #4] +10022c36: 464b mov r3, r9 +10022c38: 4651 mov r1, sl +10022c3a: 4658 mov r0, fp +10022c3c: 9604 str r6, [sp, #16] +10022c3e: f7fe ffaf bl 10021ba0 <_ntoa_format> +10022c42: 950a str r5, [sp, #40] @ 0x28 +10022c44: 4680 mov r8, r0 +10022c46: e5d7 b.n 100227f8 <_vsnprintf+0x3c> +10022c48: 2858 cmp r0, #88 @ 0x58 +10022c4a: d062 beq.n 10022d12 <_vsnprintf+0x556> +10022c4c: 2862 cmp r0, #98 @ 0x62 +10022c4e: f040 808f bne.w 10022d70 <_vsnprintf+0x5b4> +10022c52: 2702 movs r7, #2 +10022c54: 46bc mov ip, r7 +10022c56: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10022c5a: f000 80dd beq.w 10022e18 <_vsnprintf+0x65c> +10022c5e: f023 030d bic.w r3, r3, #13 +10022c62: f413 7200 ands.w r2, r3, #512 @ 0x200 +10022c66: f040 8181 bne.w 10022f6c <_vsnprintf+0x7b0> +10022c6a: 990a ldr r1, [sp, #40] @ 0x28 +10022c6c: 1d0f adds r7, r1, #4 +10022c6e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10022c72: f040 8237 bne.w 100230e4 <_vsnprintf+0x928> +10022c76: 065c lsls r4, r3, #25 +10022c78: 9a0a ldr r2, [sp, #40] @ 0x28 +10022c7a: f140 813b bpl.w 10022ef4 <_vsnprintf+0x738> +10022c7e: 7812 ldrb r2, [r2, #0] +10022c80: 2a00 cmp r2, #0 +10022c82: f040 814e bne.w 10022f22 <_vsnprintf+0x766> +10022c86: f023 0310 bic.w r3, r3, #16 +10022c8a: 2800 cmp r0, #0 +10022c8c: f000 8149 beq.w 10022f22 <_vsnprintf+0x766> +10022c90: 4611 mov r1, r2 +10022c92: aa12 add r2, sp, #72 @ 0x48 +10022c94: 920b str r2, [sp, #44] @ 0x2c +10022c96: e9cd 5305 strd r5, r3, [sp, #20] +10022c9a: e9cd c603 strd ip, r6, [sp, #12] +10022c9e: 9101 str r1, [sp, #4] +10022ca0: 9b0b ldr r3, [sp, #44] @ 0x2c +10022ca2: 4642 mov r2, r8 +10022ca4: 9300 str r3, [sp, #0] +10022ca6: 2300 movs r3, #0 +10022ca8: 4651 mov r1, sl +10022caa: 9302 str r3, [sp, #8] +10022cac: 4658 mov r0, fp +10022cae: 464b mov r3, r9 +10022cb0: f7fe ff76 bl 10021ba0 <_ntoa_format> +10022cb4: 970a str r7, [sp, #40] @ 0x28 +10022cb6: 4680 mov r8, r0 +10022cb8: e59e b.n 100227f8 <_vsnprintf+0x3c> +10022cba: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10022cbe: e729 b.n 10022b14 <_vsnprintf+0x358> +10022cc0: 2708 movs r7, #8 +10022cc2: 46bc mov ip, r7 +10022cc4: e7c7 b.n 10022c56 <_vsnprintf+0x49a> +10022cc6: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10022cca: f043 0320 orr.w r3, r3, #32 +10022cce: e721 b.n 10022b14 <_vsnprintf+0x358> +10022cd0: f013 0302 ands.w r3, r3, #2 +10022cd4: f000 818e beq.w 10022ff4 <_vsnprintf+0x838> +10022cd8: 2302 movs r3, #2 +10022cda: 950a str r5, [sp, #40] @ 0x28 +10022cdc: 461e mov r6, r3 +10022cde: 460d mov r5, r1 +10022ce0: 4642 mov r2, r8 +10022ce2: 464b mov r3, r9 +10022ce4: 4651 mov r1, sl +10022ce6: 47d8 blx fp +10022ce8: f817 0f01 ldrb.w r0, [r7, #1]! +10022cec: f108 0801 add.w r8, r8, #1 +10022cf0: 2800 cmp r0, #0 +10022cf2: d1f5 bne.n 10022ce0 <_vsnprintf+0x524> +10022cf4: 4629 mov r1, r5 +10022cf6: 4633 mov r3, r6 +10022cf8: 9d0a ldr r5, [sp, #40] @ 0x28 +10022cfa: e6e3 b.n 10022ac4 <_vsnprintf+0x308> +10022cfc: 1bd4 subs r4, r2, r7 +10022cfe: e6c2 b.n 10022a86 <_vsnprintf+0x2ca> +10022d00: 460a mov r2, r1 +10022d02: 7888 ldrb r0, [r1, #2] +10022d04: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10022d08: 3203 adds r2, #3 +10022d0a: e5d4 b.n 100228b6 <_vsnprintf+0xfa> +10022d0c: 4604 mov r4, r0 +10022d0e: 4680 mov r8, r0 +10022d10: e646 b.n 100229a0 <_vsnprintf+0x1e4> +10022d12: 2710 movs r7, #16 +10022d14: f043 0320 orr.w r3, r3, #32 +10022d18: 46bc mov ip, r7 +10022d1a: e79c b.n 10022c56 <_vsnprintf+0x49a> +10022d1c: 2d01 cmp r5, #1 +10022d1e: f240 80f8 bls.w 10022f12 <_vsnprintf+0x756> +10022d22: 4646 mov r6, r8 +10022d24: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10022d28: 442f add r7, r5 +10022d2a: 4632 mov r2, r6 +10022d2c: 464b mov r3, r9 +10022d2e: 4651 mov r1, sl +10022d30: 2020 movs r0, #32 +10022d32: 3601 adds r6, #1 +10022d34: 47d8 blx fp +10022d36: 42be cmp r6, r7 +10022d38: d1f7 bne.n 10022d2a <_vsnprintf+0x56e> +10022d3a: 9b0a ldr r3, [sp, #40] @ 0x28 +10022d3c: 4632 mov r2, r6 +10022d3e: 7818 ldrb r0, [r3, #0] +10022d40: 4651 mov r1, sl +10022d42: 464b mov r3, r9 +10022d44: 47d8 blx fp +10022d46: 44a8 add r8, r5 +10022d48: 940a str r4, [sp, #40] @ 0x28 +10022d4a: e555 b.n 100227f8 <_vsnprintf+0x3c> +10022d4c: 4646 mov r6, r8 +10022d4e: 42a5 cmp r5, r4 +10022d50: f67f aebb bls.w 10022aca <_vsnprintf+0x30e> +10022d54: 44a8 add r8, r5 +10022d56: eba8 0804 sub.w r8, r8, r4 +10022d5a: 460c mov r4, r1 +10022d5c: 4632 mov r2, r6 +10022d5e: 464b mov r3, r9 +10022d60: 4651 mov r1, sl +10022d62: 2020 movs r0, #32 +10022d64: 3601 adds r6, #1 +10022d66: 47d8 blx fp +10022d68: 4546 cmp r6, r8 +10022d6a: d1f7 bne.n 10022d5c <_vsnprintf+0x5a0> +10022d6c: 4621 mov r1, r4 +10022d6e: e6ac b.n 10022aca <_vsnprintf+0x30e> +10022d70: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10022d74: f000 80bb beq.w 10022eee <_vsnprintf+0x732> +10022d78: f44f 6280 mov.w r2, #1024 @ 0x400 +10022d7c: f023 0c11 bic.w ip, r3, #17 +10022d80: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10022d84: 9b0a ldr r3, [sp, #40] @ 0x28 +10022d86: d14a bne.n 10022e1e <_vsnprintf+0x662> +10022d88: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10022d8c: f103 0404 add.w r4, r3, #4 +10022d90: f040 8134 bne.w 10022ffc <_vsnprintf+0x840> +10022d94: f01c 0f40 tst.w ip, #64 @ 0x40 +10022d98: f040 80a3 bne.w 10022ee2 <_vsnprintf+0x726> +10022d9c: f01c 0f80 tst.w ip, #128 @ 0x80 +10022da0: f000 81d3 beq.w 1002314a <_vsnprintf+0x98e> +10022da4: f9b3 1000 ldrsh.w r1, [r3] +10022da8: ea81 77e1 eor.w r7, r1, r1, asr #31 +10022dac: eba7 77e1 sub.w r7, r7, r1, asr #31 +10022db0: b2bf uxth r7, r7 +10022db2: 0fcb lsrs r3, r1, #31 +10022db4: 2900 cmp r1, #0 +10022db6: f000 8156 beq.w 10023066 <_vsnprintf+0x8aa> +10022dba: 463a mov r2, r7 +10022dbc: a912 add r1, sp, #72 @ 0x48 +10022dbe: 460f mov r7, r1 +10022dc0: f8df e3d8 ldr.w lr, [pc, #984] @ 1002319c <_vsnprintf+0x9e0> +10022dc4: 910b str r1, [sp, #44] @ 0x2c +10022dc6: 930a str r3, [sp, #40] @ 0x28 +10022dc8: 950c str r5, [sp, #48] @ 0x30 +10022dca: e001 b.n 10022dd0 <_vsnprintf+0x614> +10022dcc: 2820 cmp r0, #32 +10022dce: d00f beq.n 10022df0 <_vsnprintf+0x634> +10022dd0: 4615 mov r5, r2 +10022dd2: fbae 1302 umull r1, r3, lr, r2 +10022dd6: 08db lsrs r3, r3, #3 +10022dd8: eb03 0183 add.w r1, r3, r3, lsl #2 +10022ddc: eba2 0141 sub.w r1, r2, r1, lsl #1 +10022de0: 3130 adds r1, #48 @ 0x30 +10022de2: 2d09 cmp r5, #9 +10022de4: 461a mov r2, r3 +10022de6: f100 0001 add.w r0, r0, #1 +10022dea: f807 1b01 strb.w r1, [r7], #1 +10022dee: d8ed bhi.n 10022dcc <_vsnprintf+0x610> +10022df0: 9b0a ldr r3, [sp, #40] @ 0x28 +10022df2: 9d0c ldr r5, [sp, #48] @ 0x30 +10022df4: e9cd 5c05 strd r5, ip, [sp, #20] +10022df8: e9cd 0301 strd r0, r3, [sp, #4] +10022dfc: 9604 str r6, [sp, #16] +10022dfe: 9b0b ldr r3, [sp, #44] @ 0x2c +10022e00: 4642 mov r2, r8 +10022e02: 9300 str r3, [sp, #0] +10022e04: 230a movs r3, #10 +10022e06: 4651 mov r1, sl +10022e08: 9303 str r3, [sp, #12] +10022e0a: 4658 mov r0, fp +10022e0c: 464b mov r3, r9 +10022e0e: f7fe fec7 bl 10021ba0 <_ntoa_format> +10022e12: 940a str r4, [sp, #40] @ 0x28 +10022e14: 4680 mov r8, r0 +10022e16: e4ef b.n 100227f8 <_vsnprintf+0x3c> +10022e18: f023 030c bic.w r3, r3, #12 +10022e1c: e721 b.n 10022c62 <_vsnprintf+0x4a6> +10022e1e: 3307 adds r3, #7 +10022e20: f023 0307 bic.w r3, r3, #7 +10022e24: 4619 mov r1, r3 +10022e26: 4608 mov r0, r1 +10022e28: 685b ldr r3, [r3, #4] +10022e2a: f850 1b08 ldr.w r1, [r0], #8 +10022e2e: 0fdf lsrs r7, r3, #31 +10022e30: 900a str r0, [sp, #40] @ 0x28 +10022e32: ea51 0003 orrs.w r0, r1, r3 +10022e36: d162 bne.n 10022efe <_vsnprintf+0x742> +10022e38: 2a00 cmp r2, #0 +10022e3a: f040 819f bne.w 1002317c <_vsnprintf+0x9c0> +10022e3e: 4613 mov r3, r2 +10022e40: 4611 mov r1, r2 +10022e42: aa12 add r2, sp, #72 @ 0x48 +10022e44: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10022e48: 2000 movs r0, #0 +10022e4a: 4615 mov r5, r2 +10022e4c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10022e50: f8df e348 ldr.w lr, [pc, #840] @ 1002319c <_vsnprintf+0x9e0> +10022e54: 920b str r2, [sp, #44] @ 0x2c +10022e56: e001 b.n 10022e5c <_vsnprintf+0x6a0> +10022e58: 2820 cmp r0, #32 +10022e5a: d02d beq.n 10022eb8 <_vsnprintf+0x6fc> +10022e5c: 185a adds r2, r3, r1 +10022e5e: f142 0200 adc.w r2, r2, #0 +10022e62: fbae 7802 umull r7, r8, lr, r2 +10022e66: f028 0703 bic.w r7, r8, #3 +10022e6a: eb07 0798 add.w r7, r7, r8, lsr #2 +10022e6e: 1bd2 subs r2, r2, r7 +10022e70: 461e mov r6, r3 +10022e72: 1a9b subs r3, r3, r2 +10022e74: f161 0700 sbc.w r7, r1, #0 +10022e78: 460c mov r4, r1 +10022e7a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10022e7e: fb01 f103 mul.w r1, r1, r3 +10022e82: fb0e 1107 mla r1, lr, r7, r1 +10022e86: fba3 730e umull r7, r3, r3, lr +10022e8a: 4419 add r1, r3 +10022e8c: 2305 movs r3, #5 +10022e8e: f007 0801 and.w r8, r7, #1 +10022e92: fba8 3803 umull r3, r8, r8, r3 +10022e96: 189b adds r3, r3, r2 +10022e98: 2e0a cmp r6, #10 +10022e9a: f103 0330 add.w r3, r3, #48 @ 0x30 +10022e9e: ea4f 0757 mov.w r7, r7, lsr #1 +10022ea2: f174 0400 sbcs.w r4, r4, #0 +10022ea6: f805 3b01 strb.w r3, [r5], #1 +10022eaa: f100 0001 add.w r0, r0, #1 +10022eae: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10022eb2: ea4f 0151 mov.w r1, r1, lsr #1 +10022eb6: d2cf bcs.n 10022e58 <_vsnprintf+0x69c> +10022eb8: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10022ebc: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10022ec0: 9b0b ldr r3, [sp, #44] @ 0x2c +10022ec2: 4642 mov r2, r8 +10022ec4: 9300 str r3, [sp, #0] +10022ec6: 230a movs r3, #10 +10022ec8: e9cd 5c05 strd r5, ip, [sp, #20] +10022ecc: e9cd 0701 strd r0, r7, [sp, #4] +10022ed0: 9604 str r6, [sp, #16] +10022ed2: 9303 str r3, [sp, #12] +10022ed4: 464b mov r3, r9 +10022ed6: 4651 mov r1, sl +10022ed8: 4658 mov r0, fp +10022eda: f7fe fe61 bl 10021ba0 <_ntoa_format> +10022ede: 4680 mov r8, r0 +10022ee0: e48a b.n 100227f8 <_vsnprintf+0x3c> +10022ee2: 7819 ldrb r1, [r3, #0] +10022ee4: 460f mov r7, r1 +10022ee6: e764 b.n 10022db2 <_vsnprintf+0x5f6> +10022ee8: 2710 movs r7, #16 +10022eea: 46bc mov ip, r7 +10022eec: e6b3 b.n 10022c56 <_vsnprintf+0x49a> +10022eee: f023 0c10 bic.w ip, r3, #16 +10022ef2: e745 b.n 10022d80 <_vsnprintf+0x5c4> +10022ef4: 061c lsls r4, r3, #24 +10022ef6: bf4c ite mi +10022ef8: 8812 ldrhmi r2, [r2, #0] +10022efa: 6812 ldrpl r2, [r2, #0] +10022efc: e6c0 b.n 10022c80 <_vsnprintf+0x4c4> +10022efe: 460a mov r2, r1 +10022f00: 1e19 subs r1, r3, #0 +10022f02: db01 blt.n 10022f08 <_vsnprintf+0x74c> +10022f04: 4613 mov r3, r2 +10022f06: e79c b.n 10022e42 <_vsnprintf+0x686> +10022f08: 4252 negs r2, r2 +10022f0a: 4613 mov r3, r2 +10022f0c: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10022f10: e797 b.n 10022e42 <_vsnprintf+0x686> +10022f12: 4613 mov r3, r2 +10022f14: 4651 mov r1, sl +10022f16: 7818 ldrb r0, [r3, #0] +10022f18: 4642 mov r2, r8 +10022f1a: 464b mov r3, r9 +10022f1c: 47d8 blx fp +10022f1e: 46b0 mov r8, r6 +10022f20: e648 b.n 10022bb4 <_vsnprintf+0x3f8> +10022f22: f013 0f20 tst.w r3, #32 +10022f26: bf14 ite ne +10022f28: 2041 movne r0, #65 @ 0x41 +10022f2a: 2061 moveq r0, #97 @ 0x61 +10022f2c: ac12 add r4, sp, #72 @ 0x48 +10022f2e: 46a6 mov lr, r4 +10022f30: 940b str r4, [sp, #44] @ 0x2c +10022f32: 930a str r3, [sp, #40] @ 0x28 +10022f34: f1a0 040a sub.w r4, r0, #10 +10022f38: 950c str r5, [sp, #48] @ 0x30 +10022f3a: e002 b.n 10022f42 <_vsnprintf+0x786> +10022f3c: 2920 cmp r1, #32 +10022f3e: d012 beq.n 10022f66 <_vsnprintf+0x7aa> +10022f40: 462a mov r2, r5 +10022f42: fbb2 f5fc udiv r5, r2, ip +10022f46: fb0c 2015 mls r0, ip, r5, r2 +10022f4a: b2c3 uxtb r3, r0 +10022f4c: 2809 cmp r0, #9 +10022f4e: f103 0030 add.w r0, r3, #48 @ 0x30 +10022f52: bf8a itet hi +10022f54: 191b addhi r3, r3, r4 +10022f56: b2c3 uxtbls r3, r0 +10022f58: b2db uxtbhi r3, r3 +10022f5a: 4562 cmp r2, ip +10022f5c: f80e 3b01 strb.w r3, [lr], #1 +10022f60: f101 0101 add.w r1, r1, #1 +10022f64: d2ea bcs.n 10022f3c <_vsnprintf+0x780> +10022f66: 9b0a ldr r3, [sp, #40] @ 0x28 +10022f68: 9d0c ldr r5, [sp, #48] @ 0x30 +10022f6a: e694 b.n 10022c96 <_vsnprintf+0x4da> +10022f6c: 9a0a ldr r2, [sp, #40] @ 0x28 +10022f6e: 3207 adds r2, #7 +10022f70: f022 0207 bic.w r2, r2, #7 +10022f74: 6851 ldr r1, [r2, #4] +10022f76: f852 4b08 ldr.w r4, [r2], #8 +10022f7a: 468e mov lr, r1 +10022f7c: 920a str r2, [sp, #40] @ 0x28 +10022f7e: ea54 0201 orrs.w r2, r4, r1 +10022f82: d176 bne.n 10023072 <_vsnprintf+0x8b6> +10022f84: f023 0310 bic.w r3, r3, #16 +10022f88: 2800 cmp r0, #0 +10022f8a: d072 beq.n 10023072 <_vsnprintf+0x8b6> +10022f8c: 2200 movs r2, #0 +10022f8e: 4611 mov r1, r2 +10022f90: aa12 add r2, sp, #72 @ 0x48 +10022f92: 920b str r2, [sp, #44] @ 0x2c +10022f94: e9cd 5305 strd r5, r3, [sp, #20] +10022f98: 9b0b ldr r3, [sp, #44] @ 0x2c +10022f9a: 4642 mov r2, r8 +10022f9c: 9300 str r3, [sp, #0] +10022f9e: 2300 movs r3, #0 +10022fa0: e9cd c603 strd ip, r6, [sp, #12] +10022fa4: 9101 str r1, [sp, #4] +10022fa6: 9302 str r3, [sp, #8] +10022fa8: e794 b.n 10022ed4 <_vsnprintf+0x718> +10022faa: 42a5 cmp r5, r4 +10022fac: bf98 it ls +10022fae: 3401 addls r4, #1 +10022fb0: f67f ad74 bls.w 10022a9c <_vsnprintf+0x2e0> +10022fb4: f44f 6380 mov.w r3, #1024 @ 0x400 +10022fb8: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10022fbc: eb05 0208 add.w r2, r5, r8 +10022fc0: 461f mov r7, r3 +10022fc2: 460d mov r5, r1 +10022fc4: 1b14 subs r4, r2, r4 +10022fc6: 4642 mov r2, r8 +10022fc8: 464b mov r3, r9 +10022fca: 4651 mov r1, sl +10022fcc: 2020 movs r0, #32 +10022fce: f108 0801 add.w r8, r8, #1 +10022fd2: 47d8 blx fp +10022fd4: 45a0 cmp r8, r4 +10022fd6: d1f6 bne.n 10022fc6 <_vsnprintf+0x80a> +10022fd8: 463b mov r3, r7 +10022fda: 9f0a ldr r7, [sp, #40] @ 0x28 +10022fdc: 4629 mov r1, r5 +10022fde: 7838 ldrb r0, [r7, #0] +10022fe0: 9d0b ldr r5, [sp, #44] @ 0x2c +10022fe2: 1c6c adds r4, r5, #1 +10022fe4: 2800 cmp r0, #0 +10022fe6: f43f ad70 beq.w 10022aca <_vsnprintf+0x30e> +10022fea: 2b00 cmp r3, #0 +10022fec: f43f ae75 beq.w 10022cda <_vsnprintf+0x51e> +10022ff0: 2300 movs r3, #0 +10022ff2: e553 b.n 10022a9c <_vsnprintf+0x2e0> +10022ff4: 42a5 cmp r5, r4 +10022ff6: d8df bhi.n 10022fb8 <_vsnprintf+0x7fc> +10022ff8: 3401 adds r4, #1 +10022ffa: e66e b.n 10022cda <_vsnprintf+0x51e> +10022ffc: 6819 ldr r1, [r3, #0] +10022ffe: 0fcb lsrs r3, r1, #31 +10023000: 2900 cmp r1, #0 +10023002: f000 80a8 beq.w 10023156 <_vsnprintf+0x99a> +10023006: ea81 72e1 eor.w r2, r1, r1, asr #31 +1002300a: eba2 72e1 sub.w r2, r2, r1, asr #31 +1002300e: a912 add r1, sp, #72 @ 0x48 +10023010: 4608 mov r0, r1 +10023012: f8df e188 ldr.w lr, [pc, #392] @ 1002319c <_vsnprintf+0x9e0> +10023016: 910b str r1, [sp, #44] @ 0x2c +10023018: 930a str r3, [sp, #40] @ 0x28 +1002301a: 950c str r5, [sp, #48] @ 0x30 +1002301c: e001 b.n 10023022 <_vsnprintf+0x866> +1002301e: 2f20 cmp r7, #32 +10023020: d00f beq.n 10023042 <_vsnprintf+0x886> +10023022: 4615 mov r5, r2 +10023024: fbae 1302 umull r1, r3, lr, r2 +10023028: 08db lsrs r3, r3, #3 +1002302a: eb03 0183 add.w r1, r3, r3, lsl #2 +1002302e: eba2 0141 sub.w r1, r2, r1, lsl #1 +10023032: 3130 adds r1, #48 @ 0x30 +10023034: 2d09 cmp r5, #9 +10023036: 461a mov r2, r3 +10023038: f107 0701 add.w r7, r7, #1 +1002303c: f800 1b01 strb.w r1, [r0], #1 +10023040: d8ed bhi.n 1002301e <_vsnprintf+0x862> +10023042: 9b0a ldr r3, [sp, #40] @ 0x28 +10023044: 9d0c ldr r5, [sp, #48] @ 0x30 +10023046: e9cd 5c05 strd r5, ip, [sp, #20] +1002304a: e9cd 7301 strd r7, r3, [sp, #4] +1002304e: 9604 str r6, [sp, #16] +10023050: e6d5 b.n 10022dfe <_vsnprintf+0x642> +10023052: 2869 cmp r0, #105 @ 0x69 +10023054: f023 0c10 bic.w ip, r3, #16 +10023058: f040 808c bne.w 10023174 <_vsnprintf+0x9b8> +1002305c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10023060: f43f ae8e beq.w 10022d80 <_vsnprintf+0x5c4> +10023064: e688 b.n 10022d78 <_vsnprintf+0x5bc> +10023066: 2a00 cmp r2, #0 +10023068: f43f aea8 beq.w 10022dbc <_vsnprintf+0x600> +1002306c: aa12 add r2, sp, #72 @ 0x48 +1002306e: 920b str r2, [sp, #44] @ 0x2c +10023070: e6c0 b.n 10022df4 <_vsnprintf+0x638> +10023072: f013 0f20 tst.w r3, #32 +10023076: bf14 ite ne +10023078: 2241 movne r2, #65 @ 0x41 +1002307a: 2261 moveq r2, #97 @ 0x61 +1002307c: 2000 movs r0, #0 +1002307e: a912 add r1, sp, #72 @ 0x48 +10023080: 3a0a subs r2, #10 +10023082: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10023086: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +1002308a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +1002308e: 4606 mov r6, r0 +10023090: 4688 mov r8, r1 +10023092: 4675 mov r5, lr +10023094: 4693 mov fp, r2 +10023096: 910b str r1, [sp, #44] @ 0x2c +10023098: f8cd c040 str.w ip, [sp, #64] @ 0x40 +1002309c: e003 b.n 100230a6 <_vsnprintf+0x8ea> +1002309e: 2e20 cmp r6, #32 +100230a0: d017 beq.n 100230d2 <_vsnprintf+0x916> +100230a2: 4604 mov r4, r0 +100230a4: 460d mov r5, r1 +100230a6: 4629 mov r1, r5 +100230a8: 463a mov r2, r7 +100230aa: 2300 movs r3, #0 +100230ac: 4620 mov r0, r4 +100230ae: f001 fdff bl 10024cb0 <____aeabi_uldivmod_veneer> +100230b2: b2d2 uxtb r2, r2 +100230b4: 2a09 cmp r2, #9 +100230b6: f102 0330 add.w r3, r2, #48 @ 0x30 +100230ba: bf88 it hi +100230bc: eb02 030b addhi.w r3, r2, fp +100230c0: 42bc cmp r4, r7 +100230c2: b2db uxtb r3, r3 +100230c4: f175 0500 sbcs.w r5, r5, #0 +100230c8: f808 3b01 strb.w r3, [r8], #1 +100230cc: f106 0601 add.w r6, r6, #1 +100230d0: d2e5 bcs.n 1002309e <_vsnprintf+0x8e2> +100230d2: 4631 mov r1, r6 +100230d4: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +100230d8: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +100230dc: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +100230e0: 9e0e ldr r6, [sp, #56] @ 0x38 +100230e2: e757 b.n 10022f94 <_vsnprintf+0x7d8> +100230e4: 990a ldr r1, [sp, #40] @ 0x28 +100230e6: 6809 ldr r1, [r1, #0] +100230e8: b951 cbnz r1, 10023100 <_vsnprintf+0x944> +100230ea: f023 0310 bic.w r3, r3, #16 +100230ee: b138 cbz r0, 10023100 <_vsnprintf+0x944> +100230f0: a912 add r1, sp, #72 @ 0x48 +100230f2: 910b str r1, [sp, #44] @ 0x2c +100230f4: e9cd 5305 strd r5, r3, [sp, #20] +100230f8: e9cd c603 strd ip, r6, [sp, #12] +100230fc: 9201 str r2, [sp, #4] +100230fe: e5cf b.n 10022ca0 <_vsnprintf+0x4e4> +10023100: f013 0f20 tst.w r3, #32 +10023104: bf14 ite ne +10023106: 2041 movne r0, #65 @ 0x41 +10023108: 2061 moveq r0, #97 @ 0x61 +1002310a: ac12 add r4, sp, #72 @ 0x48 +1002310c: 46a6 mov lr, r4 +1002310e: 940b str r4, [sp, #44] @ 0x2c +10023110: 930a str r3, [sp, #40] @ 0x28 +10023112: f1a0 040a sub.w r4, r0, #10 +10023116: 950c str r5, [sp, #48] @ 0x30 +10023118: e002 b.n 10023120 <_vsnprintf+0x964> +1002311a: 2a20 cmp r2, #32 +1002311c: d012 beq.n 10023144 <_vsnprintf+0x988> +1002311e: 4629 mov r1, r5 +10023120: fbb1 f5fc udiv r5, r1, ip +10023124: fb0c 1015 mls r0, ip, r5, r1 +10023128: b2c3 uxtb r3, r0 +1002312a: 2809 cmp r0, #9 +1002312c: f103 0030 add.w r0, r3, #48 @ 0x30 +10023130: bf8a itet hi +10023132: 191b addhi r3, r3, r4 +10023134: b2c3 uxtbls r3, r0 +10023136: b2db uxtbhi r3, r3 +10023138: 4561 cmp r1, ip +1002313a: f80e 3b01 strb.w r3, [lr], #1 +1002313e: f102 0201 add.w r2, r2, #1 +10023142: d2ea bcs.n 1002311a <_vsnprintf+0x95e> +10023144: 9b0a ldr r3, [sp, #40] @ 0x28 +10023146: 9d0c ldr r5, [sp, #48] @ 0x30 +10023148: e7d4 b.n 100230f4 <_vsnprintf+0x938> +1002314a: 6819 ldr r1, [r3, #0] +1002314c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10023150: eba7 77e1 sub.w r7, r7, r1, asr #31 +10023154: e62d b.n 10022db2 <_vsnprintf+0x5f6> +10023156: 2a00 cmp r2, #0 +10023158: f43f af59 beq.w 1002300e <_vsnprintf+0x852> +1002315c: aa12 add r2, sp, #72 @ 0x48 +1002315e: 920b str r2, [sp, #44] @ 0x2c +10023160: e771 b.n 10023046 <_vsnprintf+0x88a> +10023162: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10023166: d00d beq.n 10023184 <_vsnprintf+0x9c8> +10023168: f013 0402 ands.w r4, r3, #2 +1002316c: d012 beq.n 10023194 <_vsnprintf+0x9d8> +1002316e: 4604 mov r4, r0 +10023170: 4646 mov r6, r8 +10023172: e5ec b.n 10022d4e <_vsnprintf+0x592> +10023174: 270a movs r7, #10 +10023176: 4663 mov r3, ip +10023178: 46bc mov ip, r7 +1002317a: e56c b.n 10022c56 <_vsnprintf+0x49a> +1002317c: ab12 add r3, sp, #72 @ 0x48 +1002317e: 2000 movs r0, #0 +10023180: 930b str r3, [sp, #44] @ 0x2c +10023182: e69d b.n 10022ec0 <_vsnprintf+0x704> +10023184: f013 0302 ands.w r3, r3, #2 +10023188: f47f ade0 bne.w 10022d4c <_vsnprintf+0x590> +1002318c: 2d00 cmp r5, #0 +1002318e: f47f af13 bne.w 10022fb8 <_vsnprintf+0x7fc> +10023192: e49a b.n 10022aca <_vsnprintf+0x30e> +10023194: 2d00 cmp r5, #0 +10023196: f47f af0d bne.w 10022fb4 <_vsnprintf+0x7f8> +1002319a: e496 b.n 10022aca <_vsnprintf+0x30e> +1002319c: cccccccd .word 0xcccccccd + +100231a0 : +100231a0: b570 push {r4, r5, r6, lr} +100231a2: 4694 mov ip, r2 +100231a4: 461e mov r6, r3 +100231a6: 4605 mov r5, r0 +100231a8: 460c mov r4, r1 +100231aa: b084 sub sp, #16 +100231ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100231b0: 4663 mov r3, ip +100231b2: a902 add r1, sp, #8 +100231b4: 9600 str r6, [sp, #0] +100231b6: 4803 ldr r0, [pc, #12] @ (100231c4 ) +100231b8: e9cd 5402 strd r5, r4, [sp, #8] +100231bc: f7ff fafe bl 100227bc <_vsnprintf> +100231c0: b004 add sp, #16 +100231c2: bd70 pop {r4, r5, r6, pc} +100231c4: 10021d7d .word 0x10021d7d + +100231c8 : +100231c8: b510 push {r4, lr} +100231ca: 4b09 ldr r3, [pc, #36] @ (100231f0 ) +100231cc: b084 sub sp, #16 +100231ce: 681c ldr r4, [r3, #0] +100231d0: b14c cbz r4, 100231e6 +100231d2: 4603 mov r3, r0 +100231d4: 9100 str r1, [sp, #0] +100231d6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +100231da: a903 add r1, sp, #12 +100231dc: 4805 ldr r0, [pc, #20] @ (100231f4 ) +100231de: 47a0 blx r4 +100231e0: 2001 movs r0, #1 +100231e2: b004 add sp, #16 +100231e4: bd10 pop {r4, pc} +100231e6: f000 f97d bl 100234e4 <__wrap_puts> +100231ea: 4620 mov r0, r4 +100231ec: b004 add sp, #16 +100231ee: bd10 pop {r4, pc} +100231f0: 20002a3c .word 0x20002a3c +100231f4: 10021d75 .word 0x10021d75 + +100231f8 <_exit>: +100231f8: be00 bkpt 0x0000 +100231fa: e7fd b.n 100231f8 <_exit> + +100231fc : +100231fc: b508 push {r3, lr} +100231fe: f7ff fffb bl 100231f8 <_exit> +10023202: bf00 nop + +10023204 : +10023204: b538 push {r3, r4, r5, lr} +10023206: 4c06 ldr r4, [pc, #24] @ (10023220 ) +10023208: 4d06 ldr r5, [pc, #24] @ (10023224 ) +1002320a: f7fe fa07 bl 1002161c +1002320e: 42ac cmp r4, r5 +10023210: d204 bcs.n 1002321c +10023212: f854 3b04 ldr.w r3, [r4], #4 +10023216: 4798 blx r3 +10023218: 42ac cmp r4, r5 +1002321a: d3fa bcc.n 10023212 +1002321c: bd38 pop {r3, r4, r5, pc} +1002321e: bf00 nop +10023220: 10024d08 .word 0x10024d08 +10023224: 10024d10 .word 0x10024d10 + +10023228 : +10023228: 6803 ldr r3, [r0, #0] +1002322a: 4608 mov r0, r1 +1002322c: 4611 mov r1, r2 +1002322e: 4718 bx r3 + +10023230 : +10023230: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10023234: 4615 mov r5, r2 +10023236: 7d42 ldrb r2, [r0, #21] +10023238: 4607 mov r7, r0 +1002323a: 4688 mov r8, r1 +1002323c: 2a00 cmp r2, #0 +1002323e: d046 beq.n 100232ce +10023240: 2d00 cmp r5, #0 +10023242: dd1d ble.n 10023280 +10023244: 780b ldrb r3, [r1, #0] +10023246: 2b0a cmp r3, #10 +10023248: d023 beq.n 10023292 +1002324a: 2d01 cmp r5, #1 +1002324c: f04f 0c00 mov.w ip, #0 +10023250: d018 beq.n 10023284 +10023252: 4646 mov r6, r8 +10023254: 2401 movs r4, #1 +10023256: f816 2f01 ldrb.w r2, [r6, #1]! +1002325a: 4621 mov r1, r4 +1002325c: 2a0a cmp r2, #10 +1002325e: f104 0401 add.w r4, r4, #1 +10023262: d022 beq.n 100232aa +10023264: 42a5 cmp r5, r4 +10023266: d1f6 bne.n 10023256 +10023268: 4565 cmp r5, ip +1002326a: dc0b bgt.n 10023284 +1002326c: eb08 0305 add.w r3, r8, r5 +10023270: f813 3c01 ldrb.w r3, [r3, #-1] +10023274: f1a3 030d sub.w r3, r3, #13 +10023278: fab3 f383 clz r3, r3 +1002327c: 095b lsrs r3, r3, #5 +1002327e: 753b strb r3, [r7, #20] +10023280: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10023284: 683b ldr r3, [r7, #0] +10023286: eba5 010c sub.w r1, r5, ip +1002328a: eb08 000c add.w r0, r8, ip +1002328e: 4798 blx r3 +10023290: e7ec b.n 1002326c +10023292: 7d03 ldrb r3, [r0, #20] +10023294: 2b00 cmp r3, #0 +10023296: d1d8 bne.n 1002324a +10023298: 6803 ldr r3, [r0, #0] +1002329a: 2102 movs r1, #2 +1002329c: 480f ldr r0, [pc, #60] @ (100232dc ) +1002329e: 4798 blx r3 +100232a0: 2d01 cmp r5, #1 +100232a2: d0e3 beq.n 1002326c +100232a4: f04f 0c01 mov.w ip, #1 +100232a8: e7d3 b.n 10023252 +100232aa: f816 3c01 ldrb.w r3, [r6, #-1] +100232ae: 2b0d cmp r3, #13 +100232b0: d0d8 beq.n 10023264 +100232b2: 458c cmp ip, r1 +100232b4: eb08 000c add.w r0, r8, ip +100232b8: eba1 010c sub.w r1, r1, ip +100232bc: da01 bge.n 100232c2 +100232be: 683b ldr r3, [r7, #0] +100232c0: 4798 blx r3 +100232c2: 2102 movs r1, #2 +100232c4: 4805 ldr r0, [pc, #20] @ (100232dc ) +100232c6: 683b ldr r3, [r7, #0] +100232c8: 4798 blx r3 +100232ca: 46a4 mov ip, r4 +100232cc: e7ca b.n 10023264 +100232ce: 4629 mov r1, r5 +100232d0: 4640 mov r0, r8 +100232d2: 683b ldr r3, [r7, #0] +100232d4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100232d8: 4718 bx r3 +100232da: bf00 nop +100232dc: 10024f18 .word 0x10024f18 + +100232e0 : +100232e0: 680b ldr r3, [r1, #0] +100232e2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100232e6: 2b80 cmp r3, #128 @ 0x80 +100232e8: 460d mov r5, r1 +100232ea: 4606 mov r6, r0 +100232ec: d005 beq.n 100232fa +100232ee: 1c5a adds r2, r3, #1 +100232f0: 442b add r3, r5 +100232f2: 602a str r2, [r5, #0] +100232f4: 711e strb r6, [r3, #4] +100232f6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100232fa: 4b0f ldr r3, [pc, #60] @ (10023338 ) +100232fc: 681c ldr r4, [r3, #0] +100232fe: b1a4 cbz r4, 1002332a +10023300: 4f0e ldr r7, [pc, #56] @ (1002333c ) +10023302: f101 0804 add.w r8, r1, #4 +10023306: e001 b.n 1002330c +10023308: 6924 ldr r4, [r4, #16] +1002330a: b174 cbz r4, 1002332a +1002330c: 6823 ldr r3, [r4, #0] +1002330e: 2b00 cmp r3, #0 +10023310: d0fa beq.n 10023308 +10023312: 683b ldr r3, [r7, #0] +10023314: b10b cbz r3, 1002331a +10023316: 42a3 cmp r3, r4 +10023318: d1f6 bne.n 10023308 +1002331a: 4620 mov r0, r4 +1002331c: 4641 mov r1, r8 +1002331e: 682a ldr r2, [r5, #0] +10023320: f7ff ff86 bl 10023230 +10023324: 6924 ldr r4, [r4, #16] +10023326: 2c00 cmp r4, #0 +10023328: d1f0 bne.n 1002330c +1002332a: 2300 movs r3, #0 +1002332c: 2201 movs r2, #1 +1002332e: 442b add r3, r5 +10023330: 602a str r2, [r5, #0] +10023332: 711e strb r6, [r3, #4] +10023334: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10023338: 20002a30 .word 0x20002a30 +1002333c: 20002a34 .word 0x20002a34 + +10023340 : +10023340: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10023344: b082 sub sp, #8 +10023346: 460d mov r5, r1 +10023348: 4691 mov r9, r2 +1002334a: 461c mov r4, r3 +1002334c: 4606 mov r6, r0 +1002334e: f7fd ff95 bl 1002127c +10023352: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10023356: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +1002335a: 4a2e ldr r2, [pc, #184] @ (10023414 ) +1002335c: 1882 adds r2, r0, r2 +1002335e: f141 0300 adc.w r3, r1, #0 +10023362: 4594 cmp ip, r2 +10023364: eb77 0103 sbcs.w r1, r7, r3 +10023368: bf3c itt cc +1002336a: 4662 movcc r2, ip +1002336c: 463b movcc r3, r7 +1002336e: 482a ldr r0, [pc, #168] @ (10023418 ) +10023370: f001 fca6 bl 10024cc0 <__mutex_try_enter_block_until_veneer> +10023374: 1c6b adds r3, r5, #1 +10023376: 4680 mov r8, r0 +10023378: d040 beq.n 100233fc +1002337a: b30c cbz r4, 100233c0 +1002337c: 4f27 ldr r7, [pc, #156] @ (1002341c ) +1002337e: 4b28 ldr r3, [pc, #160] @ (10023420 ) +10023380: 681c ldr r4, [r3, #0] +10023382: b1b4 cbz r4, 100233b2 +10023384: f1b9 0f00 cmp.w r9, #0 +10023388: d11c bne.n 100233c4 +1002338a: f8df 909c ldr.w r9, [pc, #156] @ 10023428 +1002338e: e001 b.n 10023394 +10023390: 6924 ldr r4, [r4, #16] +10023392: b174 cbz r4, 100233b2 +10023394: 6823 ldr r3, [r4, #0] +10023396: 2b00 cmp r3, #0 +10023398: d0fa beq.n 10023390 +1002339a: f8d9 3000 ldr.w r3, [r9] +1002339e: b10b cbz r3, 100233a4 +100233a0: 429c cmp r4, r3 +100233a2: d1f5 bne.n 10023390 +100233a4: 4620 mov r0, r4 +100233a6: 462a mov r2, r5 +100233a8: 4631 mov r1, r6 +100233aa: 47b8 blx r7 +100233ac: 6924 ldr r4, [r4, #16] +100233ae: 2c00 cmp r4, #0 +100233b0: d1f0 bne.n 10023394 +100233b2: f1b8 0f00 cmp.w r8, #0 +100233b6: d126 bne.n 10023406 +100233b8: 4628 mov r0, r5 +100233ba: b002 add sp, #8 +100233bc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100233c0: 4f18 ldr r7, [pc, #96] @ (10023424 ) +100233c2: e7dc b.n 1002337e +100233c4: f04f 0a0a mov.w sl, #10 +100233c8: f8df 905c ldr.w r9, [pc, #92] @ 10023428 +100233cc: e002 b.n 100233d4 +100233ce: 6924 ldr r4, [r4, #16] +100233d0: 2c00 cmp r4, #0 +100233d2: d0ee beq.n 100233b2 +100233d4: 6823 ldr r3, [r4, #0] +100233d6: 2b00 cmp r3, #0 +100233d8: d0f9 beq.n 100233ce +100233da: f8d9 3000 ldr.w r3, [r9] +100233de: b10b cbz r3, 100233e4 +100233e0: 42a3 cmp r3, r4 +100233e2: d1f4 bne.n 100233ce +100233e4: 462a mov r2, r5 +100233e6: 4631 mov r1, r6 +100233e8: 4620 mov r0, r4 +100233ea: 47b8 blx r7 +100233ec: 2201 movs r2, #1 +100233ee: 4620 mov r0, r4 +100233f0: f10d 0107 add.w r1, sp, #7 +100233f4: f88d a007 strb.w sl, [sp, #7] +100233f8: 47b8 blx r7 +100233fa: e7e8 b.n 100233ce +100233fc: 4630 mov r0, r6 +100233fe: f001 fc25 bl 10024c4c +10023402: 4605 mov r5, r0 +10023404: e7b9 b.n 1002337a +10023406: 4804 ldr r0, [pc, #16] @ (10023418 ) +10023408: f001 fc56 bl 10024cb8 <__mutex_exit_veneer> +1002340c: 4628 mov r0, r5 +1002340e: b002 add sp, #8 +10023410: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10023414: 000f4240 .word 0x000f4240 +10023418: 20000624 .word 0x20000624 +1002341c: 10023231 .word 0x10023231 +10023420: 20002a30 .word 0x20002a30 +10023424: 10023229 .word 0x10023229 +10023428: 20002a34 .word 0x20002a34 + +1002342c : +1002342c: 4a08 ldr r2, [pc, #32] @ (10023450 ) +1002342e: 6813 ldr r3, [r2, #0] +10023430: b923 cbnz r3, 1002343c +10023432: e00a b.n 1002344a +10023434: f103 0210 add.w r2, r3, #16 +10023438: 691b ldr r3, [r3, #16] +1002343a: b133 cbz r3, 1002344a +1002343c: 4283 cmp r3, r0 +1002343e: d1f9 bne.n 10023434 +10023440: b929 cbnz r1, 1002344e +10023442: 6918 ldr r0, [r3, #16] +10023444: 6010 str r0, [r2, #0] +10023446: 6119 str r1, [r3, #16] +10023448: 4770 bx lr +1002344a: b101 cbz r1, 1002344e +1002344c: 6010 str r0, [r2, #0] +1002344e: 4770 bx lr +10023450: 20002a30 .word 0x20002a30 + +10023454 : +10023454: b508 push {r3, lr} +10023456: f000 f9a3 bl 100237a0 +1002345a: 2001 movs r0, #1 +1002345c: bd08 pop {r3, pc} +1002345e: bf00 nop + +10023460 <__wrap_putchar>: +10023460: b5f0 push {r4, r5, r6, r7, lr} +10023462: b083 sub sp, #12 +10023464: 4606 mov r6, r0 +10023466: f88d 0007 strb.w r0, [sp, #7] +1002346a: f7fd ff07 bl 1002127c +1002346e: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +10023472: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10023476: 4a17 ldr r2, [pc, #92] @ (100234d4 <__wrap_putchar+0x74>) +10023478: 1882 adds r2, r0, r2 +1002347a: f141 0300 adc.w r3, r1, #0 +1002347e: 4295 cmp r5, r2 +10023480: eb74 0103 sbcs.w r1, r4, r3 +10023484: bf3c itt cc +10023486: 4623 movcc r3, r4 +10023488: 462a movcc r2, r5 +1002348a: 4813 ldr r0, [pc, #76] @ (100234d8 <__wrap_putchar+0x78>) +1002348c: f001 fc18 bl 10024cc0 <__mutex_try_enter_block_until_veneer> +10023490: 4b12 ldr r3, [pc, #72] @ (100234dc <__wrap_putchar+0x7c>) +10023492: 4607 mov r7, r0 +10023494: 681c ldr r4, [r3, #0] +10023496: b19c cbz r4, 100234c0 <__wrap_putchar+0x60> +10023498: 4d11 ldr r5, [pc, #68] @ (100234e0 <__wrap_putchar+0x80>) +1002349a: e001 b.n 100234a0 <__wrap_putchar+0x40> +1002349c: 6924 ldr r4, [r4, #16] +1002349e: b17c cbz r4, 100234c0 <__wrap_putchar+0x60> +100234a0: 6823 ldr r3, [r4, #0] +100234a2: 2b00 cmp r3, #0 +100234a4: d0fa beq.n 1002349c <__wrap_putchar+0x3c> +100234a6: 682b ldr r3, [r5, #0] +100234a8: b10b cbz r3, 100234ae <__wrap_putchar+0x4e> +100234aa: 429c cmp r4, r3 +100234ac: d1f6 bne.n 1002349c <__wrap_putchar+0x3c> +100234ae: 4620 mov r0, r4 +100234b0: 2201 movs r2, #1 +100234b2: f10d 0107 add.w r1, sp, #7 +100234b6: f7ff febb bl 10023230 +100234ba: 6924 ldr r4, [r4, #16] +100234bc: 2c00 cmp r4, #0 +100234be: d1ef bne.n 100234a0 <__wrap_putchar+0x40> +100234c0: b917 cbnz r7, 100234c8 <__wrap_putchar+0x68> +100234c2: 4630 mov r0, r6 +100234c4: b003 add sp, #12 +100234c6: bdf0 pop {r4, r5, r6, r7, pc} +100234c8: 4803 ldr r0, [pc, #12] @ (100234d8 <__wrap_putchar+0x78>) +100234ca: f001 fbf5 bl 10024cb8 <__mutex_exit_veneer> +100234ce: 4630 mov r0, r6 +100234d0: b003 add sp, #12 +100234d2: bdf0 pop {r4, r5, r6, r7, pc} +100234d4: 000f4240 .word 0x000f4240 +100234d8: 20000624 .word 0x20000624 +100234dc: 20002a30 .word 0x20002a30 +100234e0: 20002a34 .word 0x20002a34 + +100234e4 <__wrap_puts>: +100234e4: b538 push {r3, r4, r5, lr} +100234e6: 4604 mov r4, r0 +100234e8: f001 fbb0 bl 10024c4c +100234ec: 2301 movs r3, #1 +100234ee: 4605 mov r5, r0 +100234f0: 461a mov r2, r3 +100234f2: 4620 mov r0, r4 +100234f4: 4629 mov r1, r5 +100234f6: f7ff ff23 bl 10023340 +100234fa: 4b08 ldr r3, [pc, #32] @ (1002351c <__wrap_puts+0x38>) +100234fc: 681c ldr r4, [r3, #0] +100234fe: b12c cbz r4, 1002350c <__wrap_puts+0x28> +10023500: 6863 ldr r3, [r4, #4] +10023502: b12b cbz r3, 10023510 <__wrap_puts+0x2c> +10023504: 4798 blx r3 +10023506: 6924 ldr r4, [r4, #16] +10023508: 2c00 cmp r4, #0 +1002350a: d1f9 bne.n 10023500 <__wrap_puts+0x1c> +1002350c: 4628 mov r0, r5 +1002350e: bd38 pop {r3, r4, r5, pc} +10023510: 6924 ldr r4, [r4, #16] +10023512: 2c00 cmp r4, #0 +10023514: d1f4 bne.n 10023500 <__wrap_puts+0x1c> +10023516: 4628 mov r0, r5 +10023518: bd38 pop {r3, r4, r5, pc} +1002351a: bf00 nop +1002351c: 20002a30 .word 0x20002a30 + +10023520 <__wrap_vprintf>: +10023520: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10023524: b0a2 sub sp, #136 @ 0x88 +10023526: 4604 mov r4, r0 +10023528: 460d mov r5, r1 +1002352a: f7fd fea7 bl 1002127c +1002352e: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +10023532: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10023536: 4a26 ldr r2, [pc, #152] @ (100235d0 <__wrap_vprintf+0xb0>) +10023538: f8df 80a4 ldr.w r8, [pc, #164] @ 100235e0 <__wrap_vprintf+0xc0> +1002353c: 1882 adds r2, r0, r2 +1002353e: f141 0300 adc.w r3, r1, #0 +10023542: 4297 cmp r7, r2 +10023544: eb76 0103 sbcs.w r1, r6, r3 +10023548: bf3c itt cc +1002354a: 463a movcc r2, r7 +1002354c: 4633 movcc r3, r6 +1002354e: 4821 ldr r0, [pc, #132] @ (100235d4 <__wrap_vprintf+0xb4>) +10023550: f001 fbb6 bl 10024cc0 <__mutex_try_enter_block_until_veneer> +10023554: 2700 movs r7, #0 +10023556: 462b mov r3, r5 +10023558: 4622 mov r2, r4 +1002355a: 4606 mov r6, r0 +1002355c: a901 add r1, sp, #4 +1002355e: 481e ldr r0, [pc, #120] @ (100235d8 <__wrap_vprintf+0xb8>) +10023560: 9701 str r7, [sp, #4] +10023562: f7ff fe1d bl 100231a0 +10023566: 9b01 ldr r3, [sp, #4] +10023568: 4605 mov r5, r0 +1002356a: f8d8 4000 ldr.w r4, [r8] +1002356e: b1c3 cbz r3, 100235a2 <__wrap_vprintf+0x82> +10023570: 2c00 cmp r4, #0 +10023572: d02b beq.n 100235cc <__wrap_vprintf+0xac> +10023574: 4f19 ldr r7, [pc, #100] @ (100235dc <__wrap_vprintf+0xbc>) +10023576: e001 b.n 1002357c <__wrap_vprintf+0x5c> +10023578: 6924 ldr r4, [r4, #16] +1002357a: b174 cbz r4, 1002359a <__wrap_vprintf+0x7a> +1002357c: 6823 ldr r3, [r4, #0] +1002357e: 2b00 cmp r3, #0 +10023580: d0fa beq.n 10023578 <__wrap_vprintf+0x58> +10023582: 683b ldr r3, [r7, #0] +10023584: b10b cbz r3, 1002358a <__wrap_vprintf+0x6a> +10023586: 42a3 cmp r3, r4 +10023588: d1f6 bne.n 10023578 <__wrap_vprintf+0x58> +1002358a: 4620 mov r0, r4 +1002358c: 9a01 ldr r2, [sp, #4] +1002358e: a902 add r1, sp, #8 +10023590: f7ff fe4e bl 10023230 +10023594: 6924 ldr r4, [r4, #16] +10023596: 2c00 cmp r4, #0 +10023598: d1f0 bne.n 1002357c <__wrap_vprintf+0x5c> +1002359a: 2300 movs r3, #0 +1002359c: f8d8 4000 ldr.w r4, [r8] +100235a0: 9301 str r3, [sp, #4] +100235a2: b12c cbz r4, 100235b0 <__wrap_vprintf+0x90> +100235a4: 6863 ldr r3, [r4, #4] +100235a6: b143 cbz r3, 100235ba <__wrap_vprintf+0x9a> +100235a8: 4798 blx r3 +100235aa: 6924 ldr r4, [r4, #16] +100235ac: 2c00 cmp r4, #0 +100235ae: d1f9 bne.n 100235a4 <__wrap_vprintf+0x84> +100235b0: b92e cbnz r6, 100235be <__wrap_vprintf+0x9e> +100235b2: 4628 mov r0, r5 +100235b4: b022 add sp, #136 @ 0x88 +100235b6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100235ba: 6924 ldr r4, [r4, #16] +100235bc: e7f1 b.n 100235a2 <__wrap_vprintf+0x82> +100235be: 4805 ldr r0, [pc, #20] @ (100235d4 <__wrap_vprintf+0xb4>) +100235c0: f001 fb7a bl 10024cb8 <__mutex_exit_veneer> +100235c4: 4628 mov r0, r5 +100235c6: b022 add sp, #136 @ 0x88 +100235c8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100235cc: 9401 str r4, [sp, #4] +100235ce: e7ef b.n 100235b0 <__wrap_vprintf+0x90> +100235d0: 000f4240 .word 0x000f4240 +100235d4: 20000624 .word 0x20000624 +100235d8: 100232e1 .word 0x100232e1 +100235dc: 20002a34 .word 0x20002a34 +100235e0: 20002a30 .word 0x20002a30 + +100235e4 <__wrap_printf>: +100235e4: b40f push {r0, r1, r2, r3} +100235e6: b500 push {lr} +100235e8: b083 sub sp, #12 +100235ea: a904 add r1, sp, #16 +100235ec: f851 0b04 ldr.w r0, [r1], #4 +100235f0: 9101 str r1, [sp, #4] +100235f2: f7ff ff95 bl 10023520 <__wrap_vprintf> +100235f6: b003 add sp, #12 +100235f8: f85d eb04 ldr.w lr, [sp], #4 +100235fc: b004 add sp, #16 +100235fe: 4770 bx lr + +10023600 : +10023600: f1b1 0c00 subs.w ip, r1, #0 +10023604: dd1d ble.n 10023642 +10023606: 4a0f ldr r2, [pc, #60] @ (10023644 ) +10023608: 4b0f ldr r3, [pc, #60] @ (10023648 ) +1002360a: 6812 ldr r2, [r2, #0] +1002360c: b530 push {r4, r5, lr} +1002360e: 1ad3 subs r3, r2, r3 +10023610: fab3 f383 clz r3, r3 +10023614: 240d movs r4, #13 +10023616: 4d0d ldr r5, [pc, #52] @ (1002364c ) +10023618: 095b lsrs r3, r3, #5 +1002361a: 1e41 subs r1, r0, #1 +1002361c: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +10023620: 448c add ip, r1 +10023622: f811 0f01 ldrb.w r0, [r1, #1]! +10023626: 4586 cmp lr, r0 +10023628: d006 beq.n 10023638 +1002362a: 6993 ldr r3, [r2, #24] +1002362c: 069b lsls r3, r3, #26 +1002362e: d4fc bmi.n 1002362a +10023630: 4561 cmp r1, ip +10023632: 6010 str r0, [r2, #0] +10023634: d1f5 bne.n 10023622 +10023636: bd30 pop {r4, r5, pc} +10023638: 6993 ldr r3, [r2, #24] +1002363a: 069d lsls r5, r3, #26 +1002363c: d4fc bmi.n 10023638 +1002363e: 6014 str r4, [r2, #0] +10023640: e7f3 b.n 1002362a +10023642: 4770 bx lr +10023644: 20002a88 .word 0x20002a88 +10023648: 40078000 .word 0x40078000 +1002364c: 20002a84 .word 0x20002a84 + +10023650 : +10023650: 4b22 ldr r3, [pc, #136] @ (100236dc ) +10023652: f1b1 0c00 subs.w ip, r1, #0 +10023656: b410 push {r4} +10023658: 681c ldr r4, [r3, #0] +1002365a: dd2e ble.n 100236ba +1002365c: 4603 mov r3, r0 +1002365e: 2000 movs r0, #0 +10023660: 4a1f ldr r2, [pc, #124] @ (100236e0 ) +10023662: 1e59 subs r1, r3, #1 +10023664: 6812 ldr r2, [r2, #0] +10023666: 6993 ldr r3, [r2, #24] +10023668: 06db lsls r3, r3, #27 +1002366a: d417 bmi.n 1002369c +1002366c: 3001 adds r0, #1 +1002366e: 6993 ldr r3, [r2, #24] +10023670: 06db lsls r3, r3, #27 +10023672: d4fc bmi.n 1002366e +10023674: 6813 ldr r3, [r2, #0] +10023676: 4584 cmp ip, r0 +10023678: f801 3f01 strb.w r3, [r1, #1]! +1002367c: d1f3 bne.n 10023666 +1002367e: b14c cbz r4, 10023694 +10023680: 2150 movs r1, #80 @ 0x50 +10023682: 4613 mov r3, r2 +10023684: 6391 str r1, [r2, #56] @ 0x38 +10023686: f853 2f34 ldr.w r2, [r3, #52]! +1002368a: f002 0238 and.w r2, r2, #56 @ 0x38 +1002368e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10023692: 601a str r2, [r3, #0] +10023694: 4660 mov r0, ip +10023696: f85d 4b04 ldr.w r4, [sp], #4 +1002369a: 4770 bx lr +1002369c: b14c cbz r4, 100236b2 +1002369e: 2150 movs r1, #80 @ 0x50 +100236a0: 4613 mov r3, r2 +100236a2: 6391 str r1, [r2, #56] @ 0x38 +100236a4: f853 2f34 ldr.w r2, [r3, #52]! +100236a8: f002 0238 and.w r2, r2, #56 @ 0x38 +100236ac: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100236b0: 601a str r2, [r3, #0] +100236b2: b178 cbz r0, 100236d4 +100236b4: f85d 4b04 ldr.w r4, [sp], #4 +100236b8: 4770 bx lr +100236ba: b15c cbz r4, 100236d4 +100236bc: 4b08 ldr r3, [pc, #32] @ (100236e0 ) +100236be: 2150 movs r1, #80 @ 0x50 +100236c0: 681a ldr r2, [r3, #0] +100236c2: 4613 mov r3, r2 +100236c4: 6391 str r1, [r2, #56] @ 0x38 +100236c6: f853 2f34 ldr.w r2, [r3, #52]! +100236ca: f002 0238 and.w r2, r2, #56 @ 0x38 +100236ce: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100236d2: 601a str r2, [r3, #0] +100236d4: f06f 0002 mvn.w r0, #2 +100236d8: e7dd b.n 10023696 +100236da: bf00 nop +100236dc: 200029fc .word 0x200029fc +100236e0: 20002a88 .word 0x20002a88 + +100236e4 : +100236e4: 4b05 ldr r3, [pc, #20] @ (100236fc ) +100236e6: 681b ldr r3, [r3, #0] +100236e8: b133 cbz r3, 100236f8 +100236ea: 2100 movs r1, #0 +100236ec: 4a04 ldr r2, [pc, #16] @ (10023700 ) +100236ee: 4805 ldr r0, [pc, #20] @ (10023704 ) +100236f0: 6812 ldr r2, [r2, #0] +100236f2: 6800 ldr r0, [r0, #0] +100236f4: 6391 str r1, [r2, #56] @ 0x38 +100236f6: 4718 bx r3 +100236f8: 4770 bx lr +100236fa: bf00 nop +100236fc: 200029fc .word 0x200029fc +10023700: 20002a88 .word 0x20002a88 +10023704: 20002a00 .word 0x20002a00 + +10023708 : +10023708: 4b02 ldr r3, [pc, #8] @ (10023714 ) +1002370a: 681a ldr r2, [r3, #0] +1002370c: 6993 ldr r3, [r2, #24] +1002370e: 071b lsls r3, r3, #28 +10023710: d4fc bmi.n 1002370c +10023712: 4770 bx lr +10023714: 20002a88 .word 0x20002a88 + +10023718 : +10023718: b5f8 push {r3, r4, r5, r6, r7, lr} +1002371a: 4f1c ldr r7, [pc, #112] @ (1002378c ) +1002371c: 4d1c ldr r5, [pc, #112] @ (10023790 ) +1002371e: 683a ldr r2, [r7, #0] +10023720: 4e1c ldr r6, [pc, #112] @ (10023794 ) +10023722: 42aa cmp r2, r5 +10023724: bf14 ite ne +10023726: 2521 movne r5, #33 @ 0x21 +10023728: 2522 moveq r5, #34 @ 0x22 +1002372a: 4604 mov r4, r0 +1002372c: f8d6 c000 ldr.w ip, [r6] +10023730: b118 cbz r0, 1002373a +10023732: f1bc 0f00 cmp.w ip, #0 +10023736: d010 beq.n 1002375a +10023738: bdf8 pop {r3, r4, r5, r6, r7, pc} +1002373a: f1bc 0f00 cmp.w ip, #0 +1002373e: d0fb beq.n 10023738 +10023740: 4601 mov r1, r0 +10023742: 6390 str r0, [r2, #56] @ 0x38 +10023744: 4628 mov r0, r5 +10023746: f7fd f821 bl 1002078c +1002374a: 4628 mov r0, r5 +1002374c: 4912 ldr r1, [pc, #72] @ (10023798 ) +1002374e: f7fd f863 bl 10020818 +10023752: 4b12 ldr r3, [pc, #72] @ (1002379c ) +10023754: 6034 str r4, [r6, #0] +10023756: 601c str r4, [r3, #0] +10023758: bdf8 pop {r3, r4, r5, r6, r7, pc} +1002375a: 460b mov r3, r1 +1002375c: 4a0f ldr r2, [pc, #60] @ (1002379c ) +1002375e: 490e ldr r1, [pc, #56] @ (10023798 ) +10023760: 6030 str r0, [r6, #0] +10023762: 4628 mov r0, r5 +10023764: 6013 str r3, [r2, #0] +10023766: f7fd f827 bl 100207b8 +1002376a: 2101 movs r1, #1 +1002376c: 4628 mov r0, r5 +1002376e: f7fd f80d bl 1002078c +10023772: 683a ldr r2, [r7, #0] +10023774: 2150 movs r1, #80 @ 0x50 +10023776: 4613 mov r3, r2 +10023778: 6391 str r1, [r2, #56] @ 0x38 +1002377a: f853 2f34 ldr.w r2, [r3, #52]! +1002377e: f002 0238 and.w r2, r2, #56 @ 0x38 +10023782: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10023786: 601a str r2, [r3, #0] +10023788: bdf8 pop {r3, r4, r5, r6, r7, pc} +1002378a: bf00 nop +1002378c: 20002a88 .word 0x20002a88 +10023790: 40078000 .word 0x40078000 +10023794: 200029fc .word 0x200029fc +10023798: 100236e5 .word 0x100236e5 +1002379c: 20002a00 .word 0x20002a00 + +100237a0 : +100237a0: b510 push {r4, lr} +100237a2: 490e ldr r1, [pc, #56] @ (100237dc ) +100237a4: 4c0e ldr r4, [pc, #56] @ (100237e0 ) +100237a6: 480f ldr r0, [pc, #60] @ (100237e4 ) +100237a8: 4a0f ldr r2, [pc, #60] @ (100237e8 ) +100237aa: 4b10 ldr r3, [pc, #64] @ (100237ec ) +100237ac: 7800 ldrb r0, [r0, #0] +100237ae: 6021 str r1, [r4, #0] +100237b0: 2000 movs r0, #0 +100237b2: 2102 movs r1, #2 +100237b4: 7812 ldrb r2, [r2, #0] +100237b6: 781b ldrb r3, [r3, #0] +100237b8: f7fc ff0e bl 100205d8 +100237bc: 2102 movs r1, #2 +100237be: 2001 movs r0, #1 +100237c0: f7fc ff0a bl 100205d8 +100237c4: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100237c8: 6820 ldr r0, [r4, #0] +100237ca: f7fd fda1 bl 10021310 +100237ce: e8bd 4010 ldmia.w sp!, {r4, lr} +100237d2: 2101 movs r1, #1 +100237d4: 4806 ldr r0, [pc, #24] @ (100237f0 ) +100237d6: f7ff be29 b.w 1002342c +100237da: bf00 nop +100237dc: 40070000 .word 0x40070000 +100237e0: 20002a88 .word 0x20002a88 +100237e4: 10024f64 .word 0x10024f64 +100237e8: 10024f60 .word 0x10024f60 +100237ec: 10024f5c .word 0x10024f5c +100237f0: 2000060c .word 0x2000060c + +100237f4 : +100237f4: 2301 movs r3, #1 +100237f6: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100237fa: f5ad 7d07 sub.w sp, sp, #540 @ 0x21c +100237fe: f20d 1117 addw r1, sp, #279 @ 0x117 +10023802: f20d 2417 addw r4, sp, #535 @ 0x217 +10023806: b258 sxtb r0, r3 +10023808: 0042 lsls r2, r0, #1 +1002380a: b252 sxtb r2, r2 +1002380c: 2800 cmp r0, #0 +1002380e: f801 3f01 strb.w r3, [r1, #1]! +10023812: bfb8 it lt +10023814: f082 021b eorlt.w r2, r2, #27 +10023818: 4053 eors r3, r2 +1002381a: 42a1 cmp r1, r4 +1002381c: b2db uxtb r3, r3 +1002381e: d1f2 bne.n 10023806 +10023820: 2301 movs r3, #1 +10023822: 2100 movs r1, #0 +10023824: f10d 0a18 add.w sl, sp, #24 +10023828: b258 sxtb r0, r3 +1002382a: 0042 lsls r2, r0, #1 +1002382c: b252 sxtb r2, r2 +1002382e: 2800 cmp r0, #0 +10023830: f80a 1003 strb.w r1, [sl, r3] +10023834: bfb8 it lt +10023836: f082 021b eorlt.w r2, r2, #27 +1002383a: 3101 adds r1, #1 +1002383c: 4053 eors r3, r2 +1002383e: f5b1 7f80 cmp.w r1, #256 @ 0x100 +10023842: b2db uxtb r3, r3 +10023844: d1f0 bne.n 10023828 +10023846: 2202 movs r2, #2 +10023848: 4b72 ldr r3, [pc, #456] @ (10023a14 ) +1002384a: 2008 movs r0, #8 +1002384c: 605a str r2, [r3, #4] +1002384e: 2204 movs r2, #4 +10023850: e9c3 2002 strd r2, r0, [r3, #8] +10023854: 2210 movs r2, #16 +10023856: 2020 movs r0, #32 +10023858: 261b movs r6, #27 +1002385a: e9c3 2004 strd r2, r0, [r3, #16] +1002385e: 2101 movs r1, #1 +10023860: 2240 movs r2, #64 @ 0x40 +10023862: 2080 movs r0, #128 @ 0x80 +10023864: 2736 movs r7, #54 @ 0x36 +10023866: e9c3 2006 strd r2, r0, [r3, #24] +1002386a: e9c3 6708 strd r6, r7, [r3, #32] +1002386e: 2200 movs r2, #0 +10023870: 6019 str r1, [r3, #0] +10023872: 2363 movs r3, #99 @ 0x63 +10023874: 4655 mov r5, sl +10023876: 4c68 ldr r4, [pc, #416] @ (10023a18 ) +10023878: 4e68 ldr r6, [pc, #416] @ (10023a1c ) +1002387a: 7023 strb r3, [r4, #0] +1002387c: f886 2063 strb.w r2, [r6, #99] @ 0x63 +10023880: a846 add r0, sp, #280 @ 0x118 +10023882: f815 3f01 ldrb.w r3, [r5, #1]! +10023886: f1c3 03ff rsb r3, r3, #255 @ 0xff +1002388a: 5cc3 ldrb r3, [r0, r3] +1002388c: 09da lsrs r2, r3, #7 +1002388e: ea42 0243 orr.w r2, r2, r3, lsl #1 +10023892: b257 sxtb r7, r2 +10023894: f3c2 1c42 ubfx ip, r2, #5, #3 +10023898: ea4c 0cc7 orr.w ip, ip, r7, lsl #3 +1002389c: ea83 030c eor.w r3, r3, ip +100238a0: f3c2 1cc0 ubfx ip, r2, #7, #1 +100238a4: 407b eors r3, r7 +100238a6: ea4c 0c47 orr.w ip, ip, r7, lsl #1 +100238aa: f3c2 1281 ubfx r2, r2, #6, #2 +100238ae: ea83 030c eor.w r3, r3, ip +100238b2: ea42 0287 orr.w r2, r2, r7, lsl #2 +100238b6: 4053 eors r3, r2 +100238b8: b2db uxtb r3, r3 +100238ba: f083 0363 eor.w r3, r3, #99 @ 0x63 +100238be: 54f1 strb r1, [r6, r3] +100238c0: 3101 adds r1, #1 +100238c2: f5b1 7f80 cmp.w r1, #256 @ 0x100 +100238c6: f804 3f01 strb.w r3, [r4, #1]! +100238ca: d1da bne.n 10023882 +100238cc: f89a 300e ldrb.w r3, [sl, #14] +100238d0: 4953 ldr r1, [pc, #332] @ (10023a20 ) +100238d2: 9302 str r3, [sp, #8] +100238d4: f89a 3009 ldrb.w r3, [sl, #9] +100238d8: f8df c168 ldr.w ip, [pc, #360] @ 10023a44 +100238dc: 9303 str r3, [sp, #12] +100238de: f89a 300d ldrb.w r3, [sl, #13] +100238e2: 4f50 ldr r7, [pc, #320] @ (10023a24 ) +100238e4: 9304 str r3, [sp, #16] +100238e6: f89a 300b ldrb.w r3, [sl, #11] +100238ea: 4e4f ldr r6, [pc, #316] @ (10023a28 ) +100238ec: 4d4f ldr r5, [pc, #316] @ (10023a2c ) +100238ee: 9305 str r3, [sp, #20] +100238f0: f501 7e80 add.w lr, r1, #256 @ 0x100 +100238f4: f811 2f01 ldrb.w r2, [r1, #1]! +100238f8: fa4f f882 sxtb.w r8, r2 +100238fc: ea4f 0348 mov.w r3, r8, lsl #1 +10023900: f1b8 0f00 cmp.w r8, #0 +10023904: b25b sxtb r3, r3 +10023906: bfb8 it lt +10023908: f083 031b eorlt.w r3, r3, #27 +1002390c: eb02 2402 add.w r4, r2, r2, lsl #8 +10023910: b2db uxtb r3, r3 +10023912: 405a eors r2, r3 +10023914: ea43 2304 orr.w r3, r3, r4, lsl #8 +10023918: ea83 6302 eor.w r3, r3, r2, lsl #24 +1002391c: ea4f 6833 mov.w r8, r3, ror #24 +10023920: ea4f 4433 mov.w r4, r3, ror #16 +10023924: ea4f 2233 mov.w r2, r3, ror #8 +10023928: 4571 cmp r1, lr +1002392a: f84c 3f04 str.w r3, [ip, #4]! +1002392e: f847 8f04 str.w r8, [r7, #4]! +10023932: f846 4f04 str.w r4, [r6, #4]! +10023936: f845 2f04 str.w r2, [r5, #4]! +1002393a: d1db bne.n 100238f4 +1002393c: 493c ldr r1, [pc, #240] @ (10023a30 ) +1002393e: f8df 8108 ldr.w r8, [pc, #264] @ 10023a48 +10023942: 4f3c ldr r7, [pc, #240] @ (10023a34 ) +10023944: 4e3c ldr r6, [pc, #240] @ (10023a38 ) +10023946: 4d3d ldr r5, [pc, #244] @ (10023a3c ) +10023948: 4c3d ldr r4, [pc, #244] @ (10023a40 ) +1002394a: f501 7b80 add.w fp, r1, #256 @ 0x100 +1002394e: f811 3f01 ldrb.w r3, [r1, #1]! +10023952: 2b00 cmp r3, #0 +10023954: d050 beq.n 100239f8 +10023956: f81a 9003 ldrb.w r9, [sl, r3] +1002395a: 9b04 ldr r3, [sp, #16] +1002395c: 4559 cmp r1, fp +1002395e: eb09 0203 add.w r2, r9, r3 +10023962: 9b03 ldr r3, [sp, #12] +10023964: eb09 0c03 add.w ip, r9, r3 +10023968: fba4 e302 umull lr, r3, r4, r2 +1002396c: ea4f 13d3 mov.w r3, r3, lsr #7 +10023970: ebc3 2303 rsb r3, r3, r3, lsl #8 +10023974: eba2 0203 sub.w r2, r2, r3 +10023978: f810 e002 ldrb.w lr, [r0, r2] +1002397c: ea4f 430e mov.w r3, lr, lsl #16 +10023980: 9301 str r3, [sp, #4] +10023982: 9b02 ldr r3, [sp, #8] +10023984: eb03 0209 add.w r2, r3, r9 +10023988: 9b05 ldr r3, [sp, #20] +1002398a: 4499 add r9, r3 +1002398c: fba4 e30c umull lr, r3, r4, ip +10023990: ea4f 13d3 mov.w r3, r3, lsr #7 +10023994: ebc3 2303 rsb r3, r3, r3, lsl #8 +10023998: ebac 0c03 sub.w ip, ip, r3 +1002399c: f810 c00c ldrb.w ip, [r0, ip] +100239a0: 9b01 ldr r3, [sp, #4] +100239a2: ea43 2c0c orr.w ip, r3, ip, lsl #8 +100239a6: fba4 e302 umull lr, r3, r4, r2 +100239aa: ea4f 13d3 mov.w r3, r3, lsr #7 +100239ae: ebc3 2303 rsb r3, r3, r3, lsl #8 +100239b2: eba2 0203 sub.w r2, r2, r3 +100239b6: 5c83 ldrb r3, [r0, r2] +100239b8: ea8c 0303 eor.w r3, ip, r3 +100239bc: fba4 c209 umull ip, r2, r4, r9 +100239c0: ea4f 12d2 mov.w r2, r2, lsr #7 +100239c4: ebc2 2202 rsb r2, r2, r2, lsl #8 +100239c8: eba9 0202 sub.w r2, r9, r2 +100239cc: 5c82 ldrb r2, [r0, r2] +100239ce: ea43 6302 orr.w r3, r3, r2, lsl #24 +100239d2: ea4f 6233 mov.w r2, r3, ror #24 +100239d6: f848 3f04 str.w r3, [r8, #4]! +100239da: f847 2f04 str.w r2, [r7, #4]! +100239de: ea4f 4233 mov.w r2, r3, ror #16 +100239e2: ea4f 2333 mov.w r3, r3, ror #8 +100239e6: f846 2f04 str.w r2, [r6, #4]! +100239ea: f845 3f04 str.w r3, [r5, #4]! +100239ee: d1ae bne.n 1002394e +100239f0: f50d 7d07 add.w sp, sp, #540 @ 0x21c +100239f4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100239f8: 4559 cmp r1, fp +100239fa: f848 3f04 str.w r3, [r8, #4]! +100239fe: f847 3f04 str.w r3, [r7, #4]! +10023a02: f846 3f04 str.w r3, [r6, #4]! +10023a06: f845 3f04 str.w r3, [r5, #4]! +10023a0a: d1a0 bne.n 1002394e +10023a0c: f50d 7d07 add.w sp, sp, #540 @ 0x21c +10023a10: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10023a14: 200008b0 .word 0x200008b0 +10023a18: 20000630 .word 0x20000630 +10023a1c: 200018d8 .word 0x200018d8 +10023a20: 2000062f .word 0x2000062f +10023a24: 20000cd4 .word 0x20000cd4 +10023a28: 200010d4 .word 0x200010d4 +10023a2c: 200014d4 .word 0x200014d4 +10023a30: 200018d7 .word 0x200018d7 +10023a34: 20001dd4 .word 0x20001dd4 +10023a38: 200021d4 .word 0x200021d4 +10023a3c: 200025d4 .word 0x200025d4 +10023a40: 80808081 .word 0x80808081 +10023a44: 200008d4 .word 0x200008d4 +10023a48: 200019d4 .word 0x200019d4 + +10023a4c : +10023a4c: f44f 728c mov.w r2, #280 @ 0x118 +10023a50: 2100 movs r1, #0 +10023a52: f001 b837 b.w 10024ac4 +10023a56: bf00 nop + +10023a58 : +10023a58: b118 cbz r0, 10023a62 +10023a5a: f44f 718c mov.w r1, #280 @ 0x118 +10023a5e: f001 b80d b.w 10024a7c +10023a62: 4770 bx lr + +10023a64 : +10023a64: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10023a68: 2ac0 cmp r2, #192 @ 0xc0 +10023a6a: 4615 mov r5, r2 +10023a6c: 4604 mov r4, r0 +10023a6e: 460e mov r6, r1 +10023a70: b083 sub sp, #12 +10023a72: d038 beq.n 10023ae6 +10023a74: f5b2 7f80 cmp.w r2, #256 @ 0x100 +10023a78: d029 beq.n 10023ace +10023a7a: 2a80 cmp r2, #128 @ 0x80 +10023a7c: d135 bne.n 10023aea +10023a7e: 230a movs r3, #10 +10023a80: 4fb2 ldr r7, [pc, #712] @ (10023d4c ) +10023a82: 6023 str r3, [r4, #0] +10023a84: 683a ldr r2, [r7, #0] +10023a86: b342 cbz r2, 10023ada +10023a88: 2200 movs r2, #0 +10023a8a: 6062 str r2, [r4, #4] +10023a8c: 6837 ldr r7, [r6, #0] +10023a8e: 096d lsrs r5, r5, #5 +10023a90: 60a7 str r7, [r4, #8] +10023a92: 6872 ldr r2, [r6, #4] +10023a94: 2d04 cmp r5, #4 +10023a96: 60e2 str r2, [r4, #12] +10023a98: 68b2 ldr r2, [r6, #8] +10023a9a: 6122 str r2, [r4, #16] +10023a9c: 68f2 ldr r2, [r6, #12] +10023a9e: 6162 str r2, [r4, #20] +10023aa0: d009 beq.n 10023ab6 +10023aa2: 6932 ldr r2, [r6, #16] +10023aa4: 2d06 cmp r5, #6 +10023aa6: 61a2 str r2, [r4, #24] +10023aa8: 6972 ldr r2, [r6, #20] +10023aaa: 61e2 str r2, [r4, #28] +10023aac: d003 beq.n 10023ab6 +10023aae: 69b2 ldr r2, [r6, #24] +10023ab0: 6222 str r2, [r4, #32] +10023ab2: 69f2 ldr r2, [r6, #28] +10023ab4: 6262 str r2, [r4, #36] @ 0x24 +10023ab6: 2b0c cmp r3, #12 +10023ab8: f000 81a7 beq.w 10023e0a +10023abc: 2b0e cmp r3, #14 +10023abe: f000 814b beq.w 10023d58 +10023ac2: 2b0a cmp r3, #10 +10023ac4: d016 beq.n 10023af4 +10023ac6: 2000 movs r0, #0 +10023ac8: b003 add sp, #12 +10023aca: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10023ace: 230e movs r3, #14 +10023ad0: 4f9e ldr r7, [pc, #632] @ (10023d4c ) +10023ad2: 6023 str r3, [r4, #0] +10023ad4: 683a ldr r2, [r7, #0] +10023ad6: 2a00 cmp r2, #0 +10023ad8: d1d6 bne.n 10023a88 +10023ada: f7ff fe8b bl 100237f4 +10023ade: 2301 movs r3, #1 +10023ae0: 603b str r3, [r7, #0] +10023ae2: 6823 ldr r3, [r4, #0] +10023ae4: e7d0 b.n 10023a88 +10023ae6: 230c movs r3, #12 +10023ae8: e7ca b.n 10023a80 +10023aea: f06f 001f mvn.w r0, #31 +10023aee: b003 add sp, #12 +10023af0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10023af4: 6963 ldr r3, [r4, #20] +10023af6: 4996 ldr r1, [pc, #600] @ (10023d50 ) +10023af8: f3c3 2207 ubfx r2, r3, #8, #8 +10023afc: 5c8d ldrb r5, [r1, r2] +10023afe: 4e95 ldr r6, [pc, #596] @ (10023d54 ) +10023b00: 68e2 ldr r2, [r4, #12] +10023b02: ea4f 6c13 mov.w ip, r3, lsr #24 +10023b06: 9201 str r2, [sp, #4] +10023b08: 6832 ldr r2, [r6, #0] +10023b0a: f811 c00c ldrb.w ip, [r1, ip] +10023b0e: 4057 eors r7, r2 +10023b10: 407d eors r5, r7 +10023b12: b2df uxtb r7, r3 +10023b14: 5dcf ldrb r7, [r1, r7] +10023b16: ea85 450c eor.w r5, r5, ip, lsl #16 +10023b1a: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023b1e: f3c3 4707 ubfx r7, r3, #16, #8 +10023b22: 5dcf ldrb r7, [r1, r7] +10023b24: 9a01 ldr r2, [sp, #4] +10023b26: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023b2a: 6920 ldr r0, [r4, #16] +10023b2c: 406a eors r2, r5 +10023b2e: ea82 0700 eor.w r7, r2, r0 +10023b32: 407b eors r3, r7 +10023b34: e9c4 5206 strd r5, r2, [r4, #24] +10023b38: e9c4 7308 strd r7, r3, [r4, #32] +10023b3c: 6877 ldr r7, [r6, #4] +10023b3e: 406f eors r7, r5 +10023b40: f3c3 2507 ubfx r5, r3, #8, #8 +10023b44: 5d4d ldrb r5, [r1, r5] +10023b46: 407d eors r5, r7 +10023b48: 0e1f lsrs r7, r3, #24 +10023b4a: 5dcf ldrb r7, [r1, r7] +10023b4c: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023b50: b2df uxtb r7, r3 +10023b52: 5dcf ldrb r7, [r1, r7] +10023b54: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023b58: f3c3 4707 ubfx r7, r3, #16, #8 +10023b5c: 5dcf ldrb r7, [r1, r7] +10023b5e: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023b62: 406a eors r2, r5 +10023b64: e9c4 520a strd r5, r2, [r4, #40] @ 0x28 +10023b68: 4068 eors r0, r5 +10023b6a: 68b7 ldr r7, [r6, #8] +10023b6c: ea80 0c03 eor.w ip, r0, r3 +10023b70: 6320 str r0, [r4, #48] @ 0x30 +10023b72: f8c4 c034 str.w ip, [r4, #52] @ 0x34 +10023b76: 407d eors r5, r7 +10023b78: f3cc 2707 ubfx r7, ip, #8, #8 +10023b7c: 5dcf ldrb r7, [r1, r7] +10023b7e: 407d eors r5, r7 +10023b80: ea4f 671c mov.w r7, ip, lsr #24 +10023b84: 5dcf ldrb r7, [r1, r7] +10023b86: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023b8a: fa5f f78c uxtb.w r7, ip +10023b8e: 5dcf ldrb r7, [r1, r7] +10023b90: f3cc 4c07 ubfx ip, ip, #16, #8 +10023b94: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023b98: f811 700c ldrb.w r7, [r1, ip] +10023b9c: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023ba0: 406a eors r2, r5 +10023ba2: 4053 eors r3, r2 +10023ba4: ea82 0700 eor.w r7, r2, r0 +10023ba8: e9c4 520e strd r5, r2, [r4, #56] @ 0x38 +10023bac: 6463 str r3, [r4, #68] @ 0x44 +10023bae: 6427 str r7, [r4, #64] @ 0x40 +10023bb0: 68f7 ldr r7, [r6, #12] +10023bb2: 406f eors r7, r5 +10023bb4: f3c3 2507 ubfx r5, r3, #8, #8 +10023bb8: 5d4d ldrb r5, [r1, r5] +10023bba: 407d eors r5, r7 +10023bbc: 0e1f lsrs r7, r3, #24 +10023bbe: 5dcf ldrb r7, [r1, r7] +10023bc0: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023bc4: b2df uxtb r7, r3 +10023bc6: 5dcf ldrb r7, [r1, r7] +10023bc8: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023bcc: f3c3 4707 ubfx r7, r3, #16, #8 +10023bd0: 5dcf ldrb r7, [r1, r7] +10023bd2: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023bd6: 406a eors r2, r5 +10023bd8: e9c4 5212 strd r5, r2, [r4, #72] @ 0x48 +10023bdc: 4068 eors r0, r5 +10023bde: 6937 ldr r7, [r6, #16] +10023be0: ea83 0c00 eor.w ip, r3, r0 +10023be4: 6520 str r0, [r4, #80] @ 0x50 +10023be6: f8c4 c054 str.w ip, [r4, #84] @ 0x54 +10023bea: 407d eors r5, r7 +10023bec: f3cc 2707 ubfx r7, ip, #8, #8 +10023bf0: 5dcf ldrb r7, [r1, r7] +10023bf2: 407d eors r5, r7 +10023bf4: ea4f 671c mov.w r7, ip, lsr #24 +10023bf8: 5dcf ldrb r7, [r1, r7] +10023bfa: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023bfe: fa5f f78c uxtb.w r7, ip +10023c02: 5dcf ldrb r7, [r1, r7] +10023c04: f3cc 4c07 ubfx ip, ip, #16, #8 +10023c08: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023c0c: f811 700c ldrb.w r7, [r1, ip] +10023c10: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023c14: 406a eors r2, r5 +10023c16: ea80 0702 eor.w r7, r0, r2 +10023c1a: e9c4 5216 strd r5, r2, [r4, #88] @ 0x58 +10023c1e: 6627 str r7, [r4, #96] @ 0x60 +10023c20: 6977 ldr r7, [r6, #20] +10023c22: 4053 eors r3, r2 +10023c24: 6663 str r3, [r4, #100] @ 0x64 +10023c26: 406f eors r7, r5 +10023c28: f3c3 2507 ubfx r5, r3, #8, #8 +10023c2c: 5d4d ldrb r5, [r1, r5] +10023c2e: 407d eors r5, r7 +10023c30: 0e1f lsrs r7, r3, #24 +10023c32: 5dcf ldrb r7, [r1, r7] +10023c34: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023c38: b2df uxtb r7, r3 +10023c3a: 5dcf ldrb r7, [r1, r7] +10023c3c: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023c40: f3c3 4707 ubfx r7, r3, #16, #8 +10023c44: 5dcf ldrb r7, [r1, r7] +10023c46: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023c4a: 406a eors r2, r5 +10023c4c: e9c4 521a strd r5, r2, [r4, #104] @ 0x68 +10023c50: 4068 eors r0, r5 +10023c52: 69b7 ldr r7, [r6, #24] +10023c54: ea83 0c00 eor.w ip, r3, r0 +10023c58: 6720 str r0, [r4, #112] @ 0x70 +10023c5a: f8c4 c074 str.w ip, [r4, #116] @ 0x74 +10023c5e: 407d eors r5, r7 +10023c60: f3cc 2707 ubfx r7, ip, #8, #8 +10023c64: 5dcf ldrb r7, [r1, r7] +10023c66: 407d eors r5, r7 +10023c68: ea4f 671c mov.w r7, ip, lsr #24 +10023c6c: 5dcf ldrb r7, [r1, r7] +10023c6e: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023c72: fa5f f78c uxtb.w r7, ip +10023c76: 5dcf ldrb r7, [r1, r7] +10023c78: f3cc 4c07 ubfx ip, ip, #16, #8 +10023c7c: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023c80: f811 700c ldrb.w r7, [r1, ip] +10023c84: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023c88: 406a eors r2, r5 +10023c8a: 4053 eors r3, r2 +10023c8c: ea80 0702 eor.w r7, r0, r2 +10023c90: e9c4 521e strd r5, r2, [r4, #120] @ 0x78 +10023c94: e9c4 7320 strd r7, r3, [r4, #128] @ 0x80 +10023c98: 69f7 ldr r7, [r6, #28] +10023c9a: 406f eors r7, r5 +10023c9c: f3c3 2507 ubfx r5, r3, #8, #8 +10023ca0: 5d4d ldrb r5, [r1, r5] +10023ca2: 407d eors r5, r7 +10023ca4: 0e1f lsrs r7, r3, #24 +10023ca6: 5dcf ldrb r7, [r1, r7] +10023ca8: ea85 4507 eor.w r5, r5, r7, lsl #16 +10023cac: b2df uxtb r7, r3 +10023cae: 5dcf ldrb r7, [r1, r7] +10023cb0: ea85 6507 eor.w r5, r5, r7, lsl #24 +10023cb4: f3c3 4707 ubfx r7, r3, #16, #8 +10023cb8: 5dcf ldrb r7, [r1, r7] +10023cba: ea85 2507 eor.w r5, r5, r7, lsl #8 +10023cbe: 406a eors r2, r5 +10023cc0: e9c4 5222 strd r5, r2, [r4, #136] @ 0x88 +10023cc4: 4068 eors r0, r5 +10023cc6: 6a37 ldr r7, [r6, #32] +10023cc8: ea83 0c00 eor.w ip, r3, r0 +10023ccc: f8c4 0090 str.w r0, [r4, #144] @ 0x90 +10023cd0: f8c4 c094 str.w ip, [r4, #148] @ 0x94 +10023cd4: 407d eors r5, r7 +10023cd6: 6a77 ldr r7, [r6, #36] @ 0x24 +10023cd8: f3cc 2607 ubfx r6, ip, #8, #8 +10023cdc: 5d8e ldrb r6, [r1, r6] +10023cde: 4075 eors r5, r6 +10023ce0: ea4f 661c mov.w r6, ip, lsr #24 +10023ce4: 5d8e ldrb r6, [r1, r6] +10023ce6: ea85 4506 eor.w r5, r5, r6, lsl #16 +10023cea: fa5f f68c uxtb.w r6, ip +10023cee: 5d8e ldrb r6, [r1, r6] +10023cf0: ea85 6506 eor.w r5, r5, r6, lsl #24 +10023cf4: f3cc 4607 ubfx r6, ip, #16, #8 +10023cf8: 5d8e ldrb r6, [r1, r6] +10023cfa: ea85 2506 eor.w r5, r5, r6, lsl #8 +10023cfe: 406a eors r2, r5 +10023d00: 4053 eors r3, r2 +10023d02: ea80 0602 eor.w r6, r0, r2 +10023d06: f8c4 5098 str.w r5, [r4, #152] @ 0x98 +10023d0a: f8c4 209c str.w r2, [r4, #156] @ 0x9c +10023d0e: f8c4 30a4 str.w r3, [r4, #164] @ 0xa4 +10023d12: f8c4 60a0 str.w r6, [r4, #160] @ 0xa0 +10023d16: f3c3 2607 ubfx r6, r3, #8, #8 +10023d1a: 5d8e ldrb r6, [r1, r6] +10023d1c: 407d eors r5, r7 +10023d1e: 4075 eors r5, r6 +10023d20: 0e1e lsrs r6, r3, #24 +10023d22: 5d8e ldrb r6, [r1, r6] +10023d24: ea85 4506 eor.w r5, r5, r6, lsl #16 +10023d28: b2de uxtb r6, r3 +10023d2a: 5d8e ldrb r6, [r1, r6] +10023d2c: ea85 6506 eor.w r5, r5, r6, lsl #24 +10023d30: f3c3 4607 ubfx r6, r3, #16, #8 +10023d34: 5d89 ldrb r1, [r1, r6] +10023d36: ea85 2101 eor.w r1, r5, r1, lsl #8 +10023d3a: 4048 eors r0, r1 +10023d3c: 404a eors r2, r1 +10023d3e: 4043 eors r3, r0 +10023d40: e9c4 122a strd r1, r2, [r4, #168] @ 0xa8 +10023d44: e9c4 032c strd r0, r3, [r4, #176] @ 0xb0 +10023d48: e6bd b.n 10023ac6 +10023d4a: bf00 nop +10023d4c: 200029f8 .word 0x200029f8 +10023d50: 20000630 .word 0x20000630 +10023d54: 200008b0 .word 0x200008b0 +10023d58: f8df a324 ldr.w sl, [pc, #804] @ 10024080 +10023d5c: 49c7 ldr r1, [pc, #796] @ (1002407c ) +10023d5e: f8d4 e018 ldr.w lr, [r4, #24] +10023d62: 68e6 ldr r6, [r4, #12] +10023d64: 6a60 ldr r0, [r4, #36] @ 0x24 +10023d66: f104 0308 add.w r3, r4, #8 +10023d6a: e9d4 8907 ldrd r8, r9, [r4, #28] +10023d6e: e9d4 c504 ldrd ip, r5, [r4, #16] +10023d72: f10a 041c add.w r4, sl, #28 +10023d76: f3c0 2207 ubfx r2, r0, #8, #8 +10023d7a: ea4f 6b10 mov.w fp, r0, lsr #24 +10023d7e: f811 b00b ldrb.w fp, [r1, fp] +10023d82: 5c8a ldrb r2, [r1, r2] +10023d84: ea42 420b orr.w r2, r2, fp, lsl #16 +10023d88: f85a bf04 ldr.w fp, [sl, #4]! +10023d8c: ea82 020b eor.w r2, r2, fp +10023d90: fa5f fb80 uxtb.w fp, r0 +10023d94: f811 b00b ldrb.w fp, [r1, fp] +10023d98: 45a2 cmp sl, r4 +10023d9a: ea82 620b eor.w r2, r2, fp, lsl #24 +10023d9e: f3c0 4b07 ubfx fp, r0, #16, #8 +10023da2: f811 b00b ldrb.w fp, [r1, fp] +10023da6: ea82 220b eor.w r2, r2, fp, lsl #8 +10023daa: ea87 0702 eor.w r7, r7, r2 +10023dae: ea86 0607 eor.w r6, r6, r7 +10023db2: ea8c 0c06 eor.w ip, ip, r6 +10023db6: ea85 050c eor.w r5, r5, ip +10023dba: e9c3 7608 strd r7, r6, [r3, #32] +10023dbe: e9c3 c50a strd ip, r5, [r3, #40] @ 0x28 +10023dc2: ea4f 6215 mov.w r2, r5, lsr #24 +10023dc6: f811 b002 ldrb.w fp, [r1, r2] +10023dca: b2ea uxtb r2, r5 +10023dcc: 5c8a ldrb r2, [r1, r2] +10023dce: ea42 620b orr.w r2, r2, fp, lsl #24 +10023dd2: f3c5 2b07 ubfx fp, r5, #8, #8 +10023dd6: f811 b00b ldrb.w fp, [r1, fp] +10023dda: ea42 220b orr.w r2, r2, fp, lsl #8 +10023dde: f3c5 4b07 ubfx fp, r5, #16, #8 +10023de2: f811 b00b ldrb.w fp, [r1, fp] +10023de6: ea42 420b orr.w r2, r2, fp, lsl #16 +10023dea: ea8e 0e02 eor.w lr, lr, r2 +10023dee: ea88 080e eor.w r8, r8, lr +10023df2: ea89 0908 eor.w r9, r9, r8 +10023df6: ea80 0009 eor.w r0, r0, r9 +10023dfa: e9c3 e80c strd lr, r8, [r3, #48] @ 0x30 +10023dfe: e9c3 900e strd r9, r0, [r3, #56] @ 0x38 +10023e02: f103 0320 add.w r3, r3, #32 +10023e06: d1b6 bne.n 10023d76 +10023e08: e65d b.n 10023ac6 +10023e0a: 69e1 ldr r1, [r4, #28] +10023e0c: 4a9b ldr r2, [pc, #620] @ (1002407c ) +10023e0e: f8df 9274 ldr.w r9, [pc, #628] @ 10024084 +10023e12: f3c1 2607 ubfx r6, r1, #8, #8 +10023e16: f812 e006 ldrb.w lr, [r2, r6] +10023e1a: f8d9 6000 ldr.w r6, [r9] +10023e1e: 68e3 ldr r3, [r4, #12] +10023e20: 407e eors r6, r7 +10023e22: 0e0f lsrs r7, r1, #24 +10023e24: 5dd7 ldrb r7, [r2, r7] +10023e26: ea8e 0606 eor.w r6, lr, r6 +10023e2a: ea86 4607 eor.w r6, r6, r7, lsl #16 +10023e2e: b2cf uxtb r7, r1 +10023e30: 5dd7 ldrb r7, [r2, r7] +10023e32: 6925 ldr r5, [r4, #16] +10023e34: ea86 6607 eor.w r6, r6, r7, lsl #24 +10023e38: f3c1 4707 ubfx r7, r1, #16, #8 +10023e3c: 5dd7 ldrb r7, [r2, r7] +10023e3e: e9d4 0c05 ldrd r0, ip, [r4, #20] +10023e42: ea86 2607 eor.w r6, r6, r7, lsl #8 +10023e46: ea83 0706 eor.w r7, r3, r6 +10023e4a: ea85 0307 eor.w r3, r5, r7 +10023e4e: ea80 0e03 eor.w lr, r0, r3 +10023e52: e9c4 3e0a strd r3, lr, [r4, #40] @ 0x28 +10023e56: ea8c 030e eor.w r3, ip, lr +10023e5a: 4059 eors r1, r3 +10023e5c: e9c4 6708 strd r6, r7, [r4, #32] +10023e60: e9c4 310c strd r3, r1, [r4, #48] @ 0x30 +10023e64: f8d9 0004 ldr.w r0, [r9, #4] +10023e68: f3c1 2307 ubfx r3, r1, #8, #8 +10023e6c: 4046 eors r6, r0 +10023e6e: 5cd0 ldrb r0, [r2, r3] +10023e70: 0e0b lsrs r3, r1, #24 +10023e72: 5cd3 ldrb r3, [r2, r3] +10023e74: 4070 eors r0, r6 +10023e76: ea80 4003 eor.w r0, r0, r3, lsl #16 +10023e7a: b2cb uxtb r3, r1 +10023e7c: 5cd3 ldrb r3, [r2, r3] +10023e7e: ea80 6003 eor.w r0, r0, r3, lsl #24 +10023e82: f3c1 4307 ubfx r3, r1, #16, #8 +10023e86: 5cd3 ldrb r3, [r2, r3] +10023e88: ea80 2303 eor.w r3, r0, r3, lsl #8 +10023e8c: 405d eors r5, r3 +10023e8e: 405f eors r7, r3 +10023e90: ea8e 0605 eor.w r6, lr, r5 +10023e94: e9c4 370e strd r3, r7, [r4, #56] @ 0x38 +10023e98: 6466 str r6, [r4, #68] @ 0x44 +10023e9a: ea8c 0005 eor.w r0, ip, r5 +10023e9e: f8d9 6008 ldr.w r6, [r9, #8] +10023ea2: ea81 0800 eor.w r8, r1, r0 +10023ea6: 6425 str r5, [r4, #64] @ 0x40 +10023ea8: 64a0 str r0, [r4, #72] @ 0x48 +10023eaa: f8c4 804c str.w r8, [r4, #76] @ 0x4c +10023eae: 4073 eors r3, r6 +10023eb0: f3c8 2607 ubfx r6, r8, #8, #8 +10023eb4: 5d96 ldrb r6, [r2, r6] +10023eb6: 405e eors r6, r3 +10023eb8: ea4f 6318 mov.w r3, r8, lsr #24 +10023ebc: 5cd3 ldrb r3, [r2, r3] +10023ebe: ea86 4603 eor.w r6, r6, r3, lsl #16 +10023ec2: fa5f f388 uxtb.w r3, r8 +10023ec6: 5cd3 ldrb r3, [r2, r3] +10023ec8: f3c8 4807 ubfx r8, r8, #16, #8 +10023ecc: ea86 6603 eor.w r6, r6, r3, lsl #24 +10023ed0: f812 3008 ldrb.w r3, [r2, r8] +10023ed4: ea86 2803 eor.w r8, r6, r3, lsl #8 +10023ed8: ea87 0308 eor.w r3, r7, r8 +10023edc: ea8e 0e03 eor.w lr, lr, r3 +10023ee0: ea85 0603 eor.w r6, r5, r3 +10023ee4: f8c4 8050 str.w r8, [r4, #80] @ 0x50 +10023ee8: ea80 000e eor.w r0, r0, lr +10023eec: 65a6 str r6, [r4, #88] @ 0x58 +10023eee: f8d9 600c ldr.w r6, [r9, #12] +10023ef2: 6620 str r0, [r4, #96] @ 0x60 +10023ef4: ea81 000e eor.w r0, r1, lr +10023ef8: 6563 str r3, [r4, #84] @ 0x54 +10023efa: f8c4 e05c str.w lr, [r4, #92] @ 0x5c +10023efe: 6660 str r0, [r4, #100] @ 0x64 +10023f00: ea88 0806 eor.w r8, r8, r6 +10023f04: f3c0 2607 ubfx r6, r0, #8, #8 +10023f08: 5d96 ldrb r6, [r2, r6] +10023f0a: 0e07 lsrs r7, r0, #24 +10023f0c: 5dd7 ldrb r7, [r2, r7] +10023f0e: ea86 0608 eor.w r6, r6, r8 +10023f12: ea86 4607 eor.w r6, r6, r7, lsl #16 +10023f16: b2c7 uxtb r7, r0 +10023f18: 5dd7 ldrb r7, [r2, r7] +10023f1a: ea86 6607 eor.w r6, r6, r7, lsl #24 +10023f1e: f3c0 4707 ubfx r7, r0, #16, #8 +10023f22: 5dd7 ldrb r7, [r2, r7] +10023f24: ea86 2607 eor.w r6, r6, r7, lsl #8 +10023f28: ea8c 0c06 eor.w ip, ip, r6 +10023f2c: 4075 eors r5, r6 +10023f2e: ea80 000c eor.w r0, r0, ip +10023f32: ea8e 0705 eor.w r7, lr, r5 +10023f36: 4073 eors r3, r6 +10023f38: e9c4 631a strd r6, r3, [r4, #104] @ 0x68 +10023f3c: e9c4 c01e strd ip, r0, [r4, #120] @ 0x78 +10023f40: 6767 str r7, [r4, #116] @ 0x74 +10023f42: f8d9 7010 ldr.w r7, [r9, #16] +10023f46: 6725 str r5, [r4, #112] @ 0x70 +10023f48: 4077 eors r7, r6 +10023f4a: f3c0 2607 ubfx r6, r0, #8, #8 +10023f4e: 5d96 ldrb r6, [r2, r6] +10023f50: 407e eors r6, r7 +10023f52: 0e07 lsrs r7, r0, #24 +10023f54: 5dd7 ldrb r7, [r2, r7] +10023f56: ea86 4607 eor.w r6, r6, r7, lsl #16 +10023f5a: b2c7 uxtb r7, r0 +10023f5c: 5dd7 ldrb r7, [r2, r7] +10023f5e: f3c0 4007 ubfx r0, r0, #16, #8 +10023f62: 5c10 ldrb r0, [r2, r0] +10023f64: ea86 6607 eor.w r6, r6, r7, lsl #24 +10023f68: ea86 2700 eor.w r7, r6, r0, lsl #8 +10023f6c: 407b eors r3, r7 +10023f6e: ea8e 0003 eor.w r0, lr, r3 +10023f72: ea85 0603 eor.w r6, r5, r3 +10023f76: f8c4 6088 str.w r6, [r4, #136] @ 0x88 +10023f7a: ea8c 0600 eor.w r6, ip, r0 +10023f7e: e9c4 7320 strd r7, r3, [r4, #128] @ 0x80 +10023f82: f8c4 6090 str.w r6, [r4, #144] @ 0x90 +10023f86: f8d9 6014 ldr.w r6, [r9, #20] +10023f8a: 4059 eors r1, r3 +10023f8c: f8c4 008c str.w r0, [r4, #140] @ 0x8c +10023f90: f8c4 1094 str.w r1, [r4, #148] @ 0x94 +10023f94: 4077 eors r7, r6 +10023f96: f3c1 2607 ubfx r6, r1, #8, #8 +10023f9a: 5d96 ldrb r6, [r2, r6] +10023f9c: 407e eors r6, r7 +10023f9e: 0e0f lsrs r7, r1, #24 +10023fa0: 5dd7 ldrb r7, [r2, r7] +10023fa2: ea86 4607 eor.w r6, r6, r7, lsl #16 +10023fa6: b2cf uxtb r7, r1 +10023fa8: 5dd7 ldrb r7, [r2, r7] +10023faa: ea86 6607 eor.w r6, r6, r7, lsl #24 +10023fae: f3c1 4707 ubfx r7, r1, #16, #8 +10023fb2: 5dd7 ldrb r7, [r2, r7] +10023fb4: ea86 2607 eor.w r6, r6, r7, lsl #8 +10023fb8: 4075 eors r5, r6 +10023fba: ea80 0705 eor.w r7, r0, r5 +10023fbe: 4073 eors r3, r6 +10023fc0: e9c4 6326 strd r6, r3, [r4, #152] @ 0x98 +10023fc4: ea8c 0e05 eor.w lr, ip, r5 +10023fc8: f8c4 70a4 str.w r7, [r4, #164] @ 0xa4 +10023fcc: f8d9 7018 ldr.w r7, [r9, #24] +10023fd0: ea81 080e eor.w r8, r1, lr +10023fd4: f8c4 50a0 str.w r5, [r4, #160] @ 0xa0 +10023fd8: f8c4 e0a8 str.w lr, [r4, #168] @ 0xa8 +10023fdc: f8c4 80ac str.w r8, [r4, #172] @ 0xac +10023fe0: ea86 0a07 eor.w sl, r6, r7 +10023fe4: f3c8 2607 ubfx r6, r8, #8, #8 +10023fe8: 5d96 ldrb r6, [r2, r6] +10023fea: f8d9 701c ldr.w r7, [r9, #28] +10023fee: ea4f 6918 mov.w r9, r8, lsr #24 +10023ff2: f812 9009 ldrb.w r9, [r2, r9] +10023ff6: ea86 060a eor.w r6, r6, sl +10023ffa: ea86 4609 eor.w r6, r6, r9, lsl #16 +10023ffe: fa5f f988 uxtb.w r9, r8 +10024002: f812 9009 ldrb.w r9, [r2, r9] +10024006: f3c8 4807 ubfx r8, r8, #16, #8 +1002400a: f812 8008 ldrb.w r8, [r2, r8] +1002400e: ea86 6609 eor.w r6, r6, r9, lsl #24 +10024012: ea86 2608 eor.w r6, r6, r8, lsl #8 +10024016: 4073 eors r3, r6 +10024018: 4058 eors r0, r3 +1002401a: 4041 eors r1, r0 +1002401c: f8c4 60b0 str.w r6, [r4, #176] @ 0xb0 +10024020: ea8e 0e00 eor.w lr, lr, r0 +10024024: 407e eors r6, r7 +10024026: ea85 0703 eor.w r7, r5, r3 +1002402a: f8c4 30b4 str.w r3, [r4, #180] @ 0xb4 +1002402e: f8c4 00bc str.w r0, [r4, #188] @ 0xbc +10024032: f8c4 10c4 str.w r1, [r4, #196] @ 0xc4 +10024036: f8c4 70b8 str.w r7, [r4, #184] @ 0xb8 +1002403a: f8c4 e0c0 str.w lr, [r4, #192] @ 0xc0 +1002403e: f3c1 2707 ubfx r7, r1, #8, #8 +10024042: 5dd7 ldrb r7, [r2, r7] +10024044: 407e eors r6, r7 +10024046: 0e0f lsrs r7, r1, #24 +10024048: 5dd7 ldrb r7, [r2, r7] +1002404a: ea86 4607 eor.w r6, r6, r7, lsl #16 +1002404e: b2cf uxtb r7, r1 +10024050: 5dd7 ldrb r7, [r2, r7] +10024052: ea86 6607 eor.w r6, r6, r7, lsl #24 +10024056: f3c1 4707 ubfx r7, r1, #16, #8 +1002405a: 5dd2 ldrb r2, [r2, r7] +1002405c: ea86 2202 eor.w r2, r6, r2, lsl #8 +10024060: 4055 eors r5, r2 +10024062: ea82 060c eor.w r6, r2, ip +10024066: 4053 eors r3, r2 +10024068: 4068 eors r0, r5 +1002406a: 4071 eors r1, r6 +1002406c: e9c4 2332 strd r2, r3, [r4, #200] @ 0xc8 +10024070: e9c4 5034 strd r5, r0, [r4, #208] @ 0xd0 +10024074: e9c4 6136 strd r6, r1, [r4, #216] @ 0xd8 +10024078: e525 b.n 10023ac6 +1002407a: bf00 nop +1002407c: 20000630 .word 0x20000630 +10024080: 200008ac .word 0x200008ac +10024084: 200008b0 .word 0x200008b0 + +10024088 : +10024088: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1002408c: b0cb sub sp, #300 @ 0x12c +1002408e: af04 add r7, sp, #16 +10024090: 4604 mov r4, r0 +10024092: 460d mov r5, r1 +10024094: 4616 mov r6, r2 +10024096: 2100 movs r1, #0 +10024098: f44f 728c mov.w r2, #280 @ 0x118 +1002409c: 4638 mov r0, r7 +1002409e: f000 fd11 bl 10024ac4 +100240a2: 2300 movs r3, #0 +100240a4: 4632 mov r2, r6 +100240a6: 4629 mov r1, r5 +100240a8: 4638 mov r0, r7 +100240aa: 6063 str r3, [r4, #4] +100240ac: f7ff fcda bl 10023a64 +100240b0: 4683 mov fp, r0 +100240b2: 2800 cmp r0, #0 +100240b4: f040 80c6 bne.w 10024244 +100240b8: e9d7 8300 ldrd r8, r3, [r7] +100240bc: 4621 mov r1, r4 +100240be: eb03 0388 add.w r3, r3, r8, lsl #2 +100240c2: aa06 add r2, sp, #24 +100240c4: eb02 0c83 add.w ip, r2, r3, lsl #2 +100240c8: f852 5023 ldr.w r5, [r2, r3, lsl #2] +100240cc: f8dc 000c ldr.w r0, [ip, #12] +100240d0: f108 39ff add.w r9, r8, #4294967295 @ 0xffffffff +100240d4: f1b9 0f00 cmp.w r9, #0 +100240d8: f841 8b18 str.w r8, [r1], #24 +100240dc: e9dc 3201 ldrd r3, r2, [ip, #4] +100240e0: f1ac 0a10 sub.w sl, ip, #16 +100240e4: e9c4 5302 strd r5, r3, [r4, #8] +100240e8: e9c4 2004 strd r2, r0, [r4, #16] +100240ec: f340 809e ble.w 1002422c +100240f0: e9cd 8a01 strd r8, sl, [sp, #4] +100240f4: f104 0028 add.w r0, r4, #40 @ 0x28 +100240f8: f8df e16c ldr.w lr, [pc, #364] @ 10024268 +100240fc: 4b56 ldr r3, [pc, #344] @ (10024258 ) +100240fe: 4e57 ldr r6, [pc, #348] @ (1002425c ) +10024100: 4d57 ldr r5, [pc, #348] @ (10024260 ) +10024102: 4c58 ldr r4, [pc, #352] @ (10024264 ) +10024104: f1ac 0c20 sub.w ip, ip, #32 +10024108: 9103 str r1, [sp, #12] +1002410a: e9dc 1204 ldrd r1, r2, [ip, #16] +1002410e: fa5f f881 uxtb.w r8, r1 +10024112: ea4f 6a11 mov.w sl, r1, lsr #24 +10024116: f813 8008 ldrb.w r8, [r3, r8] +1002411a: f813 a00a ldrb.w sl, [r3, sl] +1002411e: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +10024122: f856 a02a ldr.w sl, [r6, sl, lsl #2] +10024126: f1b9 0901 subs.w r9, r9, #1 +1002412a: ea88 080a eor.w r8, r8, sl +1002412e: f3c1 2a07 ubfx sl, r1, #8, #8 +10024132: f813 a00a ldrb.w sl, [r3, sl] +10024136: f3c1 4107 ubfx r1, r1, #16, #8 +1002413a: 5c59 ldrb r1, [r3, r1] +1002413c: f855 a02a ldr.w sl, [r5, sl, lsl #2] +10024140: f854 1021 ldr.w r1, [r4, r1, lsl #2] +10024144: ea88 0a0a eor.w sl, r8, sl +10024148: ea8a 0101 eor.w r1, sl, r1 +1002414c: f840 1c10 str.w r1, [r0, #-16] +10024150: b2d1 uxtb r1, r2 +10024152: 5c59 ldrb r1, [r3, r1] +10024154: f100 0010 add.w r0, r0, #16 +10024158: f85e 8021 ldr.w r8, [lr, r1, lsl #2] +1002415c: ea4f 6112 mov.w r1, r2, lsr #24 +10024160: 5c59 ldrb r1, [r3, r1] +10024162: f856 1021 ldr.w r1, [r6, r1, lsl #2] +10024166: ea88 0101 eor.w r1, r8, r1 +1002416a: f3c2 2807 ubfx r8, r2, #8, #8 +1002416e: f813 8008 ldrb.w r8, [r3, r8] +10024172: f3c2 4207 ubfx r2, r2, #16, #8 +10024176: 5c9a ldrb r2, [r3, r2] +10024178: f855 8028 ldr.w r8, [r5, r8, lsl #2] +1002417c: f854 2022 ldr.w r2, [r4, r2, lsl #2] +10024180: ea81 0808 eor.w r8, r1, r8 +10024184: ea88 0202 eor.w r2, r8, r2 +10024188: f840 2c1c str.w r2, [r0, #-28] +1002418c: e9dc 1206 ldrd r1, r2, [ip, #24] +10024190: fa5f f881 uxtb.w r8, r1 +10024194: ea4f 6a11 mov.w sl, r1, lsr #24 +10024198: f813 8008 ldrb.w r8, [r3, r8] +1002419c: f813 a00a ldrb.w sl, [r3, sl] +100241a0: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +100241a4: f856 a02a ldr.w sl, [r6, sl, lsl #2] +100241a8: f1ac 0c10 sub.w ip, ip, #16 +100241ac: ea88 080a eor.w r8, r8, sl +100241b0: f3c1 2a07 ubfx sl, r1, #8, #8 +100241b4: f813 a00a ldrb.w sl, [r3, sl] +100241b8: f3c1 4107 ubfx r1, r1, #16, #8 +100241bc: 5c59 ldrb r1, [r3, r1] +100241be: f855 a02a ldr.w sl, [r5, sl, lsl #2] +100241c2: f854 1021 ldr.w r1, [r4, r1, lsl #2] +100241c6: ea88 0a0a eor.w sl, r8, sl +100241ca: ea8a 0101 eor.w r1, sl, r1 +100241ce: f840 1c18 str.w r1, [r0, #-24] +100241d2: b2d1 uxtb r1, r2 +100241d4: f813 8001 ldrb.w r8, [r3, r1] +100241d8: ea4f 6112 mov.w r1, r2, lsr #24 +100241dc: 5c59 ldrb r1, [r3, r1] +100241de: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +100241e2: f856 1021 ldr.w r1, [r6, r1, lsl #2] +100241e6: ea88 0101 eor.w r1, r8, r1 +100241ea: f3c2 2807 ubfx r8, r2, #8, #8 +100241ee: f813 8008 ldrb.w r8, [r3, r8] +100241f2: f3c2 4207 ubfx r2, r2, #16, #8 +100241f6: 5c9a ldrb r2, [r3, r2] +100241f8: f855 8028 ldr.w r8, [r5, r8, lsl #2] +100241fc: f854 2022 ldr.w r2, [r4, r2, lsl #2] +10024200: ea81 0808 eor.w r8, r1, r8 +10024204: ea88 0202 eor.w r2, r8, r2 +10024208: f840 2c14 str.w r2, [r0, #-20] +1002420c: f47f af7d bne.w 1002410a +10024210: e9dd 8a01 ldrd r8, sl, [sp, #4] +10024214: f1a8 0802 sub.w r8, r8, #2 +10024218: ea4f 1808 mov.w r8, r8, lsl #4 +1002421c: 9903 ldr r1, [sp, #12] +1002421e: ebaa 0a08 sub.w sl, sl, r8 +10024222: f108 0810 add.w r8, r8, #16 +10024226: 4441 add r1, r8 +10024228: f1aa 0a10 sub.w sl, sl, #16 +1002422c: f8da 3004 ldr.w r3, [sl, #4] +10024230: 604b str r3, [r1, #4] +10024232: f8da 3008 ldr.w r3, [sl, #8] +10024236: 608b str r3, [r1, #8] +10024238: f8da 300c ldr.w r3, [sl, #12] +1002423c: 60cb str r3, [r1, #12] +1002423e: f8da 3000 ldr.w r3, [sl] +10024242: 600b str r3, [r1, #0] +10024244: 4638 mov r0, r7 +10024246: f44f 718c mov.w r1, #280 @ 0x118 +1002424a: f000 fc17 bl 10024a7c +1002424e: 4658 mov r0, fp +10024250: b04b add sp, #300 @ 0x12c +10024252: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10024256: bf00 nop +10024258: 20000630 .word 0x20000630 +1002425c: 200025d8 .word 0x200025d8 +10024260: 20001dd8 .word 0x20001dd8 +10024264: 200021d8 .word 0x200021d8 +10024268: 200019d8 .word 0x200019d8 + +1002426c : +1002426c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10024270: 6844 ldr r4, [r0, #4] +10024272: f100 0308 add.w r3, r0, #8 +10024276: eb03 0e84 add.w lr, r3, r4, lsl #2 +1002427a: 4694 mov ip, r2 +1002427c: f853 3024 ldr.w r3, [r3, r4, lsl #2] +10024280: 6802 ldr r2, [r0, #0] +10024282: 6808 ldr r0, [r1, #0] +10024284: b091 sub sp, #68 @ 0x44 +10024286: 4043 eors r3, r0 +10024288: 688e ldr r6, [r1, #8] +1002428a: 68cd ldr r5, [r1, #12] +1002428c: 9300 str r3, [sp, #0] +1002428e: 684b ldr r3, [r1, #4] +10024290: f8de 1008 ldr.w r1, [lr, #8] +10024294: 1052 asrs r2, r2, #1 +10024296: 404e eors r6, r1 +10024298: f8de 100c ldr.w r1, [lr, #12] +1002429c: f8de 0004 ldr.w r0, [lr, #4] +100242a0: 404d eors r5, r1 +100242a2: 1e51 subs r1, r2, #1 +100242a4: 2900 cmp r1, #0 +100242a6: ea83 0300 eor.w r3, r3, r0 +100242aa: 9101 str r1, [sp, #4] +100242ac: f10e 0010 add.w r0, lr, #16 +100242b0: f340 8190 ble.w 100245d4 +100242b4: e9cd 2005 strd r2, r0, [sp, #20] +100242b8: f8df b334 ldr.w fp, [pc, #820] @ 100245f0 +100242bc: f8df 9334 ldr.w r9, [pc, #820] @ 100245f4 +100242c0: f8df a334 ldr.w sl, [pc, #820] @ 100245f8 +100242c4: f8df 8334 ldr.w r8, [pc, #820] @ 100245fc +100242c8: f10e 0e30 add.w lr, lr, #48 @ 0x30 +100242cc: f8cd c01c str.w ip, [sp, #28] +100242d0: 9800 ldr r0, [sp, #0] +100242d2: f10e 0e20 add.w lr, lr, #32 +100242d6: b2c2 uxtb r2, r0 +100242d8: f85b 7022 ldr.w r7, [fp, r2, lsl #2] +100242dc: 0e2a lsrs r2, r5, #24 +100242de: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100242e2: 4057 eors r7, r2 +100242e4: b2da uxtb r2, r3 +100242e6: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +100242ea: 0e02 lsrs r2, r0, #24 +100242ec: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100242f0: ea81 0c02 eor.w ip, r1, r2 +100242f4: b2f2 uxtb r2, r6 +100242f6: f85b 4022 ldr.w r4, [fp, r2, lsl #2] +100242fa: 0e1a lsrs r2, r3, #24 +100242fc: f859 2022 ldr.w r2, [r9, r2, lsl #2] +10024300: 4054 eors r4, r2 +10024302: b2ea uxtb r2, r5 +10024304: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +10024308: 0e32 lsrs r2, r6, #24 +1002430a: f859 2022 ldr.w r2, [r9, r2, lsl #2] +1002430e: 4051 eors r1, r2 +10024310: f85e 2c40 ldr.w r2, [lr, #-64] +10024314: 4057 eors r7, r2 +10024316: f85e 2c3c ldr.w r2, [lr, #-60] +1002431a: ea8c 0c02 eor.w ip, ip, r2 +1002431e: f85e 2c38 ldr.w r2, [lr, #-56] +10024322: 4054 eors r4, r2 +10024324: f85e 2c34 ldr.w r2, [lr, #-52] +10024328: 4051 eors r1, r2 +1002432a: f3c3 2207 ubfx r2, r3, #8, #8 +1002432e: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +10024332: f3c3 4307 ubfx r3, r3, #16, #8 +10024336: 4057 eors r7, r2 +10024338: f3c6 2207 ubfx r2, r6, #8, #8 +1002433c: f3c6 4607 ubfx r6, r6, #16, #8 +10024340: f85a 0022 ldr.w r0, [sl, r2, lsl #2] +10024344: f858 2026 ldr.w r2, [r8, r6, lsl #2] +10024348: ea8c 0000 eor.w r0, ip, r0 +1002434c: ea87 0c02 eor.w ip, r7, r2 +10024350: f3c5 2207 ubfx r2, r5, #8, #8 +10024354: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +10024358: f3c5 4507 ubfx r5, r5, #16, #8 +1002435c: 4054 eors r4, r2 +1002435e: f858 2025 ldr.w r2, [r8, r5, lsl #2] +10024362: 9d00 ldr r5, [sp, #0] +10024364: 4050 eors r0, r2 +10024366: f3c5 2207 ubfx r2, r5, #8, #8 +1002436a: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1002436e: f858 3023 ldr.w r3, [r8, r3, lsl #2] +10024372: 4051 eors r1, r2 +10024374: 4059 eors r1, r3 +10024376: f3c5 4307 ubfx r3, r5, #16, #8 +1002437a: f858 3023 ldr.w r3, [r8, r3, lsl #2] +1002437e: 405c eors r4, r3 +10024380: fa5f f38c uxtb.w r3, ip +10024384: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +10024388: 0e0b lsrs r3, r1, #24 +1002438a: f859 3023 ldr.w r3, [r9, r3, lsl #2] +1002438e: 4053 eors r3, r2 +10024390: 461f mov r7, r3 +10024392: f3c0 2307 ubfx r3, r0, #8, #8 +10024396: f85a 2023 ldr.w r2, [sl, r3, lsl #2] +1002439a: f3c4 4307 ubfx r3, r4, #16, #8 +1002439e: f858 5023 ldr.w r5, [r8, r3, lsl #2] +100243a2: b2c3 uxtb r3, r0 +100243a4: 9200 str r2, [sp, #0] +100243a6: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +100243aa: ea4f 631c mov.w r3, ip, lsr #24 +100243ae: f859 3023 ldr.w r3, [r9, r3, lsl #2] +100243b2: 9502 str r5, [sp, #8] +100243b4: 405a eors r2, r3 +100243b6: f3c4 2307 ubfx r3, r4, #8, #8 +100243ba: f85a 6023 ldr.w r6, [sl, r3, lsl #2] +100243be: b2e5 uxtb r5, r4 +100243c0: f3c1 4307 ubfx r3, r1, #16, #8 +100243c4: 9603 str r6, [sp, #12] +100243c6: f858 3023 ldr.w r3, [r8, r3, lsl #2] +100243ca: f85b 6025 ldr.w r6, [fp, r5, lsl #2] +100243ce: 0e05 lsrs r5, r0, #24 +100243d0: f859 5025 ldr.w r5, [r9, r5, lsl #2] +100243d4: 0e24 lsrs r4, r4, #24 +100243d6: 406e eors r6, r5 +100243d8: b2cd uxtb r5, r1 +100243da: 9504 str r5, [sp, #16] +100243dc: f85e 5c30 ldr.w r5, [lr, #-48] +100243e0: f3c1 2107 ubfx r1, r1, #8, #8 +100243e4: 407d eors r5, r7 +100243e6: 9f00 ldr r7, [sp, #0] +100243e8: f3c0 4007 ubfx r0, r0, #16, #8 +100243ec: 407d eors r5, r7 +100243ee: 9f02 ldr r7, [sp, #8] +100243f0: 406f eors r7, r5 +100243f2: f85e 5c2c ldr.w r5, [lr, #-44] +100243f6: 9700 str r7, [sp, #0] +100243f8: 406a eors r2, r5 +100243fa: 9d03 ldr r5, [sp, #12] +100243fc: 406a eors r2, r5 +100243fe: 4053 eors r3, r2 +10024400: f85e 5c28 ldr.w r5, [lr, #-40] +10024404: 9a04 ldr r2, [sp, #16] +10024406: 406e eors r6, r5 +10024408: f85b 5022 ldr.w r5, [fp, r2, lsl #2] +1002440c: f859 2024 ldr.w r2, [r9, r4, lsl #2] +10024410: 4055 eors r5, r2 +10024412: f85a 2021 ldr.w r2, [sl, r1, lsl #2] +10024416: f858 1020 ldr.w r1, [r8, r0, lsl #2] +1002441a: 4056 eors r6, r2 +1002441c: f85e 2c24 ldr.w r2, [lr, #-36] +10024420: 4055 eors r5, r2 +10024422: f3cc 2207 ubfx r2, ip, #8, #8 +10024426: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1002442a: 4055 eors r5, r2 +1002442c: f3cc 4207 ubfx r2, ip, #16, #8 +10024430: f858 2022 ldr.w r2, [r8, r2, lsl #2] +10024434: 404d eors r5, r1 +10024436: 4056 eors r6, r2 +10024438: 9a01 ldr r2, [sp, #4] +1002443a: 3a01 subs r2, #1 +1002443c: 9201 str r2, [sp, #4] +1002443e: f47f af47 bne.w 100242d0 +10024442: e9dd 2005 ldrd r2, r0, [sp, #20] +10024446: 46be mov lr, r7 +10024448: eb00 1242 add.w r2, r0, r2, lsl #5 +1002444c: f8dd c01c ldr.w ip, [sp, #28] +10024450: f1a2 0020 sub.w r0, r2, #32 +10024454: fa5f f28e uxtb.w r2, lr +10024458: f85b 7022 ldr.w r7, [fp, r2, lsl #2] +1002445c: 0e2a lsrs r2, r5, #24 +1002445e: f859 2022 ldr.w r2, [r9, r2, lsl #2] +10024462: 4057 eors r7, r2 +10024464: b2ea uxtb r2, r5 +10024466: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +1002446a: 0e32 lsrs r2, r6, #24 +1002446c: f859 2022 ldr.w r2, [r9, r2, lsl #2] +10024470: 4051 eors r1, r2 +10024472: 6802 ldr r2, [r0, #0] +10024474: 4057 eors r7, r2 +10024476: f3c3 2207 ubfx r2, r3, #8, #8 +1002447a: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1002447e: 4057 eors r7, r2 +10024480: b2da uxtb r2, r3 +10024482: f85b 4022 ldr.w r4, [fp, r2, lsl #2] +10024486: 4672 mov r2, lr +10024488: 0e12 lsrs r2, r2, #24 +1002448a: f859 2022 ldr.w r2, [r9, r2, lsl #2] +1002448e: 4054 eors r4, r2 +10024490: 68c2 ldr r2, [r0, #12] +10024492: 9401 str r4, [sp, #4] +10024494: 4051 eors r1, r2 +10024496: f3c6 4207 ubfx r2, r6, #16, #8 +1002449a: f858 2022 ldr.w r2, [r8, r2, lsl #2] +1002449e: 9c00 ldr r4, [sp, #0] +100244a0: 407a eors r2, r7 +100244a2: b2f7 uxtb r7, r6 +100244a4: f3c6 2607 ubfx r6, r6, #8, #8 +100244a8: f85b e027 ldr.w lr, [fp, r7, lsl #2] +100244ac: f85a 7026 ldr.w r7, [sl, r6, lsl #2] +100244b0: 0e1e lsrs r6, r3, #24 +100244b2: f859 6026 ldr.w r6, [r9, r6, lsl #2] +100244b6: f3c3 4307 ubfx r3, r3, #16, #8 +100244ba: ea8e 0606 eor.w r6, lr, r6 +100244be: f3c4 2e07 ubfx lr, r4, #8, #8 +100244c2: f85a e02e ldr.w lr, [sl, lr, lsl #2] +100244c6: f858 3023 ldr.w r3, [r8, r3, lsl #2] +100244ca: ea81 010e eor.w r1, r1, lr +100244ce: 4059 eors r1, r3 +100244d0: f3c4 4907 ubfx r9, r4, #16, #8 +100244d4: 6843 ldr r3, [r0, #4] +100244d6: 9c01 ldr r4, [sp, #4] +100244d8: f858 e029 ldr.w lr, [r8, r9, lsl #2] +100244dc: 405c eors r4, r3 +100244de: 6883 ldr r3, [r0, #8] +100244e0: 407c eors r4, r7 +100244e2: 4073 eors r3, r6 +100244e4: f3c5 4607 ubfx r6, r5, #16, #8 +100244e8: f3c5 2507 ubfx r5, r5, #8, #8 +100244ec: f85a 5025 ldr.w r5, [sl, r5, lsl #2] +100244f0: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100244f4: 406b eors r3, r5 +100244f6: 4d3d ldr r5, [pc, #244] @ (100245ec ) +100244f8: 4074 eors r4, r6 +100244fa: b2d6 uxtb r6, r2 +100244fc: 5daf ldrb r7, [r5, r6] +100244fe: 6906 ldr r6, [r0, #16] +10024500: ea83 030e eor.w r3, r3, lr +10024504: 4077 eors r7, r6 +10024506: 0e0e lsrs r6, r1, #24 +10024508: 5dae ldrb r6, [r5, r6] +1002450a: e9cd 430d strd r4, r3, [sp, #52] @ 0x34 +1002450e: ea87 6706 eor.w r7, r7, r6, lsl #24 +10024512: f3c4 2607 ubfx r6, r4, #8, #8 +10024516: 5dae ldrb r6, [r5, r6] +10024518: 920c str r2, [sp, #48] @ 0x30 +1002451a: ea87 2706 eor.w r7, r7, r6, lsl #8 +1002451e: f3c3 4607 ubfx r6, r3, #16, #8 +10024522: 5dae ldrb r6, [r5, r6] +10024524: 910f str r1, [sp, #60] @ 0x3c +10024526: ea87 4706 eor.w r7, r7, r6, lsl #16 +1002452a: b2e6 uxtb r6, r4 +1002452c: 9708 str r7, [sp, #32] +1002452e: f815 e006 ldrb.w lr, [r5, r6] +10024532: 6946 ldr r6, [r0, #20] +10024534: ea4f 6a12 mov.w sl, r2, lsr #24 +10024538: ea8e 0e06 eor.w lr, lr, r6 +1002453c: f815 600a ldrb.w r6, [r5, sl] +10024540: fa5f f883 uxtb.w r8, r3 +10024544: f815 8008 ldrb.w r8, [r5, r8] +10024548: ea8e 6e06 eor.w lr, lr, r6, lsl #24 +1002454c: 6986 ldr r6, [r0, #24] +1002454e: fa5f f981 uxtb.w r9, r1 +10024552: ea88 0806 eor.w r8, r8, r6 +10024556: 0e26 lsrs r6, r4, #24 +10024558: 5dae ldrb r6, [r5, r6] +1002455a: f3c4 4407 ubfx r4, r4, #16, #8 +1002455e: f815 9009 ldrb.w r9, [r5, r9] +10024562: 69c0 ldr r0, [r0, #28] +10024564: ea88 6806 eor.w r8, r8, r6, lsl #24 +10024568: 5d2e ldrb r6, [r5, r4] +1002456a: 0e1c lsrs r4, r3, #24 +1002456c: 5d2c ldrb r4, [r5, r4] +1002456e: ea89 0000 eor.w r0, r9, r0 +10024572: f3c3 2307 ubfx r3, r3, #8, #8 +10024576: 5ceb ldrb r3, [r5, r3] +10024578: ea80 6004 eor.w r0, r0, r4, lsl #24 +1002457c: f3c1 2407 ubfx r4, r1, #8, #8 +10024580: f3c1 4107 ubfx r1, r1, #16, #8 +10024584: 5c69 ldrb r1, [r5, r1] +10024586: ea8e 2303 eor.w r3, lr, r3, lsl #8 +1002458a: ea83 4101 eor.w r1, r3, r1, lsl #16 +1002458e: f3c2 2307 ubfx r3, r2, #8, #8 +10024592: f3c2 4207 ubfx r2, r2, #16, #8 +10024596: 5d2c ldrb r4, [r5, r4] +10024598: 5ceb ldrb r3, [r5, r3] +1002459a: 5caa ldrb r2, [r5, r2] +1002459c: 9109 str r1, [sp, #36] @ 0x24 +1002459e: f8cc 1004 str.w r1, [ip, #4] +100245a2: 2120 movs r1, #32 +100245a4: ea88 2404 eor.w r4, r8, r4, lsl #8 +100245a8: ea80 2303 eor.w r3, r0, r3, lsl #8 +100245ac: ea83 4306 eor.w r3, r3, r6, lsl #16 +100245b0: ea84 4202 eor.w r2, r4, r2, lsl #16 +100245b4: eb0d 0001 add.w r0, sp, r1 +100245b8: f8cc 7000 str.w r7, [ip] +100245bc: f8cc 2008 str.w r2, [ip, #8] +100245c0: f8cc 300c str.w r3, [ip, #12] +100245c4: 930b str r3, [sp, #44] @ 0x2c +100245c6: 920a str r2, [sp, #40] @ 0x28 +100245c8: f000 fa58 bl 10024a7c +100245cc: 2000 movs r0, #0 +100245ce: b011 add sp, #68 @ 0x44 +100245d0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100245d4: f8df b018 ldr.w fp, [pc, #24] @ 100245f0 +100245d8: f8df 9018 ldr.w r9, [pc, #24] @ 100245f4 +100245dc: f8df a018 ldr.w sl, [pc, #24] @ 100245f8 +100245e0: f8df 8018 ldr.w r8, [pc, #24] @ 100245fc +100245e4: f8dd e000 ldr.w lr, [sp] +100245e8: e734 b.n 10024454 +100245ea: bf00 nop +100245ec: 20000630 .word 0x20000630 +100245f0: 200008d8 .word 0x200008d8 +100245f4: 200014d8 .word 0x200014d8 +100245f8: 20000cd8 .word 0x20000cd8 +100245fc: 200010d8 .word 0x200010d8 + +10024600 : +10024600: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10024604: 4694 mov ip, r2 +10024606: 6842 ldr r2, [r0, #4] +10024608: f100 0308 add.w r3, r0, #8 +1002460c: eb03 0582 add.w r5, r3, r2, lsl #2 +10024610: f8d1 9000 ldr.w r9, [r1] +10024614: f853 3022 ldr.w r3, [r3, r2, lsl #2] +10024618: 686a ldr r2, [r5, #4] +1002461a: ea89 0903 eor.w r9, r9, r3 +1002461e: 684b ldr r3, [r1, #4] +10024620: 68ce ldr r6, [r1, #12] +10024622: 4053 eors r3, r2 +10024624: 688a ldr r2, [r1, #8] +10024626: 68a9 ldr r1, [r5, #8] +10024628: 6807 ldr r7, [r0, #0] +1002462a: 404a eors r2, r1 +1002462c: 68e9 ldr r1, [r5, #12] +1002462e: 107f asrs r7, r7, #1 +10024630: 404e eors r6, r1 +10024632: 1e79 subs r1, r7, #1 +10024634: b093 sub sp, #76 @ 0x4c +10024636: 2900 cmp r1, #0 +10024638: 9100 str r1, [sp, #0] +1002463a: f105 0410 add.w r4, r5, #16 +1002463e: f340 8196 ble.w 1002496e +10024642: 49cf ldr r1, [pc, #828] @ (10024980 ) +10024644: e9cd 7407 strd r7, r4, [sp, #28] +10024648: 468e mov lr, r1 +1002464a: f8df b33c ldr.w fp, [pc, #828] @ 10024988 +1002464e: f8df 833c ldr.w r8, [pc, #828] @ 1002498c +10024652: f8df a33c ldr.w sl, [pc, #828] @ 10024990 +10024656: 3530 adds r5, #48 @ 0x30 +10024658: 9106 str r1, [sp, #24] +1002465a: f8cd c024 str.w ip, [sp, #36] @ 0x24 +1002465e: fa5f f189 uxtb.w r1, r9 +10024662: f85b 7021 ldr.w r7, [fp, r1, lsl #2] +10024666: 0e19 lsrs r1, r3, #24 +10024668: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +1002466c: 3520 adds r5, #32 +1002466e: 404f eors r7, r1 +10024670: b2d9 uxtb r1, r3 +10024672: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +10024676: 0e11 lsrs r1, r2, #24 +10024678: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +1002467c: ea80 0c01 eor.w ip, r0, r1 +10024680: b2d1 uxtb r1, r2 +10024682: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +10024686: 0e31 lsrs r1, r6, #24 +10024688: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +1002468c: 4048 eors r0, r1 +1002468e: b2f1 uxtb r1, r6 +10024690: f85b 4021 ldr.w r4, [fp, r1, lsl #2] +10024694: ea4f 6119 mov.w r1, r9, lsr #24 +10024698: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +1002469c: 404c eors r4, r1 +1002469e: f855 1c40 ldr.w r1, [r5, #-64] +100246a2: 404f eors r7, r1 +100246a4: f855 1c3c ldr.w r1, [r5, #-60] +100246a8: ea8c 0c01 eor.w ip, ip, r1 +100246ac: f855 1c38 ldr.w r1, [r5, #-56] +100246b0: 4048 eors r0, r1 +100246b2: f855 1c34 ldr.w r1, [r5, #-52] +100246b6: 404c eors r4, r1 +100246b8: f3c6 2107 ubfx r1, r6, #8, #8 +100246bc: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100246c0: f3c6 4607 ubfx r6, r6, #16, #8 +100246c4: 404f eors r7, r1 +100246c6: f85a 1026 ldr.w r1, [sl, r6, lsl #2] +100246ca: f3c9 2607 ubfx r6, r9, #8, #8 +100246ce: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100246d2: f3c9 4907 ubfx r9, r9, #16, #8 +100246d6: ea8c 0c06 eor.w ip, ip, r6 +100246da: f3c3 2607 ubfx r6, r3, #8, #8 +100246de: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100246e2: ea8c 0c01 eor.w ip, ip, r1 +100246e6: f85a 1029 ldr.w r1, [sl, r9, lsl #2] +100246ea: 4070 eors r0, r6 +100246ec: 4048 eors r0, r1 +100246ee: f3c2 2107 ubfx r1, r2, #8, #8 +100246f2: f3c2 4207 ubfx r2, r2, #16, #8 +100246f6: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100246fa: f85a 6022 ldr.w r6, [sl, r2, lsl #2] +100246fe: f3c3 4307 ubfx r3, r3, #16, #8 +10024702: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +10024706: 407e eors r6, r7 +10024708: 404c eors r4, r1 +1002470a: 405c eors r4, r3 +1002470c: b2f3 uxtb r3, r6 +1002470e: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +10024712: ea4f 631c mov.w r3, ip, lsr #24 +10024716: f85e 3023 ldr.w r3, [lr, r3, lsl #2] +1002471a: ea82 0903 eor.w r9, r2, r3 +1002471e: f3c4 2307 ubfx r3, r4, #8, #8 +10024722: f858 3023 ldr.w r3, [r8, r3, lsl #2] +10024726: 9301 str r3, [sp, #4] +10024728: f3c0 4307 ubfx r3, r0, #16, #8 +1002472c: f85a 2023 ldr.w r2, [sl, r3, lsl #2] +10024730: fa5f f38c uxtb.w r3, ip +10024734: f85b 1023 ldr.w r1, [fp, r3, lsl #2] +10024738: 0e03 lsrs r3, r0, #24 +1002473a: f85e 3023 ldr.w r3, [lr, r3, lsl #2] +1002473e: 9202 str r2, [sp, #8] +10024740: 4059 eors r1, r3 +10024742: f3c6 2307 ubfx r3, r6, #8, #8 +10024746: f858 7023 ldr.w r7, [r8, r3, lsl #2] +1002474a: f3c4 4307 ubfx r3, r4, #16, #8 +1002474e: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +10024752: 9703 str r7, [sp, #12] +10024754: b2c2 uxtb r2, r0 +10024756: 0e27 lsrs r7, r4, #24 +10024758: 9304 str r3, [sp, #16] +1002475a: f85b 2022 ldr.w r2, [fp, r2, lsl #2] +1002475e: f85e 7027 ldr.w r7, [lr, r7, lsl #2] +10024762: 9b01 ldr r3, [sp, #4] +10024764: 407a eors r2, r7 +10024766: 0e37 lsrs r7, r6, #24 +10024768: 9705 str r7, [sp, #20] +1002476a: f855 7c30 ldr.w r7, [r5, #-48] +1002476e: b2e4 uxtb r4, r4 +10024770: ea89 0707 eor.w r7, r9, r7 +10024774: 405f eors r7, r3 +10024776: 9b02 ldr r3, [sp, #8] +10024778: f85b 4024 ldr.w r4, [fp, r4, lsl #2] +1002477c: ea87 0903 eor.w r9, r7, r3 +10024780: f855 7c2c ldr.w r7, [r5, #-44] +10024784: 9b04 ldr r3, [sp, #16] +10024786: 4079 eors r1, r7 +10024788: 9f03 ldr r7, [sp, #12] +1002478a: f3c6 4607 ubfx r6, r6, #16, #8 +1002478e: 4079 eors r1, r7 +10024790: f855 7c28 ldr.w r7, [r5, #-40] +10024794: 404b eors r3, r1 +10024796: 407a eors r2, r7 +10024798: 9f05 ldr r7, [sp, #20] +1002479a: f3c0 2007 ubfx r0, r0, #8, #8 +1002479e: f85e 1027 ldr.w r1, [lr, r7, lsl #2] +100247a2: f85a 7026 ldr.w r7, [sl, r6, lsl #2] +100247a6: 404c eors r4, r1 +100247a8: f855 1c24 ldr.w r1, [r5, #-36] +100247ac: f858 0020 ldr.w r0, [r8, r0, lsl #2] +100247b0: ea84 0601 eor.w r6, r4, r1 +100247b4: f3cc 2107 ubfx r1, ip, #8, #8 +100247b8: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100247bc: 4046 eors r6, r0 +100247be: 404a eors r2, r1 +100247c0: f3cc 4107 ubfx r1, ip, #16, #8 +100247c4: f85a 1021 ldr.w r1, [sl, r1, lsl #2] +100247c8: 407a eors r2, r7 +100247ca: 404e eors r6, r1 +100247cc: 9900 ldr r1, [sp, #0] +100247ce: 3901 subs r1, #1 +100247d0: 9100 str r1, [sp, #0] +100247d2: f47f af44 bne.w 1002465e +100247d6: e9dd 7407 ldrd r7, r4, [sp, #28] +100247da: f8dd c024 ldr.w ip, [sp, #36] @ 0x24 +100247de: eb04 1747 add.w r7, r4, r7, lsl #5 +100247e2: f1a7 0420 sub.w r4, r7, #32 +100247e6: 9d06 ldr r5, [sp, #24] +100247e8: fa5f f189 uxtb.w r1, r9 +100247ec: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +100247f0: 0e19 lsrs r1, r3, #24 +100247f2: f855 1021 ldr.w r1, [r5, r1, lsl #2] +100247f6: 4048 eors r0, r1 +100247f8: b2d9 uxtb r1, r3 +100247fa: f85b 7021 ldr.w r7, [fp, r1, lsl #2] +100247fe: 0e11 lsrs r1, r2, #24 +10024800: f855 1021 ldr.w r1, [r5, r1, lsl #2] +10024804: 404f eors r7, r1 +10024806: 6821 ldr r1, [r4, #0] +10024808: 4048 eors r0, r1 +1002480a: f3c6 2107 ubfx r1, r6, #8, #8 +1002480e: f858 1021 ldr.w r1, [r8, r1, lsl #2] +10024812: 4048 eors r0, r1 +10024814: b2f1 uxtb r1, r6 +10024816: f85b e021 ldr.w lr, [fp, r1, lsl #2] +1002481a: ea4f 6119 mov.w r1, r9, lsr #24 +1002481e: f855 1021 ldr.w r1, [r5, r1, lsl #2] +10024822: ea8e 0101 eor.w r1, lr, r1 +10024826: 9100 str r1, [sp, #0] +10024828: 6861 ldr r1, [r4, #4] +1002482a: fa5f fe82 uxtb.w lr, r2 +1002482e: 404f eors r7, r1 +10024830: f3c2 4107 ubfx r1, r2, #16, #8 +10024834: f85a 1021 ldr.w r1, [sl, r1, lsl #2] +10024838: f3c2 2207 ubfx r2, r2, #8, #8 +1002483c: 4048 eors r0, r1 +1002483e: f3c9 2107 ubfx r1, r9, #8, #8 +10024842: f858 1021 ldr.w r1, [r8, r1, lsl #2] +10024846: f3c9 4907 ubfx r9, r9, #16, #8 +1002484a: 404f eors r7, r1 +1002484c: f85a 1029 ldr.w r1, [sl, r9, lsl #2] +10024850: f858 9022 ldr.w r9, [r8, r2, lsl #2] +10024854: 0e32 lsrs r2, r6, #24 +10024856: f855 2022 ldr.w r2, [r5, r2, lsl #2] +1002485a: f85b e02e ldr.w lr, [fp, lr, lsl #2] +1002485e: f3c6 4607 ubfx r6, r6, #16, #8 +10024862: f85a 6026 ldr.w r6, [sl, r6, lsl #2] +10024866: 9d00 ldr r5, [sp, #0] +10024868: ea8e 0e02 eor.w lr, lr, r2 +1002486c: 68e2 ldr r2, [r4, #12] +1002486e: 407e eors r6, r7 +10024870: 4055 eors r5, r2 +10024872: f3c3 2707 ubfx r7, r3, #8, #8 +10024876: 68a2 ldr r2, [r4, #8] +10024878: f3c3 4307 ubfx r3, r3, #16, #8 +1002487c: f858 7027 ldr.w r7, [r8, r7, lsl #2] +10024880: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +10024884: ea85 0509 eor.w r5, r5, r9 +10024888: ea8e 0202 eor.w r2, lr, r2 +1002488c: ea85 0803 eor.w r8, r5, r3 +10024890: 407a eors r2, r7 +10024892: 4b3c ldr r3, [pc, #240] @ (10024984 ) +10024894: 404a eors r2, r1 +10024896: b2c1 uxtb r1, r0 +10024898: 6925 ldr r5, [r4, #16] +1002489a: 5c59 ldrb r1, [r3, r1] +1002489c: e9cd 2810 strd r2, r8, [sp, #64] @ 0x40 +100248a0: 4069 eors r1, r5 +100248a2: 0e35 lsrs r5, r6, #24 +100248a4: 5d5d ldrb r5, [r3, r5] +100248a6: 900e str r0, [sp, #56] @ 0x38 +100248a8: ea81 6105 eor.w r1, r1, r5, lsl #24 +100248ac: f3c8 2507 ubfx r5, r8, #8, #8 +100248b0: 5d5d ldrb r5, [r3, r5] +100248b2: 960f str r6, [sp, #60] @ 0x3c +100248b4: ea81 2105 eor.w r1, r1, r5, lsl #8 +100248b8: f3c2 4507 ubfx r5, r2, #16, #8 +100248bc: 5d5d ldrb r5, [r3, r5] +100248be: ea4f 6a12 mov.w sl, r2, lsr #24 +100248c2: ea81 4105 eor.w r1, r1, r5, lsl #16 +100248c6: b2f5 uxtb r5, r6 +100248c8: 910a str r1, [sp, #40] @ 0x28 +100248ca: 6967 ldr r7, [r4, #20] +100248cc: 5d5d ldrb r5, [r3, r5] +100248ce: fa5f f982 uxtb.w r9, r2 +100248d2: 407d eors r5, r7 +100248d4: f813 700a ldrb.w r7, [r3, sl] +100248d8: fa5f fe88 uxtb.w lr, r8 +100248dc: f3c2 2207 ubfx r2, r2, #8, #8 +100248e0: ea85 6507 eor.w r5, r5, r7, lsl #24 +100248e4: f813 7009 ldrb.w r7, [r3, r9] +100248e8: f813 900e ldrb.w r9, [r3, lr] +100248ec: f813 e002 ldrb.w lr, [r3, r2] +100248f0: 69a2 ldr r2, [r4, #24] +100248f2: 69e4 ldr r4, [r4, #28] +100248f4: 407a eors r2, r7 +100248f6: ea4f 6718 mov.w r7, r8, lsr #24 +100248fa: 5ddf ldrb r7, [r3, r7] +100248fc: ea89 0404 eor.w r4, r9, r4 +10024900: ea82 6707 eor.w r7, r2, r7, lsl #24 +10024904: f3c8 4207 ubfx r2, r8, #16, #8 +10024908: ea4f 6810 mov.w r8, r0, lsr #24 +1002490c: f813 8008 ldrb.w r8, [r3, r8] +10024910: 5c9a ldrb r2, [r3, r2] +10024912: ea84 6408 eor.w r4, r4, r8, lsl #24 +10024916: ea84 240e eor.w r4, r4, lr, lsl #8 +1002491a: f3c0 2e07 ubfx lr, r0, #8, #8 +1002491e: f813 e00e ldrb.w lr, [r3, lr] +10024922: f3c0 4007 ubfx r0, r0, #16, #8 +10024926: ea85 250e eor.w r5, r5, lr, lsl #8 +1002492a: ea85 4502 eor.w r5, r5, r2, lsl #16 +1002492e: f3c6 2207 ubfx r2, r6, #8, #8 +10024932: 5c9a ldrb r2, [r3, r2] +10024934: f3c6 4607 ubfx r6, r6, #16, #8 +10024938: 5c18 ldrb r0, [r3, r0] +1002493a: 5d9b ldrb r3, [r3, r6] +1002493c: ea87 2202 eor.w r2, r7, r2, lsl #8 +10024940: ea82 4200 eor.w r2, r2, r0, lsl #16 +10024944: ea84 4303 eor.w r3, r4, r3, lsl #16 +10024948: f8cc 1000 str.w r1, [ip] +1002494c: a80a add r0, sp, #40 @ 0x28 +1002494e: 2120 movs r1, #32 +10024950: f8cc 5004 str.w r5, [ip, #4] +10024954: f8cc 2008 str.w r2, [ip, #8] +10024958: f8cc 300c str.w r3, [ip, #12] +1002495c: 950b str r5, [sp, #44] @ 0x2c +1002495e: 920c str r2, [sp, #48] @ 0x30 +10024960: 930d str r3, [sp, #52] @ 0x34 +10024962: f000 f88b bl 10024a7c +10024966: 2000 movs r0, #0 +10024968: b013 add sp, #76 @ 0x4c +1002496a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1002496e: 4904 ldr r1, [pc, #16] @ (10024980 ) +10024970: f8df b014 ldr.w fp, [pc, #20] @ 10024988 +10024974: f8df 8014 ldr.w r8, [pc, #20] @ 1002498c +10024978: f8df a014 ldr.w sl, [pc, #20] @ 10024990 +1002497c: 9106 str r1, [sp, #24] +1002497e: e732 b.n 100247e6 +10024980: 200025d8 .word 0x200025d8 +10024984: 200018d8 .word 0x200018d8 +10024988: 200019d8 .word 0x200019d8 +1002498c: 20001dd8 .word 0x20001dd8 +10024990: 200021d8 .word 0x200021d8 + +10024994 : +10024994: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10024998: 2901 cmp r1, #1 +1002499a: b085 sub sp, #20 +1002499c: 9e0c ldr r6, [sp, #48] @ 0x30 +1002499e: d867 bhi.n 10024a70 +100249a0: b382 cbz r2, 10024a04 +100249a2: 0714 lsls r4, r2, #28 +100249a4: d167 bne.n 10024a76 +100249a6: 4607 mov r7, r0 +100249a8: 461d mov r5, r3 +100249aa: bb79 cbnz r1, 10024a0c +100249ac: 9c0d ldr r4, [sp, #52] @ 0x34 +100249ae: eb04 0802 add.w r8, r4, r2 +100249b2: 46ec mov ip, sp +100249b4: 6830 ldr r0, [r6, #0] +100249b6: 6871 ldr r1, [r6, #4] +100249b8: 68b2 ldr r2, [r6, #8] +100249ba: 68f3 ldr r3, [r6, #12] +100249bc: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +100249c0: 4622 mov r2, r4 +100249c2: 4631 mov r1, r6 +100249c4: 4638 mov r0, r7 +100249c6: f7ff fe1b bl 10024600 +100249ca: 46ec mov ip, sp +100249cc: 6821 ldr r1, [r4, #0] +100249ce: 682a ldr r2, [r5, #0] +100249d0: 6863 ldr r3, [r4, #4] +100249d2: 404a eors r2, r1 +100249d4: 6022 str r2, [r4, #0] +100249d6: 6869 ldr r1, [r5, #4] +100249d8: 68a2 ldr r2, [r4, #8] +100249da: 404b eors r3, r1 +100249dc: 6063 str r3, [r4, #4] +100249de: 68a9 ldr r1, [r5, #8] +100249e0: 68e3 ldr r3, [r4, #12] +100249e2: 404a eors r2, r1 +100249e4: 60a2 str r2, [r4, #8] +100249e6: 68ea ldr r2, [r5, #12] +100249e8: 3410 adds r4, #16 +100249ea: 4053 eors r3, r2 +100249ec: 4544 cmp r4, r8 +100249ee: f844 3c04 str.w r3, [r4, #-4] +100249f2: f106 0610 add.w r6, r6, #16 +100249f6: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} +100249fa: 6028 str r0, [r5, #0] +100249fc: 6069 str r1, [r5, #4] +100249fe: 60aa str r2, [r5, #8] +10024a00: 60eb str r3, [r5, #12] +10024a02: d1d6 bne.n 100249b2 +10024a04: 2000 movs r0, #0 +10024a06: b005 add sp, #20 +10024a08: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10024a0c: 4691 mov r9, r2 +10024a0e: 461c mov r4, r3 +10024a10: 9b0d ldr r3, [sp, #52] @ 0x34 +10024a12: 4416 add r6, r2 +10024a14: eb03 0802 add.w r8, r3, r2 +10024a18: 4623 mov r3, r4 +10024a1a: eba6 0209 sub.w r2, r6, r9 +10024a1e: f8d3 c000 ldr.w ip, [r3] +10024a22: 6811 ldr r1, [r2, #0] +10024a24: eba8 0409 sub.w r4, r8, r9 +10024a28: ea81 010c eor.w r1, r1, ip +10024a2c: 6021 str r1, [r4, #0] +10024a2e: f8d3 c004 ldr.w ip, [r3, #4] +10024a32: 6851 ldr r1, [r2, #4] +10024a34: 4638 mov r0, r7 +10024a36: ea81 010c eor.w r1, r1, ip +10024a3a: 6061 str r1, [r4, #4] +10024a3c: 6891 ldr r1, [r2, #8] +10024a3e: f8d3 c008 ldr.w ip, [r3, #8] +10024a42: ea81 010c eor.w r1, r1, ip +10024a46: 60a1 str r1, [r4, #8] +10024a48: 68d1 ldr r1, [r2, #12] +10024a4a: 68db ldr r3, [r3, #12] +10024a4c: 4622 mov r2, r4 +10024a4e: 404b eors r3, r1 +10024a50: 60e3 str r3, [r4, #12] +10024a52: 4621 mov r1, r4 +10024a54: f7ff fc0a bl 1002426c +10024a58: f1b9 0910 subs.w r9, r9, #16 +10024a5c: d1dc bne.n 10024a18 +10024a5e: 6820 ldr r0, [r4, #0] +10024a60: 6861 ldr r1, [r4, #4] +10024a62: 68a2 ldr r2, [r4, #8] +10024a64: 68e3 ldr r3, [r4, #12] +10024a66: 6028 str r0, [r5, #0] +10024a68: 6069 str r1, [r5, #4] +10024a6a: 60aa str r2, [r5, #8] +10024a6c: 60eb str r3, [r5, #12] +10024a6e: e7c9 b.n 10024a04 +10024a70: f06f 0020 mvn.w r0, #32 +10024a74: e7c7 b.n 10024a06 +10024a76: f06f 0021 mvn.w r0, #33 @ 0x21 +10024a7a: e7c4 b.n 10024a06 + +10024a7c : +10024a7c: b139 cbz r1, 10024a8e +10024a7e: 4b04 ldr r3, [pc, #16] @ (10024a90 ) +10024a80: 460a mov r2, r1 +10024a82: b510 push {r4, lr} +10024a84: 2100 movs r1, #0 +10024a86: 681b ldr r3, [r3, #0] +10024a88: 4604 mov r4, r0 +10024a8a: 4798 blx r3 +10024a8c: bd10 pop {r4, pc} +10024a8e: 4770 bx lr +10024a90: 10024f38 .word 0x10024f38 + +10024a94 <_retrieve_unique_id_on_boot>: +10024a94: b500 push {lr} +10024a96: f245 3047 movw r0, #21319 @ 0x5347 +10024a9a: b08b sub sp, #44 @ 0x2c +10024a9c: f7fc fd7a bl 10021594 +10024aa0: 2201 movs r2, #1 +10024aa2: 4603 mov r3, r0 +10024aa4: 2109 movs r1, #9 +10024aa6: a801 add r0, sp, #4 +10024aa8: 4798 blx r3 +10024aaa: e9dd 3203 ldrd r3, r2, [sp, #12] +10024aae: 4904 ldr r1, [pc, #16] @ (10024ac0 <_retrieve_unique_id_on_boot+0x2c>) +10024ab0: ba12 rev r2, r2 +10024ab2: ba1b rev r3, r3 +10024ab4: e9c1 2300 strd r2, r3, [r1] +10024ab8: b00b add sp, #44 @ 0x2c +10024aba: f85d fb04 ldr.w pc, [sp], #4 +10024abe: bf00 nop +10024ac0: 20002a78 .word 0x20002a78 + +10024ac4 : +10024ac4: 0783 lsls r3, r0, #30 +10024ac6: b530 push {r4, r5, lr} +10024ac8: d046 beq.n 10024b58 +10024aca: 1884 adds r4, r0, r2 +10024acc: 4684 mov ip, r0 +10024ace: e004 b.n 10024ada +10024ad0: f803 1b01 strb.w r1, [r3], #1 +10024ad4: 079d lsls r5, r3, #30 +10024ad6: d004 beq.n 10024ae2 +10024ad8: 469c mov ip, r3 +10024ada: 45a4 cmp ip, r4 +10024adc: 4663 mov r3, ip +10024ade: d1f7 bne.n 10024ad0 +10024ae0: bd30 pop {r4, r5, pc} +10024ae2: 3a01 subs r2, #1 +10024ae4: 4402 add r2, r0 +10024ae6: eba2 020c sub.w r2, r2, ip +10024aea: 2a03 cmp r2, #3 +10024aec: d929 bls.n 10024b42 +10024aee: b2cc uxtb r4, r1 +10024af0: 2a0f cmp r2, #15 +10024af2: eb04 2404 add.w r4, r4, r4, lsl #8 +10024af6: eb04 4404 add.w r4, r4, r4, lsl #16 +10024afa: d92f bls.n 10024b5c +10024afc: f1a2 0c10 sub.w ip, r2, #16 +10024b00: f103 0510 add.w r5, r3, #16 +10024b04: f02c 0c0f bic.w ip, ip, #15 +10024b08: 44ac add ip, r5 +10024b0a: e9c3 4400 strd r4, r4, [r3] +10024b0e: e9c3 4402 strd r4, r4, [r3, #8] +10024b12: 3310 adds r3, #16 +10024b14: 4563 cmp r3, ip +10024b16: d1f8 bne.n 10024b0a +10024b18: f012 0f0c tst.w r2, #12 +10024b1c: f002 0e0f and.w lr, r2, #15 +10024b20: d018 beq.n 10024b54 +10024b22: f02e 0c03 bic.w ip, lr, #3 +10024b26: f1ae 0504 sub.w r5, lr, #4 +10024b2a: 461a mov r2, r3 +10024b2c: 449c add ip, r3 +10024b2e: f842 4b04 str.w r4, [r2], #4 +10024b32: 4562 cmp r2, ip +10024b34: d1fb bne.n 10024b2e +10024b36: f025 0403 bic.w r4, r5, #3 +10024b3a: 3304 adds r3, #4 +10024b3c: f00e 0203 and.w r2, lr, #3 +10024b40: 4423 add r3, r4 +10024b42: 2a00 cmp r2, #0 +10024b44: d0cc beq.n 10024ae0 +10024b46: b2c9 uxtb r1, r1 +10024b48: 441a add r2, r3 +10024b4a: f803 1b01 strb.w r1, [r3], #1 +10024b4e: 4293 cmp r3, r2 +10024b50: d1fb bne.n 10024b4a +10024b52: bd30 pop {r4, r5, pc} +10024b54: 4672 mov r2, lr +10024b56: e7f4 b.n 10024b42 +10024b58: 4603 mov r3, r0 +10024b5a: e7c6 b.n 10024aea +10024b5c: 4696 mov lr, r2 +10024b5e: e7e0 b.n 10024b22 + +10024b60 : +10024b60: 4684 mov ip, r0 +10024b62: ea41 0300 orr.w r3, r1, r0 +10024b66: f013 0303 ands.w r3, r3, #3 +10024b6a: d149 bne.n 10024c00 +10024b6c: 3a40 subs r2, #64 @ 0x40 +10024b6e: d323 bcc.n 10024bb8 +10024b70: 680b ldr r3, [r1, #0] +10024b72: 6003 str r3, [r0, #0] +10024b74: 684b ldr r3, [r1, #4] +10024b76: 6043 str r3, [r0, #4] +10024b78: 688b ldr r3, [r1, #8] +10024b7a: 6083 str r3, [r0, #8] +10024b7c: 68cb ldr r3, [r1, #12] +10024b7e: 60c3 str r3, [r0, #12] +10024b80: 690b ldr r3, [r1, #16] +10024b82: 6103 str r3, [r0, #16] +10024b84: 694b ldr r3, [r1, #20] +10024b86: 6143 str r3, [r0, #20] +10024b88: 698b ldr r3, [r1, #24] +10024b8a: 6183 str r3, [r0, #24] +10024b8c: 69cb ldr r3, [r1, #28] +10024b8e: 61c3 str r3, [r0, #28] +10024b90: 6a0b ldr r3, [r1, #32] +10024b92: 6203 str r3, [r0, #32] +10024b94: 6a4b ldr r3, [r1, #36] @ 0x24 +10024b96: 6243 str r3, [r0, #36] @ 0x24 +10024b98: 6a8b ldr r3, [r1, #40] @ 0x28 +10024b9a: 6283 str r3, [r0, #40] @ 0x28 +10024b9c: 6acb ldr r3, [r1, #44] @ 0x2c +10024b9e: 62c3 str r3, [r0, #44] @ 0x2c +10024ba0: 6b0b ldr r3, [r1, #48] @ 0x30 +10024ba2: 6303 str r3, [r0, #48] @ 0x30 +10024ba4: 6b4b ldr r3, [r1, #52] @ 0x34 +10024ba6: 6343 str r3, [r0, #52] @ 0x34 +10024ba8: 6b8b ldr r3, [r1, #56] @ 0x38 +10024baa: 6383 str r3, [r0, #56] @ 0x38 +10024bac: 6bcb ldr r3, [r1, #60] @ 0x3c +10024bae: 63c3 str r3, [r0, #60] @ 0x3c +10024bb0: 3040 adds r0, #64 @ 0x40 +10024bb2: 3140 adds r1, #64 @ 0x40 +10024bb4: 3a40 subs r2, #64 @ 0x40 +10024bb6: d2db bcs.n 10024b70 +10024bb8: 3230 adds r2, #48 @ 0x30 +10024bba: d30b bcc.n 10024bd4 +10024bbc: 680b ldr r3, [r1, #0] +10024bbe: 6003 str r3, [r0, #0] +10024bc0: 684b ldr r3, [r1, #4] +10024bc2: 6043 str r3, [r0, #4] +10024bc4: 688b ldr r3, [r1, #8] +10024bc6: 6083 str r3, [r0, #8] +10024bc8: 68cb ldr r3, [r1, #12] +10024bca: 60c3 str r3, [r0, #12] +10024bcc: 3010 adds r0, #16 +10024bce: 3110 adds r1, #16 +10024bd0: 3a10 subs r2, #16 +10024bd2: d2f3 bcs.n 10024bbc +10024bd4: 320c adds r2, #12 +10024bd6: d305 bcc.n 10024be4 +10024bd8: f851 3b04 ldr.w r3, [r1], #4 +10024bdc: f840 3b04 str.w r3, [r0], #4 +10024be0: 3a04 subs r2, #4 +10024be2: d2f9 bcs.n 10024bd8 +10024be4: 3204 adds r2, #4 +10024be6: d008 beq.n 10024bfa +10024be8: 07d2 lsls r2, r2, #31 +10024bea: bf1c itt ne +10024bec: f811 3b01 ldrbne.w r3, [r1], #1 +10024bf0: f800 3b01 strbne.w r3, [r0], #1 +10024bf4: d301 bcc.n 10024bfa +10024bf6: 880b ldrh r3, [r1, #0] +10024bf8: 8003 strh r3, [r0, #0] +10024bfa: 4660 mov r0, ip +10024bfc: 4770 bx lr +10024bfe: bf00 nop +10024c00: 2a08 cmp r2, #8 +10024c02: d313 bcc.n 10024c2c +10024c04: 078b lsls r3, r1, #30 +10024c06: d0b1 beq.n 10024b6c +10024c08: f010 0303 ands.w r3, r0, #3 +10024c0c: d0ae beq.n 10024b6c +10024c0e: f1c3 0304 rsb r3, r3, #4 +10024c12: 1ad2 subs r2, r2, r3 +10024c14: 07db lsls r3, r3, #31 +10024c16: bf1c itt ne +10024c18: f811 3b01 ldrbne.w r3, [r1], #1 +10024c1c: f800 3b01 strbne.w r3, [r0], #1 +10024c20: d3a4 bcc.n 10024b6c +10024c22: f831 3b02 ldrh.w r3, [r1], #2 +10024c26: f820 3b02 strh.w r3, [r0], #2 +10024c2a: e79f b.n 10024b6c +10024c2c: 3a04 subs r2, #4 +10024c2e: d3d9 bcc.n 10024be4 +10024c30: 3a01 subs r2, #1 +10024c32: f811 3b01 ldrb.w r3, [r1], #1 +10024c36: f800 3b01 strb.w r3, [r0], #1 +10024c3a: d2f9 bcs.n 10024c30 +10024c3c: 780b ldrb r3, [r1, #0] +10024c3e: 7003 strb r3, [r0, #0] +10024c40: 784b ldrb r3, [r1, #1] +10024c42: 7043 strb r3, [r0, #1] +10024c44: 788b ldrb r3, [r1, #2] +10024c46: 7083 strb r3, [r0, #2] +10024c48: 4660 mov r0, ip +10024c4a: 4770 bx lr + +10024c4c : +10024c4c: f020 0103 bic.w r1, r0, #3 +10024c50: f010 0003 ands.w r0, r0, #3 +10024c54: f1c0 0000 rsb r0, r0, #0 +10024c58: f851 3b04 ldr.w r3, [r1], #4 +10024c5c: f100 0c04 add.w ip, r0, #4 +10024c60: ea4f 0ccc mov.w ip, ip, lsl #3 +10024c64: f06f 0200 mvn.w r2, #0 +10024c68: bf1c itt ne +10024c6a: fa22 f20c lsrne.w r2, r2, ip +10024c6e: 4313 orrne r3, r2 +10024c70: f04f 0c01 mov.w ip, #1 +10024c74: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10024c78: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10024c7c: eba3 020c sub.w r2, r3, ip +10024c80: ea22 0203 bic.w r2, r2, r3 +10024c84: ea12 12cc ands.w r2, r2, ip, lsl #7 +10024c88: bf04 itt eq +10024c8a: f851 3b04 ldreq.w r3, [r1], #4 +10024c8e: 3004 addeq r0, #4 +10024c90: d0f4 beq.n 10024c7c +10024c92: f1c2 0100 rsb r1, r2, #0 +10024c96: ea02 0201 and.w r2, r2, r1 +10024c9a: fab2 f282 clz r2, r2 +10024c9e: f1c2 021f rsb r2, r2, #31 +10024ca2: eb00 00d2 add.w r0, r0, r2, lsr #3 +10024ca6: 4770 bx lr + +10024ca8 <_fini>: +10024ca8: b5f8 push {r3, r4, r5, r6, r7, lr} +10024caa: bf00 nop +10024cac: 0000 movs r0, r0 + ... + +10024cb0 <____aeabi_uldivmod_veneer>: +10024cb0: f85f f000 ldr.w pc, [pc] @ 10024cb4 <____aeabi_uldivmod_veneer+0x4> +10024cb4: 20000221 .word 0x20000221 + +10024cb8 <__mutex_exit_veneer>: +10024cb8: f85f f000 ldr.w pc, [pc] @ 10024cbc <__mutex_exit_veneer+0x4> +10024cbc: 200001e5 .word 0x200001e5 + +10024cc0 <__mutex_try_enter_block_until_veneer>: +10024cc0: f85f f000 ldr.w pc, [pc] @ 10024cc4 <__mutex_try_enter_block_until_veneer+0x4> +10024cc4: 2000017d .word 0x2000017d + +10024cc8 <__pre_init_runtime_init_bootrom_reset>: +10024cc8: 100216c9 .... + +10024ccc <__pre_init_runtime_init_early_resets>: +10024ccc: 1002163d =... + +10024cd0 <__pre_init_runtime_init_usb_power_down>: +10024cd0: 10021671 q... + +10024cd4 <__pre_init_runtime_init_clocks>: +10024cd4: 1002175d ]... + +10024cd8 <__pre_init_runtime_init_post_clock_resets>: +10024cd8: 100216a9 .... + +10024cdc <__pre_init_runtime_init_boot_locks_reset>: +10024cdc: 100215c1 .... + +10024ce0 <__pre_init_runtime_init_spin_locks_reset>: +10024ce0: 100216f1 .... + +10024ce4 <__pre_init_runtime_init_bootrom_locking_enable>: +10024ce4: 100215ad .... + +10024ce8 <__pre_init_runtime_init_mutex>: +10024ce8: 10020ad5 .... + +10024cec <__pre_init_runtime_init_install_ram_vector_table>: +10024cec: 100216f5 .... + +10024cf0 <__pre_init_runtime_init_default_alarm_pool>: +10024cf0: 10020e51 Q... + +10024cf4 <__pre_init_first_per_core_initializer>: +10024cf4: 1002160d .... + +10024cf8 <__pre_init_runtime_init_per_core_bootrom_reset>: +10024cf8: 100216dd .... + +10024cfc <__pre_init_runtime_init_per_core_enable_coprocessors>: +10024cfc: 1002168d .... + +10024d00 <__pre_init_spinlock_set_extexclall>: +10024d00: 10020725 %... + +10024d04 <__pre_init_runtime_init_per_core_irq_priorities>: +10024d04: 1002074d M... + +10024d08 <__init_array_start>: +10024d08: 10024a95 .word 0x10024a95 + +10024d0c <__frame_dummy_init_array_entry>: +10024d0c: 10020211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 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r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10021175 .word 0x10021175 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : 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+:105418000000000000000000000003000000000081 +:10542800000000000000FF000000000001B548680F +:1054380001318E460047704609380149884701BD49 +:105448000D0A02100000000000000000000000002B +:1054580000000000000000003007002001360210A4 +:1054680009370210513602101937021000000000E7 +:0C54780000010000000000000000000027 +:10548400D3DEFFFFFE010000FF010000B4ACFFFF0C +:04549400793512ABA9 +:040000051002014D97 +:00000001FF diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.bin b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.bin new file mode 100755 index 0000000..5fd7c1b Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.dis b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.dis new file mode 100644 index 0000000..d5ea52b --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.dis @@ -0,0 +1,9675 @@ + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00005ea8 10000000 10000000 00001000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .rodata 00000318 10005ea8 10005ea8 00006ea8 2**3 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .ARM.exidx 00000008 100061c0 100061c0 000071c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .binary_info 00000028 100061c8 100061c8 000071c8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ram_vector_table 00000110 20000000 20000000 00009000 2**2 + ALLOC + 5 .uninitialized_data 00000000 20000110 20000110 00008c7c 2**0 + CONTENTS + 6 .data 00000a78 20000110 100061f0 00008110 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 7 .tdata 00000000 20000b88 20000b88 00008c7c 2**0 + CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL + 8 .tbss 00000000 20000b88 20000b88 00000000 2**0 + ALLOC, THREAD_LOCAL + 9 .bss 000025d8 20000b88 10006c68 00009b88 2**3 + ALLOC + 10 .heap 00000800 20003160 10006c68 00009160 2**2 + ALLOC, READONLY + 11 .scratch_x 00000000 20080000 20080000 00008c7c 2**0 + CONTENTS + 12 .scratch_y 00000000 20081000 20081000 00008c7c 2**0 + CONTENTS + 13 .stack_dummy 00000800 20081000 20081000 00009000 2**5 + ALLOC, READONLY + 14 .flash_end 00000014 10006c68 10006c68 00008c68 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 15 .ARM.attributes 00000034 00000000 00000000 00008c7c 2**0 + CONTENTS, READONLY + 16 .comment 00000045 00000000 00000000 00008cb0 2**0 + CONTENTS, READONLY + 17 .debug_info 00026e2f 00000000 00000000 00008cf5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_abbrev 00007361 00000000 00000000 0002fb24 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_aranges 00000ee8 00000000 00000000 00036e88 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_rnglists 00003993 00000000 00000000 00037d70 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line 0001b875 00000000 00000000 0003b703 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_str 000073cf 00000000 00000000 00056f78 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 23 .debug_frame 00002b30 00000000 00000000 0005e348 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 24 .debug_loclists 000147e2 00000000 00000000 00060e78 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 25 .debug_line_str 000002c0 00000000 00000000 0007565a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +/Users/kevinthomas/Documents/Embedded-Hacking/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf: file format elf32-littlearm + + +Disassembly of section .text: + +10000000 <__VECTOR_TABLE>: +10000000: 20082000 .word 0x20082000 +10000004: 1000015d .word 0x1000015d +10000008: 1000011b .word 0x1000011b +1000000c: 1000011d .word 0x1000011d +10000010: 10000111 .word 0x10000111 +10000014: 10000111 .word 0x10000111 +10000018: 10000111 .word 0x10000111 +1000001c: 10000111 .word 0x10000111 +10000020: 10000119 .word 0x10000119 +10000024: 10000119 .word 0x10000119 +10000028: 10000119 .word 0x10000119 +1000002c: 1000011f .word 0x1000011f +10000030: 10000111 .word 0x10000111 +10000034: 10000119 .word 0x10000119 +10000038: 10000121 .word 0x10000121 +1000003c: 10000123 .word 0x10000123 +10000040: 10000111 .word 0x10000111 +10000044: 10000111 .word 0x10000111 +10000048: 10000111 .word 0x10000111 +1000004c: 10000111 .word 0x10000111 +10000050: 10000111 .word 0x10000111 +10000054: 10000111 .word 0x10000111 +10000058: 10000111 .word 0x10000111 +1000005c: 10000111 .word 0x10000111 +10000060: 10000111 .word 0x10000111 +10000064: 10000111 .word 0x10000111 +10000068: 10000111 .word 0x10000111 +1000006c: 10000111 .word 0x10000111 +10000070: 10000111 .word 0x10000111 +10000074: 10000111 .word 0x10000111 +10000078: 10000111 .word 0x10000111 +1000007c: 10000111 .word 0x10000111 +10000080: 10000111 .word 0x10000111 +10000084: 10000111 .word 0x10000111 +10000088: 10000111 .word 0x10000111 +1000008c: 10000111 .word 0x10000111 +10000090: 10000111 .word 0x10000111 +10000094: 10000111 .word 0x10000111 +10000098: 10000111 .word 0x10000111 +1000009c: 10000111 .word 0x10000111 +100000a0: 10000111 .word 0x10000111 +100000a4: 10000111 .word 0x10000111 +100000a8: 10000111 .word 0x10000111 +100000ac: 10000111 .word 0x10000111 +100000b0: 10000111 .word 0x10000111 +100000b4: 10000111 .word 0x10000111 +100000b8: 10000111 .word 0x10000111 +100000bc: 10000111 .word 0x10000111 +100000c0: 10000111 .word 0x10000111 +100000c4: 10000111 .word 0x10000111 +100000c8: 10000111 .word 0x10000111 +100000cc: 10000111 .word 0x10000111 +100000d0: 10000111 .word 0x10000111 +100000d4: 10000111 .word 0x10000111 +100000d8: 10000111 .word 0x10000111 +100000dc: 10000111 .word 0x10000111 +100000e0: 10000111 .word 0x10000111 +100000e4: 10000111 .word 0x10000111 +100000e8: 10000111 .word 0x10000111 +100000ec: 10000111 .word 0x10000111 +100000f0: 10000111 .word 0x10000111 +100000f4: 10000111 .word 0x10000111 +100000f8: 10000111 .word 0x10000111 +100000fc: 10000111 .word 0x10000111 +10000100: 10000111 .word 0x10000111 +10000104: 10000111 .word 0x10000111 +10000108: 10000111 .word 0x10000111 +1000010c: 10000111 .word 0x10000111 + +10000110 <__unhandled_user_irq>: +10000110: f3ef 8005 mrs r0, IPSR +10000114: 3810 subs r0, #16 + +10000116 : +10000116: be00 bkpt 0x0000 + +10000118 : +10000118: be00 bkpt 0x0000 + +1000011a : +1000011a: be00 bkpt 0x0000 + +1000011c : +1000011c: be00 bkpt 0x0000 + +1000011e : +1000011e: be00 bkpt 0x0000 + +10000120 : +10000120: be00 bkpt 0x0000 + +10000122 : +10000122: be00 bkpt 0x0000 + +10000124 <__default_isrs_end>: +10000124: 7188ebf2 .word 0x7188ebf2 +10000128: 100061c8 .word 0x100061c8 +1000012c: 100061f0 .word 0x100061f0 +10000130: 100001a0 .word 0x100001a0 +10000134: e71aa390 .word 0xe71aa390 + +10000138 <__binary_info_header_end>: +10000138: ffffded3 .word 0xffffded3 +1000013c: 10210142 .word 0x10210142 +10000140: 000001ff .word 0x000001ff +10000144: 00006b30 .word 0x00006b30 +10000148: ab123579 .word 0xab123579 + +1000014c <_entry_point>: +1000014c: f04f 0000 mov.w r0, #0 + +10000150 <_enter_vtable_in_r0>: +10000150: 491e ldr r1, [pc, #120] @ (100001cc ) +10000152: 6008 str r0, [r1, #0] +10000154: c806 ldmia r0!, {r1, r2} +10000156: f381 8808 msr MSP, r1 +1000015a: 4710 bx r2 + +1000015c <_reset_handler>: +1000015c: f04f 4050 mov.w r0, #3489660928 @ 0xd0000000 +10000160: 6800 ldr r0, [r0, #0] +10000162: b110 cbz r0, 1000016a + +10000164 : +10000164: f04f 0000 mov.w r0, #0 +10000168: e7f2 b.n 10000150 <_enter_vtable_in_r0> +1000016a: a40d add r4, pc, #52 @ (adr r4, 100001a0 ) +1000016c: cc0e ldmia r4!, {r1, r2, r3} +1000016e: 2900 cmp r1, #0 +10000170: d002 beq.n 10000178 +10000172: f000 f812 bl 1000019a +10000176: e7f9 b.n 1000016c +10000178: 4915 ldr r1, [pc, #84] @ (100001d0 ) +1000017a: 4a16 ldr r2, [pc, #88] @ (100001d4 ) +1000017c: 2000 movs r0, #0 +1000017e: e000 b.n 10000182 + +10000180 : +10000180: c101 stmia r1!, {r0} + +10000182 : +10000182: 4291 cmp r1, r2 +10000184: d1fc bne.n 10000180 + +10000186 : +10000186: 4914 ldr r1, [pc, #80] @ (100001d8 ) +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] @ (100001dc ) +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] @ (100001e0 ) +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +10000194: e7fd b.n 10000192 + +10000196 : +10000196: c901 ldmia r1!, {r0} +10000198: c201 stmia r2!, {r0} + +1000019a : +1000019a: 429a cmp r2, r3 +1000019c: d3fb bcc.n 10000196 +1000019e: 4770 bx lr + +100001a0 : +100001a0: 100061f0 .word 0x100061f0 +100001a4: 20000110 .word 0x20000110 +100001a8: 20000b88 .word 0x20000b88 +100001ac: 10006c68 .word 0x10006c68 +100001b0: 20080000 .word 0x20080000 +100001b4: 20080000 .word 0x20080000 +100001b8: 10006c68 .word 0x10006c68 +100001bc: 20081000 .word 0x20081000 +100001c0: 20081000 .word 0x20081000 +100001c4: 00000000 .word 0x00000000 +100001c8: 4770 bx lr +100001ca: 0000 .short 0x0000 +100001cc: e000ed08 .word 0xe000ed08 +100001d0: 20000b88 .word 0x20000b88 +100001d4: 20003160 .word 0x20003160 +100001d8: 10002ff1 .word 0x10002ff1 +100001dc: 10000235 .word 0x10000235 +100001e0: 10002fe9 .word 0x10002fe9 + +100001e4 <_init>: +100001e4: b5f8 push {r3, r4, r5, r6, r7, lr} +100001e6: bf00 nop + +100001e8 : +100001e8: 4b06 ldr r3, [pc, #24] @ (10000204 ) +100001ea: 4907 ldr r1, [pc, #28] @ (10000208 ) +100001ec: 1ac9 subs r1, r1, r3 +100001ee: 1089 asrs r1, r1, #2 +100001f0: bf48 it mi +100001f2: 3101 addmi r1, #1 +100001f4: 1049 asrs r1, r1, #1 +100001f6: d003 beq.n 10000200 +100001f8: 4b04 ldr r3, [pc, #16] @ (1000020c ) +100001fa: b10b cbz r3, 10000200 +100001fc: 4801 ldr r0, [pc, #4] @ (10000204 ) +100001fe: 4718 bx r3 +10000200: 4770 bx lr +10000202: bf00 nop +10000204: 20000b88 .word 0x20000b88 +10000208: 20000b88 .word 0x20000b88 +1000020c: 00000000 .word 0x00000000 + +10000210 : +10000210: b508 push {r3, lr} +10000212: 4b05 ldr r3, [pc, #20] @ (10000228 ) +10000214: b11b cbz r3, 1000021e +10000216: 4905 ldr r1, [pc, #20] @ (1000022c ) +10000218: 4805 ldr r0, [pc, #20] @ (10000230 ) +1000021a: f3af 8000 nop.w +1000021e: e8bd 4008 ldmia.w sp!, {r3, lr} +10000222: f7ff bfe1 b.w 100001e8 +10000226: bf00 nop +10000228: 00000000 .word 0x00000000 +1000022c: 20003110 .word 0x20003110 +10000230: 10005ea8 .word 0x10005ea8 + +10000234
: +10000234: b500 push {lr} +10000236: b089 sub sp, #36 @ 0x24 +10000238: f000 f81e bl 10000278 +1000023c: 4668 mov r0, sp +1000023e: f000 f843 bl 100002c8 +10000242: 4668 mov r0, sp +10000244: f000 f85a bl 100002fc +10000248: b150 cbz r0, 10000260 +1000024a: 4668 mov r0, sp +1000024c: f000 f8b0 bl 100003b0 +10000250: b150 cbz r0, 10000268 +10000252: 4668 mov r0, sp +10000254: f000 f82a bl 100002ac +10000258: 2000 movs r0, #0 +1000025a: b009 add sp, #36 @ 0x24 +1000025c: f85d fb04 ldr.w pc, [sp], #4 +10000260: 4803 ldr r0, [pc, #12] @ (10000270 ) +10000262: f000 f817 bl 10000294 +10000266: e7f0 b.n 1000024a +10000268: 4802 ldr r0, [pc, #8] @ (10000274 ) +1000026a: f000 f813 bl 10000294 +1000026e: e7f0 b.n 10000252 +10000270: 10005ea8 .word 0x10005ea8 +10000274: 10005ebc .word 0x10005ebc + +10000278 : +10000278: b508 push {r3, lr} +1000027a: f002 ffe1 bl 10003240 +1000027e: f44f 60fa mov.w r0, #2000 @ 0x7d0 +10000282: f000 fdd1 bl 10000e28 +10000286: e8bd 4008 ldmia.w sp!, {r3, lr} +1000028a: 4801 ldr r0, [pc, #4] @ (10000290 ) +1000028c: f003 b820 b.w 100032d0 <__wrap_puts> +10000290: 10005ed8 .word 0x10005ed8 + +10000294 : +10000294: 4601 mov r1, r0 +10000296: b508 push {r3, lr} +10000298: 4803 ldr r0, [pc, #12] @ (100002a8 ) +1000029a: f003 f899 bl 100033d0 <__wrap_printf> +1000029e: f44f 70fa mov.w r0, #500 @ 0x1f4 +100002a2: f000 fdc1 bl 10000e28 +100002a6: e7fa b.n 1000029e +100002a8: 10005efc .word 0x10005efc + +100002ac : +100002ac: b510 push {r4, lr} +100002ae: 4604 mov r4, r0 +100002b0: 4804 ldr r0, [pc, #16] @ (100002c4 ) +100002b2: 68a1 ldr r1, [r4, #8] +100002b4: f003 f88c bl 100033d0 <__wrap_printf> +100002b8: 68a0 ldr r0, [r4, #8] +100002ba: e8bd 4010 ldmia.w sp!, {r4, lr} +100002be: f000 b869 b.w 10000394 +100002c2: bf00 nop +100002c4: 10005f10 .word 0x10005f10 + +100002c8 : +100002c8: 4684 mov ip, r0 +100002ca: b410 push {r4} +100002cc: 4c0a ldr r4, [pc, #40] @ (100002f8 ) +100002ce: cc0f ldmia r4!, {r0, r1, r2, r3} +100002d0: f8cc 0000 str.w r0, [ip] +100002d4: f8cc 1004 str.w r1, [ip, #4] +100002d8: f8cc 2008 str.w r2, [ip, #8] +100002dc: f8cc 300c str.w r3, [ip, #12] +100002e0: cc0f ldmia r4!, {r0, r1, r2, r3} +100002e2: f85d 4b04 ldr.w r4, [sp], #4 +100002e6: f8cc 0010 str.w r0, [ip, #16] +100002ea: f8cc 1014 str.w r1, [ip, #20] +100002ee: f8cc 2018 str.w r2, [ip, #24] +100002f2: f8cc 301c str.w r3, [ip, #28] +100002f6: 4770 bx lr +100002f8: 1001f000 .word 0x1001f000 + +100002fc : +100002fc: 4b06 ldr r3, [pc, #24] @ (10000318 ) +100002fe: 6802 ldr r2, [r0, #0] +10000300: 429a cmp r2, r3 +10000302: d106 bne.n 10000312 +10000304: 6840 ldr r0, [r0, #4] +10000306: f1a0 0001 sub.w r0, r0, #1 +1000030a: fab0 f080 clz r0, r0 +1000030e: 0940 lsrs r0, r0, #5 +10000310: 4770 bx lr +10000312: 2000 movs r0, #0 +10000314: 4770 bx lr +10000316: bf00 nop +10000318: 424c4657 .word 0x424c4657 + +1000031c : +1000031c: b5f0 push {r4, r5, r6, r7, lr} +1000031e: 4606 mov r6, r0 +10000320: b083 sub sp, #12 +10000322: 2002 movs r0, #2 +10000324: 460f mov r7, r1 +10000326: 4614 mov r4, r2 +10000328: 461d mov r5, r3 +1000032a: f004 faaf bl 1000488c +1000032e: b140 cbz r0, 10000342 +10000330: 463b mov r3, r7 +10000332: 4631 mov r1, r6 +10000334: 2280 movs r2, #128 @ 0x80 +10000336: 9501 str r5, [sp, #4] +10000338: 9400 str r4, [sp, #0] +1000033a: f004 ff7d bl 10005238 +1000033e: b003 add sp, #12 +10000340: bdf0 pop {r4, r5, r6, r7, pc} +10000342: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000346: e7fa b.n 1000033e + +10000348 : +10000348: b500 push {lr} +1000034a: f8d0 c000 ldr.w ip, [r0] +1000034e: 680b ldr r3, [r1, #0] +10000350: 6842 ldr r2, [r0, #4] +10000352: ea83 030c eor.w r3, r3, ip +10000356: f8d1 c004 ldr.w ip, [r1, #4] +1000035a: f8d1 e00c ldr.w lr, [r1, #12] +1000035e: ea82 020c eor.w r2, r2, ip +10000362: f8d1 c008 ldr.w ip, [r1, #8] +10000366: 6881 ldr r1, [r0, #8] +10000368: 4313 orrs r3, r2 +1000036a: 68c2 ldr r2, [r0, #12] +1000036c: ea8c 0101 eor.w r1, ip, r1 +10000370: ea82 020e eor.w r2, r2, lr +10000374: 430b orrs r3, r1 +10000376: 4313 orrs r3, r2 +10000378: f3c3 2007 ubfx r0, r3, #8, #8 +1000037c: 4318 orrs r0, r3 +1000037e: f3c3 4207 ubfx r2, r3, #16, #8 +10000382: 4310 orrs r0, r2 +10000384: ea40 6013 orr.w r0, r0, r3, lsr #24 +10000388: b2c0 uxtb r0, r0 +1000038a: fab0 f080 clz r0, r0 +1000038e: 0940 lsrs r0, r0, #5 +10000390: f85d fb04 ldr.w pc, [sp], #4 + +10000394 : +10000394: 6843 ldr r3, [r0, #4] +10000396: b672 cpsid i +10000398: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +1000039c: f8c2 0d08 str.w r0, [r2, #3336] @ 0xd08 +100003a0: 6802 ldr r2, [r0, #0] +100003a2: f382 8808 msr MSP, r2 +100003a6: f3bf 8f4f dsb sy +100003aa: f3bf 8f6f isb sy +100003ae: 4718 bx r3 + +100003b0 : +100003b0: b510 push {r4, lr} +100003b2: 4604 mov r4, r0 +100003b4: b084 sub sp, #16 +100003b6: 466b mov r3, sp +100003b8: 4807 ldr r0, [pc, #28] @ (100003d8 ) +100003ba: 68e2 ldr r2, [r4, #12] +100003bc: 68a1 ldr r1, [r4, #8] +100003be: f7ff ffad bl 1000031c +100003c2: b110 cbz r0, 100003ca +100003c4: 2000 movs r0, #0 +100003c6: b004 add sp, #16 +100003c8: bd10 pop {r4, pc} +100003ca: 4668 mov r0, sp +100003cc: f104 0110 add.w r1, r4, #16 +100003d0: f7ff ffba bl 10000348 +100003d4: b004 add sp, #16 +100003d6: bd10 pop {r4, pc} +100003d8: 10006064 .word 0x10006064 + +100003dc : +100003dc: b410 push {r4} +100003de: f44f 7480 mov.w r4, #256 @ 0x100 +100003e2: 4b0c ldr r3, [pc, #48] @ (10000414 ) +100003e4: f853 2020 ldr.w r2, [r3, r0, lsl #2] +100003e8: eb03 0380 add.w r3, r3, r0, lsl #2 +100003ec: 00c0 lsls r0, r0, #3 +100003ee: f082 0240 eor.w r2, r2, #64 @ 0x40 +100003f2: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +100003f6: f503 5c80 add.w ip, r3, #4096 @ 0x1000 +100003fa: f002 02c0 and.w r2, r2, #192 @ 0xc0 +100003fe: f500 3020 add.w r0, r0, #163840 @ 0x28000 +10000402: f503 5340 add.w r3, r3, #12288 @ 0x3000 +10000406: f8cc 2000 str.w r2, [ip] +1000040a: 6041 str r1, [r0, #4] +1000040c: 601c str r4, [r3, #0] +1000040e: f85d 4b04 ldr.w r4, [sp], #4 +10000412: 4770 bx lr +10000414: 40038004 .word 0x40038004 + +10000418 : +10000418: b40f push {r0, r1, r2, r3} +1000041a: b500 push {lr} +1000041c: b083 sub sp, #12 +1000041e: 9c04 ldr r4, [sp, #16] +10000420: 4807 ldr r0, [pc, #28] @ (10000440 ) +10000422: f002 ff55 bl 100032d0 <__wrap_puts> +10000426: b13c cbz r4, 10000438 +10000428: a905 add r1, sp, #20 +1000042a: 4620 mov r0, r4 +1000042c: 9101 str r1, [sp, #4] +1000042e: f002 fdab bl 10002f88 +10000432: 4804 ldr r0, [pc, #16] @ (10000444 ) +10000434: f002 ff4c bl 100032d0 <__wrap_puts> +10000438: 2001 movs r0, #1 +1000043a: f002 fdbd bl 10002fb8 <_exit> +1000043e: bf00 nop +10000440: 10005f3c .word 0x10005f3c +10000444: 10005f4c .word 0x10005f4c + +10000448 : +10000448: b570 push {r4, r5, r6, lr} +1000044a: 4686 mov lr, r0 +1000044c: f3ef 8510 mrs r5, PRIMASK +10000450: b672 cpsid i +10000452: 4c12 ldr r4, [pc, #72] @ (1000049c ) +10000454: e8d4 6fcf ldaexb r6, [r4] +10000458: 2001 movs r0, #1 +1000045a: 2e00 cmp r6, #0 +1000045c: d1fa bne.n 10000454 +1000045e: e8c4 0f46 strexb r6, r0, [r4] +10000462: 2e00 cmp r6, #0 +10000464: d1f6 bne.n 10000454 +10000466: f3bf 8f5f dmb sy +1000046a: f04f 0c01 mov.w ip, #1 +1000046e: 08c8 lsrs r0, r1, #3 +10000470: f001 0307 and.w r3, r1, #7 +10000474: fa0c f303 lsl.w r3, ip, r3 +10000478: f81e c000 ldrb.w ip, [lr, r0] +1000047c: ea1c 0603 ands.w r6, ip, r3 +10000480: d108 bne.n 10000494 +10000482: ea4c 0c03 orr.w ip, ip, r3 +10000486: f80e c000 strb.w ip, [lr, r0] +1000048a: e8c4 6f8f stlb r6, [r4] +1000048e: f385 8810 msr PRIMASK, r5 +10000492: bd70 pop {r4, r5, r6, pc} +10000494: 4610 mov r0, r2 +10000496: f7ff ffbf bl 10000418 +1000049a: bf00 nop +1000049c: 200030ab .word 0x200030ab + +100004a0 : +100004a0: 4a04 ldr r2, [pc, #16] @ (100004b4 ) +100004a2: 7810 ldrb r0, [r2, #0] +100004a4: 1c43 adds r3, r0, #1 +100004a6: b2db uxtb r3, r3 +100004a8: 2b18 cmp r3, #24 +100004aa: bf28 it cs +100004ac: 2310 movcs r3, #16 +100004ae: 7013 strb r3, [r2, #0] +100004b0: 4770 bx lr +100004b2: bf00 nop +100004b4: 200005a8 .word 0x200005a8 + +100004b8 : +100004b8: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +100004bc: 6893 ldr r3, [r2, #8] +100004be: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 +100004c2: 6093 str r3, [r2, #8] +100004c4: 4770 bx lr +100004c6: bf00 nop + +100004c8 : +100004c8: 2100 movs r1, #0 +100004ca: 4b04 ldr r3, [pc, #16] @ (100004dc ) +100004cc: f103 0220 add.w r2, r3, #32 +100004d0: e8c3 1f8f stlb r1, [r3] +100004d4: 3301 adds r3, #1 +100004d6: 4293 cmp r3, r2 +100004d8: d1fa bne.n 100004d0 +100004da: 4770 bx lr +100004dc: 200030a0 .word 0x200030a0 + +100004e0 : +100004e0: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 +100004e4: f04f 3280 mov.w r2, #2155905152 @ 0x80808080 +100004e8: f8c3 2400 str.w r2, [r3, #1024] @ 0x400 +100004ec: f8c3 2404 str.w r2, [r3, #1028] @ 0x404 +100004f0: f8c3 2408 str.w r2, [r3, #1032] @ 0x408 +100004f4: f8c3 240c str.w r2, [r3, #1036] @ 0x40c +100004f8: f8c3 2410 str.w r2, [r3, #1040] @ 0x410 +100004fc: f8c3 2414 str.w r2, [r3, #1044] @ 0x414 +10000500: f8c3 2418 str.w r2, [r3, #1048] @ 0x418 +10000504: f8c3 241c str.w r2, [r3, #1052] @ 0x41c +10000508: f8c3 2420 str.w r2, [r3, #1056] @ 0x420 +1000050c: f8c3 2424 str.w r2, [r3, #1060] @ 0x424 +10000510: f8c3 2428 str.w r2, [r3, #1064] @ 0x428 +10000514: f8c3 242c str.w r2, [r3, #1068] @ 0x42c +10000518: f8c3 2430 str.w r2, [r3, #1072] @ 0x430 +1000051c: b662 cpsie i +1000051e: 4770 bx lr + +10000520 : +10000520: 2301 movs r3, #1 +10000522: f000 021f and.w r2, r0, #31 +10000526: 4093 lsls r3, r2 +10000528: 0940 lsrs r0, r0, #5 +1000052a: b141 cbz r1, 1000053e +1000052c: 0080 lsls r0, r0, #2 +1000052e: f100 4060 add.w r0, r0, #3758096384 @ 0xe0000000 +10000532: f500 4061 add.w r0, r0, #57600 @ 0xe100 +10000536: f8c0 3180 str.w r3, [r0, #384] @ 0x180 +1000053a: 6003 str r3, [r0, #0] +1000053c: 4770 bx lr +1000053e: 4a02 ldr r2, [pc, #8] @ (10000548 ) +10000540: 3020 adds r0, #32 +10000542: f842 3020 str.w r3, [r2, r0, lsl #2] +10000546: 4770 bx lr +10000548: e000e100 .word 0xe000e100 + +1000054c : +1000054c: b5f8 push {r3, r4, r5, r6, r7, lr} +1000054e: 460d mov r5, r1 +10000550: f3ef 8710 mrs r7, PRIMASK +10000554: b672 cpsid i +10000556: 4e12 ldr r6, [pc, #72] @ (100005a0 ) +10000558: e8d6 2fcf ldaexb r2, [r6] +1000055c: 2301 movs r3, #1 +1000055e: 2a00 cmp r2, #0 +10000560: d1fa bne.n 10000558 +10000562: e8c6 3f42 strexb r2, r3, [r6] +10000566: 2a00 cmp r2, #0 +10000568: d1f6 bne.n 10000558 +1000056a: f3bf 8f5f dmb sy +1000056e: 4b0d ldr r3, [pc, #52] @ (100005a4 ) +10000570: f100 0410 add.w r4, r0, #16 +10000574: 689b ldr r3, [r3, #8] +10000576: 4a0c ldr r2, [pc, #48] @ (100005a8 ) +10000578: f853 3024 ldr.w r3, [r3, r4, lsl #2] +1000057c: 4293 cmp r3, r2 +1000057e: d003 beq.n 10000588 +10000580: 4299 cmp r1, r3 +10000582: d001 beq.n 10000588 +10000584: f000 ff0c bl 100013a0 +10000588: 4b06 ldr r3, [pc, #24] @ (100005a4 ) +1000058a: 689b ldr r3, [r3, #8] +1000058c: f843 5024 str.w r5, [r3, r4, lsl #2] +10000590: f3bf 8f5f dmb sy +10000594: 2300 movs r3, #0 +10000596: e8c6 3f8f stlb r3, [r6] +1000059a: f387 8810 msr PRIMASK, r7 +1000059e: bdf8 pop {r3, r4, r5, r6, r7, pc} +100005a0: 200030a9 .word 0x200030a9 +100005a4: e000ed00 .word 0xe000ed00 +100005a8: 10000111 .word 0x10000111 + +100005ac : +100005ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100005b0: b083 sub sp, #12 +100005b2: f3ef 8a10 mrs sl, PRIMASK +100005b6: b672 cpsid i +100005b8: 4e71 ldr r6, [pc, #452] @ (10000780 ) +100005ba: e8d6 2fcf ldaexb r2, [r6] +100005be: 2301 movs r3, #1 +100005c0: 2a00 cmp r2, #0 +100005c2: d1fa bne.n 100005ba +100005c4: e8c6 3f42 strexb r2, r3, [r6] +100005c8: 2a00 cmp r2, #0 +100005ca: d1f6 bne.n 100005ba +100005cc: f3bf 8f5f dmb sy +100005d0: 4b6c ldr r3, [pc, #432] @ (10000784 ) +100005d2: f100 0810 add.w r8, r0, #16 +100005d6: 689b ldr r3, [r3, #8] +100005d8: 4a6b ldr r2, [pc, #428] @ (10000788 ) +100005da: f853 5028 ldr.w r5, [r3, r8, lsl #2] +100005de: 4295 cmp r5, r2 +100005e0: d045 beq.n 1000066e +100005e2: 428d cmp r5, r1 +100005e4: 460c mov r4, r1 +100005e6: d050 beq.n 1000068a +100005e8: 4f68 ldr r7, [pc, #416] @ (1000078c ) +100005ea: 1beb subs r3, r5, r7 +100005ec: 2b2f cmp r3, #47 @ 0x2f +100005ee: d83e bhi.n 1000066e +100005f0: 2101 movs r1, #1 +100005f2: ea4f 1950 mov.w r9, r0, lsr #5 +100005f6: ea4f 0989 mov.w r9, r9, lsl #2 +100005fa: f109 4960 add.w r9, r9, #3758096384 @ 0xe0000000 +100005fe: f509 4961 add.w r9, r9, #57600 @ 0xe100 +10000602: f000 031f and.w r3, r0, #31 +10000606: fa01 f003 lsl.w r0, r1, r3 +1000060a: f8d9 3000 ldr.w r3, [r9] +1000060e: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +10000612: ea00 0b03 and.w fp, r0, r3 +10000616: f3bf 8f5f dmb sy +1000061a: f3ef 8105 mrs r1, IPSR +1000061e: b2c9 uxtb r1, r1 +10000620: 2900 cmp r1, #0 +10000622: d034 beq.n 1000068e +10000624: 4588 cmp r8, r1 +10000626: d005 beq.n 10000634 +10000628: e9cd 1000 strd r1, r0, [sp] +1000062c: f000 feb8 bl 100013a0 +10000630: e9dd 1000 ldrd r1, r0, [sp] +10000634: f025 0e01 bic.w lr, r5, #1 +10000638: f8de c008 ldr.w ip, [lr, #8] +1000063c: 4564 cmp r4, ip +1000063e: d105 bne.n 1000064c +10000640: e089 b.n 10000756 +10000642: f8d3 c008 ldr.w ip, [r3, #8] +10000646: 4564 cmp r4, ip +10000648: d031 beq.n 100006ae +1000064a: 469e mov lr, r3 +1000064c: f99e 2006 ldrsb.w r2, [lr, #6] +10000650: eb02 0342 add.w r3, r2, r2, lsl #1 +10000654: 2a00 cmp r2, #0 +10000656: eb07 0383 add.w r3, r7, r3, lsl #2 +1000065a: daf2 bge.n 10000642 +1000065c: 4564 cmp r4, ip +1000065e: d061 beq.n 10000724 +10000660: f1bb 0f00 cmp.w fp, #0 +10000664: d020 beq.n 100006a8 +10000666: f8c9 0180 str.w r0, [r9, #384] @ 0x180 +1000066a: f8c9 0000 str.w r0, [r9] +1000066e: 4b45 ldr r3, [pc, #276] @ (10000784 ) +10000670: 689b ldr r3, [r3, #8] +10000672: f843 5028 str.w r5, [r3, r8, lsl #2] +10000676: f3bf 8f5f dmb sy +1000067a: 2300 movs r3, #0 +1000067c: e8c6 3f8f stlb r3, [r6] +10000680: f38a 8810 msr PRIMASK, sl +10000684: b003 add sp, #12 +10000686: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000068a: 4615 mov r5, r2 +1000068c: e7ef b.n 1000066e +1000068e: f025 0e01 bic.w lr, r5, #1 +10000692: f8de c008 ldr.w ip, [lr, #8] +10000696: 4564 cmp r4, ip +10000698: d1d8 bne.n 1000064c +1000069a: f99e 4006 ldrsb.w r4, [lr, #6] +1000069e: 4673 mov r3, lr +100006a0: 2c00 cmp r4, #0 +100006a2: da08 bge.n 100006b6 +100006a4: 4615 mov r5, r2 +100006a6: e046 b.n 10000736 +100006a8: f8c9 0080 str.w r0, [r9, #128] @ 0x80 +100006ac: e7df b.n 1000066e +100006ae: f993 4006 ldrsb.w r4, [r3, #6] +100006b2: 2c00 cmp r4, #0 +100006b4: db37 blt.n 10000726 +100006b6: eb04 0c44 add.w ip, r4, r4, lsl #1 +100006ba: eb07 0c8c add.w ip, r7, ip, lsl #2 +100006be: f89c 1007 ldrb.w r1, [ip, #7] +100006c2: f8dc 2008 ldr.w r2, [ip, #8] +100006c6: 71d9 strb r1, [r3, #7] +100006c8: 609a str r2, [r3, #8] +100006ca: f99c 2006 ldrsb.w r2, [ip, #6] +100006ce: 0061 lsls r1, r4, #1 +100006d0: 2a00 cmp r2, #0 +100006d2: 719a strb r2, [r3, #6] +100006d4: db3d blt.n 10000752 +100006d6: f8bc e004 ldrh.w lr, [ip, #4] +100006da: ea5f 5e4e movs.w lr, lr, lsl #21 +100006de: d505 bpl.n 100006ec +100006e0: f50e 1eff add.w lr, lr, #2088960 @ 0x1fe000 +100006e4: f50e 5eff add.w lr, lr, #8160 @ 0x1fe0 +100006e8: f10e 0e1f add.w lr, lr, #31 +100006ec: f06f 0c07 mvn.w ip, #7 +100006f0: 190a adds r2, r1, r4 +100006f2: ea4f 5e6e mov.w lr, lr, asr #21 +100006f6: 0092 lsls r2, r2, #2 +100006f8: eb02 024e add.w r2, r2, lr, lsl #1 +100006fc: 3208 adds r2, #8 +100006fe: 443a add r2, r7 +10000700: ebac 0c03 sub.w ip, ip, r3 +10000704: 4462 add r2, ip +10000706: f3c2 024a ubfx r2, r2, #1, #11 +1000070a: ea6f 42c2 mvn.w r2, r2, lsl #19 +1000070e: ea6f 42d2 mvn.w r2, r2, lsr #19 +10000712: 809a strh r2, [r3, #4] +10000714: 4b1e ldr r3, [pc, #120] @ (10000790 ) +10000716: 4421 add r1, r4 +10000718: 781a ldrb r2, [r3, #0] +1000071a: eb07 0181 add.w r1, r7, r1, lsl #2 +1000071e: 701c strb r4, [r3, #0] +10000720: 718a strb r2, [r1, #6] +10000722: e79d b.n 10000660 +10000724: 4673 mov r3, lr +10000726: b9d9 cbnz r1, 10000760 +10000728: 22ff movs r2, #255 @ 0xff +1000072a: f88e 2006 strb.w r2, [lr, #6] +1000072e: f64b 5201 movw r2, #48385 @ 0xbd01 +10000732: f8ae 2004 strh.w r2, [lr, #4] +10000736: 4c16 ldr r4, [pc, #88] @ (10000790 ) +10000738: f64a 22aa movw r2, #43690 @ 0xaaaa +1000073c: f894 c000 ldrb.w ip, [r4] +10000740: 4619 mov r1, r3 +10000742: 1bc9 subs r1, r1, r7 +10000744: 4149 adcs r1, r1 +10000746: 434a muls r2, r1 +10000748: 0d12 lsrs r2, r2, #20 +1000074a: f883 c006 strb.w ip, [r3, #6] +1000074e: 7022 strb r2, [r4, #0] +10000750: e786 b.n 10000660 +10000752: 4a10 ldr r2, [pc, #64] @ (10000794 ) +10000754: e7dd b.n 10000712 +10000756: f99e 4006 ldrsb.w r4, [lr, #6] +1000075a: 4673 mov r3, lr +1000075c: 2c00 cmp r4, #0 +1000075e: daaa bge.n 100006b6 +10000760: 4a0d ldr r2, [pc, #52] @ (10000798 ) +10000762: 4c0e ldr r4, [pc, #56] @ (1000079c ) +10000764: 1ad2 subs r2, r2, r3 +10000766: 3a08 subs r2, #8 +10000768: f3c2 310a ubfx r1, r2, #12, #11 +1000076c: ea6f 5101 mvn.w r1, r1, lsl #20 +10000770: ea6f 5111 mvn.w r1, r1, lsr #20 +10000774: ea44 0252 orr.w r2, r4, r2, lsr #1 +10000778: 80da strh r2, [r3, #6] +1000077a: 8099 strh r1, [r3, #4] +1000077c: e770 b.n 10000660 +1000077e: bf00 nop +10000780: 200030a9 .word 0x200030a9 +10000784: e000ed00 .word 0xe000ed00 +10000788: 10000111 .word 0x10000111 +1000078c: 200005ac .word 0x200005ac +10000790: 2000315c .word 0x2000315c +10000794: ffffbd01 .word 0xffffbd01 +10000798: 200005e6 .word 0x200005e6 +1000079c: fffff800 .word 0xfffff800 + +100007a0 : +100007a0: b5f0 push {r4, r5, r6, r7, lr} +100007a2: f3ef 8505 mrs r5, IPSR +100007a6: b2ed uxtb r5, r5 +100007a8: f3ef 8c10 mrs ip, PRIMASK +100007ac: b672 cpsid i +100007ae: 4926 ldr r1, [pc, #152] @ (10000848 ) +100007b0: e8d1 2fcf ldaexb r2, [r1] +100007b4: 2301 movs r3, #1 +100007b6: 2a00 cmp r2, #0 +100007b8: d1fa bne.n 100007b0 +100007ba: e8c1 3f42 strexb r2, r3, [r1] +100007be: 2a00 cmp r2, #0 +100007c0: d1f6 bne.n 100007b0 +100007c2: f3bf 8f5f dmb sy +100007c6: 4e21 ldr r6, [pc, #132] @ (1000084c ) +100007c8: f040 0e01 orr.w lr, r0, #1 +100007cc: 68b4 ldr r4, [r6, #8] +100007ce: f64a 23aa movw r3, #43690 @ 0xaaaa +100007d2: f854 7025 ldr.w r7, [r4, r5, lsl #2] +100007d6: 4a1e ldr r2, [pc, #120] @ (10000850 ) +100007d8: 4604 mov r4, r0 +100007da: 1aa4 subs r4, r4, r2 +100007dc: 4164 adcs r4, r4 +100007de: 4363 muls r3, r4 +100007e0: 0d1b lsrs r3, r3, #20 +100007e2: 4577 cmp r7, lr +100007e4: b25b sxtb r3, r3 +100007e6: d01b beq.n 10000820 +100007e8: f992 4006 ldrsb.w r4, [r2, #6] +100007ec: 429c cmp r4, r3 +100007ee: d01c beq.n 1000082a +100007f0: f992 4012 ldrsb.w r4, [r2, #18] +100007f4: 429c cmp r4, r3 +100007f6: d023 beq.n 10000840 +100007f8: f992 401e ldrsb.w r4, [r2, #30] +100007fc: 429c cmp r4, r3 +100007fe: d021 beq.n 10000844 +10000800: f992 402a ldrsb.w r4, [r2, #42] @ 0x2a +10000804: 429c cmp r4, r3 +10000806: bf08 it eq +10000808: 2403 moveq r4, #3 +1000080a: d00f beq.n 1000082c +1000080c: 4a11 ldr r2, [pc, #68] @ (10000854 ) +1000080e: 2400 movs r4, #0 +10000810: 7815 ldrb r5, [r2, #0] +10000812: 7013 strb r3, [r2, #0] +10000814: 7185 strb r5, [r0, #6] +10000816: e8c1 4f8f stlb r4, [r1] +1000081a: f38c 8810 msr PRIMASK, ip +1000081e: bdf0 pop {r4, r5, r6, r7, pc} +10000820: 68b2 ldr r2, [r6, #8] +10000822: 4c0d ldr r4, [pc, #52] @ (10000858 ) +10000824: f842 4025 str.w r4, [r2, r5, lsl #2] +10000828: e7f0 b.n 1000080c +1000082a: 2400 movs r4, #0 +1000082c: eb04 0444 add.w r4, r4, r4, lsl #1 +10000830: eb02 0284 add.w r2, r2, r4, lsl #2 +10000834: 24ff movs r4, #255 @ 0xff +10000836: 7194 strb r4, [r2, #6] +10000838: f64b 5401 movw r4, #48385 @ 0xbd01 +1000083c: 8094 strh r4, [r2, #4] +1000083e: e7e5 b.n 1000080c +10000840: 2401 movs r4, #1 +10000842: e7f3 b.n 1000082c +10000844: 2402 movs r4, #2 +10000846: e7f1 b.n 1000082c +10000848: 200030a9 .word 0x200030a9 +1000084c: e000ed00 .word 0xe000ed00 +10000850: 200005ac .word 0x200005ac +10000854: 2000315c .word 0x2000315c +10000858: 10000111 .word 0x10000111 + +1000085c : +1000085c: 4b01 ldr r3, [pc, #4] @ (10000864 ) +1000085e: 440b add r3, r1 +10000860: 6003 str r3, [r0, #0] +10000862: 4770 bx lr +10000864: 200030a0 .word 0x200030a0 + +10000868 : +10000868: b570 push {r4, r5, r6, lr} +1000086a: 4c10 ldr r4, [pc, #64] @ (100008ac ) +1000086c: 4d10 ldr r5, [pc, #64] @ (100008b0 ) +1000086e: 42ac cmp r4, r5 +10000870: d20e bcs.n 10000890 +10000872: 26ff movs r6, #255 @ 0xff +10000874: 6823 ldr r3, [r4, #0] +10000876: b163 cbz r3, 10000892 +10000878: f7ff fe12 bl 100004a0 +1000087c: 4601 mov r1, r0 +1000087e: 4620 mov r0, r4 +10000880: f7ff ffec bl 1000085c +10000884: 80a6 strh r6, [r4, #4] +10000886: f3bf 8f5f dmb sy +1000088a: 3408 adds r4, #8 +1000088c: 42ac cmp r4, r5 +1000088e: d3f1 bcc.n 10000874 +10000890: bd70 pop {r4, r5, r6, pc} +10000892: f7ff fe05 bl 100004a0 +10000896: 4601 mov r1, r0 +10000898: 4620 mov r0, r4 +1000089a: f7ff ffdf bl 1000085c +1000089e: 7126 strb r6, [r4, #4] +100008a0: f3bf 8f5f dmb sy +100008a4: 3408 adds r4, #8 +100008a6: 42ac cmp r4, r5 +100008a8: d3e4 bcc.n 10000874 +100008aa: bd70 pop {r4, r5, r6, pc} +100008ac: 20000b80 .word 0x20000b80 +100008b0: 20000b88 .word 0x20000b88 + +100008b4 : +100008b4: 4b0d ldr r3, [pc, #52] @ (100008ec ) +100008b6: 681a ldr r2, [r3, #0] +100008b8: f3ef 8110 mrs r1, PRIMASK +100008bc: b672 cpsid i +100008be: e8d2 cfcf ldaexb ip, [r2] +100008c2: 2001 movs r0, #1 +100008c4: f1bc 0f00 cmp.w ip, #0 +100008c8: d1f9 bne.n 100008be +100008ca: e8c2 0f4c strexb ip, r0, [r2] +100008ce: f1bc 0f00 cmp.w ip, #0 +100008d2: d1f4 bne.n 100008be +100008d4: f3bf 8f5f dmb sy +100008d8: 2200 movs r2, #0 +100008da: 681b ldr r3, [r3, #0] +100008dc: e8c3 2f8f stlb r2, [r3] +100008e0: f381 8810 msr PRIMASK, r1 +100008e4: bf40 sev +100008e6: 2000 movs r0, #0 +100008e8: 2100 movs r1, #0 +100008ea: 4770 bx lr +100008ec: 20003150 .word 0x20003150 + +100008f0 : +100008f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100008f4: ed2d 8b02 vpush {d8} +100008f8: b085 sub sp, #20 +100008fa: f3ef 8305 mrs r3, IPSR +100008fe: b2db uxtb r3, r3 +10000900: 3b10 subs r3, #16 +10000902: 089a lsrs r2, r3, #2 +10000904: bf18 it ne +10000906: 2201 movne r2, #1 +10000908: f04f 0101 mov.w r1, #1 +1000090c: f003 0b03 and.w fp, r3, #3 +10000910: bf18 it ne +10000912: 4daf ldrne r5, [pc, #700] @ (10000bd0 ) +10000914: 4baf ldr r3, [pc, #700] @ (10000bd4 ) +10000916: bf08 it eq +10000918: 4daf ldreq r5, [pc, #700] @ (10000bd8 ) +1000091a: eb0b 0282 add.w r2, fp, r2, lsl #2 +1000091e: f853 6022 ldr.w r6, [r3, r2, lsl #2] +10000922: fa01 f20b lsl.w r2, r1, fp +10000926: f505 5341 add.w r3, r5, #12352 @ 0x3040 +1000092a: ed9f 8ba7 vldr d8, [pc, #668] @ 10000bc8 +1000092e: 9201 str r2, [sp, #4] +10000930: 605a str r2, [r3, #4] +10000932: e02f b.n 10000994 +10000934: 88b3 ldrh r3, [r6, #4] +10000936: 041c lsls r4, r3, #16 +10000938: f140 8093 bpl.w 10000a62 +1000093c: 79b3 ldrb r3, [r6, #6] +1000093e: 2b00 cmp r3, #0 +10000940: f040 80dd bne.w 10000afe +10000944: f9b6 2008 ldrsh.w r2, [r6, #8] +10000948: 2a00 cmp r2, #0 +1000094a: f2c0 811e blt.w 10000b8a +1000094e: 6973 ldr r3, [r6, #20] +10000950: eb02 0242 add.w r2, r2, r2, lsl #1 +10000954: eb03 03c2 add.w r3, r3, r2, lsl #3 +10000958: e9d3 4702 ldrd r4, r7, [r3, #8] +1000095c: f1b7 3fff cmp.w r7, #4294967295 @ 0xffffffff +10000960: bf08 it eq +10000962: f1b4 3fff cmpeq.w r4, #4294967295 @ 0xffffffff +10000966: d00e beq.n 10000986 +10000968: eb05 018b add.w r1, r5, fp, lsl #2 +1000096c: 6aab ldr r3, [r5, #40] @ 0x28 +1000096e: 690a ldr r2, [r1, #16] +10000970: 1ad2 subs r2, r2, r3 +10000972: 1ae3 subs r3, r4, r3 +10000974: 4293 cmp r3, r2 +10000976: d305 bcc.n 10000984 +10000978: 2301 movs r3, #1 +1000097a: 6a2a ldr r2, [r5, #32] +1000097c: fa03 f30b lsl.w r3, r3, fp +10000980: 4213 tst r3, r2 +10000982: d100 bne.n 10000986 +10000984: 610c str r4, [r1, #16] +10000986: 4628 mov r0, r5 +10000988: f000 fb38 bl 10000ffc +1000098c: 42a0 cmp r0, r4 +1000098e: 41b9 sbcs r1, r7 +10000990: f2c0 80fb blt.w 10000b8a +10000994: f9b6 3008 ldrsh.w r3, [r6, #8] +10000998: 9a01 ldr r2, [sp, #4] +1000099a: 2b00 cmp r3, #0 +1000099c: 9300 str r3, [sp, #0] +1000099e: 63ea str r2, [r5, #60] @ 0x3c +100009a0: dbc8 blt.n 10000934 +100009a2: f8d6 8014 ldr.w r8, [r6, #20] +100009a6: eb03 0943 add.w r9, r3, r3, lsl #1 +100009aa: 4628 mov r0, r5 +100009ac: eb08 07c9 add.w r7, r8, r9, lsl #3 +100009b0: e9d7 4a02 ldrd r4, sl, [r7, #8] +100009b4: f000 fb22 bl 10000ffc +100009b8: 42a0 cmp r0, r4 +100009ba: eb71 010a sbcs.w r1, r1, sl +100009be: dbb9 blt.n 10000934 +100009c0: f1ba 0f00 cmp.w sl, #0 +100009c4: f2c0 80c3 blt.w 10000b4e +100009c8: e9d7 3104 ldrd r3, r1, [r7, #16] +100009cc: 4a83 ldr r2, [pc, #524] @ (10000bdc ) +100009ce: 4293 cmp r3, r2 +100009d0: f000 80ed beq.w 10000bae +100009d4: 887a ldrh r2, [r7, #2] +100009d6: f9b6 0008 ldrsh.w r0, [r6, #8] +100009da: b292 uxth r2, r2 +100009dc: ea42 4000 orr.w r0, r2, r0, lsl #16 +100009e0: 4798 blx r3 +100009e2: 4602 mov r2, r0 +100009e4: 460b mov r3, r1 +100009e6: ea52 0103 orrs.w r1, r2, r3 +100009ea: f000 80b0 beq.w 10000b4e +100009ee: 2b00 cmp r3, #0 +100009f0: f280 80d1 bge.w 10000b96 +100009f4: ebb4 0e02 subs.w lr, r4, r2 +100009f8: eb6a 0a03 sbc.w sl, sl, r3 +100009fc: f938 3039 ldrsh.w r3, [r8, r9, lsl #3] +10000a00: e9c7 ea02 strd lr, sl, [r7, #8] +10000a04: 2b00 cmp r3, #0 +10000a06: db95 blt.n 10000934 +10000a08: 6971 ldr r1, [r6, #20] +10000a0a: eb03 0243 add.w r2, r3, r3, lsl #1 +10000a0e: eb01 02c2 add.w r2, r1, r2, lsl #3 +10000a12: e9d2 7002 ldrd r7, r0, [r2, #8] +10000a16: 45be cmp lr, r7 +10000a18: eb7a 0c00 sbcs.w ip, sl, r0 +10000a1c: ea4f 0243 mov.w r2, r3, lsl #1 +10000a20: db88 blt.n 10000934 +10000a22: 46b4 mov ip, r6 +10000a24: f82c 3f08 strh.w r3, [ip, #8]! +10000a28: e006 b.n 10000a38 +10000a2a: eb03 0043 add.w r0, r3, r3, lsl #1 +10000a2e: eb01 00c0 add.w r0, r1, r0, lsl #3 +10000a32: 005a lsls r2, r3, #1 +10000a34: e9d0 7002 ldrd r7, r0, [r0, #8] +10000a38: 45be cmp lr, r7 +10000a3a: 441a add r2, r3 +10000a3c: eb7a 0000 sbcs.w r0, sl, r0 +10000a40: eb01 04c2 add.w r4, r1, r2, lsl #3 +10000a44: db04 blt.n 10000a50 +10000a46: f931 3032 ldrsh.w r3, [r1, r2, lsl #3] +10000a4a: 46a4 mov ip, r4 +10000a4c: 2b00 cmp r3, #0 +10000a4e: daec bge.n 10000a2a +10000a50: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000a54: 9b00 ldr r3, [sp, #0] +10000a56: f8ac 3000 strh.w r3, [ip] +10000a5a: 88b3 ldrh r3, [r6, #4] +10000a5c: 041c lsls r4, r3, #16 +10000a5e: f53f af6d bmi.w 1000093c +10000a62: 6933 ldr r3, [r6, #16] +10000a64: f3ef 8210 mrs r2, PRIMASK +10000a68: b672 cpsid i +10000a6a: e8d3 0fcf ldaexb r0, [r3] +10000a6e: 2101 movs r1, #1 +10000a70: 2800 cmp r0, #0 +10000a72: d1fa bne.n 10000a6a +10000a74: e8c3 1f40 strexb r0, r1, [r3] +10000a78: 2800 cmp r0, #0 +10000a7a: d1f6 bne.n 10000a6a +10000a7c: f3bf 8f5f dmb sy +10000a80: f64f 74ff movw r4, #65535 @ 0xffff +10000a84: 88b0 ldrh r0, [r6, #4] +10000a86: 2300 movs r3, #0 +10000a88: 6931 ldr r1, [r6, #16] +10000a8a: b200 sxth r0, r0 +10000a8c: 80b4 strh r4, [r6, #4] +10000a8e: e8c1 3f8f stlb r3, [r1] +10000a92: f382 8810 msr PRIMASK, r2 +10000a96: 4298 cmp r0, r3 +10000a98: f6ff af50 blt.w 1000093c +10000a9c: 4607 mov r7, r0 +10000a9e: 46a9 mov r9, r5 +10000aa0: 6974 ldr r4, [r6, #20] +10000aa2: f106 0808 add.w r8, r6, #8 +10000aa6: eb07 0e47 add.w lr, r7, r7, lsl #1 +10000aaa: eb04 03ce add.w r3, r4, lr, lsl #3 +10000aae: e9d3 5002 ldrd r5, r0, [r3, #8] +10000ab2: f9b6 3008 ldrsh.w r3, [r6, #8] +10000ab6: 46c4 mov ip, r8 +10000ab8: 2b00 cmp r3, #0 +10000aba: db13 blt.n 10000ae4 +10000abc: 46b2 mov sl, r6 +10000abe: 9700 str r7, [sp, #0] +10000ac0: e004 b.n 10000acc +10000ac2: f934 3036 ldrsh.w r3, [r4, r6, lsl #3] +10000ac6: 4694 mov ip, r2 +10000ac8: 2b00 cmp r3, #0 +10000aca: db09 blt.n 10000ae0 +10000acc: eb03 0643 add.w r6, r3, r3, lsl #1 +10000ad0: eb04 02c6 add.w r2, r4, r6, lsl #3 +10000ad4: e9d2 7102 ldrd r7, r1, [r2, #8] +10000ad8: 42bd cmp r5, r7 +10000ada: eb70 0101 sbcs.w r1, r0, r1 +10000ade: daf0 bge.n 10000ac2 +10000ae0: 4656 mov r6, sl +10000ae2: 9f00 ldr r7, [sp, #0] +10000ae4: f8ac 7000 strh.w r7, [ip] +10000ae8: f934 703e ldrsh.w r7, [r4, lr, lsl #3] +10000aec: f824 303e strh.w r3, [r4, lr, lsl #3] +10000af0: 2f00 cmp r7, #0 +10000af2: dad8 bge.n 10000aa6 +10000af4: 79b3 ldrb r3, [r6, #6] +10000af6: 464d mov r5, r9 +10000af8: 2b00 cmp r3, #0 +10000afa: f43f af23 beq.w 10000944 +10000afe: 2300 movs r3, #0 +10000b00: 71b3 strb r3, [r6, #6] +10000b02: f9b6 3008 ldrsh.w r3, [r6, #8] +10000b06: f106 0808 add.w r8, r6, #8 +10000b0a: 1c58 adds r0, r3, #1 +10000b0c: d03d beq.n 10000b8a +10000b0e: 461a mov r2, r3 +10000b10: 6977 ldr r7, [r6, #20] +10000b12: e003 b.n 10000b1c +10000b14: 4680 mov r8, r0 +10000b16: 1c59 adds r1, r3, #1 +10000b18: f43f af16 beq.w 10000948 +10000b1c: eb03 0143 add.w r1, r3, r3, lsl #1 +10000b20: eb07 00c1 add.w r0, r7, r1, lsl #3 +10000b24: f8b0 c002 ldrh.w ip, [r0, #2] +10000b28: 461c mov r4, r3 +10000b2a: f41c 4f00 tst.w ip, #32768 @ 0x8000 +10000b2e: 469e mov lr, r3 +10000b30: f937 3031 ldrsh.w r3, [r7, r1, lsl #3] +10000b34: d0ee beq.n 10000b14 +10000b36: 4294 cmp r4, r2 +10000b38: ed80 8b02 vstr d8, [r0, #8] +10000b3c: d005 beq.n 10000b4a +10000b3e: f8a8 3000 strh.w r3, [r8] +10000b42: 8932 ldrh r2, [r6, #8] +10000b44: f827 2031 strh.w r2, [r7, r1, lsl #3] +10000b48: 8134 strh r4, [r6, #8] +10000b4a: 4672 mov r2, lr +10000b4c: e7e3 b.n 10000b16 +10000b4e: f838 3039 ldrh.w r3, [r8, r9, lsl #3] +10000b52: 8133 strh r3, [r6, #8] +10000b54: 6933 ldr r3, [r6, #16] +10000b56: f3ef 8210 mrs r2, PRIMASK +10000b5a: b672 cpsid i +10000b5c: e8d3 0fcf ldaexb r0, [r3] +10000b60: 2101 movs r1, #1 +10000b62: 2800 cmp r0, #0 +10000b64: d1fa bne.n 10000b5c +10000b66: e8c3 1f40 strexb r0, r1, [r3] +10000b6a: 2800 cmp r0, #0 +10000b6c: d1f6 bne.n 10000b5c +10000b6e: f3bf 8f5f dmb sy +10000b72: 8873 ldrh r3, [r6, #2] +10000b74: 6931 ldr r1, [r6, #16] +10000b76: f828 3039 strh.w r3, [r8, r9, lsl #3] +10000b7a: 9b00 ldr r3, [sp, #0] +10000b7c: 8073 strh r3, [r6, #2] +10000b7e: 2300 movs r3, #0 +10000b80: e8c1 3f8f stlb r3, [r1] +10000b84: f382 8810 msr PRIMASK, r2 +10000b88: e6d4 b.n 10000934 +10000b8a: bf40 sev +10000b8c: b005 add sp, #20 +10000b8e: ecbd 8b02 vpop {d8} +10000b92: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10000b96: 4628 mov r0, r5 +10000b98: e9cd 2302 strd r2, r3, [sp, #8] +10000b9c: f000 fa2e bl 10000ffc +10000ba0: 9a02 ldr r2, [sp, #8] +10000ba2: 9b03 ldr r3, [sp, #12] +10000ba4: eb10 0e02 adds.w lr, r0, r2 +10000ba8: eb43 0a01 adc.w sl, r3, r1 +10000bac: e726 b.n 100009fc +10000bae: 4608 mov r0, r1 +10000bb0: 690b ldr r3, [r1, #16] +10000bb2: 9102 str r1, [sp, #8] +10000bb4: 4798 blx r3 +10000bb6: 2800 cmp r0, #0 +10000bb8: d0c9 beq.n 10000b4e +10000bba: 9902 ldr r1, [sp, #8] +10000bbc: e9d1 2300 ldrd r2, r3, [r1] +10000bc0: e711 b.n 100009e6 +10000bc2: bf00 nop +10000bc4: f3af 8000 nop.w +10000bc8: ffffffff .word 0xffffffff +10000bcc: ffffffff .word 0xffffffff +10000bd0: 400b8000 .word 0x400b8000 +10000bd4: 20003128 .word 0x20003128 +10000bd8: 400b0000 .word 0x400b0000 +10000bdc: 100008f1 .word 0x100008f1 + +10000be0 : +10000be0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000be4: 4c36 ldr r4, [pc, #216] @ (10000cc0 ) +10000be6: 6925 ldr r5, [r4, #16] +10000be8: b12d cbz r5, 10000bf6 +10000bea: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000bee: 210a movs r1, #10 +10000bf0: 4834 ldr r0, [pc, #208] @ (10000cc4 ) +10000bf2: f7ff be33 b.w 1000085c +10000bf6: f8df 80e4 ldr.w r8, [pc, #228] @ 10000cdc +10000bfa: 2103 movs r1, #3 +10000bfc: 4640 mov r0, r8 +10000bfe: f000 f9eb bl 10000fd8 +10000c02: 2603 movs r6, #3 +10000c04: f8c4 800c str.w r8, [r4, #12] +10000c08: f7ff fc4a bl 100004a0 +10000c0c: f04f 4c50 mov.w ip, #3489660928 @ 0xd0000000 +10000c10: 4b2d ldr r3, [pc, #180] @ (10000cc8 ) +10000c12: 7026 strb r6, [r4, #0] +10000c14: 4403 add r3, r0 +10000c16: 6123 str r3, [r4, #16] +10000c18: f8dc 3000 ldr.w r3, [ip] +10000c1c: 210f movs r1, #15 +10000c1e: 7063 strb r3, [r4, #1] +10000c20: 6963 ldr r3, [r4, #20] +10000c22: 8061 strh r1, [r4, #2] +10000c24: 831d strh r5, [r3, #24] +10000c26: f04f 0504 mov.w r5, #4 +10000c2a: f8a3 5078 strh.w r5, [r3, #120] @ 0x78 +10000c2e: f04f 0505 mov.w r5, #5 +10000c32: f8a3 5090 strh.w r5, [r3, #144] @ 0x90 +10000c36: f04f 0506 mov.w r5, #6 +10000c3a: f8a3 50a8 strh.w r5, [r3, #168] @ 0xa8 +10000c3e: f04f 0507 mov.w r5, #7 +10000c42: 210e movs r1, #14 +10000c44: f64f 72ff movw r2, #65535 @ 0xffff +10000c48: 2708 movs r7, #8 +10000c4a: f04f 0e0a mov.w lr, #10 +10000c4e: f8a3 50c0 strh.w r5, [r3, #192] @ 0xc0 +10000c52: f04f 0901 mov.w r9, #1 +10000c56: f04f 0c0c mov.w ip, #12 +10000c5a: f04f 0b02 mov.w fp, #2 +10000c5e: f04f 0a09 mov.w sl, #9 +10000c62: 200d movs r0, #13 +10000c64: f04f 050b mov.w r5, #11 +10000c68: f8a3 1168 strh.w r1, [r3, #360] @ 0x168 +10000c6c: 4917 ldr r1, [pc, #92] @ (10000ccc ) +10000c6e: 80a2 strh r2, [r4, #4] +10000c70: f8a3 e108 strh.w lr, [r3, #264] @ 0x108 +10000c74: 60a1 str r1, [r4, #8] +10000c76: f8a3 b048 strh.w fp, [r3, #72] @ 0x48 +10000c7a: f8a3 a0f0 strh.w sl, [r3, #240] @ 0xf0 +10000c7e: f8a3 5120 strh.w r5, [r3, #288] @ 0x120 +10000c82: f8a3 c138 strh.w ip, [r3, #312] @ 0x138 +10000c86: f8a3 0150 strh.w r0, [r3, #336] @ 0x150 +10000c8a: f8a3 9030 strh.w r9, [r3, #48] @ 0x30 +10000c8e: f8a3 6060 strh.w r6, [r3, #96] @ 0x60 +10000c92: f8a3 70d8 strh.w r7, [r3, #216] @ 0xd8 +10000c96: 801a strh r2, [r3, #0] +10000c98: 4b0d ldr r3, [pc, #52] @ (10000cd0 ) +10000c9a: 4630 mov r0, r6 +10000c9c: f8c8 7020 str.w r7, [r8, #32] +10000ca0: 490c ldr r1, [pc, #48] @ (10000cd4 ) +10000ca2: 60dc str r4, [r3, #12] +10000ca4: f7ff fc52 bl 1000054c +10000ca8: 4649 mov r1, r9 +10000caa: 4630 mov r0, r6 +10000cac: f7ff fc38 bl 10000520 +10000cb0: 4b09 ldr r3, [pc, #36] @ (10000cd8 ) +10000cb2: 210a movs r1, #10 +10000cb4: 641f str r7, [r3, #64] @ 0x40 +10000cb6: 4803 ldr r0, [pc, #12] @ (10000cc4 ) +10000cb8: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} +10000cbc: f7ff bdce b.w 1000085c +10000cc0: 200005f4 .word 0x200005f4 +10000cc4: 20003150 .word 0x20003150 +10000cc8: 200030a0 .word 0x200030a0 +10000ccc: 0010ffff .word 0x0010ffff +10000cd0: 20003128 .word 0x20003128 +10000cd4: 100008f1 .word 0x100008f1 +10000cd8: 400b2000 .word 0x400b2000 +10000cdc: 400b0000 .word 0x400b0000 + +10000ce0 : +10000ce0: 4601 mov r1, r0 +10000ce2: b5f0 push {r4, r5, r6, r7, lr} +10000ce4: 6900 ldr r0, [r0, #16] +10000ce6: f3ef 8710 mrs r7, PRIMASK +10000cea: b672 cpsid i +10000cec: e8d0 5fcf ldaexb r5, [r0] +10000cf0: 2401 movs r4, #1 +10000cf2: 2d00 cmp r5, #0 +10000cf4: d1fa bne.n 10000cec +10000cf6: e8c0 4f45 strexb r5, r4, [r0] +10000cfa: 2d00 cmp r5, #0 +10000cfc: d1f6 bne.n 10000cec +10000cfe: f3bf 8f5f dmb sy +10000d02: f9b1 e002 ldrsh.w lr, [r1, #2] +10000d06: 694c ldr r4, [r1, #20] +10000d08: eb0e 0c4e add.w ip, lr, lr, lsl #1 +10000d0c: f1be 0f00 cmp.w lr, #0 +10000d10: ea4f 05cc mov.w r5, ip, lsl #3 +10000d14: 6908 ldr r0, [r1, #16] +10000d16: eb04 0ccc add.w ip, r4, ip, lsl #3 +10000d1a: db3c blt.n 10000d96 +10000d1c: 5b66 ldrh r6, [r4, r5] +10000d1e: 804e strh r6, [r1, #2] +10000d20: 2600 movs r6, #0 +10000d22: e8c0 6f8f stlb r6, [r0] +10000d26: f387 8810 msr PRIMASK, r7 +10000d2a: f8bc 0002 ldrh.w r0, [ip, #2] +10000d2e: e9cc 2302 strd r2, r3, [ip, #8] +10000d32: 3001 adds r0, #1 +10000d34: f3c0 000e ubfx r0, r0, #0, #15 +10000d38: 2801 cmp r0, #1 +10000d3a: bf38 it cc +10000d3c: 2001 movcc r0, #1 +10000d3e: 9b05 ldr r3, [sp, #20] +10000d40: f8ac 0002 strh.w r0, [ip, #2] +10000d44: f8cc 3010 str.w r3, [ip, #16] +10000d48: 9b06 ldr r3, [sp, #24] +10000d4a: ea40 400e orr.w r0, r0, lr, lsl #16 +10000d4e: f8cc 3014 str.w r3, [ip, #20] +10000d52: 690b ldr r3, [r1, #16] +10000d54: f3ef 8210 mrs r2, PRIMASK +10000d58: b672 cpsid i +10000d5a: e8d3 cfcf ldaexb ip, [r3] +10000d5e: 2701 movs r7, #1 +10000d60: f1bc 0f00 cmp.w ip, #0 +10000d64: d1f9 bne.n 10000d5a +10000d66: e8c3 7f4c strexb ip, r7, [r3] +10000d6a: f1bc 0f00 cmp.w ip, #0 +10000d6e: d1f4 bne.n 10000d5a +10000d70: f3bf 8f5f dmb sy +10000d74: 888b ldrh r3, [r1, #4] +10000d76: 5363 strh r3, [r4, r5] +10000d78: f8a1 e004 strh.w lr, [r1, #4] +10000d7c: 690b ldr r3, [r1, #16] +10000d7e: e8c3 6f8f stlb r6, [r3] +10000d82: f382 8810 msr PRIMASK, r2 +10000d86: 2201 movs r2, #1 +10000d88: 68cb ldr r3, [r1, #12] +10000d8a: 7809 ldrb r1, [r1, #0] +10000d8c: f503 5301 add.w r3, r3, #8256 @ 0x2040 +10000d90: 408a lsls r2, r1 +10000d92: 605a str r2, [r3, #4] +10000d94: bdf0 pop {r4, r5, r6, r7, pc} +10000d96: 2300 movs r3, #0 +10000d98: e8c0 3f8f stlb r3, [r0] +10000d9c: f387 8810 msr PRIMASK, r7 +10000da0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000da4: bdf0 pop {r4, r5, r6, r7, pc} +10000da6: bf00 nop + +10000da8 : +10000da8: 4603 mov r3, r0 +10000daa: 8940 ldrh r0, [r0, #10] +10000dac: ebb0 4f21 cmp.w r0, r1, asr #16 +10000db0: dd37 ble.n 10000e22 +10000db2: 6958 ldr r0, [r3, #20] +10000db4: 140a asrs r2, r1, #16 +10000db6: eb02 0242 add.w r2, r2, r2, lsl #1 +10000dba: b510 push {r4, lr} +10000dbc: eb00 00c2 add.w r0, r0, r2, lsl #3 +10000dc0: 691c ldr r4, [r3, #16] +10000dc2: f3ef 8c10 mrs ip, PRIMASK +10000dc6: b672 cpsid i +10000dc8: e8d4 efcf ldaexb lr, [r4] +10000dcc: 2201 movs r2, #1 +10000dce: f1be 0f00 cmp.w lr, #0 +10000dd2: d1f9 bne.n 10000dc8 +10000dd4: e8c4 2f4e strexb lr, r2, [r4] +10000dd8: f1be 0f00 cmp.w lr, #0 +10000ddc: d1f4 bne.n 10000dc8 +10000dde: f3bf 8f5f dmb sy +10000de2: 8842 ldrh r2, [r0, #2] +10000de4: b289 uxth r1, r1 +10000de6: b292 uxth r2, r2 +10000de8: 428a cmp r2, r1 +10000dea: d007 beq.n 10000dfc +10000dec: 2200 movs r2, #0 +10000dee: 691b ldr r3, [r3, #16] +10000df0: e8c3 2f8f stlb r2, [r3] +10000df4: f38c 8810 msr PRIMASK, ip +10000df8: 2000 movs r0, #0 +10000dfa: bd10 pop {r4, pc} +10000dfc: f442 4200 orr.w r2, r2, #32768 @ 0x8000 +10000e00: 8042 strh r2, [r0, #2] +10000e02: 2101 movs r1, #1 +10000e04: 2200 movs r2, #0 +10000e06: 6918 ldr r0, [r3, #16] +10000e08: 7199 strb r1, [r3, #6] +10000e0a: e8c0 2f8f stlb r2, [r0] +10000e0e: f38c 8810 msr PRIMASK, ip +10000e12: 781c ldrb r4, [r3, #0] +10000e14: 68da ldr r2, [r3, #12] +10000e16: 4608 mov r0, r1 +10000e18: f502 5301 add.w r3, r2, #8256 @ 0x2040 +10000e1c: 40a1 lsls r1, r4 +10000e1e: 6059 str r1, [r3, #4] +10000e20: bd10 pop {r4, pc} +10000e22: 2000 movs r0, #0 +10000e24: 4770 bx lr +10000e26: bf00 nop + +10000e28 : +10000e28: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10000e2c: b082 sub sp, #8 +10000e2e: 4606 mov r6, r0 +10000e30: f000 f8ec bl 1000100c +10000e34: f44f 737a mov.w r3, #1000 @ 0x3e8 +10000e38: 4604 mov r4, r0 +10000e3a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10000e3e: f06f 4200 mvn.w r2, #2147483648 @ 0x80000000 +10000e42: fbe6 4103 umlal r4, r1, r6, r3 +10000e46: 42a0 cmp r0, r4 +10000e48: eb72 0301 sbcs.w r3, r2, r1 +10000e4c: bf3a itte cc +10000e4e: 4604 movcc r4, r0 +10000e50: 4615 movcc r5, r2 +10000e52: 460d movcs r5, r1 +10000e54: 1fa6 subs r6, r4, #6 +10000e56: f145 37ff adc.w r7, r5, #4294967295 @ 0xffffffff +10000e5a: 42b4 cmp r4, r6 +10000e5c: eb75 0307 sbcs.w r3, r5, r7 +10000e60: bf3c itt cc +10000e62: 2600 movcc r6, #0 +10000e64: 4637 movcc r7, r6 +10000e66: f000 f8d1 bl 1000100c +10000e6a: 1a30 subs r0, r6, r0 +10000e6c: eb67 0101 sbc.w r1, r7, r1 +10000e70: 2801 cmp r0, #1 +10000e72: f171 0100 sbcs.w r1, r1, #0 +10000e76: da06 bge.n 10000e86 +10000e78: 4620 mov r0, r4 +10000e7a: 4629 mov r1, r5 +10000e7c: b002 add sp, #8 +10000e7e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +10000e82: f000 b8fb b.w 1000107c +10000e86: f000 f8c1 bl 1000100c +10000e8a: 4286 cmp r6, r0 +10000e8c: eb67 0101 sbc.w r1, r7, r1 +10000e90: 2900 cmp r1, #0 +10000e92: db0a blt.n 10000eaa +10000e94: 2100 movs r1, #0 +10000e96: 4b17 ldr r3, [pc, #92] @ (10000ef4 ) +10000e98: 4632 mov r2, r6 +10000e9a: 9300 str r3, [sp, #0] +10000e9c: 4816 ldr r0, [pc, #88] @ (10000ef8 ) +10000e9e: 463b mov r3, r7 +10000ea0: 9101 str r1, [sp, #4] +10000ea2: f7ff ff1d bl 10000ce0 +10000ea6: 3001 adds r0, #1 +10000ea8: d0e6 beq.n 10000e78 +10000eaa: f04f 0c00 mov.w ip, #0 +10000eae: 4a13 ldr r2, [pc, #76] @ (10000efc ) +10000eb0: 4913 ldr r1, [pc, #76] @ (10000f00 ) +10000eb2: 6a53 ldr r3, [r2, #36] @ 0x24 +10000eb4: 429f cmp r7, r3 +10000eb6: d804 bhi.n 10000ec2 +10000eb8: 6a90 ldr r0, [r2, #40] @ 0x28 +10000eba: 42b0 cmp r0, r6 +10000ebc: d2dc bcs.n 10000e78 +10000ebe: 429f cmp r7, r3 +10000ec0: d1da bne.n 10000e78 +10000ec2: 680b ldr r3, [r1, #0] +10000ec4: f3ef 8010 mrs r0, PRIMASK +10000ec8: b672 cpsid i +10000eca: e8d3 8fcf ldaexb r8, [r3] +10000ece: f05f 0e01 movs.w lr, #1 +10000ed2: f1b8 0f00 cmp.w r8, #0 +10000ed6: d1f8 bne.n 10000eca +10000ed8: e8c3 ef48 strexb r8, lr, [r3] +10000edc: f1b8 0f00 cmp.w r8, #0 +10000ee0: d1f3 bne.n 10000eca +10000ee2: f3bf 8f5f dmb sy +10000ee6: 680b ldr r3, [r1, #0] +10000ee8: e8c3 cf8f stlb ip, [r3] +10000eec: f380 8810 msr PRIMASK, r0 +10000ef0: bf20 wfe +10000ef2: e7de b.n 10000eb2 +10000ef4: 100008b5 .word 0x100008b5 +10000ef8: 200005f4 .word 0x200005f4 +10000efc: 400b0000 .word 0x400b0000 +10000f00: 20003150 .word 0x20003150 + +10000f04 : +10000f04: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +10000f08: 4606 mov r6, r0 +10000f0a: 460d mov r5, r1 +10000f0c: b083 sub sp, #12 +10000f0e: f3ef 8405 mrs r4, IPSR +10000f12: b2e4 uxtb r4, r4 +10000f14: b13c cbz r4, 10000f26 +10000f16: 4b2d ldr r3, [pc, #180] @ (10000fcc ) +10000f18: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f1a: 42aa cmp r2, r5 +10000f1c: d21c bcs.n 10000f58 +10000f1e: 2000 movs r0, #0 +10000f20: b003 add sp, #12 +10000f22: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000f26: 4f2a ldr r7, [pc, #168] @ (10000fd0 ) +10000f28: f8d7 900c ldr.w r9, [r7, #12] +10000f2c: f897 8000 ldrb.w r8, [r7] +10000f30: 4648 mov r0, r9 +10000f32: f000 f863 bl 10000ffc +10000f36: f108 0804 add.w r8, r8, #4 +10000f3a: f859 3028 ldr.w r3, [r9, r8, lsl #2] +10000f3e: 1a1b subs r3, r3, r0 +10000f40: 1a30 subs r0, r6, r0 +10000f42: eb65 0101 sbc.w r1, r5, r1 +10000f46: 4298 cmp r0, r3 +10000f48: f171 0100 sbcs.w r1, r1, #0 +10000f4c: db10 blt.n 10000f70 +10000f4e: bf20 wfe +10000f50: 4b1e ldr r3, [pc, #120] @ (10000fcc ) +10000f52: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f54: 42aa cmp r2, r5 +10000f56: d3e2 bcc.n 10000f1e +10000f58: bf14 ite ne +10000f5a: 2401 movne r4, #1 +10000f5c: 2400 moveq r4, #0 +10000f5e: 6a9b ldr r3, [r3, #40] @ 0x28 +10000f60: 42b3 cmp r3, r6 +10000f62: bf34 ite cc +10000f64: 4620 movcc r0, r4 +10000f66: f044 0001 orrcs.w r0, r4, #1 +10000f6a: b003 add sp, #12 +10000f6c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +10000f70: f000 f84c bl 1000100c +10000f74: 4286 cmp r6, r0 +10000f76: eb65 0101 sbc.w r1, r5, r1 +10000f7a: 2900 cmp r1, #0 +10000f7c: db14 blt.n 10000fa8 +10000f7e: 4b15 ldr r3, [pc, #84] @ (10000fd4 ) +10000f80: 4638 mov r0, r7 +10000f82: e9cd 3400 strd r3, r4, [sp] +10000f86: 4632 mov r2, r6 +10000f88: 462b mov r3, r5 +10000f8a: f7ff fea9 bl 10000ce0 +10000f8e: 1e01 subs r1, r0, #0 +10000f90: dd0a ble.n 10000fa8 +10000f92: 4b0e ldr r3, [pc, #56] @ (10000fcc ) +10000f94: 6a5a ldr r2, [r3, #36] @ 0x24 +10000f96: 42aa cmp r2, r5 +10000f98: d316 bcc.n 10000fc8 +10000f9a: 6a9b ldr r3, [r3, #40] @ 0x28 +10000f9c: 42b3 cmp r3, r6 +10000f9e: d311 bcc.n 10000fc4 +10000fa0: 480b ldr r0, [pc, #44] @ (10000fd0 ) +10000fa2: f7ff ff01 bl 10000da8 +10000fa6: e7b6 b.n 10000f16 +10000fa8: 4b08 ldr r3, [pc, #32] @ (10000fcc ) +10000faa: 6a5c ldr r4, [r3, #36] @ 0x24 +10000fac: 42ac cmp r4, r5 +10000fae: d3b6 bcc.n 10000f1e +10000fb0: 1b64 subs r4, r4, r5 +10000fb2: bf18 it ne +10000fb4: 2401 movne r4, #1 +10000fb6: 6a9b ldr r3, [r3, #40] @ 0x28 +10000fb8: 42b3 cmp r3, r6 +10000fba: bf34 ite cc +10000fbc: 4620 movcc r0, r4 +10000fbe: f044 0001 orrcs.w r0, r4, #1 +10000fc2: e7ad b.n 10000f20 +10000fc4: 42aa cmp r2, r5 +10000fc6: d1eb bne.n 10000fa0 +10000fc8: bf20 wfe +10000fca: e7e9 b.n 10000fa0 +10000fcc: 400b0000 .word 0x400b0000 +10000fd0: 200005f4 .word 0x200005f4 +10000fd4: 100008b5 .word 0x100008b5 + +10000fd8 : +10000fd8: b410 push {r4} +10000fda: 4b05 ldr r3, [pc, #20] @ (10000ff0 ) +10000fdc: 4c05 ldr r4, [pc, #20] @ (10000ff4 ) +10000fde: 4a06 ldr r2, [pc, #24] @ (10000ff8 ) +10000fe0: 42a0 cmp r0, r4 +10000fe2: bf14 ite ne +10000fe4: 4618 movne r0, r3 +10000fe6: 1c58 addeq r0, r3, #1 +10000fe8: f85d 4b04 ldr.w r4, [sp], #4 +10000fec: f7ff ba2c b.w 10000448 +10000ff0: 200030cc .word 0x200030cc +10000ff4: 400b8000 .word 0x400b8000 +10000ff8: 10005f50 .word 0x10005f50 + +10000ffc : +10000ffc: 4603 mov r3, r0 +10000ffe: 6a41 ldr r1, [r0, #36] @ 0x24 +10001000: 460a mov r2, r1 +10001002: 6a98 ldr r0, [r3, #40] @ 0x28 +10001004: 6a59 ldr r1, [r3, #36] @ 0x24 +10001006: 428a cmp r2, r1 +10001008: d1fa bne.n 10001000 +1000100a: 4770 bx lr + +1000100c : +1000100c: 4b03 ldr r3, [pc, #12] @ (1000101c ) +1000100e: 6a59 ldr r1, [r3, #36] @ 0x24 +10001010: 460a mov r2, r1 +10001012: 6a98 ldr r0, [r3, #40] @ 0x28 +10001014: 6a59 ldr r1, [r3, #36] @ 0x24 +10001016: 4291 cmp r1, r2 +10001018: d1fa bne.n 10001010 +1000101a: 4770 bx lr +1000101c: 400b0000 .word 0x400b0000 + +10001020 : +10001020: b430 push {r4, r5} +10001022: 4a15 ldr r2, [pc, #84] @ (10001078 ) +10001024: 6a53 ldr r3, [r2, #36] @ 0x24 +10001026: 469c mov ip, r3 +10001028: 6a94 ldr r4, [r2, #40] @ 0x28 +1000102a: 6a53 ldr r3, [r2, #36] @ 0x24 +1000102c: 4563 cmp r3, ip +1000102e: d1fa bne.n 10001026 +10001030: 1902 adds r2, r0, r4 +10001032: 4159 adcs r1, r3 +10001034: f04f 0500 mov.w r5, #0 +10001038: bf28 it cs +1000103a: 2501 movcs r5, #1 +1000103c: 4b0e ldr r3, [pc, #56] @ (10001078 ) +1000103e: 6a5b ldr r3, [r3, #36] @ 0x24 +10001040: b1b5 cbz r5, 10001070 +10001042: 1c5a adds r2, r3, #1 +10001044: bf08 it eq +10001046: 461a moveq r2, r3 +10001048: d008 beq.n 1000105c +1000104a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff +1000104e: 460a mov r2, r1 +10001050: 4809 ldr r0, [pc, #36] @ (10001078 ) +10001052: 6a43 ldr r3, [r0, #36] @ 0x24 +10001054: 428b cmp r3, r1 +10001056: d3fc bcc.n 10001052 +10001058: 428b cmp r3, r1 +1000105a: d107 bne.n 1000106c +1000105c: 4906 ldr r1, [pc, #24] @ (10001078 ) +1000105e: e002 b.n 10001066 +10001060: 6a48 ldr r0, [r1, #36] @ 0x24 +10001062: 4298 cmp r0, r3 +10001064: d102 bne.n 1000106c +10001066: 6a88 ldr r0, [r1, #40] @ 0x28 +10001068: 4290 cmp r0, r2 +1000106a: d3f9 bcc.n 10001060 +1000106c: bc30 pop {r4, r5} +1000106e: 4770 bx lr +10001070: 4299 cmp r1, r3 +10001072: d8ed bhi.n 10001050 +10001074: e7f0 b.n 10001058 +10001076: bf00 nop +10001078: 400b0000 .word 0x400b0000 + +1000107c : +1000107c: 4a07 ldr r2, [pc, #28] @ (1000109c ) +1000107e: 6a53 ldr r3, [r2, #36] @ 0x24 +10001080: 4299 cmp r1, r3 +10001082: d8fc bhi.n 1000107e +10001084: 4299 cmp r1, r3 +10001086: d107 bne.n 10001098 +10001088: 4b04 ldr r3, [pc, #16] @ (1000109c ) +1000108a: e002 b.n 10001092 +1000108c: 6a5a ldr r2, [r3, #36] @ 0x24 +1000108e: 4291 cmp r1, r2 +10001090: d102 bne.n 10001098 +10001092: 6a9a ldr r2, [r3, #40] @ 0x28 +10001094: 4290 cmp r0, r2 +10001096: d8f9 bhi.n 1000108c +10001098: 4770 bx lr +1000109a: bf00 nop +1000109c: 400b0000 .word 0x400b0000 + +100010a0 : +100010a0: b5f8 push {r3, r4, r5, r6, r7, lr} +100010a2: 4605 mov r5, r0 +100010a4: 2006 movs r0, #6 +100010a6: 460e mov r6, r1 +100010a8: f000 f8e4 bl 10001274 +100010ac: 2800 cmp r0, #0 +100010ae: d042 beq.n 10001136 +100010b0: 4a35 ldr r2, [pc, #212] @ (10001188 ) +100010b2: 4836 ldr r0, [pc, #216] @ (1000118c ) +100010b4: 4295 cmp r5, r2 +100010b6: bf14 ite ne +100010b8: f04f 6280 movne.w r2, #67108864 @ 0x4000000 +100010bc: f04f 6200 moveq.w r2, #134217728 @ 0x8000000 +100010c0: 4b33 ldr r3, [pc, #204] @ (10001190 ) +100010c2: 4934 ldr r1, [pc, #208] @ (10001194 ) +100010c4: 6002 str r2, [r0, #0] +100010c6: 601a str r2, [r3, #0] +100010c8: 688c ldr r4, [r1, #8] +100010ca: ea32 0404 bics.w r4, r2, r4 +100010ce: d1fb bne.n 100010c8 +100010d0: 4b2d ldr r3, [pc, #180] @ (10001188 ) +100010d2: f44f 7180 mov.w r1, #256 @ 0x100 +100010d6: 1aeb subs r3, r5, r3 +100010d8: fab3 f383 clz r3, r3 +100010dc: 4a2e ldr r2, [pc, #184] @ (10001198 ) +100010de: 095b lsrs r3, r3, #5 +100010e0: 2006 movs r0, #6 +100010e2: f822 1013 strh.w r1, [r2, r3, lsl #1] +100010e6: f000 f8c5 bl 10001274 +100010ea: 00c3 lsls r3, r0, #3 +100010ec: fbb3 f3f6 udiv r3, r3, r6 +100010f0: 3301 adds r3, #1 +100010f2: 09da lsrs r2, r3, #7 +100010f4: d120 bne.n 10001138 +100010f6: 2640 movs r6, #64 @ 0x40 +100010f8: 2101 movs r1, #1 +100010fa: 6269 str r1, [r5, #36] @ 0x24 +100010fc: 62aa str r2, [r5, #40] @ 0x28 +100010fe: 6b2f ldr r7, [r5, #48] @ 0x30 +10001100: 07fb lsls r3, r7, #31 +10001102: d422 bmi.n 1000114a +10001104: 462b mov r3, r5 +10001106: 2200 movs r2, #0 +10001108: f853 1f2c ldr.w r1, [r3, #44]! +1000110c: 2006 movs r0, #6 +1000110e: f503 5480 add.w r4, r3, #4096 @ 0x1000 +10001112: 6022 str r2, [r4, #0] +10001114: 632f str r7, [r5, #48] @ 0x30 +10001116: f000 f8ad bl 10001274 +1000111a: f240 3101 movw r1, #769 @ 0x301 +1000111e: 2203 movs r2, #3 +10001120: 0080 lsls r0, r0, #2 +10001122: fbb0 f0f6 udiv r0, r0, r6 +10001126: 6aeb ldr r3, [r5, #44] @ 0x2c +10001128: f083 0370 eor.w r3, r3, #112 @ 0x70 +1000112c: f003 037e and.w r3, r3, #126 @ 0x7e +10001130: 6023 str r3, [r4, #0] +10001132: 6329 str r1, [r5, #48] @ 0x30 +10001134: 64aa str r2, [r5, #72] @ 0x48 +10001136: bdf8 pop {r3, r4, r5, r6, r7, pc} +10001138: f64f 71fe movw r1, #65534 @ 0xfffe +1000113c: 428a cmp r2, r1 +1000113e: d91b bls.n 10001178 +10001140: 4622 mov r2, r4 +10001142: f64f 71ff movw r1, #65535 @ 0xffff +10001146: 4e15 ldr r6, [pc, #84] @ (1000119c ) +10001148: e7d7 b.n 100010fa +1000114a: f240 3201 movw r2, #769 @ 0x301 +1000114e: f505 5340 add.w r3, r5, #12288 @ 0x3000 +10001152: 631a str r2, [r3, #48] @ 0x30 +10001154: 6a6b ldr r3, [r5, #36] @ 0x24 +10001156: 6aac ldr r4, [r5, #40] @ 0x28 +10001158: 2006 movs r0, #6 +1000115a: eb04 1483 add.w r4, r4, r3, lsl #6 +1000115e: f000 f889 bl 10001274 +10001162: 4b0f ldr r3, [pc, #60] @ (100011a0 ) +10001164: 02a4 lsls r4, r4, #10 +10001166: fba3 2300 umull r2, r3, r3, r0 +1000116a: 0adb lsrs r3, r3, #11 +1000116c: 2100 movs r1, #0 +1000116e: fbb4 f0f3 udiv r0, r4, r3 +10001172: f7ff ff55 bl 10001020 +10001176: e7c5 b.n 10001104 +10001178: f3c3 0345 ubfx r3, r3, #1, #6 +1000117c: 4611 mov r1, r2 +1000117e: eb03 1682 add.w r6, r3, r2, lsl #6 +10001182: 461a mov r2, r3 +10001184: e7b9 b.n 100010fa +10001186: bf00 nop +10001188: 40078000 .word 0x40078000 +1000118c: 40022000 .word 0x40022000 +10001190: 40023000 .word 0x40023000 +10001194: 40020000 .word 0x40020000 +10001198: 20003154 .word 0x20003154 +1000119c: 003fffc0 .word 0x003fffc0 +100011a0: 8f2b7b75 .word 0x8f2b7b75 + +100011a4 : +100011a4: eb00 0c40 add.w ip, r0, r0, lsl #1 +100011a8: ea4f 0c8c mov.w ip, ip, lsl #2 +100011ac: f10c 4c80 add.w ip, ip, #1073741824 @ 0x40000000 +100011b0: f50c 3c80 add.w ip, ip, #65536 @ 0x10000 +100011b4: b5f0 push {r4, r5, r6, r7, lr} +100011b6: 4616 mov r6, r2 +100011b8: f8dc 2004 ldr.w r2, [ip, #4] +100011bc: 1f05 subs r5, r0, #4 +100011be: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 +100011c2: bf38 it cc +100011c4: f44f 3280 movcc.w r2, #65536 @ 0x10000 +100011c8: b2ed uxtb r5, r5 +100011ca: bf38 it cc +100011cc: f8cc 2004 strcc.w r2, [ip, #4] +100011d0: 2d01 cmp r5, #1 +100011d2: d92a bls.n 1000122a +100011d4: f44f 6700 mov.w r7, #2048 @ 0x800 +100011d8: 4c25 ldr r4, [pc, #148] @ (10001270 ) +100011da: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +100011de: 6017 str r7, [r2, #0] +100011e0: f854 2020 ldr.w r2, [r4, r0, lsl #2] +100011e4: b9b2 cbnz r2, 10001214 +100011e6: f8dc 2000 ldr.w r2, [ip] +100011ea: 2d01 cmp r5, #1 +100011ec: ea82 1246 eor.w r2, r2, r6, lsl #5 +100011f0: f002 02e0 and.w r2, r2, #224 @ 0xe0 +100011f4: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +100011f8: 6032 str r2, [r6, #0] +100011fa: d92a bls.n 10001252 +100011fc: f44f 6100 mov.w r1, #2048 @ 0x800 +10001200: f844 3020 str.w r3, [r4, r0, lsl #2] +10001204: f44f 3380 mov.w r3, #65536 @ 0x10000 +10001208: f50c 5200 add.w r2, ip, #8192 @ 0x2000 +1000120c: 6011 str r1, [r2, #0] +1000120e: f8cc 3004 str.w r3, [ip, #4] +10001212: bdf0 pop {r4, r5, r6, r7, pc} +10001214: 6967 ldr r7, [r4, #20] +10001216: fbb7 fef2 udiv lr, r7, r2 +1000121a: f10e 0e01 add.w lr, lr, #1 +1000121e: eb0e 0e4e add.w lr, lr, lr, lsl #1 +10001222: f1be 0e03 subs.w lr, lr, #3 +10001226: d2fc bcs.n 10001222 +10001228: e7dd b.n 100011e6 +1000122a: 2901 cmp r1, #1 +1000122c: d1d2 bne.n 100011d4 +1000122e: 2403 movs r4, #3 +10001230: f50c 5240 add.w r2, ip, #12288 @ 0x3000 +10001234: 6014 str r4, [r2, #0] +10001236: f8dc 2008 ldr.w r2, [ip, #8] +1000123a: 07d2 lsls r2, r2, #31 +1000123c: d5fb bpl.n 10001236 +1000123e: f8dc 2000 ldr.w r2, [ip] +10001242: 4c0b ldr r4, [pc, #44] @ (10001270 ) +10001244: ea82 1246 eor.w r2, r2, r6, lsl #5 +10001248: f002 02e0 and.w r2, r2, #224 @ 0xe0 +1000124c: f50c 5680 add.w r6, ip, #4096 @ 0x1000 +10001250: 6032 str r2, [r6, #0] +10001252: 2201 movs r2, #1 +10001254: f8dc 5000 ldr.w r5, [ip] +10001258: 404d eors r5, r1 +1000125a: f005 0503 and.w r5, r5, #3 +1000125e: 6035 str r5, [r6, #0] +10001260: fa02 f101 lsl.w r1, r2, r1 +10001264: f8dc 2008 ldr.w r2, [ip, #8] +10001268: 420a tst r2, r1 +1000126a: d0fb beq.n 10001264 +1000126c: e7c6 b.n 100011fc +1000126e: bf00 nop +10001270: 200030d0 .word 0x200030d0 + +10001274 : +10001274: 4b01 ldr r3, [pc, #4] @ (1000127c ) +10001276: f853 0020 ldr.w r0, [r3, r0, lsl #2] +1000127a: 4770 bx lr +1000127c: 200030d0 .word 0x200030d0 + +10001280 : +10001280: b470 push {r4, r5, r6} +10001282: 9d03 ldr r5, [sp, #12] +10001284: 6804 ldr r4, [r0, #0] +10001286: 032d lsls r5, r5, #12 +10001288: ea45 4503 orr.w r5, r5, r3, lsl #16 +1000128c: 4b1b ldr r3, [pc, #108] @ (100012fc ) +1000128e: 2c00 cmp r4, #0 +10001290: fbb3 f3f1 udiv r3, r3, r1 +10001294: fbb2 f6f3 udiv r6, r2, r3 +10001298: db1f blt.n 100012da +1000129a: 4a19 ldr r2, [pc, #100] @ (10001300 ) +1000129c: 4b19 ldr r3, [pc, #100] @ (10001304 ) +1000129e: 4290 cmp r0, r2 +100012a0: bf14 ite ne +100012a2: f44f 4280 movne.w r2, #16384 @ 0x4000 +100012a6: f44f 4200 moveq.w r2, #32768 @ 0x8000 +100012aa: 4c17 ldr r4, [pc, #92] @ (10001308 ) +100012ac: 601a str r2, [r3, #0] +100012ae: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100012b2: 601a str r2, [r3, #0] +100012b4: 68a3 ldr r3, [r4, #8] +100012b6: ea32 0303 bics.w r3, r2, r3 +100012ba: d1fb bne.n 100012b4 +100012bc: 2221 movs r2, #33 @ 0x21 +100012be: f500 5340 add.w r3, r0, #12288 @ 0x3000 +100012c2: 3304 adds r3, #4 +100012c4: 6001 str r1, [r0, #0] +100012c6: 6086 str r6, [r0, #8] +100012c8: 601a str r2, [r3, #0] +100012ca: 6802 ldr r2, [r0, #0] +100012cc: 2a00 cmp r2, #0 +100012ce: dafc bge.n 100012ca +100012d0: 2208 movs r2, #8 +100012d2: 60c5 str r5, [r0, #12] +100012d4: 601a str r2, [r3, #0] +100012d6: bc70 pop {r4, r5, r6} +100012d8: 4770 bx lr +100012da: 6803 ldr r3, [r0, #0] +100012dc: f003 033f and.w r3, r3, #63 @ 0x3f +100012e0: 428b cmp r3, r1 +100012e2: d1da bne.n 1000129a +100012e4: 6883 ldr r3, [r0, #8] +100012e6: f3c3 030b ubfx r3, r3, #0, #12 +100012ea: 42b3 cmp r3, r6 +100012ec: d1d5 bne.n 1000129a +100012ee: 68c3 ldr r3, [r0, #12] +100012f0: f403 23ee and.w r3, r3, #487424 @ 0x77000 +100012f4: 42ab cmp r3, r5 +100012f6: d1d0 bne.n 1000129a +100012f8: e7ed b.n 100012d6 +100012fa: bf00 nop +100012fc: 00b71b00 .word 0x00b71b00 +10001300: 40058000 .word 0x40058000 +10001304: 40022000 .word 0x40022000 +10001308: 40020000 .word 0x40020000 + +1000130c : +1000130c: 2301 movs r3, #1 +1000130e: eb00 0040 add.w r0, r0, r0, lsl #1 +10001312: 0080 lsls r0, r0, #2 +10001314: f100 4080 add.w r0, r0, #1073741824 @ 0x40000000 +10001318: f500 1084 add.w r0, r0, #1081344 @ 0x108000 +1000131c: 6041 str r1, [r0, #4] +1000131e: 6003 str r3, [r0, #0] +10001320: 4770 bx lr +10001322: bf00 nop + +10001324 : +10001324: 2300 movs r3, #0 +10001326: 8adb ldrh r3, [r3, #22] +10001328: 2200 movs r2, #0 +1000132a: e842 f200 tt r2, r2 +1000132e: 0252 lsls r2, r2, #9 +10001330: d401 bmi.n 10001336 +10001332: 2110 movs r1, #16 +10001334: 4718 bx r3 +10001336: 2104 movs r1, #4 +10001338: 4718 bx r3 +1000133a: bf00 nop + +1000133c : +1000133c: 4a03 ldr r2, [pc, #12] @ (1000134c ) +1000133e: f8d2 3828 ldr.w r3, [r2, #2088] @ 0x828 +10001342: 2b00 cmp r3, #0 +10001344: d0fb beq.n 1000133e +10001346: f3bf 8f5f dmb sy +1000134a: 4770 bx lr +1000134c: 400e0000 .word 0x400e0000 + +10001350 : +10001350: 2100 movs r1, #0 +10001352: 4b04 ldr r3, [pc, #16] @ (10001364 ) +10001354: 4a04 ldr r2, [pc, #16] @ (10001368 ) +10001356: f3bf 8f5f dmb sy +1000135a: f843 1b04 str.w r1, [r3], #4 +1000135e: 4293 cmp r3, r2 +10001360: d1f9 bne.n 10001356 +10001362: 4770 bx lr +10001364: 400e080c .word 0x400e080c +10001368: 400e082c .word 0x400e082c + +1000136c : +1000136c: b410 push {r4} +1000136e: f44f 708d mov.w r0, #282 @ 0x11a +10001372: f44f 642a mov.w r4, #2720 @ 0xaa0 +10001376: 4a06 ldr r2, [pc, #24] @ (10001390 ) +10001378: 4b06 ldr r3, [pc, #24] @ (10001394 ) +1000137a: 4907 ldr r1, [pc, #28] @ (10001398 ) +1000137c: 6014 str r4, [r2, #0] +1000137e: 60d0 str r0, [r2, #12] +10001380: 6019 str r1, [r3, #0] +10001382: 6853 ldr r3, [r2, #4] +10001384: 2b00 cmp r3, #0 +10001386: dafc bge.n 10001382 +10001388: f85d 4b04 ldr.w r4, [sp], #4 +1000138c: 4770 bx lr +1000138e: bf00 nop +10001390: 40048000 .word 0x40048000 +10001394: 4004a000 .word 0x4004a000 +10001398: 00fab000 .word 0x00fab000 + +1000139c : +1000139c: 4770 bx lr +1000139e: bf00 nop + +100013a0 : +100013a0: b508 push {r3, lr} +100013a2: 4801 ldr r0, [pc, #4] @ (100013a8 ) +100013a4: f7ff f838 bl 10000418 +100013a8: 10005f74 .word 0x10005f74 + +100013ac : +100013ac: b538 push {r3, r4, r5, lr} +100013ae: 4c05 ldr r4, [pc, #20] @ (100013c4 ) +100013b0: 4d05 ldr r5, [pc, #20] @ (100013c8 ) +100013b2: 42ac cmp r4, r5 +100013b4: d204 bcs.n 100013c0 +100013b6: f854 3b04 ldr.w r3, [r4], #4 +100013ba: 4798 blx r3 +100013bc: 42ac cmp r4, r5 +100013be: d3fa bcc.n 100013b6 +100013c0: bd38 pop {r3, r4, r5, pc} +100013c2: bf00 nop +100013c4: 10005e60 .word 0x10005e60 +100013c8: 10005ea0 .word 0x10005ea0 + +100013cc : +100013cc: b410 push {r4} +100013ce: 4807 ldr r0, [pc, #28] @ (100013ec ) +100013d0: 4c07 ldr r4, [pc, #28] @ (100013f0 ) +100013d2: 4b08 ldr r3, [pc, #32] @ (100013f4 ) +100013d4: 4a08 ldr r2, [pc, #32] @ (100013f8 ) +100013d6: 4909 ldr r1, [pc, #36] @ (100013fc ) +100013d8: 6004 str r4, [r0, #0] +100013da: 601a str r2, [r3, #0] +100013dc: 688b ldr r3, [r1, #8] +100013de: ea32 0303 bics.w r3, r2, r3 +100013e2: d1fb bne.n 100013dc +100013e4: f85d 4b04 ldr.w r4, [sp], #4 +100013e8: 4770 bx lr +100013ea: bf00 nop +100013ec: 40022000 .word 0x40022000 +100013f0: efef3b7f .word 0xefef3b7f +100013f4: 40023000 .word 0x40023000 +100013f8: 03f3fff6 .word 0x03f3fff6 +100013fc: 40020000 .word 0x40020000 + +10001400 : +10001400: 4b04 ldr r3, [pc, #16] @ (10001414 ) +10001402: 6cdb ldr r3, [r3, #76] @ 0x4c +10001404: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 +10001408: d103 bne.n 10001412 +1000140a: f44f 2280 mov.w r2, #262144 @ 0x40000 +1000140e: 4b02 ldr r3, [pc, #8] @ (10001418 ) +10001410: 64da str r2, [r3, #76] @ 0x4c +10001412: 4770 bx lr +10001414: 50110000 .word 0x50110000 +10001418: 50112000 .word 0x50112000 + +1000141c : +1000141c: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 +10001420: 4b04 ldr r3, [pc, #16] @ (10001434 ) +10001422: f8d2 1d88 ldr.w r1, [r2, #3464] @ 0xd88 +10001426: 430b orrs r3, r1 +10001428: f8c2 3d88 str.w r3, [r2, #3464] @ 0xd88 +1000142c: ee10 0430 dcp_rcmp r0 +10001430: 4770 bx lr +10001432: bf00 nop +10001434: 00300303 .word 0x00300303 + +10001438 : +10001438: f06f 4160 mvn.w r1, #3758096384 @ 0xe0000000 +1000143c: 4b04 ldr r3, [pc, #16] @ (10001450 ) +1000143e: 4a05 ldr r2, [pc, #20] @ (10001454 ) +10001440: 6019 str r1, [r3, #0] +10001442: 6893 ldr r3, [r2, #8] +10001444: 43db mvns r3, r3 +10001446: f033 4360 bics.w r3, r3, #3758096384 @ 0xe0000000 +1000144a: d1fa bne.n 10001442 +1000144c: 4770 bx lr +1000144e: bf00 nop +10001450: 40023000 .word 0x40023000 +10001454: 40020000 .word 0x40020000 + +10001458 : +10001458: b510 push {r4, lr} +1000145a: f245 2053 movw r0, #21075 @ 0x5253 +1000145e: f7ff ff61 bl 10001324 +10001462: e8bd 4010 ldmia.w sp!, {r4, lr} +10001466: 4603 mov r3, r0 +10001468: 2004 movs r0, #4 +1000146a: 4718 bx r3 + +1000146c : +1000146c: b510 push {r4, lr} +1000146e: f245 2053 movw r0, #21075 @ 0x5253 +10001472: f7ff ff57 bl 10001324 +10001476: e8bd 4010 ldmia.w sp!, {r4, lr} +1000147a: 4603 mov r3, r0 +1000147c: 2001 movs r0, #1 +1000147e: 4718 bx r3 + +10001480 : +10001480: f7ff b822 b.w 100004c8 + +10001484 : +10001484: 4914 ldr r1, [pc, #80] @ (100014d8 ) +10001486: 4b15 ldr r3, [pc, #84] @ (100014dc ) +10001488: b570 push {r4, r5, r6, lr} +1000148a: 1a5c subs r4, r3, r1 +1000148c: 10a6 asrs r6, r4, #2 +1000148e: 2e44 cmp r6, #68 @ 0x44 +10001490: 4632 mov r2, r6 +10001492: bf28 it cs +10001494: 2244 movcs r2, #68 @ 0x44 +10001496: 4d12 ldr r5, [pc, #72] @ (100014e0 ) +10001498: 0092 lsls r2, r2, #2 +1000149a: 4628 mov r0, r5 +1000149c: f004 fade bl 10005a5c +100014a0: f5b4 7f86 cmp.w r4, #268 @ 0x10c +100014a4: d813 bhi.n 100014ce +100014a6: 4a0f ldr r2, [pc, #60] @ (100014e4 ) +100014a8: f1c6 0044 rsb r0, r6, #68 @ 0x44 +100014ac: d012 beq.n 100014d4 +100014ae: 192b adds r3, r5, r4 +100014b0: 0841 lsrs r1, r0, #1 +100014b2: eb03 01c1 add.w r1, r3, r1, lsl #3 +100014b6: e9c3 2200 strd r2, r2, [r3] +100014ba: 3308 adds r3, #8 +100014bc: 428b cmp r3, r1 +100014be: d1fa bne.n 100014b6 +100014c0: 07c3 lsls r3, r0, #31 +100014c2: d504 bpl.n 100014ce +100014c4: f020 0001 bic.w r0, r0, #1 +100014c8: 4430 add r0, r6 +100014ca: f845 2020 str.w r2, [r5, r0, lsl #2] +100014ce: 4b06 ldr r3, [pc, #24] @ (100014e8 ) +100014d0: 609d str r5, [r3, #8] +100014d2: bd70 pop {r4, r5, r6, pc} +100014d4: 2043 movs r0, #67 @ 0x43 +100014d6: e7f8 b.n 100014ca +100014d8: 10000000 .word 0x10000000 +100014dc: 10000110 .word 0x10000110 +100014e0: 20000000 .word 0x20000000 +100014e4: 10000111 .word 0x10000111 +100014e8: e000ed00 .word 0xe000ed00 + +100014ec : +100014ec: 2300 movs r3, #0 +100014ee: b570 push {r4, r5, r6, lr} +100014f0: 4c2b ldr r4, [pc, #172] @ (100015a0 ) +100014f2: b082 sub sp, #8 +100014f4: f8c4 3084 str.w r3, [r4, #132] @ 0x84 +100014f8: f7ff ff38 bl 1000136c +100014fc: 2201 movs r2, #1 +100014fe: 4b29 ldr r3, [pc, #164] @ (100015a4 ) +10001500: 63da str r2, [r3, #60] @ 0x3c +10001502: 6c63 ldr r3, [r4, #68] @ 0x44 +10001504: 2b01 cmp r3, #1 +10001506: d1fc bne.n 10001502 +10001508: 2103 movs r1, #3 +1000150a: 4a26 ldr r2, [pc, #152] @ (100015a4 ) +1000150c: 4b24 ldr r3, [pc, #144] @ (100015a0 ) +1000150e: 6311 str r1, [r2, #48] @ 0x30 +10001510: 6b9c ldr r4, [r3, #56] @ 0x38 +10001512: 2c01 cmp r4, #1 +10001514: d1fc bne.n 10001510 +10001516: 2602 movs r6, #2 +10001518: 2505 movs r5, #5 +1000151a: 4621 mov r1, r4 +1000151c: 2305 movs r3, #5 +1000151e: 4a22 ldr r2, [pc, #136] @ (100015a8 ) +10001520: 4822 ldr r0, [pc, #136] @ (100015ac ) +10001522: 9600 str r6, [sp, #0] +10001524: f7ff feac bl 10001280 +10001528: 4621 mov r1, r4 +1000152a: 462b mov r3, r5 +1000152c: 4a20 ldr r2, [pc, #128] @ (100015b0 ) +1000152e: 4821 ldr r0, [pc, #132] @ (100015b4 ) +10001530: 9500 str r5, [sp, #0] +10001532: f7ff fea5 bl 10001280 +10001536: 2200 movs r2, #0 +10001538: 2004 movs r0, #4 +1000153a: 4631 mov r1, r6 +1000153c: 4b1e ldr r3, [pc, #120] @ (100015b8 ) +1000153e: f7ff fe31 bl 100011a4 +10001542: 4621 mov r1, r4 +10001544: 4628 mov r0, r5 +10001546: 2200 movs r2, #0 +10001548: 4b1c ldr r3, [pc, #112] @ (100015bc ) +1000154a: f7ff fe2b bl 100011a4 +1000154e: 2200 movs r2, #0 +10001550: 2008 movs r0, #8 +10001552: 4611 mov r1, r2 +10001554: 4b1a ldr r3, [pc, #104] @ (100015c0 ) +10001556: f7ff fe25 bl 100011a4 +1000155a: 2200 movs r2, #0 +1000155c: 2009 movs r0, #9 +1000155e: 4611 mov r1, r2 +10001560: 4b17 ldr r3, [pc, #92] @ (100015c0 ) +10001562: f7ff fe1f bl 100011a4 +10001566: 2200 movs r2, #0 +10001568: 2006 movs r0, #6 +1000156a: 4611 mov r1, r2 +1000156c: 4b13 ldr r3, [pc, #76] @ (100015bc ) +1000156e: f7ff fe19 bl 100011a4 +10001572: 2200 movs r2, #0 +10001574: 4b11 ldr r3, [pc, #68] @ (100015bc ) +10001576: 2007 movs r0, #7 +10001578: 4611 mov r1, r2 +1000157a: f7ff fe13 bl 100011a4 +1000157e: 2004 movs r0, #4 +10001580: f7ff fe78 bl 10001274 +10001584: 2400 movs r4, #0 +10001586: 4b0f ldr r3, [pc, #60] @ (100015c4 ) +10001588: fba3 3500 umull r3, r5, r3, r0 +1000158c: 0cad lsrs r5, r5, #18 +1000158e: b2e0 uxtb r0, r4 +10001590: 4629 mov r1, r5 +10001592: 3401 adds r4, #1 +10001594: f7ff feba bl 1000130c +10001598: 2c06 cmp r4, #6 +1000159a: d1f8 bne.n 1000158e +1000159c: b002 add sp, #8 +1000159e: bd70 pop {r4, r5, r6, pc} +100015a0: 40010000 .word 0x40010000 +100015a4: 40013000 .word 0x40013000 +100015a8: 59682f00 .word 0x59682f00 +100015ac: 40050000 .word 0x40050000 +100015b0: 47868c00 .word 0x47868c00 +100015b4: 40058000 .word 0x40058000 +100015b8: 00b71b00 .word 0x00b71b00 +100015bc: 08f0d180 .word 0x08f0d180 +100015c0: 02dc6c00 .word 0x02dc6c00 +100015c4: 431bde83 .word 0x431bde83 + +100015c8 : +100015c8: b086 sub sp, #24 +100015ca: b403 push {r0, r1} +100015cc: fc51 0408 dcp_pxmd r0, r1 +100015d0: e9cd 0102 strd r0, r1, [sp, #8] +100015d4: fc51 0409 dcp_pymd r0, r1 +100015d8: e9cd 0104 strd r0, r1, [sp, #16] +100015dc: ec51 040a dcp_refd r0, r1 +100015e0: e9cd 0106 strd r0, r1, [sp, #24] +100015e4: bc03 pop {r0, r1} +100015e6: 47f0 blx lr + +100015e8 : +100015e8: e8bd 5000 ldmia.w sp!, {ip, lr} +100015ec: ec4e c400 dcp_wxmd ip, lr +100015f0: e8bd 5000 ldmia.w sp!, {ip, lr} +100015f4: ec4e c401 dcp_wymd ip, lr +100015f8: e8bd 5000 ldmia.w sp!, {ip, lr} +100015fc: ec4e c402 dcp_wefd ip, lr +10001600: bd00 pop {pc} +10001602: 0000 movs r0, r0 +10001604: b500 push {lr} +10001606: f7ff ffdf bl 100015c8 +1000160a: e002 b.n 10001612 <__wrap___aeabi_dadd+0x6> + +1000160c <__wrap___aeabi_dadd>: +1000160c: fe10 f430 dcp_pcmp APSR_nzcv +10001610: d4f8 bmi.n 10001604 +10001612: ec41 0410 dcp_wxup r0, r1 +10001616: ec43 2411 dcp_wyup r2, r3 +1000161a: ee00 0401 dcp_add0 +1000161e: ee10 0401 dcp_add1 +10001622: ee80 0420 dcp_nrdd +10001626: ec51 0410 dcp_rdda r0, r1 +1000162a: 4770 bx lr +1000162c: b500 push {lr} +1000162e: f7ff ffcb bl 100015c8 +10001632: e002 b.n 1000163a <__wrap___aeabi_dsub+0x6> + +10001634 <__wrap___aeabi_dsub>: +10001634: fe10 f430 dcp_pcmp APSR_nzcv +10001638: d4f8 bmi.n 1000162c <__wrap___aeabi_dadd+0x20> +1000163a: ec41 0410 dcp_wxup r0, r1 +1000163e: ec43 2411 dcp_wyup r2, r3 +10001642: ee00 0401 dcp_add0 +10001646: ee10 0421 dcp_sub1 +1000164a: ee80 0420 dcp_nrdd +1000164e: ec51 0430 dcp_rdds r0, r1 +10001652: 4770 bx lr +10001654: b500 push {lr} +10001656: f7ff ffb7 bl 100015c8 +1000165a: e002 b.n 10001662 <__wrap___aeabi_dmul+0x6> + +1000165c <__wrap___aeabi_dmul>: +1000165c: fe10 f430 dcp_pcmp APSR_nzcv +10001660: d4f8 bmi.n 10001654 <__wrap___aeabi_dsub+0x20> +10001662: b510 push {r4, lr} +10001664: ec41 0410 dcp_wxup r0, r1 +10001668: ec43 2411 dcp_wyup r2, r3 +1000166c: ec51 0404 dcp_rxms r0, r1, #0x0 +10001670: ec53 2405 dcp_ryms r2, r3, #0x0 +10001674: fba0 4c02 umull r4, ip, r0, r2 +10001678: f05f 0e00 movs.w lr, #0 +1000167c: fbe0 ce03 umlal ip, lr, r0, r3 +10001680: fbe1 ce02 umlal ip, lr, r1, r2 +10001684: ec4c 4420 dcp_wxms r4, ip +10001688: 2400 movs r4, #0 +1000168a: fbe1 e403 umlal lr, r4, r1, r3 +1000168e: ec44 e430 dcp_wxmo lr, r4 +10001692: ee80 0420 dcp_nrdd +10001696: ec51 0450 dcp_rddm r0, r1 +1000169a: e8bd 4010 ldmia.w sp!, {r4, lr} +1000169e: 4770 bx lr +100016a0: b500 push {lr} +100016a2: f7ff ff91 bl 100015c8 +100016a6: e002 b.n 100016ae <__wrap___aeabi_ddiv+0x6> + +100016a8 <__wrap___aeabi_ddiv>: +100016a8: fe10 f430 dcp_pcmp APSR_nzcv +100016ac: d4f8 bmi.n 100016a0 <__wrap___aeabi_dmul+0x44> +100016ae: ec41 0410 dcp_wxup r0, r1 +100016b2: ec43 2411 dcp_wyup r2, r3 +100016b6: ec51 0421 dcp_rymr r0, r1 +100016ba: fba0 1201 umull r1, r2, r0, r1 +100016be: ea6f 0282 mvn.w r2, r2, lsl #2 +100016c2: fb52 0010 smmlar r0, r2, r0, r0 +100016c6: fb52 f212 smmulr r2, r2, r2 +100016ca: fb52 0010 smmlar r0, r2, r0, r0 +100016ce: eba0 7cd0 sub.w ip, r0, r0, lsr #31 +100016d2: ec53 2404 dcp_rxms r2, r3, #0x0 +100016d6: fb5c f113 smmulr r1, ip, r3 +100016da: ec53 2415 dcp_ryms r2, r3, #0x1 +100016de: fba1 2002 umull r2, r0, r1, r2 +100016e2: fb01 0003 mla r0, r1, r3, r0 +100016e6: ec53 2444 dcp_rxms r2, r3, #0x4 +100016ea: eba2 0000 sub.w r0, r2, r0 +100016ee: fb50 f21c smmulr r2, r0, ip +100016f2: ea4f 1311 mov.w r3, r1, lsr #4 +100016f6: eb12 7001 adds.w r0, r2, r1, lsl #28 +100016fa: eb43 71e2 adc.w r1, r3, r2, asr #31 +100016fe: ea40 5051 orr.w r0, r0, r1, lsr #21 +10001702: ea20 5091 bic.w r0, r0, r1, lsr #22 +10001706: f020 0007 bic.w r0, r0, #7 +1000170a: ec53 2475 dcp_ryms r2, r3, #0x7 +1000170e: fba0 3c02 umull r3, ip, r0, r2 +10001712: ec53 2475 dcp_ryms r2, r3, #0x7 +10001716: fb00 cc03 mla ip, r0, r3, ip +1000171a: fb01 cc02 mla ip, r1, r2, ip +1000171e: ec53 2404 dcp_rxms r2, r3, #0x0 +10001722: ebac 4c82 sub.w ip, ip, r2, lsl #18 +10001726: ea40 705c orr.w r0, r0, ip, lsr #29 +1000172a: f1a0 0001 sub.w r0, r0, #1 +1000172e: ec41 0440 dcp_wxdd r0, r1 +10001732: ee80 0420 dcp_nrdd +10001736: ec51 0470 dcp_rddd r0, r1 +1000173a: 4770 bx lr +1000173c: b500 push {lr} +1000173e: f7ff ff43 bl 100015c8 +10001742: e002 b.n 1000174a <__wrap___aeabi_i2d+0x6> + +10001744 <__wrap___aeabi_i2d>: +10001744: fe10 f430 dcp_pcmp APSR_nzcv +10001748: d4f8 bmi.n 1000173c <__wrap___aeabi_ddiv+0x94> +1000174a: ec40 0470 dcp_wxic r0, r0 +1000174e: ee00 0401 dcp_add0 +10001752: ee10 0421 dcp_sub1 +10001756: ee80 0420 dcp_nrdd +1000175a: ec51 0430 dcp_rdds r0, r1 +1000175e: 4770 bx lr +10001760: b500 push {lr} +10001762: f7ff ff31 bl 100015c8 +10001766: e002 b.n 1000176e <__wrap___aeabi_ui2d+0x6> + +10001768 <__wrap___aeabi_ui2d>: +10001768: fe10 f430 dcp_pcmp APSR_nzcv +1000176c: d4f8 bmi.n 10001760 <__wrap___aeabi_i2d+0x1c> +1000176e: ec40 0460 dcp_wxuc r0, r0 +10001772: ee00 0401 dcp_add0 +10001776: ee10 0421 dcp_sub1 +1000177a: ee80 0420 dcp_nrdd +1000177e: ec51 0430 dcp_rdds r0, r1 +10001782: 4770 bx lr +10001784: b500 push {lr} +10001786: f7ff ff1f bl 100015c8 +1000178a: e002 b.n 10001792 + +1000178c <__wrap___aeabi_d2iz>: +1000178c: fe10 f430 dcp_pcmp APSR_nzcv +10001790: d4f8 bmi.n 10001784 <__wrap___aeabi_ui2d+0x1c> + +10001792 : +10001792: ec41 0480 dcp_wxdc r0, r1 +10001796: ee00 0401 dcp_add0 +1000179a: ee10 0401 dcp_add1 +1000179e: ee80 0440 dcp_ntdc +100017a2: ee10 0413 dcp_rdic r0 +100017a6: 4770 bx lr +100017a8: b500 push {lr} +100017aa: f7ff ff0d bl 100015c8 +100017ae: e002 b.n 100017b6 + +100017b0 <__wrap___aeabi_d2uiz>: +100017b0: fe10 f430 dcp_pcmp APSR_nzcv +100017b4: d4f8 bmi.n 100017a8 + +100017b6 : +100017b6: ec41 0480 dcp_wxdc r0, r1 +100017ba: ee00 0401 dcp_add0 +100017be: ee10 0401 dcp_add1 +100017c2: ee80 0440 dcp_ntdc +100017c6: ee10 0433 dcp_rduc r0 +100017ca: 4770 bx lr +100017cc: b500 push {lr} +100017ce: f7ff fefb bl 100015c8 +100017d2: e002 b.n 100017da <__wrap___aeabi_dcmpun+0x6> + +100017d4 <__wrap___aeabi_dcmpun>: +100017d4: fe10 f430 dcp_pcmp APSR_nzcv +100017d8: d4f8 bmi.n 100017cc +100017da: ec41 0410 dcp_wxup r0, r1 +100017de: ec43 2411 dcp_wyup r2, r3 +100017e2: ee00 0401 dcp_add0 +100017e6: ee10 0430 dcp_rcmp r0 +100017ea: f3c0 7000 ubfx r0, r0, #28, #1 +100017ee: 4770 bx lr +100017f0: b500 push {lr} +100017f2: f7ff fee9 bl 100015c8 +100017f6: e002 b.n 100017fe <__wrap___aeabi_dcmplt+0x6> + +100017f8 <__wrap___aeabi_dcmplt>: +100017f8: fe10 f430 dcp_pcmp APSR_nzcv +100017fc: d4f8 bmi.n 100017f0 <__wrap___aeabi_dcmpun+0x1c> +100017fe: ec43 2410 dcp_wxup r2, r3 +10001802: ec41 0411 dcp_wyup r0, r1 +10001806: ee00 0401 dcp_add0 +1000180a: ee10 f430 dcp_rcmp APSR_nzcv +1000180e: bf8c ite hi +10001810: 2001 movhi r0, #1 +10001812: 2000 movls r0, #0 +10001814: 4770 bx lr +10001816: bf00 nop +10001818: b500 push {lr} +1000181a: f7ff fed5 bl 100015c8 +1000181e: e002 b.n 10001826 <__wrap___aeabi_dcmple+0x6> + +10001820 <__wrap___aeabi_dcmple>: +10001820: fe10 f430 dcp_pcmp APSR_nzcv +10001824: d4f8 bmi.n 10001818 <__wrap___aeabi_dcmplt+0x20> +10001826: ec43 2410 dcp_wxup r2, r3 +1000182a: ec41 0411 dcp_wyup r0, r1 +1000182e: ee00 0401 dcp_add0 +10001832: ee10 f430 dcp_rcmp APSR_nzcv +10001836: bf2c ite cs +10001838: 2001 movcs r0, #1 +1000183a: 2000 movcc r0, #0 +1000183c: 4770 bx lr +1000183e: bf00 nop +10001840: b500 push {lr} +10001842: f7ff fec1 bl 100015c8 +10001846: e002 b.n 1000184e <__wrap___aeabi_dcmpge+0x6> + +10001848 <__wrap___aeabi_dcmpge>: +10001848: fe10 f430 dcp_pcmp APSR_nzcv +1000184c: d4f8 bmi.n 10001840 <__wrap___aeabi_dcmple+0x20> +1000184e: ec41 0410 dcp_wxup r0, r1 +10001852: ec43 2411 dcp_wyup r2, r3 +10001856: ee00 0401 dcp_add0 +1000185a: ee10 f430 dcp_rcmp APSR_nzcv +1000185e: bf2c ite cs +10001860: 2001 movcs r0, #1 +10001862: 2000 movcc r0, #0 +10001864: 4770 bx lr +10001866: bf00 nop +10001868: b500 push {lr} +1000186a: f7ff fead bl 100015c8 +1000186e: e002 b.n 10001876 <__wrap___aeabi_dcmpgt+0x6> + +10001870 <__wrap___aeabi_dcmpgt>: +10001870: fe10 f430 dcp_pcmp APSR_nzcv +10001874: d4f8 bmi.n 10001868 <__wrap___aeabi_dcmpge+0x20> +10001876: ec41 0410 dcp_wxup r0, r1 +1000187a: ec43 2411 dcp_wyup r2, r3 +1000187e: ee00 0401 dcp_add0 +10001882: ee10 f430 dcp_rcmp APSR_nzcv +10001886: bf8c ite hi +10001888: 2001 movhi r0, #1 +1000188a: 2000 movls r0, #0 +1000188c: 4770 bx lr +1000188e: bf00 nop + +10001890 <__wrap_calloc>: +10001890: b538 push {r3, r4, r5, lr} +10001892: 4604 mov r4, r0 +10001894: 460d mov r5, r1 +10001896: f003 fd59 bl 1000534c +1000189a: fb05 f404 mul.w r4, r5, r4 +1000189e: b128 cbz r0, 100018ac <__wrap_calloc+0x1c> +100018a0: 4603 mov r3, r0 +100018a2: 4a04 ldr r2, [pc, #16] @ (100018b4 <__wrap_calloc+0x24>) +100018a4: 4423 add r3, r4 +100018a6: 4293 cmp r3, r2 +100018a8: d800 bhi.n 100018ac <__wrap_calloc+0x1c> +100018aa: bd38 pop {r3, r4, r5, pc} +100018ac: 4802 ldr r0, [pc, #8] @ (100018b8 <__wrap_calloc+0x28>) +100018ae: f7fe fdb3 bl 10000418 +100018b2: bf00 nop +100018b4: 20080000 .word 0x20080000 +100018b8: 10005f80 .word 0x10005f80 + +100018bc <__wrap_free>: +100018bc: f003 bd86 b.w 100053cc + +100018c0 <_out_null>: +100018c0: 4770 bx lr +100018c2: bf00 nop + +100018c4 <_out_rev>: +100018c4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100018c8: b083 sub sp, #12 +100018ca: 4699 mov r9, r3 +100018cc: e9dd ab0d ldrd sl, fp, [sp, #52] @ 0x34 +100018d0: 9b0f ldr r3, [sp, #60] @ 0x3c +100018d2: 4688 mov r8, r1 +100018d4: 4611 mov r1, r2 +100018d6: 079a lsls r2, r3, #30 +100018d8: 4607 mov r7, r0 +100018da: d116 bne.n 1000190a <_out_rev+0x46> +100018dc: 45da cmp sl, fp +100018de: d23a bcs.n 10001956 <_out_rev+0x92> +100018e0: 460c mov r4, r1 +100018e2: 460d mov r5, r1 +100018e4: ebab 060a sub.w r6, fp, sl +100018e8: 440e add r6, r1 +100018ea: 4622 mov r2, r4 +100018ec: 464b mov r3, r9 +100018ee: 4641 mov r1, r8 +100018f0: 2020 movs r0, #32 +100018f2: 3401 adds r4, #1 +100018f4: 47b8 blx r7 +100018f6: 42b4 cmp r4, r6 +100018f8: d1f7 bne.n 100018ea <_out_rev+0x26> +100018fa: 4629 mov r1, r5 +100018fc: f1ba 0f00 cmp.w sl, #0 +10001900: d108 bne.n 10001914 <_out_rev+0x50> +10001902: 4620 mov r0, r4 +10001904: b003 add sp, #12 +10001906: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000190a: 460c mov r4, r1 +1000190c: f1ba 0f00 cmp.w sl, #0 +10001910: d010 beq.n 10001934 <_out_rev+0x70> +10001912: 460e mov r6, r1 +10001914: 4655 mov r5, sl +10001916: 9b0c ldr r3, [sp, #48] @ 0x30 +10001918: 442e add r6, r5 +1000191a: 449a add sl, r3 +1000191c: 9101 str r1, [sp, #4] +1000191e: 1b72 subs r2, r6, r5 +10001920: 464b mov r3, r9 +10001922: 3d01 subs r5, #1 +10001924: 4641 mov r1, r8 +10001926: f81a 0d01 ldrb.w r0, [sl, #-1]! +1000192a: 4634 mov r4, r6 +1000192c: 47b8 blx r7 +1000192e: 2d00 cmp r5, #0 +10001930: d1f5 bne.n 1000191e <_out_rev+0x5a> +10001932: 9901 ldr r1, [sp, #4] +10001934: 9b0f ldr r3, [sp, #60] @ 0x3c +10001936: 079b lsls r3, r3, #30 +10001938: d5e3 bpl.n 10001902 <_out_rev+0x3e> +1000193a: 1a65 subs r5, r4, r1 +1000193c: 45ab cmp fp, r5 +1000193e: d9e0 bls.n 10001902 <_out_rev+0x3e> +10001940: 4622 mov r2, r4 +10001942: 464b mov r3, r9 +10001944: 4641 mov r1, r8 +10001946: 2020 movs r0, #32 +10001948: 3501 adds r5, #1 +1000194a: 47b8 blx r7 +1000194c: 455d cmp r5, fp +1000194e: f104 0401 add.w r4, r4, #1 +10001952: d3f5 bcc.n 10001940 <_out_rev+0x7c> +10001954: e7d5 b.n 10001902 <_out_rev+0x3e> +10001956: 460c mov r4, r1 +10001958: f1ba 0f00 cmp.w sl, #0 +1000195c: d1d9 bne.n 10001912 <_out_rev+0x4e> +1000195e: e7d0 b.n 10001902 <_out_rev+0x3e> + +10001960 <_ntoa_format>: +10001960: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001964: 9f0f ldr r7, [sp, #60] @ 0x3c +10001966: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 +1000196a: f017 0f02 tst.w r7, #2 +1000196e: 9c0a ldr r4, [sp, #40] @ 0x28 +10001970: f89d a02c ldrb.w sl, [sp, #44] @ 0x2c +10001974: 9d0e ldr r5, [sp, #56] @ 0x38 +10001976: e9dd 960c ldrd r9, r6, [sp, #48] @ 0x30 +1000197a: d144 bne.n 10001a06 <_ntoa_format+0xa6> +1000197c: bbf5 cbnz r5, 100019fc <_ntoa_format+0x9c> +1000197e: 42b4 cmp r4, r6 +10001980: d241 bcs.n 10001a06 <_ntoa_format+0xa6> +10001982: f007 0b01 and.w fp, r7, #1 +10001986: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +1000198a: f04f 0e30 mov.w lr, #48 @ 0x30 +1000198e: 44c4 add ip, r8 +10001990: e004 b.n 1000199c <_ntoa_format+0x3c> +10001992: 3401 adds r4, #1 +10001994: 42a6 cmp r6, r4 +10001996: f80c ef01 strb.w lr, [ip, #1]! +1000199a: d901 bls.n 100019a0 <_ntoa_format+0x40> +1000199c: 2c20 cmp r4, #32 +1000199e: d1f8 bne.n 10001992 <_ntoa_format+0x32> +100019a0: f1bb 0f00 cmp.w fp, #0 +100019a4: f000 8088 beq.w 10001ab8 <_ntoa_format+0x158> +100019a8: 42a5 cmp r5, r4 +100019aa: d92c bls.n 10001a06 <_ntoa_format+0xa6> +100019ac: f104 3cff add.w ip, r4, #4294967295 @ 0xffffffff +100019b0: f04f 0e30 mov.w lr, #48 @ 0x30 +100019b4: 44c4 add ip, r8 +100019b6: e004 b.n 100019c2 <_ntoa_format+0x62> +100019b8: 3401 adds r4, #1 +100019ba: 42ac cmp r4, r5 +100019bc: f80c ef01 strb.w lr, [ip, #1]! +100019c0: d021 beq.n 10001a06 <_ntoa_format+0xa6> +100019c2: 2c20 cmp r4, #32 +100019c4: d1f8 bne.n 100019b8 <_ntoa_format+0x58> +100019c6: f017 0f10 tst.w r7, #16 +100019ca: d00e beq.n 100019ea <_ntoa_format+0x8a> +100019cc: f417 6f80 tst.w r7, #1024 @ 0x400 +100019d0: d154 bne.n 10001a7c <_ntoa_format+0x11c> +100019d2: 42a6 cmp r6, r4 +100019d4: d063 beq.n 10001a9e <_ntoa_format+0x13e> +100019d6: 42a5 cmp r5, r4 +100019d8: d061 beq.n 10001a9e <_ntoa_format+0x13e> +100019da: f1b9 0f10 cmp.w r9, #16 +100019de: d050 beq.n 10001a82 <_ntoa_format+0x122> +100019e0: f1b9 0f02 cmp.w r9, #2 +100019e4: d056 beq.n 10001a94 <_ntoa_format+0x134> +100019e6: 2c20 cmp r4, #32 +100019e8: d129 bne.n 10001a3e <_ntoa_format+0xde> +100019ea: 2420 movs r4, #32 +100019ec: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +100019f0: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +100019f4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100019f8: f7ff bf64 b.w 100018c4 <_out_rev> +100019fc: f017 0b01 ands.w fp, r7, #1 +10001a00: d134 bne.n 10001a6c <_ntoa_format+0x10c> +10001a02: 42b4 cmp r4, r6 +10001a04: d3bf bcc.n 10001986 <_ntoa_format+0x26> +10001a06: f017 0f10 tst.w r7, #16 +10001a0a: d01e beq.n 10001a4a <_ntoa_format+0xea> +10001a0c: f417 6f80 tst.w r7, #1024 @ 0x400 +10001a10: d1e3 bne.n 100019da <_ntoa_format+0x7a> +10001a12: 2c00 cmp r4, #0 +10001a14: d1dd bne.n 100019d2 <_ntoa_format+0x72> +10001a16: f1b9 0f10 cmp.w r9, #16 +10001a1a: d063 beq.n 10001ae4 <_ntoa_format+0x184> +10001a1c: f1b9 0f02 cmp.w r9, #2 +10001a20: d077 beq.n 10001b12 <_ntoa_format+0x1b2> +10001a22: 2430 movs r4, #48 @ 0x30 +10001a24: f888 4000 strb.w r4, [r8] +10001a28: 2401 movs r4, #1 +10001a2a: f1ba 0f00 cmp.w sl, #0 +10001a2e: d111 bne.n 10001a54 <_ntoa_format+0xf4> +10001a30: 077e lsls r6, r7, #29 +10001a32: d548 bpl.n 10001ac6 <_ntoa_format+0x166> +10001a34: 262b movs r6, #43 @ 0x2b +10001a36: f808 6004 strb.w r6, [r8, r4] +10001a3a: 3401 adds r4, #1 +10001a3c: e7d6 b.n 100019ec <_ntoa_format+0x8c> +10001a3e: 4626 mov r6, r4 +10001a40: 3401 adds r4, #1 +10001a42: f04f 0c30 mov.w ip, #48 @ 0x30 +10001a46: f808 c006 strb.w ip, [r8, r6] +10001a4a: 2c20 cmp r4, #32 +10001a4c: d0cd beq.n 100019ea <_ntoa_format+0x8a> +10001a4e: f1ba 0f00 cmp.w sl, #0 +10001a52: d0ed beq.n 10001a30 <_ntoa_format+0xd0> +10001a54: 262d movs r6, #45 @ 0x2d +10001a56: f808 6004 strb.w r6, [r8, r4] +10001a5a: 3401 adds r4, #1 +10001a5c: e9cd 570b strd r5, r7, [sp, #44] @ 0x2c +10001a60: e9cd 8409 strd r8, r4, [sp, #36] @ 0x24 +10001a64: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001a68: f7ff bf2c b.w 100018c4 <_out_rev> +10001a6c: f1ba 0f00 cmp.w sl, #0 +10001a70: d030 beq.n 10001ad4 <_ntoa_format+0x174> +10001a72: 42b4 cmp r4, r6 +10001a74: f105 35ff add.w r5, r5, #4294967295 @ 0xffffffff +10001a78: d385 bcc.n 10001986 <_ntoa_format+0x26> +10001a7a: e795 b.n 100019a8 <_ntoa_format+0x48> +10001a7c: f1b9 0f10 cmp.w r9, #16 +10001a80: d1b3 bne.n 100019ea <_ntoa_format+0x8a> +10001a82: 06be lsls r6, r7, #26 +10001a84: d53b bpl.n 10001afe <_ntoa_format+0x19e> +10001a86: 2c20 cmp r4, #32 +10001a88: d0af beq.n 100019ea <_ntoa_format+0x8a> +10001a8a: 2658 movs r6, #88 @ 0x58 +10001a8c: f808 6004 strb.w r6, [r8, r4] +10001a90: 3401 adds r4, #1 +10001a92: e7a8 b.n 100019e6 <_ntoa_format+0x86> +10001a94: 2c20 cmp r4, #32 +10001a96: d0a8 beq.n 100019ea <_ntoa_format+0x8a> +10001a98: 4626 mov r6, r4 +10001a9a: 3401 adds r4, #1 +10001a9c: e007 b.n 10001aae <_ntoa_format+0x14e> +10001a9e: 1e66 subs r6, r4, #1 +10001aa0: d0b9 beq.n 10001a16 <_ntoa_format+0xb6> +10001aa2: f1b9 0f10 cmp.w r9, #16 +10001aa6: d036 beq.n 10001b16 <_ntoa_format+0x1b6> +10001aa8: f1b9 0f02 cmp.w r9, #2 +10001aac: d1c9 bne.n 10001a42 <_ntoa_format+0xe2> +10001aae: f04f 0c62 mov.w ip, #98 @ 0x62 +10001ab2: f808 c006 strb.w ip, [r8, r6] +10001ab6: e796 b.n 100019e6 <_ntoa_format+0x86> +10001ab8: f017 0f10 tst.w r7, #16 +10001abc: d0c5 beq.n 10001a4a <_ntoa_format+0xea> +10001abe: f417 6f80 tst.w r7, #1024 @ 0x400 +10001ac2: d086 beq.n 100019d2 <_ntoa_format+0x72> +10001ac4: e789 b.n 100019da <_ntoa_format+0x7a> +10001ac6: 073e lsls r6, r7, #28 +10001ac8: d590 bpl.n 100019ec <_ntoa_format+0x8c> +10001aca: 2620 movs r6, #32 +10001acc: f808 6004 strb.w r6, [r8, r4] +10001ad0: 3401 adds r4, #1 +10001ad2: e78b b.n 100019ec <_ntoa_format+0x8c> +10001ad4: f017 0f0c tst.w r7, #12 +10001ad8: d000 beq.n 10001adc <_ntoa_format+0x17c> +10001ada: 3d01 subs r5, #1 +10001adc: 42b4 cmp r4, r6 +10001ade: f4ff af52 bcc.w 10001986 <_ntoa_format+0x26> +10001ae2: e761 b.n 100019a8 <_ntoa_format+0x48> +10001ae4: 06bc lsls r4, r7, #26 +10001ae6: d412 bmi.n 10001b0e <_ntoa_format+0x1ae> +10001ae8: 2478 movs r4, #120 @ 0x78 +10001aea: f888 4000 strb.w r4, [r8] +10001aee: 2430 movs r4, #48 @ 0x30 +10001af0: f888 4001 strb.w r4, [r8, #1] +10001af4: 2402 movs r4, #2 +10001af6: f1ba 0f00 cmp.w sl, #0 +10001afa: d099 beq.n 10001a30 <_ntoa_format+0xd0> +10001afc: e7aa b.n 10001a54 <_ntoa_format+0xf4> +10001afe: 2c20 cmp r4, #32 +10001b00: f43f af73 beq.w 100019ea <_ntoa_format+0x8a> +10001b04: 2678 movs r6, #120 @ 0x78 +10001b06: f808 6004 strb.w r6, [r8, r4] +10001b0a: 3401 adds r4, #1 +10001b0c: e76b b.n 100019e6 <_ntoa_format+0x86> +10001b0e: 2458 movs r4, #88 @ 0x58 +10001b10: e7eb b.n 10001aea <_ntoa_format+0x18a> +10001b12: 2462 movs r4, #98 @ 0x62 +10001b14: e7e9 b.n 10001aea <_ntoa_format+0x18a> +10001b16: f017 0f20 tst.w r7, #32 +10001b1a: f1a4 0c02 sub.w ip, r4, #2 +10001b1e: d004 beq.n 10001b2a <_ntoa_format+0x1ca> +10001b20: f04f 0e58 mov.w lr, #88 @ 0x58 +10001b24: f808 e00c strb.w lr, [r8, ip] +10001b28: e78b b.n 10001a42 <_ntoa_format+0xe2> +10001b2a: f04f 0e78 mov.w lr, #120 @ 0x78 +10001b2e: f808 e00c strb.w lr, [r8, ip] +10001b32: e786 b.n 10001a42 <_ntoa_format+0xe2> + +10001b34 <_out_char>: +10001b34: b900 cbnz r0, 10001b38 <_out_char+0x4> +10001b36: 4770 bx lr +10001b38: f001 bb88 b.w 1000324c <__wrap_putchar> + +10001b3c <_out_fct>: +10001b3c: b110 cbz r0, 10001b44 <_out_fct+0x8> +10001b3e: e9d1 3100 ldrd r3, r1, [r1] +10001b42: 4718 bx r3 +10001b44: 4770 bx lr +10001b46: bf00 nop + +10001b48 <_ftoa>: +10001b48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001b4c: b097 sub sp, #92 @ 0x5c +10001b4e: ed9d 7b20 vldr d7, [sp, #128] @ 0x80 +10001b52: e9dd 5b22 ldrd r5, fp, [sp, #136] @ 0x88 +10001b56: 4607 mov r7, r0 +10001b58: 4688 mov r8, r1 +10001b5a: ec51 0b17 vmov r0, r1, d7 +10001b5e: 9c24 ldr r4, [sp, #144] @ 0x90 +10001b60: 4699 mov r9, r3 +10001b62: 920c str r2, [sp, #48] @ 0x30 +10001b64: 460b mov r3, r1 +10001b66: 4602 mov r2, r0 +10001b68: ed8d 7b04 vstr d7, [sp, #16] +10001b6c: 9407 str r4, [sp, #28] +10001b6e: f7ff fe31 bl 100017d4 <__wrap___aeabi_dcmpun> +10001b72: 2800 cmp r0, #0 +10001b74: f040 81f4 bne.w 10001f60 <_ftoa+0x418> +10001b78: e9dd 0104 ldrd r0, r1, [sp, #16] +10001b7c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001b80: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10001b84: f7ff fe38 bl 100017f8 <__wrap___aeabi_dcmplt> +10001b88: 2800 cmp r0, #0 +10001b8a: f040 811b bne.w 10001dc4 <_ftoa+0x27c> +10001b8e: e9dd 0104 ldrd r0, r1, [sp, #16] +10001b92: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10001b96: 4bac ldr r3, [pc, #688] @ (10001e48 <_ftoa+0x300>) +10001b98: f7ff fe6a bl 10001870 <__wrap___aeabi_dcmpgt> +10001b9c: 2800 cmp r0, #0 +10001b9e: f040 80ee bne.w 10001d7e <_ftoa+0x236> +10001ba2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001ba6: a3a4 add r3, pc, #656 @ (adr r3, 10001e38 <_ftoa+0x2f0>) +10001ba8: e9d3 2300 ldrd r2, r3, [r3] +10001bac: f7ff fe60 bl 10001870 <__wrap___aeabi_dcmpgt> +10001bb0: 2800 cmp r0, #0 +10001bb2: f040 80d3 bne.w 10001d5c <_ftoa+0x214> +10001bb6: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bba: a3a1 add r3, pc, #644 @ (adr r3, 10001e40 <_ftoa+0x2f8>) +10001bbc: e9d3 2300 ldrd r2, r3, [r3] +10001bc0: f7ff fe1a bl 100017f8 <__wrap___aeabi_dcmplt> +10001bc4: 2800 cmp r0, #0 +10001bc6: f040 80c9 bne.w 10001d5c <_ftoa+0x214> +10001bca: e9dd 0104 ldrd r0, r1, [sp, #16] +10001bce: 2200 movs r2, #0 +10001bd0: 2300 movs r3, #0 +10001bd2: f7ff fe11 bl 100017f8 <__wrap___aeabi_dcmplt> +10001bd6: 2800 cmp r0, #0 +10001bd8: f040 80e8 bne.w 10001dac <_ftoa+0x264> +10001bdc: 4623 mov r3, r4 +10001bde: 900d str r0, [sp, #52] @ 0x34 +10001be0: f413 6f80 tst.w r3, #1024 @ 0x400 +10001be4: bf08 it eq +10001be6: 2506 moveq r5, #6 +10001be8: 2130 movs r1, #48 @ 0x30 +10001bea: 462b mov r3, r5 +10001bec: aa0e add r2, sp, #56 @ 0x38 +10001bee: f1a5 0620 sub.w r6, r5, #32 +10001bf2: e005 b.n 10001c00 <_ftoa+0xb8> +10001bf4: 3b01 subs r3, #1 +10001bf6: 42b3 cmp r3, r6 +10001bf8: f802 1b01 strb.w r1, [r2], #1 +10001bfc: f000 8193 beq.w 10001f26 <_ftoa+0x3de> +10001c00: 2b09 cmp r3, #9 +10001c02: d8f7 bhi.n 10001bf4 <_ftoa+0xac> +10001c04: 461e mov r6, r3 +10001c06: 1aed subs r5, r5, r3 +10001c08: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c0c: f7ff fdbe bl 1000178c <__wrap___aeabi_d2iz> +10001c10: 4b8e ldr r3, [pc, #568] @ (10001e4c <_ftoa+0x304>) +10001c12: 4604 mov r4, r0 +10001c14: eb03 03c6 add.w r3, r3, r6, lsl #3 +10001c18: ed93 7b00 vldr d7, [r3] +10001c1c: ed8d 7b08 vstr d7, [sp, #32] +10001c20: f7ff fd90 bl 10001744 <__wrap___aeabi_i2d> +10001c24: 4602 mov r2, r0 +10001c26: 460b mov r3, r1 +10001c28: e9dd 0104 ldrd r0, r1, [sp, #16] +10001c2c: f7ff fd02 bl 10001634 <__wrap___aeabi_dsub> +10001c30: e9dd 2308 ldrd r2, r3, [sp, #32] +10001c34: f7ff fd12 bl 1000165c <__wrap___aeabi_dmul> +10001c38: 4602 mov r2, r0 +10001c3a: 460b mov r3, r1 +10001c3c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001c40: f7ff fdb6 bl 100017b0 <__wrap___aeabi_d2uiz> +10001c44: 4682 mov sl, r0 +10001c46: f7ff fd8f bl 10001768 <__wrap___aeabi_ui2d> +10001c4a: 4602 mov r2, r0 +10001c4c: 460b mov r3, r1 +10001c4e: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001c52: f7ff fcef bl 10001634 <__wrap___aeabi_dsub> +10001c56: 4602 mov r2, r0 +10001c58: 460b mov r3, r1 +10001c5a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 +10001c5e: 2200 movs r2, #0 +10001c60: 4b7b ldr r3, [pc, #492] @ (10001e50 <_ftoa+0x308>) +10001c62: f7ff fe05 bl 10001870 <__wrap___aeabi_dcmpgt> +10001c66: 2800 cmp r0, #0 +10001c68: f000 80fe beq.w 10001e68 <_ftoa+0x320> +10001c6c: f10a 0a01 add.w sl, sl, #1 +10001c70: 4650 mov r0, sl +10001c72: f7ff fd79 bl 10001768 <__wrap___aeabi_ui2d> +10001c76: 4602 mov r2, r0 +10001c78: 460b mov r3, r1 +10001c7a: e9dd 0108 ldrd r0, r1, [sp, #32] +10001c7e: f7ff fdcf bl 10001820 <__wrap___aeabi_dcmple> +10001c82: b110 cbz r0, 10001c8a <_ftoa+0x142> +10001c84: f04f 0a00 mov.w sl, #0 +10001c88: 3401 adds r4, #1 +10001c8a: 2e00 cmp r6, #0 +10001c8c: f000 80fd beq.w 10001e8a <_ftoa+0x342> +10001c90: 1e68 subs r0, r5, #1 +10001c92: ab0e add r3, sp, #56 @ 0x38 +10001c94: f8df c1cc ldr.w ip, [pc, #460] @ 10001e64 <_ftoa+0x31c> +10001c98: 4418 add r0, r3 +10001c9a: e00f b.n 10001cbc <_ftoa+0x174> +10001c9c: fbac 210a umull r2, r1, ip, sl +10001ca0: 08c9 lsrs r1, r1, #3 +10001ca2: eb01 0281 add.w r2, r1, r1, lsl #2 +10001ca6: ebaa 0242 sub.w r2, sl, r2, lsl #1 +10001caa: 3230 adds r2, #48 @ 0x30 +10001cac: f1ba 0f09 cmp.w sl, #9 +10001cb0: f800 2f01 strb.w r2, [r0, #1]! +10001cb4: f240 811c bls.w 10001ef0 <_ftoa+0x3a8> +10001cb8: 468a mov sl, r1 +10001cba: 461d mov r5, r3 +10001cbc: 2d20 cmp r5, #32 +10001cbe: f105 0301 add.w r3, r5, #1 +10001cc2: f106 36ff add.w r6, r6, #4294967295 @ 0xffffffff +10001cc6: d1e9 bne.n 10001c9c <_ftoa+0x154> +10001cc8: 2520 movs r5, #32 +10001cca: 1e69 subs r1, r5, #1 +10001ccc: ab0e add r3, sp, #56 @ 0x38 +10001cce: 4861 ldr r0, [pc, #388] @ (10001e54 <_ftoa+0x30c>) +10001cd0: 4419 add r1, r3 +10001cd2: e010 b.n 10001cf6 <_ftoa+0x1ae> +10001cd4: fb80 6204 smull r6, r2, r0, r4 +10001cd8: ebc3 03a2 rsb r3, r3, r2, asr #2 +10001cdc: eb03 0283 add.w r2, r3, r3, lsl #2 +10001ce0: eba4 0442 sub.w r4, r4, r2, lsl #1 +10001ce4: f104 0230 add.w r2, r4, #48 @ 0x30 +10001ce8: 3501 adds r5, #1 +10001cea: 461c mov r4, r3 +10001cec: f801 2f01 strb.w r2, [r1, #1]! +10001cf0: 2b00 cmp r3, #0 +10001cf2: f000 80eb beq.w 10001ecc <_ftoa+0x384> +10001cf6: 2d20 cmp r5, #32 +10001cf8: ea4f 73e4 mov.w r3, r4, asr #31 +10001cfc: d1ea bne.n 10001cd4 <_ftoa+0x18c> +10001cfe: 9b07 ldr r3, [sp, #28] +10001d00: f003 0303 and.w r3, r3, #3 +10001d04: 2b01 cmp r3, #1 +10001d06: d118 bne.n 10001d3a <_ftoa+0x1f2> +10001d08: f1bb 0f00 cmp.w fp, #0 +10001d0c: d015 beq.n 10001d3a <_ftoa+0x1f2> +10001d0e: 9b0d ldr r3, [sp, #52] @ 0x34 +10001d10: 2b00 cmp r3, #0 +10001d12: f000 810a beq.w 10001f2a <_ftoa+0x3e2> +10001d16: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001d1a: f1bb 0f20 cmp.w fp, #32 +10001d1e: d90c bls.n 10001d3a <_ftoa+0x1f2> +10001d20: 1e6b subs r3, r5, #1 +10001d22: a90e add r1, sp, #56 @ 0x38 +10001d24: 2230 movs r2, #48 @ 0x30 +10001d26: 440b add r3, r1 +10001d28: e005 b.n 10001d36 <_ftoa+0x1ee> +10001d2a: 3501 adds r5, #1 +10001d2c: 455d cmp r5, fp +10001d2e: f803 2f01 strb.w r2, [r3, #1]! +10001d32: f080 80d1 bcs.w 10001ed8 <_ftoa+0x390> +10001d36: 2d20 cmp r5, #32 +10001d38: d1f7 bne.n 10001d2a <_ftoa+0x1e2> +10001d3a: 9b07 ldr r3, [sp, #28] +10001d3c: ac0e add r4, sp, #56 @ 0x38 +10001d3e: e9cd b302 strd fp, r3, [sp, #8] +10001d42: 4641 mov r1, r8 +10001d44: 464b mov r3, r9 +10001d46: 4638 mov r0, r7 +10001d48: 9a0c ldr r2, [sp, #48] @ 0x30 +10001d4a: 9501 str r5, [sp, #4] +10001d4c: 9400 str r4, [sp, #0] +10001d4e: f7ff fdb9 bl 100018c4 <_out_rev> +10001d52: 4682 mov sl, r0 +10001d54: 4650 mov r0, sl +10001d56: b017 add sp, #92 @ 0x5c +10001d58: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10001d5c: 9b07 ldr r3, [sp, #28] +10001d5e: ed9d 7b04 vldr d7, [sp, #16] +10001d62: e9cd b323 strd fp, r3, [sp, #140] @ 0x8c +10001d66: 4641 mov r1, r8 +10001d68: 464b mov r3, r9 +10001d6a: 4638 mov r0, r7 +10001d6c: 9a0c ldr r2, [sp, #48] @ 0x30 +10001d6e: ed8d 7b20 vstr d7, [sp, #128] @ 0x80 +10001d72: 9522 str r5, [sp, #136] @ 0x88 +10001d74: b017 add sp, #92 @ 0x5c +10001d76: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001d7a: f000 b945 b.w 10002008 <_etoa> +10001d7e: 0761 lsls r1, r4, #29 +10001d80: 4623 mov r3, r4 +10001d82: bf4c ite mi +10001d84: 2304 movmi r3, #4 +10001d86: 2303 movpl r3, #3 +10001d88: 4641 mov r1, r8 +10001d8a: 9321 str r3, [sp, #132] @ 0x84 +10001d8c: 4638 mov r0, r7 +10001d8e: 464b mov r3, r9 +10001d90: 9a07 ldr r2, [sp, #28] +10001d92: bf48 it mi +10001d94: 4c30 ldrmi r4, [pc, #192] @ (10001e58 <_ftoa+0x310>) +10001d96: e9cd b222 strd fp, r2, [sp, #136] @ 0x88 +10001d9a: bf58 it pl +10001d9c: 4c2f ldrpl r4, [pc, #188] @ (10001e5c <_ftoa+0x314>) +10001d9e: 9a0c ldr r2, [sp, #48] @ 0x30 +10001da0: 9420 str r4, [sp, #128] @ 0x80 +10001da2: b017 add sp, #92 @ 0x5c +10001da4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10001da8: f7ff bd8c b.w 100018c4 <_out_rev> +10001dac: e9dd 2304 ldrd r2, r3, [sp, #16] +10001db0: 2000 movs r0, #0 +10001db2: 2100 movs r1, #0 +10001db4: f7ff fc3e bl 10001634 <__wrap___aeabi_dsub> +10001db8: 2301 movs r3, #1 +10001dba: e9cd 0104 strd r0, r1, [sp, #16] +10001dbe: 930d str r3, [sp, #52] @ 0x34 +10001dc0: 4623 mov r3, r4 +10001dc2: e70d b.n 10001be0 <_ftoa+0x98> +10001dc4: 4623 mov r3, r4 +10001dc6: 079c lsls r4, r3, #30 +10001dc8: f040 80aa bne.w 10001f20 <_ftoa+0x3d8> +10001dcc: f1bb 0f04 cmp.w fp, #4 +10001dd0: f240 80a6 bls.w 10001f20 <_ftoa+0x3d8> +10001dd4: 9b0c ldr r3, [sp, #48] @ 0x30 +10001dd6: 461d mov r5, r3 +10001dd8: 1f1c subs r4, r3, #4 +10001dda: eb04 0a0b add.w sl, r4, fp +10001dde: 462a mov r2, r5 +10001de0: 464b mov r3, r9 +10001de2: 4641 mov r1, r8 +10001de4: 2020 movs r0, #32 +10001de6: 3501 adds r5, #1 +10001de8: 47b8 blx r7 +10001dea: 45aa cmp sl, r5 +10001dec: d1f7 bne.n 10001dde <_ftoa+0x296> +10001dee: 4655 mov r5, sl +10001df0: 4c1b ldr r4, [pc, #108] @ (10001e60 <_ftoa+0x318>) +10001df2: 1f26 subs r6, r4, #4 +10001df4: f814 0d01 ldrb.w r0, [r4, #-1]! +10001df8: 462a mov r2, r5 +10001dfa: 464b mov r3, r9 +10001dfc: 4641 mov r1, r8 +10001dfe: 47b8 blx r7 +10001e00: 42b4 cmp r4, r6 +10001e02: f105 0501 add.w r5, r5, #1 +10001e06: d1f5 bne.n 10001df4 <_ftoa+0x2ac> +10001e08: 9b07 ldr r3, [sp, #28] +10001e0a: f10a 0a04 add.w sl, sl, #4 +10001e0e: 0798 lsls r0, r3, #30 +10001e10: d5a0 bpl.n 10001d54 <_ftoa+0x20c> +10001e12: 9c0c ldr r4, [sp, #48] @ 0x30 +10001e14: ebaa 0304 sub.w r3, sl, r4 +10001e18: 459b cmp fp, r3 +10001e1a: d99b bls.n 10001d54 <_ftoa+0x20c> +10001e1c: 4652 mov r2, sl +10001e1e: 464b mov r3, r9 +10001e20: 4641 mov r1, r8 +10001e22: 2020 movs r0, #32 +10001e24: f10a 0a01 add.w sl, sl, #1 +10001e28: 47b8 blx r7 +10001e2a: ebaa 0304 sub.w r3, sl, r4 +10001e2e: 455b cmp r3, fp +10001e30: d3f4 bcc.n 10001e1c <_ftoa+0x2d4> +10001e32: e78f b.n 10001d54 <_ftoa+0x20c> +10001e34: f3af 8000 nop.w +10001e38: 00000000 .word 0x00000000 +10001e3c: 41cdcd65 .word 0x41cdcd65 +10001e40: 00000000 .word 0x00000000 +10001e44: c1cdcd65 .word 0xc1cdcd65 +10001e48: 7fefffff .word 0x7fefffff +10001e4c: 100060c8 .word 0x100060c8 +10001e50: 3fe00000 .word 0x3fe00000 +10001e54: 66666667 .word 0x66666667 +10001e58: 10005fd8 .word 0x10005fd8 +10001e5c: 10005fe0 .word 0x10005fe0 +10001e60: 10005fec .word 0x10005fec +10001e64: cccccccd .word 0xcccccccd +10001e68: 2200 movs r2, #0 +10001e6a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10001e6e: 4b63 ldr r3, [pc, #396] @ (10001ffc <_ftoa+0x4b4>) +10001e70: f7ff fcc2 bl 100017f8 <__wrap___aeabi_dcmplt> +10001e74: 2800 cmp r0, #0 +10001e76: f47f af08 bne.w 10001c8a <_ftoa+0x142> +10001e7a: f1ba 0f00 cmp.w sl, #0 +10001e7e: d16a bne.n 10001f56 <_ftoa+0x40e> +10001e80: f10a 0a01 add.w sl, sl, #1 +10001e84: 2e00 cmp r6, #0 +10001e86: f47f af03 bne.w 10001c90 <_ftoa+0x148> +10001e8a: 4620 mov r0, r4 +10001e8c: f7ff fc5a bl 10001744 <__wrap___aeabi_i2d> +10001e90: 4602 mov r2, r0 +10001e92: 460b mov r3, r1 +10001e94: e9dd 0104 ldrd r0, r1, [sp, #16] +10001e98: f7ff fbcc bl 10001634 <__wrap___aeabi_dsub> +10001e9c: 4602 mov r2, r0 +10001e9e: 460b mov r3, r1 +10001ea0: e9cd 2304 strd r2, r3, [sp, #16] +10001ea4: 2200 movs r2, #0 +10001ea6: 4b55 ldr r3, [pc, #340] @ (10001ffc <_ftoa+0x4b4>) +10001ea8: f7ff fca6 bl 100017f8 <__wrap___aeabi_dcmplt> +10001eac: 2800 cmp r0, #0 +10001eae: f47f af0c bne.w 10001cca <_ftoa+0x182> +10001eb2: e9dd 0104 ldrd r0, r1, [sp, #16] +10001eb6: 2200 movs r2, #0 +10001eb8: 4b50 ldr r3, [pc, #320] @ (10001ffc <_ftoa+0x4b4>) +10001eba: f7ff fcd9 bl 10001870 <__wrap___aeabi_dcmpgt> +10001ebe: 2800 cmp r0, #0 +10001ec0: f47f af03 bne.w 10001cca <_ftoa+0x182> +10001ec4: 3401 adds r4, #1 +10001ec6: f024 0401 bic.w r4, r4, #1 +10001eca: e6fe b.n 10001cca <_ftoa+0x182> +10001ecc: 9b07 ldr r3, [sp, #28] +10001ece: f003 0303 and.w r3, r3, #3 +10001ed2: 2b01 cmp r3, #1 +10001ed4: f000 8082 beq.w 10001fdc <_ftoa+0x494> +10001ed8: 2d20 cmp r5, #32 +10001eda: f43f af2e beq.w 10001d3a <_ftoa+0x1f2> +10001ede: 9b0d ldr r3, [sp, #52] @ 0x34 +10001ee0: b37b cbz r3, 10001f42 <_ftoa+0x3fa> +10001ee2: 222d movs r2, #45 @ 0x2d +10001ee4: eb0d 0305 add.w r3, sp, r5 +10001ee8: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001eec: 3501 adds r5, #1 +10001eee: e724 b.n 10001d3a <_ftoa+0x1f2> +10001ef0: 2b20 cmp r3, #32 +10001ef2: f43f aee9 beq.w 10001cc8 <_ftoa+0x180> +10001ef6: aa0e add r2, sp, #56 @ 0x38 +10001ef8: 4415 add r5, r2 +10001efa: 441e add r6, r3 +10001efc: 2230 movs r2, #48 @ 0x30 +10001efe: e004 b.n 10001f0a <_ftoa+0x3c2> +10001f00: 2b20 cmp r3, #32 +10001f02: f805 2f01 strb.w r2, [r5, #1]! +10001f06: f43f aedf beq.w 10001cc8 <_ftoa+0x180> +10001f0a: 429e cmp r6, r3 +10001f0c: f103 0301 add.w r3, r3, #1 +10001f10: d1f6 bne.n 10001f00 <_ftoa+0x3b8> +10001f12: 222e movs r2, #46 @ 0x2e +10001f14: eb0d 0306 add.w r3, sp, r6 +10001f18: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10001f1c: 1c75 adds r5, r6, #1 +10001f1e: e6d4 b.n 10001cca <_ftoa+0x182> +10001f20: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001f24: e763 b.n 10001dee <_ftoa+0x2a6> +10001f26: 2520 movs r5, #32 +10001f28: e66e b.n 10001c08 <_ftoa+0xc0> +10001f2a: 9b07 ldr r3, [sp, #28] +10001f2c: f013 0f0c tst.w r3, #12 +10001f30: d050 beq.n 10001fd4 <_ftoa+0x48c> +10001f32: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001f36: 45ab cmp fp, r5 +10001f38: f63f aef2 bhi.w 10001d20 <_ftoa+0x1d8> +10001f3c: 2d20 cmp r5, #32 +10001f3e: f43f aefc beq.w 10001d3a <_ftoa+0x1f2> +10001f42: 9b07 ldr r3, [sp, #28] +10001f44: 075a lsls r2, r3, #29 +10001f46: d501 bpl.n 10001f4c <_ftoa+0x404> +10001f48: 222b movs r2, #43 @ 0x2b +10001f4a: e7cb b.n 10001ee4 <_ftoa+0x39c> +10001f4c: 071b lsls r3, r3, #28 +10001f4e: f57f aef4 bpl.w 10001d3a <_ftoa+0x1f2> +10001f52: 2220 movs r2, #32 +10001f54: e7c6 b.n 10001ee4 <_ftoa+0x39c> +10001f56: f01a 0f01 tst.w sl, #1 +10001f5a: f43f ae96 beq.w 10001c8a <_ftoa+0x142> +10001f5e: e78f b.n 10001e80 <_ftoa+0x338> +10001f60: 07a6 lsls r6, r4, #30 +10001f62: d134 bne.n 10001fce <_ftoa+0x486> +10001f64: f1bb 0f03 cmp.w fp, #3 +10001f68: d931 bls.n 10001fce <_ftoa+0x486> +10001f6a: 9b0c ldr r3, [sp, #48] @ 0x30 +10001f6c: 461d mov r5, r3 +10001f6e: 1edc subs r4, r3, #3 +10001f70: eb04 0a0b add.w sl, r4, fp +10001f74: 462a mov r2, r5 +10001f76: 464b mov r3, r9 +10001f78: 4641 mov r1, r8 +10001f7a: 2020 movs r0, #32 +10001f7c: 3501 adds r5, #1 +10001f7e: 47b8 blx r7 +10001f80: 4555 cmp r5, sl +10001f82: d1f7 bne.n 10001f74 <_ftoa+0x42c> +10001f84: 4655 mov r5, sl +10001f86: 4c1e ldr r4, [pc, #120] @ (10002000 <_ftoa+0x4b8>) +10001f88: 1ee6 subs r6, r4, #3 +10001f8a: f814 0d01 ldrb.w r0, [r4, #-1]! +10001f8e: 462a mov r2, r5 +10001f90: 464b mov r3, r9 +10001f92: 4641 mov r1, r8 +10001f94: 47b8 blx r7 +10001f96: 42a6 cmp r6, r4 +10001f98: f105 0501 add.w r5, r5, #1 +10001f9c: d1f5 bne.n 10001f8a <_ftoa+0x442> +10001f9e: 9b07 ldr r3, [sp, #28] +10001fa0: f10a 0a03 add.w sl, sl, #3 +10001fa4: 079d lsls r5, r3, #30 +10001fa6: f57f aed5 bpl.w 10001d54 <_ftoa+0x20c> +10001faa: 9c0c ldr r4, [sp, #48] @ 0x30 +10001fac: ebaa 0304 sub.w r3, sl, r4 +10001fb0: 459b cmp fp, r3 +10001fb2: f67f aecf bls.w 10001d54 <_ftoa+0x20c> +10001fb6: 4652 mov r2, sl +10001fb8: 464b mov r3, r9 +10001fba: 4641 mov r1, r8 +10001fbc: 2020 movs r0, #32 +10001fbe: f10a 0a01 add.w sl, sl, #1 +10001fc2: 47b8 blx r7 +10001fc4: ebaa 0304 sub.w r3, sl, r4 +10001fc8: 459b cmp fp, r3 +10001fca: d8f4 bhi.n 10001fb6 <_ftoa+0x46e> +10001fcc: e6c2 b.n 10001d54 <_ftoa+0x20c> +10001fce: f8dd a030 ldr.w sl, [sp, #48] @ 0x30 +10001fd2: e7d7 b.n 10001f84 <_ftoa+0x43c> +10001fd4: 45ab cmp fp, r5 +10001fd6: f63f aea3 bhi.w 10001d20 <_ftoa+0x1d8> +10001fda: e6ae b.n 10001d3a <_ftoa+0x1f2> +10001fdc: f1bb 0f00 cmp.w fp, #0 +10001fe0: f43f af7a beq.w 10001ed8 <_ftoa+0x390> +10001fe4: 9b0d ldr r3, [sp, #52] @ 0x34 +10001fe6: 2b00 cmp r3, #0 +10001fe8: d09f beq.n 10001f2a <_ftoa+0x3e2> +10001fea: f10b 3bff add.w fp, fp, #4294967295 @ 0xffffffff +10001fee: 455d cmp r5, fp +10001ff0: f4ff ae96 bcc.w 10001d20 <_ftoa+0x1d8> +10001ff4: 2d20 cmp r5, #32 +10001ff6: f47f af74 bne.w 10001ee2 <_ftoa+0x39a> +10001ffa: e69e b.n 10001d3a <_ftoa+0x1f2> +10001ffc: 3fe00000 .word 0x3fe00000 +10002000: 10005fe7 .word 0x10005fe7 +10002004: 00000000 .word 0x00000000 + +10002008 <_etoa>: +10002008: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000200c: b09f sub sp, #124 @ 0x7c +1000200e: 9e2a ldr r6, [sp, #168] @ 0xa8 +10002010: e9dd 4528 ldrd r4, r5, [sp, #160] @ 0xa0 +10002014: 4607 mov r7, r0 +10002016: 4693 mov fp, r2 +10002018: 9108 str r1, [sp, #32] +1000201a: 9309 str r3, [sp, #36] @ 0x24 +1000201c: 4622 mov r2, r4 +1000201e: 462b mov r3, r5 +10002020: 4620 mov r0, r4 +10002022: 4629 mov r1, r5 +10002024: 960e str r6, [sp, #56] @ 0x38 +10002026: e9dd a62b ldrd sl, r6, [sp, #172] @ 0xac +1000202a: f7ff fbd3 bl 100017d4 <__wrap___aeabi_dcmpun> +1000202e: 2800 cmp r0, #0 +10002030: f040 80be bne.w 100021b0 <_etoa+0x1a8> +10002034: 4620 mov r0, r4 +10002036: 4629 mov r1, r5 +10002038: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +1000203c: 4b78 ldr r3, [pc, #480] @ (10002220 <_etoa+0x218>) +1000203e: f7ff fc17 bl 10001870 <__wrap___aeabi_dcmpgt> +10002042: 2800 cmp r0, #0 +10002044: f040 80b4 bne.w 100021b0 <_etoa+0x1a8> +10002048: 4620 mov r0, r4 +1000204a: 4629 mov r1, r5 +1000204c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002050: f46f 1380 mvn.w r3, #1048576 @ 0x100000 +10002054: f7ff fbd0 bl 100017f8 <__wrap___aeabi_dcmplt> +10002058: 2800 cmp r0, #0 +1000205a: f040 80a9 bne.w 100021b0 <_etoa+0x1a8> +1000205e: 4620 mov r0, r4 +10002060: 4629 mov r1, r5 +10002062: 2200 movs r2, #0 +10002064: 2300 movs r3, #0 +10002066: f7ff fbc7 bl 100017f8 <__wrap___aeabi_dcmplt> +1000206a: 2800 cmp r0, #0 +1000206c: f040 81d5 bne.w 1000241a <_etoa+0x412> +10002070: e9cd 450a strd r4, r5, [sp, #40] @ 0x28 +10002074: e9dd 230a ldrd r2, r3, [sp, #40] @ 0x28 +10002078: 4690 mov r8, r2 +1000207a: 4699 mov r9, r3 +1000207c: f406 6200 and.w r2, r6, #2048 @ 0x800 +10002080: f416 6380 ands.w r3, r6, #1024 @ 0x400 +10002084: 920f str r2, [sp, #60] @ 0x3c +10002086: 9313 str r3, [sp, #76] @ 0x4c +10002088: f040 80a1 bne.w 100021ce <_etoa+0x1c6> +1000208c: ea58 0309 orrs.w r3, r8, r9 +10002090: f040 80ca bne.w 10002228 <_etoa+0x220> +10002094: 2a00 cmp r2, #0 +10002096: f040 81e3 bne.w 10002460 <_etoa+0x458> +1000209a: 2306 movs r3, #6 +1000209c: 930e str r3, [sp, #56] @ 0x38 +1000209e: f016 0202 ands.w r2, r6, #2 +100020a2: 9210 str r2, [sp, #64] @ 0x40 +100020a4: f040 81d4 bne.w 10002450 <_etoa+0x448> +100020a8: 4653 mov r3, sl +100020aa: 2b04 cmp r3, #4 +100020ac: bf38 it cc +100020ae: 2304 movcc r3, #4 +100020b0: 920c str r2, [sp, #48] @ 0x30 +100020b2: 2204 movs r2, #4 +100020b4: 3b04 subs r3, #4 +100020b6: 9212 str r2, [sp, #72] @ 0x48 +100020b8: 930f str r3, [sp, #60] @ 0x3c +100020ba: 4620 mov r0, r4 +100020bc: 4629 mov r1, r5 +100020be: 2200 movs r2, #0 +100020c0: 2300 movs r3, #0 +100020c2: f7ff fb99 bl 100017f8 <__wrap___aeabi_dcmplt> +100020c6: 2800 cmp r0, #0 +100020c8: f040 81f3 bne.w 100024b2 <_etoa+0x4aa> +100020cc: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +100020d0: 9b0f ldr r3, [sp, #60] @ 0x3c +100020d2: 465a mov r2, fp +100020d4: 9303 str r3, [sp, #12] +100020d6: 9b0e ldr r3, [sp, #56] @ 0x38 +100020d8: ed8d 7b00 vstr d7, [sp] +100020dc: 9302 str r3, [sp, #8] +100020de: f426 6300 bic.w r3, r6, #2048 @ 0x800 +100020e2: 9304 str r3, [sp, #16] +100020e4: 4638 mov r0, r7 +100020e6: 9b09 ldr r3, [sp, #36] @ 0x24 +100020e8: 9908 ldr r1, [sp, #32] +100020ea: f7ff fd2d bl 10001b48 <_ftoa> +100020ee: 4602 mov r2, r0 +100020f0: f016 0f20 tst.w r6, #32 +100020f4: 9b09 ldr r3, [sp, #36] @ 0x24 +100020f6: 9908 ldr r1, [sp, #32] +100020f8: bf0c ite eq +100020fa: 2065 moveq r0, #101 @ 0x65 +100020fc: 2045 movne r0, #69 @ 0x45 +100020fe: f102 0801 add.w r8, r2, #1 +10002102: 47b8 blx r7 +10002104: 9a0c ldr r2, [sp, #48] @ 0x30 +10002106: 9b12 ldr r3, [sp, #72] @ 0x48 +10002108: ac16 add r4, sp, #88 @ 0x58 +1000210a: 1e5d subs r5, r3, #1 +1000210c: ea82 73e2 eor.w r3, r2, r2, asr #31 +10002110: eba3 73e2 sub.w r3, r3, r2, asr #31 +10002114: 0fd1 lsrs r1, r2, #31 +10002116: 2600 movs r6, #0 +10002118: 4622 mov r2, r4 +1000211a: 4699 mov r9, r3 +1000211c: f8df c104 ldr.w ip, [pc, #260] @ 10002224 <_etoa+0x21c> +10002120: e001 b.n 10002126 <_etoa+0x11e> +10002122: 2e20 cmp r6, #32 +10002124: d010 beq.n 10002148 <_etoa+0x140> +10002126: 46ce mov lr, r9 +10002128: fbac 3009 umull r3, r0, ip, r9 +1000212c: 08c0 lsrs r0, r0, #3 +1000212e: eb00 0380 add.w r3, r0, r0, lsl #2 +10002132: eba9 0343 sub.w r3, r9, r3, lsl #1 +10002136: 3330 adds r3, #48 @ 0x30 +10002138: f1be 0f09 cmp.w lr, #9 +1000213c: 4681 mov r9, r0 +1000213e: f106 0601 add.w r6, r6, #1 +10002142: f802 3b01 strb.w r3, [r2], #1 +10002146: d8ec bhi.n 10002122 <_etoa+0x11a> +10002148: 2305 movs r3, #5 +1000214a: 2000 movs r0, #0 +1000214c: 9306 str r3, [sp, #24] +1000214e: 230a movs r3, #10 +10002150: 9505 str r5, [sp, #20] +10002152: 9400 str r4, [sp, #0] +10002154: 9d09 ldr r5, [sp, #36] @ 0x24 +10002156: 9c08 ldr r4, [sp, #32] +10002158: 4642 mov r2, r8 +1000215a: e9cd 3003 strd r3, r0, [sp, #12] +1000215e: e9cd 6101 strd r6, r1, [sp, #4] +10002162: 462b mov r3, r5 +10002164: 4621 mov r1, r4 +10002166: 4638 mov r0, r7 +10002168: f7ff fbfa bl 10001960 <_ntoa_format> +1000216c: 9a10 ldr r2, [sp, #64] @ 0x40 +1000216e: 4680 mov r8, r0 +10002170: b1d2 cbz r2, 100021a8 <_etoa+0x1a0> +10002172: eba0 060b sub.w r6, r0, fp +10002176: 45b2 cmp sl, r6 +10002178: d916 bls.n 100021a8 <_etoa+0x1a0> +1000217a: eb0b 0206 add.w r2, fp, r6 +1000217e: 462b mov r3, r5 +10002180: 4621 mov r1, r4 +10002182: 2020 movs r0, #32 +10002184: 3601 adds r6, #1 +10002186: 47b8 blx r7 +10002188: 45b2 cmp sl, r6 +1000218a: d8f6 bhi.n 1000217a <_etoa+0x172> +1000218c: f10b 33ff add.w r3, fp, #4294967295 @ 0xffffffff +10002190: 4453 add r3, sl +10002192: f1cb 0201 rsb r2, fp, #1 +10002196: eba3 0308 sub.w r3, r3, r8 +1000219a: 4442 add r2, r8 +1000219c: 4592 cmp sl, r2 +1000219e: bf38 it cc +100021a0: 2300 movcc r3, #0 +100021a2: f108 0801 add.w r8, r8, #1 +100021a6: 4498 add r8, r3 +100021a8: 4640 mov r0, r8 +100021aa: b01f add sp, #124 @ 0x7c +100021ac: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100021b0: 465a mov r2, fp +100021b2: 4638 mov r0, r7 +100021b4: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +100021b8: e9cd a62b strd sl, r6, [sp, #172] @ 0xac +100021bc: 9c0e ldr r4, [sp, #56] @ 0x38 +100021be: 9b09 ldr r3, [sp, #36] @ 0x24 +100021c0: 9908 ldr r1, [sp, #32] +100021c2: 942a str r4, [sp, #168] @ 0xa8 +100021c4: b01f add sp, #124 @ 0x7c +100021c6: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100021ca: f7ff bcbd b.w 10001b48 <_ftoa> +100021ce: ea58 0309 orrs.w r3, r8, r9 +100021d2: d12b bne.n 1000222c <_etoa+0x224> +100021d4: 2a00 cmp r2, #0 +100021d6: f43f af62 beq.w 1000209e <_etoa+0x96> +100021da: 2300 movs r3, #0 +100021dc: 930c str r3, [sp, #48] @ 0x30 +100021de: 9b0e ldr r3, [sp, #56] @ 0x38 +100021e0: 9a0c ldr r2, [sp, #48] @ 0x30 +100021e2: 4293 cmp r3, r2 +100021e4: f300 81b9 bgt.w 1000255a <_etoa+0x552> +100021e8: f04f 0800 mov.w r8, #0 +100021ec: 4620 mov r0, r4 +100021ee: 4629 mov r1, r5 +100021f0: 2200 movs r2, #0 +100021f2: 2300 movs r3, #0 +100021f4: f7ff fb00 bl 100017f8 <__wrap___aeabi_dcmplt> +100021f8: 2800 cmp r0, #0 +100021fa: f040 8113 bne.w 10002424 <_etoa+0x41c> +100021fe: ed9d 7b0a vldr d7, [sp, #40] @ 0x28 +10002202: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002206: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000220a: ed8d 7b28 vstr d7, [sp, #160] @ 0xa0 +1000220e: 465a mov r2, fp +10002210: 4638 mov r0, r7 +10002212: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002216: 9b09 ldr r3, [sp, #36] @ 0x24 +10002218: 9908 ldr r1, [sp, #32] +1000221a: 962c str r6, [sp, #176] @ 0xb0 +1000221c: e7d2 b.n 100021c4 <_etoa+0x1bc> +1000221e: bf00 nop +10002220: 7fefffff .word 0x7fefffff +10002224: cccccccd .word 0xcccccccd +10002228: 2306 movs r3, #6 +1000222a: 930e str r3, [sp, #56] @ 0x38 +1000222c: f3c9 500a ubfx r0, r9, #20, #11 +10002230: f2a0 30ff subw r0, r0, #1023 @ 0x3ff +10002234: f7ff fa86 bl 10001744 <__wrap___aeabi_i2d> +10002238: a3c1 add r3, pc, #772 @ (adr r3, 10002540 <_etoa+0x538>) +1000223a: e9d3 2300 ldrd r2, r3, [r3] +1000223e: f7ff fa0d bl 1000165c <__wrap___aeabi_dmul> +10002242: a3c1 add r3, pc, #772 @ (adr r3, 10002548 <_etoa+0x540>) +10002244: e9d3 2300 ldrd r2, r3, [r3] +10002248: f7ff f9e0 bl 1000160c <__wrap___aeabi_dadd> +1000224c: f3c9 0913 ubfx r9, r9, #0, #20 +10002250: e9cd 010c strd r0, r1, [sp, #48] @ 0x30 +10002254: f049 517f orr.w r1, r9, #1069547520 @ 0x3fc00000 +10002258: 4640 mov r0, r8 +1000225a: 2200 movs r2, #0 +1000225c: 4bb2 ldr r3, [pc, #712] @ (10002528 <_etoa+0x520>) +1000225e: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 +10002262: f7ff f9e7 bl 10001634 <__wrap___aeabi_dsub> +10002266: a3a4 add r3, pc, #656 @ (adr r3, 100024f8 <_etoa+0x4f0>) +10002268: e9d3 2300 ldrd r2, r3, [r3] +1000226c: f7ff f9f6 bl 1000165c <__wrap___aeabi_dmul> +10002270: 4602 mov r2, r0 +10002272: 460b mov r3, r1 +10002274: e9dd 010c ldrd r0, r1, [sp, #48] @ 0x30 +10002278: f7ff f9c8 bl 1000160c <__wrap___aeabi_dadd> +1000227c: f7ff fa86 bl 1000178c <__wrap___aeabi_d2iz> +10002280: 900c str r0, [sp, #48] @ 0x30 +10002282: f7ff fa5f bl 10001744 <__wrap___aeabi_i2d> +10002286: a39e add r3, pc, #632 @ (adr r3, 10002500 <_etoa+0x4f8>) +10002288: e9d3 2300 ldrd r2, r3, [r3] +1000228c: 4680 mov r8, r0 +1000228e: 4689 mov r9, r1 +10002290: f7ff f9e4 bl 1000165c <__wrap___aeabi_dmul> +10002294: 2200 movs r2, #0 +10002296: 4ba5 ldr r3, [pc, #660] @ (1000252c <_etoa+0x524>) +10002298: f7ff f9b8 bl 1000160c <__wrap___aeabi_dadd> +1000229c: f7ff fa76 bl 1000178c <__wrap___aeabi_d2iz> +100022a0: 4603 mov r3, r0 +100022a2: 4649 mov r1, r9 +100022a4: 4640 mov r0, r8 +100022a6: 9312 str r3, [sp, #72] @ 0x48 +100022a8: a397 add r3, pc, #604 @ (adr r3, 10002508 <_etoa+0x500>) +100022aa: e9d3 2300 ldrd r2, r3, [r3] +100022ae: f7ff f9d5 bl 1000165c <__wrap___aeabi_dmul> +100022b2: 4680 mov r8, r0 +100022b4: 9812 ldr r0, [sp, #72] @ 0x48 +100022b6: 4689 mov r9, r1 +100022b8: f7ff fa44 bl 10001744 <__wrap___aeabi_i2d> +100022bc: a394 add r3, pc, #592 @ (adr r3, 10002510 <_etoa+0x508>) +100022be: e9d3 2300 ldrd r2, r3, [r3] +100022c2: f7ff f9cb bl 1000165c <__wrap___aeabi_dmul> +100022c6: 4602 mov r2, r0 +100022c8: 460b mov r3, r1 +100022ca: 4640 mov r0, r8 +100022cc: 4649 mov r1, r9 +100022ce: f7ff f9b1 bl 10001634 <__wrap___aeabi_dsub> +100022d2: 4602 mov r2, r0 +100022d4: 460b mov r3, r1 +100022d6: 4680 mov r8, r0 +100022d8: 4689 mov r9, r1 +100022da: f7ff f9bf bl 1000165c <__wrap___aeabi_dmul> +100022de: 4642 mov r2, r8 +100022e0: 464b mov r3, r9 +100022e2: e9cd 0110 strd r0, r1, [sp, #64] @ 0x40 +100022e6: 4640 mov r0, r8 +100022e8: 4649 mov r1, r9 +100022ea: f7ff f98f bl 1000160c <__wrap___aeabi_dadd> +100022ee: 2200 movs r2, #0 +100022f0: e9cd 0114 strd r0, r1, [sp, #80] @ 0x50 +100022f4: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +100022f8: 4b8d ldr r3, [pc, #564] @ (10002530 <_etoa+0x528>) +100022fa: f7ff f9d5 bl 100016a8 <__wrap___aeabi_ddiv> +100022fe: 2200 movs r2, #0 +10002300: 4b8c ldr r3, [pc, #560] @ (10002534 <_etoa+0x52c>) +10002302: f7ff f983 bl 1000160c <__wrap___aeabi_dadd> +10002306: 4602 mov r2, r0 +10002308: 460b mov r3, r1 +1000230a: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +1000230e: f7ff f9cb bl 100016a8 <__wrap___aeabi_ddiv> +10002312: 2200 movs r2, #0 +10002314: 4b88 ldr r3, [pc, #544] @ (10002538 <_etoa+0x530>) +10002316: f7ff f979 bl 1000160c <__wrap___aeabi_dadd> +1000231a: 4602 mov r2, r0 +1000231c: 460b mov r3, r1 +1000231e: e9dd 0110 ldrd r0, r1, [sp, #64] @ 0x40 +10002322: f7ff f9c1 bl 100016a8 <__wrap___aeabi_ddiv> +10002326: 4642 mov r2, r8 +10002328: 464b mov r3, r9 +1000232a: 4680 mov r8, r0 +1000232c: 4689 mov r9, r1 +1000232e: 2000 movs r0, #0 +10002330: f04f 4180 mov.w r1, #1073741824 @ 0x40000000 +10002334: f7ff f97e bl 10001634 <__wrap___aeabi_dsub> +10002338: 4602 mov r2, r0 +1000233a: 460b mov r3, r1 +1000233c: 4640 mov r0, r8 +1000233e: 4649 mov r1, r9 +10002340: f7ff f964 bl 1000160c <__wrap___aeabi_dadd> +10002344: 4602 mov r2, r0 +10002346: 460b mov r3, r1 +10002348: e9dd 0114 ldrd r0, r1, [sp, #80] @ 0x50 +1000234c: f7ff f9ac bl 100016a8 <__wrap___aeabi_ddiv> +10002350: 2200 movs r2, #0 +10002352: 4b7a ldr r3, [pc, #488] @ (1000253c <_etoa+0x534>) +10002354: f7ff f95a bl 1000160c <__wrap___aeabi_dadd> +10002358: 9b12 ldr r3, [sp, #72] @ 0x48 +1000235a: 2200 movs r2, #0 +1000235c: f203 3cff addw ip, r3, #1023 @ 0x3ff +10002360: ea4f 530c mov.w r3, ip, lsl #20 +10002364: f7ff f97a bl 1000165c <__wrap___aeabi_dmul> +10002368: 4680 mov r8, r0 +1000236a: 4689 mov r9, r1 +1000236c: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002370: 4642 mov r2, r8 +10002372: 464b mov r3, r9 +10002374: f7ff fa40 bl 100017f8 <__wrap___aeabi_dcmplt> +10002378: b150 cbz r0, 10002390 <_etoa+0x388> +1000237a: 9b0c ldr r3, [sp, #48] @ 0x30 +1000237c: 4640 mov r0, r8 +1000237e: 3b01 subs r3, #1 +10002380: 4649 mov r1, r9 +10002382: 930c str r3, [sp, #48] @ 0x30 +10002384: 2200 movs r2, #0 +10002386: 4b6b ldr r3, [pc, #428] @ (10002534 <_etoa+0x52c>) +10002388: f7ff f98e bl 100016a8 <__wrap___aeabi_ddiv> +1000238c: 4680 mov r8, r0 +1000238e: 4689 mov r9, r1 +10002390: 9a0c ldr r2, [sp, #48] @ 0x30 +10002392: 4643 mov r3, r8 +10002394: 3263 adds r2, #99 @ 0x63 +10002396: 2ac6 cmp r2, #198 @ 0xc6 +10002398: f006 0202 and.w r2, r6, #2 +1000239c: 9210 str r2, [sp, #64] @ 0x40 +1000239e: 4649 mov r1, r9 +100023a0: 9a0f ldr r2, [sp, #60] @ 0x3c +100023a2: d82c bhi.n 100023fe <_etoa+0x3f6> +100023a4: 2a00 cmp r2, #0 +100023a6: d05e beq.n 10002466 <_etoa+0x45e> +100023a8: 2204 movs r2, #4 +100023aa: 9212 str r2, [sp, #72] @ 0x48 +100023ac: 430b orrs r3, r1 +100023ae: f43f af16 beq.w 100021de <_etoa+0x1d6> +100023b2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100023b6: a358 add r3, pc, #352 @ (adr r3, 10002518 <_etoa+0x510>) +100023b8: e9d3 2300 ldrd r2, r3, [r3] +100023bc: f7ff fa44 bl 10001848 <__wrap___aeabi_dcmpge> +100023c0: b148 cbz r0, 100023d6 <_etoa+0x3ce> +100023c2: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +100023c6: a356 add r3, pc, #344 @ (adr r3, 10002520 <_etoa+0x518>) +100023c8: e9d3 2300 ldrd r2, r3, [r3] +100023cc: f7ff fa14 bl 100017f8 <__wrap___aeabi_dcmplt> +100023d0: 2800 cmp r0, #0 +100023d2: f47f af04 bne.w 100021de <_etoa+0x1d6> +100023d6: 9b0e ldr r3, [sp, #56] @ 0x38 +100023d8: 2b00 cmp r3, #0 +100023da: d050 beq.n 1000247e <_etoa+0x476> +100023dc: 9a13 ldr r2, [sp, #76] @ 0x4c +100023de: 2a00 cmp r2, #0 +100023e0: d07d beq.n 100024de <_etoa+0x4d6> +100023e2: 3b01 subs r3, #1 +100023e4: 930e str r3, [sp, #56] @ 0x38 +100023e6: 9b12 ldr r3, [sp, #72] @ 0x48 +100023e8: 459a cmp sl, r3 +100023ea: d905 bls.n 100023f8 <_etoa+0x3f0> +100023ec: 9b10 ldr r3, [sp, #64] @ 0x40 +100023ee: 2b00 cmp r3, #0 +100023f0: f000 80ae beq.w 10002550 <_etoa+0x548> +100023f4: 2302 movs r3, #2 +100023f6: 9310 str r3, [sp, #64] @ 0x40 +100023f8: 2300 movs r3, #0 +100023fa: 930f str r3, [sp, #60] @ 0x3c +100023fc: e044 b.n 10002488 <_etoa+0x480> +100023fe: bb22 cbnz r2, 1000244a <_etoa+0x442> +10002400: f1ba 0f05 cmp.w sl, #5 +10002404: d94f bls.n 100024a6 <_etoa+0x49e> +10002406: f006 0302 and.w r3, r6, #2 +1000240a: 2b00 cmp r3, #0 +1000240c: d149 bne.n 100024a2 <_etoa+0x49a> +1000240e: 2305 movs r3, #5 +10002410: 9312 str r3, [sp, #72] @ 0x48 +10002412: f1aa 0305 sub.w r3, sl, #5 +10002416: 930f str r3, [sp, #60] @ 0x3c +10002418: e03a b.n 10002490 <_etoa+0x488> +1000241a: f105 4300 add.w r3, r5, #2147483648 @ 0x80000000 +1000241e: 940a str r4, [sp, #40] @ 0x28 +10002420: 930b str r3, [sp, #44] @ 0x2c +10002422: e627 b.n 10002074 <_etoa+0x6c> +10002424: f426 6600 bic.w r6, r6, #2048 @ 0x800 +10002428: f446 6680 orr.w r6, r6, #1024 @ 0x400 +1000242c: 4638 mov r0, r7 +1000242e: 962c str r6, [sp, #176] @ 0xb0 +10002430: e9dd 670a ldrd r6, r7, [sp, #40] @ 0x28 +10002434: 4634 mov r4, r6 +10002436: f107 4500 add.w r5, r7, #2147483648 @ 0x80000000 +1000243a: 465a mov r2, fp +1000243c: e9cd 8a2a strd r8, sl, [sp, #168] @ 0xa8 +10002440: e9cd 4528 strd r4, r5, [sp, #160] @ 0xa0 +10002444: 9b09 ldr r3, [sp, #36] @ 0x24 +10002446: 9908 ldr r1, [sp, #32] +10002448: e6bc b.n 100021c4 <_etoa+0x1bc> +1000244a: 2205 movs r2, #5 +1000244c: 9212 str r2, [sp, #72] @ 0x48 +1000244e: e7ad b.n 100023ac <_etoa+0x3a4> +10002450: 2300 movs r3, #0 +10002452: 2202 movs r2, #2 +10002454: e9cd 320f strd r3, r2, [sp, #60] @ 0x3c +10002458: 2204 movs r2, #4 +1000245a: 930c str r3, [sp, #48] @ 0x30 +1000245c: 9212 str r2, [sp, #72] @ 0x48 +1000245e: e62c b.n 100020ba <_etoa+0xb2> +10002460: f04f 0805 mov.w r8, #5 +10002464: e6c2 b.n 100021ec <_etoa+0x1e4> +10002466: f1ba 0f04 cmp.w sl, #4 +1000246a: d91f bls.n 100024ac <_etoa+0x4a4> +1000246c: 9b10 ldr r3, [sp, #64] @ 0x40 +1000246e: 2b00 cmp r3, #0 +10002470: d178 bne.n 10002564 <_etoa+0x55c> +10002472: 2304 movs r3, #4 +10002474: 9312 str r3, [sp, #72] @ 0x48 +10002476: f1aa 0304 sub.w r3, sl, #4 +1000247a: 930f str r3, [sp, #60] @ 0x3c +1000247c: e004 b.n 10002488 <_etoa+0x480> +1000247e: 9b12 ldr r3, [sp, #72] @ 0x48 +10002480: 459a cmp sl, r3 +10002482: d831 bhi.n 100024e8 <_etoa+0x4e0> +10002484: 9b0e ldr r3, [sp, #56] @ 0x38 +10002486: 930f str r3, [sp, #60] @ 0x3c +10002488: 9b0c ldr r3, [sp, #48] @ 0x30 +1000248a: 2b00 cmp r3, #0 +1000248c: f43f ae15 beq.w 100020ba <_etoa+0xb2> +10002490: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28 +10002494: 4642 mov r2, r8 +10002496: 464b mov r3, r9 +10002498: f7ff f906 bl 100016a8 <__wrap___aeabi_ddiv> +1000249c: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 +100024a0: e60b b.n 100020ba <_etoa+0xb2> +100024a2: 2302 movs r3, #2 +100024a4: 9310 str r3, [sp, #64] @ 0x40 +100024a6: 2305 movs r3, #5 +100024a8: 9312 str r3, [sp, #72] @ 0x48 +100024aa: e7f1 b.n 10002490 <_etoa+0x488> +100024ac: 2304 movs r3, #4 +100024ae: 9312 str r3, [sp, #72] @ 0x48 +100024b0: e7ea b.n 10002488 <_etoa+0x480> +100024b2: e9dd 450a ldrd r4, r5, [sp, #40] @ 0x28 +100024b6: 46a0 mov r8, r4 +100024b8: 9b0f ldr r3, [sp, #60] @ 0x3c +100024ba: f105 4900 add.w r9, r5, #2147483648 @ 0x80000000 +100024be: 9303 str r3, [sp, #12] +100024c0: 9b0e ldr r3, [sp, #56] @ 0x38 +100024c2: 465a mov r2, fp +100024c4: 9302 str r3, [sp, #8] +100024c6: f426 6300 bic.w r3, r6, #2048 @ 0x800 +100024ca: 9304 str r3, [sp, #16] +100024cc: 4638 mov r0, r7 +100024ce: e9cd 8900 strd r8, r9, [sp] +100024d2: 9b09 ldr r3, [sp, #36] @ 0x24 +100024d4: 9908 ldr r1, [sp, #32] +100024d6: f7ff fb37 bl 10001b48 <_ftoa> +100024da: 4602 mov r2, r0 +100024dc: e608 b.n 100020f0 <_etoa+0xe8> +100024de: 9b12 ldr r3, [sp, #72] @ 0x48 +100024e0: 459a cmp sl, r3 +100024e2: d844 bhi.n 1000256e <_etoa+0x566> +100024e4: 920f str r2, [sp, #60] @ 0x3c +100024e6: e7cf b.n 10002488 <_etoa+0x480> +100024e8: 9b10 ldr r3, [sp, #64] @ 0x40 +100024ea: b38b cbz r3, 10002550 <_etoa+0x548> +100024ec: 9b0e ldr r3, [sp, #56] @ 0x38 +100024ee: 930f str r3, [sp, #60] @ 0x3c +100024f0: 2302 movs r3, #2 +100024f2: 9310 str r3, [sp, #64] @ 0x40 +100024f4: e7c8 b.n 10002488 <_etoa+0x480> +100024f6: bf00 nop +100024f8: 636f4361 .word 0x636f4361 +100024fc: 3fd287a7 .word 0x3fd287a7 +10002500: 0979a371 .word 0x0979a371 +10002504: 400a934f .word 0x400a934f +10002508: bbb55516 .word 0xbbb55516 +1000250c: 40026bb1 .word 0x40026bb1 +10002510: fefa39ef .word 0xfefa39ef +10002514: 3fe62e42 .word 0x3fe62e42 +10002518: eb1c432d .word 0xeb1c432d +1000251c: 3f1a36e2 .word 0x3f1a36e2 +10002520: 00000000 .word 0x00000000 +10002524: 412e8480 .word 0x412e8480 +10002528: 3ff80000 .word 0x3ff80000 +1000252c: 3fe00000 .word 0x3fe00000 +10002530: 402c0000 .word 0x402c0000 +10002534: 40240000 .word 0x40240000 +10002538: 40180000 .word 0x40180000 +1000253c: 3ff00000 .word 0x3ff00000 +10002540: 509f79fb .word 0x509f79fb +10002544: 3fd34413 .word 0x3fd34413 +10002548: 8b60c8b3 .word 0x8b60c8b3 +1000254c: 3fc68a28 .word 0x3fc68a28 +10002550: 9b12 ldr r3, [sp, #72] @ 0x48 +10002552: ebaa 0303 sub.w r3, sl, r3 +10002556: 930f str r3, [sp, #60] @ 0x3c +10002558: e796 b.n 10002488 <_etoa+0x480> +1000255a: eba3 0802 sub.w r8, r3, r2 +1000255e: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +10002562: e643 b.n 100021ec <_etoa+0x1e4> +10002564: 2304 movs r3, #4 +10002566: 9312 str r3, [sp, #72] @ 0x48 +10002568: 2302 movs r3, #2 +1000256a: 9310 str r3, [sp, #64] @ 0x40 +1000256c: e78c b.n 10002488 <_etoa+0x480> +1000256e: 9b10 ldr r3, [sp, #64] @ 0x40 +10002570: 2b00 cmp r3, #0 +10002572: d0ed beq.n 10002550 <_etoa+0x548> +10002574: 2302 movs r3, #2 +10002576: 920f str r2, [sp, #60] @ 0x3c +10002578: 9310 str r3, [sp, #64] @ 0x40 +1000257a: e785 b.n 10002488 <_etoa+0x480> + +1000257c <_vsnprintf>: +1000257c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10002580: b09b sub sp, #108 @ 0x6c +10002582: 9c24 ldr r4, [sp, #144] @ 0x90 +10002584: 4d95 ldr r5, [pc, #596] @ (100027dc <_vsnprintf+0x260>) +10002586: 940a str r4, [sp, #40] @ 0x28 +10002588: 4c95 ldr r4, [pc, #596] @ (100027e0 <_vsnprintf+0x264>) +1000258a: f1b1 0a00 subs.w sl, r1, #0 +1000258e: bf18 it ne +10002590: 4683 movne fp, r0 +10002592: 6025 str r5, [r4, #0] +10002594: 7818 ldrb r0, [r3, #0] +10002596: 4c93 ldr r4, [pc, #588] @ (100027e4 <_vsnprintf+0x268>) +10002598: 4691 mov r9, r2 +1000259a: bf08 it eq +1000259c: 46a3 moveq fp, r4 +1000259e: 9309 str r3, [sp, #36] @ 0x24 +100025a0: 2800 cmp r0, #0 +100025a2: f000 8293 beq.w 10002acc <_vsnprintf+0x550> +100025a6: f04f 0800 mov.w r8, #0 +100025aa: e00a b.n 100025c2 <_vsnprintf+0x46> +100025ac: 4642 mov r2, r8 +100025ae: 464b mov r3, r9 +100025b0: 4651 mov r1, sl +100025b2: f108 0801 add.w r8, r8, #1 +100025b6: 47d8 blx fp +100025b8: 9b09 ldr r3, [sp, #36] @ 0x24 +100025ba: 7818 ldrb r0, [r3, #0] +100025bc: 2800 cmp r0, #0 +100025be: f000 80ce beq.w 1000275e <_vsnprintf+0x1e2> +100025c2: 9b09 ldr r3, [sp, #36] @ 0x24 +100025c4: 2825 cmp r0, #37 @ 0x25 +100025c6: f103 0301 add.w r3, r3, #1 +100025ca: 9309 str r3, [sp, #36] @ 0x24 +100025cc: d1ee bne.n 100025ac <_vsnprintf+0x30> +100025ce: 461c mov r4, r3 +100025d0: 2300 movs r3, #0 +100025d2: 4622 mov r2, r4 +100025d4: f812 0b01 ldrb.w r0, [r2], #1 +100025d8: f1a0 0120 sub.w r1, r0, #32 +100025dc: 2910 cmp r1, #16 +100025de: d80a bhi.n 100025f6 <_vsnprintf+0x7a> +100025e0: e8df f001 tbb [pc, r1] +100025e4: 3c090940 .word 0x3c090940 +100025e8: 09090909 .word 0x09090909 +100025ec: 38090909 .word 0x38090909 +100025f0: 09093409 .word 0x09093409 +100025f4: 30 .byte 0x30 +100025f5: 00 .byte 0x00 +100025f6: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +100025fa: 2909 cmp r1, #9 +100025fc: 9409 str r4, [sp, #36] @ 0x24 +100025fe: f240 808a bls.w 10002716 <_vsnprintf+0x19a> +10002602: 282a cmp r0, #42 @ 0x2a +10002604: f000 80f0 beq.w 100027e8 <_vsnprintf+0x26c> +10002608: 2500 movs r5, #0 +1000260a: 282e cmp r0, #46 @ 0x2e +1000260c: f000 8096 beq.w 1000273c <_vsnprintf+0x1c0> +10002610: 2600 movs r6, #0 +10002612: f1a0 0168 sub.w r1, r0, #104 @ 0x68 +10002616: 2912 cmp r1, #18 +10002618: d82d bhi.n 10002676 <_vsnprintf+0xfa> +1000261a: e8df f011 tbh [pc, r1, lsl #1] +1000261e: 0149 .short 0x0149 +10002620: 0143002c .word 0x0143002c +10002624: 0138002c .word 0x0138002c +10002628: 002c002c .word 0x002c002c +1000262c: 002c002c .word 0x002c002c +10002630: 002c002c .word 0x002c002c +10002634: 0027002c .word 0x0027002c +10002638: 002c002c .word 0x002c002c +1000263c: 002c002c .word 0x002c002c +10002640: 0027002c .word 0x0027002c +10002644: 4614 mov r4, r2 +10002646: f043 0301 orr.w r3, r3, #1 +1000264a: e7c2 b.n 100025d2 <_vsnprintf+0x56> +1000264c: 4614 mov r4, r2 +1000264e: f043 0302 orr.w r3, r3, #2 +10002652: e7be b.n 100025d2 <_vsnprintf+0x56> +10002654: 4614 mov r4, r2 +10002656: f043 0304 orr.w r3, r3, #4 +1000265a: e7ba b.n 100025d2 <_vsnprintf+0x56> +1000265c: 4614 mov r4, r2 +1000265e: f043 0310 orr.w r3, r3, #16 +10002662: e7b6 b.n 100025d2 <_vsnprintf+0x56> +10002664: 4614 mov r4, r2 +10002666: f043 0308 orr.w r3, r3, #8 +1000266a: e7b2 b.n 100025d2 <_vsnprintf+0x56> +1000266c: 9909 ldr r1, [sp, #36] @ 0x24 +1000266e: 7848 ldrb r0, [r1, #1] +10002670: f443 7380 orr.w r3, r3, #256 @ 0x100 +10002674: 3201 adds r2, #1 +10002676: 2867 cmp r0, #103 @ 0x67 +10002678: 9209 str r2, [sp, #36] @ 0x24 +1000267a: d87e bhi.n 1000277a <_vsnprintf+0x1fe> +1000267c: 2824 cmp r0, #36 @ 0x24 +1000267e: f240 80c1 bls.w 10002804 <_vsnprintf+0x288> +10002682: f1a0 0225 sub.w r2, r0, #37 @ 0x25 +10002686: 2a42 cmp r2, #66 @ 0x42 +10002688: f200 80bc bhi.w 10002804 <_vsnprintf+0x288> +1000268c: e8df f012 tbh [pc, r2, lsl #1] +10002690: 00ba0150 .word 0x00ba0150 +10002694: 00ba00ba .word 0x00ba00ba +10002698: 00ba00ba .word 0x00ba00ba +1000269c: 00ba00ba .word 0x00ba00ba +100026a0: 00ba00ba .word 0x00ba00ba +100026a4: 00ba00ba .word 0x00ba00ba +100026a8: 00ba00ba .word 0x00ba00ba +100026ac: 00ba00ba .word 0x00ba00ba +100026b0: 00ba00ba .word 0x00ba00ba +100026b4: 00ba00ba .word 0x00ba00ba +100026b8: 00ba00ba .word 0x00ba00ba +100026bc: 00ba00ba .word 0x00ba00ba +100026c0: 00ba00ba .word 0x00ba00ba +100026c4: 00ba00ba .word 0x00ba00ba +100026c8: 00ba00ba .word 0x00ba00ba +100026cc: 00ba00ba .word 0x00ba00ba +100026d0: 01370119 .word 0x01370119 +100026d4: 00ba0119 .word 0x00ba0119 +100026d8: 00ba00ba .word 0x00ba00ba +100026dc: 00ba00ba .word 0x00ba00ba +100026e0: 00ba00ba .word 0x00ba00ba +100026e4: 00ba00ba .word 0x00ba00ba +100026e8: 00ba00ba .word 0x00ba00ba +100026ec: 00ba00ba .word 0x00ba00ba +100026f0: 00ba00ba .word 0x00ba00ba +100026f4: 01bc00ba .word 0x01bc00ba +100026f8: 00ba00ba .word 0x00ba00ba +100026fc: 00ba00ba .word 0x00ba00ba +10002700: 00ba00ba .word 0x00ba00ba +10002704: 00ba00ba .word 0x00ba00ba +10002708: 01bc00ba .word 0x01bc00ba +1000270c: 01bc0158 .word 0x01bc0158 +10002710: 01370119 .word 0x01370119 +10002714: 0119 .short 0x0119 +10002716: 2500 movs r5, #0 +10002718: e000 b.n 1000271c <_vsnprintf+0x1a0> +1000271a: 3201 adds r2, #1 +1000271c: eb05 0585 add.w r5, r5, r5, lsl #2 +10002720: eb00 0545 add.w r5, r0, r5, lsl #1 +10002724: 7810 ldrb r0, [r2, #0] +10002726: 3d30 subs r5, #48 @ 0x30 +10002728: f1a0 0130 sub.w r1, r0, #48 @ 0x30 +1000272c: 2909 cmp r1, #9 +1000272e: d9f4 bls.n 1000271a <_vsnprintf+0x19e> +10002730: 282e cmp r0, #46 @ 0x2e +10002732: 9209 str r2, [sp, #36] @ 0x24 +10002734: f102 0201 add.w r2, r2, #1 +10002738: f47f af6a bne.w 10002610 <_vsnprintf+0x94> +1000273c: 9909 ldr r1, [sp, #36] @ 0x24 +1000273e: f443 6380 orr.w r3, r3, #1024 @ 0x400 +10002742: 7848 ldrb r0, [r1, #1] +10002744: 4611 mov r1, r2 +10002746: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +1000274a: 2e09 cmp r6, #9 +1000274c: f240 8121 bls.w 10002992 <_vsnprintf+0x416> +10002750: 282a cmp r0, #42 @ 0x2a +10002752: f000 812f beq.w 100029b4 <_vsnprintf+0x438> +10002756: 9209 str r2, [sp, #36] @ 0x24 +10002758: 2600 movs r6, #0 +1000275a: 3201 adds r2, #1 +1000275c: e759 b.n 10002612 <_vsnprintf+0x96> +1000275e: 4644 mov r4, r8 +10002760: 45c1 cmp r9, r8 +10002762: d801 bhi.n 10002768 <_vsnprintf+0x1ec> +10002764: f109 38ff add.w r8, r9, #4294967295 @ 0xffffffff +10002768: 464b mov r3, r9 +1000276a: 4642 mov r2, r8 +1000276c: 4651 mov r1, sl +1000276e: 2000 movs r0, #0 +10002770: 47d8 blx fp +10002772: 4620 mov r0, r4 +10002774: b01b add sp, #108 @ 0x6c +10002776: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000277a: f1a0 0269 sub.w r2, r0, #105 @ 0x69 +1000277e: b2d2 uxtb r2, r2 +10002780: 2a0f cmp r2, #15 +10002782: d83f bhi.n 10002804 <_vsnprintf+0x288> +10002784: 2101 movs r1, #1 +10002786: f249 0741 movw r7, #36929 @ 0x9041 +1000278a: 4091 lsls r1, r2 +1000278c: 4039 ands r1, r7 +1000278e: f040 80f3 bne.w 10002978 <_vsnprintf+0x3fc> +10002792: 2a0a cmp r2, #10 +10002794: d03d beq.n 10002812 <_vsnprintf+0x296> +10002796: 2a07 cmp r2, #7 +10002798: d134 bne.n 10002804 <_vsnprintf+0x288> +1000279a: 9d0a ldr r5, [sp, #40] @ 0x28 +1000279c: f855 2b04 ldr.w r2, [r5], #4 +100027a0: 2a00 cmp r2, #0 +100027a2: f000 8113 beq.w 100029cc <_vsnprintf+0x450> +100027a6: f043 0021 orr.w r0, r3, #33 @ 0x21 +100027aa: ab12 add r3, sp, #72 @ 0x48 +100027ac: 461f mov r7, r3 +100027ae: 930b str r3, [sp, #44] @ 0x2c +100027b0: e003 b.n 100027ba <_vsnprintf+0x23e> +100027b2: 2920 cmp r1, #32 +100027b4: f000 8114 beq.w 100029e0 <_vsnprintf+0x464> +100027b8: 461a mov r2, r3 +100027ba: f002 040f and.w r4, r2, #15 +100027be: 4623 mov r3, r4 +100027c0: 2c09 cmp r4, #9 +100027c2: bf94 ite ls +100027c4: 3330 addls r3, #48 @ 0x30 +100027c6: 3337 addhi r3, #55 @ 0x37 +100027c8: 2a0f cmp r2, #15 +100027ca: f807 3b01 strb.w r3, [r7], #1 +100027ce: f101 0101 add.w r1, r1, #1 +100027d2: ea4f 1312 mov.w r3, r2, lsr #4 +100027d6: d8ec bhi.n 100027b2 <_vsnprintf+0x236> +100027d8: e102 b.n 100029e0 <_vsnprintf+0x464> +100027da: bf00 nop +100027dc: 1000257d .word 0x1000257d +100027e0: 20003108 .word 0x20003108 +100027e4: 100018c1 .word 0x100018c1 +100027e8: 990a ldr r1, [sp, #40] @ 0x28 +100027ea: 9809 ldr r0, [sp, #36] @ 0x24 +100027ec: f851 5b04 ldr.w r5, [r1], #4 +100027f0: 7840 ldrb r0, [r0, #1] +100027f2: 2d00 cmp r5, #0 +100027f4: e9cd 2109 strd r2, r1, [sp, #36] @ 0x24 +100027f8: bfbc itt lt +100027fa: f043 0302 orrlt.w r3, r3, #2 +100027fe: 426d neglt r5, r5 +10002800: 3201 adds r2, #1 +10002802: e702 b.n 1000260a <_vsnprintf+0x8e> +10002804: 4642 mov r2, r8 +10002806: 464b mov r3, r9 +10002808: 4651 mov r1, sl +1000280a: f108 0801 add.w r8, r8, #1 +1000280e: 47d8 blx fp +10002810: e6d2 b.n 100025b8 <_vsnprintf+0x3c> +10002812: 990a ldr r1, [sp, #40] @ 0x28 +10002814: 2e00 cmp r6, #0 +10002816: f851 7b04 ldr.w r7, [r1], #4 +1000281a: bf18 it ne +1000281c: 4632 movne r2, r6 +1000281e: 7838 ldrb r0, [r7, #0] +10002820: bf08 it eq +10002822: f04f 32ff moveq.w r2, #4294967295 @ 0xffffffff +10002826: 2800 cmp r0, #0 +10002828: f000 837b beq.w 10002f22 <_vsnprintf+0x9a6> +1000282c: 18bc adds r4, r7, r2 +1000282e: 46a4 mov ip, r4 +10002830: 463a mov r2, r7 +10002832: e004 b.n 1000283e <_vsnprintf+0x2c2> +10002834: f812 4f01 ldrb.w r4, [r2, #1]! +10002838: 2c00 cmp r4, #0 +1000283a: f000 813f beq.w 10002abc <_vsnprintf+0x540> +1000283e: 4594 cmp ip, r2 +10002840: d1f8 bne.n 10002834 <_vsnprintf+0x2b8> +10002842: 4664 mov r4, ip +10002844: 1be4 subs r4, r4, r7 +10002846: 055a lsls r2, r3, #21 +10002848: f140 8122 bpl.w 10002a90 <_vsnprintf+0x514> +1000284c: 42b4 cmp r4, r6 +1000284e: bf28 it cs +10002850: 4634 movcs r4, r6 +10002852: f013 0302 ands.w r3, r3, #2 +10002856: f000 8288 beq.w 10002d6a <_vsnprintf+0x7ee> +1000285a: 2302 movs r3, #2 +1000285c: e9cd 510a strd r5, r1, [sp, #40] @ 0x28 +10002860: 4642 mov r2, r8 +10002862: 461d mov r5, r3 +10002864: 4446 add r6, r8 +10002866: e008 b.n 1000287a <_vsnprintf+0x2fe> +10002868: 464b mov r3, r9 +1000286a: 4651 mov r1, sl +1000286c: 47d8 blx fp +1000286e: f817 0f01 ldrb.w r0, [r7, #1]! +10002872: f108 0801 add.w r8, r8, #1 +10002876: b110 cbz r0, 1000287e <_vsnprintf+0x302> +10002878: 4642 mov r2, r8 +1000287a: 4546 cmp r6, r8 +1000287c: d1f4 bne.n 10002868 <_vsnprintf+0x2ec> +1000287e: 462b mov r3, r5 +10002880: 990b ldr r1, [sp, #44] @ 0x2c +10002882: 9d0a ldr r5, [sp, #40] @ 0x28 +10002884: 2b00 cmp r3, #0 +10002886: f040 8141 bne.w 10002b0c <_vsnprintf+0x590> +1000288a: 910a str r1, [sp, #40] @ 0x28 +1000288c: e694 b.n 100025b8 <_vsnprintf+0x3c> +1000288e: 9909 ldr r1, [sp, #36] @ 0x24 +10002890: 7848 ldrb r0, [r1, #1] +10002892: 286c cmp r0, #108 @ 0x6c +10002894: f47f aeec bne.w 10002670 <_vsnprintf+0xf4> +10002898: 460a mov r2, r1 +1000289a: 7888 ldrb r0, [r1, #2] +1000289c: f443 7340 orr.w r3, r3, #768 @ 0x300 +100028a0: 3203 adds r2, #3 +100028a2: e6e8 b.n 10002676 <_vsnprintf+0xfa> +100028a4: 9909 ldr r1, [sp, #36] @ 0x24 +100028a6: f443 7300 orr.w r3, r3, #512 @ 0x200 +100028aa: 7848 ldrb r0, [r1, #1] +100028ac: 3201 adds r2, #1 +100028ae: e6e2 b.n 10002676 <_vsnprintf+0xfa> +100028b0: 9909 ldr r1, [sp, #36] @ 0x24 +100028b2: 7848 ldrb r0, [r1, #1] +100028b4: 2868 cmp r0, #104 @ 0x68 +100028b6: f000 8103 beq.w 10002ac0 <_vsnprintf+0x544> +100028ba: f043 0380 orr.w r3, r3, #128 @ 0x80 +100028be: 3201 adds r2, #1 +100028c0: e6d9 b.n 10002676 <_vsnprintf+0xfa> +100028c2: 2867 cmp r0, #103 @ 0x67 +100028c4: f000 80d9 beq.w 10002a7a <_vsnprintf+0x4fe> +100028c8: 2847 cmp r0, #71 @ 0x47 +100028ca: f000 80dc beq.w 10002a86 <_vsnprintf+0x50a> +100028ce: 2845 cmp r0, #69 @ 0x45 +100028d0: f000 80db beq.w 10002a8a <_vsnprintf+0x50e> +100028d4: e9cd 5303 strd r5, r3, [sp, #12] +100028d8: 9b0a ldr r3, [sp, #40] @ 0x28 +100028da: 9602 str r6, [sp, #8] +100028dc: 3307 adds r3, #7 +100028de: f023 0307 bic.w r3, r3, #7 +100028e2: 461c mov r4, r3 +100028e4: 4642 mov r2, r8 +100028e6: e8f4 6702 ldrd r6, r7, [r4], #8 +100028ea: 464b mov r3, r9 +100028ec: 4651 mov r1, sl +100028ee: 4658 mov r0, fp +100028f0: e9cd 6700 strd r6, r7, [sp] +100028f4: 940a str r4, [sp, #40] @ 0x28 +100028f6: f7ff fb87 bl 10002008 <_etoa> +100028fa: 4680 mov r8, r0 +100028fc: e65c b.n 100025b8 <_vsnprintf+0x3c> +100028fe: 2846 cmp r0, #70 @ 0x46 +10002900: bf08 it eq +10002902: f043 0320 orreq.w r3, r3, #32 +10002906: e9cd 5303 strd r5, r3, [sp, #12] +1000290a: 9b0a ldr r3, [sp, #40] @ 0x28 +1000290c: 9602 str r6, [sp, #8] +1000290e: 3307 adds r3, #7 +10002910: f023 0307 bic.w r3, r3, #7 +10002914: 461c mov r4, r3 +10002916: 4642 mov r2, r8 +10002918: e8f4 6702 ldrd r6, r7, [r4], #8 +1000291c: 464b mov r3, r9 +1000291e: 4651 mov r1, sl +10002920: 4658 mov r0, fp +10002922: e9cd 6700 strd r6, r7, [sp] +10002926: 940a str r4, [sp, #40] @ 0x28 +10002928: f7ff f90e bl 10001b48 <_ftoa> +1000292c: 4680 mov r8, r0 +1000292e: e643 b.n 100025b8 <_vsnprintf+0x3c> +10002930: 4642 mov r2, r8 +10002932: 464b mov r3, r9 +10002934: 4651 mov r1, sl +10002936: 2025 movs r0, #37 @ 0x25 +10002938: f108 0801 add.w r8, r8, #1 +1000293c: 47d8 blx fp +1000293e: e63b b.n 100025b8 <_vsnprintf+0x3c> +10002940: 9a0a ldr r2, [sp, #40] @ 0x28 +10002942: 0799 lsls r1, r3, #30 +10002944: f102 0404 add.w r4, r2, #4 +10002948: f108 0601 add.w r6, r8, #1 +1000294c: f140 80c6 bpl.w 10002adc <_vsnprintf+0x560> +10002950: 7810 ldrb r0, [r2, #0] +10002952: 464b mov r3, r9 +10002954: 4642 mov r2, r8 +10002956: 4651 mov r1, sl +10002958: 47d8 blx fp +1000295a: 2d01 cmp r5, #1 +1000295c: bf88 it hi +1000295e: 44a8 addhi r8, r5 +10002960: f240 81bd bls.w 10002cde <_vsnprintf+0x762> +10002964: 4632 mov r2, r6 +10002966: 464b mov r3, r9 +10002968: 4651 mov r1, sl +1000296a: 2020 movs r0, #32 +1000296c: 3601 adds r6, #1 +1000296e: 47d8 blx fp +10002970: 4546 cmp r6, r8 +10002972: d1f7 bne.n 10002964 <_vsnprintf+0x3e8> +10002974: 940a str r4, [sp, #40] @ 0x28 +10002976: e61f b.n 100025b8 <_vsnprintf+0x3c> +10002978: 286f cmp r0, #111 @ 0x6f +1000297a: f000 8081 beq.w 10002a80 <_vsnprintf+0x504> +1000297e: f240 8248 bls.w 10002e12 <_vsnprintf+0x896> +10002982: 2878 cmp r0, #120 @ 0x78 +10002984: f000 8190 beq.w 10002ca8 <_vsnprintf+0x72c> +10002988: 270a movs r7, #10 +1000298a: f023 0310 bic.w r3, r3, #16 +1000298e: 46bc mov ip, r7 +10002990: e041 b.n 10002a16 <_vsnprintf+0x49a> +10002992: 2600 movs r6, #0 +10002994: eb06 0686 add.w r6, r6, r6, lsl #2 +10002998: eb00 0046 add.w r0, r0, r6, lsl #1 +1000299c: f1a0 0630 sub.w r6, r0, #48 @ 0x30 +100029a0: f811 0f01 ldrb.w r0, [r1, #1]! +100029a4: f1a0 0230 sub.w r2, r0, #48 @ 0x30 +100029a8: 2a09 cmp r2, #9 +100029aa: d9f3 bls.n 10002994 <_vsnprintf+0x418> +100029ac: 460a mov r2, r1 +100029ae: 9109 str r1, [sp, #36] @ 0x24 +100029b0: 3201 adds r2, #1 +100029b2: e62e b.n 10002612 <_vsnprintf+0x96> +100029b4: e9dd 2109 ldrd r2, r1, [sp, #36] @ 0x24 +100029b8: f851 6b04 ldr.w r6, [r1], #4 +100029bc: 7890 ldrb r0, [r2, #2] +100029be: 3202 adds r2, #2 +100029c0: 9209 str r2, [sp, #36] @ 0x24 +100029c2: 910a str r1, [sp, #40] @ 0x28 +100029c4: 3201 adds r2, #1 +100029c6: ea26 76e6 bic.w r6, r6, r6, asr #31 +100029ca: e622 b.n 10002612 <_vsnprintf+0x96> +100029cc: f023 0010 bic.w r0, r3, #16 +100029d0: f413 6280 ands.w r2, r3, #1024 @ 0x400 +100029d4: f040 0021 orr.w r0, r0, #33 @ 0x21 +100029d8: f43f aee7 beq.w 100027aa <_vsnprintf+0x22e> +100029dc: ab12 add r3, sp, #72 @ 0x48 +100029de: 930b str r3, [sp, #44] @ 0x2c +100029e0: 9b0b ldr r3, [sp, #44] @ 0x2c +100029e2: 9006 str r0, [sp, #24] +100029e4: 9300 str r3, [sp, #0] +100029e6: 2308 movs r3, #8 +100029e8: 2010 movs r0, #16 +100029ea: 9305 str r3, [sp, #20] +100029ec: 2300 movs r3, #0 +100029ee: 4642 mov r2, r8 +100029f0: e9cd 3002 strd r3, r0, [sp, #8] +100029f4: 9101 str r1, [sp, #4] +100029f6: 464b mov r3, r9 +100029f8: 4651 mov r1, sl +100029fa: 4658 mov r0, fp +100029fc: 9604 str r6, [sp, #16] +100029fe: f7fe ffaf bl 10001960 <_ntoa_format> +10002a02: 950a str r5, [sp, #40] @ 0x28 +10002a04: 4680 mov r8, r0 +10002a06: e5d7 b.n 100025b8 <_vsnprintf+0x3c> +10002a08: 2858 cmp r0, #88 @ 0x58 +10002a0a: d062 beq.n 10002ad2 <_vsnprintf+0x556> +10002a0c: 2862 cmp r0, #98 @ 0x62 +10002a0e: f040 808f bne.w 10002b30 <_vsnprintf+0x5b4> +10002a12: 2702 movs r7, #2 +10002a14: 46bc mov ip, r7 +10002a16: f413 6080 ands.w r0, r3, #1024 @ 0x400 +10002a1a: f000 80dd beq.w 10002bd8 <_vsnprintf+0x65c> +10002a1e: f023 030d bic.w r3, r3, #13 +10002a22: f413 7200 ands.w r2, r3, #512 @ 0x200 +10002a26: f040 8181 bne.w 10002d2c <_vsnprintf+0x7b0> +10002a2a: 990a ldr r1, [sp, #40] @ 0x28 +10002a2c: 1d0f adds r7, r1, #4 +10002a2e: f413 7180 ands.w r1, r3, #256 @ 0x100 +10002a32: f040 8237 bne.w 10002ea4 <_vsnprintf+0x928> +10002a36: 065c lsls r4, r3, #25 +10002a38: 9a0a ldr r2, [sp, #40] @ 0x28 +10002a3a: f140 813b bpl.w 10002cb4 <_vsnprintf+0x738> +10002a3e: 7812 ldrb r2, [r2, #0] +10002a40: 2a00 cmp r2, #0 +10002a42: f040 814e bne.w 10002ce2 <_vsnprintf+0x766> +10002a46: f023 0310 bic.w r3, r3, #16 +10002a4a: 2800 cmp r0, #0 +10002a4c: f000 8149 beq.w 10002ce2 <_vsnprintf+0x766> +10002a50: 4611 mov r1, r2 +10002a52: aa12 add r2, sp, #72 @ 0x48 +10002a54: 920b str r2, [sp, #44] @ 0x2c +10002a56: e9cd 5305 strd r5, r3, [sp, #20] +10002a5a: e9cd c603 strd ip, r6, [sp, #12] +10002a5e: 9101 str r1, [sp, #4] +10002a60: 9b0b ldr r3, [sp, #44] @ 0x2c +10002a62: 4642 mov r2, r8 +10002a64: 9300 str r3, [sp, #0] +10002a66: 2300 movs r3, #0 +10002a68: 4651 mov r1, sl +10002a6a: 9302 str r3, [sp, #8] +10002a6c: 4658 mov r0, fp +10002a6e: 464b mov r3, r9 +10002a70: f7fe ff76 bl 10001960 <_ntoa_format> +10002a74: 970a str r7, [sp, #40] @ 0x28 +10002a76: 4680 mov r8, r0 +10002a78: e59e b.n 100025b8 <_vsnprintf+0x3c> +10002a7a: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002a7e: e729 b.n 100028d4 <_vsnprintf+0x358> +10002a80: 2708 movs r7, #8 +10002a82: 46bc mov ip, r7 +10002a84: e7c7 b.n 10002a16 <_vsnprintf+0x49a> +10002a86: f443 6300 orr.w r3, r3, #2048 @ 0x800 +10002a8a: f043 0320 orr.w r3, r3, #32 +10002a8e: e721 b.n 100028d4 <_vsnprintf+0x358> +10002a90: f013 0302 ands.w r3, r3, #2 +10002a94: f000 818e beq.w 10002db4 <_vsnprintf+0x838> +10002a98: 2302 movs r3, #2 +10002a9a: 950a str r5, [sp, #40] @ 0x28 +10002a9c: 461e mov r6, r3 +10002a9e: 460d mov r5, r1 +10002aa0: 4642 mov r2, r8 +10002aa2: 464b mov r3, r9 +10002aa4: 4651 mov r1, sl +10002aa6: 47d8 blx fp +10002aa8: f817 0f01 ldrb.w r0, [r7, #1]! +10002aac: f108 0801 add.w r8, r8, #1 +10002ab0: 2800 cmp r0, #0 +10002ab2: d1f5 bne.n 10002aa0 <_vsnprintf+0x524> +10002ab4: 4629 mov r1, r5 +10002ab6: 4633 mov r3, r6 +10002ab8: 9d0a ldr r5, [sp, #40] @ 0x28 +10002aba: e6e3 b.n 10002884 <_vsnprintf+0x308> +10002abc: 1bd4 subs r4, r2, r7 +10002abe: e6c2 b.n 10002846 <_vsnprintf+0x2ca> +10002ac0: 460a mov r2, r1 +10002ac2: 7888 ldrb r0, [r1, #2] +10002ac4: f043 03c0 orr.w r3, r3, #192 @ 0xc0 +10002ac8: 3203 adds r2, #3 +10002aca: e5d4 b.n 10002676 <_vsnprintf+0xfa> +10002acc: 4604 mov r4, r0 +10002ace: 4680 mov r8, r0 +10002ad0: e646 b.n 10002760 <_vsnprintf+0x1e4> +10002ad2: 2710 movs r7, #16 +10002ad4: f043 0320 orr.w r3, r3, #32 +10002ad8: 46bc mov ip, r7 +10002ada: e79c b.n 10002a16 <_vsnprintf+0x49a> +10002adc: 2d01 cmp r5, #1 +10002ade: f240 80f8 bls.w 10002cd2 <_vsnprintf+0x756> +10002ae2: 4646 mov r6, r8 +10002ae4: f108 37ff add.w r7, r8, #4294967295 @ 0xffffffff +10002ae8: 442f add r7, r5 +10002aea: 4632 mov r2, r6 +10002aec: 464b mov r3, r9 +10002aee: 4651 mov r1, sl +10002af0: 2020 movs r0, #32 +10002af2: 3601 adds r6, #1 +10002af4: 47d8 blx fp +10002af6: 42be cmp r6, r7 +10002af8: d1f7 bne.n 10002aea <_vsnprintf+0x56e> +10002afa: 9b0a ldr r3, [sp, #40] @ 0x28 +10002afc: 4632 mov r2, r6 +10002afe: 7818 ldrb r0, [r3, #0] +10002b00: 4651 mov r1, sl +10002b02: 464b mov r3, r9 +10002b04: 47d8 blx fp +10002b06: 44a8 add r8, r5 +10002b08: 940a str r4, [sp, #40] @ 0x28 +10002b0a: e555 b.n 100025b8 <_vsnprintf+0x3c> +10002b0c: 4646 mov r6, r8 +10002b0e: 42a5 cmp r5, r4 +10002b10: f67f aebb bls.w 1000288a <_vsnprintf+0x30e> +10002b14: 44a8 add r8, r5 +10002b16: eba8 0804 sub.w r8, r8, r4 +10002b1a: 460c mov r4, r1 +10002b1c: 4632 mov r2, r6 +10002b1e: 464b mov r3, r9 +10002b20: 4651 mov r1, sl +10002b22: 2020 movs r0, #32 +10002b24: 3601 adds r6, #1 +10002b26: 47d8 blx fp +10002b28: 4546 cmp r6, r8 +10002b2a: d1f7 bne.n 10002b1c <_vsnprintf+0x5a0> +10002b2c: 4621 mov r1, r4 +10002b2e: e6ac b.n 1000288a <_vsnprintf+0x30e> +10002b30: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002b34: f000 80bb beq.w 10002cae <_vsnprintf+0x732> +10002b38: f44f 6280 mov.w r2, #1024 @ 0x400 +10002b3c: f023 0c11 bic.w ip, r3, #17 +10002b40: f41c 7700 ands.w r7, ip, #512 @ 0x200 +10002b44: 9b0a ldr r3, [sp, #40] @ 0x28 +10002b46: d14a bne.n 10002bde <_vsnprintf+0x662> +10002b48: f41c 7080 ands.w r0, ip, #256 @ 0x100 +10002b4c: f103 0404 add.w r4, r3, #4 +10002b50: f040 8134 bne.w 10002dbc <_vsnprintf+0x840> +10002b54: f01c 0f40 tst.w ip, #64 @ 0x40 +10002b58: f040 80a3 bne.w 10002ca2 <_vsnprintf+0x726> +10002b5c: f01c 0f80 tst.w ip, #128 @ 0x80 +10002b60: f000 81d3 beq.w 10002f0a <_vsnprintf+0x98e> +10002b64: f9b3 1000 ldrsh.w r1, [r3] +10002b68: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002b6c: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002b70: b2bf uxth r7, r7 +10002b72: 0fcb lsrs r3, r1, #31 +10002b74: 2900 cmp r1, #0 +10002b76: f000 8156 beq.w 10002e26 <_vsnprintf+0x8aa> +10002b7a: 463a mov r2, r7 +10002b7c: a912 add r1, sp, #72 @ 0x48 +10002b7e: 460f mov r7, r1 +10002b80: f8df e3d8 ldr.w lr, [pc, #984] @ 10002f5c <_vsnprintf+0x9e0> +10002b84: 910b str r1, [sp, #44] @ 0x2c +10002b86: 930a str r3, [sp, #40] @ 0x28 +10002b88: 950c str r5, [sp, #48] @ 0x30 +10002b8a: e001 b.n 10002b90 <_vsnprintf+0x614> +10002b8c: 2820 cmp r0, #32 +10002b8e: d00f beq.n 10002bb0 <_vsnprintf+0x634> +10002b90: 4615 mov r5, r2 +10002b92: fbae 1302 umull r1, r3, lr, r2 +10002b96: 08db lsrs r3, r3, #3 +10002b98: eb03 0183 add.w r1, r3, r3, lsl #2 +10002b9c: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002ba0: 3130 adds r1, #48 @ 0x30 +10002ba2: 2d09 cmp r5, #9 +10002ba4: 461a mov r2, r3 +10002ba6: f100 0001 add.w r0, r0, #1 +10002baa: f807 1b01 strb.w r1, [r7], #1 +10002bae: d8ed bhi.n 10002b8c <_vsnprintf+0x610> +10002bb0: 9b0a ldr r3, [sp, #40] @ 0x28 +10002bb2: 9d0c ldr r5, [sp, #48] @ 0x30 +10002bb4: e9cd 5c05 strd r5, ip, [sp, #20] +10002bb8: e9cd 0301 strd r0, r3, [sp, #4] +10002bbc: 9604 str r6, [sp, #16] +10002bbe: 9b0b ldr r3, [sp, #44] @ 0x2c +10002bc0: 4642 mov r2, r8 +10002bc2: 9300 str r3, [sp, #0] +10002bc4: 230a movs r3, #10 +10002bc6: 4651 mov r1, sl +10002bc8: 9303 str r3, [sp, #12] +10002bca: 4658 mov r0, fp +10002bcc: 464b mov r3, r9 +10002bce: f7fe fec7 bl 10001960 <_ntoa_format> +10002bd2: 940a str r4, [sp, #40] @ 0x28 +10002bd4: 4680 mov r8, r0 +10002bd6: e4ef b.n 100025b8 <_vsnprintf+0x3c> +10002bd8: f023 030c bic.w r3, r3, #12 +10002bdc: e721 b.n 10002a22 <_vsnprintf+0x4a6> +10002bde: 3307 adds r3, #7 +10002be0: f023 0307 bic.w r3, r3, #7 +10002be4: 4619 mov r1, r3 +10002be6: 4608 mov r0, r1 +10002be8: 685b ldr r3, [r3, #4] +10002bea: f850 1b08 ldr.w r1, [r0], #8 +10002bee: 0fdf lsrs r7, r3, #31 +10002bf0: 900a str r0, [sp, #40] @ 0x28 +10002bf2: ea51 0003 orrs.w r0, r1, r3 +10002bf6: d162 bne.n 10002cbe <_vsnprintf+0x742> +10002bf8: 2a00 cmp r2, #0 +10002bfa: f040 819f bne.w 10002f3c <_vsnprintf+0x9c0> +10002bfe: 4613 mov r3, r2 +10002c00: 4611 mov r1, r2 +10002c02: aa12 add r2, sp, #72 @ 0x48 +10002c04: e9cd 750c strd r7, r5, [sp, #48] @ 0x30 +10002c08: 2000 movs r0, #0 +10002c0a: 4615 mov r5, r2 +10002c0c: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002c10: f8df e348 ldr.w lr, [pc, #840] @ 10002f5c <_vsnprintf+0x9e0> +10002c14: 920b str r2, [sp, #44] @ 0x2c +10002c16: e001 b.n 10002c1c <_vsnprintf+0x6a0> +10002c18: 2820 cmp r0, #32 +10002c1a: d02d beq.n 10002c78 <_vsnprintf+0x6fc> +10002c1c: 185a adds r2, r3, r1 +10002c1e: f142 0200 adc.w r2, r2, #0 +10002c22: fbae 7802 umull r7, r8, lr, r2 +10002c26: f028 0703 bic.w r7, r8, #3 +10002c2a: eb07 0798 add.w r7, r7, r8, lsr #2 +10002c2e: 1bd2 subs r2, r2, r7 +10002c30: 461e mov r6, r3 +10002c32: 1a9b subs r3, r3, r2 +10002c34: f161 0700 sbc.w r7, r1, #0 +10002c38: 460c mov r4, r1 +10002c3a: f04f 31cc mov.w r1, #3435973836 @ 0xcccccccc +10002c3e: fb01 f103 mul.w r1, r1, r3 +10002c42: fb0e 1107 mla r1, lr, r7, r1 +10002c46: fba3 730e umull r7, r3, r3, lr +10002c4a: 4419 add r1, r3 +10002c4c: 2305 movs r3, #5 +10002c4e: f007 0801 and.w r8, r7, #1 +10002c52: fba8 3803 umull r3, r8, r8, r3 +10002c56: 189b adds r3, r3, r2 +10002c58: 2e0a cmp r6, #10 +10002c5a: f103 0330 add.w r3, r3, #48 @ 0x30 +10002c5e: ea4f 0757 mov.w r7, r7, lsr #1 +10002c62: f174 0400 sbcs.w r4, r4, #0 +10002c66: f805 3b01 strb.w r3, [r5], #1 +10002c6a: f100 0001 add.w r0, r0, #1 +10002c6e: ea47 73c1 orr.w r3, r7, r1, lsl #31 +10002c72: ea4f 0151 mov.w r1, r1, lsr #1 +10002c76: d2cf bcs.n 10002c18 <_vsnprintf+0x69c> +10002c78: e9dd 750c ldrd r7, r5, [sp, #48] @ 0x30 +10002c7c: e9dd 680e ldrd r6, r8, [sp, #56] @ 0x38 +10002c80: 9b0b ldr r3, [sp, #44] @ 0x2c +10002c82: 4642 mov r2, r8 +10002c84: 9300 str r3, [sp, #0] +10002c86: 230a movs r3, #10 +10002c88: e9cd 5c05 strd r5, ip, [sp, #20] +10002c8c: e9cd 0701 strd r0, r7, [sp, #4] +10002c90: 9604 str r6, [sp, #16] +10002c92: 9303 str r3, [sp, #12] +10002c94: 464b mov r3, r9 +10002c96: 4651 mov r1, sl +10002c98: 4658 mov r0, fp +10002c9a: f7fe fe61 bl 10001960 <_ntoa_format> +10002c9e: 4680 mov r8, r0 +10002ca0: e48a b.n 100025b8 <_vsnprintf+0x3c> +10002ca2: 7819 ldrb r1, [r3, #0] +10002ca4: 460f mov r7, r1 +10002ca6: e764 b.n 10002b72 <_vsnprintf+0x5f6> +10002ca8: 2710 movs r7, #16 +10002caa: 46bc mov ip, r7 +10002cac: e6b3 b.n 10002a16 <_vsnprintf+0x49a> +10002cae: f023 0c10 bic.w ip, r3, #16 +10002cb2: e745 b.n 10002b40 <_vsnprintf+0x5c4> +10002cb4: 061c lsls r4, r3, #24 +10002cb6: bf4c ite mi +10002cb8: 8812 ldrhmi r2, [r2, #0] +10002cba: 6812 ldrpl r2, [r2, #0] +10002cbc: e6c0 b.n 10002a40 <_vsnprintf+0x4c4> +10002cbe: 460a mov r2, r1 +10002cc0: 1e19 subs r1, r3, #0 +10002cc2: db01 blt.n 10002cc8 <_vsnprintf+0x74c> +10002cc4: 4613 mov r3, r2 +10002cc6: e79c b.n 10002c02 <_vsnprintf+0x686> +10002cc8: 4252 negs r2, r2 +10002cca: 4613 mov r3, r2 +10002ccc: eb61 0141 sbc.w r1, r1, r1, lsl #1 +10002cd0: e797 b.n 10002c02 <_vsnprintf+0x686> +10002cd2: 4613 mov r3, r2 +10002cd4: 4651 mov r1, sl +10002cd6: 7818 ldrb r0, [r3, #0] +10002cd8: 4642 mov r2, r8 +10002cda: 464b mov r3, r9 +10002cdc: 47d8 blx fp +10002cde: 46b0 mov r8, r6 +10002ce0: e648 b.n 10002974 <_vsnprintf+0x3f8> +10002ce2: f013 0f20 tst.w r3, #32 +10002ce6: bf14 ite ne +10002ce8: 2041 movne r0, #65 @ 0x41 +10002cea: 2061 moveq r0, #97 @ 0x61 +10002cec: ac12 add r4, sp, #72 @ 0x48 +10002cee: 46a6 mov lr, r4 +10002cf0: 940b str r4, [sp, #44] @ 0x2c +10002cf2: 930a str r3, [sp, #40] @ 0x28 +10002cf4: f1a0 040a sub.w r4, r0, #10 +10002cf8: 950c str r5, [sp, #48] @ 0x30 +10002cfa: e002 b.n 10002d02 <_vsnprintf+0x786> +10002cfc: 2920 cmp r1, #32 +10002cfe: d012 beq.n 10002d26 <_vsnprintf+0x7aa> +10002d00: 462a mov r2, r5 +10002d02: fbb2 f5fc udiv r5, r2, ip +10002d06: fb0c 2015 mls r0, ip, r5, r2 +10002d0a: b2c3 uxtb r3, r0 +10002d0c: 2809 cmp r0, #9 +10002d0e: f103 0030 add.w r0, r3, #48 @ 0x30 +10002d12: bf8a itet hi +10002d14: 191b addhi r3, r3, r4 +10002d16: b2c3 uxtbls r3, r0 +10002d18: b2db uxtbhi r3, r3 +10002d1a: 4562 cmp r2, ip +10002d1c: f80e 3b01 strb.w r3, [lr], #1 +10002d20: f101 0101 add.w r1, r1, #1 +10002d24: d2ea bcs.n 10002cfc <_vsnprintf+0x780> +10002d26: 9b0a ldr r3, [sp, #40] @ 0x28 +10002d28: 9d0c ldr r5, [sp, #48] @ 0x30 +10002d2a: e694 b.n 10002a56 <_vsnprintf+0x4da> +10002d2c: 9a0a ldr r2, [sp, #40] @ 0x28 +10002d2e: 3207 adds r2, #7 +10002d30: f022 0207 bic.w r2, r2, #7 +10002d34: 6851 ldr r1, [r2, #4] +10002d36: f852 4b08 ldr.w r4, [r2], #8 +10002d3a: 468e mov lr, r1 +10002d3c: 920a str r2, [sp, #40] @ 0x28 +10002d3e: ea54 0201 orrs.w r2, r4, r1 +10002d42: d176 bne.n 10002e32 <_vsnprintf+0x8b6> +10002d44: f023 0310 bic.w r3, r3, #16 +10002d48: 2800 cmp r0, #0 +10002d4a: d072 beq.n 10002e32 <_vsnprintf+0x8b6> +10002d4c: 2200 movs r2, #0 +10002d4e: 4611 mov r1, r2 +10002d50: aa12 add r2, sp, #72 @ 0x48 +10002d52: 920b str r2, [sp, #44] @ 0x2c +10002d54: e9cd 5305 strd r5, r3, [sp, #20] +10002d58: 9b0b ldr r3, [sp, #44] @ 0x2c +10002d5a: 4642 mov r2, r8 +10002d5c: 9300 str r3, [sp, #0] +10002d5e: 2300 movs r3, #0 +10002d60: e9cd c603 strd ip, r6, [sp, #12] +10002d64: 9101 str r1, [sp, #4] +10002d66: 9302 str r3, [sp, #8] +10002d68: e794 b.n 10002c94 <_vsnprintf+0x718> +10002d6a: 42a5 cmp r5, r4 +10002d6c: bf98 it ls +10002d6e: 3401 addls r4, #1 +10002d70: f67f ad74 bls.w 1000285c <_vsnprintf+0x2e0> +10002d74: f44f 6380 mov.w r3, #1024 @ 0x400 +10002d78: e9cd 750a strd r7, r5, [sp, #40] @ 0x28 +10002d7c: eb05 0208 add.w r2, r5, r8 +10002d80: 461f mov r7, r3 +10002d82: 460d mov r5, r1 +10002d84: 1b14 subs r4, r2, r4 +10002d86: 4642 mov r2, r8 +10002d88: 464b mov r3, r9 +10002d8a: 4651 mov r1, sl +10002d8c: 2020 movs r0, #32 +10002d8e: f108 0801 add.w r8, r8, #1 +10002d92: 47d8 blx fp +10002d94: 45a0 cmp r8, r4 +10002d96: d1f6 bne.n 10002d86 <_vsnprintf+0x80a> +10002d98: 463b mov r3, r7 +10002d9a: 9f0a ldr r7, [sp, #40] @ 0x28 +10002d9c: 4629 mov r1, r5 +10002d9e: 7838 ldrb r0, [r7, #0] +10002da0: 9d0b ldr r5, [sp, #44] @ 0x2c +10002da2: 1c6c adds r4, r5, #1 +10002da4: 2800 cmp r0, #0 +10002da6: f43f ad70 beq.w 1000288a <_vsnprintf+0x30e> +10002daa: 2b00 cmp r3, #0 +10002dac: f43f ae75 beq.w 10002a9a <_vsnprintf+0x51e> +10002db0: 2300 movs r3, #0 +10002db2: e553 b.n 1000285c <_vsnprintf+0x2e0> +10002db4: 42a5 cmp r5, r4 +10002db6: d8df bhi.n 10002d78 <_vsnprintf+0x7fc> +10002db8: 3401 adds r4, #1 +10002dba: e66e b.n 10002a9a <_vsnprintf+0x51e> +10002dbc: 6819 ldr r1, [r3, #0] +10002dbe: 0fcb lsrs r3, r1, #31 +10002dc0: 2900 cmp r1, #0 +10002dc2: f000 80a8 beq.w 10002f16 <_vsnprintf+0x99a> +10002dc6: ea81 72e1 eor.w r2, r1, r1, asr #31 +10002dca: eba2 72e1 sub.w r2, r2, r1, asr #31 +10002dce: a912 add r1, sp, #72 @ 0x48 +10002dd0: 4608 mov r0, r1 +10002dd2: f8df e188 ldr.w lr, [pc, #392] @ 10002f5c <_vsnprintf+0x9e0> +10002dd6: 910b str r1, [sp, #44] @ 0x2c +10002dd8: 930a str r3, [sp, #40] @ 0x28 +10002dda: 950c str r5, [sp, #48] @ 0x30 +10002ddc: e001 b.n 10002de2 <_vsnprintf+0x866> +10002dde: 2f20 cmp r7, #32 +10002de0: d00f beq.n 10002e02 <_vsnprintf+0x886> +10002de2: 4615 mov r5, r2 +10002de4: fbae 1302 umull r1, r3, lr, r2 +10002de8: 08db lsrs r3, r3, #3 +10002dea: eb03 0183 add.w r1, r3, r3, lsl #2 +10002dee: eba2 0141 sub.w r1, r2, r1, lsl #1 +10002df2: 3130 adds r1, #48 @ 0x30 +10002df4: 2d09 cmp r5, #9 +10002df6: 461a mov r2, r3 +10002df8: f107 0701 add.w r7, r7, #1 +10002dfc: f800 1b01 strb.w r1, [r0], #1 +10002e00: d8ed bhi.n 10002dde <_vsnprintf+0x862> +10002e02: 9b0a ldr r3, [sp, #40] @ 0x28 +10002e04: 9d0c ldr r5, [sp, #48] @ 0x30 +10002e06: e9cd 5c05 strd r5, ip, [sp, #20] +10002e0a: e9cd 7301 strd r7, r3, [sp, #4] +10002e0e: 9604 str r6, [sp, #16] +10002e10: e6d5 b.n 10002bbe <_vsnprintf+0x642> +10002e12: 2869 cmp r0, #105 @ 0x69 +10002e14: f023 0c10 bic.w ip, r3, #16 +10002e18: f040 808c bne.w 10002f34 <_vsnprintf+0x9b8> +10002e1c: f413 6280 ands.w r2, r3, #1024 @ 0x400 +10002e20: f43f ae8e beq.w 10002b40 <_vsnprintf+0x5c4> +10002e24: e688 b.n 10002b38 <_vsnprintf+0x5bc> +10002e26: 2a00 cmp r2, #0 +10002e28: f43f aea8 beq.w 10002b7c <_vsnprintf+0x600> +10002e2c: aa12 add r2, sp, #72 @ 0x48 +10002e2e: 920b str r2, [sp, #44] @ 0x2c +10002e30: e6c0 b.n 10002bb4 <_vsnprintf+0x638> +10002e32: f013 0f20 tst.w r3, #32 +10002e36: bf14 ite ne +10002e38: 2241 movne r2, #65 @ 0x41 +10002e3a: 2261 moveq r2, #97 @ 0x61 +10002e3c: 2000 movs r0, #0 +10002e3e: a912 add r1, sp, #72 @ 0x48 +10002e40: 3a0a subs r2, #10 +10002e42: e9cd 680e strd r6, r8, [sp, #56] @ 0x38 +10002e46: e9cd 350c strd r3, r5, [sp, #48] @ 0x30 +10002e4a: f8cd b044 str.w fp, [sp, #68] @ 0x44 +10002e4e: 4606 mov r6, r0 +10002e50: 4688 mov r8, r1 +10002e52: 4675 mov r5, lr +10002e54: 4693 mov fp, r2 +10002e56: 910b str r1, [sp, #44] @ 0x2c +10002e58: f8cd c040 str.w ip, [sp, #64] @ 0x40 +10002e5c: e003 b.n 10002e66 <_vsnprintf+0x8ea> +10002e5e: 2e20 cmp r6, #32 +10002e60: d017 beq.n 10002e92 <_vsnprintf+0x916> +10002e62: 4604 mov r4, r0 +10002e64: 460d mov r5, r1 +10002e66: 4629 mov r1, r5 +10002e68: 463a mov r2, r7 +10002e6a: 2300 movs r3, #0 +10002e6c: 4620 mov r0, r4 +10002e6e: f002 ffeb bl 10005e48 <____aeabi_uldivmod_veneer> +10002e72: b2d2 uxtb r2, r2 +10002e74: 2a09 cmp r2, #9 +10002e76: f102 0330 add.w r3, r2, #48 @ 0x30 +10002e7a: bf88 it hi +10002e7c: eb02 030b addhi.w r3, r2, fp +10002e80: 42bc cmp r4, r7 +10002e82: b2db uxtb r3, r3 +10002e84: f175 0500 sbcs.w r5, r5, #0 +10002e88: f808 3b01 strb.w r3, [r8], #1 +10002e8c: f106 0601 add.w r6, r6, #1 +10002e90: d2e5 bcs.n 10002e5e <_vsnprintf+0x8e2> +10002e92: 4631 mov r1, r6 +10002e94: e9dd 350c ldrd r3, r5, [sp, #48] @ 0x30 +10002e98: e9dd cb10 ldrd ip, fp, [sp, #64] @ 0x40 +10002e9c: f8dd 803c ldr.w r8, [sp, #60] @ 0x3c +10002ea0: 9e0e ldr r6, [sp, #56] @ 0x38 +10002ea2: e757 b.n 10002d54 <_vsnprintf+0x7d8> +10002ea4: 990a ldr r1, [sp, #40] @ 0x28 +10002ea6: 6809 ldr r1, [r1, #0] +10002ea8: b951 cbnz r1, 10002ec0 <_vsnprintf+0x944> +10002eaa: f023 0310 bic.w r3, r3, #16 +10002eae: b138 cbz r0, 10002ec0 <_vsnprintf+0x944> +10002eb0: a912 add r1, sp, #72 @ 0x48 +10002eb2: 910b str r1, [sp, #44] @ 0x2c +10002eb4: e9cd 5305 strd r5, r3, [sp, #20] +10002eb8: e9cd c603 strd ip, r6, [sp, #12] +10002ebc: 9201 str r2, [sp, #4] +10002ebe: e5cf b.n 10002a60 <_vsnprintf+0x4e4> +10002ec0: f013 0f20 tst.w r3, #32 +10002ec4: bf14 ite ne +10002ec6: 2041 movne r0, #65 @ 0x41 +10002ec8: 2061 moveq r0, #97 @ 0x61 +10002eca: ac12 add r4, sp, #72 @ 0x48 +10002ecc: 46a6 mov lr, r4 +10002ece: 940b str r4, [sp, #44] @ 0x2c +10002ed0: 930a str r3, [sp, #40] @ 0x28 +10002ed2: f1a0 040a sub.w r4, r0, #10 +10002ed6: 950c str r5, [sp, #48] @ 0x30 +10002ed8: e002 b.n 10002ee0 <_vsnprintf+0x964> +10002eda: 2a20 cmp r2, #32 +10002edc: d012 beq.n 10002f04 <_vsnprintf+0x988> +10002ede: 4629 mov r1, r5 +10002ee0: fbb1 f5fc udiv r5, r1, ip +10002ee4: fb0c 1015 mls r0, ip, r5, r1 +10002ee8: b2c3 uxtb r3, r0 +10002eea: 2809 cmp r0, #9 +10002eec: f103 0030 add.w r0, r3, #48 @ 0x30 +10002ef0: bf8a itet hi +10002ef2: 191b addhi r3, r3, r4 +10002ef4: b2c3 uxtbls r3, r0 +10002ef6: b2db uxtbhi r3, r3 +10002ef8: 4561 cmp r1, ip +10002efa: f80e 3b01 strb.w r3, [lr], #1 +10002efe: f102 0201 add.w r2, r2, #1 +10002f02: d2ea bcs.n 10002eda <_vsnprintf+0x95e> +10002f04: 9b0a ldr r3, [sp, #40] @ 0x28 +10002f06: 9d0c ldr r5, [sp, #48] @ 0x30 +10002f08: e7d4 b.n 10002eb4 <_vsnprintf+0x938> +10002f0a: 6819 ldr r1, [r3, #0] +10002f0c: ea81 77e1 eor.w r7, r1, r1, asr #31 +10002f10: eba7 77e1 sub.w r7, r7, r1, asr #31 +10002f14: e62d b.n 10002b72 <_vsnprintf+0x5f6> +10002f16: 2a00 cmp r2, #0 +10002f18: f43f af59 beq.w 10002dce <_vsnprintf+0x852> +10002f1c: aa12 add r2, sp, #72 @ 0x48 +10002f1e: 920b str r2, [sp, #44] @ 0x2c +10002f20: e771 b.n 10002e06 <_vsnprintf+0x88a> +10002f22: f413 6480 ands.w r4, r3, #1024 @ 0x400 +10002f26: d00d beq.n 10002f44 <_vsnprintf+0x9c8> +10002f28: f013 0402 ands.w r4, r3, #2 +10002f2c: d012 beq.n 10002f54 <_vsnprintf+0x9d8> +10002f2e: 4604 mov r4, r0 +10002f30: 4646 mov r6, r8 +10002f32: e5ec b.n 10002b0e <_vsnprintf+0x592> +10002f34: 270a movs r7, #10 +10002f36: 4663 mov r3, ip +10002f38: 46bc mov ip, r7 +10002f3a: e56c b.n 10002a16 <_vsnprintf+0x49a> +10002f3c: ab12 add r3, sp, #72 @ 0x48 +10002f3e: 2000 movs r0, #0 +10002f40: 930b str r3, [sp, #44] @ 0x2c +10002f42: e69d b.n 10002c80 <_vsnprintf+0x704> +10002f44: f013 0302 ands.w r3, r3, #2 +10002f48: f47f ade0 bne.w 10002b0c <_vsnprintf+0x590> +10002f4c: 2d00 cmp r5, #0 +10002f4e: f47f af13 bne.w 10002d78 <_vsnprintf+0x7fc> +10002f52: e49a b.n 1000288a <_vsnprintf+0x30e> +10002f54: 2d00 cmp r5, #0 +10002f56: f47f af0d bne.w 10002d74 <_vsnprintf+0x7f8> +10002f5a: e496 b.n 1000288a <_vsnprintf+0x30e> +10002f5c: cccccccd .word 0xcccccccd + +10002f60 : +10002f60: b570 push {r4, r5, r6, lr} +10002f62: 4694 mov ip, r2 +10002f64: 461e mov r6, r3 +10002f66: 4605 mov r5, r0 +10002f68: 460c mov r4, r1 +10002f6a: b084 sub sp, #16 +10002f6c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002f70: 4663 mov r3, ip +10002f72: a902 add r1, sp, #8 +10002f74: 9600 str r6, [sp, #0] +10002f76: 4803 ldr r0, [pc, #12] @ (10002f84 ) +10002f78: e9cd 5402 strd r5, r4, [sp, #8] +10002f7c: f7ff fafe bl 1000257c <_vsnprintf> +10002f80: b004 add sp, #16 +10002f82: bd70 pop {r4, r5, r6, pc} +10002f84: 10001b3d .word 0x10001b3d + +10002f88 : +10002f88: b510 push {r4, lr} +10002f8a: 4b09 ldr r3, [pc, #36] @ (10002fb0 ) +10002f8c: b084 sub sp, #16 +10002f8e: 681c ldr r4, [r3, #0] +10002f90: b14c cbz r4, 10002fa6 +10002f92: 4603 mov r3, r0 +10002f94: 9100 str r1, [sp, #0] +10002f96: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff +10002f9a: a903 add r1, sp, #12 +10002f9c: 4805 ldr r0, [pc, #20] @ (10002fb4 ) +10002f9e: 47a0 blx r4 +10002fa0: 2001 movs r0, #1 +10002fa2: b004 add sp, #16 +10002fa4: bd10 pop {r4, pc} +10002fa6: f000 f993 bl 100032d0 <__wrap_puts> +10002faa: 4620 mov r0, r4 +10002fac: b004 add sp, #16 +10002fae: bd10 pop {r4, pc} +10002fb0: 20003108 .word 0x20003108 +10002fb4: 10001b35 .word 0x10001b35 + +10002fb8 <_exit>: +10002fb8: be00 bkpt 0x0000 +10002fba: e7fd b.n 10002fb8 <_exit> + +10002fbc <_sbrk>: +10002fbc: 4a07 ldr r2, [pc, #28] @ (10002fdc <_sbrk+0x20>) +10002fbe: 4603 mov r3, r0 +10002fc0: 6810 ldr r0, [r2, #0] +10002fc2: b138 cbz r0, 10002fd4 <_sbrk+0x18> +10002fc4: 4906 ldr r1, [pc, #24] @ (10002fe0 <_sbrk+0x24>) +10002fc6: 4403 add r3, r0 +10002fc8: 428b cmp r3, r1 +10002fca: bf8c ite hi +10002fcc: f04f 30ff movhi.w r0, #4294967295 @ 0xffffffff +10002fd0: 6013 strls r3, [r2, #0] +10002fd2: 4770 bx lr +10002fd4: 4903 ldr r1, [pc, #12] @ (10002fe4 <_sbrk+0x28>) +10002fd6: 4608 mov r0, r1 +10002fd8: 6011 str r1, [r2, #0] +10002fda: e7f3 b.n 10002fc4 <_sbrk+0x8> +10002fdc: 20003104 .word 0x20003104 +10002fe0: 20080000 .word 0x20080000 +10002fe4: 20003160 .word 0x20003160 + +10002fe8 : +10002fe8: b508 push {r3, lr} +10002fea: f7ff ffe5 bl 10002fb8 <_exit> +10002fee: bf00 nop + +10002ff0 : +10002ff0: b538 push {r3, r4, r5, lr} +10002ff2: 4c06 ldr r4, [pc, #24] @ (1000300c ) +10002ff4: 4d06 ldr r5, [pc, #24] @ (10003010 ) +10002ff6: f7fe f9d9 bl 100013ac +10002ffa: 42ac cmp r4, r5 +10002ffc: d204 bcs.n 10003008 +10002ffe: f854 3b04 ldr.w r3, [r4], #4 +10003002: 4798 blx r3 +10003004: 42ac cmp r4, r5 +10003006: d3fa bcc.n 10002ffe +10003008: bd38 pop {r3, r4, r5, pc} +1000300a: bf00 nop +1000300c: 10005ea0 .word 0x10005ea0 +10003010: 10005ea8 .word 0x10005ea8 + +10003014 : +10003014: 6803 ldr r3, [r0, #0] +10003016: 4608 mov r0, r1 +10003018: 4611 mov r1, r2 +1000301a: 4718 bx r3 + +1000301c : +1000301c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003020: 4615 mov r5, r2 +10003022: 7d42 ldrb r2, [r0, #21] +10003024: 4607 mov r7, r0 +10003026: 4688 mov r8, r1 +10003028: 2a00 cmp r2, #0 +1000302a: d046 beq.n 100030ba +1000302c: 2d00 cmp r5, #0 +1000302e: dd1d ble.n 1000306c +10003030: 780b ldrb r3, [r1, #0] +10003032: 2b0a cmp r3, #10 +10003034: d023 beq.n 1000307e +10003036: 2d01 cmp r5, #1 +10003038: f04f 0c00 mov.w ip, #0 +1000303c: d018 beq.n 10003070 +1000303e: 4646 mov r6, r8 +10003040: 2401 movs r4, #1 +10003042: f816 2f01 ldrb.w r2, [r6, #1]! +10003046: 4621 mov r1, r4 +10003048: 2a0a cmp r2, #10 +1000304a: f104 0401 add.w r4, r4, #1 +1000304e: d022 beq.n 10003096 +10003050: 42a5 cmp r5, r4 +10003052: d1f6 bne.n 10003042 +10003054: 4565 cmp r5, ip +10003056: dc0b bgt.n 10003070 +10003058: eb08 0305 add.w r3, r8, r5 +1000305c: f813 3c01 ldrb.w r3, [r3, #-1] +10003060: f1a3 030d sub.w r3, r3, #13 +10003064: fab3 f383 clz r3, r3 +10003068: 095b lsrs r3, r3, #5 +1000306a: 753b strb r3, [r7, #20] +1000306c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003070: 683b ldr r3, [r7, #0] +10003072: eba5 010c sub.w r1, r5, ip +10003076: eb08 000c add.w r0, r8, ip +1000307a: 4798 blx r3 +1000307c: e7ec b.n 10003058 +1000307e: 7d03 ldrb r3, [r0, #20] +10003080: 2b00 cmp r3, #0 +10003082: d1d8 bne.n 10003036 +10003084: 6803 ldr r3, [r0, #0] +10003086: 2102 movs r1, #2 +10003088: 480f ldr r0, [pc, #60] @ (100030c8 ) +1000308a: 4798 blx r3 +1000308c: 2d01 cmp r5, #1 +1000308e: d0e3 beq.n 10003058 +10003090: f04f 0c01 mov.w ip, #1 +10003094: e7d3 b.n 1000303e +10003096: f816 3c01 ldrb.w r3, [r6, #-1] +1000309a: 2b0d cmp r3, #13 +1000309c: d0d8 beq.n 10003050 +1000309e: 458c cmp ip, r1 +100030a0: eb08 000c add.w r0, r8, ip +100030a4: eba1 010c sub.w r1, r1, ip +100030a8: da01 bge.n 100030ae +100030aa: 683b ldr r3, [r7, #0] +100030ac: 4798 blx r3 +100030ae: 2102 movs r1, #2 +100030b0: 4805 ldr r0, [pc, #20] @ (100030c8 ) +100030b2: 683b ldr r3, [r7, #0] +100030b4: 4798 blx r3 +100030b6: 46a4 mov ip, r4 +100030b8: e7ca b.n 10003050 +100030ba: 4629 mov r1, r5 +100030bc: 4640 mov r0, r8 +100030be: 683b ldr r3, [r7, #0] +100030c0: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} +100030c4: 4718 bx r3 +100030c6: bf00 nop +100030c8: 10006118 .word 0x10006118 + +100030cc : +100030cc: 680b ldr r3, [r1, #0] +100030ce: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +100030d2: 2b80 cmp r3, #128 @ 0x80 +100030d4: 460d mov r5, r1 +100030d6: 4606 mov r6, r0 +100030d8: d005 beq.n 100030e6 +100030da: 1c5a adds r2, r3, #1 +100030dc: 442b add r3, r5 +100030de: 602a str r2, [r5, #0] +100030e0: 711e strb r6, [r3, #4] +100030e2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100030e6: 4b0f ldr r3, [pc, #60] @ (10003124 ) +100030e8: 681c ldr r4, [r3, #0] +100030ea: b1a4 cbz r4, 10003116 +100030ec: 4f0e ldr r7, [pc, #56] @ (10003128 ) +100030ee: f101 0804 add.w r8, r1, #4 +100030f2: e001 b.n 100030f8 +100030f4: 6924 ldr r4, [r4, #16] +100030f6: b174 cbz r4, 10003116 +100030f8: 6823 ldr r3, [r4, #0] +100030fa: 2b00 cmp r3, #0 +100030fc: d0fa beq.n 100030f4 +100030fe: 683b ldr r3, [r7, #0] +10003100: b10b cbz r3, 10003106 +10003102: 42a3 cmp r3, r4 +10003104: d1f6 bne.n 100030f4 +10003106: 4620 mov r0, r4 +10003108: 4641 mov r1, r8 +1000310a: 682a ldr r2, [r5, #0] +1000310c: f7ff ff86 bl 1000301c +10003110: 6924 ldr r4, [r4, #16] +10003112: 2c00 cmp r4, #0 +10003114: d1f0 bne.n 100030f8 +10003116: 2300 movs r3, #0 +10003118: 2201 movs r2, #1 +1000311a: 442b add r3, r5 +1000311c: 602a str r2, [r5, #0] +1000311e: 711e strb r6, [r3, #4] +10003120: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10003124: 200030f8 .word 0x200030f8 +10003128: 20003100 .word 0x20003100 + +1000312c : +1000312c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +10003130: b082 sub sp, #8 +10003132: 460d mov r5, r1 +10003134: 4691 mov r9, r2 +10003136: 461c mov r4, r3 +10003138: 4606 mov r6, r0 +1000313a: f7fd ff67 bl 1000100c +1000313e: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff +10003142: f06f 4700 mvn.w r7, #2147483648 @ 0x80000000 +10003146: 4a2e ldr r2, [pc, #184] @ (10003200 ) +10003148: 1882 adds r2, r0, r2 +1000314a: f141 0300 adc.w r3, r1, #0 +1000314e: 4594 cmp ip, r2 +10003150: eb77 0103 sbcs.w r1, r7, r3 +10003154: bf3c itt cc +10003156: 4662 movcc r2, ip +10003158: 463b movcc r3, r7 +1000315a: 482a ldr r0, [pc, #168] @ (10003204 ) +1000315c: f002 fe7c bl 10005e58 <__mutex_try_enter_block_until_veneer> +10003160: 1c6b adds r3, r5, #1 +10003162: 4680 mov r8, r0 +10003164: d040 beq.n 100031e8 +10003166: b30c cbz r4, 100031ac +10003168: 4f27 ldr r7, [pc, #156] @ (10003208 ) +1000316a: 4b28 ldr r3, [pc, #160] @ (1000320c ) +1000316c: 681c ldr r4, [r3, #0] +1000316e: b1b4 cbz r4, 1000319e +10003170: f1b9 0f00 cmp.w r9, #0 +10003174: d11c bne.n 100031b0 +10003176: f8df 909c ldr.w r9, [pc, #156] @ 10003214 +1000317a: e001 b.n 10003180 +1000317c: 6924 ldr r4, [r4, #16] +1000317e: b174 cbz r4, 1000319e +10003180: 6823 ldr r3, [r4, #0] +10003182: 2b00 cmp r3, #0 +10003184: d0fa beq.n 1000317c +10003186: f8d9 3000 ldr.w r3, [r9] +1000318a: b10b cbz r3, 10003190 +1000318c: 429c cmp r4, r3 +1000318e: d1f5 bne.n 1000317c +10003190: 4620 mov r0, r4 +10003192: 462a mov r2, r5 +10003194: 4631 mov r1, r6 +10003196: 47b8 blx r7 +10003198: 6924 ldr r4, [r4, #16] +1000319a: 2c00 cmp r4, #0 +1000319c: d1f0 bne.n 10003180 +1000319e: f1b8 0f00 cmp.w r8, #0 +100031a2: d126 bne.n 100031f2 +100031a4: 4628 mov r0, r5 +100031a6: b002 add sp, #8 +100031a8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +100031ac: 4f18 ldr r7, [pc, #96] @ (10003210 ) +100031ae: e7dc b.n 1000316a +100031b0: f04f 0a0a mov.w sl, #10 +100031b4: f8df 905c ldr.w r9, [pc, #92] @ 10003214 +100031b8: e002 b.n 100031c0 +100031ba: 6924 ldr r4, [r4, #16] +100031bc: 2c00 cmp r4, #0 +100031be: d0ee beq.n 1000319e +100031c0: 6823 ldr r3, [r4, #0] +100031c2: 2b00 cmp r3, #0 +100031c4: d0f9 beq.n 100031ba +100031c6: f8d9 3000 ldr.w r3, [r9] +100031ca: b10b cbz r3, 100031d0 +100031cc: 42a3 cmp r3, r4 +100031ce: d1f4 bne.n 100031ba +100031d0: 462a mov r2, r5 +100031d2: 4631 mov r1, r6 +100031d4: 4620 mov r0, r4 +100031d6: 47b8 blx r7 +100031d8: 2201 movs r2, #1 +100031da: 4620 mov r0, r4 +100031dc: f10d 0107 add.w r1, sp, #7 +100031e0: f88d a007 strb.w sl, [sp, #7] +100031e4: 47b8 blx r7 +100031e6: e7e8 b.n 100031ba +100031e8: 4630 mov r0, r6 +100031ea: f002 fcad bl 10005b48 +100031ee: 4605 mov r5, r0 +100031f0: e7b9 b.n 10003166 +100031f2: 4804 ldr r0, [pc, #16] @ (10003204 ) +100031f4: f002 fe2c bl 10005e50 <__mutex_exit_veneer> +100031f8: 4628 mov r0, r5 +100031fa: b002 add sp, #8 +100031fc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +10003200: 000f4240 .word 0x000f4240 +10003204: 20000b80 .word 0x20000b80 +10003208: 1000301d .word 0x1000301d +1000320c: 200030f8 .word 0x200030f8 +10003210: 10003015 .word 0x10003015 +10003214: 20003100 .word 0x20003100 + +10003218 : +10003218: 4a08 ldr r2, [pc, #32] @ (1000323c ) +1000321a: 6813 ldr r3, [r2, #0] +1000321c: b923 cbnz r3, 10003228 +1000321e: e00a b.n 10003236 +10003220: f103 0210 add.w r2, r3, #16 +10003224: 691b ldr r3, [r3, #16] +10003226: b133 cbz r3, 10003236 +10003228: 4283 cmp r3, r0 +1000322a: d1f9 bne.n 10003220 +1000322c: b929 cbnz r1, 1000323a +1000322e: 6918 ldr r0, [r3, #16] +10003230: 6010 str r0, [r2, #0] +10003232: 6119 str r1, [r3, #16] +10003234: 4770 bx lr +10003236: b101 cbz r1, 1000323a +10003238: 6010 str r0, [r2, #0] +1000323a: 4770 bx lr +1000323c: 200030f8 .word 0x200030f8 + +10003240 : +10003240: b508 push {r3, lr} +10003242: f000 f9a3 bl 1000358c +10003246: 2001 movs r0, #1 +10003248: bd08 pop {r3, pc} +1000324a: bf00 nop + +1000324c <__wrap_putchar>: +1000324c: b5f0 push {r4, r5, r6, r7, lr} +1000324e: b083 sub sp, #12 +10003250: 4606 mov r6, r0 +10003252: f88d 0007 strb.w r0, [sp, #7] +10003256: f7fd fed9 bl 1000100c +1000325a: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff +1000325e: f06f 4400 mvn.w r4, #2147483648 @ 0x80000000 +10003262: 4a17 ldr r2, [pc, #92] @ (100032c0 <__wrap_putchar+0x74>) +10003264: 1882 adds r2, r0, r2 +10003266: f141 0300 adc.w r3, r1, #0 +1000326a: 4295 cmp r5, r2 +1000326c: eb74 0103 sbcs.w r1, r4, r3 +10003270: bf3c itt cc +10003272: 4623 movcc r3, r4 +10003274: 462a movcc r2, r5 +10003276: 4813 ldr r0, [pc, #76] @ (100032c4 <__wrap_putchar+0x78>) +10003278: f002 fdee bl 10005e58 <__mutex_try_enter_block_until_veneer> +1000327c: 4b12 ldr r3, [pc, #72] @ (100032c8 <__wrap_putchar+0x7c>) +1000327e: 4607 mov r7, r0 +10003280: 681c ldr r4, [r3, #0] +10003282: b19c cbz r4, 100032ac <__wrap_putchar+0x60> +10003284: 4d11 ldr r5, [pc, #68] @ (100032cc <__wrap_putchar+0x80>) +10003286: e001 b.n 1000328c <__wrap_putchar+0x40> +10003288: 6924 ldr r4, [r4, #16] +1000328a: b17c cbz r4, 100032ac <__wrap_putchar+0x60> +1000328c: 6823 ldr r3, [r4, #0] +1000328e: 2b00 cmp r3, #0 +10003290: d0fa beq.n 10003288 <__wrap_putchar+0x3c> +10003292: 682b ldr r3, [r5, #0] +10003294: b10b cbz r3, 1000329a <__wrap_putchar+0x4e> +10003296: 429c cmp r4, r3 +10003298: d1f6 bne.n 10003288 <__wrap_putchar+0x3c> +1000329a: 4620 mov r0, r4 +1000329c: 2201 movs r2, #1 +1000329e: f10d 0107 add.w r1, sp, #7 +100032a2: f7ff febb bl 1000301c +100032a6: 6924 ldr r4, [r4, #16] +100032a8: 2c00 cmp r4, #0 +100032aa: d1ef bne.n 1000328c <__wrap_putchar+0x40> +100032ac: b917 cbnz r7, 100032b4 <__wrap_putchar+0x68> +100032ae: 4630 mov r0, r6 +100032b0: b003 add sp, #12 +100032b2: bdf0 pop {r4, r5, r6, r7, pc} +100032b4: 4803 ldr r0, [pc, #12] @ (100032c4 <__wrap_putchar+0x78>) +100032b6: f002 fdcb bl 10005e50 <__mutex_exit_veneer> +100032ba: 4630 mov r0, r6 +100032bc: b003 add sp, #12 +100032be: bdf0 pop {r4, r5, r6, r7, pc} +100032c0: 000f4240 .word 0x000f4240 +100032c4: 20000b80 .word 0x20000b80 +100032c8: 200030f8 .word 0x200030f8 +100032cc: 20003100 .word 0x20003100 + +100032d0 <__wrap_puts>: +100032d0: b538 push {r3, r4, r5, lr} +100032d2: 4604 mov r4, r0 +100032d4: f002 fc38 bl 10005b48 +100032d8: 2301 movs r3, #1 +100032da: 4605 mov r5, r0 +100032dc: 461a mov r2, r3 +100032de: 4620 mov r0, r4 +100032e0: 4629 mov r1, r5 +100032e2: f7ff ff23 bl 1000312c +100032e6: 4b08 ldr r3, [pc, #32] @ (10003308 <__wrap_puts+0x38>) +100032e8: 681c ldr r4, [r3, #0] +100032ea: b12c cbz r4, 100032f8 <__wrap_puts+0x28> +100032ec: 6863 ldr r3, [r4, #4] +100032ee: b12b cbz r3, 100032fc <__wrap_puts+0x2c> +100032f0: 4798 blx r3 +100032f2: 6924 ldr r4, [r4, #16] +100032f4: 2c00 cmp r4, #0 +100032f6: d1f9 bne.n 100032ec <__wrap_puts+0x1c> +100032f8: 4628 mov r0, r5 +100032fa: bd38 pop {r3, r4, r5, pc} +100032fc: 6924 ldr r4, [r4, #16] +100032fe: 2c00 cmp r4, #0 +10003300: d1f4 bne.n 100032ec <__wrap_puts+0x1c> +10003302: 4628 mov r0, r5 +10003304: bd38 pop {r3, r4, r5, pc} +10003306: bf00 nop +10003308: 200030f8 .word 0x200030f8 + +1000330c <__wrap_vprintf>: +1000330c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +10003310: b0a2 sub sp, #136 @ 0x88 +10003312: 4604 mov r4, r0 +10003314: 460d mov r5, r1 +10003316: f7fd fe79 bl 1000100c +1000331a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff +1000331e: f06f 4600 mvn.w r6, #2147483648 @ 0x80000000 +10003322: 4a26 ldr r2, [pc, #152] @ (100033bc <__wrap_vprintf+0xb0>) +10003324: f8df 80a4 ldr.w r8, [pc, #164] @ 100033cc <__wrap_vprintf+0xc0> +10003328: 1882 adds r2, r0, r2 +1000332a: f141 0300 adc.w r3, r1, #0 +1000332e: 4297 cmp r7, r2 +10003330: eb76 0103 sbcs.w r1, r6, r3 +10003334: bf3c itt cc +10003336: 463a movcc r2, r7 +10003338: 4633 movcc r3, r6 +1000333a: 4821 ldr r0, [pc, #132] @ (100033c0 <__wrap_vprintf+0xb4>) +1000333c: f002 fd8c bl 10005e58 <__mutex_try_enter_block_until_veneer> +10003340: 2700 movs r7, #0 +10003342: 462b mov r3, r5 +10003344: 4622 mov r2, r4 +10003346: 4606 mov r6, r0 +10003348: a901 add r1, sp, #4 +1000334a: 481e ldr r0, [pc, #120] @ (100033c4 <__wrap_vprintf+0xb8>) +1000334c: 9701 str r7, [sp, #4] +1000334e: f7ff fe07 bl 10002f60 +10003352: 9b01 ldr r3, [sp, #4] +10003354: 4605 mov r5, r0 +10003356: f8d8 4000 ldr.w r4, [r8] +1000335a: b1c3 cbz r3, 1000338e <__wrap_vprintf+0x82> +1000335c: 2c00 cmp r4, #0 +1000335e: d02b beq.n 100033b8 <__wrap_vprintf+0xac> +10003360: 4f19 ldr r7, [pc, #100] @ (100033c8 <__wrap_vprintf+0xbc>) +10003362: e001 b.n 10003368 <__wrap_vprintf+0x5c> +10003364: 6924 ldr r4, [r4, #16] +10003366: b174 cbz r4, 10003386 <__wrap_vprintf+0x7a> +10003368: 6823 ldr r3, [r4, #0] +1000336a: 2b00 cmp r3, #0 +1000336c: d0fa beq.n 10003364 <__wrap_vprintf+0x58> +1000336e: 683b ldr r3, [r7, #0] +10003370: b10b cbz r3, 10003376 <__wrap_vprintf+0x6a> +10003372: 42a3 cmp r3, r4 +10003374: d1f6 bne.n 10003364 <__wrap_vprintf+0x58> +10003376: 4620 mov r0, r4 +10003378: 9a01 ldr r2, [sp, #4] +1000337a: a902 add r1, sp, #8 +1000337c: f7ff fe4e bl 1000301c +10003380: 6924 ldr r4, [r4, #16] +10003382: 2c00 cmp r4, #0 +10003384: d1f0 bne.n 10003368 <__wrap_vprintf+0x5c> +10003386: 2300 movs r3, #0 +10003388: f8d8 4000 ldr.w r4, [r8] +1000338c: 9301 str r3, [sp, #4] +1000338e: b12c cbz r4, 1000339c <__wrap_vprintf+0x90> +10003390: 6863 ldr r3, [r4, #4] +10003392: b143 cbz r3, 100033a6 <__wrap_vprintf+0x9a> +10003394: 4798 blx r3 +10003396: 6924 ldr r4, [r4, #16] +10003398: 2c00 cmp r4, #0 +1000339a: d1f9 bne.n 10003390 <__wrap_vprintf+0x84> +1000339c: b92e cbnz r6, 100033aa <__wrap_vprintf+0x9e> +1000339e: 4628 mov r0, r5 +100033a0: b022 add sp, #136 @ 0x88 +100033a2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100033a6: 6924 ldr r4, [r4, #16] +100033a8: e7f1 b.n 1000338e <__wrap_vprintf+0x82> +100033aa: 4805 ldr r0, [pc, #20] @ (100033c0 <__wrap_vprintf+0xb4>) +100033ac: f002 fd50 bl 10005e50 <__mutex_exit_veneer> +100033b0: 4628 mov r0, r5 +100033b2: b022 add sp, #136 @ 0x88 +100033b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +100033b8: 9401 str r4, [sp, #4] +100033ba: e7ef b.n 1000339c <__wrap_vprintf+0x90> +100033bc: 000f4240 .word 0x000f4240 +100033c0: 20000b80 .word 0x20000b80 +100033c4: 100030cd .word 0x100030cd +100033c8: 20003100 .word 0x20003100 +100033cc: 200030f8 .word 0x200030f8 + +100033d0 <__wrap_printf>: +100033d0: b40f push {r0, r1, r2, r3} +100033d2: b500 push {lr} +100033d4: b083 sub sp, #12 +100033d6: a904 add r1, sp, #16 +100033d8: f851 0b04 ldr.w r0, [r1], #4 +100033dc: 9101 str r1, [sp, #4] +100033de: f7ff ff95 bl 1000330c <__wrap_vprintf> +100033e2: b003 add sp, #12 +100033e4: f85d eb04 ldr.w lr, [sp], #4 +100033e8: b004 add sp, #16 +100033ea: 4770 bx lr + +100033ec : +100033ec: f1b1 0c00 subs.w ip, r1, #0 +100033f0: dd1d ble.n 1000342e +100033f2: 4a0f ldr r2, [pc, #60] @ (10003430 ) +100033f4: 4b0f ldr r3, [pc, #60] @ (10003434 ) +100033f6: 6812 ldr r2, [r2, #0] +100033f8: b530 push {r4, r5, lr} +100033fa: 1ad3 subs r3, r2, r3 +100033fc: fab3 f383 clz r3, r3 +10003400: 240d movs r4, #13 +10003402: 4d0d ldr r5, [pc, #52] @ (10003438 ) +10003404: 095b lsrs r3, r3, #5 +10003406: 1e41 subs r1, r0, #1 +10003408: f935 e013 ldrsh.w lr, [r5, r3, lsl #1] +1000340c: 448c add ip, r1 +1000340e: f811 0f01 ldrb.w r0, [r1, #1]! +10003412: 4586 cmp lr, r0 +10003414: d006 beq.n 10003424 +10003416: 6993 ldr r3, [r2, #24] +10003418: 069b lsls r3, r3, #26 +1000341a: d4fc bmi.n 10003416 +1000341c: 4561 cmp r1, ip +1000341e: 6010 str r0, [r2, #0] +10003420: d1f5 bne.n 1000340e +10003422: bd30 pop {r4, r5, pc} +10003424: 6993 ldr r3, [r2, #24] +10003426: 069d lsls r5, r3, #26 +10003428: d4fc bmi.n 10003424 +1000342a: 6014 str r4, [r2, #0] +1000342c: e7f3 b.n 10003416 +1000342e: 4770 bx lr +10003430: 20003158 .word 0x20003158 +10003434: 40078000 .word 0x40078000 +10003438: 20003154 .word 0x20003154 + +1000343c : +1000343c: 4b22 ldr r3, [pc, #136] @ (100034c8 ) +1000343e: f1b1 0c00 subs.w ip, r1, #0 +10003442: b410 push {r4} +10003444: 681c ldr r4, [r3, #0] +10003446: dd2e ble.n 100034a6 +10003448: 4603 mov r3, r0 +1000344a: 2000 movs r0, #0 +1000344c: 4a1f ldr r2, [pc, #124] @ (100034cc ) +1000344e: 1e59 subs r1, r3, #1 +10003450: 6812 ldr r2, [r2, #0] +10003452: 6993 ldr r3, [r2, #24] +10003454: 06db lsls r3, r3, #27 +10003456: d417 bmi.n 10003488 +10003458: 3001 adds r0, #1 +1000345a: 6993 ldr r3, [r2, #24] +1000345c: 06db lsls r3, r3, #27 +1000345e: d4fc bmi.n 1000345a +10003460: 6813 ldr r3, [r2, #0] +10003462: 4584 cmp ip, r0 +10003464: f801 3f01 strb.w r3, [r1, #1]! +10003468: d1f3 bne.n 10003452 +1000346a: b14c cbz r4, 10003480 +1000346c: 2150 movs r1, #80 @ 0x50 +1000346e: 4613 mov r3, r2 +10003470: 6391 str r1, [r2, #56] @ 0x38 +10003472: f853 2f34 ldr.w r2, [r3, #52]! +10003476: f002 0238 and.w r2, r2, #56 @ 0x38 +1000347a: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000347e: 601a str r2, [r3, #0] +10003480: 4660 mov r0, ip +10003482: f85d 4b04 ldr.w r4, [sp], #4 +10003486: 4770 bx lr +10003488: b14c cbz r4, 1000349e +1000348a: 2150 movs r1, #80 @ 0x50 +1000348c: 4613 mov r3, r2 +1000348e: 6391 str r1, [r2, #56] @ 0x38 +10003490: f853 2f34 ldr.w r2, [r3, #52]! +10003494: f002 0238 and.w r2, r2, #56 @ 0x38 +10003498: f503 5380 add.w r3, r3, #4096 @ 0x1000 +1000349c: 601a str r2, [r3, #0] +1000349e: b178 cbz r0, 100034c0 +100034a0: f85d 4b04 ldr.w r4, [sp], #4 +100034a4: 4770 bx lr +100034a6: b15c cbz r4, 100034c0 +100034a8: 4b08 ldr r3, [pc, #32] @ (100034cc ) +100034aa: 2150 movs r1, #80 @ 0x50 +100034ac: 681a ldr r2, [r3, #0] +100034ae: 4613 mov r3, r2 +100034b0: 6391 str r1, [r2, #56] @ 0x38 +100034b2: f853 2f34 ldr.w r2, [r3, #52]! +100034b6: f002 0238 and.w r2, r2, #56 @ 0x38 +100034ba: f503 5380 add.w r3, r3, #4096 @ 0x1000 +100034be: 601a str r2, [r3, #0] +100034c0: f06f 0002 mvn.w r0, #2 +100034c4: e7dd b.n 10003482 +100034c6: bf00 nop +100034c8: 200030c4 .word 0x200030c4 +100034cc: 20003158 .word 0x20003158 + +100034d0 : +100034d0: 4b05 ldr r3, [pc, #20] @ (100034e8 ) +100034d2: 681b ldr r3, [r3, #0] +100034d4: b133 cbz r3, 100034e4 +100034d6: 2100 movs r1, #0 +100034d8: 4a04 ldr r2, [pc, #16] @ (100034ec ) +100034da: 4805 ldr r0, [pc, #20] @ (100034f0 ) +100034dc: 6812 ldr r2, [r2, #0] +100034de: 6800 ldr r0, [r0, #0] +100034e0: 6391 str r1, [r2, #56] @ 0x38 +100034e2: 4718 bx r3 +100034e4: 4770 bx lr +100034e6: bf00 nop +100034e8: 200030c4 .word 0x200030c4 +100034ec: 20003158 .word 0x20003158 +100034f0: 200030c8 .word 0x200030c8 + +100034f4 : +100034f4: 4b02 ldr r3, [pc, #8] @ (10003500 ) +100034f6: 681a ldr r2, [r3, #0] +100034f8: 6993 ldr r3, [r2, #24] +100034fa: 071b lsls r3, r3, #28 +100034fc: d4fc bmi.n 100034f8 +100034fe: 4770 bx lr +10003500: 20003158 .word 0x20003158 + +10003504 : +10003504: b5f8 push {r3, r4, r5, r6, r7, lr} +10003506: 4f1c ldr r7, [pc, #112] @ (10003578 ) +10003508: 4d1c ldr r5, [pc, #112] @ (1000357c ) +1000350a: 683a ldr r2, [r7, #0] +1000350c: 4e1c ldr r6, [pc, #112] @ (10003580 ) +1000350e: 42aa cmp r2, r5 +10003510: bf14 ite ne +10003512: 2521 movne r5, #33 @ 0x21 +10003514: 2522 moveq r5, #34 @ 0x22 +10003516: 4604 mov r4, r0 +10003518: f8d6 c000 ldr.w ip, [r6] +1000351c: b118 cbz r0, 10003526 +1000351e: f1bc 0f00 cmp.w ip, #0 +10003522: d010 beq.n 10003546 +10003524: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003526: f1bc 0f00 cmp.w ip, #0 +1000352a: d0fb beq.n 10003524 +1000352c: 4601 mov r1, r0 +1000352e: 6390 str r0, [r2, #56] @ 0x38 +10003530: 4628 mov r0, r5 +10003532: f7fc fff5 bl 10000520 +10003536: 4628 mov r0, r5 +10003538: 4912 ldr r1, [pc, #72] @ (10003584 ) +1000353a: f7fd f837 bl 100005ac +1000353e: 4b12 ldr r3, [pc, #72] @ (10003588 ) +10003540: 6034 str r4, [r6, #0] +10003542: 601c str r4, [r3, #0] +10003544: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003546: 460b mov r3, r1 +10003548: 4a0f ldr r2, [pc, #60] @ (10003588 ) +1000354a: 490e ldr r1, [pc, #56] @ (10003584 ) +1000354c: 6030 str r0, [r6, #0] +1000354e: 4628 mov r0, r5 +10003550: 6013 str r3, [r2, #0] +10003552: f7fc fffb bl 1000054c +10003556: 2101 movs r1, #1 +10003558: 4628 mov r0, r5 +1000355a: f7fc ffe1 bl 10000520 +1000355e: 683a ldr r2, [r7, #0] +10003560: 2150 movs r1, #80 @ 0x50 +10003562: 4613 mov r3, r2 +10003564: 6391 str r1, [r2, #56] @ 0x38 +10003566: f853 2f34 ldr.w r2, [r3, #52]! +1000356a: f002 0238 and.w r2, r2, #56 @ 0x38 +1000356e: f503 5380 add.w r3, r3, #4096 @ 0x1000 +10003572: 601a str r2, [r3, #0] +10003574: bdf8 pop {r3, r4, r5, r6, r7, pc} +10003576: bf00 nop +10003578: 20003158 .word 0x20003158 +1000357c: 40078000 .word 0x40078000 +10003580: 200030c4 .word 0x200030c4 +10003584: 100034d1 .word 0x100034d1 +10003588: 200030c8 .word 0x200030c8 + +1000358c : +1000358c: b510 push {r4, lr} +1000358e: 490e ldr r1, [pc, #56] @ (100035c8 ) +10003590: 4c0e ldr r4, [pc, #56] @ (100035cc ) +10003592: 480f ldr r0, [pc, #60] @ (100035d0 ) +10003594: 4a0f ldr r2, [pc, #60] @ (100035d4 ) +10003596: 4b10 ldr r3, [pc, #64] @ (100035d8 ) +10003598: 7800 ldrb r0, [r0, #0] +1000359a: 6021 str r1, [r4, #0] +1000359c: 2000 movs r0, #0 +1000359e: 2102 movs r1, #2 +100035a0: 7812 ldrb r2, [r2, #0] +100035a2: 781b ldrb r3, [r3, #0] +100035a4: f7fc ff1a bl 100003dc +100035a8: 2102 movs r1, #2 +100035aa: 2001 movs r0, #1 +100035ac: f7fc ff16 bl 100003dc +100035b0: f44f 31e1 mov.w r1, #115200 @ 0x1c200 +100035b4: 6820 ldr r0, [r4, #0] +100035b6: f7fd fd73 bl 100010a0 +100035ba: e8bd 4010 ldmia.w sp!, {r4, lr} +100035be: 2101 movs r1, #1 +100035c0: 4806 ldr r0, [pc, #24] @ (100035dc ) +100035c2: f7ff be29 b.w 10003218 +100035c6: bf00 nop +100035c8: 40070000 .word 0x40070000 +100035cc: 20003158 .word 0x20003158 +100035d0: 100061ec .word 0x100061ec +100035d4: 100061e8 .word 0x100061e8 +100035d8: 100061e4 .word 0x100061e4 +100035dc: 2000060c .word 0x2000060c + +100035e0 : +100035e0: 2301 movs r3, #1 +100035e2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100035e6: f5ad 7d07 sub.w sp, sp, #540 @ 0x21c +100035ea: f20d 1117 addw r1, sp, #279 @ 0x117 +100035ee: f20d 2417 addw r4, sp, #535 @ 0x217 +100035f2: b258 sxtb r0, r3 +100035f4: 0042 lsls r2, r0, #1 +100035f6: b252 sxtb r2, r2 +100035f8: 2800 cmp r0, #0 +100035fa: f801 3f01 strb.w r3, [r1, #1]! +100035fe: bfb8 it lt +10003600: f082 021b eorlt.w r2, r2, #27 +10003604: 4053 eors r3, r2 +10003606: 42a1 cmp r1, r4 +10003608: b2db uxtb r3, r3 +1000360a: d1f2 bne.n 100035f2 +1000360c: 2301 movs r3, #1 +1000360e: 2100 movs r1, #0 +10003610: f10d 0a18 add.w sl, sp, #24 +10003614: b258 sxtb r0, r3 +10003616: 0042 lsls r2, r0, #1 +10003618: b252 sxtb r2, r2 +1000361a: 2800 cmp r0, #0 +1000361c: f80a 1003 strb.w r1, [sl, r3] +10003620: bfb8 it lt +10003622: f082 021b eorlt.w r2, r2, #27 +10003626: 3101 adds r1, #1 +10003628: 4053 eors r3, r2 +1000362a: f5b1 7f80 cmp.w r1, #256 @ 0x100 +1000362e: b2db uxtb r3, r3 +10003630: d1f0 bne.n 10003614 +10003632: 2202 movs r2, #2 +10003634: 4b72 ldr r3, [pc, #456] @ (10003800 ) +10003636: 2008 movs r0, #8 +10003638: 605a str r2, [r3, #4] +1000363a: 2204 movs r2, #4 +1000363c: e9c3 2002 strd r2, r0, [r3, #8] +10003640: 2210 movs r2, #16 +10003642: 2020 movs r0, #32 +10003644: 261b movs r6, #27 +10003646: e9c3 2004 strd r2, r0, [r3, #16] +1000364a: 2101 movs r1, #1 +1000364c: 2240 movs r2, #64 @ 0x40 +1000364e: 2080 movs r0, #128 @ 0x80 +10003650: 2736 movs r7, #54 @ 0x36 +10003652: e9c3 2006 strd r2, r0, [r3, #24] +10003656: e9c3 6708 strd r6, r7, [r3, #32] +1000365a: 2200 movs r2, #0 +1000365c: 6019 str r1, [r3, #0] +1000365e: 2363 movs r3, #99 @ 0x63 +10003660: 4655 mov r5, sl +10003662: 4c68 ldr r4, [pc, #416] @ (10003804 ) +10003664: 4e68 ldr r6, [pc, #416] @ (10003808 ) +10003666: 7023 strb r3, [r4, #0] +10003668: f886 2063 strb.w r2, [r6, #99] @ 0x63 +1000366c: a846 add r0, sp, #280 @ 0x118 +1000366e: f815 3f01 ldrb.w r3, [r5, #1]! +10003672: f1c3 03ff rsb r3, r3, #255 @ 0xff +10003676: 5cc3 ldrb r3, [r0, r3] +10003678: 09da lsrs r2, r3, #7 +1000367a: ea42 0243 orr.w r2, r2, r3, lsl #1 +1000367e: b257 sxtb r7, r2 +10003680: f3c2 1c42 ubfx ip, r2, #5, #3 +10003684: ea4c 0cc7 orr.w ip, ip, r7, lsl #3 +10003688: ea83 030c eor.w r3, r3, ip +1000368c: f3c2 1cc0 ubfx ip, r2, #7, #1 +10003690: 407b eors r3, r7 +10003692: ea4c 0c47 orr.w ip, ip, r7, lsl #1 +10003696: f3c2 1281 ubfx r2, r2, #6, #2 +1000369a: ea83 030c eor.w r3, r3, ip +1000369e: ea42 0287 orr.w r2, r2, r7, lsl #2 +100036a2: 4053 eors r3, r2 +100036a4: b2db uxtb r3, r3 +100036a6: f083 0363 eor.w r3, r3, #99 @ 0x63 +100036aa: 54f1 strb r1, [r6, r3] +100036ac: 3101 adds r1, #1 +100036ae: f5b1 7f80 cmp.w r1, #256 @ 0x100 +100036b2: f804 3f01 strb.w r3, [r4, #1]! +100036b6: d1da bne.n 1000366e +100036b8: f89a 300e ldrb.w r3, [sl, #14] +100036bc: 4953 ldr r1, [pc, #332] @ (1000380c ) +100036be: 9302 str r3, [sp, #8] +100036c0: f89a 3009 ldrb.w r3, [sl, #9] +100036c4: f8df c168 ldr.w ip, [pc, #360] @ 10003830 +100036c8: 9303 str r3, [sp, #12] +100036ca: f89a 300d ldrb.w r3, [sl, #13] +100036ce: 4f50 ldr r7, [pc, #320] @ (10003810 ) +100036d0: 9304 str r3, [sp, #16] +100036d2: f89a 300b ldrb.w r3, [sl, #11] +100036d6: 4e4f ldr r6, [pc, #316] @ (10003814 ) +100036d8: 4d4f ldr r5, [pc, #316] @ (10003818 ) +100036da: 9305 str r3, [sp, #20] +100036dc: f501 7e80 add.w lr, r1, #256 @ 0x100 +100036e0: f811 2f01 ldrb.w r2, [r1, #1]! +100036e4: fa4f f882 sxtb.w r8, r2 +100036e8: ea4f 0348 mov.w r3, r8, lsl #1 +100036ec: f1b8 0f00 cmp.w r8, #0 +100036f0: b25b sxtb r3, r3 +100036f2: bfb8 it lt +100036f4: f083 031b eorlt.w r3, r3, #27 +100036f8: eb02 2402 add.w r4, r2, r2, lsl #8 +100036fc: b2db uxtb r3, r3 +100036fe: 405a eors r2, r3 +10003700: ea43 2304 orr.w r3, r3, r4, lsl #8 +10003704: ea83 6302 eor.w r3, r3, r2, lsl #24 +10003708: ea4f 6833 mov.w r8, r3, ror #24 +1000370c: ea4f 4433 mov.w r4, r3, ror #16 +10003710: ea4f 2233 mov.w r2, r3, ror #8 +10003714: 4571 cmp r1, lr +10003716: f84c 3f04 str.w r3, [ip, #4]! +1000371a: f847 8f04 str.w r8, [r7, #4]! +1000371e: f846 4f04 str.w r4, [r6, #4]! +10003722: f845 2f04 str.w r2, [r5, #4]! +10003726: d1db bne.n 100036e0 +10003728: 493c ldr r1, [pc, #240] @ (1000381c ) +1000372a: f8df 8108 ldr.w r8, [pc, #264] @ 10003834 +1000372e: 4f3c ldr r7, [pc, #240] @ (10003820 ) +10003730: 4e3c ldr r6, [pc, #240] @ (10003824 ) +10003732: 4d3d ldr r5, [pc, #244] @ (10003828 ) +10003734: 4c3d ldr r4, [pc, #244] @ (1000382c ) +10003736: f501 7b80 add.w fp, r1, #256 @ 0x100 +1000373a: f811 3f01 ldrb.w r3, [r1, #1]! +1000373e: 2b00 cmp r3, #0 +10003740: d050 beq.n 100037e4 +10003742: f81a 9003 ldrb.w r9, [sl, r3] +10003746: 9b04 ldr r3, [sp, #16] +10003748: 4559 cmp r1, fp +1000374a: eb09 0203 add.w r2, r9, r3 +1000374e: 9b03 ldr r3, [sp, #12] +10003750: eb09 0c03 add.w ip, r9, r3 +10003754: fba4 e302 umull lr, r3, r4, r2 +10003758: ea4f 13d3 mov.w r3, r3, lsr #7 +1000375c: ebc3 2303 rsb r3, r3, r3, lsl #8 +10003760: eba2 0203 sub.w r2, r2, r3 +10003764: f810 e002 ldrb.w lr, [r0, r2] +10003768: ea4f 430e mov.w r3, lr, lsl #16 +1000376c: 9301 str r3, [sp, #4] +1000376e: 9b02 ldr r3, [sp, #8] +10003770: eb03 0209 add.w r2, r3, r9 +10003774: 9b05 ldr r3, [sp, #20] +10003776: 4499 add r9, r3 +10003778: fba4 e30c umull lr, r3, r4, ip +1000377c: ea4f 13d3 mov.w r3, r3, lsr #7 +10003780: ebc3 2303 rsb r3, r3, r3, lsl #8 +10003784: ebac 0c03 sub.w ip, ip, r3 +10003788: f810 c00c ldrb.w ip, [r0, ip] +1000378c: 9b01 ldr r3, [sp, #4] +1000378e: ea43 2c0c orr.w ip, r3, ip, lsl #8 +10003792: fba4 e302 umull lr, r3, r4, r2 +10003796: ea4f 13d3 mov.w r3, r3, lsr #7 +1000379a: ebc3 2303 rsb r3, r3, r3, lsl #8 +1000379e: eba2 0203 sub.w r2, r2, r3 +100037a2: 5c83 ldrb r3, [r0, r2] +100037a4: ea8c 0303 eor.w r3, ip, r3 +100037a8: fba4 c209 umull ip, r2, r4, r9 +100037ac: ea4f 12d2 mov.w r2, r2, lsr #7 +100037b0: ebc2 2202 rsb r2, r2, r2, lsl #8 +100037b4: eba9 0202 sub.w r2, r9, r2 +100037b8: 5c82 ldrb r2, [r0, r2] +100037ba: ea43 6302 orr.w r3, r3, r2, lsl #24 +100037be: ea4f 6233 mov.w r2, r3, ror #24 +100037c2: f848 3f04 str.w r3, [r8, #4]! +100037c6: f847 2f04 str.w r2, [r7, #4]! +100037ca: ea4f 4233 mov.w r2, r3, ror #16 +100037ce: ea4f 2333 mov.w r3, r3, ror #8 +100037d2: f846 2f04 str.w r2, [r6, #4]! +100037d6: f845 3f04 str.w r3, [r5, #4]! +100037da: d1ae bne.n 1000373a +100037dc: f50d 7d07 add.w sp, sp, #540 @ 0x21c +100037e0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100037e4: 4559 cmp r1, fp +100037e6: f848 3f04 str.w r3, [r8, #4]! +100037ea: f847 3f04 str.w r3, [r7, #4]! +100037ee: f846 3f04 str.w r3, [r6, #4]! +100037f2: f845 3f04 str.w r3, [r5, #4]! +100037f6: d1a0 bne.n 1000373a +100037f8: f50d 7d07 add.w sp, sp, #540 @ 0x21c +100037fc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10003800: 20000e08 .word 0x20000e08 +10003804: 20000b88 .word 0x20000b88 +10003808: 20001e30 .word 0x20001e30 +1000380c: 20000b87 .word 0x20000b87 +10003810: 2000122c .word 0x2000122c +10003814: 2000162c .word 0x2000162c +10003818: 20001a2c .word 0x20001a2c +1000381c: 20001e2f .word 0x20001e2f +10003820: 2000232c .word 0x2000232c +10003824: 2000272c .word 0x2000272c +10003828: 20002b2c .word 0x20002b2c +1000382c: 80808081 .word 0x80808081 +10003830: 20000e2c .word 0x20000e2c +10003834: 20001f2c .word 0x20001f2c + +10003838 : +10003838: f44f 728c mov.w r2, #280 @ 0x118 +1000383c: 2100 movs r1, #0 +1000383e: f002 b895 b.w 1000596c +10003842: bf00 nop + +10003844 : +10003844: b118 cbz r0, 1000384e +10003846: f44f 718c mov.w r1, #280 @ 0x118 +1000384a: f001 bd4b b.w 100052e4 +1000384e: 4770 bx lr + +10003850 : +10003850: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10003854: 2ac0 cmp r2, #192 @ 0xc0 +10003856: 4615 mov r5, r2 +10003858: 4604 mov r4, r0 +1000385a: 460e mov r6, r1 +1000385c: b083 sub sp, #12 +1000385e: d038 beq.n 100038d2 +10003860: f5b2 7f80 cmp.w r2, #256 @ 0x100 +10003864: d029 beq.n 100038ba +10003866: 2a80 cmp r2, #128 @ 0x80 +10003868: d135 bne.n 100038d6 +1000386a: 230a movs r3, #10 +1000386c: 4fb2 ldr r7, [pc, #712] @ (10003b38 ) +1000386e: 6023 str r3, [r4, #0] +10003870: 683a ldr r2, [r7, #0] +10003872: b342 cbz r2, 100038c6 +10003874: 2200 movs r2, #0 +10003876: 6062 str r2, [r4, #4] +10003878: 6837 ldr r7, [r6, #0] +1000387a: 096d lsrs r5, r5, #5 +1000387c: 60a7 str r7, [r4, #8] +1000387e: 6872 ldr r2, [r6, #4] +10003880: 2d04 cmp r5, #4 +10003882: 60e2 str r2, [r4, #12] +10003884: 68b2 ldr r2, [r6, #8] +10003886: 6122 str r2, [r4, #16] +10003888: 68f2 ldr r2, [r6, #12] +1000388a: 6162 str r2, [r4, #20] +1000388c: d009 beq.n 100038a2 +1000388e: 6932 ldr r2, [r6, #16] +10003890: 2d06 cmp r5, #6 +10003892: 61a2 str r2, [r4, #24] +10003894: 6972 ldr r2, [r6, #20] +10003896: 61e2 str r2, [r4, #28] +10003898: d003 beq.n 100038a2 +1000389a: 69b2 ldr r2, [r6, #24] +1000389c: 6222 str r2, [r4, #32] +1000389e: 69f2 ldr r2, [r6, #28] +100038a0: 6262 str r2, [r4, #36] @ 0x24 +100038a2: 2b0c cmp r3, #12 +100038a4: f000 81a7 beq.w 10003bf6 +100038a8: 2b0e cmp r3, #14 +100038aa: f000 814b beq.w 10003b44 +100038ae: 2b0a cmp r3, #10 +100038b0: d016 beq.n 100038e0 +100038b2: 2000 movs r0, #0 +100038b4: b003 add sp, #12 +100038b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100038ba: 230e movs r3, #14 +100038bc: 4f9e ldr r7, [pc, #632] @ (10003b38 ) +100038be: 6023 str r3, [r4, #0] +100038c0: 683a ldr r2, [r7, #0] +100038c2: 2a00 cmp r2, #0 +100038c4: d1d6 bne.n 10003874 +100038c6: f7ff fe8b bl 100035e0 +100038ca: 2301 movs r3, #1 +100038cc: 603b str r3, [r7, #0] +100038ce: 6823 ldr r3, [r4, #0] +100038d0: e7d0 b.n 10003874 +100038d2: 230c movs r3, #12 +100038d4: e7ca b.n 1000386c +100038d6: f06f 001f mvn.w r0, #31 +100038da: b003 add sp, #12 +100038dc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100038e0: 6963 ldr r3, [r4, #20] +100038e2: 4996 ldr r1, [pc, #600] @ (10003b3c ) +100038e4: f3c3 2207 ubfx r2, r3, #8, #8 +100038e8: 5c8d ldrb r5, [r1, r2] +100038ea: 4e95 ldr r6, [pc, #596] @ (10003b40 ) +100038ec: 68e2 ldr r2, [r4, #12] +100038ee: ea4f 6c13 mov.w ip, r3, lsr #24 +100038f2: 9201 str r2, [sp, #4] +100038f4: 6832 ldr r2, [r6, #0] +100038f6: f811 c00c ldrb.w ip, [r1, ip] +100038fa: 4057 eors r7, r2 +100038fc: 407d eors r5, r7 +100038fe: b2df uxtb r7, r3 +10003900: 5dcf ldrb r7, [r1, r7] +10003902: ea85 450c eor.w r5, r5, ip, lsl #16 +10003906: ea85 6507 eor.w r5, r5, r7, lsl #24 +1000390a: f3c3 4707 ubfx r7, r3, #16, #8 +1000390e: 5dcf ldrb r7, [r1, r7] +10003910: 9a01 ldr r2, [sp, #4] +10003912: ea85 2507 eor.w r5, r5, r7, lsl #8 +10003916: 6920 ldr r0, [r4, #16] +10003918: 406a eors r2, r5 +1000391a: ea82 0700 eor.w r7, r2, r0 +1000391e: 407b eors r3, r7 +10003920: e9c4 5206 strd r5, r2, [r4, #24] +10003924: e9c4 7308 strd r7, r3, [r4, #32] +10003928: 6877 ldr r7, [r6, #4] +1000392a: 406f eors r7, r5 +1000392c: f3c3 2507 ubfx r5, r3, #8, #8 +10003930: 5d4d ldrb r5, [r1, r5] +10003932: 407d eors r5, r7 +10003934: 0e1f lsrs r7, r3, #24 +10003936: 5dcf ldrb r7, [r1, r7] +10003938: ea85 4507 eor.w r5, r5, r7, lsl #16 +1000393c: b2df uxtb r7, r3 +1000393e: 5dcf ldrb r7, [r1, r7] +10003940: ea85 6507 eor.w r5, r5, r7, lsl #24 +10003944: f3c3 4707 ubfx r7, r3, #16, #8 +10003948: 5dcf ldrb r7, [r1, r7] +1000394a: ea85 2507 eor.w r5, r5, r7, lsl #8 +1000394e: 406a eors r2, r5 +10003950: e9c4 520a strd r5, r2, [r4, #40] @ 0x28 +10003954: 4068 eors r0, r5 +10003956: 68b7 ldr r7, [r6, #8] +10003958: ea80 0c03 eor.w ip, r0, r3 +1000395c: 6320 str r0, [r4, #48] @ 0x30 +1000395e: f8c4 c034 str.w ip, [r4, #52] @ 0x34 +10003962: 407d eors r5, r7 +10003964: f3cc 2707 ubfx r7, ip, #8, #8 +10003968: 5dcf ldrb r7, [r1, r7] +1000396a: 407d eors r5, r7 +1000396c: ea4f 671c mov.w r7, ip, lsr #24 +10003970: 5dcf ldrb r7, [r1, r7] +10003972: ea85 4507 eor.w r5, r5, r7, lsl #16 +10003976: fa5f f78c uxtb.w r7, ip +1000397a: 5dcf ldrb r7, [r1, r7] +1000397c: f3cc 4c07 ubfx ip, ip, #16, #8 +10003980: ea85 6507 eor.w r5, r5, r7, lsl #24 +10003984: f811 700c ldrb.w r7, [r1, ip] +10003988: ea85 2507 eor.w r5, r5, r7, lsl #8 +1000398c: 406a eors r2, r5 +1000398e: 4053 eors r3, r2 +10003990: ea82 0700 eor.w r7, r2, r0 +10003994: e9c4 520e strd r5, r2, [r4, #56] @ 0x38 +10003998: 6463 str r3, [r4, #68] @ 0x44 +1000399a: 6427 str r7, [r4, #64] @ 0x40 +1000399c: 68f7 ldr r7, [r6, #12] +1000399e: 406f eors r7, r5 +100039a0: f3c3 2507 ubfx r5, r3, #8, #8 +100039a4: 5d4d ldrb r5, [r1, r5] +100039a6: 407d eors r5, r7 +100039a8: 0e1f lsrs r7, r3, #24 +100039aa: 5dcf ldrb r7, [r1, r7] +100039ac: ea85 4507 eor.w r5, r5, r7, lsl #16 +100039b0: b2df uxtb r7, r3 +100039b2: 5dcf ldrb r7, [r1, r7] +100039b4: ea85 6507 eor.w r5, r5, r7, lsl #24 +100039b8: f3c3 4707 ubfx r7, r3, #16, #8 +100039bc: 5dcf ldrb r7, [r1, r7] +100039be: ea85 2507 eor.w r5, r5, r7, lsl #8 +100039c2: 406a eors r2, r5 +100039c4: e9c4 5212 strd r5, r2, [r4, #72] @ 0x48 +100039c8: 4068 eors r0, r5 +100039ca: 6937 ldr r7, [r6, #16] +100039cc: ea83 0c00 eor.w ip, r3, r0 +100039d0: 6520 str r0, [r4, #80] @ 0x50 +100039d2: f8c4 c054 str.w ip, [r4, #84] @ 0x54 +100039d6: 407d eors r5, r7 +100039d8: f3cc 2707 ubfx r7, ip, #8, #8 +100039dc: 5dcf ldrb r7, [r1, r7] +100039de: 407d eors r5, r7 +100039e0: ea4f 671c mov.w r7, ip, lsr #24 +100039e4: 5dcf ldrb r7, [r1, r7] +100039e6: ea85 4507 eor.w r5, r5, r7, lsl #16 +100039ea: fa5f f78c uxtb.w r7, ip +100039ee: 5dcf ldrb r7, [r1, r7] +100039f0: f3cc 4c07 ubfx ip, ip, #16, #8 +100039f4: ea85 6507 eor.w r5, r5, r7, lsl #24 +100039f8: f811 700c ldrb.w r7, [r1, ip] +100039fc: ea85 2507 eor.w r5, r5, r7, lsl #8 +10003a00: 406a eors r2, r5 +10003a02: ea80 0702 eor.w r7, r0, r2 +10003a06: e9c4 5216 strd r5, r2, [r4, #88] @ 0x58 +10003a0a: 6627 str r7, [r4, #96] @ 0x60 +10003a0c: 6977 ldr r7, [r6, #20] +10003a0e: 4053 eors r3, r2 +10003a10: 6663 str r3, [r4, #100] @ 0x64 +10003a12: 406f eors r7, r5 +10003a14: f3c3 2507 ubfx r5, r3, #8, #8 +10003a18: 5d4d ldrb r5, [r1, r5] +10003a1a: 407d eors r5, r7 +10003a1c: 0e1f lsrs r7, r3, #24 +10003a1e: 5dcf ldrb r7, [r1, r7] +10003a20: ea85 4507 eor.w r5, r5, r7, lsl #16 +10003a24: b2df uxtb r7, r3 +10003a26: 5dcf ldrb r7, [r1, r7] +10003a28: ea85 6507 eor.w r5, r5, r7, lsl #24 +10003a2c: f3c3 4707 ubfx r7, r3, #16, #8 +10003a30: 5dcf ldrb r7, [r1, r7] +10003a32: ea85 2507 eor.w r5, r5, r7, lsl #8 +10003a36: 406a eors r2, r5 +10003a38: e9c4 521a strd r5, r2, [r4, #104] @ 0x68 +10003a3c: 4068 eors r0, r5 +10003a3e: 69b7 ldr r7, [r6, #24] +10003a40: ea83 0c00 eor.w ip, r3, r0 +10003a44: 6720 str r0, [r4, #112] @ 0x70 +10003a46: f8c4 c074 str.w ip, [r4, #116] @ 0x74 +10003a4a: 407d eors r5, r7 +10003a4c: f3cc 2707 ubfx r7, ip, #8, #8 +10003a50: 5dcf ldrb r7, [r1, r7] +10003a52: 407d eors r5, r7 +10003a54: ea4f 671c mov.w r7, ip, lsr #24 +10003a58: 5dcf ldrb r7, [r1, r7] +10003a5a: ea85 4507 eor.w r5, r5, r7, lsl #16 +10003a5e: fa5f f78c uxtb.w r7, ip +10003a62: 5dcf ldrb r7, [r1, r7] +10003a64: f3cc 4c07 ubfx ip, ip, #16, #8 +10003a68: ea85 6507 eor.w r5, r5, r7, lsl #24 +10003a6c: f811 700c ldrb.w r7, [r1, ip] +10003a70: ea85 2507 eor.w r5, r5, r7, lsl #8 +10003a74: 406a eors r2, r5 +10003a76: 4053 eors r3, r2 +10003a78: ea80 0702 eor.w r7, r0, r2 +10003a7c: e9c4 521e strd r5, r2, [r4, #120] @ 0x78 +10003a80: e9c4 7320 strd r7, r3, [r4, #128] @ 0x80 +10003a84: 69f7 ldr r7, [r6, #28] +10003a86: 406f eors r7, r5 +10003a88: f3c3 2507 ubfx r5, r3, #8, #8 +10003a8c: 5d4d ldrb r5, [r1, r5] +10003a8e: 407d eors r5, r7 +10003a90: 0e1f lsrs r7, r3, #24 +10003a92: 5dcf ldrb r7, [r1, r7] +10003a94: ea85 4507 eor.w r5, r5, r7, lsl #16 +10003a98: b2df uxtb r7, r3 +10003a9a: 5dcf ldrb r7, [r1, r7] +10003a9c: ea85 6507 eor.w r5, r5, r7, lsl #24 +10003aa0: f3c3 4707 ubfx r7, r3, #16, #8 +10003aa4: 5dcf ldrb r7, [r1, r7] +10003aa6: ea85 2507 eor.w r5, r5, r7, lsl #8 +10003aaa: 406a eors r2, r5 +10003aac: e9c4 5222 strd r5, r2, [r4, #136] @ 0x88 +10003ab0: 4068 eors r0, r5 +10003ab2: 6a37 ldr r7, [r6, #32] +10003ab4: ea83 0c00 eor.w ip, r3, r0 +10003ab8: f8c4 0090 str.w r0, [r4, #144] @ 0x90 +10003abc: f8c4 c094 str.w ip, [r4, #148] @ 0x94 +10003ac0: 407d eors r5, r7 +10003ac2: 6a77 ldr r7, [r6, #36] @ 0x24 +10003ac4: f3cc 2607 ubfx r6, ip, #8, #8 +10003ac8: 5d8e ldrb r6, [r1, r6] +10003aca: 4075 eors r5, r6 +10003acc: ea4f 661c mov.w r6, ip, lsr #24 +10003ad0: 5d8e ldrb r6, [r1, r6] +10003ad2: ea85 4506 eor.w r5, r5, r6, lsl #16 +10003ad6: fa5f f68c uxtb.w r6, ip +10003ada: 5d8e ldrb r6, [r1, r6] +10003adc: ea85 6506 eor.w r5, r5, r6, lsl #24 +10003ae0: f3cc 4607 ubfx r6, ip, #16, #8 +10003ae4: 5d8e ldrb r6, [r1, r6] +10003ae6: ea85 2506 eor.w r5, r5, r6, lsl #8 +10003aea: 406a eors r2, r5 +10003aec: 4053 eors r3, r2 +10003aee: ea80 0602 eor.w r6, r0, r2 +10003af2: f8c4 5098 str.w r5, [r4, #152] @ 0x98 +10003af6: f8c4 209c str.w r2, [r4, #156] @ 0x9c +10003afa: f8c4 30a4 str.w r3, [r4, #164] @ 0xa4 +10003afe: f8c4 60a0 str.w r6, [r4, #160] @ 0xa0 +10003b02: f3c3 2607 ubfx r6, r3, #8, #8 +10003b06: 5d8e ldrb r6, [r1, r6] +10003b08: 407d eors r5, r7 +10003b0a: 4075 eors r5, r6 +10003b0c: 0e1e lsrs r6, r3, #24 +10003b0e: 5d8e ldrb r6, [r1, r6] +10003b10: ea85 4506 eor.w r5, r5, r6, lsl #16 +10003b14: b2de uxtb r6, r3 +10003b16: 5d8e ldrb r6, [r1, r6] +10003b18: ea85 6506 eor.w r5, r5, r6, lsl #24 +10003b1c: f3c3 4607 ubfx r6, r3, #16, #8 +10003b20: 5d89 ldrb r1, [r1, r6] +10003b22: ea85 2101 eor.w r1, r5, r1, lsl #8 +10003b26: 4048 eors r0, r1 +10003b28: 404a eors r2, r1 +10003b2a: 4043 eors r3, r0 +10003b2c: e9c4 122a strd r1, r2, [r4, #168] @ 0xa8 +10003b30: e9c4 032c strd r0, r3, [r4, #176] @ 0xb0 +10003b34: e6bd b.n 100038b2 +10003b36: bf00 nop +10003b38: 200030c0 .word 0x200030c0 +10003b3c: 20000b88 .word 0x20000b88 +10003b40: 20000e08 .word 0x20000e08 +10003b44: f8df a324 ldr.w sl, [pc, #804] @ 10003e6c +10003b48: 49c7 ldr r1, [pc, #796] @ (10003e68 ) +10003b4a: f8d4 e018 ldr.w lr, [r4, #24] +10003b4e: 68e6 ldr r6, [r4, #12] +10003b50: 6a60 ldr r0, [r4, #36] @ 0x24 +10003b52: f104 0308 add.w r3, r4, #8 +10003b56: e9d4 8907 ldrd r8, r9, [r4, #28] +10003b5a: e9d4 c504 ldrd ip, r5, [r4, #16] +10003b5e: f10a 041c add.w r4, sl, #28 +10003b62: f3c0 2207 ubfx r2, r0, #8, #8 +10003b66: ea4f 6b10 mov.w fp, r0, lsr #24 +10003b6a: f811 b00b ldrb.w fp, [r1, fp] +10003b6e: 5c8a ldrb r2, [r1, r2] +10003b70: ea42 420b orr.w r2, r2, fp, lsl #16 +10003b74: f85a bf04 ldr.w fp, [sl, #4]! +10003b78: ea82 020b eor.w r2, r2, fp +10003b7c: fa5f fb80 uxtb.w fp, r0 +10003b80: f811 b00b ldrb.w fp, [r1, fp] +10003b84: 45a2 cmp sl, r4 +10003b86: ea82 620b eor.w r2, r2, fp, lsl #24 +10003b8a: f3c0 4b07 ubfx fp, r0, #16, #8 +10003b8e: f811 b00b ldrb.w fp, [r1, fp] +10003b92: ea82 220b eor.w r2, r2, fp, lsl #8 +10003b96: ea87 0702 eor.w r7, r7, r2 +10003b9a: ea86 0607 eor.w r6, r6, r7 +10003b9e: ea8c 0c06 eor.w ip, ip, r6 +10003ba2: ea85 050c eor.w r5, r5, ip +10003ba6: e9c3 7608 strd r7, r6, [r3, #32] +10003baa: e9c3 c50a strd ip, r5, [r3, #40] @ 0x28 +10003bae: ea4f 6215 mov.w r2, r5, lsr #24 +10003bb2: f811 b002 ldrb.w fp, [r1, r2] +10003bb6: b2ea uxtb r2, r5 +10003bb8: 5c8a ldrb r2, [r1, r2] +10003bba: ea42 620b orr.w r2, r2, fp, lsl #24 +10003bbe: f3c5 2b07 ubfx fp, r5, #8, #8 +10003bc2: f811 b00b ldrb.w fp, [r1, fp] +10003bc6: ea42 220b orr.w r2, r2, fp, lsl #8 +10003bca: f3c5 4b07 ubfx fp, r5, #16, #8 +10003bce: f811 b00b ldrb.w fp, [r1, fp] +10003bd2: ea42 420b orr.w r2, r2, fp, lsl #16 +10003bd6: ea8e 0e02 eor.w lr, lr, r2 +10003bda: ea88 080e eor.w r8, r8, lr +10003bde: ea89 0908 eor.w r9, r9, r8 +10003be2: ea80 0009 eor.w r0, r0, r9 +10003be6: e9c3 e80c strd lr, r8, [r3, #48] @ 0x30 +10003bea: e9c3 900e strd r9, r0, [r3, #56] @ 0x38 +10003bee: f103 0320 add.w r3, r3, #32 +10003bf2: d1b6 bne.n 10003b62 +10003bf4: e65d b.n 100038b2 +10003bf6: 69e1 ldr r1, [r4, #28] +10003bf8: 4a9b ldr r2, [pc, #620] @ (10003e68 ) +10003bfa: f8df 9274 ldr.w r9, [pc, #628] @ 10003e70 +10003bfe: f3c1 2607 ubfx r6, r1, #8, #8 +10003c02: f812 e006 ldrb.w lr, [r2, r6] +10003c06: f8d9 6000 ldr.w r6, [r9] +10003c0a: 68e3 ldr r3, [r4, #12] +10003c0c: 407e eors r6, r7 +10003c0e: 0e0f lsrs r7, r1, #24 +10003c10: 5dd7 ldrb r7, [r2, r7] +10003c12: ea8e 0606 eor.w r6, lr, r6 +10003c16: ea86 4607 eor.w r6, r6, r7, lsl #16 +10003c1a: b2cf uxtb r7, r1 +10003c1c: 5dd7 ldrb r7, [r2, r7] +10003c1e: 6925 ldr r5, [r4, #16] +10003c20: ea86 6607 eor.w r6, r6, r7, lsl #24 +10003c24: f3c1 4707 ubfx r7, r1, #16, #8 +10003c28: 5dd7 ldrb r7, [r2, r7] +10003c2a: e9d4 0c05 ldrd r0, ip, [r4, #20] +10003c2e: ea86 2607 eor.w r6, r6, r7, lsl #8 +10003c32: ea83 0706 eor.w r7, r3, r6 +10003c36: ea85 0307 eor.w r3, r5, r7 +10003c3a: ea80 0e03 eor.w lr, r0, r3 +10003c3e: e9c4 3e0a strd r3, lr, [r4, #40] @ 0x28 +10003c42: ea8c 030e eor.w r3, ip, lr +10003c46: 4059 eors r1, r3 +10003c48: e9c4 6708 strd r6, r7, [r4, #32] +10003c4c: e9c4 310c strd r3, r1, [r4, #48] @ 0x30 +10003c50: f8d9 0004 ldr.w r0, [r9, #4] +10003c54: f3c1 2307 ubfx r3, r1, #8, #8 +10003c58: 4046 eors r6, r0 +10003c5a: 5cd0 ldrb r0, [r2, r3] +10003c5c: 0e0b lsrs r3, r1, #24 +10003c5e: 5cd3 ldrb r3, [r2, r3] +10003c60: 4070 eors r0, r6 +10003c62: ea80 4003 eor.w r0, r0, r3, lsl #16 +10003c66: b2cb uxtb r3, r1 +10003c68: 5cd3 ldrb r3, [r2, r3] +10003c6a: ea80 6003 eor.w r0, r0, r3, lsl #24 +10003c6e: f3c1 4307 ubfx r3, r1, #16, #8 +10003c72: 5cd3 ldrb r3, [r2, r3] +10003c74: ea80 2303 eor.w r3, r0, r3, lsl #8 +10003c78: 405d eors r5, r3 +10003c7a: 405f eors r7, r3 +10003c7c: ea8e 0605 eor.w r6, lr, r5 +10003c80: e9c4 370e strd r3, r7, [r4, #56] @ 0x38 +10003c84: 6466 str r6, [r4, #68] @ 0x44 +10003c86: ea8c 0005 eor.w r0, ip, r5 +10003c8a: f8d9 6008 ldr.w r6, [r9, #8] +10003c8e: ea81 0800 eor.w r8, r1, r0 +10003c92: 6425 str r5, [r4, #64] @ 0x40 +10003c94: 64a0 str r0, [r4, #72] @ 0x48 +10003c96: f8c4 804c str.w r8, [r4, #76] @ 0x4c +10003c9a: 4073 eors r3, r6 +10003c9c: f3c8 2607 ubfx r6, r8, #8, #8 +10003ca0: 5d96 ldrb r6, [r2, r6] +10003ca2: 405e eors r6, r3 +10003ca4: ea4f 6318 mov.w r3, r8, lsr #24 +10003ca8: 5cd3 ldrb r3, [r2, r3] +10003caa: ea86 4603 eor.w r6, r6, r3, lsl #16 +10003cae: fa5f f388 uxtb.w r3, r8 +10003cb2: 5cd3 ldrb r3, [r2, r3] +10003cb4: f3c8 4807 ubfx r8, r8, #16, #8 +10003cb8: ea86 6603 eor.w r6, r6, r3, lsl #24 +10003cbc: f812 3008 ldrb.w r3, [r2, r8] +10003cc0: ea86 2803 eor.w r8, r6, r3, lsl #8 +10003cc4: ea87 0308 eor.w r3, r7, r8 +10003cc8: ea8e 0e03 eor.w lr, lr, r3 +10003ccc: ea85 0603 eor.w r6, r5, r3 +10003cd0: f8c4 8050 str.w r8, [r4, #80] @ 0x50 +10003cd4: ea80 000e eor.w r0, r0, lr +10003cd8: 65a6 str r6, [r4, #88] @ 0x58 +10003cda: f8d9 600c ldr.w r6, [r9, #12] +10003cde: 6620 str r0, [r4, #96] @ 0x60 +10003ce0: ea81 000e eor.w r0, r1, lr +10003ce4: 6563 str r3, [r4, #84] @ 0x54 +10003ce6: f8c4 e05c str.w lr, [r4, #92] @ 0x5c +10003cea: 6660 str r0, [r4, #100] @ 0x64 +10003cec: ea88 0806 eor.w r8, r8, r6 +10003cf0: f3c0 2607 ubfx r6, r0, #8, #8 +10003cf4: 5d96 ldrb r6, [r2, r6] +10003cf6: 0e07 lsrs r7, r0, #24 +10003cf8: 5dd7 ldrb r7, [r2, r7] +10003cfa: ea86 0608 eor.w r6, r6, r8 +10003cfe: ea86 4607 eor.w r6, r6, r7, lsl #16 +10003d02: b2c7 uxtb r7, r0 +10003d04: 5dd7 ldrb r7, [r2, r7] +10003d06: ea86 6607 eor.w r6, r6, r7, lsl #24 +10003d0a: f3c0 4707 ubfx r7, r0, #16, #8 +10003d0e: 5dd7 ldrb r7, [r2, r7] +10003d10: ea86 2607 eor.w r6, r6, r7, lsl #8 +10003d14: ea8c 0c06 eor.w ip, ip, r6 +10003d18: 4075 eors r5, r6 +10003d1a: ea80 000c eor.w r0, r0, ip +10003d1e: ea8e 0705 eor.w r7, lr, r5 +10003d22: 4073 eors r3, r6 +10003d24: e9c4 631a strd r6, r3, [r4, #104] @ 0x68 +10003d28: e9c4 c01e strd ip, r0, [r4, #120] @ 0x78 +10003d2c: 6767 str r7, [r4, #116] @ 0x74 +10003d2e: f8d9 7010 ldr.w r7, [r9, #16] +10003d32: 6725 str r5, [r4, #112] @ 0x70 +10003d34: 4077 eors r7, r6 +10003d36: f3c0 2607 ubfx r6, r0, #8, #8 +10003d3a: 5d96 ldrb r6, [r2, r6] +10003d3c: 407e eors r6, r7 +10003d3e: 0e07 lsrs r7, r0, #24 +10003d40: 5dd7 ldrb r7, [r2, r7] +10003d42: ea86 4607 eor.w r6, r6, r7, lsl #16 +10003d46: b2c7 uxtb r7, r0 +10003d48: 5dd7 ldrb r7, [r2, r7] +10003d4a: f3c0 4007 ubfx r0, r0, #16, #8 +10003d4e: 5c10 ldrb r0, [r2, r0] +10003d50: ea86 6607 eor.w r6, r6, r7, lsl #24 +10003d54: ea86 2700 eor.w r7, r6, r0, lsl #8 +10003d58: 407b eors r3, r7 +10003d5a: ea8e 0003 eor.w r0, lr, r3 +10003d5e: ea85 0603 eor.w r6, r5, r3 +10003d62: f8c4 6088 str.w r6, [r4, #136] @ 0x88 +10003d66: ea8c 0600 eor.w r6, ip, r0 +10003d6a: e9c4 7320 strd r7, r3, [r4, #128] @ 0x80 +10003d6e: f8c4 6090 str.w r6, [r4, #144] @ 0x90 +10003d72: f8d9 6014 ldr.w r6, [r9, #20] +10003d76: 4059 eors r1, r3 +10003d78: f8c4 008c str.w r0, [r4, #140] @ 0x8c +10003d7c: f8c4 1094 str.w r1, [r4, #148] @ 0x94 +10003d80: 4077 eors r7, r6 +10003d82: f3c1 2607 ubfx r6, r1, #8, #8 +10003d86: 5d96 ldrb r6, [r2, r6] +10003d88: 407e eors r6, r7 +10003d8a: 0e0f lsrs r7, r1, #24 +10003d8c: 5dd7 ldrb r7, [r2, r7] +10003d8e: ea86 4607 eor.w r6, r6, r7, lsl #16 +10003d92: b2cf uxtb r7, r1 +10003d94: 5dd7 ldrb r7, [r2, r7] +10003d96: ea86 6607 eor.w r6, r6, r7, lsl #24 +10003d9a: f3c1 4707 ubfx r7, r1, #16, #8 +10003d9e: 5dd7 ldrb r7, [r2, r7] +10003da0: ea86 2607 eor.w r6, r6, r7, lsl #8 +10003da4: 4075 eors r5, r6 +10003da6: ea80 0705 eor.w r7, r0, r5 +10003daa: 4073 eors r3, r6 +10003dac: e9c4 6326 strd r6, r3, [r4, #152] @ 0x98 +10003db0: ea8c 0e05 eor.w lr, ip, r5 +10003db4: f8c4 70a4 str.w r7, [r4, #164] @ 0xa4 +10003db8: f8d9 7018 ldr.w r7, [r9, #24] +10003dbc: ea81 080e eor.w r8, r1, lr +10003dc0: f8c4 50a0 str.w r5, [r4, #160] @ 0xa0 +10003dc4: f8c4 e0a8 str.w lr, [r4, #168] @ 0xa8 +10003dc8: f8c4 80ac str.w r8, [r4, #172] @ 0xac +10003dcc: ea86 0a07 eor.w sl, r6, r7 +10003dd0: f3c8 2607 ubfx r6, r8, #8, #8 +10003dd4: 5d96 ldrb r6, [r2, r6] +10003dd6: f8d9 701c ldr.w r7, [r9, #28] +10003dda: ea4f 6918 mov.w r9, r8, lsr #24 +10003dde: f812 9009 ldrb.w r9, [r2, r9] +10003de2: ea86 060a eor.w r6, r6, sl +10003de6: ea86 4609 eor.w r6, r6, r9, lsl #16 +10003dea: fa5f f988 uxtb.w r9, r8 +10003dee: f812 9009 ldrb.w r9, [r2, r9] +10003df2: f3c8 4807 ubfx r8, r8, #16, #8 +10003df6: f812 8008 ldrb.w r8, [r2, r8] +10003dfa: ea86 6609 eor.w r6, r6, r9, lsl #24 +10003dfe: ea86 2608 eor.w r6, r6, r8, lsl #8 +10003e02: 4073 eors r3, r6 +10003e04: 4058 eors r0, r3 +10003e06: 4041 eors r1, r0 +10003e08: f8c4 60b0 str.w r6, [r4, #176] @ 0xb0 +10003e0c: ea8e 0e00 eor.w lr, lr, r0 +10003e10: 407e eors r6, r7 +10003e12: ea85 0703 eor.w r7, r5, r3 +10003e16: f8c4 30b4 str.w r3, [r4, #180] @ 0xb4 +10003e1a: f8c4 00bc str.w r0, [r4, #188] @ 0xbc +10003e1e: f8c4 10c4 str.w r1, [r4, #196] @ 0xc4 +10003e22: f8c4 70b8 str.w r7, [r4, #184] @ 0xb8 +10003e26: f8c4 e0c0 str.w lr, [r4, #192] @ 0xc0 +10003e2a: f3c1 2707 ubfx r7, r1, #8, #8 +10003e2e: 5dd7 ldrb r7, [r2, r7] +10003e30: 407e eors r6, r7 +10003e32: 0e0f lsrs r7, r1, #24 +10003e34: 5dd7 ldrb r7, [r2, r7] +10003e36: ea86 4607 eor.w r6, r6, r7, lsl #16 +10003e3a: b2cf uxtb r7, r1 +10003e3c: 5dd7 ldrb r7, [r2, r7] +10003e3e: ea86 6607 eor.w r6, r6, r7, lsl #24 +10003e42: f3c1 4707 ubfx r7, r1, #16, #8 +10003e46: 5dd2 ldrb r2, [r2, r7] +10003e48: ea86 2202 eor.w r2, r6, r2, lsl #8 +10003e4c: 4055 eors r5, r2 +10003e4e: ea82 060c eor.w r6, r2, ip +10003e52: 4053 eors r3, r2 +10003e54: 4068 eors r0, r5 +10003e56: 4071 eors r1, r6 +10003e58: e9c4 2332 strd r2, r3, [r4, #200] @ 0xc8 +10003e5c: e9c4 5034 strd r5, r0, [r4, #208] @ 0xd0 +10003e60: e9c4 6136 strd r6, r1, [r4, #216] @ 0xd8 +10003e64: e525 b.n 100038b2 +10003e66: bf00 nop +10003e68: 20000b88 .word 0x20000b88 +10003e6c: 20000e04 .word 0x20000e04 +10003e70: 20000e08 .word 0x20000e08 + +10003e74 : +10003e74: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10003e78: b0cb sub sp, #300 @ 0x12c +10003e7a: af04 add r7, sp, #16 +10003e7c: 4604 mov r4, r0 +10003e7e: 460d mov r5, r1 +10003e80: 4616 mov r6, r2 +10003e82: 2100 movs r1, #0 +10003e84: f44f 728c mov.w r2, #280 @ 0x118 +10003e88: 4638 mov r0, r7 +10003e8a: f001 fd6f bl 1000596c +10003e8e: 2300 movs r3, #0 +10003e90: 4632 mov r2, r6 +10003e92: 4629 mov r1, r5 +10003e94: 4638 mov r0, r7 +10003e96: 6063 str r3, [r4, #4] +10003e98: f7ff fcda bl 10003850 +10003e9c: 4683 mov fp, r0 +10003e9e: 2800 cmp r0, #0 +10003ea0: f040 80c6 bne.w 10004030 +10003ea4: e9d7 8300 ldrd r8, r3, [r7] +10003ea8: 4621 mov r1, r4 +10003eaa: eb03 0388 add.w r3, r3, r8, lsl #2 +10003eae: aa06 add r2, sp, #24 +10003eb0: eb02 0c83 add.w ip, r2, r3, lsl #2 +10003eb4: f852 5023 ldr.w r5, [r2, r3, lsl #2] +10003eb8: f8dc 000c ldr.w r0, [ip, #12] +10003ebc: f108 39ff add.w r9, r8, #4294967295 @ 0xffffffff +10003ec0: f1b9 0f00 cmp.w r9, #0 +10003ec4: f841 8b18 str.w r8, [r1], #24 +10003ec8: e9dc 3201 ldrd r3, r2, [ip, #4] +10003ecc: f1ac 0a10 sub.w sl, ip, #16 +10003ed0: e9c4 5302 strd r5, r3, [r4, #8] +10003ed4: e9c4 2004 strd r2, r0, [r4, #16] +10003ed8: f340 809e ble.w 10004018 +10003edc: e9cd 8a01 strd r8, sl, [sp, #4] +10003ee0: f104 0028 add.w r0, r4, #40 @ 0x28 +10003ee4: f8df e16c ldr.w lr, [pc, #364] @ 10004054 +10003ee8: 4b56 ldr r3, [pc, #344] @ (10004044 ) +10003eea: 4e57 ldr r6, [pc, #348] @ (10004048 ) +10003eec: 4d57 ldr r5, [pc, #348] @ (1000404c ) +10003eee: 4c58 ldr r4, [pc, #352] @ (10004050 ) +10003ef0: f1ac 0c20 sub.w ip, ip, #32 +10003ef4: 9103 str r1, [sp, #12] +10003ef6: e9dc 1204 ldrd r1, r2, [ip, #16] +10003efa: fa5f f881 uxtb.w r8, r1 +10003efe: ea4f 6a11 mov.w sl, r1, lsr #24 +10003f02: f813 8008 ldrb.w r8, [r3, r8] +10003f06: f813 a00a ldrb.w sl, [r3, sl] +10003f0a: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +10003f0e: f856 a02a ldr.w sl, [r6, sl, lsl #2] +10003f12: f1b9 0901 subs.w r9, r9, #1 +10003f16: ea88 080a eor.w r8, r8, sl +10003f1a: f3c1 2a07 ubfx sl, r1, #8, #8 +10003f1e: f813 a00a ldrb.w sl, [r3, sl] +10003f22: f3c1 4107 ubfx r1, r1, #16, #8 +10003f26: 5c59 ldrb r1, [r3, r1] +10003f28: f855 a02a ldr.w sl, [r5, sl, lsl #2] +10003f2c: f854 1021 ldr.w r1, [r4, r1, lsl #2] +10003f30: ea88 0a0a eor.w sl, r8, sl +10003f34: ea8a 0101 eor.w r1, sl, r1 +10003f38: f840 1c10 str.w r1, [r0, #-16] +10003f3c: b2d1 uxtb r1, r2 +10003f3e: 5c59 ldrb r1, [r3, r1] +10003f40: f100 0010 add.w r0, r0, #16 +10003f44: f85e 8021 ldr.w r8, [lr, r1, lsl #2] +10003f48: ea4f 6112 mov.w r1, r2, lsr #24 +10003f4c: 5c59 ldrb r1, [r3, r1] +10003f4e: f856 1021 ldr.w r1, [r6, r1, lsl #2] +10003f52: ea88 0101 eor.w r1, r8, r1 +10003f56: f3c2 2807 ubfx r8, r2, #8, #8 +10003f5a: f813 8008 ldrb.w r8, [r3, r8] +10003f5e: f3c2 4207 ubfx r2, r2, #16, #8 +10003f62: 5c9a ldrb r2, [r3, r2] +10003f64: f855 8028 ldr.w r8, [r5, r8, lsl #2] +10003f68: f854 2022 ldr.w r2, [r4, r2, lsl #2] +10003f6c: ea81 0808 eor.w r8, r1, r8 +10003f70: ea88 0202 eor.w r2, r8, r2 +10003f74: f840 2c1c str.w r2, [r0, #-28] +10003f78: e9dc 1206 ldrd r1, r2, [ip, #24] +10003f7c: fa5f f881 uxtb.w r8, r1 +10003f80: ea4f 6a11 mov.w sl, r1, lsr #24 +10003f84: f813 8008 ldrb.w r8, [r3, r8] +10003f88: f813 a00a ldrb.w sl, [r3, sl] +10003f8c: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +10003f90: f856 a02a ldr.w sl, [r6, sl, lsl #2] +10003f94: f1ac 0c10 sub.w ip, ip, #16 +10003f98: ea88 080a eor.w r8, r8, sl +10003f9c: f3c1 2a07 ubfx sl, r1, #8, #8 +10003fa0: f813 a00a ldrb.w sl, [r3, sl] +10003fa4: f3c1 4107 ubfx r1, r1, #16, #8 +10003fa8: 5c59 ldrb r1, [r3, r1] +10003faa: f855 a02a ldr.w sl, [r5, sl, lsl #2] +10003fae: f854 1021 ldr.w r1, [r4, r1, lsl #2] +10003fb2: ea88 0a0a eor.w sl, r8, sl +10003fb6: ea8a 0101 eor.w r1, sl, r1 +10003fba: f840 1c18 str.w r1, [r0, #-24] +10003fbe: b2d1 uxtb r1, r2 +10003fc0: f813 8001 ldrb.w r8, [r3, r1] +10003fc4: ea4f 6112 mov.w r1, r2, lsr #24 +10003fc8: 5c59 ldrb r1, [r3, r1] +10003fca: f85e 8028 ldr.w r8, [lr, r8, lsl #2] +10003fce: f856 1021 ldr.w r1, [r6, r1, lsl #2] +10003fd2: ea88 0101 eor.w r1, r8, r1 +10003fd6: f3c2 2807 ubfx r8, r2, #8, #8 +10003fda: f813 8008 ldrb.w r8, [r3, r8] +10003fde: f3c2 4207 ubfx r2, r2, #16, #8 +10003fe2: 5c9a ldrb r2, [r3, r2] +10003fe4: f855 8028 ldr.w r8, [r5, r8, lsl #2] +10003fe8: f854 2022 ldr.w r2, [r4, r2, lsl #2] +10003fec: ea81 0808 eor.w r8, r1, r8 +10003ff0: ea88 0202 eor.w r2, r8, r2 +10003ff4: f840 2c14 str.w r2, [r0, #-20] +10003ff8: f47f af7d bne.w 10003ef6 +10003ffc: e9dd 8a01 ldrd r8, sl, [sp, #4] +10004000: f1a8 0802 sub.w r8, r8, #2 +10004004: ea4f 1808 mov.w r8, r8, lsl #4 +10004008: 9903 ldr r1, [sp, #12] +1000400a: ebaa 0a08 sub.w sl, sl, r8 +1000400e: f108 0810 add.w r8, r8, #16 +10004012: 4441 add r1, r8 +10004014: f1aa 0a10 sub.w sl, sl, #16 +10004018: f8da 3004 ldr.w r3, [sl, #4] +1000401c: 604b str r3, [r1, #4] +1000401e: f8da 3008 ldr.w r3, [sl, #8] +10004022: 608b str r3, [r1, #8] +10004024: f8da 300c ldr.w r3, [sl, #12] +10004028: 60cb str r3, [r1, #12] +1000402a: f8da 3000 ldr.w r3, [sl] +1000402e: 600b str r3, [r1, #0] +10004030: 4638 mov r0, r7 +10004032: f44f 718c mov.w r1, #280 @ 0x118 +10004036: f001 f955 bl 100052e4 +1000403a: 4658 mov r0, fp +1000403c: b04b add sp, #300 @ 0x12c +1000403e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004042: bf00 nop +10004044: 20000b88 .word 0x20000b88 +10004048: 20002b30 .word 0x20002b30 +1000404c: 20002330 .word 0x20002330 +10004050: 20002730 .word 0x20002730 +10004054: 20001f30 .word 0x20001f30 + +10004058 : +10004058: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +1000405c: 6844 ldr r4, [r0, #4] +1000405e: f100 0308 add.w r3, r0, #8 +10004062: eb03 0e84 add.w lr, r3, r4, lsl #2 +10004066: 4694 mov ip, r2 +10004068: f853 3024 ldr.w r3, [r3, r4, lsl #2] +1000406c: 6802 ldr r2, [r0, #0] +1000406e: 6808 ldr r0, [r1, #0] +10004070: b091 sub sp, #68 @ 0x44 +10004072: 4043 eors r3, r0 +10004074: 688e ldr r6, [r1, #8] +10004076: 68cd ldr r5, [r1, #12] +10004078: 9300 str r3, [sp, #0] +1000407a: 684b ldr r3, [r1, #4] +1000407c: f8de 1008 ldr.w r1, [lr, #8] +10004080: 1052 asrs r2, r2, #1 +10004082: 404e eors r6, r1 +10004084: f8de 100c ldr.w r1, [lr, #12] +10004088: f8de 0004 ldr.w r0, [lr, #4] +1000408c: 404d eors r5, r1 +1000408e: 1e51 subs r1, r2, #1 +10004090: 2900 cmp r1, #0 +10004092: ea83 0300 eor.w r3, r3, r0 +10004096: 9101 str r1, [sp, #4] +10004098: f10e 0010 add.w r0, lr, #16 +1000409c: f340 8190 ble.w 100043c0 +100040a0: e9cd 2005 strd r2, r0, [sp, #20] +100040a4: f8df b334 ldr.w fp, [pc, #820] @ 100043dc +100040a8: f8df 9334 ldr.w r9, [pc, #820] @ 100043e0 +100040ac: f8df a334 ldr.w sl, [pc, #820] @ 100043e4 +100040b0: f8df 8334 ldr.w r8, [pc, #820] @ 100043e8 +100040b4: f10e 0e30 add.w lr, lr, #48 @ 0x30 +100040b8: f8cd c01c str.w ip, [sp, #28] +100040bc: 9800 ldr r0, [sp, #0] +100040be: f10e 0e20 add.w lr, lr, #32 +100040c2: b2c2 uxtb r2, r0 +100040c4: f85b 7022 ldr.w r7, [fp, r2, lsl #2] +100040c8: 0e2a lsrs r2, r5, #24 +100040ca: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100040ce: 4057 eors r7, r2 +100040d0: b2da uxtb r2, r3 +100040d2: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +100040d6: 0e02 lsrs r2, r0, #24 +100040d8: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100040dc: ea81 0c02 eor.w ip, r1, r2 +100040e0: b2f2 uxtb r2, r6 +100040e2: f85b 4022 ldr.w r4, [fp, r2, lsl #2] +100040e6: 0e1a lsrs r2, r3, #24 +100040e8: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100040ec: 4054 eors r4, r2 +100040ee: b2ea uxtb r2, r5 +100040f0: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +100040f4: 0e32 lsrs r2, r6, #24 +100040f6: f859 2022 ldr.w r2, [r9, r2, lsl #2] +100040fa: 4051 eors r1, r2 +100040fc: f85e 2c40 ldr.w r2, [lr, #-64] +10004100: 4057 eors r7, r2 +10004102: f85e 2c3c ldr.w r2, [lr, #-60] +10004106: ea8c 0c02 eor.w ip, ip, r2 +1000410a: f85e 2c38 ldr.w r2, [lr, #-56] +1000410e: 4054 eors r4, r2 +10004110: f85e 2c34 ldr.w r2, [lr, #-52] +10004114: 4051 eors r1, r2 +10004116: f3c3 2207 ubfx r2, r3, #8, #8 +1000411a: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1000411e: f3c3 4307 ubfx r3, r3, #16, #8 +10004122: 4057 eors r7, r2 +10004124: f3c6 2207 ubfx r2, r6, #8, #8 +10004128: f3c6 4607 ubfx r6, r6, #16, #8 +1000412c: f85a 0022 ldr.w r0, [sl, r2, lsl #2] +10004130: f858 2026 ldr.w r2, [r8, r6, lsl #2] +10004134: ea8c 0000 eor.w r0, ip, r0 +10004138: ea87 0c02 eor.w ip, r7, r2 +1000413c: f3c5 2207 ubfx r2, r5, #8, #8 +10004140: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +10004144: f3c5 4507 ubfx r5, r5, #16, #8 +10004148: 4054 eors r4, r2 +1000414a: f858 2025 ldr.w r2, [r8, r5, lsl #2] +1000414e: 9d00 ldr r5, [sp, #0] +10004150: 4050 eors r0, r2 +10004152: f3c5 2207 ubfx r2, r5, #8, #8 +10004156: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1000415a: f858 3023 ldr.w r3, [r8, r3, lsl #2] +1000415e: 4051 eors r1, r2 +10004160: 4059 eors r1, r3 +10004162: f3c5 4307 ubfx r3, r5, #16, #8 +10004166: f858 3023 ldr.w r3, [r8, r3, lsl #2] +1000416a: 405c eors r4, r3 +1000416c: fa5f f38c uxtb.w r3, ip +10004170: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +10004174: 0e0b lsrs r3, r1, #24 +10004176: f859 3023 ldr.w r3, [r9, r3, lsl #2] +1000417a: 4053 eors r3, r2 +1000417c: 461f mov r7, r3 +1000417e: f3c0 2307 ubfx r3, r0, #8, #8 +10004182: f85a 2023 ldr.w r2, [sl, r3, lsl #2] +10004186: f3c4 4307 ubfx r3, r4, #16, #8 +1000418a: f858 5023 ldr.w r5, [r8, r3, lsl #2] +1000418e: b2c3 uxtb r3, r0 +10004190: 9200 str r2, [sp, #0] +10004192: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +10004196: ea4f 631c mov.w r3, ip, lsr #24 +1000419a: f859 3023 ldr.w r3, [r9, r3, lsl #2] +1000419e: 9502 str r5, [sp, #8] +100041a0: 405a eors r2, r3 +100041a2: f3c4 2307 ubfx r3, r4, #8, #8 +100041a6: f85a 6023 ldr.w r6, [sl, r3, lsl #2] +100041aa: b2e5 uxtb r5, r4 +100041ac: f3c1 4307 ubfx r3, r1, #16, #8 +100041b0: 9603 str r6, [sp, #12] +100041b2: f858 3023 ldr.w r3, [r8, r3, lsl #2] +100041b6: f85b 6025 ldr.w r6, [fp, r5, lsl #2] +100041ba: 0e05 lsrs r5, r0, #24 +100041bc: f859 5025 ldr.w r5, [r9, r5, lsl #2] +100041c0: 0e24 lsrs r4, r4, #24 +100041c2: 406e eors r6, r5 +100041c4: b2cd uxtb r5, r1 +100041c6: 9504 str r5, [sp, #16] +100041c8: f85e 5c30 ldr.w r5, [lr, #-48] +100041cc: f3c1 2107 ubfx r1, r1, #8, #8 +100041d0: 407d eors r5, r7 +100041d2: 9f00 ldr r7, [sp, #0] +100041d4: f3c0 4007 ubfx r0, r0, #16, #8 +100041d8: 407d eors r5, r7 +100041da: 9f02 ldr r7, [sp, #8] +100041dc: 406f eors r7, r5 +100041de: f85e 5c2c ldr.w r5, [lr, #-44] +100041e2: 9700 str r7, [sp, #0] +100041e4: 406a eors r2, r5 +100041e6: 9d03 ldr r5, [sp, #12] +100041e8: 406a eors r2, r5 +100041ea: 4053 eors r3, r2 +100041ec: f85e 5c28 ldr.w r5, [lr, #-40] +100041f0: 9a04 ldr r2, [sp, #16] +100041f2: 406e eors r6, r5 +100041f4: f85b 5022 ldr.w r5, [fp, r2, lsl #2] +100041f8: f859 2024 ldr.w r2, [r9, r4, lsl #2] +100041fc: 4055 eors r5, r2 +100041fe: f85a 2021 ldr.w r2, [sl, r1, lsl #2] +10004202: f858 1020 ldr.w r1, [r8, r0, lsl #2] +10004206: 4056 eors r6, r2 +10004208: f85e 2c24 ldr.w r2, [lr, #-36] +1000420c: 4055 eors r5, r2 +1000420e: f3cc 2207 ubfx r2, ip, #8, #8 +10004212: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +10004216: 4055 eors r5, r2 +10004218: f3cc 4207 ubfx r2, ip, #16, #8 +1000421c: f858 2022 ldr.w r2, [r8, r2, lsl #2] +10004220: 404d eors r5, r1 +10004222: 4056 eors r6, r2 +10004224: 9a01 ldr r2, [sp, #4] +10004226: 3a01 subs r2, #1 +10004228: 9201 str r2, [sp, #4] +1000422a: f47f af47 bne.w 100040bc +1000422e: e9dd 2005 ldrd r2, r0, [sp, #20] +10004232: 46be mov lr, r7 +10004234: eb00 1242 add.w r2, r0, r2, lsl #5 +10004238: f8dd c01c ldr.w ip, [sp, #28] +1000423c: f1a2 0020 sub.w r0, r2, #32 +10004240: fa5f f28e uxtb.w r2, lr +10004244: f85b 7022 ldr.w r7, [fp, r2, lsl #2] +10004248: 0e2a lsrs r2, r5, #24 +1000424a: f859 2022 ldr.w r2, [r9, r2, lsl #2] +1000424e: 4057 eors r7, r2 +10004250: b2ea uxtb r2, r5 +10004252: f85b 1022 ldr.w r1, [fp, r2, lsl #2] +10004256: 0e32 lsrs r2, r6, #24 +10004258: f859 2022 ldr.w r2, [r9, r2, lsl #2] +1000425c: 4051 eors r1, r2 +1000425e: 6802 ldr r2, [r0, #0] +10004260: 4057 eors r7, r2 +10004262: f3c3 2207 ubfx r2, r3, #8, #8 +10004266: f85a 2022 ldr.w r2, [sl, r2, lsl #2] +1000426a: 4057 eors r7, r2 +1000426c: b2da uxtb r2, r3 +1000426e: f85b 4022 ldr.w r4, [fp, r2, lsl #2] +10004272: 4672 mov r2, lr +10004274: 0e12 lsrs r2, r2, #24 +10004276: f859 2022 ldr.w r2, [r9, r2, lsl #2] +1000427a: 4054 eors r4, r2 +1000427c: 68c2 ldr r2, [r0, #12] +1000427e: 9401 str r4, [sp, #4] +10004280: 4051 eors r1, r2 +10004282: f3c6 4207 ubfx r2, r6, #16, #8 +10004286: f858 2022 ldr.w r2, [r8, r2, lsl #2] +1000428a: 9c00 ldr r4, [sp, #0] +1000428c: 407a eors r2, r7 +1000428e: b2f7 uxtb r7, r6 +10004290: f3c6 2607 ubfx r6, r6, #8, #8 +10004294: f85b e027 ldr.w lr, [fp, r7, lsl #2] +10004298: f85a 7026 ldr.w r7, [sl, r6, lsl #2] +1000429c: 0e1e lsrs r6, r3, #24 +1000429e: f859 6026 ldr.w r6, [r9, r6, lsl #2] +100042a2: f3c3 4307 ubfx r3, r3, #16, #8 +100042a6: ea8e 0606 eor.w r6, lr, r6 +100042aa: f3c4 2e07 ubfx lr, r4, #8, #8 +100042ae: f85a e02e ldr.w lr, [sl, lr, lsl #2] +100042b2: f858 3023 ldr.w r3, [r8, r3, lsl #2] +100042b6: ea81 010e eor.w r1, r1, lr +100042ba: 4059 eors r1, r3 +100042bc: f3c4 4907 ubfx r9, r4, #16, #8 +100042c0: 6843 ldr r3, [r0, #4] +100042c2: 9c01 ldr r4, [sp, #4] +100042c4: f858 e029 ldr.w lr, [r8, r9, lsl #2] +100042c8: 405c eors r4, r3 +100042ca: 6883 ldr r3, [r0, #8] +100042cc: 407c eors r4, r7 +100042ce: 4073 eors r3, r6 +100042d0: f3c5 4607 ubfx r6, r5, #16, #8 +100042d4: f3c5 2507 ubfx r5, r5, #8, #8 +100042d8: f85a 5025 ldr.w r5, [sl, r5, lsl #2] +100042dc: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100042e0: 406b eors r3, r5 +100042e2: 4d3d ldr r5, [pc, #244] @ (100043d8 ) +100042e4: 4074 eors r4, r6 +100042e6: b2d6 uxtb r6, r2 +100042e8: 5daf ldrb r7, [r5, r6] +100042ea: 6906 ldr r6, [r0, #16] +100042ec: ea83 030e eor.w r3, r3, lr +100042f0: 4077 eors r7, r6 +100042f2: 0e0e lsrs r6, r1, #24 +100042f4: 5dae ldrb r6, [r5, r6] +100042f6: e9cd 430d strd r4, r3, [sp, #52] @ 0x34 +100042fa: ea87 6706 eor.w r7, r7, r6, lsl #24 +100042fe: f3c4 2607 ubfx r6, r4, #8, #8 +10004302: 5dae ldrb r6, [r5, r6] +10004304: 920c str r2, [sp, #48] @ 0x30 +10004306: ea87 2706 eor.w r7, r7, r6, lsl #8 +1000430a: f3c3 4607 ubfx r6, r3, #16, #8 +1000430e: 5dae ldrb r6, [r5, r6] +10004310: 910f str r1, [sp, #60] @ 0x3c +10004312: ea87 4706 eor.w r7, r7, r6, lsl #16 +10004316: b2e6 uxtb r6, r4 +10004318: 9708 str r7, [sp, #32] +1000431a: f815 e006 ldrb.w lr, [r5, r6] +1000431e: 6946 ldr r6, [r0, #20] +10004320: ea4f 6a12 mov.w sl, r2, lsr #24 +10004324: ea8e 0e06 eor.w lr, lr, r6 +10004328: f815 600a ldrb.w r6, [r5, sl] +1000432c: fa5f f883 uxtb.w r8, r3 +10004330: f815 8008 ldrb.w r8, [r5, r8] +10004334: ea8e 6e06 eor.w lr, lr, r6, lsl #24 +10004338: 6986 ldr r6, [r0, #24] +1000433a: fa5f f981 uxtb.w r9, r1 +1000433e: ea88 0806 eor.w r8, r8, r6 +10004342: 0e26 lsrs r6, r4, #24 +10004344: 5dae ldrb r6, [r5, r6] +10004346: f3c4 4407 ubfx r4, r4, #16, #8 +1000434a: f815 9009 ldrb.w r9, [r5, r9] +1000434e: 69c0 ldr r0, [r0, #28] +10004350: ea88 6806 eor.w r8, r8, r6, lsl #24 +10004354: 5d2e ldrb r6, [r5, r4] +10004356: 0e1c lsrs r4, r3, #24 +10004358: 5d2c ldrb r4, [r5, r4] +1000435a: ea89 0000 eor.w r0, r9, r0 +1000435e: f3c3 2307 ubfx r3, r3, #8, #8 +10004362: 5ceb ldrb r3, [r5, r3] +10004364: ea80 6004 eor.w r0, r0, r4, lsl #24 +10004368: f3c1 2407 ubfx r4, r1, #8, #8 +1000436c: f3c1 4107 ubfx r1, r1, #16, #8 +10004370: 5c69 ldrb r1, [r5, r1] +10004372: ea8e 2303 eor.w r3, lr, r3, lsl #8 +10004376: ea83 4101 eor.w r1, r3, r1, lsl #16 +1000437a: f3c2 2307 ubfx r3, r2, #8, #8 +1000437e: f3c2 4207 ubfx r2, r2, #16, #8 +10004382: 5d2c ldrb r4, [r5, r4] +10004384: 5ceb ldrb r3, [r5, r3] +10004386: 5caa ldrb r2, [r5, r2] +10004388: 9109 str r1, [sp, #36] @ 0x24 +1000438a: f8cc 1004 str.w r1, [ip, #4] +1000438e: 2120 movs r1, #32 +10004390: ea88 2404 eor.w r4, r8, r4, lsl #8 +10004394: ea80 2303 eor.w r3, r0, r3, lsl #8 +10004398: ea83 4306 eor.w r3, r3, r6, lsl #16 +1000439c: ea84 4202 eor.w r2, r4, r2, lsl #16 +100043a0: eb0d 0001 add.w r0, sp, r1 +100043a4: f8cc 7000 str.w r7, [ip] +100043a8: f8cc 2008 str.w r2, [ip, #8] +100043ac: f8cc 300c str.w r3, [ip, #12] +100043b0: 930b str r3, [sp, #44] @ 0x2c +100043b2: 920a str r2, [sp, #40] @ 0x28 +100043b4: f000 ff96 bl 100052e4 +100043b8: 2000 movs r0, #0 +100043ba: b011 add sp, #68 @ 0x44 +100043bc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100043c0: f8df b018 ldr.w fp, [pc, #24] @ 100043dc +100043c4: f8df 9018 ldr.w r9, [pc, #24] @ 100043e0 +100043c8: f8df a018 ldr.w sl, [pc, #24] @ 100043e4 +100043cc: f8df 8018 ldr.w r8, [pc, #24] @ 100043e8 +100043d0: f8dd e000 ldr.w lr, [sp] +100043d4: e734 b.n 10004240 +100043d6: bf00 nop +100043d8: 20000b88 .word 0x20000b88 +100043dc: 20000e30 .word 0x20000e30 +100043e0: 20001a30 .word 0x20001a30 +100043e4: 20001230 .word 0x20001230 +100043e8: 20001630 .word 0x20001630 + +100043ec : +100043ec: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100043f0: 4694 mov ip, r2 +100043f2: 6842 ldr r2, [r0, #4] +100043f4: f100 0308 add.w r3, r0, #8 +100043f8: eb03 0582 add.w r5, r3, r2, lsl #2 +100043fc: f8d1 9000 ldr.w r9, [r1] +10004400: f853 3022 ldr.w r3, [r3, r2, lsl #2] +10004404: 686a ldr r2, [r5, #4] +10004406: ea89 0903 eor.w r9, r9, r3 +1000440a: 684b ldr r3, [r1, #4] +1000440c: 68ce ldr r6, [r1, #12] +1000440e: 4053 eors r3, r2 +10004410: 688a ldr r2, [r1, #8] +10004412: 68a9 ldr r1, [r5, #8] +10004414: 6807 ldr r7, [r0, #0] +10004416: 404a eors r2, r1 +10004418: 68e9 ldr r1, [r5, #12] +1000441a: 107f asrs r7, r7, #1 +1000441c: 404e eors r6, r1 +1000441e: 1e79 subs r1, r7, #1 +10004420: b093 sub sp, #76 @ 0x4c +10004422: 2900 cmp r1, #0 +10004424: 9100 str r1, [sp, #0] +10004426: f105 0410 add.w r4, r5, #16 +1000442a: f340 8196 ble.w 1000475a +1000442e: 49cf ldr r1, [pc, #828] @ (1000476c ) +10004430: e9cd 7407 strd r7, r4, [sp, #28] +10004434: 468e mov lr, r1 +10004436: f8df b33c ldr.w fp, [pc, #828] @ 10004774 +1000443a: f8df 833c ldr.w r8, [pc, #828] @ 10004778 +1000443e: f8df a33c ldr.w sl, [pc, #828] @ 1000477c +10004442: 3530 adds r5, #48 @ 0x30 +10004444: 9106 str r1, [sp, #24] +10004446: f8cd c024 str.w ip, [sp, #36] @ 0x24 +1000444a: fa5f f189 uxtb.w r1, r9 +1000444e: f85b 7021 ldr.w r7, [fp, r1, lsl #2] +10004452: 0e19 lsrs r1, r3, #24 +10004454: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +10004458: 3520 adds r5, #32 +1000445a: 404f eors r7, r1 +1000445c: b2d9 uxtb r1, r3 +1000445e: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +10004462: 0e11 lsrs r1, r2, #24 +10004464: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +10004468: ea80 0c01 eor.w ip, r0, r1 +1000446c: b2d1 uxtb r1, r2 +1000446e: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +10004472: 0e31 lsrs r1, r6, #24 +10004474: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +10004478: 4048 eors r0, r1 +1000447a: b2f1 uxtb r1, r6 +1000447c: f85b 4021 ldr.w r4, [fp, r1, lsl #2] +10004480: ea4f 6119 mov.w r1, r9, lsr #24 +10004484: f85e 1021 ldr.w r1, [lr, r1, lsl #2] +10004488: 404c eors r4, r1 +1000448a: f855 1c40 ldr.w r1, [r5, #-64] +1000448e: 404f eors r7, r1 +10004490: f855 1c3c ldr.w r1, [r5, #-60] +10004494: ea8c 0c01 eor.w ip, ip, r1 +10004498: f855 1c38 ldr.w r1, [r5, #-56] +1000449c: 4048 eors r0, r1 +1000449e: f855 1c34 ldr.w r1, [r5, #-52] +100044a2: 404c eors r4, r1 +100044a4: f3c6 2107 ubfx r1, r6, #8, #8 +100044a8: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100044ac: f3c6 4607 ubfx r6, r6, #16, #8 +100044b0: 404f eors r7, r1 +100044b2: f85a 1026 ldr.w r1, [sl, r6, lsl #2] +100044b6: f3c9 2607 ubfx r6, r9, #8, #8 +100044ba: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100044be: f3c9 4907 ubfx r9, r9, #16, #8 +100044c2: ea8c 0c06 eor.w ip, ip, r6 +100044c6: f3c3 2607 ubfx r6, r3, #8, #8 +100044ca: f858 6026 ldr.w r6, [r8, r6, lsl #2] +100044ce: ea8c 0c01 eor.w ip, ip, r1 +100044d2: f85a 1029 ldr.w r1, [sl, r9, lsl #2] +100044d6: 4070 eors r0, r6 +100044d8: 4048 eors r0, r1 +100044da: f3c2 2107 ubfx r1, r2, #8, #8 +100044de: f3c2 4207 ubfx r2, r2, #16, #8 +100044e2: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100044e6: f85a 6022 ldr.w r6, [sl, r2, lsl #2] +100044ea: f3c3 4307 ubfx r3, r3, #16, #8 +100044ee: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +100044f2: 407e eors r6, r7 +100044f4: 404c eors r4, r1 +100044f6: 405c eors r4, r3 +100044f8: b2f3 uxtb r3, r6 +100044fa: f85b 2023 ldr.w r2, [fp, r3, lsl #2] +100044fe: ea4f 631c mov.w r3, ip, lsr #24 +10004502: f85e 3023 ldr.w r3, [lr, r3, lsl #2] +10004506: ea82 0903 eor.w r9, r2, r3 +1000450a: f3c4 2307 ubfx r3, r4, #8, #8 +1000450e: f858 3023 ldr.w r3, [r8, r3, lsl #2] +10004512: 9301 str r3, [sp, #4] +10004514: f3c0 4307 ubfx r3, r0, #16, #8 +10004518: f85a 2023 ldr.w r2, [sl, r3, lsl #2] +1000451c: fa5f f38c uxtb.w r3, ip +10004520: f85b 1023 ldr.w r1, [fp, r3, lsl #2] +10004524: 0e03 lsrs r3, r0, #24 +10004526: f85e 3023 ldr.w r3, [lr, r3, lsl #2] +1000452a: 9202 str r2, [sp, #8] +1000452c: 4059 eors r1, r3 +1000452e: f3c6 2307 ubfx r3, r6, #8, #8 +10004532: f858 7023 ldr.w r7, [r8, r3, lsl #2] +10004536: f3c4 4307 ubfx r3, r4, #16, #8 +1000453a: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +1000453e: 9703 str r7, [sp, #12] +10004540: b2c2 uxtb r2, r0 +10004542: 0e27 lsrs r7, r4, #24 +10004544: 9304 str r3, [sp, #16] +10004546: f85b 2022 ldr.w r2, [fp, r2, lsl #2] +1000454a: f85e 7027 ldr.w r7, [lr, r7, lsl #2] +1000454e: 9b01 ldr r3, [sp, #4] +10004550: 407a eors r2, r7 +10004552: 0e37 lsrs r7, r6, #24 +10004554: 9705 str r7, [sp, #20] +10004556: f855 7c30 ldr.w r7, [r5, #-48] +1000455a: b2e4 uxtb r4, r4 +1000455c: ea89 0707 eor.w r7, r9, r7 +10004560: 405f eors r7, r3 +10004562: 9b02 ldr r3, [sp, #8] +10004564: f85b 4024 ldr.w r4, [fp, r4, lsl #2] +10004568: ea87 0903 eor.w r9, r7, r3 +1000456c: f855 7c2c ldr.w r7, [r5, #-44] +10004570: 9b04 ldr r3, [sp, #16] +10004572: 4079 eors r1, r7 +10004574: 9f03 ldr r7, [sp, #12] +10004576: f3c6 4607 ubfx r6, r6, #16, #8 +1000457a: 4079 eors r1, r7 +1000457c: f855 7c28 ldr.w r7, [r5, #-40] +10004580: 404b eors r3, r1 +10004582: 407a eors r2, r7 +10004584: 9f05 ldr r7, [sp, #20] +10004586: f3c0 2007 ubfx r0, r0, #8, #8 +1000458a: f85e 1027 ldr.w r1, [lr, r7, lsl #2] +1000458e: f85a 7026 ldr.w r7, [sl, r6, lsl #2] +10004592: 404c eors r4, r1 +10004594: f855 1c24 ldr.w r1, [r5, #-36] +10004598: f858 0020 ldr.w r0, [r8, r0, lsl #2] +1000459c: ea84 0601 eor.w r6, r4, r1 +100045a0: f3cc 2107 ubfx r1, ip, #8, #8 +100045a4: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100045a8: 4046 eors r6, r0 +100045aa: 404a eors r2, r1 +100045ac: f3cc 4107 ubfx r1, ip, #16, #8 +100045b0: f85a 1021 ldr.w r1, [sl, r1, lsl #2] +100045b4: 407a eors r2, r7 +100045b6: 404e eors r6, r1 +100045b8: 9900 ldr r1, [sp, #0] +100045ba: 3901 subs r1, #1 +100045bc: 9100 str r1, [sp, #0] +100045be: f47f af44 bne.w 1000444a +100045c2: e9dd 7407 ldrd r7, r4, [sp, #28] +100045c6: f8dd c024 ldr.w ip, [sp, #36] @ 0x24 +100045ca: eb04 1747 add.w r7, r4, r7, lsl #5 +100045ce: f1a7 0420 sub.w r4, r7, #32 +100045d2: 9d06 ldr r5, [sp, #24] +100045d4: fa5f f189 uxtb.w r1, r9 +100045d8: f85b 0021 ldr.w r0, [fp, r1, lsl #2] +100045dc: 0e19 lsrs r1, r3, #24 +100045de: f855 1021 ldr.w r1, [r5, r1, lsl #2] +100045e2: 4048 eors r0, r1 +100045e4: b2d9 uxtb r1, r3 +100045e6: f85b 7021 ldr.w r7, [fp, r1, lsl #2] +100045ea: 0e11 lsrs r1, r2, #24 +100045ec: f855 1021 ldr.w r1, [r5, r1, lsl #2] +100045f0: 404f eors r7, r1 +100045f2: 6821 ldr r1, [r4, #0] +100045f4: 4048 eors r0, r1 +100045f6: f3c6 2107 ubfx r1, r6, #8, #8 +100045fa: f858 1021 ldr.w r1, [r8, r1, lsl #2] +100045fe: 4048 eors r0, r1 +10004600: b2f1 uxtb r1, r6 +10004602: f85b e021 ldr.w lr, [fp, r1, lsl #2] +10004606: ea4f 6119 mov.w r1, r9, lsr #24 +1000460a: f855 1021 ldr.w r1, [r5, r1, lsl #2] +1000460e: ea8e 0101 eor.w r1, lr, r1 +10004612: 9100 str r1, [sp, #0] +10004614: 6861 ldr r1, [r4, #4] +10004616: fa5f fe82 uxtb.w lr, r2 +1000461a: 404f eors r7, r1 +1000461c: f3c2 4107 ubfx r1, r2, #16, #8 +10004620: f85a 1021 ldr.w r1, [sl, r1, lsl #2] +10004624: f3c2 2207 ubfx r2, r2, #8, #8 +10004628: 4048 eors r0, r1 +1000462a: f3c9 2107 ubfx r1, r9, #8, #8 +1000462e: f858 1021 ldr.w r1, [r8, r1, lsl #2] +10004632: f3c9 4907 ubfx r9, r9, #16, #8 +10004636: 404f eors r7, r1 +10004638: f85a 1029 ldr.w r1, [sl, r9, lsl #2] +1000463c: f858 9022 ldr.w r9, [r8, r2, lsl #2] +10004640: 0e32 lsrs r2, r6, #24 +10004642: f855 2022 ldr.w r2, [r5, r2, lsl #2] +10004646: f85b e02e ldr.w lr, [fp, lr, lsl #2] +1000464a: f3c6 4607 ubfx r6, r6, #16, #8 +1000464e: f85a 6026 ldr.w r6, [sl, r6, lsl #2] +10004652: 9d00 ldr r5, [sp, #0] +10004654: ea8e 0e02 eor.w lr, lr, r2 +10004658: 68e2 ldr r2, [r4, #12] +1000465a: 407e eors r6, r7 +1000465c: 4055 eors r5, r2 +1000465e: f3c3 2707 ubfx r7, r3, #8, #8 +10004662: 68a2 ldr r2, [r4, #8] +10004664: f3c3 4307 ubfx r3, r3, #16, #8 +10004668: f858 7027 ldr.w r7, [r8, r7, lsl #2] +1000466c: f85a 3023 ldr.w r3, [sl, r3, lsl #2] +10004670: ea85 0509 eor.w r5, r5, r9 +10004674: ea8e 0202 eor.w r2, lr, r2 +10004678: ea85 0803 eor.w r8, r5, r3 +1000467c: 407a eors r2, r7 +1000467e: 4b3c ldr r3, [pc, #240] @ (10004770 ) +10004680: 404a eors r2, r1 +10004682: b2c1 uxtb r1, r0 +10004684: 6925 ldr r5, [r4, #16] +10004686: 5c59 ldrb r1, [r3, r1] +10004688: e9cd 2810 strd r2, r8, [sp, #64] @ 0x40 +1000468c: 4069 eors r1, r5 +1000468e: 0e35 lsrs r5, r6, #24 +10004690: 5d5d ldrb r5, [r3, r5] +10004692: 900e str r0, [sp, #56] @ 0x38 +10004694: ea81 6105 eor.w r1, r1, r5, lsl #24 +10004698: f3c8 2507 ubfx r5, r8, #8, #8 +1000469c: 5d5d ldrb r5, [r3, r5] +1000469e: 960f str r6, [sp, #60] @ 0x3c +100046a0: ea81 2105 eor.w r1, r1, r5, lsl #8 +100046a4: f3c2 4507 ubfx r5, r2, #16, #8 +100046a8: 5d5d ldrb r5, [r3, r5] +100046aa: ea4f 6a12 mov.w sl, r2, lsr #24 +100046ae: ea81 4105 eor.w r1, r1, r5, lsl #16 +100046b2: b2f5 uxtb r5, r6 +100046b4: 910a str r1, [sp, #40] @ 0x28 +100046b6: 6967 ldr r7, [r4, #20] +100046b8: 5d5d ldrb r5, [r3, r5] +100046ba: fa5f f982 uxtb.w r9, r2 +100046be: 407d eors r5, r7 +100046c0: f813 700a ldrb.w r7, [r3, sl] +100046c4: fa5f fe88 uxtb.w lr, r8 +100046c8: f3c2 2207 ubfx r2, r2, #8, #8 +100046cc: ea85 6507 eor.w r5, r5, r7, lsl #24 +100046d0: f813 7009 ldrb.w r7, [r3, r9] +100046d4: f813 900e ldrb.w r9, [r3, lr] +100046d8: f813 e002 ldrb.w lr, [r3, r2] +100046dc: 69a2 ldr r2, [r4, #24] +100046de: 69e4 ldr r4, [r4, #28] +100046e0: 407a eors r2, r7 +100046e2: ea4f 6718 mov.w r7, r8, lsr #24 +100046e6: 5ddf ldrb r7, [r3, r7] +100046e8: ea89 0404 eor.w r4, r9, r4 +100046ec: ea82 6707 eor.w r7, r2, r7, lsl #24 +100046f0: f3c8 4207 ubfx r2, r8, #16, #8 +100046f4: ea4f 6810 mov.w r8, r0, lsr #24 +100046f8: f813 8008 ldrb.w r8, [r3, r8] +100046fc: 5c9a ldrb r2, [r3, r2] +100046fe: ea84 6408 eor.w r4, r4, r8, lsl #24 +10004702: ea84 240e eor.w r4, r4, lr, lsl #8 +10004706: f3c0 2e07 ubfx lr, r0, #8, #8 +1000470a: f813 e00e ldrb.w lr, [r3, lr] +1000470e: f3c0 4007 ubfx r0, r0, #16, #8 +10004712: ea85 250e eor.w r5, r5, lr, lsl #8 +10004716: ea85 4502 eor.w r5, r5, r2, lsl #16 +1000471a: f3c6 2207 ubfx r2, r6, #8, #8 +1000471e: 5c9a ldrb r2, [r3, r2] +10004720: f3c6 4607 ubfx r6, r6, #16, #8 +10004724: 5c18 ldrb r0, [r3, r0] +10004726: 5d9b ldrb r3, [r3, r6] +10004728: ea87 2202 eor.w r2, r7, r2, lsl #8 +1000472c: ea82 4200 eor.w r2, r2, r0, lsl #16 +10004730: ea84 4303 eor.w r3, r4, r3, lsl #16 +10004734: f8cc 1000 str.w r1, [ip] +10004738: a80a add r0, sp, #40 @ 0x28 +1000473a: 2120 movs r1, #32 +1000473c: f8cc 5004 str.w r5, [ip, #4] +10004740: f8cc 2008 str.w r2, [ip, #8] +10004744: f8cc 300c str.w r3, [ip, #12] +10004748: 950b str r5, [sp, #44] @ 0x2c +1000474a: 920c str r2, [sp, #48] @ 0x30 +1000474c: 930d str r3, [sp, #52] @ 0x34 +1000474e: f000 fdc9 bl 100052e4 +10004752: 2000 movs r0, #0 +10004754: b013 add sp, #76 @ 0x4c +10004756: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000475a: 4904 ldr r1, [pc, #16] @ (1000476c ) +1000475c: f8df b014 ldr.w fp, [pc, #20] @ 10004774 +10004760: f8df 8014 ldr.w r8, [pc, #20] @ 10004778 +10004764: f8df a014 ldr.w sl, [pc, #20] @ 1000477c +10004768: 9106 str r1, [sp, #24] +1000476a: e732 b.n 100045d2 +1000476c: 20002b30 .word 0x20002b30 +10004770: 20001e30 .word 0x20001e30 +10004774: 20001f30 .word 0x20001f30 +10004778: 20002330 .word 0x20002330 +1000477c: 20002730 .word 0x20002730 + +10004780 : +10004780: 2901 cmp r1, #1 +10004782: b510 push {r4, lr} +10004784: 460c mov r4, r1 +10004786: d809 bhi.n 1000479c +10004788: 4611 mov r1, r2 +1000478a: 461a mov r2, r3 +1000478c: b11c cbz r4, 10004796 +1000478e: f7ff fc63 bl 10004058 +10004792: 2000 movs r0, #0 +10004794: bd10 pop {r4, pc} +10004796: f7ff fe29 bl 100043ec +1000479a: e7fa b.n 10004792 +1000479c: f06f 0020 mvn.w r0, #32 +100047a0: bd10 pop {r4, pc} +100047a2: bf00 nop + +100047a4 : +100047a4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} +100047a8: 2901 cmp r1, #1 +100047aa: b085 sub sp, #20 +100047ac: 9e0c ldr r6, [sp, #48] @ 0x30 +100047ae: d867 bhi.n 10004880 +100047b0: b382 cbz r2, 10004814 +100047b2: 0714 lsls r4, r2, #28 +100047b4: d167 bne.n 10004886 +100047b6: 4607 mov r7, r0 +100047b8: 461d mov r5, r3 +100047ba: bb79 cbnz r1, 1000481c +100047bc: 9c0d ldr r4, [sp, #52] @ 0x34 +100047be: eb04 0802 add.w r8, r4, r2 +100047c2: 46ec mov ip, sp +100047c4: 6830 ldr r0, [r6, #0] +100047c6: 6871 ldr r1, [r6, #4] +100047c8: 68b2 ldr r2, [r6, #8] +100047ca: 68f3 ldr r3, [r6, #12] +100047cc: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} +100047d0: 4622 mov r2, r4 +100047d2: 4631 mov r1, r6 +100047d4: 4638 mov r0, r7 +100047d6: f7ff fe09 bl 100043ec +100047da: 46ec mov ip, sp +100047dc: 6821 ldr r1, [r4, #0] +100047de: 682a ldr r2, [r5, #0] +100047e0: 6863 ldr r3, [r4, #4] +100047e2: 404a eors r2, r1 +100047e4: 6022 str r2, [r4, #0] +100047e6: 6869 ldr r1, [r5, #4] +100047e8: 68a2 ldr r2, [r4, #8] +100047ea: 404b eors r3, r1 +100047ec: 6063 str r3, [r4, #4] +100047ee: 68a9 ldr r1, [r5, #8] +100047f0: 68e3 ldr r3, [r4, #12] +100047f2: 404a eors r2, r1 +100047f4: 60a2 str r2, [r4, #8] +100047f6: 68ea ldr r2, [r5, #12] +100047f8: 3410 adds r4, #16 +100047fa: 4053 eors r3, r2 +100047fc: 4544 cmp r4, r8 +100047fe: f844 3c04 str.w r3, [r4, #-4] +10004802: f106 0610 add.w r6, r6, #16 +10004806: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} +1000480a: 6028 str r0, [r5, #0] +1000480c: 6069 str r1, [r5, #4] +1000480e: 60aa str r2, [r5, #8] +10004810: 60eb str r3, [r5, #12] +10004812: d1d6 bne.n 100047c2 +10004814: 2000 movs r0, #0 +10004816: b005 add sp, #20 +10004818: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} +1000481c: 4691 mov r9, r2 +1000481e: 461c mov r4, r3 +10004820: 9b0d ldr r3, [sp, #52] @ 0x34 +10004822: 4416 add r6, r2 +10004824: eb03 0802 add.w r8, r3, r2 +10004828: 4623 mov r3, r4 +1000482a: eba6 0209 sub.w r2, r6, r9 +1000482e: f8d3 c000 ldr.w ip, [r3] +10004832: 6811 ldr r1, [r2, #0] +10004834: eba8 0409 sub.w r4, r8, r9 +10004838: ea81 010c eor.w r1, r1, ip +1000483c: 6021 str r1, [r4, #0] +1000483e: f8d3 c004 ldr.w ip, [r3, #4] +10004842: 6851 ldr r1, [r2, #4] +10004844: 4638 mov r0, r7 +10004846: ea81 010c eor.w r1, r1, ip +1000484a: 6061 str r1, [r4, #4] +1000484c: 6891 ldr r1, [r2, #8] +1000484e: f8d3 c008 ldr.w ip, [r3, #8] +10004852: ea81 010c eor.w r1, r1, ip +10004856: 60a1 str r1, [r4, #8] +10004858: 68d1 ldr r1, [r2, #12] +1000485a: 68db ldr r3, [r3, #12] +1000485c: 4622 mov r2, r4 +1000485e: 404b eors r3, r1 +10004860: 60e3 str r3, [r4, #12] +10004862: 4621 mov r1, r4 +10004864: f7ff fbf8 bl 10004058 +10004868: f1b9 0910 subs.w r9, r9, #16 +1000486c: d1dc bne.n 10004828 +1000486e: 6820 ldr r0, [r4, #0] +10004870: 6861 ldr r1, [r4, #4] +10004872: 68a2 ldr r2, [r4, #8] +10004874: 68e3 ldr r3, [r4, #12] +10004876: 6028 str r0, [r5, #0] +10004878: 6069 str r1, [r5, #4] +1000487a: 60aa str r2, [r5, #8] +1000487c: 60eb str r3, [r5, #12] +1000487e: e7c9 b.n 10004814 +10004880: f06f 0020 mvn.w r0, #32 +10004884: e7c7 b.n 10004816 +10004886: f06f 0021 mvn.w r0, #33 @ 0x21 +1000488a: e7c4 b.n 10004816 + +1000488c : +1000488c: 4b07 ldr r3, [pc, #28] @ (100048ac ) +1000488e: 685a ldr r2, [r3, #4] +10004890: b14a cbz r2, 100048a6 +10004892: 3308 adds r3, #8 +10004894: e002 b.n 1000489c +10004896: f853 2c04 ldr.w r2, [r3, #-4] +1000489a: b122 cbz r2, 100048a6 +1000489c: f813 1c08 ldrb.w r1, [r3, #-8] +100048a0: 3308 adds r3, #8 +100048a2: 4281 cmp r1, r0 +100048a4: d1f7 bne.n 10004896 +100048a6: 4610 mov r0, r2 +100048a8: 4770 bx lr +100048aa: bf00 nop +100048ac: 10006138 .word 0x10006138 + +100048b0 : +100048b0: 2244 movs r2, #68 @ 0x44 +100048b2: 2100 movs r1, #0 +100048b4: f001 b85a b.w 1000596c + +100048b8 : +100048b8: b1b8 cbz r0, 100048ea +100048ba: b510 push {r4, lr} +100048bc: 4604 mov r4, r0 +100048be: 6c00 ldr r0, [r0, #64] @ 0x40 +100048c0: b110 cbz r0, 100048c8 +100048c2: 2124 movs r1, #36 @ 0x24 +100048c4: f000 fd1a bl 100052fc +100048c8: 6be0 ldr r0, [r4, #60] @ 0x3c +100048ca: b140 cbz r0, 100048de +100048cc: 6823 ldr r3, [r4, #0] +100048ce: 4a07 ldr r2, [pc, #28] @ (100048ec ) +100048d0: 79db ldrb r3, [r3, #7] +100048d2: f3c3 0384 ubfx r3, r3, #2, #5 +100048d6: f852 3023 ldr.w r3, [r2, r3, lsl #2] +100048da: 699b ldr r3, [r3, #24] +100048dc: 4798 blx r3 +100048de: 4620 mov r0, r4 +100048e0: e8bd 4010 ldmia.w sp!, {r4, lr} +100048e4: 2144 movs r1, #68 @ 0x44 +100048e6: f000 bcfd b.w 100052e4 +100048ea: 4770 bx lr +100048ec: 20000624 .word 0x20000624 + +100048f0 : +100048f0: b1a1 cbz r1, 1000491c +100048f2: b538 push {r3, r4, r5, lr} +100048f4: 460c mov r4, r1 +100048f6: 2244 movs r2, #68 @ 0x44 +100048f8: 2100 movs r1, #0 +100048fa: 4605 mov r5, r0 +100048fc: f001 f836 bl 1000596c +10004900: 79e3 ldrb r3, [r4, #7] +10004902: 4a09 ldr r2, [pc, #36] @ (10004928 ) +10004904: f3c3 0384 ubfx r3, r3, #2, #5 +10004908: f852 3023 ldr.w r3, [r2, r3, lsl #2] +1000490c: 695b ldr r3, [r3, #20] +1000490e: b113 cbz r3, 10004916 +10004910: 4798 blx r3 +10004912: 63e8 str r0, [r5, #60] @ 0x3c +10004914: b120 cbz r0, 10004920 +10004916: 2000 movs r0, #0 +10004918: 602c str r4, [r5, #0] +1000491a: bd38 pop {r3, r4, r5, pc} +1000491c: 4803 ldr r0, [pc, #12] @ (1000492c ) +1000491e: 4770 bx lr +10004920: f5a0 40c3 sub.w r0, r0, #24960 @ 0x6180 +10004924: bd38 pop {r3, r4, r5, pc} +10004926: bf00 nop +10004928: 20000624 .word 0x20000624 +1000492c: ffff9f00 .word 0xffff9f00 + +10004930 : +10004930: b430 push {r4, r5} +10004932: b2dc uxtb r4, r3 +10004934: 2c01 cmp r4, #1 +10004936: d829 bhi.n 1000498c +10004938: 6804 ldr r4, [r0, #0] +1000493a: b33c cbz r4, 1000498c +1000493c: f894 c007 ldrb.w ip, [r4, #7] +10004940: f00c 0c03 and.w ip, ip, #3 +10004944: f1bc 0f01 cmp.w ip, #1 +10004948: d91a bls.n 10004980 +1000494a: 7203 strb r3, [r0, #8] +1000494c: f894 c007 ldrb.w ip, [r4, #7] +10004950: 4d10 ldr r5, [pc, #64] @ (10004994 ) +10004952: f3cc 0c84 ubfx ip, ip, #2, #5 +10004956: 2b01 cmp r3, #1 +10004958: 6042 str r2, [r0, #4] +1000495a: f855 502c ldr.w r5, [r5, ip, lsl #2] +1000495e: 6bc0 ldr r0, [r0, #60] @ 0x3c +10004960: d00b beq.n 1000497a +10004962: 7963 ldrb r3, [r4, #5] +10004964: f003 04f0 and.w r4, r3, #240 @ 0xf0 +10004968: 2c30 cmp r4, #48 @ 0x30 +1000496a: d006 beq.n 1000497a +1000496c: f003 03e0 and.w r3, r3, #224 @ 0xe0 +10004970: 2b40 cmp r3, #64 @ 0x40 +10004972: d002 beq.n 1000497a +10004974: 692b ldr r3, [r5, #16] +10004976: bc30 pop {r4, r5} +10004978: 4718 bx r3 +1000497a: 68eb ldr r3, [r5, #12] +1000497c: bc30 pop {r4, r5} +1000497e: 4718 bx r3 +10004980: 7965 ldrb r5, [r4, #5] +10004982: f005 050f and.w r5, r5, #15 +10004986: ebb2 1f85 cmp.w r2, r5, lsl #6 +1000498a: d0de beq.n 1000494a +1000498c: 4802 ldr r0, [pc, #8] @ (10004998 ) +1000498e: bc30 pop {r4, r5} +10004990: 4770 bx lr +10004992: bf00 nop +10004994: 20000624 .word 0x20000624 +10004998: ffff9f00 .word 0xffff9f00 + +1000499c : +1000499c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100049a0: b085 sub sp, #20 +100049a2: 9103 str r1, [sp, #12] +100049a4: 6801 ldr r1, [r0, #0] +100049a6: f8dd 9038 ldr.w r9, [sp, #56] @ 0x38 +100049aa: 2900 cmp r1, #0 +100049ac: f000 809e beq.w 10004aec +100049b0: 4615 mov r5, r2 +100049b2: 2200 movs r2, #0 +100049b4: 790e ldrb r6, [r1, #4] +100049b6: f8c9 2000 str.w r2, [r9] +100049ba: f016 061f ands.w r6, r6, #31 +100049be: f000 80c9 beq.w 10004b54 +100049c2: 794a ldrb r2, [r1, #5] +100049c4: 4604 mov r4, r0 +100049c6: f002 02f0 and.w r2, r2, #240 @ 0xf0 +100049ca: 2a10 cmp r2, #16 +100049cc: d071 beq.n 10004ab2 +100049ce: 4698 mov r8, r3 +100049d0: 9b03 ldr r3, [sp, #12] +100049d2: 4543 cmp r3, r8 +100049d4: f000 8081 beq.w 10004ada +100049d8: 2a20 cmp r2, #32 +100049da: f040 80b9 bne.w 10004b50 +100049de: f994 3008 ldrsb.w r3, [r4, #8] +100049e2: f8d4 a024 ldr.w sl, [r4, #36] @ 0x24 +100049e6: 2b00 cmp r3, #0 +100049e8: d138 bne.n 10004a5c +100049ea: 68e3 ldr r3, [r4, #12] +100049ec: eba6 0b0a sub.w fp, r6, sl +100049f0: 2b00 cmp r3, #0 +100049f2: d047 beq.n 10004a84 +100049f4: 455d cmp r5, fp +100049f6: d937 bls.n 10004a68 +100049f8: f1ba 0f00 cmp.w sl, #0 +100049fc: d17a bne.n 10004af4 +100049fe: fbb5 fafb udiv sl, r5, fp +10004a02: fb0b 5a1a mls sl, fp, sl, r5 +10004a06: f1ba 0f00 cmp.w sl, #0 +10004a0a: bf08 it eq +10004a0c: 46da moveq sl, fp +10004a0e: 9b03 ldr r3, [sp, #12] +10004a10: eba5 050a sub.w r5, r5, sl +10004a14: 1959 adds r1, r3, r5 +10004a16: 4652 mov r2, sl +10004a18: f104 0014 add.w r0, r4, #20 +10004a1c: f001 f81e bl 10005a5c +10004a20: 6a63 ldr r3, [r4, #36] @ 0x24 +10004a22: 4453 add r3, sl +10004a24: 6263 str r3, [r4, #36] @ 0x24 +10004a26: b34d cbz r5, 10004a7c +10004a28: f994 1008 ldrsb.w r1, [r4, #8] +10004a2c: 6823 ldr r3, [r4, #0] +10004a2e: 4a4b ldr r2, [pc, #300] @ (10004b5c ) +10004a30: 79db ldrb r3, [r3, #7] +10004a32: f3c3 0384 ubfx r3, r3, #2, #5 +10004a36: f852 3023 ldr.w r3, [r2, r3, lsl #2] +10004a3a: 9a03 ldr r2, [sp, #12] +10004a3c: f8cd 8004 str.w r8, [sp, #4] +10004a40: 9200 str r2, [sp, #0] +10004a42: 689e ldr r6, [r3, #8] +10004a44: 462a mov r2, r5 +10004a46: 6be0 ldr r0, [r4, #60] @ 0x3c +10004a48: f104 0328 add.w r3, r4, #40 @ 0x28 +10004a4c: 47b0 blx r6 +10004a4e: b9b0 cbnz r0, 10004a7e +10004a50: f8d9 3000 ldr.w r3, [r9] +10004a54: 442b add r3, r5 +10004a56: f8c9 3000 str.w r3, [r9] +10004a5a: e010 b.n 10004a7e +10004a5c: 2b01 cmp r3, #1 +10004a5e: d113 bne.n 10004a88 +10004a60: eba6 030a sub.w r3, r6, sl +10004a64: 42ab cmp r3, r5 +10004a66: d90f bls.n 10004a88 +10004a68: f10a 0014 add.w r0, sl, #20 +10004a6c: 462a mov r2, r5 +10004a6e: 9903 ldr r1, [sp, #12] +10004a70: 4420 add r0, r4 +10004a72: f000 fff3 bl 10005a5c +10004a76: 6a63 ldr r3, [r4, #36] @ 0x24 +10004a78: 442b add r3, r5 +10004a7a: 6263 str r3, [r4, #36] @ 0x24 +10004a7c: 2000 movs r0, #0 +10004a7e: b005 add sp, #20 +10004a80: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004a84: 455d cmp r5, fp +10004a86: d3ef bcc.n 10004a68 +10004a88: f1ba 0f00 cmp.w sl, #0 +10004a8c: d130 bne.n 10004af0 +10004a8e: 2d00 cmp r5, #0 +10004a90: d0f4 beq.n 10004a7c +10004a92: fbb5 faf6 udiv sl, r5, r6 +10004a96: fb06 5a1a mls sl, r6, sl, r5 +10004a9a: f1ba 0f00 cmp.w sl, #0 +10004a9e: d1b6 bne.n 10004a0e +10004aa0: f994 1008 ldrsb.w r1, [r4, #8] +10004aa4: 2900 cmp r1, #0 +10004aa6: d1c1 bne.n 10004a2c +10004aa8: 68e3 ldr r3, [r4, #12] +10004aaa: 2b00 cmp r3, #0 +10004aac: d0be beq.n 10004a2c +10004aae: 46b2 mov sl, r6 +10004ab0: e7ad b.n 10004a0e +10004ab2: 42b5 cmp r5, r6 +10004ab4: d150 bne.n 10004b58 +10004ab6: 79ca ldrb r2, [r1, #7] +10004ab8: 4928 ldr r1, [pc, #160] @ (10004b5c ) +10004aba: f3c2 0284 ubfx r2, r2, #2, #5 +10004abe: f851 1022 ldr.w r1, [r1, r2, lsl #2] +10004ac2: f8c9 5000 str.w r5, [r9] +10004ac6: 684d ldr r5, [r1, #4] +10004ac8: 9a03 ldr r2, [sp, #12] +10004aca: 46ac mov ip, r5 +10004acc: f990 1008 ldrsb.w r1, [r0, #8] +10004ad0: 6bc0 ldr r0, [r0, #60] @ 0x3c +10004ad2: b005 add sp, #20 +10004ad4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10004ad8: 4760 bx ip +10004ada: 6a43 ldr r3, [r0, #36] @ 0x24 +10004adc: b933 cbnz r3, 10004aec +10004ade: fbb5 f3f6 udiv r3, r5, r6 +10004ae2: fb06 5313 mls r3, r6, r3, r5 +10004ae6: 2b00 cmp r3, #0 +10004ae8: f43f af76 beq.w 100049d8 +10004aec: 481c ldr r0, [pc, #112] @ (10004b60 ) +10004aee: e7c6 b.n 10004a7e +10004af0: eba6 0b0a sub.w fp, r6, sl +10004af4: f10a 0014 add.w r0, sl, #20 +10004af8: 465a mov r2, fp +10004afa: 9903 ldr r1, [sp, #12] +10004afc: 4420 add r0, r4 +10004afe: f000 ffad bl 10005a5c +10004b02: 46a4 mov ip, r4 +10004b04: f85c eb14 ldr.w lr, [ip], #20 +10004b08: 4f14 ldr r7, [pc, #80] @ (10004b5c ) +10004b0a: f89e e007 ldrb.w lr, [lr, #7] +10004b0e: f994 1008 ldrsb.w r1, [r4, #8] +10004b12: f3ce 0e84 ubfx lr, lr, #2, #5 +10004b16: f857 e02e ldr.w lr, [r7, lr, lsl #2] +10004b1a: 6be0 ldr r0, [r4, #60] @ 0x3c +10004b1c: e9cd c800 strd ip, r8, [sp] +10004b20: 4632 mov r2, r6 +10004b22: f8de 7008 ldr.w r7, [lr, #8] +10004b26: f104 0328 add.w r3, r4, #40 @ 0x28 +10004b2a: 47b8 blx r7 +10004b2c: 2800 cmp r0, #0 +10004b2e: d1a6 bne.n 10004a7e +10004b30: 9b03 ldr r3, [sp, #12] +10004b32: 44aa add sl, r5 +10004b34: 445b add r3, fp +10004b36: 9303 str r3, [sp, #12] +10004b38: f8d9 3000 ldr.w r3, [r9] +10004b3c: ebaa 0506 sub.w r5, sl, r6 +10004b40: 4433 add r3, r6 +10004b42: f8c9 3000 str.w r3, [r9] +10004b46: 44b0 add r8, r6 +10004b48: 6260 str r0, [r4, #36] @ 0x24 +10004b4a: 2d00 cmp r5, #0 +10004b4c: d1a1 bne.n 10004a92 +10004b4e: e795 b.n 10004a7c +10004b50: 4804 ldr r0, [pc, #16] @ (10004b64 ) +10004b52: e794 b.n 10004a7e +10004b54: 4804 ldr r0, [pc, #16] @ (10004b68 ) +10004b56: e792 b.n 10004a7e +10004b58: 4804 ldr r0, [pc, #16] @ (10004b6c ) +10004b5a: e790 b.n 10004a7e +10004b5c: 20000624 .word 0x20000624 +10004b60: ffff9f00 .word 0xffff9f00 +10004b64: ffff9f80 .word 0xffff9f80 +10004b68: ffff9c80 .word 0xffff9c80 +10004b6c: ffff9d80 .word 0xffff9d80 + +10004b70 : +10004b70: b510 push {r4, lr} +10004b72: 4604 mov r4, r0 +10004b74: f7fe fe66 bl 10003844 +10004b78: 4620 mov r0, r4 +10004b7a: e8bd 4010 ldmia.w sp!, {r4, lr} +10004b7e: f7fc be9d b.w 100018bc <__wrap_free> +10004b82: bf00 nop + +10004b84 : +10004b84: b510 push {r4, lr} +10004b86: f44f 718c mov.w r1, #280 @ 0x118 +10004b8a: 2001 movs r0, #1 +10004b8c: f7fc fe80 bl 10001890 <__wrap_calloc> +10004b90: 4604 mov r4, r0 +10004b92: b108 cbz r0, 10004b98 +10004b94: f7fe fe50 bl 10003838 +10004b98: 4620 mov r0, r4 +10004b9a: bd10 pop {r4, pc} + +10004b9c : +10004b9c: f7ff b96a b.w 10003e74 + +10004ba0 : +10004ba0: f7fe be56 b.w 10003850 + +10004ba4 : +10004ba4: f7ff bdfe b.w 100047a4 + +10004ba8 : +10004ba8: f7ff bdea b.w 10004780 + +10004bac : +10004bac: 2800 cmp r0, #0 +10004bae: f000 80ca beq.w 10004d46 +10004bb2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10004bb6: 6803 ldr r3, [r0, #0] +10004bb8: 4681 mov r9, r0 +10004bba: b087 sub sp, #28 +10004bbc: 2b00 cmp r3, #0 +10004bbe: f000 80c0 beq.w 10004d42 +10004bc2: 460e mov r6, r1 +10004bc4: 2900 cmp r1, #0 +10004bc6: f000 80bc beq.w 10004d42 +10004bca: f8d0 a040 ldr.w sl, [r0, #64] @ 0x40 +10004bce: f1ba 0f00 cmp.w sl, #0 +10004bd2: f000 80b6 beq.w 10004d42 +10004bd6: 791d ldrb r5, [r3, #4] +10004bd8: f8da 3020 ldr.w r3, [sl, #32] +10004bdc: 4690 mov r8, r2 +10004bde: f005 051f and.w r5, r5, #31 +10004be2: 2b00 cmp r3, #0 +10004be4: d155 bne.n 10004c92 +10004be6: f105 3bff add.w fp, r5, #4294967295 @ 0xffffffff +10004bea: 44c3 add fp, r8 +10004bec: fbbb fbf5 udiv fp, fp, r5 +10004bf0: f1bb 0f01 cmp.w fp, #1 +10004bf4: d946 bls.n 10004c84 +10004bf6: ab05 add r3, sp, #20 +10004bf8: f1aa 0404 sub.w r4, sl, #4 +10004bfc: f8cd 900c str.w r9, [sp, #12] +10004c00: 2701 movs r7, #1 +10004c02: 46d1 mov r9, sl +10004c04: 46aa mov sl, r5 +10004c06: 461d mov r5, r3 +10004c08: f1ba 0f03 cmp.w sl, #3 +10004c0c: bf98 it ls +10004c0e: f04f 0c00 movls.w ip, #0 +10004c12: d90a bls.n 10004c2a +10004c14: 2004 movs r0, #4 +10004c16: 1833 adds r3, r6, r0 +10004c18: 5822 ldr r2, [r4, r0] +10004c1a: f853 3c04 ldr.w r3, [r3, #-4] +10004c1e: 4684 mov ip, r0 +10004c20: 4053 eors r3, r2 +10004c22: 5023 str r3, [r4, r0] +10004c24: 3004 adds r0, #4 +10004c26: 4550 cmp r0, sl +10004c28: d9f5 bls.n 10004c16 +10004c2a: 45e2 cmp sl, ip +10004c2c: d91b bls.n 10004c66 +10004c2e: f819 200c ldrb.w r2, [r9, ip] +10004c32: f816 100c ldrb.w r1, [r6, ip] +10004c36: 4051 eors r1, r2 +10004c38: f10c 0201 add.w r2, ip, #1 +10004c3c: 4592 cmp sl, r2 +10004c3e: f809 100c strb.w r1, [r9, ip] +10004c42: d910 bls.n 10004c66 +10004c44: 5cb1 ldrb r1, [r6, r2] +10004c46: f819 0002 ldrb.w r0, [r9, r2] +10004c4a: f10c 0c02 add.w ip, ip, #2 +10004c4e: 4041 eors r1, r0 +10004c50: 45e2 cmp sl, ip +10004c52: f809 1002 strb.w r1, [r9, r2] +10004c56: d906 bls.n 10004c66 +10004c58: f816 200c ldrb.w r2, [r6, ip] +10004c5c: f819 100c ldrb.w r1, [r9, ip] +10004c60: 404a eors r2, r1 +10004c62: f809 200c strb.w r2, [r9, ip] +10004c66: 464b mov r3, r9 +10004c68: 4652 mov r2, sl +10004c6a: 4649 mov r1, r9 +10004c6c: 9803 ldr r0, [sp, #12] +10004c6e: 9500 str r5, [sp, #0] +10004c70: f7ff fe94 bl 1000499c +10004c74: b950 cbnz r0, 10004c8c +10004c76: 3701 adds r7, #1 +10004c78: 45bb cmp fp, r7 +10004c7a: eba8 080a sub.w r8, r8, sl +10004c7e: 4456 add r6, sl +10004c80: d1c2 bne.n 10004c08 +10004c82: 46ca mov sl, r9 +10004c84: f1b8 0f00 cmp.w r8, #0 +10004c88: d14a bne.n 10004d20 +10004c8a: 2000 movs r0, #0 +10004c8c: b007 add sp, #28 +10004c8e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004c92: 1aea subs r2, r5, r3 +10004c94: 4542 cmp r2, r8 +10004c96: d2a6 bcs.n 10004be6 +10004c98: 3310 adds r3, #16 +10004c9a: eb0a 0003 add.w r0, sl, r3 +10004c9e: f000 fedd bl 10005a5c +10004ca2: 2d03 cmp r5, #3 +10004ca4: f10a 0010 add.w r0, sl, #16 +10004ca8: d949 bls.n 10004d3e +10004caa: 2304 movs r3, #4 +10004cac: f1aa 0104 sub.w r1, sl, #4 +10004cb0: eb0a 0203 add.w r2, sl, r3 +10004cb4: 58cc ldr r4, [r1, r3] +10004cb6: 68d2 ldr r2, [r2, #12] +10004cb8: 4062 eors r2, r4 +10004cba: 50ca str r2, [r1, r3] +10004cbc: 461a mov r2, r3 +10004cbe: 3304 adds r3, #4 +10004cc0: 42ab cmp r3, r5 +10004cc2: d9f5 bls.n 10004cb0 +10004cc4: 4295 cmp r5, r2 +10004cc6: d917 bls.n 10004cf8 +10004cc8: 5c83 ldrb r3, [r0, r2] +10004cca: f81a 1002 ldrb.w r1, [sl, r2] +10004cce: 404b eors r3, r1 +10004cd0: f80a 3002 strb.w r3, [sl, r2] +10004cd4: 1c53 adds r3, r2, #1 +10004cd6: 429d cmp r5, r3 +10004cd8: d90e bls.n 10004cf8 +10004cda: 5cc1 ldrb r1, [r0, r3] +10004cdc: f81a 4003 ldrb.w r4, [sl, r3] +10004ce0: 3202 adds r2, #2 +10004ce2: 4061 eors r1, r4 +10004ce4: 42aa cmp r2, r5 +10004ce6: f80a 1003 strb.w r1, [sl, r3] +10004cea: d205 bcs.n 10004cf8 +10004cec: 5c83 ldrb r3, [r0, r2] +10004cee: f81a 1002 ldrb.w r1, [sl, r2] +10004cf2: 404b eors r3, r1 +10004cf4: f80a 3002 strb.w r3, [sl, r2] +10004cf8: ab05 add r3, sp, #20 +10004cfa: 9300 str r3, [sp, #0] +10004cfc: 462a mov r2, r5 +10004cfe: 4653 mov r3, sl +10004d00: 4651 mov r1, sl +10004d02: 4648 mov r0, r9 +10004d04: f7ff fe4a bl 1000499c +10004d08: 2800 cmp r0, #0 +10004d0a: d1bf bne.n 10004c8c +10004d0c: f8da 3020 ldr.w r3, [sl, #32] +10004d10: f8ca 0020 str.w r0, [sl, #32] +10004d14: 4498 add r8, r3 +10004d16: 1aeb subs r3, r5, r3 +10004d18: 441e add r6, r3 +10004d1a: eba8 0805 sub.w r8, r8, r5 +10004d1e: e762 b.n 10004be6 +10004d20: f8da 3020 ldr.w r3, [sl, #32] +10004d24: 4642 mov r2, r8 +10004d26: 3310 adds r3, #16 +10004d28: eb0a 0003 add.w r0, sl, r3 +10004d2c: 4631 mov r1, r6 +10004d2e: f000 fe95 bl 10005a5c +10004d32: f8da 3020 ldr.w r3, [sl, #32] +10004d36: 4443 add r3, r8 +10004d38: f8ca 3020 str.w r3, [sl, #32] +10004d3c: e7a5 b.n 10004c8a +10004d3e: 2200 movs r2, #0 +10004d40: e7c0 b.n 10004cc4 +10004d42: 4802 ldr r0, [pc, #8] @ (10004d4c ) +10004d44: e7a2 b.n 10004c8c +10004d46: 4801 ldr r0, [pc, #4] @ (10004d4c ) +10004d48: 4770 bx lr +10004d4a: bf00 nop +10004d4c: ffff9f00 .word 0xffff9f00 + +10004d50 : +10004d50: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +10004d54: b093 sub sp, #76 @ 0x4c +10004d56: 9103 str r1, [sp, #12] +10004d58: 2800 cmp r0, #0 +10004d5a: f000 8269 beq.w 10005230 +10004d5e: 6803 ldr r3, [r0, #0] +10004d60: 4606 mov r6, r0 +10004d62: 2b00 cmp r3, #0 +10004d64: f000 8264 beq.w 10005230 +10004d68: 6c05 ldr r5, [r0, #64] @ 0x40 +10004d6a: 2d00 cmp r5, #0 +10004d6c: f000 8260 beq.w 10005230 +10004d70: 2900 cmp r1, #0 +10004d72: f000 825d beq.w 10005230 +10004d76: 2110 movs r1, #16 +10004d78: a806 add r0, sp, #24 +10004d7a: 791c ldrb r4, [r3, #4] +10004d7c: f10d 0a38 add.w sl, sp, #56 @ 0x38 +10004d80: f000 fab0 bl 100052e4 +10004d84: 2110 movs r1, #16 +10004d86: a80a add r0, sp, #40 @ 0x28 +10004d88: f000 faac bl 100052e4 +10004d8c: 2110 movs r1, #16 +10004d8e: 4650 mov r0, sl +10004d90: f000 faa8 bl 100052e4 +10004d94: 6832 ldr r2, [r6, #0] +10004d96: f004 041f and.w r4, r4, #31 +10004d9a: 2a00 cmp r2, #0 +10004d9c: f000 8236 beq.w 1000520c +10004da0: f892 8004 ldrb.w r8, [r2, #4] +10004da4: f10d 0914 add.w r9, sp, #20 +10004da8: f008 081f and.w r8, r8, #31 +10004dac: 4653 mov r3, sl +10004dae: 4642 mov r2, r8 +10004db0: 4651 mov r1, sl +10004db2: 4630 mov r0, r6 +10004db4: f8cd 9000 str.w r9, [sp] +10004db8: f7ff fdf0 bl 1000499c +10004dbc: 2800 cmp r0, #0 +10004dbe: d168 bne.n 10004e92 +10004dc0: f1b8 0f10 cmp.w r8, #16 +10004dc4: d165 bne.n 10004e92 +10004dc6: 4b7e ldr r3, [pc, #504] @ (10004fc0 ) +10004dc8: f89d 1038 ldrb.w r1, [sp, #56] @ 0x38 +10004dcc: 681a ldr r2, [r3, #0] +10004dce: 9811 ldr r0, [sp, #68] @ 0x44 +10004dd0: ea82 1cd1 eor.w ip, r2, r1, lsr #7 +10004dd4: 6819 ldr r1, [r3, #0] +10004dd6: e9dd 320e ldrd r3, r2, [sp, #56] @ 0x38 +10004dda: fa93 fe83 rev.w lr, r3 +10004dde: ea4f 035c mov.w r3, ip, lsr #1 +10004de2: 425b negs r3, r3 +10004de4: f1cc 0c00 rsb ip, ip, #0 +10004de8: ea43 030c orr.w r3, r3, ip +10004dec: fa90 fc80 rev.w ip, r0 +10004df0: 17db asrs r3, r3, #31 +10004df2: ea4f 0c4c mov.w ip, ip, lsl #1 +10004df6: fa9c fc8c rev.w ip, ip +10004dfa: f003 0387 and.w r3, r3, #135 @ 0x87 +10004dfe: ea83 631c eor.w r3, r3, ip, lsr #24 +10004e02: f8cd c024 str.w ip, [sp, #36] @ 0x24 +10004e06: f3c2 1cc0 ubfx ip, r2, #7, #1 +10004e0a: ea4c 0c4e orr.w ip, ip, lr, lsl #1 +10004e0e: f88d 3027 strb.w r3, [sp, #39] @ 0x27 +10004e12: fa9c f38c rev.w r3, ip +10004e16: f3c3 1ec0 ubfx lr, r3, #7, #1 +10004e1a: 9306 str r3, [sp, #24] +10004e1c: 9b10 ldr r3, [sp, #64] @ 0x40 +10004e1e: ea8e 0e01 eor.w lr, lr, r1 +10004e22: ba12 rev r2, r2 +10004e24: fa93 f883 rev.w r8, r3 +10004e28: f3c3 13c0 ubfx r3, r3, #7, #1 +10004e2c: ea43 0342 orr.w r3, r3, r2, lsl #1 +10004e30: f3c0 10c0 ubfx r0, r0, #7, #1 +10004e34: ea4f 025e mov.w r2, lr, lsr #1 +10004e38: ea40 0048 orr.w r0, r0, r8, lsl #1 +10004e3c: f1ce 0e00 rsb lr, lr, #0 +10004e40: 4252 negs r2, r2 +10004e42: ea42 020e orr.w r2, r2, lr +10004e46: fa90 fe80 rev.w lr, r0 +10004e4a: f8cd e020 str.w lr, [sp, #32] +10004e4e: f3ce 1ec0 ubfx lr, lr, #7, #1 +10004e52: ea4e 0e43 orr.w lr, lr, r3, lsl #1 +10004e56: ba1b rev r3, r3 +10004e58: 9307 str r3, [sp, #28] +10004e5a: f3c3 13c0 ubfx r3, r3, #7, #1 +10004e5e: 9909 ldr r1, [sp, #36] @ 0x24 +10004e60: ea43 034c orr.w r3, r3, ip, lsl #1 +10004e64: ba1b rev r3, r3 +10004e66: 930a str r3, [sp, #40] @ 0x28 +10004e68: ba0b rev r3, r1 +10004e6a: 17d2 asrs r2, r2, #31 +10004e6c: 005b lsls r3, r3, #1 +10004e6e: f3c1 11c0 ubfx r1, r1, #7, #1 +10004e72: ba1b rev r3, r3 +10004e74: f002 0287 and.w r2, r2, #135 @ 0x87 +10004e78: ea41 0140 orr.w r1, r1, r0, lsl #1 +10004e7c: fa9e fe8e rev.w lr, lr +10004e80: ba09 rev r1, r1 +10004e82: ea82 6213 eor.w r2, r2, r3, lsr #24 +10004e86: 930d str r3, [sp, #52] @ 0x34 +10004e88: f8cd e02c str.w lr, [sp, #44] @ 0x2c +10004e8c: 910c str r1, [sp, #48] @ 0x30 +10004e8e: f88d 2037 strb.w r2, [sp, #55] @ 0x37 +10004e92: 2110 movs r1, #16 +10004e94: 4650 mov r0, sl +10004e96: f000 fa25 bl 100052e4 +10004e9a: f8d5 b020 ldr.w fp, [r5, #32] +10004e9e: f105 0810 add.w r8, r5, #16 +10004ea2: 45a3 cmp fp, r4 +10004ea4: f0c0 808e bcc.w 10004fc4 +10004ea8: 2c03 cmp r4, #3 +10004eaa: f240 81bc bls.w 10005226 +10004eae: 4650 mov r0, sl +10004eb0: 2204 movs r2, #4 +10004eb2: f10d 0c18 add.w ip, sp, #24 +10004eb6: 4611 mov r1, r2 +10004eb8: 442a add r2, r5 +10004eba: 68d3 ldr r3, [r2, #12] +10004ebc: f85c 2b04 ldr.w r2, [ip], #4 +10004ec0: 4053 eors r3, r2 +10004ec2: 1d0a adds r2, r1, #4 +10004ec4: 4294 cmp r4, r2 +10004ec6: f840 3b04 str.w r3, [r0], #4 +10004eca: d2f4 bcs.n 10004eb6 +10004ecc: 42a1 cmp r1, r4 +10004ece: d220 bcs.n 10004f12 +10004ed0: eb0d 0301 add.w r3, sp, r1 +10004ed4: 7e18 ldrb r0, [r3, #24] +10004ed6: f818 2001 ldrb.w r2, [r8, r1] +10004eda: 4042 eors r2, r0 +10004edc: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10004ee0: 1c4b adds r3, r1, #1 +10004ee2: 429c cmp r4, r3 +10004ee4: d912 bls.n 10004f0c +10004ee6: eb0d 0203 add.w r2, sp, r3 +10004eea: 7e10 ldrb r0, [r2, #24] +10004eec: f818 3003 ldrb.w r3, [r8, r3] +10004ef0: 3102 adds r1, #2 +10004ef2: 4043 eors r3, r0 +10004ef4: 428c cmp r4, r1 +10004ef6: f882 3038 strb.w r3, [r2, #56] @ 0x38 +10004efa: d907 bls.n 10004f0c +10004efc: eb0d 0201 add.w r2, sp, r1 +10004f00: f818 3001 ldrb.w r3, [r8, r1] +10004f04: 7e11 ldrb r1, [r2, #24] +10004f06: 404b eors r3, r1 +10004f08: f882 3038 strb.w r3, [r2, #56] @ 0x38 +10004f0c: 2c03 cmp r4, #3 +10004f0e: f240 8187 bls.w 10005220 +10004f12: 4650 mov r0, sl +10004f14: 2204 movs r2, #4 +10004f16: 1f2b subs r3, r5, #4 +10004f18: f853 c002 ldr.w ip, [r3, r2] +10004f1c: f850 1b04 ldr.w r1, [r0], #4 +10004f20: 4696 mov lr, r2 +10004f22: ea8c 0c01 eor.w ip, ip, r1 +10004f26: f843 c002 str.w ip, [r3, r2] +10004f2a: 3204 adds r2, #4 +10004f2c: 4294 cmp r4, r2 +10004f2e: d2f3 bcs.n 10004f18 +10004f30: 4574 cmp r4, lr +10004f32: d920 bls.n 10004f76 +10004f34: eb0d 030e add.w r3, sp, lr +10004f38: f815 200e ldrb.w r2, [r5, lr] +10004f3c: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 +10004f40: 4053 eors r3, r2 +10004f42: f805 300e strb.w r3, [r5, lr] +10004f46: f10e 0301 add.w r3, lr, #1 +10004f4a: 429c cmp r4, r3 +10004f4c: d913 bls.n 10004f76 +10004f4e: eb0d 0203 add.w r2, sp, r3 +10004f52: 5ce9 ldrb r1, [r5, r3] +10004f54: f892 2038 ldrb.w r2, [r2, #56] @ 0x38 +10004f58: f10e 0e02 add.w lr, lr, #2 +10004f5c: 404a eors r2, r1 +10004f5e: 4574 cmp r4, lr +10004f60: 54ea strb r2, [r5, r3] +10004f62: d908 bls.n 10004f76 +10004f64: eb0d 030e add.w r3, sp, lr +10004f68: f815 200e ldrb.w r2, [r5, lr] +10004f6c: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 +10004f70: 4053 eors r3, r2 +10004f72: f805 300e strb.w r3, [r5, lr] +10004f76: 4630 mov r0, r6 +10004f78: 462b mov r3, r5 +10004f7a: 4622 mov r2, r4 +10004f7c: 4629 mov r1, r5 +10004f7e: f8cd 9000 str.w r9, [sp] +10004f82: f7ff fd0b bl 1000499c +10004f86: 4606 mov r6, r0 +10004f88: b920 cbnz r0, 10004f94 +10004f8a: 4622 mov r2, r4 +10004f8c: 4629 mov r1, r5 +10004f8e: 9803 ldr r0, [sp, #12] +10004f90: f000 fd64 bl 10005a5c +10004f94: 2110 movs r1, #16 +10004f96: a806 add r0, sp, #24 +10004f98: f000 f9a4 bl 100052e4 +10004f9c: 2110 movs r1, #16 +10004f9e: a80a add r0, sp, #40 @ 0x28 +10004fa0: f000 f9a0 bl 100052e4 +10004fa4: 2300 movs r3, #0 +10004fa6: 2110 movs r1, #16 +10004fa8: 4640 mov r0, r8 +10004faa: 622b str r3, [r5, #32] +10004fac: f000 f99a bl 100052e4 +10004fb0: 2110 movs r1, #16 +10004fb2: 4628 mov r0, r5 +10004fb4: f000 f996 bl 100052e4 +10004fb8: 4630 mov r0, r6 +10004fba: b013 add sp, #76 @ 0x4c +10004fbc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10004fc0: 2000310c .word 0x2000310c +10004fc4: f1bb 0f00 cmp.w fp, #0 +10004fc8: f040 80d7 bne.w 1000517a +10004fcc: 2380 movs r3, #128 @ 0x80 +10004fce: 2c01 cmp r4, #1 +10004fd0: f88d 3038 strb.w r3, [sp, #56] @ 0x38 +10004fd4: f000 8118 beq.w 10005208 +10004fd8: 2301 movs r3, #1 +10004fda: 2200 movs r2, #0 +10004fdc: 446b add r3, sp +10004fde: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10004fe2: f10b 0302 add.w r3, fp, #2 +10004fe6: 429c cmp r4, r3 +10004fe8: f240 80d8 bls.w 1000519c +10004fec: ebab 0103 sub.w r1, fp, r3 +10004ff0: fab1 f181 clz r1, r1 +10004ff4: f10b 0203 add.w r2, fp, #3 +10004ff8: 0949 lsrs r1, r1, #5 +10004ffa: 446b add r3, sp +10004ffc: 01c9 lsls r1, r1, #7 +10004ffe: 4294 cmp r4, r2 +10005000: f883 1038 strb.w r1, [r3, #56] @ 0x38 +10005004: f240 80ca bls.w 1000519c +10005008: ebab 0102 sub.w r1, fp, r2 +1000500c: fab1 f181 clz r1, r1 +10005010: f10b 0304 add.w r3, fp, #4 +10005014: 0949 lsrs r1, r1, #5 +10005016: eb0d 020b add.w r2, sp, fp +1000501a: 01c9 lsls r1, r1, #7 +1000501c: 429c cmp r4, r3 +1000501e: f882 103b strb.w r1, [r2, #59] @ 0x3b +10005022: f240 80bd bls.w 100051a0 +10005026: ebab 0103 sub.w r1, fp, r3 +1000502a: fab1 f181 clz r1, r1 +1000502e: f10b 0205 add.w r2, fp, #5 +10005032: 0949 lsrs r1, r1, #5 +10005034: eb0d 030b add.w r3, sp, fp +10005038: 01c9 lsls r1, r1, #7 +1000503a: 4294 cmp r4, r2 +1000503c: f883 103c strb.w r1, [r3, #60] @ 0x3c +10005040: f240 80ae bls.w 100051a0 +10005044: ebab 0102 sub.w r1, fp, r2 +10005048: fab1 f181 clz r1, r1 +1000504c: f10b 0306 add.w r3, fp, #6 +10005050: 0949 lsrs r1, r1, #5 +10005052: eb0d 020b add.w r2, sp, fp +10005056: 01c9 lsls r1, r1, #7 +10005058: 429c cmp r4, r3 +1000505a: f882 103d strb.w r1, [r2, #61] @ 0x3d +1000505e: f240 809f bls.w 100051a0 +10005062: ebab 0103 sub.w r1, fp, r3 +10005066: fab1 f181 clz r1, r1 +1000506a: f10b 0207 add.w r2, fp, #7 +1000506e: 0949 lsrs r1, r1, #5 +10005070: eb0d 030b add.w r3, sp, fp +10005074: 01c9 lsls r1, r1, #7 +10005076: 4294 cmp r4, r2 +10005078: f883 103e strb.w r1, [r3, #62] @ 0x3e +1000507c: f240 8090 bls.w 100051a0 +10005080: ebab 0102 sub.w r1, fp, r2 +10005084: fab1 f181 clz r1, r1 +10005088: f10b 0308 add.w r3, fp, #8 +1000508c: 0949 lsrs r1, r1, #5 +1000508e: eb0d 020b add.w r2, sp, fp +10005092: 01c9 lsls r1, r1, #7 +10005094: 429c cmp r4, r3 +10005096: f882 103f strb.w r1, [r2, #63] @ 0x3f +1000509a: f240 8081 bls.w 100051a0 +1000509e: ebab 0103 sub.w r1, fp, r3 +100050a2: fab1 f181 clz r1, r1 +100050a6: f10b 0209 add.w r2, fp, #9 +100050aa: 0949 lsrs r1, r1, #5 +100050ac: eb0d 030b add.w r3, sp, fp +100050b0: 01c9 lsls r1, r1, #7 +100050b2: 42a2 cmp r2, r4 +100050b4: f883 1040 strb.w r1, [r3, #64] @ 0x40 +100050b8: d272 bcs.n 100051a0 +100050ba: ebab 0102 sub.w r1, fp, r2 +100050be: fab1 f181 clz r1, r1 +100050c2: f10b 030a add.w r3, fp, #10 +100050c6: 0949 lsrs r1, r1, #5 +100050c8: eb0d 020b add.w r2, sp, fp +100050cc: 01c9 lsls r1, r1, #7 +100050ce: 42a3 cmp r3, r4 +100050d0: f882 1041 strb.w r1, [r2, #65] @ 0x41 +100050d4: d264 bcs.n 100051a0 +100050d6: ebab 0103 sub.w r1, fp, r3 +100050da: fab1 f181 clz r1, r1 +100050de: f10b 020b add.w r2, fp, #11 +100050e2: 0949 lsrs r1, r1, #5 +100050e4: eb0d 030b add.w r3, sp, fp +100050e8: 01c9 lsls r1, r1, #7 +100050ea: 4294 cmp r4, r2 +100050ec: f883 1042 strb.w r1, [r3, #66] @ 0x42 +100050f0: d956 bls.n 100051a0 +100050f2: ebab 0102 sub.w r1, fp, r2 +100050f6: fab1 f181 clz r1, r1 +100050fa: f10b 030c add.w r3, fp, #12 +100050fe: 0949 lsrs r1, r1, #5 +10005100: eb0d 020b add.w r2, sp, fp +10005104: 01c9 lsls r1, r1, #7 +10005106: 429c cmp r4, r3 +10005108: f882 1043 strb.w r1, [r2, #67] @ 0x43 +1000510c: d948 bls.n 100051a0 +1000510e: ebab 0103 sub.w r1, fp, r3 +10005112: fab1 f181 clz r1, r1 +10005116: f10b 020d add.w r2, fp, #13 +1000511a: 0949 lsrs r1, r1, #5 +1000511c: eb0d 030b add.w r3, sp, fp +10005120: 01c9 lsls r1, r1, #7 +10005122: 4294 cmp r4, r2 +10005124: f883 1044 strb.w r1, [r3, #68] @ 0x44 +10005128: d93a bls.n 100051a0 +1000512a: ebab 0102 sub.w r1, fp, r2 +1000512e: fab1 f181 clz r1, r1 +10005132: f10b 030e add.w r3, fp, #14 +10005136: 0949 lsrs r1, r1, #5 +10005138: eb0d 020b add.w r2, sp, fp +1000513c: 01c9 lsls r1, r1, #7 +1000513e: 429c cmp r4, r3 +10005140: f882 1045 strb.w r1, [r2, #69] @ 0x45 +10005144: d92c bls.n 100051a0 +10005146: ebab 0203 sub.w r2, fp, r3 +1000514a: f1bb 0f00 cmp.w fp, #0 +1000514e: fab2 f282 clz r2, r2 +10005152: bf0c ite eq +10005154: 210f moveq r1, #15 +10005156: 2110 movne r1, #16 +10005158: 0952 lsrs r2, r2, #5 +1000515a: eb0d 030b add.w r3, sp, fp +1000515e: 01d2 lsls r2, r2, #7 +10005160: 428c cmp r4, r1 +10005162: f883 2046 strb.w r2, [r3, #70] @ 0x46 +10005166: d91b bls.n 100051a0 +10005168: f1ab 030f sub.w r3, fp, #15 +1000516c: fab3 f383 clz r3, r3 +10005170: 095b lsrs r3, r3, #5 +10005172: 01db lsls r3, r3, #7 +10005174: f88d 3047 strb.w r3, [sp, #71] @ 0x47 +10005178: e012 b.n 100051a0 +1000517a: 465a mov r2, fp +1000517c: 4641 mov r1, r8 +1000517e: 4650 mov r0, sl +10005180: f000 fc6c bl 10005a5c +10005184: 45a3 cmp fp, r4 +10005186: d209 bcs.n 1000519c +10005188: 2280 movs r2, #128 @ 0x80 +1000518a: eb0d 030b add.w r3, sp, fp +1000518e: f883 2038 strb.w r2, [r3, #56] @ 0x38 +10005192: f10b 0301 add.w r3, fp, #1 +10005196: 42a3 cmp r3, r4 +10005198: f4ff af1f bcc.w 10004fda +1000519c: 2c03 cmp r4, #3 +1000519e: d933 bls.n 10005208 +100051a0: 4652 mov r2, sl +100051a2: 2304 movs r3, #4 +100051a4: a80a add r0, sp, #40 @ 0x28 +100051a6: 4619 mov r1, r3 +100051a8: 6817 ldr r7, [r2, #0] +100051aa: f850 3b04 ldr.w r3, [r0], #4 +100051ae: 407b eors r3, r7 +100051b0: f842 3b04 str.w r3, [r2], #4 +100051b4: 1d0b adds r3, r1, #4 +100051b6: 429c cmp r4, r3 +100051b8: d2f5 bcs.n 100051a6 +100051ba: 428c cmp r4, r1 +100051bc: f67f aea9 bls.w 10004f12 +100051c0: eb0d 0301 add.w r3, sp, r1 +100051c4: f81a 2001 ldrb.w r2, [sl, r1] +100051c8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 +100051cc: 4053 eors r3, r2 +100051ce: f80a 3001 strb.w r3, [sl, r1] +100051d2: 1c4b adds r3, r1, #1 +100051d4: 429c cmp r4, r3 +100051d6: f67f ae99 bls.w 10004f0c +100051da: eb0d 0203 add.w r2, sp, r3 +100051de: f81a 0003 ldrb.w r0, [sl, r3] +100051e2: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 +100051e6: 3102 adds r1, #2 +100051e8: 4042 eors r2, r0 +100051ea: 428c cmp r4, r1 +100051ec: f80a 2003 strb.w r2, [sl, r3] +100051f0: f67f ae8c bls.w 10004f0c +100051f4: eb0d 0301 add.w r3, sp, r1 +100051f8: f81a 2001 ldrb.w r2, [sl, r1] +100051fc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 +10005200: 4053 eors r3, r2 +10005202: f80a 3001 strb.w r3, [sl, r1] +10005206: e681 b.n 10004f0c +10005208: 2100 movs r1, #0 +1000520a: e7d9 b.n 100051c0 +1000520c: f10d 0914 add.w r9, sp, #20 +10005210: 4653 mov r3, sl +10005212: 4651 mov r1, sl +10005214: 4630 mov r0, r6 +10005216: f8cd 9000 str.w r9, [sp] +1000521a: f7ff fbbf bl 1000499c +1000521e: e638 b.n 10004e92 +10005220: f04f 0e00 mov.w lr, #0 +10005224: e686 b.n 10004f34 +10005226: 2c00 cmp r4, #0 +10005228: f43f aea5 beq.w 10004f76 +1000522c: 2100 movs r1, #0 +1000522e: e64f b.n 10004ed0 +10005230: 4e00 ldr r6, [pc, #0] @ (10005234 ) +10005232: e6c1 b.n 10004fb8 +10005234: ffff9f00 .word 0xffff9f00 + +10005238 : +10005238: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +1000523c: b092 sub sp, #72 @ 0x48 +1000523e: 9d19 ldr r5, [sp, #100] @ 0x64 +10005240: 2800 cmp r0, #0 +10005242: d046 beq.n 100052d2 +10005244: 460e mov r6, r1 +10005246: 2900 cmp r1, #0 +10005248: d043 beq.n 100052d2 +1000524a: 461f mov r7, r3 +1000524c: 2b00 cmp r3, #0 +1000524e: d040 beq.n 100052d2 +10005250: 2d00 cmp r5, #0 +10005252: d03e beq.n 100052d2 +10005254: 4604 mov r4, r0 +10005256: a801 add r0, sp, #4 +10005258: 4690 mov r8, r2 +1000525a: f7ff fb29 bl 100048b0 +1000525e: 4621 mov r1, r4 +10005260: a801 add r0, sp, #4 +10005262: f7ff fb45 bl 100048f0 +10005266: 4604 mov r4, r0 +10005268: b130 cbz r0, 10005278 +1000526a: a801 add r0, sp, #4 +1000526c: f7ff fb24 bl 100048b8 +10005270: 4620 mov r0, r4 +10005272: b012 add sp, #72 @ 0x48 +10005274: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +10005278: 9b01 ldr r3, [sp, #4] +1000527a: b343 cbz r3, 100052ce +1000527c: 4642 mov r2, r8 +1000527e: 4631 mov r1, r6 +10005280: 2301 movs r3, #1 +10005282: a801 add r0, sp, #4 +10005284: f7ff fb54 bl 10004930 +10005288: 4604 mov r4, r0 +1000528a: 2800 cmp r0, #0 +1000528c: d1ed bne.n 1000526a +1000528e: 9b01 ldr r3, [sp, #4] +10005290: b1eb cbz r3, 100052ce +10005292: 799b ldrb r3, [r3, #6] +10005294: 2b04 cmp r3, #4 +10005296: d918 bls.n 100052ca +10005298: 2b24 cmp r3, #36 @ 0x24 +1000529a: d118 bne.n 100052ce +1000529c: 2124 movs r1, #36 @ 0x24 +1000529e: 2001 movs r0, #1 +100052a0: f7fc faf6 bl 10001890 <__wrap_calloc> +100052a4: b1b8 cbz r0, 100052d6 +100052a6: 2110 movs r1, #16 +100052a8: 9011 str r0, [sp, #68] @ 0x44 +100052aa: f000 f81b bl 100052e4 +100052ae: 4639 mov r1, r7 +100052b0: 9a18 ldr r2, [sp, #96] @ 0x60 +100052b2: a801 add r0, sp, #4 +100052b4: f7ff fc7a bl 10004bac +100052b8: 4604 mov r4, r0 +100052ba: 2800 cmp r0, #0 +100052bc: d1d5 bne.n 1000526a +100052be: 4629 mov r1, r5 +100052c0: a801 add r0, sp, #4 +100052c2: f7ff fd45 bl 10004d50 +100052c6: 4604 mov r4, r0 +100052c8: e7cf b.n 1000526a +100052ca: 2b01 cmp r3, #1 +100052cc: d8e6 bhi.n 1000529c +100052ce: 4c03 ldr r4, [pc, #12] @ (100052dc ) +100052d0: e7cb b.n 1000526a +100052d2: 4c02 ldr r4, [pc, #8] @ (100052dc ) +100052d4: e7cc b.n 10005270 +100052d6: 4c02 ldr r4, [pc, #8] @ (100052e0 ) +100052d8: e7c7 b.n 1000526a +100052da: bf00 nop +100052dc: ffff9f00 .word 0xffff9f00 +100052e0: ffff9e80 .word 0xffff9e80 + +100052e4 : +100052e4: b139 cbz r1, 100052f6 +100052e6: 4b04 ldr r3, [pc, #16] @ (100052f8 ) +100052e8: 460a mov r2, r1 +100052ea: b510 push {r4, lr} +100052ec: 2100 movs r1, #0 +100052ee: 681b ldr r3, [r3, #0] +100052f0: 4604 mov r4, r0 +100052f2: 4798 blx r3 +100052f4: bd10 pop {r4, pc} +100052f6: 4770 bx lr +100052f8: 100061bc .word 0x100061bc + +100052fc : +100052fc: b510 push {r4, lr} +100052fe: 4604 mov r4, r0 +10005300: b128 cbz r0, 1000530e +10005302: b121 cbz r1, 1000530e +10005304: 4b04 ldr r3, [pc, #16] @ (10005318 ) +10005306: 460a mov r2, r1 +10005308: 681b ldr r3, [r3, #0] +1000530a: 2100 movs r1, #0 +1000530c: 4798 blx r3 +1000530e: 4620 mov r0, r4 +10005310: e8bd 4010 ldmia.w sp!, {r4, lr} +10005314: f7fc bad2 b.w 100018bc <__wrap_free> +10005318: 100061bc .word 0x100061bc + +1000531c <_retrieve_unique_id_on_boot>: +1000531c: b500 push {lr} +1000531e: f245 3047 movw r0, #21319 @ 0x5347 +10005322: b08b sub sp, #44 @ 0x2c +10005324: f7fb fffe bl 10001324 +10005328: 2201 movs r2, #1 +1000532a: 4603 mov r3, r0 +1000532c: 2109 movs r1, #9 +1000532e: a801 add r0, sp, #4 +10005330: 4798 blx r3 +10005332: e9dd 3203 ldrd r3, r2, [sp, #12] +10005336: 4904 ldr r1, [pc, #16] @ (10005348 <_retrieve_unique_id_on_boot+0x2c>) +10005338: ba12 rev r2, r2 +1000533a: ba1b rev r3, r3 +1000533c: e9c1 2300 strd r2, r3, [r1] +10005340: b00b add sp, #44 @ 0x2c +10005342: f85d fb04 ldr.w pc, [sp], #4 +10005346: bf00 nop +10005348: 20003148 .word 0x20003148 + +1000534c : +1000534c: 4b02 ldr r3, [pc, #8] @ (10005358 ) +1000534e: 460a mov r2, r1 +10005350: 4601 mov r1, r0 +10005352: 6818 ldr r0, [r3, #0] +10005354: f000 b802 b.w 1000535c <_calloc_r> +10005358: 20000a38 .word 0x20000a38 + +1000535c <_calloc_r>: +1000535c: b538 push {r3, r4, r5, lr} +1000535e: fba1 1402 umull r1, r4, r1, r2 +10005362: bb34 cbnz r4, 100053b2 <_calloc_r+0x56> +10005364: f000 f83a bl 100053dc <_malloc_r> +10005368: 4605 mov r5, r0 +1000536a: b330 cbz r0, 100053ba <_calloc_r+0x5e> +1000536c: f850 2c04 ldr.w r2, [r0, #-4] +10005370: f022 0203 bic.w r2, r2, #3 +10005374: 3a04 subs r2, #4 +10005376: 2a24 cmp r2, #36 @ 0x24 +10005378: d80c bhi.n 10005394 <_calloc_r+0x38> +1000537a: 2a13 cmp r2, #19 +1000537c: d90f bls.n 1000539e <_calloc_r+0x42> +1000537e: 2a1b cmp r2, #27 +10005380: e9c0 4400 strd r4, r4, [r0] +10005384: d912 bls.n 100053ac <_calloc_r+0x50> +10005386: 2a24 cmp r2, #36 @ 0x24 +10005388: e9c0 4402 strd r4, r4, [r0, #8] +1000538c: d018 beq.n 100053c0 <_calloc_r+0x64> +1000538e: f100 0210 add.w r2, r0, #16 +10005392: e005 b.n 100053a0 <_calloc_r+0x44> +10005394: 4621 mov r1, r4 +10005396: f000 fae9 bl 1000596c +1000539a: 4628 mov r0, r5 +1000539c: bd38 pop {r3, r4, r5, pc} +1000539e: 4602 mov r2, r0 +100053a0: 2300 movs r3, #0 +100053a2: 4628 mov r0, r5 +100053a4: e9c2 3300 strd r3, r3, [r2] +100053a8: 6093 str r3, [r2, #8] +100053aa: bd38 pop {r3, r4, r5, pc} +100053ac: f100 0208 add.w r2, r0, #8 +100053b0: e7f6 b.n 100053a0 <_calloc_r+0x44> +100053b2: f000 fb3b bl 10005a2c <__errno> +100053b6: 230c movs r3, #12 +100053b8: 6003 str r3, [r0, #0] +100053ba: 2500 movs r5, #0 +100053bc: 4628 mov r0, r5 +100053be: bd38 pop {r3, r4, r5, pc} +100053c0: f100 0218 add.w r2, r0, #24 +100053c4: e9c0 4404 strd r4, r4, [r0, #16] +100053c8: e7ea b.n 100053a0 <_calloc_r+0x44> +100053ca: bf00 nop + +100053cc : +100053cc: 4b02 ldr r3, [pc, #8] @ (100053d8 ) +100053ce: 4601 mov r1, r0 +100053d0: 6818 ldr r0, [r3, #0] +100053d2: f000 bc43 b.w 10005c5c <_free_r> +100053d6: bf00 nop +100053d8: 20000a38 .word 0x20000a38 + +100053dc <_malloc_r>: +100053dc: f101 030b add.w r3, r1, #11 +100053e0: 2b16 cmp r3, #22 +100053e2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +100053e6: 4607 mov r7, r0 +100053e8: b083 sub sp, #12 +100053ea: d823 bhi.n 10005434 <_malloc_r+0x58> +100053ec: 2910 cmp r1, #16 +100053ee: f200 80af bhi.w 10005550 <_malloc_r+0x174> +100053f2: f000 faaf bl 10005954 <__malloc_lock> +100053f6: 2510 movs r5, #16 +100053f8: 2318 movs r3, #24 +100053fa: 2002 movs r0, #2 +100053fc: 4eba ldr r6, [pc, #744] @ (100056e8 <_malloc_r+0x30c>) +100053fe: 4433 add r3, r6 +10005400: 685c ldr r4, [r3, #4] +10005402: f1a3 0208 sub.w r2, r3, #8 +10005406: 4294 cmp r4, r2 +10005408: f000 8156 beq.w 100056b8 <_malloc_r+0x2dc> +1000540c: 6863 ldr r3, [r4, #4] +1000540e: 4638 mov r0, r7 +10005410: f023 0303 bic.w r3, r3, #3 +10005414: e9d4 1202 ldrd r1, r2, [r4, #8] +10005418: 4423 add r3, r4 +1000541a: 60ca str r2, [r1, #12] +1000541c: 6091 str r1, [r2, #8] +1000541e: 685a ldr r2, [r3, #4] +10005420: 3408 adds r4, #8 +10005422: f042 0201 orr.w r2, r2, #1 +10005426: 605a str r2, [r3, #4] +10005428: f000 fa9a bl 10005960 <__malloc_unlock> +1000542c: 4620 mov r0, r4 +1000542e: b003 add sp, #12 +10005430: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +10005434: 2b00 cmp r3, #0 +10005436: f023 0507 bic.w r5, r3, #7 +1000543a: f2c0 8089 blt.w 10005550 <_malloc_r+0x174> +1000543e: 42a9 cmp r1, r5 +10005440: f200 8086 bhi.w 10005550 <_malloc_r+0x174> +10005444: f000 fa86 bl 10005954 <__malloc_lock> +10005448: f5b5 7ffc cmp.w r5, #504 @ 0x1f8 +1000544c: f0c0 827b bcc.w 10005946 <_malloc_r+0x56a> +10005450: 0a6b lsrs r3, r5, #9 +10005452: f000 8084 beq.w 1000555e <_malloc_r+0x182> +10005456: 2b04 cmp r3, #4 +10005458: f200 8162 bhi.w 10005720 <_malloc_r+0x344> +1000545c: 09ab lsrs r3, r5, #6 +1000545e: f103 0039 add.w r0, r3, #57 @ 0x39 +10005462: f103 0e38 add.w lr, r3, #56 @ 0x38 +10005466: 00c3 lsls r3, r0, #3 +10005468: 4e9f ldr r6, [pc, #636] @ (100056e8 <_malloc_r+0x30c>) +1000546a: 4433 add r3, r6 +1000546c: f1a3 0c08 sub.w ip, r3, #8 +10005470: 685c ldr r4, [r3, #4] +10005472: 45a4 cmp ip, r4 +10005474: d107 bne.n 10005486 <_malloc_r+0xaa> +10005476: e00d b.n 10005494 <_malloc_r+0xb8> +10005478: 2a00 cmp r2, #0 +1000547a: 68e1 ldr r1, [r4, #12] +1000547c: f280 8116 bge.w 100056ac <_malloc_r+0x2d0> +10005480: 458c cmp ip, r1 +10005482: 460c mov r4, r1 +10005484: d006 beq.n 10005494 <_malloc_r+0xb8> +10005486: 6863 ldr r3, [r4, #4] +10005488: f023 0303 bic.w r3, r3, #3 +1000548c: 1b5a subs r2, r3, r5 +1000548e: 2a0f cmp r2, #15 +10005490: ddf2 ble.n 10005478 <_malloc_r+0x9c> +10005492: 4670 mov r0, lr +10005494: f8df 8268 ldr.w r8, [pc, #616] @ 10005700 <_malloc_r+0x324> +10005498: 6934 ldr r4, [r6, #16] +1000549a: 4544 cmp r4, r8 +1000549c: f000 80f2 beq.w 10005684 <_malloc_r+0x2a8> +100054a0: 6863 ldr r3, [r4, #4] +100054a2: f023 0c03 bic.w ip, r3, #3 +100054a6: ebac 0305 sub.w r3, ip, r5 +100054aa: 2b0f cmp r3, #15 +100054ac: f300 8174 bgt.w 10005798 <_malloc_r+0x3bc> +100054b0: 2b00 cmp r3, #0 +100054b2: e9c6 8804 strd r8, r8, [r6, #16] +100054b6: f280 8163 bge.w 10005780 <_malloc_r+0x3a4> +100054ba: f5bc 7f00 cmp.w ip, #512 @ 0x200 +100054be: f8d6 e004 ldr.w lr, [r6, #4] +100054c2: f080 80ff bcs.w 100056c4 <_malloc_r+0x2e8> +100054c6: ea4f 03dc mov.w r3, ip, lsr #3 +100054ca: 2201 movs r2, #1 +100054cc: ea4f 1c5c mov.w ip, ip, lsr #5 +100054d0: 3301 adds r3, #1 +100054d2: fa02 f20c lsl.w r2, r2, ip +100054d6: f856 1033 ldr.w r1, [r6, r3, lsl #3] +100054da: ea4e 0e02 orr.w lr, lr, r2 +100054de: eb06 02c3 add.w r2, r6, r3, lsl #3 +100054e2: 3a08 subs r2, #8 +100054e4: f8c6 e004 str.w lr, [r6, #4] +100054e8: e9c4 1202 strd r1, r2, [r4, #8] +100054ec: f846 4033 str.w r4, [r6, r3, lsl #3] +100054f0: 60cc str r4, [r1, #12] +100054f2: 1083 asrs r3, r0, #2 +100054f4: f04f 0c01 mov.w ip, #1 +100054f8: fa0c fc03 lsl.w ip, ip, r3 +100054fc: 45f4 cmp ip, lr +100054fe: d834 bhi.n 1000556a <_malloc_r+0x18e> +10005500: ea1c 0f0e tst.w ip, lr +10005504: d107 bne.n 10005516 <_malloc_r+0x13a> +10005506: f020 0003 bic.w r0, r0, #3 +1000550a: ea4f 0c4c mov.w ip, ip, lsl #1 +1000550e: 3004 adds r0, #4 +10005510: ea1c 0f0e tst.w ip, lr +10005514: d0f9 beq.n 1000550a <_malloc_r+0x12e> +10005516: eb06 0ac0 add.w sl, r6, r0, lsl #3 +1000551a: 4681 mov r9, r0 +1000551c: 46d6 mov lr, sl +1000551e: f8de 300c ldr.w r3, [lr, #12] +10005522: e00b b.n 1000553c <_malloc_r+0x160> +10005524: 685a ldr r2, [r3, #4] +10005526: 461c mov r4, r3 +10005528: 68db ldr r3, [r3, #12] +1000552a: f022 0203 bic.w r2, r2, #3 +1000552e: 1b51 subs r1, r2, r5 +10005530: 290f cmp r1, #15 +10005532: f300 8101 bgt.w 10005738 <_malloc_r+0x35c> +10005536: 2900 cmp r1, #0 +10005538: f280 8115 bge.w 10005766 <_malloc_r+0x38a> +1000553c: 459e cmp lr, r3 +1000553e: d1f1 bne.n 10005524 <_malloc_r+0x148> +10005540: f109 0901 add.w r9, r9, #1 +10005544: f10e 0e08 add.w lr, lr, #8 +10005548: f019 0f03 tst.w r9, #3 +1000554c: d1e7 bne.n 1000551e <_malloc_r+0x142> +1000554e: e158 b.n 10005802 <_malloc_r+0x426> +10005550: 230c movs r3, #12 +10005552: 603b str r3, [r7, #0] +10005554: 2400 movs r4, #0 +10005556: 4620 mov r0, r4 +10005558: b003 add sp, #12 +1000555a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +1000555e: f44f 7300 mov.w r3, #512 @ 0x200 +10005562: 2040 movs r0, #64 @ 0x40 +10005564: f04f 0e3f mov.w lr, #63 @ 0x3f +10005568: e77e b.n 10005468 <_malloc_r+0x8c> +1000556a: 68b4 ldr r4, [r6, #8] +1000556c: 6863 ldr r3, [r4, #4] +1000556e: f023 0903 bic.w r9, r3, #3 +10005572: 45a9 cmp r9, r5 +10005574: eba9 0305 sub.w r3, r9, r5 +10005578: d302 bcc.n 10005580 <_malloc_r+0x1a4> +1000557a: 2b0f cmp r3, #15 +1000557c: f300 8085 bgt.w 1000568a <_malloc_r+0x2ae> +10005580: 4b5a ldr r3, [pc, #360] @ (100056ec <_malloc_r+0x310>) +10005582: 2008 movs r0, #8 +10005584: 681b ldr r3, [r3, #0] +10005586: f103 0810 add.w r8, r3, #16 +1000558a: eb04 0309 add.w r3, r4, r9 +1000558e: 9300 str r3, [sp, #0] +10005590: f000 fa52 bl 10005a38 +10005594: 4a56 ldr r2, [pc, #344] @ (100056f0 <_malloc_r+0x314>) +10005596: 44a8 add r8, r5 +10005598: 4683 mov fp, r0 +1000559a: 6813 ldr r3, [r2, #0] +1000559c: 3301 adds r3, #1 +1000559e: d005 beq.n 100055ac <_malloc_r+0x1d0> +100055a0: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff +100055a4: 4243 negs r3, r0 +100055a6: 4480 add r8, r0 +100055a8: ea03 0808 and.w r8, r3, r8 +100055ac: 4641 mov r1, r8 +100055ae: 4638 mov r0, r7 +100055b0: f000 fa2a bl 10005a08 <_sbrk_r> +100055b4: f1b0 3fff cmp.w r0, #4294967295 @ 0xffffffff +100055b8: 4682 mov sl, r0 +100055ba: 4a4d ldr r2, [pc, #308] @ (100056f0 <_malloc_r+0x314>) +100055bc: f000 8107 beq.w 100057ce <_malloc_r+0x3f2> +100055c0: eb04 0309 add.w r3, r4, r9 +100055c4: 4283 cmp r3, r0 +100055c6: f200 8100 bhi.w 100057ca <_malloc_r+0x3ee> +100055ca: 4b4a ldr r3, [pc, #296] @ (100056f4 <_malloc_r+0x318>) +100055cc: f10b 3cff add.w ip, fp, #4294967295 @ 0xffffffff +100055d0: 6818 ldr r0, [r3, #0] +100055d2: 4440 add r0, r8 +100055d4: 6018 str r0, [r3, #0] +100055d6: f000 8164 beq.w 100058a2 <_malloc_r+0x4c6> +100055da: 6811 ldr r1, [r2, #0] +100055dc: 3101 adds r1, #1 +100055de: f000 816c beq.w 100058ba <_malloc_r+0x4de> +100055e2: eb04 0209 add.w r2, r4, r9 +100055e6: ebaa 0202 sub.w r2, sl, r2 +100055ea: 4402 add r2, r0 +100055ec: 601a str r2, [r3, #0] +100055ee: f01a 0207 ands.w r2, sl, #7 +100055f2: e9cd 2300 strd r2, r3, [sp] +100055f6: f000 8127 beq.w 10005848 <_malloc_r+0x46c> +100055fa: f1c2 0208 rsb r2, r2, #8 +100055fe: 4638 mov r0, r7 +10005600: 4492 add sl, r2 +10005602: 445a add r2, fp +10005604: 44d0 add r8, sl +10005606: ea08 010c and.w r1, r8, ip +1000560a: 1a52 subs r2, r2, r1 +1000560c: ea02 0b0c and.w fp, r2, ip +10005610: 4659 mov r1, fp +10005612: f000 f9f9 bl 10005a08 <_sbrk_r> +10005616: 1c42 adds r2, r0, #1 +10005618: 9b01 ldr r3, [sp, #4] +1000561a: f000 816a beq.w 100058f2 <_malloc_r+0x516> +1000561e: eba0 000a sub.w r0, r0, sl +10005622: eb00 080b add.w r8, r0, fp +10005626: 6818 ldr r0, [r3, #0] +10005628: f048 0201 orr.w r2, r8, #1 +1000562c: 42b4 cmp r4, r6 +1000562e: f8c6 a008 str.w sl, [r6, #8] +10005632: 4458 add r0, fp +10005634: f8ca 2004 str.w r2, [sl, #4] +10005638: 6018 str r0, [r3, #0] +1000563a: d017 beq.n 1000566c <_malloc_r+0x290> +1000563c: f1b9 0f0f cmp.w r9, #15 +10005640: f240 813e bls.w 100058c0 <_malloc_r+0x4e4> +10005644: 6861 ldr r1, [r4, #4] +10005646: f1a9 020c sub.w r2, r9, #12 +1000564a: f04f 0c05 mov.w ip, #5 +1000564e: f022 0207 bic.w r2, r2, #7 +10005652: f001 0101 and.w r1, r1, #1 +10005656: 4311 orrs r1, r2 +10005658: 2a0f cmp r2, #15 +1000565a: 6061 str r1, [r4, #4] +1000565c: eb04 0102 add.w r1, r4, r2 +10005660: e9c1 cc01 strd ip, ip, [r1, #4] +10005664: f200 814d bhi.w 10005902 <_malloc_r+0x526> +10005668: f8da 2004 ldr.w r2, [sl, #4] +1000566c: 4b22 ldr r3, [pc, #136] @ (100056f8 <_malloc_r+0x31c>) +1000566e: 4654 mov r4, sl +10005670: 6819 ldr r1, [r3, #0] +10005672: 4281 cmp r1, r0 +10005674: bf38 it cc +10005676: 6018 strcc r0, [r3, #0] +10005678: 4b20 ldr r3, [pc, #128] @ (100056fc <_malloc_r+0x320>) +1000567a: 6819 ldr r1, [r3, #0] +1000567c: 4281 cmp r1, r0 +1000567e: bf38 it cc +10005680: 6018 strcc r0, [r3, #0] +10005682: e0a6 b.n 100057d2 <_malloc_r+0x3f6> +10005684: f8d6 e004 ldr.w lr, [r6, #4] +10005688: e733 b.n 100054f2 <_malloc_r+0x116> +1000568a: 1962 adds r2, r4, r5 +1000568c: f045 0501 orr.w r5, r5, #1 +10005690: f043 0301 orr.w r3, r3, #1 +10005694: 3408 adds r4, #8 +10005696: f844 5c04 str.w r5, [r4, #-4] +1000569a: 4638 mov r0, r7 +1000569c: 60b2 str r2, [r6, #8] +1000569e: 6053 str r3, [r2, #4] +100056a0: f000 f95e bl 10005960 <__malloc_unlock> +100056a4: 4620 mov r0, r4 +100056a6: b003 add sp, #12 +100056a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +100056ac: 68a2 ldr r2, [r4, #8] +100056ae: 4423 add r3, r4 +100056b0: 4638 mov r0, r7 +100056b2: 60d1 str r1, [r2, #12] +100056b4: 608a str r2, [r1, #8] +100056b6: e6b2 b.n 1000541e <_malloc_r+0x42> +100056b8: 68dc ldr r4, [r3, #12] +100056ba: 42a3 cmp r3, r4 +100056bc: f47f aea6 bne.w 1000540c <_malloc_r+0x30> +100056c0: 3002 adds r0, #2 +100056c2: e6e7 b.n 10005494 <_malloc_r+0xb8> +100056c4: f5bc 6f20 cmp.w ip, #2560 @ 0xa00 +100056c8: ea4f 225c mov.w r2, ip, lsr #9 +100056cc: d376 bcc.n 100057bc <_malloc_r+0x3e0> +100056ce: 2a14 cmp r2, #20 +100056d0: f200 80cd bhi.w 1000586e <_malloc_r+0x492> +100056d4: f102 035c add.w r3, r2, #92 @ 0x5c +100056d8: 325b adds r2, #91 @ 0x5b +100056da: 00db lsls r3, r3, #3 +100056dc: 18f1 adds r1, r6, r3 +100056de: 58f3 ldr r3, [r6, r3] +100056e0: 3908 subs r1, #8 +100056e2: 4299 cmp r1, r3 +100056e4: d111 bne.n 1000570a <_malloc_r+0x32e> +100056e6: e0a5 b.n 10005834 <_malloc_r+0x458> +100056e8: 20000630 .word 0x20000630 +100056ec: 20002f64 .word 0x20002f64 +100056f0: 20000628 .word 0x20000628 +100056f4: 20002f34 .word 0x20002f34 +100056f8: 20002f5c .word 0x20002f5c +100056fc: 20002f60 .word 0x20002f60 +10005700: 20000638 .word 0x20000638 +10005704: 689b ldr r3, [r3, #8] +10005706: 4299 cmp r1, r3 +10005708: d004 beq.n 10005714 <_malloc_r+0x338> +1000570a: 685a ldr r2, [r3, #4] +1000570c: f022 0203 bic.w r2, r2, #3 +10005710: 4562 cmp r2, ip +10005712: d8f7 bhi.n 10005704 <_malloc_r+0x328> +10005714: 68d9 ldr r1, [r3, #12] +10005716: e9c4 3102 strd r3, r1, [r4, #8] +1000571a: 608c str r4, [r1, #8] +1000571c: 60dc str r4, [r3, #12] +1000571e: e6e8 b.n 100054f2 <_malloc_r+0x116> +10005720: 2b14 cmp r3, #20 +10005722: d963 bls.n 100057ec <_malloc_r+0x410> +10005724: 2b54 cmp r3, #84 @ 0x54 +10005726: f200 80ab bhi.w 10005880 <_malloc_r+0x4a4> +1000572a: 0b2b lsrs r3, r5, #12 +1000572c: f103 006f add.w r0, r3, #111 @ 0x6f +10005730: f103 0e6e add.w lr, r3, #110 @ 0x6e +10005734: 00c3 lsls r3, r0, #3 +10005736: e697 b.n 10005468 <_malloc_r+0x8c> +10005738: f8d4 c008 ldr.w ip, [r4, #8] +1000573c: 4638 mov r0, r7 +1000573e: 1967 adds r7, r4, r5 +10005740: f045 0501 orr.w r5, r5, #1 +10005744: 6065 str r5, [r4, #4] +10005746: f8cc 300c str.w r3, [ip, #12] +1000574a: f8c3 c008 str.w ip, [r3, #8] +1000574e: f041 0301 orr.w r3, r1, #1 +10005752: e9c6 7704 strd r7, r7, [r6, #16] +10005756: e9c7 8802 strd r8, r8, [r7, #8] +1000575a: 607b str r3, [r7, #4] +1000575c: 50a1 str r1, [r4, r2] +1000575e: 3408 adds r4, #8 +10005760: f000 f8fe bl 10005960 <__malloc_unlock> +10005764: e6f7 b.n 10005556 <_malloc_r+0x17a> +10005766: 4422 add r2, r4 +10005768: 4638 mov r0, r7 +1000576a: 6851 ldr r1, [r2, #4] +1000576c: f041 0101 orr.w r1, r1, #1 +10005770: 6051 str r1, [r2, #4] +10005772: f854 2f08 ldr.w r2, [r4, #8]! +10005776: 60d3 str r3, [r2, #12] +10005778: 609a str r2, [r3, #8] +1000577a: f000 f8f1 bl 10005960 <__malloc_unlock> +1000577e: e6ea b.n 10005556 <_malloc_r+0x17a> +10005780: 44a4 add ip, r4 +10005782: 4638 mov r0, r7 +10005784: 3408 adds r4, #8 +10005786: f8dc 3004 ldr.w r3, [ip, #4] +1000578a: f043 0301 orr.w r3, r3, #1 +1000578e: f8cc 3004 str.w r3, [ip, #4] +10005792: f000 f8e5 bl 10005960 <__malloc_unlock> +10005796: e6de b.n 10005556 <_malloc_r+0x17a> +10005798: 1962 adds r2, r4, r5 +1000579a: f043 0101 orr.w r1, r3, #1 +1000579e: f045 0501 orr.w r5, r5, #1 +100057a2: 4638 mov r0, r7 +100057a4: 6065 str r5, [r4, #4] +100057a6: e9c6 2204 strd r2, r2, [r6, #16] +100057aa: e9c2 8802 strd r8, r8, [r2, #8] +100057ae: 6051 str r1, [r2, #4] +100057b0: f844 300c str.w r3, [r4, ip] +100057b4: 3408 adds r4, #8 +100057b6: f000 f8d3 bl 10005960 <__malloc_unlock> +100057ba: e6cc b.n 10005556 <_malloc_r+0x17a> +100057bc: ea4f 129c mov.w r2, ip, lsr #6 +100057c0: f102 0339 add.w r3, r2, #57 @ 0x39 +100057c4: 3238 adds r2, #56 @ 0x38 +100057c6: 00db lsls r3, r3, #3 +100057c8: e788 b.n 100056dc <_malloc_r+0x300> +100057ca: 42b4 cmp r4, r6 +100057cc: d062 beq.n 10005894 <_malloc_r+0x4b8> +100057ce: 68b4 ldr r4, [r6, #8] +100057d0: 6862 ldr r2, [r4, #4] +100057d2: f022 0803 bic.w r8, r2, #3 +100057d6: 45a8 cmp r8, r5 +100057d8: eba8 0305 sub.w r3, r8, r5 +100057dc: d302 bcc.n 100057e4 <_malloc_r+0x408> +100057de: 2b0f cmp r3, #15 +100057e0: f73f af53 bgt.w 1000568a <_malloc_r+0x2ae> +100057e4: 4638 mov r0, r7 +100057e6: f000 f8bb bl 10005960 <__malloc_unlock> +100057ea: e6b3 b.n 10005554 <_malloc_r+0x178> +100057ec: f103 005c add.w r0, r3, #92 @ 0x5c +100057f0: f103 0e5b add.w lr, r3, #91 @ 0x5b +100057f4: 00c3 lsls r3, r0, #3 +100057f6: e637 b.n 10005468 <_malloc_r+0x8c> +100057f8: f85a 3908 ldr.w r3, [sl], #-8 +100057fc: 4553 cmp r3, sl +100057fe: f040 80a0 bne.w 10005942 <_malloc_r+0x566> +10005802: f010 0f03 tst.w r0, #3 +10005806: f100 30ff add.w r0, r0, #4294967295 @ 0xffffffff +1000580a: d1f5 bne.n 100057f8 <_malloc_r+0x41c> +1000580c: 6873 ldr r3, [r6, #4] +1000580e: ea23 030c bic.w r3, r3, ip +10005812: 6073 str r3, [r6, #4] +10005814: ea4f 0c4c mov.w ip, ip, lsl #1 +10005818: f10c 32ff add.w r2, ip, #4294967295 @ 0xffffffff +1000581c: 429a cmp r2, r3 +1000581e: d304 bcc.n 1000582a <_malloc_r+0x44e> +10005820: e6a3 b.n 1000556a <_malloc_r+0x18e> +10005822: ea4f 0c4c mov.w ip, ip, lsl #1 +10005826: f109 0904 add.w r9, r9, #4 +1000582a: ea1c 0f03 tst.w ip, r3 +1000582e: d0f8 beq.n 10005822 <_malloc_r+0x446> +10005830: 4648 mov r0, r9 +10005832: e670 b.n 10005516 <_malloc_r+0x13a> +10005834: 1092 asrs r2, r2, #2 +10005836: f04f 0c01 mov.w ip, #1 +1000583a: fa0c f202 lsl.w r2, ip, r2 +1000583e: ea4e 0e02 orr.w lr, lr, r2 +10005842: f8c6 e004 str.w lr, [r6, #4] +10005846: e766 b.n 10005716 <_malloc_r+0x33a> +10005848: eb0a 0208 add.w r2, sl, r8 +1000584c: 4638 mov r0, r7 +1000584e: ea02 020c and.w r2, r2, ip +10005852: ebab 0b02 sub.w fp, fp, r2 +10005856: ea0b 0b0c and.w fp, fp, ip +1000585a: 4659 mov r1, fp +1000585c: f000 f8d4 bl 10005a08 <_sbrk_r> +10005860: 1c43 adds r3, r0, #1 +10005862: 9b01 ldr r3, [sp, #4] +10005864: f47f aedb bne.w 1000561e <_malloc_r+0x242> +10005868: f8dd b000 ldr.w fp, [sp] +1000586c: e6db b.n 10005626 <_malloc_r+0x24a> +1000586e: 2a54 cmp r2, #84 @ 0x54 +10005870: d82a bhi.n 100058c8 <_malloc_r+0x4ec> +10005872: ea4f 321c mov.w r2, ip, lsr #12 +10005876: f102 036f add.w r3, r2, #111 @ 0x6f +1000587a: 326e adds r2, #110 @ 0x6e +1000587c: 00db lsls r3, r3, #3 +1000587e: e72d b.n 100056dc <_malloc_r+0x300> +10005880: f5b3 7faa cmp.w r3, #340 @ 0x154 +10005884: d82a bhi.n 100058dc <_malloc_r+0x500> +10005886: 0beb lsrs r3, r5, #15 +10005888: f103 0078 add.w r0, r3, #120 @ 0x78 +1000588c: f103 0e77 add.w lr, r3, #119 @ 0x77 +10005890: 00c3 lsls r3, r0, #3 +10005892: e5e9 b.n 10005468 <_malloc_r+0x8c> +10005894: 4b2e ldr r3, [pc, #184] @ (10005950 <_malloc_r+0x574>) +10005896: f10b 3cff add.w ip, fp, #4294967295 @ 0xffffffff +1000589a: 6818 ldr r0, [r3, #0] +1000589c: 4440 add r0, r8 +1000589e: 6018 str r0, [r3, #0] +100058a0: e69b b.n 100055da <_malloc_r+0x1fe> +100058a2: ea1a 0f0c tst.w sl, ip +100058a6: f47f ae98 bne.w 100055da <_malloc_r+0x1fe> +100058aa: 44c8 add r8, r9 +100058ac: f8d6 a008 ldr.w sl, [r6, #8] +100058b0: f048 0201 orr.w r2, r8, #1 +100058b4: f8ca 2004 str.w r2, [sl, #4] +100058b8: e6d8 b.n 1000566c <_malloc_r+0x290> +100058ba: f8c2 a000 str.w sl, [r2] +100058be: e696 b.n 100055ee <_malloc_r+0x212> +100058c0: 2301 movs r3, #1 +100058c2: f8ca 3004 str.w r3, [sl, #4] +100058c6: e78d b.n 100057e4 <_malloc_r+0x408> +100058c8: f5b2 7faa cmp.w r2, #340 @ 0x154 +100058cc: d824 bhi.n 10005918 <_malloc_r+0x53c> +100058ce: ea4f 32dc mov.w r2, ip, lsr #15 +100058d2: f102 0378 add.w r3, r2, #120 @ 0x78 +100058d6: 3277 adds r2, #119 @ 0x77 +100058d8: 00db lsls r3, r3, #3 +100058da: e6ff b.n 100056dc <_malloc_r+0x300> +100058dc: f240 5254 movw r2, #1364 @ 0x554 +100058e0: 4293 cmp r3, r2 +100058e2: d824 bhi.n 1000592e <_malloc_r+0x552> +100058e4: 0cab lsrs r3, r5, #18 +100058e6: f103 007d add.w r0, r3, #125 @ 0x7d +100058ea: f103 0e7c add.w lr, r3, #124 @ 0x7c +100058ee: 00c3 lsls r3, r0, #3 +100058f0: e5ba b.n 10005468 <_malloc_r+0x8c> +100058f2: 9a00 ldr r2, [sp, #0] +100058f4: f04f 0b00 mov.w fp, #0 +100058f8: 3a08 subs r2, #8 +100058fa: 4490 add r8, r2 +100058fc: eba8 080a sub.w r8, r8, sl +10005900: e691 b.n 10005626 <_malloc_r+0x24a> +10005902: 4638 mov r0, r7 +10005904: f104 0108 add.w r1, r4, #8 +10005908: 9300 str r3, [sp, #0] +1000590a: f000 f9a7 bl 10005c5c <_free_r> +1000590e: 9b00 ldr r3, [sp, #0] +10005910: f8d6 a008 ldr.w sl, [r6, #8] +10005914: 6818 ldr r0, [r3, #0] +10005916: e6a7 b.n 10005668 <_malloc_r+0x28c> +10005918: f240 5354 movw r3, #1364 @ 0x554 +1000591c: 429a cmp r2, r3 +1000591e: d80c bhi.n 1000593a <_malloc_r+0x55e> +10005920: ea4f 429c mov.w r2, ip, lsr #18 +10005924: f102 037d add.w r3, r2, #125 @ 0x7d +10005928: 327c adds r2, #124 @ 0x7c +1000592a: 00db lsls r3, r3, #3 +1000592c: e6d6 b.n 100056dc <_malloc_r+0x300> +1000592e: f44f 737e mov.w r3, #1016 @ 0x3f8 +10005932: 207f movs r0, #127 @ 0x7f +10005934: f04f 0e7e mov.w lr, #126 @ 0x7e +10005938: e596 b.n 10005468 <_malloc_r+0x8c> +1000593a: f44f 737e mov.w r3, #1016 @ 0x3f8 +1000593e: 227e movs r2, #126 @ 0x7e +10005940: e6cc b.n 100056dc <_malloc_r+0x300> +10005942: 6873 ldr r3, [r6, #4] +10005944: e766 b.n 10005814 <_malloc_r+0x438> +10005946: 08e8 lsrs r0, r5, #3 +10005948: f105 0308 add.w r3, r5, #8 +1000594c: e556 b.n 100053fc <_malloc_r+0x20> +1000594e: bf00 nop +10005950: 20002f34 .word 0x20002f34 + +10005954 <__malloc_lock>: +10005954: 4801 ldr r0, [pc, #4] @ (1000595c <__malloc_lock+0x8>) +10005956: f000 b87d b.w 10005a54 <__retarget_lock_acquire_recursive> +1000595a: bf00 nop +1000595c: 20002f30 .word 0x20002f30 + +10005960 <__malloc_unlock>: +10005960: 4801 ldr r0, [pc, #4] @ (10005968 <__malloc_unlock+0x8>) +10005962: f000 b879 b.w 10005a58 <__retarget_lock_release_recursive> +10005966: bf00 nop +10005968: 20002f30 .word 0x20002f30 + +1000596c : +1000596c: 0783 lsls r3, r0, #30 +1000596e: b530 push {r4, r5, lr} +10005970: d046 beq.n 10005a00 +10005972: 1884 adds r4, r0, r2 +10005974: 4684 mov ip, r0 +10005976: e004 b.n 10005982 +10005978: f803 1b01 strb.w r1, [r3], #1 +1000597c: 079d lsls r5, r3, #30 +1000597e: d004 beq.n 1000598a +10005980: 469c mov ip, r3 +10005982: 45a4 cmp ip, r4 +10005984: 4663 mov r3, ip +10005986: d1f7 bne.n 10005978 +10005988: bd30 pop {r4, r5, pc} +1000598a: 3a01 subs r2, #1 +1000598c: 4402 add r2, r0 +1000598e: eba2 020c sub.w r2, r2, ip +10005992: 2a03 cmp r2, #3 +10005994: d929 bls.n 100059ea +10005996: b2cc uxtb r4, r1 +10005998: 2a0f cmp r2, #15 +1000599a: eb04 2404 add.w r4, r4, r4, lsl #8 +1000599e: eb04 4404 add.w r4, r4, r4, lsl #16 +100059a2: d92f bls.n 10005a04 +100059a4: f1a2 0c10 sub.w ip, r2, #16 +100059a8: f103 0510 add.w r5, r3, #16 +100059ac: f02c 0c0f bic.w ip, ip, #15 +100059b0: 44ac add ip, r5 +100059b2: e9c3 4400 strd r4, r4, [r3] +100059b6: e9c3 4402 strd r4, r4, [r3, #8] +100059ba: 3310 adds r3, #16 +100059bc: 4563 cmp r3, ip +100059be: d1f8 bne.n 100059b2 +100059c0: f012 0f0c tst.w r2, #12 +100059c4: f002 0e0f and.w lr, r2, #15 +100059c8: d018 beq.n 100059fc +100059ca: f02e 0c03 bic.w ip, lr, #3 +100059ce: f1ae 0504 sub.w r5, lr, #4 +100059d2: 461a mov r2, r3 +100059d4: 449c add ip, r3 +100059d6: f842 4b04 str.w r4, [r2], #4 +100059da: 4562 cmp r2, ip +100059dc: d1fb bne.n 100059d6 +100059de: f025 0403 bic.w r4, r5, #3 +100059e2: 3304 adds r3, #4 +100059e4: f00e 0203 and.w r2, lr, #3 +100059e8: 4423 add r3, r4 +100059ea: 2a00 cmp r2, #0 +100059ec: d0cc beq.n 10005988 +100059ee: b2c9 uxtb r1, r1 +100059f0: 441a add r2, r3 +100059f2: f803 1b01 strb.w r1, [r3], #1 +100059f6: 4293 cmp r3, r2 +100059f8: d1fb bne.n 100059f2 +100059fa: bd30 pop {r4, r5, pc} +100059fc: 4672 mov r2, lr +100059fe: e7f4 b.n 100059ea +10005a00: 4603 mov r3, r0 +10005a02: e7c6 b.n 10005992 +10005a04: 4696 mov lr, r2 +10005a06: e7e0 b.n 100059ca + +10005a08 <_sbrk_r>: +10005a08: b538 push {r3, r4, r5, lr} +10005a0a: 2200 movs r2, #0 +10005a0c: 4d06 ldr r5, [pc, #24] @ (10005a28 <_sbrk_r+0x20>) +10005a0e: 4604 mov r4, r0 +10005a10: 4608 mov r0, r1 +10005a12: 602a str r2, [r5, #0] +10005a14: f7fd fad2 bl 10002fbc <_sbrk> +10005a18: 1c43 adds r3, r0, #1 +10005a1a: d000 beq.n 10005a1e <_sbrk_r+0x16> +10005a1c: bd38 pop {r3, r4, r5, pc} +10005a1e: 682b ldr r3, [r5, #0] +10005a20: 2b00 cmp r3, #0 +10005a22: d0fb beq.n 10005a1c <_sbrk_r+0x14> +10005a24: 6023 str r3, [r4, #0] +10005a26: bd38 pop {r3, r4, r5, pc} +10005a28: 200030fc .word 0x200030fc + +10005a2c <__errno>: +10005a2c: 4b01 ldr r3, [pc, #4] @ (10005a34 <__errno+0x8>) +10005a2e: 6818 ldr r0, [r3, #0] +10005a30: 4770 bx lr +10005a32: bf00 nop +10005a34: 20000a38 .word 0x20000a38 + +10005a38 : +10005a38: 2808 cmp r0, #8 +10005a3a: d102 bne.n 10005a42 +10005a3c: f44f 5080 mov.w r0, #4096 @ 0x1000 +10005a40: 4770 bx lr +10005a42: b508 push {r3, lr} +10005a44: f7ff fff2 bl 10005a2c <__errno> +10005a48: 2216 movs r2, #22 +10005a4a: 4603 mov r3, r0 +10005a4c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff +10005a50: 601a str r2, [r3, #0] +10005a52: bd08 pop {r3, pc} + +10005a54 <__retarget_lock_acquire_recursive>: +10005a54: 4770 bx lr +10005a56: bf00 nop + +10005a58 <__retarget_lock_release_recursive>: +10005a58: 4770 bx lr +10005a5a: bf00 nop + +10005a5c : +10005a5c: 4684 mov ip, r0 +10005a5e: ea41 0300 orr.w r3, r1, r0 +10005a62: f013 0303 ands.w r3, r3, #3 +10005a66: d149 bne.n 10005afc +10005a68: 3a40 subs r2, #64 @ 0x40 +10005a6a: d323 bcc.n 10005ab4 +10005a6c: 680b ldr r3, [r1, #0] +10005a6e: 6003 str r3, [r0, #0] +10005a70: 684b ldr r3, [r1, #4] +10005a72: 6043 str r3, [r0, #4] +10005a74: 688b ldr r3, [r1, #8] +10005a76: 6083 str r3, [r0, #8] +10005a78: 68cb ldr r3, [r1, #12] +10005a7a: 60c3 str r3, [r0, #12] +10005a7c: 690b ldr r3, [r1, #16] +10005a7e: 6103 str r3, [r0, #16] +10005a80: 694b ldr r3, [r1, #20] +10005a82: 6143 str r3, [r0, #20] +10005a84: 698b ldr r3, [r1, #24] +10005a86: 6183 str r3, [r0, #24] +10005a88: 69cb ldr r3, [r1, #28] +10005a8a: 61c3 str r3, [r0, #28] +10005a8c: 6a0b ldr r3, [r1, #32] +10005a8e: 6203 str r3, [r0, #32] +10005a90: 6a4b ldr r3, [r1, #36] @ 0x24 +10005a92: 6243 str r3, [r0, #36] @ 0x24 +10005a94: 6a8b ldr r3, [r1, #40] @ 0x28 +10005a96: 6283 str r3, [r0, #40] @ 0x28 +10005a98: 6acb ldr r3, [r1, #44] @ 0x2c +10005a9a: 62c3 str r3, [r0, #44] @ 0x2c +10005a9c: 6b0b ldr r3, [r1, #48] @ 0x30 +10005a9e: 6303 str r3, [r0, #48] @ 0x30 +10005aa0: 6b4b ldr r3, [r1, #52] @ 0x34 +10005aa2: 6343 str r3, [r0, #52] @ 0x34 +10005aa4: 6b8b ldr r3, [r1, #56] @ 0x38 +10005aa6: 6383 str r3, [r0, #56] @ 0x38 +10005aa8: 6bcb ldr r3, [r1, #60] @ 0x3c +10005aaa: 63c3 str r3, [r0, #60] @ 0x3c +10005aac: 3040 adds r0, #64 @ 0x40 +10005aae: 3140 adds r1, #64 @ 0x40 +10005ab0: 3a40 subs r2, #64 @ 0x40 +10005ab2: d2db bcs.n 10005a6c +10005ab4: 3230 adds r2, #48 @ 0x30 +10005ab6: d30b bcc.n 10005ad0 +10005ab8: 680b ldr r3, [r1, #0] +10005aba: 6003 str r3, [r0, #0] +10005abc: 684b ldr r3, [r1, #4] +10005abe: 6043 str r3, [r0, #4] +10005ac0: 688b ldr r3, [r1, #8] +10005ac2: 6083 str r3, [r0, #8] +10005ac4: 68cb ldr r3, [r1, #12] +10005ac6: 60c3 str r3, [r0, #12] +10005ac8: 3010 adds r0, #16 +10005aca: 3110 adds r1, #16 +10005acc: 3a10 subs r2, #16 +10005ace: d2f3 bcs.n 10005ab8 +10005ad0: 320c adds r2, #12 +10005ad2: d305 bcc.n 10005ae0 +10005ad4: f851 3b04 ldr.w r3, [r1], #4 +10005ad8: f840 3b04 str.w r3, [r0], #4 +10005adc: 3a04 subs r2, #4 +10005ade: d2f9 bcs.n 10005ad4 +10005ae0: 3204 adds r2, #4 +10005ae2: d008 beq.n 10005af6 +10005ae4: 07d2 lsls r2, r2, #31 +10005ae6: bf1c itt ne +10005ae8: f811 3b01 ldrbne.w r3, [r1], #1 +10005aec: f800 3b01 strbne.w r3, [r0], #1 +10005af0: d301 bcc.n 10005af6 +10005af2: 880b ldrh r3, [r1, #0] +10005af4: 8003 strh r3, [r0, #0] +10005af6: 4660 mov r0, ip +10005af8: 4770 bx lr +10005afa: bf00 nop +10005afc: 2a08 cmp r2, #8 +10005afe: d313 bcc.n 10005b28 +10005b00: 078b lsls r3, r1, #30 +10005b02: d0b1 beq.n 10005a68 +10005b04: f010 0303 ands.w r3, r0, #3 +10005b08: d0ae beq.n 10005a68 +10005b0a: f1c3 0304 rsb r3, r3, #4 +10005b0e: 1ad2 subs r2, r2, r3 +10005b10: 07db lsls r3, r3, #31 +10005b12: bf1c itt ne +10005b14: f811 3b01 ldrbne.w r3, [r1], #1 +10005b18: f800 3b01 strbne.w r3, [r0], #1 +10005b1c: d3a4 bcc.n 10005a68 +10005b1e: f831 3b02 ldrh.w r3, [r1], #2 +10005b22: f820 3b02 strh.w r3, [r0], #2 +10005b26: e79f b.n 10005a68 +10005b28: 3a04 subs r2, #4 +10005b2a: d3d9 bcc.n 10005ae0 +10005b2c: 3a01 subs r2, #1 +10005b2e: f811 3b01 ldrb.w r3, [r1], #1 +10005b32: f800 3b01 strb.w r3, [r0], #1 +10005b36: d2f9 bcs.n 10005b2c +10005b38: 780b ldrb r3, [r1, #0] +10005b3a: 7003 strb r3, [r0, #0] +10005b3c: 784b ldrb r3, [r1, #1] +10005b3e: 7043 strb r3, [r0, #1] +10005b40: 788b ldrb r3, [r1, #2] +10005b42: 7083 strb r3, [r0, #2] +10005b44: 4660 mov r0, ip +10005b46: 4770 bx lr + +10005b48 : +10005b48: f020 0103 bic.w r1, r0, #3 +10005b4c: f010 0003 ands.w r0, r0, #3 +10005b50: f1c0 0000 rsb r0, r0, #0 +10005b54: f851 3b04 ldr.w r3, [r1], #4 +10005b58: f100 0c04 add.w ip, r0, #4 +10005b5c: ea4f 0ccc mov.w ip, ip, lsl #3 +10005b60: f06f 0200 mvn.w r2, #0 +10005b64: bf1c itt ne +10005b66: fa22 f20c lsrne.w r2, r2, ip +10005b6a: 4313 orrne r3, r2 +10005b6c: f04f 0c01 mov.w ip, #1 +10005b70: ea4c 2c0c orr.w ip, ip, ip, lsl #8 +10005b74: ea4c 4c0c orr.w ip, ip, ip, lsl #16 +10005b78: eba3 020c sub.w r2, r3, ip +10005b7c: ea22 0203 bic.w r2, r2, r3 +10005b80: ea12 12cc ands.w r2, r2, ip, lsl #7 +10005b84: bf04 itt eq +10005b86: f851 3b04 ldreq.w r3, [r1], #4 +10005b8a: 3004 addeq r0, #4 +10005b8c: d0f4 beq.n 10005b78 +10005b8e: f1c2 0100 rsb r1, r2, #0 +10005b92: ea02 0201 and.w r2, r2, r1 +10005b96: fab2 f282 clz r2, r2 +10005b9a: f1c2 021f rsb r2, r2, #31 +10005b9e: eb00 00d2 add.w r0, r0, r2, lsr #3 +10005ba2: 4770 bx lr + +10005ba4 <_malloc_trim_r>: +10005ba4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} +10005ba8: 4606 mov r6, r0 +10005baa: f8df 80ac ldr.w r8, [pc, #172] @ 10005c58 <_malloc_trim_r+0xb4> +10005bae: 2008 movs r0, #8 +10005bb0: 4689 mov r9, r1 +10005bb2: f7ff ff41 bl 10005a38 +10005bb6: 4605 mov r5, r0 +10005bb8: 4630 mov r0, r6 +10005bba: f7ff fecb bl 10005954 <__malloc_lock> +10005bbe: f8d8 3008 ldr.w r3, [r8, #8] +10005bc2: 685f ldr r7, [r3, #4] +10005bc4: f027 0703 bic.w r7, r7, #3 +10005bc8: f1a7 0411 sub.w r4, r7, #17 +10005bcc: eba4 0409 sub.w r4, r4, r9 +10005bd0: 442c add r4, r5 +10005bd2: fbb4 f4f5 udiv r4, r4, r5 +10005bd6: 3c01 subs r4, #1 +10005bd8: fb05 f404 mul.w r4, r5, r4 +10005bdc: 42a5 cmp r5, r4 +10005bde: dc08 bgt.n 10005bf2 <_malloc_trim_r+0x4e> +10005be0: 2100 movs r1, #0 +10005be2: 4630 mov r0, r6 +10005be4: f7ff ff10 bl 10005a08 <_sbrk_r> +10005be8: f8d8 3008 ldr.w r3, [r8, #8] +10005bec: 443b add r3, r7 +10005bee: 4298 cmp r0, r3 +10005bf0: d005 beq.n 10005bfe <_malloc_trim_r+0x5a> +10005bf2: 4630 mov r0, r6 +10005bf4: f7ff feb4 bl 10005960 <__malloc_unlock> +10005bf8: 2000 movs r0, #0 +10005bfa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} +10005bfe: 4261 negs r1, r4 +10005c00: 4630 mov r0, r6 +10005c02: f7ff ff01 bl 10005a08 <_sbrk_r> +10005c06: 3001 adds r0, #1 +10005c08: d00f beq.n 10005c2a <_malloc_trim_r+0x86> +10005c0a: 1b3f subs r7, r7, r4 +10005c0c: 4a10 ldr r2, [pc, #64] @ (10005c50 <_malloc_trim_r+0xac>) +10005c0e: f8d8 3008 ldr.w r3, [r8, #8] +10005c12: 4630 mov r0, r6 +10005c14: f047 0701 orr.w r7, r7, #1 +10005c18: 605f str r7, [r3, #4] +10005c1a: 6813 ldr r3, [r2, #0] +10005c1c: 1b1b subs r3, r3, r4 +10005c1e: 6013 str r3, [r2, #0] +10005c20: f7ff fe9e bl 10005960 <__malloc_unlock> +10005c24: 2001 movs r0, #1 +10005c26: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} +10005c2a: 2100 movs r1, #0 +10005c2c: 4630 mov r0, r6 +10005c2e: f7ff feeb bl 10005a08 <_sbrk_r> +10005c32: f8d8 2008 ldr.w r2, [r8, #8] +10005c36: 1a83 subs r3, r0, r2 +10005c38: 2b0f cmp r3, #15 +10005c3a: ddda ble.n 10005bf2 <_malloc_trim_r+0x4e> +10005c3c: f043 0301 orr.w r3, r3, #1 +10005c40: 4903 ldr r1, [pc, #12] @ (10005c50 <_malloc_trim_r+0xac>) +10005c42: 6053 str r3, [r2, #4] +10005c44: 4b03 ldr r3, [pc, #12] @ (10005c54 <_malloc_trim_r+0xb0>) +10005c46: 681b ldr r3, [r3, #0] +10005c48: 1ac0 subs r0, r0, r3 +10005c4a: 6008 str r0, [r1, #0] +10005c4c: e7d1 b.n 10005bf2 <_malloc_trim_r+0x4e> +10005c4e: bf00 nop +10005c50: 20002f34 .word 0x20002f34 +10005c54: 20000628 .word 0x20000628 +10005c58: 20000630 .word 0x20000630 + +10005c5c <_free_r>: +10005c5c: 2900 cmp r1, #0 +10005c5e: d05a beq.n 10005d16 <_free_r+0xba> +10005c60: b5f8 push {r3, r4, r5, r6, r7, lr} +10005c62: 460c mov r4, r1 +10005c64: 4607 mov r7, r0 +10005c66: f7ff fe75 bl 10005954 <__malloc_lock> +10005c6a: 4d73 ldr r5, [pc, #460] @ (10005e38 <_free_r+0x1dc>) +10005c6c: f854 cc04 ldr.w ip, [r4, #-4] +10005c70: f1a4 0208 sub.w r2, r4, #8 +10005c74: 68a8 ldr r0, [r5, #8] +10005c76: f02c 0301 bic.w r3, ip, #1 +10005c7a: f00c 0e01 and.w lr, ip, #1 +10005c7e: 18d1 adds r1, r2, r3 +10005c80: 684e ldr r6, [r1, #4] +10005c82: 4288 cmp r0, r1 +10005c84: f026 0603 bic.w r6, r6, #3 +10005c88: d07c beq.n 10005d84 <_free_r+0x128> +10005c8a: 1988 adds r0, r1, r6 +10005c8c: 604e str r6, [r1, #4] +10005c8e: 6840 ldr r0, [r0, #4] +10005c90: f000 0001 and.w r0, r0, #1 +10005c94: f1be 0f00 cmp.w lr, #0 +10005c98: d12e bne.n 10005cf8 <_free_r+0x9c> +10005c9a: f854 4c08 ldr.w r4, [r4, #-8] +10005c9e: f105 0c08 add.w ip, r5, #8 +10005ca2: 1b12 subs r2, r2, r4 +10005ca4: 4423 add r3, r4 +10005ca6: 6894 ldr r4, [r2, #8] +10005ca8: 4564 cmp r4, ip +10005caa: d060 beq.n 10005d6e <_free_r+0x112> +10005cac: f8d2 e00c ldr.w lr, [r2, #12] +10005cb0: f8c4 e00c str.w lr, [r4, #12] +10005cb4: f8ce 4008 str.w r4, [lr, #8] +10005cb8: 2800 cmp r0, #0 +10005cba: d07d beq.n 10005db8 <_free_r+0x15c> +10005cbc: f043 0001 orr.w r0, r3, #1 +10005cc0: 6050 str r0, [r2, #4] +10005cc2: 600b str r3, [r1, #0] +10005cc4: f5b3 7f00 cmp.w r3, #512 @ 0x200 +10005cc8: d22e bcs.n 10005d28 <_free_r+0xcc> +10005cca: 0958 lsrs r0, r3, #5 +10005ccc: 08d9 lsrs r1, r3, #3 +10005cce: 2301 movs r3, #1 +10005cd0: 4083 lsls r3, r0 +10005cd2: 6868 ldr r0, [r5, #4] +10005cd4: 3101 adds r1, #1 +10005cd6: 4303 orrs r3, r0 +10005cd8: f855 0031 ldr.w r0, [r5, r1, lsl #3] +10005cdc: 606b str r3, [r5, #4] +10005cde: eb05 03c1 add.w r3, r5, r1, lsl #3 +10005ce2: 3b08 subs r3, #8 +10005ce4: e9c2 0302 strd r0, r3, [r2, #8] +10005ce8: f845 2031 str.w r2, [r5, r1, lsl #3] +10005cec: 60c2 str r2, [r0, #12] +10005cee: 4638 mov r0, r7 +10005cf0: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} +10005cf4: f7ff be34 b.w 10005960 <__malloc_unlock> +10005cf8: b970 cbnz r0, 10005d18 <_free_r+0xbc> +10005cfa: 4433 add r3, r6 +10005cfc: f105 0c08 add.w ip, r5, #8 +10005d00: 6888 ldr r0, [r1, #8] +10005d02: f043 0401 orr.w r4, r3, #1 +10005d06: 4560 cmp r0, ip +10005d08: d06e beq.n 10005de8 <_free_r+0x18c> +10005d0a: 68c9 ldr r1, [r1, #12] +10005d0c: 60c1 str r1, [r0, #12] +10005d0e: 6088 str r0, [r1, #8] +10005d10: 6054 str r4, [r2, #4] +10005d12: 50d3 str r3, [r2, r3] +10005d14: e7d6 b.n 10005cc4 <_free_r+0x68> +10005d16: 4770 bx lr +10005d18: f04c 0101 orr.w r1, ip, #1 +10005d1c: f5b3 7f00 cmp.w r3, #512 @ 0x200 +10005d20: f844 1c04 str.w r1, [r4, #-4] +10005d24: 50d3 str r3, [r2, r3] +10005d26: d3d0 bcc.n 10005cca <_free_r+0x6e> +10005d28: f5b3 6f20 cmp.w r3, #2560 @ 0xa00 +10005d2c: ea4f 2153 mov.w r1, r3, lsr #9 +10005d30: d244 bcs.n 10005dbc <_free_r+0x160> +10005d32: 0999 lsrs r1, r3, #6 +10005d34: f101 0039 add.w r0, r1, #57 @ 0x39 +10005d38: f101 0438 add.w r4, r1, #56 @ 0x38 +10005d3c: 00c1 lsls r1, r0, #3 +10005d3e: 1868 adds r0, r5, r1 +10005d40: 5869 ldr r1, [r5, r1] +10005d42: 3808 subs r0, #8 +10005d44: 4288 cmp r0, r1 +10005d46: d103 bne.n 10005d50 <_free_r+0xf4> +10005d48: e055 b.n 10005df6 <_free_r+0x19a> +10005d4a: 6889 ldr r1, [r1, #8] +10005d4c: 4288 cmp r0, r1 +10005d4e: d004 beq.n 10005d5a <_free_r+0xfe> +10005d50: 684c ldr r4, [r1, #4] +10005d52: f024 0403 bic.w r4, r4, #3 +10005d56: 429c cmp r4, r3 +10005d58: d8f7 bhi.n 10005d4a <_free_r+0xee> +10005d5a: 68c8 ldr r0, [r1, #12] +10005d5c: e9c2 1002 strd r1, r0, [r2, #8] +10005d60: 6082 str r2, [r0, #8] +10005d62: 4638 mov r0, r7 +10005d64: 60ca str r2, [r1, #12] +10005d66: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} +10005d6a: f7ff bdf9 b.w 10005960 <__malloc_unlock> +10005d6e: bb80 cbnz r0, 10005dd2 <_free_r+0x176> +10005d70: 441e add r6, r3 +10005d72: e9d1 1302 ldrd r1, r3, [r1, #8] +10005d76: 60cb str r3, [r1, #12] +10005d78: 6099 str r1, [r3, #8] +10005d7a: f046 0301 orr.w r3, r6, #1 +10005d7e: 6053 str r3, [r2, #4] +10005d80: 5196 str r6, [r2, r6] +10005d82: e7b4 b.n 10005cee <_free_r+0x92> +10005d84: 441e add r6, r3 +10005d86: f1be 0f00 cmp.w lr, #0 +10005d8a: d107 bne.n 10005d9c <_free_r+0x140> +10005d8c: f854 3c08 ldr.w r3, [r4, #-8] +10005d90: 1ad2 subs r2, r2, r3 +10005d92: 441e add r6, r3 +10005d94: e9d2 1302 ldrd r1, r3, [r2, #8] +10005d98: 60cb str r3, [r1, #12] +10005d9a: 6099 str r1, [r3, #8] +10005d9c: f046 0301 orr.w r3, r6, #1 +10005da0: 6053 str r3, [r2, #4] +10005da2: 4b26 ldr r3, [pc, #152] @ (10005e3c <_free_r+0x1e0>) +10005da4: 60aa str r2, [r5, #8] +10005da6: 681b ldr r3, [r3, #0] +10005da8: 42b3 cmp r3, r6 +10005daa: d8a0 bhi.n 10005cee <_free_r+0x92> +10005dac: 4b24 ldr r3, [pc, #144] @ (10005e40 <_free_r+0x1e4>) +10005dae: 4638 mov r0, r7 +10005db0: 6819 ldr r1, [r3, #0] +10005db2: f7ff fef7 bl 10005ba4 <_malloc_trim_r> +10005db6: e79a b.n 10005cee <_free_r+0x92> +10005db8: 4433 add r3, r6 +10005dba: e7a1 b.n 10005d00 <_free_r+0xa4> +10005dbc: 2914 cmp r1, #20 +10005dbe: d90d bls.n 10005ddc <_free_r+0x180> +10005dc0: 2954 cmp r1, #84 @ 0x54 +10005dc2: d81f bhi.n 10005e04 <_free_r+0x1a8> +10005dc4: 0b19 lsrs r1, r3, #12 +10005dc6: f101 006f add.w r0, r1, #111 @ 0x6f +10005dca: f101 046e add.w r4, r1, #110 @ 0x6e +10005dce: 00c1 lsls r1, r0, #3 +10005dd0: e7b5 b.n 10005d3e <_free_r+0xe2> +10005dd2: f043 0001 orr.w r0, r3, #1 +10005dd6: 6050 str r0, [r2, #4] +10005dd8: 600b str r3, [r1, #0] +10005dda: e788 b.n 10005cee <_free_r+0x92> +10005ddc: f101 005c add.w r0, r1, #92 @ 0x5c +10005de0: f101 045b add.w r4, r1, #91 @ 0x5b +10005de4: 00c1 lsls r1, r0, #3 +10005de6: e7aa b.n 10005d3e <_free_r+0xe2> +10005de8: e9c5 2204 strd r2, r2, [r5, #16] +10005dec: e9c2 cc02 strd ip, ip, [r2, #8] +10005df0: 6054 str r4, [r2, #4] +10005df2: 50d3 str r3, [r2, r3] +10005df4: e77b b.n 10005cee <_free_r+0x92> +10005df6: 10a4 asrs r4, r4, #2 +10005df8: 2301 movs r3, #1 +10005dfa: 40a3 lsls r3, r4 +10005dfc: 686c ldr r4, [r5, #4] +10005dfe: 4323 orrs r3, r4 +10005e00: 606b str r3, [r5, #4] +10005e02: e7ab b.n 10005d5c <_free_r+0x100> +10005e04: f5b1 7faa cmp.w r1, #340 @ 0x154 +10005e08: d806 bhi.n 10005e18 <_free_r+0x1bc> +10005e0a: 0bd9 lsrs r1, r3, #15 +10005e0c: f101 0078 add.w r0, r1, #120 @ 0x78 +10005e10: f101 0477 add.w r4, r1, #119 @ 0x77 +10005e14: 00c1 lsls r1, r0, #3 +10005e16: e792 b.n 10005d3e <_free_r+0xe2> +10005e18: f240 5054 movw r0, #1364 @ 0x554 +10005e1c: 4281 cmp r1, r0 +10005e1e: d806 bhi.n 10005e2e <_free_r+0x1d2> +10005e20: 0c99 lsrs r1, r3, #18 +10005e22: f101 007d add.w r0, r1, #125 @ 0x7d +10005e26: f101 047c add.w r4, r1, #124 @ 0x7c +10005e2a: 00c1 lsls r1, r0, #3 +10005e2c: e787 b.n 10005d3e <_free_r+0xe2> +10005e2e: f44f 717e mov.w r1, #1016 @ 0x3f8 +10005e32: 247e movs r4, #126 @ 0x7e +10005e34: e783 b.n 10005d3e <_free_r+0xe2> +10005e36: bf00 nop +10005e38: 20000630 .word 0x20000630 +10005e3c: 2000062c .word 0x2000062c +10005e40: 20002f64 .word 0x20002f64 + +10005e44 <_fini>: +10005e44: b5f8 push {r3, r4, r5, r6, r7, lr} +10005e46: bf00 nop + +10005e48 <____aeabi_uldivmod_veneer>: +10005e48: f85f f000 ldr.w pc, [pc] @ 10005e4c <____aeabi_uldivmod_veneer+0x4> +10005e4c: 20000221 .word 0x20000221 + +10005e50 <__mutex_exit_veneer>: +10005e50: f85f f000 ldr.w pc, [pc] @ 10005e54 <__mutex_exit_veneer+0x4> +10005e54: 200001e5 .word 0x200001e5 + +10005e58 <__mutex_try_enter_block_until_veneer>: +10005e58: f85f f000 ldr.w pc, [pc] @ 10005e5c <__mutex_try_enter_block_until_veneer+0x4> +10005e5c: 2000017d .word 0x2000017d + +10005e60 <__pre_init_runtime_init_bootrom_reset>: +10005e60: 10001459 Y... + +10005e64 <__pre_init_runtime_init_early_resets>: +10005e64: 100013cd .... + +10005e68 <__pre_init_runtime_init_usb_power_down>: +10005e68: 10001401 .... + +10005e6c <__pre_init_runtime_init_clocks>: +10005e6c: 100014ed .... + +10005e70 <__pre_init_runtime_init_post_clock_resets>: +10005e70: 10001439 9... + +10005e74 <__pre_init_runtime_init_boot_locks_reset>: +10005e74: 10001351 Q... + +10005e78 <__pre_init_runtime_init_spin_locks_reset>: +10005e78: 10001481 .... + +10005e7c <__pre_init_runtime_init_bootrom_locking_enable>: +10005e7c: 1000133d =... + +10005e80 <__pre_init_runtime_init_mutex>: +10005e80: 10000869 i... + +10005e84 <__pre_init_runtime_init_install_ram_vector_table>: +10005e84: 10001485 .... + +10005e88 <__pre_init_runtime_init_default_alarm_pool>: +10005e88: 10000be1 .... + +10005e8c <__pre_init_first_per_core_initializer>: +10005e8c: 1000139d .... + +10005e90 <__pre_init_runtime_init_per_core_bootrom_reset>: +10005e90: 1000146d m... + +10005e94 <__pre_init_runtime_init_per_core_enable_coprocessors>: +10005e94: 1000141d .... + +10005e98 <__pre_init_spinlock_set_extexclall>: +10005e98: 100004b9 .... + +10005e9c <__pre_init_runtime_init_per_core_irq_priorities>: +10005e9c: 100004e1 .... + +10005ea0 <__init_array_start>: +10005ea0: 1000531d .word 0x1000531d + +10005ea4 <__frame_dummy_init_array_entry>: +10005ea4: 10000211 .... + +Disassembly of section .data: + +20000110 : +20000110: f04f 4150 mov.w r1, #3489660928 @ 0xd0000000 +20000114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} +20000118: 2700 movs r7, #0 +2000011a: 4604 mov r4, r0 +2000011c: 4616 mov r6, r2 +2000011e: 461d mov r5, r3 +20000120: f8d1 8000 ldr.w r8, [r1] +20000124: e008 b.n 20000138 +20000126: e8c1 7f8f stlb r7, [r1] +2000012a: f38c 8810 msr PRIMASK, ip +2000012e: 4630 mov r0, r6 +20000130: 4629 mov r1, r5 +20000132: f000 fa35 bl 200005a0 <__best_effort_wfe_or_timeout_veneer> +20000136: b9e8 cbnz r0, 20000174 +20000138: 6821 ldr r1, [r4, #0] +2000013a: f3ef 8c10 mrs ip, PRIMASK +2000013e: b672 cpsid i +20000140: e8d1 2fcf ldaexb r2, [r1] +20000144: 2301 movs r3, #1 +20000146: 2a00 cmp r2, #0 +20000148: d1fa bne.n 20000140 +2000014a: e8c1 3f42 strexb r2, r3, [r1] +2000014e: 2a00 cmp r2, #0 +20000150: d1f6 bne.n 20000140 +20000152: f3bf 8f5f dmb sy +20000156: f994 3004 ldrsb.w r3, [r4, #4] +2000015a: 6821 ldr r1, [r4, #0] +2000015c: 2b00 cmp r3, #0 +2000015e: dae2 bge.n 20000126 +20000160: 2300 movs r3, #0 +20000162: f884 8004 strb.w r8, [r4, #4] +20000166: e8c1 3f8f stlb r3, [r1] +2000016a: f38c 8810 msr PRIMASK, ip +2000016e: 2001 movs r0, #1 +20000170: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +20000174: 2000 movs r0, #0 +20000176: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +2000017a: bf00 nop + +2000017c : +2000017c: b530 push {r4, r5, lr} +2000017e: 6804 ldr r4, [r0, #0] +20000180: f3ef 8c10 mrs ip, PRIMASK +20000184: b672 cpsid i +20000186: e8d4 efcf ldaexb lr, [r4] +2000018a: 2501 movs r5, #1 +2000018c: f1be 0f00 cmp.w lr, #0 +20000190: d1f9 bne.n 20000186 +20000192: e8c4 5f4e strexb lr, r5, [r4] +20000196: f1be 0f00 cmp.w lr, #0 +2000019a: d1f4 bne.n 20000186 +2000019c: f3bf 8f5f dmb sy +200001a0: f990 4004 ldrsb.w r4, [r0, #4] +200001a4: 6805 ldr r5, [r0, #0] +200001a6: 2c00 cmp r4, #0 +200001a8: db10 blt.n 200001cc +200001aa: 2100 movs r1, #0 +200001ac: e8c5 1f8f stlb r1, [r5] +200001b0: f38c 8810 msr PRIMASK, ip +200001b4: f04f 4550 mov.w r5, #3489660928 @ 0xd0000000 +200001b8: f995 5000 ldrsb.w r5, [r5] +200001bc: 42a5 cmp r5, r4 +200001be: d101 bne.n 200001c4 +200001c0: 4608 mov r0, r1 +200001c2: bd30 pop {r4, r5, pc} +200001c4: e8bd 4030 ldmia.w sp!, {r4, r5, lr} +200001c8: f7ff bfa2 b.w 20000110 +200001cc: f04f 4250 mov.w r2, #3489660928 @ 0xd0000000 +200001d0: 6812 ldr r2, [r2, #0] +200001d2: 2300 movs r3, #0 +200001d4: 7102 strb r2, [r0, #4] +200001d6: e8c5 3f8f stlb r3, [r5] +200001da: f38c 8810 msr PRIMASK, ip +200001de: 2001 movs r0, #1 +200001e0: bd30 pop {r4, r5, pc} +200001e2: bf00 nop + +200001e4 : +200001e4: 6803 ldr r3, [r0, #0] +200001e6: f3ef 8210 mrs r2, PRIMASK +200001ea: b672 cpsid i +200001ec: e8d3 cfcf ldaexb ip, [r3] +200001f0: 2101 movs r1, #1 +200001f2: f1bc 0f00 cmp.w ip, #0 +200001f6: d1f9 bne.n 200001ec +200001f8: e8c3 1f4c strexb ip, r1, [r3] +200001fc: f1bc 0f00 cmp.w ip, #0 +20000200: d1f4 bne.n 200001ec +20000202: f3bf 8f5f dmb sy +20000206: f04f 0cff mov.w ip, #255 @ 0xff +2000020a: 2300 movs r3, #0 +2000020c: 6801 ldr r1, [r0, #0] +2000020e: f880 c004 strb.w ip, [r0, #4] +20000212: e8c1 3f8f stlb r3, [r1] +20000216: f382 8810 msr PRIMASK, r2 +2000021a: bf40 sev +2000021c: 4770 bx lr +2000021e: bf00 nop + +20000220 <__aeabi_uldivmod>: +20000220: b953 cbnz r3, 20000238 <__aeabi_uldivmod+0x18> +20000222: b94a cbnz r2, 20000238 <__aeabi_uldivmod+0x18> +20000224: 2900 cmp r1, #0 +20000226: bf08 it eq +20000228: 2800 cmpeq r0, #0 +2000022a: bf1c itt ne +2000022c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff +20000230: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff +20000234: f000 b9b2 b.w 2000059c <__aeabi_idiv0> +20000238: f1ad 0c08 sub.w ip, sp, #8 +2000023c: e96d ce04 strd ip, lr, [sp, #-16]! +20000240: f000 f806 bl 20000250 <__udivmoddi4> +20000244: f8dd e004 ldr.w lr, [sp, #4] +20000248: e9dd 2302 ldrd r2, r3, [sp, #8] +2000024c: b004 add sp, #16 +2000024e: 4770 bx lr + +20000250 <__udivmoddi4>: +20000250: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} +20000254: 468c mov ip, r1 +20000256: 9e09 ldr r6, [sp, #36] @ 0x24 +20000258: 4604 mov r4, r0 +2000025a: 460f mov r7, r1 +2000025c: 2b00 cmp r3, #0 +2000025e: d148 bne.n 200002f2 <__udivmoddi4+0xa2> +20000260: 428a cmp r2, r1 +20000262: 4615 mov r5, r2 +20000264: d95e bls.n 20000324 <__udivmoddi4+0xd4> +20000266: fab2 f382 clz r3, r2 +2000026a: b13b cbz r3, 2000027c <__udivmoddi4+0x2c> +2000026c: f1c3 0220 rsb r2, r3, #32 +20000270: 409f lsls r7, r3 +20000272: 409d lsls r5, r3 +20000274: 409c lsls r4, r3 +20000276: fa20 f202 lsr.w r2, r0, r2 +2000027a: 4317 orrs r7, r2 +2000027c: ea4f 4e15 mov.w lr, r5, lsr #16 +20000280: fa1f fc85 uxth.w ip, r5 +20000284: 0c22 lsrs r2, r4, #16 +20000286: fbb7 f1fe udiv r1, r7, lr +2000028a: fb0e 7711 mls r7, lr, r1, r7 +2000028e: fb01 f00c mul.w r0, r1, ip +20000292: ea42 4207 orr.w r2, r2, r7, lsl #16 +20000296: 4290 cmp r0, r2 +20000298: d907 bls.n 200002aa <__udivmoddi4+0x5a> +2000029a: 18aa adds r2, r5, r2 +2000029c: f101 37ff add.w r7, r1, #4294967295 @ 0xffffffff +200002a0: d202 bcs.n 200002a8 <__udivmoddi4+0x58> +200002a2: 4290 cmp r0, r2 +200002a4: f200 8158 bhi.w 20000558 <__udivmoddi4+0x308> +200002a8: 4639 mov r1, r7 +200002aa: 1a12 subs r2, r2, r0 +200002ac: b2a4 uxth r4, r4 +200002ae: fbb2 f0fe udiv r0, r2, lr +200002b2: fb0e 2210 mls r2, lr, r0, r2 +200002b6: fb00 fc0c mul.w ip, r0, ip +200002ba: ea44 4402 orr.w r4, r4, r2, lsl #16 +200002be: 45a4 cmp ip, r4 +200002c0: d90b bls.n 200002da <__udivmoddi4+0x8a> +200002c2: 192c adds r4, r5, r4 +200002c4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +200002c8: bf2c ite cs +200002ca: 2701 movcs r7, #1 +200002cc: 2700 movcc r7, #0 +200002ce: 45a4 cmp ip, r4 +200002d0: d902 bls.n 200002d8 <__udivmoddi4+0x88> +200002d2: 2f00 cmp r7, #0 +200002d4: f000 8143 beq.w 2000055e <__udivmoddi4+0x30e> +200002d8: 4610 mov r0, r2 +200002da: ea40 4001 orr.w r0, r0, r1, lsl #16 +200002de: eba4 040c sub.w r4, r4, ip +200002e2: 2100 movs r1, #0 +200002e4: b11e cbz r6, 200002ee <__udivmoddi4+0x9e> +200002e6: 40dc lsrs r4, r3 +200002e8: 2300 movs r3, #0 +200002ea: e9c6 4300 strd r4, r3, [r6] +200002ee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +200002f2: 428b cmp r3, r1 +200002f4: d906 bls.n 20000304 <__udivmoddi4+0xb4> +200002f6: b10e cbz r6, 200002fc <__udivmoddi4+0xac> +200002f8: e9c6 0100 strd r0, r1, [r6] +200002fc: 2100 movs r1, #0 +200002fe: 4608 mov r0, r1 +20000300: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +20000304: fab3 f183 clz r1, r3 +20000308: 2900 cmp r1, #0 +2000030a: d151 bne.n 200003b0 <__udivmoddi4+0x160> +2000030c: 4563 cmp r3, ip +2000030e: f0c0 8116 bcc.w 2000053e <__udivmoddi4+0x2ee> +20000312: 4282 cmp r2, r0 +20000314: f240 8113 bls.w 2000053e <__udivmoddi4+0x2ee> +20000318: 4608 mov r0, r1 +2000031a: 2e00 cmp r6, #0 +2000031c: d0e7 beq.n 200002ee <__udivmoddi4+0x9e> +2000031e: e9c6 4700 strd r4, r7, [r6] +20000322: e7e4 b.n 200002ee <__udivmoddi4+0x9e> +20000324: 2a00 cmp r2, #0 +20000326: f000 80af beq.w 20000488 <__udivmoddi4+0x238> +2000032a: fab2 f382 clz r3, r2 +2000032e: 2b00 cmp r3, #0 +20000330: f040 80c2 bne.w 200004b8 <__udivmoddi4+0x268> +20000334: 1a8a subs r2, r1, r2 +20000336: ea4f 4e15 mov.w lr, r5, lsr #16 +2000033a: b2af uxth r7, r5 +2000033c: 2101 movs r1, #1 +2000033e: 0c20 lsrs r0, r4, #16 +20000340: fbb2 fcfe udiv ip, r2, lr +20000344: fb0e 221c mls r2, lr, ip, r2 +20000348: ea40 4202 orr.w r2, r0, r2, lsl #16 +2000034c: fb07 f00c mul.w r0, r7, ip +20000350: 4290 cmp r0, r2 +20000352: d90e bls.n 20000372 <__udivmoddi4+0x122> +20000354: 18aa adds r2, r5, r2 +20000356: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff +2000035a: bf2c ite cs +2000035c: f04f 0901 movcs.w r9, #1 +20000360: f04f 0900 movcc.w r9, #0 +20000364: 4290 cmp r0, r2 +20000366: d903 bls.n 20000370 <__udivmoddi4+0x120> +20000368: f1b9 0f00 cmp.w r9, #0 +2000036c: f000 80f0 beq.w 20000550 <__udivmoddi4+0x300> +20000370: 46c4 mov ip, r8 +20000372: 1a12 subs r2, r2, r0 +20000374: b2a4 uxth r4, r4 +20000376: fbb2 f0fe udiv r0, r2, lr +2000037a: fb0e 2210 mls r2, lr, r0, r2 +2000037e: fb00 f707 mul.w r7, r0, r7 +20000382: ea44 4402 orr.w r4, r4, r2, lsl #16 +20000386: 42a7 cmp r7, r4 +20000388: d90e bls.n 200003a8 <__udivmoddi4+0x158> +2000038a: 192c adds r4, r5, r4 +2000038c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff +20000390: bf2c ite cs +20000392: f04f 0e01 movcs.w lr, #1 +20000396: f04f 0e00 movcc.w lr, #0 +2000039a: 42a7 cmp r7, r4 +2000039c: d903 bls.n 200003a6 <__udivmoddi4+0x156> +2000039e: f1be 0f00 cmp.w lr, #0 +200003a2: f000 80d2 beq.w 2000054a <__udivmoddi4+0x2fa> +200003a6: 4610 mov r0, r2 +200003a8: 1be4 subs r4, r4, r7 +200003aa: ea40 400c orr.w r0, r0, ip, lsl #16 +200003ae: e799 b.n 200002e4 <__udivmoddi4+0x94> +200003b0: f1c1 0520 rsb r5, r1, #32 +200003b4: 408b lsls r3, r1 +200003b6: fa0c f401 lsl.w r4, ip, r1 +200003ba: fa00 f901 lsl.w r9, r0, r1 +200003be: fa22 f705 lsr.w r7, r2, r5 +200003c2: fa2c fc05 lsr.w ip, ip, r5 +200003c6: 408a lsls r2, r1 +200003c8: 431f orrs r7, r3 +200003ca: fa20 f305 lsr.w r3, r0, r5 +200003ce: 0c38 lsrs r0, r7, #16 +200003d0: 4323 orrs r3, r4 +200003d2: fa1f fe87 uxth.w lr, r7 +200003d6: 0c1c lsrs r4, r3, #16 +200003d8: fbbc f8f0 udiv r8, ip, r0 +200003dc: fb00 cc18 mls ip, r0, r8, ip +200003e0: ea44 440c orr.w r4, r4, ip, lsl #16 +200003e4: fb08 fc0e mul.w ip, r8, lr +200003e8: 45a4 cmp ip, r4 +200003ea: d90e bls.n 2000040a <__udivmoddi4+0x1ba> +200003ec: 193c adds r4, r7, r4 +200003ee: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff +200003f2: bf2c ite cs +200003f4: f04f 0b01 movcs.w fp, #1 +200003f8: f04f 0b00 movcc.w fp, #0 +200003fc: 45a4 cmp ip, r4 +200003fe: d903 bls.n 20000408 <__udivmoddi4+0x1b8> +20000400: f1bb 0f00 cmp.w fp, #0 +20000404: f000 80b8 beq.w 20000578 <__udivmoddi4+0x328> +20000408: 46d0 mov r8, sl +2000040a: eba4 040c sub.w r4, r4, ip +2000040e: fa1f fc83 uxth.w ip, r3 +20000412: fbb4 f3f0 udiv r3, r4, r0 +20000416: fb00 4413 mls r4, r0, r3, r4 +2000041a: fb03 fe0e mul.w lr, r3, lr +2000041e: ea4c 4404 orr.w r4, ip, r4, lsl #16 +20000422: 45a6 cmp lr, r4 +20000424: d90e bls.n 20000444 <__udivmoddi4+0x1f4> +20000426: 193c adds r4, r7, r4 +20000428: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff +2000042c: bf2c ite cs +2000042e: f04f 0c01 movcs.w ip, #1 +20000432: f04f 0c00 movcc.w ip, #0 +20000436: 45a6 cmp lr, r4 +20000438: d903 bls.n 20000442 <__udivmoddi4+0x1f2> +2000043a: f1bc 0f00 cmp.w ip, #0 +2000043e: f000 809f beq.w 20000580 <__udivmoddi4+0x330> +20000442: 4603 mov r3, r0 +20000444: ea43 4008 orr.w r0, r3, r8, lsl #16 +20000448: eba4 040e sub.w r4, r4, lr +2000044c: fba0 ec02 umull lr, ip, r0, r2 +20000450: 4564 cmp r4, ip +20000452: 4673 mov r3, lr +20000454: 46e0 mov r8, ip +20000456: d302 bcc.n 2000045e <__udivmoddi4+0x20e> +20000458: d107 bne.n 2000046a <__udivmoddi4+0x21a> +2000045a: 45f1 cmp r9, lr +2000045c: d205 bcs.n 2000046a <__udivmoddi4+0x21a> +2000045e: ebbe 0302 subs.w r3, lr, r2 +20000462: eb6c 0c07 sbc.w ip, ip, r7 +20000466: 3801 subs r0, #1 +20000468: 46e0 mov r8, ip +2000046a: b15e cbz r6, 20000484 <__udivmoddi4+0x234> +2000046c: ebb9 0203 subs.w r2, r9, r3 +20000470: eb64 0408 sbc.w r4, r4, r8 +20000474: fa04 f505 lsl.w r5, r4, r5 +20000478: fa22 f301 lsr.w r3, r2, r1 +2000047c: 40cc lsrs r4, r1 +2000047e: 431d orrs r5, r3 +20000480: e9c6 5400 strd r5, r4, [r6] +20000484: 2100 movs r1, #0 +20000486: e732 b.n 200002ee <__udivmoddi4+0x9e> +20000488: 0842 lsrs r2, r0, #1 +2000048a: 462f mov r7, r5 +2000048c: 084b lsrs r3, r1, #1 +2000048e: 46ac mov ip, r5 +20000490: ea42 72c1 orr.w r2, r2, r1, lsl #31 +20000494: 46ae mov lr, r5 +20000496: 07c4 lsls r4, r0, #31 +20000498: 0c11 lsrs r1, r2, #16 +2000049a: b292 uxth r2, r2 +2000049c: ea41 4103 orr.w r1, r1, r3, lsl #16 +200004a0: ea42 4201 orr.w r2, r2, r1, lsl #16 +200004a4: fbb1 f1f5 udiv r1, r1, r5 +200004a8: fbb3 f0f5 udiv r0, r3, r5 +200004ac: 231f movs r3, #31 +200004ae: eba2 020c sub.w r2, r2, ip +200004b2: ea41 4100 orr.w r1, r1, r0, lsl #16 +200004b6: e742 b.n 2000033e <__udivmoddi4+0xee> +200004b8: 409d lsls r5, r3 +200004ba: f1c3 0220 rsb r2, r3, #32 +200004be: 4099 lsls r1, r3 +200004c0: 409c lsls r4, r3 +200004c2: fa2c fc02 lsr.w ip, ip, r2 +200004c6: ea4f 4e15 mov.w lr, r5, lsr #16 +200004ca: fa20 f202 lsr.w r2, r0, r2 +200004ce: b2af uxth r7, r5 +200004d0: fbbc f8fe udiv r8, ip, lr +200004d4: 430a orrs r2, r1 +200004d6: fb0e cc18 mls ip, lr, r8, ip +200004da: 0c11 lsrs r1, r2, #16 +200004dc: ea41 410c orr.w r1, r1, ip, lsl #16 +200004e0: fb08 fc07 mul.w ip, r8, r7 +200004e4: 458c cmp ip, r1 +200004e6: d950 bls.n 2000058a <__udivmoddi4+0x33a> +200004e8: 1869 adds r1, r5, r1 +200004ea: f108 30ff add.w r0, r8, #4294967295 @ 0xffffffff +200004ee: bf2c ite cs +200004f0: f04f 0901 movcs.w r9, #1 +200004f4: f04f 0900 movcc.w r9, #0 +200004f8: 458c cmp ip, r1 +200004fa: d902 bls.n 20000502 <__udivmoddi4+0x2b2> +200004fc: f1b9 0f00 cmp.w r9, #0 +20000500: d030 beq.n 20000564 <__udivmoddi4+0x314> +20000502: eba1 010c sub.w r1, r1, ip +20000506: fbb1 f8fe udiv r8, r1, lr +2000050a: fb08 fc07 mul.w ip, r8, r7 +2000050e: fb0e 1118 mls r1, lr, r8, r1 +20000512: b292 uxth r2, r2 +20000514: ea42 4201 orr.w r2, r2, r1, lsl #16 +20000518: 4562 cmp r2, ip +2000051a: d234 bcs.n 20000586 <__udivmoddi4+0x336> +2000051c: 18aa adds r2, r5, r2 +2000051e: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff +20000522: bf2c ite cs +20000524: f04f 0901 movcs.w r9, #1 +20000528: f04f 0900 movcc.w r9, #0 +2000052c: 4562 cmp r2, ip +2000052e: d2be bcs.n 200004ae <__udivmoddi4+0x25e> +20000530: f1b9 0f00 cmp.w r9, #0 +20000534: d1bb bne.n 200004ae <__udivmoddi4+0x25e> +20000536: f1a8 0102 sub.w r1, r8, #2 +2000053a: 442a add r2, r5 +2000053c: e7b7 b.n 200004ae <__udivmoddi4+0x25e> +2000053e: 1a84 subs r4, r0, r2 +20000540: eb6c 0203 sbc.w r2, ip, r3 +20000544: 2001 movs r0, #1 +20000546: 4617 mov r7, r2 +20000548: e6e7 b.n 2000031a <__udivmoddi4+0xca> +2000054a: 442c add r4, r5 +2000054c: 3802 subs r0, #2 +2000054e: e72b b.n 200003a8 <__udivmoddi4+0x158> +20000550: f1ac 0c02 sub.w ip, ip, #2 +20000554: 442a add r2, r5 +20000556: e70c b.n 20000372 <__udivmoddi4+0x122> +20000558: 3902 subs r1, #2 +2000055a: 442a add r2, r5 +2000055c: e6a5 b.n 200002aa <__udivmoddi4+0x5a> +2000055e: 442c add r4, r5 +20000560: 3802 subs r0, #2 +20000562: e6ba b.n 200002da <__udivmoddi4+0x8a> +20000564: eba5 0c0c sub.w ip, r5, ip +20000568: f1a8 0002 sub.w r0, r8, #2 +2000056c: 4461 add r1, ip +2000056e: fbb1 f8fe udiv r8, r1, lr +20000572: fb08 fc07 mul.w ip, r8, r7 +20000576: e7ca b.n 2000050e <__udivmoddi4+0x2be> +20000578: f1a8 0802 sub.w r8, r8, #2 +2000057c: 443c add r4, r7 +2000057e: e744 b.n 2000040a <__udivmoddi4+0x1ba> +20000580: 3b02 subs r3, #2 +20000582: 443c add r4, r7 +20000584: e75e b.n 20000444 <__udivmoddi4+0x1f4> +20000586: 4641 mov r1, r8 +20000588: e791 b.n 200004ae <__udivmoddi4+0x25e> +2000058a: eba1 010c sub.w r1, r1, ip +2000058e: 4640 mov r0, r8 +20000590: fbb1 f8fe udiv r8, r1, lr +20000594: fb08 fc07 mul.w ip, r8, r7 +20000598: e7b9 b.n 2000050e <__udivmoddi4+0x2be> +2000059a: bf00 nop + +2000059c <__aeabi_idiv0>: +2000059c: 4770 bx lr +2000059e: bf00 nop + +200005a0 <__best_effort_wfe_or_timeout_veneer>: +200005a0: f85f f000 ldr.w pc, [pc] @ 200005a4 <__best_effort_wfe_or_timeout_veneer+0x4> +200005a4: 10000f05 .word 0x10000f05 + +200005a8 : +200005a8: 00000010 .... + +200005ac : +200005ac: 00000000 .word 0x00000000 +200005b0: 00010000 .word 0x00010000 + ... +200005bc: 00020000 .word 0x00020000 + ... +200005c8: 00030000 .word 0x00030000 + ... +200005d4: 00ff0000 .word 0x00ff0000 +200005d8: 00000000 .word 0x00000000 + +200005dc : +200005dc: b501 push {r0, lr} +200005de: 6848 ldr r0, [r1, #4] +200005e0: 3101 adds r1, #1 +200005e2: 468e mov lr, r1 +200005e4: 4700 bx r0 + +200005e6 : +200005e6: 4670 mov r0, lr +200005e8: 3809 subs r0, #9 +200005ea: 4901 ldr r1, [pc, #4] @ (200005f0 ) +200005ec: 4788 blx r1 +200005ee: bd01 pop {r0, pc} +200005f0: 100007a1 .word 0x100007a1 + +200005f4 : + ... +20000608: 20000c88 ... + +2000060c : +2000060c: 100033ed 100034f5 1000343d 10003505 .3...4..=4...5.. +2000061c: 00000000 00000100 ........ + +20000624 : +20000624: 100061a0 .a.. + +20000628 <__malloc_sbrk_base>: +20000628: ffffffff .... + +2000062c <__malloc_trim_threshold>: +2000062c: 00020000 .... + +20000630 <__malloc_av_>: + ... +20000638: 20000630 20000630 20000638 20000638 0.. 0.. 8.. 8.. +20000648: 20000640 20000640 20000648 20000648 @.. @.. H.. H.. +20000658: 20000650 20000650 20000658 20000658 P.. P.. X.. X.. +20000668: 20000660 20000660 20000668 20000668 `.. `.. h.. h.. +20000678: 20000670 20000670 20000678 20000678 p.. p.. x.. x.. +20000688: 20000680 20000680 20000688 20000688 ... ... ... ... +20000698: 20000690 20000690 20000698 20000698 ... ... ... ... +200006a8: 200006a0 200006a0 200006a8 200006a8 ... ... ... ... +200006b8: 200006b0 200006b0 200006b8 200006b8 ... ... ... ... +200006c8: 200006c0 200006c0 200006c8 200006c8 ... ... ... ... +200006d8: 200006d0 200006d0 200006d8 200006d8 ... ... ... ... +200006e8: 200006e0 200006e0 200006e8 200006e8 ... ... ... ... +200006f8: 200006f0 200006f0 200006f8 200006f8 ... ... ... ... +20000708: 20000700 20000700 20000708 20000708 ... ... ... ... +20000718: 20000710 20000710 20000718 20000718 ... ... ... ... +20000728: 20000720 20000720 20000728 20000728 .. .. (.. (.. +20000738: 20000730 20000730 20000738 20000738 0.. 0.. 8.. 8.. +20000748: 20000740 20000740 20000748 20000748 @.. @.. H.. H.. +20000758: 20000750 20000750 20000758 20000758 P.. P.. X.. X.. +20000768: 20000760 20000760 20000768 20000768 `.. `.. h.. h.. +20000778: 20000770 20000770 20000778 20000778 p.. p.. x.. x.. +20000788: 20000780 20000780 20000788 20000788 ... ... ... ... +20000798: 20000790 20000790 20000798 20000798 ... ... ... ... +200007a8: 200007a0 200007a0 200007a8 200007a8 ... ... ... ... +200007b8: 200007b0 200007b0 200007b8 200007b8 ... ... ... ... +200007c8: 200007c0 200007c0 200007c8 200007c8 ... ... ... ... +200007d8: 200007d0 200007d0 200007d8 200007d8 ... ... ... ... +200007e8: 200007e0 200007e0 200007e8 200007e8 ... ... ... ... +200007f8: 200007f0 200007f0 200007f8 200007f8 ... ... ... ... +20000808: 20000800 20000800 20000808 20000808 ... ... ... ... +20000818: 20000810 20000810 20000818 20000818 ... ... ... ... +20000828: 20000820 20000820 20000828 20000828 .. .. (.. (.. +20000838: 20000830 20000830 20000838 20000838 0.. 0.. 8.. 8.. +20000848: 20000840 20000840 20000848 20000848 @.. @.. H.. H.. +20000858: 20000850 20000850 20000858 20000858 P.. P.. X.. X.. +20000868: 20000860 20000860 20000868 20000868 `.. `.. h.. h.. +20000878: 20000870 20000870 20000878 20000878 p.. p.. x.. x.. +20000888: 20000880 20000880 20000888 20000888 ... ... ... ... +20000898: 20000890 20000890 20000898 20000898 ... ... ... ... +200008a8: 200008a0 200008a0 200008a8 200008a8 ... ... ... ... +200008b8: 200008b0 200008b0 200008b8 200008b8 ... ... ... ... +200008c8: 200008c0 200008c0 200008c8 200008c8 ... ... ... ... +200008d8: 200008d0 200008d0 200008d8 200008d8 ... ... ... ... +200008e8: 200008e0 200008e0 200008e8 200008e8 ... ... ... ... +200008f8: 200008f0 200008f0 200008f8 200008f8 ... ... ... ... +20000908: 20000900 20000900 20000908 20000908 ... ... ... ... +20000918: 20000910 20000910 20000918 20000918 ... ... ... ... +20000928: 20000920 20000920 20000928 20000928 .. .. (.. (.. +20000938: 20000930 20000930 20000938 20000938 0.. 0.. 8.. 8.. +20000948: 20000940 20000940 20000948 20000948 @.. @.. H.. H.. +20000958: 20000950 20000950 20000958 20000958 P.. P.. X.. X.. +20000968: 20000960 20000960 20000968 20000968 `.. `.. h.. h.. +20000978: 20000970 20000970 20000978 20000978 p.. p.. x.. x.. +20000988: 20000980 20000980 20000988 20000988 ... ... ... ... +20000998: 20000990 20000990 20000998 20000998 ... ... ... ... +200009a8: 200009a0 200009a0 200009a8 200009a8 ... ... ... ... +200009b8: 200009b0 200009b0 200009b8 200009b8 ... ... ... ... +200009c8: 200009c0 200009c0 200009c8 200009c8 ... ... ... ... +200009d8: 200009d0 200009d0 200009d8 200009d8 ... ... ... ... +200009e8: 200009e0 200009e0 200009e8 200009e8 ... ... ... ... +200009f8: 200009f0 200009f0 200009f8 200009f8 ... ... ... ... +20000a08: 20000a00 20000a00 20000a08 20000a08 ... ... ... ... +20000a18: 20000a10 20000a10 20000a18 20000a18 ... ... ... ... +20000a28: 20000a20 20000a20 20000a28 20000a28 .. .. (.. (.. + +20000a38 <_impure_ptr>: +20000a38: 20000a40 00000000 @.. .... + +20000a40 <_impure_data>: +20000a40: 00000000 20002f68 20002fd0 20003038 ....h/. ./. 80. + ... +20000ad8: 00000001 00000000 abcd330e e66d1234 .........3..4.m. +20000ae8: 0005deec 0000000b 00000000 00000000 ................ + ... + +20000b80 : + ... diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf new file mode 100755 index 0000000..eabd395 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf differ diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf.map b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf.map new file mode 100644 index 0000000..fa03509 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.elf.map @@ -0,0 +1,5453 @@ +Archive member included to satisfy reference by file (symbol) + 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+:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000100000000000000D4 +:106BC0000E33CDAB34126DE6ECDE05000B00000099 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:086C600000000000000000002C +:106C6800D3DEFFFFFE010000FF010000D094FFFF0C +:046C7800793512ABAD +:040000051000014D99 +:00000001FF diff --git a/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.uf2 b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.uf2 new file mode 100644 index 0000000..dc84248 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/build/0x0026a_bootloader.uf2 differ diff --git a/WEEK11/0x0026a_custom-bootloader/build/manifest.bin b/WEEK11/0x0026a_custom-bootloader/build/manifest.bin new file mode 100644 index 0000000..7b734c4 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/build/manifest.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/build/pico_flash_region.ld b/WEEK11/0x0026a_custom-bootloader/build/pico_flash_region.ld new file mode 100644 index 0000000..217ec0d --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/build/pico_flash_region.ld @@ -0,0 +1 @@ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) diff --git a/WEEK11/0x0026a_custom-bootloader/common/include/mbedtls_config.h b/WEEK11/0x0026a_custom-bootloader/common/include/mbedtls_config.h new file mode 100644 index 0000000..12ec622 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/common/include/mbedtls_config.h @@ -0,0 +1,25 @@ +/** + * @file mbedtls_config.h + * @brief Minimal Mbed TLS configuration for the 0x0026a bootloader and app. + * @author Kevin Thomas + * @date 2026 + * + * MIT License + * Copyright (c) 2026 Kevin Thomas + * + * The Pico SDK points MBEDTLS_CONFIG_FILE at pico_mbedtls_config.h, which in + * turn includes this file. Only the AES-128 building blocks needed for CMAC + * authentication and CBC encryption are enabled, keeping the image small. + */ + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +#include + +#define MBEDTLS_AES_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_CMAC_C + +#endif diff --git a/WEEK11/0x0026a_custom-bootloader/manifest.bin b/WEEK11/0x0026a_custom-bootloader/manifest.bin new file mode 100644 index 0000000..7b734c4 Binary files /dev/null and b/WEEK11/0x0026a_custom-bootloader/manifest.bin differ diff --git a/WEEK11/0x0026a_custom-bootloader/pico_sdk_import.cmake b/WEEK11/0x0026a_custom-bootloader/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/WEEK11/0x0026a_custom-bootloader/tools/make_full_uf2.py b/WEEK11/0x0026a_custom-bootloader/tools/make_full_uf2.py new file mode 100755 index 0000000..bf65bea --- /dev/null +++ b/WEEK11/0x0026a_custom-bootloader/tools/make_full_uf2.py @@ -0,0 +1,118 @@ +#!/usr/bin/env python3 +"""Build a single BOOTSEL-draggable UF2 holding the whole secure-boot chain. + +The 0x0026a chain is three separate images at three flash addresses: + + bootloader 0x10000000 (owns the system, verifies the next image) + manifest 0x1001F000 (header + AES-128-CMAC tag) + app 0x10020000 (the signed application) + +The SDK emits a UF2 only for the bootloader, so a bare board would need three +separate flashes. This tool packs all three into ONE UF2 so a single BOOTSEL +drag-and-drop brings the whole device up. + +How it works: + + 1. Lay the three images out in a flat buffer whose offset 0 maps to + 0x10000000, filling the reserved gap between them with 0xFF (erased + flash). + 2. Hand that flat image to picotool as a normal image at 0x10000000. + 3. picotool numbers the blocks, tags them with the rp2350-arm-s family and + injects the RP2350-E10 absolute block that makes the boot ROM write each + block to its absolute address. + +The result is exactly the shape the boot ROM accepts over the BOOTSEL mass +storage interface, and it has been verified on hardware: the ROM accepts the +drag, the bootloader verifies the manifest, and the app runs. +""" + +import argparse +import hashlib +import os +import struct +import subprocess +import sys +import tempfile + +BOOTLOADER_BASE = 0x10000000 +MANIFEST_BASE = 0x1001F000 +APP_BASE = 0x10020000 +FAMILY = "rp2350-arm-s" +PLATFORM = "rp2350" + + +def build_flat(bootloader, manifest, app): + """Lay the three images out flat, offset 0 mapped to 0x10000000.""" + if APP_BASE < MANIFEST_BASE < BOOTLOADER_BASE: + raise SystemExit("address map is not ordered") + size = (APP_BASE - BOOTLOADER_BASE) + len(app) + image = bytearray(b"\xFF" * size) + image[0:len(bootloader)] = bootloader + m_off = MANIFEST_BASE - BOOTLOADER_BASE + image[m_off:m_off + len(manifest)] = manifest + a_off = APP_BASE - BOOTLOADER_BASE + image[a_off:a_off + len(app)] = app + return bytes(image) + + +def convert(flat, out, picotool): + """Run picotool to turn the flat image into an absolute-address UF2.""" + with tempfile.NamedTemporaryFile(suffix=".bin", delete=False) as tmp: + tmp.write(flat) + flat_path = tmp.name + try: + cmd = [ + picotool, "uf2", "convert", flat_path, out, + "-o", hex(BOOTLOADER_BASE), + "--family", FAMILY, + "--platform", PLATFORM, + "--abs-block", + ] + subprocess.run(cmd, check=True) + finally: + os.unlink(flat_path) + + +def verify(out): + """Report the block count and the families present in the UF2.""" + data = open(out, "rb").read() + blocks = [data[i:i + 512] for i in range(0, len(data), 512)] + families = set() + payload = 0 + for blk in blocks: + if len(blk) != 512 or struct.unpack_from(" int: + """Multiply a byte by x in GF(2^8).""" + value <<= 1 + return (value ^ RB) & 0xFF if value & 0x100 else value + + +def _expand_key(key: bytes) -> list[int]: + """Expand a 16-byte key into the 176-byte AES-128 round key schedule.""" + schedule = list(key) + for index in range(16, 176, 4): + word = schedule[index - 4:index] + if index % 16 == 0: + word = word[1:] + word[:1] + word = [SBOX[byte] for byte in word] + word[0] ^= RCON[index // 16 - 1] + for offset in range(4): + schedule.append(schedule[index - 16 + offset] ^ word[offset]) + return schedule + + +def _add_round_key(state: list[int], schedule: list[int]) -> None: + """XOR the round key into the state in place.""" + for index in range(16): + state[index] ^= schedule[index] + + +def _sub_bytes(state: list[int]) -> None: + """Apply the AES S-box to every byte of the state.""" + for index in range(16): + state[index] = SBOX[state[index]] + + +def _shift_rows(state: list[int]) -> None: + """Rotate each row of the AES state left by its row index.""" + for row in range(1, 4): + cells = [state[row + 4 * col] for col in range(4)] + cells = cells[row:] + cells[:row] + for col in range(4): + state[row + 4 * col] = cells[col] + + +def _mix_columns(state: list[int]) -> None: + """Mix each column of the AES state with the fixed AES matrix.""" + for col in range(4): + base = 4 * col + a0, a1, a2, a3 = state[base:base + 4] + total = a0 ^ a1 ^ a2 ^ a3 + state[base + 0] = a0 ^ total ^ _xtime(a0 ^ a1) + state[base + 1] = a1 ^ total ^ _xtime(a1 ^ a2) + state[base + 2] = a2 ^ total ^ _xtime(a2 ^ a3) + state[base + 3] = a3 ^ total ^ _xtime(a3 ^ a0) + + +def aes_encrypt_block(block: bytes, schedule: list[int]) -> bytes: + """Encrypt one 16-byte block with the supplied round key schedule.""" + state = list(block) + _add_round_key(state, schedule) + for round_index in range(1, 10): + _sub_bytes(state) + _shift_rows(state) + _mix_columns(state) + _add_round_key(state, schedule[16 * round_index:]) + _sub_bytes(state) + _shift_rows(state) + _add_round_key(state, schedule[160:]) + return bytes(state) + + +def _double(block: bytes) -> bytes: + """Left-shift a 128-bit big-endian value, folding in the CMAC constant.""" + value = int.from_bytes(block, "big") + value <<= 1 + if block[0] & 0x80: + value ^= RB_128 + return (value & ((1 << 128) - 1)).to_bytes(16, "big") + + +def _subkeys(schedule: list[int]) -> tuple[bytes, bytes]: + """Derive the RFC 4493 K1 and K2 subkeys.""" + k1 = _double(aes_encrypt_block(bytes(16), schedule)) + return k1, _double(k1) + + +def _xor(left: bytes, right: bytes) -> bytes: + """XOR two equal-length byte strings.""" + return bytes(a ^ b for a, b in zip(left, right)) + + +def aes128_cmac(key: bytes, message: bytes) -> bytes: + """Return the RFC 4493 AES-128-CMAC tag of a message.""" + schedule = _expand_key(key) + k1, k2 = _subkeys(schedule) + blocks = [message[i:i + 16] for i in range(0, len(message), 16)] + complete = bool(blocks) and len(blocks[-1]) == 16 + if not complete: + tail = (blocks[-1] + b"\x80") if blocks else b"\x80" + blocks = blocks[:-1] + [tail.ljust(16, b"\x00")] + last = blocks[-1] + last = _xor(last, k1 if complete else k2) + state = bytes(16) + for block in blocks[:-1]: + state = aes_encrypt_block(_xor(state, block), schedule) + return aes_encrypt_block(_xor(state, last), schedule) + + +def build_manifest(app: bytes, app_base: int, key: bytes) -> bytes: + """Assemble the padded manifest sector for an application image.""" + tag = aes128_cmac(key, app) + header = struct.pack(" bytes: + """Decode a hex or UTF-8 key argument into 16 bytes.""" + raw = bytes.fromhex(text) if len(text) == 32 else text.encode() + if len(raw) != 16: + raise argparse.ArgumentTypeError("key must be 16 bytes") + return raw + + +def _read_image(path: str) -> bytes: + """Read an application binary from disk.""" + data = Path(path).read_bytes() + if not data: + raise SystemExit(f"error: {path} is empty") + return data + + +def _cmd_sign(args: argparse.Namespace) -> int: + """Sign an image and write the manifest sector.""" + app = _read_image(args.image) + manifest = build_manifest(app, args.app_base, args.key) + out = Path(args.out) + out.parent.mkdir(parents=True, exist_ok=True) + out.write_bytes(manifest) + tag = manifest[16:32].hex() + print(f"image : {args.image} ({len(app)} bytes)") + print(f"app_base : 0x{args.app_base:08x}") + print(f"cmac tag : {tag}") + print(f"manifest : {out} ({len(manifest)} bytes)") + return 0 + + +def _cmd_verify(args: argparse.Namespace) -> int: + """Recompute the tag and compare it against a manifest on disk.""" + app = _read_image(args.image) + manifest = Path(args.verify).read_bytes() + stored = manifest[16:32] + expected = aes128_cmac(args.key, app) + print(f"stored : {stored.hex()}") + print(f"computed : {expected.hex()}") + if stored != expected: + print("result : MISMATCH") + return 1 + print("result : MATCH") + return 0 + + +def main() -> int: + """Parse arguments and dispatch to sign or verify.""" + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("image", help="raw application .bin to sign") + parser.add_argument("--out", default="manifest.bin", + help="manifest output path (default: manifest.bin)") + parser.add_argument("--app-base", type=lambda v: int(v, 0), + default=DEFAULT_APP_BASE, + help="application base address (default: 0x10020000)") + parser.add_argument("--key", type=_parse_key, default=DEFAULT_KEY, + help="16-byte AES key as text or 32 hex digits") + parser.add_argument("--verify", metavar="MANIFEST", + help="verify an existing manifest instead of signing") + args = parser.parse_args() + if args.verify: + return _cmd_verify(args) + return _cmd_sign(args) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/WEEK11/WEEK11-BN.md b/WEEK11/WEEK11-BN.md new file mode 100644 index 0000000..26a7640 --- /dev/null +++ b/WEEK11/WEEK11-BN.md @@ -0,0 +1,1891 @@ +# Week 11-BN: Binary Ninja Personal — Hack Structs & Functions with the NEC IR Remote (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get an `.elf` and a raw `.bin` for each +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load each raw `.bin` into Binary Ninja at `0x10000000` +- **Break at `main`** on live silicon, even though `main` can move between programs +- **Hack each running target live** by editing a register and redirecting a string in Binary Ninja +- **Resolve the functions in the Binary Ninja GUI** using the ELF symbol map +- See how the compiler **flattens a C struct into hard-coded immediates** and **inlines every helper function** +- **Patch** the LED pin immediates and the NEC format string, export, convert, and flash +- Understand the security lesson: **the log says one thing while the hardware does another** + +--- + +## How This Guide Works + +Each project builds two files: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table and DWARF | Ground truth for every function address and signature | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into Binary Ninja and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the current `Release` builds. `Release` flattens the LED struct into plain immediates and inlines every `static` helper (`make_default_leds`, `init_led_gpios`, `process_ir_key`, `poll_ir`, and in Project 2 `ir_to_led_number`, `get_led_pin`, `leds_all_off`, `blink_led`, `process_ir_led_command`, `handle_ir_key`, `poll_and_handle_ir`) into `main`. If you build `Debug`, the SDK function addresses move and the helpers stay separate, so nothing lines up. Always build `Release` for this lesson. + +The order is **dynamic first, static second**, twice — once per project: + +1. Break on the live target and prove what the code does. +2. Hack it live in the debugger and watch the behavior change. +3. Resolve the functions in Binary Ninja using the ELF symbol map. +4. Patch the bytes, export, convert, and flash. + +| Project | Prints | Also does | The hacks | +| ------- | ------ | --------- | --------- | +| `0x0023_structures` | `IR receiver on GPIO 5 ready`, then `NEC command: 0xNN` per key | lights LED1/2/3 on GPIO 16/17/18 from the flattened struct | move LED1 to GPIO 18 live; swap LED1↔LED3 pins; rename the `NEC` string | +| `0x0026_functions` | the same, plus `LED N activated on GPIO P` | blinks the mapped LED 3× then holds it | forge the decoded key live; swap LED1↔LED3 pins (log desync); rename the `NEC` string | + +> **The struct disappears.** `simple_led_ctrl_t` has six members (three `uint8_t` pins and three `bool` states), but the optimizer proves it never escapes `main`, so it is never placed in memory. `leds.led1_pin` becomes the literal `16`, `leds.led2_pin` becomes `17`, `leds.led3_pin` becomes `18`, and the `bool` states become register values. That is why you patch **immediates**, not a struct field. + +> **The functions disappear too.** Every `static` helper is inlined, so there is no `process_ir_key` or `blink_led` symbol to rename. You see their bodies directly inside `main`. The only real functions `main` calls are the SDK routines and `ir_init`/`ir_getkey`. + +> **The SVD file lives in `WEEK04`.** If you want the RP2350 peripheral register map for the SIO/GPIO side of the lab, it is `Embedded-Hacking/WEEK04/rp2350.svd` — it is **not** in `WEEK11`. + +### Background: the NEC IR remote in one paragraph + +An IR receiver on **GPIO 5** demodulates a 38 kHz carrier and presents the NEC frame as a digital mark/space train. `ir_getkey()` waits for the 9 ms leader + 4.5 ms space, samples 32 bits by timing the marks, then validates that the address and command pairs are bitwise inverses. It returns the **command byte** (`0x0C`, `0x18`, or `0x5E` for buttons 1, 2, 3) or `-1`. `main` maps that byte to one of three LEDs on **GPIO 16 (red), 17 (green), 18 (yellow)**. Because the struct is flattened, that mapping is a set of hard-coded pin numbers in the loop — exactly what we patch. + +--- + +## Part 1: Build, Flash, and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **Binary Ninja Personal** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + +```bash +brew install cmake ninja +``` + +- Install **Binary Ninja Personal** and complete its license activation. +- Install the **Arm GNU Toolchain**, or let the VS Code Pico extension manage it. + +**Linux x64** + +```bash +sudo apt install cmake ninja-build gcc-arm-none-eabi libnewlib-arm-none-eabi git python3 openocd minicom +``` + +- Install **Binary Ninja Personal** and complete its license activation. + +### Step 2: Verify your tools are the right architecture (do not skip this) + +On **macOS Apple Silicon**, the most common failure is an Intel `x86_64` tool on your `PATH`: + +``` +zsh: bad CPU type in executable: cmake +``` + +You may have **two Homebrews**: the arm64 one at `/opt/homebrew` and the Intel one at `/usr/local`. If `/usr/local/bin` wins, every `brew` tool is x86_64. Check: + +```bash +file "$(which cmake)" +file "$(which ninja)" +file "$(which arm-none-eabi-gdb)" +file "$(which arm-none-eabi-nm)" +file "$(which openocd)" +``` + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + +To make it permanent, add that `export` to `~/.zshrc`. Do not use Rosetta as a fix; OpenOCD and GDB are exactly the kind of programs where a translation layer produces failures that look like debugger bugs. + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x0023_structures/` and once inside `0x0026_functions/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point Binary Ninja at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so Binary Ninja never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the Binary Ninja console**, so the whole build -> patch -> flash loop stays inside Binary Ninja. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x0023_structures/build/0x0023_structures.elf` and `.bin` — `.bin` is **16372** bytes (`0x3ff4`) +- `0x0026_functions/build/0x0026_functions.elf` and `.bin` — `.bin` is **16476** bytes (`0x405c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin` | +| Linux x64 | `/usr` | + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0023_structures.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0026_functions.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0023_structures.elf | Select-String ' [Tt] ' +arm-none-eabi-nm -n --defined-only build\0x0026_functions.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. The signatures below come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Project 1 — `0x0023_structures` — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (struct flattened, all helpers inlined) | +| `0x100002cc` | `ir_init` | `void ir_init(uint8_t)` | the `ir.c` receiver init | +| `0x100002f4` | `ir_getkey` | `int ir_getkey(void)` | the blocking NEC decoder (timing helpers inlined) | + +**Project 1 — the GPIO, UART, stdio, and `printf` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100004e8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000524` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull-up/down (used by `ir_init`) | +| `0x1000054c` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | +| `0x10000fa8` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000118c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (NEC timing) | +| `0x100011a0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001220` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x100013f4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x1000310c` | `exit` | `void exit(int)` | C runtime exit | +| `0x10003114` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003140` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003250` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000333c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003364` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100033f4` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (adjacent stdio family) | +| `0x10003430` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100034f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (both prints) | +| `0x100036b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100037f0` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**Project 2 — `0x0026_functions` — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (struct flattened, all helpers inlined) | +| `0x10000318` | `ir_init` | `void ir_init(uint8_t)` | the `ir.c` receiver init | +| `0x10000340` | `ir_getkey` | `int ir_getkey(void)` | the blocking NEC decoder (timing helpers inlined) | + +**Project 2 — the GPIO, UART, stdio, and `printf` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000534` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000570` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull-up/down (used by `ir_init`) | +| `0x10000598` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | +| `0x10000ff0` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x100011d4` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (NEC timing) | +| `0x100011e8` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001268` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x1000143c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x10003154` | `exit` | `void exit(int)` | C runtime exit | +| `0x1000315c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003188` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003298` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10003384` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100033ac` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x1000343c` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (adjacent stdio family) | +| `0x10003478` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x1000353c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (all three prints) | +| `0x100036f8` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003838` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +> **`main` is `0x10000234` in both projects.** Both programs put `main` at the same address because the startup code and the linker layout are identical; only the body of `main` and the functions after it move. In a `Debug` build the helpers stay separate and `main` moves — another reason to build `Release`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. The `__wrap_puts` symbol exists in the image (the stdio family always does), but our `printf` path does not call it. + +### Step 5: Flash Project 1 and confirm the NEC/LED behavior + +A `.bin` has no headers, so OpenOCD must be told the base address `0x10000000`. From the repository root: + +**macOS Apple Silicon / Linux x64:** + +```bash +./flash.sh 0x0023_structures/build/0x0023_structures.bin +``` + +**Windows x64 (PowerShell):** + +```powershell +.\flash.ps1 -Bin 0x0023_structures\build\0x0023_structures.bin +``` + +**Or flash from the Binary Ninja console:** + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0023_structures", "build", "0x0023_structures.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0023_structures", "build", "0x0023_structures.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 16372 bytes ...` and `** Verified OK **`. Open a serial monitor at **115200** baud: + +- **Windows x64:** PuTTY -> Connection type **Serial**, the Pico's COM port, speed `115200`. +- **macOS Apple Silicon:** `screen /dev/tty.usbmodem* 115200` (quit with `Ctrl-A` then `K`). +- **Linux x64:** `minicom -D /dev/ttyACM0 -b 115200`. + +On reset it prints the banner once, then a line for every button press: + +``` +IR receiver on GPIO 5 ready +NEC command: 0x0C <- button "1" -> red LED (GPIO 16) +NEC command: 0x18 <- button "2" -> green LED (GPIO 17) +NEC command: 0x5E <- button "3" -> yellow LED (GPIO 18) +``` + +### Step 6: Flash Project 2 and confirm the blink behavior + +```bash +# macOS / Linux +./flash.sh 0x0026_functions/build/0x0026_functions.bin +``` +```powershell +# Windows +.\flash.ps1 -Bin 0x0026_functions\build\0x0026_functions.bin +``` + +**Or flash from the Binary Ninja console** (same form, pointing at the Project 2 `.bin`): + +**macOS / Linux:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0026_functions", "build", "0x0026_functions.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +**Windows:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +bin_path = os.path.join(root, "0x0026_functions", "build", "0x0026_functions.bin") +log = os.path.join(os.path.dirname(bin_path), "flash.log") +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first +subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("flashing in the background; log:", log) +``` + +Wait for `wrote 16476 bytes ...`. The serial monitor shows the banner, then for each button: + +``` +IR receiver on GPIO 5 ready +NEC command: 0x0C +LED 1 activated on GPIO 16 <- red LED blinks 3x, then holds on +NEC command: 0x18 +LED 2 activated on GPIO 17 <- green LED blinks 3x, then holds on +NEC command: 0x5E +LED 3 activated on GPIO 18 <- yellow LED blinks 3x, then holds on +``` + +> **Watch the two lines together.** The `LED N activated on GPIO P` line is built from the struct's *pin constants*, which the compiler hard-coded. Later we change the pin the loop actually drives but leave the print constant alone — that is the **log desynchronization** this week is about. + +--- + +## Part 2: Load the Raw `.bin` into Binary Ninja (Project 1) + +Start from a fresh Binary Ninja state. If you already have a `.bndb` for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into Binary Ninja + +A raw `.bin` has no headers, so Binary Ninja cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, Binary Ninja may load it at address `0x0` with a guessed architecture, and every address in this lesson will be wrong. + +1. Choose `File -> Open with Options...` (do **not** use plain `File -> Open`). +2. Select `0x0023_structures/build/0x0023_structures.bin`. +3. In the loader options, set: + - **Architecture:** `thumb2` (the ARMv7-M / ARMv8-M Thumb-2 architecture, which covers the Cortex-M33) + - **Platform:** `thumb2` + - **Base Address:** `0x10000000` (the XIP flash base) +4. Click **Open**. + +Binary Ninja analyzes the image and opens the linear view. + +**Verify the load before going further.** Press `G`, type `0x10000000`, and read the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you instead see data at `0x00000000`, or a vector word without bit 0 set, close the tab and repeat with `Open with Options`. The Cortex-M33 only executes Thumb-2, so `thumb2` is the only correct architecture. + +> **Console equivalent:** +> ```python +> load("0x0023_structures/build/0x0023_structures.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +### Step 8: Save it as a Binary Ninja database (`.bndb`) + +Binary Ninja never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.bndb`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x0023_structures.bndb`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +| File | Role | +| ---- | ---- | +| `0x0023_structures.bin` | the raw firmware image; Binary Ninja never modifies it | +| `0x0023_structures.bndb` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.bndb`**, not the `.bin`; that restores all your work. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. Breakpoints are set from the GUI through the GDB MI adapter — see Step 13. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Dynamic — Break at `main` and Hack Live (Project 1) + +### Step 10: Start OpenOCD as a live debug server + +Make sure no other OpenOCD is running; a forgotten server holds port `3333`. + +**macOS / Linux:** + +```bash +ps aux | grep -i openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process | Where-Object { $_.ProcessName -like '*openocd*' } +``` + +Stop any leftover server gracefully: + +**macOS / Linux:** + +```bash +pkill -TERM -f openocd +``` + +**Windows (PowerShell):** + +```powershell +Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process +``` + +Start the server **parked at `main`**: + +**macOS Apple Silicon / Linux x64:** + +```bash +BP_ADDR=0x10000234 ./debug-server.sh +``` + +**Windows x64 (PowerShell):** + +```powershell +$env:BP_ADDR="0x10000234"; .\debug-server.ps1 +``` + +**Or start it from the Binary Ninja console**, freeing the probe first and launching the server in the background so the console returns immediately: + +**macOS Apple Silicon / Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop any running server first +log = os.path.join(root, "openocd.log") +p = subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) +print("OpenOCD started (pid", p.pid, "); log:", log) +``` + +`Popen` returns in a few milliseconds; the server keeps running in the background. Check `openocd.log` for `Listening on port 3333`, then connect in Step 11. + +Wait for: + +``` +Info : [rp2350.dap.core0] Examination succeed +Startup breakpoint at 0x10000234 (2-byte hardware execute, one-shot). +Info : starting gdb server for rp2350.dap.core0 on 3333 +Info : Listening on port 3333 for gdb connections +``` + +> **`BP_ADDR` parks the core at `main` before any client connects.** The script arms a 2-byte hardware breakpoint and then does the startup `reset run`, so the core runs from the vector table and stops at your address with no debugger attached yet. When Binary Ninja connects a moment later, the first thing it reads is already the truth: `Stopped at 0x10000234`. + +> **This startup stop is single-use.** OpenOCD flushes breakpoints when a client connects, so this one is gone once Binary Ninja attaches — fine for `main`, which only runs once per reset. Every breakpoint after that is set from the Binary Ninja GUI (Step 13) and is repeatable. To stop at `main` again, restart the server with `BP_ADDR` and reconnect. + +> **Exactly one core.** The line must say `core0` and must **not** mention `core1`. Core1 is never started by this firmware; exposing it makes Binary Ninja read core1's reset-state registers, which are not real addresses, and OpenOCD floods the log with `Failed to read memory at 0xf0000000`. The scripts already use `USE_CORE=0`; do not change it. + +> **Windows driver note:** the Debug Probe must use the **WinUSB** driver. If OpenOCD reports `unable to open CMSIS-DAP device`, install it with [Zadig](https://zadig.akeo.ie/) (select `Debug Probe (CMSIS-DAP)` -> WinUSB). + +### Step 11: Connect Binary Ninja to the GDB server + +1. Make sure the image is open and analyzed (Part 2) and the server from Step 10 is running (parked at `main`). +2. Choose `Debugger -> Connect to Remote Process`. +3. In the **adapter** dropdown, select **GDB MI**. +4. In the **connect** settings group, set **IP Address** to `127.0.0.1` and **Port** to `3333`. +5. Set **Full GDB Executable Path** to the `arm-none-eabi-gdb` from the **Arm GNU Toolchain 14.2.rel1**. It ships for all three hosts, and the Raspberry Pi Pico VS Code extension installs that same 14.2.rel1 toolchain (including `arm-none-eabi-gdb`) on all of them: + + | OS | `arm-none-eabi-gdb` path | + | -- | ------------------------ | + | macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin/arm-none-eabi-gdb` (or the Pico extension's `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb`) | + | Windows x64 | `%USERPROFILE%\.pico-sdk\toolchain\14_2_Rel1\bin\arm-none-eabi-gdb.exe` (Pico extension), or `C:\Program Files (x86)\Arm GNU Toolchain arm-none-eabi\14.2 rel1\bin\arm-none-eabi-gdb.exe` | + | Linux x64 | `~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb` (Pico extension), or the `bin/` directory of the extracted `arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi` tarball | +6. Click **Accept**. +7. Restrict the GDB memory map (prevents OpenOCD SWD faults and reconnect loops): + In the bottom console panel, click the **Debugger Console** tab (or `View -> Tabs -> Debugger Console`) and enter: + ```gdb + source pico-gdb-memory.gdb + ``` + *(If not running from the repository root, enter the absolute path to `pico-gdb-memory.gdb`.)* + Confirm `info mem` displays the Flash (`0x10000000 0x10400000 ro`) and SRAM (`0x20000000 0x20082000 rw`) ranges. + +> **Why `source pico-gdb-memory.gdb` is required.** Binary Ninja's register widget automatically previews memory pointed to by registers. When a register contains an unmapped address (such as uninitialized data or constants like `0x69000000`), Binary Ninja probes it. Without a bounded memory map, OpenOCD attempts to read that invalid address over SWD, faults, and reconnects the debug port (`Info : SWD DPIDR 0x4c013477`). Sourcing `pico-gdb-memory.gdb` sets `inaccessible-by-default on` in GDB, causing GDB to intercept and reject invalid reads locally before any packet reaches OpenOCD, eliminating SWD reconnect storms. + +> **Use the GDB MI adapter.** It launches a real `arm-none-eabi-gdb --interpreter=mi2` and lets Binary Ninja drive it, so breakpoints and stepping go through real GDB — which sends the correct 2-byte breakpoint length. Verified working end to end: connect, GUI breakpoints (**Add Hardware Breakpoint...**, hardware execute), **Step Into** / **Step Over**, and register edits. + +> **Do NOT have any breakpoints set in Binary Ninja before you connect.** With the GDB MI adapter, attaching while Binary Ninja already has a breakpoint **hangs the session**. Start the server parked with `BP_ADDR` (Step 10), connect, and only add hardware breakpoints *after* the connection is up. This is a Binary Ninja bug; it is the single most common GDB MI failure. + +> **The GDB executable path matters.** Use the **14.2.rel1** build on every OS (Windows, macOS, Linux). The 13.3.rel1 build did **not** connect in testing. +> +> **This step is temporary.** Vector35 plans to ship a GDB binary with the GDB MI adapter ([Vector35/debugger#929](https://github.com/Vector35/debugger/issues/929), milestone *Langara*). Once that lands, Binary Ninja provides GDB itself and you will not need to set **Full GDB Executable Path** at all. + +> **Do not pick Corellium.** Binary Ninja's adapter dropdown also lists **Corellium**, which is for Corellium's virtual devices and expects an API token, not a local OpenOCD server. Always read the label back and confirm it says **GDB MI** before clicking **Accept**. + +> **The adapter and port are not saved in the `.bndb`.** Every time you relaunch Binary Ninja you must re-select **GDB MI**, re-enter port `3333`, and re-set the GDB path. + +The target keeps running. Open the **Registers** tab (bug icon) and confirm you see live values. `pc` inside `0x10003xxx` and `sp` just below `0x20082000` are healthy. + +> **If `pc` is `0x00000088`, `0x000000ec`, or `sp` is `0xf0000000`, the session is bad.** Restart the server, then restart Binary Ninja (a server restart while attached leaves Binary Ninja in a stale session), and connect again. + +### Step 12: Find `main` without relying on its address + +`main` can move between programs, so we do not guess it. We follow the one fixed path to it. Press `G` and go to `0x10000000`: + +``` +0x10000000 0x20082000 initial stack pointer (top of SRAM) +0x10000004 0x1000015d reset vector +``` + +Bit 0 of a vector is the Thumb bit, so `0x1000015d` means "start at `0x1000015c`". That is `_reset_handler`. Follow the reset path to `0x10000186`, `platform_entry`: + +```asm +10000186 : +10000186: 4914 ldr r1, [pc, #80] +10000188: 4788 blx r1 +1000018a: 4914 ldr r1, [pc, #80] +1000018c: 4788 blx r1 +1000018e: 4914 ldr r1, [pc, #80] +10000190: 4788 blx r1 +10000192: be00 bkpt 0x0000 +``` + +**The middle `blx` at `0x1000018c` is the call to `main`.** `platform_entry` is byte-identical in both projects, so `0x1000018c` catches `main` no matter where the linker placed it. The literal pool at `0x100001dc` holds `main | 1`; clearing bit 0 gives `0x10000234`. + +### Step 13: Set a hardware breakpoint in the GUI + +With the **GDB MI** adapter, Binary Ninja sets breakpoints through real GDB, which sends the correct 2-byte length, so you set them **in the UI**. There is no command port here. + +#### Where you can stop + +| You want to stop at | Project 1 address | How | Repeatable? | +| --- | --- | --- | --- | +| **`main`** | `0x10000234` | The server starts parked there with `BP_ADDR=0x10000234` (Step 10), so Binary Ninja is already stopped at `main` when it connects. | No — `main` runs once per reset. | +| **First `printf` (`IR receiver...`)** | `0x1000026c` | Set a hardware breakpoint in the GUI, then click **Resume**. | No — runs once before the loop. | +| **Loop `printf` (`NEC command...`)** | `0x1000027c` | Same. | Yes — fires on every key press. | +| **First `gpio_put` (`mcrr`)** | `0x1000028a` | Same — this is where LED1's pin is written. | Yes — fires on every key press. | +| **`ir_getkey` return** | `0x10000274` | Same. | Yes. | + +#### Set a breakpoint in the GUI + +1. Press `G`, type the address (for example `0x1000028a`), and press Enter. +2. Set a **hardware execution** breakpoint at that address, either way: + - `Debugger -> Add Hardware Breakpoint...` — a **hardware execute** (`HE`) breakpoint. **Use this one.** + - click the line and press `F2` (`Debugger -> Toggle Breakpoint`) — a **software** breakpoint. It will **not** work here: the code is in read-only flash, so GDB cannot install it and the core just keeps running. +3. Click **Resume**. The core is already running the loop, so the breakpoint fires on the next key press. Binary Ninja stops with the PC at the address and reports it as a **Breakpoint**. + +> **No breakpoints before you connect.** With GDB MI, a breakpoint set before the connection hangs the session (Step 11). Start parked with `BP_ADDR`, connect, *then* add breakpoints. + +> **Step Over on the raw `.bin` steps *into* calls.** The raw image has no symbol for `__wrap_printf`, `ir_getkey`, or `sleep_ms`, so **Step Over** at a `bl` behaves like **Step Into**. When the lab needs to execute the call and then stop, it moves the breakpoint to the return site and clicks **Resume** instead (Step 14 shows this). + +> **Never use Binary Ninja's Restart button.** On RP2350 it resets and halts inside the boot ROM (`pc=0x88`, `sp=0xf0000000`). To reset cleanly, restart the server with `BP_ADDR` and reconnect. + +### Step 14: HACK IT LIVE — move LED1 from GPIO 16 to GPIO 18 + +`main` loads the constant `16` into `r5` once at `0x10000240`, before the loop, and the loop's first `mcrr` at `0x1000028a` writes the LED1 state to the pin in `r5`. Because `r5` is **never reloaded inside the loop**, changing it once is sticky for every later key press. We break on that `mcrr` and change it live. + +1. Press `G`, go to `0x1000028a` (the first `mcrr`, `gpio_put(r5, ...)` for LED1). +2. Set a **hardware execute** breakpoint there: `Debugger -> Add Hardware Breakpoint...`. (Do not use `F2` — that is a software breakpoint and will not work on read-only flash.) +3. Click **Resume** in Binary Ninja, then press **"1"** on the IR remote. The `ir_getkey` call returns, the `printf` at `0x1000027c` prints `NEC command: 0x0C`, and the breakpoint fires at `0x1000028a`. +4. Open the **Registers** widget (bug icon -> **Registers**). Find `r5`. Its value is `16` (`0x10`) — LED1's pin. +5. **Set `r5` to `18` (`0x12`).** From Binary Ninja's Python console (`Plugins -> Python Console`): + ```python + dbg.set_reg_value("r5", 0x12) # LED1 now drives GPIO 18 + ``` + `dbg.set_reg_value(name, value)` writes one register (returns `True` on success). You can also right-click `r5` in the **Registers** widget, press `E` (edit), type `12`, and press Enter. The widget may not repaint the value, but the write reaches the target. +6. Remove the breakpoint at `0x1000028a` and click **Resume**. The core executes the `mcrr` with `r5 = 18`, so pressing **"1"** now lights the **yellow** LED on GPIO 18 instead of the red LED on GPIO 16. + +Because `r5` is set once and never reloaded, the change sticks for every subsequent key press until you reset. Press **"1"** again: the yellow LED lights again, while the terminal still says `NEC command: 0x0C`. + +> **`r5` is the sticky register here.** If you instead edit `r3` (the state, computed by the `clz` trick) or `r2`, the next iteration recomputes them, so the edit lasts one pass. `r5` is the pin, loaded once, so it is the one worth moving. + +### Step 14b: HACK THE STRING LIVE — change `NEC` to `HACKED` + +The text `"NEC command: 0x%02X\n"` lives in flash (`.rodata`) at `0x100038d0`, and flash is **read-only at runtime** — a debugger write there does not stick. So you cannot overwrite the text in place. Instead you redirect the pointer: at the loop `printf` call, `r0` holds the format-string address, so you point `r0` at a replacement string you place in RAM. + +1. Press `G`, go to `0x1000027c` (the loop `bl __wrap_printf`) and set a **hardware execute** breakpoint. Resume and press **"1"** on the remote. At the stop, `r0 = 0x100038d0` (the `ldr r0, [pc, #76]` at `0x1000027a` just loaded the `"NEC command: 0x%02X\n"` pointer) and `r1 = 0x0C`. +2. Put the replacement string into free RAM at `0x20080000` from the **Python console**: + ```python + dbg.write_memory(0x20080000, b"HACKED: 0x%02X\n\x00") # one %02X, same argument + ``` + `dbg.write_memory(address, bytes)` is Binary Ninja's debugger memory-write API; it returns `True` on success. Keep exactly one `%02X` so `printf` still consumes the key in `r1`. +3. Point `r0` at that string: + ```python + dbg.set_reg_value("r0", 0x20080000) + ``` + (Or right-click `r0` in the **Registers** widget, press `E`, type `20080000`, and press Enter.) +4. Move the breakpoint past the call in the GUI (remove it at `0x1000027c`, set one at `0x10000280`) and click **Resume**. The core runs `printf` with `r0` pointing at your RAM string and `r1 = 0x0C`, so this iteration prints: + ``` + HACKED: 0x0C + ``` + then stops at `0x10000280`. + +Like the pin hack, this is **one iteration only**: the loop reloads `r0` from the literal pool on every pass, so the next key prints `NEC command: ...` again. The permanent version is the static patch in Step 18b. + +### Step 15: Why the hack reverts (and why we patch next) + +Press **Resume**. The loop branches back to `0x10000270`, reloads `r0` from `0x100038d0` at `0x1000027a`, and `r5` stays at `18` only until the next reset (it is loaded once at `0x10000240`). The string edit was one iteration; the pin edit was sticky but lives only in a register. To make the behavior permanent we must patch the bytes — the static pass. + +Press **Pause** to stop the output flood. + +### Step 15b: Kill the debugger and OpenOCD + +The live hack is done. Do this **before** the static pass. + +1. In the **Debugger** sidebar, click the **X** (**Kill**) (or **`Debugger -> Kill`**) to disconnect Binary Ninja. +2. **Kill does not stop the OpenOCD process** — `debug-server.sh` started it separately, and it keeps running and holding the probe. Stop it from the Binary Ninja console: + + **macOS / Linux:** + + ```python + import subprocess + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe + ``` + + **Windows:** + + ```python + import subprocess + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe + ``` + +3. Confirm nothing is left: `pgrep -fl openocd` (macOS/Linux) prints nothing. + +From a terminal it is the same: `pkill -TERM -f openocd`, or `Get-Process openocd | Stop-Process` on Windows. + +--- + +## Part 4: Static — Resolve the Functions in Binary Ninja and Patch (Project 1) + +### Step 16: Resolve the functions in the Binary Ninja GUI + +We now name the functions in Binary Ninja using the ELF symbol map from Step 4. Binary Ninja loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | Binary Ninja action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in Binary Ninja (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003364()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. Binary Ninja parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. + +> **Binary Ninja shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and Binary Ninja's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `ir_init` + +1. `G` -> `0x100002cc`. +2. `Y` -> `void ir_init(uint8_t pin)`. + +It takes a `uint8_t` pin; `main` calls it with `5` (`movs r0, #5`). It opens with `gpio_init(pin)`, then writes the direction and calls `gpio_set_pulls` for the pull-up. + +#### Worked example: `ir_getkey` + +1. `G` -> `0x100002f4`. +2. `Y` -> `int ir_getkey(void)`. + +It returns `-1` on timeout and the command byte otherwise. The NEC timing helpers (`wait_for_level`, `wait_leader`, `read_nec_bit`, `read_32_bits`, `validate_nec_frame`) are all `static` and **inlined** into it, so you will not find them as separate functions. + +#### Worked example: `gpio_init` + +1. `G` -> `0x1000054c`. +2. `Y` -> `void gpio_init(uint gpio)`. + +`main` calls it three times with `16`, `17`, `18` — the flattened struct pins. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x10003364`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100034f4`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init +│ │ └── uart_init ── clock_get_hz, busy_wait_us +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ └── stdio_put_string ── strlen, time_us_64 +├── gpio_init +├── ir_init ── gpio_init, gpio_set_pulls +├── ir_getkey ── time_us_64 (the NEC timing helpers are inlined) +└── __wrap_printf ── __wrap_vprintf +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002cc` | `ir_init` | `void ir_init(uint8_t)` | +| `0x100002f4` | `ir_getkey` | `int ir_getkey(void)` | +| `0x100004e8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000524` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x1000054c` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000fa8` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000118c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011a0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001220` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x100013f4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x1000310c` | `exit` | `void exit(int)` | +| `0x10003114` | `runtime_init` | `void runtime_init(void)` | +| `0x10003140` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003250` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000333c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003364` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100033f4` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003430` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100034f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100037f0` | `strlen` | `size_t strlen(const char*)` | + +> **A `void` return type may not stick — here is the fix.** Binary Ninja treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type Binary Ninja thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into Binary Ninja's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002cc: ("ir_init", "void ir_init(uint8_t)"), +> 0x100002f4: ("ir_getkey", "int ir_getkey(void)"), +> 0x100004e8: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000524: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x1000054c: ("gpio_init", "void gpio_init(uint)"), +> 0x10000fa8: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000118c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011a0: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001220: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x100013f4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x1000310c: ("exit", "void exit(int)"), +> 0x10003114: ("runtime_init", "void runtime_init(void)"), +> 0x10003140: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003250: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000333c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003364: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100033f4: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003430: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x100034f4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036b0: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x100037f0: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, `clock_handle_t`, plus `uint`, `va_list`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first. Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. The whole program is one function because every `static` helper was inlined: + +```asm +10000234
: +10000234: b508 push {r3, lr} +10000236: f003 f895 bl 10003364 +1000023a: 2010 movs r0, #16 +1000023c: f000 f986 bl 1000054c +10000240: 2510 movs r5, #16 +10000242: f04f 0401 mov.w r4, #1 +10000246: ec44 5044 mcrr 0, 4, r5, r4, cr4 +1000024a: 2011 movs r0, #17 +1000024c: f000 f97e bl 1000054c +10000250: 2311 movs r3, #17 +10000252: ec44 3044 mcrr 0, 4, r3, r4, cr4 +10000256: 2012 movs r0, #18 +10000258: f000 f978 bl 1000054c +1000025c: 2312 movs r3, #18 +1000025e: ec44 3044 mcrr 0, 4, r3, r4, cr4 +10000262: 2005 movs r0, #5 +10000264: f000 f832 bl 100002cc +10000268: 2105 movs r1, #5 +1000026a: 4816 ldr r0, [pc, #88] +1000026c: f003 f942 bl 100034f4 <__wrap_printf> +10000270: f000 f840 bl 100002f4 +10000274: 1e04 subs r4, r0, #0 +10000276: db21 blt.n 100002bc +10000278: 4621 mov r1, r4 +1000027a: 4813 ldr r0, [pc, #76] +1000027c: f003 f93a bl 100034f4 <__wrap_printf> +10000280: f1a4 030c sub.w r3, r4, #12 +10000284: fab3 f383 clz r3, r3 +10000288: 095b lsrs r3, r3, #5 +1000028a: ec43 5040 mcrr 0, 4, r5, r3, cr0 +1000028e: f1a4 0218 sub.w r2, r4, #24 +10000292: fab2 f282 clz r2, r2 +10000296: 2311 movs r3, #17 +10000298: 0952 lsrs r2, r2, #5 +1000029a: ec42 3040 mcrr 0, 4, r3, r2, cr0 +1000029e: f1a4 045e sub.w r4, r4, #94 +100002a2: fab4 f484 clz r4, r4 +100002a6: 2312 movs r3, #18 +100002a8: 0964 lsrs r4, r4, #5 +100002aa: ec44 3040 mcrr 0, 4, r3, r4, cr0 +100002ae: 200a movs r0, #10 +100002b0: f000 fe7a bl 10000fa8 +100002b4: f000 f81e bl 100002f4 +100002b8: 1e04 subs r4, r0, #0 +100002ba: dadd bge.n 10000278 +100002bc: 2001 movs r0, #1 +100002be: f000 fe73 bl 10000fa8 +100002c2: e7d5 b.n 10000270 +100002c4: 100038b0 .word 0x100038b0 +100002c8: 100038d0 .word 0x100038d0 +``` + +The decompiler reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + gpio_init(0x10); gpio_set_dir(0x10, 1); // led1_pin = 16 + gpio_init(0x11); gpio_set_dir(0x11, 1); // led2_pin = 17 + gpio_init(0x12); gpio_set_dir(0x12, 1); // led3_pin = 18 + ir_init(5); + __wrap_printf("IR receiver on GPIO %d ready\n", 5); + do + { + int32_t key = ir_getkey(); + if (key >= 0) + { + __wrap_printf("NEC command: 0x%02X\n", key); + mcrr(0x10, key == 0x0c); // led1_pin = 16 + mcrr(0x11, key == 0x18); // led2_pin = 17 + mcrr(0x12, key == 0x5e); // led3_pin = 18 + sleep_ms(10); + } + else + { + sleep_ms(1); + } + } while (true); +} +``` + +- **There is no struct.** `16`, `17`, `18` are immediates; `led1_state` etc. are the `clz`-computed register values. +- The `clz`/`lsrs` pair is how the compiler turns `(key == 0x0C)` into a `0`/`1` without a branch: `sub.w r3, r4, #12` sets the flags, `clz r3, r3` counts leading zeros, `lsrs r3, r3, #5` reduces it to `0` or `1`. +- `0x100002c4` and `0x100002c8` point at `"IR receiver on GPIO %d ready\n"` (`0x100038b0`) and `"NEC command: 0x%02X\n"` (`0x100038d0`) in `.rodata`. + +### Step 18: Patch 1 — swap LED1 and LED3 pins + +The original lesson swaps LED pin assignments. LED1 is the red LED on GPIO 16 and LED3 is the yellow LED on GPIO 18. Swap them so button **"1"** lights yellow and button **"3"** lights red. The two pins are hard-coded immediates: + +| Address | Instruction | Bytes before | Bytes after | Role | +| ------- | ----------- | ------------ | ----------- | ---- | +| `0x10000240` | `movs r5, #16` | `10 25` | `12 25` | LED1's pin (`r5`) 16 -> 18 | +| `0x100002a6` | `movs r3, #18` | `12 23` | `10 23` | LED3's pin (`r3`) 18 -> 16 | + +In the **Hex** view (`View -> Hex`, lock off) change the low byte of each, then right-click `main` -> `Reanalyze`. Or in the Python console: + +```python +bv.write(0x10000240, b"\x12") # movs r5, #18 (LED1 -> GPIO 18) +bv.write(0x100002a6, b"\x10") # movs r3, #16 (LED3 -> GPIO 16) +print(bv.read(0x10000240, 2).hex(" ")) # -> 12 25 +print(bv.read(0x100002a6, 2).hex(" ")) # -> 10 23 +``` + +After reanalysis the loop reads `movs r5, #18` and `movs r3, #16`, so button **"1"** drives GPIO 18 (yellow) and button **"3"** drives GPIO 16 (red). The `NEC command:` log still prints the *command byte*, so the log and the physical LED mapping no longer agree — the log desynchronization. + +### Step 18b: Patch 2 — rename the `NEC` string to `PWN` + +The format string `"NEC command: 0x%02X\n"` starts at `0x100038d0`. Its first three bytes are `4e 45 43` (`NEC`). Change them to `50 57 4e` (`PWN`), leaving the ` command: 0x%02X\n` tail untouched, so the line prints `PWN command: 0x0C`. + +**Option A — Hex view:** go to `0x100038d0` and change the three bytes `4e 45 43` to `50 57 4e`, then reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100038d0, b"PWN") +print(bv.read(0x100038d0, 20)) # -> b'PWN command: 0x%02X\n\x00' +``` + +Keep the replacement exactly three bytes. If you use a shorter string you must pad it, or `%02X` shifts and `printf` reads the wrong argument. A longer string would overwrite the ` command:` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0023_structures", "build"), "0x0023_structures-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16372 /.../build/0x0023_structures-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base Binary Ninja loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3ff4` = 16372). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. + +> **No relative path.** Binary Ninja's Python console runs with a read-only working directory (inside the app bundle), so a relative `open(...)` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/`. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0023_structures-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0023_structures-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the Binary Ninja console** — `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0023_structures", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0023_structures-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` + +### Step 21: Flash and verify the swapped LEDs + +Hold **BOOTSEL**, plug in the Pico 2, and drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console (stop any running OpenOCD first, and use `Popen`, not `run`, so the console is not blocked): + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +bin_path = os.path.join(os.path.join(root, "0x0023_structures", "build"), "0x0023_structures-h.bin") +log = os.path.join(os.path.join(root, "0x0023_structures", "build"), "flash.log") +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first +p = subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) +print("flashing in the background; log:", log) +``` + +Open the serial monitor and press the buttons: + +``` +PWN command: 0x0C <- button "1" now lights the YELLOW LED (GPIO 18) +PWN command: 0x18 <- button "2" still lights the green LED (GPIO 17) +PWN command: 0x5E <- button "3" now lights the RED LED (GPIO 16) +``` + +**Two bytes swapped the LEDs and three bytes renamed the log — no source code.** + +--- + +## Part 5: Reflash Project 2 and Load It into Binary Ninja + +### Step 22: Reflash Project 2 and restart the session + +Part 4 left the Pico running the patched Project 1 image. Put the original Project 2 back and start a fresh session. + +1. Stop any running debug server so the flash script can use the probe: + + ```bash + # macOS / Linux + pkill -TERM -f openocd + ``` + ```powershell + # Windows + Get-Process openocd -ErrorAction SilentlyContinue | Stop-Process + ``` + +2. Flash the original Project 2 image: + + ```bash + # macOS / Linux + ./flash.sh 0x0026_functions/build/0x0026_functions.bin + ``` + ```powershell + # Windows + .\flash.ps1 -Bin 0x0026_functions\build\0x0026_functions.bin + ``` + + **Or do steps 1–2 from the Binary Ninja console:** + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0026_functions", "build", "0x0026_functions.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # free the probe first + subprocess.Popen([os.path.join(root, "flash.sh"), bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("flashing Project 2 in the background; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() # set once (Step 3) + bin_path = os.path.join(root, "0x0026_functions", "build", "0x0026_functions.bin") + log = os.path.join(os.path.dirname(bin_path), "flash.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # free the probe first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "flash.ps1"), "-Bin", bin_path], + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("flashing Project 2 in the background; log:", log) + ``` + +3. Load Project 2 and save its database — see Step 22b. + +Confirm the Pico responds to `1` / `2` / `3` again. + +### Step 22b: Load Project 2 into Binary Ninja and save the database + +Exactly like Steps 7–8, but for Project 2. **Use `File -> Open with Options...`** (not plain `File -> Open`), select `0x0026_functions/build/0x0026_functions.bin`, and set: + +- **Architecture:** `thumb2` +- **Platform:** `thumb2` +- **Base Address:** `0x10000000` + +Click **Open**. Then press `G`, type `0x10000000`, and confirm the first two words: + +``` +0x10000000 0x20082000 initial stack pointer +0x10000004 0x1000015d reset vector (bit 0 = Thumb) +``` + +If you see data at `0x00000000`, close the tab and redo it with `Open with Options`. + +Save it with `File -> Save As...` as `0x0026_functions.bndb` (next to the `.bin`). From now on open the `.bndb`, not the `.bin`; save with `Cmd+S` / `Ctrl+S` after every rename or patch. + +> **Console equivalent:** +> ```python +> load("0x0026_functions/build/0x0026_functions.bin", +> options={"loader.imageBase": 0x10000000, "loader.platform": "thumb2"}) +> ``` + +--- + +## Part 6: Dynamic — Break at `main` and Hack Live (Project 2) + +### Step 23: Break at `main` + +`main` is at `0x10000234` in this project too. Start the server parked at `main` (Step 10 form) and connect with the **GDB MI** adapter (Step 11): + +1. Restart the server parked at `main`: + + **macOS / Linux:** + + ```bash + BP_ADDR=0x10000234 ./debug-server.sh + ``` + ```powershell + # Windows + $env:BP_ADDR="0x10000234"; .\debug-server.ps1 + ``` + + **Or restart it from the Binary Ninja console:** + + **macOS / Linux:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # kill any running server first + subprocess.Popen([os.path.join(root, "debug-server.sh")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT, start_new_session=True) + print("OpenOCD restarted parked at main; log:", log) + ``` + + **Windows:** + + ```python + import os, subprocess + root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() + log = os.path.join(root, "openocd.log") + subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # kill any running server first + subprocess.Popen(["powershell", "-ExecutionPolicy", "Bypass", "-File", + os.path.join(root, "debug-server.ps1")], cwd=root, + env=dict(os.environ, BP_ADDR="0x10000234"), + stdout=open(log, "w"), stderr=subprocess.STDOUT) + print("OpenOCD restarted parked at main; log:", log) + ``` +2. Connect Binary Ninja (Step 11): adapter **GDB MI**, IP `127.0.0.1`, port `3333`. + +The target is already halted at `main` when Binary Ninja connects, and the sidebar reads `Stopped at 0x10000234`. + +### Step 24: Read `main` and find the inlined function bodies + +The whole loop is one function because every helper was inlined. The key difference from Project 1 is the extra `printf` and the blink loop that carries the LED pin in `r5`: + +```asm +10000234
: +10000234: b580 push {r7, lr} +10000236: f003 f8b9 bl 100033ac +1000023a: 2010 movs r0, #16 +1000023c: f000 f9ac bl 10000598 +10000240: f04f 0701 mov.w r7, #1 +10000244: 2310 movs r3, #16 +10000246: ec47 3044 mcrr 0, 4, r3, r7, cr4 +1000024a: 2011 movs r0, #17 +1000024c: f000 f9a4 bl 10000598 +10000250: 2311 movs r3, #17 +10000252: ec47 3044 mcrr 0, 4, r3, r7, cr4 +10000256: 2012 movs r0, #18 +10000258: f000 f99e bl 10000598 +1000025c: 2312 movs r3, #18 +1000025e: ec47 3044 mcrr 0, 4, r3, r7, cr4 +10000262: 2005 movs r0, #5 +10000264: f000 f858 bl 10000318 +10000268: 2105 movs r1, #5 +1000026a: 4828 ldr r0, [pc, #160] +1000026c: f003 f966 bl 1000353c <__wrap_printf> +10000270: f04f 0600 mov.w r6, #0 +10000274: f000 f864 bl 10000340 +10000278: 1e04 subs r4, r0, #0 +1000027a: db19 blt.n 100002b0 +1000027c: 4621 mov r1, r4 +1000027e: 4824 ldr r0, [pc, #144] +10000280: f003 f95c bl 1000353c <__wrap_printf> +10000284: 2510 movs r5, #16 +10000286: ec46 5040 mcrr 0, 4, r5, r6, cr0 +1000028a: 2311 movs r3, #17 +1000028c: ec46 3040 mcrr 0, 4, r3, r6, cr0 +10000290: 2212 movs r2, #18 +10000292: ec46 2040 mcrr 0, 4, r2, r6, cr0 +10000296: 2c0c cmp r4, #12 +10000298: d00e beq.n 100002b8 +1000029a: 2c18 cmp r4, #24 +1000029c: d02e beq.n 100002fc +1000029e: 2c5e cmp r4, #94 +100002a0: d030 beq.n 10000304 +100002a2: 200a movs r0, #10 +100002a4: f000 fea4 bl 10000ff0 +100002a8: f000 f84a bl 10000340 +100002ac: 1e04 subs r4, r0, #0 +100002ae: dae5 bge.n 1000027c +100002b0: 2001 movs r0, #1 +100002b2: f000 fe9d bl 10000ff0 +100002b6: e7dd b.n 10000274 +100002b8: f04f 0801 mov.w r8, #1 +100002bc: 2403 movs r4, #3 +100002be: ec47 5040 mcrr 0, 4, r5, r7, cr0 +100002c2: 2032 movs r0, #50 +100002c4: f000 fe94 bl 10000ff0 +100002c8: ec46 5040 mcrr 0, 4, r5, r6, cr0 +100002cc: 2032 movs r0, #50 +100002ce: f000 fe8f bl 10000ff0 +100002d2: 1e63 subs r3, r4, #1 +100002d4: f013 04ff ands.w r4, r3, #255 +100002d8: d1f1 bne.n 100002be +100002da: ec47 5040 mcrr 0, 4, r5, r7, cr0 +100002de: f1b8 0f01 cmp.w r8, #1 +100002e2: d009 beq.n 100002f8 +100002e4: f1b8 0f02 cmp.w r8, #2 +100002e8: bf14 ite ne +100002ea: 2212 movne r2, #18 +100002ec: 2211 moveq r2, #17 +100002ee: 4641 mov r1, r8 +100002f0: 4808 ldr r0, [pc, #32] +100002f2: f003 f923 bl 1000353c <__wrap_printf> +100002f6: e7d4 b.n 100002a2 +100002f8: 2210 movs r2, #16 +100002fa: e7f8 b.n 100002ee +100002fc: 461d mov r5, r3 +100002fe: f04f 0802 mov.w r8, #2 +10000302: e7db b.n 100002bc +10000304: 4615 mov r5, r2 +10000306: f04f 0803 mov.w r8, #3 +1000030a: e7d7 b.n 100002bc +1000030c: 100038f8 .word 0x100038f8 +10000310: 10003918 .word 0x10003918 +10000314: 10003930 .word 0x10003930 +``` + +What the inlining produced: + +- **`leds_all_off(&leds)`** is the three `mcrr` writes at `0x10000286`, `0x1000028c`, `0x10000292`, all using `r6 = 0` (`mov.w r6, #0` at `0x10000270`). +- **`ir_to_led_number`** is the `cmp`/`beq` chain at `0x10000296`–`0x100002a0` (`12`, `24`, `94`). +- **`get_led_pin`** is the `mov r5, r3` at `0x100002fc` (key 24 -> pin 17) and the `mov r5, r2` at `0x10000304` (key 94 -> pin 18); for key 12, `r5` keeps the `16` loaded at `0x10000284`. +- **`blink_led`** is the loop at `0x100002be`–`0x100002d8`; `r4` counts 3 down to 0, `r5` is the pin, `r7 = 1` and `r6 = 0` drive it on/off. +- **`get_led_pin` in the final print** is `movs r2, #16` at `0x100002f8` (key 1), `moveq r2, #17` at `0x100002ec` (key 2), and `movne r2, #18` at `0x100002ea` (key 3). These are the constants that will **lie** after we patch the loop pins. + +The string map, read straight from `.rodata`: + +| Literal | Points at | String | +| ------- | --------- | ------ | +| `0x1000030c` | `0x100038f8` | `"IR receiver on GPIO %d ready\n"` | +| `0x10000310` | `0x10003918` | `"NEC command: 0x%02X\n"` | +| `0x10000314` | `0x10003930` | `"LED %d activated on GPIO %d\n"` | + +### Step 25: HACK IT LIVE — forge the decoded NEC key + +`ir_getkey` returns the command byte in `r0`; `main` copies it into `r4` at `0x10000278`. We stop right after the read and overwrite `r4` so the program takes a different button's path — even though the operator pressed a different button. + +1. Press `G`, go to `0x1000027c` (the `mov r1, r4` right after the `blt.n`, inside the `key >= 0` block). Set a **hardware execute** breakpoint: `Debugger -> Add Hardware Breakpoint...`. +2. Click **Resume** and press **"1"** on the IR remote. `ir_getkey` returns, `subs r4, r0, #0` at `0x10000278` runs, and the breakpoint fires at `0x1000027c` with `r4 = 0x0C` (12). +3. **Set `r4` to `0x5E` (94)** from the Python console: + ```python + dbg.set_reg_value("r4", 0x5E) # pretend button "3" was pressed + ``` + (Or right-click `r4` in the **Registers** widget, press `E`, type `5e`, and press Enter.) +4. Remove the breakpoint at `0x1000027c` and click **Resume**. The core runs `mov r1, r4`, so the `printf` prints `NEC command: 0x5E`, the `cmp` chain takes the key-94 branch at `0x10000304`, and the Pico blinks the **yellow** LED on GPIO 18 — although you pressed **"1"**. + +> **The pin variant.** If you prefer to move the pin instead of the key, break at `0x10000286` (the first `mcrr`, after `movs r5, #16` at `0x10000284`) and set `r5 = 0x12`. LED1's blink then drives GPIO 18, but `r5` is reloaded at `0x10000284` on the next key, so it is a one-key change. The `r4` edit above is the same idea one step earlier in the pipeline. + +### Step 25b: HACK THE STRING LIVE — change `NEC` to `HACKED` + +The `"NEC command: 0x%02X\n"` format is at `0x10003918`; redirect `r0` to a RAM string at the `printf` call. + +1. Press `G`, go to `0x10000280` (the `bl __wrap_printf` on the key path) and set a **hardware execute** breakpoint. Resume and press **"1"**. At the stop, `r0 = 0x10003918` — the `ldr r0, [pc, #144]` at `0x1000027e` loaded the pointer — and `r1 = 0x0C`. +2. Write the replacement to RAM and repoint `r0`: + ```python + dbg.write_memory(0x20080000, b"HACKED: 0x%02X\n\x00") # keep one %02X + dbg.set_reg_value("r0", 0x20080000) + ``` +3. Remove the breakpoint at `0x10000280`, set one at `0x10000284`, and click **Resume**. This iteration prints: + ``` + HACKED: 0x0C + ``` + One iteration only — the loop reloads `r0` from the literal pool each pass. The permanent version is the static patch in Step 27b. + +### Step 25c: Kill the debugger and OpenOCD + +Same as Step 15b: click the **X** (**Kill**) in the **Debugger** sidebar (or **`Debugger -> Kill`**), then stop OpenOCD from the Binary Ninja console: + +**macOS / Linux:** + +```python +import subprocess +subprocess.run(["pkill", "-TERM", "-f", "openocd"]) # stop the debug server, free the probe +``` + +**Windows:** + +```python +import subprocess +subprocess.run(["taskkill", "/F", "/IM", "openocd.exe"]) # stop the debug server, free the probe +``` + +--- + +## Part 7: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the Binary Ninja GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +#### Worked example: `main` + +1. `G` -> `0x10000234`. +2. `Y` -> `int main(void)` (Binary Ninja shows `int32_t main(void)` — the same 32-bit `int`). + +#### Worked example: `ir_init` + +1. `G` -> `0x10000318`. +2. `Y` -> `void ir_init(uint8_t pin)`. + +#### Worked example: `ir_getkey` + +1. `G` -> `0x10000340`. +2. `Y` -> `int ir_getkey(void)`. + +#### Worked example: `gpio_init` + +1. `G` -> `0x10000598`. +2. `Y` -> `void gpio_init(uint gpio)`. + +`main` calls it three times with `16`, `17`, `18` — the flattened struct pins. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x1000353c`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. It forwards to `__wrap_vprintf`. + +#### Worked example: `sleep_ms` + +1. `G` -> `0x10000ff0`. +2. `Y` -> `void sleep_ms(uint32_t ms)`. + +The blink loop and the idle path both load `10` or `50` immediately before calling it. + +The call chain for this project is the same as Project 1, plus the extra `printf` and the blink loop: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init +│ │ └── uart_init ── clock_get_hz, busy_wait_us +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ └── stdio_put_string ── strlen, time_us_64 +├── gpio_init +├── ir_init ── gpio_init, gpio_set_pulls +├── ir_getkey ── time_us_64 (the NEC timing helpers are inlined) +├── __wrap_printf ── __wrap_vprintf (NEC line and LED line) +└── sleep_ms +``` + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x10000318` | `ir_init` | `void ir_init(uint8_t)` | +| `0x10000340` | `ir_getkey` | `int ir_getkey(void)` | +| `0x10000534` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000570` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10000598` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000ff0` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x100011d4` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011e8` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001268` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x1000143c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10003154` | `exit` | `void exit(int)` | +| `0x1000315c` | `runtime_init` | `void runtime_init(void)` | +| `0x10003188` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003298` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10003384` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100033ac` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x1000343c` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003478` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x1000353c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036f8` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003838` | `strlen` | `size_t strlen(const char*)` | + +> **Shortcut — resolves name *and* type for every function.** Paste this into Binary Ninja's Python console: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x10000318: ("ir_init", "void ir_init(uint8_t)"), +> 0x10000340: ("ir_getkey", "int ir_getkey(void)"), +> 0x10000534: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000570: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10000598: ("gpio_init", "void gpio_init(uint)"), +> 0x10000ff0: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x100011d4: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011e8: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001268: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x1000143c: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10003154: ("exit", "void exit(int)"), +> 0x1000315c: ("runtime_init", "void runtime_init(void)"), +> 0x10003188: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003298: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x10003384: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100033ac: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x1000343c: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003478: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x1000353c: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036f8: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003838: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` + +### Step 27: Patch 1 — swap LED1 and LED3 pins + +The original lesson swaps LED 1 and LED 3. LED1 is the red LED on GPIO 16 and LED3 is the yellow LED on GPIO 18. In the loop the pins are `movs r5, #16` at `0x10000284` (LED1) and `movs r2, #18` at `0x10000290` (LED3). Swap the two immediates: + +| Address | Instruction | Bytes before | Bytes after | Role | +| ------- | ----------- | ------------ | ----------- | ---- | +| `0x10000284` | `movs r5, #16` | `10 25` | `12 25` | LED1's pin (`r5`) 16 -> 18 | +| `0x10000290` | `movs r2, #18` | `12 22` | `10 22` | LED3's pin (`r2`) 18 -> 16 | + +```python +bv.write(0x10000284, b"\x12") # movs r5, #18 (LED1 -> GPIO 18) +bv.write(0x10000290, b"\x10") # movs r2, #16 (LED3 -> GPIO 16) +print(bv.read(0x10000284, 2).hex(" ")) # -> 12 25 +print(bv.read(0x10000290, 2).hex(" ")) # -> 10 22 +``` + +Now button **"1"** blinks GPIO 18 (yellow) and button **"3"** blinks GPIO 16 (red). The `LED N activated on GPIO P` prints are **not** changed, so they still say `GPIO 16` and `GPIO 18` — **the log no longer matches the hardware.** That mismatch is the security lesson: the operator's console shows the old, expected mapping while the pins do something else. + +> **Optional consistency patch.** If you want the print to tell the truth instead, also change `movs r2, #16` at `0x100002f8` to `#18` (and the key-3 print constant `movne r2, #18` at `0x100002ea` to `#16`). For this lesson we leave them alone on purpose, so the desynchronization is visible. +> +> | Address | Instruction | Bytes before | Bytes after | Role | +> | ------- | ----------- | ------------ | ----------- | ---- | +> | `0x100002f8` | `movs r2, #16` | `10 22` | `12 22` | optional: key-1 print now says GPIO 18 | + +### Step 27b: Patch 2 — rename the `NEC` string to `PWN` + +The format string starts at `0x10003918`; change its first three bytes `4e 45 43` (`NEC`) to `50 57 4e` (`PWN`): + +```python +bv.write(0x10003918, b"PWN") +print(bv.read(0x10003918, 20)) # -> b'PWN command: 0x%02X\n\x00' +``` + +Exactly three bytes, same rule as Project 1: a shorter string must be padded, a longer one overwrites the ` command:` tail. + +### Step 28: Export, convert, and flash + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0026_functions", "build"), "0x0026_functions-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16476 /.../build/0x0026_functions-h.bin +``` + +`seg.data_length` is the image size (`0x405c` = 16476) read from the view — nothing hardcoded. + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0026_functions-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0026_functions-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the Binary Ninja console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21. + +### Step 29: Verify + +Open the serial monitor: + +- press **"1"** -> the **YELLOW** LED on GPIO 18 blinks (it used to be the red LED on GPIO 16), and the terminal still prints `LED 1 activated on GPIO 16` — **wrong**, it is actually GPIO 18; +- press **"3"** -> the **RED** LED on GPIO 16 blinks (it used to be the yellow LED on GPIO 18), and the terminal still prints `LED 3 activated on GPIO 18` — **wrong**, it is actually GPIO 16; +- press **"2"** -> the green LED on GPIO 17 is unchanged; +- every `NEC command:` line now reads `PWN command:`. + +**The log says one thing, the hardware does another — with two bytes and no source code.** + +--- + +## Cheatsheet + +### Binary Ninja GUI actions + +| Action | How | +| ------ | --- | +| Go to address | `G` | +| Rename function/symbol | `N` | +| Set type or signature | `Y` | +| Add comment | `;` | +| Open Hex view | `View -> Hex` | +| Enable hex editing | Toggle the lock in the status bar | +| Reanalyze after a patch | Right-click function -> `Reanalyze` | +| Edit a register live | `dbg.set_reg_value("r4", 0x5E)` in the Python console (or right-click the register, press `E`, type hex, Enter) | +| Write debugger memory | `dbg.write_memory(0x20080000, b"HACKED: 0x%02X\n\x00")` | +| Set a breakpoint | `Debugger -> Add Hardware Breakpoint...` (hardware execute). Do **not** use `F2` — software breakpoints cannot be written to read-only flash. | +| Move a breakpoint | Remove it and set it at the new address in the GUI (command-port fallback: `rbp ` then `bp 2 hw`) | +| Confirm what is armed | The **Breakpoints** widget lists it (command-port fallback: `mdw 0xE0002000 8`, each armed breakpoint shows as ``) | +| Apply the ELF symbol map | Paste the Python snippet from Step 16 / 26 into the Python Console | + +### OpenOCD server and reset + +The server runs with `gdb_breakpoint_override hard` so that flash-writes are never attempted. Breakpoints in this lab are set in the Binary Ninja GUI through the **GDB MI** adapter (Step 13). The command-port rows below are the fallback if you use the **GDB RSP** adapter instead. + +| Action | Command | +| ------ | ------- | +| Connect to the OpenOCD prompt (fallback) | `nc 127.0.0.1 4444` (or `telnet 127.0.0.1 4444`) | +| Reset and run (command port) | `reset run` | +| Check core state (command port) | `targets` | +| Set a breakpoint in the GUI | `Debugger -> Add Hardware Breakpoint...` (hardware execute; `F2` software breakpoints do not work on flash) | +| (fallback) Add a breakpoint without the GUI | `bp 2 hw` | +| Remove one breakpoint | `rbp ` — **address only, no length, no `hw`** | +| Remove every breakpoint | `rbp all` | +| Start the server parked at `main` | macOS/Linux: `BP_ADDR=0x10000234 ./debug-server.sh` — Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1` (one-shot) | +| Break on the loop in a running target | set a hardware breakpoint in the GUI at the loop address, then **Resume** — repeatable | +| Make Binary Ninja stepping work | `rp2350.dap.core0 configure -rtos none` (already in the scripts) | +| Step without re-trapping | move the breakpoint off the current PC first, then **Step Into**/**Step Over** | +| Reset without desyncing Binary Ninja | **Detach**, `reset run` on the port, reconnect — never `reset run` while attached | +| Kill the debugger | click **X** in the **Debugger** sidebar, or `Debugger -> Kill` | +| Stop OpenOCD | macOS/Linux: `pkill -TERM -f openocd` — Windows: `taskkill /F /IM openocd.exe` | + +### Where you can stop + +| Stop at | Project 1 `0x0023` | Project 2 `0x0026` | +| ------- | ------------------ | ------------------ | +| `main` (once per reset) | `0x10000234` | `0x10000234` | +| `ir_getkey` return | `0x10000274` | `0x10000274` | +| Loop `printf` (`NEC command`) | `0x1000027c` | `0x10000280` | +| First `gpio_put` (`mcrr`, LED1 pin) | `0x1000028a` | `0x10000286` | +| LED3 `gpio_put` (`mcrr`) | `0x100002aa` | `0x10000292` | + +### Every address and byte we changed + +| Project | Address | Before | After | Effect | +| ------- | ------- | ------ | ----- | ------ | +| `0x0023` | `0x10000240` | `10` | `12` | LED1 pin 16 -> 18 | +| `0x0023` | `0x100002a6` | `12` | `10` | LED3 pin 18 -> 16 | +| `0x0023` | `0x100038d0` | `4e 45 43` | `50 57 4e` | prints `PWN` instead of `NEC` | +| `0x0026` | `0x10000284` | `10` | `12` | LED1 pin 16 -> 18 | +| `0x0026` | `0x10000290` | `12` | `10` | LED3 pin 18 -> 16 | +| `0x0026` | `0x100002f8` | `10` | `12` | optional: key-1 print says GPIO 18 | +| `0x0026` | `0x10003918` | `4e 45 43` | `50 57 4e` | prints `PWN` instead of `NEC` | + +### Raw image facts + +| Item | Value | +| ---- | ----- | +| Build type | `Release` | +| Load base address | `0x10000000` | +| Project 1 size | `16372` bytes (`0x3ff4`) | +| Project 2 size | `16476` bytes (`0x405c`) | +| Initial stack pointer (both) | `0x20082000` | +| Reset vector (both) | `0x1000015d` | +| Fixed `main` anchor (both) | `0x1000018c` | +| `main` (both) | `0x10000234` | +| `ir_init`, Project 1 | `0x100002cc` | +| `ir_init`, Project 2 | `0x10000318` | +| `ir_getkey`, Project 1 | `0x100002f4` | +| `ir_getkey`, Project 2 | `0x10000340` | +| Project 1 `IR receiver` string | `0x100038b0` | +| Project 1 `NEC command` string | `0x100038d0` | +| Project 2 `IR receiver` string | `0x100038f8` | +| Project 2 `NEC command` string | `0x10003918` | +| Project 2 `LED activated` string | `0x10003930` | +| RP2350 UF2 family ID | `0xe48bff59` | + +--- + +## Troubleshooting + +### Binary Ninja hangs or crashes when you connect (macOS 27) + +Three different causes have been seen on this setup; check them in this order. + +- **A breakpoint set before connecting.** With the **GDB MI** adapter, if the binary view already has a breakpoint, the session hangs. Start parked with `BP_ADDR`, connect, then add breakpoints. +- **The wrong GDB executable.** Point **Full GDB Executable Path** at the **14.2.rel1** toolchain (Step 11). The 13.3.rel1 build did not connect in testing. +- **The LLDB adapter.** A crash report with `libdebuggercore.dylib -> std::terminate() -> abort()` and `liblldb` in the stack is the **LLDB** adapter, not GDB MI. Avoid LLDB on this setup. + +If Binary Ninja hangs, force-quit it; the connect dialog has no working Cancel. The static steps (resolve, patch, export, flash) never touch the debugger and always work. + +### GDB MI hangs when you connect (a breakpoint already existed) + +With the **GDB MI** adapter, if Binary Ninja already has a breakpoint set when you connect, the session **hangs**. The working order is: + +1. Start the server parked, e.g. `BP_ADDR=0x10000234 ./debug-server.sh` (Windows: `$env:BP_ADDR="0x10000234"; .\debug-server.ps1`). +2. Connect with the **GDB MI** adapter. +3. Only *then* set hardware breakpoints in the UI. + +### Step Into / Step Over does nothing (PC never moves) + +Two causes have been seen on this target. + +1. **A breakpoint on the current PC re-traps the step.** OpenOCD's step-over-breakpoint logic fails with `Duplicate Breakpoint address` and the PC stays put. Fix: move the breakpoint off the current PC (in the GUI), then step. +2. **The `hwthread` RTOS (GDB RSP adapter only).** With the **GDB RSP** adapter, OpenOCD can log `fake step thread 0` and reply without stepping. Fix: `rp2350.dap.core0 configure -rtos none`. **GDB MI does not hit this.** + +### `zsh: bad CPU type in executable: cmake` + +An Intel `x86_64` tool is on your `PATH` on Apple Silicon. Run Step 2: `export PATH="/opt/homebrew/bin:$PATH"`, then `hash -r`. Add it to `~/.zshrc` to make it permanent. + +### My addresses do not match this guide + +You probably built `Debug`. This lesson is a `Release` build. Re-run Step 3 with `-DCMAKE_BUILD_TYPE=Release`. A `Debug` build moves the SDK functions and keeps the `static` helpers separate, so `main` is not at `0x10000234`. + +### A breakpoint never fires + +First, confirm you actually set one, and that it is a **hardware** breakpoint. `Debugger -> Add Hardware Breakpoint...` (hardware execute) should land in the **Breakpoints** widget. If nothing lands, or the core keeps running, you probably used `F2` (`Toggle Breakpoint`) — a software breakpoint cannot be written to read-only flash. Also check you are on **GDB MI**, not **GDB RSP** (the GDB RSP adapter cannot set breakpoints on this target at all). + +Then check the order and the state: + +- **Arm it only after Binary Ninja is connected.** OpenOCD flushes every breakpoint when a client attaches, so anything armed earlier is gone. This also applies to `BP_ADDR` on the startup command line. +- **Is the core running?** If it is stopped, click **Resume**. +- **Does the address get reached again?** `main` runs once per reset, so use `BP_ADDR` at startup rather than `reset run` while attached. Loop addresses such as `0x1000028a` (P1) and `0x10000286` (P2) fire on the next key press with no reset. For the `NEC` print addresses (`0x1000027c` / `0x10000280`) you must also press a remote button, because they sit inside the `if (key >= 0)` block. + +### I edit `r4` / `r5` and it reverts + +For Project 2's key forgery, `subs r4, r0, #0` reloads `r4` from `ir_getkey` on every key press, so the edit is visible for one key. For Project 1's `r5` pin edit, `r5` is loaded once at `0x10000240` and never reloaded, so it sticks until reset. For Project 2's `r5` pin edit, `movs r5, #16` at `0x10000284` reloads it on every key. The edit sticks only while the core is **genuinely stopped** at the breakpoint. + +> **The Registers widget is a snapshot, not a live view.** Binary Ninja reads the registers at each stop and shows that snapshot; it does not poll the target. A value changed outside Binary Ninja will not appear until the next stop. + +### The string hack does nothing (or prints garbage) + +Pick a RAM address that is free — `0x20080000` is safe here (well above the `.data`/`.bss` end at about `0x20000810`). Write a NUL-terminated string, and keep exactly the format specifiers the call consumes: the NEC format has one `%02X`, so the replacement must keep one `%02X`. Then set `r0`, not `r1`. + +### The patched string shifted `printf` output + +The `NEC command: 0x%02X\n` format has one `%02X`. Keep the replacement exactly three bytes (`NEC` -> `PWN`); a longer string would overwrite the ` command:` tail and a shorter one would leave a stray character. In the live hack you write a whole new NUL-terminated string to RAM, so any length is fine as long as it keeps one `%02X`. + +### The struct is not in memory — where is it? + +It is not. `Release` proved `simple_led_ctrl_t` never escapes `main`, so the compiler **flattened** it: the three `uint8_t` pins became the immediates `16`, `17`, `18` and the three `bool` states became register values. There is no `sub sp` for the struct and no memory address to inspect. You patch the immediates instead. If you need to see the struct in memory, build `Debug`, but then none of the addresses in this guide apply. + +### Project 2's `LED N activated on GPIO P` line is wrong after the patch + +That is the point. Step 27 swaps the pins the loop *drives* but leaves the print constants (`0x100002f8`, `0x100002ea`, `0x100002ec`) untouched, so the log shows the old mapping. If you want the print to match, apply the optional consistency patch in Step 27. + +### The serial capture is garbage on macOS + +Reading `/dev/cu.usbmodem*` with a bare `read()` returns garbage. Set **raw termios at 115200** first, or just use `screen /dev/cu.usbmodem* 115200`, which does it for you. + +### It worked for a second, then stopped (Binary Ninja's view desyncs) + +The main cause is **driving the core from the OpenOCD command port while Binary Ninja is connected**. If you must reset, **Detach first**, reset, then reconnect. Never leave a breakpoint on the PC you are about to step or resume from. + +### The console floods with `Failed to read memory` or `SWD DPIDR` reconnects + +Two causes: +1. **Core 1 is exposed.** The scripts must run with `USE_CORE=0`. Stop the server, confirm only `core0` is reported, restart, then restart Binary Ninja. +2. **Binary Ninja probed an unmapped address for a register preview.** When a register holds an arbitrary integer or uninitialized value (e.g. `0x69000000`), Binary Ninja tries to preview that memory address, triggering an OpenOCD SWD fault and debug-port reconnect (`SWD DPIDR 0x4c013477`). In the **Debugger Console**, run `source pico-gdb-memory.gdb`. This restricts GDB to valid Flash and SRAM, filtering invalid reads locally so OpenOCD's SWD connection stays completely stable. + +### The decompiler still shows the old value after patching + +Right-click the function and choose `Reanalyze`. + +--- + +## Fallback: do the dynamic steps with GDB (macOS 27) + +If Binary Ninja's debugger crashes on attach on macOS 27, you can still do the live hacks with the ARM GDB from the toolchain, against the same OpenOCD server. The addresses and register values are identical to the GUI steps. + +Start the debug server (Step 10), then in a new terminal: + +``` +arm-none-eabi-gdb +``` + +At the `(gdb)` prompt for Project 1: + +``` +set architecture armv8-m.main +target extended-remote :3333 +hbreak *0x1000028a +continue +``` + +Do **not** run `monitor reset run` before `hbreak`. `0x1000028a` is inside `main`'s loop, so the breakpoint fires on the next key press with no reset. Press **"1"** on the remote, then: + +``` +info registers pc r5 # pc = 0x1000028a, r5 = 0x10 +set $r5 = 0x12 +continue +``` + +The next LED1 write drives GPIO 18 — the same temporary live hack as editing `r5` in the Binary Ninja Registers widget. For the string hack, break at `0x1000027c`, then `set {char[19]}0x20080000 = "HACKED: 0x%02X\n"` and `set $r0 = 0x20080000`. + +Project 2 is the same with the other call site and value: + +``` +hbreak *0x1000027c +continue +info registers pc r4 # r4 holds the decoded key you pressed +set $r4 = 0x5E +continue +``` + +`hbreak` sets a hardware breakpoint, which is required for read-only flash. It works from plain GDB because GDB sends the 2-byte length the Cortex-M33 comparators need. Binary Ninja's **GDB MI** adapter goes through the same GDB, so its GUI breakpoints work too. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **Flattening** | The optimizer replacing struct member accesses with the member's constant value; why `simple_led_ctrl_t` disappears | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +| **Hardware breakpoint** | A breakpoint serviced by the CPU comparators, required for read-only flash | +| **Inlining** | The optimizer replacing a function call with the function body; why every `static` helper disappears from `main` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **`mcrr`** | Move to coprocessor from two registers — how the SIO GPIO writes are encoded | +| **NEC** | A common IR protocol: 9 ms leader + 4.5 ms space, then 32 data bits (address, ~address, command, ~command) | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Prove the behavior dynamically, resolve the names from the ELF, then patch the bytes and flash. \ No newline at end of file diff --git a/WEEK11/WEEK11-BN.pdf b/WEEK11/WEEK11-BN.pdf new file mode 100644 index 0000000..4564551 Binary files /dev/null and b/WEEK11/WEEK11-BN.pdf differ diff --git a/WEEK11/WEEK11-IDA.md b/WEEK11/WEEK11-IDA.md new file mode 100644 index 0000000..9331136 --- /dev/null +++ b/WEEK11/WEEK11-IDA.md @@ -0,0 +1,950 @@ +# Week 11-IDA: IDA Pro — Hack Structs & Functions with the NEC IR Remote (Raw `.bin`) + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +- Build the two lesson projects with `Release` and get an `.elf` and a raw `.bin` for each +- Dump the **ELF symbol map** with `arm-none-eabi-nm` and use it as ground truth +- Load each raw `.bin` into IDA at `0x10000000` +- **Resolve the functions in the IDA GUI** using the ELF symbol map +- See how the compiler **flattens a C struct into hard-coded immediates** and **inlines every helper function** +- **Patch** the LED pin immediates and the NEC format string, export, convert and export +- Understand the security lesson: **the log says one thing while the hardware does another** + +--- + +## How This Guide Works + +Each project builds two files: + +| File | What it is | How we use it | +| ---- | ---------- | ------------- | +| `.elf` | The linked image with a full symbol table and DWARF | Ground truth for every function address and signature | +| `.bin` | The raw flash image, no headers, no symbols | The image we load into IDA and reverse | + +The `.bin` is built **from** the `.elf`, so the ELF tells you exactly what is at every address. We reverse-engineer the raw `.bin` the way a real extracted firmware image is reversed. + +> **Build `Release`, not `Debug`.** Every address in this guide matches the current `Release` builds. `Release` flattens the LED struct into plain immediates and inlines every `static` helper (`make_default_leds`, `init_led_gpios`, `process_ir_key`, `poll_ir`, and in Project 2 `ir_to_led_number`, `get_led_pin`, `leds_all_off`, `blink_led`, `process_ir_led_command`, `handle_ir_key`, `poll_and_handle_ir`) into `main`. If you build `Debug`, the SDK function addresses move and the helpers stay separate, so nothing lines up. Always build `Release` for this lesson. + +The workflow is static-only: import the raw image, recover the code, decompile it, and patch the artifact: + +d prove what the code does. +ge. +3. Resolve the functions in IDA using the ELF symbol map. +4. Patch the bytes, export, convert and export. + +| Project | Prints | Also does | The hacks | +| ------- | ------ | --------- | --------- | +| `0x0023_structures` | `IR receiver on GPIO 5 ready`, then `NEC command: 0xNN` per key | lights LED1/2/3 on GPIO 16/17/18 from the flattened struct | move LED1 to GPIO 18 live; swap LED1↔LED3 pins; rename the `NEC` string | +| `0x0026_functions` | the same, plus `LED N activated on GPIO P` | blinks the mapped LED 3× then holds it | forge the decoded key live; swap LED1↔LED3 pins (log desync); rename the `NEC` string | + +> **The struct disappears.** `simple_led_ctrl_t` has six members (three `uint8_t` pins and three `bool` states), but the optimizer proves it never escapes `main`, so it is never placed in memory. `leds.led1_pin` becomes the literal `16`, `leds.led2_pin` becomes `17`, `leds.led3_pin` becomes `18`, and the `bool` states become register values. That is why you patch **immediates**, not a struct field. + +> **The functions disappear too.** Every `static` helper is inlined, so there is no `process_ir_key` or `blink_led` symbol to rename. You see their bodies directly inside `main`. The only real functions `main` calls are the SDK routines and `ir_init`/`ir_getkey`. + +> **The SVD file lives in `WEEK04`.** If you want the RP2350 peripheral register map for the SIO/GPIO side of the lab, it is `Embedded-Hacking/WEEK04/rp2350.svd` — it is **not** in `WEEK11`. + +### Background: the NEC IR remote in one paragraph + +An IR receiver on **GPIO 5** demodulates a 38 kHz carrier and presents the NEC frame as a digital mark/space train. `ir_getkey()` waits for the 9 ms leader + 4.5 ms space, samples 32 bits by timing the marks, then validates that the address and command pairs are bitwise inverses. It returns the **command byte** (`0x0C`, `0x18`, or `0x5E` for buttons 1, 2, 3) or `-1`. `main` maps that byte to one of three LEDs on **GPIO 16 (red), 17 (green), 18 (yellow)**. Because the struct is flattened, that mapping is a set of hard-coded pin numbers in the loop — exactly what we patch. + +--- + +## Part 1: Build and Get the Symbol Map + +### Step 1: Install the toolchain + +**Windows x64** + +- Install the **Raspberry Pi Pico** extension in VS Code. It installs the ARM GNU toolchain, CMake, Ninja, and the Pico SDK. +- Install **IDA Pro** and complete its license activation. +- Install **PuTTY** for the serial monitor. + +**macOS Apple Silicon** + + +All must report `arm64`. If any is `x86_64`, put the Apple Silicon prefix first for the session and check again: + +```bash +export PATH="/opt/homebrew/bin:$PATH" +hash -r +file "$(which cmake)" +``` + + +**Windows x64** and **Linux x64** do not have this problem. Skip to Step 3. + +### Step 3: Build the two projects with `Release` + +Run this once inside `0x0023_structures/` and once inside `0x0026_functions/`: + +```bash +cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 -DCMAKE_BUILD_TYPE=Release +cmake --build build +``` + +**Point IDA at this repository (once).** Every console snippet below reads the repo root from `~/.embedded-hacking-repo`, so IDA never needs a database open and nothing is hardcoded. From the repo root, run once: + +**macOS / Linux:** + +```bash +pwd > ~/.embedded-hacking-repo +``` + +**Windows (PowerShell):** + +```powershell +(Get-Location).Path | Set-Content "$env:USERPROFILE\.embedded-hacking-repo" +``` + +**Then build from the IDA console**, so the whole build -> patch -> flash loop stays inside IDA. The console inherits a minimal `PATH` — on macOS just `/usr/bin:/bin:/usr/sbin:/sbin` — so it does not see Homebrew; add your package manager's `bin` first, then run plain `cmake`. + +**macOS Apple Silicon:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +os.environ["PATH"] = "/opt/homebrew/bin:" + os.environ["PATH"] # the console's PATH omits Homebrew +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Linux x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +**Windows x64:** + +```python +import os, subprocess +root = open(os.path.expanduser("~/.embedded-hacking-repo")).read().strip() +for name in ("0x0023_structures", "0x0026_functions"): + proj = os.path.join(root, name) + subprocess.run(["cmake", "-B", "build", "-G", "Ninja", "-DPICO_BOARD=pico2", + "-DPICO_PLATFORM=rp2350", "-DCMAKE_BUILD_TYPE=Release"], cwd=proj) + subprocess.run(["cmake", "--build", "build"], cwd=proj) +``` + +Each build directory now contains the pair we need: + +- `0x0023_structures/build/0x0023_structures.elf` and `.bin` — `.bin` is **16372** bytes (`0x3ff4`) +- `0x0026_functions/build/0x0026_functions.elf` and `.bin` — `.bin` is **16476** bytes (`0x405c`) + +If the ARM toolchain is not on your `PATH`, add `-DPICO_TOOLCHAIN_PATH=...`: + +| OS | Typical toolchain path | +| -- | ---------------------- | +| Windows x64 | `C:/Program Files/Arm GNU Toolchain arm-none-eabi/14.2 rel1/bin` | +| macOS Apple Silicon | `/Applications/ArmGNUToolchain/14.2.rel1/arm-none-eabi/bin` | +| Linux x64 | `/usr` | + +### Step 4: Dump the ELF symbol map + +This is the ground truth for the whole lesson. Run `arm-none-eabi-nm` on each ELF and keep the output in a terminal or a text file: + +**macOS Apple Silicon / Linux x64:** + +```bash +arm-none-eabi-nm -n --defined-only build/0x0023_structures.elf | grep -E ' [Tt] ' +arm-none-eabi-nm -n --defined-only build/0x0026_functions.elf | grep -E ' [Tt] ' +``` + +**Windows x64:** + +```powershell +arm-none-eabi-nm -n --defined-only build\0x0023_structures.elf | Select-String ' [Tt] ' +arm-none-eabi-nm -n --defined-only build\0x0026_functions.elf | Select-String ' [Tt] ' +``` + +Each line is `address type name`. The `T`/`t` type is a function. The signatures below come from the ELF's DWARF debug info queried with `arm-none-eabi-gdb -batch -ex "ptype "`, so they are exact. + +**Project 1 — `0x0023_structures` — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (struct flattened, all helpers inlined) | +| `0x100002cc` | `ir_init` | `void ir_init(uint8_t)` | the `ir.c` receiver init | +| `0x100002f4` | `ir_getkey` | `int ir_getkey(void)` | the blocking NEC decoder (timing helpers inlined) | + +**Project 1 — the GPIO, UART, stdio, and `printf` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x100004e8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000524` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull-up/down (used by `ir_init`) | +| `0x1000054c` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | +| `0x10000fa8` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x1000118c` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (NEC timing) | +| `0x100011a0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001220` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x100013f4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x1000310c` | `exit` | `void exit(int)` | C runtime exit | +| `0x10003114` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003140` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003250` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x1000333c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x10003364` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x100033f4` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (adjacent stdio family) | +| `0x10003430` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x100034f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (both prints) | +| `0x100036b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x100037f0` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +**Project 2 — `0x0026_functions` — our code and the startup chain:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | reset entry | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | calls `runtime_init`, `main`, `exit` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | copies `.data` from flash to SRAM | +| `0x100001e4` | `_init` | `void _init(void)` | runs `.init_array` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | C runtime boilerplate | +| `0x10000234` | `main` | `int main(void)` | the lesson function (struct flattened, all helpers inlined) | +| `0x10000318` | `ir_init` | `void ir_init(uint8_t)` | the `ir.c` receiver init | +| `0x10000340` | `ir_getkey` | `int ir_getkey(void)` | the blocking NEC decoder (timing helpers inlined) | + +**Project 2 — the GPIO, UART, stdio, and `printf` chain `main` reaches:** + +| Address | ELF symbol | Signature | Role | +| ------- | ---------- | --------- | ---- | +| `0x10000534` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | SDK GPIO function select | +| `0x10000570` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | SDK pull-up/down (used by `ir_init`) | +| `0x10000598` | `gpio_init` | `void gpio_init(uint)` | SDK GPIO init | +| `0x10000ff0` | `sleep_ms` | `void sleep_ms(uint32_t)` | SDK millisecond delay | +| `0x100011d4` | `time_us_64` | `uint64_t time_us_64(void)` | SDK microsecond clock (NEC timing) | +| `0x100011e8` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | UART timing loop | +| `0x10001268` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | SDK UART init | +| `0x1000143c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | UART clock lookup | +| `0x10003154` | `exit` | `void exit(int)` | C runtime exit | +| `0x1000315c` | `runtime_init` | `void runtime_init(void)` | SDK runtime init | +| `0x10003188` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | CRLF output driver | +| `0x10003298` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | buffered string output | +| `0x10003384` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | enable the UART driver | +| `0x100033ac` | `stdio_init_all` | `bool stdio_init_all(void)` | SDK serial init | +| `0x1000343c` | `__wrap_puts` | `int __wrap_puts(const char*)` | the `puts` wrapper (adjacent stdio family) | +| `0x10003478` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | printf core | +| `0x1000353c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | the `printf` wrapper (all three prints) | +| `0x100036f8` | `stdio_uart_init` | `void stdio_uart_init(void)` | SDK UART stdio init | +| `0x10003838` | `strlen` | `size_t strlen(const char*)` | C runtime string length | + +> **`main` is `0x10000234` in both projects.** Both programs put `main` at the same address because the startup code and the linker layout are identical; only the body of `main` and the functions after it move. In a `Debug` build the helpers stay separate and `main` moves — another reason to build `Release`. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper, which forwards to `__wrap_vprintf`. The `__wrap_puts` symbol exists in the image (the stdio family always does), but our `printf` path does not call it. + +## Part 2: Load the Raw `.bin` into IDA + +Start from a fresh IDA state. If you already have a database for this lesson, **close it and start over**; a stale database keeps old names and patches. + +### Step 7: Bring the raw `.bin` into IDA + +A raw `.bin` has no headers, so IDA cannot know where it belongs or what architecture it is. You must supply both. If you just double-click the `.bin`, IDA may load it with a guessed architecture, and every address in this lesson will be wrong. + +#### 1.1 Open the file +1. **File ▸ Open…** (Ctrl/Cmd+O). +2. Select the `.bin` file and click **Open**. + +IDA opens the **"Load a new file"** dialog because a raw `.bin` has no header. + +#### 1.2 Set the format and processor +In the *Load a new file* dialog: +1. **Format**: leave it as **Binary file** (IDA auto-detects a headerless image). +2. **Processor type**: click the **…** button next to the processor field. In the *Processor type* dialog: + - Family: **ARM** + - Type: **ARM Little-endian** (the 32-bit ARM module). + - Click **OK**. + +> If IDA asks **"Do you want to disassemble it as 64-bit code?"** — click **No**. +> The RP2350 is 32-bit; answering *Yes* loads AArch64 and you get `X` registers / data. (This is the single most common cause of the `DCB` wall.) + +#### 1.3 Configure the ARM architecture and Thumb mode +Still in the *Load a new file* dialog, open the processor options (the **Processor options** / **Set…** button, which opens the dialog titled **ARM architecture options**): +- **ARM architecture**: choose **ARMv8-M** (this is the Cortex-M33 / RP2350 core). +- **Thumb instructions**: select **Thumb-2** (ARMv8-M is Thumb-only, so this is the correct mode). +- Leave **automatic ARM-THUMB switch** off; we want Thumb throughout. + +#### 1.4 Set the loading address +- **Loading address**: enter **`10000000`** (hex; the RP2350 XIP flash base). + IDA rejects addresses that don't look like ROM/RAM with *"The loading address should belong to RAM or ROM"* — `0x10000000` is the correct flash window. + +Leave **Manual load** and **Create segments** at their defaults. Click **OK**. + +#### 1.5 Force Thumb, then seed the code from the vector table +A raw `.bin` has no header, so IDA's loader has **no entry point** and defaults the segment to **ARM mode** (which cannot decode Thumb). Two required steps — in this order: + +**A. Set the segment to Thumb (do this first).** +- **Edit ▸ Segments ▸ Set default segment register value…** → register **`T`** = **`1`** (or press **`Alt+G`**). IDA reanalyzes the segment as Thumb automatically. + +**B. Seed the code from the vector table.** +1. **G** → `10000000`. The first two words are the initial stack pointer and the **reset vector**. +2. **Read the 4-byte word at `0x10000004`** (do **not** assume its value — it differs per build). +3. **Clear bit 0** (the ARM **Thumb** flag) → the reset handler address. +4. **G** to that address → press **C** (**MakeCode**). IDA disassembles the reset handler and follows its `bl`s into `main`. + +Once `main` shows code, the import is correct. + +**Why IDA needs this and others don't:** IDA's generic raw-binary ARM loader treats the image as flat data and waits for you to set Thumb and mark the entry point. It's an IDA quirk, not a mistake on your part. + +### Step 8: Save it as a IDA database (`.i64`) + +IDA never writes back into the `.bin`. Your names, comments, types, and patches live in a separate **`.i64`** database. Save one now, before you make any changes: + +1. Choose `File -> Save As...`. +2. Save it next to the image as `0x0023_structures.i64`. +3. From now on, save with `File -> Save` (`Cmd+S` on macOS, `Ctrl+S` on Windows/Linux) whenever you rename or patch. + +| File | Role | +| ---- | ---- | +| `0x0023_structures.bin` | the raw firmware image; IDA never modifies it | +| `0x0023_structures.i64` | your analysis database: names, types, comments, and patches | + +When you come back later, **open the `.i64`**, not the `.bin`; that restores all your work. You export the patched image out of this view later, in Step 19. + +### Step 9: The views you will use + +- **Linear view:** the disassembly listing. You navigate, read, and patch here. +- **Graph view:** the control-flow graph of the current function. +- **Decompiler (HLIL):** the pseudo-C decompilation. +- **Hex view:** raw bytes, used for patching. +- **Function list:** the sidebar list of every detected function. + +Navigation: `G` go to address, `N` rename, `Y` set type or signature, `;` add a comment. + +> **macOS function keys:** the top-row `F` keys are usually mapped to system functions. Every step here uses menu paths that work without them. + +--- + +## Part 3: Static — Resolve the Functions in IDA and Patch (Project 1) + +### Step 16: Resolve the functions in the IDA GUI + +We now name the functions in IDA using the ELF symbol map from Step 4. IDA loaded the raw `.bin` with **no symbols**, so every function shows as `sub_` — resolving means giving each one its real name and signature. + +Three keys do all the work: + +| Key | IDA action | Use it for | +| --- | --- | --- | +| `G` | Go to address | Jump to a function's address | +| `Y` | **Change Type** | Set the function's signature. The dialog shows the full prototype, so this sets the name *and* the type in one step. | +| `N` | Rename | Rename only, when you just want the name and not the type | + +For each function below: `G` to its address, then **`Y` (Change Type)** and type the prototype from the table. + +#### How to resolve a function in IDA (`Y`) + +`Y` is the **Change Type** key, and it is what actually resolves the function — it turns `void sub_10003364()` into `bool stdio_init_all(void)`. The Change Type dialog shows the full declaration (name and type), so typing the prototype sets both: + +1. `G` to the function's address. The cursor lands on the function. +2. Press **`Y`**. In the Change Type dialog, type the prototype from the table exactly — for example `bool stdio_init_all(void)` — and press Enter. + +If `Y` seems to do nothing, confirm the cursor is on the function, or right-click it and pick **Change Type...**. IDA parses what you type and silently keeps the old type if it does not parse, so glance at the header after each `Y`. + +#### Worked example: `main` + +1. Press `G`, type `0x10000234`, press Enter. The cursor lands on `sub_10000234`. +2. Press **`Y`** (Change Type), type `int main(void)`, press Enter. + +> **IDA shows `int32_t` where Ghidra shows `int`.** After you set `int main(void)`, the decompiler header may read `int32_t main(void)`. That is the same type — on this platform `int` is 32 bits and IDA's parser normalises it to `int32_t`. Do not fight it; it is not an error. + +#### Worked example: `ir_init` + +1. `G` -> `0x100002cc`. +2. `Y` -> `void ir_init(uint8_t pin)`. + +It takes a `uint8_t` pin; `main` calls it with `5` (`movs r0, #5`). It opens with `gpio_init(pin)`, then writes the direction and calls `gpio_set_pulls` for the pull-up. + +#### Worked example: `ir_getkey` + +1. `G` -> `0x100002f4`. +2. `Y` -> `int ir_getkey(void)`. + +It returns `-1` on timeout and the command byte otherwise. The NEC timing helpers (`wait_for_level`, `wait_leader`, `read_nec_bit`, `read_32_bits`, `validate_nec_frame`) are all `static` and **inlined** into it, so you will not find them as separate functions. + +#### Worked example: `gpio_init` + +1. `G` -> `0x1000054c`. +2. `Y` -> `void gpio_init(uint gpio)`. + +`main` calls it three times with `16`, `17`, `18` — the flattened struct pins. + +#### Worked example: `stdio_init_all` + +1. `G` -> `0x10003364`. +2. `Y` -> `bool stdio_init_all(void)`. + +It returns **`bool`**, not `void` — the ELF says `_Bool stdio_init_all(void)`. Our `main` ignores the return value, so the decompiler still reads cleanly. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x100034f4`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. + +> **`printf` in our source is `__wrap_printf` in the binary.** The SDK links our `printf` calls to its `__wrap_printf` wrapper. + +The rest of the chain is the same two keystrokes per function (`G`, then `Y`). This is **our code plus the library functions it actually calls** — not the whole SDK. The call chain for this project: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init +│ │ └── uart_init ── clock_get_hz, busy_wait_us +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ └── stdio_put_string ── strlen, time_us_64 +├── gpio_init +├── ir_init ── gpio_init, gpio_set_pulls +├── ir_getkey ── time_us_64 (the NEC timing helpers are inlined) +└── __wrap_printf ── __wrap_vprintf +``` + +**Project 1 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x100002cc` | `ir_init` | `void ir_init(uint8_t)` | +| `0x100002f4` | `ir_getkey` | `int ir_getkey(void)` | +| `0x100004e8` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000524` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x1000054c` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000fa8` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x1000118c` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011a0` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001220` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x100013f4` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x1000310c` | `exit` | `void exit(int)` | +| `0x10003114` | `runtime_init` | `void runtime_init(void)` | +| `0x10003140` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003250` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x1000333c` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x10003364` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x100033f4` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003430` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x100034f4` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036b0` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x100037f0` | `strlen` | `size_t strlen(const char*)` | + +> **A `void` return type may not stick — here is the fix.** IDA treats `void` as low-confidence, and its analysis can override it with an inferred type — most often `int32_t` on this 32-bit target. It is most visible on `_reset_handler` (a hand-written assembly entry that never returns normally), but it can happen to **any** function whose return type IDA thinks it can infer. +> +> Setting the full signature with `Y` reproduces the unwanted `int32_t`, and `fn.return_type = ...` fails too. What works is the **return-value** setter: +> +> ```python +> from binaryninja import ReturnValue, Type +> fn = bv.get_function_at(0x1000015c) +> if fn is not None: +> fn.return_value = ReturnValue(Type.void()) +> ``` +> +> That holds `_reset_handler` at `void` even after reanalysis. If it still will not stick, leave it — it does not affect the rest of the lesson. + +> **Shortcut — resolves name *and* type for every function.** Instead of doing `N` + `Y` by hand, paste this into IDA's Python console (`Plugins -> Python Console`). It sets each function's name and signature programmatically: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x100002cc: ("ir_init", "void ir_init(uint8_t)"), +> 0x100002f4: ("ir_getkey", "int ir_getkey(void)"), +> 0x100004e8: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000524: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x1000054c: ("gpio_init", "void gpio_init(uint)"), +> 0x10000fa8: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x1000118c: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011a0: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001220: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x100013f4: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x1000310c: ("exit", "void exit(int)"), +> 0x10003114: ("runtime_init", "void runtime_init(void)"), +> 0x10003140: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003250: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x1000333c: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x10003364: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x100033f4: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003430: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x100034f4: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036b0: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x100037f0: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` +> +> SDK type names (`stdio_driver_t`, `uart_inst_t`, `gpio_function_t`, `clock_handle_t`, plus `uint`, `va_list`) are **not** in the raw `.bin`. `set_user_type` re-parses each signature as C, so an undefined name raises `SyntaxError: unknown type name '...'` and stops the loop — it is not harmless. The `sdk` block above defines them first. Standard names (`uint8_t`, `uint32_t`, `uint64_t`, `bool`, `size_t`) are built in. + +### Step 17: Read `main` in the decompiler + +Open the **Decompiler** view on `main`. The whole program is one function because every `static` helper was inlined: + +```asm +10000234
: +10000234: b508 push {r3, lr} +10000236: f003 f895 bl 10003364 +1000023a: 2010 movs r0, #16 +1000023c: f000 f986 bl 1000054c +10000240: 2510 movs r5, #16 +10000242: f04f 0401 mov.w r4, #1 +10000246: ec44 5044 mcrr 0, 4, r5, r4, cr4 +1000024a: 2011 movs r0, #17 +1000024c: f000 f97e bl 1000054c +10000250: 2311 movs r3, #17 +10000252: ec44 3044 mcrr 0, 4, r3, r4, cr4 +10000256: 2012 movs r0, #18 +10000258: f000 f978 bl 1000054c +1000025c: 2312 movs r3, #18 +1000025e: ec44 3044 mcrr 0, 4, r3, r4, cr4 +10000262: 2005 movs r0, #5 +10000264: f000 f832 bl 100002cc +10000268: 2105 movs r1, #5 +1000026a: 4816 ldr r0, [pc, #88] +1000026c: f003 f942 bl 100034f4 <__wrap_printf> +10000270: f000 f840 bl 100002f4 +10000274: 1e04 subs r4, r0, #0 +10000276: db21 blt.n 100002bc +10000278: 4621 mov r1, r4 +1000027a: 4813 ldr r0, [pc, #76] +1000027c: f003 f93a bl 100034f4 <__wrap_printf> +10000280: f1a4 030c sub.w r3, r4, #12 +10000284: fab3 f383 clz r3, r3 +10000288: 095b lsrs r3, r3, #5 +1000028a: ec43 5040 mcrr 0, 4, r5, r3, cr0 +1000028e: f1a4 0218 sub.w r2, r4, #24 +10000292: fab2 f282 clz r2, r2 +10000296: 2311 movs r3, #17 +10000298: 0952 lsrs r2, r2, #5 +1000029a: ec42 3040 mcrr 0, 4, r3, r2, cr0 +1000029e: f1a4 045e sub.w r4, r4, #94 +100002a2: fab4 f484 clz r4, r4 +100002a6: 2312 movs r3, #18 +100002a8: 0964 lsrs r4, r4, #5 +100002aa: ec44 3040 mcrr 0, 4, r3, r4, cr0 +100002ae: 200a movs r0, #10 +100002b0: f000 fe7a bl 10000fa8 +100002b4: f000 f81e bl 100002f4 +100002b8: 1e04 subs r4, r0, #0 +100002ba: dadd bge.n 10000278 +100002bc: 2001 movs r0, #1 +100002be: f000 fe73 bl 10000fa8 +100002c2: e7d5 b.n 10000270 +100002c4: 100038b0 .word 0x100038b0 +100002c8: 100038d0 .word 0x100038d0 +``` + +The decompiler reads roughly: + +```c +int32_t main(void) +{ + stdio_init_all(); + gpio_init(0x10); gpio_set_dir(0x10, 1); // led1_pin = 16 + gpio_init(0x11); gpio_set_dir(0x11, 1); // led2_pin = 17 + gpio_init(0x12); gpio_set_dir(0x12, 1); // led3_pin = 18 + ir_init(5); + __wrap_printf("IR receiver on GPIO %d ready\n", 5); + do + { + int32_t key = ir_getkey(); + if (key >= 0) + { + __wrap_printf("NEC command: 0x%02X\n", key); + mcrr(0x10, key == 0x0c); // led1_pin = 16 + mcrr(0x11, key == 0x18); // led2_pin = 17 + mcrr(0x12, key == 0x5e); // led3_pin = 18 + sleep_ms(10); + } + else + { + sleep_ms(1); + } + } while (true); +} +``` + +- **There is no struct.** `16`, `17`, `18` are immediates; `led1_state` etc. are the `clz`-computed register values. +- The `clz`/`lsrs` pair is how the compiler turns `(key == 0x0C)` into a `0`/`1` without a branch: `sub.w r3, r4, #12` sets the flags, `clz r3, r3` counts leading zeros, `lsrs r3, r3, #5` reduces it to `0` or `1`. +- `0x100002c4` and `0x100002c8` point at `"IR receiver on GPIO %d ready\n"` (`0x100038b0`) and `"NEC command: 0x%02X\n"` (`0x100038d0`) in `.rodata`. + +### Step 18: Patch 1 — swap LED1 and LED3 pins + +The original lesson swaps LED pin assignments. LED1 is the red LED on GPIO 16 and LED3 is the yellow LED on GPIO 18. Swap them so button **"1"** lights yellow and button **"3"** lights red. The two pins are hard-coded immediates: + +| Address | Instruction | Bytes before | Bytes after | Role | +| ------- | ----------- | ------------ | ----------- | ---- | +| `0x10000240` | `movs r5, #16` | `10 25` | `12 25` | LED1's pin (`r5`) 16 -> 18 | +| `0x100002a6` | `movs r3, #18` | `12 23` | `10 23` | LED3's pin (`r3`) 18 -> 16 | + +In the **Hex** view (`View -> Hex`, lock off) change the low byte of each, then right-click `main` -> `Reanalyze`. Or in the Python console: + +```python +bv.write(0x10000240, b"\x12") # movs r5, #18 (LED1 -> GPIO 18) +bv.write(0x100002a6, b"\x10") # movs r3, #16 (LED3 -> GPIO 16) +print(bv.read(0x10000240, 2).hex(" ")) # -> 12 25 +print(bv.read(0x100002a6, 2).hex(" ")) # -> 10 23 +``` + +After reanalysis the loop reads `movs r5, #18` and `movs r3, #16`, so button **"1"** drives GPIO 18 (yellow) and button **"3"** drives GPIO 16 (red). The `NEC command:` log still prints the *command byte*, so the log and the physical LED mapping no longer agree — the log desynchronization. + +### Step 18b: Patch 2 — rename the `NEC` string to `PWN` + +The format string `"NEC command: 0x%02X\n"` starts at `0x100038d0`. Its first three bytes are `4e 45 43` (`NEC`). Change them to `50 57 4e` (`PWN`), leaving the ` command: 0x%02X\n` tail untouched, so the line prints `PWN command: 0x0C`. + +**Option A — Hex view:** go to `0x100038d0` and change the three bytes `4e 45 43` to `50 57 4e`, then reanalyze. + +**Option B — Python console:** + +```python +bv.write(0x100038d0, b"PWN") +print(bv.read(0x100038d0, 20)) # -> b'PWN command: 0x%02X\n\x00' +``` + +Keep the replacement exactly three bytes. If you use a shorter string you must pad it, or `%02X` shifts and `printf` reads the wrong argument. A longer string would overwrite the ` command:` tail. + +### Step 19: Export the patched `.bin` + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size come from the view itself +out = os.path.join(os.path.join(root, "0x0023_structures", "build"), "0x0023_structures-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16372 /.../build/0x0023_structures-h.bin +``` + +Where the two numbers come from — nothing is hardcoded: + +- **`seg.start`** is the image base IDA loaded the `.bin` at (`0x10000000`), the same value you pass to `uf2conv --base`. +- **`seg.data_length`** is the segment's size in the file (`0x3ff4` = 16372). Exactly one segment carries data (the image); every peripheral and synthetic segment has `data_length == 0`, so `next(...)` picks the image. + +> **No relative path.** IDA's Python console runs with a read-only working directory (inside the app bundle), so a relative `open(...)` fails with `OSError: [Errno 30] Read-only file system`. `root` (from `~/.embedded-hacking-repo`, Step 3) is the repo, so the file is written into the project's `build/`. + +### Step 20: Convert to UF2 + +Run from the project directory: + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0023_structures-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0023_structures-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +> **Or convert from the IDA console** — `chdir` to a writable directory first (the default one is read-only), then run the script: +> +> ```python +> import os, sys, runpy +> os.chdir(os.path.join(root, "0x0023_structures", "build")) # the project build dir (writable) +> sys.argv = ["uf2conv.py", "0x0023_structures-h.bin", +> "--base", "0x10000000", "--family", "0xe48bff59", "--output", "hacked.uf2"] +> runpy.run_path("../../uf2conv.py", run_name="__main__") # path to your uf2conv.py +> ``` + +## Part 5: Static — Resolve the Functions and Patch (Project 2) + +### Step 26: Resolve the functions in the IDA GUI + +Same two keys as Step 16 — `G` to the address, then `Y` (Change Type) to set the prototype — using the Project 2 ELF symbol map from Step 4. + +#### Worked example: `main` + +1. `G` -> `0x10000234`. +2. `Y` -> `int main(void)` (IDA shows `int32_t main(void)` — the same 32-bit `int`). + +#### Worked example: `ir_init` + +1. `G` -> `0x10000318`. +2. `Y` -> `void ir_init(uint8_t pin)`. + +#### Worked example: `ir_getkey` + +1. `G` -> `0x10000340`. +2. `Y` -> `int ir_getkey(void)`. + +#### Worked example: `gpio_init` + +1. `G` -> `0x10000598`. +2. `Y` -> `void gpio_init(uint gpio)`. + +`main` calls it three times with `16`, `17`, `18` — the flattened struct pins. + +#### Worked example: `__wrap_printf` + +1. `G` -> `0x1000353c`. +2. `Y` -> `int __wrap_printf(const char *fmt, ...)`. Keep the `...` — `printf` is variadic. It forwards to `__wrap_vprintf`. + +#### Worked example: `sleep_ms` + +1. `G` -> `0x10000ff0`. +2. `Y` -> `void sleep_ms(uint32_t ms)`. + +The blink loop and the idle path both load `10` or `50` immediately before calling it. + +The call chain for this project is the same as Project 1, plus the extra `printf` and the blink loop: + +``` +main +├── stdio_init_all ── stdio_uart_init ── gpio_set_function, uart_init +│ │ └── uart_init ── clock_get_hz, busy_wait_us +│ ├── stdio_set_driver_enabled +│ ├── stdio_out_chars_crlf +│ └── stdio_put_string ── strlen, time_us_64 +├── gpio_init +├── ir_init ── gpio_init, gpio_set_pulls +├── ir_getkey ── time_us_64 (the NEC timing helpers are inlined) +├── __wrap_printf ── __wrap_vprintf (NEC line and LED line) +└── sleep_ms +``` + +**Project 2 — resolve every function in that chain:** + +| Address | Rename to (`N`) | Signature (`Y`) | +| ------- | --------------- | --------------- | +| `0x1000015c` | `_reset_handler` | `void _reset_handler(void)` | +| `0x10000186` | `platform_entry` | `void platform_entry(void)` | +| `0x1000019a` | `data_cpy` | `void data_cpy(void*, void*, void*)` | +| `0x100001e4` | `_init` | `void _init(void)` | +| `0x10000210` | `frame_dummy` | `void frame_dummy(void)` | +| **`0x10000234`** | **`main`** | **`int main(void)`** | +| `0x10000318` | `ir_init` | `void ir_init(uint8_t)` | +| `0x10000340` | `ir_getkey` | `int ir_getkey(void)` | +| `0x10000534` | `gpio_set_function` | `void gpio_set_function(uint, gpio_function_t)` | +| `0x10000570` | `gpio_set_pulls` | `void gpio_set_pulls(uint, bool, bool)` | +| `0x10000598` | `gpio_init` | `void gpio_init(uint)` | +| `0x10000ff0` | `sleep_ms` | `void sleep_ms(uint32_t)` | +| `0x100011d4` | `time_us_64` | `uint64_t time_us_64(void)` | +| `0x100011e8` | `busy_wait_us` | `void busy_wait_us(uint64_t)` | +| `0x10001268` | `uart_init` | `uint uart_init(uart_inst_t*, uint)` | +| `0x1000143c` | `clock_get_hz` | `unsigned long clock_get_hz(clock_handle_t)` | +| `0x10003154` | `exit` | `void exit(int)` | +| `0x1000315c` | `runtime_init` | `void runtime_init(void)` | +| `0x10003188` | `stdio_out_chars_crlf` | `void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)` | +| `0x10003298` | `stdio_put_string` | `int stdio_put_string(const char*, int, bool, bool)` | +| `0x10003384` | `stdio_set_driver_enabled` | `void stdio_set_driver_enabled(stdio_driver_t*, bool)` | +| `0x100033ac` | `stdio_init_all` | `bool stdio_init_all(void)` | +| `0x1000343c` | `__wrap_puts` | `int __wrap_puts(const char*)` | +| `0x10003478` | `__wrap_vprintf` | `int __wrap_vprintf(const char*, va_list)` | +| `0x1000353c` | `__wrap_printf` | `int __wrap_printf(const char*, ...)` | +| `0x100036f8` | `stdio_uart_init` | `void stdio_uart_init(void)` | +| `0x10003838` | `strlen` | `size_t strlen(const char*)` | + +> **Shortcut — resolves name *and* type for every function.** Paste this into IDA's Python console: +> +> ```python +> from binaryninja import Symbol, SymbolType +> # The raw .bin has no headers, so these SDK types don't exist. set_user_type() +> # re-parses each signature as C, so an undefined name raises +> # "SyntaxError: unknown type name '...'". Define them first. +> sdk = bv.parse_types_from_string(""" +> typedef unsigned int uint; +> typedef char* va_list; +> typedef unsigned long clock_handle_t; +> struct stdio_driver; +> typedef struct stdio_driver stdio_driver_t; +> struct uart_inst; +> typedef struct uart_inst uart_inst_t; +> enum gpio_function { +> GPIO_FUNC_XIP = 0, GPIO_FUNC_SPI = 1, GPIO_FUNC_UART = 2, GPIO_FUNC_I2C = 3, +> GPIO_FUNC_PWM = 4, GPIO_FUNC_SIO = 5, GPIO_FUNC_PIO0 = 6, GPIO_FUNC_PIO1 = 7, +> GPIO_FUNC_GPCK = 8, GPIO_FUNC_USB = 9, GPIO_FUNC_NULL = 0x1f, +> }; +> typedef enum gpio_function gpio_function_t; +> """) +> for name, ty in sdk.types.items(): +> bv.define_user_type(name, ty) +> +> # address: (name, signature) +> funcs = { +> 0x1000015c: ("_reset_handler", "void _reset_handler(void)"), +> 0x10000186: ("platform_entry", "void platform_entry(void)"), +> 0x1000019a: ("data_cpy", "void data_cpy(void*, void*, void*)"), +> 0x100001e4: ("_init", "void _init(void)"), +> 0x10000210: ("frame_dummy", "void frame_dummy(void)"), +> 0x10000234: ("main", "int main(void)"), +> 0x10000318: ("ir_init", "void ir_init(uint8_t)"), +> 0x10000340: ("ir_getkey", "int ir_getkey(void)"), +> 0x10000534: ("gpio_set_function", "void gpio_set_function(uint, gpio_function_t)"), +> 0x10000570: ("gpio_set_pulls", "void gpio_set_pulls(uint, bool, bool)"), +> 0x10000598: ("gpio_init", "void gpio_init(uint)"), +> 0x10000ff0: ("sleep_ms", "void sleep_ms(uint32_t)"), +> 0x100011d4: ("time_us_64", "uint64_t time_us_64(void)"), +> 0x100011e8: ("busy_wait_us", "void busy_wait_us(uint64_t)"), +> 0x10001268: ("uart_init", "uint uart_init(uart_inst_t*, uint)"), +> 0x1000143c: ("clock_get_hz", "unsigned long clock_get_hz(clock_handle_t)"), +> 0x10003154: ("exit", "void exit(int)"), +> 0x1000315c: ("runtime_init", "void runtime_init(void)"), +> 0x10003188: ("stdio_out_chars_crlf", "void stdio_out_chars_crlf(stdio_driver_t*, const char*, int)"), +> 0x10003298: ("stdio_put_string", "int stdio_put_string(const char*, int, bool, bool)"), +> 0x10003384: ("stdio_set_driver_enabled", "void stdio_set_driver_enabled(stdio_driver_t*, bool)"), +> 0x100033ac: ("stdio_init_all", "bool stdio_init_all(void)"), +> 0x1000343c: ("__wrap_puts", "int __wrap_puts(const char*)"), +> 0x10003478: ("__wrap_vprintf", "int __wrap_vprintf(const char*, va_list)"), +> 0x1000353c: ("__wrap_printf", "int __wrap_printf(const char*, ...)"), +> 0x100036f8: ("stdio_uart_init", "void stdio_uart_init(void)"), +> 0x10003838: ("strlen", "size_t strlen(const char*)"), +> } +> for addr, (name, sig) in funcs.items(): +> bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, addr, name)) +> f = bv.get_function_at(addr) +> if f is not None: +> f.set_user_type(sig) +> ``` + +### Step 27: Patch 1 — swap LED1 and LED3 pins + +The original lesson swaps LED 1 and LED 3. LED1 is the red LED on GPIO 16 and LED3 is the yellow LED on GPIO 18. In the loop the pins are `movs r5, #16` at `0x10000284` (LED1) and `movs r2, #18` at `0x10000290` (LED3). Swap the two immediates: + +| Address | Instruction | Bytes before | Bytes after | Role | +| ------- | ----------- | ------------ | ----------- | ---- | +| `0x10000284` | `movs r5, #16` | `10 25` | `12 25` | LED1's pin (`r5`) 16 -> 18 | +| `0x10000290` | `movs r2, #18` | `12 22` | `10 22` | LED3's pin (`r2`) 18 -> 16 | + +```python +bv.write(0x10000284, b"\x12") # movs r5, #18 (LED1 -> GPIO 18) +bv.write(0x10000290, b"\x10") # movs r2, #16 (LED3 -> GPIO 16) +print(bv.read(0x10000284, 2).hex(" ")) # -> 12 25 +print(bv.read(0x10000290, 2).hex(" ")) # -> 10 22 +``` + +Now button **"1"** blinks GPIO 18 (yellow) and button **"3"** blinks GPIO 16 (red). The `LED N activated on GPIO P` prints are **not** changed, so they still say `GPIO 16` and `GPIO 18` — **the log no longer matches the hardware.** That mismatch is the security lesson: the operator's console shows the old, expected mapping while the pins do something else. + +> **Optional consistency patch.** If you want the print to tell the truth instead, also change `movs r2, #16` at `0x100002f8` to `#18` (and the key-3 print constant `movne r2, #18` at `0x100002ea` to `#16`). For this lesson we leave them alone on purpose, so the desynchronization is visible. +> +> | Address | Instruction | Bytes before | Bytes after | Role | +> | ------- | ----------- | ------------ | ----------- | ---- | +> | `0x100002f8` | `movs r2, #16` | `10 22` | `12 22` | optional: key-1 print now says GPIO 18 | + +### Step 27b: Patch 2 — rename the `NEC` string to `PWN` + +The format string starts at `0x10003918`; change its first three bytes `4e 45 43` (`NEC`) to `50 57 4e` (`PWN`): + +```python +bv.write(0x10003918, b"PWN") +print(bv.read(0x10003918, 20)) # -> b'PWN command: 0x%02X\n\x00' +``` + +Exactly three bytes, same rule as Project 1: a shorter string must be padded, a longer one overwrites the ` command:` tail. + +### Step 28: Export, convert and export + +```python +import os +seg = next(s for s in bv.segments if s.data_length) # the loadable image segment +data = bv.read(seg.start, seg.data_length) # base + size from the view itself +out = os.path.join(os.path.join(root, "0x0026_functions", "build"), "0x0026_functions-h.bin") +open(out, "wb").write(data) +print(len(data), out) # -> 16476 /.../build/0x0026_functions-h.bin +``` + +`seg.data_length` is the image size (`0x405c` = 16476) read from the view — nothing hardcoded. + +**macOS Apple Silicon / Linux x64:** + +```bash +python3 ../uf2conv.py 0x0026_functions-h.bin \ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +**Windows x64:** + +```cmd +python ..\uf2conv.py 0x0026_functions-h.bin ^ + --base 0x10000000 --family 0xe48bff59 --output hacked.uf2 +``` + +Or run the conversion from the IDA console, exactly as in Step 20 (`os.chdir` to the build dir, then `runpy.run_path("../../uf2conv.py", run_name="__main__")` with `sys.argv` set to the arguments above). + +Hold **BOOTSEL**, plug in the Pico 2, drag `hacked.uf2` onto the **`RP2350`** drive. Or flash the `.bin` over the Debug Probe with SWD — no BOOTSEL — from the console, exactly as in Step 21. + +## Glossary + +| Term | Definition | +| ---- | ---------- | +| **`.bss`** | Section for uninitialized global variables; zeroed by startup code | +| **`.data`** | Section for initialized global variables; copied from flash to SRAM at boot | +| **`.elf`** | Linked image with the symbol table; the ground truth for addresses and names | +| **Flattening** | The optimizer replacing struct member accesses with the member's constant value; why `simple_led_ctrl_t` disappears | +| **GPIO** | General Purpose Input/Output — controllable pins on the microcontroller | +ly flash | +| **Inlining** | The optimizer replacing a function call with the function body; why every `static` helper disappears from `main` | +| **Literal pool** | A block of 32-bit constants that Thumb-2 code reaches with PC-relative `ldr` | +| **`mcrr`** | Move to coprocessor from two registers — how the SIO GPIO writes are encoded | +| **NEC** | A common IR protocol: 9 ms leader + 4.5 ms space, then 32 data bits (address, ~address, command, ~command) | +| **`.rodata`** | Read-only section for constants and string literals; stays in flash | +| **SIO** | Single-cycle I/O — the fast GPIO block in the RP2350, at `0xd0000000` | +| **Thumb bit** | Bit 0 of a Cortex-M function pointer; selects Thumb instruction mode | +| **UF2** | USB Flashing Format — the file format the Pico 2 bootloader accepts | +| **Vector table** | The first words of flash: initial stack pointer and exception vectors | + +--- + +**Remember:** the ELF tells you what every address is, and the `.bin` is what you actually patch. Verify the static behavior from the recovered instructions. \ No newline at end of file diff --git a/WEEK11/WEEK11-IDA.pdf b/WEEK11/WEEK11-IDA.pdf new file mode 100644 index 0000000..27cb09e Binary files /dev/null and b/WEEK11/WEEK11-IDA.pdf differ diff --git a/WEEK11/WEEK11-SLIDES.pdf b/WEEK11/WEEK11-SLIDES.pdf new file mode 100644 index 0000000..a21fe50 Binary files /dev/null and b/WEEK11/WEEK11-SLIDES.pdf differ diff --git a/WEEK11/WEEK11.md b/WEEK11/WEEK11.md new file mode 100644 index 0000000..0ba1925 --- /dev/null +++ b/WEEK11/WEEK11.md @@ -0,0 +1,1607 @@ +# Week 11: Structures and Functions in Embedded Systems: Debugging and Hacking w/ IR Remote Control and NEC Protocol Basics + +*** +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand C structures (structs) and how they organize related data +- Know how structs are represented in memory and assembly code +- Understand the NEC infrared (IR) protocol for remote control communication +- Create and use functions with parameters and return values +- Identify struct member access patterns in Ghidra +- Recognize how compilers "flatten" structs into individual operations +- Hack GPIO pin assignments to swap LED behavior +- Understand the security implications of log/behavior desynchronization +- Analyze .elf files in addition to .bin files in Ghidra + +--- + +## Part 1: Understanding C Structures (Structs) + +### What is a Struct? + +A **structure** (or **struct**) is a user-defined data type that groups related variables together under one name. Think of it like a form with multiple fields - each field can hold different types of data, but they all belong together. + +```c +// Define a struct type +typedef struct { + uint8_t led1_pin; // GPIO pin for LED 1 + uint8_t led2_pin; // GPIO pin for LED 2 + uint8_t led3_pin; // GPIO pin for LED 3 + bool led1_state; // Is LED 1 on? + bool led2_state; // Is LED 2 on? + bool led3_state; // Is LED 3 on? +} simple_led_ctrl_t; +``` + +``` ++-----------------------------------------------------------------+ +| Structure as a Container | +| | +| simple_led_ctrl_t leds | +| +-------------------------------------------------------------+ | +| | led1_pin: 16 led2_pin: 17 led3_pin: 18 | | +| | +--------+ +--------+ +--------+ | | +| | | 16 | | 17 | | 18 | | | +| | +--------+ +--------+ +--------+ | | +| | | | +| | led1_state: false led2_state: false led3_state: false | | +| | +--------+ +--------+ +--------+ | | +| | | false | | false | | false | | | +| | +--------+ +--------+ +--------+ | | +| +-------------------------------------------------------------+ | +| | +| All 6 members live together as ONE variable called "leds" | +| | ++-----------------------------------------------------------------+ +``` + +### Why Use Structs? + +| Without Structs (Messy!) | With Structs (Clean!) | +| -------------------------- | --------------------------- | +| `uint8_t led1_pin = 16;` | `simple_led_ctrl_t leds;` | +| `uint8_t led2_pin = 17;` | `leds.led1_pin = 16;` | +| `uint8_t led3_pin = 18;` | `leds.led2_pin = 17;` | +| `bool led1_state = false;` | `leds.led3_pin = 18;` | +| `bool led2_state = false;` | `leds.led1_state = false;` | +| `bool led3_state = false;` | ... (all in one container!) | + +**Benefits of Structs:** + +1. **Organization** - Related data stays together +2. **Readability** - Code is easier to understand +3. **Maintainability** - Changes are easier to make +4. **Scalability** - Easy to add more LEDs or features +5. **Passing to Functions** - Pass one struct instead of many variables + +--- + +## Part 2: Struct Memory Layout + +### How Structs are Stored in Memory + +When you create a struct, the compiler places each member in consecutive memory locations: + +``` ++-----------------------------------------------------------------+ +| Memory Layout of simple_led_ctrl_t | +| | +| Address Member Size Value | +| ------------------------------------------------------------- | +| 0x2000000 led1_pin 1 byte 16 (0x10) | +| 0x2000001 led2_pin 1 byte 17 (0x11) | +| 0x2000002 led3_pin 1 byte 18 (0x12) | +| 0x2000003 led1_state 1 byte 0 (false) | +| 0x2000004 led2_state 1 byte 0 (false) | +| 0x2000005 led3_state 1 byte 0 (false) | +| | +| Total struct size: 6 bytes | +| | ++-----------------------------------------------------------------+ +``` + +### Accessing Struct Members + +Use the **dot operator** (`.`) to access members: + +```c +simple_led_ctrl_t leds; + +// Set values +leds.led1_pin = 16; +leds.led1_state = true; + +// Read values +printf("Pin: %d\n", leds.led1_pin); +``` + +### Pointer to Struct (Arrow Operator) + +When you have a **pointer** to a struct, use the **arrow operator** (`->`): + +```c +simple_led_ctrl_t leds; +simple_led_ctrl_t *ptr = &leds; // Pointer to the struct + +// These are equivalent: +leds.led1_pin = 16; // Using dot with struct variable +ptr->led1_pin = 16; // Using arrow with pointer +(*ptr).led1_pin = 16; // Dereferencing then dot (same thing) +``` + +``` ++-----------------------------------------------------------------+ +| Dot vs Arrow Operator | +| | +| struct_variable.member <-- Use with actual struct | +| | +| pointer_to_struct->member <-- Use with pointer to struct | +| | +| The arrow (->) is shorthand for (*pointer).member | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 3: Designated Initializers + +### Clean Struct Initialization + +C allows you to initialize struct members by name using **designated initializers**: + +```c +simple_led_ctrl_t leds = { + .led1_pin = 16, + .led2_pin = 17, + .led3_pin = 18, + .led1_state = false, + .led2_state = false, + .led3_state = false +}; +``` + +**Benefits:** + +- Clear which value goes to which member +- Order doesn't matter (can rearrange lines) +- Self-documenting code +- Easy to add new members later + +--- + +## Part 4: Understanding the NEC IR Protocol + +### What is Infrared (IR) Communication? + +**Infrared** communication uses invisible light pulses to send data. Your TV remote uses IR to send commands to your TV. The LED in the remote flashes on and off very quickly in specific patterns that represent different buttons. + +``` ++-----------------------------------------------------------------+ +| IR Communication | +| | +| Remote Control IR Receiver | +| +----------+ +----------+ | +| | Button | | | | +| | 1 | --- IR Light Pulses --- | ++ | | +| | +---+ | ~~~~~~~~~~~~> | Sensor | | +| | | Tx | | | | | +| | +---+ | +----+-----+ | +| | IR LED | | | +| +----------+ v | +| GPIO Pin | +| (Digital signal) | +| | ++-----------------------------------------------------------------+ +``` + +### The NEC Protocol + +**NEC** is one of the most common IR protocols. When you press a button, the remote sends: + +1. **Leader pulse** - 9ms HIGH, 4.5ms LOW (says "attention!") +2. **Address** - 8 bits identifying the device +3. **Address Inverse** - 8 bits (for error checking) +4. **Command** - 8 bits for the button pressed +5. **Command Inverse** - 8 bits (for error checking) + +``` ++-----------------------------------------------------------------+ +| NEC Protocol Frame | +| | +| +---------+---------+---------+---------+---------+---------+ | +| | Leader | Address | Address | Command | Command | Stop | | +| | Pulse | 8-bit | Inverse | 8-bit | Inverse | Bit | | +| | 9+4.5ms | | 8-bit | | 8-bit | | | +| +---------+---------+---------+---------+---------+---------+ | +| | +| Total: 32 bits of data (+ leader + stop) | +| | ++-----------------------------------------------------------------+ +``` + +### NEC Command Codes for Our Remote + +| Button | NEC Command Code | Hex Value | +| ------ | ---------------- | --------- | +| 1 | 0x0C | 12 | +| 2 | 0x18 | 24 | +| 3 | 0x5E | 94 | + +**Note:** Different remotes have different codes. These are specific to our example remote. + +--- + +## Part 5: Understanding Functions in C + +### What is a Function? + +A **function** is a reusable block of code that performs a specific task. Functions help organize code and avoid repetition. + +```c +// Function definition +int add_numbers(int a, int b) { + return a + b; +} + +// Function call +int result = add_numbers(5, 3); // result = 8 +``` + +### Function Components + +``` ++-----------------------------------------------------------------+ +| Anatomy of a Function | +| | +| return_type function_name ( parameters ) { | +| // function body | +| return value; | +| } | +| | +| Example: | +| +-------------------------------------------------------------+ | +| | int ir_to_led_number ( int ir_command ) { | | +| | --- --------------- --------------- | | +| | | | | | | +| | | | +-- Parameter (input) | | +| | | +-- Function name | | +| | +-- Return type (what it gives back) | | +| | | | +| | if (ir_command == 0x0C) return 1; <-- Body | | +| | if (ir_command == 0x18) return 2; | | +| | return 0; <-- Return value | | +| | } | | +| +-------------------------------------------------------------+ | +| | ++-----------------------------------------------------------------+ +``` + +### Types of Functions + +| Type | Description | Example | +| ---------------------------- | ------------------------- | ---------------------------- | +| **No params, no return** | Just does something | `void leds_all_off(void)` | +| **With params, no return** | Takes input, no output | `void blink_led(pin, count)` | +| **No params, with return** | No input, gives output | `int ir_getkey(void)` | +| **With params, with return** | Takes input, gives output | `int ir_to_led_number(cmd)` | + +--- + +## Part 6: Functions with Struct Pointers + +### Passing Structs to Functions + +When passing a struct to a function, you usually pass a **pointer** to avoid copying all the data: + +```c +// Function takes a POINTER to the struct +void leds_all_off(simple_led_ctrl_t *leds) { + gpio_put(leds->led1_pin, false); // Use arrow operator! + gpio_put(leds->led2_pin, false); + gpio_put(leds->led3_pin, false); +} + +// Call with address-of operator +simple_led_ctrl_t my_leds; +leds_all_off(&my_leds); // Pass the ADDRESS of my_leds +``` + +``` ++-----------------------------------------------------------------+ +| Passing Struct by Pointer | +| | +| main() { | +| simple_led_ctrl_t leds; <-- Struct lives here | +| leds_all_off(&leds); <-- Pass ADDRESS (pointer) | +| } | | +| | | +| v | +| leds_all_off(simple_led_ctrl_t *leds) { | +| gpio_put(leds->led1_pin, false); | +| ---- | +| | | +| +-- Arrow because leds is a POINTER | +| } | +| | +| WHY use pointers? | +| - Efficient: Only 4 bytes (address) instead of entire struct | +| - Allows modification: Function can change the original | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 7: How Compilers Handle Structs + +### Struct "Flattening" in Assembly + +When the compiler converts your C code to assembly, it "flattens" struct operations into individual memory accesses: + +**C Code:** +```c +gpio_init(leds.led1_pin); // leds.led1_pin = 16 +gpio_init(leds.led2_pin); // leds.led2_pin = 17 +gpio_init(leds.led3_pin); // leds.led3_pin = 18 +``` + +**Assembly (what the compiler produces):** +```assembly +movs r0, #0x10 ; r0 = 16 (led1_pin value) +bl gpio_init ; call gpio_init(16) + +movs r0, #0x11 ; r0 = 17 (led2_pin value) +bl gpio_init ; call gpio_init(17) + +movs r0, #0x12 ; r0 = 18 (led3_pin value) +bl gpio_init ; call gpio_init(18) +``` + +``` ++-----------------------------------------------------------------+ +| Struct Flattening | +| | +| C Level (High-level abstraction): | +| +-------------------------------------------------------------+ | +| | gpio_init(leds.led1_pin); | | +| | gpio_init(leds.led2_pin); | | +| | gpio_init(leds.led3_pin); | | +| +-------------------------------------------------------------+ | +| | | +| | Compiler transforms | +| v | +| Assembly Level (Flattened): | +| +-------------------------------------------------------------+ | +| | movs r0, #16 ; Just the VALUE, no struct reference | | +| | bl gpio_init | | +| | movs r0, #17 ; Next value directly | | +| | bl gpio_init | | +| | movs r0, #18 ; Next value directly | | +| | bl gpio_init | | +| +-------------------------------------------------------------+ | +| | +| The struct abstraction DISAPPEARS at the assembly level! | +| We just see individual values being loaded and used. | +| | ++-----------------------------------------------------------------+ +``` + +### Why This Matters for Reverse Engineering + +- In Ghidra, you won't always see "struct" - just individual values +- You must recognize PATTERNS (sequential values like 16, 17, 18) +- Understanding flattening helps you reconstruct the original struct + +--- + +## Part 8: Setting Up Your Environment + +### Prerequisites + +Before we start, make sure you have: + +1. A Raspberry Pi Pico 2 board +2. A Raspberry Pi Pico Debug Probe +3. Ghidra installed (for static analysis) +4. Python installed (for UF2 conversion) +5. A serial monitor (PuTTY, minicom, or screen) +6. An IR receiver module (like VS1838B) +7. An IR remote control (any NEC-compatible remote) +8. Three LEDs (red, green, yellow) with resistors +9. The sample projects: `0x0023_structures` and `0x0026_functions` + +### Hardware Setup + +**IR Receiver Wiring:** + +| IR Receiver Pin | Pico 2 Pin | +| --------------- | ---------- | +| VCC | 3.3V | +| GND | GND | +| OUT/DATA | GPIO 5 | + +**LED Wiring:** + +| LED | GPIO Pin | Resistor | +| ------ | -------- | --------- | +| Red | GPIO 16 | 220-330 ohm | +| Green | GPIO 17 | 220-330 ohm | +| Yellow | GPIO 18 | 220-330 ohm | + +``` ++-----------------------------------------------------------------+ +| Complete Wiring Diagram | +| | +| Pico 2 Components | +| +----------+ | +| | | +-------------+ | +| | GPIO 5 |--------------+ IR Receiver | | +| | | | (VS1838B) | | +| | | +------+------+ | +| | | | | +| | GPIO 16 |---[220 ohm]---(RED LED)----+ | +| | | | | +| | GPIO 17 |---[220 ohm]---(GRN LED)----+ | +| | | | | +| | GPIO 18 |---[220 ohm]---(YEL LED)----+ | +| | | | | +| | 3.3V |-------------------------+-- IR VCC | +| | | | | +| | GND |-------------------------+-- All GNDs | +| | | | +| +----------+ | +| | ++-----------------------------------------------------------------+ +``` + +### Project Structure + +``` +Embedded-Hacking/ ++-- 0x0023_structures/ +| +-- build/ +| | +-- 0x0023_structures.uf2 +| | +-- 0x0023_structures.bin +| +-- main/ +| | +-- 0x0023_structures.c +| +-- ir.h ++-- 0x0026_functions/ +| +-- build/ +| | +-- 0x0026_functions.uf2 +| | +-- 0x0026_functions.bin +| | +-- 0x0026_functions.elf +| +-- main/ +| | +-- 0x0026_functions.c +| +-- ir.h ++-- uf2conv.py +``` + +--- + +## Part 9: Hands-On Tutorial - Structures Code + +### Step 1: Review the Source Code + +Let's examine the structures code: + +**File: `0x0023_structures.c`** + +```c +#include +#include +#include "pico/stdlib.h" +#include "ir.h" + +#define IR_PIN 5 + +typedef struct { + uint8_t led1_pin; + uint8_t led2_pin; + uint8_t led3_pin; + bool led1_state; + bool led2_state; + bool led3_state; +} simple_led_ctrl_t; + +int main(void) { + stdio_init_all(); + + simple_led_ctrl_t leds = { + .led1_pin = 16, + .led2_pin = 17, + .led3_pin = 18, + .led1_state = false, + .led2_state = false, + .led3_state = false + }; + + gpio_init(leds.led1_pin); gpio_set_dir(leds.led1_pin, GPIO_OUT); + gpio_init(leds.led2_pin); gpio_set_dir(leds.led2_pin, GPIO_OUT); + gpio_init(leds.led3_pin); gpio_set_dir(leds.led3_pin, GPIO_OUT); + + ir_init(IR_PIN); + printf("IR receiver on GPIO %d ready\n", IR_PIN); + + while (true) { + int key = ir_getkey(); + if (key >= 0) { + printf("NEC command: 0x%02X\n", key); + + // Turn all off first + leds.led1_state = false; + leds.led2_state = false; + leds.led3_state = false; + + // Check NEC codes + if (key == 0x0C) leds.led1_state = true; // GPIO16 + if (key == 0x18) leds.led2_state = true; // GPIO17 + if (key == 0x5E) leds.led3_state = true; // GPIO18 + + // Apply states + gpio_put(leds.led1_pin, leds.led1_state); + gpio_put(leds.led2_pin, leds.led2_state); + gpio_put(leds.led3_pin, leds.led3_state); + + sleep_ms(10); + } else { + sleep_ms(1); + } + } +} +``` + +### Step 2: Understand the Program Flow + +``` ++-----------------------------------------------------------------+ +| Program Flow | +| | +| 1. Initialize UART (stdio_init_all) | +| 2. Create LED struct with pins 16, 17, 18 | +| 3. Initialize GPIO pins as outputs | +| 4. Initialize IR receiver on GPIO 5 | +| 5. Enter infinite loop: | +| a. Check for IR key press | +| b. If key received: | +| - Print the NEC command code | +| - Turn all LEDs off | +| - Check which button: 0x0C, 0x18, or 0x5E | +| - Turn on the matching LED | +| - Apply states to GPIO pins | +| c. Sleep briefly and repeat | +| | ++-----------------------------------------------------------------+ +``` + +### Step 3: Flash the Binary to Your Pico 2 + +1. Hold the BOOTSEL button on your Pico 2 +2. Plug in the USB cable (while holding BOOTSEL) +3. Release BOOTSEL - a drive called "RPI-RP2" appears +4. Drag and drop `0x0023_structures.uf2` onto the drive +5. The Pico will reboot and start running! + +### Step 4: Verify It's Working + +**Open PuTTY (115200 baud) and test:** + +- Press "1" on remote -> Red LED lights, terminal shows `NEC command: 0x0C` +- Press "2" on remote -> Green LED lights, terminal shows `NEC command: 0x18` +- Press "3" on remote -> Yellow LED lights, terminal shows `NEC command: 0x5E` + +--- + +## Part 10: Debugging with GDB (Structures) + +### Step 5: Start OpenOCD (Terminal 1) + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +You should see output indicating OpenOCD connected successfully to your Pico 2 via the Debug Probe. + +### Step 6: Start GDB (Terminal 2) + +Open a **new terminal** and launch GDB with the binary: + +```cmd +arm-none-eabi-gdb build\0x0023_structures.elf +``` + +### Step 7: Connect to the Remote Target + +In GDB, connect to OpenOCD: + +```gdb +target extended-remote :3333 +``` + +### Step 8: Halt the Running Binary + +Stop the processor: + +```gdb +monitor halt +``` + +### Step 9: Examine Main Function + +Disassemble around main to see struct initialization: + +```gdb +disassemble 0x10000234,+200 +``` + +Look for the struct member initialization sequence (mov instructions with values 16, 17, 18). + +### Step 10: Set a Breakpoint at Main + +```gdb +break *0x10000234 +``` + +Reset and run to hit the breakpoint: + +```gdb +monitor reset halt +continue +``` + +### Step 11: Observe the Flattened Struct + +Instead of allocating the struct on the stack, the compiler completely **flattened and optimized** it out! There is no `sub sp` instruction for the struct. + +Examine the `main` disassembly again: + +```gdb +disassemble 0x10000234,+200 +``` + +Notice how values 16, 17, and 18 are just loaded directly into registers (`movs r0, #16`, etc.) and passed to functions. The struct abstraction is entirely gone. + +### Step 12: Watch GPIO Initialization + +Set a breakpoint on the first `gpio_init` call and watch the LED pin get initialized: + +```gdb +break *0x1000023c +continue +info registers r0 +``` + +You should see `r0 = 16`. If you set breakpoints on the subsequent calls (`0x1000024c`, `0x10000258`) and continue, you will see `17` and `18`. + +### Step 13: Examine IR Key Processing + +Because `ir_getkey` is polled in a loop and returns `-1` constantly when no key is pressed, breaking at the immediate return (`0x10000274`) will just flood you with `-1`s! + +Instead, set a breakpoint *inside* the `if (key >= 0)` block at `0x10000278`. This is right after the `blt.n` conditional branch that skips over the processing logic when no key is pressed: + +```gdb +break *0x10000278 +continue +``` + +Now press a button on the remote. The program will halt. At this point, the key value has been moved into `r4` (from the `subs r4, r0, #0` instruction earlier): + +```gdb +info registers r4 +``` + +You'll see the decimal value of the NEC code (e.g., 12 for `0x0C`, 24 for `0x18`, or 94 for `0x5E`). + +### Step 14: Watch the Conditional Checks + +Let's look at the comparisons where the code checks which button was pressed: + +```gdb +break *0x10000280 +continue +``` + +*(Note: If the program doesn't halt immediately, press a button on the remote to trigger the breakpoint!)* + +```gdb +x/8i $pc +``` + +Notice the compiler uses decimal comparisons: `cmp r4, #12` (which is `0x0c`), `cmp r4, #24` (which is `0x18`), and a subtraction trick `sub.w r4, r4, #94` (which is `0x5e`) to determine which button was pressed. + +### Step 15: Observe Inlined GPIO Operations + +The compiler even inlined the `gpio_put` calls! First, let's clear any old breakpoints so we don't accidentally stop somewhere else (like you might have seen if you hit an old breakpoint first!): + +```gdb +delete +break *0x10000298 +continue +``` + +*(Note: Again, press a button on the remote if it doesn't halt immediately!)* + +Now check the registers: + +```gdb +info registers r1 r2 r3 r4 +``` + +Depending on which button you pressed, one of the state registers will be `1` (ON) and the others will be `0` (OFF): + +- `r1` = State for the **Red** LED (GPIO 16) +- `r3` = State for the **Green** LED (GPIO 17) +- `r4` = State for the **Yellow** LED (GPIO 18) +- `r2` = `16` (`0x10`), which is the starting pin number being written to. + +*(Note: Since you are paused here, the physical LEDs haven't updated yet! They will only change after these `mcrr` instructions execute.)* + +Instead of branching to `gpio_put`, it uses direct hardware instructions (disassembled as `mcrr` on the RP2350) to write the states directly to the GPIO hardware. + +### Step 16: Exit GDB + +When done exploring: + +```gdb +quit +``` + +--- + +## Part 11: Setting Up Ghidra for Structures + +### Step 17: Start Ghidra + +Open a terminal and type: + +```cmd +ghidraRun +``` + +### Step 18: Create a New Project + +1. Click **File** -> **New Project** +2. Select **Non-Shared Project** +3. Click **Next** +4. Enter Project Name: `0x0023_structures` +5. Click **Finish** + +### Step 19: Import the Binary + +1. Navigate to the `0x0023_structures/build/` folder +2. **Drag and drop** the `.bin` file into Ghidra's project window + +### Step 20: Configure the Binary Format + +**Click the three dots (...) next to "Language" and:** + +1. Search for "Cortex" +2. Select **ARM Cortex 32 little endian default** +3. Click **OK** + +**Click the "Options..." button and:** + +1. Change **Block Name** to `.text` +2. Change **Base Address** to `10000000` +3. Click **OK** + +### Step 21: Analyze the Binary + +1. Double-click on the file in the project window +2. A dialog asks "Analyze now?" - Click **Yes** +3. Use default analysis options and click **Analyze** + +Wait for analysis to complete. + +--- + +## Part 12: Resolving Functions - Structures Project + +### Step 22: Navigate to Main + +1. Press `G` (Go to address) and type `10000234` +2. Right-click -> **Edit Function Signature** +3. Change to: `int main(void)` +4. Click **OK** + +### Step 23: Resolve stdio_init_all + +At address `0x10000236`: + +1. Double-click on the called function +2. Right-click -> **Edit Function Signature** +3. Change to: `bool stdio_init_all(void)` +4. Click **OK** + +### Step 24: Identify gpio_init from Struct Pattern + +Look for three consecutive calls with values 16, 17, 18: + +```assembly +1000023a 10 20 movs r0,#0x10 +1000023c 00 f0 8c f9 bl FUN_10000558 ; gpio_init + +1000024a 11 20 movs r0,#0x11 +1000024c 00 f0 84 f9 bl FUN_10000558 ; gpio_init + +10000256 12 20 movs r0,#0x12 +10000258 00 f0 7e f9 bl FUN_10000558 ; gpio_init +``` + +This pattern reveals the struct members! Update the function signature: + +1. Right-click on `FUN_10000558` -> **Edit Function Signature** +2. Change to: `void gpio_init(uint gpio)` +3. Click **OK** + +### Step 25: Resolve ir_init + +Look for a function call with GPIO 5: + +```assembly +10000262 05 20 movs r0,#0x5 +10000264 00 f0 38 f8 bl FUN_100002d8 ; ir_init +``` + +1. Right-click on `FUN_100002d8` -> **Edit Function Signature** +2. Change to: `void ir_init(uint pin)` +3. Click **OK** + +### Step 26: Resolve printf + +Right after ir_init, look for the "IR receiver on GPIO" string being loaded and passed to a function: + +```assembly +1000026a 19 48 ldr r0=>s_IR_receiver_on_GPIO_%d... +1000026c 03 f0 46 f9 bl FUN_100034fc ; printf +``` + +1. Right-click on `FUN_100034fc` -> **Edit Function Signature** +2. Change to: `int printf(char *format,...)` +3. Check the **Varargs** checkbox +4. Click **OK** + +### Step 27: Resolve ir_getkey + +Look for a function that returns a value checked against conditions: + +```assembly +10000270 00 f0 46 f8 bl FUN_10000300 ; Call ir_getkey +10000274 04 1e subs r4,r0,#0x0 ; Check if >= 0 +10000276 1e db blt LAB_100002b6 ; If negative, no key pressed +``` + +1. Right-click on `FUN_10000300` -> **Edit Function Signature** +2. Change to: `int ir_getkey(void)` +3. Click **OK** + +### Step 28: Resolve sleep_ms + +Look for calls with 10 (0x0A) or 1 (0x01): + +```assembly +100002a8 0a 20 movs r0,#0xa +100002aa 00 f0 81 fe bl FUN_10000fb0 ; sleep_ms +``` + +1. Right-click on `FUN_10000fb0` -> **Edit Function Signature** +2. Change to: `void sleep_ms(uint ms)` +3. Click **OK** + +--- + +## Part 13: Recognizing Struct Patterns in Assembly + +### Step 29: Identify GPIO Set Direction + +After each `gpio_init`, look for direction setting: + +```assembly +10000240 4f f0 01 04 mov.w r4,#0x1 ; direction = output +10000244 10 23 movs r3,#0x10 ; GPIO 16 +10000246 44 ec 44 30 mcrr p0,0x4,r3,r4,cr4 ; Configure GPIO direction register +``` + +This is the compiler's heavily optimized version of `gpio_set_dir(pin, GPIO_OUT)`. + +### Step 30: Map the Struct Members + +Create a mental (or written) map: + +``` ++-----------------------------------------------------------------+ +| Struct Member Mapping | +| | +| Assembly Value -> Struct Member -> Physical LED | +| ------------------------------------------------------------- | +| 0x10 (16) -> led1_pin -> Red LED | +| 0x11 (17) -> led2_pin -> Green LED | +| 0x12 (18) -> led3_pin -> Yellow LED | +| | +| NEC Code -> State Member -> Action | +| ------------------------------------------------------------- | +| 0x0C -> led1_state=true -> Red LED ON | +| 0x18 -> led2_state=true -> Green LED ON | +| 0x5E -> led3_state=true -> Yellow LED ON | +| | ++-----------------------------------------------------------------+ +``` + +--- + +## Part 14: Hacking Structures + +### Step 31: Patching Instructions + +To modify assembly instructions in Ghidra, you can use either the direct **Bytes Window** workflow or the GUI **Patch Instruction** dialog. Direct byte editing via the Bytes Window is the standard, bulletproof workflow across all embedded reverse engineering tasks because it avoids assembler context conflicts. + +### Step 32: Swap LED Pin Assignments + +We'll swap the red and green LED pins to reverse their behavior! Because the compiler fully flattened the struct, modifying the `gpio_init` pins won't actually change the main loop's behavior (since all three pins are initialized anyway). We must patch the hardcoded pins inside the **main loop** itself! + +**Method A: Bytes Window Workflow (Recommended)** +1. Ensure the Bytes window is open (**Window** -> **Bytes: 0x0023_structures.bin**). +2. Click the **pencil icon** (**Toggle Edit Mode**) in the Bytes window toolbar. +3. In the **Listing** window, navigate to `10000296` where the red LED pin is loaded (`movs r2,#0x10`) and press **`C`** (**Clear Code Bytes**). +4. In the **Bytes** window at offset `10000296`, change byte `10` to **`11`** (swap red to green's pin). +5. In the **Listing** window, click back on `10000296` and press **`D`** (**Disassemble**). +6. In the **Listing** window, navigate to `1000029c` where the green LED pin is loaded (`movs r2,#0x11`) and press **`C`** (**Clear Code Bytes**). +7. In the **Bytes** window at offset `1000029c`, change byte `11` to **`10`** (swap green to red's pin). +8. In the **Listing** window, click back on `1000029c` and press **`D`** (**Disassemble**). + +**Method B: Patch Instruction** +1. Navigate to `10000296`: right-click `movs r2,#0x10` -> **Patch Instruction** (or press `Ctrl+Shift+G`), change `#0x10` to `#0x11`, and press **Enter**. +2. Navigate to `1000029c`: right-click `movs r2,#0x11` -> **Patch Instruction**, change `#0x11` to `#0x10`, and press **Enter**. + +**Before:** +``` +LED 1 (0x0C) -> GPIO 16 -> Red LED +LED 2 (0x18) -> GPIO 17 -> Green LED +``` + +**After:** +``` +LED 1 (0x0C) -> GPIO 17 -> Green LED (SWAPPED!) +LED 2 (0x18) -> GPIO 16 -> Red LED (SWAPPED!) +``` + +### Step 33: Export and Flash + +1. Click **File** -> **Export Program** +2. Set **Format** to **Raw Bytes** +3. Name: `0x0023_structures-h.bin` +4. Click **OK** + +Convert and flash: + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0023_structures +python ..\uf2conv.py build\0x0023_structures-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 34: Verify the Hack + +**Open PuTTY and test:** + +- Press "1" on remote -> **GREEN** LED lights (was red!) +- Terminal still shows `NEC command: 0x0C` +- Press "2" on remote -> **RED** LED lights (was green!) +- Terminal still shows `NEC command: 0x18` + +**The log says one thing, but the hardware does another!** + +--- + +## Part 15: Security Implications - Log Desynchronization + +### The Danger of Mismatched Logs + +``` ++-----------------------------------------------------------------+ +| Log vs Reality Desynchronization | +| | +| +-----------------+ +-----------------+ | +| | Terminal Log | | Physical LEDs | | +| +-----------------+ +-----------------+ | +| | NEC: 0x0C | +------- | GREEN LED on | <-- Mismatch! | +| | (expects RED) | | (not red!) | | +| +-----------------+ +-----------------+ | +| | NEC: 0x18 | +------- | RED LED on | <-- Mismatch! | +| | (expects GREEN) | | (not green!) | | +| +-----------------+ +-----------------+ | +| | +| The OPERATOR sees correct logs but WRONG physical behavior! | +| | ++-----------------------------------------------------------------+ +``` + +### Real-World Example: Stuxnet + +**Stuxnet** was a cyberweapon that: + +- Attacked Iranian nuclear centrifuges +- Made centrifuges spin at dangerous speeds +- Fed FALSE "everything normal" data to operators +- Operators saw stable readings while equipment was destroyed + +Our LED example demonstrates the same principle: + +- Logs show expected behavior +- Hardware performs different actions +- Attackers can hide malicious activity + +--- + +## Part 16: Functions Project - Advanced Code + +### Step 35: Review the Functions Code + +**File: `0x0026_functions.c`** (key functions shown) + +```c +// Map IR command to LED number +int ir_to_led_number(int ir_command) { + if (ir_command == 0x0C) return 1; + if (ir_command == 0x18) return 2; + if (ir_command == 0x5E) return 3; + return 0; +} + +// Get GPIO pin for LED number +uint8_t get_led_pin(simple_led_ctrl_t *leds, int led_num) { + if (led_num == 1) return leds->led1_pin; + if (led_num == 2) return leds->led2_pin; + if (led_num == 3) return leds->led3_pin; + return 0; +} + +// Turn off all LEDs +void leds_all_off(simple_led_ctrl_t *leds) { + gpio_put(leds->led1_pin, false); + gpio_put(leds->led2_pin, false); + gpio_put(leds->led3_pin, false); +} + +// Blink an LED +void blink_led(uint8_t pin, uint8_t count, uint32_t delay_ms) { + for (uint8_t i = 0; i < count; i++) { + gpio_put(pin, true); + sleep_ms(delay_ms); + gpio_put(pin, false); + sleep_ms(delay_ms); + } +} + +// Main command processor +int process_ir_led_command(int ir_command, simple_led_ctrl_t *leds, uint8_t blink_count) { + if (!leds || ir_command < 0) return -1; + + leds_all_off(leds); + int led_num = ir_to_led_number(ir_command); + if (led_num == 0) return 0; + + uint8_t pin = get_led_pin(leds, led_num); + blink_led(pin, blink_count, 50); + gpio_put(pin, true); + + return led_num; +} +``` + +### Step 36: Understand the Function Call Chain + +``` ++-----------------------------------------------------------------+ +| Function Call Chain | +| | +| main() | +| | | +| +--> process_ir_led_command(key, &leds, 3) | +| | | +| +--> leds_all_off(&leds) | +| | +--> gpio_put() * 3 | +| | | +| +--> ir_to_led_number(ir_command) | +| | +--> returns 1, 2, or 3 | +| | | +| +--> get_led_pin(&leds, led_num) | +| | +--> returns GPIO pin number | +| | | +| +--> blink_led(pin, 3, 50) | +| | +--> gpio_put() + sleep_ms() in loop | +| | | +| +--> gpio_put(pin, true) | +| | ++-----------------------------------------------------------------+ +``` + +### Step 37: Flash and Test + +1. Flash `0x0026_functions.uf2` to your Pico 2 +2. Open PuTTY +3. Press remote buttons: + - "1" -> Red LED blinks 3 times, then stays on + - "2" -> Green LED blinks 3 times, then stays on + - "3" -> Yellow LED blinks 3 times, then stays on + +--- + +## Part 17: Debugging with GDB (Functions) + +### Step 38: Start OpenOCD (Terminal 1) + +Open a terminal and start OpenOCD: + +```powershell +openocd -s "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev\scripts" -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed 5000" +``` + +You should see output indicating OpenOCD connected successfully to your Pico 2 via the Debug Probe. + +### Step 39: Start GDB (Terminal 2) + +Open a **new terminal** and launch GDB with the binary: + +```cmd +arm-none-eabi-gdb build\0x0026_functions.elf +``` + +### Step 40: Connect to the Remote Target + +In GDB, connect to OpenOCD: + +```gdb +target extended-remote :3333 +``` + +### Step 41: Halt the Running Binary + +Stop the processor: + +```gdb +monitor halt +``` + +### Step 42: Examine the Function Layout + +Disassemble to see the multiple functions: + +```gdb +disassemble 0x10000234,+300 +``` + +You'll see multiple function prologues (push) and epilogues (pop) for the helper functions. + +### Step 43: Discover the Missing Functions + +The C code relies heavily on helper functions (`process_ir_led_command`, `leds_all_off`, `ir_to_led_number`, `blink_led`). But if you scroll through the disassembly, you'll notice a distinct lack of function prologues, epilogues, or `bl` calls to anything other than `sleep_ms` or `printf`! + +The compiler has aggressively **inlined** every single helper function into the main loop. + +Let's trace exactly how the compiler flattened this logic. First, set a breakpoint right when a key press is detected: + +```gdb +break *0x10000284 +continue +``` + +*(Press a button on your remote to trigger the breakpoint!)* + +### Step 44: Examine leds_all_off (Inlined) + +In the C code, `process_ir_led_command` starts by calling `leds_all_off(&leds)`. + +Let's look at the next few instructions starting from our breakpoint: +```gdb +x/8i $pc +``` + +You'll see: +```assembly +0x10000284 : mov r1, r4 +0x10000286 : ldr r0, [pc, #156] +0x10000288 : bl 0x10003554 <__wrap_printf> +0x1000028c : movs r5, #16 +0x1000028e : mcrr 0, 4, r5, r6, cr0 +0x10000292 : movs r3, #17 +0x10000294 : mcrr 0, 4, r3, r6, cr0 +0x10000298 : movs r2, #18 +``` +Because `r6` was set to `0` earlier, the compiler is just directly writing `0` to pins 16, 17, and 18 using `mcrr`. It bypassed the function call entirely! + +### Step 45: Examine ir_to_led_number (Inlined) + +Next, the C code calls `ir_to_led_number` and `get_led_pin`. Let's see how the compiler handled that by inspecting further down: + +```gdb +x/4i 0x1000029e +``` + +```assembly +0x1000029e : cmp r4, #12 +0x100002a0 : beq.n 0x100002c6 +0x100002a2 : cmp r4, #24 +0x100002a4 : beq.n 0x1000030a +``` +Instead of a separate function, it simply compares the button code in `r4` (`12`, `24`, `94`) and branches straight to the correct blinking logic! + +### Step 46: Watch the blink_led Loop + +Let's set a breakpoint where the blinking loop begins for Button 1 (which handles the Red LED on pin 16). + +```gdb +break *0x100002c6 +continue +``` + +Once halted, inspect the setup: +```gdb +x/6i $pc +``` + +```assembly +0x100002c6 : mov.w r8, #1 @ led_num = 1 +0x100002ca : movs r4, #3 @ blink_count = 3 +0x100002cc : mcrr 0, 4, r5, r7, cr0 @ Turn LED ON (r7=1) +0x100002d0 : movs r0, #50 @ Delay 50ms +0x100002d2 : bl 0x10001008 +0x100002d6 : mcrr 0, 4, r5, r6, cr0 @ Turn LED OFF (r6=0) +``` +The compiler placed the blink count in `r4` and handles the toggling with `mcrr` instructions surrounding `sleep_ms`. + +### Step 47: The Struct Pointer is a Lie + +If you were trying to find the `leds` struct pointer to examine the pins using `x/6xb`, you'd be looking forever. Because the compiler realized the struct is never passed to any external non-inlined functions, it **never bothered creating it in memory**. It simply kept track of the pin numbers (16, 17, 18) directly in registers during compilation! + +### Step 48: Observe the Loop Condition + +Continue execution until you hit the end of the blink loop: + +```gdb +break *0x100002e0 +continue +``` + +At this point, GDB is halted **right before** it performs the subtraction. If you check `r3` now, it will contain random leftover garbage (like `0x400b0000`) because the instruction hasn't run yet! Check `r4` (the current blink count): + +```gdb +info registers r4 +``` + +Now, step forward two instructions to let it actually do the math: + +```gdb +stepi 2 +info registers r3 r4 +``` + +```assembly +0x100002e0 : subs r3, r4, #1 +0x100002e2 : ands.w r4, r3, #255 +0x100002e6 : bne.n 0x100002cc +``` +You will now see `r3` become `2`, and `r4` become `2`! It successfully subtracted 1 from the blink count and stored it back. Since it hasn't hit 0 yet, the `bne.n` instruction will branch back to the start of the blink (`0x100002cc`) to flash the LED again! + +### Step 49: Exit GDB + +When done exploring: + +```gdb +quit +``` + +--- + +## Part 18: Analyzing .ELF Files in Ghidra + +### Step 50: Create New Ghidra Project + +1. Create project: `0x0026_functions` +2. Import the `.elf` file (NOT the .bin this time!) + +### Why Use .ELF Instead of .BIN? + +| Feature | .BIN File | .ELF File | +| -------------- | -------------------- | --------------------------- | +| **Symbols** | None | Function/variable names | +| **Sections** | Raw bytes only | .text, .data, .rodata, etc. | +| **Debug info** | None | May include debug symbols | +| **Size** | Smaller | Larger | +| **Use case** | Flashing to hardware | Analysis and debugging | + +### Step 51: Import and Analyze the .ELF + +1. Drag and drop the `.elf` file into Ghidra +2. Ghidra automatically detects ARM format! +3. Click **Yes** to analyze +4. Wait for analysis to complete + +### Step 52: Explore the Symbol Tree + +With .ELF files, you get more information: + +1. Look at the **Symbol Tree** panel +2. Expand **Functions** - you may see named functions! +3. Expand **Labels** - data labels may appear + +--- + +## Part 19: Hacking the Functions Project + +### Step 53: Find LED Pin Values + +Look for the struct initialization pattern: + +```assembly +movs r0, #0x10 ; led1_pin = 16 +movs r0, #0x11 ; led2_pin = 17 +movs r0, #0x12 ; led3_pin = 18 +``` + +### Step 54: Swap LED 1 and LED 3 + +We'll swap the red (GPIO 16) and yellow (GPIO 18) LEDs: + +**Find and patch in the .bin file:** + +Using the Bytes window in Ghidra (enable the pencil icon, press **`C`** in the Listing, change the byte in the Bytes window, and press **`D`** in the Listing) or a hex editor: +1. Change `0x10` (16) to `0x12` (18) +2. Change `0x12` (18) to `0x10` (16) + +**Before:** +``` +Button 1 -> LED 1 -> GPIO 16 -> Red +Button 3 -> LED 3 -> GPIO 18 -> Yellow +``` + +**After:** +``` +Button 1 -> LED 1 -> GPIO 18 -> Yellow (SWAPPED!) +Button 3 -> LED 3 -> GPIO 16 -> Red (SWAPPED!) +``` + +### Step 55: Export the Patched .BIN + +**Important:** Even though we analyzed the .elf, we patch the .bin! + +1. Open the original `.bin` file in Ghidra (or a hex editor) +2. Apply the patches using the Bytes window workflow +3. Export as `0x0026_functions-h.bin` + +### Step 56: Convert and Flash + +```cmd +cd C:\Users\flare-vm\Desktop\Embedded-Hacking-main\0x0026_functions +python ..\uf2conv.py build\0x0026_functions-h.bin --base 0x10000000 --family 0xe48bff59 --output build\hacked.uf2 +``` + +### Step 57: Verify the Hack + +**Open PuTTY and test:** + +- Press "1" -> **YELLOW** LED blinks (was red!) +- Terminal shows: `LED 1 activated on GPIO 16` (WRONG - it's actually GPIO 18!) +- Press "3" -> **RED** LED blinks (was yellow!) +- Terminal shows: `LED 3 activated on GPIO 18` (WRONG - it's actually GPIO 16!) + +**Again, logs don't match reality!** + +--- + +## Part 20: Summary and Review + +### What We Accomplished + +1. **Learned C structures** - Grouping related data together +2. **Understood struct memory layout** - How members are stored consecutively +3. **Mastered dot and arrow operators** - Accessing struct members +4. **Learned the NEC IR protocol** - How remotes communicate +5. **Understood functions with parameters** - Passing data in and out +6. **Saw struct flattening in assembly** - How compilers transform structs +7. **Analyzed .ELF files** - Getting more symbol information +8. **Hacked GPIO assignments** - Swapping LED behavior +9. **Discovered log desynchronization** - Security implications + +### Struct Operations Summary + +``` ++-----------------------------------------------------------------+ +| Struct Operations | +| | +| Definition: | +| typedef struct { | +| uint8_t pin; | +| bool state; | +| } led_t; | +| | +| Creation: | +| led_t led = { .pin = 16, .state = false }; | +| | +| Access (variable): led.pin | +| Access (pointer): ptr->pin or (*ptr).pin | +| | +| Passing to function: void func(led_t *led) | +| Calling: func(&led) | +| | ++-----------------------------------------------------------------+ +``` + +### Function Types Summary + +``` ++-----------------------------------------------------------------+ +| Function Patterns | +| | +| No params, no return: | +| void leds_all_off(void) | +| | +| With params, no return: | +| void blink_led(uint8_t pin, uint8_t count, uint32_t delay) | +| | +| No params, with return: | +| int ir_getkey(void) | +| | +| With params, with return: | +| int ir_to_led_number(int ir_command) | +| | +| With struct pointer: | +| uint8_t get_led_pin(simple_led_ctrl_t *leds, int led_num) | +| | ++-----------------------------------------------------------------+ +``` + +### Key Memory Addresses + +| Memory Address | Description | +| -------------- | ------------------------------- | +| `0x10000234` | main() function | +| `0x10` (16) | GPIO 16 - Red LED (led1_pin) | +| `0x11` (17) | GPIO 17 - Green LED (led2_pin) | +| `0x12` (18) | GPIO 18 - Yellow LED (led3_pin) | +| `0x05` | GPIO 5 - IR receiver | +| `0x0C` | NEC code for button 1 | +| `0x18` | NEC code for button 2 | +| `0x5E` | NEC code for button 3 | + +--- + +--- + +## Key Takeaways + +1. **Structs group related data** - Better organization than separate variables + +2. **Dot operator for variables, arrow for pointers** - `.` vs `->` + +3. **Designated initializers are cleaner** - `.member = value` syntax + +4. **Compilers flatten structs** - You see values, not struct names, in assembly + +5. **NEC protocol uses 8-bit commands** - 0x0C, 0x18, 0x5E for our buttons + +6. **Functions separate concerns** - Each function does one job + +7. **.ELF files contain more info than .BIN** - Symbols, sections, debug data + +8. **Log desynchronization is dangerous** - Logs can lie about real behavior + +9. **Pattern recognition is key** - Consecutive values like 16, 17, 18 reveal structs + +10. **Always patch the .bin for flashing** - .elf is for analysis only + +--- + +## Glossary + +| Term | Definition | +| -------------------------- | -------------------------------------------------- | +| **Arrow Operator (->)** | Accesses struct member through a pointer | +| **Designated Initializer** | Syntax `.member = value` for struct initialization | +| **Dot Operator (.)** | Accesses struct member from a struct variable | +| **.ELF File** | Executable and Linkable Format - contains symbols | +| **Flattening** | Compiler converting structs to individual values | +| **IR (Infrared)** | Invisible light used for remote control | +| **Log Desynchronization** | When logs don't match actual system behavior | +| **Member** | A variable inside a struct | +| **NEC Protocol** | Common IR communication standard | +| **Struct** | User-defined type grouping related variables | +| **typedef** | Creates an alias for a type | + +--- + +## Additional Resources + +### NEC IR Command Reference + +| Button | Command | Binary | +| ------ | ------- | --------- | +| 1 | 0x0C | 0000 1100 | +| 2 | 0x18 | 0001 1000 | +| 3 | 0x5E | 0101 1110 | + +### GPIO Pin Quick Reference + +| GPIO | Default Function | Our Usage | +| ---- | ---------------- | ----------- | +| 5 | General I/O | IR Receiver | +| 16 | General I/O | Red LED | +| 17 | General I/O | Green LED | +| 18 | General I/O | Yellow LED | + +### Struct Size Calculation + +| Type | Size (bytes) | +| ---------- | ------------ | +| `uint8_t` | 1 | +| `bool` | 1 | +| `uint16_t` | 2 | +| `uint32_t` | 4 | +| `int` | 4 | +| `float` | 4 | +| `pointer` | 4 (on ARM32) | + +--- + +## Real-World Implications + +### What You've Learned in This Course + +Over these weeks, you've built skills that few people possess: + +1. **Hardware fundamentals** - GPIO, I2C, PWM, IR protocols +2. **Reverse engineering** - Ghidra, disassembly, function identification +3. **Binary patching** - Modifying compiled code +4. **Security awareness** - Understanding vulnerabilities + +### The Power and Responsibility + +The techniques you've learned can be used for: + +**Good:** + +- Security research +- Debugging proprietary systems +- Understanding how things work +- Career in cybersecurity + +**Danger:** + +- Unauthorized system access +- Sabotage of critical infrastructure +- Fraud and deception + +**Always use your skills ethically and legally!** + +### Keep Learning + +This is just the beginning: + +- Explore more complex protocols (SPI, CAN bus) +- Learn dynamic analysis with debuggers +- Study cryptographic implementations +- Practice on CTF challenges + +--- + +**Congratulations on completing this course! You now have the curiosity, persistence, and skills that embedded systems engineers and security researchers thrive on. Keep experimenting, documenting, and sharing your work. The world needs more builders and defenders like you!** + +Happy hacking! :) diff --git a/WEEK11/WEEK11.pdf b/WEEK11/WEEK11.pdf new file mode 100644 index 0000000..cb82ce5 Binary files /dev/null and b/WEEK11/WEEK11.pdf differ diff --git a/WEEK11/WEEK11a.md b/WEEK11/WEEK11a.md new file mode 100644 index 0000000..0653dfc --- /dev/null +++ b/WEEK11/WEEK11a.md @@ -0,0 +1,2237 @@ +# Week 11a: Custom Secure Boot + AES in Firmware: Building a CAC-Signed Bootloader and Reverse Engineering It + +*** + +**LEGAL DISCLAIMER:** +The information, tools, and code provided in this repository and course are strictly for educational, research, and defensive purposes only. + +You are explicitly prohibited from using any materials contained herein to access, test, modify, or exploit any device, network, or system that you do not own 100% or for which you do not have explicit, documented, and legally binding authorization to interact with. + +By using this repository and course, you acknowledge and agree that: + +1. Any illegal, unauthorized, or malicious use of this information is solely your responsibility. +2. The author(s) and contributor(s) of this repository and course shall not be held liable for any damages, legal repercussions, criminal charges, or unauthorized actions resulting from the use, misuse, or abuse of the contents herein. +3. You will comply with all applicable local, state, national, and international laws regarding cybersecurity and computer fraud. + +**IF YOU DO NOT AGREE WITH THESE TERMS, DO NOT USE THIS REPOSITORY AND COURSE.** + +*** + +## What You'll Learn This Week + +By the end of this tutorial, you will be able to: + +- Understand why consumer and industrial devices use a secure (authenticated) boot chain +- Explain, with a diagram, how AES-128-CMAC (RFC 4493) authenticates a firmware image +- Read a custom linker script, modify the MEMORY block, and relocate a program to a higher flash address +- Inspect a relocated ELF with `readelf`, `nm`, and `objdump` to confirm where every section and symbol lives +- Use Mbed TLS (already shipped inside the Pico SDK) in your own C code to decrypt data at runtime +- Flash a raw `.bin`, a manifest, and an application to three different flash addresses with OpenOCD +- Tamper with a single byte of firmware and watch the bootloader reject it at boot +- Reverse engineer the bootloader with GDB live on the Pico 2 (breakpoints, memory dumps, single-stepping the jump) +- Reverse engineer both firmware images in Ghidra, including recovering an AES key, IV, and ciphertext from flash +- Explain why a static key is not a real secret, and how real products solve secure boot (OTP keys, ROM verification, ECDSA) + +--- + +## Part 1: Why Secure Boot? (The Threat Model) + +### Firmware is a Product, and Products Get Modified + +Everything you have flashed onto your Pico 2 so far in this course has been a **single standalone image**. The RP2350 boot ROM reads the image at `0x10000000`, your program runs, done. That is exactly how millions of cheap embedded products work, and it has a serious weakness: + +**Anybody with a $5 probe can replace the flash contents.** + +OpenOCD, a 5-pin SWD connection, and a serial terminal are all an attacker needs to: + +1. Dump your firmware (read flash) +2. Modify a byte (change a password, unlock a feature, bypass a license) +3. Flash their own image (rootkit the device) + +Now tighten the screw. Imagine your product is: + +- A smart lock that talks to the network +- A security camera that signs video +- A commercial battery charger that detects counterfeit batteries +- An update server that pushes "fixes" to thousands of deployed devices + +In those products, **running modified or unauthorized firmware is a real-world safety and business problem**. If a device can be made to run code it did not originate, that device cannot be trusted, and neither can the data it produces. + +### The Defense: A Verified Boot Chain + +The modern defense is a **boot chain**. Each stage of the chain refuses to start the next stage until it has proven (cryptographically) that the next stage is authentic: + +``` ++========================================================================+ +| BOOT CHAIN (each stage authenticates the next) | +| | +| +-----------------------------------------------------------------+ | +| | STAGE 0: ROM in the chip (frozen in silicon, cannot be changed) | | +| | verifies ... | | +| +-----------------------------------------------------------------+ | +| | trusts | +| v | +| +-----------------------------------------------------------------+ | +| | STAGE 1: bootloader in flash (this lab) | | +| | verifies the app with an AES-128-CMAC tag | | +| +-----------------------------------------------------------------+ | +| | trusts (only if the tag matches) | +| v | +| +-----------------------------------------------------------------+ | +| | STAGE 2: application firmware (the IR remote control app) | | +| +-----------------------------------------------------------------+ | +| | +| An attacker's modified app is REJECTED at stage 1 and never runs. | +| The device is very hard to brick with bad firmware, and cheap | +| modification attacks fail. | ++========================================================================+ +``` + +> **What this lab does, and what it does not.** +> +> The 0x0026a bootloader authenticates the application using a key that is +> **embedded in the bootloader itself**. That stops a casual attacker who uses +> OpenOCD to patch a byte or two. A serious attacker who dumps the flash can +> read the key and re-sign their own image. Real products push Stage 0 into +> the ROM and store the key in **OTP (one-time programmable) memory** that +> flash reads cannot access. Part 19 shows how to think about that gap. + +--- + +## Part 2: Choosing the Authentication Primitive + +The bootloader must answer one question about the application image: +"Did this byte-for-byte image come from the person who holds the key?" + +### The Candidate Tools + +| Tool | What it computes | Can an attacker forge it? | +| ------------- | ---------------------------------------- | ----------------------------------------------------------- | +| CRC-32 | A simple checksum | YES, trivially. CRC is designed to catch noise, not attackers. | +| SHA-256 hash | A one-way digest of the image | YES, if there is no secret. Anyone can compute the hash after editing. | +| HMAC-SHA256 | A keyed digest | NO (without the key). Strong, but needs a keyed hash implementation. | +| AES-CMAC | A keyed MAC built from a block cipher | NO (without the key). Uses the AES primitive you already have. | +| ECDSA signature | An asymmetric signature | NO. The verifier holds only a public key, so even a full flash dump cannot forge. | + +### Why AES-CMAC for This Lab + +Two practical reasons: + +1. **The Pico SDK already ships a fast, well-tested AES.** CMAC is built on AES + (it is a CBC-MAC variant), so we do not add SHA code or HMAC glue; we reuse + the `mbedtls` library that ships inside the SDK (`pico_mbedtls`). +2. **One primitive, two lessons.** The same AES engine that authenticates the + image in the bootloader is also used inside the application to decrypt a + secret banner (Part 9). You see one cipher doing two classic jobs. + +ECDSA would be stronger (asymmetric, so the flash dump does not reveal the +signing key), and the RP2350 ROM ships a `secp256k1` verifier. The gap between +where this lab leaves off and where the ROM verifier lies is an important +"real product" paragraph in Part 19. + +--- + +## Part 3: AES-128-CMAC in Depth (RFC 4493) + +### A MAC Is a Keyed Checksum + +A **Message Authentication Code (MAC)** takes three inputs: + +- a secret key `K` +- a message `M` +- (optionally) a length `Tlen` + +and produces a short, fixed-size **tag** `T`. Security property: without `K`, +an attacker cannot construct `(M, T)` that verifies, even if they are allowed +to see thousands of valid `(M, T)` pairs. + +### Outline of CMAC + +CMAC is a keyed block-cipher MAC standardised in **NIST SP 800-38B** and +implemented in **RFC 4493** for AES-128. It is a **CBC-MAC with a twist**: the +final block is XORed with one of two derived subkeys before the last AES +encryption, which removes the classical CBC-MAC extension attack. + +``` ++---------------------------------------------------------------+ +| Subkey derivation (once, at key setup) | +| | +| L = AES_K(0^128) AES-encrypt a zero block | +| if MSB(L) == 0: K1 = L << 1 | +| else: K1 = (L << 1) XOR 0x87 (0x87 = Rb for AES) | +| same step on K1 yields K2 | +| | +| Tagging (per message M, split into 128-bit blocks M1..Mn) | +| | +| M0 = 0^128 | +| if M is an exact multiple of 128 bits: | +| Mn' = Mn XOR K1 | +| else: (pad M with 10...0 to a full block) | +| Mn' = padded(Mn) XOR K2 | +| | +| for each block: C[i] = AES_K( C[i-1] XOR M[i] ) | +| Tag = C[n] (first Tlen bits) | ++---------------------------------------------------------------+ +``` + +The two subkeys exist precisely to encode "full last block" vs "short last +block" into the tag. If we reused plain CBC-MAC, an attacker could cut the +message after a block boundary and still produce a valid tag. + +### Where Is AES-128-CMAC Not Really "Analysis" But Simple Math? + +Study the equation for a single message block: + +``` +C[1] = AES_K( 0^128 XOR M1 ) +``` + +Because this is a block cipher, a 1-bit change anywhere in `M1` results in a +completely unrelated tag. And without `K`, you cannot compute +`AES_K(...)` at all. Both facts are what make the tag unforgeable in practice. + +### The RFC 4493 Test Vectors (how the tool proves itself) + +The host signer `tools/sign_firmware.py` implements AES and CMAC from scratch +in pure Python, so the build toolchain has zero extra dependency on the +development machine. It is validated against the four official test vectors +from RFC 4493 using the well-known test key: + +``` +Key = 2b7e151628aed2a6abf7158809cf4f3c + +Message = (empty) +Tag = bb1d6929e95937287fa37d129b756746 + +Message = 6bc1bee22e409f96e93d7e117393172a +Tag = 070a16b46b4d4144f79bdd9dd04a287c + +Message = 40-byte repeating sample +Tag = dfa66747de9ae63030ca32611497c827 + +Message = 64-byte repeating sample +Tag = 51f0bebf7e3b9d92fc49741779363cfe +``` + +Read the tool's top-of-file comment; the four vectors are exercised against the +signer's internal CMAC routine before any real image is signed. + +--- + +## Part 4: The Hardware and the Flash Map + +### The Pieces + +| Component | Role in this lab | +| ---------------- | ------------------------------------------------------------------- | +| Pico 2 (RP2350) | The target. Two Cortex-M33 cores, 512 KB SRAM, executes code in place from XIP flash. | +| Debug Probe | CMSIS-DAP SWD adapter for flashing, debugging, and UART serial. It owns the SWD port and usually also gives a UART console channel. | +| IR receiver | GPIO5 input; decodes NEC remote commands in the application. | +| 3 LEDs | GPIO16, GPIO17, GPIO18; driven by decoded commands. | +| USB-UART/cable | If the Debug Probe's UART is wired to the Pico's UART0, the bootloader and app log to it. | + +### Why 0x10000000? + +On the RP2350 the first 4 MiB of the address map (from `0x10000000`) is a +**memory-mapped view of external XIP flash** (eXecute In Place). The CPU +fetches instructions straight from that window; the flash controller reads the +bytes transparently through the XIP cache. The boot ROM boots from this flash +window because it is simply memory. + +So "flashing at `0x10000000`" means "making the contents of physical flash +visible at the addresses your program expects." A raw `.bin` carries no address +information; you must always supply the load address out of band (Part 12). + +### The 0x0026a Flash Layout + +``` ++-------------------------------------------------+-------------+ +| BOOTLOADER image (0x0026a_bootloader.bin) | 0x10000000 | +| boot.c verify.c manifest.c aes_cmac.c | | +| image.c main.c (~28 KB total) | ~0x10006D00 | ++-------------------------------------------------+-------------+ +| (free padding) | | ++-------------------------------------------------+-------------+ +| MANIFEST sector (4 KB, one flash sector) | 0x1001F000 | +| magic, version, app base address, app size, | | +| and a 16-byte AES-128-CMAC tag | | ++-------------------------------------------------+-------------+ +| APPLICATION image (0x0026a_app.bin) | 0x10020000 | +| the Week 11 IR remote app plus an AES-128-CBC | | +| secret banner, linked to run from here | size 0x5498 | ++-------------------------------------------------+-------------+ +| (free padding) | | ++-------------------------------------------------+-------------+ +| End of usable flash (2 MiB region) | 0x10200000 | ++-------------------------------------------------+-------------+ +``` + +Three things to notice: + +1. The manifest sits in its **own flash sector** (`0x1001F000`), so updating + it never touches the bootloader or the application. +2. The application is **relocated** above both, starting at `0x10020000`. It is + not written at `0x10000000`. +3. The bootloader jump at the end of Part 8 hands control to the app's reset + vector, which lives at `0x1002015C`. + +--- + +## Part 5: The Manifest Format + +Before code runs, the bootloader reads a 4 KB record from flash. The first 28 +bytes matter; the rest is `0xFF` padding (erased flash). + +``` +Declared in bootloader/include/manifest.h +#pragma pack(push, 1) +typedef struct { + uint32_t magic; // 0x424C4657 ("WFLB") + uint32_t version; // 1 + uint32_t app_base; // 0x10020000 + uint32_t app_size; // 0x5498 (21656 bytes) + uint8_t tag[16]; // AES-128-CMAC of the app image +} fw_manifest_t; +#pragma pack(pop) +``` + +Annotated hex dump of the real `manifest.bin` produced in Part 11: + +``` +00000000: 57 46 4c 42 01 00 00 00 00 00 02 10 98 54 00 00 WFLB........T.. + ^^^^^^^^^^^ ^^^^^^^^^^^ ^^^^^^^^^^^ ^^^^^^^^^^^ + magic version app_base app_size + 0x10020000 0x5498 + +00000010: ef 04 1e c5 92 f0 c5 67 27 da 26 51 d3 73 94 7b .......g'.&Q.s.{ + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + tag (16 bytes): AES-128-CMAC over the application +00000020: ff ff ff ff ... (0xFF padding to 0x1000) +``` + +Note the little-endian layout. `00 00 02 10` reads as `0x10020000`, and +`98 54 00 00` reads as `0x5498`. The tag is the raw 16-byte CMAC output, not a +text string. + +--- + +## Part 6: The Custom Linker Script (Where Your Program Really Lives) + +This is the part that answers a question students ask constantly: *"If I want +to put a second program above the first one, how does the compiler know where +it belongs?"* Answer: **the linker script says so.** Understand this file and +you control a device's entire memory layout; ignore it and relocated firmware +silently corrupts itself. + +### 6.1 What a Linker Script Is + +Compilation produces **object files** with named sections: `.text` (code), +`.rodata` (constants), `.data` (initialized globals), `.bss` (zeroed globals), +and so on. The linker (here, the GNU `arm-none-eabi-ld`) merges those sections +into a single ELF and decides **which virtual addresses each section gets**. +That decision comes from a script, normally `/path/to/lds` or, for the Pico +SDK, a script your CMake passes in. + +A copy of the RP2350 script lives here: + +``` +app/memmap_app.ld <- our modified version, used for the app only +``` + +The SDK's original (do not edit) is inside the Pico SDK: + +``` +~/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_crt0/rp2350/memmap_default.ld +``` + +### 6.2 The MEMORY Command: ORIGIN and LENGTH + +The heart of the script is the `MEMORY` block. It tells the linker which +address ranges are real and how big they are. The SDK's default is: + +``` +/* from memmap_default.ld */ +MEMORY +{ + INCLUDE "pico_flash_region.ld" + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} +``` + +What each line says: + +| Region | ORIGIN | LENGTH | What lives there | +| ------------ | ----------- | ------ | --------------------------------------------------- | +| FLASH | 0x10000000 | board flash size | `.text`, `.rodata`, and initial values for `.data` (XIP). | +| RAM | 0x20000000 | 512k | `.data`, `.bss`, heap | +| SCRATCH_X | 0x20080000 | 4k | Core 1 stack / time-critical scratch | +| SCRATCH_Y | 0x20081000 | 4k | Core 0 stack (ends at `0x20082000`) | + +`ORIGIN` is the first byte of the region; `LENGTH` is how many bytes it spans. +Anything placed in `FLASH` runs directly from the XIP window; anything placed +in a RAM region is copied there at boot by the `_reset_handler`. + +### 6.3 Where FLASH Actually Comes From: `pico_flash_region.ld` + +Notice that `FLASH` is not declared inline; it is **included**: + +``` +INCLUDE "pico_flash_region.ld" +``` + +The SDK's CMake generates this tiny file for you based on the board's flash +size. Ours (from the build directory) is: + +``` +/* build/pico_flash_region.ld */ +FLASH(rx) : ORIGIN = 0x10000000, LENGTH = (4 * 1024 * 1024) +``` + +So for the default Pico 2 the whole 4 MiB of flash is one region called +`FLASH`, read-only + execute, starting at `0x10000000`. If you build a board +with 2 MiB you would see `LENGTH = (2 * 1024 * 1024)`. + +### 6.4 The Modification: Relocating the Application + +The bootloader owns the start of flash, so the app must not begin at +`0x10000000`. We copy the SDK script and change **one thing in MEMORY**: the +FLASH line. In `app/memmap_app.ld`: + +``` +MEMORY +{ + /* Relocated for the custom bootloader: the application is linked to run + from 0x10020000, leaving the first 128k of flash for the bootloader and + its manifest. */ + FLASH(rx) : ORIGIN = 0x10020000, LENGTH = 1920k + RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 512k + SCRATCH_X(rwx) : ORIGIN = 0x20080000, LENGTH = 4k + SCRATCH_Y(rwx) : ORIGIN = 0x20081000, LENGTH = 4k +} +``` + +Arithmetic behind `1920k`: + +``` +default FLASH region: 0x10000000 + 2048 KiB (2 MiB reserved layout) +reserved for boot/manifest: + bootloader image ~28 KiB, manifest at 0x1001F000..0x10020000 + -> reserve the first 128 KiB (0x20000 bytes) +application window: 0x10020000 + 1920 KiB = 0x10200000 end of 2 MiB +1920 KiB = 2048 KiB - 128 KiB +``` + +Every `> FLASH` and `> RAM AT> FLASH` section in the rest of the script now +places itself inside this smaller, relocated window. The `SECTIONS` body is +otherwise identical to the SDK default. + +### 6.5 Wiring the Script Into the Build (CMake) + +The SDK exposes a CMake function that swaps in our script for one target only: + +``` +# CMakeLists.txt +pico_set_linker_script(0x0026a_app + ${CMAKE_CURRENT_LIST_DIR}/app/memmap_app.ld) +``` + +The bootloader target gets no such call, so it uses the SDK default +(`FLASH` at `0x10000000`) exactly as before. + +### 6.6 Symbols the Script Defines + +A linker script does not only place sections; it also **exports symbol values** +that startup code uses. Grep `memmap_app.ld` for these while you read: + +| Symbol | Meaning | Value for the app | +| ---------------------- | -------------------------------------------------------------- | --------------------------- | +| `__flash_binary_start` | First byte of the image in flash | `0x10020000` | +| `__logical_binary_start`| Same as above in this script | `0x10020000` | +| `__etext` | End of code (start of `.data` initial values in flash) | near `0x10026000` | +| `__data_start__` | Loaded `.data` base in RAM | `0x20000000` | +| `__bss_start__`/`__bss_end__` | Zero-initialized globals in RAM | inside `0x20000000` region | +| `__StackLimit` | Heap cap (historically the "stack limit") | `0x20080000` | +| `__StackTop` | Top of core 0 stack (end of SCRATCH_Y) | `0x20082000` | +| `__HeapLimit` | End of RAM = `ORIGIN(RAM) + LENGTH(RAM)` | `0x20080000` | + +The crucial practical consequence: **the first word of the app's vector table +must be `__StackTop` = `0x20082000`.** +Check it: + +``` +$ xxd -l 16 0x0026a_app.bin +00000000: 0020 0820 5d01 0210 1b01 0210 1d01 0210 . . ]........... +``` + +- bytes 0-3 `00 20 08 20` = little-endian `0x20082000` = initial SP +- bytes 4-7 `5d 01 02 10` = little-endian `0x1002015d` = reset vector (the + `_reset_handler` symbol, Thumb-encoded with bit 0 set) + +That `0x1002015d` would be impossible to obtain without the relocated MEMORY +block. This is the tangible proof that the linker script did its job. + +### 6.7 ENTRY(_entry_point) Versus the Reset Vector + +At the top of the script: + +``` +ENTRY(_entry_point) +``` + +This names the ELF entry point used by debuggers. In the SDK, `_entry_point` +is a tiny stub in `crt0.S` that routes a debugger-launched session back +through the boot ROM (so XIP setup happens as on a cold boot). It is +**not** the same as the reset vector in the vector table. + +The bootloader does not use `_entry_point` at all. It jumps straight at the +app's **reset vector** (`vector[1]`), which is `_reset_handler`, the function +that actually initializes `.data`, zeros `.bss`, and calls `main`. Part 8 +shows that branch instruction. This distinction matters when you are poking a +relocated image with a debugger: breaking on `_entry_point` and breaking on +`_reset_handler` are different sessions. + +### 6.8 Inspecting the Result With readelf and nm + +After building (Part 10), look at what the linker produced. The section table: + +``` +$ ~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-readelf -S build/0x0026a_app.elf + [ 0] null + [ 1] .flash_begin PROGBITS 10020000 00001000 000000 00 WA 0 0 1 + [ 2] .text PROGBITS 10020100 00001100 005e34 00 AX 0 0 16 + ... + [ 5] .rodata PROGBITS 10025f40 00006f40 000235 00 A 0 0 8 + ... +``` + +Note that every flash section is stamped `1002xxxx`, never `1000xxxx`. The +program headers (use `readelf -l`) likewise show `LOAD` segments whose vaddr +sits in the `0x10020000` window. `nm` shows symbol addresses: + +``` +$ ~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-nm -n build/0x0026a_app.elf +... +1002015c T _reset_handler +10020234 T main +1002027c T ir_init +... +``` + +### 6.9 One UF2 for the Whole Chain + +No single image is the whole story. The device needs the bootloader at +`0x10000000`, the manifest at `0x1001F000`, and the app at `0x10020000`. A +standalone `0x0026a_app.uf2` would flash only the app region, leaving the other +two to be written separately, so the app is deliberately built with explicit +`.bin`/`.hex`/`.dis`/`.map` outputs instead of its own UF2. + +To bring a bare board up in one move the lab ships a single combined UF2, +`0x0026a_full.uf2`, that carries all three images. It is built by laying the +images out flat - offset 0 mapped to `0x10000000`, the reserved gaps filled +with `0xFF` - and handing the result to picotool as one image: + +``` +$ PICOTOOL=~/.pico-sdk/picotool/2.3.1/picotool/picotool \ + python3 tools/make_full_uf2.py +``` + +picotool numbers the blocks, tags them with the `rp2350-arm-s` family, and +injects the RP2350-E10 "absolute block" (family `0xE48BFF57` at `0x10FFFF00`) +that tells the boot ROM to write every block to its **absolute** address rather +than into a partition. A single BOOTSEL drag then restores the whole chain. +Part 11 uses it. Note the contrast with the naive file layout: a UF2 is not +restricted to `0x10000000`, but a multi-region UF2 is only correct once the +blocks and the E10 absolute block are laid out the way picotool produces them. + +--- + +## Part 7: The Bootloader Source, Module by Module + +The bootloader applies the standard we use for every module in this course: +**`main.c` contains only the sequence; each job has its own `.c` + `.h` pair.** + +``` +bootloader/ + include/ + flash_layout.h addresses of the three flash partitions + manifest.h fw_manifest_t type + read/validate API + boot.h console, halt, launch API + verify.h firmware authenticity check + aes_cmac.h mbedtls front-end + constant-time compare + image.h low-level jump to the app + src/ + main.c ONLY the 5-step boot sequence + boot.c banner console, fatal-haunt loop, handoff + manifest.c flash-read + magic/version validation + verify.c the static key + CMAC recompute + tag compare + aes_cmac.c computes the tag with mbedtls AES-128-CMAC + image.c VTOR/MSP rebase + branch to reset vector +``` + +### 7.1 `main.c`: Only the Sequence + +The whole of `main.c`: + +```c +int main(void) { + fw_manifest_t manifest; + boot_init(); + manifest_read(&manifest); + if (!manifest_is_valid(&manifest)) boot_halt("manifest invalid"); + if (!verify_manifest(&manifest)) boot_halt("firmware signature invalid"); + boot_launch(&manifest); +} +``` + +Read it as a check-list, one step per line: + +1. `boot_init()` - stdio up, 2 s pause, banner print +2. `manifest_read` - copy the 28 useful bytes out of the `0x1001F000` sector +3. `manifest_is_valid` - magic `WFLB` and version == 1? +4. `verify_manifest` - recompute CMAC over the app, compare to stored tag +5. `boot_launch` - print success, jump to the app reset vector + +There is **no** stdio, no key, no crypto in this file. Everything below is a +different module. + +### 7.2 `verify.c`: The Secret and the Verdict + +```c +/** @brief AES-128 key that authenticates the application image. */ +static const uint8_t fw_key[FW_TAG_SIZE] = { + 0x49, 0x72, 0x6F, 0x6E, 0x4E, 0x65, 0x74, 0x42, + 0x6F, 0x6F, 0x74, 0x4B, 0x65, 0x79, 0x21, 0x21 +}; + +bool verify_manifest(const fw_manifest_t *manifest) { + const uint8_t *base = (const uint8_t *)manifest->app_base; + uint8_t computed[FW_TAG_SIZE]; + int rc = aes128_cmac(fw_key, base, manifest->app_size, computed); + if (rc != 0) return false; + return cmac_tags_equal(computed, manifest->tag); +} +``` + +What is important here: + +- The key is 16 bytes `"IronNetBootKey!!"`. It is `static const`, so the + compiler puts it in `.rodata`, right in the binary, at a predictable + address (you will extract it in Ghidra in Part 15). +- The CMAC is computed over **the raw bytes the processor will execute**, + starting at `manifest->app_base` for `app_size` bytes. That is exactly the + `0x0026a_app.bin` content (21656 bytes, `0x5498`). +- The comparison is deliberately a full 16-byte compare with no shortcut, so + the runtime does not leak *which* byte mismatched (timing side-channels). + +### 7.3 `boot.c`: Console and Handoff + +```c +void boot_init(void) { + stdio_init_all(); + sleep_ms(2000); + printf("\n=== 0x0026a secure bootloader ===\n"); +} + +void boot_halt(const char *reason) { + printf("BOOT FAILED: %s\n", reason); + while (true) { + sleep_ms(500); + } +} + +void boot_launch(const fw_manifest_t *manifest) { + printf("signature valid, entering app at 0x%08lx\n", + (unsigned long)manifest->app_base); + image_start(manifest->app_base); +} +``` + +A 2 000 ms delay before the banner gives a human time to open a serial +terminal; the blink of that pause is also a simple "alive" signal. On failure, +`boot_halt` loops forever with a 500 ms heart-beat so you can see the red LED +blinking and the exact reason on the console. + +### 7.4 `image.c`: The Actual Jump + +```c +static void halt_irq_and_rebase(uint32_t base) { + __asm volatile ("cpsid i" ::: "memory"); + *(volatile uint32_t *)0xE000ED08U = base; +} + +void image_start(uint32_t vector_base) { + uint32_t *vectors = (uint32_t *)vector_base; + image_entry_t entry = (image_entry_t)vectors[1]; + halt_irq_and_rebase(vector_base); + __asm volatile ("msr msp, %0" :: "r" (vectors[0]) : "memory"); + __asm volatile ("dsb\n\tisb" ::: "memory"); + entry(); +} +``` + +Step by step: + +1. Read the app's vector table at `vector_base` (`0x10020000`). +2. `entry = vectors[1]` - the reset vector (`0x1002015d`), bit 0 set for + Thumb mode. Branching to a Thumb-encoded address is how you switch modes. +3. `cpsid i` - mask interrupts so nothing fires mid-handoff. +4. Write `0xE000ED08` (the **VTOR** register) with the new vector table base. + From here on, exceptions use the app's vectors. +5. `msr msp` - load the app's initial stack pointer from `vectors[0]` + (`0x20082000`). +6. `dsb`/`isb` - force the memory and instruction pipelines to catch up. +7. `entry()` - call the reset handler. It never returns to the bootloader. + +The assembly, as it appears in the ELF (this is exactly what you will +disassemble in GDB and Ghidra): + +``` +10000394 : + 10000394: 6843 ldr r3, [r0, #4] ; entry = vectors[1] + 10000396: b672 cpsid i ; mask IRQs + 10000398: mov.w r2, #0xe000e000 ; SCB base + 1000039c: str.w r0, [r2, #3336] ; VTOR = r0 (0xE000ED08) + 100003a0: ldr r2, [r0, #0] ; sp = vectors[0] + 100003a2: msr MSP, r2 + 100003a6: dsb sy + 100003aa: isb sy + 100003ae: bx r3 ; branch to reset handler +``` + +When you set a breakpoint on `image_start` and single-step, you will see the +PC jump from `100003ae` to `1002015d` and disappear into application startup. + +--- + +## Part 8: Using AES in the Application (a Fully Worked Example) + +The application is the Week 11 IR remote firmware, but with one addition: a +module (`secret.c`) that decrypts a banner at runtime using the **Mbed TLS AES +that ships inside the Pico SDK**. This part teaches you the SDK's real AES API +on real code, and it plants the exact artifact you will hunt for in the +reverse-engineering parts. + +### 8.1 The API You Need (all from mbedtls, all shipped in the SDK) + +Four calls. That is the entire surface we touch: + +| Call | Purpose | +| --------------------------------------- | ---------------------------------------------- | +| `mbedtls_aes_init(ctx)` | Give the context a clean base state. | +| `mbedtls_aes_setkey_dec(ctx, key, 128)` | Expand the 16-byte key for decryption. | +| `mbedtls_aes_crypt_cbc(ctx, mode, len, iv, src, dst)` | Decrypt one or more whole blocks. | +| `mbedtls_aes_free(ctx)` | Clean up (releases nothing for a stack context). | + +`mbedtls_aes_crypt_cbc` is the workhorse. Its important contract: + +- `len` must be a multiple of 16 (a whole number of AES blocks). +- The IV is **read and updated in place**; you must give it a mutable copy. +- `src` and `dst` may be the same pointer - the operation is **in-place**. + That is how `secret_decrypt` reuses one 33-byte buffer for ciphertext, then + plaintext. + +### 8.2 The Secret Banner Link: Host Side Production + +The plaintext banner is exactly 32 bytes (two AES blocks), so no padding is +needed. It was encrypted on the host with OpenSSL using the same key and IV: + +``` +$ printf '%s' 'SECRET: IR LINK SECURED ONLINE ' \ + | openssl enc -aes-128-cbc \ + -K 49726f6e4e6574426f6f744b65792121 \ + -iv 41707053656372657449563132333435 \ + -nopad | xxd -p +baec4a1925861bb92dfd9f13f79b3e80cf12b698db9165be8fd7c3477bb2e76e +``` + +The hex strings are: + +``` +KEY = 49 72 6F 6E 4E 65 74 42 6F 6F 74 4B 65 79 21 21 = "IronNetBootKey!!" +IV = 41 70 70 53 65 63 72 65 74 49 56 31 32 33 34 35 = "AppSecretIV12345" +CT = ba ec 4a 19 25 86 1b b9 2d fd 9f 13 f7 9b 3e 80 + cf 12 b6 98 db 91 65 be 8f d7 c3 47 7b b2 e7 6e +PT = "SECRET: IR LINK SECURED ONLINE " (32 bytes, two spaces padded) +``` + +Notice: the ciphertext bytes in the disassembly of `secret_print_banner` +(Part 16) are **exactly** `baec4a19...76e6`. You will re-discover that the +reverse engineers' job is rarely to break AES (you cannot); it is to find +where the key, IV, and ciphertext are stored and feed them to a decryptor. +Here the key is 70 bytes away from the ciphertext. + +### 8.3 The Application-Side Module (`secret.c`) + +```c +static int secret_cbc(mbedtls_aes_context *aes, uint8_t *iv, uint8_t *buf) { + int rc = mbedtls_aes_crypt_cbc(aes, MBEDTLS_AES_DECRYPT, APP_BANNER_LEN, + iv, buf, buf); + return rc; +} + +static int secret_decrypt(uint8_t *buf) { + mbedtls_aes_context aes; + uint8_t iv[APP_AES_BLOCK]; + memcpy(iv, banner_iv, APP_AES_BLOCK); + mbedtls_aes_init(&aes); + mbedtls_aes_setkey_dec(&aes, banner_key, 128); + int rc = secret_cbc(&aes, iv, buf); + mbedtls_aes_free(&aes); + return rc; +} + +int secret_print_banner(void) { + uint8_t buf[APP_BANNER_LEN + 1]; + memcpy(buf, banner_ct, APP_BANNER_LEN); + buf[APP_BANNER_LEN] = '\0'; + int rc = secret_decrypt(buf); + if (rc != 0) return rc; + printf("app banner: %s\n", (char *)buf); + return 0; +} +``` + +Walk through it: + +1. `memcpy(buf, banner_ct, 32)` - pull the two ciphertext blocks into a working + buffer (with a spare byte for the terminating `'\0'`). +2. `banner_iv` is `static const`, so it cannot be safely mutated by the CBC + routine; copy it to a local array first. +3. Init + expand the key ("setkey_dec" stores the pre-computed decryption key + schedule once, so `crypt_cbc` is fast). +4. `crypt_cbc` writes the plaintext back into `buf`: `src == dst`. +5. Print. Release. + +If the SDK's mbedtls were misconfigured (say, you forgot to enable +`MBEDTLS_AES_C` in `common/include/mbedtls_config.h`), `crypt_cbc` returns a +negative error instead of decrypting, and the module refuses to print garbage. + +### 8.4 CBC, In Pictures + +CBC decryption undoes each block with the *previous* ciphertext block: + +``` ++-------+ +-------+ +-------+ +| C1 | | C2 | | C3 | ++-------+ +-------+ +-------+ + | | | + v v v ++-------+ +-------+ +-------+ +| AES-d | | AES-d | | AES-d | ++-------+ +-------+ +-------+ + | | | + v v v ++-------+ +-------+ +-------+ +| XOR | | XOR | | XOR | ++-------+ +-------+ +-------+ + | | | + v v v ++-------+ +-------+ +-------+ +| P1 | | P2 | | P3 | ++-------+ +-------+ +-------+ +``` + +That is why the IV is the "previous block" for block 1. In-place operation is +safe because C1 is no longer needed once P1 is produced ... except block two +needs C1, so the ciphertext *before* it was overwritten must still be intact. +mbedtls handles this correctly internally; you only owe it an untouched IV +copy. + +### 8.5 How the Application Is Structured (modules, not a mega-file) + +This week the app got the same treatment as the bootloader: `app_main.c` is +only entry + the poll loop. Everything else lives in a module: + +``` +app/ + include/ + ir.h NEC receiver API (ir_init, ir_getkey) + led.h LED controller type + API (simple_led_ctrl_t, led_default, + led_init, led_handle_ir) + secret.h AES banner API (secret_print_banner) + src/ + app_main.c ONLY stdio, banner, led_init, ir_init, then the poll loop + ir.c NEC timing decoder + led.c 3-LED controller (mapping, blink, hold-on) + secret.c the AES-128-CBC banner module +``` + +`app_main.c` in full: + +```c +static void ir_poll_loop(simple_led_ctrl_t *leds) { + while (true) { + int key = ir_getkey(); + if (key >= 0) led_handle_ir(leds, key); + else sleep_ms(1); + } +} + +int main(void) { + stdio_init_all(); + secret_print_banner(); + simple_led_ctrl_t leds = led_default(); + led_init(&leds); + ir_init(IR_PIN); + printf("IR receiver on GPIO %d ready\n", IR_PIN); + ir_poll_loop(&leds); +} +``` + +The `simple_led_ctrl_t` type carries a Doxygen block in `led.h`; notice the +struct fields (`led1_pin`...`led3_state`) are visible in `ir_getkey`'s +callers but the types stay in the header, exactly the WEEK 11 lesson about +structs being flattened by the compiler (see the `led_handle_ir` disassembly +in Part 16 for the flattened, inlined version). + +--- + +## Part 9: Building Everything + +### Step 1: Configure the CMake build + +From the project directory: + +``` +$ cd 0x0026a_custom-bootloader + +$ cmake -B build -G Ninja \ + -DPICO_BOARD=pico2 \ + -DPICO_PLATFORM=rp2350 \ + -DCMAKE_BUILD_TYPE=Release \ + -DPICO_SDK_PATH="$HOME/.pico-sdk/sdk/2.2.0" \ + -DPICO_TOOLCHAIN_PATH="$HOME/.pico-sdk/toolchain/14_2_Rel1" +``` + +### Step 2: Build both images + +``` +$ cmake --build build +``` + +You should see two linked executables, no warnings: + +``` +[6/7] Linking CXX executable 0x0026a_app.elf +[7/7] Linking CXX executable 0x0026a_bootloader.elf +``` + +### Step 3: Check the artifacts + +``` +$ ls -l build/0x0026a_bootloader.bin build/0x0026a_app.bin +-rwxr-xr-x 27772 0x0026a_bootloader.bin +-rwxr-xr-x 21656 0x0026a_app.bin +``` + +The bootloader includes the second-stage loader and binary-info, so it is +larger; the app is 21656 bytes (`0x5498`), which is the number baked into the +manifest. + +### Step 4: Confirm the app really is relocated + +``` +$ ~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-nm -n build/0x0026a_app.elf | grep -E ' _reset_handler| main$| ir_getkey| secret_print_banner' +1002015c T _reset_handler +10020234 T main +100202a4 T ir_getkey +10020568 T secret_print_banner +``` + +Every address is `0x1002xxxx`. If you see `0x1000015c` for `_reset_handler`, +the linker script was not applied and the bootloader would jump the wrong way. + +--- + +## Part 10: Signing the Image on the Host + +### Step 5: Compute the tag and write the manifest + +``` +$ python3 tools/sign_firmware.py build/0x0026a_app.bin --out build/manifest.bin +image : build/0x0026a_app.bin (21656 bytes) +app_base : 0x10020000 +cmac tag : ef041ec592f0c56727da2651d373947b +manifest : build/manifest.bin (4096 bytes) +``` + +### Step 6: Verify the manifest against the image + +``` +$ python3 tools/sign_firmware.py 0x0026a_app.bin --verify build/manifest.bin +computed : ef041ec592f0c56727da2651d373947b +result : MATCH +``` + +MATCH means the exact bytes in `0x0026a_app.bin` produce exactly the tag the +bootloader will read from flash. Signing is not magic: it is one CMAC +computation over the bytes, plus a 36-byte header written into a 4 KB sector. + +### Step 7: Read the manifest back byte by byte + +``` +$ xxd build/manifest.bin | head -3 +00000000: 5746 4c42 0100 0000 0000 0210 9854 0000 WFLB........T.. +00000010: ef04 1ec5 92f0 c567 27da 2651 d373 947b .......g'.&Q.s.{ +00000020: ffff ffff ffff ffff ffff ffff ffff ffff ................ +``` + +Cross-reference with Part 5: magic, version 1, base `0x10020000`, size +`0x5498`, then the 16-byte tag, then `0xFF` padding. + +--- + +## Part 11: Flashing the Three Images + +Three images, three addresses. The bootloader first (it owns the system), then +the manifest, then the app. If you flash the app before the manifest, the +bootloader happily boots it anyway (the manifest is already in flash from a +previous lab run) - order only matters on a bare board. + +### The whole chain in one drag (recommended) + +On a bare board skip straight to one file: hold BOOTSEL, connect the Pico 2, +and copy `0x0026a_full.uf2` to the `RP2350` drive. That single UF2 writes all +three images at once - no OpenOCD, no second drag. Section 6.9 explains how it +is built; the hardware-verified behavior is: + +- BOOTSEL accepts it and unmounts the drive; +- the boot ROM writes bootloader, manifest, and app to their absolute + addresses; +- on reset the bootloader verifies the manifest and jumps to the app. + +The steps below are the three-image equivalent, which is what you use while +iterating on a single image or when you prefer OpenOCD over the button. + +### A. The bootloader: two options + +**Option 1 - BOOTSEL (no extra tools):** hold the BOOTSEL button, connect the +Pico 2, copy `0x0026a_bootloader.uf2` to the drive, which lands the bootloader +at `0x10000000` (or drag `0x0026a_full.uf2` to write the whole chain in one +shot). + +**Option 2 - OpenOCD:** + +``` +$ "$HOME/.pico-sdk/openocd/0.12.0+dev/openocd" \ + -s "$HOME/.pico-sdk/openocd/0.12.0+dev/scripts" \ + -f interface/cmsis-dap.cfg -f target/rp2350.cfg \ + -c "adapter speed 5000" \ + -c "program 0x0026a_bootloader.bin 0x10000000 verify reset exit" +``` + +The flags, in the repo's own words: + +| Flag | Meaning | +| --------------- | ------------------------------------------------------------- | +| `cmsis-dap.cfg` | The Debug Probe is a CMSIS-DAP v1 adapter | +| `rp2350.cfg` | RP2350 target: dual Cortex-M33 with a B0-style DAP | +| `adapter speed` | SWD clock in kHz; 5000 is a conservative write-path default | +| `program` | Write + `verify` (read-back compare) + `reset` + `exit` | + +### B. The manifest (always its own sector) + +``` +$ "$HOME/.pico-sdk/openocd/0.12.0+dev/openocd" \ + -s "$HOME/.pico-sdk/openocd/0.12.0+dev/scripts" \ + -f interface/cmsis-dap.cfg -f target/rp2350.cfg \ + -c "adapter speed 5000" \ + -c "program manifest.bin 0x1001F000 verify reset exit" +``` + +### C. The application (relocated target) + +``` +$ "$HOME/.pico-sdk/openocd/0.12.0+dev/openocd" \ + -s "$HOME/.pico-sdk/openocd/0.12.0+dev/scripts" \ + -f interface/cmsis-dap.cfg -f target/rp2350.cfg \ + -c "adapter speed 5000" \ + -c "program 0x0026a_app.bin 0x10020000 verify reset exit" +``` + +Each `program` invocation ends with `verify reset exit`, so OpenOCD reads the +bytes back and aborts loudly on a mismatch. `verify` here is straight +flash read-back - a completely different check from the CMAC the bootloader +does at boot. + +While you are at it, note that the repo's `flash.sh` helper always programs at +`0x10000000` - convenient for the bootloader, wrong for the manifest and app. +The three explicit commands above are the tutorial forms. + +--- + +## Part 12: Running It (First Boot, Serial Console) + +### Step 8: Open a serial console + +Open a terminal on the Debug Probe's UART channel (or the board's USB-UART +bridge if you wired one) at 115200 baud: + +``` +$ screen /dev/cu.usbmodem311402 115200 +``` + +Replace the device name with whatever `ls /dev/cu.usb*` shows. + +### Step 9: Reset the board and watch the bootlog + +Press the RESET button (or let OpenOCD's `reset` do it). After roughly two +seconds you see the bootloader banner, then the app banner: + +``` +=== 0x0026a secure bootloader === +signature valid, entering app at 0x10020000 +app banner: SECRET: IR LINK SECURED ONLINE +IR receiver on GPIO 5 ready +``` + +The three lines tell you the whole story: the bootloader ran, it verified the +image against the manifest (Part 10), it jumped to `0x10020000`, and inside +the app `secret_print_banner()` decrypted the banner with the SDK AES and +printed it (Part 8). Press keys on the remote and the `NEC command:` lines +appear. + +What you just watched, in one trace (the exact functions and where they live): + +| Line on screen | Function that printed it | Address | +| ------------------------------------------- | ------------------------ | ------------ | +| `=== 0x0026a secure bootloader ===` | `boot_init` | `0x10000278` | +| `signature valid, entering app at ...` | `boot_launch` | `0x100002ac` | +| `app banner: SECRET...` | `secret_print_banner` | `0x10020568` | +| `IR receiver on GPIO 5 ready` | `main` (app) | `0x10020234` | + +--- + +## Part 13: The Tamper Test (Breaking the Chain) + +Now do the attacker's favorite move: change one byte, keep everything else, +reflash, and see what the bootloader does. + +### Step 10: Flip a byte in the app image (do NOT re-sign) + +``` +$ cp 0x0026a_app.bin rogue_app.bin +$ printf 'X' | dd of=rogue_app.bin bs=1 seek=0 count=1 conv=notrunc +``` + +(The byte at offset 0 is the low byte of the initial SP; any change breaks the +CMAC, so the location is irrelevant for this test.) + +### Step 11: Flash the rogue image over the good one + +Re-run the app `program` command from Part 11 but with `rogue_app.bin`. Do not +touch the manifest - the tag inside it still corresponds to the *original* +image. + +### Step 12: Reset and observe the rejection + +``` +=== 0x0026a secure bootloader === +BOOT FAILED: firmware signature invalid +``` + +The second line is missing. The app never ran. The blue/yellow LED heartbeat +on the board keeps blinking (500 ms), which is `boot_halt()`'s idle loop. No +matter how many times you re-flash a modified image without a matching tag, +the bootloader refuses. + +### Step 13: Confirm it still boots after restoring the good image + +Re-flash `0x0026a_app.bin` (fresh, matching the manifest) and reset - or just +drag `0x0026a_full.uf2` onto the BOOTSEL drive again to restore the whole +chain in one move. The banner returns. The bootloader is doing real +enforcement, not just complaining once. + +Stop and think about the security statement this demonstrated: + +- **Patch a byte, no re-sign -> reject.** The device cannot be modified cheaply. +- **Dump flash, read the key, re-sign -> accept.** Because the key lives in the + binary (Part 7.2), a full flash dump defeats this scheme. Part 19 fixes that + in a real product. + +--- + +## Part 14: Reverse Engineering the Bootloader with GDB (Live) + +Live debugging on the Pico 2 uses the repo's two scripts: `debug-server.sh` +owns the Debug Probe as a GDB server, and `pico-gdb-memory.gdb` confines GDB +memory reads to valid flash/RAM so bogus register previews cannot fault SWD. + +### Step 14: Start the GDB server (Terminal 1) + +``` +$ ./debug-server.sh +``` + +The script resets the target and leaves it *running* (`reset run`), exposing +`127.0.0.1:3333`. + +### Step 15: Start GDB on the bootloader (Terminal 2) + +``` +$ ~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb build/0x0026a_bootloader.elf +``` + +Connect and confine memory access: + +``` +(gdb) target extended-remote :3333 +(gdb) source ../../pico-gdb-memory.gdb +``` + +``` +delete mem +mem 0x10000000 0x10400000 ro +mem 0x20000000 0x20082000 rw +set mem inaccessible-by-default on +info mem +``` + +### Step 16: Stop the running target cleanly + +``` +(gdb) monitor halt +(gdb) monitor reg pc +``` + +You will land somewhere in the bootloader or app depending on how far the +resets progressed - either is fine. + +### Step 17: Disassemble `main` and read the boot sequence + +``` +(gdb) disassemble 0x10000234,+80 +``` + +You should see the miniature version of Part 7.1: + +``` +0x10000234
: push {lr} +0x10000238 : bl 0x10000278 +0x1000023e : bl 0x100002c8 +0x10000244 : bl 0x100002fc +0x1000024c : bl 0x100003b0 +0x10000254 : bl 0x100002ac +``` + +Note `main` does almost nothing itself - it is a sequence of calls, exactly +the design we built. + +Before accepting `0x10000234` as "the start", note that it is not the start of +the image at all. The image begins at `0x10000000` with the Cortex-M vector +table, and `main` sits `0x234` bytes in because the vector table, the default +ISRs, the SDK binary-info header, the RP2350 IMAGE_DEF block, the reset handler, +and crt0 all run before it. Appendix A.2 derives that layout from first +principles and proves it on the board. It is also why you will see `0x10000234` +for the bootloader and `0x10020234` for the app: the same `0x234` offset, with +the base shifted by `0x20000`. + +### Step 18: Stop inside the crypto (the payoff breakpoint) + +The interesting code is `verify_manifest` at `0x100003b0` and the mbedtls +front-end `aes128_cmac` at `0x1000031c`. Re-arm a hardware breakpoint and +reset: + +``` +(gdb) hbreak *0x100003b0 +(gdb) monitor reset halt +(gdb) continue +``` + +After 2 s (the startup pause) the core stops at the top of `verify_manifest`, +with `r0` pointing at the manifest copy on the stack. Step a little and watch +the argument registers the mbedtls call receives: + +``` +(gdb) disassemble 0x100003b0,+50 +(gdb) x/4bx 0x10006064 # low nibbles of the key? no: dump the key +(gdb) x/16bx 0x10006064 # the 16-byte fw_key from .rodata +0x10006064: 49 72 6f 6e 4e 65 74 42 6f 6f 74 4b 65 79 21 21 +``` + +`0x49 0x72 0x6F 0x6E ...` is `"IronNetBootKey!!"`. You just pulled the boot +key out of live flash with three GDB commands. (Refresh: the key's virtual +address is `0x10006064`; `nm` reports it as `10006064 r fw_key`.) + +### Step 19: Watch the verdict + +Let it run to the compare: + +``` +(gdb) hbreak *0x100003d0 # the bl cmac_tags_equal +(gdb) continue +``` + +`cmac_tags_equal` compares the freshly computed tag (on the stack) against the +16 bytes at offset +16 of the manifest (which came from flash). Step over it +(`next`) and check the return: + +``` +(gdb) next +(gdb) info registers r0 +``` + +`r0 == 1` means the tags matched and `boot_launch` is next. + +### Step 20: Single-step the application jump + +Set a breakpoint at the tail of `image_start` and keep going: + +``` +(gdb) break *0x100003ae +(gdb) continue +``` + +At `0x100003ae` the core is one `bx r3` away from the app. Inspect what it is +about to execute: + +``` +(gdb) info registers r3 +r3 0x1002015d +(gdb) x/4bx 0x10020000 # the app's vector table +0x10020000: 00 20 08 20 5d 01 02 10 # SP=0x20082000, reset=0x1002015d +``` + +`r3` and `vectors[1]` agree. Step into the jump: + +``` +(gdb) stepi +``` + +Watch the PC: it is now `0x1002015c` (the unencoded reset-vector address of +`_reset_handler`) and the stack pointer is `0x20082000`. The bootloader is +finished; the application startup code owns the machine. + +### Step 21: Re-verify from the application's side + +Quit and relaunch GDB against the app ELF (the core is already running it, so +no reset needed - reattach so symbols load): + +``` +(gdb) file build/0x0026a_app.elf +(gdb) target extended-remote :3333 +(gdb) hbreak *0x10020234 # app main +(gdb) monitor reset halt +(gdb) continue +``` + +When you hit `main`, the banner has already been decrypted and printed (it +runs before `main`). To watch the AES itself, break at +`secret_print_banner` instead: + +``` +(gdb) hbreak *0x10020568 +(gdb) monitor reset halt +(gdb) continue +``` + +Then single-step the four mbedtls calls from Part 8.1. At +`0x10020598` you can read the key argument: + +``` +(gdb) disassemble 0x10020568,+110 +(gdb) x/16bx 0x10024e6c # banner_key in .rodata +``` + +`0x24e6c` is the offset of the key inside the app image (Part 16/17 confirms +by Ghidra). You are reading the same constant three different ways: C source, +GDB, and now Ghidra. + +--- + +## Part 15: Reverse Engineering the Bootloader in Ghidra + +### Step 22: Import the ELF (not the raw .bin) + +Ghidra will happily import either, but the **ELF** brings symbols, section +names, and types. For a stripped factory image you would import the raw `.bin` +as a "Raw Binary" at base `0x10000000`; for this lab, use the ELF and check +the green "found symbols" messages after auto-analysis. + +1. **File > New Project** (non-shared), +2. **File > Import File**, select `build/0x0026a_bootloader.elf`, +3. Language: confirm `ARM LE:LE32:v8M` / Cortex-M33 view, +4. **Analyze** (auto-analysis defaults are fine). + +### Step 23: Find the interesting functions + +Open **Symbol Tree > Functions**: + +| Function | Address | What you will see | +| -------------------- | ------------ | -------------------------------------------------- | +| `main` | `0x10000234` | Five calls, no logic of its own | +| `boot_init` | `0x10000278` | `stdio_init_all`, a wait, a puts | +| `verify_manifest` | `0x100003b0` | the 16-byte key push + `aes128_cmac` + compare | +| `aes128_cmac` | `0x1000031c` | `mbedtls_cipher_info_from_type` + `mbedtls_cipher_cmac` | +| `image_start` | `0x10000394` | the VTOR/MSP/bx block from Part 7.4 | + +Double-click `verify_manifest`. Ghidra's decompiler shows something close to +our C - including the constant table it pulled from `.rodata`. Open the +**Data** panel and navigate to `0x10006064`: Ghidra lists a 16-byte array. It +is the key. Rename it by selecting and pressing `L` (e.g. `fw_key`), then +annotate `main`'s call graph with the whole boot sequence. + +Do not read the bare addresses in that table as arbitrary. `main` at +`0x10000234` is `0x234` bytes into the image because the vector table and the +SDK startup preamble occupy everything ahead of it, and the app's `main` is the +same offset at `0x10020234`. Appendix A.2 derives this from first principles and +proves it with a live GDB session against the board. + +### Step 24: Recover the "spec" from the image + +- List exports/imports: the binary imports `cdns_usb_table`, stdio routines, + and - from `.dynamic` or relocation - nothing surprising for an SDK binary. +- Note `binary_info` header: the SDK stores program_name + (`0x0026a_bootloader`) and build date inside the image at `0x10000100`; this + is exactly what `picotool info` prints and a useful fingerprint for hunting + unknown binaries in the wild. + +--- + +## Part 16: Reverse Engineering the Application in Ghidra (Find the AES) + +The app is the richer target. Repeating Part 15 step 22 with +`build/0x0026a_app.elf` gives you the full symbol table, because we shipped +the ELF. On a real malicious/hardened build you would import +`0x0026a_app.bin` at `0x10020000` (base from `manifest.bin`) and rely on +strings. + +### Step 25: The easy tour (symbols) + +| Symbol | Address | Observations | +| ---------------------- | ------------ | --------------------------------------------------- | +| `_reset_handler` | `0x1002015c` | first code; assumes SP/VTOR set (our bootloader does) | +| `main` | `0x10020234` | the thin orchestrator from Part 8.5 | +| `secret_print_banner` | `0x10020568` | four mbedtls calls; the AES gate | +| `led_handle_ir` | `0x100204d8` | flattened struct logic (see below) | + +Open `main`. Because everything was inlined and optimized, Ghidra shows a +clean calling skeleton - the same one GDB showed in Part 14 Step 21. + +Compare the addresses with the bootloader's from Step 23 and you will see the +relocation for yourself: `_reset_handler` moved from `0x1000015c` to +`0x1002015c`, and `main` from `0x10000234` to `0x10020234`. Every symbol is the +bootloader's plus `0x20000`; only the base changed. Appendix A.2 explains and +proves why both images put `main` `0x234` bytes in. + +### Step 26: The "struct is a lie" lesson, revisited + +Open `led_handle_ir` at `0x100204d8`. Ghidra's decompiler will *not* show you +`simple_led_ctrl_t` fields by name (the type was flattened at compile time, +WEEK 11 Part 10). Instead you see direct byte loads off the pointer and the +constant compares `0xc`, `0x18`, `0x5e` - the NEC commands. The three +`mcrr`/`strb` groups are the `gpio_put`/`gpio_set_dir` calls inlined from the +LED module. Same behavior, zero struct abstraction, single program counter. + +### Step 27: Find the four AES calls + +Open `secret_print_banner`. The decompiler names the imported mbedtls calls +directly: + +``` +mbedtls_aes_init(ctx) +mbedtls_aes_setkey_dec(ctx, key, 128) +mbedtls_aes_crypt_cbc(ctx, MBEDTLS_AES_DECRYPT, 32, iv, ct_buf, ct_buf) +mbedtls_aes_free(ctx) +``` + +The red referenced addresses are: + +| Data | Address (VA) | Bytes | ASCII | +| ---------------- | ------------ | ------------------------------- | ------------ | +| banner ciphertext| `0x10024d78` | `ba ec 4a 19 ... 7b b2 e7 6e` | (binary) | +| banner IV | `0x10024d9c` | `41 70 70 53 65 63 72 65 74 49 56 31 32 33 34 35` | `AppSecretIV12345` | +| `app banner: %s` | `0x10024d68` | `61 70 70 20 62 61 6e 6e 65 72 3a 20 25 73 0a` | `app banner: %s\n` | +| banner key | `0x10024e6c` | `49 72 6f 6e 4e 65 74 42 6f 6f 74 4b 65 79 21 21` | `IronNetBootKey!!` | + +### Step 28: Decrypt it with what you found + +Ghidra hands you plain values; OpenSSL decrypts for you - you do not need to +recover the source: + +``` +$ printf 'baec4a1925861bb92dfd9f13f79b3e80cf12b698db9165be8fd7c3477bb2e76e' \ + | xxd -r -p \ + | openssl enc -d -aes-128-cbc \ + -K 49726f6e4e6574426f6f744b65792121 \ + -iv 41707053656372657449563132333435 -nopad +SECRET: IR LINK SECURED ONLINE +``` + +Because the key is 70 bytes from its ciphertext in the same ELF, "breaking" +the app took: import, click, copy three hex constants, run one command. The +whole exercise is about **finding key material**, never about cracking AES. + +### Step 29: Now repeat it on the stripped .bin (harder, real-world) + +Delete the app from the project, import `0x0026a_app.bin` with **Language = +ARM LE v8M** and **Image base = 0x10020000**. No symbols. Now your anchors +are: + +- The string `app banner: %s` (String search, `Ctrl+Shift+S`), which xrefs to + the second half of `secret_print_banner`. +- The 16 bytes `AppSecretIV12345` nearby in `.rodata`. +- The constant `0x48564d411f...` = `AppSecretIV12345` pattern as 4 little + endian words (this is your Ghidra jump-start trick: search for the hex of an + ASCII IV). + +Renaming data (`L`) and entering type views as you go will reconstruct the +module structure from the stripped blob exactly as if a debugger had been +kind. + +--- + +## Part 17: A Bootloader You Can Read (Reference Address Map) + +Everything you should have collected so far, in one table. Builds are +deterministic for the checked-in sources, so your numbers should match. + +Read every address as `base + offset`. The bootloader is based at `0x10000000` +and the app at `0x10020000`, so `main` is `0x10000234` in one and `0x10020234` +in the other - the same `0x234` offset, relocated. Appendix A.2 derives that +offset from the vector table and the SDK startup code and proves it on the +board. + +### Bootloader (0x0026a_bootloader.elf) + +| Role | Symbol | Address | +| ----------------------- | ------------------- | ------------ | +| Reset vector (vector[1])| `_reset_handler` | `0x1000015c` | +| Initial SP (vector[0]) | (data) | `0x20082000` | +| Boot sequence | `main` | `0x10000234` | +| Console + 2 s pause | `boot_init` | `0x10000278` | +| Failure idle loop | `boot_halt` | `0x10000294` | +| Success handoff | `boot_launch` | `0x100002ac` | +| Flash manifest read | `manifest_read` | `0x100002c8` | +| Magic/version check | `manifest_is_valid` | `0x100002fc` | +| mbedtls CMAC front-end | `aes128_cmac` | `0x1000031c` | +| Constant-time compare | `cmac_tags_equal` | `0x10000348` | +| VTOR/MSP/bx jump | `image_start` | `0x10000394` | +| CMAC verdict | `verify_manifest` | `0x100003b0` | +| Boot key (rodata) | `fw_key` | `0x10006064` | + +### Application (0x0026a_app.elf) + +| Role | Symbol | Address | +| ----------------------- | --------------------- | ------------ | +| App reset vector | `_reset_handler` | `0x1002015c` | +| App entry point | `main` | `0x10020234` | +| NEC decoder init | `ir_init` | `0x1002027c` | +| NEC blocking decode | `ir_getkey` | `0x100202a4` | +| LED default config | `led_default` | `0x10020498` | +| LED GPIO setup | `led_init` | `0x100204a8` | +| IR -> LED dispatch | `led_handle_ir` | `0x100204d8` | +| AES banner decrypt | `secret_print_banner` | `0x10020568` | +| String `app banner: %s` | (rodata) | `0x10024d68` | +| Banner ciphertext | (rodata) | `0x10024d78` | +| Banner IV | (rodata) | `0x10024d9c` | +| Banner key | (rodata) | `0x10024e6c` | +| Initial SP (vector[0]) | (data) | `0x20082000` | + +--- + +## Part 18: Summary and Review + +### What You Built + +``` ++---------------+ +---------------+ +---------------+ +| ROM | | BOOTLOADER | | APPLICATION | +| (silicon) | --> | @0x10000000 | --> | @0x10020000 | ++---------------+ +---------------+ +---------------+ +``` + +Enforcement point: `verify_manifest` recomputes +`AES_CMAC(fw_key, app_base, app_size)` and compares to the stored tag. On +match, `image_start` sets VTOR, loads SP, and branches to the app reset +vector. On mismatch, `boot_halt` reports and idles. One flipped byte in the +app and the whole chain refuses. + +### Key Lessons + +1. **Linker scripts place your program.** `MEMORY`/ORIGIN/LENGTH + a changed + `FLASH` line moved the app 128 KiB up. `__StackTop = 0x20082000` in the + vector table is direct evidence. +2. **Modules keep firmware readable.** Both `main.c` files are thin; crypto, + manifest, IR, LED, and banner live in one-responsibility `.c`/`.h` pairs, + every prototype Doxygen-documented, nothing past 8 executable lines. +3. **AES is everywhere in SDK firmware.** `pico_mbedtls` gives you a tuned AES + for free. You used it both to authenticate (bootloader CMAC) and to hide a + string (app CBC banner). +4. **CBC with no padding** encrypts 32 bytes as two blocks; IV is read/updated + in place - give `crypt_cbc` a mutable copy. +5. **Static keys are secrets-in-name only.** SWD/GDB/Ghidra read the key from + flash (`0x10006064`) in minutes. Real products store root keys in OTP and + verify with the ROM (Part 19). +6. **Reverse engineering = treasure hunt.** You never "break" AES; you find + the key, IV, and ciphertext and press decrypt. + +--- + +## Part 19: Your Turn (Hacking Exercises) + +Try these on your own board; each one is a small, safe extension. + +### Challenge 1 - Swap two LED pins without touching the source + +The PINs are value-initialized data in `led_default` (the struct fields the +compiler stored in `.rodata`). Find the address in the stripped app `.bin` +(Ghidra: `led_default` xrefs the literals 16, 17, 18), patch the 16 and 18 +literals, re-flash the *unsigned* image, and watch the bootloader reject it - +then re-sign with `sign_firmware.py` and this time it boots with the hack. + +### Challenge 2 - Change the boot key (both sides) + +Edit the 16 bytes in `verify.c`, rebuild only the bootloader, re-sign the app +with `--key` matching, flash all three, and boot. Then sign the app with the +OLD key and confirm rejection. You have now installed your own signing +authority on your own board. + +### Challenge 3 - Make the banner say something else + +Change the plaintext (must stay 32 bytes for the no-padding CBC), re-encrypt +with `openssl`, update `banner_ct` in `secret.c`, rebuild, re-sign, flash. +Your Ghidra notes from Part 16 now decode the new banner id +to differentiate it. + +### Challenge 4 - Think through the upgrade path + +The manifest has a `version` field that is currently ignored after a magic +check. Sketch how `boot_launch` could validate a counter ("only downgrade a +fixed number of times") - the classic anti-rollback feature that separates +consumer OTA from device management-grade OTA. You should be able to name the +flash sectors you would need to reserve to make that safe (hint: state must +survive app updates, so it cannot live in the app image). + +### Challenge 5 - The honest conversation about the key + +Write one paragraph each for a product manager: (1) why AES-CMAC with a flash +key stops a script-kiddie flash overwrite, and (2) why it does not stop a +determined hardware attacker, and (3) which real mechanism (OTP key, ROM +verifier with `secp256k1`, anti-dumping measurements) closes that hole. If you +can explain all three, you understand secure boot at a professional level. + +--- + +## Key Takeaways + +- Authenticated boot = each stage refuses to start the next until a secret join + the image to a tag proves it is the right bytes. +- AES-128-CMAC (RFC 4493) is a keyed CBC-MAC with two subkeys; unforgeable + without the key, verifiable with a few lines of mbedtls. +- `manifest.bin` is a 4096-byte sector at `0x1001F000`; a 16-byte tag is the + only secret-bearing field. +- The app lives at `0x10020000` because `memmap_app.ld` says so; the vector + table's `0x20082000` stack pointer proves it. +- The SDK bundles Mbed TLS; `mbedtls_aes_*` decrypts at runtime with zero + third-party code. +- OpenOCD `program verify reset exit` writes each partition; + flash read-back `verify` is not authentication. +- GDB `hbreak`/`stepi`/`x/16bx` on a live Pico 2 shows you key bytes and the + exact `bx` that enters the app. +- Ghidra on the ELF names the AES calls; Ghidra on the .bin finds them via the + constant table and IV string. +- A key dumped from flash is not a secret. OTP + ROM verification is. + +--- + +## Glossary + +| Term | Definition | +| ------------------- | ------------------------------------------------------------------- | +| Boot chain | Ordered stages where each stage authenticates the next. | +| XIP | Execute-in-place: code runs straight from flash memory-mapped at 0x10000000. | +| CMAC | Keyed message-authentication code based on a block cipher (NIST CMAC / RFC 4493). | +| CBC-MAC | MAC built by chaining AES-CBC blocks; needs the final-block fix CMAC adds. | +| Tag | The short authenticator output (16 bytes here) proving message integrity. | +| Manifest | Small signed record describing an image: address, size, tag. | +| VTOR | Vector Table Offset Register; tells the CPU where the vector table is. | +| MagnumOpus issue | A willful misunderstanding source: see Part 18. | +| OTP | One-time-programmable memory; writes once, reads forever, cannot be re-flashed. | +| RO/RW/HAL | read only / read write / hardware abstraction layer, the three concerns a linker script separates. | + +--- + +## Additional Resources + +### RFC and Standard References + +- RFC 4493 - The AES-CMAC Algorithm (the subkey derivation and four vectors used here) +- NIST SP 800-38B - Recommendation for Block Cipher Modes of Operation: The CMAC Mode for Authentication + +### In the Repo + +- `tools/sign_firmware.py` - the pure-Python signer/verifier (read the header comment for a CMAC walkthrough) +- `common/include/mbedtls_config.h` - the minimal SDK mbedtls config (AES_C, CBC, CMAC_C) + +### Pico SDK Internals (open these while you read Part 6) + +- `~/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_crt0/rp2350/memmap_default.ld` - the SDK linker script we copied +- `~/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_standard_link/` - crumbs for flash region generation +- `~/.pico-sdk/sdk/2.2.0/src/rp2_common/pico_crt0/crt0.S` - `_reset_handler`, `_entry_point`, and the vector table layout + +### Tooling Used in This Lab + +- OpenOCD from the SDK (`~/.pico-sdk/openocd/0.12.0+dev`) +- GDB / objdump / nm from the ARM GNU toolchain (`~/.pico-sdk/toolchain/14_2_Rel1`) +- Ghidra (import both ELF and raw .bin; see Parts 15-16) +- `openssl enc -aes-128-cbc -nopad` for host-side banner cryptography + +--- + +## Real-World Implications + +### What You've Learned in This Course + +Your Pico 2 is now a small secure-boot platform: ROM -> bootloader -> manifest +-> app, with an authenticated handoff at every boundary you control. The same +skills invert perfectly for defense: when you audit a device, this is the +mental model you bring - *what authenticates the next stage, where is the key, +and what happens if it is not there?* + +### The Power and Responsibility + +- The **power**: you can now build boot chains, move firmware around the + address space at will, extract keys, and re-sign images. That is the exact + toolbox used both to protect smart locks and to compromise them. +- The **responsibility**: only ever apply these techniques to devices you own + 100% or are explicitly authorized to test. The moment you run + `BOOT FAILED` on someone else's device, you have crossed into criminal + tampering and possibly a safety-critical product. +- The **engineering honesty**: a flash key is a speed bump, not a wall. Any + product story that claims "AES secure boot" must be asked, *where is the key, + and who can read it?* If the answer is "in the firmware," the whiteboard does + not add up. + +### Keep Learning + +- Swap the CMAC for the RP2350 ROM `secp256k1` verifier to get real + asymmetric trust (flash dumps stop being useful). +- Use `pico_set_uf2_...` on a real board to ship an OTA payload that your own + bootloader authenticates before the boot stage writes it. +- Read how real device IDs (RP2350's unique serial) can be mixed into the key + schedule so an image signed for one board will not run on another. + +**Now go flash your own CA.** You control the manifest, the key, and the +gate that decides what runs on your hardware. + +--- + +## Appendix A: End-to-End Reverse Engineering with GDB and Ghidra + +Parts 14-16 teach the two tools one at a time. This appendix is the +consolidated, start-to-finish version: a single adversary workflow that starts +with nothing but the shipped artifacts and a board, and ends with a forged +image the bootloader accepts. Every command is meant to be run in order. It is +the "give me the whole hunt" version - keep a terminal and a Ghidra window +open side by side. + +For short paths throughout, set: + +``` +$ export W=0x0026a_custom-bootloader +$ export GDB=~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb +$ export PCT=~/.pico-sdk/picotool/2.3.1/picotool/picotool +``` + +### A.1 What the attacker starts with + +Assume you were handed the release folder and a Debug Probe, with no source +and no README. Each artifact leaks a specific thing: + +| Artifact | What it gives you | +| ------------------------- | ----------------------------------------------------- | +| `0x0026a_bootloader.elf` | Full symbols for the gate: function names + addresses | +| `0x0026a_bootloader.bin` | The same code with no symbols (the real-world case) | +| `manifest.bin` | The on-flash spec: magic, base, size, and the tag | +| `0x0026a_app.bin` | The signed payload; its `.rodata` hides the AES key | +| `0x0026a_full.uf2` | The one-drag installer (bootloader + manifest + app) | + +The trust boundary is a single comparison: a freshly computed AES-128-CMAC of +the app bytes versus the 16-byte `tag` in the manifest. Everything below is +about recovering the inputs to that comparison, then supplying your own. + +### A.2 The image layout: from the vector table to main + +Read a Pico image at the byte level and know, with nothing assumed, why `main` +is at `0x234` and why the relocated app's `main` is at `0x10020234`. Every +number below is confirmed on the live board in A.2.5. + +#### A.2.1 The rule: an address is a base plus an offset + +An image is linked at a base address: `0x10000000` for the bootloader, +`0x10020000` for the app. The linker places byte 0 of the program at the base, +so every address is `base + offset`: + +``` +0x10000234 = 0x10000000 + 0x234 +``` + +`0x234` is hexadecimal (564 decimal). It is not a whole address and it is not +"the 234th byte"; it is the distance from the start of the image. + +#### A.2.2 The first bytes are a vector table, not main + +The Cortex-M33 does not reset into `main`. The hardware requires a vector table +at the image base and reads two words from it to start: word 0 is the initial +stack pointer, word 1 is the reset handler. The RP2350 has 16 system vectors +plus 52 IRQs, so the table is 68 words = 272 bytes = `0x110`. Live dump from +this board: + +``` +(gdb) x/16wx 0x10000000 +0x10000000 <__vectors>: 0x20082000 0x1000015d 0x1000011b 0x1000011d +0x10000010 <__vectors+16>: 0x10000111 0x10000111 0x10000111 0x10000111 +``` + +| Word | Value | Meaning | +| ---- | ------------ | ----------------------------------------------------------- | +| 0 | `0x20082000` | initial stack pointer (top of RP2350 SRAM) | +| 1 | `0x1000015d` | reset handler = `_reset_handler` (`0x1000015c`) + Thumb bit | +| 2 | `0x1000011b` | NMI | +| 3 | `0x1000011d` | HardFault | +| 4 | `0x10000111` | MemManage | +| ... | ... | remaining system vectors, then IRQ0..IRQ51 | + +Word 1 ends in `...5d`, not `...5c`, because Cortex-M code is Thumb code: the +hardware uses that low bit and branches to `0x1000015c`. GDB resolves it: + +``` +(gdb) info symbol 0x1000015d +_reset_handler + 1 in section .text +``` + +Two entry numbers exist and are not the same: +- the reset vector (table word 1) = `_reset_handler` at `0x1000015c`; +- the ELF entry point (`readelf -h`) = `0x1000014d` = `_entry_point` at + `0x1000014c`, an SDK trampoline that reloads SP and branches to + `_reset_handler`. + +Both converge on `_reset_handler`. Neither is `main`. + +#### A.2.3 The rest of the preamble and the arithmetic + +After the table, this fixed preamble runs before `main`: + +| Address | Symbol | Purpose | +| ------------ | ---------------------------- | ------------------------------------------- | +| `0x10000110` | `__default_isrs_start` | weak ISR defaults (`isr_irq0`..`isr_irq51`) | +| `0x10000124` | `binary_info_header` | name/build date shown by `picotool info` | +| `0x10000138` | `embedded_block` (IMAGE_DEF) | RP2350 metadata block the ROM reads | +| `0x1000014c` | `_entry_point` | trampoline | +| `0x10000150` | `_enter_vtable_in_r0` | `msr MSP` then `bx` to the reset handler | +| `0x1000015c` | `_reset_handler` | reset entry | +| `0x10000164` | `hold_non_core0_in_bootrom` | parks core 1 | +| `0x10000180` | `bss_fill_loop` / `data_cpy` | zero `.bss`, copy `.data` | +| `0x100001e4` | `_init` | runtime / constructors | +| `0x10000234` | `main` | your code | + +The sizes add up exactly: + +``` +vector table 0x110 (68 words) +default ISRs 0x014 +binary_info_header 0x014 +embedded IMAGE_DEF 0x014 + ----- +fixed preamble 0x14c ends at 0x1000014c +reset handler + crt0 0x0e8 fills 0x1000014c .. 0x10000234 + ----- +main 0x234 +``` + +So `main` is at `0x10000000 + 0x234`: 564 bytes in, because the hardware tables +and the C runtime occupy the first 564 bytes. This is the SDK layout for every +image; it is not specific to a bootloader. + +The live disassembly of the trampoline and reset handler shows the handoff: + +``` +(gdb) disassemble 0x1000014c,+56 +0x1000014c <_entry_point+0>: mov.w r0, #0 +0x10000150 <_enter_vtable_in_r0+0>: ldr r1, [pc, #120] +... +0x10000154 <_enter_vtable_in_r0+4>: ldmia r0!, {r1, r2} +0x10000156 <_enter_vtable_in_r0+6>: msr MSP, r1 +0x1000015a <_enter_vtable_in_r0+10>: bx r2 +0x1000015c <_reset_handler+0>: mov.w r0, #3489660928 +... +0x10000172 : bl 0x1000019a +... +0x10000180 : stmia r1!, {r0} +``` + +`_enter_vtable_in_r0` loads the initial stack pointer into MSP (`msr MSP, r1`) +and branches to the reset handler (`bx r2`); `_reset_handler` then parks core 1, +copies `.data`, zeroes `.bss`, runs `_init`, and calls `main`. + +#### A.2.4 Relocation: the same layout, base shifted + +The app is the same image linked at `0x10020000`, so every startup symbol shifts +by `0x20000`: + +| Symbol | Bootloader | App | +| ---------------- | ------------ | ------------ | +| `__VECTOR_TABLE` | `0x10000000` | `0x10020000` | +| `__vectors_end` | `0x10000110` | `0x10020110` | +| `_entry_point` | `0x1000014c` | `0x1002014c` | +| `_reset_handler` | `0x1000015c` | `0x1002015c` | +| `main` | `0x10000234` | `0x10020234` | + +`main` is at offset `0x234` in both. Relocation changed the base only, which is +why the bootloader can jump to an app linked at a different address. + +#### A.2.5 Reproduce and verify + +With the probe attached and `./debug-server.sh` running, this command proves +every claim above. The output is verbatim from this lab's board: + +``` +$ ~/.pico-sdk/toolchain/14_2_Rel1/bin/arm-none-eabi-gdb -batch \ + -ex "file 0x0026a_custom-bootloader/build/0x0026a_bootloader.elf" \ + -ex "target extended-remote :3333" \ + -ex "source pico-gdb-memory.gdb" \ + -ex "monitor halt" \ + -ex "x/16wx 0x10000000" \ + -ex "info symbol *(unsigned int*)0x10000004" \ + -ex "info address main" \ + -ex "x/4wx 0x10020000" + +0x10000000 <__vectors>: 0x20082000 0x1000015d 0x1000011b 0x1000011d +0x10000010 <__vectors+16>: 0x10000111 0x10000111 0x10000111 0x10000111 +... +_reset_handler + 1 in section .text +Symbol "main" is a function at address 0x10000234. +0x10020000: 0x20082000 0x1002015d 0x1002011b 0x1002011d +``` + +What each line proves: +- `0x10000000` = `0x20082000` then `0x1000015d`: the image begins with + `[initial SP][reset handler]`. +- `info symbol` resolves the reset word to `_reset_handler`. +- `info address main` = `0x10000234`, 564 bytes in. +- `0x10020000` repeats the same shape shifted by `0x20000`; the app's `main` is + `0x10020234`. +- Attaching mid-run showed the PC at `0x100202cc`, inside the app region: the + bootloader had already handed off. + +#### A.2.6 Two gotchas + +- `0x234` is hex; `0x234` = 564 decimal. +- No boot2 blob: `__boot2_start__ == __boot2_end__` in both images, so the image + begins at the vector table (the RP2350 boot ROM handles flash setup). + + +### A.3 Static reconnaissance (before any disassembler) + +Never open Ghidra first. Two minutes of `file`/`strings`/`xxd` frames the whole +investigation: + +``` +$ file $W/0x0026a_bootloader.elf $W/0x0026a_bootloader.bin $W/0x0026a_app.bin +$ $PCT info -a $W/0x0026a_full.uf2 +$ arm-none-eabi-size $W/build/0x0026a_bootloader.elf $W/build/0x0026a_app.elf +$ shasum -a 256 $W/0x0026a_app.bin +$ strings -n 6 $W/0x0026a_app.bin | sort -u | head -40 +$ xxd -l 64 $W/manifest.bin +``` + +What each answers: + +- `file` says ARM little-endian, and `picotool info` names the family + (`rp2350-arm-s`) and the target - so you know the ISA and the load address. +- `arm-none-eabi-size` prints the ELF `text`/`data`/`bss` totals, and + `wc -c` on `0x0026a_app.bin` reports 21656 bytes = `0x5498`, which is exactly + `app_size` in the manifest. Two artifacts agree, so the flash map is + confirmed without a single line of source. +- `shasum` gives you a fingerprint to prove a re-signed image actually changed. +- `strings` shows `app banner: %s`, `%s` printf formats, and NUL-split + fragments. Note them as search anchors for Ghidra. +- `xxd manifest.bin` ends the "what is the format" question immediately: + +``` +00000000: 5746 4c42 0100 0000 0000 0210 9854 0000 WFLB.........T.. +00000010: ef04 1ec5 92f0 c567 27da 2651 d373 947b .......g'.&Q.s.{ +``` + +Decode it as five little-endian words plus a blob: + +| Offset | Bytes | Meaning | +| ------ | ---------------- | ---------------------------------------- | +| 0x00 | `57 46 4c 42` | magic `WFLB` (`0x424C4657` little-endian)| +| 0x04 | `01 00 00 00` | version 1 | +| 0x08 | `00 00 02 10` | app base `0x10020000` | +| 0x0C | `98 54 00 00` | app size `0x5498` (21656) | +| 0x10 | 16 bytes | `ef04...947b`, the AES-CMAC tag | +| 0x20 | `ff` x 4064 | erased sector padding | + +You have the manifest spec before opening a decompiler. `binwalk -E` (if +installed) confirms a low-entropy, uncompressed image - none of it is packed. + +### A.4 Ghidra on the bootloader (the easy path) + +1. **File > New Project** (non-shared), then **File > Import File** and pick + `$W/build/0x0026a_bootloader.elf`. +2. Accept the detected language `ARM:LE:32:v8` (Cortex-M33). Click **Analyze** + and take the defaults. +3. In **Symbol Tree > Functions**, confirm the boot sequence by address: + +| Function | Address | Reads as | +| ------------------ | ------------ | ----------------------------------------------- | +| `main` | `0x10000234` | five `BL`s, no logic of its own | +| `boot_init` | `0x10000278` | `stdio_init_all`, a wait, one `puts` | +| `manifest_read` | `0x100002c8` | `memcpy` of 32 bytes from `0x1001F000` | +| `manifest_is_valid`| `0x100002fc` | two compares: magic and version | +| `verify_manifest` | `0x100003b0` | the 16-byte key push + CMAC + tag compare | +| `aes128_cmac` | `0x1000031c` | mbedtls `cipher_info_from_type` + `cipher_cmac` | +| `cmac_tags_equal` | `0x10000348` | constant-time 16-byte compare | +| `image_start` | `0x10000394` | VTOR / MSP / `bx` launch block | +| `boot_halt` | `0x10000294` | the `BOOT FAILED` dead end | + +Double-click `verify_manifest`. The decompiler will show a stack copy of the +manifest and a call that hands `fw_key` to `aes128_cmac`, then a 16-byte +compare with the tag. That is the entire security model on one screen. + +### A.5 Recovering the key from the image (static) + +Inside `verify_manifest`, note the address pushed as the CMAC key. Follow it in +the **Data** panel to `0x10006064`, or just ask the binary: + +``` +$ arm-none-eabi-nm -n $W/build/0x0026a_bootloader.elf | grep fw_key +10006064 r fw_key +``` + +Rename the data (`L`) to `fw_key`, then read it as bytes in Ghidra - it is +`49 72 6f 6e 4e 65 74 42 6f 6f 74 4b 65 79 21 21`, which is ASCII +`IronNetBootKey!!`. That is the AES-128-CMAC key. There was no cryptography to +break: the key was in `.rodata` the whole time. + +Cross-check the finding without the board. The signer implements AES and CMAC +in pure Python, so the four official RFC 4493 vectors are a self-test you can +read and reproduce (the `Key =`/`Tag =` block in Part 3 is your checklist). +If your recovered key reproduces the shipped tag, you have proven both the key +and the algorithm: + +``` +$ python3 $W/tools/sign_firmware.py $W/0x0026a_app.bin \ + --verify $W/manifest.bin \ + --key 49726f6e4e6574426f6f744b65792121 +stored : ef041ec592f0c56727da2651d373947b +computed : ef041ec592f0c56727da2651d373947b +result : MATCH +``` + +### A.6 Ghidra on the application (the AES gate) + +Repeat A.4 with `$W/build/0x0026a_app.elf`. The app is the richer target. + +| Symbol | Address | Observations | +| --------------------- | ------------ | ----------------------------------------------- | +| `_reset_handler` | `0x1002015c` | first code; trusts the SP/VTOR the bootloader set| +| `main` | `0x10020234` | thin orchestrator | +| `ir_init` / `ir_getkey`| `0x1002027c` / `0x100202a4` | NEC receiver setup | +| `led_handle_ir` | `0x100204d8` | flattened struct logic; compares `0xc`, `0x18`, `0x5e` | +| `secret_print_banner` | `0x10020568` | four mbedtls calls; the banner decrypt | + +Open `secret_print_banner`. The decompiler names the imported calls directly: + +``` +mbedtls_aes_init(ctx) +mbedtls_aes_setkey_dec(ctx, key, 128) +mbedtls_aes_crypt_cbc(ctx, MBEDTLS_AES_DECRYPT, 32, iv, ct, ct) +mbedtls_aes_free(ctx) +``` + +The red data references give you every constant you need: + +| Data | Address (VA) | Bytes | ASCII | +| ----------------- | ------------ | ------------------------------------------------- | ----------------- | +| banner format | `0x10024d68` | `61 70 70 20 62 61 6e 6e 65 72 3a 20 25 73 0a 00` | `app banner: %s\n`| +| banner ciphertext | `0x10024d78` | `ba ec 4a 19 ... 7b b2 e7 6e` (32 bytes) | (binary) | +| banner IV | `0x10024d9c` | `41 70 70 53...31 32 33 34 35` | `AppSecretIV12345`| +| banner key | `0x10024e6c` | `49 72 6f 6e...21 21` | `IronNetBootKey!!`| + +Note the last row: the AES key is identical to the CMAC key. One compromise, the +whole chain falls - the classic "one key, two jobs" smell. + +### A.7 Decrypt on the host + +Ciphertext, IV, and key are now just three hex strings. OpenSSL finishes the +job; you never needed the source: + +``` +$ printf 'baec4a1925861bb92dfd9f13f79b3e80cf12b698db9165be8fd7c3477bb2e76e' \ + | xxd -r -p \ + | openssl enc -d -aes-128-cbc \ + -K 49726f6e4e6574426f6f744b65792121 \ + -iv 41707053656372657449563132333435 -nopad +SECRET: IR LINK SECURED ONLINE +``` + +Breaking the application took: import, click, copy three hex constants, run one +command. AES was never attacked - the key schedule was simply lying in `.rodata`. + +### A.8 Forging an image the bootloader accepts + +The recovery is only interesting if you can act on it. Because you own the key, +you can sign anything: + +1. Tamper the app (any byte, e.g. flip one in `0x0026a_app.bin`). +2. Re-sign the tampered image, producing a new manifest, with the recovered + key: + +``` +$ python3 $W/tools/sign_firmware.py $W/0x0026a_app.bin \ + --out $W/manifest.bin \ + --key 49726f6e4e6574426f6f744b65792121 \ + --app-base 0x10020000 +$ python3 $W/tools/sign_firmware.py $W/0x0026a_app.bin \ + --verify $W/manifest.bin --key 49726f6e4e6574426f6f744b65792121 +``` + +3. Flash the tampered app at `0x10020000` and the new manifest at `0x1001F000` + (Part 11). The bootloader computes the same CMAC over the tampered bytes, + the tag matches, and the rogue image runs. That is the whole "secure boot" + defeated with a key you read out of the image it was protecting. + +### A.9 Live GDB: watching the boot gate + +Now do the same hunt at runtime. The repo ships `debug-server.sh` (owns the +Probe, leaves the target running on `127.0.0.1:3333`) and `pico-gdb-memory.gdb` +(confines GDB reads to valid flash/RAM so register previews cannot fault SWD). + +Terminal 1: + +``` +$ ./debug-server.sh +``` + +Terminal 2: + +``` +$ $GDB $W/build/0x0026a_bootloader.elf +(gdb) target extended-remote :3333 +(gdb) source pico-gdb-memory.gdb +(gdb) monitor halt +``` + +Read the manifest straight out of flash and confirm the A.3 decode at runtime: + +``` +(gdb) x/4wx 0x1001F000 +0x1001f000: 0x424c4657 0x00000001 0x10020000 0x00005498 +(gdb) x/16bx 0x1001F010 +0x1001f010: 0xef 0x04 0x1e 0xc5 0x92 0xf0 0xc5 0x67 ... +``` + +Break on the gate, reset, and continue: + +``` +(gdb) hbreak *0x100003b0 +(gdb) monitor reset halt +(gdb) continue +``` + +When it stops, dump the key argument the CMAC call will receive - the live +version of A.5: + +``` +(gdb) x/16bx 0x10006064 +0x10060064: 0x49 0x72 0x6f 0x6e 0x4e 0x65 0x74 0x42 ... +``` + +`0x49 0x72 0x6f 0x6e ...` is `IronNetBootKey!!` again. Then watch the verdict: + +``` +(gdb) finish +(gdb) info registers r0 +``` + +`r0 == 1` means the tags matched and `boot_launch` is next. Set a breakpoint at +the launch tail and single-step the handoff: + +``` +(gdb) break *0x100003ae +(gdb) continue +(gdb) info registers r3 +(gdb) x/2wx 0x10020000 +(gdb) stepi +``` + +`r3` equals `vectors[1]`, and after `stepi` the PC is in the app's +`_reset_handler` with SP already set to `0x20082000`. The gate is behind you. + +### A.10 Live GDB: the application's AES + +Reattach to the app ELF (the core is already running it, so no reset is +strictly needed, but a reset proves the chain end to end): + +``` +(gdb) file $W/build/0x0026a_app.elf +(gdb) hbreak *0x10020568 +(gdb) monitor reset halt +(gdb) continue +``` + +You are now at `secret_print_banner`, before the banner exists in RAM. Disassemble +and read the three constants the same way Ghidra showed them: + +``` +(gdb) disassemble 0x10020568,+120 +(gdb) x/16bx 0x10024e6c # banner key -> IronNetBootKey!! +(gdb) x/16bx 0x10024d9c # banner IV -> AppSecretIV12345 +(gdb) x/32bx 0x10024d78 # banner ciphertext +``` + +Single-step the four mbedtls calls and confirm the argument registers line up +with A.6 (`r0 = ctx`, `r3 = iv`, and the ciphertext pointer on the stack). By +the time `secret_print_banner` returns, the plaintext `SECRET: IR LINK SECURED +ONLINE` has been printed - the same bytes OpenSSL produced on the host, now +observed live on the silicon. + +### A.11 The stripped binary (no symbols, the real case) + +Everything above leaned on symbols. A shipped image usually has none. Delete the +app from the Ghidra project and import `$W/0x0026a_app.bin` with **Language = +ARM:LE:32:v8** and **Image base = 0x10020000**. Now reconstruct the anchors you +already know from the easy pass: + +- **Strings first.** `Ctrl+Shift+S`, search `app banner: %s`. Its only xref is + the second half of `secret_print_banner` - you have found the function blind. +- **Then its neighbours.** The IV `AppSecretIV12345` sits 0x24 bytes later in + `.rodata`; the key `IronNetBootKey!!` sits at `0x10024e6c`. Search the raw + bytes (`Search > For Bytes`, `41 70 70 53 ...`) to jump straight to them. +- **Then the calls.** The `BL` targets into the mbedtls block + (`mbedtls_aes_setkey_dec` at `0x10024088`, `mbedtls_aes_crypt_cbc` at + `0x10024994`) confirm the four-call shape even without names. +- **Then the manifest magic.** In the bootloader `.bin`, search for + `57 46 4c 42` (`WFLB`); its only compare is `manifest_is_valid`, which anchors + the whole boot sequence the same way `app banner: %s` anchored the app. + +Renaming data (`L`), applying types, and setting a couple of function +signatures rebuilds the module structure from the raw blob - no debugger, no +source, no strings beyond a printf format. + +### A.12 Cheat sheet + +| Task | Command / address | +| ----------------------------- | ------------------------------------------------------------ | +| Start GDB server | `./debug-server.sh` then `target extended-remote :3333` | +| Confine memory reads | `source pico-gdb-memory.gdb` | +| Stop / reset target | `monitor halt` / `monitor reset halt` | +| Break on the gate | `hbreak *0x100003b0` (`verify_manifest`) | +| Manifest in flash | `x/4wx 0x1001F000` | +| CMAC key in flash | `x/16bx 0x10006064` -> `IronNetBootKey!!` | +| App banner gate | `hbreak *0x10020568` (`secret_print_banner`) | +| Banner key / IV / ciphertext | `0x10024e6c` / `0x10024d9c` / `0x10024d78` | +| Re-sign an image | `python3 tools/sign_firmware.py --out manifest.bin \` | +| | ` --key --app-base 0x10020000` | +| Verify a manifest | `python3 tools/sign_firmware.py --verify manifest.bin` | + +The lesson of the appendix is the lesson of the lab: the adversary never breaks +AES. They read the manifest spec from a sector, lift the key from `.rodata`, +and re-sign. Design your next boot chain so that the key is not in the image +you are trusting it to protect. \ No newline at end of file diff --git a/WEEK11/WEEK11a.pdf b/WEEK11/WEEK11a.pdf new file mode 100644 index 0000000..f4fbbb1 Binary files /dev/null and b/WEEK11/WEEK11a.pdf differ diff --git a/WEEK11/slides/WEEK11-IMG00.svg b/WEEK11/slides/WEEK11-IMG00.svg new file mode 100644 index 0000000..0469f90 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG00.svg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + 4F 70 65 6E 4F 43 44 + 10 00 02 34 08 B5 01 + 47 44 42 20 52 45 56 + 20 08 20 00 FF AA 00 + 52 50 32 33 35 30 00 + 0A 0A 0F 12 12 1A 1A + 41 52 4D 76 38 2D 4D + 00 FF 41 00 D4 FF 88 + 47 48 49 44 52 41 00 + FF 00 40 C0 C0 C0 00 + + + + + + + + + + + + +Embedded Systems +Reverse Engineering + + + + + +// WEEK 11 + + +Structures and Functions in +Embedded Systems: Debugging and Hacking +w/ IR Remote Control & NEC Protocol + + + + + +George Mason University + + + +RP2350 // ARM Cortex-M33 + diff --git a/WEEK11/slides/WEEK11-IMG01.svg b/WEEK11/slides/WEEK11-IMG01.svg new file mode 100644 index 0000000..6701ba4 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG01.svg @@ -0,0 +1,70 @@ + + + + +C Structures (Structs) +Grouping Related Data Together + + + +What is a Struct? +A user-defined type that groups +related variables under one name +Like a form with multiple fields +-- each field holds different data + + + +Struct Definition + +typedef struct { +uint8_t led1_pin; +uint8_t led2_pin; +uint8_t led3_pin; +bool led1_state; +bool led2_state; +bool led3_state; +} simple_led_ctrl_t; + + + +Why Use Structs? +1. +Organization +Related data stays together +2. +Readability +Code easier to understand +3. +Scalability +Easy to add more features +4. +Pass to Functions + + + +simple_led_ctrl_t leds + +pin1: 16 + +pin2: 17 + +pin3: 18 + +state1: 0 + +state2: 0 + +state3: 0 + diff --git a/WEEK11/slides/WEEK11-IMG02.svg b/WEEK11/slides/WEEK11-IMG02.svg new file mode 100644 index 0000000..6157da6 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG02.svg @@ -0,0 +1,85 @@ + + + + +Struct Memory Layout +How Structs Are Stored and Accessed + + + +Memory Layout (6 bytes total) + +Address +Member +Size +Value + + +0x20000000 +led1_pin +1 byte +16 (0x10) + +0x20000001 +led2_pin +1 byte +17 (0x11) + +0x20000002 +led3_pin +1 byte +18 (0x12) + +0x20000003 +led1_state +1 byte +0 (false) + +0x20000004 +led2_state +1 byte +0 (false) + +0x20000005 +led3_state +1 byte +0 (false) + + + +Dot Operator ( . ) +Use with struct variable + +leds.led1_pin = 16; +leds.led1_state = true; + + + +Arrow Operator ( -> ) +Use with pointer to struct + +ptr->led1_pin = 16; +// same as (*ptr).led1_pin + + + +Designated Initializers + +simple_led_ctrl_t leds = { +.led1_pin = 16, .led2_pin = 17, .led3_pin = 18 +}; +Clear which value goes +to which member +Order doesn't matter + diff --git a/WEEK11/slides/WEEK11-IMG03.svg b/WEEK11/slides/WEEK11-IMG03.svg new file mode 100644 index 0000000..c44ccd0 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG03.svg @@ -0,0 +1,88 @@ + + + + +NEC IR Protocol +Infrared Remote Control Communication + + + +How IR Works +Remote sends invisible light pulses +IR receiver on GPIO 5 reads signal +IR LED flashes in specific patterns +Each pattern = different button + + + +NEC Protocol Frame (32 bits) + + +Leader + +Address + +Addr Inv + +Command + +Cmd Inv + +Stop + +9ms+4.5ms +8-bit +8-bit check +8-bit +8-bit check + +Leader says "attention!", address identifies device, command is the button pressed + + + +NEC Command Codes + +Button +NEC Code +LED + + +1 +0x0C +Red (GP16) + +2 +0x18 +Green (GP17) + +3 +0x5E +Yellow (GP18) + + + +Hardware Wiring +GPIO 5 +IR Receiver (VS1838B) +GPIO 16 +Red LED + 220 ohm +GPIO 17 +Green LED + 220 ohm +GPIO 18 +Yellow LED + 220 ohm + + + +Projects: 0x0023_structures and 0x0026_functions + diff --git a/WEEK11/slides/WEEK11-IMG04.svg b/WEEK11/slides/WEEK11-IMG04.svg new file mode 100644 index 0000000..719946b --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG04.svg @@ -0,0 +1,91 @@ + + + + +Functions in C +Reusable Blocks of Code + + + +Anatomy of a Function + +int ir_to_led_number(int ir_command) { + +^^^ +^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^ +ret +function name +parameter + + +if (ir_command == 0x0C) return 1; +// body + return value + + + +Function Types + +Type +Example + + +No params, no ret +leds_all_off() + +Params, no return +blink_led(..) + +No params, return +ir_getkey() + +Params + return +ir_to_led_num() + +Struct pointer +get_led_pin() + + + +Key Functions + +ir_to_led_number(cmd) +Maps NEC code to LED 1/2/3 + +get_led_pin(leds, num) +Returns GPIO pin for LED + +blink_led(pin, cnt, ms) +Blinks LED cnt times + + + +Function Call Chain + +main() +--> +process_ir_led_command() + +1. leds_all_off() +Turn all LEDs off + +2. ir_to_led_number() +Map NEC to LED + +3. get_led_pin() +Get GPIO pin + +4. blink_led() +Blink + stay on + diff --git a/WEEK11/slides/WEEK11-IMG05.svg b/WEEK11/slides/WEEK11-IMG05.svg new file mode 100644 index 0000000..9058acc --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG05.svg @@ -0,0 +1,66 @@ + + + + +Struct Pointers in Functions +Passing Data Efficiently + + + +Why Pass by Pointer? +Efficient +4 bytes (address) not 6 +Modifiable +Function can change original +Standard +Embedded systems practice + + + +Arrow Operator +leds->led1_pin +Same as (*leds).led1_pin +Use -> when leds is a pointer + + + +leds_all_off() + +void leds_all_off( +simple_led_ctrl_t *leds) { +gpio_put(leds->led1_pin, 0); +gpio_put(leds->led2_pin, 0); + + + +blink_led() + +void blink_led(uint8_t pin, +uint8_t count, uint32_t ms){ +gpio_put(pin, true); +sleep_ms(ms); + + + +process_ir_led_command() -- Main Command Processor + +int process_ir_led_command(int cmd, +simple_led_ctrl_t *leds, uint8_t blink_count) { +leds_all_off(leds); +// turn all off first +int num = ir_to_led_number(cmd); +// map NEC to LED +blink_led(get_led_pin(leds, num), +// blink then stay on + diff --git a/WEEK11/slides/WEEK11-IMG06.svg b/WEEK11/slides/WEEK11-IMG06.svg new file mode 100644 index 0000000..84c7359 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG06.svg @@ -0,0 +1,57 @@ + + + + +Structures Source Code +0x0023_structures.c + + + +Full Source + + +#include <stdio.h> +#include "pico/stdlib.h" +#include "ir.h" + +typedef struct { +uint8_t led1_pin, led2_pin, led3_pin; +bool led1_state, led2_state, led3_state; +} simple_led_ctrl_t; + +int main(void) { +stdio_init_all(); +simple_led_ctrl_t leds = { +.led1_pin=16, .led2_pin=17, .led3_pin=18 +}; + +gpio_init(leds.led1_pin); +// init 16, 17, 18 +ir_init(5); +// IR on GPIO 5 +while (true) { +// main loop + + + +Main Loop Flow +ir_getkey() +--> +check NEC code +--> +set state +--> +gpio_put() +0x0C=LED1(red) 0x18=LED2(green) 0x5E=LED3(yellow) + diff --git a/WEEK11/slides/WEEK11-IMG07.svg b/WEEK11/slides/WEEK11-IMG07.svg new file mode 100644 index 0000000..514e9f0 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG07.svg @@ -0,0 +1,73 @@ + + + + +Struct Flattening +How Compilers Transform Structs + + + +C Code (High Level) + +gpio_init(leds.led1_pin); +// leds.led1_pin = 16 +gpio_init(leds.led2_pin); +// leds.led2_pin = 17 + + + +Assembly (Flattened) + +movs r0, #0x10 +// 16 +bl gpio_init +movs r0, #0x11 +// 17 +bl gpio_init + + + +The Key Insight +Struct abstraction DISAPPEARS +at assembly level +You see individual values (16, 17, 18) not struct names + + + +Struct Member Mapping + +Assembly +Struct Member +Physical +NEC Code + + +0x10 (16) +led1_pin +Red LED +0x0C + +0x11 (17) +led2_pin +Green LED +0x18 + +0x12 (18) +led3_pin +Yellow LED +0x5E + +Sequential values (16,17,18) reveal the struct pattern +Recognize patterns to reconstruct original structs in Ghidra + diff --git a/WEEK11/slides/WEEK11-IMG08.svg b/WEEK11/slides/WEEK11-IMG08.svg new file mode 100644 index 0000000..8eb24ae --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG08.svg @@ -0,0 +1,77 @@ + + + + +Hacking Structures +Swapping GPIO Pin Assignments + + + +Swap LED 1 and LED 2 +Find gpio_init values: +0x10 (16) +--> +0x11 (17) +0x11 (17) +--> +0x10 (16) +Swap the two byte values + + + +Result After Hack + +Before: +Btn 1 --> GPIO 16 --> Red +Btn 2 --> GPIO 17 --> Green + +After: +SWAPPED! + + + +Before (Normal) +Btn 1 (0x0C) --> GPIO 16 +Red +Btn 2 (0x18) --> GPIO 17 +Green +Log and LED match correctly + + +After (Hacked) +Btn 1 (0x0C) --> GPIO 17 +Green! +Btn 2 (0x18) --> GPIO 16 +Red! +Log says RED but GREEN lights + + + +Log Desynchronization + +Terminal Log: +NEC command: 0x0C +(expects Red) + +Physical LED: +GREEN LED on +MISMATCH! + +Operator sees correct logs but WRONG behavior + + + +Stuxnet: +False "normal" data to operators, equipment destroyed + diff --git a/WEEK11/slides/WEEK11-IMG09.svg b/WEEK11/slides/WEEK11-IMG09.svg new file mode 100644 index 0000000..e6ae7a2 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG09.svg @@ -0,0 +1,73 @@ + + + + +.ELF vs .BIN Analysis +Ghidra Analysis of 0x0026_functions + + + +.ELF vs .BIN Comparison + +Feature +.BIN File +.ELF File + + +Symbols +None +Function names + +Sections +Raw bytes only +.text .data .rodata + +Debug info +None +May include debug + +Use case +Flash to device +Analysis + debug + + + +Importing .BIN +Manual setup required: +ARM Cortex 32 little endian +Block: .text +Base: 10000000 +No function names + + +Importing .ELF +Auto-detected by Ghidra: +ARM format recognized +Sections auto-loaded +Symbol tree populated +Named functions visible + + + +Important Rule +Analyze the .ELF +for symbol information +Patch the .BIN +for flashing + + + +Export Workflow +Patch .bin in Ghidra --> uf2conv.py --> flash to Pico 2 + diff --git a/WEEK11/slides/WEEK11-IMG10.svg b/WEEK11/slides/WEEK11-IMG10.svg new file mode 100644 index 0000000..3906d05 --- /dev/null +++ b/WEEK11/slides/WEEK11-IMG10.svg @@ -0,0 +1,85 @@ + + + + +Structs & IR Protocol +Structs, Functions, IR, and Hacking + + + +C Structures +Group related data together +Dot (.) for variables +Arrow (->) for pointers +Designated init: .pin = 16 + + + +NEC IR Protocol +32-bit frame: addr + cmd +0x0C +Button 1 +0x18 +Button 2 +0x5E +Button 3 + + + +Functions +Reusable blocks, one job each +ir_to_led_number() +get_led_pin() / blink_led() +process_ir_led_command() + + + +Assembly Flattening +Structs vanish in assembly +Only see values: 0x10 0x11 0x12 +Pattern recognition is key +.ELF has symbols, .BIN doesn't + + + +Key Values +0x10000234 +main() +GPIO 5 +IR receiver +GPIO 16/17/18 +Red/Green/Yellow + + + +Hacking Techniques +GPIO swap +0x10 <--> 0x11 +Log desync +Logs lie! +Stuxnet +Same concept + + + +Projects +0x0023_structures +0x0026_functions + + + +Key Takeaway +Patch bytes, mislead logs +hardware does what YOU say + diff --git a/datasheets/DDI0553B_y_armv8m_arm.pdf b/datasheets/DDI0553B_y_armv8m_arm.pdf new file mode 100644 index 0000000..00f7e8d Binary files /dev/null and b/datasheets/DDI0553B_y_armv8m_arm.pdf differ diff --git a/datasheets/aapcs32.pdf b/datasheets/aapcs32.pdf new file mode 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0000000..454f801 --- /dev/null +++ b/debug-server.ps1 @@ -0,0 +1,286 @@ +<# +.SYNOPSIS + Start OpenOCD as a live GDB server for the RP2350 via the Pico Debug Probe. + +.DESCRIPTION + Starts OpenOCD in the foreground as a long-running GDB server. It exposes + rp2350.dap.core0 on 127.0.0.1:3333 and leaves the core RUNNING, so that a + debugger (Binary Ninja, or plain GDB) can attach to a target that is already + executing and therefore has sane registers. + + This script is deliberately NOT flash.ps1. flash.ps1 programs flash and + exits; this one claims the probe and stays up so you can single-step, read + memory, and set breakpoints. Do not run both at once -- exactly one process + may own the debug probe. + + The script ends with "reset run" rather than OpenOCD's default halt. This is + the single most important line in the file; see "Why reset run" below. + +.PARAMETER OCD + Optional. Directory containing openocd.exe AND its scripts\ directory. + Overrides the PICO_OPENOCD environment variable. + +.ENVIRONMENT + PICO_OPENOCD Directory containing openocd.exe AND its scripts\ directory. + Default: $env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev + The path is used for BOTH the executable and the -s scripts + argument. This must be an OpenOCD build matching your machine + architecture (x64). + ADAPTER_SPEED SWD clock in kHz. Default: 24000. + This is a read-mostly debug session, so a fast clock is fine + and makes stepping noticeably smoother. Drop it (10000 or + lower) if the link is flaky or you are using long dupont + wires instead of the probe's own connector. + USE_CORE Which cores to expose to the client. Default: 0 (core0 only). + Accepted values: + 0 core0 only <- use this with Binary Ninja + 1 core1 only <- rarely useful + SMP both cores as hwthreads <- see "Why USE_CORE=0" + Do not change this to SMP when driving Binary Ninja. The + explanation below is the whole reason this default is 0. + BP_ADDR OPTIONAL address to halt at during the startup run, as 0x + prefixed hex, e.g. 0x10000234 for main. Unset by default, + which is the normal "attach to a running target" behaviour. + Arms a 2-byte hardware execute breakpoint just before the + final "reset run", so the core runs from the vector table + and stops there on its own, with no client attached yet. + See "Why BP_ADDR is one-shot" below for the important + limitation. Arming a length of 2 is mandatory: the Cortex-M33 + comparators are halfword-based and reject anything else. + +.NOTES + Requirements: + * Pico Debug Probe (or any CMSIS-DAP / SWD adapter) connected to the target. + * OpenOCD with the rp2350 target script installed. See PICO_OPENOCD. + * Exactly one process may own the debug probe. + * A firmware image already programmed into flash (use flash.ps1 first). + * The Debug Probe must use the WinUSB driver. If OpenOCD reports + "unable to open CMSIS-DAP device", install it with Zadig + (https://zadig.akeo.ie/), selecting "Debug Probe (CMSIS-DAP)" -> WinUSB. + + Why USE_CORE=0 (core1 must be hidden from the client) + The RP2350 has two Cortex-M33 cores. Core1 does not start on its own: + nothing in a Pico SDK application releases it from reset unless the program + explicitly does so. If you expose it anyway (USE_CORE=SMP), its registers + read back as meaningless reset defaults: + + core1: pc 0x000000ec sp 0xf0000000 xpsr 0x09000000 lr 0x00000147 + core0: pc 0x1000320c sp 0x20081f38 xpsr 0xa9000000 lr 0x100030ab + + Binary Ninja's register widget renders a memory preview for every register, + which means it treats each register value as an ADDRESS and reads it. The + core1 values above are not real addresses. Each read data-aborts, and + OpenOCD responds by tearing down and re-establishing the SWD debug port, + logging a pair of lines per fault: + + Error: Failed to read memory at 0xf0000000 + Info : SWD DPIDR 0x4c013477 + + That becomes a self-sustaining loop of roughly 450 fault-and-recover cycles + every two seconds, which makes the session unusable. It looks exactly like a + broken debugger or a broken firmware. It is neither: it is a configuration + mismatch, and hiding core1 removes it completely. + + Note on Core 0 register previews (pico-gdb-memory.gdb): + Even with USE_CORE=0, whenever a Core 0 register holds an arbitrary integer + or unmapped value (e.g. 0x69000000), Binary Ninja's UI probes that address + for memory previews. In OpenOCD, failed SWD reads trigger the same SWD DPIDR + reconnect behavior. Source "pico-gdb-memory.gdb" in Binary Ninja's Debugger + Console to restrict GDB to valid Flash and SRAM, filtering invalid reads locally. + + Why reset run (the target must be released, not halted) + On RP2350, halting during reset stops the core at the boot ROM stub BEFORE + the stack pointer is loaded: + + xPSR: 0xf9000000 pc: 0x00000088 msp: 0xf0000000 lr: 0xffffffff + + Those values are garbage for every core, including core0. Attaching in that + window triggers the identical fault storm described above. Ending this + script with "reset run" means the core starts from the vector table and is + executing normally by the time you attach, so registers read back correct. + + Consequence for the client: ATTACH WHILE THE TARGET IS RUNNING. Do not + press Reset/Restart in Binary Ninja -- it performs reset-halt and puts you + back in the garbage window. If you must reset, send "reset run" over the + OpenOCD telnet port (4444) instead. See WEEK04\WEEK04-BN.md. + + Why BP_ADDR is one-shot (read this before relying on it) + A breakpoint armed here DOES fire during the startup "reset run" and halts + the core at your address, so the server comes up parked there and your + debugger can simply attach and look at it. That part works. + + What you do NOT get is a reusable breakpoint. As soon as any GDB client + connects, OpenOCD unconditionally flushes every breakpoint it is holding: + + Info : accepting 'gdb' connection on tcp/3333 + Debug: breakpoints.c:328 breakpoint_remove_all_internal(): + [rp2350.dap.core0] Delete all breakpoints + + So by the time Binary Ninja is up, the comparator is gone -- reading + 0xE0002000 shows zeros, not your address. Consequences: + + * The startup stop is single-use. You cannot Resume and re-catch the + same address. + * You cannot use BP_ADDR to stop in a loop that is already running, + because the core only passes that point once per reset. + * main (0x10000234) is a good BP_ADDR value precisely because it is + reached exactly once, right after reset. + + To arm anything further, or to re-arm main, do it from the OpenOCD command + port AFTER your debugger has connected -- the order is the whole trick: + + nc 127.0.0.1 4444 + > bp 0x1000023e 2 hw + > reset run + + Arming before the client connects does not work (flushed above), and in + plain GDB the equivalent "hbreak" is cleared by "detach" -- both were + verified by reading the FPB comparator registers back. + + Related Binary Ninja bug: Binary Ninja's own breakpoints cannot be used on + this target at all. It sends Z0,,1 -- a 1-byte packet -- and + OpenOCD answers "only breakpoints of two bytes length supported". Both + Toggle Breakpoint (F2) and Add Hardware Breakpoint (F3) fail, at every + address, and the dialog's Size field is disabled so there is no UI way + around it. gdb_breakpoint_override hard does not change this. Hence the + command-port workflow described above. + + Why the remaining OpenOCD flags are set + gdb_breakpoint_override hard + Force every client breakpoint onto the Cortex-M33 hardware comparators + (the RP2350 has 8 breakpoints and 4 watchpoints). Without this, a + client may try to write a BKPT instruction into flash at 0x10000000, + which is read-only XIP memory, and the write fails. + gdb_memory_map disable + Stops the client probing the entire 32 MiB flash map on connect. Pure + Raspberry Pi guidance for suppressing spurious "Failed to read memory" + reports during target discovery. + cortex_m reset_config sysresetreq + The Cortex-M33 in the RP2350 has no VECTRESET. Without this, OpenOCD + warns on every reset: + VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ + instead + NOTE: this MUST be the generic "cortex_m" command, not + "rp2350.dap.core1 cortex_m ...". With USE_CORE=0 the core1 target does + not exist, so a core1-scoped command aborts OpenOCD before "init" runs, + and the script exits silently having printed nothing useful. + adapter speed + See ADAPTER_SPEED above. + +.EXAMPLE + .\debug-server.ps1 + +.EXAMPLE + $env:ADAPTER_SPEED=10000; .\debug-server.ps1 + +.EXAMPLE + $env:PICO_OPENOCD="C:\openocd\bin"; .\debug-server.ps1 + +.EXAMPLE + $env:BP_ADDR="0x10000234"; .\debug-server.ps1 + Comes up halted at main (one-shot; see "Why BP_ADDR is one-shot"). + +.NOTES + Exit status: + * propagated from OpenOCD. A clean shutdown via Ctrl-C exits 0; an + OpenOCD configuration error exits non-zero. + + Related scripts: + flash.ps1 one-shot raw .bin programmer (exits when done) + + See also: + WEEK04\WEEK04-BN.md the full walkthrough this script belongs to +#> + +[CmdletBinding()] +param( + [Parameter()] + [string]$OCD +) + +Set-StrictMode -Version Latest +$ErrorActionPreference = 'Stop' + +# --- configuration --------------------------------------------------------- + +if (-not $OCD) { $OCD = $env:PICO_OPENOCD } +if (-not $OCD) { $OCD = "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev" } + +$SPEED = if ($env:ADAPTER_SPEED) { $env:ADAPTER_SPEED } else { "24000" } +$USE_CORE = if ($env:USE_CORE) { $env:USE_CORE } else { "0" } +$BP_ADDR = if ($env:BP_ADDR) { $env:BP_ADDR.Trim() } else { "" } + +if ($BP_ADDR -and $BP_ADDR -notmatch '^0x[0-9a-fA-F]+$') { + Write-Error "BP_ADDR must be 0x-prefixed hex, e.g. 0x10000234 (got '$BP_ADDR')" + exit 1 +} + +if (-not (Test-Path "$OCD\openocd.exe")) { + Write-Error "OpenOCD not found at $OCD\openocd.exe (set PICO_OPENOCD or -OCD to the directory containing openocd.exe)" + exit 1 +} + +# --- announce, so the operator can verify intent before the target is touched -- + +Write-Host "Starting OpenOCD GDB server on 127.0.0.1:3333 using $OCD\openocd.exe" +Write-Host "SWD adapter speed: $SPEED kHz" +Write-Host "Cores exposed to GDB (USE_CORE): $USE_CORE" +Write-Host "Target will be reset and released (reset run) - attach while it is running." + +if ($BP_ADDR) { + Write-Host "Startup breakpoint at $BP_ADDR (2-byte hardware execute, one-shot)." + Write-Host " It fires during this startup reset run. Any client connecting later" + Write-Host " causes OpenOCD to delete it, so arm further breakpoints on port 4444" + Write-Host " after attaching: bp 2 hw" +} + +# --- start ----------------------------------------------------------------- +# +# Order matters: USE_CORE must be set BEFORE -f target/rp2350.cfg is read, +# because the target script branches on it when creating the DAP targets. +# +# "reset run" is last so it happens after init and after the target is +# examined, releasing the core rather than halting it. See .NOTES for why. +# +# Any BP_ADDR breakpoint is inserted after "init" (the target must exist before +# a comparator can be programmed) but before "reset run" (so the core is already +# armed when it starts). The length must be 2: Cortex-M33 comparators reject +# other widths. + +$ocdArgs = @( + "-s", "$OCD\scripts", + "-f", "interface/cmsis-dap.cfg", + "-c", "set USE_CORE $USE_CORE", + "-f", "target/rp2350.cfg", + # Drop the hwthread RTOS the RP2350 target script attaches to core0. + # + # target/rp2350.cfg creates core0 with "-rtos hwthread", which registers a + # fake RTOS whose "current thread" is coreid+1 = 1. Binary Ninja single-steps + # with the GDB packet "vCont;s" and no thread id, i.e. thread 0. OpenOCD's + # gdb_server sees rtos->current_thread (1) != thread_id (0) and takes its + # "fake step" path, replying with a stop without ever stepping the core: + # + # gdb_server.c gdb_handle_vcont_packet(): fake step thread 0 + # + # The result is that Step Into / Step Over in Binary Ninja does nothing: the + # PC never moves. Clearing the RTOS removes the mismatch so the step is real. + # Harmless for single-core use, which is all this lab does (USE_CORE=0). + # The core's name differs between OpenOCD builds (rp2350.dap.core0 vs rp2350.cm0 + # in the Pico SDK's Windows build), so look it up instead of hard-coding it. + "-c", "[lindex [target names] 0] configure -rtos none", + "-c", "adapter speed $SPEED", + "-c", "gdb_memory_map disable", + "-c", "gdb_breakpoint_override hard", + "-c", "cortex_m reset_config sysresetreq", + "-c", "init" +) + +if ($BP_ADDR) { + $ocdArgs += @("-c", "bp $BP_ADDR 2 hw") +} + +$ocdArgs += @("-c", "reset run") + +& "$OCD\openocd.exe" @ocdArgs + +exit $LASTEXITCODE diff --git a/debug-server.sh b/debug-server.sh new file mode 100755 index 0000000..85dde19 --- /dev/null +++ b/debug-server.sh @@ -0,0 +1,266 @@ +#!/usr/bin/env bash +# +# debug-server.sh - start OpenOCD as a live GDB server for the RP2350 via the Pico Debug Probe. +# +# Synopsis: +# ./debug-server.sh +# +# Description: +# Starts OpenOCD in the foreground as a long-running GDB server. It exposes +# rp2350.dap.core0 on 127.0.0.1:3333 and leaves the core RUNNING, so that a +# debugger (Binary Ninja, or plain GDB) can attach to a target that is already +# executing and therefore has sane registers. +# +# This script is deliberately NOT flash.sh. flash.sh programs flash and exits; +# this one claims the probe and stays up so you can single-step, read memory, +# and set breakpoints. Do not run both at once -- exactly one process may own +# the debug probe. +# +# The script ends with "reset run" rather than OpenOCD's default halt. This is +# the single most important line in the file; see "Why reset run" below. +# +# Requirements: +# - Pico Debug Probe (or any CMSIS-DAP / SWD adapter) connected to the target. +# - OpenOCD with the rp2350 target script installed. See PICO_OPENOCD. +# - Exactly one process may own the debug probe. +# - A firmware image already programmed into flash (use flash.sh first). +# +# Environment variables: +# PICO_OPENOCD Directory containing the openocd binary AND its scripts/ +# directory. Default: $HOME/.pico-sdk/openocd/0.12.0+dev +# macOS note: an OpenOCD on PATH is frequently the x86_64 +# Homebrew build, which will not run under Rosetta on some +# setups and cannot talk to the ARM64 firmware tooling. The +# Pico SDK ships an arm64 build; point this at it explicitly. +# ADAPTER_SPEED SWD clock in kHz. Default: 24000. +# This is a read-mostly debug session, so a fast clock is fine +# and makes stepping noticeably smoother. Drop it (10000 or +# lower) if the link is flaky or you are using long dupont +# wires instead of the probe's own connector. +# BP_ADDR OPTIONAL address to halt at during the startup run, as 0x +# prefixed hex, e.g. 0x10000234 for main. Unset by default, +# which is the normal "attach to a running target" behavior. +# Arms a 2-byte hardware execute breakpoint just before the +# final "reset run", so the core runs from the vector table +# and stops there on its own, with no client attached yet. +# See "Why BP_ADDR is one-shot" below for the important +# limitation. Arming a length of 2 is mandatory: the Cortex-M33 +# comparators are halfword-based and reject anything else. +# USE_CORE Which cores to expose to the client. Default: 0 (core0 only). +# Accepted values: +# 0 core0 only <- use this with Binary Ninja +# 1 core1 only <- rarely useful +# SMP both cores as hwthreads <- see "Why USE_CORE=0" +# Do not change this to SMP when driving Binary Ninja. The +# explanation below is the whole reason this default is 0. +# +# Why USE_CORE=0 (core1 must be hidden from the client) +# The RP2350 has two Cortex-M33 cores. Core1 does not start on its own: nothing +# in a Pico SDK application releases it from reset unless the program +# explicitly does so. If you expose it anyway (USE_CORE=SMP), its registers +# read back as meaningless reset defaults: +# +# core1: pc 0x000000ec sp 0xf0000000 xpsr 0x09000000 lr 0x00000147 +# core0: pc 0x1000320c sp 0x20081f38 xpsr 0xa9000000 lr 0x100030ab +# +# Binary Ninja's register widget renders a memory preview for every register, +# which means it treats each register value as an ADDRESS and reads it. The +# core1 values above are not real addresses. Each read data-aborts, and +# OpenOCD responds by tearing down and re-establishing the SWD debug port, +# logging a pair of lines per fault: +# +# Error: Failed to read memory at 0xf0000000 +# Info : SWD DPIDR 0x4c013477 +# +# That becomes a self-sustaining loop of roughly 450 fault-and-recover cycles +# every two seconds, which makes the session unusable. It looks exactly like a +# broken debugger or a broken firmware. It is neither: it is a configuration +# mismatch, and hiding core1 removes it completely. +# +# Note on Core 0 register previews (pico-gdb-memory.gdb): +# Even with USE_CORE=0, whenever a Core 0 register holds an arbitrary integer +# or unmapped value (e.g. 0x69000000), Binary Ninja's UI probes that address +# for memory previews. In OpenOCD, failed SWD reads trigger the same SWD DPIDR +# reconnect behavior. Source "pico-gdb-memory.gdb" in Binary Ninja's Debugger +# Console to restrict GDB to valid Flash and SRAM, filtering invalid reads locally. +# +# Why reset run (the target must be released, not halted) +# On RP2350, halting during reset stops the core at the boot ROM stub BEFORE +# the stack pointer is loaded: +# +# xPSR: 0xf9000000 pc: 0x00000088 msp: 0xf0000000 lr: 0xffffffff +# +# Those values are garbage for every core, including core0. Attaching in that +# window triggers the identical fault storm described above. Ending this +# script with "reset run" means the core starts from the vector table and is +# executing normally by the time you attach, so registers read back correct. +# +# Consequence for the client: ATTACH WHILE THE TARGET IS RUNNING. Do not +# press Reset/Restart in Binary Ninja -- it performs reset-halt and puts you +# back in the garbage window. If you must reset, send "reset run" over the +# OpenOCD telnet port (4444) instead: +# +# nc 127.0.0.1 4444 then type: reset run +# +# ...or use debug-server.sh's restart instructions in WEEK04/WEEK04-BN.md. +# +# Why BP_ADDR is one-shot (read this before relying on it) +# A breakpoint armed here DOES fire during the startup "reset run" and halts +# the core at your address, so the server comes up parked there and your +# debugger can simply attach and look at it. That part works. +# +# What you do NOT get is a reusable breakpoint. As soon as any GDB client +# connects, OpenOCD unconditionally flushes every breakpoint it is holding: +# +# Info : accepting 'gdb' connection on tcp/3333 +# Debug: breakpoints.c:328 breakpoint_remove_all_internal(): +# [rp2350.dap.core0] Delete all breakpoints +# +# So by the time Binary Ninja is up, the comparator is gone -- reading +# 0xE0002000 shows zeros, not your address. Consequences: +# +# * The startup stop is single-use. You cannot Resume and re-catch the +# same address. +# * You cannot use BP_ADDR to stop in a loop that is already running, +# because the core only passes that point once per reset. +# * main (0x10000234) is a good BP_ADDR value precisely because it is +# reached exactly once, right after reset. +# +# To arm anything further, or to re-arm main, do it from the OpenOCD command +# port AFTER your debugger has connected -- the order is the whole trick: +# +# nc 127.0.0.1 4444 +# > bp 0x1000023e 2 hw +# > reset run +# +# Arming before the client connects does not work (flushed above), and in +# plain GDB the equivalent "hbreak" is cleared by "detach" -- both were +# verified by reading the FPB comparator registers back. +# +# Related Binary Ninja bug: Binary Ninja's own breakpoints cannot be used on +# this target at all. It sends Z0,,1 -- a 1-byte packet -- and OpenOCD +# answers "only breakpoints of two bytes length supported". Both Toggle +# Breakpoint (F2) and Add Hardware Breakpoint (F3) fail, at every address, and +# the dialog's Size field is disabled so there is no UI way around it. +# gdb_breakpoint_override hard does not change this. Hence the command-port +# workflow described above. +# +# Why the remaining OpenOCD flags are set +# gdb_breakpoint_override hard +# Force every client breakpoint onto the Cortex-M33 hardware comparators +# (the RP2350 has 8 breakpoints and 4 watchpoints). Without this, a client +# may try to write a BKPT instruction into flash at 0x10000000, which is +# read-only XIP memory, and the write fails. +# gdb_memory_map disable +# Stops the client probing the entire 32 MiB flash map on connect. Pure +# Raspberry Pi guidance for suppressing spurious "Failed to read memory" +# reports during target discovery. +# cortex_m reset_config sysresetreq +# The Cortex-M33 in the RP2350 has no VECTRESET. Without this, OpenOCD +# warns on every reset: +# VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ +# instead +# NOTE: this MUST be the generic "cortex_m" command, not +# "rp2350.dap.core1 cortex_m ...". With USE_CORE=0 the core1 target does +# not exist, so a core1-scoped command aborts OpenOCD before "init" runs, +# and the script exits silently having printed nothing useful. +# adapter speed +# See ADAPTER_SPEED above. +# +# Examples: +# ./debug-server.sh +# ADAPTER_SPEED=10000 ./debug-server.sh +# PICO_OPENOCD=/opt/homebrew/bin ./debug-server.sh +# BP_ADDR=0x10000234 ./debug-server.sh +# Comes up halted at main (one-shot; see "Why BP_ADDR is one-shot"). +# +# Exit status: +# * propagated from OpenOCD. A clean shutdown via Ctrl-C exits 0; an +# OpenOCD configuration error exits non-zero. +# +# Related scripts: +# flash.sh / flash.ps1 one-shot raw .bin programmer (exits when done) +# +# See also: +# WEEK04/WEEK04-BN.md the full walkthrough this script belongs to + +set -euo pipefail + +# --- configuration --------------------------------------------------------- + +OCD="${PICO_OPENOCD:-$HOME/.pico-sdk/openocd/0.12.0+dev}" +SPEED="${ADAPTER_SPEED:-24000}" +USE_CORE="${USE_CORE:-0}" +BP_ADDR="${BP_ADDR:-}" + +if [ -n "$BP_ADDR" ] && ! printf '%s' "$BP_ADDR" | grep -qiE '^0x[0-9a-f]+$'; then + echo "error: BP_ADDR must be 0x-prefixed hex, e.g. 0x10000234 (got '$BP_ADDR')" >&2 + exit 1 +fi + +if [ ! -x "$OCD/openocd" ]; then + echo "error: OpenOCD not found at $OCD/openocd" >&2 + echo " set PICO_OPENOCD=/path/to/openocd (the directory containing the openocd binary)" >&2 + exit 1 +fi + +# --- announce, so the operator can verify intent before the target is touched -- + +echo "Starting OpenOCD GDB server on 127.0.0.1:3333 using $OCD/openocd" +echo "SWD adapter speed: ${SPEED} kHz" +echo "Cores exposed to GDB (USE_CORE): ${USE_CORE}" +echo "Target will be reset and released (reset run) - attach while it is running." + +if [ -n "$BP_ADDR" ]; then + echo "Startup breakpoint at ${BP_ADDR} (2-byte hardware execute, one-shot)." + echo " It fires during this startup reset run. Any client connecting later" + echo " causes OpenOCD to delete it, so arm further breakpoints on port 4444" + echo " after attaching: bp 2 hw" +fi + +# --- start ----------------------------------------------------------------- +# +# Order matters: USE_CORE must be set BEFORE -f target/rp2350.cfg is read, +# because the target script branches on it when creating the DAP targets. +# +# "reset run" is last so it happens after init and after the target is +# examined, releasing the core rather than halting it. See the header for why. +# +# Any BP_ADDR breakpoint is inserted after "init" (the target must exist before +# a comparator can be programmed) but before "reset run" (so the core is already +# armed when it starts). The length must be 2: Cortex-M33 comparators reject +# other widths. + +ocd_args=( + -s "$OCD/scripts" + -f interface/cmsis-dap.cfg + -c "set USE_CORE ${USE_CORE}" + -f target/rp2350.cfg + # Drop the hwthread RTOS the RP2350 target script attaches to core0. + # + # target/rp2350.cfg creates core0 with "-rtos hwthread", which registers a + # fake RTOS whose "current thread" is coreid+1 = 1. Binary Ninja single-steps + # with the GDB packet "vCont;s" and no thread id, i.e. thread 0. OpenOCD's + # gdb_server sees rtos->current_thread (1) != thread_id (0) and takes its + # "fake step" path, replying with a stop without ever stepping the core: + # + # gdb_server.c gdb_handle_vcont_packet(): fake step thread 0 + # + # The result is that Step Into / Step Over in Binary Ninja does nothing: the + # PC never moves. Clearing the RTOS removes the mismatch so the step is real. + # Harmless for single-core use, which is all this lab does (USE_CORE=0). + -c "rp2350.dap.core0 configure -rtos none" + -c "adapter speed ${SPEED}" + -c "gdb_memory_map disable" + -c "gdb_breakpoint_override hard" + -c "cortex_m reset_config sysresetreq" + -c "init" +) + +if [ -n "$BP_ADDR" ]; then + ocd_args+=(-c "bp ${BP_ADDR} 2 hw") +fi + +ocd_args+=(-c "reset run") + +exec "$OCD/openocd" "${ocd_args[@]}" diff --git a/flash.ps1 b/flash.ps1 new file mode 100644 index 0000000..428f6ca --- /dev/null +++ b/flash.ps1 @@ -0,0 +1,132 @@ +<# +.SYNOPSIS + Program a raw .bin into RP2350 XIP flash via the Pico Debug Probe and OpenOCD. + +.DESCRIPTION + Writes a headerless raw binary to the RP2350's external XIP flash starting at + physical address 0x10000000, verifies the written bytes by reading them back, + then releases the core so the freshly programmed firmware runs. + + A raw .bin carries no address information, no entry point and no section + table, so the load address MUST be supplied out of band. On the RP2350 the + only correct value is 0x10000000: that is where the boot ROM jumps after + pulling the reset vector out of the on-chip XIP window. Flashing anywhere + else produces a board that enumerates over USB and then does nothing. + + The target must already be running the stock RP2350 bootrom (the default + state after power-up, or after any BOOTSEL + UF2 reflash). OpenOCD attaches + to the bootrom over SWD, halts it, programs flash, verifies, and resets. + + This is the macOS / Linux equivalent of flash.sh. The two must stay in + lockstep: same base address, same verify, same conservative SWD clock. + +.PARAMETER Bin + Mandatory. Path to the raw .bin image to program. + +.ENVIRONMENT + PICO_OPENOCD Directory containing openocd.exe AND its scripts\ directory. + Default: $env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev + The path is used for BOTH the executable and the -s scripts + argument. + ADAPTER_SPEED SWD clock in kHz. Default: 5000. + 5000 kHz is deliberately conservative. This is a write path, + not a read-only debug session, and a marginal USB cable or + long dupont run produces spurious verify failures at higher + clocks. Raise it (24000) for read-only work; if + "Error: target not halted" or verify mismatches appear, + lower it to 1000. + +.EXAMPLE + .\flash.ps1 -Bin WEEK04\0x0005_intro-to-variables\build\0x0005_intro-to-variables.bin + +.EXAMPLE + $env:ADAPTER_SPEED=1000; .\flash.ps1 -Bin build\hacked.bin + +.EXAMPLE + $env:PICO_OPENOCD="C:\openocd\bin"; .\flash.ps1 -Bin build\hacked.bin + +.NOTES + Requirements: + * Pico Debug Probe (or any CMSIS-DAP / SWD adapter) connected to the target. + * OpenOCD with the rp2350 target script installed. + * The Debug Probe must use the WinUSB driver. If OpenOCD reports + "unable to open CMSIS-DAP device", install it with Zadig + (https://zadig.akeo.ie/), selecting "Debug Probe (CMSIS-DAP)" -> WinUSB. + * Exactly one process may own the debug probe. Close any other OpenOCD, + GDB, or IDE debug session first. + + Exit status: + 0 flash written, verified, and core released + 1 input file missing or OpenOCD not found + * any other status is propagated from OpenOCD, so a failed verify or a + write error is visible to the caller rather than being swallowed. + + Related scripts: + debug-server.ps1 long-running GDB server for live debugging with + Binary Ninja. Use that instead of this script when you + need to single-step. + + See also: + WEEK04\WEEK04-BN.md the full walkthrough this script belongs to +#> + +[CmdletBinding()] +param( + [Parameter(Mandatory = $true)] + [ValidateNotNullOrEmpty()] + [string]$Bin +) + +Set-StrictMode -Version Latest +$ErrorActionPreference = 'Stop' + +# --- argument validation --------------------------------------------------- + +if (-not (Test-Path -PathType Leaf $Bin)) { + Write-Error "file not found: $Bin" + Write-Host "build it first: cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 ; cmake --build build" + exit 1 +} + +# --- toolchain resolution -------------------------------------------------- + +$OCD = if ($env:PICO_OPENOCD) { $env:PICO_OPENOCD } else { "$env:USERPROFILE\.pico-sdk\openocd\0.12.0+dev" } +if (-not (Test-Path "$OCD\openocd.exe")) { + Write-Error "OpenOCD not found at $OCD\openocd.exe (set PICO_OPENOCD to the directory containing openocd.exe)" + exit 1 +} + +$SPEED = if ($env:ADAPTER_SPEED) { $env:ADAPTER_SPEED } else { "5000" } + +# --- program --------------------------------------------------------------- + +# OpenOCD flag notes: +# -f interface/cmsis-dap.cfg the Pico Debug Probe is a CMSIS-DAP v1 device +# -f target/rp2350.cfg RP2350 dual Cortex-M33 + RP2350B0-style DAP; +# sets USE_CORE=SMP by default, which is fine here +# because we never hand uninitialised core1 +# registers to a debugger. For live debugging use +# debug-server.ps1, which forces USE_CORE=0. +# -c "program BIN 0x10000000 verify reset exit" +# program the write +# 0x10000000 base address (see .DESCRIPTION) +# verify read back and compare every byte; a mismatch aborts +# reset reset the core so the new image starts at its vectors +# exit release the probe and return to the shell +# +# The adapter speed is deliberately lower here than in debug-server.ps1; see +# ADAPTER_SPEED in .ENVIRONMENT. +Write-Host "Flashing $Bin -> 0x10000000 using $OCD\openocd.exe (SWD $SPEED kHz)" + +# OpenOCD parses -c strings as Tcl, which eats backslashes ("\build" -> backspace+"uild"). +# Hand it an absolute path with forward slashes, braced so spaces survive. +$BinTcl = (Resolve-Path $Bin).Path -replace '\\', '/' + +& "$OCD\openocd.exe" ` + -s "$OCD\scripts" ` + -f interface/cmsis-dap.cfg ` + -f target/rp2350.cfg ` + -c "adapter speed $SPEED" ` + -c "program {$BinTcl} 0x10000000 verify reset exit" + +exit $LASTEXITCODE diff --git a/flash.sh b/flash.sh new file mode 100755 index 0000000..12a5d17 --- /dev/null +++ b/flash.sh @@ -0,0 +1,111 @@ +#!/usr/bin/env bash +# +# flash.sh - program a raw .bin into RP2350 XIP flash via the Pico Debug Probe + OpenOCD. +# +# Synopsis: +# ./flash.sh +# +# Description: +# Writes a headerless raw binary to the RP2350's external XIP flash starting at +# physical address 0x10000000, then verifies the written bytes by reading them +# back, then releases the core so the freshly programmed firmware runs. +# +# A raw .bin carries no address information, no entry point and no section +# table, so the load address MUST be supplied out of band. On the RP2350 the +# only correct value is 0x10000000: that is where the boot ROM jumps after +# pulling the reset vector out of the on-chip XIP window. Flashing anywhere +# else produces a board that enumerates over USB and then does nothing. +# +# The target must already be running the stock RP2350 bootrom (the default +# state after power-up or after any BOOTSEL+UF2 reflash). OpenOCD attaches to +# the bootrom via SWD, halts it, programs flash, verifies, and resets. +# +# Requirements: +# - Pico Debug Probe (or any CMSIS-DAP / SWD adapter) connected to the target. +# - OpenOCD with the rp2350 target script installed. The Pico SDK ships one; +# see PICO_OPENOCD below. +# - Exactly one process may own the debug probe. Close any other OpenOCD, +# GDB, or IDE debug session first. +# +# Environment variables: +# PICO_OPENOCD Directory containing the openocd binary AND its scripts/ +# directory. Default: $HOME/.pico-sdk/openocd/0.12.0+dev +# The path is used for BOTH the executable and -s scripts. +# ADAPTER_SPEED SWD clock in kHz. Default: 5000. +# 5000 kHz is deliberately conservative. This is a write path, +# not a read-only debug session, and a marginal USB cable or +# long dupont run will produce spurious verify failures at +# higher clocks. Raise it (24000) for read-only work; if +# "Error: target not halted" or verify mismatches appear, +# lower it to 1000. +# +# Examples: +# ./flash.sh WEEK04/0x0005_intro-to-variables/build/0x0005_intro-to-variables.bin +# ADAPTER_SPEED=1000 ./flash.sh build/hacked.bin +# PICO_OPENOCD=/opt/homebrew/bin ./flash.sh build/hacked.bin +# +# Exit status: +# 0 flash written, verified, and core released +# 1 bad usage, missing input file, or OpenOCD not found +# * any other status is propagated from OpenOCD, so a failed verify or a +# write error is visible to the caller rather than being swallowed. +# +# Related scripts: +# debug-server.sh / debug-server.ps1 long-running GDB server for live +# debugging with Binary Ninja +# +# See also: +# WEEK04/WEEK04-BN.md the full walkthrough this script belongs to + +set -euo pipefail + +# --- argument validation --------------------------------------------------- + +BIN="${1:-}" +if [ -z "$BIN" ]; then + echo "usage: $0 " >&2 + exit 1 +fi + +if [ ! -f "$BIN" ]; then + echo "error: file not found: $BIN" >&2 + echo " build it first: cmake -B build -G Ninja -DPICO_BOARD=pico2 -DPICO_PLATFORM=rp2350 && cmake --build build" >&2 + exit 1 +fi + +# --- toolchain resolution -------------------------------------------------- + +OCD="${PICO_OPENOCD:-$HOME/.pico-sdk/openocd/0.12.0+dev}" +if [ ! -x "$OCD/openocd" ]; then + echo "error: OpenOCD not found at $OCD/openocd" >&2 + echo " set PICO_OPENOCD=/path/to/openocd (the directory containing the openocd binary)" >&2 + exit 1 +fi + +SPEED="${ADAPTER_SPEED:-5000}" + +# --- program --------------------------------------------------------------- + +# OpenOCD flag notes: +# -f interface/cmsis-dap.cfg the Pico Debug Probe is a CMSIS-DAP v1 device +# -f target/rp2350.cfg RP2350 dual Cortex-M33 + RP2350B0-style DAP; +# sets USE_CORE=SMP by default, which is fine here +# because we never hand uninitialised core1 +# registers to a debugger. For live debugging use +# debug-server.sh, which forces USE_CORE=0. +# -c "program BIN 0x10000000 verify reset exit" +# program the write +# 0x10000000 base address (see header) +# verify read back and compare every byte; a mismatch aborts +# reset reset the core so the new image starts at its vectors +# exit release the probe and return to the shell +# +# The adapter speed is deliberately lower here than in debug-server.sh; see +# ADAPTER_SPEED in the header. +echo "Flashing $BIN -> 0x10000000 using $OCD/openocd (SWD ${SPEED} kHz)" +"$OCD/openocd" \ + -s "$OCD/scripts" \ + -f interface/cmsis-dap.cfg \ + -f target/rp2350.cfg \ + -c "adapter speed ${SPEED}" \ + -c "program $BIN 0x10000000 verify reset exit" diff --git a/hardware/EHP2.fzz b/hardware/EHP2.fzz new file mode 100644 index 0000000..149e6b1 Binary files /dev/null and b/hardware/EHP2.fzz differ diff --git a/hardware/EHP2_bb.png b/hardware/EHP2_bb.png new file mode 100644 index 0000000..3b81e76 Binary files /dev/null and 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pico-gdb-memory.gdb - Restrict GDB memory access to valid RP2350 / Pico 2 W memory ranges. +# +# Prevents Binary Ninja register-value preview dereferences and out-of-bounds reads +# from triggering OpenOCD SWD faults and debug port reconnects (SWD DPIDR storms). +# +# In Binary Ninja's Debugger Console (with GDB MI adapter connected), run: +# source pico-gdb-memory.gdb +# (or provide the full path to this file). + +delete mem +mem 0x10000000 0x10400000 ro +mem 0x20000000 0x20082000 rw +set mem inaccessible-by-default on +info mem diff --git a/pyproject.toml b/pyproject.toml new file mode 100644 index 0000000..5bed409 --- /dev/null +++ b/pyproject.toml @@ -0,0 +1,94 @@ +# Python standards for this repository. +# +# Scope note: only the small number of first-party helper scripts at the repo +# root are linted. Firmware projects under 0x*/ are C/C++/ASM and are not +# Python, and vendored trees (pico-sdk, build/) are excluded explicitly. +# +# Run: +# ruff check . +# ruff format . +# ruff check --fix . + +[project] +name = "embedded-hacking-tools" +version = "1.0.0" +description = "Host-side tooling for the Embedded Hacking course" +requires-python = ">=3.10" + +[tool.ruff] +target-version = "py310" +line-length = 88 +# Scope: the first-party host-side helpers at the repo root only. The lesson +# trees below are per-lesson material that predates this config and are +# intentionally not linted; migrate a file to the repo root, or run ruff on it +# directly with an explicit path, when you touch it. +extend-exclude = [ + "0x*", + "WEEK*", + "**/build", + "pico-sdk", + "**/pico-sdk", + "node_modules", +] + +[tool.ruff.lint] +# E/W pycodestyle - formatting-independent style +# F pyflakes - unused imports, undefined names, f-string gaps +# I isort - import ordering +# UP pyupgrade - modern syntax for the declared target version +# B bugbear - real bug patterns +# SIM simplify - redundant code +# C4 comprehensions - needless comprehension / generator misuse +# RET return - inconsistent returns +# PTH pathlib - use pathlib instead of os.path +# ARG unused-arguments - dead parameters +# D pydocstyle - docstring presence and convention +# ANN annotations - type annotations +# TRY tryceratops - correct exception handling +# PIE misc - misc lints +# RUF ruff-specific - modern idioms and correctness rules +select = [ + "E", + "F", + "I", + "UP", + "B", + "SIM", + "C4", + "RET", + "PTH", + "ARG", + "D", + "ANN", + "TRY", + "PIE", + "RUF", +] + +ignore = [ + # The UF2 block format is a byte-level binary format; several conversions + # legitimately deal in loose byte slices and magic integers. + "E501", + # C901 complexity: convert_from_uf2 is a linear decoder over a block stream + # and reads far better as one pass than split into helpers. + "C901", + # Legacy CLI scripts print progress to stdout as their primary output. + "T201", +] + +[tool.ruff.lint.per-file-ignores] +# Tutorial scripts are run directly and use a permissive argparse style. +"uf2conv.py" = ["D100"] + +[tool.ruff.lint.pydocstyle] +convention = "google" + +[tool.ruff.lint.flake8-annotations] +# Accept `-> None` omission only on __init__; require annotations elsewhere. +suppress-dummy-args = false +mypy-init-return = true + +[tool.ruff.format] +quote-style = "double" +indent-style = "space" +line-ending = "lf" diff --git a/textbook/Embedded-Hacking.pdf b/textbook/Embedded-Hacking.pdf new file mode 100644 index 0000000..af0b640 Binary files /dev/null and b/textbook/Embedded-Hacking.pdf differ diff --git a/uf2conv.py b/uf2conv.py new file mode 100644 index 0000000..c5a832f --- /dev/null +++ b/uf2conv.py @@ -0,0 +1,861 @@ +#!/usr/bin/env python3 +r"""Convert firmware images between Intel HEX, raw BIN, and Raspberry Pi UF2. + +This is the course's single canonical copy of the converter. Every week that +patches a binary refers to the copy at the repository root: + + python ../uf2conv.py build/image-h.bin --base 0x10000000 \\ + --family 0xe48bff59 --output build/hacked.uf2 + +It descends from the upstream Raspberry Pi ``uf2conv.py``, with the following +changes made for this course: + +* Full type annotations and Google-style docstrings on every public callable. +* ``pathlib`` instead of ``os.path``, and explicit ``except`` clauses. +* Latent crash bugs in the upstream error paths fixed (see + :func:`convert_from_uf2`). +* Module globals replaced with an explicit :class:`ConverterContext`, so the + base address and family ID are threaded through rather than mutated behind + the caller's back. + +UF2 format, for reference +------------------------- +A UF2 file is a flat sequence of 512-byte blocks. Each block is:: + + offset size field + 0x00 4 magicStart0 = 0x0A324655 ("UF2\\n") + 0x04 4 magicStart1 = 0x9E5D5157 (arbitrary constant) + 0x08 4 flags + 0x0C 4 targetAddr + 0x10 4 payloadSize (max 476) + 0x14 4 blockNo + 0x18 4 numBlocks + 0x1C 4 familyID + 0x20 476 data + 0x1FC 4 magicEnd = 0x0AB16F30 + +Flags that matter here: + +* ``0x00000001`` -- "do not flash"; this block is a no-flash marker. +* ``0x00002000`` -- "family ID present"; ``familyID`` is meaningful. + +For the RP2350 the family ID is ``0xe48bff59``, and it is what tells the +boot ROM that this UF2 targets RP2350 hardware rather than, say, an RP2040 or +a Pico W. + +See Also: +-------- +* ``uf2families.json`` -- the family-name to family-ID table, loaded from the + directory containing this file. +* ``flash.sh`` / ``flash.ps1`` -- program a raw ``.bin`` over SWD instead. +""" + +from __future__ import annotations + +import argparse +import json +import os +import re +import struct +import subprocess +import sys +from dataclasses import dataclass +from pathlib import Path +from time import sleep + +# --------------------------------------------------------------------------- +# UF2 format constants +# --------------------------------------------------------------------------- + +#: First magic word, ``"UF2\n"`` read as a little-endian uint32. +UF2_MAGIC_START0 = 0x0A324655 +#: Second magic word. The value is arbitrary but must be constant. +UF2_MAGIC_START1 = 0x9E5D5157 +#: Trailing magic word closing every 512-byte block. +UF2_MAGIC_END = 0x0AB16F30 + +#: Size of one UF2 block in bytes. +UF2_BLOCK_SIZE = 512 +#: Offset of the 32-byte block header within a block. +UF2_HEADER_SIZE = 32 +#: Largest payload a single block may carry (476 = 512 - 32 header - 4 magic). +UF2_MAX_PAYLOAD = UF2_BLOCK_SIZE - UF2_HEADER_SIZE - 4 + +#: Flag bit marking a block the bootloader must NOT program. +UF2_FLAG_NOFLASH = 0x00000001 +#: Flag bit announcing that ``familyID`` carries a meaningful value. +UF2_FLAG_FAMILY_ID = 0x00002000 + +#: Name of the marker file the boot ROM exposes on its flash-drive volume. +INFO_FILE = "INFO_UF2.TXT" + +#: Struct format for the 32-byte UF2 block header. +_HEADER_STRUCT = struct.Struct("UF2 + conversion of RP2040-era images, and the wrong behaviour for + RP2350, which is why the course always passes ``--family``. + """ + + appstartaddr: int | None = DEFAULT_BASE_ADDRESS + familyid: int = DEFAULT_FAMILY_ID + + +# --------------------------------------------------------------------------- +# Format detection +# --------------------------------------------------------------------------- + + +def is_uf2(buf: bytes) -> bool: + """Report whether a buffer begins with the UF2 start magic. + + Args: + buf: Raw file contents. + + Returns: + ``True`` if the first two uint32 words are the UF2 start magic. + """ + if len(buf) < 8: + return False + word0, word1 = _HEADER_STRUCT.unpack_from(buf, 0)[:2] + return word0 == UF2_MAGIC_START0 and word1 == UF2_MAGIC_START1 + + +def is_hex(buf: bytes) -> bool: + """Report whether a buffer looks like an Intel HEX file. + + A file qualifies when it decodes as UTF-8, begins with a record marker + ``:``, and contains only characters legal in Intel HEX records. + + Args: + buf: Raw file contents. + + Returns: + ``True`` if the buffer should be treated as Intel HEX. + """ + try: + text = buf[:30].decode("utf-8") + except UnicodeDecodeError: + return False + if not text.startswith(":"): + return False + return re.match(rb"^[:0-9a-fA-F\r\n]+$", buf) is not None + + +# --------------------------------------------------------------------------- +# UF2 -> BIN +# --------------------------------------------------------------------------- + + +def convert_from_uf2(buf: bytes, ctx: ConverterContext) -> bytes: + """Decode a UF2 file back into a flat binary image. + + Blocks are visited in file order. Gaps between consecutive block addresses + are filled with zero words, and any trailing gap is dropped so that the + result ends at the last byte actually programmed. + + A UF2 file may legitimately interleave blocks from several families (this + is how a multicore image ships both cores in one download). When more than + one family is present and the caller did not constrain the family with + ``--family``, the conversion is ambiguous, so the payload is emptied and + ``appstartaddr`` reset to ``0``. + + Args: + buf: Complete UF2 file contents. + ctx: Conversion state; updated in place with the discovered base + address. + + Returns: + The decoded payload. + + Raises: + Uf2Error: If a block declares an oversized payload, the blocks are out + of order, or the implied padding exceeds 10 MiB. + + Note: + The upstream Raspberry Pi version of this function crashes on its own + error paths: it builds the message with ``"..." + ptr`` where ``ptr`` + is an ``int``, which raises :class:`TypeError` and masks the real + problem. The messages here use f-strings so the diagnostic survives. + """ + numblocks = len(buf) // UF2_BLOCK_SIZE + curraddr: int | None = None + currfamilyid: int | None = None + families_found: dict[int, int] = {} + prev_flag: int | None = None + all_flags_same = True + outp: list[bytes] = [] + + for blockno in range(numblocks): + ptr = blockno * UF2_BLOCK_SIZE + block = buf[ptr : ptr + UF2_BLOCK_SIZE] + ( + magic0, + magic1, + flags, + target_addr, + datalen, + _blockno, + _numblocks, + block_family, + ) = _HEADER_STRUCT.unpack_from(block, 0) + + if magic0 != UF2_MAGIC_START0 or magic1 != UF2_MAGIC_START1: + print(f"Skipping block at {ptr:#x}; bad magic") + continue + + if flags & UF2_FLAG_NOFLASH: + continue + + if datalen > UF2_MAX_PAYLOAD: + msg = f"Invalid UF2 data size at {ptr:#x}: {datalen}" + raise Uf2Error(msg) + + if flags & UF2_FLAG_FAMILY_ID and currfamilyid is None: + currfamilyid = block_family + + # A new contiguous run starts when the address jumps or the family + # changes. appstartaddr tracks the start of the current run, which is + # what makes the reported start address the image's true base rather + # than the address of its last block. + if curraddr is None or ( + flags & UF2_FLAG_FAMILY_ID and block_family != currfamilyid + ): + currfamilyid = block_family + curraddr = target_addr + if ctx.familyid == DEFAULT_FAMILY_ID or ctx.familyid == block_family: + ctx.appstartaddr = target_addr + + padding = target_addr - curraddr + if padding < 0: + msg = f"Block out of order at {ptr:#x}: {target_addr:#x} < {curraddr:#x}" + raise Uf2Error(msg) + if padding > 10 * 1024 * 1024: + msg = f"More than 10M of padding needed at {ptr:#x}" + raise Uf2Error(msg) + if padding % 4 != 0: + msg = f"Non-word padding size at {ptr:#x}: {padding}" + raise Uf2Error(msg) + + while padding > 0: + padding -= 4 + outp.append(b"\x00\x00\x00\x00") + + if ctx.familyid == DEFAULT_FAMILY_ID or ( + flags & UF2_FLAG_FAMILY_ID and ctx.familyid == block_family + ): + outp.append( + block[UF2_HEADER_SIZE : UF2_HEADER_SIZE + datalen], + ) + + curraddr = target_addr + datalen + + if flags & UF2_FLAG_FAMILY_ID: + existing = families_found.get(block_family) + if existing is None or existing > target_addr: + families_found[block_family] = target_addr + + if prev_flag is None: + prev_flag = flags + elif prev_flag != flags: + all_flags_same = False + + if blockno == numblocks - 1: + _print_uf2_header_info(families_found, all_flags_same, flags) + if len(families_found) > 1 and ctx.familyid == DEFAULT_FAMILY_ID: + outp = [] + ctx.appstartaddr = 0x0 + + return b"".join(outp) + + +def _print_uf2_header_info( + families_found: dict[int, int], + all_flags_same: bool, + flags: int, +) -> None: + """Print the family summary block that follows a UF2->BIN conversion. + + Args: + families_found: Mapping of family ID to the lowest target address seen + for that family. + all_flags_same: Whether every block carried an identical flag word. + flags: The flag word from the final block, used for display. + """ + print("--- UF2 File Header Info ---") + families = load_families() + name_by_id = {value: key for key, value in families.items()} + for family_hex, address in families_found.items(): + short_name = name_by_id.get(family_hex, "") + print(f"Family ID is {short_name}, hex value is {family_hex:#010x}") + print(f"Target Address is {address:#010x}") + if all_flags_same: + print(f"All block flag values consistent, {flags:#06x}") + else: + print("Flags were not all the same") + print("----------------------------") + + +# --------------------------------------------------------------------------- +# BIN -> UF2 +# --------------------------------------------------------------------------- + + +def convert_to_uf2(file_content: bytes, ctx: ConverterContext) -> bytes: + """Wrap a raw binary in UF2 blocks. + + The binary is split into 256-byte payloads; the final block is zero-padded. + Each block's ``targetAddr`` is the byte offset within the image plus + :attr:`ConverterContext.appstartaddr`, so for RP2350 firmware built at + ``0x10000000`` the caller passes ``--base 0x10000000``. + + Args: + file_content: The raw image. + ctx: Conversion state supplying the base address and family ID. + + Returns: + The UF2 file contents, always a whole number of 512-byte blocks. + """ + datapadding = bytes(UF2_BLOCK_SIZE - 256 - UF2_HEADER_SIZE - 4) + numblocks = (len(file_content) + 255) // 256 + flags = UF2_FLAG_FAMILY_ID if ctx.familyid else 0x0 + base = ctx.appstartaddr or 0 + + blocks: list[bytes] = [] + for blockno in range(numblocks): + ptr = 256 * blockno + chunk = file_content[ptr : ptr + 256] + header = _HEADER_STRUCT.pack( + UF2_MAGIC_START0, + UF2_MAGIC_START1, + flags, + ptr + base, + 256, + blockno, + numblocks, + ctx.familyid, + ) + payload = chunk + bytes(256 - len(chunk)) + block = header + payload + datapadding + struct.pack(" bytes: + """Render a binary as a C array initialiser for embedding in firmware. + + Args: + file_content: The raw image. + + Returns: + UTF-8 bytes of a C translation unit fragment. + """ + parts = [ + f"const unsigned long bindata_len = {len(file_content)};\n", + "const unsigned char bindata[] __attribute__((aligned(16))) = {", + ] + for index, value in enumerate(file_content): + if index % 16 == 0: + parts.append("\n") + parts.append(f"{value:#04x}, ") + parts.append("\n};\n") + return "".join(parts).encode() + + +# --------------------------------------------------------------------------- +# Intel HEX -> UF2 +# --------------------------------------------------------------------------- + + +@dataclass +class Block: + """A single 256-byte-aligned region of an image under construction. + + Attributes: + addr: Base address of the block, always 256-byte aligned. + data: The block's bytes, initialised to ``default_data``. + """ + + addr: int + data: bytearray + + def __init__(self, addr: int, default_data: int = 0xFF) -> None: + """Initialise an erased 256-byte block. + + Args: + addr: 256-byte-aligned base address of the block. + default_data: Fill byte; ``0xFF`` matches erased flash. + """ + self.addr = addr + self.data = bytearray([default_data] * 256) + + def encode(self, blockno: int, numblocks: int, ctx: ConverterContext) -> bytes: + """Serialise this block into a 512-byte UF2 block. + + Args: + blockno: Index of this block within the file. + numblocks: Total number of blocks in the file. + ctx: Conversion state supplying the family ID. + + Returns: + Exactly 512 bytes. + """ + flags = UF2_FLAG_FAMILY_ID if ctx.familyid else 0x0 + out = _HEADER_STRUCT.pack( + UF2_MAGIC_START0, + UF2_MAGIC_START1, + flags, + self.addr, + 256, + blockno, + numblocks, + ctx.familyid, + ) + out += self.data[0:256] + out += bytes(UF2_BLOCK_SIZE - 4 - len(out)) + out += struct.pack(" bytes: + """Assemble Intel HEX records into a UF2 file. + + Only record types 0x00 (data), 0x01 (EOF), 0x02 (extended segment address) + and 0x04 (extended linear address) are handled; any other type is ignored, + matching the upstream behaviour. + + Args: + text: Decoded Intel HEX file contents. + ctx: Conversion state; ``appstartaddr`` is set to the first data + address seen. + + Returns: + The UF2 file contents. + """ + ctx.appstartaddr = None + upper = 0 + currblock: Block | None = None + blocks: list[Block] = [] + + for line in text.split("\n"): + if not line.startswith(":"): + continue + record = [int(line[i : i + 2], 16) for i in range(1, len(line) - 1, 2)] + rec_type = record[3] + if rec_type == 4: + upper = ((record[4] << 8) | record[5]) << 16 + elif rec_type == 2: + upper = ((record[4] << 8) | record[5]) << 4 + elif rec_type == 1: + break + elif rec_type == 0: + addr = upper + ((record[1] << 8) | record[2]) + if ctx.appstartaddr is None: + ctx.appstartaddr = addr + index = 4 + while index < len(record) - 1: + if currblock is None or currblock.addr & ~0xFF != addr & ~0xFF: + currblock = Block(addr & ~0xFF) + blocks.append(currblock) + currblock.data[addr & 0xFF] = record[index] + addr += 1 + index += 1 + + numblocks = len(blocks) + return b"".join(blocks[i].encode(i, numblocks, ctx) for i in range(numblocks)) + + +# --------------------------------------------------------------------------- +# Drive discovery +# --------------------------------------------------------------------------- + + +def _iter_candidate_dirs() -> list[Path]: + """Return the directories that may contain mounted removable volumes.""" + if sys.platform == "win32": + return [] + + searchpaths = [Path("/mnt"), Path("/media")] + if sys.platform == "darwin": + searchpaths = [Path("/Volumes")] + elif sys.platform == "linux": + user = environ_user() + if user: + searchpaths += [Path("/media") / user, Path("/run/media") / user] + sudo_user = os.environ.get("SUDO_USER") + if sudo_user: + searchpaths += [ + Path("/media") / sudo_user, + Path("/run/media") / sudo_user, + ] + return searchpaths + + +def environ_user() -> str | None: + """Return the current user name from the environment. + + Tried under several variable names so the search works on macOS, Linux and + Windows shells alike. + + Returns: + The user name, or ``None`` if it cannot be determined. + """ + for var in ("USER", "USERNAME", "LOGNAME"): + value = os.environ.get(var) + if value: + return value + return None + + +def get_drives() -> list[Path]: + """Find mounted Pico boot drives. + + A drive qualifies when it contains the ``INFO_UF2.TXT`` marker the boot ROM + writes when it presents the flash as a USB mass-storage device. + + Returns: + Every qualifying mount point. + """ + drives: list[Path] = [] + + if sys.platform == "win32": + command = ( + "(Get-Volume | Where-Object { $_.FileSystemLabel -match 'RP2350|RPI-RP2' })" + ".DriveLetter" + ) + try: + raw = subprocess.check_output( + ["powershell", "-Command", command], + text=True, + ) + except (subprocess.CalledProcessError, FileNotFoundError, OSError): + return [] + for letter in raw.split(): + if len(letter) == 1 and letter.isalpha(): + drives.append(Path(f"{letter.upper()}:\\")) + return drives + + for rootpath in _iter_candidate_dirs(): + if not rootpath.is_dir(): + continue + try: + entries = list(rootpath.iterdir()) + except OSError: + continue + for entry in entries: + if not entry.is_dir(): + continue + if (entry / INFO_FILE).is_file(): + drives.append(entry) + return drives + + +def board_id(path: Path) -> str: + """Read the ``Board-ID`` field from a boot drive's info file. + + Args: + path: Mount point of the boot drive. + + Returns: + The board ID string, for example ``RP2350``. + + Raises: + Uf2Error: If the info file is missing or has no ``Board-ID`` field. + """ + info = path / INFO_FILE + if not info.is_file(): + msg = f"Not a Pico boot drive: {path} has no {INFO_FILE}" + raise Uf2Error(msg) + match = re.search(r"Board-ID: ([^\r\n]*)", info.read_text()) + if match is None: + msg = f"No Board-ID field in {info}" + raise Uf2Error(msg) + return match.group(1) + + +def list_drives() -> None: + """Print every connected Pico boot drive and its board ID.""" + for drive in get_drives(): + try: + print(drive, board_id(drive)) + except Uf2Error as exc: + print(f"{drive} ") + + +def write_file(name: Path | str, buf: bytes) -> None: + """Write a buffer to disk and report the size written. + + Args: + name: Destination path. + buf: Bytes to write. + """ + path = Path(name) + path.parent.mkdir(parents=True, exist_ok=True) + path.write_bytes(buf) + print(f"Wrote {len(buf)} bytes to {path}") + + +def load_families() -> dict[str, int]: + """Load the family-name to family-ID table. + + ``uf2families.json`` is read from the directory containing this script, so + the converter works regardless of the caller's working directory. + + Returns: + Mapping of upper-case short name to family ID. + + Raises: + Uf2Error: If the JSON file is missing or malformed. + """ + pathname = Path(__file__).resolve().parent / "uf2families.json" + try: + raw_families = json.loads(pathname.read_text()) + except FileNotFoundError as exc: + msg = f"Required family table not found: {pathname}" + raise Uf2Error(msg) from exc + except json.JSONDecodeError as exc: + msg = f"Malformed family table {pathname}: {exc}" + raise Uf2Error(msg) from exc + + return {fam["short_name"]: int(fam["id"], 0) for fam in raw_families} + + +# --------------------------------------------------------------------------- +# CLI +# --------------------------------------------------------------------------- + + +def _build_parser() -> argparse.ArgumentParser: + """Construct the command-line argument parser. + + Returns: + A configured :class:`argparse.ArgumentParser`. + """ + parser = argparse.ArgumentParser( + prog="uf2conv.py", + description="Convert firmware between Intel HEX, raw BIN and UF2.", + epilog=( + "Course example (RP2350 raw image built for XIP flash):\n" + " python ../uf2conv.py build/image-h.bin " + "--base 0x10000000 \\\n" + " --family 0xe48bff59 --output build/hacked.uf2\n" + ), + formatter_class=argparse.RawDescriptionHelpFormatter, + ) + parser.add_argument( + "input", + metavar="INPUT", + nargs="?", + help="input file (HEX, BIN or UF2); omit when using --list", + ) + parser.add_argument( + "-b", + "--base", + default=hex(DEFAULT_BASE_ADDRESS), + help=( + "base address of the application for BIN input " + f"(default: {hex(DEFAULT_BASE_ADDRESS)}; use 0x10000000 for RP2350 XIP)" + ), + ) + parser.add_argument( + "-f", + "--family", + default=hex(DEFAULT_FAMILY_ID), + help=( + "family ID as a number or a name from uf2families.json " + f"(default: {hex(DEFAULT_FAMILY_ID)}; RP2350 is 0xe48bff59)" + ), + ) + parser.add_argument( + "-o", + "--output", + metavar="FILE", + help='write output to FILE; defaults to "flash.uf2" or "flash.bin"', + ) + parser.add_argument( + "-d", + "--device", + dest="device_path", + help="select a specific device path to flash (reserved; unused)", + ) + parser.add_argument( + "-l", + "--list", + action="store_true", + help="list connected Pico boot drives and exit", + ) + parser.add_argument( + "-c", + "--convert", + action="store_true", + help="convert only; do not deploy to a mounted boot drive", + ) + parser.add_argument( + "-D", + "--deploy", + action="store_true", + help="deploy the input file unchanged; do not convert", + ) + parser.add_argument( + "-w", + "--wait", + action="store_true", + help="poll for a boot drive to appear instead of failing immediately", + ) + parser.add_argument( + "-C", + "--carray", + action="store_true", + help="emit a C array initialiser instead of a UF2 file", + ) + parser.add_argument( + "-i", + "--info", + action="store_true", + help="print UF2 header information and exit without converting", + ) + return parser + + +def _resolve_family(spec: str) -> int: + """Resolve a ``--family`` value to a numeric family ID. + + Args: + spec: Either a family short name (case-insensitive) or an integer + literal such as ``0xe48bff59``. + + Returns: + The numeric family ID. + + Raises: + Uf2Error: If the value is neither a known name nor a valid integer. + """ + families = load_families() + if spec.upper() in families: + return families[spec.upper()] + try: + return int(spec, 0) + except ValueError as exc: + msg = "Family ID needs to be a number or one of: " + ", ".join(families) + raise Uf2Error(msg) from exc + + +def _wait_for_drive() -> Path | None: + """Poll for a boot drive to be mounted. + + Returns: + The first drive found, or ``None`` if the wait was interrupted. + """ + print("Waiting for drive to deploy...") + while True: + drives = get_drives() + if drives: + return drives[0] + sleep(0.1) + + +def main(argv: list[str] | None = None) -> int: + """Run the command-line converter. + + Args: + argv: Argument list, defaulting to :data:`sys.argv` ``[1:]``. + + Returns: + ``0`` on success, ``1`` on a user or input error. + """ + parser = _build_parser() + args = parser.parse_args(argv) + + ctx = ConverterContext() + try: + ctx.familyid = _resolve_family(args.family) + ctx.appstartaddr = int(args.base, 0) + except (Uf2Error, ValueError) as exc: + print(exc, file=sys.stderr) + return 1 + + if args.list: + list_drives() + return 0 + + if not args.input: + print("Need an input file (or use --list)", file=sys.stderr) + return 1 + + source = Path(args.input) + if not source.is_file(): + print(f"error: file not found: {source}", file=sys.stderr) + return 1 + + inpbuf = source.read_bytes() + from_uf2 = is_uf2(inpbuf) + ext = "uf2" + + try: + if args.deploy: + outbuf = inpbuf + elif from_uf2 and not args.info: + outbuf = convert_from_uf2(inpbuf, ctx) + ext = "bin" + elif from_uf2 and args.info: + outbuf = b"" + convert_from_uf2(inpbuf, ctx) + elif is_hex(inpbuf): + outbuf = convert_from_hex_to_uf2(inpbuf.decode("utf-8"), ctx) + elif args.carray: + outbuf = convert_to_carray(inpbuf) + ext = "h" + else: + outbuf = convert_to_uf2(inpbuf, ctx) + except Uf2Error as exc: + print(f"error: {exc}", file=sys.stderr) + return 1 + + if not args.deploy and not args.info: + print( + f"Converted to {ext}, output size: {len(outbuf)}, " + f"start address: {ctx.appstartaddr or 0:#x}", + ) + + if (args.convert or ext != "uf2") and args.output is None: + args.output = f"flash.{ext}" + if args.output: + write_file(args.output, outbuf) + + if ext == "uf2" and not args.convert and not args.info: + drives = get_drives() + if not drives: + if args.wait: + found = _wait_for_drive() + drives = [found] if found else [] + elif not args.output: + print("error: no drive to deploy", file=sys.stderr) + return 1 + for drive in drives: + print(f"Flashing {drive} ({board_id(drive)})") + write_file(drive / "NEW.UF2", outbuf) + + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/uf2families.json b/uf2families.json new file mode 100644 index 0000000..39373c4 --- /dev/null +++ b/uf2families.json @@ -0,0 +1,22 @@ +[ + { + "short_name": "RP2040", + "id": "0xe48bff56", + "description": "Raspberry Pi RP2040" + }, + { + "short_name": "RP2350-ARM-S", + "id": "0xe48bff59", + "description": "Raspberry Pi RP2350, ARM, Secure" + }, + { + "short_name": "RP2350-ARM-NS", + "id": "0xe48bff5a", + "description": "Raspberry Pi RP2350, ARM, Non-Secure" + }, + { + "short_name": "RP2350-RISCV", + "id": "0xe48bff5b", + "description": "Raspberry Pi RP2350, RISC-V" + } +] \ No newline at end of file