Initial commit

This commit is contained in:
Kevin Thomas
2026-07-06 14:32:12 -04:00
commit f62db776e1
615 changed files with 72344 additions and 0 deletions
+32
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[build]
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[target.thumbv8m.main-none-eabihf]
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runner = "${PICOTOOL_PATH} load -u -v -x -t elf"
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runner = "${PICOTOOL_PATH} load -u -v -x -t elf"
[env]
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+1
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rp2350
+8
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+41
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+8
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+124
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"rp2040-hal-macros",
"rp2040-pac",
"usb-device",
"vcell",
"void",
]
[[package]]
name = "rp2040-hal-macros"
version = "0.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "86479063e497efe1ae81995ef9071f54fd1c7427e04d6c5b84cde545ff672a5e"
dependencies = [
"cortex-m-rt",
"proc-macro2",
"quote",
"syn 1.0.109",
]
[[package]]
name = "rp2040-pac"
version = "0.6.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "83cbcd3f7a0ca7bbe61dc4eb7e202842bee4e27b769a7bf3a4a72fa399d6e404"
dependencies = [
"cortex-m",
"cortex-m-rt",
"critical-section",
"vcell",
]
[[package]]
name = "rp235x-hal"
version = "0.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e2939c82776b0b4ae110168b4298b5adf831e6cff249b057bf2a2187453b959c"
dependencies = [
"bitfield 0.14.0",
"cortex-m",
"cortex-m-rt",
"critical-section",
"embedded-dma",
"embedded-hal 0.2.7",
"embedded-hal 1.0.0",
"embedded-hal-async",
"embedded-hal-nb",
"embedded-io",
"frunk",
"fugit",
"gcd",
"itertools 0.13.0",
"nb 1.1.0",
"paste",
"pio",
"rand_core",
"riscv",
"riscv-rt",
"rp-binary-info",
"rp-hal-common",
"rp235x-hal-macros",
"rp235x-pac",
"sha2-const-stable",
"usb-device",
"vcell",
"void",
]
[[package]]
name = "rp235x-hal-macros"
version = "0.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "74edd7a5979e9763bbb98e9746e711bac7464ee3397af7288e6c288ff0d3c764"
dependencies = [
"proc-macro2",
"quote",
"syn 2.0.117",
]
[[package]]
name = "rp235x-pac"
version = "0.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5ffcb6931deee4242886b5a1df62db5e2555b0eb6ae1e8be101f3ea3e58e65c6"
dependencies = [
"cortex-m",
"cortex-m-rt",
"critical-section",
"vcell",
]
[[package]]
name = "rustc_version"
version = "0.2.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a"
dependencies = [
"semver",
]
[[package]]
name = "semver"
version = "0.9.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403"
dependencies = [
"semver-parser",
]
[[package]]
name = "semver-parser"
version = "0.7.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3"
[[package]]
name = "sha2-const-stable"
version = "0.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5f179d4e11094a893b82fff208f74d448a7512f99f5a0acbd5c679b705f83ed9"
[[package]]
name = "spi"
version = "0.1.0"
dependencies = [
"cortex-m",
"cortex-m-rt",
"defmt",
"defmt-rtt",
"embedded-hal 1.0.0",
"fugit",
"panic-halt",
"panic-probe",
"rp2040-boot2",
"rp2040-hal",
"rp235x-hal",
]
[[package]]
name = "stable_deref_trait"
version = "1.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596"
[[package]]
name = "syn"
version = "1.0.109"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "syn"
version = "2.0.117"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "thiserror"
version = "2.0.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4"
dependencies = [
"thiserror-impl",
]
[[package]]
name = "thiserror-impl"
version = "2.0.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5"
dependencies = [
"proc-macro2",
"quote",
"syn 2.0.117",
]
[[package]]
name = "unicode-ident"
version = "1.0.24"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75"
[[package]]
name = "usb-device"
version = "0.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "98816b1accafbb09085168b90f27e93d790b4bfa19d883466b5e53315b5f06a6"
dependencies = [
"heapless",
"portable-atomic",
]
[[package]]
name = "vcell"
version = "0.1.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
[[package]]
name = "void"
version = "1.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
[[package]]
name = "volatile-register"
version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
dependencies = [
"vcell",
]
+80
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@@ -0,0 +1,80 @@
[package]
edition = "2024"
name = "spi"
version = "0.1.0"
license = "MIT or Apache-2.0"
[lib]
name = "spi_lib"
path = "src/lib.rs"
[[bin]]
name = "spi"
path = "src/main.rs"
[dependencies]
cortex-m = "0.7"
cortex-m-rt = "0.7"
fugit = "0.3"
defmt = "1"
defmt-rtt = "1"
embedded-hal = "1.0"
[target.'cfg( target_arch = "arm" )'.dependencies]
panic-probe = { version = "1", features = ["print-defmt"] }
[target.'cfg( target_arch = "riscv32" )'.dependencies]
panic-halt = { version = "1.0.0" }
[target.thumbv6m-none-eabi.dependencies]
rp2040-boot2 = "0.3"
rp2040-hal = { version = "0.11", features = ["rt", "critical-section-impl"] }
[target.riscv32imac-unknown-none-elf.dependencies]
rp235x-hal = { version = "0.3", features = ["rt", "critical-section-impl"] }
[target."thumbv8m.main-none-eabihf".dependencies]
rp235x-hal = { version = "0.3", features = ["rt", "critical-section-impl"] }
# cargo build/run
[profile.dev]
debug = 2
debug-assertions = true
opt-level = 2
overflow-checks = true
# cargo build/run --release
[profile.release]
debug = 2
debug-assertions = false
lto = "fat"
opt-level = 2
overflow-checks = false
# do not optimize proc-macro crates = faster builds from scratch
[profile.dev.build-override]
debug = false
debug-assertions = false
overflow-checks = false
opt-level = 0
[profile.release.build-override]
debug = false
debug-assertions = false
overflow-checks = false
opt-level = 0
# cargo test
[profile.test]
debug = 2
debug-assertions = true
opt-level = 2
overflow-checks = true
# cargo test --release
[profile.bench]
debug = 2
debug-assertions = false
lto = "fat"
opt-level = 3
+111
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# 0x0b SPI Rust Driver
This repository contains a Bare-Metal Rust driver for the **SPI (Serial Peripheral Interface)** bus on the **RP2350** (and RP2040) microcontrollers.
It includes:
- A demo (`src/main.rs`) that executes an SPI loopback transfer (MOSI wired to MISO) and logs the results over UART.
- A reusable library module (`src/spi.rs`) providing a hardware-agnostic `spi_lib` containing formatting helpers for UART logging.
- Board initialization logic (`src/board.rs`).
## 🚀 Getting Started from Scratch
If you're starting with a fresh machine, follow these exact steps to install the toolchain, build the code, and flash it to your microcontroller.
### 1. Install Rust
First, install `rustup` (the Rust toolchain installer) if you haven't already:
```bash
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
```
*Note: Restart your terminal or run `source $HOME/.cargo/env` after this finishes.*
Ensure your Rust compiler is up to date:
```bash
rustup update
```
### 2. Install the Target Architecture
This project is configured for the **RP2350** (ARM Cortex-M33). We need to install the cross-compilation target for it:
```bash
rustup target add thumbv8m.main-none-eabihf
```
*(If you were targeting the RP2040, you would use `thumbv6m-none-eabi` instead).*
### 3. Install Build Tools
You will need a few extra tools to help link and format the firmware for the RP-series chips.
Install `flip-link` (adds zero-cost stack overflow protection):
```bash
cargo install flip-link
```
Install `picotool` (used by `cargo run` to flash the chip):
- **macOS:** `brew install picotool`
- **Linux/Windows:** Follow the official Raspberry Pi documentation to install `picotool` or build it from source.
### 4. Building the Code
To compile the code for the microcontroller, simply run:
```bash
cargo build
```
To build a highly optimized release version (smaller and faster):
```bash
cargo build --release
```
### 5. Flashing to the Microcontroller
This project is pre-configured in `.cargo/config.toml` to use `picotool` as the custom runner.
To flash the code:
1. Hold down the **BOOTSEL** button on your RP2350 board.
2. Plug it into your computer via USB (or press the RUN/RESET button while holding BOOTSEL).
3. Run the following command:
```bash
cargo run --release
```
*`cargo` will compile the code and automatically use `picotool` to upload the `.elf` file directly to your board and start executing it!*
### 6. Testing on the Host
Because the string formatting logic is separated into a reusable math library without touching hardware registers, you can run the unit tests natively on your computer!
However, because this project sets a default bare-metal target (`thumbv8m.main-none-eabihf`) in `.cargo/config.toml`, running a plain `cargo test` will fail because the standard library doesn't exist on the microcontroller. You must explicitly tell Cargo to compile the tests for your host computer's processor architecture:
**Mac (Apple Silicon):**
```bash
cargo test --lib --target aarch64-apple-darwin
```
**Linux (Intel/AMD 64-bit):**
```bash
cargo test --lib --target x86_64-unknown-linux-gnu
```
**Windows (64-bit):**
```bash
cargo test --lib --target x86_64-pc-windows-msvc
```
## 🧠 Code Walkthrough
This section explains exactly how the code works, where the entry point is, and traces the flow of execution as if you were stepping through it line-by-line.
### 1. The Entry Point (`src/main.rs`)
Unlike a standard computer program, bare-metal microcontrollers do not have an operating system to call `main()`. Instead, we use the `#[entry]` macro from the HAL (Hardware Abstraction Layer) to define the very first function that runs after the chip boots up.
* **`main() -> !`**: This is the absolute start of our code. It takes ownership of all the hardware peripherals (`hal::pac::Peripherals::take().unwrap()`) and immediately passes them into `board::run(...)`. The `-> !` means this function never returns (because embedded devices run in an infinite loop).
### 2. Board Initialization (`src/board.rs`)
Once execution enters `board.rs`, we initialize the system clocks, pins, UART (for logging), SysTick (for delay), and the SPI peripheral.
* **`run(...)`**: The master setup function. Calls the helper initialization functions below, prints an initialization banner over UART, and enters the infinite loop executing SPI transfers.
* **`init_spi(...)`**: Configures the hardware `SPI0` peripheral. Reconfigures MISO, MOSI, and SCK for SPI function, and configures CS as a software-controlled SIO output. Sets the SPI speed to 1 MHz in Mode 0 (CPOL=0, CPHA=0).
* **`loopback_transfer(...)`**: Called repeatedly in the main loop. It allocates an RX buffer, calls `execute_transfer()`, formats the TX and RX buffers as ASCII strings, and streams them over UART so you can verify the loopback on your console.
* **`execute_transfer(...)`**: The core hardware interaction. Asserts chip select (low), blocks while executing a full-duplex transfer using the `embedded-hal` SPI trait (`spi_dev.transfer()`), and de-asserts chip select (high).
### 3. The Reusable SPI Library (`src/spi.rs`)
While `board.rs` handles the hardware registers, `spi.rs` abstracts away the string formatting logic required to cleanly log the SPI transfers over UART without requiring dynamic memory allocation.
* **`clear_rx_buffer(...)`**: Clears the receive buffer before the next loopback transfer to ensure no stale data remains.
* **`format_tx_line(...)` / `format_rx_line(...)`**: Formats the byte arrays into `TX: ...` and `RX: ...` strings terminating in CRLF.
* **`copy_c_string(...)`**: A safe helper that copies bytes up to the first NUL terminator, allowing us to safely log C-style strings over UART.
+105
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//! Implementation module
//!
//! **File:** `build.rs`
//! **Author:** Kevin Thomas
//! **Date:** 2025
//!
//! MIT License
//!
//! Copyright (c) 2025 Kevin Thomas
//!
//! Permission is hereby granted, free of charge, to any person obtaining a copy
//! of this software and associated documentation files (the "Software"), to deal
//! in the Software without restriction, including without limitation the rights
//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//! copies of the Software, and to permit persons to whom the Software is
//! furnished to do so, subject to the following conditions:
//!
//! The above copyright notice and this permission notice shall be included in
//! all copies or substantial portions of the Software.
//!
//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//! SOFTWARE.
// Import dependencies from std::fs
use std::fs::{read_to_string, File};
// Import std::io::Write
use std::io::Write;
// Import std::path::{Path, PathBuf}
use std::path::{Path, PathBuf};
/// The main entry point.
fn main() {
let out = PathBuf::from(std::env::var_os("OUT_DIR").unwrap());
let c = read_to_string(".pico-rs").unwrap_or_default().trim().to_lowercase();
setup_target(&c, &out);
write_riscv(&out);
print_cfgs(&out);
}
/// Executes the setup target operation.
///
/// # Arguments
///
/// * `c` - Target string from config.
/// * `out` - Output path.
fn setup_target(c: &str, out: &Path) {
if c == "rp2040" {
write_rp2040(out);
} else {
write_rp2350(out);
}
}
/// Executes the write rp2040 operation.
///
/// # Arguments
///
/// * `out` - Output path.
fn write_rp2040(out: &Path) {
let b = include_bytes!("rp2040.x");
File::create(out.join("memory.x")).unwrap().write_all(b).unwrap();
println!("cargo::rustc-cfg=rp2040");
println!("cargo:rerun-if-changed=rp2040.x");
}
/// Executes the write rp2350 operation.
///
/// # Arguments
///
/// * `out` - Output path.
fn write_rp2350(out: &Path) {
let b = include_bytes!("rp2350.x");
File::create(out.join("memory.x")).unwrap().write_all(b).unwrap();
println!("cargo::rustc-cfg=rp2350");
println!("cargo:rerun-if-changed=rp2350.x");
}
/// Executes the write riscv operation.
///
/// # Arguments
///
/// * `out` - Output path.
fn write_riscv(out: &Path) {
let b = include_bytes!("rp2350_riscv.x");
File::create(out.join("rp2350_riscv.x")).unwrap().write_all(b).unwrap();
}
/// Executes the print cfgs operation.
///
/// # Arguments
///
/// * `out` - Output path.
fn print_cfgs(out: &Path) {
println!("cargo::rustc-check-cfg=cfg(rp2040)");
println!("cargo::rustc-check-cfg=cfg(rp2350)");
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=.pico-rs");
println!("cargo:rerun-if-changed=rp2350_riscv.x");
println!("cargo:rerun-if-changed=build.rs");
}
+44
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@@ -0,0 +1,44 @@
/*
* SPDX-License-Identifier: MIT OR Apache-2.0
*
* Copyright (c) 2021-2024 The rp-rs Developers
* Copyright (c) 2021 rp-rs organization
* Copyright (c) 2025 Raspberry Pi Ltd.
*/
MEMORY {
BOOT2 : ORIGIN = 0x10000000, LENGTH = 0x100
FLASH : ORIGIN = 0x10000100, LENGTH = 2048K - 0x100
RAM : ORIGIN = 0x20000000, LENGTH = 256K
SRAM4 : ORIGIN = 0x20040000, LENGTH = 4k
SRAM5 : ORIGIN = 0x20041000, LENGTH = 4k
}
EXTERN(BOOT2_FIRMWARE)
SECTIONS {
.boot2 ORIGIN(BOOT2) :
{
KEEP(*(.boot2));
} > BOOT2
} INSERT BEFORE .text;
SECTIONS {
.boot_info : ALIGN(4)
{
KEEP(*(.boot_info));
} > FLASH
} INSERT AFTER .vector_table;
_stext = ADDR(.boot_info) + SIZEOF(.boot_info);
SECTIONS {
.bi_entries : ALIGN(4)
{
__bi_entries_start = .;
KEEP(*(.bi_entries));
. = ALIGN(4);
__bi_entries_end = .;
} > FLASH
} INSERT AFTER .text;
+47
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@@ -0,0 +1,47 @@
/*
* SPDX-License-Identifier: MIT OR Apache-2.0
*
* Copyright (c) 2021-2024 The rp-rs Developers
* Copyright (c) 2021 rp-rs organization
* Copyright (c) 2025 Raspberry Pi Ltd.
*/
MEMORY {
FLASH : ORIGIN = 0x10000000, LENGTH = 2048K
RAM : ORIGIN = 0x20000000, LENGTH = 512K
SRAM4 : ORIGIN = 0x20080000, LENGTH = 4K
SRAM5 : ORIGIN = 0x20081000, LENGTH = 4K
}
SECTIONS {
.start_block : ALIGN(4)
{
__start_block_addr = .;
KEEP(*(.start_block));
} > FLASH
} INSERT AFTER .vector_table;
_stext = ADDR(.start_block) + SIZEOF(.start_block);
SECTIONS {
.bi_entries : ALIGN(4)
{
__bi_entries_start = .;
KEEP(*(.bi_entries));
. = ALIGN(4);
__bi_entries_end = .;
} > FLASH
} INSERT AFTER .text;
SECTIONS {
.end_block : ALIGN(4)
{
__end_block_addr = .;
KEEP(*(.end_block));
} > FLASH
} INSERT AFTER .uninit;
PROVIDE(start_to_end = __end_block_addr - __start_block_addr);
PROVIDE(end_to_start = __start_block_addr - __end_block_addr);
+58
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@@ -0,0 +1,58 @@
/*
* SPDX-License-Identifier: MIT OR Apache-2.0
*
* Copyright (c) 2021-2024 The rp-rs Developers
* Copyright (c) 2021 rp-rs organization
* Copyright (c) 2025 Raspberry Pi Ltd.
*/
MEMORY {
FLASH : ORIGIN = 0x10000000, LENGTH = 2048K
RAM : ORIGIN = 0x20000000, LENGTH = 512K
SRAM4 : ORIGIN = 0x20080000, LENGTH = 4K
SRAM5 : ORIGIN = 0x20081000, LENGTH = 4K
}
PROVIDE(_stext = ORIGIN(FLASH));
PROVIDE(_stack_start = ORIGIN(RAM) + LENGTH(RAM));
PROVIDE(_max_hart_id = 0);
PROVIDE(_hart_stack_size = 2K);
PROVIDE(_heap_size = 0);
PROVIDE(InstructionMisaligned = ExceptionHandler);
PROVIDE(InstructionFault = ExceptionHandler);
PROVIDE(IllegalInstruction = ExceptionHandler);
PROVIDE(Breakpoint = ExceptionHandler);
PROVIDE(LoadMisaligned = ExceptionHandler);
PROVIDE(LoadFault = ExceptionHandler);
PROVIDE(StoreMisaligned = ExceptionHandler);
PROVIDE(StoreFault = ExceptionHandler);
PROVIDE(UserEnvCall = ExceptionHandler);
PROVIDE(SupervisorEnvCall = ExceptionHandler);
PROVIDE(MachineEnvCall = ExceptionHandler);
PROVIDE(InstructionPageFault = ExceptionHandler);
PROVIDE(LoadPageFault = ExceptionHandler);
PROVIDE(StorePageFault = ExceptionHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__pre_init = default_pre_init);
PROVIDE(_setup_interrupts = default_setup_interrupts);
PROVIDE(_mp_hook = default_mp_hook);
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.text.dummy (NOLOAD) :
{
. = ABSOLUTE(_stext);
} > FLASH
}
+288
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@@ -0,0 +1,288 @@
//! Implementation module
//!
//! **File:** `board.rs`
//! **Author:** Kevin Thomas
//! **Date:** 2025
//!
//! MIT License
//!
//! Copyright (c) 2025 Kevin Thomas
//!
//! Permission is hereby granted, free of charge, to any person obtaining a copy
//! of this software and associated documentation files (the "Software"), to deal
//! in the Software without restriction, including without limitation the rights
//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//! copies of the Software, and to permit persons to whom the Software is
//! furnished to do so, subject to the following conditions:
//!
//! The above copyright notice and this permission notice shall be included in
//! all copies or substantial portions of the Software.
//!
//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//! SOFTWARE.
// SPI pure-logic helpers and constants
use spi_lib::spi;
// Digital output trait for software-controlled chip select
use embedded_hal::digital::OutputPin;
// SPI bus trait for full-duplex transfer
use embedded_hal::spi::SpiBus;
// Rate extension trait for .Hz() baud rate construction
use fugit::RateExtU32;
// Clock trait for accessing system clock frequency
use hal::Clock;
// GPIO pin types and function selectors
use hal::gpio::{FunctionNull, FunctionSio, FunctionSpi, FunctionUart, Pin, PullDown, PullNone};
// SPI peripheral type
use hal::spi::Spi;
// UART configuration and peripheral types
use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral};
// Alias our HAL crate
#[cfg(rp2350)]
// Import rp235x_hal as hal
use rp235x_hal as hal;
#[cfg(rp2040)]
// Import rp2040_hal as hal
use rp2040_hal as hal;
/// External crystal frequency in Hz (12 MHz).
pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32;
/// UART baud rate in bits per second.
pub(crate) const UART_BAUD: u32 = 115_200;
/// Delay between loopback transfers in milliseconds.
pub(crate) const POLL_MS: u32 = 1_000;
/// Type alias for the configured TX pin (GPIO 0, UART function, no pull).
pub(crate) type TxPin = Pin<hal::gpio::bank0::Gpio0, FunctionUart, PullNone>;
/// Type alias for the configured RX pin (GPIO 1, UART function, no pull).
pub(crate) type RxPin = Pin<hal::gpio::bank0::Gpio1, FunctionUart, PullNone>;
/// Type alias for the default TX pin state from `Pins::new()`.
pub(crate) type TxPinDefault = Pin<hal::gpio::bank0::Gpio0, FunctionNull, PullDown>;
/// Type alias for the default RX pin state from `Pins::new()`.
pub(crate) type RxPinDefault = Pin<hal::gpio::bank0::Gpio1, FunctionNull, PullDown>;
/// Type alias for the configured SPI RX pin (GPIO16).
pub(crate) type MisoPin = Pin<hal::gpio::bank0::Gpio16, FunctionSpi, PullNone>;
/// Type alias for the configured SPI chip-select pin (GPIO17).
pub(crate) type CsPin = Pin<hal::gpio::bank0::Gpio17, FunctionSio<hal::gpio::SioOutput>, PullNone>;
/// Type alias for the configured SPI clock pin (GPIO18).
pub(crate) type SckPin = Pin<hal::gpio::bank0::Gpio18, FunctionSpi, PullNone>;
/// Type alias for the configured SPI TX pin (GPIO19).
pub(crate) type MosiPin = Pin<hal::gpio::bank0::Gpio19, FunctionSpi, PullNone>;
/// Type alias for the fully-enabled UART0 peripheral with TX/RX p.
pub(crate) type EnabledUart = UartPeripheral<Enabled, hal::pac::UART0, (TxPin, RxPin)>;
/// Type alias for the SPI0 peripheral configured in 8-bit master mode.
pub(crate) type EnabledSpi = Spi<hal::spi::Enabled, hal::pac::SPI0, (MosiPin, MisoPin, SckPin), 8>;
/// Initialise system clocks and PLLs from the external 12 MHz crystal.
pub(crate) fn init_clocks(
xosc: hal::pac::XOSC, clocks: hal::pac::CLOCKS, pll_sys: hal::pac::PLL_SYS, pll_usb: hal::pac::PLL_USB,
resets: &mut hal::pac::RESETS, watchdog: &mut hal::Watchdog,
) -> hal::clocks::ClocksManager {
hal::clocks::init_clocks_and_plls(XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog).unwrap()
}
/// Unlock the GPIO bank and return the pin set.
pub(crate) fn init_pins(
io: hal::pac::IO_BANK0, pads: hal::pac::PADS_BANK0, sio: hal::pac::SIO, rst: &mut hal::pac::RESETS
) -> hal::gpio::Pins {
hal::gpio::Pins::new(io, pads, hal::Sio::new(sio).gpio_bank0, rst)
}
/// Initialise UART0 for serial output.
pub(crate) fn init_uart(
uart0: hal::pac::UART0, tx: TxPinDefault, rx: RxPinDefault, rst: &mut hal::pac::RESETS, c: &hal::clocks::ClocksManager
) -> EnabledUart {
let pins = (tx.reconfigure::<FunctionUart, PullNone>(), rx.reconfigure::<FunctionUart, PullNone>());
let cfg = UartConfig::new(UART_BAUD.Hz(), DataBits::Eight, None, StopBits::One);
UartPeripheral::new(uart0, pins, rst).enable(cfg, c.peripheral_clock.freq()).unwrap()
}
/// Create a blocking delay timer from the ARM SysTick peripheral.
///
/// # Arguments
///
/// * `clocks` - The `clocks` parameter.
///
/// # Returns
///
/// A value of type `cortex_m::delay::Delay`.
///
/// # Arguments
///
/// * `clocks` - The `clocks` parameter.
///
/// # Returns
///
/// A value of type `cortex_m::delay::Delay`.
pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay::Delay {
let core = cortex_m::Peripherals::take().unwrap();
cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz())
}
/// Executes the reconfigure miso, sck, and mosi pins from default to spi operation.
fn reconfigure_data_pins(
miso: hal::gpio::Pin<hal::gpio::bank0::Gpio16, FunctionNull, PullDown>,
sck: hal::gpio::Pin<hal::gpio::bank0::Gpio18, FunctionNull, PullDown>,
mosi: hal::gpio::Pin<hal::gpio::bank0::Gpio19, FunctionNull, PullDown>,
) -> (MosiPin, MisoPin, SckPin) {
(mosi.reconfigure::<FunctionSpi, PullNone>(), miso.reconfigure::<FunctionSpi, PullNone>(), sck.reconfigure::<FunctionSpi, PullNone>())
}
/// Reconfigure a pin as digital output and de-assert chip select (drive high).
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
/// * `FunctionNull` - The `FunctionNull` parameter.
/// * `PullDown>` - The `PullDown>` parameter.
///
/// # Returns
///
/// A value of type `CsPin`.
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
/// * `FunctionNull` - The `FunctionNull` parameter.
/// * `PullDown>` - The `PullDown>` parameter.
///
/// # Returns
///
/// A value of type `CsPin`.
fn init_cs_pin(cs: hal::gpio::Pin<hal::gpio::bank0::Gpio17, FunctionNull, PullDown>) -> CsPin {
let mut cs = cs.reconfigure::<FunctionSio<hal::gpio::SioOutput>, PullNone>();
let _ = cs.set_high(); cs
}
/// Configure SPI0 and the software-controlled chip-select pin.
pub(crate) fn init_spi(
spi0: hal::pac::SPI0, miso: hal::gpio::Pin<hal::gpio::bank0::Gpio16, FunctionNull, PullDown>,
cs: hal::gpio::Pin<hal::gpio::bank0::Gpio17, FunctionNull, PullDown>, sck: hal::gpio::Pin<hal::gpio::bank0::Gpio18, FunctionNull, PullDown>,
mosi: hal::gpio::Pin<hal::gpio::bank0::Gpio19, FunctionNull, PullDown>,
resets: &mut hal::pac::RESETS, clocks: &hal::clocks::ClocksManager,
) -> (EnabledSpi, CsPin) {
let (mosi, miso, sck) = reconfigure_data_pins(miso, sck, mosi);
let s = Spi::<_, _, _, 8>::new(spi0, (mosi, miso, sck)).init(resets, clocks.peripheral_clock.freq(), spi::SPI_BAUD_HZ.Hz(), embedded_hal::spi::MODE_0);
(s, init_cs_pin(cs))
}
/// Drive chip select active (low).
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
fn cs_select(cs: &mut CsPin) {
let _ = cs.set_low();
}
/// Drive chip select inactive (high).
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
///
/// # Arguments
///
/// * `cs` - The `cs` parameter.
fn cs_deselect(cs: &mut CsPin) {
let _ = cs.set_high();
}
/// Execute a full-duplex SPI transfer with chip-select framing.
///
/// # Arguments
///
/// * `spi_dev` - The `spi_dev` parameter.
/// * `cs` - The `cs` parameter.
/// * `rx` - The `rx` parameter.
///
/// # Arguments
///
/// * `spi_dev` - The `spi_dev` parameter.
/// * `cs` - The `cs` parameter.
/// * `rx` - The `rx` parameter.
fn execute_transfer(spi_dev: &mut EnabledSpi, cs: &mut CsPin, rx: &mut [u8]) {
cs_select(cs);
let _ = spi_dev.transfer(rx, spi::TX_MESSAGE);
cs_deselect(cs);
}
/// Format and print the TX and RX lines over UART.
///
/// # Arguments
///
/// * `uart` - The `uart` parameter.
/// * `rx` - The `rx` parameter.
///
/// # Arguments
///
/// * `uart` - The `uart` parameter.
/// * `rx` - The `rx` parameter.
fn print_transfer_result(uart: &EnabledUart, rx: &[u8]) {
let mut line_buf = [0u8; 24];
let tx_len = spi::format_tx_line(&mut line_buf, spi::TX_MESSAGE);
uart.write_full_blocking(&line_buf[..tx_len]);
let rx_len = spi::format_rx_line(&mut line_buf, rx);
uart.write_full_blocking(&line_buf[..rx_len]);
}
/// Perform one SPI loopback transfer and print TX/RX text over UART.
pub(crate) fn loopback_transfer(
spi_dev: &mut EnabledSpi,
cs: &mut CsPin,
uart: &EnabledUart,
delay: &mut cortex_m::delay::Delay,
) {
let mut rx = [0u8; spi::TX_MESSAGE.len()];
execute_transfer(spi_dev, cs, &mut rx);
print_transfer_result(uart, &rx);
spi::clear_rx_buffer(&mut rx);
delay.delay_ms(POLL_MS);
}
/// Initialise all peripherals and run the SPI loopback demo.
///
/// # Arguments
///
/// * `pac` - PAC Peripherals singleton (consumed).
///
/// # Returns
///
/// A value of type `!`.
///
/// # Arguments
///
/// * `pac` - The `pac` parameter.
///
/// # Returns
///
/// A value of type `!`.
pub(crate) fn run(mut p: hal::pac::Peripherals) -> ! {
let c = init_clocks(p.XOSC, p.CLOCKS, p.PLL_SYS, p.PLL_USB, &mut p.RESETS, &mut hal::Watchdog::new(p.WATCHDOG));
let pins = init_pins(p.IO_BANK0, p.PADS_BANK0, p.SIO, &mut p.RESETS);
let (u, mut d) = (init_uart(p.UART0, pins.gpio0, pins.gpio1, &mut p.RESETS, &c), init_delay(&c));
let (mut s, mut cs) = init_spi(p.SPI0, pins.gpio16, pins.gpio17, pins.gpio18, pins.gpio19, &mut p.RESETS, &c);
u.write_full_blocking(b"SPI driver initialized on SPI0 at 1000000 Hz\r\n");
loop { loopback_transfer(&mut s, &mut cs, &u, &mut d); }
}
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//! Driver crate
#![deny(missing_docs)]
#![deny(clippy::missing_docs_in_private_items)]
#![cfg_attr(not(test), no_std)]
pub mod spi;
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//! Driver crate
#![deny(missing_docs)]
#![deny(clippy::missing_docs_in_private_items)]
//! Implementation module
//!
//! **File:** `main.rs`
//! **Author:** Kevin Thomas
//! **Date:** 2025
//!
//! MIT License
//!
//! Copyright (c) 2025 Kevin Thomas
//!
//! Permission is hereby granted, free of charge, to any person obtaining a copy
//! of this software and associated documentation files (the "Software"), to deal
//! in the Software without restriction, including without limitation the rights
//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//! copies of the Software, and to permit persons to whom the Software is
//! furnished to do so, subject to the following conditions:
//!
//! The above copyright notice and this permission notice shall be included in
//! all copies or substantial portions of the Software.
//!
//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//! SOFTWARE.
#![no_std]
#![no_main]
// Board-level helpers: constants, type aliases, and init functions
mod board;
// SPI driver module — suppress warnings for unused public API functions
// Debugging output over RTT
use defmt_rtt as _;
// Panic handler for RISC-V targets
#[cfg(target_arch = "riscv32")]
// Import panic_halt as _
use panic_halt as _;
// Panic handler for ARM targets
#[cfg(target_arch = "arm")]
// Import panic_probe as _
use panic_probe as _;
// HAL entry-point macro
use hal::entry;
// Alias our HAL crate
#[cfg(rp2350)]
// Import rp235x_hal as hal
use rp235x_hal as hal;
#[cfg(rp2040)]
// Import rp2040_hal as hal
use rp2040_hal as hal;
/// Second-stage boot loader for RP2040
#[unsafe(link_section = ".boot2")]
#[used]
#[cfg(rp2040)]
pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
/// Boot metadata for the RP2350 Boot ROM
#[unsafe(link_section = ".start_block")]
#[used]
#[cfg(rp2350)]
pub static IMAGE_DEF: hal::block::ImageDef = hal::block::ImageDef::secure_exe();
/// Application entry point for the SPI loopback demo.
///
/// # Returns
///
/// A value of type `!`.
///
/// # Returns
///
/// A value of type `!`.
#[entry]
fn main() -> ! {
board::run(hal::pac::Peripherals::take().unwrap())
}
/// Picotool binary info metadata
#[unsafe(link_section = ".bi_entries")]
#[used]
pub static PICOTOOL_ENTRIES: [hal::binary_info::EntryAddr; 5] = [
hal::binary_info::rp_cargo_bin_name!(),
hal::binary_info::rp_cargo_version!(),
hal::binary_info::rp_program_description!(c"SPI Loopback Demo"),
hal::binary_info::rp_cargo_homepage_url!(),
hal::binary_info::rp_program_build_attribute!(),
];
#[cfg(test)]
mod tests {
// Import all parent module items
use super::*;
}
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//! Implementation module
//!
//! **File:** `spi.rs`
//! **Author:** Kevin Thomas
//! **Date:** 2025
//!
//! MIT License
//!
//! Copyright (c) 2025 Kevin Thomas
//!
//! Permission is hereby granted, free of charge, to any person obtaining a copy
//! of this software and associated documentation files (the "Software"), to deal
//! in the Software without restriction, including without limitation the rights
//! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//! copies of the Software, and to permit persons to whom the Software is
//! furnished to do so, subject to the following conditions:
//!
//! The above copyright notice and this permission notice shall be included in
//! all copies or substantial portions of the Software.
//!
//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//! SOFTWARE.
/// SPI port number used by the loopback demo.
pub const SPI_PORT: u8 = 0;
/// SPI clock frequency used by the loopback demo.
pub const SPI_BAUD_HZ: u32 = 1_000_000;
/// GPIO pin number for MISO.
pub const PIN_MISO: u8 = 16;
/// GPIO pin number for chip select.
pub const PIN_CS: u8 = 17;
/// GPIO pin number for SCK.
pub const PIN_SCK: u8 = 18;
/// GPIO pin number for MOSI.
pub const PIN_MOSI: u8 = 19;
/// Fixed transmit message used by the SPI loopback demo.
pub const TX_MESSAGE: &[u8; 16] = b"SPI loopback OK\0";
/// Return true when the selected SPI port is supported by the driver.
///
/// # Arguments
///
/// * `port` - The `port` parameter.
///
/// # Returns
///
/// `true` if successful or set, `false` otherwise.
///
/// # Arguments
///
/// * `port` - The `port` parameter.
///
/// # Returns
///
/// `true` if successful or set, `false` otherwise.
#[inline]
pub fn is_valid_port(port: u8) -> bool {
port <= 1
}
/// Clear a receive buffer to all zeros.
///
/// # Arguments
///
/// * `rx` - The `rx` parameter.
///
/// # Arguments
///
/// * `rx` - The `rx` parameter.
#[inline]
pub fn clear_rx_buffer(rx: &mut [u8]) {
rx.fill(0);
}
/// Copy `src` into `dst` up to the minimum length of both slices.
///
/// # Arguments
///
/// * `src` - The `src` parameter.
/// * `dst` - The `dst` parameter.
///
/// # Arguments
///
/// * `src` - The `src` parameter.
/// * `dst` - The `dst` parameter.
#[inline]
pub fn copy_transfer_result(src: &[u8], dst: &mut [u8]) {
let len = core::cmp::min(src.len(), dst.len()); dst[..len].copy_from_slice(&src[..len]);
}
/// Format the `TX:` line with trailing CRLF.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `tx` - The `tx` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `tx` - The `tx` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
pub fn format_tx_line(buf: &mut [u8], tx: &[u8]) -> usize {
format_line(buf, b"TX: ", tx, false)
}
/// Format the `RX:` line with an extra blank line after it.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `rx` - The `rx` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `rx` - The `rx` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
pub fn format_rx_line(buf: &mut [u8], rx: &[u8]) -> usize {
format_line(buf, b"RX: ", rx, true)
}
/// Format a single ASCII line for UART output.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `prefix` - The `prefix` parameter.
/// * `text` - The `text` parameter.
/// * `extra_blank_line` - The `extra_blank_line` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `prefix` - The `prefix` parameter.
/// * `text` - The `text` parameter.
/// * `extra_blank_line` - The `extra_blank_line` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
fn format_line(buf: &mut [u8], prefix: &[u8], text: &[u8], extra_blank_line: bool) -> usize {
let mut pos = 0; buf[pos..pos + prefix.len()].copy_from_slice(prefix); pos += prefix.len();
pos += copy_c_string(&mut buf[pos..], text); pos += append_crlf(&mut buf[pos..], extra_blank_line);
pos
}
/// Copy bytes from `text` up to the first NUL into `buf`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `text` - The `text` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `text` - The `text` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
fn copy_c_string(buf: &mut [u8], text: &[u8]) -> usize {
let len = c_string_len(text); buf[..len].copy_from_slice(&text[..len]); len
}
/// Append CRLF (and optionally a second blank CRLF) to `buf`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `extra` - The `extra` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `buf` - The `buf` parameter.
/// * `extra` - The `extra` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
fn append_crlf(buf: &mut [u8], extra: bool) -> usize {
buf[0] = b'\r'; buf[1] = b'\n';
if extra { buf[2] = b'\r'; buf[3] = b'\n'; 4 } else { 2 }
}
/// Return the length up to the first NUL byte or full slice length.
///
/// # Arguments
///
/// * `text` - The `text` parameter.
///
/// # Returns
///
/// A value of type `usize`.
///
/// # Arguments
///
/// * `text` - The `text` parameter.
///
/// # Returns
///
/// A value of type `usize`.
#[inline]
fn c_string_len(text: &[u8]) -> usize {
let mut len = 0usize;
while len < text.len() && text[len] != 0 { len += 1; }
len
}
#[cfg(test)]
mod tests {
// Import all parent module items
use super::*;
/// Executes the valid ports are zero and one operation.
#[test]
fn valid_ports_are_zero_and_one() {
assert!(is_valid_port(0));
assert!(is_valid_port(1));
assert!(!is_valid_port(2));
}
/// Executes the clear rx buffer zeroes all bytes operation.
#[test]
fn clear_rx_buffer_zeroes_all_bytes() {
let mut rx = [1u8, 2, 3, 4];
clear_rx_buffer(&mut rx);
assert_eq!(rx, [0u8; 4]);
}
/// Executes the copy transfer result copies common prefix operation.
#[test]
fn copy_transfer_result_copies_common_prefix() {
let src = b"abcd";
let mut dst = [0u8; 3];
copy_transfer_result(src, &mut dst);
assert_eq!(&dst, b"abc");
}
/// Executes the format tx line omits trailing nul operation.
#[test]
fn format_tx_line_omits_trailing_nul() {
let mut buf = [0u8; 32];
let n = format_tx_line(&mut buf, TX_MESSAGE);
assert_eq!(&buf[..n], b"TX: SPI loopback OK\r\n");
}
/// Executes the format rx line adds blank line operation.
#[test]
fn format_rx_line_adds_blank_line() {
let mut buf = [0u8; 32];
let n = format_rx_line(&mut buf, TX_MESSAGE);
assert_eq!(&buf[..n], b"RX: SPI loopback OK\r\n\r\n");
}
/// Executes the c string len stops at nul operation.
#[test]
fn c_string_len_stops_at_nul() {
assert_eq!(c_string_len(b"abc\0xyz"), 3);
}
}