//! @file board.rs //! @brief Board-level HAL helpers for the PWM driver //! @author Kevin Thomas //! @date 2025 //! //! MIT License //! //! Copyright (c) 2025 Kevin Thomas //! //! Permission is hereby granted, free of charge, to any person obtaining a copy //! of this software and associated documentation files (the "Software"), to deal //! in the Software without restriction, including without limitation the rights //! to use, copy, modify, merge, publish, distribute, sublicense, and/or sell //! copies of the Software, and to permit persons to whom the Software is //! furnished to do so, subject to the following conditions: //! //! The above copyright notice and this permission notice shall be included in //! all copies or substantial portions of the Software. //! //! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR //! IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, //! FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE //! AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER //! LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, //! OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE //! SOFTWARE. // PWM duty-cycle trait for .set_duty_cycle() use embedded_hal::pwm::SetDutyCycle; // Rate extension trait for .Hz() baud rate construction use fugit::RateExtU32; // Clock trait for accessing system clock frequency use hal::Clock; // GPIO pin types and function selectors use hal::gpio::{FunctionNull, FunctionUart, Pin, PullDown, PullNone}; // UART configuration and peripheral types use hal::uart::{DataBits, Enabled, StopBits, UartConfig, UartPeripheral}; // Alias our HAL crate #[cfg(rp2350)] use rp235x_hal as hal; #[cfg(rp2040)] use rp2040_hal as hal; /// External crystal frequency in Hz (12 MHz). pub(crate) const XTAL_FREQ_HZ: u32 = 12_000_000u32; /// UART baud rate in bits per second. pub(crate) const UART_BAUD: u32 = 115_200; /// Desired PWM output frequency in Hz. pub(crate) const PWM_FREQ_HZ: u32 = 1000; /// PWM counter wrap value (period - 1). pub(crate) const PWM_WRAP: u32 = 10000 - 1; /// Type alias for the configured TX pin (GPIO 0, UART function, no pull). pub(crate) type TxPin = Pin; /// Type alias for the configured RX pin (GPIO 1, UART function, no pull). pub(crate) type RxPin = Pin; /// Type alias for the default TX pin state from `Pins::new()`. pub(crate) type TxPinDefault = Pin; /// Type alias for the default RX pin state from `Pins::new()`. pub(crate) type RxPinDefault = Pin; /// Type alias for the fully-enabled UART0 peripheral with TX/RX pins. pub(crate) type EnabledUart = UartPeripheral; /// Initialise system clocks and PLLs from the external 12 MHz crystal. /// /// # Arguments /// /// * `xosc` - XOSC peripheral singleton. /// * `clocks` - CLOCKS peripheral singleton. /// * `pll_sys` - PLL_SYS peripheral singleton. /// * `pll_usb` - PLL_USB peripheral singleton. /// * `resets` - Mutable reference to the RESETS peripheral. /// * `watchdog` - Mutable reference to the watchdog timer. /// /// # Returns /// /// Configured clocks manager. /// /// # Panics /// /// Panics if clock initialisation fails. pub(crate) fn init_clocks( xosc: hal::pac::XOSC, clocks: hal::pac::CLOCKS, pll_sys: hal::pac::PLL_SYS, pll_usb: hal::pac::PLL_USB, resets: &mut hal::pac::RESETS, watchdog: &mut hal::Watchdog, ) -> hal::clocks::ClocksManager { hal::clocks::init_clocks_and_plls( XTAL_FREQ_HZ, xosc, clocks, pll_sys, pll_usb, resets, watchdog, ) .unwrap() } /// Unlock the GPIO bank and return the pin set. /// /// # Arguments /// /// * `io_bank0` - IO_BANK0 peripheral singleton. /// * `pads_bank0` - PADS_BANK0 peripheral singleton. /// * `sio` - SIO peripheral singleton. /// * `resets` - Mutable reference to the RESETS peripheral. /// /// # Returns /// /// GPIO pin set for the entire bank. pub(crate) fn init_pins( io_bank0: hal::pac::IO_BANK0, pads_bank0: hal::pac::PADS_BANK0, sio: hal::pac::SIO, resets: &mut hal::pac::RESETS, ) -> hal::gpio::Pins { let sio = hal::Sio::new(sio); hal::gpio::Pins::new(io_bank0, pads_bank0, sio.gpio_bank0, resets) } /// Initialise UART0 for serial output (stdio equivalent). /// /// # Arguments /// /// * `uart0` - PAC UART0 peripheral singleton. /// * `tx_pin` - GPIO pin to use as UART0 TX (GPIO 0). /// * `rx_pin` - GPIO pin to use as UART0 RX (GPIO 1). /// * `resets` - Mutable reference to the RESETS peripheral. /// * `clocks` - Reference to the initialised clock configuration. /// /// # Returns /// /// Enabled UART0 peripheral ready for blocking writes. /// /// # Panics /// /// Panics if the HAL cannot achieve the requested baud rate. pub(crate) fn init_uart( uart0: hal::pac::UART0, tx_pin: TxPinDefault, rx_pin: RxPinDefault, resets: &mut hal::pac::RESETS, clocks: &hal::clocks::ClocksManager, ) -> EnabledUart { let pins = ( tx_pin.reconfigure::(), rx_pin.reconfigure::(), ); let cfg = UartConfig::new(UART_BAUD.Hz(), DataBits::Eight, None, StopBits::One); UartPeripheral::new(uart0, pins, resets) .enable(cfg, clocks.peripheral_clock.freq()) .unwrap() } /// Create a blocking delay timer from the ARM SysTick peripheral. /// /// # Arguments /// /// * `clocks` - Reference to the initialised clock configuration. /// /// # Returns /// /// Blocking delay provider. /// /// # Panics /// /// Panics if the cortex-m core peripherals have already been taken. pub(crate) fn init_delay(clocks: &hal::clocks::ClocksManager) -> cortex_m::delay::Delay { let core = cortex_m::Peripherals::take().unwrap(); cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().to_Hz()) } /// Format a duty percentage into a fixed byte buffer as "Duty: NNN%\r\n". /// /// # Arguments /// /// * `buf` - Mutable byte slice (must be at least 16 bytes). /// * `duty` - Duty cycle percentage to format. /// /// # Returns /// /// Number of bytes written into the buffer. pub(crate) fn format_duty(buf: &mut [u8], duty: u8) -> usize { let prefix = b"Duty: "; buf[..6].copy_from_slice(prefix); let mut pos = 6; if duty >= 100 { buf[pos] = b'1'; pos += 1; buf[pos] = b'0'; pos += 1; buf[pos] = b'0'; pos += 1; } else if duty >= 10 { buf[pos] = b' '; pos += 1; buf[pos] = b'0' + duty / 10; pos += 1; buf[pos] = b'0' + duty % 10; pos += 1; } else { buf[pos] = b' '; pos += 1; buf[pos] = b' '; pos += 1; buf[pos] = b'0' + duty; pos += 1; } buf[pos] = b'%'; pos += 1; buf[pos] = b'\r'; pos += 1; buf[pos] = b'\n'; pos += 1; pos } /// Sweep the PWM duty cycle from 0% to 100% in steps of 5. /// /// # Arguments /// /// * `uart` - UART peripheral for serial output. /// * `channel` - PWM channel to set duty on. /// * `delay` - Delay provider for 50 ms pauses. /// * `buf` - Scratch buffer for formatting output. pub(crate) fn sweep_up( uart: &EnabledUart, channel: &mut impl SetDutyCycle, delay: &mut cortex_m::delay::Delay, buf: &mut [u8; 16], ) { let mut duty: u8 = 0; while duty <= 100 { let level = crate::pwm::duty_to_level(duty, PWM_WRAP) as u16; channel.set_duty_cycle(level).ok(); let n = format_duty(buf, duty); uart.write_full_blocking(&buf[..n]); delay.delay_ms(50u32); duty += 5; } } /// Sweep the PWM duty cycle from 100% to 0% in steps of 5. /// /// # Arguments /// /// * `uart` - UART peripheral for serial output. /// * `channel` - PWM channel to set duty on. /// * `delay` - Delay provider for 50 ms pauses. /// * `buf` - Scratch buffer for formatting output. pub(crate) fn sweep_down( uart: &EnabledUart, channel: &mut impl SetDutyCycle, delay: &mut cortex_m::delay::Delay, buf: &mut [u8; 16], ) { let mut duty: i8 = 100; while duty >= 0 { let level = crate::pwm::duty_to_level(duty as u8, PWM_WRAP) as u16; channel.set_duty_cycle(level).ok(); let n = format_duty(buf, duty as u8); uart.write_full_blocking(&buf[..n]); delay.delay_ms(50u32); duty -= 5; } } // End of file