mirror of
https://github.com/mytechnotalent/Embedded-Hacking.git
synced 2026-05-22 07:37:00 +02:00
Kevin Thomas
276 lines
10 KiB
C
276 lines
10 KiB
C
/**
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* @file rp2350.h
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* @brief RP2350 Device Peripheral Access Layer Header File.
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* @author Kevin Thomas
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* @date 2026
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*
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* Memory-mapped register structures and peripheral base addresses
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* for the RP2350 microcontroller (Cortex-M33 dual-core). All
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* register offsets verified against the RP2350 datasheet
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* (RP-008373-DS-2).
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*
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* MIT License
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*
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* Copyright (c) 2026 Kevin Thomas
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __RP2350_H
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#define __RP2350_H
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#include <stdint.h>
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#include <stdbool.h>
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/*!< Defines 'read / write' permissions */
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#define __IO volatile
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/*!< Stack addresses */
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#define STACK_TOP 0x20082000UL
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#define STACK_LIMIT 0x2007A000UL
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/*!< Memory map */
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#define XIP_BASE 0x10000000UL
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#define SRAM_BASE 0x20000000UL
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#define SIO_BASE 0xD0000000UL
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#define PPB_BASE 0xE0000000UL
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/*!< APB peripherals */
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#define CLOCKS_BASE 0x40010000UL
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#define RESETS_BASE 0x40020000UL
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#define IO_BANK0_BASE 0x40028000UL
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#define PADS_BANK0_BASE 0x40038000UL
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#define XOSC_BASE 0x40048000UL
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#define UART0_BASE 0x40070000UL
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#define TICKS_BASE 0x40108000UL
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#define TIMER0_BASE 0x400B0000UL
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/*!< Atomic register alias offsets */
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#define ATOMIC_SET_OFFSET 0x2000UL
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#define ATOMIC_CLR_OFFSET 0x3000UL
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/**
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* @brief XOSC (External Crystal Oscillator)
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*/
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typedef struct
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{
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__IO uint32_t CTRL; // Control register Address offset: 0x00
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__IO uint32_t STATUS; // Status register Address offset: 0x04
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__IO uint32_t DORMANT; // Dormant mode Address offset: 0x08
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__IO uint32_t STARTUP; // Startup delay Address offset: 0x0C
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__IO uint32_t COUNT; // Frequency count Address offset: 0x10
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} XOSC_TypeDef;
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/**
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* @brief CLOCKS
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*/
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typedef struct
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{
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__IO uint32_t RESERVED0[12]; // GPOUT0..GPOUT3 registers Address offset: 0x00-0x2C
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__IO uint32_t CLK_REF_CTRL; // Reference clock control Address offset: 0x30
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__IO uint32_t RESERVED1[5]; // CLK_REF_DIV..CLK_SYS_SELECTED Address offset: 0x34-0x44
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__IO uint32_t CLK_PERI_CTRL; // Peripheral clock control Address offset: 0x48
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} CLOCKS_TypeDef;
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/**
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* @brief RESETS
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*/
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typedef struct
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{
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__IO uint32_t RESET; // Reset control Address offset: 0x00
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__IO uint32_t WDSEL; // Watchdog select Address offset: 0x04
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__IO uint32_t RESET_DONE; // Reset done status Address offset: 0x08
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} RESETS_TypeDef;
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/**
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* @brief IO_BANK0 GPIO Control (one per GPIO)
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*/
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typedef struct
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{
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__IO uint32_t STATUS; // GPIO status Address offset: 0x00
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__IO uint32_t CTRL; // GPIO control Address offset: 0x04
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} IO_BANK0_GPIO_TypeDef;
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/**
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* @brief IO_BANK0
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*/
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typedef struct
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{
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IO_BANK0_GPIO_TypeDef GPIO[30]; // GPIO 0-29 status/ctrl pairs Address offset: 0x000-0x0E8
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} IO_BANK0_TypeDef;
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/**
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* @brief PADS_BANK0
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*/
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typedef struct
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{
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__IO uint32_t VOLTAGE_SELECT; // Voltage select Address offset: 0x00
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__IO uint32_t GPIO[30]; // GPIO 0-29 pad control Address offset: 0x04-0x78
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} PADS_BANK0_TypeDef;
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/**
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* @brief TIMER0 (System Timer)
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*/
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typedef struct
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{
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__IO uint32_t TIMEHW; // Write to bits 63:32 of time (no side effects) Address offset: 0x00
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__IO uint32_t TIMELW; // Write to bits 31:0 of time (triggers latch) Address offset: 0x04
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__IO uint32_t TIMEHR; // Read bits 63:32 of time (latched on TIMELR) Address offset: 0x08
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__IO uint32_t TIMELR; // Read bits 31:0 of time (latches TIMEHR) Address offset: 0x0C
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__IO uint32_t ALARM0; // Alarm 0 target (arms on write) Address offset: 0x10
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__IO uint32_t ALARM1; // Alarm 1 target (arms on write) Address offset: 0x14
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__IO uint32_t ALARM2; // Alarm 2 target (arms on write) Address offset: 0x18
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__IO uint32_t ALARM3; // Alarm 3 target (arms on write) Address offset: 0x1C
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__IO uint32_t ARMED; // Armed status / disarm by writing 1 Address offset: 0x20
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__IO uint32_t TIMERAWH; // Raw read bits 63:32 (no latch) Address offset: 0x24
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__IO uint32_t TIMERAWL; // Raw read bits 31:0 (no latch) Address offset: 0x28
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__IO uint32_t DBGPAUSE; // Debug pause control Address offset: 0x2C
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__IO uint32_t PAUSE; // Pause timer Address offset: 0x30
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__IO uint32_t LOCKED; // Lock writes to timer Address offset: 0x34
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__IO uint32_t SOURCE; // Clock source select Address offset: 0x38
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__IO uint32_t INTR; // Raw interrupts Address offset: 0x3C
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__IO uint32_t INTE; // Interrupt enable Address offset: 0x40
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__IO uint32_t INTF; // Interrupt force Address offset: 0x44
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__IO uint32_t INTS; // Interrupt status after masking & forcing Address offset: 0x48
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} TIMER_TypeDef;
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/**
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* @brief TICKS (Tick Generator entry, one per source)
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*/
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typedef struct
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{
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__IO uint32_t CTRL; // Enable tick generator (bit 0) Address offset: 0x00
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__IO uint32_t CYCLES; // Number of CLK_REF cycles per tick (bits 8:0) Address offset: 0x04
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__IO uint32_t COUNT; // Running counter of ticks (read-only) Address offset: 0x08
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} TICKS_Entry_TypeDef;
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/**
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* @brief Peripheral Definitions
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*/
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#define XOSC ((XOSC_TypeDef *) XOSC_BASE)
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#define CLOCKS ((CLOCKS_TypeDef *) CLOCKS_BASE)
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#define RESETS ((RESETS_TypeDef *) RESETS_BASE)
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#define IO_BANK0 ((IO_BANK0_TypeDef *) IO_BANK0_BASE)
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#define PADS_BANK0 ((PADS_BANK0_TypeDef *) PADS_BANK0_BASE)
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#define SIO ((volatile uint32_t *) SIO_BASE)
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#define CPACR ((volatile uint32_t *) (PPB_BASE + 0x0ED88UL))
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#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
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/**
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* @brief TICKS entries (indexed from TICKS_BASE, 12-byte stride)
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*/
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#define TICKS_TIMER0 ((TICKS_Entry_TypeDef *) (TICKS_BASE + 0x18UL))
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/**
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* @brief NVIC registers
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*/
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#define NVIC_ISER0 ((volatile uint32_t *) (PPB_BASE + 0x0E100UL))
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/**
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* @brief XOSC bit definitions
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*/
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#define XOSC_STATUS_STABLE_SHIFT 31U
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/**
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* @brief CPACR bit definitions
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*/
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#define CPACR_CP0_SHIFT 0U
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#define CPACR_CP1_SHIFT 1U
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/**
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* @brief CLK_REF bit definitions
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*/
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#define CLK_REF_CTRL_SRC_XOSC 2U
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/**
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* @brief CLOCKS bit definitions
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*/
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#define CLK_PERI_CTRL_ENABLE_SHIFT 11U
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#define CLK_PERI_CTRL_AUXSRC_SHIFT 5U
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#define CLK_PERI_CTRL_AUXSRC_MASK (0x07U << CLK_PERI_CTRL_AUXSRC_SHIFT)
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#define CLK_PERI_CTRL_AUXSRC_XOSC 4U
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/**
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* @brief RESETS bit definitions
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*/
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#define RESETS_RESET_IO_BANK0_SHIFT 6U
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#define RESETS_RESET_PADS_BANK0_SHIFT 9U
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#define RESETS_RESET_UART0_SHIFT 26U
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#define RESETS_RESET_TIMER0_SHIFT 23U
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/**
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* @brief IO_BANK0 bit definitions
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*/
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#define IO_BANK0_CTRL_FUNCSEL_MASK 0x1FU
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#define IO_BANK0_CTRL_FUNCSEL_UART 0x02U
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#define IO_BANK0_CTRL_FUNCSEL_SIO 0x05U
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#define IO_BANK0_CTRL_FUNCSEL_NULL 0x1FU
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/**
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* @brief PADS_BANK0 bit definitions
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*/
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#define PADS_BANK0_OD_SHIFT 7U
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#define PADS_BANK0_IE_SHIFT 6U
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#define PADS_BANK0_ISO_SHIFT 8U
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#define PADS_BANK0_PUE_SHIFT 3U
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#define PADS_BANK0_PDE_SHIFT 2U
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/**
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* @brief SIO GPIO register offsets (word indices from SIO_BASE)
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*/
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#define SIO_GPIO_OUT_SET_OFFSET (0x018U / 4U)
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#define SIO_GPIO_OUT_CLR_OFFSET (0x020U / 4U)
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#define SIO_GPIO_OE_SET_OFFSET (0x038U / 4U)
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/**
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* @brief UART register offsets (word indices from UART0_BASE)
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*/
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#define UART_DR_OFFSET (0x000U / 4U)
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#define UART_FR_OFFSET (0x018U / 4U)
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#define UART_IBRD_OFFSET (0x024U / 4U)
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#define UART_FBRD_OFFSET (0x028U / 4U)
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#define UART_LCR_H_OFFSET (0x02CU / 4U)
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#define UART_CR_OFFSET (0x030U / 4U)
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/**
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* @brief UART flag register bit definitions
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*/
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#define UART_FR_TXFF_MASK 32U
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#define UART_FR_RXFE_MASK 16U
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/**
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* @brief UART line control and enable values
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*/
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#define UART_LCR_H_8N1_FIFO 0x70U
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#define UART_CR_ENABLE ((3U << 8) | 1U)
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/**
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* @brief TIMER0 bit definitions
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*/
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#define TIMER0_ALARM0_IRQ 0U
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#define TIMER_INTE_ALARM0_SHIFT 0U
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#define TIMER_INTR_ALARM0_MASK (1U << 0)
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/**
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* @brief TICKS bit definitions
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*/
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#define TICKS_CTRL_ENABLE_SHIFT 0U
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#define TICKS_TIMER0_CYCLES_12MHZ 12U
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#endif /* __RP2350_H */
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