/*
   This file has been generated by IDA.
   It contains local type definitions from
   the type library 'entry1_type0x09.dylib'
*/
#include "ida_types.h"

#define __int8 char
#define __int16 short
#define __int32 int
#define __int64 long long

typedef struct {
    uint64_t field_0x00;   // [x21+0x00]: pointer (has +0x38 = int)
    uint64_t base_ptr;   // [x21+0x08]: base pointer for result offset calc
    uint64_t size;   // [x21+0x10]: checked non-null
    // ... other fields
} SearchObj;

/* 160 */
enum CPUFamily : uint32_t
{
  CPUFamily_ARM_CYCLONE = 0x37A09642,
  CPUFamily_A8 = 0x2C91A47E,
  CPUFamily_A9 = 0x92FB37C8,
  CPUFamily_A10 = 0x67CEEE93,
  CPUFamily_A11 = 0xE81E7EF6,
  CPUFamily_A12 = 0x7D34B9F,
  CPUFamily_A13 = 0x462504D2,
  CPUFamily_A14 = 0x1B588BB3,
  CPUFamily_A15 = 0xDA33D83D,
  CPUFamily_A16 = 0x8765EDEA,
  CPUFamily_A17 = 0x2876F5B5,
  CPUFamily_ARM_TYPHOON = CPUFamily_A8,
  CPUFamily_ARM_TWISTER = CPUFamily_A9,
  CPUFamily_ARM_HURRICANE = CPUFamily_A10,
  CPUFamily_ARM_MONSOON_MISTRAL = CPUFamily_A11,
  CPUFamily_ARM_VORTEX_TEMPEST = CPUFamily_A12,
  CPUFamily_ARM_LIGHTNING_THUNDER = CPUFamily_A13,
  CPUFamily_ARM_FIRESTORM_ICESTORM = CPUFamily_A14,
  CPUFamily_ARM_BLIZZARD_AVALANCHE = CPUFamily_A15,
  CPUFamily_ARM_EVEREST_SAWTOOTH = CPUFamily_A16,
  CPUFamily_ARM_COLL = CPUFamily_A17,
  CPUFamily_ARM_IBIZA = 0xFA33415E,
  CPUFamily_ARM_PALMA = 0x72015832,
  CPUFamily_ARM_LOBOS = 0x5F4DEA93,
  CPUFamily_ARM_DONAN = 0x6F5129AC,
  CPUFamily_ARM_BRAVA = 0x17D5B93A,
  CPUFamily_ARM_TAHITI = 0x75D4ACB9,
  CPUFamily_ARM_TUPAI = 0x204526D0,
  CPUFamily_ARM_THERA = 0xAB345F09,
  CPUFamily_ARM_TILOS = 0x01D7A72B,
  CPUFamily_ARM_UNKNOWN_573B5EEC = 0x573B5EEC,
};

#define XNU_VERSION_PACKED(major, minor, patch, build, variant) \
  (((uint64_t)((major) & 0x7FFF) << 40) | ((uint64_t)((minor) & 0x3FF) << 30) | ((uint64_t)((patch) & 0x3FF) << 20) | ((uint64_t)((build) & 0x3FF) << 10) | (uint64_t)((variant) & 0x3FF))


/* 164 */
struct struct_krwCtx
{
  uint32_t flags;
  uint8_t gap4[168];
  uint32_t threadForKernelRead;
  uint8_t gap42[144];
  int xnuMajorVersion;
  uint8_t gap144[20];
  uint64_t xnuVersionPacked;
  uint8_t gap160[8];
  int stride168;
  int gap16C[5];
  int pageSizeOrSomething;
  int gap16C2;
  uint64_t pageMask;
  uint8_t gap190[136];
  uint64_t gap190u;
  uint8_t gap190_[56];
  int isRW;
  struct mach_timebase_info timebase;
  mach_port_t semaphore;
  pthread_mutex_t someMutex;
  uint32_t someInt1;
  uint32_t someInt2;
  uint64_t gap19100[16];
  pthread_mutex_t someMutex2;
  uint64_t gap191[695];
  uint32_t gap1909;
  uint32_t gap1910;
  uint32_t gap1911[2];
  uint32_t gap1913;
  uint32_t gap1914;
  uint32_t gap1915;
  uint32_t gap1916;
  uint64_t gap192[16];
  uint64_t machHeaderPlus0x8000;
  uint64_t gap19210;
  uint64_t gap19211;
  uint64_t slideMaybe;
  uint64_t gap1921[108];
  uint64_t IOKitConnInfo;
};
typedef struct struct_krwCtx struct_krwCtx;

/* 165 */
struct __attribute__((packed)) __attribute__((aligned(4))) struct_IOKitConnInfo
{
  uint8_t gap0[80];
  uint64_t qword50;
  uint64_t qword58;
  uint64_t qword60;
  uint64_t qword68;
  uint32_t ioPort;
};
typedef struct __attribute__((packed)) __attribute__((aligned(4))) struct_IOKitConnInfo struct_IOKitConnInfo;

/* 166 */
struct __attribute__((packed)) __attribute__((aligned(8))) struct_xnuMajorVersion
{
  __int128 majorVersion;
  __int128 oword10;
  uint64_t qword20;
};
typedef struct __attribute__((packed)) __attribute__((aligned(8))) struct_xnuMajorVersion struct_xnuMajorVersion;

/* 168 */
struct __attribute__((packed)) __attribute__((aligned(2))) struct_v83
{
  uint8_t gap0[48];
  uint32_t dword30;
  uint8_t gap34[4];
  uint32_t dword38;
  uint8_t gap3C[52];
  __int128 xnuMajorVersion;
  __int128 oword80;
  uint64_t qword90;
  uint32_t dword98;
  uint8_t gap9C[12];
  uint64_t qwordA8;
  uint8_t gapB0[81];
  uint8_t byte101;
};
typedef struct __attribute__((packed)) __attribute__((aligned(2))) struct_v83 struct_v83;

/* 169 */
struct __attribute__((packed)) __attribute__((aligned(8))) struct_a1
{
  __int128 oword0;
  __int128 oword10;
  __int128 oword20;
  __int128 oword30;
  __int128 oword40;
  __int128 oword50;
  __int128 oword60;
  __int128 xnuMajorVersion;
  __int128 oword80;
  __int128 oword90;
  __int128 owordA0;
  __int128 owordB0;
  __int128 owordC0;
  __int128 owordD0;
  __int128 owordE0;
  __int128 owordF0;
  __int128 oword100;
  __int128 oword110;
  uint64_t qword120;
};
typedef struct __attribute__((packed)) __attribute__((aligned(8))) struct_a1 struct_a1;

/* 173 */
enum krw_ctx_flags
{
  KRW_CTX_FLAG_CPU_A12 = 0x00000001,
  KRW_CTX_FLAG_MOBILEBACKUP_SANDBOX_PATCHED = 0x00000004,
  KRW_CTX_FLAG_CPU_HIGH_CORE_CLUSTER = 0x00000008,
  KRW_CTX_FLAG_HOST_PORT_READY = 0x00000010,
  KRW_CTX_FLAG_PAC_KERNEL_LAYOUT = 0x00000020,
  KRW_CTX_FLAG_CPU_A10 = 0x00000040,
  KRW_CTX_FLAG_KERNEL_PORT_READY = 0x00000100,
  KRW_CTX_FLAG_CPU_A11 = 0x00000200,
  KRW_CTX_FLAG_SNAPSHOT_MOUNTED = 0x00000400,
  KRW_CTX_FLAG_HAS_AUXKC_INFO = 0x00001000,
  KRW_CTX_FLAG_CPU_A9 = 0x00002000,
  KRW_CTX_FLAG_CPU_A13 = 0x00004000,
  KRW_CTX_FLAG_CPU_A8 = 0x00008000,
  KRW_CTX_FLAG_KRW_METHODS_READY = 0x00010000,
  KRW_CTX_FLAG_CPU_A14 = 0x00080000,
  KRW_CTX_FLAG_CPU_A15 = 0x00100000,
  // These two bits are queried by dmaFail, but no ctx setter has been found in this dylib.
  // The same numeric values also appear as 2 MiB / 32 MiB translation block sizes.
  KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET = 0x00200000,
  // Included in the original binary's broader A12+ guard mask, but no setter has been found yet.
  KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN = 0x00400000,
  KRW_CTX_FLAG_SELF_TASK_PORT_CLEARED = 0x00800000,
  KRW_CTX_FLAG_CPU_A16 = 0x01000000,
  KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET = 0x02000000,
  KRW_CTX_FLAG_CPU_A17 = 0x04000000,
  KRW_CTX_FLAG_SELF_TASK_IPC_SPACE_CLEARED = 0x08000000,
  KRW_CTX_FLAG_LOW_MEMORY_DEVICE = 0x10000000,

  KRW_CTX_FLAG_CS_TXM = KRW_CTX_FLAG_PAC_KERNEL_LAYOUT,
  KRW_CTX_FLAG_CS_PPL_MAYBE = KRW_CTX_FLAG_CPU_HIGH_CORE_CLUSTER,

  KRW_CTX_FLAG_CPU_A13_A14_MASK = KRW_CTX_FLAG_CPU_A13 | KRW_CTX_FLAG_CPU_A14,
  KRW_CTX_FLAG_CPU_A12_A13_A14_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13_A14_MASK,
  KRW_CTX_FLAG_CPU_A15_A16_MASK = KRW_CTX_FLAG_CPU_A15 | KRW_CTX_FLAG_CPU_A16,
  KRW_CTX_FLAG_CPU_A14_DMA_ALT = KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A15_DMA_ALT = KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A14_A15_DMA_ALT_MASK = KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET | KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A16_A17_MASK = KRW_CTX_FLAG_CPU_A16 | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A14 | KRW_CTX_FLAG_CPU_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A13_A14_MASK | KRW_CTX_FLAG_CPU_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A11 | KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A13_A14_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_A17_MASK =
      KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A10_A11_A9_MASK = KRW_CTX_FLAG_CPU_A10 | KRW_CTX_FLAG_CPU_A11 | KRW_CTX_FLAG_CPU_A9,
  KRW_CTX_FLAG_CPU_A12_A13_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13,
  KRW_CTX_FLAG_CPU_A8_TO_A17_MASK =
      KRW_CTX_FLAG_CPU_A8 | KRW_CTX_FLAG_CPU_A9 | KRW_CTX_FLAG_CPU_A10 | KRW_CTX_FLAG_CPU_A11 |
      KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK,
  /*
   * Historical decompiler names. The original binary uses CPU-only masks here
   * (0x5584001 and 0x5584201); SELF_TASK_PORT_CLEARED is handled separately.
   */
  KRW_CTX_FLAG_CPU_A12_TO_A17_OR_SELF_TASK_PORT_MASK =
      KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK | KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN,
  KRW_CTX_FLAG_CPU_A11_TO_A17_OR_SELF_TASK_PORT_MASK =
      KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_A17_MASK | KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN,
};
