/*
   This file has been generated by IDA.
   It contains local type definitions from
   the type library 'entry1_type0x09.dylib'
*/
#include "ida_types.h"

#define __int8 char
#define __int16 short
#define __int32 int
#define __int64 long long

typedef struct {
    uint64_t field_0x00;   // [x21+0x00]: pointer (has +0x38 = int)
    uint64_t base_ptr;   // [x21+0x08]: base pointer for result offset calc
    uint64_t size;   // [x21+0x10]: checked non-null
    // ... other fields
} SearchObj;

typedef struct {
    uint64_t tableKva;
    uint64_t virtualBase;
    uint32_t span;
    uint8_t level;
    uint8_t reserved15[3];
    uint32_t attributes;
    uint64_t descriptor;
} PgtableWalkCacheEntry;

/* 160 */
enum CPUFamily : uint32_t
{
  CPUFamily_ARM_CYCLONE = 0x37A09642,
  CPUFamily_A8 = 0x2C91A47E,
  CPUFamily_A9 = 0x92FB37C8,
  CPUFamily_A10 = 0x67CEEE93,
  CPUFamily_A11 = 0xE81E7EF6,
  CPUFamily_A12 = 0x7D34B9F,
  CPUFamily_A13 = 0x462504D2,
  CPUFamily_A14 = 0x1B588BB3,
  CPUFamily_A15 = 0xDA33D83D,
  CPUFamily_A16 = 0x8765EDEA,
  CPUFamily_A17 = 0x2876F5B5,
  CPUFamily_ARM_TYPHOON = CPUFamily_A8,
  CPUFamily_ARM_TWISTER = CPUFamily_A9,
  CPUFamily_ARM_HURRICANE = CPUFamily_A10,
  CPUFamily_ARM_MONSOON_MISTRAL = CPUFamily_A11,
  CPUFamily_ARM_VORTEX_TEMPEST = CPUFamily_A12,
  CPUFamily_ARM_LIGHTNING_THUNDER = CPUFamily_A13,
  CPUFamily_ARM_FIRESTORM_ICESTORM = CPUFamily_A14,
  CPUFamily_ARM_BLIZZARD_AVALANCHE = CPUFamily_A15,
  CPUFamily_ARM_EVEREST_SAWTOOTH = CPUFamily_A16,
  CPUFamily_ARM_COLL = CPUFamily_A17,
  CPUFamily_ARM_IBIZA = 0xFA33415E,
  CPUFamily_ARM_PALMA = 0x72015832,
  CPUFamily_ARM_LOBOS = 0x5F4DEA93,
  CPUFamily_ARM_DONAN = 0x6F5129AC,
  CPUFamily_ARM_BRAVA = 0x17D5B93A,
  CPUFamily_ARM_TAHITI = 0x75D4ACB9,
  CPUFamily_ARM_TUPAI = 0x204526D0,
  CPUFamily_ARM_THERA = 0xAB345F09,
  CPUFamily_ARM_TILOS = 0x01D7A72B,
  CPUFamily_ARM_UNKNOWN_573B5EEC = 0x573B5EEC,
};

#define XNU_VERSION_PACKED(major, minor, patch, build, variant) \
  (((uint64_t)((major) & 0x7FFF) << 40) | ((uint64_t)((minor) & 0x3FF) << 30) | ((uint64_t)((patch) & 0x3FF) << 20) | ((uint64_t)((build) & 0x3FF) << 10) | (uint64_t)((variant) & 0x3FF))


/* 164 */
#if !RECOMP_TEMP_FAKE_OBJC_CLASS
#pragma pack(push, 1)
struct __attribute__((packed)) struct_krwCtx
{
#else
@interface struct_krwCtx : NSObject
    {
    @public
#endif
        /*  00000000 */ uint32_t flags;
        union {
        /*  00000004 */ uint8_t raw_0x4[0xA8];
            struct {
        /*  00000004 */ uint8_t gap_0x4_to_0xB[0x7];
        /*  0000000B */ uint8_t isSandboxed;
        /*  0000000C */ uint8_t gap_0xC;
        /*  0000000D */ uint8_t gap_0xD_to_0x10[0x3];
        /*  00000010 */ uint32_t iosurfaceObj;
        /*  00000014 */ uint8_t gap_0x14_to_0x18[0x4];
        /*  00000018 */ uint64_t gap_0x18;
        /*  00000020 */ uint64_t gap_0x20;
        /*  00000028 */ uint64_t semaphoreHelperCtx;
        /*  00000030 */ uint64_t iogpuKreadFn;
        /*  00000038 */ uint64_t iogpuKread2Fn;
        /*  00000040 */ uint64_t iogpuKwriteFn;
        /*  00000048 */ uint64_t iogpuKwrite2Fn;
        /*  00000050 */ uint64_t iogpuCtx;
        /*  00000058 */ uint32_t ioSurfaceMemEntryMaybe;
        /*  0000005C */ uint32_t gap_0x5C_size4;
        /*  00000060 */ uint8_t gap_0x60_to_0x80[0x20];
        /*  00000080 */ uint64_t physmapBasePhys;
        /*  00000088 */ uint32_t physmapSize;
        /*  0000008C */ uint8_t gap_0x8C_to_0x90[0x4];
        /*  00000090 */ uint64_t gap_0x90;
        /*  00000098 */ uint64_t gap_0x98;
        /*  000000A0 */ uint64_t percpuBasePhys;
        /*  000000A8 */ uint32_t percpuSize;
            };
        };
        /*  000000AC */ uint32_t threadForKernelRead;
        /*  00000B0 */ uint64_t threadStateMapAddr;
        /*  000000B8 */ uint64_t threadStateMapSize;
        /*  000000C0 */ uint64_t threadStatePageOffset;
        /*  000000C8 */ uint64_t threadStateMappedPtr;
        /*  000000D0 */ uint64_t threadStateScratchKaddr;
        /*  000000D8 */ uint64_t threadStateKrwPhysAddr;
        /*  000000E0 */ uint64_t threadStateSavedPtr;
        /*  000000E8 */ uint64_t ioConnectPort; // low 32 bits
        /*  000000F0 */ uint64_t ioConnectKernelValue;
        /*  000000F8 */ uint64_t ioConnectMappedAddr;
        /*  00000100 */ uint64_t ioConnectMappedSize;
        /*  00000108 */ uint64_t ioConnectDataOffset;
        /*  00000110 */ uint32_t ioConnectDataSize;
        /*  00000114 */ uint32_t ioConnectMemPort;
        union {
        /*  00000118 */ uint64_t mappedKernelRegion;
        /*  00000118 */ uint64_t mappedKernelRegion_size8byte;
        };
        union {
        /*  00000120 */ uint64_t mappedKernelSize;
        /*  00000120 */ uint64_t mappedKernelSize_size8byte;
        };
        /*  00000128 */ uint64_t gap_0x128;
        /*  00000130 */ uint64_t gap_0x130;
        /*  00000138 */ uint64_t gap_0x138;
        /*  00000140 */ int xnuMajorVersion;
        union {
        /*  00000144 */ uint8_t raw_0x144[20];
            struct {
        /*  00000144 */ uint8_t gap_0x144_to_0x150[0xC];
        /*  00000150 */ uint64_t gap_0x150;
            };
        };
        /*  00000158 */ uint64_t xnuVersionPacked;
        union {
        /*  00000160 */ uint8_t raw_0x160[8];
        /*  00000160 */ uint64_t gap_0x160_size8;
        };
        /*  00000168 */ int stride_0x168;
        union {
        /*  0000016C */ int raw_0x16C[5];
            struct {
        /*  0000016C */ int gap_0x16C_0;
        /*  00000170 */ int gap_0x170;
        /*  00000174 */ int gap_0x174;
        union {
        /*  00000178 */ uint32_t vmMapSize;
        /*  00000178 */ uint32_t vmMapSize_size4;
        };
        /*  0000017C */ int gap_0x17C;
            };
        };
        /*  00000180 */ uint32_t pageSizeOrSomething;
        /*  00000184 */ int gap_0x184;
        /*  00000188 */ uint64_t pageMask;
        union {
        /*  00000190 */ uint8_t raw_0x190[136];
            struct {
        /*  00000190 */ uint8_t gap_0x190_to_0x1A0[0x10];
        /*  000001A0 */ uint64_t gap_0x1A0;
        /*  000001A8 */ uint64_t gap_0x1A8_size8;
        /*  000001B0 */ uint64_t gap_0x1B0;
        /*  000001B8 */ uint8_t gap_0x1B8_to_0x1D0[0x18];
        /*  000001D0 */ uint64_t cleanup_hook;
        /*  000001D8 */ uint8_t gap_0x1D8_to_0x1E0[0x8];
        /*  000001E0 */ uint64_t gap_0x1E0;
        /*  000001E8 */ uint64_t gap_0x1E8;
        /*  000001F0 */ uint64_t gap_0x1F0;
        /*  000001F8 */ uint64_t gap_0x1F8;
        /*  00000200 */ uint64_t gap_0x200;
        /*  00000208 */ uint64_t gap_0x208;
        /*  00000210 */ uint64_t gap_0x210;
        ///*  00000200 */ uint8_t gap_0x200_to_0x218[0x18];
            };
        };
        /*  00000218 */ uint64_t gap_0x218;
        union {
        /*  00000220 */ uint8_t raw_0x220[56];
            struct {
        /*  00000220 */ uint64_t gap_0x220;
        /*  00000228 */ uint64_t gap_0x228;
        /*  00000230 */ uint64_t gap_0x230;
        /*  00000238 */ uint8_t gap_0x238_to_0x248[0x10];
        /*  00000248 */ uint64_t gap_0x248;
        /*  00000250 */ uint64_t gap_0x250;
            };
        };
        union {
        /*  00000258 */ int isRW;
        /*  00000258 */ uint32_t gap_0x258_size4;
        };
        /*  0000025C */ struct mach_timebase_info timebase;
        /*  00000264 */ mach_port_t semaphore;
        /*  00000268 */ pthread_mutex_t someMutex;
        /*  000002A8 */ uint32_t someInt1;
        /*  000002AC */ uint32_t someInt2;
        /*  000002B0 */ uint64_t raw_0x2B0[16];
        /*  00000330 */ pthread_mutex_t someMutex2;
        union {
        /*  00000370 */ uint64_t raw_0x370[695];
            struct {
        /*  00000370 */ uint64_t restoreRecordListHead;
        union {
        /*  00000378 */ uint64_t gap_0x378;
            struct {
        /*  00000378 */ uint32_t gap_0x378_size4;
        /*  0000037C */ uint32_t gap_0x37C_size4;
            };
        };
        /*  00000380 */ uint8_t gap_0x380_to_0x390[0x10];
        /*  00000390 */ uint64_t gap_0x390;
        /*  00000398 */ uint64_t gap_0x398;
        /*  000003A0 */ uint64_t gap_0x3A0;
        /*  000003A8 */ uint64_t gap_0x3A8;
        /*  000003B0 */ uint64_t gap_0x3B0;
        /*  000003B8 */ uint8_t gap_0x3B8_to_0x5C0[0x208];
        /*  000005C0 */ uint64_t gap_0x5C0;
        /*  000005C8 */ uint8_t gap_0x5C8_to_0x5D0[0x8];
        /*  000005D0 */ uint64_t pgtableRootKva;
        /*  000005D8 */ uint64_t pgtableRootDelta;
        /*  000005E0 */ uint32_t pgtableRootSpan;
        /*  000005E4 */ uint8_t gap_0x5E4_to_0x5E8[0x4];
        /*  000005E8 */ PgtableWalkCacheEntry pgtableWalkCache[16];
        /*  00000868 */ uint64_t lruCacheLastUpdatedTime;
        /*  00000870 */ uint64_t gap_0x870;
        /*  00000878 */ uint64_t gap_0x878;
        /*  00000880 */ uint8_t gap_0x880_to_0x1888[0x1008];
        /*  00001888 */ uint64_t pplPhysmapBase;
        /*  00001890 */ uint32_t pplPhysmapSize;
        /*  00001894 */ uint8_t gap_0x1894_to_0x1898[0x4];
        /*  00001898 */ uint64_t iogpuKobjPtr2;
        /*  000018A0 */ uint64_t iogpuObjCount;
        /*  000018A8 */ uint64_t gap_0x18A8;
        /*  000018B0 */ uint64_t gap_0x18B0;
        /*  000018B8 */ uint64_t gap_0x18B8;
        /*  000018C0 */ uint64_t gap_0x18C0;
        /*  000018C8 */ uint8_t gap_0x18C8_to_0x18D8[0x10];
        /*  000018D8 */ uint32_t gap_0x18D8_size4;
        /*  000018DC */ uint8_t gap_0x18DC_to_0x18E0[0x4];
        /*  000018E0 */ uint64_t cachedSelfTaskKaddr;
        /*  000018E8 */ uint64_t gap_0x18E8;
        /*  000018F0 */ uint64_t gap_0x18F0;
        /*  000018F8 */ uint64_t gap_0x18F8;
        /*  00001900 */ uint64_t selfTaskDyldInfoKaddr;
        /*  00001908 */ uint64_t selfTaskDyldInfoValue;
        union {
        /*  00001910 */ uint64_t savedUidGid;
            struct {
        /*  00001910 */ uint32_t savedUid;
        /*  00001914 */ uint32_t savedGid;
            };
        };
        union {
        /*  00001918 */ uint64_t targetAndParentTaskPorts;
            struct {
        /*  00001918 */ uint32_t targetVmPort;
        /*  0000191C */ uint32_t parentTaskPort;
            };
        };
        union {
        /*  00001920 */ uint64_t hostPrivAndSecurityPorts;
            struct {
        /*  00001920 */ uint32_t hostPrivPort;
        /*  00001924 */ uint32_t hostSecurityPort;
            };
        };
            };
        };
        /*  00001928 */ uint32_t hostSelfPort;
        /*  0000192C */ uint32_t exploitThread;
        /*  00001930 */ uint32_t krw_pipe_0;
        /*  00001934 */ uint32_t krw_pipe_1;
        /*  00001938 */ uint32_t pipeFd0;
        /*  0000193C */ uint32_t pipeFd1;
        union {
        /*  00001940 */ uint32_t iosurfaceFd;
        /*  00001940 */ uint32_t iosurfaceFd_size4;
        };
        /*  00001944 */ uint32_t necpFd;
        union {
        /*  00001948 */ uint64_t necpClientUuidAndState[16];
            struct {
        /*  00001948 */ uint8_t necpClientUuid[0x10];
        /*  00001958 */ uint64_t necpClientKaddr;
        /*  00001960 */ uint8_t gap_0x1960_to_0x1990[0x30];
        /*  00001990 */ uint64_t gap_0x1990_size8;
        /*  00001998 */ uint64_t gap_0x1998;
        /*  000019A0 */ uint64_t gap_0x19A0;
        /*  000019A8 */ uint8_t gap_0x19A8_to_0x19C8[0x20];
            };
        };
        /*  000019C8 */ uint64_t machHeaderPlus0x8000;
        union {
        /*  000019D0 */ uint64_t gap_0x19D0;
        /*  000019D0 */ uint64_t gap_0x19D0_size8;
        };
        /*  000019D8 */ uint64_t gap_0x19D8;
        union {
        /*  000019E0 */ uint64_t slideMaybe;
        /*  000019E0 */ uint64_t gap_0x19E0_size8;
        };
        /*  000019E8 */ uint64_t gap_0x19E8;
        /*  000019F0 */ uint64_t gap_0x19F0;
        /*  000019F8 */ uint64_t *kernelMachoCtx;
        /*  00001A00 */ uint64_t auxkcMachoCtx;
        union {
        /*  00001A08 */ uint64_t raw_0x1A08[104];
            struct {
        /*  00001A08 */ uint8_t gap_0x1A08_to_0x1D08[0x300];
        /*  00001D08 */ uint32_t gap_0x1D08_size4;
        /*  00001D0C */ uint8_t gap_0x1D0C_to_0x1D10[0x4];
        /*  00001D10 */ uint64_t puafPagesBuf;
        /*  00001D18 */ uint64_t sandboxMachoCtx;
        /*  00001D20 */ uint64_t amfiMachoCtx;
        /*  00001D28 */ uint64_t kextMachoCtx0;
        /*  00001D30 */ uint64_t kextMachoCtx1;
        /*  00001D38 */ uint64_t kextMachoCtx2;
        /*  00001D40 */ uint8_t gap_0x1D40_to_0x1D48[0x8];
            };
        };
        /*  00001D48 */ uint64_t IOKitConnInfo;
        /*  00001D50 */ uint64_t gap_0x1D50;
        /*  00001D58 */ uint64_t dmaFailCtx;
        /*  00001D60 */ // end
    };
#if !RECOMP_TEMP_FAKE_OBJC_CLASS
typedef struct struct_krwCtx struct_krwCtx;
#pragma pack(pop)
#define KRWCTX_FROM_UINTPTR(value) ((struct_krwCtx *)(uintptr_t)(value))
#define KRWCTX_RAW_PTR(ctx) ((char *)(ctx))
#else
@end
@implementation struct_krwCtx
@end
#define KRWCTX_FROM_UINTPTR(value) ((__bridge struct_krwCtx *)(void *)(uintptr_t)(value))
#define KRWCTX_RAW_PTR(ctx) ((char *)(__bridge void *)(ctx))
#endif
#define KRWCTX_FROM_RAW_FIELD(base, offset) KRWCTX_FROM_UINTPTR(*(uint64_t *)((char *)(base) + (offset)))
#define KRWCTX_FIELD_U64(ctx, offset) (*(uint64_t *)(KRWCTX_RAW_PTR(ctx) + (offset)))

/* 165 */
struct __attribute__((packed)) __attribute__((aligned(4))) struct_IOKitConnInfo
{
  uint8_t gap0[80];
  uint64_t qword50;
  uint64_t qword58;
  uint64_t qword60;
  uint64_t qword68;
  uint32_t ioPort;
};
typedef struct __attribute__((packed)) __attribute__((aligned(4))) struct_IOKitConnInfo struct_IOKitConnInfo;

/* 166 */
struct __attribute__((packed)) __attribute__((aligned(8))) struct_xnuMajorVersion
{
  __int128 majorVersion;
  __int128 oword10;
  uint64_t qword20;
};
typedef struct __attribute__((packed)) __attribute__((aligned(8))) struct_xnuMajorVersion struct_xnuMajorVersion;

/* 168 */
struct __attribute__((packed)) __attribute__((aligned(2))) struct_v83
{
  uint8_t gap0[48];
  uint32_t dword30;
  uint8_t gap34[4];
  uint32_t dword38;
  uint8_t gap3C[52];
  __int128 xnuMajorVersion;
  __int128 oword80;
  uint64_t qword90;
  uint32_t dword98;
  uint8_t gap9C[12];
  uint64_t qwordA8;
  uint8_t gapB0[81];
  uint8_t byte101;
};
typedef struct __attribute__((packed)) __attribute__((aligned(2))) struct_v83 struct_v83;

/* 169 */
struct __attribute__((packed)) __attribute__((aligned(8))) struct_a1
{
  __int128 oword0;
  __int128 oword10;
  __int128 oword20;
  __int128 oword30;
  __int128 oword40;
  __int128 oword50;
  __int128 oword60;
  __int128 xnuMajorVersion;
  __int128 oword80;
  __int128 oword90;
  __int128 owordA0;
  __int128 owordB0;
  __int128 owordC0;
  __int128 owordD0;
  __int128 owordE0;
  __int128 owordF0;
  __int128 oword100;
  __int128 oword110;
  uint64_t qword120;
};
typedef struct __attribute__((packed)) __attribute__((aligned(8))) struct_a1 struct_a1;

/* 173 */
enum krw_ctx_flags
{
  KRW_CTX_FLAG_CPU_A12 = 0x00000001,
  KRW_CTX_FLAG_MOBILEBACKUP_SANDBOX_PATCHED = 0x00000004,
  KRW_CTX_FLAG_CPU_HIGH_CORE_CLUSTER = 0x00000008,
  KRW_CTX_FLAG_HOST_PORT_READY = 0x00000010,
  KRW_CTX_FLAG_PAC_KERNEL_LAYOUT = 0x00000020,
  KRW_CTX_FLAG_CPU_A10 = 0x00000040,
  KRW_CTX_FLAG_KERNEL_PORT_READY = 0x00000100,
  KRW_CTX_FLAG_CPU_A11 = 0x00000200,
  KRW_CTX_FLAG_SNAPSHOT_MOUNTED = 0x00000400,
  KRW_CTX_FLAG_HAS_AUXKC_INFO = 0x00001000,
  KRW_CTX_FLAG_CPU_A9 = 0x00002000,
  KRW_CTX_FLAG_CPU_A13 = 0x00004000,
  KRW_CTX_FLAG_CPU_A8 = 0x00008000,
  KRW_CTX_FLAG_KRW_METHODS_READY = 0x00010000,
  KRW_CTX_FLAG_CPU_A14 = 0x00080000,
  KRW_CTX_FLAG_CPU_A15 = 0x00100000,
  // These two bits are queried by dmaFail, but no ctx setter has been found in this dylib.
  // The same numeric values also appear as 2 MiB / 32 MiB translation block sizes.
  KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET = 0x00200000,
  // Included in the original binary's broader A12+ guard mask, but no setter has been found yet.
  KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN = 0x00400000,
  KRW_CTX_FLAG_SELF_TASK_PORT_CLEARED = 0x00800000,
  KRW_CTX_FLAG_CPU_A16 = 0x01000000,
  KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET = 0x02000000,
  KRW_CTX_FLAG_CPU_A17 = 0x04000000,
  KRW_CTX_FLAG_SELF_TASK_IPC_SPACE_CLEARED = 0x08000000,
  KRW_CTX_FLAG_LOW_MEMORY_DEVICE = 0x10000000,

  KRW_CTX_FLAG_CS_TXM = KRW_CTX_FLAG_PAC_KERNEL_LAYOUT,
  KRW_CTX_FLAG_CS_PPL_MAYBE = KRW_CTX_FLAG_CPU_HIGH_CORE_CLUSTER,

  KRW_CTX_FLAG_CPU_A13_A14_MASK = KRW_CTX_FLAG_CPU_A13 | KRW_CTX_FLAG_CPU_A14,
  KRW_CTX_FLAG_CPU_A12_A13_A14_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13_A14_MASK,
  KRW_CTX_FLAG_CPU_A15_A16_MASK = KRW_CTX_FLAG_CPU_A15 | KRW_CTX_FLAG_CPU_A16,
  KRW_CTX_FLAG_CPU_A14_DMA_ALT = KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A15_DMA_ALT = KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A14_A15_DMA_ALT_MASK = KRW_CTX_FLAG_CPU_A14_DMA_ALT_UNSET | KRW_CTX_FLAG_CPU_A15_DMA_ALT_UNSET,
  KRW_CTX_FLAG_CPU_A16_A17_MASK = KRW_CTX_FLAG_CPU_A16 | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A14 | KRW_CTX_FLAG_CPU_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A13_A14_MASK | KRW_CTX_FLAG_CPU_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_MASK = KRW_CTX_FLAG_CPU_A11 | KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK,
  KRW_CTX_FLAG_CPU_A13_A14_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK = KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_A17_MASK =
      KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_MASK | KRW_CTX_FLAG_CPU_A17,
  KRW_CTX_FLAG_CPU_A10_A11_A9_MASK = KRW_CTX_FLAG_CPU_A10 | KRW_CTX_FLAG_CPU_A11 | KRW_CTX_FLAG_CPU_A9,
  KRW_CTX_FLAG_CPU_A12_A13_MASK = KRW_CTX_FLAG_CPU_A12 | KRW_CTX_FLAG_CPU_A13,
  KRW_CTX_FLAG_CPU_A8_TO_A17_MASK =
      KRW_CTX_FLAG_CPU_A8 | KRW_CTX_FLAG_CPU_A9 | KRW_CTX_FLAG_CPU_A10 | KRW_CTX_FLAG_CPU_A11 |
      KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK,
  /*
   * Historical decompiler names. The original binary uses CPU-only masks here
   * (0x5584001 and 0x5584201); SELF_TASK_PORT_CLEARED is handled separately.
   */
  KRW_CTX_FLAG_CPU_A12_TO_A17_OR_SELF_TASK_PORT_MASK =
      KRW_CTX_FLAG_CPU_A12_A13_A14_A15_A16_A17_MASK | KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN,
  KRW_CTX_FLAG_CPU_A11_TO_A17_OR_SELF_TASK_PORT_MASK =
      KRW_CTX_FLAG_CPU_A11_A12_A13_A14_A15_A16_A17_MASK | KRW_CTX_FLAG_CPU_A12_TO_A17_UNKNOWN,
};
