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Added bare-metal blinky

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# RP2350 GPIO Coprocessor Blink - RAW Assembler, NO SDK
<img src="https://github.com/mytechnotalent/RP2350_Blink_Driver/blob/main/RP2350_Blink_Driver.png?raw=true">
## Overview
## FREE Reverse Engineering Self-Study Course [HERE](https://github.com/mytechnotalent/Reverse-Engineering-Tutorial)
This is a **bare-metal assembly program** for the **Raspberry Pi RP2350** microcontroller that demonstrates the use of the **ARM Cortex-M33 coprocessor interface** to control GPIO pins. Unlike traditional GPIO control using direct memory-mapped register writes, this version uses the RP2350's **hardware GPIO coprocessor (CP0)** with **MCRR (Move to Coprocessor from two ARM Registers)** instructions.
<br>
The program blinks an LED connected to **GPIO16** with a 500ms on/off cycle using the specialized coprocessor instructions for high-performance GPIO operations.
# RP2350 Blink Driver
An RP2350 blink driver written entirely in Assembler.
---
# Code
```assembler
/**
* FILE: main.s
*
* DESCRIPTION:
* RP2350 Bare-Metal GPIO16 Blink, Coprocessor Version.
* Minimal bare‑metal LED blink on the RP2350 using direct coprocessor
* (MCRR) instructions to manipulate GPIO control registers. This bypasses
* SDK abstractions and demonstrates register‑level control in assembler.
*
* AUTHOR: Kevin Thomas
* CREATION DATE: October 5, 2025
* UPDATE DATE: October 5, 2025
*/
## What Makes This Special?
.syntax unified // use unified assembly syntax
.cpu cortex-m33 // target Cortex-M33 core
.thumb // use Thumb instruction set
### Traditional GPIO Control vs Coprocessor Control
/**
* Memory addresses and constants.
*/
.equ IO_BANK0_BASE, 0x40028000 // base address of IO_BANK0
.equ PADS_BANK0_BASE, 0x40038000 // base address of PADS_BANK0
.equ SIO_BASE, 0xD0000000 // base address of SIO block
.equ GPIO16_CTRL, 0x84 // io[16].ctrl offset
.equ GPIO16_PAD, 0x44 // pads io[16] offset
.equ GPIO16_BIT, (1<<16) // bit mask for GPIO16
.equ GPIO_OUT_SET, 0x18 // SIO->GPIO_OUT_SET offset
.equ GPIO_OUT_XOR, 0x28 // SIO->GPIO_OUT_XOR offset
.equ GPIO_OE_SET, 0x38 // SIO->GPIO_OE_SET offset
.equ STACK_TOP, 0x20082000 // top of non-secure SRAM
.equ STACK_LIMIT, 0x2007A000 // stack limit (32 KB below top)
**Traditional Method (Direct Register Access):**
```assembly
LDR R0, =SIO_BASE ; Load SIO base address
LDR R1, =GPIO16_BIT ; Load GPIO bit mask
STR R1, [R0, #GPIO_OUT_SET] ; Write to memory-mapped register
```
/**
* Initialize the .vectors section. The .vectors section contains vector
* table.
*/
.section .vectors, "ax" // vector table section
.align 2 // align to 4-byte boundary
**Coprocessor Method (This Implementation):**
```assembly
MOVS R4, #16 ; GPIO pin number
MOVS R5, #1 ; Value to write
MCRR p0, #4, R4, R5, c0 ; Single coprocessor instruction
```
### Advantages of the Coprocessor Approach:
1. **Faster execution** - Single instruction instead of multiple memory operations
2. **More atomic** - Less chance of race conditions
3. **Hardware-accelerated** - Direct hardware interface
4. **Cleaner code** - No need to manage bit masks and base addresses
5. **RP2350-specific** - Takes advantage of advanced features
---
## Hardware Requirements
- **RP2350-based board** (e.g., Raspberry Pi Pico 2)
- **LED** connected to **GPIO16** (or use built-in LED if available)
- Optional: Current-limiting resistor (typically 330Ω - 1kΩ)
- **USB cable** for programming
### GPIO16 Connection
```
RP2350 GPIO16 ----[330Ω]----[LED]---- GND
(Resistor) (Anode to GPIO, Cathode to GND)
```
---
## Technical Details
### Coprocessor Interface
The RP2350 implements a **custom GPIO coprocessor (CP0)** accessible through the ARM Cortex-M33's coprocessor interface. This is documented in the RP2350 datasheet.
#### MCRR Instruction Format
```
MCRR p0, #opcode, Rt, Rt2, CRm
```
Where:
- `p0` = Coprocessor 0 (GPIO coprocessor)
- `#opcode` = Operation code (4 for GPIO operations)
- `Rt` = First source register (GPIO pin number in R4)
- `Rt2` = Second source register (value in R5)
- `CRm` = Coprocessor register (c0 for OUT, c4 for OE)
### GPIO Coprocessor Operations Used
#### 1. `gpioc_bit_out_put(gpio, value)`
**Purpose:** Set or clear a GPIO output pin
**Encoding:** `MCRR p0, #4, R4, R5, c0`
**Parameters:**
- R4 = GPIO pin number (16 in our case)
- R5 = Output value (0 or 1)
**Example:**
```assembly
MOVS R4, #16 ; GPIO16
MOVS R5, #1 ; Set HIGH
MCRR p0, #4, R4, R5, c0
```
#### 2. `gpioc_bit_oe_put(gpio, enable)`
**Purpose:** Set output enable for a GPIO pin
**Encoding:** `MCRR p0, #4, R4, R5, c4`
**Parameters:**
- R4 = GPIO pin number (16 in our case)
- R5 = Output enable (1 to enable output)
**Example:**
```assembly
MOVS R4, #16 ; GPIO16
MOVS R5, #1 ; Enable output
MCRR p0, #4, R4, R5, c4
```
---
## Memory Map & Register Addresses
### Critical Memory Addresses Used
| Address | Register | Purpose |
|--------------|-----------------------------------|--------------------------------------|
| `0xE000ED88` | CPACR (Coprocessor Access Control)| Enable CP0 access |
| `0x40038044` | PADS_BANK0_GPIO16 | Pad configuration for GPIO16 |
| `0x40028084` | IO_BANK0_GPIO16_CTRL | Function select for GPIO16 |
| `0x20082000` | STACK_TOP | Initial stack pointer |
| `0x2007A000` | STACK_LIMIT | Stack limit for overflow protection |
### Register Details
#### CPACR (Coprocessor Access Control Register) - 0xE000ED88
```
Bits [1:0] - CP0 access privileges
00 = No access
01 = Privileged access only
10 = Reserved
11 = Full access (used in this code)
```
#### PADS_BANK0_GPIO16 - 0x40038044
```
Bit 8 (ISO) - Isolate pad (0 = normal operation)
Bit 7 (OD) - Output disable (0 = output enabled)
Bit 6 (IE) - Input enable (1 = input buffer enabled)
Bits [5:4] - Drive strength
Bits [3:2] - Slew rate
Bit 1 (PDE) - Pull-down enable
Bit 0 (PUE) - Pull-up enable
```
#### IO_BANK0_GPIO16_CTRL - 0x40028084
```
Bits [4:0] (FUNCSEL) - Function select
0 = JTAG (TDI)
1 = SPI
2 = UART
3 = I2C
4 = PWM
5 = SIO (Software controlled I/O) ← Used for GPIO
6-8 = PIO
9 = USB
31 = NULL
```
---
## Code Structure & Execution Flow
### 1. Vector Table (`.vectors` section)
```assembly
.section .vectors, "ax"
.align 2
.global _vectors
/**
* Vector table section.
*/
.global _vectors // export symbol
_vectors:
.word STACK_TOP /* 0x20082000 - Initial Stack Pointer */
.word Reset_Handler + 1 /* Reset Handler (Thumb bit set) */
```
.word STACK_TOP // initial stack pointer
.word Reset_Handler + 1 // reset handler (Thumb bit set)
**Why `+ 1`?**
The Cortex-M33 uses the Thumb instruction set exclusively. The LSB (least significant bit) of function pointers must be set to 1 to indicate Thumb mode. This is automatically handled by the processor.
### 2. Stack Initialization
```assembly
/**
* @brief Reset handler for RP2350.
*
* @details Entry point after reset. Performs:
* - Stack initialization
* - Coprocessor enable
* - GPIO16 pad/function configuration
* - Branches to main() which contains the blink loop
*
* @param None
* @retval None
*/
.global Reset_Handler // export Reset_Handler
.type Reset_Handler, %function // mark as function
Reset_Handler:
/* Initialize stack pointers for Cortex-M33 */
LDR R0, =STACK_TOP
MSR PSP, R0 /* Process Stack Pointer */
LDR R0, =STACK_LIMIT
MSR MSPLIM, R0 /* Main Stack Pointer Limit */
MSR PSPLIM, R0 /* Process Stack Pointer Limit */
LDR R0, =STACK_TOP
MSR MSP, R0 /* Main Stack Pointer */
BL Init_Stack // initialize MSP/PSP and limits
BL Enable_Coprocessor // enable CP0 in CPACR for MCRR
B main // branch to main loop
.size Reset_Handler, . - Reset_Handler
/**
* @brief Initialize stack pointers.
*
* @details Sets Main and Process Stack Pointers (MSP/PSP) and their limits.
*
* @param None
* @retval None
*/
.type Init_Stack, %function
Init_Stack:
LDR R0, =STACK_TOP // load stack top
MSR PSP, R0 // set PSP
LDR R0, =STACK_LIMIT // load stack limit
MSR MSPLIM, R0 // set MSP limit
MSR PSPLIM, R0 // set PSP limit
LDR R0, =STACK_TOP // reload stack top
MSR MSP, R0 // set MSP
BX LR // return
/**
* @brief Enable coprocessor access.
*
* @details Grants full access to coprocessor 0 (CP0) via CPACR.
*
* @param None
* @retval None
*/
.type Enable_Coprocessor , %function
Enable_Coprocessor:
LDR R0, =0xE000ED88 // CPACR address
LDR R1, [R0] // read CPACR
ORR R1, R1, #0x3 // set CP0 full access
STR R1, [R0] // write CPACR
DSB // data sync barrier
ISB // instruction sync barrier
BX LR // return
/**
* Initialize the .text section.
* The .text section contains executable code.
*/
.section .text // code section
.align 2 // align to 4-byte boundary
/**
* @brief Main application entry point.
*
* @details Implements the infinite blink loop:
* - Set GPIO16 high
* - Delay ~500 ms
* - Set GPIO16 low
* - Delay ~500 ms
* - Repeat forever
*
* @param None
* @retval None
*/
.global main // export main
.type main, %function // mark as function
main:
.Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Config:
BL GPIO16_Config // configure pads and FUNCSEL for GPIO16
.Loop:
BL GPIO16_Set // set GPIO16 high
BL Delay_500ms // ~500 ms delay
BL GPIO16_Clear // set GPIO16 low
BL Delay_500ms // ~500 ms delay
B Loop // loop forever
.Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Configure GPIO16 for SIO control.
*
* @details Sets pad control (IE, OD, ISO) and FUNCSEL = 5 (SIO). Enables OE.
*
* @param None
* @retval None
*/
.type GPIO16_Config, %function
GPIO16_Config:
.GPIO16_Config_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Config_Modify_Pad:
LDR R3, =PADS_BANK0_BASE + GPIO16_PAD // pad control address
LDR R2, [R3] // read pad config
BIC R2, R2, #0x80 // clear OD
ORR R2, R2, #0x40 // set IE
BIC R2, R2, #0x100 // clear ISO
STR R2, [R3] // write pad config
.GPIO16_Config_Modify_IO:
LDR R3, =IO_BANK0_BASE + GPIO16_CTRL // IO control address
LDR R2, [R3] // read IO config
BIC R2, R2, #0x1F // clear FUNCSEL
ORR R2, R2, #5 // set FUNCSEL=5
STR R2, [R3] // write IO config
.GPIO16_Config_Enable_OE:
MOVS R4, #16 // GPIO number
MOVS R5, #1 // enable output
MCRR p0, #4, R4, R5, c4 // gpioc_bit_oe_put(16, 1)
.GPIO16_Config_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return
/**
* @brief Set GPIO16 high.
*
* @details Drives GPIO16 output = 1 via coprocessor MCRR.
*
* @param None
* @retval None
*/
.type GPIO16_Set, %function
GPIO16_Set:
.GPIO16_Set_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Set_Load_Operands:
MOVS R4, #16 // GPIO number
MOVS R5, #1 // logic high
.GPIO16_Set_Execute:
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 1)
.GPIO16_Set_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Clear GPIO16 (set low).
*
* @details Drives GPIO16 output = 0 via coprocessor MCRR.
*
* @param None
* @retval None
*/
.type GPIO16_Clear, %function
GPIO16_Clear:
.GPIO16_Clear_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Clear_Load_Operands:
MOVS R4, #16 // GPIO number
MOVS R5, #0 // logic low
.GPIO16_Clear_Execute:
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 0)
.GPIO16_Clear_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Busy‑wait Delay_500ms loop.
*
* @details Consumes ~2,000,000 cycles to approximate ~500 ms at boot clock.
*
* @param None
* @retval None
*/
.type Delay_500ms, %function
Delay_500ms:
.Delay_500ms_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.Delay_500ms_Setup:
LDR R2, =2000000 // loop count (~500 ms)
.Delay_500ms_Loop:
SUBS R2, R2, #1 // decrement counter
BNE .Delay_500ms_Loop // branch until zero
.Delay_500ms_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* Test data and constants.
* The .rodata section is used for constants and static data.
*/
.section .rodata // read-only data section
/**
* Initialized global data.
* The .data section is used for initialized global or static variables.
*/
.section .data // data section
/**
* Uninitialized global data.
* The .bss section is used for uninitialized global or static variables.
*/
.section .bss // BSS section
```
**Cortex-M33 Stack Features:**
- **Dual stack pointers:** MSP (Main) and PSP (Process)
- **Stack limit registers:** MSPLIM and PSPLIM for overflow detection
- **Security feature:** Prevents stack overflow from corrupting memory
<br>
### 3. Coprocessor Access Enablement
```assembly
/* Enable coprocessor access - set CP0 to full access */
LDR R0, =0xE000ED88 /* CPACR address */
LDR R1, [R0] /* Read current value */
ORR R1, R1, #0x3 /* Set CP0 bits [1:0] to 11 (full access) */
STR R1, [R0] /* Write back */
DSB /* Data Synchronization Barrier */
ISB /* Instruction Synchronization Barrier */
```
**Critical Step:** Without this, MCRR instructions will trigger a **UsageFault** exception!
**Memory Barriers:**
- `DSB` - Ensures all memory operations complete before proceeding
- `ISB` - Flushes instruction pipeline to ensure new settings take effect
### 4. GPIO Pad Configuration
```assembly
/* Configure pad for GPIO16 */
LDR R3, =0x40038044 /* &pads_bank0_hw->io[16] */
LDR R2, [R3] /* load current config */
BIC R2, R2, #0x80 /* clear OD (bit 7) - enable output */
ORR R2, R2, #0x40 /* set IE (bit 6) - enable input buffer */
STR R2, [R3] /* store updated config */
```
**What this does:**
- Clears OD (Output Disable) bit → Allows pin to drive output
- Sets IE (Input Enable) bit → Enables input buffer for reading
- Preserves other settings (pull-ups, drive strength, etc.)
### 5. Function Selection
```assembly
/* Set GPIO16 function to SIO (Software I/O) */
LDR R3, =0x40028084 /* &io_bank0_hw->io[16].ctrl */
LDR R2, [R3] /* load current config */
BIC R2, R2, #0x1F /* clear FUNCSEL bits [4:0] */
ORR R2, R2, #5 /* set FUNCSEL = 5 (SIO) */
STR R2, [R3] /* store updated config */
```
**Function 5 (SIO):**
- Routes GPIO to software control
- Required before using coprocessor GPIO operations
- Other functions route to hardware peripherals (UART, SPI, etc.)
### 6. Pad Isolation
```assembly
/* Un-isolate the pad */
LDR R3, =0x40038044 /* &pads_bank0_hw->io[16] */
LDR R2, [R3] /* load current config */
BIC R2, R2, #0x100 /* clear ISO bit (bit 8) */
STR R2, [R3] /* store updated config */
```
**ISO bit:**
- When set (1): Pad is isolated from peripherals
- When clear (0): Pad is connected and functional
- Must be cleared for GPIO to work
### 7. Enable GPIO Output
```assembly
/* Enable output using coprocessor */
MOVS R4, #16 /* GPIO16 */
MOVS R5, #1 /* Enable output */
MCRR p0, #4, R4, R5, c4 /* gpioc_bit_oe_put(16, 1) */
```
**This is the first coprocessor instruction!**
- Sets the Output Enable (OE) bit for GPIO16
- Makes the pin drive its output value
- Uses coprocessor register c4 (OE control)
### 8. Main Blink Loop
```assembly
blink_loop:
/* Turn LED ON */
MOVS R4, #16 /* GPIO16 */
MOVS R5, #1 /* HIGH */
MCRR p0, #4, R4, R5, c0 /* gpioc_bit_out_put(16, 1) */
/* Delay ~500ms */
LDR R2, =2000000 /* 2M cycles */
delay_on:
SUBS R2, R2, #1 /* Decrement */
BNE delay_on /* Loop until zero */
/* Turn LED OFF */
MOVS R4, #16 /* GPIO16 */
MOVS R5, #0 /* LOW */
MCRR p0, #4, R4, R5, c0 /* gpioc_bit_out_put(16, 0) */
/* Delay ~500ms */
LDR R2, =2000000 /* 2M cycles */
delay_off:
SUBS R2, R2, #1 /* Decrement */
BNE delay_off /* Loop until zero */
B blink_loop /* Repeat forever */
```
**Delay Calculation:**
- 2,000,000 cycles at ~4-12 MHz boot clock
- Approximately 500ms per delay
- Total period: ~1 second (1Hz blink rate)
---
## Build Process
### Prerequisites
1. **ARM GNU Toolchain** installed and in PATH:
- `arm-none-eabi-as` (Assembler)
- `arm-none-eabi-ld` (Linker)
- `arm-none-eabi-objcopy` (Object copy utility)
2. **Python** (for UF2 conversion)
3. **uf2conv.py** script (located two directories up: `../../uf2conv.py`)
### Build Script (`build.bat`)
```batch
@echo off
REM Build script for RP2350 GPIO16 blink
echo Building GPIO16 blink...
REM Assemble main code
arm-none-eabi-as -mcpu=cortex-m33 -mthumb gpio16_blink.s -o gpio16_blink.o
REM Assemble image definition
arm-none-eabi-as -mcpu=cortex-m33 -mthumb image_def.s -o image_def.o
REM Link with linker script
arm-none-eabi-ld -T linker.ld gpio16_blink.o image_def.o -o gpio16_blink.elf
REM Create raw binary
arm-none-eabi-objcopy -O binary gpio16_blink.elf gpio16_blink.bin
REM Create UF2 bootloader format
python ..\..\uf2conv.py -b 0x10000000 -f 0xe48bff59 -o gpio16_blink.uf2 gpio16_blink.bin
```
### Build Command
```powershell
.\build.bat
```
### Build Flags Explained
**`-mcpu=cortex-m33`**
- Target the Cortex-M33 processor in RP2350
- Enables M33-specific features (stack limits, DSB/ISB instructions, coprocessor)
**`-mthumb`**
- Generate Thumb-2 instruction set (mandatory for Cortex-M)
- Provides 16-bit and 32-bit instruction mix for code density
**`-T linker.ld`**
- Use custom linker script to define memory layout
- Places code at flash start (0x10000000)
**UF2 Parameters:**
- `-b 0x10000000` - Base address (RP2350 flash start)
- `-f 0xe48bff59` - Family ID for RP2350
- `-o gpio16_blink.uf2` - Output filename
---
## Flashing Instructions
### Method 1: UF2 Bootloader (Easiest)
1. **Disconnect** the RP2350 from USB
2. **Hold the BOOTSEL button** on the board
3. **Connect USB cable** while holding BOOTSEL
4. **Release BOOTSEL** - Board appears as USB mass storage device
5. **Copy** `gpio16_blink.uf2` to the RP2350 drive
6. **Board automatically reboots** and starts running the program
### Method 2: OpenOCD with Debug Probe
If you have a debug probe (e.g., Raspberry Pi Debug Probe, CMSIS-DAP):
```bash
openocd -f interface/cmsis-dap.cfg -f target/rp2350.cfg \
-c "adapter speed 5000" \
-c "program gpio16_blink.elf verify reset exit"
```
---
## Debugging & Troubleshooting
### Problem: LED doesn't blink
**Check 1: Coprocessor Access**
- Ensure CPACR is set correctly
- Without this, MCRR triggers UsageFault
- Verify DSB/ISB barriers are present
**Check 2: GPIO Configuration**
- Verify FUNCSEL is set to 5 (SIO)
- Check OD bit is cleared (output enabled)
- Ensure ISO bit is cleared (pad connected)
**Check 3: Hardware Connections**
- LED polarity (anode to GPIO, cathode to GND)
- Current-limiting resistor present
- GPIO16 physically connected
**Check 4: Clock Speed**
- Boot clock may vary (4-12 MHz typical)
- Delay timing depends on actual clock
- Adjust delay constant if needed
### Problem: Build fails
**Missing toolchain:**
```
'arm-none-eabi-as' is not recognized...
```
Solution: Install ARM GNU Toolchain and add to PATH
**Missing uf2conv.py:**
```
python: can't open file 'uf2conv.py'
```
Solution: Ensure uf2conv.py is in `../../` relative to build directory
**Assembly errors:**
```
Error: bad instruction 'mcrr'
```
Solution: Ensure `-mcpu=cortex-m33` flag is used (M33 supports coprocessor)
### Problem: Board doesn't appear as USB drive
**Solution 1:** Try different USB cable (must support data, not just power)
**Solution 2:** Hold BOOTSEL earlier (before connecting USB)
**Solution 3:** Check USB port functionality
---
## Performance Analysis
### Instruction Cycle Counts (Approximate)
**Traditional GPIO Write (3-4 instructions):**
```assembly
LDR R0, =SIO_BASE ; 2 cycles
LDR R1, =GPIO16_BIT ; 2 cycles
STR R1, [R0, #offset] ; 2 cycles
; Total: ~6 cycles + memory latency
```
**Coprocessor GPIO Write (2 instructions):**
```assembly
MOVS R4, #16 ; 1 cycle
MOVS R5, #1 ; 1 cycle
MCRR p0, #4, R4, R5, c0 ; 1 cycle (hardware accelerated)
; Total: ~3 cycles
```
**Performance Gain: ~50% faster execution**
### Memory Usage
| Section | Size | Location |
|-------------|---------|----------------|
| Vector Table| 8 bytes | 0x10000000 |
| Code (.text)| ~140 bytes | 0x10000008 |
| Total Flash | ~148 bytes | Flash |
| Stack | 32 KB | RAM (0x2007A000-0x20082000) |
**UF2 File Size:** 512 bytes (minimum UF2 block size)
---
## Advanced Topics
### Extending to Multiple GPIOs
To control multiple GPIOs with coprocessor:
```assembly
; Blink GPIO16 and GPIO17 alternately
blink_multi:
; Turn GPIO16 ON, GPIO17 OFF
MOVS R4, #16
MOVS R5, #1
MCRR p0, #4, R4, R5, c0
MOVS R4, #17
MOVS R5, #0
MCRR p0, #4, R4, R5, c0
; Delay...
; Turn GPIO16 OFF, GPIO17 ON
MOVS R4, #16
MOVS R5, #0
MCRR p0, #4, R4, R5, c0
MOVS R4, #17
MOVS R5, #1
MCRR p0, #4, R4, R5, c0
```
### Reading GPIO with Coprocessor
The RP2350 also supports GPIO read operations:
```assembly
; Read GPIO state using MRRC (Move to ARM Registers from Coprocessor)
MOVS R4, #16 ; GPIO to read
MRRC p0, #opcode, R4, R5, c0 ; Result in R5
```
*(Exact opcode may vary - consult RP2350 datasheet)*
### Interrupt-Driven Delays
For production code, replace busy-wait delays with timer interrupts:
```assembly
; Configure SysTick for 1ms interrupts
LDR R0, =0xE000E010 ; SysTick base
LDR R1, =4000 ; Reload value for 1ms at 4MHz
STR R1, [R0, #4] ; SYST_RVR
MOV R1, #7 ; Enable + interrupt + clock
STR R1, [R0, #0] ; SYST_CSR
```
---
## Reference Documentation
### Official Documentation
1. **RP2350 Datasheet** - Complete hardware reference
- Section on GPIO Coprocessor (CP0)
- Register maps and bit definitions
- Electrical characteristics
2. **ARM Cortex-M33 Technical Reference Manual**
- Coprocessor interface specification
- MCRR/MRRC instruction encoding
- Stack limit and security features
3. **ARM Architecture Reference Manual (ARMv8-M)**
- Thumb-2 instruction set
- System control registers (CPACR, etc.)
- Exception handling
### Instruction Reference
**MCRR (Move to Coprocessor from ARM Registers):**
```
MCRR coproc, opc1, Rt, Rt2, CRm
coproc: p0-p15 (coprocessor number)
opc1: 4-bit operation code
Rt: First source register
Rt2: Second source register
CRm: Coprocessor register
```
**DSB (Data Synchronization Barrier):**
- Ensures completion of memory operations
- Required after CPACR modification
**ISB (Instruction Synchronization Barrier):**
- Flushes instruction pipeline
- Required after system control changes
---
## Version History
### Version 1.0 (October 2025)
- Initial release
- Implements GPIO16 blink using coprocessor
- 500ms on/off cycle
- CPACR enablement for CP0 access
- Proper initialization sequence
---
## License & Credits
This code is provided as-is for educational and experimental purposes.
**Created for:** Bare-metal RP2350 development
**Target Board:** Raspberry Pi Pico 2 (RP2350)
**Architecture:** ARM Cortex-M33
**Assembly Syntax:** GNU AS (Unified ARM Syntax)
---
## Future Enhancements
Potential improvements:
1. **Add interrupt-driven timing** instead of busy-wait loops
2. **Implement GPIO read operations** using MRRC
3. **Create PWM effects** using variable duty cycles
4. **Multi-GPIO patterns** (Knight Rider, binary counter, etc.)
5. **Add error handling** for fault exceptions
6. **Clock configuration** for precise timing
7. **Low-power modes** using WFI (Wait For Interrupt)
---
## Contact & Support
For issues, questions, or contributions related to this coprocessor implementation, please refer to:
- RP2350 community forums
- ARM Cortex-M33 documentation
- Raspberry Pi Pico SDK examples
**Happy coding with coprocessors!** 🚀
## License
[Apache License 2.0](https://github.com/mytechnotalent/RP2350_Blink_Driver/blob/main/LICENSE)

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@echo off
REM ============================================================================
REM ==============================================================================
REM FILE: build.bat
REM
REM DESCRIPTION:
REM Build script for RP2350 GPIO16 Blink (Coprocessor Version).
REM Build script for RP2350.
REM Automates the process of assembling, linking, and generating UF2 firmware.
REM
REM AUTHOR: Kevin Thomas
@@ -16,46 +16,46 @@ REM 2. Link objects with linker script (linker.ld)
REM 3. Convert ELF to BIN
REM 4. Convert BIN to UF2 with correct family ID (RP2350 = 0xe48bff59)
REM 5. Provide flashing instructions (UF2 drag‑and‑drop or OpenOCD)
REM ============================================================================
REM ==============================================================================
echo Building GPIO16 blink...
REM ============================================================================
REM ==============================================================================
REM Assemble source files
REM ============================================================================
arm-none-eabi-as -mcpu=cortex-m33 -mthumb gpio16_blink.s -o gpio16_blink.o
REM ==============================================================================
arm-none-eabi-as -mcpu=cortex-m33 -mthumb main.s -o main.o
if errorlevel 1 goto error
arm-none-eabi-as -mcpu=cortex-m33 -mthumb image_def.s -o image_def.o
if errorlevel 1 goto error
REM ============================================================================
REM ==============================================================================
REM Link object files into ELF using linker script
REM ============================================================================
REM ==============================================================================
arm-none-eabi-ld -T linker.ld gpio16_blink.o image_def.o -o gpio16_blink.elf
if errorlevel 1 goto error
REM ============================================================================
REM ==============================================================================
REM Create raw binary from ELF
REM ============================================================================
REM ==============================================================================
arm-none-eabi-objcopy -O binary gpio16_blink.elf gpio16_blink.bin
if errorlevel 1 goto error
REM ============================================================================
REM ==============================================================================
REM Create UF2 image for RP2350
REM -b 0x10000000 : base address
REM -f 0xe48bff59 : RP2350 family ID
REM ============================================================================
python ..\..\uf2conv.py -b 0x10000000 -f 0xe48bff59 -o gpio16_blink.uf2 gpio16_blink.bin
REM ==============================================================================
python uf2conv.py -b 0x10000000 -f 0xe48bff59 -o gpio16_blink.uf2 gpio16_blink.bin
if errorlevel 1 goto error
REM ============================================================================
REM ==============================================================================
REM Success message and flashing instructions
REM ============================================================================
REM ==============================================================================
echo.
echo ========================================
echo =================================
echo SUCCESS! Created gpio16_blink.uf2
echo ========================================
echo =================================
echo.
echo To flash via UF2:
echo 1. Hold BOOTSEL button
@@ -67,9 +67,9 @@ echo openocd -f interface/cmsis-dap.cfg -f target/rp2350.cfg -c "adapter speed
echo.
goto end
REM ============================================================================
REM ==============================================================================
REM Error handling
REM ============================================================================
REM ==============================================================================
:error
echo.
echo BUILD FAILED!

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/**
* FILE: main.s
*
* DESCRIPTION:
* RP2350 Bare-Metal GPIO16 Blink, Coprocessor Version.
* Minimal bare‑metal LED blink on the RP2350 using direct coprocessor
* (MCRR) instructions to manipulate GPIO control registers. This bypasses
* SDK abstractions and demonstrates register‑level control in assembler.
*
* AUTHOR: Kevin Thomas
* CREATION DATE: October 5, 2025
* UPDATE DATE: October 5, 2025
*/
.syntax unified // use unified assembly syntax
.cpu cortex-m33 // target Cortex-M33 core
.thumb // use Thumb instruction set
/**
* Memory addresses and constants.
*/
.equ IO_BANK0_BASE, 0x40028000 // base address of IO_BANK0
.equ PADS_BANK0_BASE, 0x40038000 // base address of PADS_BANK0
.equ SIO_BASE, 0xD0000000 // base address of SIO block
.equ GPIO16_CTRL, 0x84 // io[16].ctrl offset
.equ GPIO16_PAD, 0x44 // pads io[16] offset
.equ GPIO16_BIT, (1 << 16) // bit mask for GPIO16
.equ GPIO_OUT_SET, 0x18 // SIO->GPIO_OUT_SET offset
.equ GPIO_OUT_XOR, 0x28 // SIO->GPIO_OUT_XOR offset
.equ GPIO_OE_SET, 0x38 // SIO->GPIO_OE_SET offset
.equ STACK_TOP, 0x20082000 // top of non-secure SRAM
.equ STACK_LIMIT, 0x2007A000 // stack limit (32 KB below top)
/**
* Vector table section.
*/
.section .vectors, "ax" // vector table section
.align 2 // align to 4 bytes
.global _vectors // export symbol
_vectors:
.word STACK_TOP // initial stack pointer
.word Reset_Handler + 1 // reset handler (Thumb bit set)
/**
* @brief Reset handler for RP2350.
* @details Entry point after reset. Performs:
* - Stack initialization
* - Coprocessor enable
* - GPIO16 pad/function configuration
* - Infinite blink loop using coprocessor writes
* @param None
* @retval None
*/
.section .text // code section
.align 2 // align functions
.global Reset_Handler // export Reset_Handler
.type Reset_Handler, %function // mark as function
Reset_Handler:
BL init_stack // initialize MSP/PSP and limits
BL enable_coprocessor // enable CP0 in CPACR for MCRR
BL gpio16_config // configure pads and FUNCSEL for GPIO16
blink_loop:
BL gpio16_set // set GPIO16 high
BL delay // delay ~500 ms
BL gpio16_clear // set GPIO16 low
BL delay // delay ~500 ms
B blink_loop // loop forever
.size Reset_Handler, . - Reset_Handler
/**
* @brief Initialize stack pointers.
* @details Sets Main and Process Stack Pointers (MSP/PSP) and their limits.
* @param None
* @retval None
*/
.type init_stack, %function
init_stack:
LDR R0, =STACK_TOP // load stack top
MSR PSP, R0 // set PSP
LDR R0, =STACK_LIMIT // load stack limit
MSR MSPLIM, R0 // set MSP limit
MSR PSPLIM, R0 // set PSP limit
LDR R0, =STACK_TOP // reload stack top
MSR MSP, R0 // set MSP
BX LR // return
/**
* @brief Enable coprocessor access.
* @details Grants full access to coprocessor 0 (CP0) via CPACR.
* @param None
* @retval None
*/
.type enable_coprocessor, %function
enable_coprocessor:
LDR R0, =0xE000ED88 // CPACR address
LDR R1, [R0] // read CPACR
ORR R1, R1, #0x3 // set CP0 full access
STR R1, [R0] // write CPACR
DSB // data sync barrier
ISB // instruction sync barrier
BX LR // return
/**
* @brief Configure GPIO16 for SIO control.
* @details Sets pad control (IE, OD, ISO) and FUNCSEL = 5 (SIO). Enables OE.
* @param None
* @retval None
*/
.type gpio16_config, %function
gpio16_config:
LDR R3, =PADS_BANK0_BASE + GPIO16_PAD // pad control address
LDR R2, [R3] // read pad config
BIC R2, R2, #0x80 // clear OD
ORR R2, R2, #0x40 // set IE
BIC R2, R2, #0x100 // clear ISO
STR R2, [R3] // write pad config
LDR R3, =IO_BANK0_BASE + GPIO16_CTRL // IO control address
LDR R2, [R3] // read IO config
BIC R2, R2, #0x1F // clear FUNCSEL
ORR R2, R2, #5 // set FUNCSEL = 5
STR R2, [R3] // write IO config
MOVS R4, #16 // GPIO number
MOVS R5, #1 // enable output
MCRR p0, #4, R4, R5, c4 // gpioc_bit_oe_put(16, 1)
BX LR // return
/**
* @brief Set GPIO16 high.
* @details Drives GPIO16 output = 1 via coprocessor MCRR.
* @param None
* @retval None
*/
.type gpio16_set, %function
gpio16_set:
MOVS R4, #16 // GPIO number
MOVS R5, #1 // logic high
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 1)
BX LR // return
/**
* @brief Clear GPIO16 (set low).
* @details Drives GPIO16 output = 0 via coprocessor MCRR.
* @param None
* @retval None
*/
.type gpio16_clear, %function
gpio16_clear:
MOVS R4, #16 // GPIO number
MOVS R5, #0 // logic low
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 0)
BX LR // return
/**
* @brief Busy‑wait delay loop.
* @details Consumes ~2,000,000 cycles to approximate ~500 ms at boot clock.
* @param None
* @retval None
*/
.type delay, %function
delay:
LDR R2, =2000000 // loop count
1:SUBS R2, R2, #1 // decrement
BNE 1b // loop until zero
BX LR // return

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* binary for the bootrom to recognise it as a valid program image, as opposed to,
* for example, blank flash contents or a disconnected flash device. This must
* appear within the first 4 kB of a flash image, or anywhere in a RAM or OTP image.
*
* Unlike RP2040, there is no requirement for flash binaries to have a checksummed
* "boot2" flash setup function at flash address 0. The RP2350 bootrom performs a
* simple best‑effort XIP setup during flash scanning, and a flash‑resident program

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/**
* FILE: main.s
*
* DESCRIPTION:
* RP2350 Bare-Metal GPIO16 Blink, Coprocessor Version.
* Minimal bare‑metal LED blink on the RP2350 using direct coprocessor
* (MCRR) instructions to manipulate GPIO control registers. This bypasses
* SDK abstractions and demonstrates register‑level control in assembler.
*
* AUTHOR: Kevin Thomas
* CREATION DATE: October 5, 2025
* UPDATE DATE: October 5, 2025
*/
.syntax unified // use unified assembly syntax
.cpu cortex-m33 // target Cortex-M33 core
.thumb // use Thumb instruction set
/**
* Memory addresses and constants.
*/
.equ IO_BANK0_BASE, 0x40028000 // base address of IO_BANK0
.equ PADS_BANK0_BASE, 0x40038000 // base address of PADS_BANK0
.equ SIO_BASE, 0xD0000000 // base address of SIO block
.equ GPIO16_CTRL, 0x84 // io[16].ctrl offset
.equ GPIO16_PAD, 0x44 // pads io[16] offset
.equ GPIO16_BIT, (1<<16) // bit mask for GPIO16
.equ GPIO_OUT_SET, 0x18 // SIO->GPIO_OUT_SET offset
.equ GPIO_OUT_XOR, 0x28 // SIO->GPIO_OUT_XOR offset
.equ GPIO_OE_SET, 0x38 // SIO->GPIO_OE_SET offset
.equ STACK_TOP, 0x20082000 // top of non-secure SRAM
.equ STACK_LIMIT, 0x2007A000 // stack limit (32 KB below top)
/**
* Initialize the .vectors section. The .vectors section contains vector
* table.
*/
.section .vectors, "ax" // vector table section
.align 2 // align to 4-byte boundary
/**
* Vector table section.
*/
.global _vectors // export symbol
_vectors:
.word STACK_TOP // initial stack pointer
.word Reset_Handler + 1 // reset handler (Thumb bit set)
/**
* @brief Reset handler for RP2350.
*
* @details Entry point after reset. Performs:
* - Stack initialization
* - Coprocessor enable
* - GPIO16 pad/function configuration
* - Branches to main() which contains the blink loop
*
* @param None
* @retval None
*/
.global Reset_Handler // export Reset_Handler
.type Reset_Handler, %function // mark as function
Reset_Handler:
BL Init_Stack // initialize MSP/PSP and limits
BL Enable_Coprocessor // enable CP0 in CPACR for MCRR
B main // branch to main loop
.size Reset_Handler, . - Reset_Handler
/**
* @brief Initialize stack pointers.
*
* @details Sets Main and Process Stack Pointers (MSP/PSP) and their limits.
*
* @param None
* @retval None
*/
.type Init_Stack, %function
Init_Stack:
LDR R0, =STACK_TOP // load stack top
MSR PSP, R0 // set PSP
LDR R0, =STACK_LIMIT // load stack limit
MSR MSPLIM, R0 // set MSP limit
MSR PSPLIM, R0 // set PSP limit
LDR R0, =STACK_TOP // reload stack top
MSR MSP, R0 // set MSP
BX LR // return
/**
* @brief Enable coprocessor access.
*
* @details Grants full access to coprocessor 0 (CP0) via CPACR.
*
* @param None
* @retval None
*/
.type Enable_Coprocessor , %function
Enable_Coprocessor:
LDR R0, =0xE000ED88 // CPACR address
LDR R1, [R0] // read CPACR
ORR R1, R1, #0x3 // set CP0 full access
STR R1, [R0] // write CPACR
DSB // data sync barrier
ISB // instruction sync barrier
BX LR // return
/**
* Initialize the .text section.
* The .text section contains executable code.
*/
.section .text // code section
.align 2 // align to 4-byte boundary
/**
* @brief Main application entry point.
*
* @details Implements the infinite blink loop:
* - Set GPIO16 high
* - Delay ~500 ms
* - Set GPIO16 low
* - Delay ~500 ms
* - Repeat forever
*
* @param None
* @retval None
*/
.global main // export main
.type main, %function // mark as function
main:
.Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Config:
BL GPIO16_Config // configure pads and FUNCSEL for GPIO16
.Loop:
BL GPIO16_Set // set GPIO16 high
BL Delay_500ms // ~500 ms delay
BL GPIO16_Clear // set GPIO16 low
BL Delay_500ms // ~500 ms delay
B Loop // loop forever
.Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Configure GPIO16 for SIO control.
*
* @details Sets pad control (IE, OD, ISO) and FUNCSEL = 5 (SIO). Enables OE.
*
* @param None
* @retval None
*/
.type GPIO16_Config, %function
GPIO16_Config:
.GPIO16_Config_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Config_Modify_Pad:
LDR R3, =PADS_BANK0_BASE + GPIO16_PAD // pad control address
LDR R2, [R3] // read pad config
BIC R2, R2, #0x80 // clear OD
ORR R2, R2, #0x40 // set IE
BIC R2, R2, #0x100 // clear ISO
STR R2, [R3] // write pad config
.GPIO16_Config_Modify_IO:
LDR R3, =IO_BANK0_BASE + GPIO16_CTRL // IO control address
LDR R2, [R3] // read IO config
BIC R2, R2, #0x1F // clear FUNCSEL
ORR R2, R2, #5 // set FUNCSEL=5
STR R2, [R3] // write IO config
.GPIO16_Config_Enable_OE:
MOVS R4, #16 // GPIO number
MOVS R5, #1 // enable output
MCRR p0, #4, R4, R5, c4 // gpioc_bit_oe_put(16, 1)
.GPIO16_Config_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return
/**
* @brief Set GPIO16 high.
*
* @details Drives GPIO16 output = 1 via coprocessor MCRR.
*
* @param None
* @retval None
*/
.type GPIO16_Set, %function
GPIO16_Set:
.GPIO16_Set_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Set_Load_Operands:
MOVS R4, #16 // GPIO number
MOVS R5, #1 // logic high
.GPIO16_Set_Execute:
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 1)
.GPIO16_Set_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Clear GPIO16 (set low).
*
* @details Drives GPIO16 output = 0 via coprocessor MCRR.
*
* @param None
* @retval None
*/
.type GPIO16_Clear, %function
GPIO16_Clear:
.GPIO16_Clear_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.GPIO16_Clear_Load_Operands:
MOVS R4, #16 // GPIO number
MOVS R5, #0 // logic low
.GPIO16_Clear_Execute:
MCRR p0, #4, R4, R5, c0 // gpioc_bit_out_put(16, 0)
.GPIO16_Clear_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* @brief Busy‑wait Delay_500ms loop.
*
* @details Consumes ~2,000,000 cycles to approximate ~500 ms at boot clock.
*
* @param None
* @retval None
*/
.type Delay_500ms, %function
Delay_500ms:
.Delay_500ms_Push_Registers:
PUSH {R4-R12, LR} // push registers R4-R12, LR to the stack
.Delay_500ms_Setup:
LDR R2, =2000000 // loop count (~500 ms)
.Delay_500ms_Loop:
SUBS R2, R2, #1 // decrement counter
BNE .Delay_500ms_Loop // branch until zero
.Delay_500ms_Pop_Registers:
POP {R4-R12, LR} // pop registers R4-R12, LR from the stack
BX LR // return to caller
/**
* Test data and constants.
* The .rodata section is used for constants and static data.
*/
.section .rodata // read-only data section
/**
* Initialized global data.
* The .data section is used for initialized global or static variables.
*/
.section .data // data section
/**
* Uninitialized global data.
* The .bss section is used for uninitialized global or static variables.
*/
.section .bss // BSS section

69
RA-0x0001-GPIO-Output/review.bat
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@@ -1,69 +0,0 @@
@echo off
REM ============================================================================
REM FILE: review.bat
REM
REM DESCRIPTION:
REM Review script for RP2350 ELF and BIN outputs.
REM Runs a suite of GNU binutils tools to inspect ELF and BIN files.
REM Dumps results into text files for easy review.
REM
REM AUTHOR: Kevin Thomas
REM CREATION DATE: October 5, 2025
REM UPDATE DATE: October 5, 2025
REM ============================================================================
set ELF_FILE=gpio16_blink.elf
set BIN_FILE=gpio16_blink.bin
set OUT_DIR=review_reports
if not exist %OUT_DIR% mkdir %OUT_DIR%
echo Reviewing %ELF_FILE% and %BIN_FILE% ...
REM ============================================================================
REM ELF inspection tools
REM ============================================================================
arm-none-eabi-readelf -a %ELF_FILE% > %OUT_DIR%\readelf_all.txt
arm-none-eabi-readelf -h %ELF_FILE% > %OUT_DIR%\readelf_header.txt
arm-none-eabi-readelf -S %ELF_FILE% > %OUT_DIR%\readelf_sections.txt
arm-none-eabi-readelf -s %ELF_FILE% > %OUT_DIR%\readelf_symbols.txt
arm-none-eabi-readelf -r %ELF_FILE% > %OUT_DIR%\readelf_relocs.txt
arm-none-eabi-objdump -x %ELF_FILE% > %OUT_DIR%\objdump_headers.txt
arm-none-eabi-objdump -d %ELF_FILE% > %OUT_DIR%\objdump_disasm.txt
arm-none-eabi-objdump -s %ELF_FILE% > %OUT_DIR%\objdump_fullhex.txt
arm-none-eabi-objdump -h %ELF_FILE% > %OUT_DIR%\objdump_sections.txt
arm-none-eabi-nm -n %ELF_FILE% > %OUT_DIR%\nm_symbols.txt
arm-none-eabi-size %ELF_FILE% > %OUT_DIR%\size.txt
arm-none-eabi-strings %ELF_FILE% > %OUT_DIR%\strings.txt
REM ============================================================================
REM BIN inspection tools
REM ============================================================================
xxd -g4 -l 256 %BIN_FILE% > %OUT_DIR%\bin_hexdump.txt
REM ============================================================================
REM Summary
REM ============================================================================
echo.
echo ========================================
echo REVIEW COMPLETE
echo Reports written to %OUT_DIR%\
echo ========================================
echo.
echo Key files:
echo - readelf_all.txt (everything about ELF)
echo - objdump_disasm.txt (disassembly)
echo - nm_symbols.txt (symbols)
echo - size.txt (section sizes)
echo - bin_hexdump.txt (first 256 bytes of BIN)
echo.
goto end
:error
echo.
echo REVIEW FAILED!
echo.
:end

0
RA-0x0001-GPIO-Output/review_reports/bin_hexdump.txt
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28
RA-0x0001-GPIO-Output/review_reports/nm_symbols.txt
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@@ -1,28 +0,0 @@
00000018 a GPIO_OUT_SET
00000028 a GPIO_OUT_XOR
00000038 a GPIO_OE_SET
00000044 a GPIO16_PAD
00000084 a GPIO16_CTRL
00008000 A __STACK_SIZE
00010000 a GPIO16_BIT
00080000 A __SRAM_SIZE
02000000 A __XIP_SIZE
10000000 A __XIP_BASE
10000000 T _vectors
10000008 T Reset_Handler
10000014 t blink_loop
10000026 t init_stack
1000003e t enable_coprocessor
10000052 t gpio16_config
1000007c t gpio16_set
10000086 t gpio16_clear
10000090 t delay
20000000 A __SRAM_BASE
20078000 A __StackLimit
2007a000 a STACK_LIMIT
20080000 A __stack
20080000 T __StackTop
20082000 a STACK_TOP
40028000 a IO_BANK0_BASE
40038000 a PADS_BANK0_BASE
d0000000 a SIO_BASE

101
RA-0x0001-GPIO-Output/review_reports/objdump_disasm.txt
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@@ -1,101 +0,0 @@
gpio16_blink.elf: file format elf32-littlearm
Disassembly of section .vectors:
10000000 <_vectors>:
10000000: 20082000 .word 0x20082000
10000004: 10000009 .word 0x10000009
Disassembly of section .text:
10000008 <Reset_Handler>:
10000008: f000 f80d bl 10000026 <init_stack>
1000000c: f000 f817 bl 1000003e <enable_coprocessor>
10000010: f000 f81f bl 10000052 <gpio16_config>
10000014 <blink_loop>:
10000014: f000 f832 bl 1000007c <gpio16_set>
10000018: f000 f83a bl 10000090 <delay>
1000001c: f000 f833 bl 10000086 <gpio16_clear>
10000020: f000 f836 bl 10000090 <delay>
10000024: e7f6 b.n 10000014 <blink_loop>
10000026 <init_stack>:
10000026: 481c ldr r0, [pc, #112] @ (10000098 <delay+0x8>)
10000028: f380 8809 msr PSP, r0
1000002c: 481b ldr r0, [pc, #108] @ (1000009c <delay+0xc>)
1000002e: f380 880a msr MSPLIM, r0
10000032: f380 880b msr PSPLIM, r0
10000036: 4818 ldr r0, [pc, #96] @ (10000098 <delay+0x8>)
10000038: f380 8808 msr MSP, r0
1000003c: 4770 bx lr
1000003e <enable_coprocessor>:
1000003e: 4818 ldr r0, [pc, #96] @ (100000a0 <delay+0x10>)
10000040: 6801 ldr r1, [r0, #0]
10000042: f041 0103 orr.w r1, r1, #3
10000046: 6001 str r1, [r0, #0]
10000048: f3bf 8f4f dsb sy
1000004c: f3bf 8f6f isb sy
10000050: 4770 bx lr
10000052 <gpio16_config>:
10000052: 4b14 ldr r3, [pc, #80] @ (100000a4 <delay+0x14>)
10000054: 681a ldr r2, [r3, #0]
10000056: f022 0280 bic.w r2, r2, #128 @ 0x80
1000005a: f042 0240 orr.w r2, r2, #64 @ 0x40
1000005e: f422 7280 bic.w r2, r2, #256 @ 0x100
10000062: 601a str r2, [r3, #0]
10000064: 4b10 ldr r3, [pc, #64] @ (100000a8 <delay+0x18>)
10000066: 681a ldr r2, [r3, #0]
10000068: f022 021f bic.w r2, r2, #31
1000006c: f042 0205 orr.w r2, r2, #5
10000070: 601a str r2, [r3, #0]
10000072: 2410 movs r4, #16
10000074: 2501 movs r5, #1
10000076: ec45 4044 stcl 0, cr4, [r5], {68} @ 0x44
1000007a: 4770 bx lr
1000007c <gpio16_set>:
1000007c: 2410 movs r4, #16
1000007e: 2501 movs r5, #1
10000080: ec45 4040 stcl 0, cr4, [r5], {64} @ 0x40
10000084: 4770 bx lr
10000086 <gpio16_clear>:
10000086: 2410 movs r4, #16
10000088: 2500 movs r5, #0
1000008a: ec45 4040 stcl 0, cr4, [r5], {64} @ 0x40
1000008e: 4770 bx lr
10000090 <delay>:
10000090: 4a06 ldr r2, [pc, #24] @ (100000ac <delay+0x1c>)
10000092: 3a01 subs r2, #1
10000094: d1fd bne.n 10000092 <delay+0x2>
10000096: 4770 bx lr
10000098: 20082000 .word 0x20082000
1000009c: 2007a000 .word 0x2007a000
100000a0: e000ed88 .word 0xe000ed88
100000a4: 40038044 .word 0x40038044
100000a8: 40028084 .word 0x40028084
100000ac: 001e8480 .word 0x001e8480
100000b0: 00002341 .word 0x00002341
100000b4: 61656100 .word 0x61656100
100000b8: 01006962 .word 0x01006962
100000bc: 00000019 .word 0x00000019
100000c0: 726f4305 .word 0x726f4305
100000c4: 2d786574 .word 0x2d786574
100000c8: 0033334d .word 0x0033334d
100000cc: 4d071106 .word 0x4d071106
100000d0: 012e0309 .word 0x012e0309
100000d4: 00002341 .word 0x00002341
100000d8: 61656100 .word 0x61656100
100000dc: 01006962 .word 0x01006962
100000e0: 00000019 .word 0x00000019
100000e4: 726f4305 .word 0x726f4305
100000e8: 2d786574 .word 0x2d786574
100000ec: 0033334d .word 0x0033334d
100000f0: 4d071106 .word 0x4d071106
100000f4: 012e0309 .word 0x012e0309

24
RA-0x0001-GPIO-Output/review_reports/objdump_fullhex.txt
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@@ -1,24 +0,0 @@
gpio16_blink.elf: file format elf32-littlearm
Contents of section .vectors:
10000000 00200820 09000010 . . ....
Contents of section .text:
10000008 00f00df8 00f017f8 00f01ff8 00f032f8 ..............2.
10000018 00f03af8 00f033f8 00f036f8 f6e71c48 ..:...3...6....H
10000028 80f30988 1b4880f3 0a8880f3 0b881848 .....H.........H
10000038 80f30888 70471848 016841f0 03010160 ....pG.H.hA....`
10000048 bff34f8f bff36f8f 7047144b 1a6822f0 ..O...o.pG.K.h".
10000058 800242f0 400222f4 80721a60 104b1a68 ..B.@."..r.`.K.h
10000068 22f01f02 42f00502 1a601024 012545ec "...B....`.$.%E.
10000078 44407047 10240125 45ec4040 70471024 D@pG.$.%E.@@pG.$
10000088 002545ec 40407047 064a013a fdd17047 .%E.@@pG.J.:..pG
10000098 00200820 00a00720 88ed00e0 44800340 . . ... ....D..@
100000a8 84800240 80841e00 41230000 00616561 ...@....A#...aea
100000b8 62690001 19000000 05436f72 7465782d bi.......Cortex-
100000c8 4d333300 0611074d 09032e01 41230000 M33....M....A#..
100000d8 00616561 62690001 19000000 05436f72 .aeabi.......Cor
100000e8 7465782d 4d333300 0611074d 09032e01 tex-M33....M....
Contents of section .picobin_block:
100000f8 d3deffff 42012110 ff010000 00000000 ....B.!.........
10000108 793512ab y5..

58
RA-0x0001-GPIO-Output/review_reports/objdump_headers.txt
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@@ -1,58 +0,0 @@
gpio16_blink.elf: file format elf32-littlearm
gpio16_blink.elf
architecture: armv3m, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x10000009
Program Header:
LOAD off 0x00001000 vaddr 0x10000000 paddr 0x10000000 align 2**12
filesz 0x0000010c memsz 0x0000010c flags r-x
private flags = 0x5000200: [Version5 EABI] [soft-float ABI]
Sections:
Idx Name Size VMA LMA File off Algn
0 .vectors 00000008 10000000 10000000 00001000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .text 000000f0 10000008 10000008 00001008 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .picobin_block 00000014 100000f8 100000f8 000010f8 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .stack 00000000 20000000 20000000 0000110c 2**0
CONTENTS
SYMBOL TABLE:
10000000 l d .vectors 00000000 .vectors
10000008 l d .text 00000000 .text
100000f8 l d .picobin_block 00000000 .picobin_block
20000000 l d .stack 00000000 .stack
00000000 l df *ABS* 00000000 gpio16_blink.o
40028000 l *ABS* 00000000 IO_BANK0_BASE
40038000 l *ABS* 00000000 PADS_BANK0_BASE
d0000000 l *ABS* 00000000 SIO_BASE
00000084 l *ABS* 00000000 GPIO16_CTRL
00000044 l *ABS* 00000000 GPIO16_PAD
00010000 l *ABS* 00000000 GPIO16_BIT
00000018 l *ABS* 00000000 GPIO_OUT_SET
00000028 l *ABS* 00000000 GPIO_OUT_XOR
00000038 l *ABS* 00000000 GPIO_OE_SET
20082000 l *ABS* 00000000 STACK_TOP
2007a000 l *ABS* 00000000 STACK_LIMIT
10000026 l F .text 00000000 init_stack
1000003e l F .text 00000000 enable_coprocessor
10000052 l F .text 00000000 gpio16_config
10000014 l .text 00000000 blink_loop
1000007c l F .text 00000000 gpio16_set
10000090 l F .text 00000000 delay
10000086 l F .text 00000000 gpio16_clear
00080000 g *ABS* 00000000 __SRAM_SIZE
10000000 g .vectors 00000000 _vectors
20000000 g *ABS* 00000000 __SRAM_BASE
10000008 g F .text 0000001e Reset_Handler
00008000 g *ABS* 00000000 __STACK_SIZE
20080000 g .text 00000000 __StackTop
20080000 g *ABS* 00000000 __stack
20078000 g *ABS* 00000000 __StackLimit
02000000 g *ABS* 00000000 __XIP_SIZE
10000000 g *ABS* 00000000 __XIP_BASE

13
RA-0x0001-GPIO-Output/review_reports/objdump_sections.txt
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@@ -1,13 +0,0 @@
gpio16_blink.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .vectors 00000008 10000000 10000000 00001000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .text 000000f0 10000008 10000008 00001008 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .picobin_block 00000014 100000f8 100000f8 000010f8 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .stack 00000000 20000000 20000000 0000110c 2**0
CONTENTS

97
RA-0x0001-GPIO-Output/review_reports/readelf_all.txt
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@@ -1,97 +0,0 @@
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: EXEC (Executable file)
Machine: ARM
Version: 0x1
Entry point address: 0x10000009
Start of program headers: 52 (bytes into file)
Start of section headers: 5424 (bytes into file)
Flags: 0x5000200, Version5 EABI, soft-float ABI
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 8
Section header string table index: 7
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .vectors PROGBITS 10000000 001000 000008 00 AX 0 0 4
[ 2] .text PROGBITS 10000008 001008 0000f0 00 AX 0 0 4
[ 3] .picobin_block PROGBITS 100000f8 0010f8 000014 00 A 0 0 1
[ 4] .stack PROGBITS 20000000 00110c 000000 00 W 0 0 1
[ 5] .symtab SYMTAB 00000000 00110c 000280 10 6 30 4
[ 6] .strtab STRTAB 00000000 00138c 000162 00 0 0 1
[ 7] .shstrtab STRTAB 00000000 0014ee 000040 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
C (compressed), x (unknown), o (OS specific), E (exclude),
D (mbind), y (purecode), p (processor specific)
There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x10000000 0x10000000 0x0010c 0x0010c R E 0x1000
Section to Segment mapping:
Segment Sections...
00 .vectors .text .picobin_block
There is no dynamic section in this file.
There are no relocations in this file.
There are no unwind sections in this file.
Symbol table '.symtab' contains 40 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 10000000 0 SECTION LOCAL DEFAULT 1 .vectors
2: 10000008 0 SECTION LOCAL DEFAULT 2 .text
3: 100000f8 0 SECTION LOCAL DEFAULT 3 .picobin_block
4: 20000000 0 SECTION LOCAL DEFAULT 4 .stack
5: 00000000 0 FILE LOCAL DEFAULT ABS gpio16_blink.o
6: 40028000 0 NOTYPE LOCAL DEFAULT ABS IO_BANK0_BASE
7: 40038000 0 NOTYPE LOCAL DEFAULT ABS PADS_BANK0_BASE
8: d0000000 0 NOTYPE LOCAL DEFAULT ABS SIO_BASE
9: 00000084 0 NOTYPE LOCAL DEFAULT ABS GPIO16_CTRL
10: 00000044 0 NOTYPE LOCAL DEFAULT ABS GPIO16_PAD
11: 00010000 0 NOTYPE LOCAL DEFAULT ABS GPIO16_BIT
12: 00000018 0 NOTYPE LOCAL DEFAULT ABS GPIO_OUT_SET
13: 00000028 0 NOTYPE LOCAL DEFAULT ABS GPIO_OUT_XOR
14: 00000038 0 NOTYPE LOCAL DEFAULT ABS GPIO_OE_SET
15: 20082000 0 NOTYPE LOCAL DEFAULT ABS STACK_TOP
16: 2007a000 0 NOTYPE LOCAL DEFAULT ABS STACK_LIMIT
17: 10000000 0 NOTYPE LOCAL DEFAULT 1 $d
18: 10000008 0 NOTYPE LOCAL DEFAULT 2 $t
19: 10000027 0 FUNC LOCAL DEFAULT 2 init_stack
20: 1000003f 0 FUNC LOCAL DEFAULT 2 enable_coprocessor
21: 10000053 0 FUNC LOCAL DEFAULT 2 gpio16_config
22: 10000014 0 NOTYPE LOCAL DEFAULT 2 blink_loop
23: 1000007d 0 FUNC LOCAL DEFAULT 2 gpio16_set
24: 10000091 0 FUNC LOCAL DEFAULT 2 delay
25: 10000087 0 FUNC LOCAL DEFAULT 2 gpio16_clear
26: 10000098 0 NOTYPE LOCAL DEFAULT 2 $d
27: 100000b0 0 NOTYPE LOCAL DEFAULT 2 $d
28: 100000f8 0 NOTYPE LOCAL DEFAULT 3 $d
29: 100000d4 0 NOTYPE LOCAL DEFAULT 2 $d
30: 00080000 0 NOTYPE GLOBAL DEFAULT ABS __SRAM_SIZE
31: 10000000 0 NOTYPE GLOBAL DEFAULT 1 _vectors
32: 20000000 0 NOTYPE GLOBAL DEFAULT ABS __SRAM_BASE
33: 10000009 30 FUNC GLOBAL DEFAULT 2 Reset_Handler
34: 00008000 0 NOTYPE GLOBAL DEFAULT ABS __STACK_SIZE
35: 20080000 0 NOTYPE GLOBAL DEFAULT 2 __StackTop
36: 20080000 0 NOTYPE GLOBAL DEFAULT ABS __stack
37: 20078000 0 NOTYPE GLOBAL DEFAULT ABS __StackLimit
38: 02000000 0 NOTYPE GLOBAL DEFAULT ABS __XIP_SIZE
39: 10000000 0 NOTYPE GLOBAL DEFAULT ABS __XIP_BASE
No version information found in this file.

20
RA-0x0001-GPIO-Output/review_reports/readelf_header.txt
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@@ -1,20 +0,0 @@
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: EXEC (Executable file)
Machine: ARM
Version: 0x1
Entry point address: 0x10000009
Start of program headers: 52 (bytes into file)
Start of section headers: 5424 (bytes into file)
Flags: 0x5000200, Version5 EABI, soft-float ABI
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 8
Section header string table index: 7

2
RA-0x0001-GPIO-Output/review_reports/readelf_relocs.txt
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@@ -1,2 +0,0 @@
There are no relocations in this file.

17
RA-0x0001-GPIO-Output/review_reports/readelf_sections.txt
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@@ -1,17 +0,0 @@
There are 8 section headers, starting at offset 0x1530:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .vectors PROGBITS 10000000 001000 000008 00 AX 0 0 4
[ 2] .text PROGBITS 10000008 001008 0000f0 00 AX 0 0 4
[ 3] .picobin_block PROGBITS 100000f8 0010f8 000014 00 A 0 0 1
[ 4] .stack PROGBITS 20000000 00110c 000000 00 W 0 0 1
[ 5] .symtab SYMTAB 00000000 00110c 000280 10 6 30 4
[ 6] .strtab STRTAB 00000000 00138c 000162 00 0 0 1
[ 7] .shstrtab STRTAB 00000000 0014ee 000040 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
C (compressed), x (unknown), o (OS specific), E (exclude),
D (mbind), y (purecode), p (processor specific)

43
RA-0x0001-GPIO-Output/review_reports/readelf_symbols.txt
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@@ -1,43 +0,0 @@
Symbol table '.symtab' contains 40 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 10000000 0 SECTION LOCAL DEFAULT 1 .vectors
2: 10000008 0 SECTION LOCAL DEFAULT 2 .text
3: 100000f8 0 SECTION LOCAL DEFAULT 3 .picobin_block
4: 20000000 0 SECTION LOCAL DEFAULT 4 .stack
5: 00000000 0 FILE LOCAL DEFAULT ABS gpio16_blink.o
6: 40028000 0 NOTYPE LOCAL DEFAULT ABS IO_BANK0_BASE
7: 40038000 0 NOTYPE LOCAL DEFAULT ABS PADS_BANK0_BASE
8: d0000000 0 NOTYPE LOCAL DEFAULT ABS SIO_BASE
9: 00000084 0 NOTYPE LOCAL DEFAULT ABS GPIO16_CTRL
10: 00000044 0 NOTYPE LOCAL DEFAULT ABS GPIO16_PAD
11: 00010000 0 NOTYPE LOCAL DEFAULT ABS GPIO16_BIT
12: 00000018 0 NOTYPE LOCAL DEFAULT ABS GPIO_OUT_SET
13: 00000028 0 NOTYPE LOCAL DEFAULT ABS GPIO_OUT_XOR
14: 00000038 0 NOTYPE LOCAL DEFAULT ABS GPIO_OE_SET
15: 20082000 0 NOTYPE LOCAL DEFAULT ABS STACK_TOP
16: 2007a000 0 NOTYPE LOCAL DEFAULT ABS STACK_LIMIT
17: 10000000 0 NOTYPE LOCAL DEFAULT 1 $d
18: 10000008 0 NOTYPE LOCAL DEFAULT 2 $t
19: 10000027 0 FUNC LOCAL DEFAULT 2 init_stack
20: 1000003f 0 FUNC LOCAL DEFAULT 2 enable_coprocessor
21: 10000053 0 FUNC LOCAL DEFAULT 2 gpio16_config
22: 10000014 0 NOTYPE LOCAL DEFAULT 2 blink_loop
23: 1000007d 0 FUNC LOCAL DEFAULT 2 gpio16_set
24: 10000091 0 FUNC LOCAL DEFAULT 2 delay
25: 10000087 0 FUNC LOCAL DEFAULT 2 gpio16_clear
26: 10000098 0 NOTYPE LOCAL DEFAULT 2 $d
27: 100000b0 0 NOTYPE LOCAL DEFAULT 2 $d
28: 100000f8 0 NOTYPE LOCAL DEFAULT 3 $d
29: 100000d4 0 NOTYPE LOCAL DEFAULT 2 $d
30: 00080000 0 NOTYPE GLOBAL DEFAULT ABS __SRAM_SIZE
31: 10000000 0 NOTYPE GLOBAL DEFAULT 1 _vectors
32: 20000000 0 NOTYPE GLOBAL DEFAULT ABS __SRAM_BASE
33: 10000009 30 FUNC GLOBAL DEFAULT 2 Reset_Handler
34: 00008000 0 NOTYPE GLOBAL DEFAULT ABS __STACK_SIZE
35: 20080000 0 NOTYPE GLOBAL DEFAULT 2 __StackTop
36: 20080000 0 NOTYPE GLOBAL DEFAULT ABS __stack
37: 20078000 0 NOTYPE GLOBAL DEFAULT ABS __StackLimit
38: 02000000 0 NOTYPE GLOBAL DEFAULT ABS __XIP_SIZE
39: 10000000 0 NOTYPE GLOBAL DEFAULT ABS __XIP_BASE

2
RA-0x0001-GPIO-Output/review_reports/size.txt
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@@ -1,2 +0,0 @@
text data bss dec hex filename
268 0 0 268 10c gpio16_blink.elf

43
RA-0x0001-GPIO-Output/review_reports/strings.txt
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@@ -1,43 +0,0 @@
D@pG
@@pG
@@pG
aeabi
Cortex-M33
aeabi
Cortex-M33
gpio16_blink.o
IO_BANK0_BASE
PADS_BANK0_BASE
SIO_BASE
GPIO16_CTRL
GPIO16_PAD
GPIO16_BIT
GPIO_OUT_SET
GPIO_OUT_XOR
GPIO_OE_SET
STACK_TOP
STACK_LIMIT
init_stack
enable_coprocessor
gpio16_config
blink_loop
gpio16_set
delay
gpio16_clear
__SRAM_SIZE
_vectors
__SRAM_BASE
Reset_Handler
__STACK_SIZE
__StackTop
__stack
__StackLimit
__XIP_SIZE
__XIP_BASE
.symtab
.strtab
.shstrtab
.vectors
.text
.picobin_block
.stack