mirror of
https://github.com/mytechnotalent/Embedded-Hacking.git
synced 2026-08-11 13:40:20 +02:00
Kevin Thomas
7a42b2e088
- PWM slice 4, channel B on GPIO25 (onboard LED) - Duty cycle sweep 0-100% in 5% steps for breathing effect - Wrap 9999 with no clock division (~650 Hz from ROSC) - UART reports each duty step - 1390B FLASH, 11 source files, zero warnings
215 lines
6.6 KiB
C
215 lines
6.6 KiB
C
/**
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******************************************************************************
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* @file rp2350.h
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* @author Kevin Thomas
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* @brief RP2350 Device Peripheral Access Layer Header File.
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*
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* Memory-mapped register structures and peripheral base addresses
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* for the RP2350 microcontroller (Cortex-M33 dual-core). All
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* register offsets verified against the RP2350 datasheet
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* (RP-008373-DS-2).
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 Kevin Thomas.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#ifndef __RP2350_H
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#define __RP2350_H
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#include <stdint.h>
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#include <stdbool.h>
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/*!< Defines 'read / write' permissions */
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#define __IO volatile
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/*!< Stack addresses */
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#define STACK_TOP 0x20082000UL
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#define STACK_LIMIT 0x2007A000UL
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/*!< Memory map */
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#define XIP_BASE 0x10000000UL
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#define SRAM_BASE 0x20000000UL
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#define SIO_BASE 0xD0000000UL
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#define PPB_BASE 0xE0000000UL
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/*!< APB peripherals */
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#define CLOCKS_BASE 0x40010000UL
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#define RESETS_BASE 0x40020000UL
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#define IO_BANK0_BASE 0x40028000UL
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#define PADS_BANK0_BASE 0x40038000UL
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#define XOSC_BASE 0x40048000UL
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#define UART0_BASE 0x40070000UL
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#define PWM_BASE 0x400A8000UL
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/**
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* @brief XOSC (External Crystal Oscillator)
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*/
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typedef struct
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{
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__IO uint32_t CTRL; // Control register Address offset: 0x00
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__IO uint32_t STATUS; // Status register Address offset: 0x04
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__IO uint32_t DORMANT; // Dormant mode Address offset: 0x08
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__IO uint32_t STARTUP; // Startup delay Address offset: 0x0C
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__IO uint32_t COUNT; // Frequency count Address offset: 0x10
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} XOSC_TypeDef;
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/**
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* @brief CLOCKS
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*/
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typedef struct
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{
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__IO uint32_t RESERVED0[18]; // Other clock registers Address offset: 0x00-0x44
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__IO uint32_t CLK_PERI_CTRL; // Peripheral clock control Address offset: 0x48
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} CLOCKS_TypeDef;
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/**
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* @brief RESETS
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*/
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typedef struct
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{
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__IO uint32_t RESET; // Reset control Address offset: 0x00
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__IO uint32_t WDSEL; // Watchdog select Address offset: 0x04
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__IO uint32_t RESET_DONE; // Reset done status Address offset: 0x08
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} RESETS_TypeDef;
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/**
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* @brief IO_BANK0 GPIO Control (one per GPIO)
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*/
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typedef struct
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{
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__IO uint32_t STATUS; // GPIO status Address offset: 0x00
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__IO uint32_t CTRL; // GPIO control Address offset: 0x04
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} IO_BANK0_GPIO_TypeDef;
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/**
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* @brief IO_BANK0
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*/
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typedef struct
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{
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IO_BANK0_GPIO_TypeDef GPIO[30]; // GPIO 0-29 status/ctrl pairs Address offset: 0x000-0x0E8
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} IO_BANK0_TypeDef;
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/**
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* @brief PADS_BANK0
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*/
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typedef struct
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{
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__IO uint32_t VOLTAGE_SELECT; // Voltage select Address offset: 0x00
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__IO uint32_t GPIO[30]; // GPIO 0-29 pad control Address offset: 0x04-0x78
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} PADS_BANK0_TypeDef;
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/**
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* @brief Peripheral Definitions
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*/
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#define XOSC ((XOSC_TypeDef *) XOSC_BASE)
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#define CLOCKS ((CLOCKS_TypeDef *) CLOCKS_BASE)
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#define RESETS ((RESETS_TypeDef *) RESETS_BASE)
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#define IO_BANK0 ((IO_BANK0_TypeDef *) IO_BANK0_BASE)
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#define PADS_BANK0 ((PADS_BANK0_TypeDef *) PADS_BANK0_BASE)
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#define SIO ((volatile uint32_t *) SIO_BASE)
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#define CPACR ((volatile uint32_t *) (PPB_BASE + 0x0ED88UL))
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/**
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* @brief XOSC bit definitions
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*/
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#define XOSC_STATUS_STABLE_SHIFT 31U
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/**
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* @brief CPACR bit definitions
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*/
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#define CPACR_CP0_SHIFT 0U
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#define CPACR_CP1_SHIFT 1U
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/**
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* @brief CLOCKS bit definitions
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*/
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#define CLK_PERI_CTRL_ENABLE_SHIFT 11U
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#define CLK_PERI_CTRL_AUXSRC_SHIFT 5U
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#define CLK_PERI_CTRL_AUXSRC_XOSC 4U
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/**
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* @brief RESETS bit definitions
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*/
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#define RESETS_RESET_IO_BANK0_SHIFT 6U
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#define RESETS_RESET_PWM_SHIFT 16U
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#define RESETS_RESET_UART0_SHIFT 26U
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/**
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* @brief IO_BANK0 bit definitions
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*/
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#define IO_BANK0_CTRL_FUNCSEL_MASK 0x1FU
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#define IO_BANK0_CTRL_FUNCSEL_UART 0x02U
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#define IO_BANK0_CTRL_FUNCSEL_PWM 0x04U
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#define IO_BANK0_CTRL_FUNCSEL_SIO 0x05U
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/**
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* @brief PADS_BANK0 bit definitions
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*/
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#define PADS_BANK0_OD_SHIFT 7U
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#define PADS_BANK0_IE_SHIFT 6U
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#define PADS_BANK0_ISO_SHIFT 8U
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/**
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* @brief UART register offsets (word indices from UART0_BASE)
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*/
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#define UART_DR_OFFSET (0x000U / 4U)
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#define UART_FR_OFFSET (0x018U / 4U)
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#define UART_IBRD_OFFSET (0x024U / 4U)
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#define UART_FBRD_OFFSET (0x028U / 4U)
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#define UART_LCR_H_OFFSET (0x02CU / 4U)
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#define UART_CR_OFFSET (0x030U / 4U)
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/**
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* @brief UART flag register bit definitions
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*/
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#define UART_FR_TXFF_MASK 32U
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#define UART_FR_RXFE_MASK 16U
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/**
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* @brief UART line control and enable values
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*/
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#define UART_LCR_H_8N1_FIFO 0x70U
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#define UART_CR_ENABLE ((3U << 8) | 1U)
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/**
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* @brief GPIO pin definitions
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*/
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#define LED_PIN 25U
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/**
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* @brief SIO GPIO register offsets (word indices from SIO_BASE)
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*/
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#define SIO_GPIO_IN_OFFSET (0x004U / 4U)
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#define SIO_GPIO_OUT_SET_OFFSET (0x018U / 4U)
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#define SIO_GPIO_OUT_CLR_OFFSET (0x020U / 4U)
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#define SIO_GPIO_OUT_XOR_OFFSET (0x028U / 4U)
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#define SIO_GPIO_OE_SET_OFFSET (0x038U / 4U)
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/**
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* @brief PWM register offsets (per slice, stride 0x14)
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*/
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#define PWM_CH_CSR_OFFSET 0x00U
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#define PWM_CH_DIV_OFFSET 0x04U
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#define PWM_CH_CC_OFFSET 0x0CU
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#define PWM_CH_TOP_OFFSET 0x10U
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#define PWM_CH_STRIDE 0x14U
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/**
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* @brief PWM bit definitions
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*/
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#define PWM_CSR_EN_SHIFT 0U
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#define PWM_DIV_INT_SHIFT 4U
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#define PWM_CC_B_SHIFT 16U
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#define PWM_WRAP_DEFAULT 9999U
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#endif /* __RP2350_H */
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