mirror of
https://github.com/mytechnotalent/Embedded-Hacking.git
synced 2026-04-21 18:46:07 +02:00
Kevin Thomas
42 lines
2.1 KiB
ArmAsm
42 lines
2.1 KiB
ArmAsm
/**
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* FILE: constants.s
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*
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* DESCRIPTION:
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* RP2350 Memory Addresses and Constants.
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*
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* BRIEF:
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* Defines all memory-mapped register addresses and constants used
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* throughout the RP2350 driver.
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*
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* AUTHOR: Kevin Thomas
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* CREATION DATE: November 27, 2025
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* UPDATE DATE: November 27, 2025
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*/
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.syntax unified // use unified assembly syntax
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.cpu cortex-m33 // target Cortex-M33 core
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.thumb // use Thumb instruction set
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/**
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* Memory addresses and constants.
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*/
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.equ STACK_TOP, 0x20082000 // top of stack
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.equ STACK_LIMIT, 0x2007a000 // stack limit
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.equ XOSC_BASE, 0x40048000 // XOSC base address
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.equ XOSC_CTRL, XOSC_BASE + 0x00 // XOSC control register
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.equ XOSC_STATUS, XOSC_BASE + 0x04 // XOSC status register
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.equ XOSC_STARTUP, XOSC_BASE + 0x0c // XOSC startup register
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.equ PPB_BASE, 0xe0000000 // PPB base address
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.equ CPACR, PPB_BASE + 0x0ed88 // coprocessor access control
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.equ CLOCKS_BASE, 0x40010000 // clocks base address
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.equ CLK_PERI_CTRL, CLOCKS_BASE + 0x48 // peripheral clock control
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.equ RESETS_BASE, 0x40020000 // resets base address
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.equ RESETS_RESET, RESETS_BASE + 0x0 // reset register
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.equ RESETS_RESET_CLEAR, RESETS_BASE + 0x3000 // reset clear (atomic)
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.equ RESETS_RESET_DONE, RESETS_BASE + 0x8 // reset done register
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.equ IO_BANK0_BASE, 0x40028000 // IO_BANK0 base address
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.equ IO_BANK0_GPIO16_CTRL_OFFSET, 0x84 // GPIO16 control offset
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.equ PADS_BANK0_BASE, 0x40038000 // PADS_BANK0 base address
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.equ PADS_BANK0_GPIO16_OFFSET, 0x44 // GPIO16 pad offset
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.equ UART0_BASE, 0x40070000 // UART0 base address
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